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[devtools] Fix dbgconf handling when not present in PDSC
1 parent b4ab6b8 commit 0589e67

6 files changed

Lines changed: 245 additions & 2 deletions

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libs/rtemodel/src/RteProject.cpp

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1405,7 +1405,9 @@ void RteProject::CollectSettings(const string& targetName)
14051405
t->AddDeviceProperties(d, processorName);
14061406
// add dbgconf file
14071407
auto debugVars = t->GetDeviceDebugVars();
1408-
AddFileInstance(nullptr, debugVars, 0, t);
1408+
if (debugVars && debugVars->HasAttribute("configfile")) {
1409+
AddFileInstance(nullptr, debugVars, 0, t);
1410+
}
14091411

14101412
// collect copied files and sources
14111413
for (auto [_,fi] : m_files) {

test/packs/ARM/RteTest_DFP/0.1.1/ARM.RteTest_DFP.pdsc

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,7 @@
2727
RteTest ARM M Device Family
2828
</description>
2929
<algorithm name="Device/ARM/Flash/FAMILY.FLM" start="0x00000000" size="0x00040000" default="1"/>
30-
<debugvars configfile="Device/ARM/Debug/ARMCM.dbgconf">
30+
<debugvars>
3131
__var DbgMCU_CR = 0x00000007; // DBGMCU_CR: DBG_SLEEP, DBG_STOP, DBG_STANDBY
3232
__var TraceClk_Pin = 0x00040002; // PE2
3333
__var TraceD0_Pin = 0x00040003; // PE3
Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,19 @@
1+
# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/main/tools/projmgr/schemas/csolution.schema.json
2+
3+
solution:
4+
5+
compiler: AC6
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7+
target-types:
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- type: ARMCM3
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device: RteTest_ARMCM3
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target-set:
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- set:
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images:
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- project-context: run-debug
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projects:
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- project: run-debug.cproject.yml
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packs:
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- pack: ARM::RteTest_DFP@0.1.1
Lines changed: 112 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,112 @@
1+
cbuild-run:
2+
generated-by: csolution version 0.0.0+gc1fb4eb2
3+
solution: ../data/TestRunDebug/no-dbgconf.csolution.yml
4+
target-type: ARMCM3
5+
target-set: <default>
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compiler: AC6
7+
device: ARM::RteTest_ARMCM3
8+
device-pack: ARM::RteTest_DFP@0.1.1
9+
output:
10+
- file: out/run-debug/ARMCM3/run-debug.axf
11+
info: generate by run-debug+ARMCM3
12+
type: elf
13+
load: symbols
14+
- file: out/run-debug/ARMCM3/run-debug.hex
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info: generate by run-debug+ARMCM3
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type: hex
17+
load: image
18+
- file: out/run-debug/ARMCM3/run-debug.bin
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info: generate by run-debug+ARMCM3
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type: bin
21+
load: none
22+
system-resources:
23+
memory:
24+
- name: IROM1
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access: rx
26+
start: 0x00000000
27+
size: 0x00040000
28+
from-pack: ARM::RteTest_DFP@0.1.1
29+
- name: IRAM1
30+
access: rwx
31+
start: 0x20000000
32+
size: 0x00020000
33+
from-pack: ARM::RteTest_DFP@0.1.1
34+
system-descriptions:
35+
- file: ${CMSIS_PACK_ROOT}/ARM/RteTest_DFP/0.1.1/Device/ARM/SVD/ARMCM3.svd
36+
type: svd
37+
debugger:
38+
name: CMSIS-DAP@pyOCD
39+
protocol: swd
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clock: 10000000
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gdbserver:
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- port: 3333
43+
debug-vars:
44+
vars: |
45+
__var DbgMCU_CR = 0x00000007; // DBGMCU_CR: DBG_SLEEP, DBG_STOP, DBG_STANDBY
46+
__var TraceClk_Pin = 0x00040002; // PE2
47+
__var TraceD0_Pin = 0x00040003; // PE3
48+
__var TraceD1_Pin = 0x00040004; // PE4
49+
debug-sequences:
50+
- name: DebugDeviceUnlock
51+
blocks:
52+
- execute: |
53+
Sequence("CheckID");
54+
- name: DebugCoreStart
55+
blocks:
56+
- execute: |
57+
// Replication of Standard Functionality
58+
Write32(0xE000EDF0, 0xA05F0001); // Enable Core Debug via DHCSR
59+
- info: DbgMCU registers
60+
execute: |
61+
// Device Specific Debug Setup
62+
Write32(0x40021018, Read32(0x40021018) | 0x00400000); // Set RCC_APB2ENR.DBGMCUEN
63+
- name: CheckID
64+
blocks:
65+
- execute: |
66+
__var pidr1 = 0;
67+
__var pidr2 = 0;
68+
__var jep106id = 0;
69+
__var ROMTableBase = 0;
70+
71+
__ap = 0; // AHB-AP
72+
73+
ROMTableBase = ReadAP(0xF8) & ~0x3;
74+
75+
pidr1 = Read32(ROMTableBase + 0x0FE4);
76+
pidr2 = Read32(ROMTableBase + 0x0FE8);
77+
jep106id = ((pidr2 & 0x7) << 4 ) | ((pidr1 >> 4) & 0xF);
78+
- if: jep106id != 0x20
79+
execute: |
80+
Query(0, "Incorrect ID! Abort connection", 1);
81+
Message(2, "Incorrect ID! Abort connection.");
82+
- name: DebugPortStop
83+
blocks:
84+
- execute: |
85+
__var connectionFlash = ( __connection & 0xF ) == 2 ;
86+
__var FLASH_BASE = 0x40022000 ;
87+
__var FLASH_CR = FLASH_BASE + 0x10 ;
88+
__var OBL_LAUNCH_BIT = ( 1 << 13 ) ;
89+
__var FLASH_CR_Value = 0 ;
90+
__var DoDebugPortStop = 1 ;
91+
__var DP_CTRL_STAT = 0x4 ;
92+
__var DP_SELECT = 0x8 ;
93+
- if: connectionFlash && DoDebugPortStop
94+
execute: |
95+
DoDebugPortStop = 0 ;
96+
FLASH_CR_Value = Read32( FLASH_CR ) ;
97+
__errorcontrol = 1 ;
98+
// write OBL_LAUNCH bit (causes a reset)
99+
Write32( FLASH_CR, FLASH_CR_Value | ( OBL_LAUNCH_BIT ) ) ;
100+
__errorcontrol = 0 ;
101+
- if: DoDebugPortStop
102+
execute: |
103+
// Switch to DP Register Bank 0
104+
WriteDP(DP_SELECT, 0x00000000);
105+
// Power Down Debug port
106+
WriteDP(DP_CTRL_STAT, 0x00000000);
107+
programming:
108+
- algorithm: ${CMSIS_PACK_ROOT}/ARM/RteTest_DFP/0.1.1/Device/ARM/Flash/FAMILY.FLM
109+
start: 0x00000000
110+
size: 0x00040000
111+
ram-start: 0x20000000
112+
ram-size: 0x00020000
Lines changed: 94 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,94 @@
1+
build:
2+
generated-by: csolution version 0.0.0+gc1fb4eb2
3+
solution: ../data/TestRunDebug/no-dbgconf.csolution.yml
4+
project: ../data/TestRunDebug/run-debug.cproject.yml
5+
context: run-debug+ARMCM3
6+
compiler: AC6
7+
device: ARM::RteTest_ARMCM3
8+
device-pack: ARM::RteTest_DFP@0.1.1
9+
device-books:
10+
- name: http://infocenter.arm.com/help/topic/com.arm.doc.dui0552a/index.html
11+
title: Cortex-M3 Device Generic Users Guide
12+
processor:
13+
fpu: off
14+
core: Cortex-M3
15+
packs:
16+
- pack: ARM::RteTest_DFP@0.1.1
17+
path: ${CMSIS_PACK_ROOT}/ARM/RteTest_DFP/0.1.1
18+
define:
19+
- ARMCM3
20+
- _RTE_
21+
define-asm:
22+
- ARMCM3
23+
- _RTE_
24+
add-path:
25+
- ../data/TestRunDebug/RTE/_ARMCM3
26+
- ${CMSIS_PACK_ROOT}/ARM/RteTest_DFP/0.1.1/Device/ARM/ARMCM3/Include
27+
add-path-asm:
28+
- ../data/TestRunDebug/RTE/_ARMCM3
29+
- ${CMSIS_PACK_ROOT}/ARM/RteTest_DFP/0.1.1/Device/ARM/ARMCM3/Include
30+
output-dirs:
31+
intdir: tmp
32+
outdir: out/run-debug/ARMCM3
33+
rtedir: ../data/TestRunDebug/RTE
34+
output:
35+
- type: bin
36+
file: run-debug.bin
37+
- type: elf
38+
file: run-debug.axf
39+
- type: hex
40+
file: run-debug.hex
41+
components:
42+
- component: ARM::Device:Startup&RteTest Startup@2.0.3
43+
condition: ARMCM3 RteTest
44+
from-pack: ARM::RteTest_DFP@0.1.1
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selected-by: Startup
46+
files:
47+
- file: ${CMSIS_PACK_ROOT}/ARM/RteTest_DFP/0.1.1/Device/ARM/ARMCM3/Include/ARMCM3.h
48+
category: header
49+
version: 2.0.3
50+
- file: https://arm-software.github.io/CMSIS_5/Core_A/html/startup_c_pg.html
51+
category: doc
52+
version: 2.0.3
53+
- file: ../data/TestRunDebug/RTE/Device/RteTest_ARMCM3/ARMCM3_ac6.sct
54+
category: linkerScript
55+
attr: config
56+
version: 1.0.0
57+
- file: ../data/TestRunDebug/RTE/Device/RteTest_ARMCM3/startup_ARMCM3.c
58+
category: sourceC
59+
attr: config
60+
version: 2.0.3
61+
- file: ../data/TestRunDebug/RTE/Device/RteTest_ARMCM3/system_ARMCM3.c
62+
category: sourceC
63+
attr: config
64+
version: 1.0.1
65+
- component: ARM::RteTest:CORE@0.1.1
66+
condition: Cortex-M Device
67+
from-pack: ARM::RteTest_DFP@0.1.1
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selected-by: CORE
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implements: RteTest:CORE@1.1.1
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files:
71+
- file: ${CMSIS_PACK_ROOT}/ARM/RteTest_DFP/0.1.1/Doc/html/index.html
72+
category: doc
73+
version: 0.1.1
74+
apis:
75+
- api: RteTest:CORE@1.1.1
76+
from-pack: ARM::RteTest_DFP@0.1.1
77+
implemented-by: ARM::RteTest:CORE@0.1.1
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files:
79+
- file: https://arm-software.github.io/CMSIS_5/Pack/html/pdsc_apis_pg.html
80+
category: doc
81+
version: 1.1.1
82+
linker:
83+
script: ../data/TestRunDebug/RTE/Device/RteTest_ARMCM3/ARMCM3_ac6.sct
84+
constructed-files:
85+
- file: ../data/TestRunDebug/RTE/_ARMCM3/RTE_Components.h
86+
category: header
87+
licenses:
88+
- license: <unknown>
89+
packs:
90+
- pack: ARM::RteTest_DFP@0.1.1
91+
components:
92+
- component: ARM::Device:Startup&RteTest Startup@2.0.3
93+
- component: ARM::RteTest:CORE@0.1.1
94+
- component: RteTest:CORE(API)

tools/projmgr/test/src/ProjMgrUnitTests.cpp

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6721,6 +6721,22 @@ TEST_F(ProjMgrUnitTests, TestRunDebug) {
67216721
testinput_folder + "/TestRunDebug/ref/run-debug+TestHW2.cbuild.yml");
67226722
}
67236723

6724+
TEST_F(ProjMgrUnitTests, TestNoDbgconf) {
6725+
char* argv[7];
6726+
const string& csolution = testinput_folder + "/TestRunDebug/no-dbgconf.csolution.yml";
6727+
argv[1] = (char*)"convert";
6728+
argv[2] = (char*)csolution.c_str();
6729+
argv[3] = (char*)"-o";
6730+
argv[4] = (char*)testoutput_folder.c_str();
6731+
argv[5] = (char*)"--active";
6732+
argv[6] = (char*)"ARMCM3";
6733+
EXPECT_EQ(0, RunProjMgr(7, argv, m_envp));
6734+
ProjMgrTestEnv::CompareFile(testoutput_folder + "/no-dbgconf+ARMCM3.cbuild-run.yml",
6735+
testinput_folder + "/TestRunDebug/ref/no-dbgconf+ARMCM3.cbuild-run.yml");
6736+
ProjMgrTestEnv::CompareFile(testoutput_folder + "/run-debug+ARMCM3.cbuild.yml",
6737+
testinput_folder + "/TestRunDebug/ref/run-debug+ARMCM3.cbuild.yml");
6738+
}
6739+
67246740
TEST_F(ProjMgrUnitTests, TestRunDebugMulticore) {
67256741
char* argv[7];
67266742
const string& csolution = testinput_folder + "/TestRunDebug/run-debug.csolution.yml";

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