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dicejdicej
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Merge pull request #224 from bytecodealliance/dicej/upstream-merge
upstream merge
2 parents bf85653 + 8e650aa commit 0bcd54e

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‎.github/workflows/main.yml‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -778,7 +778,7 @@ jobs:
778778
test_wasi_nn:
779779
strategy:
780780
matrix:
781-
feature: ["openvino"]
781+
feature: ["openvino", "onnx-download"]
782782
os: ["ubuntu-24.04", "windows-2025"]
783783
include:
784784
- os: windows-2025
@@ -794,7 +794,7 @@ jobs:
794794
- uses: ./.github/actions/install-rust
795795

796796
# Install OpenVINO
797-
- uses: abrown/install-openvino-action@v9
797+
- uses: abrown/install-openvino-action@v10
798798
if: runner.arch == 'X64'
799799

800800
# Install WinML for testing wasi-nn WinML backend. WinML is only available
@@ -835,7 +835,7 @@ jobs:
835835
needs: determine
836836
if: needs.determine.outputs.run-dwarf
837837
name: Test DWARF debugging
838-
runs-on: ubuntu-22.04 # FIXME: fails on `ubuntu-24.04` right now
838+
runs-on: ubuntu-24.04
839839
steps:
840840
- uses: actions/checkout@v4
841841
with:
@@ -848,14 +848,14 @@ jobs:
848848
tar -xzf wasi-sdk-25.0-x86_64-linux.tar.gz
849849
mv wasi-sdk-25.0-x86_64-linux wasi-sdk
850850
- run: |
851-
sudo apt-get update && sudo apt-get install -y gdb lldb-15 llvm
851+
sudo apt-get update && sudo apt-get install -y gdb lldb-18 llvm
852852
# workaround for https://bugs.launchpad.net/ubuntu/+source/llvm-defaults/+bug/1972855
853853
sudo mkdir -p /usr/lib/local/lib/python3.10/dist-packages/lldb
854854
sudo ln -s /usr/lib/llvm-15/lib/python3.10/dist-packages/lldb/* /usr/lib/python3/dist-packages/lldb/
855855
# Only testing release since it is more likely to expose issues with our low-level symbol handling.
856856
cargo test --release --test all -- --ignored --test-threads 1 debug::
857857
env:
858-
LLDB: lldb-15 # override default version, 14
858+
LLDB: lldb-18
859859
WASI_SDK_PATH: /tmp/wasi-sdk
860860
861861
build-preview1-component-adapter:

‎Cargo.lock‎

Lines changed: 6 additions & 7 deletions
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‎cranelift/assembler-x64/meta/src/dsl/features.rs‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -38,12 +38,10 @@ impl Features {
3838
}
3939

4040
pub(crate) fn is_sse(&self) -> bool {
41-
self.0.iter().any(|f| {
42-
matches!(
43-
f,
44-
Feature::sse | Feature::sse2 | Feature::ssse3 | Feature::sse41
45-
)
46-
})
41+
use Feature::*;
42+
self.0
43+
.iter()
44+
.any(|f| matches!(f, sse | sse2 | sse3 | ssse3 | sse41 | sse42))
4745
}
4846
}
4947

@@ -86,6 +84,7 @@ pub enum Feature {
8684
lzcnt,
8785
popcnt,
8886
avx,
87+
avx2,
8988
cmpxchg16b,
9089
}
9190

@@ -110,6 +109,7 @@ pub const ALL_FEATURES: &[Feature] = &[
110109
Feature::lzcnt,
111110
Feature::popcnt,
112111
Feature::avx,
112+
Feature::avx2,
113113
Feature::cmpxchg16b,
114114
];
115115

‎cranelift/assembler-x64/meta/src/dsl/format.rs‎

Lines changed: 25 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -333,6 +333,7 @@ pub enum Location {
333333
xmm1,
334334
xmm2,
335335
xmm3,
336+
xmm_m8,
336337
xmm_m16,
337338
xmm_m32,
338339
xmm_m64,
@@ -352,7 +353,7 @@ impl Location {
352353
pub fn bits(&self) -> u16 {
353354
use Location::*;
354355
match self {
355-
al | cl | imm8 | r8 | rm8 | m8 => 8,
356+
al | cl | imm8 | r8 | rm8 | m8 | xmm_m8 => 8,
356357
ax | dx | imm16 | r16 | rm16 | m16 | xmm_m16 => 16,
357358
eax | edx | imm32 | r32 | r32a | r32b | rm32 | m32 | xmm_m32 => 32,
358359
rax | rbx | rcx | rdx | imm64 | r64 | r64a | r64b | rm64 | m64 | xmm_m64 => 64,
@@ -399,7 +400,7 @@ impl Location {
399400
r8 | r16 | r32 | r32a | r32b | r64 | r64a | r64b | xmm1 | xmm2 | xmm3 => {
400401
OperandKind::Reg(*self)
401402
}
402-
rm8 | rm16 | rm32 | rm64 | xmm_m16 | xmm_m32 | xmm_m64 | xmm_m128 => {
403+
rm8 | rm16 | rm32 | rm64 | xmm_m8 | xmm_m16 | xmm_m32 | xmm_m64 | xmm_m128 => {
403404
OperandKind::RegMem(*self)
404405
}
405406
m8 | m16 | m32 | m64 | m128 => OperandKind::Mem(*self),
@@ -417,7 +418,7 @@ impl Location {
417418
imm8 | imm16 | imm32 | imm64 | m8 | m16 | m32 | m64 | m128 => None,
418419
al | ax | eax | rax | rbx | cl | rcx | dx | edx | rdx | r8 | r16 | r32 | r32a
419420
| r32b | r64 | r64a | r64b | rm8 | rm16 | rm32 | rm64 => Some(RegClass::Gpr),
420-
xmm1 | xmm2 | xmm3 | xmm_m16 | xmm_m32 | xmm_m64 | xmm_m128 | xmm0 => {
421+
xmm1 | xmm2 | xmm3 | xmm_m8 | xmm_m16 | xmm_m32 | xmm_m64 | xmm_m128 | xmm0 => {
421422
Some(RegClass::Xmm)
422423
}
423424
}
@@ -461,6 +462,7 @@ impl core::fmt::Display for Location {
461462
xmm1 => write!(f, "xmm1"),
462463
xmm2 => write!(f, "xmm2"),
463464
xmm3 => write!(f, "xmm3"),
465+
xmm_m8 => write!(f, "xmm_m8"),
464466
xmm_m16 => write!(f, "xmm_m16"),
465467
xmm_m32 => write!(f, "xmm_m32"),
466468
xmm_m64 => write!(f, "xmm_m64"),
@@ -598,6 +600,26 @@ pub enum Eflags {
598600
RW,
599601
}
600602

603+
impl Eflags {
604+
/// Returns whether this represents a read of any bit in the EFLAGS
605+
/// register.
606+
pub fn is_read(&self) -> bool {
607+
match self {
608+
Eflags::None | Eflags::W => false,
609+
Eflags::R | Eflags::RW => true,
610+
}
611+
}
612+
613+
/// Returns whether this represents a writes to any bit in the EFLAGS
614+
/// register.
615+
pub fn is_write(&self) -> bool {
616+
match self {
617+
Eflags::None | Eflags::R => false,
618+
Eflags::W | Eflags::RW => true,
619+
}
620+
}
621+
}
622+
601623
impl Default for Eflags {
602624
fn default() -> Self {
603625
Self::None

‎cranelift/assembler-x64/meta/src/generate/format.rs‎

Lines changed: 14 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -274,26 +274,34 @@ impl dsl::Format {
274274
assert!(!vex.is4);
275275
let reg = reg_or_vvvv;
276276
fmtln!(f, "let reg = self.{reg}.enc();");
277-
fmtln!(f, "let vvvv = {};", "0b0");
278277
fmtln!(f, "let rm = self.{rm}.encode_bx_regs();");
279-
fmtln!(f, "let vex = VexPrefix::three_op(reg, vvvv, rm, {bits});");
278+
fmtln!(f, "let vex = VexPrefix::two_op(reg, rm, {bits});");
280279
ModRmStyle::RegMem {
281280
reg: ModRmReg::Reg(*reg),
282281
rm: *rm,
283282
}
284283
}
285284
},
286-
[Reg(reg), Reg(rm)] => {
285+
[Reg(reg), Reg(rm)] | [Reg(reg), Reg(rm), Imm(_)] => {
287286
assert!(!vex.is4);
288287
fmtln!(f, "let reg = self.{reg}.enc();");
289-
fmtln!(f, "let vvvv = 0;");
290-
fmtln!(f, "let rm = (Some(self.{rm}.enc()), None);");
291-
fmtln!(f, "let vex = VexPrefix::three_op(reg, vvvv, rm, {bits});");
288+
fmtln!(f, "let rm = self.{rm}.encode_bx_regs();");
289+
fmtln!(f, "let vex = VexPrefix::two_op(reg, rm, {bits});");
292290
ModRmStyle::Reg {
293291
reg: ModRmReg::Reg(*reg),
294292
rm: *rm,
295293
}
296294
}
295+
[Reg(reg), Mem(rm)] | [Mem(rm), Reg(reg)] | [RegMem(rm), Reg(reg), Imm(_)] => {
296+
assert!(!vex.is4);
297+
fmtln!(f, "let reg = self.{reg}.enc();");
298+
fmtln!(f, "let rm = self.{rm}.encode_bx_regs();");
299+
fmtln!(f, "let vex = VexPrefix::two_op(reg, rm, {bits});");
300+
ModRmStyle::RegMem {
301+
reg: ModRmReg::Reg(*reg),
302+
rm: *rm,
303+
}
304+
}
297305
unknown => unimplemented!("unknown pattern: {unknown:?}"),
298306
};
299307

‎cranelift/assembler-x64/meta/src/generate/operand.rs‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -29,7 +29,7 @@ impl dsl::Operand {
2929
xmm1 | xmm2 | xmm3 => {
3030
format!("Xmm<R::{mut_}Xmm>")
3131
}
32-
xmm_m16 | xmm_m32 | xmm_m64 | xmm_m128 => {
32+
xmm_m8 | xmm_m16 | xmm_m32 | xmm_m64 | xmm_m128 => {
3333
format!("XmmMem<R::{mut_}Xmm, R::ReadGpr>")
3434
}
3535
m8 | m16 | m32 | m64 | m128 => format!("Amode<R::ReadGpr>"),
@@ -64,8 +64,8 @@ impl dsl::Location {
6464
None => format!("self.{self}.to_string(None)"),
6565
}
6666
}
67-
xmm_m16 | xmm_m32 | xmm_m64 | xmm1 | xmm2 | xmm3 | xmm_m128 | m8 | m16 | m32 | m64
68-
| m128 => {
67+
xmm1 | xmm2 | xmm3 | xmm_m8 | xmm_m16 | xmm_m32 | xmm_m64 | xmm_m128 | m8 | m16
68+
| m32 | m64 | m128 => {
6969
format!("self.{self}.to_string()")
7070
}
7171
}
@@ -84,7 +84,7 @@ impl dsl::Location {
8484
m8 | m16 | m32 | m64 | m128 => {
8585
panic!("no need to generate a size for memory-only access")
8686
}
87-
xmm1 | xmm2 | xmm3 | xmm_m16 | xmm_m32 | xmm_m64 | xmm_m128 | xmm0 => None,
87+
xmm1 | xmm2 | xmm3 | xmm_m8 | xmm_m16 | xmm_m32 | xmm_m64 | xmm_m128 | xmm0 => None,
8888
}
8989
}
9090
}

‎cranelift/assembler-x64/meta/src/instructions.rs‎

Lines changed: 52 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,13 @@
11
//! Defines x64 instructions using the DSL.
22
3+
mod abs;
34
mod add;
5+
mod align;
46
mod and;
57
mod atomic;
68
mod avg;
79
mod bitmanip;
10+
mod cmov;
811
mod cmp;
912
mod cvt;
1013
mod div;
@@ -17,6 +20,7 @@ mod mul;
1720
mod neg;
1821
mod nop;
1922
mod or;
23+
mod pack;
2024
mod round;
2125
mod shift;
2226
mod sqrt;
@@ -31,11 +35,14 @@ use std::collections::HashMap;
3135
#[must_use]
3236
pub fn list() -> Vec<Inst> {
3337
let mut all = vec![];
38+
all.extend(abs::list());
3439
all.extend(add::list());
40+
all.extend(align::list());
3541
all.extend(and::list());
3642
all.extend(atomic::list());
3743
all.extend(avg::list());
3844
all.extend(bitmanip::list());
45+
all.extend(cmov::list());
3946
all.extend(cmp::list());
4047
all.extend(cvt::list());
4148
all.extend(div::list());
@@ -48,6 +55,7 @@ pub fn list() -> Vec<Inst> {
4855
all.extend(neg::list());
4956
all.extend(nop::list());
5057
all.extend(or::list());
58+
all.extend(pack::list());
5159
all.extend(round::list());
5260
all.extend(shift::list());
5361
all.extend(sqrt::list());
@@ -74,7 +82,10 @@ fn check_avx_alternates(all: &mut [Inst]) {
7482
.map(|(index, inst)| (inst.name().clone(), index))
7583
.collect();
7684
for inst in all.iter().filter(|inst| inst.alternate.is_some()) {
77-
assert!(inst.features.is_sse());
85+
assert!(
86+
inst.features.is_sse(),
87+
"expected an SSE instruction: {inst}"
88+
);
7889
let alternate = inst.alternate.as_ref().unwrap();
7990
assert_eq!(alternate.feature, Feature::avx);
8091
let avx_index = name_to_index.get(&alternate.name).expect(&format!(
@@ -116,16 +127,54 @@ fn check_sse_matches_avx(sse_inst: &Inst, avx_inst: &Inst) {
116127
// may have slightly different operand semantics (e.g., `roundss` ->
117128
// `vroundss`) and we want to be careful about matching too freely.
118129
(
119-
[(ReadWrite, Reg(_)), (Read, Reg(_) | RegMem(_) | Mem(_))],
130+
[
131+
(ReadWrite | Write, Reg(_)),
132+
(Read, Reg(_) | RegMem(_) | Mem(_)),
133+
],
120134
[
121135
(Write, Reg(_)),
122136
(Read, Reg(_)),
123137
(Read, Reg(_) | RegMem(_) | Mem(_)),
124138
],
125139
) => {}
140+
(
141+
[
142+
(Write, Reg(_) | RegMem(_) | Mem(_)),
143+
(Read, Reg(_) | RegMem(_) | Mem(_)),
144+
],
145+
[
146+
(Write, Reg(_) | RegMem(_) | Mem(_)),
147+
(Read, Reg(_) | RegMem(_) | Mem(_)),
148+
],
149+
) => {}
150+
(
151+
[
152+
(Write, Reg(_) | RegMem(_)),
153+
(Read, Reg(_) | RegMem(_)),
154+
(Read, Imm(_)),
155+
],
156+
[
157+
(Write, Reg(_) | RegMem(_)),
158+
(Read, Reg(_) | RegMem(_)),
159+
(Read, Imm(_)),
160+
],
161+
) => {}
162+
(
163+
[(ReadWrite, Reg(_)), (Read, RegMem(_)), (Read, Imm(_))],
164+
[
165+
(Write, Reg(_)),
166+
(Read, Reg(_)),
167+
(Read, RegMem(_)),
168+
(Read, Imm(_)),
169+
],
170+
) => {}
126171
// We panic on other formats for now; feel free to add more patterns to
127172
// avoid this.
128-
_ => panic!("unmatched formats for SSE-to-AVX alternate:\n{sse_inst}\n{avx_inst}"),
173+
_ => panic!(
174+
"unmatched formats for SSE-to-AVX alternate:\n{sse_inst}\n{avx_inst}. {:?}, {:?}",
175+
list_ops(sse_inst),
176+
list_ops(avx_inst)
177+
),
129178
}
130179
}
131180

‎cranelift/assembler-x64/meta/src/instructions/abs.rs‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,14 @@
1+
use crate::dsl::{Feature::*, Inst, Location::*, VexLength::*};
2+
use crate::dsl::{align, fmt, inst, r, rex, vex, w};
3+
4+
#[rustfmt::skip] // Keeps instructions on a single line.
5+
pub fn list() -> Vec<Inst> {
6+
vec![
7+
inst("pabsb", fmt("A", [w(xmm1), r(align(xmm_m128))]), rex([0x66, 0x0F, 0x38, 0x1C]), _64b | compat | ssse3).alt(avx, "vpabsb_a"),
8+
inst("vpabsb", fmt("A", [w(xmm1), r(xmm_m128)]), vex(L128)._66()._0f38().op(0x1C), _64b | compat | avx),
9+
inst("pabsw", fmt("A", [w(xmm1), r(align(xmm_m128))]), rex([0x66, 0x0F, 0x38, 0x1D]), _64b | compat | ssse3).alt(avx, "vpabsw_a"),
10+
inst("vpabsw", fmt("A", [w(xmm1), r(xmm_m128)]), vex(L128)._66()._0f38().op(0x1D), _64b | compat | avx),
11+
inst("pabsd", fmt("A", [w(xmm1), r(align(xmm_m128))]), rex([0x66, 0x0F, 0x38, 0x1E]), _64b | compat | ssse3).alt(avx, "vpabsd_a"),
12+
inst("vpabsd", fmt("A", [w(xmm1), r(xmm_m128)]), vex(L128)._66()._0f38().op(0x1E), _64b | compat | avx),
13+
]
14+
}

‎cranelift/assembler-x64/meta/src/instructions/align.rs‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,10 @@
1+
use crate::dsl::{Feature::*, Inst, Location::*, VexLength::*};
2+
use crate::dsl::{align, fmt, inst, r, rex, rw, vex, w};
3+
4+
#[rustfmt::skip] // Keeps instructions on a single line.
5+
pub fn list() -> Vec<Inst> {
6+
vec![
7+
inst("palignr", fmt("A", [rw(xmm1), r(align(xmm_m128)), r(imm8)]), rex([0x66, 0x0F, 0x3A, 0x0F]).ib(), _64b | compat | ssse3).alt(avx, "vpalignr_b"),
8+
inst("vpalignr", fmt("B", [w(xmm1), r(xmm2), r(xmm_m128), r(imm8)]), vex(L128)._66()._0f3a().ib().op(0x0F), _64b | compat | avx),
9+
]
10+
}

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