Enable LoongArch target

build-scripts/build_llvm.py

@@ -108,7 +108,7 @@ def build_llvm(llvm_dir, platform, backends, projects, use_clang=False, extra_fl
     LLVM_TARGETS_TO_BUILD = [
         '-DLLVM_TARGETS_TO_BUILD:STRING="' + ";".join(normal_backends) + '"'
         if normal_backends
-        else '-DLLVM_TARGETS_TO_BUILD:STRING="AArch64;ARM;Mips;RISCV;X86"'
+        else '-DLLVM_TARGETS_TO_BUILD:STRING="AArch64;ARM;Mips;RISCV;LoongArch;X86"'
     ]
 
     # if not on ARC platform, but want to add expeirmental backend ARC as target
@@ -307,6 +307,11 @@ def main():
             "repo_ssh": "git@github.com:espressif/llvm-project.git",
             "branch": "xtensa_release_17.0.1",
         },
+        "loongarch": {
+            "repo": "https://github.com/llvm/llvm-project.git",
+            "repo_ssh": "git@github.com:llvm/llvm-project.git",
+            "branch": "release/19.x",
+        },
         "default": {
             "repo": "https://github.com/llvm/llvm-project.git",
             "repo_ssh": "git@github.com:llvm/llvm-project.git",

build-scripts/config_common.cmake

@@ -43,6 +43,16 @@ elseif (WAMR_BUILD_TARGET STREQUAL "RISCV32_ILP32F")
   add_definitions(-DBUILD_TARGET_RISCV32_ILP32F)
 elseif (WAMR_BUILD_TARGET STREQUAL "RISCV32_ILP32")
   add_definitions(-DBUILD_TARGET_RISCV32_ILP32)
+elseif (WAMR_BUILD_TARGET STREQUAL "LOONGARCH64" OR WAMR_BUILD_TARGET STREQUAL "LOONGARCH64_LP64D")
+  add_definitions(-DBUILD_TARGET_LOONGARCH64_LP64D)
+elseif (WAMR_BUILD_TARGET STREQUAL "LOONGARCH64_LP64")
+  add_definitions(-DBUILD_TARGET_LOONGARCH64_LP64)
+elseif (WAMR_BUILD_TARGET STREQUAL "LOONGARCH32" OR WAMR_BUILD_TARGET STREQUAL "LOONGARCH32_ILP32D")
+  add_definitions(-DBUILD_TARGET_LOONGARCH32_ILP32D)
+elseif (WAMR_BUILD_TARGET STREQUAL "LOONGARCH32_ILP32F")
+  add_definitions(-DBUILD_TARGET_LOONGARCH32_ILP32F)
+elseif (WAMR_BUILD_TARGET STREQUAL "LOONGARCH32_ILP32")
+  add_definitions(-DBUILD_TARGET_LOONGARCH32_ILP32)
 elseif (WAMR_BUILD_TARGET STREQUAL "ARC")
   add_definitions(-DBUILD_TARGET_ARC)
 else ()
@@ -55,7 +65,8 @@ endif ()
 
 if (CMAKE_SIZEOF_VOID_P EQUAL 8)
   if (WAMR_BUILD_TARGET STREQUAL "X86_64" OR WAMR_BUILD_TARGET STREQUAL "AMD_64"
-      OR WAMR_BUILD_TARGET MATCHES "AARCH64.*" OR WAMR_BUILD_TARGET MATCHES "RISCV64.*")
+      OR WAMR_BUILD_TARGET MATCHES "AARCH64.*" OR WAMR_BUILD_TARGET MATCHES "RISCV64.*"
+      OR WAMR_BUILD_TARGET MATCHES "LOONGARCH64.*")
     if (NOT WAMR_BUILD_PLATFORM STREQUAL "windows")
       # Add -fPIC flag if build as 64-bit
       set (CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -fPIC")
@@ -317,11 +328,12 @@ else ()
   message ("     Wakeup of blocking operations enabled")
 endif ()
 if (WAMR_BUILD_SIMD EQUAL 1)
-  if (NOT WAMR_BUILD_TARGET MATCHES "RISCV64.*")
+  if ((NOT WAMR_BUILD_TARGET MATCHES "RISCV64.*")
+      AND (NOT WAMR_BUILD_TARGET MATCHES "LOONGARCH64.*"))
     add_definitions (-DWASM_ENABLE_SIMD=1)
     message ("     SIMD enabled")
   else ()
-    message ("     SIMD disabled due to not supported on target RISCV64")
+    message ("     SIMD disabled due to not supported on target RISCV64 or LOONGARCH64")
   endif ()
 endif ()
 if (WAMR_BUILD_AOT_STACK_FRAME EQUAL 1)

build-scripts/runtime_lib.cmake

@@ -31,11 +31,14 @@ endif ()
 # Set WAMR_BUILD_TARGET, currently values supported:
 # "X86_64", "AMD_64", "X86_32", "AARCH64[sub]", "ARM[sub]", "THUMB[sub]",
 # "MIPS", "XTENSA", "RISCV64[sub]", "RISCV32[sub]"
+# "LOONGARCH64[sub]", "LOONGARCH32[sub]"
 if (NOT DEFINED WAMR_BUILD_TARGET)
     if (CMAKE_SYSTEM_PROCESSOR MATCHES "^(arm64|aarch64)")
         set (WAMR_BUILD_TARGET "AARCH64")
     elseif (CMAKE_SYSTEM_PROCESSOR STREQUAL "riscv64")
         set (WAMR_BUILD_TARGET "RISCV64")
+    elseif (CMAKE_SYSTEM_PROCESSOR STREQUAL "loongarch64")
+        set (WAMR_BUILD_TARGET "LOONGARCH64")
     elseif (CMAKE_SIZEOF_VOID_P EQUAL 8)
         # Build as X86_64 by default in 64-bit platform
         set (WAMR_BUILD_TARGET "X86_64")

core/config.h

@@ -22,6 +22,11 @@
     && !defined(BUILD_TARGET_RISCV32_ILP32D) \
     && !defined(BUILD_TARGET_RISCV32_ILP32F) \
     && !defined(BUILD_TARGET_RISCV32_ILP32) \
+    && !defined(BUILD_TARGET_LOONGARCH64_LP64D) \
+    && !defined(BUILD_TARGET_LOONGARCH64_LP64) \
+    && !defined(BUILD_TARGET_LOONGARCH32_ILP32D) \
+    && !defined(BUILD_TARGET_LOONGARCH32_ILP32F) \
+    && !defined(BUILD_TARGET_LOONGARCH32_ILP32) \
     && !defined(BUILD_TARGET_ARC)
 /* clang-format on */
 #if defined(__x86_64__) || defined(__x86_64)
@@ -50,6 +55,17 @@
 #define BUILD_TARGET_RISCV32_ILP32F
 #elif defined(__riscv) && (__riscv_xlen == 32) && (__riscv_flen == 64)
 #define BUILD_TARGET_RISCV32_ILP32D
+#elif defined(__loongarch) && (__loongarch_grlen == 64)
+#define BUILD_TARGET_LOONGARCH64_LP64D
+#elif defined(__loongarch) && (__loongarch_grlen == 32) \
+    && (__loongarch_frlen == 0)
+#define BUILD_TARGET_LOONGARCH32_ILP32
+#elif defined(__loongarch) && (__loongarch_grlen == 32) \
+    && (__loongarch_frlen == 32)
+#define BUILD_TARGET_LOONGARCH32_ILP32F
+#elif defined(__loongarch) && (__loongarch_grlen == 32) \
+    && (__loongarch_frlen == 64)
+#define BUILD_TARGET_LOONGARCH32_ILP32D
 #elif defined(__arc__)
 #define BUILD_TARGET_ARC
 #else

core/iwasm/aot/aot_intrinsic.c

@@ -867,6 +867,19 @@ aot_intrinsic_fill_capability_flags(AOTCompContext *comp_ctx)
             add_i64_common_intrinsics(comp_ctx);
         }
     }
+    else if (!strncmp(comp_ctx->target_arch, "loongarch", 9)) {
+        add_intrinsic_capability(comp_ctx, AOT_INTRINSIC_FLAG_I32_CONST);
+        /*
+         * Note: Use builtin intrinsics since hardware float operation
+         * will cause rodata relocation
+         */
+        add_f32_common_intrinsics(comp_ctx);
+        add_f64_common_intrinsics(comp_ctx);
+        add_common_float_integer_conversion(comp_ctx);
+        if (!strncmp(comp_ctx->target_arch, "loongarch32", 11)) {
+            add_i64_common_intrinsics(comp_ctx);
+        }
+    }
     else if (!strncmp(comp_ctx->target_arch, "xtensa", 6)) {
         /*
          * Note: Use builtin intrinsics since hardware float operation

core/iwasm/aot/aot_loader.c

@@ -273,6 +273,7 @@ GET_U16_FROM_ADDR(const uint8 *p)
 #define E_MACHINE_ARC_COMPACT2 195  /* Synopsys ARCompact V2 */
 #define E_MACHINE_XTENSA 94         /* Tensilica Xtensa Architecture */
 #define E_MACHINE_RISCV 243         /* RISC-V 32/64 */
+#define E_MACHINE_LOONGARCH 253     /* LoongArch 32/64 */
 #define E_MACHINE_WIN_I386 0x14c    /* Windows i386 architecture */
 #define E_MACHINE_WIN_X86_64 0x8664 /* Windows x86-64 architecture */
 
@@ -303,7 +304,9 @@ loader_mmap(uint32 size, bool prot_exec, char *error_buf, uint32 error_buf_size)
 
 #if defined(BUILD_TARGET_X86_64) || defined(BUILD_TARGET_AMD_64) \
     || defined(BUILD_TARGET_RISCV64_LP64D)                       \
-    || defined(BUILD_TARGET_RISCV64_LP64)
+    || defined(BUILD_TARGET_RISCV64_LP64)                        \
+    || defined(BUILD_TARGET_LOONGARCH64_LP64D)                   \
+    || defined(BUILD_TARGET_LOONGARCH64_LP64)
 #if !defined(__APPLE__) && !defined(BH_PLATFORM_LINUX_SGX)
     /* The mmapped AOT data and code in 64-bit targets had better be in
        range 0 to 2G, or aot loader may fail to apply some relocations,
@@ -421,6 +424,9 @@ get_aot_file_target(AOTTargetInfo *target_info, char *target_buf,
         case E_MACHINE_RISCV:
             machine_type = "riscv";
             break;
+        case E_MACHINE_LOONGARCH:
+            machine_type = "loongarch";
+            break;
         case E_MACHINE_ARC_COMPACT:
         case E_MACHINE_ARC_COMPACT2:
             machine_type = "arc";

core/iwasm/aot/arch/aot_reloc_loongarch.c

@@ -0,0 +1,54 @@
+/*
+ * Copyright (C) 2019 Intel Corporation. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+#include "aot_reloc.h"
+
+static SymbolMap target_sym_map[] = {
+    /* clang-format off */
+    REG_COMMON_SYMBOLS
+    /* clang-format on */
+};
+
+void
+get_current_target(char *target_buf, uint32 target_buf_size)
+{
+    snprintf(target_buf, target_buf_size, "loongarch");
+}
+
+uint32
+get_plt_item_size(void)
+{
+    /* TODO */
+    return 0;
+}
+
+SymbolMap *
+get_target_symbol_map(uint32 *sym_num)
+{
+    *sym_num = sizeof(target_sym_map) / sizeof(SymbolMap);
+    return target_sym_map;
+}
+
+uint32
+get_plt_table_size()
+{
+    return get_plt_item_size() * (sizeof(target_sym_map) / sizeof(SymbolMap));
+}
+
+void
+init_plt_table(uint8 *plt)
+{
+    /* TODO */
+}
+
+bool
+apply_relocation(AOTModule *module, uint8 *target_section_addr,
+                 uint32 target_section_size, uint64 reloc_offset,
+                 int64 reloc_addend, uint32 reloc_type, void *symbol_addr,
+                 int32 symbol_index, char *error_buf, uint32 error_buf_size)
+{
+    /* TODO */
+    return false;
+}

core/iwasm/aot/debug/elf.h

@@ -70,14 +70,15 @@
 #define EM_SH 42          /* SuperH */
 #define EM_SPARCV9 43     /* SPARC v9 64-bit */
 #define EM_H8_300 46
-#define EM_IA_64 50  /* HP/Intel IA-64 */
-#define EM_X86_64 62 /* AMD x86-64 */
-#define EM_S390 22   /* IBM S/390 */
-#define EM_CRIS 76   /* Axis Communications 32-bit embedded processor */
-#define EM_V850 87   /* NEC v850 */
-#define EM_M32R 88   /* Renesas M32R */
-#define EM_XTENSA 94 /* Tensilica Xtensa */
-#define EM_RISCV 243 /* RISC-V */
+#define EM_IA_64 50      /* HP/Intel IA-64 */
+#define EM_X86_64 62     /* AMD x86-64 */
+#define EM_S390 22       /* IBM S/390 */
+#define EM_CRIS 76       /* Axis Communications 32-bit embedded processor */
+#define EM_V850 87       /* NEC v850 */
+#define EM_M32R 88       /* Renesas M32R */
+#define EM_XTENSA 94     /* Tensilica Xtensa */
+#define EM_RISCV 243     /* RISC-V */
+#define EM_LOONGARCH 253 /* LoongArch */
 #define EM_ALPHA 0x9026
 #define EM_CYGNUS_V850 0x9080
 #define EM_CYGNUS_M32R 0x9041

core/iwasm/aot/iwasm_aot.cmake

@@ -25,6 +25,8 @@ elseif (WAMR_BUILD_TARGET STREQUAL "XTENSA")
   set (arch_source ${IWASM_AOT_DIR}/arch/aot_reloc_xtensa.c)
 elseif (WAMR_BUILD_TARGET MATCHES "RISCV*")
   set (arch_source ${IWASM_AOT_DIR}/arch/aot_reloc_riscv.c)
+elseif (WAMR_BUILD_TARGET MATCHES "LOONGARCH*")
+  set (arch_source ${IWASM_AOT_DIR}/arch/aot_reloc_loongarch.c)
 elseif (WAMR_BUILD_TARGET STREQUAL "ARC")
   set (arch_source ${IWASM_AOT_DIR}/arch/aot_reloc_arc.c)
 else ()

core/iwasm/common/arch/invokeNative_loongarch.S

@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2019 Intel Corporation.  All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ */
+
+        .text
+        .align  2
+#ifndef BH_PLATFORM_DARWIN
+        .globl invokeNative
+        .type  invokeNative, function
+invokeNative:
+#else
+        .globl _invokeNative
+_invokeNative:
+#endif /* end of BH_PLATFORM_DARWIN */
+
+/*
+ * Arguments passed in:
+ *
+ * function ptr
+ * argv
+ * nstacks
+ */
+
+    /* TODO */

core/iwasm/common/iwasm_common.cmake

@@ -89,6 +89,8 @@ elseif (WAMR_BUILD_TARGET STREQUAL "XTENSA")
   set (source_all ${c_source_all} ${IWASM_COMMON_DIR}/arch/invokeNative_xtensa.s)
 elseif (WAMR_BUILD_TARGET MATCHES "RISCV*")
   set (source_all ${c_source_all} ${IWASM_COMMON_DIR}/arch/invokeNative_riscv.S)
+elseif (WAMR_BUILD_TARGET MATCHES "LOONGARCH*")
+  set (source_all ${c_source_all} ${IWASM_COMMON_DIR}/arch/invokeNative_loongarch.S)
 elseif (WAMR_BUILD_TARGET STREQUAL "ARC")
   set (source_all ${c_source_all} ${IWASM_COMMON_DIR}/arch/invokeNative_arc.s)
 else ()