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refactor: remove unused field
PR #3131 fixed the failing builds by allowing this field to be dead. After looking at it further the field is not being used and can be removedi completely.
1 parent 4632b6a commit 26c78c0

6 files changed

Lines changed: 4 additions & 21 deletions

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cranelift/codegen/meta/src/cdsl/isa.rs

Lines changed: 1 addition & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -2,16 +2,14 @@ use std::collections::HashSet;
22
use std::iter::FromIterator;
33

44
use crate::cdsl::cpu_modes::CpuMode;
5-
use crate::cdsl::instructions::{InstructionGroup, InstructionPredicateMap};
5+
use crate::cdsl::instructions::InstructionPredicateMap;
66
use crate::cdsl::recipes::Recipes;
77
use crate::cdsl::regs::IsaRegs;
88
use crate::cdsl::settings::SettingGroup;
99
use crate::cdsl::xform::{TransformGroupIndex, TransformGroups};
1010

1111
pub(crate) struct TargetIsa {
1212
pub name: &'static str,
13-
#[allow(dead_code)]
14-
pub instructions: InstructionGroup,
1513
pub settings: SettingGroup,
1614
pub regs: IsaRegs,
1715
pub recipes: Recipes,
@@ -27,7 +25,6 @@ pub(crate) struct TargetIsa {
2725
impl TargetIsa {
2826
pub fn new(
2927
name: &'static str,
30-
instructions: InstructionGroup,
3128
settings: SettingGroup,
3229
regs: IsaRegs,
3330
recipes: Recipes,
@@ -52,7 +49,6 @@ impl TargetIsa {
5249

5350
Self {
5451
name,
55-
instructions,
5652
settings,
5753
regs,
5854
recipes,

cranelift/codegen/meta/src/isa/arm32/mod.rs

Lines changed: 1 addition & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
use crate::cdsl::instructions::{InstructionGroupBuilder, InstructionPredicateMap};
1+
use crate::cdsl::instructions::InstructionPredicateMap;
22
use crate::cdsl::isa::TargetIsa;
33
use crate::cdsl::recipes::Recipes;
44
use crate::cdsl::regs::{IsaRegs, IsaRegsBuilder, RegBankBuilder, RegClassBuilder};
@@ -52,8 +52,6 @@ pub(crate) fn define(shared_defs: &mut SharedDefinitions) -> TargetIsa {
5252
let settings = define_settings(&shared_defs.settings);
5353
let regs = define_regs();
5454

55-
let inst_group = InstructionGroupBuilder::new(&mut shared_defs.all_instructions).build();
56-
5755
let cpu_modes = vec![];
5856

5957
// TODO implement arm32 recipes.
@@ -64,7 +62,6 @@ pub(crate) fn define(shared_defs: &mut SharedDefinitions) -> TargetIsa {
6462

6563
TargetIsa::new(
6664
"arm32",
67-
inst_group,
6865
settings,
6966
regs,
7067
recipes,

cranelift/codegen/meta/src/isa/arm64/mod.rs

Lines changed: 1 addition & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
use crate::cdsl::instructions::{InstructionGroupBuilder, InstructionPredicateMap};
1+
use crate::cdsl::instructions::InstructionPredicateMap;
22
use crate::cdsl::isa::TargetIsa;
33
use crate::cdsl::recipes::Recipes;
44
use crate::cdsl::regs::{IsaRegs, IsaRegsBuilder, RegBankBuilder, RegClassBuilder};
@@ -51,8 +51,6 @@ pub(crate) fn define(shared_defs: &mut SharedDefinitions) -> TargetIsa {
5151
let settings = define_settings(&shared_defs.settings);
5252
let regs = define_registers();
5353

54-
let inst_group = InstructionGroupBuilder::new(&mut shared_defs.all_instructions).build();
55-
5654
let cpu_modes = vec![];
5755

5856
// TODO implement arm64 recipes.
@@ -63,7 +61,6 @@ pub(crate) fn define(shared_defs: &mut SharedDefinitions) -> TargetIsa {
6361

6462
TargetIsa::new(
6563
"arm64",
66-
inst_group,
6764
settings,
6865
regs,
6966
recipes,

cranelift/codegen/meta/src/isa/riscv/mod.rs

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,4 @@
11
use crate::cdsl::cpu_modes::CpuMode;
2-
use crate::cdsl::instructions::InstructionGroupBuilder;
32
use crate::cdsl::isa::TargetIsa;
43
use crate::cdsl::regs::{IsaRegs, IsaRegsBuilder, RegBankBuilder, RegClassBuilder};
54
use crate::cdsl::settings::{PredicateNode, SettingGroup, SettingGroupBuilder};
@@ -95,8 +94,6 @@ pub(crate) fn define(shared_defs: &mut SharedDefinitions) -> TargetIsa {
9594
let settings = define_settings(&shared_defs.settings);
9695
let regs = define_registers();
9796

98-
let inst_group = InstructionGroupBuilder::new(&mut shared_defs.all_instructions).build();
99-
10097
// CPU modes for 32-bit and 64-bit operation.
10198
let mut rv_32 = CpuMode::new("RV32");
10299
let mut rv_64 = CpuMode::new("RV64");
@@ -130,7 +127,6 @@ pub(crate) fn define(shared_defs: &mut SharedDefinitions) -> TargetIsa {
130127

131128
TargetIsa::new(
132129
"riscv",
133-
inst_group,
134130
settings,
135131
regs,
136132
recipes,

cranelift/codegen/meta/src/isa/s390x/mod.rs

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
use crate::cdsl::instructions::{InstructionGroupBuilder, InstructionPredicateMap};
1+
use crate::cdsl::instructions::InstructionPredicateMap;
22
use crate::cdsl::isa::TargetIsa;
33
use crate::cdsl::recipes::Recipes;
44
use crate::cdsl::regs::IsaRegsBuilder;
@@ -44,7 +44,6 @@ fn define_settings(_shared: &SettingGroup) -> SettingGroup {
4444
}
4545

4646
pub(crate) fn define(shared_defs: &mut SharedDefinitions) -> TargetIsa {
47-
let inst_group = InstructionGroupBuilder::new(&mut shared_defs.all_instructions).build();
4847
let settings = define_settings(&shared_defs.settings);
4948
let regs = IsaRegsBuilder::new().build();
5049
let recipes = Recipes::new();
@@ -54,7 +53,6 @@ pub(crate) fn define(shared_defs: &mut SharedDefinitions) -> TargetIsa {
5453

5554
TargetIsa::new(
5655
"s390x",
57-
inst_group,
5856
settings,
5957
regs,
6058
recipes,

cranelift/codegen/meta/src/isa/x86/mod.rs

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -78,7 +78,6 @@ pub(crate) fn define(shared_defs: &mut SharedDefinitions) -> TargetIsa {
7878

7979
TargetIsa::new(
8080
"x86",
81-
inst_group,
8281
settings,
8382
regs,
8483
recipes,

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