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MarinPostmaMarinPostma
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implement winch x64 cmpxchg (#10039)
1 parent 4841cc0 commit 3ab865a

13 files changed

Lines changed: 441 additions & 0 deletions

‎tests/disas/winch/x64/atomic/rmw/cmpxchg/i32_atomic_rmw16_cmpxchgu.wat‎

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;;! target = "x86_64"
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;;! test = "winch"
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(module
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(memory 1 1 shared)
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(func (export "_start") (result i32)
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(i32.atomic.rmw16.cmpxchg_u (i32.const 0) (i32.const 42) (i32.const 1337))))
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;; wasm[0]::function[0]:
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;; pushq %rbp
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;; movq %rsp, %rbp
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;; movq 8(%rdi), %r11
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;; movq 0x10(%r11), %r11
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;; addq $0x18, %r11
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;; cmpq %rsp, %r11
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;; ja 0x82
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;; 1c: movq %rdi, %r14
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;; subq $0x10, %rsp
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;; movq %rdi, 8(%rsp)
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;; movq %rsi, (%rsp)
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;; movl $0x539, %eax
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;; movl $0x2a, %ecx
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;; movl $0, %edx
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;; andw $1, %dx
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;; cmpw $0, %dx
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;; jne 0x84
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;; 49: movl $0, %edx
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;; movq 0x58(%r14), %r11
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;; movq (%r11), %rbx
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;; addq %rdx, %rbx
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;; subq $4, %rsp
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;; movl %ecx, (%rsp)
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;; subq $4, %rsp
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;; movl %eax, (%rsp)
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;; movl (%rsp), %ecx
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;; addq $4, %rsp
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;; movl (%rsp), %eax
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;; addq $4, %rsp
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;; lock cmpxchgw %cx, (%rbx)
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;; movzwl %ax, %eax
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;; addq $0x10, %rsp
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;; popq %rbp
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;; retq
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;; 82: ud2
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;; 84: ud2

‎tests/disas/winch/x64/atomic/rmw/cmpxchg/i32_atomic_rmw8_cmpxchgu.wat‎

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;;! target = "x86_64"
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;;! test = "winch"
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(module
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(memory 1 1 shared)
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(func (export "_start") (result i32)
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(i32.atomic.rmw8.cmpxchg_u (i32.const 0) (i32.const 42) (i32.const 1337))))
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;; wasm[0]::function[0]:
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;; pushq %rbp
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;; movq %rsp, %rbp
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;; movq 8(%rdi), %r11
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;; movq 0x10(%r11), %r11
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;; addq $0x18, %r11
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;; cmpq %rsp, %r11
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;; ja 0x6e
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;; 1c: movq %rdi, %r14
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;; subq $0x10, %rsp
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;; movq %rdi, 8(%rsp)
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;; movq %rsi, (%rsp)
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;; movl $0x539, %eax
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;; movl $0x2a, %ecx
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;; movl $0, %edx
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;; movq 0x58(%r14), %r11
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;; movq (%r11), %rbx
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;; addq %rdx, %rbx
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;; subq $4, %rsp
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;; movl %ecx, (%rsp)
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;; subq $4, %rsp
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;; movl %eax, (%rsp)
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;; movl (%rsp), %ecx
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;; addq $4, %rsp
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;; movl (%rsp), %eax
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;; addq $4, %rsp
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;; lock cmpxchgb %cl, (%rbx)
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;; movzbl %al, %eax
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;; addq $0x10, %rsp
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;; popq %rbp
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;; retq
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;; 6e: ud2

‎tests/disas/winch/x64/atomic/rmw/cmpxchg/i32_atomic_rmw_cmpxchg.wat‎

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;;! target = "x86_64"
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;;! test = "winch"
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(module
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(memory 1 1 shared)
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(func (export "_start") (result i32)
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(i32.atomic.rmw.cmpxchg (i32.const 0) (i32.const 42) (i32.const 1337))))
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;; wasm[0]::function[0]:
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;; pushq %rbp
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;; movq %rsp, %rbp
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;; movq 8(%rdi), %r11
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;; movq 0x10(%r11), %r11
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;; addq $0x18, %r11
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;; cmpq %rsp, %r11
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;; ja 0x7c
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;; 1c: movq %rdi, %r14
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;; subq $0x10, %rsp
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;; movq %rdi, 8(%rsp)
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;; movq %rsi, (%rsp)
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;; movl $0x539, %eax
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;; movl $0x2a, %ecx
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;; movl $0, %edx
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;; andl $3, %edx
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;; cmpl $0, %edx
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;; jne 0x7e
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;; 47: movl $0, %edx
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;; movq 0x58(%r14), %r11
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;; movq (%r11), %rbx
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;; addq %rdx, %rbx
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;; subq $4, %rsp
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;; movl %ecx, (%rsp)
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;; subq $4, %rsp
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;; movl %eax, (%rsp)
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;; movl (%rsp), %ecx
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;; addq $4, %rsp
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;; movl (%rsp), %eax
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;; addq $4, %rsp
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;; lock cmpxchgl %ecx, (%rbx)
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;; addq $0x10, %rsp
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;; popq %rbp
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;; retq
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;; 7c: ud2
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;; 7e: ud2

‎tests/disas/winch/x64/atomic/rmw/cmpxchg/i64_atomic_rmw16_cmpxchgu.wat‎

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;;! target = "x86_64"
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;;! test = "winch"
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(module
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(memory 1 1 shared)
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(func (export "_start") (result i64)
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(i64.atomic.rmw16.cmpxchg_u (i32.const 0) (i64.const 42) (i64.const 1337))))
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;; wasm[0]::function[0]:
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;; pushq %rbp
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;; movq %rsp, %rbp
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;; movq 8(%rdi), %r11
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;; movq 0x10(%r11), %r11
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;; addq $0x20, %r11
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;; cmpq %rsp, %r11
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;; ja 0x6f
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;; 1c: movq %rdi, %r14
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;; subq $0x10, %rsp
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;; movq %rdi, 8(%rsp)
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;; movq %rsi, (%rsp)
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;; movq $0x539, %rax
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;; movq $0x2a, %rcx
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;; movl $0, %edx
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;; andw $1, %dx
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;; cmpw $0, %dx
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;; jne 0x71
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;; 4d: movl $0, %edx
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;; movq 0x58(%r14), %r11
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;; movq (%r11), %rbx
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;; addq %rdx, %rbx
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;; pushq %rcx
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;; pushq %rax
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;; popq %rcx
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;; popq %rax
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;; lock cmpxchgw %cx, (%rbx)
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;; movzwq %ax, %rax
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;; addq $0x10, %rsp
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;; popq %rbp
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;; retq
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;; 6f: ud2
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;; 71: ud2

‎tests/disas/winch/x64/atomic/rmw/cmpxchg/i64_atomic_rmw32_cmpxchgu.wat‎

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;;! target = "x86_64"
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;;! test = "winch"
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(module
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(memory 1 1 shared)
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(func (export "_start") (result i64)
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(i64.atomic.rmw32.cmpxchg_u (i32.const 0) (i64.const 42) (i64.const 1337))))
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;; wasm[0]::function[0]:
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;; pushq %rbp
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;; movq %rsp, %rbp
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;; movq 8(%rdi), %r11
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;; movq 0x10(%r11), %r11
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;; addq $0x20, %r11
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;; cmpq %rsp, %r11
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;; ja 0x68
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;; 1c: movq %rdi, %r14
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;; subq $0x10, %rsp
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;; movq %rdi, 8(%rsp)
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;; movq %rsi, (%rsp)
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;; movq $0x539, %rax
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;; movq $0x2a, %rcx
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;; movl $0, %edx
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;; andl $3, %edx
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;; cmpl $0, %edx
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;; jne 0x6a
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;; 4b: movl $0, %edx
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;; movq 0x58(%r14), %r11
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;; movq (%r11), %rbx
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;; addq %rdx, %rbx
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;; pushq %rcx
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;; pushq %rax
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;; popq %rcx
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;; popq %rax
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;; lock cmpxchgl %ecx, (%rbx)
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;; addq $0x10, %rsp
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;; popq %rbp
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;; retq
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;; 68: ud2
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;; 6a: ud2

‎tests/disas/winch/x64/atomic/rmw/cmpxchg/i64_atomic_rmw8_cmpxchgu.wat‎

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;;! target = "x86_64"
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;;! test = "winch"
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(module
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(memory 1 1 shared)
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(func (export "_start") (result i64)
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(i64.atomic.rmw8.cmpxchg_u (i32.const 0) (i64.const 42) (i64.const 1337))))
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;; wasm[0]::function[0]:
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;; pushq %rbp
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;; movq %rsp, %rbp
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;; movq 8(%rdi), %r11
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;; movq 0x10(%r11), %r11
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;; addq $0x20, %r11
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;; cmpq %rsp, %r11
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;; ja 0x5b
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;; 1c: movq %rdi, %r14
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;; subq $0x10, %rsp
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;; movq %rdi, 8(%rsp)
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;; movq %rsi, (%rsp)
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;; movq $0x539, %rax
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;; movq $0x2a, %rcx
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;; movl $0, %edx
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;; movq 0x58(%r14), %r11
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;; movq (%r11), %rbx
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;; addq %rdx, %rbx
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;; pushq %rcx
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;; pushq %rax
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;; popq %rcx
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;; popq %rax
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;; lock cmpxchgb %cl, (%rbx)
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;; movzbq %al, %rax
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;; addq $0x10, %rsp
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;; popq %rbp
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;; retq
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;; 5b: ud2

‎tests/disas/winch/x64/atomic/rmw/cmpxchg/i64_atomic_rmw_cmpxchg.wat‎

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;;! target = "x86_64"
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;;! test = "winch"
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(module
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(memory 1 1 shared)
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(func (export "_start") (result i64)
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(i64.atomic.rmw.cmpxchg (i32.const 0) (i64.const 42) (i64.const 1337))))
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;; wasm[0]::function[0]:
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;; pushq %rbp
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;; movq %rsp, %rbp
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;; movq 8(%rdi), %r11
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;; movq 0x10(%r11), %r11
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;; addq $0x20, %r11
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;; cmpq %rsp, %r11
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;; ja 0x6b
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;; 1c: movq %rdi, %r14
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;; subq $0x10, %rsp
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;; movq %rdi, 8(%rsp)
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;; movq %rsi, (%rsp)
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;; movq $0x539, %rax
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;; movq $0x2a, %rcx
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;; movl $0, %edx
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;; andq $7, %rdx
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;; cmpq $0, %rdx
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;; jne 0x6d
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;; 4d: movl $0, %edx
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;; movq 0x58(%r14), %r11
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;; movq (%r11), %rbx
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;; addq %rdx, %rbx
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;; pushq %rcx
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;; pushq %rax
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;; popq %rcx
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;; popq %rax
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;; lock cmpxchgq %rcx, (%rbx)
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;; addq $0x10, %rsp
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;; popq %rbp
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;; retq
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;; 6b: ud2
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;; 6d: ud2

‎winch/codegen/src/codegen/mod.rs‎

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@@ -1384,6 +1384,39 @@ where
13841384

13851385
Ok(())
13861386
}
1387+
1388+
pub(crate) fn emit_atomic_cmpxchg(
1389+
&mut self,
1390+
arg: &MemArg,
1391+
size: OperandSize,
1392+
extend: Option<Extend<Zero>>,
1393+
) -> Result<()> {
1394+
// Emission for this instruction is a bit trickier. The address for the CAS is the 3rd from
1395+
// the top of the stack, and we must emit instruction to compute the actual address with
1396+
// `emit_compute_heap_address_align_checked`, while we still have access to self. However,
1397+
// some ISAs have requirements with regard to the registers used for some arguments, so we
1398+
// need to pass the context to the masm. To solve this issue, we pop the two first
1399+
// arguments from the stack, compute the address, push back the arguments, and hand over
1400+
// the control to masm. The implementer of `atomic_cas` can expect to find `expected` and
1401+
// `replacement` at the top the context's stack.
1402+
1403+
// pop the args
1404+
let replacement = self.context.pop_to_reg(self.masm, None)?;
1405+
let expected = self.context.pop_to_reg(self.masm, None)?;
1406+
1407+
if let Some(addr) = self.emit_compute_heap_address_align_checked(arg, size)? {
1408+
// push back the args
1409+
self.context.stack.push(expected.into());
1410+
self.context.stack.push(replacement.into());
1411+
1412+
let src = self.masm.address_at_reg(addr, 0)?;
1413+
self.masm
1414+
.atomic_cas(&mut self.context, src, size, UNTRUSTED_FLAGS, extend)?;
1415+
1416+
self.context.free_reg(addr);
1417+
}
1418+
Ok(())
1419+
}
13871420
}
13881421

13891422
/// Returns the index of the [`ControlStackFrame`] for the given

‎winch/codegen/src/isa/aarch64/masm.rs‎

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@@ -928,6 +928,17 @@ impl Masm for MacroAssembler {
928928
) -> Result<()> {
929929
bail!(CodeGenError::unimplemented_masm_instruction())
930930
}
931+
932+
fn atomic_cas(
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&mut self,
934+
_context: &mut CodeGenContext<Emission>,
935+
_addr: Self::Address,
936+
_size: OperandSize,
937+
_flags: MemFlags,
938+
_extend: Option<Extend<Zero>>,
939+
) -> Result<()> {
940+
Err(anyhow!(CodeGenError::unimplemented_masm_instruction()))
941+
}
931942
}
932943

933944
impl MacroAssembler {

‎winch/codegen/src/isa/x64/asm.rs‎

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Original file line numberDiff line numberDiff line change
@@ -1196,6 +1196,32 @@ impl Assembler {
11961196
dst_old: dst.map(Into::into),
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});
11981198
}
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pub fn cmpxchg(
1200+
&mut self,
1201+
addr: Address,
1202+
expected: Reg,
1203+
replacement: Reg,
1204+
dst: WritableReg,
1205+
size: OperandSize,
1206+
flags: MemFlags,
1207+
) {
1208+
assert!(addr.is_offset());
1209+
let mem = Self::to_synthetic_amode(
1210+
&addr,
1211+
&mut self.pool,
1212+
&mut self.constants,
1213+
&mut self.buffer,
1214+
flags,
1215+
);
1216+
1217+
self.emit(Inst::LockCmpxchg {
1218+
ty: Type::int_with_byte_size(size.bytes() as _).unwrap(),
1219+
replacement: replacement.into(),
1220+
expected: expected.into(),
1221+
mem,
1222+
dst_old: dst.map(Into::into),
1223+
})
1224+
}
11991225

12001226
pub fn cmp_ir(&mut self, src1: Reg, imm: i32, size: OperandSize) {
12011227
let imm = RegMemImm::imm(imm as u32);

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