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Add extend-add-pairwise instructions x64
1 parent 5737558 commit 4c97443

9 files changed

Lines changed: 135 additions & 10 deletions

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‎build.rs‎

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -192,10 +192,8 @@ fn x64_should_panic(testsuite: &str, testname: &str, strategy: &str) -> bool {
192192

193193
match (testsuite, testname) {
194194
("simd", "simd_conversions") => return true, // unknown operator or unexpected token: tests/spec_testsuite/proposals/simd/simd_conversions.wast:724:6
195-
("simd", "simd_i16x8_extadd_pairwise_i8x16") => return true,
196195
("simd", "simd_i16x8_extmul_i8x16") => return true,
197196
("simd", "simd_i16x8_q15mulr_sat_s") => return true,
198-
("simd", "simd_i32x4_extadd_pairwise_i16x8") => return true,
199197
("simd", "simd_i32x4_extmul_i16x8") => return true,
200198
("simd", "simd_i32x4_trunc_sat_f64x2") => return true,
201199
("simd", "simd_i64x2_extmul_i32x4") => return true,
@@ -232,10 +230,8 @@ fn ignore(testsuite: &str, testname: &str, strategy: &str) -> bool {
232230
// These are new instructions that are not really implemented in any backend.
233231
("simd", "simd_i8x16_arith2")
234232
| ("simd", "simd_conversions")
235-
| ("simd", "simd_i16x8_extadd_pairwise_i8x16")
236233
| ("simd", "simd_i16x8_extmul_i8x16")
237234
| ("simd", "simd_i16x8_q15mulr_sat_s")
238-
| ("simd", "simd_i32x4_extadd_pairwise_i16x8")
239235
| ("simd", "simd_i32x4_extmul_i16x8")
240236
| ("simd", "simd_i32x4_trunc_sat_f64x2")
241237
| ("simd", "simd_i64x2_extmul_i32x4") => return true,

‎cranelift/codegen/meta/src/shared/instructions.rs‎

Lines changed: 28 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4068,7 +4068,34 @@ pub(crate) fn define(
40684068
Inst::new(
40694069
"uwiden_high",
40704070
r#"
4071-
Widen the high lanes of `x` using unsigned extension.
4071+
Lane-wise integer extended pairwise addition producing extended results
4072+
(twice wider results than the input)
4073+
"#,
4074+
&formats.unary,
4075+
)
4076+
.operands_in(vec![x])
4077+
.operands_out(vec![a]),
4078+
);
4079+
4080+
ig.push(
4081+
Inst::new(
4082+
"extended_pairwise_add_signed",
4083+
r#"
4084+
Widen the high lanes of `x` using signed extension.
4085+
4086+
This will double the lane width and halve the number of lanes.
4087+
"#,
4088+
&formats.unary,
4089+
)
4090+
.operands_in(vec![x])
4091+
.operands_out(vec![a]),
4092+
);
4093+
4094+
ig.push(
4095+
Inst::new(
4096+
"extended_pairwise_add_unsigned",
4097+
r#"
4098+
Widen the high lanes of `x` extending with zeros.
40724099
40734100
This will double the lane width and halve the number of lanes.
40744101
"#,

‎cranelift/codegen/src/isa/aarch64/lower_inst.rs‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3359,6 +3359,8 @@ pub(crate) fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
33593359
Opcode::FcvtLowFromSint => unimplemented!("FcvtLowFromSint"),
33603360
Opcode::FvpromoteLow => unimplemented!("FvpromoteLow"),
33613361
Opcode::Fvdemote => unimplemented!("Fvdemote"),
3362+
Opcode::ExtendedPairwiseAddSigned => unimplemented!("ExtendedPairwiseAddSigned"),
3363+
Opcode::ExtendedPairwiseAddUnsigned => unimplemented!("ExtendedPairwiseAddUnsigned"),
33623364
}
33633365

33643366
Ok(())

‎cranelift/codegen/src/isa/s390x/lower.rs‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2550,7 +2550,9 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
25502550
| Opcode::UwidenHigh
25512551
| Opcode::WideningPairwiseDotProductS
25522552
| Opcode::FvpromoteLow
2553-
| Opcode::Fvdemote => {
2553+
| Opcode::Fvdemote
2554+
| Opcode::ExtendedPairwiseAddSigned
2555+
| Opcode::ExtendedPairwiseAddUnsigned => {
25542556
// TODO
25552557
panic!("Vector ops not implemented.");
25562558
}

‎cranelift/codegen/src/isa/x64/inst/args.rs‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -567,6 +567,7 @@ pub enum SseOpcode {
567567
Pinsrb,
568568
Pinsrw,
569569
Pinsrd,
570+
Pmaddubsw,
570571
Pmaddwd,
571572
Pmaxsb,
572573
Pmaxsw,
@@ -734,6 +735,7 @@ impl SseOpcode {
734735
| SseOpcode::Pcmpgtd
735736
| SseOpcode::Pextrw
736737
| SseOpcode::Pinsrw
738+
| SseOpcode::Pmaddubsw
737739
| SseOpcode::Pmaddwd
738740
| SseOpcode::Pmaxsw
739741
| SseOpcode::Pmaxub
@@ -925,6 +927,7 @@ impl fmt::Debug for SseOpcode {
925927
SseOpcode::Pinsrb => "pinsrb",
926928
SseOpcode::Pinsrw => "pinsrw",
927929
SseOpcode::Pinsrd => "pinsrd",
930+
SseOpcode::Pmaddubsw => "pmaddubsw",
928931
SseOpcode::Pmaddwd => "pmaddwd",
929932
SseOpcode::Pmaxsb => "pmaxsb",
930933
SseOpcode::Pmaxsw => "pmaxsw",

‎cranelift/codegen/src/isa/x64/inst/emit.rs‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1483,6 +1483,7 @@ pub(crate) fn emit(
14831483
SseOpcode::Paddsw => (LegacyPrefixes::_66, 0x0FED, 2),
14841484
SseOpcode::Paddusb => (LegacyPrefixes::_66, 0x0FDC, 2),
14851485
SseOpcode::Paddusw => (LegacyPrefixes::_66, 0x0FDD, 2),
1486+
SseOpcode::Pmaddubsw => (LegacyPrefixes::_66, 0x0F3804, 3),
14861487
SseOpcode::Pand => (LegacyPrefixes::_66, 0x0FDB, 2),
14871488
SseOpcode::Pandn => (LegacyPrefixes::_66, 0x0FDF, 2),
14881489
SseOpcode::Pavgb => (LegacyPrefixes::_66, 0x0FE0, 2),

‎cranelift/codegen/src/isa/x64/lower.rs‎

Lines changed: 80 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4472,6 +4472,86 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
44724472
}
44734473
}
44744474
}
4475+
Opcode::ExtendedPairwiseAddSigned | Opcode::ExtendedPairwiseAddUnsigned => {
4476+
4477+
// Extended pairwise addition instructions computes extended sums within adjacent
4478+
// pairs of lanes of a SIMD vector, producing a SIMD vector with half as many lanes.
4479+
// Instruction sequences taken from instruction SPEC PR https://github.com/WebAssembly/simd/pull/380
4480+
4481+
let input_ty = ctx.input_ty(insn, 0);
4482+
let output_ty = ctx.output_ty(insn, 0);
4483+
let src = put_input_in_reg(ctx, inputs[0]);
4484+
let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
4485+
match op {
4486+
Opcode::ExtendedPairwiseAddSigned => match (input_ty, output_ty) {
4487+
(types::I8X16, types::I16X8) => {
4488+
static MUL_CONST: [u8; 16] = [0x01; 16];
4489+
let mul_const = ctx.use_constant(VCodeConstantData::WellKnown(&MUL_CONST));
4490+
let mul_const_reg = ctx.alloc_tmp(types::I8X16).only_reg().unwrap();
4491+
ctx.emit(Inst::xmm_load_const(mul_const, mul_const_reg, types::I8X16));
4492+
ctx.emit(Inst::xmm_mov(
4493+
SseOpcode::Movdqa,
4494+
RegMem::reg(mul_const_reg.to_reg()),
4495+
dst,
4496+
));
4497+
ctx.emit(Inst::xmm_rm_r(SseOpcode::Pmaddubsw, RegMem::reg(src), dst));
4498+
},
4499+
(types::I16X8, types::I32X4) => {
4500+
static MUL_CONST: [u8; 16] = [0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00];
4501+
let mul_const = ctx.use_constant(VCodeConstantData::WellKnown(&MUL_CONST));
4502+
let mul_const_reg = ctx.alloc_tmp(types::I16X8).only_reg().unwrap();
4503+
ctx.emit(Inst::xmm_load_const(mul_const, mul_const_reg, types::I16X8));
4504+
ctx.emit(Inst::xmm_mov(
4505+
SseOpcode::Movdqa,
4506+
RegMem::reg(src),
4507+
dst,
4508+
));
4509+
ctx.emit(Inst::xmm_rm_r(SseOpcode::Pmaddwd, RegMem::reg(mul_const_reg.to_reg()), dst));
4510+
},
4511+
_ => unreachable!("Type pattern not supported {:?}-{:?} not supported for {:?}.", input_ty, output_ty, op),
4512+
},
4513+
Opcode::ExtendedPairwiseAddUnsigned => match (input_ty, output_ty) {
4514+
(types::I8X16, types::I16X8) => {
4515+
static MUL_CONST: [u8; 16] = [0x01; 16];
4516+
let mul_const = ctx.use_constant(VCodeConstantData::WellKnown(&MUL_CONST));
4517+
let mul_const_reg = ctx.alloc_tmp(types::I8X16).only_reg().unwrap();
4518+
ctx.emit(Inst::xmm_load_const(mul_const, mul_const_reg, types::I8X16));
4519+
ctx.emit(Inst::xmm_mov(
4520+
SseOpcode::Movdqa,
4521+
RegMem::reg(src),
4522+
dst,
4523+
));
4524+
ctx.emit(Inst::xmm_rm_r(SseOpcode::Pmaddubsw, RegMem::reg(mul_const_reg.to_reg()), dst));
4525+
},
4526+
(types::I16X8, types::I32X4) => {
4527+
static PXOR_CONST: [u8; 16] = [0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80];
4528+
let pxor_const = ctx.use_constant(VCodeConstantData::WellKnown(&PXOR_CONST));
4529+
let pxor_const_reg = ctx.alloc_tmp(types::I16X8).only_reg().unwrap();
4530+
ctx.emit(Inst::xmm_load_const(pxor_const, pxor_const_reg, types::I16X8));
4531+
ctx.emit(Inst::xmm_mov(
4532+
SseOpcode::Movdqa,
4533+
RegMem::reg(src),
4534+
dst,
4535+
));
4536+
ctx.emit(Inst::xmm_rm_r(SseOpcode::Pxor, RegMem::reg(pxor_const_reg.to_reg()), dst));
4537+
4538+
static MADD_CONST: [u8; 16] = [0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00];
4539+
let madd_const = ctx.use_constant(VCodeConstantData::WellKnown(&MADD_CONST));
4540+
let madd_const_reg = ctx.alloc_tmp(types::I8X16).only_reg().unwrap();
4541+
ctx.emit(Inst::xmm_load_const(madd_const, madd_const_reg, types::I16X8));
4542+
ctx.emit(Inst::xmm_rm_r(SseOpcode::Pmaddwd, RegMem::reg(madd_const_reg.to_reg()), dst));
4543+
4544+
static ADDD_CONST2: [u8; 16] = [0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00];
4545+
let addd_const2 = ctx.use_constant(VCodeConstantData::WellKnown(&ADDD_CONST2));
4546+
let addd_const2_reg = ctx.alloc_tmp(types::I8X16).only_reg().unwrap();
4547+
ctx.emit(Inst::xmm_load_const(addd_const2, addd_const2_reg, types::I16X8));
4548+
ctx.emit(Inst::xmm_rm_r(SseOpcode::Paddd, RegMem::reg(addd_const2_reg.to_reg()), dst));
4549+
},
4550+
_ => unreachable!("Type pattern not supported {:?}-{:?} not supported for {:?}.", input_ty, output_ty, op),
4551+
},
4552+
_ => unreachable!("{:?} not supported.", op),
4553+
}
4554+
}
44754555
Opcode::UwidenHigh | Opcode::UwidenLow | Opcode::SwidenHigh | Opcode::SwidenLow => {
44764556
let input_ty = ctx.input_ty(insn, 0);
44774557
let output_ty = ctx.output_ty(insn, 0);

‎cranelift/interpreter/src/step.rs‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -574,6 +574,8 @@ where
574574
Opcode::AtomicStore => unimplemented!("AtomicStore"),
575575
Opcode::Fence => unimplemented!("Fence"),
576576
Opcode::WideningPairwiseDotProductS => unimplemented!("WideningPairwiseDotProductS"),
577+
Opcode::ExtendedPairwiseAddSigned => unimplemented!("ExtendedPairwiseAddSigned"),
578+
Opcode::ExtendedPairwiseAddUnsigned => unimplemented!("ExtendedPairwiseAddUnsigned"),
577579

578580
// TODO: these instructions should be removed once the new backend makes these obsolete
579581
// (see https://github.com/bytecodealliance/wasmtime/issues/1936); additionally, the

‎cranelift/wasm/src/code_translator.rs‎

Lines changed: 16 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1859,6 +1859,22 @@ pub fn translate_operator<FE: FuncEnvironment + ?Sized>(
18591859
let a = pop1_with_bitcast(state, I32X4, builder);
18601860
state.push1(builder.ins().uwiden_high(a))
18611861
}
1862+
Operator::I16x8ExtAddPairwiseI8x16S => {
1863+
let a = pop1_with_bitcast(state, I8X16, builder);
1864+
state.push1(builder.ins().extended_pairwise_add_signed(a))
1865+
}
1866+
Operator::I32x4ExtAddPairwiseI16x8S => {
1867+
let a = pop1_with_bitcast(state, I16X8, builder);
1868+
state.push1(builder.ins().extended_pairwise_add_signed(a))
1869+
}
1870+
Operator::I16x8ExtAddPairwiseI8x16U => {
1871+
let a = pop1_with_bitcast(state, I8X16, builder);
1872+
state.push1(builder.ins().extended_pairwise_add_unsigned(a))
1873+
}
1874+
Operator::I32x4ExtAddPairwiseI16x8U => {
1875+
let a = pop1_with_bitcast(state, I16X8, builder);
1876+
state.push1(builder.ins().extended_pairwise_add_unsigned(a))
1877+
}
18621878
Operator::F32x4Ceil | Operator::F64x2Ceil => {
18631879
// This is something of a misuse of `type_of`, because that produces the return type
18641880
// of `op`. In this case we want the arg type, but we know it's the same as the
@@ -1899,10 +1915,6 @@ pub fn translate_operator<FE: FuncEnvironment + ?Sized>(
18991915
| Operator::I64x2ExtMulHighI32x4S
19001916
| Operator::I64x2ExtMulLowI32x4U
19011917
| Operator::I64x2ExtMulHighI32x4U
1902-
| Operator::I16x8ExtAddPairwiseI8x16S
1903-
| Operator::I16x8ExtAddPairwiseI8x16U
1904-
| Operator::I32x4ExtAddPairwiseI16x8S
1905-
| Operator::I32x4ExtAddPairwiseI16x8U
19061918
| Operator::F64x2ConvertLowI32x4U
19071919
| Operator::I32x4TruncSatF64x2SZero
19081920
| Operator::I32x4TruncSatF64x2UZero => {

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