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cfallincfallin
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Merge pull request #3035 from akirilov-arm/simd_i16x8_q15mulr_sat_s
Enable the simd_i16x8_q15mulr_sat_s test on AArch64
2 parents d42c869 + 98f1ac7 commit 522cc8a

11 files changed

Lines changed: 110 additions & 22 deletions

File tree

‎build.rs‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -231,7 +231,6 @@ fn ignore(testsuite: &str, testname: &str, strategy: &str) -> bool {
231231
("simd", "simd_conversions")
232232
| ("simd", "simd_i16x8_extadd_pairwise_i8x16")
233233
| ("simd", "simd_i16x8_extmul_i8x16")
234-
| ("simd", "simd_i16x8_q15mulr_sat_s")
235234
| ("simd", "simd_i32x4_extadd_pairwise_i16x8")
236235
| ("simd", "simd_i32x4_extmul_i16x8")
237236
| ("simd", "simd_i32x4_trunc_sat_f64x2")

‎cranelift/codegen/meta/src/shared/instructions.rs‎

Lines changed: 27 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2479,6 +2479,33 @@ pub(crate) fn define(
24792479
.operands_out(vec![a]),
24802480
);
24812481

2482+
let I16or32 = &TypeVar::new(
2483+
"I16or32",
2484+
"A scalar or vector integer type with 16- or 32-bit numbers",
2485+
TypeSetBuilder::new().ints(16..32).simd_lanes(4..8).build(),
2486+
);
2487+
2488+
let qx = &Operand::new("x", I16or32);
2489+
let qy = &Operand::new("y", I16or32);
2490+
let qa = &Operand::new("a", I16or32);
2491+
2492+
ig.push(
2493+
Inst::new(
2494+
"sqmul_round_sat",
2495+
r#"
2496+
Fixed-point multiplication of numbers in the QN format, where N + 1
2497+
is the number bitwidth:
2498+
`a := signed_saturate((x * y + 1 << (Q - 1)) >> Q)`
2499+
2500+
Polymorphic over all integer types (scalar and vector) with 16- or
2501+
32-bit numbers.
2502+
"#,
2503+
&formats.binary,
2504+
)
2505+
.operands_in(vec![qx, qy])
2506+
.operands_out(vec![qa]),
2507+
);
2508+
24822509
ig.push(
24832510
Inst::new(
24842511
"udiv",

‎cranelift/codegen/src/isa/aarch64/inst/emit.rs‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2228,6 +2228,14 @@ impl MachInstEmit for Inst {
22282228
VecALUOp::Zip1 => (0b01001110_00_0 | enc_size << 1, 0b001110),
22292229
VecALUOp::Smull => (0b000_01110_00_1 | enc_size << 1, 0b110000),
22302230
VecALUOp::Smull2 => (0b010_01110_00_1 | enc_size << 1, 0b110000),
2231+
VecALUOp::Sqrdmulh => {
2232+
debug_assert!(
2233+
size.lane_size() == ScalarSize::Size16
2234+
|| size.lane_size() == ScalarSize::Size32
2235+
);
2236+
2237+
(0b001_01110_00_1 | enc_size << 1, 0b101101)
2238+
}
22312239
};
22322240
let top11 = match alu_op {
22332241
VecALUOp::Smull | VecALUOp::Smull2 => top11,

‎cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs‎

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3610,6 +3610,30 @@ fn test_aarch64_binemit() {
36103610
"smull2 v8.2d, v12.4s, v14.4s",
36113611
));
36123612

3613+
insns.push((
3614+
Inst::VecRRR {
3615+
alu_op: VecALUOp::Sqrdmulh,
3616+
rd: writable_vreg(31),
3617+
rn: vreg(0),
3618+
rm: vreg(31),
3619+
size: VectorSize::Size16x8,
3620+
},
3621+
"1FB47F6E",
3622+
"sqrdmulh v31.8h, v0.8h, v31.8h",
3623+
));
3624+
3625+
insns.push((
3626+
Inst::VecRRR {
3627+
alu_op: VecALUOp::Sqrdmulh,
3628+
rd: writable_vreg(7),
3629+
rn: vreg(7),
3630+
rm: vreg(23),
3631+
size: VectorSize::Size32x2,
3632+
},
3633+
"E7B4B72E",
3634+
"sqrdmulh v7.2s, v7.2s, v23.2s",
3635+
));
3636+
36133637
insns.push((
36143638
Inst::VecMisc {
36153639
op: VecMisc2::Not,

‎cranelift/codegen/src/isa/aarch64/inst/mod.rs‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -311,6 +311,8 @@ pub enum VecALUOp {
311311
Smull,
312312
/// Signed multiply long (high halves)
313313
Smull2,
314+
/// Signed saturating rounding doubling multiply returning high half
315+
Sqrdmulh,
314316
}
315317

316318
/// A Vector miscellaneous operation with two registers.
@@ -3980,6 +3982,7 @@ impl Inst {
39803982
VecALUOp::Zip1 => ("zip1", size),
39813983
VecALUOp::Smull => ("smull", size),
39823984
VecALUOp::Smull2 => ("smull2", size),
3985+
VecALUOp::Sqrdmulh => ("sqrdmulh", size),
39833986
};
39843987
let rd_size = match alu_op {
39853988
VecALUOp::Umlal | VecALUOp::Smull | VecALUOp::Smull2 => size.widen(),

‎cranelift/codegen/src/isa/aarch64/lower_inst.rs‎

Lines changed: 29 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1650,8 +1650,6 @@ pub(crate) fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
16501650
panic!("table_addr should have been removed by legalization!");
16511651
}
16521652

1653-
Opcode::ConstAddr => unimplemented!(),
1654-
16551653
Opcode::Nop => {
16561654
// Nothing.
16571655
}
@@ -2684,11 +2682,6 @@ pub(crate) fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
26842682
});
26852683
}
26862684

2687-
Opcode::Vsplit | Opcode::Vconcat => {
2688-
// TODO
2689-
panic!("Vector ops not implemented.");
2690-
}
2691-
26922685
Opcode::Isplit => {
26932686
assert_eq!(
26942687
ctx.input_ty(insn, 0),
@@ -3524,9 +3517,35 @@ pub(crate) fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
35243517
}
35253518
},
35263519

3527-
Opcode::FcvtLowFromSint => unimplemented!("FcvtLowFromSint"),
3528-
Opcode::FvpromoteLow => unimplemented!("FvpromoteLow"),
3529-
Opcode::Fvdemote => unimplemented!("Fvdemote"),
3520+
Opcode::SqmulRoundSat => {
3521+
let ty = ty.unwrap();
3522+
3523+
if !ty.is_vector() || (ty.lane_type() != I16 && ty.lane_type() != I32) {
3524+
return Err(CodegenError::Unsupported(format!(
3525+
"Unsupported type: {:?}",
3526+
ty
3527+
)));
3528+
}
3529+
3530+
let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
3531+
let rn = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None);
3532+
let rm = put_input_in_reg(ctx, inputs[1], NarrowValueMode::None);
3533+
3534+
ctx.emit(Inst::VecRRR {
3535+
alu_op: VecALUOp::Sqrdmulh,
3536+
rd,
3537+
rn,
3538+
rm,
3539+
size: VectorSize::from_ty(ty),
3540+
});
3541+
}
3542+
3543+
Opcode::ConstAddr
3544+
| Opcode::FcvtLowFromSint
3545+
| Opcode::Fvdemote
3546+
| Opcode::FvpromoteLow
3547+
| Opcode::Vconcat
3548+
| Opcode::Vsplit => unimplemented!("lowering {}", op),
35303549
}
35313550

35323551
Ok(())

‎cranelift/codegen/src/isa/s390x/lower.rs‎

Lines changed: 10 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -2458,11 +2458,11 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
24582458
}
24592459

24602460
Opcode::TlsValue => {
2461-
panic!("Thread-local storage support not implemented!");
2461+
unimplemented!("Thread-local storage support not implemented!");
24622462
}
24632463

24642464
Opcode::GetPinnedReg | Opcode::SetPinnedReg => {
2465-
panic!("Pinned register support not implemented!");
2465+
unimplemented!("Pinned register support not implemented!");
24662466
}
24672467

24682468
Opcode::Icmp => {
@@ -2679,10 +2679,10 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
26792679
let ty = ty.unwrap();
26802680
assert!(is_valid_atomic_transaction_ty(ty));
26812681
if endianness == Endianness::Little {
2682-
panic!("Little-endian atomic operations not implemented");
2682+
unimplemented!("Little-endian atomic operations not implemented");
26832683
}
26842684
if ty_bits(ty) < 32 {
2685-
panic!("Sub-word atomic operations not implemented");
2685+
unimplemented!("Sub-word atomic operations not implemented");
26862686
}
26872687
let op = inst_common::AtomicRmwOp::from(ctx.data(insn).atomic_rmw_op().unwrap());
26882688
let (alu_op, rn) = match op {
@@ -2701,7 +2701,7 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
27012701
});
27022702
(choose_32_64(ty, ALUOp::Add32, ALUOp::Add64), tmp.to_reg())
27032703
}
2704-
_ => panic!("AtomicRmw operation type {:?} not implemented", op),
2704+
_ => unimplemented!("AtomicRmw operation type {:?} not implemented", op),
27052705
};
27062706
let mem = MemArg::reg(addr, flags);
27072707
ctx.emit(Inst::AtomicRmw {
@@ -2721,10 +2721,10 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
27212721
let ty = ty.unwrap();
27222722
assert!(is_valid_atomic_transaction_ty(ty));
27232723
if endianness == Endianness::Little {
2724-
panic!("Little-endian atomic operations not implemented");
2724+
unimplemented!("Little-endian atomic operations not implemented");
27252725
}
27262726
if ty_bits(ty) < 32 {
2727-
panic!("Sub-word atomic operations not implemented");
2727+
unimplemented!("Sub-word atomic operations not implemented");
27282728
}
27292729
let mem = MemArg::reg(addr, flags);
27302730
ctx.emit(Inst::gen_move(rd, rm, ty));
@@ -2865,13 +2865,14 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
28652865
| Opcode::UwidenLow
28662866
| Opcode::UwidenHigh
28672867
| Opcode::WideningPairwiseDotProductS
2868+
| Opcode::SqmulRoundSat
28682869
| Opcode::FvpromoteLow
28692870
| Opcode::Fvdemote => {
28702871
// TODO
2871-
panic!("Vector ops not implemented.");
2872+
unimplemented!("Vector ops not implemented.");
28722873
}
28732874

2874-
Opcode::Isplit | Opcode::Iconcat => panic!("Wide integer ops not implemented."),
2875+
Opcode::Isplit | Opcode::Iconcat => unimplemented!("Wide integer ops not implemented."),
28752876

28762877
Opcode::Spill
28772878
| Opcode::Fill

‎cranelift/codegen/src/isa/x64/lower.rs‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6001,6 +6001,8 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
60016001
unimplemented!("Vector split/concat ops not implemented.");
60026002
}
60036003

6004+
Opcode::SqmulRoundSat => unimplemented!("unimplemented lowering for opcode {:?}", op),
6005+
60046006
// Opcodes that should be removed by legalization. These should
60056007
// eventually be removed if/when we replace in-situ legalization with
60066008
// something better.

‎cranelift/codegen/src/preopt.serialized‎

0 Bytes
Binary file not shown.

‎cranelift/interpreter/src/step.rs‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -574,6 +574,7 @@ where
574574
Opcode::AtomicStore => unimplemented!("AtomicStore"),
575575
Opcode::Fence => unimplemented!("Fence"),
576576
Opcode::WideningPairwiseDotProductS => unimplemented!("WideningPairwiseDotProductS"),
577+
Opcode::SqmulRoundSat => unimplemented!("SqmulRoundSat"),
577578

578579
// TODO: these instructions should be removed once the new backend makes these obsolete
579580
// (see https://github.com/bytecodealliance/wasmtime/issues/1936); additionally, the

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