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afonso360afonso360
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riscv64: Add bitmanip extension flags (#5847)
1 parent bd3dcd3 commit 6e6a103

6 files changed

Lines changed: 145 additions & 75 deletions

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‎cranelift/codegen/meta/src/isa/riscv64.rs‎

Lines changed: 42 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -11,13 +11,50 @@ fn define_settings(_shared: &SettingGroup) -> SettingGroup {
1111
let _has_f = setting.add_bool("has_f", "has extension F?", "", false);
1212
let _has_d = setting.add_bool("has_d", "has extension D?", "", false);
1313
let _has_v = setting.add_bool("has_v", "has extension V?", "", false);
14-
let _has_b = setting.add_bool("has_b", "has extension B?", "", false);
1514
let _has_c = setting.add_bool("has_c", "has extension C?", "", false);
16-
let _has_zbkb = setting.add_bool("has_zbkb", "has extension zbkb?", "", false);
17-
let _has_zbb = setting.add_bool("has_zbb", "has extension zbb?", "", false);
15+
let _has_zbkb = setting.add_bool(
16+
"has_zbkb",
17+
"has extension zbkb?",
18+
"Zbkb: Bit-manipulation for Cryptography",
19+
false,
20+
);
21+
let _has_zba = setting.add_bool(
22+
"has_zba",
23+
"has extension zba?",
24+
"Zba: Address Generation",
25+
false,
26+
);
27+
let _has_zbb = setting.add_bool(
28+
"has_zbb",
29+
"has extension zbb?",
30+
"Zbb: Basic bit-manipulation",
31+
false,
32+
);
33+
let _has_zbc = setting.add_bool(
34+
"has_zbc",
35+
"has extension zbc?",
36+
"Zbc: Carry-less multiplication",
37+
false,
38+
);
39+
let _has_zbx = setting.add_bool(
40+
"has_zbs",
41+
"has extension zbs?",
42+
"Zbs: Single-bit instructions",
43+
false,
44+
);
1845

19-
let _has_zicsr = setting.add_bool("has_zicsr", "has extension zicsr?", "", false);
20-
let _has_zifencei = setting.add_bool("has_zifencei", "has extension zifencei?", "", false);
46+
let _has_zicsr = setting.add_bool(
47+
"has_zicsr",
48+
"has extension zicsr?",
49+
"Zicsr: Control and Status Register (CSR) Instructions",
50+
false,
51+
);
52+
let _has_zifencei = setting.add_bool(
53+
"has_zifencei",
54+
"has extension zifencei?",
55+
"Zifencei: Instruction-Fetch Fence",
56+
false,
57+
);
2158

2259
setting.build()
2360
}

‎cranelift/codegen/src/isa/riscv64/inst.isle‎

Lines changed: 78 additions & 56 deletions
Original file line numberDiff line numberDiff line change
@@ -531,39 +531,44 @@
531531
(RemU)
532532

533533
;; RV64M Standard Extension (in addition to RV32M)
534-
535534
(Mulw)
536535
(Divw)
537536
(Divuw)
538537
(Remw)
539538
(Remuw)
540539

541-
;; bitmapip
540+
;; Zba: Address Generation Instructions
542541
(Adduw)
542+
(Sh1add)
543+
(Sh1adduw)
544+
(Sh2add)
545+
(Sh2adduw)
546+
(Sh3add)
547+
(Sh3adduw)
548+
549+
;; Zbb: Bit Manipulation Instructions
543550
(Andn)
544-
(Bclr)
545-
(Bext)
546-
(Binv)
547-
(Bset)
548-
(Clmul)
549-
(Clmulh)
550-
(Clmulr)
551+
(Orn)
552+
(Xnor)
551553
(Max)
552554
(Maxu)
553555
(Min)
554556
(Minu)
555-
(Orn)
556557
(Rol)
557558
(Rolw)
558559
(Ror)
559560
(Rorw)
560-
(Sh1add)
561-
(Sh1adduw)
562-
(Sh2add)
563-
(Sh2adduw)
564-
(Sh3add)
565-
(Sh3adduw)
566-
(Xnor)
561+
562+
;; Zbs: Single-bit instructions
563+
(Bclr)
564+
(Bext)
565+
(Binv)
566+
(Bset)
567+
568+
;; Zbc: Carry-less multiplication
569+
(Clmul)
570+
(Clmulh)
571+
(Clmulr)
567572
))
568573

569574

@@ -601,6 +606,7 @@
601606

602607

603608
(type AluOPRRI (enum
609+
;; Base ISA
604610
(Addi)
605611
(Slti)
606612
(SltiU)
@@ -614,25 +620,31 @@
614620
(Slliw)
615621
(SrliW)
616622
(Sraiw)
617-
(Bclri)
618-
(Bexti)
619-
(Binvi)
620-
(Bseti)
621-
(Rori)
622-
(Roriw)
623+
624+
;; Zba: Address Generation Instructions
623625
(SlliUw)
626+
627+
;; Zbb: Bit Manipulation Instructions
624628
(Clz)
625629
(Clzw)
626-
(Cpop)
627-
(Cpopw)
628630
(Ctz)
629631
(Ctzw)
630-
(Rev8)
632+
(Cpop)
633+
(Cpopw)
631634
(Sextb)
632635
(Sexth)
633636
(Zexth)
634-
(Orcb)
637+
(Rori)
638+
(Roriw)
639+
(Rev8)
635640
(Brev8)
641+
(Orcb)
642+
643+
;; Zbs: Single-bit instructions
644+
(Bclri)
645+
(Bexti)
646+
(Binvi)
647+
(Bseti)
636648
))
637649

638650

@@ -695,6 +707,23 @@
695707
(type AMO (primitive AMO))
696708
(type VecMachLabel extern (enum))
697709

710+
;; ISA Extension helpers
711+
712+
(decl pure has_zbkb () bool)
713+
(extern constructor has_zbkb has_zbkb)
714+
715+
(decl pure has_zba () bool)
716+
(extern constructor has_zba has_zba)
717+
718+
(decl pure has_zbb () bool)
719+
(extern constructor has_zbb has_zbb)
720+
721+
(decl pure has_zbc () bool)
722+
(extern constructor has_zbc has_zbc)
723+
724+
(decl pure has_zbs () bool)
725+
(extern constructor has_zbs has_zbs)
726+
698727
;; Helper for creating the zero register.
699728
(decl zero_reg () Reg)
700729
(extern constructor zero_reg zero_reg)
@@ -908,22 +937,24 @@
908937
(decl lower_ctz (Type Reg) Reg)
909938
(rule
910939
(lower_ctz ty x)
911-
(if-let $false (has_b))
940+
(if-let $false (has_zbb))
912941
(gen_cltz $false x ty))
913942

914943
(rule 2
915944
(lower_ctz $I64 x)
916-
(if-let $true (has_b))
945+
(if-let $true (has_zbb))
917946
(alu_rr_funct12 (AluOPRRI.Ctz) x))
918947

919948
(rule 2
920949
(lower_ctz $I32 x)
921-
(if-let $true (has_b))
950+
(if-let $true (has_zbb))
922951
(alu_rr_funct12 (AluOPRRI.Ctzw) x))
952+
923953
;;;; for I8 and I16
924954
(rule 1
925955
(lower_ctz ty x)
926-
(if-let $true (has_b))
956+
(if-let $true (has_zbb))
957+
(if-let $true (has_zbs))
927958
(let
928959
((tmp Reg (alu_rr_imm12 (AluOPRRI.Bseti) x (imm12_const (ty_bits ty)))))
929960
(alu_rr_funct12 (AluOPRRI.Ctzw) x)))
@@ -954,21 +985,21 @@
954985
(decl lower_clz (Type Reg) Reg)
955986
(rule
956987
(lower_clz ty rs)
957-
(if-let $false (has_b))
988+
(if-let $false (has_zbb))
958989
(gen_cltz $true rs ty))
959990
(rule 2
960991
(lower_clz $I64 r)
961-
(if-let $true (has_b))
992+
(if-let $true (has_zbb))
962993
(alu_rr_funct12 (AluOPRRI.Clz) r))
963994
(rule 2
964995
(lower_clz $I32 r)
965-
(if-let $true (has_b))
996+
(if-let $true (has_zbb))
966997
(alu_rr_funct12 (AluOPRRI.Clzw) r))
967998

968999
;;; for I8 and I16
9691000
(rule 1
9701001
(lower_clz ty r)
971-
(if-let $true (has_b))
1002+
(if-let $true (has_zbb))
9721003
(let
9731004
( ;; narrow int make all upper bits are zeros.
9741005
(tmp Reg (ext_int_if_need $false r ty ))
@@ -1078,30 +1109,26 @@
10781109
(alu_rr_imm12 (AluOPRRI.Srli) tmp (imm12_const (ty_bits ty)))))
10791110

10801111

1081-
;;; has extension B??
1082-
(decl pure has_b () bool)
1083-
(extern constructor has_b has_b)
1084-
10851112
(decl lower_rotl (Type Reg Reg) Reg)
10861113

10871114
(rule 1
10881115
(lower_rotl $I64 rs amount)
1089-
(if-let $true (has_b))
1116+
(if-let $true (has_zbb))
10901117
(alu_rrr (AluOPRRR.Rol) rs amount))
10911118

10921119
(rule
10931120
(lower_rotl $I64 rs amount)
1094-
(if-let $false (has_b))
1121+
(if-let $false (has_zbb))
10951122
(lower_rotl_shift $I64 rs amount))
10961123

10971124
(rule 1
10981125
(lower_rotl $I32 rs amount)
1099-
(if-let $true (has_b))
1126+
(if-let $true (has_zbb))
11001127
(alu_rrr (AluOPRRR.Rolw) rs amount))
11011128

11021129
(rule
11031130
(lower_rotl $I32 rs amount)
1104-
(if-let $false (has_b))
1131+
(if-let $false (has_zbb))
11051132
(lower_rotl_shift $I32 rs amount))
11061133

11071134
(rule -1
@@ -1136,21 +1163,21 @@
11361163

11371164
(rule 1
11381165
(lower_rotr $I64 rs amount)
1139-
(if-let $true (has_b))
1166+
(if-let $true (has_zbb))
11401167
(alu_rrr (AluOPRRR.Ror) rs amount))
11411168
(rule
11421169
(lower_rotr $I64 rs amount)
1143-
(if-let $false (has_b))
1170+
(if-let $false (has_zbb))
11441171
(lower_rotr_shift $I64 rs amount))
11451172

11461173
(rule 1
11471174
(lower_rotr $I32 rs amount)
1148-
(if-let $true (has_b))
1175+
(if-let $true (has_zbb))
11491176
(alu_rrr (AluOPRRR.Rorw) rs amount))
11501177

11511178
(rule
11521179
(lower_rotr $I32 rs amount)
1153-
(if-let $false (has_b))
1180+
(if-let $false (has_zbb))
11541181
(lower_rotr_shift $I32 rs amount))
11551182

11561183
(rule -1
@@ -1208,10 +1235,10 @@
12081235

12091236
(decl lower_popcnt (Reg Type) Reg)
12101237
(rule 1 (lower_popcnt rs ty )
1211-
(if-let $true (has_b))
1238+
(if-let $true (has_zbb))
12121239
(alu_rr_funct12 (AluOPRRI.Cpop) (ext_int_if_need $false rs ty)))
12131240
(rule (lower_popcnt rs ty)
1214-
(if-let $false (has_b))
1241+
(if-let $false (has_zbb))
12151242
(gen_popcnt rs ty))
12161243

12171244
(decl lower_popcnt_i128 (ValueRegs) ValueRegs)
@@ -1962,24 +1989,19 @@
19621989
(decl gen_rev8 (Reg) Reg)
19631990
(rule 1
19641991
(gen_rev8 rs)
1965-
(if-let $true (has_b))
1992+
(if-let $true (has_zbb))
19661993
(alu_rr_funct12 (AluOPRRI.Rev8) rs))
19671994

19681995
(rule
19691996
(gen_rev8 rs)
1970-
(if-let $false (has_b))
1997+
(if-let $false (has_zbb))
19711998
(let
19721999
((rd WritableReg (temp_writable_reg $I64))
19732000
(tmp WritableReg (temp_writable_reg $I64))
19742001
(step WritableReg (temp_writable_reg $I64))
19752002
(_ Unit (emit (MInst.Rev8 rs step tmp rd))))
19762003
(writable_reg_to_reg rd)))
19772004

1978-
(decl pure has_zbkb () bool)
1979-
(extern constructor has_zbkb has_zbkb)
1980-
1981-
(decl pure has_zbb () bool)
1982-
(extern constructor has_zbb has_zbb)
19832005

19842006
(decl gen_brev8 (Reg Type) Reg)
19852007
(rule 1

‎cranelift/codegen/src/isa/riscv64/lower.isle‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -209,19 +209,19 @@
209209
;; forms early on.
210210

211211
(rule 3 (lower (has_type (fits_in_64 ty) (band x (bnot y))))
212-
(if-let $true (has_b))
212+
(if-let $true (has_zbb))
213213
(gen_andn x y))
214214
(rule 4 (lower (has_type (fits_in_64 ty) (band (bnot y) x)))
215-
(if-let $true (has_b))
215+
(if-let $true (has_zbb))
216216
(gen_andn x y))
217217
(rule 5 (lower (has_type $I128 (band x (bnot y))))
218-
(if-let $true (has_b))
218+
(if-let $true (has_zbb))
219219
(let
220220
((low Reg (gen_andn (value_regs_get x 0) (value_regs_get y 0)))
221221
(high Reg (gen_andn (value_regs_get x 1) (value_regs_get y 1))))
222222
(value_regs low high)))
223223
(rule 6 (lower (has_type $I128 (band (bnot y) x)))
224-
(if-let $true (has_b))
224+
(if-let $true (has_zbb))
225225
(let
226226
((low Reg (gen_andn (value_regs_get x 0) (value_regs_get y 0)))
227227
(high Reg (gen_andn (value_regs_get x 1) (value_regs_get y 1))))
@@ -250,20 +250,20 @@
250250
;; forms early on.
251251

252252
(rule 3 (lower (has_type (fits_in_64 ty) (bor x (bnot y))))
253-
(if-let $true (has_b))
253+
(if-let $true (has_zbb))
254254
(gen_orn x y))
255255
(rule 4 (lower (has_type (fits_in_64 ty) (bor (bnot y) x)))
256-
(if-let $true (has_b))
256+
(if-let $true (has_zbb))
257257
(gen_orn x y))
258258

259259
(rule 5 (lower (has_type $I128 (bor x (bnot y))))
260-
(if-let $true (has_b))
260+
(if-let $true (has_zbb))
261261
(let
262262
((low Reg (gen_orn (value_regs_get x 0) (value_regs_get y 0)))
263263
(high Reg (gen_orn (value_regs_get x 1) (value_regs_get y 1))))
264264
(value_regs low high)))
265265
(rule 6 (lower (has_type $I128 (bor (bnot y) x)))
266-
(if-let $true (has_b))
266+
(if-let $true (has_zbb))
267267
(let
268268
((low Reg (gen_orn (value_regs_get x 0) (value_regs_get y 0)))
269269
(high Reg (gen_orn (value_regs_get x 1) (value_regs_get y 1))))

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