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winch(aarch64): ABI integration (#10312)
* winch(aarch64): ABI integration This commit finalizes the ABI integration between Winch and Cranelift, notably: * Updates the Cranelift ABI to ensure that all the Winch register clobbers are taken into account. * Updates the Winch ABI to treat x28 as callee-saved, since it's used as the shadow stack pointer. The alternative to treating x28 as callee-saved is to treat it as caller-saved and save it when required e.g., at call-sites, even though this approach works, it's probably more efficient to perform a store/pop once per function, to minimize the number of move instructions required. There are still some changes needed in order to fully enable running spec tests for aarch64, however, this change is one step further. If interested, you can run the call.wast test via: cargo run -- wast -Ccompiler=winch tests/spec_testsuite/call_indirect.wast * Update disas tests
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‎cranelift/codegen/src/isa/aarch64/abi.rs‎

Lines changed: 76 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1123,8 +1123,11 @@ impl ABIMachineSpec for AArch64MachineDeps {
11231123
}
11241124
}
11251125

1126-
fn get_regs_clobbered_by_call(_call_conv: isa::CallConv) -> PRegSet {
1127-
DEFAULT_AAPCS_CLOBBERS
1126+
fn get_regs_clobbered_by_call(call_conv: isa::CallConv) -> PRegSet {
1127+
match call_conv {
1128+
isa::CallConv::Winch => WINCH_CLOBBERS,
1129+
_ => DEFAULT_AAPCS_CLOBBERS,
1130+
}
11281131
}
11291132

11301133
fn get_ext_mode(
@@ -1438,7 +1441,78 @@ const fn default_aapcs_clobbers() -> PRegSet {
14381441
.with(vreg_preg(31))
14391442
}
14401443

1444+
const fn winch_clobbers() -> PRegSet {
1445+
PRegSet::empty()
1446+
.with(xreg_preg(0))
1447+
.with(xreg_preg(1))
1448+
.with(xreg_preg(2))
1449+
.with(xreg_preg(3))
1450+
.with(xreg_preg(4))
1451+
.with(xreg_preg(5))
1452+
.with(xreg_preg(6))
1453+
.with(xreg_preg(7))
1454+
.with(xreg_preg(8))
1455+
.with(xreg_preg(9))
1456+
.with(xreg_preg(10))
1457+
.with(xreg_preg(11))
1458+
.with(xreg_preg(12))
1459+
.with(xreg_preg(13))
1460+
.with(xreg_preg(14))
1461+
.with(xreg_preg(15))
1462+
.with(xreg_preg(16))
1463+
.with(xreg_preg(17))
1464+
// x18 is used to carry platform state and is not allocatable by Winch.
1465+
//
1466+
// x19 - x27 are considered caller-saved in Winch's calling convention.
1467+
.with(xreg_preg(19))
1468+
.with(xreg_preg(20))
1469+
.with(xreg_preg(21))
1470+
.with(xreg_preg(22))
1471+
.with(xreg_preg(23))
1472+
.with(xreg_preg(24))
1473+
.with(xreg_preg(25))
1474+
.with(xreg_preg(26))
1475+
.with(xreg_preg(27))
1476+
// x28 is used as the shadow stack pointer and is considered
1477+
// callee-saved.
1478+
//
1479+
// All vregs are considered caller-saved.
1480+
.with(vreg_preg(0))
1481+
.with(vreg_preg(1))
1482+
.with(vreg_preg(2))
1483+
.with(vreg_preg(3))
1484+
.with(vreg_preg(4))
1485+
.with(vreg_preg(5))
1486+
.with(vreg_preg(6))
1487+
.with(vreg_preg(7))
1488+
.with(vreg_preg(8))
1489+
.with(vreg_preg(9))
1490+
.with(vreg_preg(10))
1491+
.with(vreg_preg(11))
1492+
.with(vreg_preg(12))
1493+
.with(vreg_preg(13))
1494+
.with(vreg_preg(14))
1495+
.with(vreg_preg(15))
1496+
.with(vreg_preg(16))
1497+
.with(vreg_preg(17))
1498+
.with(vreg_preg(18))
1499+
.with(vreg_preg(19))
1500+
.with(vreg_preg(20))
1501+
.with(vreg_preg(21))
1502+
.with(vreg_preg(22))
1503+
.with(vreg_preg(23))
1504+
.with(vreg_preg(24))
1505+
.with(vreg_preg(25))
1506+
.with(vreg_preg(26))
1507+
.with(vreg_preg(27))
1508+
.with(vreg_preg(28))
1509+
.with(vreg_preg(29))
1510+
.with(vreg_preg(30))
1511+
.with(vreg_preg(31))
1512+
}
1513+
14411514
const DEFAULT_AAPCS_CLOBBERS: PRegSet = default_aapcs_clobbers();
1515+
const WINCH_CLOBBERS: PRegSet = winch_clobbers();
14421516

14431517
fn create_reg_env(enable_pinned_reg: bool) -> MachineEnv {
14441518
fn preg(r: Reg) -> PReg {

‎tests/disas/winch/aarch64/br/as_br_if_cond.wat‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,7 @@
88
;; wasm[0]::function[0]:
99
;; stp x29, x30, [sp, #-0x10]!
1010
;; mov x29, sp
11+
;; str x28, [sp, #-0x10]!
1112
;; mov x28, sp
1213
;; mov x9, x0
1314
;; sub x28, x28, #0x10
@@ -17,5 +18,6 @@
1718
;; add x28, x28, #0x10
1819
;; mov sp, x28
1920
;; mov sp, x28
21+
;; ldr x28, [sp], #0x10
2022
;; ldp x29, x30, [sp], #0x10
2123
;; ret

‎tests/disas/winch/aarch64/br/as_br_value.wat‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,7 @@
88
;; wasm[0]::function[0]:
99
;; stp x29, x30, [sp, #-0x10]!
1010
;; mov x29, sp
11+
;; str x28, [sp, #-0x10]!
1112
;; mov x28, sp
1213
;; mov x9, x0
1314
;; sub x28, x28, #0x10
@@ -19,5 +20,6 @@
1920
;; add x28, x28, #0x10
2021
;; mov sp, x28
2122
;; mov sp, x28
23+
;; ldr x28, [sp], #0x10
2224
;; ldp x29, x30, [sp], #0x10
2325
;; ret

‎tests/disas/winch/aarch64/br/as_if_cond.wat‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,7 @@
1313
;; wasm[0]::function[0]:
1414
;; stp x29, x30, [sp, #-0x10]!
1515
;; mov x29, sp
16+
;; str x28, [sp, #-0x10]!
1617
;; mov x28, sp
1718
;; mov x9, x0
1819
;; sub x28, x28, #0x10
@@ -24,5 +25,6 @@
2425
;; add x28, x28, #0x10
2526
;; mov sp, x28
2627
;; mov sp, x28
28+
;; ldr x28, [sp], #0x10
2729
;; ldp x29, x30, [sp], #0x10
2830
;; ret

‎tests/disas/winch/aarch64/br/as_if_else.wat‎

Lines changed: 7 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,7 @@
1313
;; wasm[0]::function[0]:
1414
;; stp x29, x30, [sp, #-0x10]!
1515
;; mov x29, sp
16+
;; str x28, [sp, #-0x10]!
1617
;; mov x28, sp
1718
;; mov x9, x0
1819
;; sub x28, x28, #0x18
@@ -23,14 +24,15 @@
2324
;; stur w3, [x28]
2425
;; ldur w0, [x28, #4]
2526
;; tst w0, w0
26-
;; b.eq #0x40
27-
;; b #0x38
28-
;; 38: ldur w0, [x28]
29-
;; b #0x48
30-
;; 40: mov x16, #4
27+
;; b.eq #0x44
28+
;; b #0x3c
29+
;; 3c: ldur w0, [x28]
30+
;; b #0x4c
31+
;; 44: mov x16, #4
3132
;; mov w0, w16
3233
;; add x28, x28, #0x18
3334
;; mov sp, x28
3435
;; mov sp, x28
36+
;; ldr x28, [sp], #0x10
3537
;; ldp x29, x30, [sp], #0x10
3638
;; ret

‎tests/disas/winch/aarch64/br/as_if_then.wat‎

Lines changed: 7 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,7 @@
1313
;; wasm[0]::function[0]:
1414
;; stp x29, x30, [sp, #-0x10]!
1515
;; mov x29, sp
16+
;; str x28, [sp, #-0x10]!
1617
;; mov x28, sp
1718
;; mov x9, x0
1819
;; sub x28, x28, #0x18
@@ -23,14 +24,15 @@
2324
;; stur w3, [x28]
2425
;; ldur w0, [x28, #4]
2526
;; tst w0, w0
26-
;; b.eq #0x44
27-
;; b #0x38
28-
;; 38: mov x16, #3
27+
;; b.eq #0x48
28+
;; b #0x3c
29+
;; 3c: mov x16, #3
2930
;; mov w0, w16
30-
;; b #0x48
31-
;; 44: ldur w0, [x28]
31+
;; b #0x4c
32+
;; 48: ldur w0, [x28]
3233
;; add x28, x28, #0x18
3334
;; mov sp, x28
3435
;; mov sp, x28
36+
;; ldr x28, [sp], #0x10
3537
;; ldp x29, x30, [sp], #0x10
3638
;; ret

‎tests/disas/winch/aarch64/br/as_loop_first.wat‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,7 @@
99
;; wasm[0]::function[0]:
1010
;; stp x29, x30, [sp, #-0x10]!
1111
;; mov x29, sp
12+
;; str x28, [sp, #-0x10]!
1213
;; mov x28, sp
1314
;; mov x9, x0
1415
;; sub x28, x28, #0x10
@@ -20,5 +21,6 @@
2021
;; add x28, x28, #0x10
2122
;; mov sp, x28
2223
;; mov sp, x28
24+
;; ldr x28, [sp], #0x10
2325
;; ldp x29, x30, [sp], #0x10
2426
;; ret

‎tests/disas/winch/aarch64/br/br_jump.wat‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,7 @@
1616
;; wasm[0]::function[0]:
1717
;; stp x29, x30, [sp, #-0x10]!
1818
;; mov x29, sp
19+
;; str x28, [sp, #-0x10]!
1920
;; mov x28, sp
2021
;; mov x9, x0
2122
;; sub x28, x28, #0x18
@@ -34,9 +35,10 @@
3435
;; stur w16, [x28]
3536
;; add x28, x28, #4
3637
;; mov sp, x28
37-
;; b #0x38
38-
;; 54: add x28, x28, #0x18
38+
;; b #0x3c
39+
;; 58: add x28, x28, #0x18
3940
;; mov sp, x28
4041
;; mov sp, x28
42+
;; ldr x28, [sp], #0x10
4143
;; ldp x29, x30, [sp], #0x10
4244
;; ret

‎tests/disas/winch/aarch64/br_if/as_br_if_cond.wat‎

Lines changed: 8 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,7 @@
88
;; wasm[0]::function[0]:
99
;; stp x29, x30, [sp, #-0x10]!
1010
;; mov x29, sp
11+
;; str x28, [sp, #-0x10]!
1112
;; mov x28, sp
1213
;; mov x9, x0
1314
;; sub x28, x28, #0x10
@@ -17,15 +18,16 @@
1718
;; mov x16, #1
1819
;; mov w0, w16
1920
;; tst w0, w0
20-
;; b.ne #0x48
21-
;; b #0x34
22-
;; 34: mov x16, #1
21+
;; b.ne #0x4c
22+
;; b #0x38
23+
;; 38: mov x16, #1
2324
;; mov w0, w16
2425
;; tst w0, w0
25-
;; b.ne #0x48
26-
;; b #0x48
27-
;; 48: add x28, x28, #0x10
26+
;; b.ne #0x4c
27+
;; b #0x4c
28+
;; 4c: add x28, x28, #0x10
2829
;; mov sp, x28
2930
;; mov sp, x28
31+
;; ldr x28, [sp], #0x10
3032
;; ldp x29, x30, [sp], #0x10
3133
;; ret

‎tests/disas/winch/aarch64/br_if/as_br_value.wat‎

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,7 @@
88
;; wasm[0]::function[0]:
99
;; stp x29, x30, [sp, #-0x10]!
1010
;; mov x29, sp
11+
;; str x28, [sp, #-0x10]!
1112
;; mov x28, sp
1213
;; mov x9, x0
1314
;; sub x28, x28, #0x10
@@ -19,10 +20,11 @@
1920
;; mov x16, #1
2021
;; mov w0, w16
2122
;; tst w1, w1
22-
;; b.ne #0x3c
23-
;; b #0x3c
24-
;; 3c: add x28, x28, #0x10
23+
;; b.ne #0x40
24+
;; b #0x40
25+
;; 40: add x28, x28, #0x10
2526
;; mov sp, x28
2627
;; mov sp, x28
28+
;; ldr x28, [sp], #0x10
2729
;; ldp x29, x30, [sp], #0x10
2830
;; ret

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