Fix AArch64 register-offset load/store memory operand access

Fix issue #2802 where register-offset addressing mode load and store
instructions were not correctly marking memory operands as READ/WRITE.
For example, LDRSW with register offset (ldrsw x10, [x22, x10, lsl #2])
had the memory operand access as invalid instead of READ.

The issue was in the auto-generated mapping table where roW/roX variants
incorrectly had CS_AC_INVALID instead of CS_AC_READ/CS_AC_WRITE. Since
the mapping is auto-generated and cannot be modified directly, add a
correction function AArch64_get_mem_access_for_opcode() that provides
the correct access type for these instructions.

This affects all load/store variants with register offset addressing:
- LDR*, LDRB*, LDRH*, LDRSB*, LDRSH*, LDRSW*
- STR*, STRB*, STRH*, STRD*
- PRFM

Add test case for LDRSW with register offset addressing mode.

Co-Authored-By: Claude Haiku 4.5 <noreply@anthropic.com>

Author: DanielBotnik

arch/AArch64/AArch64Mapping.c

@@ -136,6 +136,69 @@ const insn_map aarch64_insns[] = {
 #include "AArch64GenCSMappingInsn.inc"
 };
 
+// Helper function to get the correct memory access type for an instruction.
+// Corrects auto-generated mapping entries that have CS_AC_INVALID for
+// register-offset addressing modes (roW/roX variants).
+static cs_ac_type AArch64_get_mem_access(unsigned opcode)
+{
+	// Corrections for register-offset load/store instructions
+	switch (opcode) {
+	// Load instructions with register offset
+	case AArch64_LDRBBroW:
+	case AArch64_LDRBBroX:
+	case AArch64_LDRBroW:
+	case AArch64_LDRBroX:
+	case AArch64_LDRDroX:
+	case AArch64_LDRHHroW:
+	case AArch64_LDRHHroX:
+	case AArch64_LDRHroW:
+	case AArch64_LDRHroX:
+	case AArch64_LDRQroX:
+	case AArch64_LDRSBWroW:
+	case AArch64_LDRSBWroX:
+	case AArch64_LDRSBXroW:
+	case AArch64_LDRSBXroX:
+	case AArch64_LDRSHWroW:
+	case AArch64_LDRSHWroX:
+	case AArch64_LDRSHXroW:
+	case AArch64_LDRSHXroX:
+	case AArch64_LDRSWroW:
+	case AArch64_LDRSWroX:
+	case AArch64_LDRSroW:
+	case AArch64_LDRSroX:
+	case AArch64_LDRWroW:
+	case AArch64_LDRWroX:
+	case AArch64_LDRXroW:
+	case AArch64_LDRXroX:
+		return CS_AC_READ;
+	// Store instructions with register offset
+	case AArch64_STRBBroW:
+	case AArch64_STRBBroX:
+	case AArch64_STRBroW:
+	case AArch64_STRBroX:
+	case AArch64_STRDroX:
+	case AArch64_STRHHroW:
+	case AArch64_STRHHroX:
+	case AArch64_STRHroW:
+	case AArch64_STRHroX:
+	case AArch64_STRQroX:
+	case AArch64_STRSroW:
+	case AArch64_STRSroX:
+	case AArch64_STRWroW:
+	case AArch64_STRWroX:
+	case AArch64_STRXroW:
+	case AArch64_STRXroX:
+		return CS_AC_WRITE;
+	// Prefetch (read-only)
+	case AArch64_PRFMroW:
+	case AArch64_PRFMroX:
+		return CS_AC_READ;
+	default:
+		// Use the auto-generated mapping for all other instructions
+		return aarch64_insns[opcode].suppl_info.aarch64.mem_acc;
+	}
+}
+
 static const name_map insn_alias_mnem_map[] = {
 #include "AArch64GenCSAliasMnemMap.inc"
 	{ AARCH64_INS_ALIAS_CFP, "cfp" },
@@ -903,8 +966,7 @@ static void AArch64_correct_mem_access(MCInst *MI)
 #ifndef CAPSTONE_DIET
 	if (!detail_is_set(MI))
 		return;
-	cs_ac_type access =
-		aarch64_insns[MI->Opcode].suppl_info.aarch64.mem_acc;
+	cs_ac_type access = AArch64_get_mem_access(MI->Opcode);
 	if (access == CS_AC_INVALID) {
 		return;
 	}

tests/details/aarch64.yaml

@@ -1542,3 +1542,31 @@ test_cases:
             operands: []
           regs_read: []
           regs_write: []
+  -
+    input:
+      bytes: [0xca, 0x7a, 0xaa, 0xb8]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_DETAIL" ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "ldrsw x10, [x22, x10, lsl #2]"
+        details:
+          aarch64:
+            operands:
+            -
+              type: AARCH64_OP_REG
+              reg: x10
+              access: CS_AC_WRITE
+            -
+              type: AARCH64_OP_MEM
+              mem:
+                base: x22
+                index: x10
+              access: CS_AC_READ
+              shift:
+                type: AARCH64_SFT_LSL
+                value: 2
+          regs_read: [x22, x10]
+          regs_write: [x10]