Remove the call group from JAL and JALR instructions because they're not always calls, formatting

Author: moste00

MathExtras.h

@@ -63,12 +63,14 @@ static inline bool isIntN(unsigned N, int64_t x)
 }
 
 /// isShiftedIntN - Checks if a signed integer is an N bit number shifted left by S.
-static inline bool isShiftedIntN(unsigned N, unsigned S, int64_t x) {
-  return isIntN(N + S, x) && (x % (UINT64_C(1) << S) == 0);
+static inline bool isShiftedIntN(unsigned N, unsigned S, int64_t x)
+{
+	return isIntN(N + S, x) && (x % (UINT64_C(1) << S) == 0);
 }
 
-static inline bool isShiftedUIntN(unsigned N, unsigned S, uint64_t x) {
-  return isUIntN(N + S, x) && (x % (UINT64_C(1) << S) == 0);
+static inline bool isShiftedUIntN(unsigned N, unsigned S, uint64_t x)
+{
+	return isUIntN(N + S, x) && (x % (UINT64_C(1) << S) == 0);
 }
 
 /// isMask_32 - This function returns true if the argument is a sequence of ones

arch/RISCV/RISCVGenCSMappingInsn.inc

@@ -82962,7 +82962,7 @@
   /* c.jr	$rs1 */
   RISCV_C_JR /* 11772 */, RISCV_INS_C_JR,
   #ifndef CAPSTONE_DIET
-    { 0 }, { 0 }, { RISCV_GRP_JUMP, RISCV_FEATURE_HASSTDEXTCORZCA, 0 }, 1, 0, {{ 0 }}
+    { 0 }, { 0 }, { RISCV_FEATURE_HASSTDEXTCORZCA, 0 }, 0, 0, {{ 0 }}
 
   #endif
 },
@@ -85504,15 +85504,15 @@
   /* jal	$rd, $imm20 */
   RISCV_JAL /* 12092 */, RISCV_INS_JAL,
   #ifndef CAPSTONE_DIET
-    { 0 }, { 0 }, { RISCV_GRP_CALL, RISCV_GRP_BRANCH_RELATIVE, 0 }, 0, 0, {{ 0 }}
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
 
   #endif
 },
 {
   /* jalr	$rd, ${imm12}(${rs1}) */
   RISCV_JALR /* 12093 */, RISCV_INS_JALR,
   #ifndef CAPSTONE_DIET
-    { 0 }, { 0 }, { RISCV_GRP_CALL, 0 }, 0, 0, {{ 0 }}
+    { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}
 
   #endif
 },

arch/RISCV/RISCVMapping.c

@@ -1,4 +1,5 @@
 
+#include "capstone/cs_operand.h"
 #include "capstone/riscv.h"
 #include <stdint.h>
 #ifdef CAPSTONE_HAS_RISCV
@@ -166,11 +167,43 @@ static inline void RISCV_add_interrupt_ret_group(MCInst *MI)
 	}
 }
 
+// calls are implemented in RISCV as plain jumps that happen to set a link register containing the return address
+// but this link register could be given as the null register x0, discarding the return address and making them jumps
+static inline void RISCV_add_call_group(MCInst *MI)
+{
+	if (MI->Opcode == RISCV_JAL || MI->Opcode == RISCV_JALR) {
+		cs_riscv_op op = MI->flat_insn->detail->riscv.operands[0];
+		if ((op.type == (riscv_op_type)CS_OP_REG) &&
+		    op.reg != RISCV_REG_X0 && (op.access & CS_AC_WRITE)) {
+			add_group(MI, RISCV_GRP_CALL);
+		}
+		if (MI->Opcode == RISCV_JAL) {
+			add_group(MI, RISCV_GRP_BRANCH_RELATIVE);
+		}
+	}
+}
+
+// returns are implemented in RISCV as a plain indirect jump that happen to reference the return address register ra == x1
+static inline void RISCV_add_ret_group(MCInst *MI)
+{
+	if (MI->Opcode == RISCV_C_JR) {
+		cs_riscv_op op = MI->flat_insn->detail->riscv.operands[0];
+		if ((op.type == (riscv_op_type)CS_OP_REG) &&
+		    op.reg == RISCV_REG_X1) {
+			add_group(MI, RISCV_GRP_RET);
+		} else {
+			add_group(MI, RISCV_GRP_JUMP);
+		}
+	}
+}
+
 static inline void RISCV_add_adhoc_groups(MCInst *MI)
 {
 	RISCV_add_privileged_group(MI);
 	RISCV_add_interrupt_group(MI);
 	RISCV_add_interrupt_ret_group(MI);
+	RISCV_add_call_group(MI);
+	RISCV_add_ret_group(MI);
 }
 
 // for weird reasons some instructions end up with valid operands that are

bindings/python/capstone/riscv_const.py

@@ -1,6 +1,16 @@
 from . import (CS_OP_FP, CS_OP_IMM, CS_OP_INVALID, CS_OP_MEM, CS_OP_MEM_IMM, CS_OP_MEM_REG, CS_OP_PRED, CS_OP_REG, CS_OP_SPECIAL, UINT8_MAX, UINT16_MAX,)
 
 # For Capstone Engine. AUTO-GENERATED FILE DO NOT EDIT [riscv_const.py]
+#
+# ####################################################### ###########################################################
+# ####################################################### ###########################################################
+# ##################################################### TODO ########################################################
+# ########################### This file is supposed to be generated automatically by the bindings generator
+# ########################### But the generator is currently broken, so for now all new constants are manually added
+# ########################### Fix and ensure all the constants are still correctly added when the generator is fixed
+# # ####################################################### ###########################################################
+# ####################################################### ###########################################################
+# ####################################################### ###########################################################
 
 # Operand type for instruction's operands
 RISCV_OP_INVALID = CS_OP_INVALID
@@ -2938,6 +2948,10 @@
 RISCV_SYSREG_MCONFIGPTR = 0xf15
 RISCV_SYSREG_MTOPI = 0xfb0
 
+# ####################################################### ###########################################################
+# ####################################################### ###########################################################
+# ####################################################### ###########################################################
+# Add functionality to the generator script to generate this from the SYSREG array
 SYSREG_NAME_TO_VAL = {
     "fflags": RISCV_SYSREG_FFLAGS, "frm": RISCV_SYSREG_FRM, "fcsr": RISCV_SYSREG_FCSR,
     "vstart": RISCV_SYSREG_VSTART, "vxsat": RISCV_SYSREG_VXSAT, "vxrm": RISCV_SYSREG_VXRM,

cstool/cstool.c

@@ -64,9 +64,11 @@ static struct {
 	  { CS_ARCH_LOONGARCH, CS_ARCH_MIPS, CS_ARCH_MAX },
 	  CS_OPT_SYNTAX_NO_DOLLAR,
 	  0 },
-	{ "+noalias", "Does not print the text alias of an alias instruction", {
-		CS_ARCH_RISCV, CS_ARCH_MAX
-	}, CS_OPT_SYNTAX_NO_ALIAS_TEXT, 0},
+	{ "+noalias",
+	  "Does not print the text alias of an alias instruction",
+	  { CS_ARCH_RISCV, CS_ARCH_MAX },
+	  CS_OPT_SYNTAX_NO_ALIAS_TEXT,
+	  0 },
 	// cs_mode only
 	{ "+nofloat",
 	  "Disables floating point support",
@@ -150,12 +152,12 @@ static struct {
 	  CS_MODE_RISCV_FD },
 	{ "+v",
 	  "Enables RISCV V extension.",
-          { CS_ARCH_RISCV, CS_ARCH_MAX },
-          0,
-          CS_MODE_RISCV_V },
+	  { CS_ARCH_RISCV, CS_ARCH_MAX },
+	  0,
+	  CS_MODE_RISCV_V },
 	{ "+inx",
 	  "Enables RISCV Zfinx, Zdinx, and Zhinx extensions,"
-	  	" zhinxmin is also enabled as it's subset of zhinx ",
+	  " zhinxmin is also enabled as it's subset of zhinx ",
 	  { CS_ARCH_RISCV, CS_ARCH_MAX },
 	  0,
 	  CS_MODE_RISCV_ZFINX },
@@ -166,7 +168,7 @@ static struct {
 	  CS_MODE_RISCV_ZCMP_ZCMT_ZCE },
 	{ "a",
 	  "Enables the RISCV A extension",
-	  { CS_ARCH_RISCV, CS_ARCH_MAX},
+	  { CS_ARCH_RISCV, CS_ARCH_MAX },
 	  0,
 	  CS_MODE_RISCV_A },
 	{ NULL }
@@ -990,7 +992,8 @@ int main(int argc, char **argv)
 
 	count = cs_disasm(handle, assembly, size, address, 0, &insn);
 	printf("\nINSN TEXT: %s, %s", insn->mnemonic, insn->op_str);
-	printf("\n ------------------------------ COUNT OF CS INSN OPS : %d \n", insn->detail->riscv.op_count);
+	printf("\n ------------------------------ COUNT OF CS INSN OPS : %d \n",
+	       insn->detail->riscv.op_count);
 	if (count > 0) {
 		for (i = 0; i < count; i++) {
 			int j;

include/capstone/capstone.h

@@ -204,13 +204,13 @@ typedef enum cs_mode {
 	CS_MODE_M680X_CPU12 = 1 << 9, ///< M680X Motorola/Freescale/NXP CPU12
 	///< used on M68HC12/HCS12
 	CS_MODE_M680X_HCS08 = 1 << 10, ///< M680X Freescale/NXP HCS08 mode
-	CS_MODE_BPF_CLASSIC = 0,	///< Classic BPF mode (default)
-	CS_MODE_BPF_EXTENDED = 1 << 0,	///< Extended BPF mode
-	CS_MODE_RISCV32  = 1 << 0,        ///< RISCV RV32G
-	CS_MODE_RISCV64  = 1 << 1,        ///< RISCV RV64G
-	CS_MODE_RISCV_C   = 1 << 2,        ///< RISCV compressed instructure mode
-	CS_MODE_RISCV_FD  = 1 << 3,
-	CS_MODE_RISCV_V   = 1 << 4,
+	CS_MODE_BPF_CLASSIC = 0, ///< Classic BPF mode (default)
+	CS_MODE_BPF_EXTENDED = 1 << 0, ///< Extended BPF mode
+	CS_MODE_RISCV32 = 1 << 0, ///< RISCV RV32G
+	CS_MODE_RISCV64 = 1 << 1, ///< RISCV RV64G
+	CS_MODE_RISCV_C = 1 << 2, ///< RISCV compressed instructure mode
+	CS_MODE_RISCV_FD = 1 << 3,
+	CS_MODE_RISCV_V = 1 << 4,
 	CS_MODE_RISCV_ZFINX = 1 << 5,
 	CS_MODE_RISCV_ZCMP_ZCMT_ZCE = 1 << 6,
 	CS_MODE_RISCV_ZICFISS = 1 << 7,
@@ -220,13 +220,13 @@ typedef enum cs_mode {
 	CS_MODE_RISCV_THEAD = 1 << 11,
 	CS_MODE_RISCV_SIFIVE = 1 << 12,
 	CS_MODE_RISCV_BITMANIP = 1 << 13,
-	CS_MODE_RISCV_ZBA  = 1 << 14,
-	CS_MODE_RISCV_ZBB  = 1 << 15,
-	CS_MODE_RISCV_ZBC  = 1 << 16,
+	CS_MODE_RISCV_ZBA = 1 << 14,
+	CS_MODE_RISCV_ZBB = 1 << 15,
+	CS_MODE_RISCV_ZBC = 1 << 16,
 	CS_MODE_RISCV_ZBKB = 1 << 17,
 	CS_MODE_RISCV_ZBKC = 1 << 18,
 	CS_MODE_RISCV_ZBKX = 1 << 19,
-	CS_MODE_RISCV_ZBS  = 1 << 20,
+	CS_MODE_RISCV_ZBS = 1 << 20,
 	CS_MODE_MOS65XX_6502 = 1 << 1, ///< MOS65XXX MOS 6502
 	CS_MODE_MOS65XX_65C02 = 1 << 2, ///< MOS65XXX WDC 65c02
 	CS_MODE_MOS65XX_W65C02 = 1 << 3, ///< MOS65XXX WDC W65c02

tests/details/riscv.yaml

@@ -1665,7 +1665,7 @@ test_cases:
                 - type: RISCV_OP_REG
                   reg: t0
                   access: CS_AC_READ
-            groups: [RISCV_GRP_JUMP, RISCV_FEATURE_HasStdExtCOrZca]
+            groups: [RISCV_FEATURE_HasStdExtCOrZca, RISCV_GRP_JUMP]
         - asm_text: "c.jal 4140"
           details:
             riscv:
@@ -1736,7 +1736,7 @@ test_cases:
                 - type: RISCV_OP_IMM
                   imm: 0x8
                   access: CS_AC_READ
-            groups: [RISCV_GRP_CALL, RISCV_GRP_BRANCH_RELATIVE]
+            groups: [RISCV_GRP_BRANCH_RELATIVE]
   - input:
       bytes: [0xef, 0xf0, 0x1f, 0xff]
       arch: "CS_ARCH_RISCV"
@@ -1751,7 +1751,7 @@ test_cases:
                 - type: RISCV_OP_IMM
                   imm: -0x10
                   access: CS_AC_READ
-            groups: [RISCV_GRP_CALL, RISCV_GRP_BRANCH_RELATIVE]
+            groups: [RISCV_GRP_BRANCH_RELATIVE]
   - input:
       bytes: [0xe7, 0x00, 0x45, 0x00]
       arch: "CS_ARCH_RISCV"
@@ -3653,7 +3653,7 @@ test_cases:
                 - type: RISCV_OP_REG
                   reg: t0
                   access: CS_AC_READ
-            groups: [RISCV_GRP_JUMP, RISCV_FEATURE_HasStdExtCOrZca]
+            groups: [RISCV_FEATURE_HasStdExtCOrZca, RISCV_GRP_JUMP]
   - input:
       bytes: [0x11, 0x20]
       arch: "CS_ARCH_RISCV"

tests/issues/issues.yaml

@@ -120,7 +120,7 @@ test_cases:
               -
                 type: RISCV_OP_IMM
                 imm: 0x4
-          groups: [ call, branch_relative ]
+          groups: [ branch_relative ]
   -
     input:
       name: "issue 2007 RISCV32 instruction groups"
@@ -172,7 +172,7 @@ test_cases:
               -
                 type: RISCV_OP_IMM
                 imm: 0x4
-          groups: [ call, branch_relative ]
+          groups: [ branch_relative ]
   -
     input:
       name: "issue 2007 RISCV32 instruction groups"