Refactoring the RISCV architecture to Auto-Sync on LLVM (#2756)

- Updated to LLVM-18
- Operands have now read/write access information
- Previously only the basic extensions and the compressed ISA was supported, now every extension supported by LLVM-18 also available (e.g. vector, crypto, ...)
- Changed register names
  * FP Regs: Instead of `RISCV_REG_F<n>_32` and `RISCV_REG_F<n>_64`, they're named `RISCV_REG_F<n>_F`
  and `RISCV_REG_F<n>_D` for n in `0..31`
- Added register names
  * Vector registes and combinations thereof `RISCV_REG_V<n>[_V<n_i>]*`, examples
    * `RISCV_REG_V21`
    * `RISCV_REG_V9_V10`
    * `RISCV_REG_V3_V4_V5`
    * etc... up to 8-register combinations
  * Half-percision (16-bit) FP registers `RISCV_REG_F<n>_H` for n in `0..31`
- Changed instruction names
  * Instructions ending in `_AQ_RL` now end in `_AQRL`
- Added instruction names: massive amount, see `include/capstone/riscv.h`
- Added `dimm` and `csr` fields inside the union data of `cs_riscv_op`, with corresponding `riscv_op_type`
  * `dimm` is used for instructions with FP immediates
  * `csr` is used for instructions with CSR systrem registes
- Added ISA flags to turn ISA extensions on and off

Author: moste00

CMakeLists.txt

@@ -599,25 +599,38 @@ endif()
 if(CAPSTONE_RISCV_SUPPORT)
     add_definitions(-DCAPSTONE_HAS_RISCV)
     set(SOURCES_RISCV
+        arch/RISCV/RISCVBaseInfo.c
         arch/RISCV/RISCVDisassembler.c
+        arch/RISCV/RISCVDisassemblerExtension.c
         arch/RISCV/RISCVInstPrinter.c
         arch/RISCV/RISCVMapping.c
         arch/RISCV/RISCVModule.c
     )
     set(HEADERS_RISCV
         arch/RISCV/RISCVBaseInfo.h
-        arch/RISCV/RISCVDisassembler.h
+        arch/RISCV/RISCVDisassemblerExtension.h
         arch/RISCV/RISCVInstPrinter.h
         arch/RISCV/RISCVMapping.h
         arch/RISCV/RISCVModule.h
+        arch/RISCV/RISCVLinkage.h
         arch/RISCV/RISCVGenAsmWriter.inc
+        arch/RISCV/RISCVGenCSAliasMnemMap.inc
+        arch/RISCV/RISCVGenCSFeatureName.inc
+        arch/RISCV/RISCVGenCSMappingInsn.inc
+        arch/RISCV/RISCVGenCSMappingInsnName.inc
+        arch/RISCV/RISCVGenCSMappingInsnOp.inc
+        arch/RISCV/RISCVGenCSOpGroup.inc
+        arch/RISCV/RISCVGenCSSystemOperandsEnum.inc
         arch/RISCV/RISCVGenDisassemblerTables.inc
-        arch/RISCV/RISCVGenInsnNameMaps.inc
         arch/RISCV/RISCVGenInstrInfo.inc
         arch/RISCV/RISCVGenRegisterInfo.inc
         arch/RISCV/RISCVGenSubtargetInfo.inc
-        arch/RISCV/RISCVMappingInsn.inc
-        arch/RISCV/RISCVMappingInsnOp.inc
+        arch/RISCV/RISCVGenSystemOperands.inc
+        arch/RISCV/RISCVGenCompressedInstructionsInfo.inc
+        arch/RISCV/RISCVGenCSAliasEnum.inc
+        arch/RISCV/RISCVGenCSFeatureEnum.inc
+        arch/RISCV/RISCVGenCSInsnEnum.inc
+        arch/RISCV/RISCVGenCSRegEnum.inc
     )
 endif()
 

MCInstPrinter.c

@@ -11,6 +11,7 @@ extern bool Mips_getFeatureBits(unsigned int mode, unsigned int feature);
 extern bool AArch64_getFeatureBits(unsigned int mode, unsigned int feature);
 extern bool TriCore_getFeatureBits(unsigned int mode, unsigned int feature);
 extern bool Sparc_getFeatureBits(unsigned int mode, unsigned int feature);
+extern bool RISCV_getFeatureBits(unsigned int mode, unsigned int feature);
 
 static bool testFeatureBits(const MCInst *MI, uint32_t Value)
 {
@@ -42,6 +43,10 @@ static bool testFeatureBits(const MCInst *MI, uint32_t Value)
 #ifdef CAPSTONE_HAS_SPARC
 	case CS_ARCH_SPARC:
 		return Sparc_getFeatureBits(MI->csh->mode, Value);
+#endif
+#ifdef CAPSTONE_HAS_RISCV
+	case CS_ARCH_RISCV:
+		return RISCV_getFeatureBits(MI->csh->mode, Value);
 #endif
 	}
 }

Mapping.c

@@ -359,6 +359,34 @@ DEFINE_get_detail_op(bpf, BPF, BPF);
 DEFINE_get_detail_op(arc, ARC, ARC);
 DEFINE_get_detail_op(sparc, Sparc, SPARC);
 
+/// Returns the operand at detail->arch.operands[index]
+/// Or NULL if detail is not set or the index would be out of bounds.
+#define DEFINE_get_detail_op_at(arch, ARCH, ARCH_UPPER) \
+	cs_##arch##_op *ARCH##_get_detail_op_at(MCInst *MI, int index) \
+	{ \
+		if (!MI->flat_insn->detail) \
+			return NULL; \
+		if (index < 0 || index >= NUM_##ARCH_UPPER##_OPS) { \
+			return NULL; \
+		} \
+		return &MI->flat_insn->detail->arch.operands[index]; \
+	}
+
+DEFINE_get_detail_op_at(arm, ARM, ARM);
+DEFINE_get_detail_op_at(ppc, PPC, PPC);
+DEFINE_get_detail_op_at(tricore, TriCore, TRICORE);
+DEFINE_get_detail_op_at(aarch64, AArch64, AARCH64);
+DEFINE_get_detail_op_at(alpha, Alpha, ALPHA);
+DEFINE_get_detail_op_at(hppa, HPPA, HPPA);
+DEFINE_get_detail_op_at(loongarch, LoongArch, LOONGARCH);
+DEFINE_get_detail_op_at(mips, Mips, MIPS);
+DEFINE_get_detail_op_at(riscv, RISCV, RISCV);
+DEFINE_get_detail_op_at(systemz, SystemZ, SYSTEMZ);
+DEFINE_get_detail_op_at(xtensa, Xtensa, XTENSA);
+DEFINE_get_detail_op_at(bpf, BPF, BPF);
+DEFINE_get_detail_op_at(arc, ARC, ARC);
+DEFINE_get_detail_op_at(sparc, Sparc, SPARC);
+
 /// Returns true if for this architecture the
 /// alias operands should be filled.
 /// TODO: Replace this with a proper option.

Mapping.h

@@ -21,9 +21,9 @@ typedef struct insn_map {
 	unsigned short mapid; // The Capstone instruction id
 #ifndef CAPSTONE_DIET
 	uint16_t regs_use[MAX_IMPL_R_REGS]; ///< list of implicit registers used by
-		///< this instruction
+	///< this instruction
 	uint16_t regs_mod[MAX_IMPL_W_REGS]; ///< list of implicit registers modified
-		///< by this instruction
+	///< by this instruction
 	unsigned char groups
 		[MAX_NUM_GROUPS]; ///< list of group this instruction belong to
 	bool branch; // branch instruction?
@@ -48,7 +48,7 @@ unsigned short insn_find(const insn_map *m, unsigned int max, unsigned int id,
 unsigned int find_cs_id(unsigned MC_Opcode, const insn_map *imap,
 			unsigned imap_size);
 
-#define MAX_NO_DATA_TYPES 16
+#define MAX_NO_DATA_TYPES 32
 
 ///< A LLVM<->CS Mapping entry of an MCOperand.
 typedef struct {
@@ -147,6 +147,24 @@ DECL_get_detail_op(bpf, BPF);
 DECL_get_detail_op(arc, ARC);
 DECL_get_detail_op(sparc, Sparc);
 
+#define DECL_get_detail_op_at(arch, ARCH) \
+	cs_##arch##_op *ARCH##_get_detail_op_at(MCInst *MI, int offset);
+
+DECL_get_detail_op_at(arm, ARM);
+DECL_get_detail_op_at(ppc, PPC);
+DECL_get_detail_op_at(tricore, TriCore);
+DECL_get_detail_op_at(aarch64, AArch64);
+DECL_get_detail_op_at(alpha, Alpha);
+DECL_get_detail_op_at(hppa, HPPA);
+DECL_get_detail_op_at(loongarch, LoongArch);
+DECL_get_detail_op_at(mips, Mips);
+DECL_get_detail_op_at(riscv, RISCV);
+DECL_get_detail_op_at(systemz, SystemZ);
+DECL_get_detail_op_at(xtensa, Xtensa);
+DECL_get_detail_op_at(bpf, BPF);
+DECL_get_detail_op_at(arc, ARC);
+DECL_get_detail_op_at(sparc, Sparc);
+
 /// Increments the detail->arch.op_count by one.
 #define DEFINE_inc_detail_op_count(arch, ARCH) \
 	static inline void ARCH##_inc_op_count(MCInst *MI) \

MathExtras.h

@@ -62,6 +62,17 @@ static inline bool isIntN(unsigned N, int64_t x)
 	       (-(INT64_C(1) << (N - 1)) <= x && x < (INT64_C(1) << (N - 1)));
 }
 
+/// isShiftedIntN - Checks if a signed integer is an N bit number shifted left by S.
+static inline bool isShiftedIntN(unsigned N, unsigned S, int64_t x)
+{
+	return isIntN(N + S, x) && (x % (UINT64_C(1) << S) == 0);
+}
+
+static inline bool isShiftedUIntN(unsigned N, unsigned S, uint64_t x)
+{
+	return isUIntN(N + S, x) && (x % (UINT64_C(1) << S) == 0);
+}
+
 /// isMask_32 - This function returns true if the argument is a sequence of ones
 /// starting at the least significant bit with the remainder zero (32 bit
 /// version).   Ex. isMask_32(0x0000FFFFU) == true.

SStream.c

@@ -510,6 +510,13 @@ void printFloat(SStream *ss, float val)
 	SStream_concat(ss, "%e", val);
 }
 
+void printfFloat(SStream *ss, const char *fmt, float val)
+{
+	assert(ss);
+	SSTREAM_RETURN_IF_CLOSED(ss);
+	SStream_concat(ss, fmt, val);
+}
+
 void printFloatBang(SStream *ss, float val)
 {
 	assert(ss);

SStream.h

@@ -94,6 +94,8 @@ void printInt32BangDec(SStream *O, int32_t val);
 
 void printFloat(SStream *O, float val);
 
+void printfFloat(SStream *ss, const char *fmt, float val);
+
 void printFloatBang(SStream *O, float val);
 
 void printExpr(SStream *O, uint64_t val);

arch/RISCV/RISCVBaseInfo.c

@@ -0,0 +1,139 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically translated source file from LLVM. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Only small edits allowed. */
+/* For multiple similar edits, please create a Patch for the translator. */
+
+/* Capstone's C++ file translator: */
+/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
+
+//===-- RISCVBaseInfo.cpp - Top level definitions for RISC-V MC -----------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains small standalone enum definitions for the RISC-V target
+// useful for the compiler back-end and the MC libraries.
+//
+//===----------------------------------------------------------------------===//
+
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+#include <capstone/platform.h>
+
+#include "RISCVBaseInfo.h"
+
+#define CONCAT(a, b) CONCAT_(a, b)
+#define CONCAT_(a, b) a##_##b
+
+typedef struct {
+	unsigned value;
+	bool isFractional;
+} VLMULDecodeResult;
+VLMULDecodeResult decodeVLMUL(RISCVII_VLMUL VLMUL)
+{
+	switch (VLMUL) {
+	default:
+		CS_ASSERT(0 && "Unexpected LMUL value!");
+	case RISCVII_LMUL_1:
+	case RISCVII_LMUL_2:
+	case RISCVII_LMUL_4:
+	case RISCVII_LMUL_8: {
+		VLMULDecodeResult result = { .value = 1 << (unsigned)(VLMUL),
+					     .isFractional = false };
+		return result;
+	}
+	case RISCVII_LMUL_F2:
+	case RISCVII_LMUL_F4:
+	case RISCVII_LMUL_F8: {
+		VLMULDecodeResult result = { .value = 1 << (8 -
+							    (unsigned)(VLMUL)),
+					     .isFractional = true };
+		return result;
+	}
+	}
+}
+
+void printVType(unsigned VType, SStream *OS)
+{
+	unsigned Sew = RISCVVType_getSEW(VType);
+	SStream_concat(OS, "%s", "e");
+	printUInt64(OS, Sew);
+
+	unsigned LMul;
+	bool Fractional;
+	VLMULDecodeResult result = decodeVLMUL(RISCVVType_getVLMUL(VType));
+	LMul = result.value;
+	Fractional = result.isFractional;
+
+	if (Fractional)
+		SStream_concat0(OS, ", mf");
+	else
+		SStream_concat0(OS, ", m");
+	printUInt64(OS, LMul);
+
+	if (RISCVVType_isTailAgnostic(VType))
+		SStream_concat0(OS, ", ta");
+	else
+		SStream_concat0(OS, ", tu");
+
+	if (RISCVVType_isMaskAgnostic(VType))
+		SStream_concat0(OS, ", ma");
+	else
+		SStream_concat0(OS, ", mu");
+}
+
+typedef struct {
+	uint8_t first;
+	uint8_t second;
+} LoadFP32ImmArrElement;
+
+// Lookup table for fli.s for entries 2-31.
+static const LoadFP32ImmArrElement LoadFP32ImmArr[] = {
+	{ 0x6f, 0x00 }, { 0x70, 0x00 }, { 0x77, 0x00 }, { 0x78, 0x00 },
+	{ 0x7b, 0x00 }, { 0x7c, 0x00 }, { 0x7d, 0x00 }, { 0x7d, 0x01 },
+	{ 0x7d, 0x02 }, { 0x7d, 0x03 }, { 0x7e, 0x00 }, { 0x7e, 0x01 },
+	{ 0x7e, 0x02 }, { 0x7e, 0x03 }, { 0x7f, 0x00 }, { 0x7f, 0x01 },
+	{ 0x7f, 0x02 }, { 0x7f, 0x03 }, { 0x80, 0x00 }, { 0x80, 0x01 },
+	{ 0x80, 0x02 }, { 0x81, 0x00 }, { 0x82, 0x00 }, { 0x83, 0x00 },
+	{ 0x86, 0x00 }, { 0x87, 0x00 }, { 0x8e, 0x00 }, { 0x8f, 0x00 },
+	{ 0xff, 0x00 }, { 0xff, 0x02 },
+};
+
+float getFPImm(unsigned Imm)
+{
+	CS_ASSERT(Imm != 1 && Imm != 30 && Imm != 31 &&
+		  "Unsupported immediate");
+	CS_ASSERT((Imm == 0 || (Imm >= 2 && Imm < 30)) &&
+		  "Unsupported immediate");
+	// Entry 0 is -1.0, the only negative value. Entry 16 is 1.0.
+	uint32_t Sign = 0;
+	if (Imm == 0) {
+		Sign = 0x01;
+		Imm = 16;
+	}
+
+	uint32_t Exp = LoadFP32ImmArr[Imm - 2].first;
+	uint32_t Mantissa = LoadFP32ImmArr[Imm - 2].second;
+
+	uint32_t I = Sign << 31 | Exp << 23 | Mantissa << 21;
+	float result;
+	memcpy(&result, &I, sizeof(float));
+	return result;
+}
+
+void RISCVZC_printSpimm(int64_t Spimm, SStream *OS)
+{
+	printInt32(OS, Spimm);
+}
+
+// namespace llvm