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repository-name	e20-4yp-neuromorphic-memory-optimization
title	Neuromorphic-memory-optimization

Project Title: Neuromorphic Memory Optimization for Edge AI Accelerators

Team

• E/20/024, Ariyarathna D.B.S., e20024@eng.pdn.ac.lk
• E/20/242, Malinga G.A.I, e20242@eng.pdn.ac.lk
• E/20/279, Panawennage L.S., e20279@eng.pdn.ac.lk

Supervisors

• Prof. Roshan G. Ragel, roshanr@eng.pdn.ac.lk
• Dr. Isuru Nawinne, isurunawinne@eng.pdn.ac.lk

Table of Content

1. Abstract
2. Related Works
3. Methodology
4. Repository Structure
5. Experiment Setup and Implementation
6. Results and Analysis
7. Conclusion
8. Publications
9. Links

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1. Abstract

Neuromorphic computing mimics the brain’s neural structure, enabling event-driven, spike-based communication that overcomes the traditional Von Neumann memory bottleneck. However, this architecture introduces its own memory challenge: synaptic memory typically occupies over 70% of total chip area and accounts for more than 80% of power consumption.

In the Cerebra-H accelerator of the SNAP-V SoC, weight memory alone consumes 95.97% (479.95 mW) of total system power. This work targets that bottleneck by optimizing memory across three dimensions: representation, organization, and access mechanisms.

Key hyperparameters investigated include synaptic weight bit-width, quantization strategies, and fixed-point (QM.N) format selection. Using a Bayesian optimization loop to navigate this design space, we identified a Q12.4 fixed-point configuration with Time-To-First-Spike (TTFS) encoding as the optimal operating point — achieving 82.4% inference accuracy at 0.248 W, a nearly 50% reduction in power relative to the SNAP-V baseline (96.69% accuracy at 0.5001 W).

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2. Related Works

• MorphIC [Frenkel et al.] – Binary-weight digital neuromorphic processor with stochastic online learning.
• TrueNorth [IBM] – Landmark 1 million neuron programmable neurosynaptic chip.
• CyNAPSE – Adaptive caching for power savings in event-driven accelerators.
• SpiDR & Compute-in-Memory designs – Demonstrated high efficiency through sparsity exploitation.
• Q-SpiNN & other quantization frameworks – Focused on low-precision SNN weights.
• SNAP-V SoC (our baseline) – RISC-V based neuromorphic platform with Cerebra-H accelerator.

This work builds upon these milestones by introducing a systematic, hardware-aware workflow combining quantization pipelines, fixed-point iteration arithmetic, and structural encoding scheme co-optimization.

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3. Methodology

This project follows a strict hardware–software co-design approach to optimize the synaptic memory subsystem across three primary pillars:

1. Representation Optimization

• Hardware-aware quantization converting floating-point weights down to lower bit-widths (8/16/32-bit).
• Deep design exploration of fixed-point QM.N formats (where $M$ represents integer bits and $N$ represents fractional bits) to successfully balance numeric clipping against underflow.

2. Organization & Access Mechanisms

• Modifications to Cerebra-H’s clustered architecture and internal weight memory layout.
• Parameterized RTL-level changes to support dynamically sized bit-widths and custom event-driven encoding schemes.
• Evaluation of alternative spike encodings: Rate Encoding vs. Time-To-First-Spike (TTFS).

3. Automated Design Space Exploration

A closed-loop Bayesian Optimization infrastructure with a Gaussian Process surrogate framework was designed to systematically navigate hardware trade-offs by integrating:

• High-level functional software simulation (TENNLab, snnTorch)
• Structural RTL generation (Verilog)
• Physical memory macro generation (OpenRAM 6T SRAM)
• Gate-level power analysis (Synopsys VCS + RTL Compiler + PrimePower)

Figure 1: Baseline SNAP-V SoC microarchitecture showing integration with the Cerebra-H neuromorphic accelerator core.

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4. Repository Structure

The codebase is organized into distinct logical layers separating hardware synthesis flows from high-level software compiler and verification toolchains:

├── src/
│   ├── hardware/                 # Verilog RTL Codebase
│   │   ├── weight_mem.v          # Parameterized Synaptic Memory Macro
│   │   ├── cluster_core.v        # Accelerator Core Logic
│   │   └── tb_neuromorphic.v     # Cycle-accurate Testbench Infrastructure
│   │
│   ├── software/                 # Compilation & Quantization Pipelines
│   │   ├── neuron_mapper.py      # Layer-to-Cluster Mapping Engine
│   │   ├── quantizer.py          # Floating-to-Fixed-Point Conversion Tool
│   │   └── trace_analyzer.py     # Simulation Trace Analytics & Plotting
│   
├── data/
│   ├── traces/                   # Logged read/write telemetry (.trc files)
│   └── weights/                  # Extracted model parameter matrices
│
├── images/                       # Project documentation figures and plots
│   ├── accuracy_vs_bitwidth.png
│   ├── mnist_power_tradeoff.png
│   ├── snapv_soc.png
│   └── weight_memory.png
│
├── docs/                         # Automated Jekyll portal assets
│   └── index.json                # Project portal metadata descriptor
└── README.md                     # Main repository report