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Update .gitignore to exclude additional documentation files
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‎.gitignore‎

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# Markdown docs (keep READMEs only)
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mdfiles/
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GITHUB_LAUNCH_CHECKLIST.md
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‎CONTRIBUTING.md‎

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# Contributing to Garuda
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Contributions are welcome. This document provides guidelines for contributing to the Garuda RISC-V ML accelerator project.
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## How to Contribute
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### Reporting Issues
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- Use GitHub Issues to report bugs or request features
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- Provide a clear description of the issue or feature request
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- For bugs, include steps to reproduce and expected vs actual behavior
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- For RTL issues, include testbench code that demonstrates the problem
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### Code Contributions
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#### Development Setup
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1. **Clone the repository:**
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```bash
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git clone https://github.com/certainly-param/garuda-accelerator.git
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cd garuda-accelerator
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git submodule update --init --recursive
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```
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2. **Install dependencies:**
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- **Icarus Verilog** (for basic simulations)
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- Ubuntu/Debian: `sudo apt-get install iverilog`
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- macOS: `brew install icarus-verilog`
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- **Verilator** (for advanced verification)
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- Ubuntu/Debian: `sudo apt-get install verilator`
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- **Yosys** (for synthesis)
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- Ubuntu/Debian: `sudo apt-get install yosys`
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3. **Verify setup:**
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```bash
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# Run a quick test
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iverilog -g2012 -o sim_test.vvp garuda/tb/tb_register_rename_table.sv garuda/rtl/register_rename_table.sv
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vvp sim_test.vvp
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```
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#### Coding Standards
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- **SystemVerilog**: Follow SystemVerilog 2012 standard
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- **Naming conventions**:
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- Module names: `snake_case` (e.g., `int8_mac_unit`)
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- Signals: `snake_case` with suffix indicating direction (`_i` for input, `_o` for output, `_q` for registered)
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- Constants: `UPPER_SNAKE_CASE`
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- **Code organization**: One module per file, file name matches module name
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- **Comments**: Document all modules, parameters, and non-obvious logic
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- **Icarus compatibility**: Code must compile with Icarus Verilog (avoid advanced SystemVerilog features not supported by Icarus)
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#### Testbench Requirements
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- All new RTL modules must include a testbench
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- Testbenches should be self-verifying (use `$display` or assertions)
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- Testbenches should run with Icarus Verilog: `iverilog -g2012`
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- Add new testbenches to `ci/run_iverilog_sims.sh` for CI integration
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#### Submission Process
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1. **Fork the repository** and create a feature branch:
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```bash
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git checkout -b feature/your-feature-name
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```
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2. **Make your changes:**
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- Write or modify RTL modules
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- Add testbenches for new functionality
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- Update documentation as needed
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3. **Test your changes:**
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```bash
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# Run all simulations
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bash ci/run_iverilog_sims.sh
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```
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4. **Commit with clear messages:**
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```bash
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git commit -m "Add feature: brief description"
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```
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5. **Push and create a Pull Request:**
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- Ensure CI passes (all testbenches run successfully)
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- Describe your changes in the PR description
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- Reference any related issues
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### Areas for Contribution
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#### RTL Improvements
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- Performance optimizations
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- Area/power reductions
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- New instruction implementations
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- Bug fixes
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#### Verification
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- Additional testbenches
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- Coverage improvements
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- Integration tests
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- Formal verification
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#### Documentation
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- Code comments and module documentation
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- Architecture diagrams
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- Tutorial examples
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- Use case documentation
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#### Software Tools
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- Compiler support for custom instructions
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- Benchmark suites
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- Performance analysis tools
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#### Synthesis & PPA
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- FPGA/ASIC synthesis scripts
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- Timing closure improvements
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- Area optimizations
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## Project Structure
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```
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garuda-accelerator/
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├── garuda/
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│ ├── rtl/ # RTL source files
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│ ├── tb/ # Testbenches
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│ ├── dv/ # Cocotb verification
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│ └── synth/ # Synthesis scripts
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├── ci/ # CI helper scripts
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└── .github/ # GitHub Actions workflows
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```
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## Code Review Process
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- All PRs require review before merging
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- Reviewers will check:
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- Code quality and adherence to standards
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- Test coverage (testbenches must pass)
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- Documentation completeness
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- CI status (must pass)
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## Questions?
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- Open a GitHub Issue for questions about contributing
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- Check existing issues before creating a new one
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- Be respectful and constructive in discussions
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Thank you for contributing to Garuda!

‎LICENSE‎

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