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cursoragent
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Add double_wide openframe project type support.
Detect double_wide_openframe_project_wrapper GDS, use the double-wide XOR erase box, and extend LVS/OEB/CVC defaults for 59-GPIO padframes. Co-authored-by: Cursor <cursoragent@cursor.com>
1 parent 5360030 commit 92ecdea

17 files changed

Lines changed: 241 additions & 12 deletions

‎README.md‎

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@@ -60,6 +60,36 @@ cf-precheck -i ./my_project -p $PDK_ROOT/sky130A -c ./caravel --magic-drc
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cf-precheck -i ./my_project -p $PDK_ROOT/sky130A -c ./caravel --skip-checks lvs oeb
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```
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## Double-wide openframe
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Double-wide projects are detected when exactly one of these GDS files is present:
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`gds/double_wide_openframe_project_wrapper.gds`
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| Field | Value |
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|-------|--------|
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| Type | `double_wide` |
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| User module | `double_wide_openframe_project_wrapper` |
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| Top module | `double_wide_chip_io` |
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| Golden wrapper | `double_wide_openframe_project_wrapper_empty` |
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| User area | 6754.63 × 4766.63 µm (59 GPIOs) |
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Pass the double-wide **harness** root (not stock Caravel) as `-c`. That root must
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provide:
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- `gds/double_wide_openframe_project_wrapper_empty.gds`
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- `verilog/rtl/__double_wide_openframe_project_wrapper.v` (port-list golden)
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```bash
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cf-precheck \
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-i ../dw_openframe_user_project \
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-p $PDK_ROOT/sky130A \
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-c ../dw_openframe
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```
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XOR uses `erase_box_double_wide.tcl` (scaled openframe perimeter erase). OEB uses
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the openframe CVC path with GPIO indices `0..58`.
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## Checks
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| Check | Description |

‎src/cf_precheck/be_checks/run_openframe_check‎

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@@ -129,8 +129,14 @@ ERROR: Could not create $WORK_ROOT/cvcrc.oeb"
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fi
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if [[ "$DESIGN_NAME" == *openframe_project_wrapper ]]; then
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# Standard openframe: 44 GPIOs (0..43). Double-wide: 59 GPIOs (0..58).
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if [[ "$DESIGN_NAME" == *double_wide* ]]; then
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gpio_max=58
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else
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gpio_max=43
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fi
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echo "c 6" >$WORK_ROOT/cvc.oeb.script
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for ((i = 0; i <= 43; i++)); do
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for ((i = 0; i <= gpio_max; i++)); do
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cat >>$WORK_ROOT/cvc.oeb.script <<-cvcin
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gn analog_io[$i]
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gn analog_noesd_io[$i]

‎src/cf_precheck/be_checks/tech/sky130A/cvc.power.double_wide_openframe_project_wrapper‎

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por_l input min@0.0 max@1.8
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porb_h input min@0.0 max@3.3
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porb_l input min@0.0 max@1.8
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resetb_h input min@0.0 max@3.3
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resetb_l input min@0.0 max@1.8
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vccd1 power 1.8
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vdda1 power 3.3
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vssa1 power 0.0
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vssio power 0.0
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vccd2 power 1.8
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vddio power 3.3
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vssa2 power 0.0
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vdda2 power 3.3
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vdda power 3.3
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vssd1 power 0.0
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vssd2 power vssd1
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vccd power 1.8
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vssa power 0.0
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vssd power 0.0
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analog_io
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analog_noesd_io
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gpio_analog_en[*] expectMin@0.0 expectMax@1.8
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gpio_analog_pol[*] expectMin@0.0 expectMax@1.8
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gpio_analog_sel[*] expectMin@0.0 expectMax@1.8
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gpio_dm0[*] expectMin@0.0 expectMax@1.8
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gpio_dm1[*] expectMin@0.0 expectMax@1.8
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gpio_dm2[*] expectMin@0.0 expectMax@1.8
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gpio_holdover[*] expectMin@0.0 expectMax@1.8
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gpio_ib_mode_sel[*] expectMin@0.0 expectMax@1.8
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gpio_in[*] input min@0.0 max@1.8
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gpio_in_h[*] input min@0.0 max@3.3
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gpio_inp_dis[*] expectMin@0.0 expectMax@1.8
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gpio_loopback_one[*] input 1.8
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gpio_loopback_zero[*] input 0.0
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gpio_oeb[*] expectMin@0.0 expectMax@1.8
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gpio_out[*] expectMin@0.0 expectMax@1.8
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gpio_slow_sel[*] expectMin@0.0 expectMax@1.8
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gpio_vtrip_sel[*] expectMin@0.0 expectMax@1.8
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mask_rev[*] input min@0.0 max@1.8

‎src/cf_precheck/be_checks/tech/sky130A/lvs_config.double_wide_openframe_project_wrapper.json‎

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{
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"STD_CELL_LIBRARY": "sky130_fd_sc_hd",
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"INCLUDE_CONFIGS": [
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"$LVS_ROOT/tech/$PDK/lvs_config.base.json"
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],
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"TOP_SOURCE": "double_wide_openframe_project_wrapper",
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"TOP_LAYOUT": "$TOP_SOURCE",
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"EXTRACT_FLATGLOB": [
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""
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],
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"EXTRACT_ABSTRACT": [
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""
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],
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"EXTRACT_CREATE_SUBCUT": [
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""
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],
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"LVS_FLATTEN": [
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""
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],
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"LVS_NOFLATTEN": [
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""
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],
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"LVS_IGNORE": [
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""
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],
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"LVS_SPICE_FILES": [
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""
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],
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"LVS_VERILOG_FILES": [
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"$UPRJ_ROOT/verilog/gl/double_wide_openframe_project_wrapper.v"
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],
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"LAYOUT_FILE": "$UPRJ_ROOT/gds/double_wide_openframe_project_wrapper.gds"
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}

‎src/cf_precheck/be_checks/tech/sky130B/cvc.power.double_wide_openframe_project_wrapper‎

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por_l input min@0.0 max@1.8
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porb_h input min@0.0 max@3.3
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porb_l input min@0.0 max@1.8
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resetb_h input min@0.0 max@3.3
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resetb_l input min@0.0 max@1.8
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vccd1 power 1.8
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vdda1 power 3.3
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vssa1 power 0.0
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vssio power 0.0
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vccd2 power 1.8
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vddio power 3.3
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vssa2 power 0.0
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vdda2 power 3.3
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vdda power 3.3
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vssd1 power 0.0
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vssd2 power vssd1
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vccd power 1.8
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vssa power 0.0
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vssd power 0.0
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analog_io
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analog_noesd_io
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gpio_analog_en[*] expectMin@0.0 expectMax@1.8
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gpio_analog_pol[*] expectMin@0.0 expectMax@1.8
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gpio_analog_sel[*] expectMin@0.0 expectMax@1.8
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gpio_dm0[*] expectMin@0.0 expectMax@1.8
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gpio_dm1[*] expectMin@0.0 expectMax@1.8
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gpio_dm2[*] expectMin@0.0 expectMax@1.8
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gpio_holdover[*] expectMin@0.0 expectMax@1.8
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gpio_ib_mode_sel[*] expectMin@0.0 expectMax@1.8
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gpio_in[*] input min@0.0 max@1.8
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gpio_in_h[*] input min@0.0 max@3.3
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gpio_inp_dis[*] expectMin@0.0 expectMax@1.8
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gpio_loopback_one[*] input 1.8
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gpio_loopback_zero[*] input 0.0
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gpio_oeb[*] expectMin@0.0 expectMax@1.8
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gpio_out[*] expectMin@0.0 expectMax@1.8
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gpio_slow_sel[*] expectMin@0.0 expectMax@1.8
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gpio_vtrip_sel[*] expectMin@0.0 expectMax@1.8
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mask_rev[*] input min@0.0 max@1.8

‎src/cf_precheck/be_checks/tech/sky130B/lvs_config.double_wide_openframe_project_wrapper.json‎

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{
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"STD_CELL_LIBRARY": "sky130_fd_sc_hd",
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"INCLUDE_CONFIGS": [
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"$LVS_ROOT/tech/$PDK/lvs_config.base.json"
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],
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"TOP_SOURCE": "double_wide_openframe_project_wrapper",
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"TOP_LAYOUT": "$TOP_SOURCE",
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"EXTRACT_FLATGLOB": [
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""
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],
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"EXTRACT_ABSTRACT": [
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""
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],
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"EXTRACT_CREATE_SUBCUT": [
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""
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],
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"LVS_FLATTEN": [
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""
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],
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"LVS_NOFLATTEN": [
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""
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],
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"LVS_IGNORE": [
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""
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],
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"LVS_SPICE_FILES": [
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""
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],
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"LVS_VERILOG_FILES": [
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"$UPRJ_ROOT/verilog/gl/double_wide_openframe_project_wrapper.v"
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],
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"LAYOUT_FILE": "$UPRJ_ROOT/gds/double_wide_openframe_project_wrapper.gds"
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}

‎src/cf_precheck/check_manager.py‎

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@@ -30,7 +30,7 @@ class CheckManager:
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__ref__: str | None = None
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__surname__: str | None = None
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__supported_pdks__: list[str] | None = None
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__supported_type__: list[str] = ["analog", "digital", "openframe", "mini"]
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__supported_type__: list[str] = ["analog", "digital", "openframe", "mini", "double_wide"]
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__optional__: bool = False
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def __init__(self, precheck_config: dict, project_config: dict):

‎src/cf_precheck/checks/illegal_cellname.py‎

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@@ -29,7 +29,7 @@ class IllegalCellnameCheck:
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__ref__ = "illegal_cellname_check"
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__surname__ = "Illegal Cellname"
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__supported_pdks__ = ["sky130A", "sky130B"]
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__supported_type__ = ["analog", "digital", "openframe", "mini"]
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__supported_type__ = ["analog", "digital", "openframe", "mini", "double_wide"]
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__optional__ = False
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def __init__(self, precheck_config: dict, project_config: dict):

‎src/cf_precheck/checks/klayout_drc.py‎

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@@ -66,7 +66,7 @@ class _KlayoutDRCBase:
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__ref__: str | None = None
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__surname__: str | None = None
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__supported_pdks__: list[str] | None = None
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__supported_type__ = ["analog", "digital", "openframe", "mini"]
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__supported_type__ = ["analog", "digital", "openframe", "mini", "double_wide"]
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__optional__ = False
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def __init__(self, precheck_config: dict, project_config: dict):

‎src/cf_precheck/checks/lvs.py‎

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@@ -18,7 +18,7 @@ class Lvs:
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__ref__ = "lvs"
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__surname__ = "LVS"
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__supported_pdks__ = ["gf180mcuC", "gf180mcuD", "sky130A", "sky130B"]
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__supported_type__ = ["analog", "digital", "openframe", "mini"]
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__supported_type__ = ["analog", "digital", "openframe", "mini", "double_wide"]
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__optional__ = False
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def __init__(self, precheck_config: dict, project_config: dict):
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type_to_design = {
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"analog": "user_analog_project_wrapper",
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"openframe": "openframe_project_wrapper",
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"double_wide": "double_wide_openframe_project_wrapper",
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"mini": "user_project_wrapper_mini4",
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}
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self.design_name = type_to_design.get(proj_type, "user_project_wrapper")

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