suffix always be "sv"

[balanx]

Type of issue: Bug Report

Please provide the steps to reproduce the problem:

object Test extends App {
  val firtoolOptions = Array(
    "--verilog",                //  <===  **NO effect**
    "--default-layer-specialization=enable",
    "--verification-flavor=immediate",
    "--strip-debug-info",
    "--strip-fir-debug-info",
    "--disable-all-randomization",
    "--lowering-options=" + List(
      "disallowLocalVariables",
      "disallowPackedArrays",
      "locationInfoStyle=wrapInAtSquareBracket"
    ).reduce(_ + "," + _)
  )

  val commonArgs = Array(
    "--target", "verilog",     //  <===  **NO effect**
    "--target-dir", "out/verilog",
    "--split-verilog"
  )

  circt.stage.ChiselStage.emitSystemVerilogFile(new MyTest(), args ++ commonArgs, firtoolOptions)
}

What is the current behavior?
generating verilog named "MyTest.sv"

What is the expected behavior?
generating verilog named "MyTest.v", i.e. file extension name should be "v" when target is verilog, and be "sv" when target is systemverilog.

Please tell us about your environment:

WSL-ubuntu 24, chisel:7.7.0 , mill-0.12.11

Other Information

What is the use case for changing the behavior?

[seldridge]

When you run in -split-verilog this will generate multiple files that all have a .sv suffix. There is no way to change this (from Chisel or firtool). firtool only has one option, -verilog, which means "SystemVerilog". Is there a reason why you specifically want the file extension changed?

Chisel always generates SystemVerilog. It has constructs which are not Verilog like assert. firtool doesn't have a notion of "compilation of SystemVerilog constructs to Verilog". Hence, this always uses .sv for the same reason.

Usually, the real request is that you are using some tool which cannot support specific constructs like automatic logic. There is a guide on different lowering options for firtool here: https://circt.llvm.org/docs/VerilogGeneration/ Is this your real issue?

Also, see prior discussion about this: #3677.