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Merge pull request #683 from ckormanyos/bl602_sifive_e24_riscv
Fix #681 via Bl602 sifive e24 riscv
2 parents dd34dc4 + 914b48e commit 0288a47

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Lines changed: 1693 additions & 59 deletions

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‎.github/workflows/real-time-cpp.yml‎

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@@ -236,19 +236,19 @@ jobs:
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strategy:
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fail-fast: false
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matrix:
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suite: [ riscvfe310, wch_ch32v307, xtensa_esp32_s3_riscv_cop ]
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suite: [ bl602_sifive_e24_riscv, riscvfe310, wch_ch32v307, xtensa_esp32_s3_riscv_cop ]
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steps:
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- uses: actions/checkout@v4
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with:
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fetch-depth: '0'
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- name: update-tools
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run: |
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wget --no-check-certificate https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack/releases/download/v14.2.0-3/xpack-riscv-none-elf-gcc-14.2.0-3-linux-x64.tar.gz
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tar -xzf xpack-riscv-none-elf-gcc-14.2.0-3-linux-x64.tar.gz -C ${{ runner.workspace }}
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wget --no-check-certificate https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack/releases/download/v15.2.0-1/xpack-riscv-none-elf-gcc-15.2.0-1-linux-x64.tar.gz
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tar -xzf xpack-riscv-none-elf-gcc-15.2.0-1-linux-x64.tar.gz -C ${{ runner.workspace }}
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working-directory: ./
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- name: target-riscv-${{ matrix.suite }}
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run: |
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PATH="${{ runner.workspace }}/xpack-riscv-none-elf-gcc-14.2.0-3/bin:$PATH"
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PATH="${{ runner.workspace }}/xpack-riscv-none-elf-gcc-15.2.0-1/bin:$PATH"
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./target/build/build.sh ${{ matrix.suite }} rebuild
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ls -la ./bin/ref_app.elf ./bin/ref_app.hex ./bin/ref_app.map ./bin/ref_app.s19
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working-directory: ./ref_app/

‎readme.md‎

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@@ -71,11 +71,12 @@ The reference application supports the following targets (in alpha-numeric order
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| Target name (as used in build command) | Target Description | *(breadboard) |
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| -------------------------------------- | ----------------------------------------------------------- | ------------- |
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| `am335x` | BeagleBone with Texas Instruments(R) AM335x ARM(R) A8 | |
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| `am6254_soc_` | PocketBeagle2 with multicore Texas Instruments(R) AM6254 | |
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| `am6254_soc` | PocketBeagle2 with multicore Texas Instruments(R) AM6254 | |
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| `atmega2560` | MICROCHIP(R) [former ATMEL(R)] AVR(R) ATmega2560 | |
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| `atmega4809` | MICROCHIP(R) [former ATMEL(R)] AVR(R) ATmegax4809 | X |
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| `avr` (as used in the book) | MICROCHIP(R) [former ATMEL(R)] AVR(R) ATmega328P | X |
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| `bcm2835_raspi_b` | RaspberryPi(R) Zero with ARM1176-JZFS(TM) | X |
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| `bl602_sifive_e24_riscv` | BL602 single-core RISC-V (SiFive E24) | X |
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| `Debug`/`Release` | PC on `Win*` via MSVC x64 compiler `Debug`/`Release` | |
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| `host` | PC/Workstation on `Win*`/`mingw64`/`*nix` via host compiler | |
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| `lpc11c24` | NXP(R) OM13093 LPC11C24 board ARM(R) Cortex(R)-M0+ | |
@@ -415,6 +416,13 @@ called `target avr` (as used in the book) runs
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on a classic ARDUINO(R) compatible board.
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The program toggles the yellow LED on `portb.5`.
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Target `bl602_sifive_e24_riscv` contains a fully manually-written bare-metal project
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for the BL602 single-core RISC-V (SiFive E24), making no use of any SDK.
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The boot code and bare-metal register interactions are based
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on the creative work in
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[`Chalandi/Baremetal_BL602_SiFive_E24_RISC-V`](https://github.com/Chalandi/Baremetal_BL602_SiFive_E24_RISC-V).
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This configuration toggles pin `IO3` and requires a self-fitted LED.
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The ARM(R) 1176-JZF-S configuration (called `target bcm2835_raspi_b`) runs on the
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RaspberryPi(R) Zero (PiZero) single core controller.
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This project creates a bare-metal program for the PiZero.

‎ref_app/ref_app.sln‎

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@@ -52,6 +52,7 @@ Global
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target atmega4809|x64 = target atmega4809|x64
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target avr|x64 = target avr|x64
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target bcm2835_raspi_b|x64 = target bcm2835_raspi_b|x64
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target bl602_sifive_e24_riscv|x64 = target bl602_sifive_e24_riscv|x64
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target lpc11c24|x64 = target lpc11c24|x64
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target nxp_imxrt1062|x64 = target nxp_imxrt1062|x64
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target riscvfe310|x64 = target riscvfe310|x64
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{C8B59726-9319-45C3-8F11-F9F388FB6A2C}.target atmega4809|x64.ActiveCfg = Release|x64
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{C8B59726-9319-45C3-8F11-F9F388FB6A2C}.target avr|x64.ActiveCfg = Release|x64
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{C8B59726-9319-45C3-8F11-F9F388FB6A2C}.target bcm2835_raspi_b|x64.ActiveCfg = Release|x64
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{C8B59726-9319-45C3-8F11-F9F388FB6A2C}.target bl602_sifive_e24_riscv|x64.ActiveCfg = Release|x64
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{C8B59726-9319-45C3-8F11-F9F388FB6A2C}.target lpc11c24|x64.ActiveCfg = Release|x64
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{C8B59726-9319-45C3-8F11-F9F388FB6A2C}.target nxp_imxrt1062|x64.ActiveCfg = Release|x64
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{C8B59726-9319-45C3-8F11-F9F388FB6A2C}.target riscvfe310|x64.ActiveCfg = Release|x64
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{30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target avr|x64.Build.0 = target avr|x64
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{30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target bcm2835_raspi_b|x64.ActiveCfg = target bcm2835_raspi_b|x64
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{30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target bcm2835_raspi_b|x64.Build.0 = target bcm2835_raspi_b|x64
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{30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target bl602_sifive_e24_riscv|x64.ActiveCfg = target bl602_sifive_e24_riscv|x64
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{30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target bl602_sifive_e24_riscv|x64.Build.0 = target bl602_sifive_e24_riscv|x64
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{30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target lpc11c24|x64.ActiveCfg = target lpc11c24|x64
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{30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target lpc11c24|x64.Build.0 = target lpc11c24|x64
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{30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target nxp_imxrt1062|x64.ActiveCfg = target nxp_imxrt1062|x64

‎ref_app/ref_app.vcxproj‎

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<ClCompile Include="src\mcal\bl602_sifive_e24_riscv\mcal_eep.cpp">
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<ClCompile Include="src\mcal\bl602_sifive_e24_riscv\mcal_gpt.cpp">
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<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Debug|x64'">true</ExcludedFromBuild>
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<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Release|x64'">true</ExcludedFromBuild>
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</ClCompile>
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<ClCompile Include="src\mcal\bl602_sifive_e24_riscv\mcal_irq.cpp">
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<ClCompile Include="src\mcal\bl602_sifive_e24_riscv\mcal_osc.cpp">
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<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Debug|x64'">true</ExcludedFromBuild>
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<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Release|x64'">true</ExcludedFromBuild>
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</ClCompile>
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<ClCompile Include="src\mcal\bl602_sifive_e24_riscv\mcal_port.cpp">
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<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Debug|x64'">true</ExcludedFromBuild>
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<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Release|x64'">true</ExcludedFromBuild>
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</ClCompile>
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<ClCompile Include="src\mcal\bl602_sifive_e24_riscv\mcal_pwm.cpp">
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<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Debug|x64'">true</ExcludedFromBuild>
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<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Release|x64'">true</ExcludedFromBuild>
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</ClCompile>
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<ClCompile Include="src\mcal\bl602_sifive_e24_riscv\mcal_spi.cpp">
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<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Debug|x64'">true</ExcludedFromBuild>
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<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Release|x64'">true</ExcludedFromBuild>
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</ClCompile>
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<ClCompile Include="src\mcal\bl602_sifive_e24_riscv\mcal_wdg.cpp">
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<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Debug|x64'">true</ExcludedFromBuild>
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<ClCompile Include="src\mcal\host\mcal_eep.cpp" />
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<ClCompile Include="src\mcal\host\mcal_gpt.cpp" />
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<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Release|x64'">true</ExcludedFromBuild>
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<ClInclude Include="src\mcal\bl602_sifive_e24_riscv\mcal_cpu.h">
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</ClInclude>
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<ClInclude Include="src\mcal\bl602_sifive_e24_riscv\mcal_eep.h">
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<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Debug|x64'">true</ExcludedFromBuild>
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<ClInclude Include="src\mcal\bl602_sifive_e24_riscv\mcal_gpt.h">
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<ClInclude Include="src\mcal\host\mcal_benchmark.h" />
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‎ref_app/ref_app.vcxproj.filters‎

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<Filter Include="src\mcal\am6254_soc">
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<UniqueIdentifier>{74714130-9ba7-45a5-a860-74f8cb6eae22}</UniqueIdentifier>
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</Filter>
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<Filter Include="src\mcal\bl602_sifive_e24_riscv">
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<UniqueIdentifier>{9575513c-b5da-473e-9095-bbd968c02f6b}</UniqueIdentifier>
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</Filter>
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</ItemGroup>
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<ItemGroup>
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<ClCompile Include="src\app\led\app_led.cpp">
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<Filter>src\mcal\am6254_soc</Filter>
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</ClCompile>
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<Filter>src\mcal\bl602_sifive_e24_riscv</Filter>
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</ClCompile>
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‎ref_app/src/mcal/am6254_soc/mcal_gpt.cpp‎

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auto mcal::gpt::secure::get_time_elapsed() -> mcal::gpt::value_type
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{
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// Get the system tick from the system counter register.
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const value_type consistent_microsecond_tick = static_cast<value_type>(ARM64_READ_SYSREG(CNTPCT_EL0));
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// Get the consistent system tick from the system counter register.
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const value_type
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consistent_microsecond_tick
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{
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static_cast<value_type>(ARM64_READ_SYSREG(CNTPCT_EL0))
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};
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// Convert the consistent tick to microseconds.
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return static_cast<value_type>(static_cast<value_type>(consistent_microsecond_tick + UINT64_C(100)) / UINT64_C(200));
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return
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static_cast<value_type>
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(
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static_cast<value_type>(consistent_microsecond_tick + UINT64_C(100)) / UINT64_C(200)
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);
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}
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2129
auto mcal::gpt::secure::get_time_elapsed_core1() -> mcal::gpt::value_type_core1

‎ref_app/src/mcal/bl602_sifive_e24_riscv/mcal_benchmark.h‎

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///////////////////////////////////////////////////////////////////////////////
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// Copyright Christopher Kormanyos 2014 - 2025.
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// Distributed under the Boost Software License,
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// Version 1.0. (See accompanying file LICENSE_1_0.txt
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// or copy at http://www.boost.org/LICENSE_1_0.txt)
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//
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#ifndef MCAL_BENCHMARK_2014_04_16_H
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#define MCAL_BENCHMARK_2014_04_16_H
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#include <mcal_port.h>
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#include <mcal_reg.h>
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#include <cstdint>
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namespace mcal
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{
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namespace benchmark
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{
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using benchmark_port_type = mcal::port::port_pin<unsigned { UINT8_C(4) }>;
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}
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}
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#endif // MCAL_BENCHMARK_2014_04_16_H

‎ref_app/src/mcal/bl602_sifive_e24_riscv/mcal_cpu.cpp‎

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///////////////////////////////////////////////////////////////////////////////
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// Copyright Christopher Kormanyos 2007 - 2025.
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// Distributed under the Boost Software License,
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// Version 1.0. (See accompanying file LICENSE_1_0.txt
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// or copy at http://www.boost.org/LICENSE_1_0.txt)
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//
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#include <mcal_cpu.h>
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auto mcal::cpu::init() -> void
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{
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}

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