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Merge pull request #623 from ckormanyos/esp32s3_riscv_cop
Fix #621 via Esp32s3 riscv cop
2 parents ae67311 + 91122fe commit 425e2fb

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‎.github/workflows/real-time-cpp.yml‎

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@@ -213,7 +213,7 @@ jobs:
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strategy:
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fail-fast: false
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matrix:
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suite: [ riscvfe310, wch_ch32v307 ]
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suite: [ riscvfe310, wch_ch32v307, xtensa_esp32_s3_riscv_cop ]
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steps:
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- uses: actions/checkout@v4
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with:

‎readme.md‎

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@@ -403,11 +403,13 @@ features a bare-metal startup _without_ using any of the SDK.
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The bare-metal startup was taken from the work of
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[Chalandi/Baremetal_esp32s3_nosdk](https://github.com/Chalandi/Baremetal_esp32s3_nosdk).
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The dual-core system first boots core0 which subsequently
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starts up core1. Blinky runs in the standard `ref_app`
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starts up core1 and also starts up the RISC-V coprocessor core.
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Blinky runs in the standard `ref_app`
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on core0 toggling `port7` while an endless timer loop on core1
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toggles `port6`. The LED ports togle in near unison at $\frac{1}{2}~\text{Hz}$.
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Self-procured LEDs and resistors need to be fitted in order to observe
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blinky on this particular board.
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blinky on this particular board. The RISC-V coprocessor
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toggles `port17` at a randomly selected frequency of $\sim\frac{2}{3}~\text{Hz}$.
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The NXP(R) OM13093 LPC11C24 board ARM(R) Cortex(R)-M0+ configuration
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called `target lpc11c24` toggles the LED on `port0.8`.

‎ref_app/ref_app.sln‎

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target wch_ch32v307_llvm|x64 = target wch_ch32v307_llvm|x64
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target wch_ch32v307|x64 = target wch_ch32v307|x64
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target x86_64-w64-mingw32|x64 = target x86_64-w64-mingw32|x64
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target xtensa_esp32_s3_riscv_cop|x64 = target xtensa_esp32_s3_riscv_cop|x64
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target xtensa_esp32_s3|x64 = target xtensa_esp32_s3|x64
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target xtensa32|x64 = target xtensa32|x64
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EndGlobalSection
@@ -102,6 +103,7 @@ Global
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{C8B59726-9319-45C3-8F11-F9F388FB6A2C}.target wch_ch32v307_llvm|x64.ActiveCfg = Release|x64
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{C8B59726-9319-45C3-8F11-F9F388FB6A2C}.target wch_ch32v307|x64.ActiveCfg = Release|x64
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{C8B59726-9319-45C3-8F11-F9F388FB6A2C}.target x86_64-w64-mingw32|x64.ActiveCfg = Release|x64
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{C8B59726-9319-45C3-8F11-F9F388FB6A2C}.target xtensa_esp32_s3_riscv_cop|x64.ActiveCfg = Release|x64
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{C8B59726-9319-45C3-8F11-F9F388FB6A2C}.target xtensa_esp32_s3|x64.ActiveCfg = Release|x64
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{C8B59726-9319-45C3-8F11-F9F388FB6A2C}.target xtensa32|x64.ActiveCfg = Release|x64
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{30CE370B-40F3-4BCD-8986-64AAFF8971BD}.Debug|x64.ActiveCfg = target avr|x64
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{30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target wch_ch32v307|x64.Build.0 = target wch_ch32v307|x64
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{30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target x86_64-w64-mingw32|x64.ActiveCfg = target x86_64-w64-mingw32|x64
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{30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target x86_64-w64-mingw32|x64.Build.0 = target x86_64-w64-mingw32|x64
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{30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target xtensa_esp32_s3_riscv_cop|x64.ActiveCfg = target xtensa_esp32_s3_riscv_cop|x64
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{30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target xtensa_esp32_s3_riscv_cop|x64.Build.0 = target xtensa_esp32_s3_riscv_cop|x64
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{30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target xtensa_esp32_s3|x64.ActiveCfg = target xtensa_esp32_s3|x64
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{30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target xtensa_esp32_s3|x64.Build.0 = target xtensa_esp32_s3|x64
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{30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target xtensa32|x64.ActiveCfg = target xtensa32|x64

‎ref_app/ref_app.vcxproj‎

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‎ref_app/ref_app.vcxproj.filters‎

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