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ckormanyosckormanyos
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Add more files and prelim build in CI
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Lines changed: 529 additions & 10 deletions

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‎.github/workflows/real-time-cpp.yml‎

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@@ -213,7 +213,7 @@ jobs:
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strategy:
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fail-fast: false
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matrix:
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suite: [ riscvfe310, wch_ch32v307 ]
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suite: [ riscvfe310, wch_ch32v307, xtensa_esp32_s3_riscv_cop ]
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steps:
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- uses: actions/checkout@v4
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with:

‎ref_app/target.vcxproj‎

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@@ -1040,6 +1040,8 @@
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<None Include="target\micros\xtensa_esp32_s3_riscv_cop\make\xtensa_esp32_s3_riscv_cop.ld" />
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<None Include="target\micros\xtensa_esp32_s3_riscv_cop\make\xtensa_esp32_s3_riscv_cop_files.gmk" />
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<None Include="target\micros\xtensa_esp32_s3_riscv_cop\make\xtensa_esp32_s3_riscv_cop_flags.gmk" />
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<None Include="target\micros\xtensa_esp32_s3_riscv_cop\startup\from_no_sdk\Startup\boot.S" />
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<None Include="target\micros\xtensa_esp32_s3_riscv_cop\startup\from_no_sdk\Startup\IntVectTable.S" />
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</ItemGroup>
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<ItemGroup>
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<ClCompile Include="target\micros\am335x\startup\crt0.cpp" />
@@ -1144,12 +1146,14 @@
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<ClCompile Include="target\micros\xtensa_esp32_s3\startup\crt0_init_ram.cpp" />
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<ClCompile Include="target\micros\xtensa_esp32_s3\startup\crt1.cpp" />
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<ClCompile Include="target\micros\xtensa_esp32_s3\startup\Std\StdLib.cpp" />
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<ClCompile Include="target\micros\xtensa_esp32_s3_riscv_cop\startup\from_no_sdk\Startup\Startup.c" />
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</ItemGroup>
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<ItemGroup>
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<Text Include="target\micros\bcm2835_raspi_b\startup\SD_CARD\PiZero\config.txt" />
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</ItemGroup>
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<ItemGroup>
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<ClInclude Include="target\micros\xtensa_esp32_s3\startup\Std\core-isa.h" />
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<ClInclude Include="target\micros\xtensa_esp32_s3_riscv_cop\startup\from_no_sdk\Startup\custom_ops.h" />
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</ItemGroup>
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<ItemGroup>
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<Library Include="target\micros\xtensa_esp32_s3\startup\Std\lib_call0_abi\libc_call0_abi.a" />

‎ref_app/target.vcxproj.filters‎

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@@ -283,6 +283,18 @@
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<Filter Include="micros\xtensa_esp32_s3_riscv_cop">
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<UniqueIdentifier>{d85fd616-0c1e-4254-bcba-6cf308b63dff}</UniqueIdentifier>
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</Filter>
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<Filter Include="micros\xtensa_esp32_s3_riscv_cop\make">
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<UniqueIdentifier>{884fecba-24b2-4059-8063-3a7c56c0cadf}</UniqueIdentifier>
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</Filter>
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<Filter Include="micros\xtensa_esp32_s3_riscv_cop\startup">
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<UniqueIdentifier>{a71738e7-0c88-4bb9-a1bd-3a5ffd125490}</UniqueIdentifier>
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</Filter>
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<Filter Include="micros\xtensa_esp32_s3_riscv_cop\startup\from_no_sdk">
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<UniqueIdentifier>{bb1fed00-c4cd-4e52-833d-16cf0f69bc10}</UniqueIdentifier>
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</Filter>
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<Filter Include="micros\xtensa_esp32_s3_riscv_cop\startup\from_no_sdk\Startup">
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<UniqueIdentifier>{66ae9aa3-915d-4366-9492-87cdb30add93}</UniqueIdentifier>
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</Filter>
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</ItemGroup>
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<ItemGroup>
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<None Include="target\app\make\app_files.gmk">
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<None Include="target\micros\xtensa_esp32_s3\make\xtensa_esp32_s3_flags_extra.gmk">
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<Filter>micros\xtensa_esp32_s3\make</Filter>
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</None>
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<None Include="target\micros\xtensa_esp32_s3_riscv_cop\make\xtensa_esp32_s3_riscv_cop_flags.gmk">
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<Filter>micros\xtensa_esp32_s3_riscv_cop</Filter>
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</None>
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<None Include="target\micros\xtensa_esp32_s3_riscv_cop\make\xtensa_esp32_s3_riscv_cop.ld">
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<Filter>micros\xtensa_esp32_s3_riscv_cop</Filter>
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<Filter>micros\xtensa_esp32_s3_riscv_cop\make</Filter>
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</None>
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<None Include="target\micros\xtensa_esp32_s3_riscv_cop\make\xtensa_esp32_s3_riscv_cop_files.gmk">
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<Filter>micros\xtensa_esp32_s3_riscv_cop</Filter>
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<Filter>micros\xtensa_esp32_s3_riscv_cop\make</Filter>
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</None>
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<None Include="target\micros\xtensa_esp32_s3_riscv_cop\make\xtensa_esp32_s3_riscv_cop_flags.gmk">
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<Filter>micros\xtensa_esp32_s3_riscv_cop\make</Filter>
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</None>
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<None Include="target\micros\xtensa_esp32_s3_riscv_cop\startup\from_no_sdk\Startup\boot.S">
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<Filter>micros\xtensa_esp32_s3_riscv_cop\startup\from_no_sdk\Startup</Filter>
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</None>
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<None Include="target\micros\xtensa_esp32_s3_riscv_cop\startup\from_no_sdk\Startup\IntVectTable.S">
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<Filter>micros\xtensa_esp32_s3_riscv_cop\startup\from_no_sdk\Startup</Filter>
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</None>
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</ItemGroup>
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<ItemGroup>
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<ClCompile Include="target\micros\xtensa_esp32_s3\startup\Std\StdLib.cpp">
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<Filter>micros\xtensa_esp32_s3\startup\Std</Filter>
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</ClCompile>
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<ClCompile Include="target\micros\xtensa_esp32_s3_riscv_cop\startup\from_no_sdk\Startup\Startup.c">
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<Filter>micros\xtensa_esp32_s3_riscv_cop\startup\from_no_sdk\Startup</Filter>
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</ClCompile>
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</ItemGroup>
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<ItemGroup>
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<Text Include="target\micros\bcm2835_raspi_b\startup\SD_CARD\PiZero\config.txt">
@@ -981,6 +1002,9 @@
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<ClInclude Include="target\micros\xtensa_esp32_s3\startup\Std\core-isa.h">
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<Filter>micros\xtensa_esp32_s3\startup\Std</Filter>
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</ClInclude>
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<ClInclude Include="target\micros\xtensa_esp32_s3_riscv_cop\startup\from_no_sdk\Startup\custom_ops.h">
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<Filter>micros\xtensa_esp32_s3_riscv_cop\startup\from_no_sdk\Startup</Filter>
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</ClInclude>
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</ItemGroup>
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<ItemGroup>
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<Library Include="target\micros\xtensa_esp32_s3\startup\Std\lib_call0_abi\libc_call0_abi.a">

‎ref_app/target/micros/xtensa_esp32_s3/make/xtensa_esp32_s3_files.gmk‎

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@@ -1,12 +1,12 @@
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#
2-
# Copyright Christopher Kormanyos 2018 - 2025.
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# Copyright Christopher Kormanyos 2025.
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# Distributed under the Boost Software License,
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# Version 1.0. (See accompanying file LICENSE_1_0.txt
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# or copy at http://www.boost.org/LICENSE_1_0.txt)
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#
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# ------------------------------------------------------------------------------
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# File list of the xtensa32 esspressif ESP32 files in the project
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# File list of the ESP32-S3 files in the project
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# ------------------------------------------------------------------------------
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FILES_TGT := $(PATH_APP)/mcal/mcal_gcc_cxx_completion \

‎ref_app/target/micros/xtensa_esp32_s3_riscv_cop/make/xtensa_esp32_s3_riscv_cop_files.gmk‎

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#
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# ------------------------------------------------------------------------------
9-
# File list of the xtensa32 esspressif ESP32 files in the project
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# File list of the ESP32-S3 RISC-V coprocessor files in the project
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# ------------------------------------------------------------------------------
1111

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FILES_TGT := $(PATH_APP)/mcal/mcal_gcc_cxx_completion
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FILES_TGT := $(PATH_APP)/mcal/mcal_gcc_cxx_completion \
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$(PATH_TGT)/startup/from_no_sdk/Startup/boot \
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$(PATH_TGT)/startup/from_no_sdk/Startup/IntVectTable \
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$(PATH_TGT)/startup/from_no_sdk/Startup/Startup

‎ref_app/target/micros/xtensa_esp32_s3_riscv_cop/make/xtensa_esp32_s3_riscv_cop_flags.gmk‎

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@@ -42,3 +42,25 @@ TGT_LDFLAGS = -nostdlib \
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$(TGT_ALLFLAGS) \
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--specs=nano.specs \
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--specs=nosys.specs
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# ------------------------------------------------------------------------------
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# Rule to assemble source file (*.S) to object file (*.o).
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# ------------------------------------------------------------------------------
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ifeq ($(TYP_OS),WIN)
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TGT_GCC := $(PATH_TOOLS_CC)/$(GCC_PREFIX)-gcc.exe
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TGT_GCC := $(subst /,\,$(TGT_GCC))
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else
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TGT_GCC := $(GCC_PREFIX)-gcc
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endif
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$(PATH_OBJ)/%.o : %.S
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@$(ECHO) +++ assemble for esp32s3 riscv cop: $< to $@
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# Assemble the source file,
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# ...and reformat (using sed) any possible error/warning messages
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# for the VisualStudio(R) output window,
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# ...and create an assembly listing using objdump
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@-$(CC) $(TGT_ALLFLAGS) $(C_INCLUDES) $< -c -o $(PATH_OBJ)/$(basename $(@F)).o 2> $(PATH_ERR)/$(basename $(@F)).err
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@-$(SED) -e 's|:\([0-9]*\):|(\1) :|' $(PATH_ERR)/$(basename $(@F)).err
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@-$(OBJDUMP) -S $(PATH_OBJ)/$(basename $(@F)).o > $(PATH_LST)/$(basename $(@F)).lst

‎ref_app/target/micros/xtensa_esp32_s3_riscv_cop/startup/from_no_sdk/Startup/IntVectTable.S‎

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/******************************************************************************************
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Filename : IntVectTable.S
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Core : RISC-V
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MCU : ESP32-S3
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Author : Chalandi Amine
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Owner : Chalandi Amine
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Date : 22.02.2025
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Description : interrupt vector table implementation for ULP-RISC-V Co-processor
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******************************************************************************************/
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#include "custom_ops.h"
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/*******************************************************************************************
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\brief
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\param
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\return
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********************************************************************************************/
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.section .vector
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.type _InterruptVectorTable, @function
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.align 4
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.extern _IRQ_VECTORS
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.globl _InterruptVectorTable
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_InterruptVectorTable:
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/* reset vector */
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j _start
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/* irq vector */
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.org _InterruptVectorTable + 0x10
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j _IRQ_VECTORS
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.size _InterruptVectorTable, .-_InterruptVectorTable
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/*******************************************************************************************
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\brief
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\param
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\return
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********************************************************************************************/
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.section .text
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.type _IRQ_VECTORS, @function
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.align 4
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.extern irq_vector
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.globl _IRQ_VECTORS
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_IRQ_VECTORS:
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addi sp, sp, -(17*4)
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sw ra, 0(sp)
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sw tp, 4(sp)
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sw t0, 8(sp)
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sw t1, 12(sp)
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sw t2, 16(sp)
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sw a0, 20(sp)
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sw a1, 24(sp)
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sw a2, 28(sp)
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sw a3, 32(sp)
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sw a4, 36(sp)
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sw a5, 40(sp)
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sw a6, 44(sp)
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sw a7, 48(sp)
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sw t3, 52(sp)
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sw t4, 56(sp)
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sw t5, 60(sp)
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sw t6, 64(sp)
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picorv32_getq_insn(a0,q1)
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jal irq_vector
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lw ra, 0(sp)
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lw tp, 4(sp)
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lw t0, 8(sp)
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lw t1, 12(sp)
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lw t2, 16(sp)
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lw a0, 20(sp)
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lw a1, 24(sp)
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lw a2, 28(sp)
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lw a3, 32(sp)
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lw a4, 36(sp)
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lw a5, 40(sp)
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lw a6, 44(sp)
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lw a7, 48(sp)
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lw t3, 52(sp)
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lw t4, 56(sp)
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lw t5, 60(sp)
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lw t6, 64(sp)
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addi sp,sp, (17*4)
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picorv32_retirq_insn()
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.size _IRQ_VECTORS, .-_IRQ_VECTORS
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/*******************************************************************************************
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\brief
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\param
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\return
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********************************************************************************************/
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.section .text
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.type set_timer_counter, @function
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.align 4
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.globl set_timer_counter
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set_timer_counter:
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/* custom instruction to set the timer counter */
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picorv32_timer_insn(zero, a0)
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ret
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.size set_timer_counter, .-set_timer_counter

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