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BL602 startup and get benches running
1 parent 0288a47 commit 5e72eca

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Lines changed: 301 additions & 299 deletions

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‎ref_app/src/app/benchmark/readme.md‎

Lines changed: 14 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -81,16 +81,17 @@ template class.
8181
A very wide range of microcontroller performance classes is shown in the following table.
8282
The benchmark used is a ${\sim}100$ decimal digit AGM $\pi$ calculation.
8383

84-
| Target | runtime $[ms]$ | relative |
85-
|--------------------|-----------------|------------|
86-
| `am6254_soc` | 0.37 | 1.0 |
87-
| `am335x` | 1.5 | 4.1 |
88-
| `stm32f446` | 5.1 | 14 |
89-
| `rpi_pico2_rp2350` | 6.3 | 17 |
90-
| `wch_ch32v307` | 8.0 | 22 |
91-
| `xtensa_esp32_s3` | 9.1 | 25 |
92-
| `rpi_pico_rp2040` | 19 | 51 |
93-
| `avr` | 410 | 1100 |
84+
| Target | runtime $[ms]$ | relative |
85+
|---------------------------|-----------------|------------|
86+
| `am6254_soc` | 0.37 | 1.0 |
87+
| `am335x` | 1.5 | 4.1 |
88+
| `stm32f446` | 5.1 | 14 |
89+
| `rpi_pico2_rp2350` | 6.3 | 17 |
90+
| `wch_ch32v307` | 8.0 | 22 |
91+
| `xtensa_esp32_s3` | 9.1 | 25 |
92+
| `bl602_sifive_e24_riscv` | 11 | 30 |
93+
| `rpi_pico_rp2040` | 19 | 51 |
94+
| `avr` | 410 | 1100 |
9495

9596
There are strikingly differing performance classes
9697
for the $8$-bit MICROCHIP(R) AVR controller of the ARDUINO
@@ -113,7 +114,9 @@ with a result of $5.1~{\text{ms}}$.
113114

114115
The $32$-bit RISC-V controller (having a novel _open-source_ core)
115116
on the `wch_ch32v307` board boasts a quite respectable
116-
time of $8.0~{\text{ms}}$.
117+
time of $8.0~{\text{ms}}$. A different $32$-bit RISC-V controller
118+
on target `bl602_sifive_e24_riscv` has similar performance,
119+
running the benchmark in about $11~{\text{ms}}$.
117120

118121
Running on only one core (core0) of the $32$-bit
119122
controller of the `xtensa_esp32_s3` board results in

‎ref_app/src/mcal/bl602_sifive_e24_riscv/mcal_port.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -73,12 +73,12 @@
7373

7474
static auto set_pin_high() noexcept -> void
7575
{
76-
// Not yet implemented.
76+
mcal::reg::reg_access_static<std::uintptr_t, std::uint32_t, mcal::reg::gpio_cfgctl32, port_index>::bit_set();
7777
}
7878

7979
static auto set_pin_low() noexcept -> void
8080
{
81-
// Not yet implemented.
81+
mcal::reg::reg_access_static<std::uintptr_t, std::uint32_t, mcal::reg::gpio_cfgctl32, port_index>::bit_clr();
8282
}
8383

8484
static auto read_input_value() noexcept -> bool

‎ref_app/target.vcxproj‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1132,8 +1132,10 @@
11321132
<ClCompile Include="target\micros\bcm2835_raspi_b\startup\crt0_init_ram.cpp" />
11331133
<ClCompile Include="target\micros\bcm2835_raspi_b\startup\crt1.cpp" />
11341134
<ClCompile Include="Target\Micros\AVR\Startup\int_vect.cpp" />
1135+
<ClCompile Include="target\micros\bl602_sifive_e24_riscv\startup\crt0.cpp" />
1136+
<ClCompile Include="target\micros\bl602_sifive_e24_riscv\startup\crt0_init_ram.cpp" />
1137+
<ClCompile Include="target\micros\bl602_sifive_e24_riscv\startup\crt1.cpp" />
11351138
<ClCompile Include="target\micros\bl602_sifive_e24_riscv\startup\intvect.c" />
1136-
<ClCompile Include="target\micros\bl602_sifive_e24_riscv\startup\Startup.c" />
11371139
<ClCompile Include="target\micros\lpc11c24\startup\crt0.cpp" />
11381140
<ClCompile Include="target\micros\lpc11c24\startup\crt0_init_ram.cpp" />
11391141
<ClCompile Include="target\micros\lpc11c24\startup\crt1.cpp" />

‎ref_app/target.vcxproj.filters‎

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1094,7 +1094,13 @@
10941094
<ClCompile Include="target\micros\bl602_sifive_e24_riscv\startup\intvect.c">
10951095
<Filter>micros\bl602_sifive_e24_riscv\startup</Filter>
10961096
</ClCompile>
1097-
<ClCompile Include="target\micros\bl602_sifive_e24_riscv\startup\Startup.c">
1097+
<ClCompile Include="target\micros\bl602_sifive_e24_riscv\startup\crt1.cpp">
1098+
<Filter>micros\bl602_sifive_e24_riscv\startup</Filter>
1099+
</ClCompile>
1100+
<ClCompile Include="target\micros\bl602_sifive_e24_riscv\startup\crt0.cpp">
1101+
<Filter>micros\bl602_sifive_e24_riscv\startup</Filter>
1102+
</ClCompile>
1103+
<ClCompile Include="target\micros\bl602_sifive_e24_riscv\startup\crt0_init_ram.cpp">
10981104
<Filter>micros\bl602_sifive_e24_riscv\startup</Filter>
10991105
</ClCompile>
11001106
</ItemGroup>

‎ref_app/target/micros/bl602_sifive_e24_riscv/make/bl602_sifive_e24_riscv.ld‎

Lines changed: 109 additions & 80 deletions
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,8 @@
1515
1616
******************************************************************************************/
1717

18+
INPUT(libc.a libm.a libgcc.a)
19+
1820
/******************************************************************************************
1921
ELF Entrypoint
2022
******************************************************************************************/
@@ -23,137 +25,164 @@ ENTRY(_start)
2325
/******************************************************************************************
2426
Globals
2527
******************************************************************************************/
26-
__FLASH_START_ADDRESS = 0x23000000;
27-
__FLASH_SIZE = 2M;
2828

29-
__ITCM_START_ADDRESS = 0x22008000;
30-
__ITCM_SIZE = 48K;
29+
__STACK_SIZE = 4K;
3130

32-
__DTCM_START_ADDRESS = 0x42014000;
33-
__DTCM_SIZE = 48K;
31+
__RAM_START_ADDRESS = 0x42020000;
32+
__RAM_SIZE = 64K - __STACK_SIZE;
3433

35-
__STACK_START_ADDRESS = 0x42020000;
36-
__STACK_SIZE = 1K;
34+
__STACK_START_ADDRESS = __RAM_START_ADDRESS + __RAM_SIZE;
3735

38-
__RAM_START_ADDRESS = 0x42020000 + __STACK_SIZE;
39-
__RAM_SIZE = 64K - __STACK_SIZE;
36+
__ROM_START_ADDRESS = 0x23000000;
4037

4138
/******************************************************************************************
4239
Memory configuration
4340
******************************************************************************************/
4441

4542
MEMORY
4643
{
47-
FLASH(rx) : ORIGIN = __FLASH_START_ADDRESS, LENGTH = __FLASH_SIZE
48-
ITCM(rx) : ORIGIN = __ITCM_START_ADDRESS, LENGTH = __ITCM_SIZE
49-
DTCM(rx) : ORIGIN = __DTCM_START_ADDRESS, LENGTH = __DTCM_SIZE
50-
STACK(rw) : ORIGIN = __STACK_START_ADDRESS, LENGTH = __STACK_SIZE
51-
RAM(rwx) : ORIGIN = __RAM_START_ADDRESS, LENGTH = __RAM_SIZE
44+
BOOT(rx) : ORIGIN = 0x23000000, LENGTH = 0x100
45+
START(rx) : ORIGIN = 0x23000100, LENGTH = 0x300
46+
ROM(rx) : ORIGIN = 0x23000400, LENGTH = 256K - 0x400
47+
SRAM(rwx) : ORIGIN = __RAM_START_ADDRESS, LENGTH = 32K
48+
RAM(rwx) : ORIGIN = __RAM_START_ADDRESS + 32K, LENGTH = __RAM_SIZE - 32K
49+
STACK(rw) : ORIGIN = __STACK_START_ADDRESS, LENGTH = __STACK_SIZE
5250
}
5351

5452
/******************************************************************************************
5553
Sections definition
5654
******************************************************************************************/
5755
SECTIONS
5856
{
59-
/* Program code (text) */
60-
.text : ALIGN(4)
57+
. = __ROM_START_ADDRESS;
58+
59+
.boot : ALIGN(0x10)
6160
{
62-
PROVIDE(__CODE_BASE_ADDRESS = .);
6361
*(.boot)
64-
*(.text)
65-
. = ALIGN(4);
66-
} > FLASH
62+
. = ALIGN(0x10);
63+
*(.boot*)
64+
. = ALIGN(0x10);
65+
} > BOOT = 0x5555
6766

68-
/* Read-only data (.rodata) */
69-
.rodata : ALIGN(4)
67+
.startup : ALIGN(0x10)
7068
{
71-
PROVIDE(__RODATA_BASE_ADDRESS = .);
72-
*(.rodata)
73-
} > FLASH
69+
*(.startup)
70+
. = ALIGN(0x10);
71+
*(.startup*)
72+
. = ALIGN(0x10);
73+
} > START = 0x5555
7474

75-
/* Section for constructors */
76-
.ctors : ALIGN(4)
75+
/* Program code (text) */
76+
.text : ALIGN(0x100)
7777
{
78-
PROVIDE(__CTOR_LIST__ = .);
79-
KEEP (*(SORT(.ctors.*)))
80-
KEEP (*(.ctors))
81-
KEEP (*(SORT(.init_array.*)))
82-
KEEP (*(.init_array))
83-
LONG(-1) ;
84-
PROVIDE(__CTOR_END__ = .);
78+
_ctors_begin = .;
79+
KEEP(*(SORT(.init_array.*)))
80+
KEEP(*(.init_array*))
81+
_ctors_end = .;
82+
*(.progmem*)
8583
. = ALIGN(4);
86-
} > FLASH
87-
84+
*(.text)
85+
. = ALIGN(4);
86+
*(.text*)
87+
. = ALIGN(4);
88+
*(.rodata)
89+
. = ALIGN(4);
90+
*(.rodata*)
91+
. = ALIGN(4);
92+
*(.srodata)
93+
. = ALIGN(4);
94+
*(.srodata*)
95+
. = ALIGN(4);
96+
*(.glue_7)
97+
. = ALIGN(4);
98+
*(.glue_7t)
99+
. = ALIGN(4);
100+
} > ROM
88101

89-
/* Section for destructors */
90-
.dtors : ALIGN(4)
102+
.riscv.extab :
91103
{
92-
PROVIDE(__DTOR_LIST__ = .);
93-
KEEP (*(SORT(.dtors.*)))
94-
KEEP (*(.dtors))
95-
KEEP (*(SORT(.fini_array.*)))
96-
KEEP (*(.fini_array))
97-
LONG(-1) ;
98-
PROVIDE(__DTOR_END__ = .);
99-
. = ALIGN(4);
100-
} > FLASH
101-
102-
/* Runtime clear table */
103-
.clear_sec : ALIGN(4)
104+
. = ALIGN(4);
105+
*(.riscv.extab)
106+
*(.gnu.linkonce.riscvextab.*)
107+
. = ALIGN(4);
108+
} > ROM
109+
110+
.exidx :
104111
{
105-
PROVIDE(__RUNTIME_CLEAR_TABLE = .) ;
106-
LONG(0 + ADDR(.bss)); LONG(SIZEOF(.bss));
107-
LONG(-1); LONG(-1);
108112
. = ALIGN(4);
109-
} > FLASH
113+
PROVIDE(__exidx_start = .);
114+
*(.riscv.exidx*)
115+
. = ALIGN(4);
116+
PROVIDE(__exidx_end = .);
117+
} > ROM
118+
119+
. = __RAM_START_ADDRESS;
120+
. = ALIGN(4);
110121

111-
/* Runtime copy table */
112-
.copy_sec : ALIGN(4)
122+
/* The ROM-to-RAM initialized sdata section */
123+
.sdata : ALIGN(4)
113124
{
114-
PROVIDE(__RUNTIME_COPY_TABLE = .) ;
115-
LONG(LOADADDR(.data)); LONG(0 + ADDR(.data)); LONG(SIZEOF(.data));
116-
LONG(LOADADDR(.sdata)); LONG(0 + ADDR(.sdata)); LONG(SIZEOF(.sdata));
117-
LONG(-1); LONG(-1); LONG(-1);
125+
_sdata_begin = .;
126+
*(.sdata)
118127
. = ALIGN(4);
119-
PROVIDE(__CODE_END_ADDRESS = .);
120-
} > FLASH
128+
KEEP (*(.sdata))
129+
*(.sdata*)
130+
. = ALIGN(4);
131+
KEEP (*(.sdata*))
132+
_sdata_end = .;
133+
} > SRAM AT > ROM
121134

122-
/* The ROM-to-RAM initialized data sections */
123-
.data : ALIGN(4)
135+
/* The ROM-to-RAM initialized data section */
136+
.data : ALIGN(4)
124137
{
138+
_data_begin = .;
125139
*(.data)
140+
. = ALIGN(4);
141+
KEEP (*(.data))
126142
*(.data*)
127143
. = ALIGN(4);
128-
} > RAM AT>FLASH
129-
130-
.sdata : ALIGN(4)
144+
KEEP (*(.data*))
145+
_data_end = .;
146+
} > RAM AT > ROM
147+
148+
/* The uninitialized (zero-cleared) sbss section */
149+
.sbss : ALIGN(4)
131150
{
132-
*(.sdata)
151+
_sbss_begin = .;
152+
*(.sbss)
133153
. = ALIGN(4);
134-
} > RAM AT>FLASH
135-
136-
154+
KEEP (*(.sbss))
155+
*(.sbss*)
156+
. = ALIGN(4);
157+
KEEP (*(.sbss*))
158+
_sbss_end = .;
159+
} > SRAM
137160

138-
/* The uninitialized (zero-cleared) data sections */
161+
/* The uninitialized (zero-cleared) bss section */
139162
.bss : ALIGN(4)
140163
{
164+
_bss_begin = .;
141165
*(.bss)
142-
*(.bss*)
143166
. = ALIGN(4);
144-
} > RAM
145-
146-
.sbss : ALIGN(4)
147-
{
148-
*(.sbss)
167+
KEEP (*(.bss))
168+
*(.bss*)
149169
. = ALIGN(4);
170+
KEEP (*(.bss*))
171+
_bss_end = .;
150172
} > RAM
151173

174+
PROVIDE(end = .);
175+
PROVIDE(_fini = .);
176+
177+
. = __STACK_START_ADDRESS;
178+
152179
/* stack definition */
153180
.stack :
154181
{
155182
. = ALIGN(MAX(__STACK_SIZE , .), 8);
156-
PROVIDE(__STACK_TOP = .) ;
183+
PROVIDE(__initial_stack_pointer = .) ;
157184
} > STACK
158185

186+
_srom_data_begin = LOADADDR(.sdata);
187+
_rom_data_begin = LOADADDR(.data);
159188
}

‎ref_app/target/micros/bl602_sifive_e24_riscv/make/bl602_sifive_e24_riscv_files.gmk‎

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,9 @@
99
# File list of the target-specific files in the project
1010
# ------------------------------------------------------------------------------
1111

12-
FILES_TGT = $(PATH_APP)/mcal/mcal_gcc_cxx_completion \
13-
$(PATH_TGT)/Code/Startup/boot \
14-
$(PATH_TGT)/startup/intvect \
15-
$(PATH_TGT)/startup/Startup
12+
FILES_TGT = $(PATH_APP)/mcal/mcal_gcc_cxx_completion \
13+
$(PATH_TGT)/Code/Startup/boot \
14+
$(PATH_TGT)/startup/crt0 \
15+
$(PATH_TGT)/startup/crt0_init_ram \
16+
$(PATH_TGT)/startup/crt1 \
17+
$(PATH_TGT)/startup/intvect

‎ref_app/target/micros/bl602_sifive_e24_riscv/make/bl602_sifive_e24_riscv_flags.gmk‎

Lines changed: 5 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -15,17 +15,12 @@ GCC_VERSION := 15.2.0
1515

1616
TGT_SUFFIX = elf
1717

18-
ARCH := -mcpu=sifive-e24 \
19-
-mabi=ilp32 \
20-
-msmall-data-limit=0 \
21-
-falign-functions=4
22-
2318
TGT_ALLFLAGS = -O2 \
24-
$(ARCH) \
25-
-DPRINTF_INCLUDE_CONFIG_H \
26-
-fomit-frame-pointer \
27-
-fno-reorder-blocks-and-partition \
28-
-fno-reorder-functions
19+
-ffast-math \
20+
-mcpu=sifive-e24 \
21+
-mabi=ilp32 \
22+
-msmall-data-limit=32 \
23+
-falign-functions=4
2924

3025

3126
TGT_CFLAGS = -std=c11 \

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