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ckormanyosckormanyos
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Get RISC-V coprocessor booting and running
1 parent f7002b0 commit 7891c39

23 files changed

Lines changed: 39722 additions & 251 deletions

‎ref_app/src/mcal/xtensa_esp32_s3/esp32s3.h‎

Lines changed: 39052 additions & 0 deletions
Large diffs are not rendered by default.

‎ref_app/src/mcal/xtensa_esp32_s3/mcal_cpu.cpp‎

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Original file line numberDiff line numberDiff line change
@@ -14,10 +14,13 @@
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#include <mcal_reg.h>
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#include <mcal_wdg.h>
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#include <esp32s3.h>
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1719
extern "C"
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{
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auto main_c1() -> void;
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auto Mcu_StartCore1() -> void;
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auto Mcu_StartCoProcessorRiscV() -> void;
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extern auto set_cpu_private_timer1(uint32_t) -> void;
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extern auto _start() -> void;
@@ -83,6 +86,18 @@ auto Mcu_StartCore1() -> void
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}
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}
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89+
extern "C"
90+
auto Mcu_StartCoProcessorRiscV() -> void
91+
{
92+
RTC_CNTL->COCPU_CTRL.bit.COCPU_SHUT_RESET_EN = 1;
93+
RTC_CNTL->ULP_CP_TIMER.reg = 0;
94+
RTC_CNTL->COCPU_CTRL.bit.COCPU_CLK_FO = 1;
95+
RTC_CNTL->COCPU_CTRL.bit.COCPU_DONE_FORCE = 1;
96+
RTC_CNTL->COCPU_CTRL.bit.COCPU_CLKGATE_EN = 1;
97+
RTC_CNTL->COCPU_CTRL.bit.COCPU_SEL = 0;
98+
RTC_CNTL->ULP_CP_CTRL.bit.ULP_CP_FORCE_START_TOP = 0;
99+
}
100+
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extern "C"
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auto main_c1() -> void
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{
@@ -108,6 +123,9 @@ auto mcal::cpu::post_init() noexcept -> void
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// Set the private cpu timer1 for core0.
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set_cpu_private_timer1(mcal::gpt::timer1_reload());
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126+
// Use core0 to start the RISC-V core.
127+
Mcu_StartCoProcessorRiscV();
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// Use core0 to start core1.
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Mcu_StartCore1();
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}

‎ref_app/src/mcal/xtensa_esp32_s3/mcal_port.h‎

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@@ -35,6 +35,10 @@
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static void set_direction_input()
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{
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mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, mcal::reg::gpio::enable_w1ts, bit_pos>::bit_clr();
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mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, mcal::reg::gpio::enable1_w1ts, bit_pos>::bit_clr();
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mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, mcal::reg::gpio::out, bit_pos>::bit_clr();
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mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, mcal::reg::gpio::out1, bit_pos>::bit_clr();
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}
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static void set_pin_high()

‎ref_app/src/mcal/xtensa_esp32_s3/mcal_reg.h‎

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Original file line numberDiff line numberDiff line change
@@ -96,6 +96,23 @@
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constexpr std::uint32_t swd_wprotect { rtc_cntl_base + UINT32_C(0x000000B8) };
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constexpr std::uint32_t sw_cpu_stall { rtc_cntl_base + UINT32_C(0x000000BC) };
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constexpr std::uint32_t store4 { rtc_cntl_base + UINT32_C(0x000000C0) };
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constexpr std::uint32_t store5 { rtc_cntl_base + UINT32_C(0x000000C4) };
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constexpr std::uint32_t store6 { rtc_cntl_base + UINT32_C(0x000000C8) };
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constexpr std::uint32_t store7 { rtc_cntl_base + UINT32_C(0x000000CC) };
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constexpr std::uint32_t low_power_st { rtc_cntl_base + UINT32_C(0x000000D0) };
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constexpr std::uint32_t diag0 { rtc_cntl_base + UINT32_C(0x000000D4) };
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constexpr std::uint32_t pad_hold { rtc_cntl_base + UINT32_C(0x000000D8) };
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constexpr std::uint32_t dig_pad_hold { rtc_cntl_base + UINT32_C(0x000000DC) };
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constexpr std::uint32_t ext_wakeup1 { rtc_cntl_base + UINT32_C(0x000000E0) };
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constexpr std::uint32_t ext_wakeup1_status { rtc_cntl_base + UINT32_C(0x000000E4) };
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constexpr std::uint32_t brown_out { rtc_cntl_base + UINT32_C(0x000000E8) };
109+
constexpr std::uint32_t time_low1 { rtc_cntl_base + UINT32_C(0x000000EC) };
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constexpr std::uint32_t time_high1 { rtc_cntl_base + UINT32_C(0x000000F0) };
111+
constexpr std::uint32_t xtal32k_clk_factor { rtc_cntl_base + UINT32_C(0x000000F4) };
112+
constexpr std::uint32_t xtal32k_conf { rtc_cntl_base + UINT32_C(0x000000F8) };
113+
constexpr std::uint32_t ulp_cp_timer { rtc_cntl_base + UINT32_C(0x000000FC) };
114+
constexpr std::uint32_t ulp_cp_ctrl { rtc_cntl_base + UINT32_C(0x00000100) };
115+
constexpr std::uint32_t cocpu_ctrl { rtc_cntl_base + UINT32_C(0x00000104) };
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} // namespace rtc_cntl
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namespace timg0

‎ref_app/target.vcxproj‎

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@@ -1034,14 +1034,16 @@
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<None Include="target\micros\xtensa_esp32_s3\make\xtensa_esp32_s3_flags.gmk" />
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<None Include="target\micros\xtensa_esp32_s3\make\xtensa_esp32_s3_flags_extra.gmk" />
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<None Include="target\micros\xtensa_esp32_s3\startup\boot.S" />
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<None Include="target\micros\xtensa_esp32_s3\startup\coprocessor_binary.S" />
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<None Include="target\micros\xtensa_esp32_s3\startup\IntVectTable.S" />
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<None Include="target\micros\xtensa_esp32_s3\startup\Std\ieee754-sf.S" />
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<None Include="target\micros\xtensa_esp32_s3\startup\Std\lib1funcs.S" />
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<None Include="target\micros\xtensa_esp32_s3_riscv_cop\make\xtensa_esp32_s3_riscv_cop.ld" />
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<None Include="target\micros\xtensa_esp32_s3_riscv_cop\make\xtensa_esp32_s3_riscv_cop_files.gmk" />
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<None Include="target\micros\xtensa_esp32_s3_riscv_cop\make\xtensa_esp32_s3_riscv_cop_flags.gmk" />
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<None Include="target\micros\xtensa_esp32_s3_riscv_cop\startup\from_no_sdk\Startup\boot.S" />
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<None Include="target\micros\xtensa_esp32_s3_riscv_cop\startup\from_no_sdk\Startup\IntVectTable.S" />
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<None Include="target\micros\xtensa_esp32_s3_riscv_cop\startup\from_no_sdk\Code\Startup\boot.S" />
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<None Include="target\micros\xtensa_esp32_s3_riscv_cop\startup\from_no_sdk\Code\Startup\IntVectTable.S" />
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<None Include="target\micros\xtensa_esp32_s3_riscv_cop\startup\from_no_sdk\Scripts\bin2asm.py" />
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</ItemGroup>
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<ItemGroup>
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<ClCompile Include="target\micros\am335x\startup\crt0.cpp" />
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<ClCompile Include="target\micros\xtensa_esp32_s3\startup\crt0_init_ram.cpp" />
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<ClCompile Include="target\micros\xtensa_esp32_s3\startup\crt1.cpp" />
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<ClCompile Include="target\micros\xtensa_esp32_s3\startup\Std\StdLib.cpp" />
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<ClCompile Include="target\micros\xtensa_esp32_s3_riscv_cop\startup\from_no_sdk\Appli\main.cpp" />
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<ClCompile Include="target\micros\xtensa_esp32_s3_riscv_cop\startup\from_no_sdk\Startup\Startup.c" />
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<ClCompile Include="target\micros\xtensa_esp32_s3_riscv_cop\startup\from_no_sdk\Code\Appli\main.cpp" />
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<ClCompile Include="target\micros\xtensa_esp32_s3_riscv_cop\startup\from_no_sdk\Code\Mcal\Mcu.cpp" />
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<ClCompile Include="target\micros\xtensa_esp32_s3_riscv_cop\startup\from_no_sdk\Code\Startup\Startup.c" />
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</ItemGroup>
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<ItemGroup>
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<Text Include="target\micros\bcm2835_raspi_b\startup\SD_CARD\PiZero\config.txt" />
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</ItemGroup>
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<ItemGroup>
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<ClInclude Include="target\micros\xtensa_esp32_s3\startup\Std\core-isa.h" />
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<ClInclude Include="target\micros\xtensa_esp32_s3_riscv_cop\startup\from_no_sdk\Startup\custom_ops.h" />
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</ItemGroup>
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<ItemGroup>
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<Library Include="target\micros\xtensa_esp32_s3\startup\Std\lib_call0_abi\libc_call0_abi.a" />

‎ref_app/target.vcxproj.filters‎

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@@ -292,12 +292,21 @@
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<Filter Include="micros\xtensa_esp32_s3_riscv_cop\startup\from_no_sdk">
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<UniqueIdentifier>{bb1fed00-c4cd-4e52-833d-16cf0f69bc10}</UniqueIdentifier>
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</Filter>
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<Filter Include="micros\xtensa_esp32_s3_riscv_cop\startup\from_no_sdk\Startup">
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<UniqueIdentifier>{66ae9aa3-915d-4366-9492-87cdb30add93}</UniqueIdentifier>
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<Filter Include="micros\xtensa_esp32_s3_riscv_cop\startup\from_no_sdk\Code">
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<UniqueIdentifier>{de099968-fa17-4f75-b098-50ed5325d04f}</UniqueIdentifier>
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</Filter>
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<Filter Include="micros\xtensa_esp32_s3_riscv_cop\startup\from_no_sdk\Appli">
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<Filter Include="micros\xtensa_esp32_s3_riscv_cop\startup\from_no_sdk\Code\Appli">
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<UniqueIdentifier>{7b9aadde-8fde-47da-bd4b-d348e1b2778d}</UniqueIdentifier>
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</Filter>
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<Filter Include="micros\xtensa_esp32_s3_riscv_cop\startup\from_no_sdk\Code\Mcal">
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<UniqueIdentifier>{fbf8a8a1-b81b-418d-b1b2-9f8d5724180d}</UniqueIdentifier>
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</Filter>
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<Filter Include="micros\xtensa_esp32_s3_riscv_cop\startup\from_no_sdk\Code\Startup">
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<UniqueIdentifier>{66ae9aa3-915d-4366-9492-87cdb30add93}</UniqueIdentifier>
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</Filter>
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<Filter Include="micros\xtensa_esp32_s3_riscv_cop\startup\from_no_sdk\Scripts">
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<UniqueIdentifier>{1a0b187b-0ef0-4365-b263-303097393b67}</UniqueIdentifier>
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</Filter>
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</ItemGroup>
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<ItemGroup>
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<None Include="target\app\make\app_files.gmk">
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<None Include="target\micros\xtensa_esp32_s3_riscv_cop\make\xtensa_esp32_s3_riscv_cop_flags.gmk">
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<Filter>micros\xtensa_esp32_s3_riscv_cop\make</Filter>
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</None>
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<None Include="target\micros\xtensa_esp32_s3_riscv_cop\startup\from_no_sdk\Startup\boot.S">
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<Filter>micros\xtensa_esp32_s3_riscv_cop\startup\from_no_sdk\Startup</Filter>
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<None Include="target\micros\xtensa_esp32_s3_riscv_cop\startup\from_no_sdk\Code\Startup\IntVectTable.S">
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<Filter>micros\xtensa_esp32_s3_riscv_cop\startup\from_no_sdk\Code\Startup</Filter>
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</None>
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<None Include="target\micros\xtensa_esp32_s3_riscv_cop\startup\from_no_sdk\Startup\IntVectTable.S">
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<Filter>micros\xtensa_esp32_s3_riscv_cop\startup\from_no_sdk\Startup</Filter>
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<None Include="target\micros\xtensa_esp32_s3_riscv_cop\startup\from_no_sdk\Code\Startup\boot.S">
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<Filter>micros\xtensa_esp32_s3_riscv_cop\startup\from_no_sdk\Code\Startup</Filter>
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</None>
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<None Include="target\micros\xtensa_esp32_s3_riscv_cop\startup\from_no_sdk\Scripts\bin2asm.py">
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<Filter>micros\xtensa_esp32_s3_riscv_cop\startup\from_no_sdk\Scripts</Filter>
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</None>
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<None Include="target\micros\xtensa_esp32_s3\startup\coprocessor_binary.S">
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<Filter>micros\xtensa_esp32_s3\startup</Filter>
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</None>
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</ItemGroup>
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<ItemGroup>
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<ClCompile Include="target\micros\xtensa_esp32_s3\startup\Std\StdLib.cpp">
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<Filter>micros\xtensa_esp32_s3\startup\Std</Filter>
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</ClCompile>
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<ClCompile Include="target\micros\xtensa_esp32_s3_riscv_cop\startup\from_no_sdk\Startup\Startup.c">
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<Filter>micros\xtensa_esp32_s3_riscv_cop\startup\from_no_sdk\Startup</Filter>
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<ClCompile Include="target\micros\xtensa_esp32_s3_riscv_cop\startup\from_no_sdk\Code\Mcal\Mcu.cpp">
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<Filter>micros\xtensa_esp32_s3_riscv_cop\startup\from_no_sdk\Code\Mcal</Filter>
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</ClCompile>
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<ClCompile Include="target\micros\xtensa_esp32_s3_riscv_cop\startup\from_no_sdk\Appli\main.cpp">
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<Filter>micros\xtensa_esp32_s3_riscv_cop\startup\from_no_sdk\Appli</Filter>
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<ClCompile Include="target\micros\xtensa_esp32_s3_riscv_cop\startup\from_no_sdk\Code\Startup\Startup.c">
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<Filter>micros\xtensa_esp32_s3_riscv_cop\startup\from_no_sdk\Code\Startup</Filter>
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</ClCompile>
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<ClCompile Include="target\micros\xtensa_esp32_s3_riscv_cop\startup\from_no_sdk\Code\Appli\main.cpp">
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<Filter>micros\xtensa_esp32_s3_riscv_cop\startup\from_no_sdk\Code\Appli</Filter>
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</ClCompile>
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</ItemGroup>
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<ItemGroup>
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<ClInclude Include="target\micros\xtensa_esp32_s3\startup\Std\core-isa.h">
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<Filter>micros\xtensa_esp32_s3\startup\Std</Filter>
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</ClInclude>
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<ClInclude Include="target\micros\xtensa_esp32_s3_riscv_cop\startup\from_no_sdk\Startup\custom_ops.h">
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<Filter>micros\xtensa_esp32_s3_riscv_cop\startup\from_no_sdk\Startup</Filter>
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</ClInclude>
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</ItemGroup>
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<ItemGroup>
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<Library Include="target\micros\xtensa_esp32_s3\startup\Std\lib_call0_abi\libc_call0_abi.a">

‎ref_app/target/micros/xtensa_esp32_s3/make/xtensa_esp32_s3.ld‎

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PROVIDE(__CORE1_STACK_TOP = .) ;
127127
} > D_SRAM
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129+
. = 0x50000000;
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129131
.ulp :
130132
{
131133
*(.coprocessor*)

‎ref_app/target/micros/xtensa_esp32_s3/make/xtensa_esp32_s3_files.gmk‎

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FILES_TGT := $(PATH_APP)/mcal/mcal_gcc_cxx_completion \
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$(PATH_TGT)/startup/boot \
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$(PATH_TGT)/startup/coprocessor_binary \
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$(PATH_TGT)/startup/crt0 \
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$(PATH_TGT)/startup/crt0_init_ram \
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$(PATH_TGT)/startup/crt1 \

‎ref_app/target/micros/xtensa_esp32_s3/make/xtensa_esp32_s3_flags.gmk‎

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TGT_SUFFIX = elf
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WARN_FLAGS := -Wall \
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-Wextra \
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-Wpointer-arith \
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-Wno-maybe-uninitialized \
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-Wno-unused-function \
@@ -64,7 +65,6 @@ TGT_AFLAGS =
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TGT_LDFLAGS = -nostartfiles \
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-nostdlib \
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-L$(PATH_TGT)/startup/Std/lib_call0_abi \
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-Wl,--gc-sections \
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-Wl,-Map,$(APP).map \
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-T $(LINKER_DEFINITION_FILE) \
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--specs=nano.specs \

‎ref_app/target/micros/xtensa_esp32_s3/startup/Std/StdLib.cpp‎

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//
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// Originally from:
9-
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/******************************************************************************************
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Filename : StdLib.c
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