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1 | 1 | /////////////////////////////////////////////////////////////////////////////// |
2 | | -// Copyright Christopher Kormanyos 2007 - 2024. |
| 2 | +// Copyright Christopher Kormanyos 2007 - 2025. |
3 | 3 | // Distributed under the Boost Software License, |
4 | 4 | // Version 1.0. (See accompanying file LICENSE_1_0.txt |
5 | 5 | // or copy at http://www.boost.org/LICENSE_1_0.txt) |
@@ -29,19 +29,28 @@ auto mcal::wdg::init(const config_type*) -> void |
29 | 29 | // Reset the watchdog timer. |
30 | 30 | asm volatile("wdr"); |
31 | 31 |
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32 | | - // Set the watchdog timer period and activate the watchdog timer. |
| 32 | + // Start timed sequence in order to set the watchdog |
| 33 | + // timer period and activate the watchdog timer. |
33 | 34 | mcal::reg::reg_access_static<std::uint8_t, |
34 | 35 | std::uint8_t, |
35 | 36 | mcal::reg::wdtcsr, |
36 | 37 | std::uint8_t(0x18U)>::reg_set(); |
37 | 38 |
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38 | | - // See Chapter 11.9.2, Table 11-2: Watchdog Timer Prescale Select. |
39 | | - // Select WDP3:WDP0 in WDTCSR to binary 0b0111, resulting |
40 | | - // in a watchdog period of approximately 2s. |
| 39 | + // In "Atmel-7810-Automotive-Microcontrollers-ATmega328P_Datasheet.pdf", |
| 40 | + // see Chapter 10.9.2, Table 10-3: Watchdog Timer Prescale Select. |
| 41 | + // Set WDP3 (bit 5) and clear WDP2:WDP0 (bits 0, 1 and 2) in WDTCSR |
| 42 | + // (i.e., set to hex 0x20). This results in a watchdog period |
| 43 | + // of approximately 4s. |
41 | 44 | mcal::reg::reg_access_static<std::uint8_t, |
42 | 45 | std::uint8_t, |
43 | 46 | mcal::reg::wdtcsr, |
44 | | - std::uint8_t(0x08U) | std::uint8_t(0x07U)>::reg_set(); |
| 47 | + std::uint8_t(0x20U)>::reg_set(); |
| 48 | + |
| 49 | + // Set WDRF in the MCU status register. |
| 50 | + mcal::reg::reg_access_static<std::uint8_t, |
| 51 | + std::uint8_t, |
| 52 | + mcal::reg::mcusr, |
| 53 | + std::uint8_t(3U)>::bit_set(); |
45 | 54 | } |
46 | 55 |
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47 | 56 | auto mcal::wdg::secure::trigger() -> void |
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