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ckormanyosckormanyos
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Use C++-ified regs but port_pin still needed
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Lines changed: 49 additions & 23 deletions

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‎readme.md‎

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@@ -76,6 +76,7 @@ The reference application supports the following targets (in alpha-numeric order
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| `atmega4809` | MICROCHIP(R) [former ATMEL(R)] AVR(R) ATmegax4809 | X |
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| `avr` (as used in the book) | MICROCHIP(R) [former ATMEL(R)] AVR(R) ATmega328P | X |
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| `bcm2835_raspi_b` | RaspberryPi(R) Zero with ARM1176-JZFS(TM) | X |
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| `bl602_sifive_e24_riscv` | BL602 single-core RISC-V (SiFive E24) | X |
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| `Debug`/`Release` | PC on `Win*` via MSVC x64 compiler `Debug`/`Release` | |
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| `host` | PC/Workstation on `Win*`/`mingw64`/`*nix` via host compiler | |
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| `lpc11c24` | NXP(R) OM13093 LPC11C24 board ARM(R) Cortex(R)-M0+ | |
@@ -415,6 +416,13 @@ called `target avr` (as used in the book) runs
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on a classic ARDUINO(R) compatible board.
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The program toggles the yellow LED on `portb.5`.
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Target `bl602_sifive_e24_riscv` contains a fully manually-written bare-metal project
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for the BL602 single-core RISC-V (SiFive E24), making no use of any SDK.
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The boot code and bare-metal register interactions are based
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on the creative work in
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[`Chalandi/Baremetal_BL602_SiFive_E24_RISC-V`](https://github.com/Chalandi/Baremetal_BL602_SiFive_E24_RISC-V).
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This configuration toggles pin `IO3` and requires a self-fitted LED.
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The ARM(R) 1176-JZF-S configuration (called `target bcm2835_raspi_b`) runs on the
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RaspberryPi(R) Zero (PiZero) single core controller.
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This project creates a bare-metal program for the PiZero.

‎ref_app/src/mcal/bl602_sifive_e24_riscv/BL602.h‎

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#ifndef BL602_H
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#define BL602_H
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#if 0
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#include "stdint.h"
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#ifdef __cplusplus
@@ -1150,4 +1151,6 @@ typedef struct { /*!< glb Structure
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}
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#endif
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#endif
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#endif /* BL602_H */

‎ref_app/src/mcal/bl602_sifive_e24_riscv/mcal_led.cpp‎

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@@ -5,37 +5,52 @@
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// or copy at http://www.boost.org/LICENSE_1_0.txt)
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//
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#include <mcal_led.h>
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#include <mcal_led/mcal_led_boolean_state_base.h>
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#include <mcal_led.h>
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#include <mcal_reg.h>
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#include <util/utility/util_time.h>
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#include "BL602.h"
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#include <cstdint>
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namespace
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{
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constexpr std::uint32_t GPIO_FUN_SDIO { UINT32_C( 1) };
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constexpr std::uint32_t GPIO_FUN_FLASH { UINT32_C( 2) };
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constexpr std::uint32_t GPIO_FUN_SPI { UINT32_C( 4) };
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constexpr std::uint32_t GPIO_FUN_I2C { UINT32_C( 6) };
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constexpr std::uint32_t GPIO_FUN_UART { UINT32_C( 7) };
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constexpr std::uint32_t GPIO_FUN_PWM { UINT32_C( 8) };
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constexpr std::uint32_t GPIO_FUN_EXT_PA { UINT32_C( 9) };
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constexpr std::uint32_t GPIO_FUN_ANALOG { UINT32_C(10) };
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constexpr std::uint32_t GPIO_FUN_SWGPIO { UINT32_C(11) };
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constexpr std::uint32_t GPIO_FUN_JTAG { UINT32_C(14) };
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} // anonymous namespace
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class led_port_tmp_bl606 : public mcal::led::led_boolean_state_base
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{
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public:
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led_port_tmp_bl606() noexcept
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{
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/* configure IO3 as output */
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glb->GPIO_CFGCTL1.bit.reg_gpio_3_func_sel = GPIO_FUN_SWGPIO;
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glb->GPIO_CFGCTL1.bit.reg_gpio_3_ie = 0ul;
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glb->GPIO_CFGCTL1.bit.reg_gpio_3_drv = 0ul;
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glb->GPIO_CFGCTL1.bit.reg_gpio_3_smt = 0ul;
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glb->GPIO_CFGCTL34.bit.reg_gpio_3_oe = 1ul;
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// Configure IO3 as output, low.
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// glb->GPIO_CFGCTL1.bit.reg_gpio_3_func_sel = GPIO_FUN_SWGPIO;
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// glb->GPIO_CFGCTL1.bit.reg_gpio_3_ie = 0ul;
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// glb->GPIO_CFGCTL1.bit.reg_gpio_3_smt = 0ul;
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// glb->GPIO_CFGCTL1.bit.reg_gpio_3_drv = 0ul;
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// glb->GPIO_CFGCTL34.bit.reg_gpio_3_oe = 1ul;
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mcal::reg::reg_access_static<std::uintptr_t, std::uint32_t, mcal::reg::gpio_cfgctl1, static_cast<std::uint32_t>(GPIO_FUN_SWGPIO << 24U)>::template reg_msk<static_cast<std::uint32_t>(UINT32_C(0xF) << 24U)>();
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mcal::reg::reg_access_static<std::uintptr_t, std::uint32_t, mcal::reg::gpio_cfgctl1, UINT32_C(16)>::bit_clr();
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mcal::reg::reg_access_static<std::uintptr_t, std::uint32_t, mcal::reg::gpio_cfgctl1, UINT32_C(17)>::bit_clr();
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mcal::reg::reg_access_static<std::uintptr_t, std::uint32_t, mcal::reg::gpio_cfgctl1, UINT32_C(0) << 18U>::template reg_msk<UINT32_C(3) << 18U>();
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mcal::reg::reg_access_static<std::uintptr_t, std::uint32_t, mcal::reg::gpio_cfgctl34, UINT32_C(3)>::bit_set();
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}
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~led_port_tmp_bl606() override = default;
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auto toggle() noexcept -> void override
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{
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using base_class_type = led_boolean_state_base;
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// Toggle the IO3 pin.
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// glb->GPIO_CFGCTL32.bit.reg_gpio_3_o ^= 1ul;
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mcal::reg::reg_access_static<std::uintptr_t, std::uint32_t, mcal::reg::gpio_cfgctl32, UINT32_C(3)>::bit_not();
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//glb->GPIO_CFGCTL32.bit.reg_gpio_3_o ^= 1ul;
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using base_class_type = led_boolean_state_base;
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base_class_type::toggle();
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}

‎ref_app/src/mcal/bl602_sifive_e24_riscv/mcal_reg.h‎

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constexpr std::uintptr_t clic_clk_gate { clic_ctrl_addr + UINT32_C(0x007FF000) };
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constexpr std::uintptr_t glb_base { UINT32_C(0x40000000) };
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constexpr std::uintptr_t gpio_cfgctl0 { glb_base + UINT32_C(0x40) };
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constexpr std::uintptr_t gpio_cfgctl1 { glb_base + UINT32_C(0x44) };
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constexpr std::uintptr_t gpio_cfgctl2 { glb_base + UINT32_C(0x48) };
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constexpr std::uintptr_t gpio_cfgctl3 { glb_base + UINT32_C(0x4C) };
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constexpr std::uintptr_t gpio_cfgctl4 { glb_base + UINT32_C(0x50) };
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constexpr std::uintptr_t gpio_cfgctl30 { glb_base + UINT32_C(0x180) };
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constexpr std::uintptr_t gpio_cfgctl31 { glb_base + UINT32_C(0x184) };
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constexpr std::uintptr_t gpio_cfgctl32 { glb_base + UINT32_C(0x188) };
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constexpr std::uintptr_t gpio_cfgctl33 { glb_base + UINT32_C(0x18C) };
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constexpr std::uintptr_t gpio_cfgctl34 { glb_base + UINT32_C(0x190) };
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constexpr std::uintptr_t gpio_cfgctl0 { glb_base + UINT32_C(0x00000100) };
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constexpr std::uintptr_t gpio_cfgctl1 { glb_base + UINT32_C(0x00000104) };
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constexpr std::uintptr_t gpio_cfgctl2 { glb_base + UINT32_C(0x00000108) };
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constexpr std::uintptr_t gpio_cfgctl3 { glb_base + UINT32_C(0x0000010C) };
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constexpr std::uintptr_t gpio_cfgctl4 { glb_base + UINT32_C(0x00000104) };
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constexpr std::uintptr_t gpio_cfgctl30 { glb_base + UINT32_C(0x00000180) };
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constexpr std::uintptr_t gpio_cfgctl31 { glb_base + UINT32_C(0x00000184) };
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constexpr std::uintptr_t gpio_cfgctl32 { glb_base + UINT32_C(0x00000188) };
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constexpr std::uintptr_t gpio_cfgctl33 { glb_base + UINT32_C(0x0000018C) };
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constexpr std::uintptr_t gpio_cfgctl34 { glb_base + UINT32_C(0x00000190) };
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}
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}
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