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ckormanyosckormanyos
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Get esp32_p4 benches running via hybrid startup
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12 files changed

+477
-219
lines changed

12 files changed

+477
-219
lines changed

‎ref_app/src/mcal/xtensa_esp32_p4/mcal_benchmark.h‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -5,8 +5,8 @@
55
// or copy at http://www.boost.org/LICENSE_1_0.txt)
66
//
77

8-
#ifndef MCAL_BENCHMARK_2014_04_16_H_
9-
#define MCAL_BENCHMARK_2014_04_16_H_
8+
#ifndef MCAL_BENCHMARK_2014_04_16_H
9+
#define MCAL_BENCHMARK_2014_04_16_H
1010

1111
#include <mcal_port.h>
1212
#include <mcal_reg.h>
@@ -17,8 +17,8 @@
1717
{
1818
namespace benchmark
1919
{
20-
typedef mcal::port::port_pin<UINT32_C(8)> benchmark_port_type;
20+
typedef mcal::port::port_pin<unsigned { UINT8_C(18) }> benchmark_port_type;
2121
}
2222
}
2323

24-
#endif // MCAL_BENCHMARK_2014_04_16_H_
24+
#endif // MCAL_BENCHMARK_2014_04_16_H

‎ref_app/src/mcal/xtensa_esp32_p4/mcal_port.h‎

Lines changed: 94 additions & 91 deletions
Original file line numberDiff line numberDiff line change
@@ -24,8 +24,8 @@
2424
2525
******************************************************************************************/
2626

27-
#ifndef MCAL_PORT_2025_02_22_H
28-
#define MCAL_PORT_2025_02_22_H
27+
#ifndef MCAL_PORT_2026_02_13_H
28+
#define MCAL_PORT_2026_02_13_H
2929

3030
#include <mcal_reg.h>
3131

@@ -46,122 +46,71 @@
4646
private:
4747
static constexpr std::uint8_t my_pin { static_cast<std::uint8_t>(PortIndex) };
4848

49-
static constexpr uintptr_t GPIO_BASE { (uintptr_t) UINT32_C(0x500E0000) };
50-
static constexpr uintptr_t LP_IO_MUX_BASE { (uintptr_t) UINT32_C(0x5012B000) };
51-
static constexpr uintptr_t IO_MUX_BASE { (uintptr_t) UINT32_C(0x500E1000) };
52-
5349
typedef union
5450
{
55-
volatile uint32_t reg;
51+
volatile std::uint32_t reg;
5652

5753
struct
5854
{
59-
volatile uint32_t MCU_OE : 1;
60-
volatile uint32_t SLP_SEL : 1;
61-
volatile uint32_t MCU_WPD : 1;
62-
volatile uint32_t MCU_WPU : 1;
63-
volatile uint32_t MCU_IE : 1;
64-
volatile uint32_t MCU_DRV : 2;
65-
volatile uint32_t FUN_WPD : 1;
66-
volatile uint32_t FUN_WPU : 1;
67-
volatile uint32_t FUN_IE : 1;
68-
volatile uint32_t FUN_DRV : 2;
69-
volatile uint32_t MCU_SEL : 3;
70-
volatile uint32_t FILTER_EN : 1;
71-
uint32_t : 16;
55+
volatile std::uint32_t MCU_OE : 1;
56+
volatile std::uint32_t SLP_SEL : 1;
57+
volatile std::uint32_t MCU_WPD : 1;
58+
volatile std::uint32_t MCU_WPU : 1;
59+
volatile std::uint32_t MCU_IE : 1;
60+
volatile std::uint32_t MCU_DRV : 2;
61+
volatile std::uint32_t FUN_WPD : 1;
62+
volatile std::uint32_t FUN_WPU : 1;
63+
volatile std::uint32_t FUN_IE : 1;
64+
volatile std::uint32_t FUN_DRV : 2;
65+
volatile std::uint32_t MCU_SEL : 3;
66+
volatile std::uint32_t FILTER_EN : 1;
67+
std::uint32_t : 16;
7268
}
7369
bit;
7470
}
7571
IO_MUX_GPIO;
7672

7773
typedef union
7874
{
79-
volatile uint32_t reg;
75+
volatile std::uint32_t reg;
8076

8177
struct
8278
{
83-
volatile uint32_t OUT_SEL : 9;
84-
volatile uint32_t INV_SEL : 1;
85-
volatile uint32_t OEN_SEL : 1;
86-
volatile uint32_t OEN_INV_SEL : 1;
87-
uint32_t : 20;
79+
volatile std::uint32_t OUT_SEL : 9;
80+
volatile std::uint32_t INV_SEL : 1;
81+
volatile std::uint32_t OEN_SEL : 1;
82+
volatile std::uint32_t OEN_INV_SEL : 1;
83+
std::uint32_t : 20;
8884
}
8985
bit;
9086
}
9187
GPIO_FUNC_OUT_SEL_CFG;
9288

9389
typedef union
9490
{
95-
volatile uint32_t reg;
91+
volatile std::uint32_t reg;
9692

9793
struct
9894
{
99-
volatile uint32_t REG_PAD_DRV : 2;
100-
volatile uint32_t REG_PAD_RDE : 1;
101-
volatile uint32_t REG_PAD_RUE : 1;
102-
volatile uint32_t REG_PAD_MUX_SEL : 1;
103-
volatile uint32_t REG_PAD_FUN_SEL : 2;
104-
volatile uint32_t REG_PAD_SLP_SEL : 1;
105-
volatile uint32_t REG_PAD_SLP_IE : 1;
106-
volatile uint32_t REG_PAD_SLP_OE : 1;
107-
volatile uint32_t REG_PAD_FUN_IE : 1;
108-
volatile uint32_t REG_PAD_FILTER_EN : 1;
109-
uint32_t : 20;
95+
volatile std::uint32_t REG_PAD_DRV : 2;
96+
volatile std::uint32_t REG_PAD_RDE : 1;
97+
volatile std::uint32_t REG_PAD_RUE : 1;
98+
volatile std::uint32_t REG_PAD_MUX_SEL : 1;
99+
volatile std::uint32_t REG_PAD_FUN_SEL : 2;
100+
volatile std::uint32_t REG_PAD_SLP_SEL : 1;
101+
volatile std::uint32_t REG_PAD_SLP_IE : 1;
102+
volatile std::uint32_t REG_PAD_SLP_OE : 1;
103+
volatile std::uint32_t REG_PAD_FUN_IE : 1;
104+
volatile std::uint32_t REG_PAD_FILTER_EN : 1;
105+
std::uint32_t : 20;
110106
}
111107
bit;
112108
}
113109
LP_IO_MUX_GPIO;
114110

115-
static void gpio_cfg_output()
116-
{
117-
if((unsigned) my_pin <= 54u)
118-
{
119-
volatile IO_MUX_GPIO* pIO_MUX_GPIO = (volatile IO_MUX_GPIO*)(IO_MUX_BASE + 4u + 4u * (unsigned) my_pin);
120-
volatile GPIO_FUNC_OUT_SEL_CFG* pGPIO_FUNC_OUT_SEL_CFG = (volatile GPIO_FUNC_OUT_SEL_CFG*)(GPIO_BASE + 0x558ul + 4u * (unsigned) my_pin);
121-
volatile LP_IO_MUX_GPIO* pLP_IO_MUX_GPIO = (volatile LP_IO_MUX_GPIO*)(LP_IO_MUX_BASE + 8u + 4u * (unsigned) my_pin);
122-
volatile uint32_t* pGPIO_OUTx_W1TC = (volatile uint32_t*)(GPIO_BASE + (((unsigned) my_pin < 32u) ? 0x0Cu : 0x18u));
123-
volatile uint32_t* pGPIO_ENABLE1x_W1TS = (volatile uint32_t*)(GPIO_BASE + (((unsigned) my_pin < 32u) ? 0x24u : 0x30u));
124-
125-
/* configure the pinmux */
126-
pIO_MUX_GPIO->bit.FUN_DRV = 2;
127-
pIO_MUX_GPIO->bit.FUN_IE = 0;
128-
pIO_MUX_GPIO->bit.MCU_SEL = 1;
129-
130-
/* set the output configuration */
131-
pGPIO_FUNC_OUT_SEL_CFG->bit.OUT_SEL = 256;
132-
pGPIO_FUNC_OUT_SEL_CFG->bit.OEN_SEL = 1;
133-
134-
if((unsigned) my_pin < 16u)
135-
{
136-
/* make LP_GPIO use HP_IO_MUX */
137-
pLP_IO_MUX_GPIO->bit.REG_PAD_MUX_SEL = 0;
138-
}
139-
140-
/* drive the IO output low */
141-
*pGPIO_OUTx_W1TC = (uint32_t)(1u << (((unsigned) my_pin < 32u) ? (unsigned) my_pin : ((unsigned) my_pin - 32u)));
142-
*pGPIO_ENABLE1x_W1TS = (uint32_t)(1u << (((unsigned) my_pin < 32u) ? (unsigned) my_pin : ((unsigned) my_pin - 32u)));
143-
}
144-
}
145-
146-
static void gpio_set_output_level(const uint8_t level)
147-
{
148-
if(((unsigned) my_pin <= 54u) && ((unsigned) level <= 1u))
149-
{
150-
volatile uint32_t* pGPIO_OUT_W1Tx = (volatile uint32_t*)(GPIO_BASE + (((unsigned) my_pin < 32u) ? 8u : 0x14u) + (((unsigned) level == 1u) ? (0u) : (4u)));
151-
152-
*pGPIO_OUT_W1Tx = (uint32_t)(1u << (((unsigned) my_pin < 32u) ? (unsigned) my_pin : ((unsigned) my_pin - 32u)));
153-
}
154-
}
155-
156-
static void gpio_toggle_output_level()
157-
{
158-
if((unsigned) my_pin <= 54u)
159-
{
160-
volatile uint32_t* pGPIO_OUT = (volatile uint32_t*)(GPIO_BASE + 4u + (((unsigned) my_pin < 32u) ? 0u : 0xCu));
161-
162-
*pGPIO_OUT ^= (uint32_t)(1u << (((unsigned) my_pin < 32u) ? (unsigned) my_pin : ((unsigned) my_pin - 32u)));
163-
}
164-
}
111+
static void gpio_cfg_output();
112+
static void gpio_set_output_level(const std::uint8_t level);
113+
static void gpio_toggle_output_level();
165114

166115
public:
167116
static auto set_direction_output() -> void
@@ -193,7 +142,61 @@
193142
gpio_toggle_output_level();
194143
}
195144
};
196-
}
197-
}
198145

199-
#endif // MCAL_PORT_2025_02_22_H
146+
template<const unsigned PortIndex>
147+
void port_pin<PortIndex>::gpio_cfg_output()
148+
{
149+
if(unsigned { my_pin } <= 54u)
150+
{
151+
volatile IO_MUX_GPIO* pIO_MUX_GPIO { reinterpret_cast<volatile IO_MUX_GPIO*> (mcal::reg::io_mux_base + 4u + 4u * unsigned { my_pin }) };
152+
volatile GPIO_FUNC_OUT_SEL_CFG* pGPIO_FUNC_OUT_SEL_CFG { reinterpret_cast<volatile GPIO_FUNC_OUT_SEL_CFG*>(mcal::reg::gpio_base + 0x558u + 4u * unsigned { my_pin }) };
153+
volatile LP_IO_MUX_GPIO* pLP_IO_MUX_GPIO { reinterpret_cast<volatile LP_IO_MUX_GPIO*> (mcal::reg::lp_io_mux_base + 8u + 4u * unsigned { my_pin }) };
154+
volatile std::uint32_t* pGPIO_OUTx_W1TC { reinterpret_cast<volatile std::uint32_t*> (mcal::reg::gpio_base + ((unsigned { my_pin } < 32u) ? 0x0Cu : 0x18u)) };
155+
volatile std::uint32_t* pGPIO_ENABLE1x_W1TS { reinterpret_cast<volatile std::uint32_t*> (mcal::reg::gpio_base + ((unsigned { my_pin } < 32u) ? 0x24u : 0x30u)) };
156+
157+
// Configure the pinmux.
158+
pIO_MUX_GPIO->bit.FUN_DRV = 2;
159+
pIO_MUX_GPIO->bit.FUN_IE = 0;
160+
pIO_MUX_GPIO->bit.MCU_SEL = 1;
161+
162+
// Set the output configuration.
163+
pGPIO_FUNC_OUT_SEL_CFG->bit.OUT_SEL = 256;
164+
pGPIO_FUNC_OUT_SEL_CFG->bit.OEN_SEL = 1;
165+
166+
if(unsigned { my_pin } < 16u)
167+
{
168+
// Make LP_GPIO use HP_IO_MUX.
169+
pLP_IO_MUX_GPIO->bit.REG_PAD_MUX_SEL = 0;
170+
}
171+
172+
// Drive the IO output low.
173+
*pGPIO_OUTx_W1TC = static_cast<std::uint32_t>(1u << ((unsigned { my_pin } < 32u) ? unsigned { my_pin } : (unsigned { my_pin } - 32u)));
174+
*pGPIO_ENABLE1x_W1TS = static_cast<std::uint32_t>(1u << ((unsigned { my_pin } < 32u) ? unsigned { my_pin } : (unsigned { my_pin } - 32u)));
175+
}
176+
}
177+
178+
template<const unsigned PortIndex>
179+
void port_pin<PortIndex>::gpio_set_output_level(const uint8_t level)
180+
{
181+
if((unsigned { my_pin } <= 54u) && (unsigned { level } <= 1u))
182+
{
183+
volatile std::uint32_t* pGPIO_OUT_W1Tx { reinterpret_cast<volatile std::uint32_t*>(mcal::reg::gpio_base + ((unsigned { my_pin } < 32u) ? 8u : 0x14u) + (((unsigned) level == 1u) ? (0u) : (4u))) };
184+
185+
*pGPIO_OUT_W1Tx = static_cast<std::uint32_t>(1u << ((unsigned { my_pin } < 32u) ? unsigned { my_pin } : (unsigned { my_pin } - 32u)));
186+
}
187+
}
188+
189+
template<const unsigned PortIndex>
190+
void port_pin<PortIndex>::gpio_toggle_output_level()
191+
{
192+
if(unsigned { my_pin } <= 54u)
193+
{
194+
volatile std::uint32_t* pGPIO_OUT { reinterpret_cast<volatile std::uint32_t*>(mcal::reg::gpio_base + 4u + ((unsigned { my_pin } < 32u) ? 0u : 0xCu)) };
195+
196+
*pGPIO_OUT ^= static_cast<std::uint32_t>(1u << ((unsigned { my_pin } < 32u) ? unsigned { my_pin } : (unsigned { my_pin } - 32u)));
197+
}
198+
}
199+
} // namespace port
200+
} // namespace mcal
201+
202+
#endif // MCAL_PORT_2026_02_13_H

‎ref_app/src/mcal/xtensa_esp32_p4/mcal_reg.h‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -21,6 +21,10 @@
2121
constexpr std::uint32_t clint_mtimecmph { clint_base + static_cast<std::uint32_t>(UINT32_C(0x00004004)) };
2222

2323
constexpr std::uint32_t clic_base { UINT32_C(0x20800000) };
24+
25+
constexpr std::uint32_t gpio_base { UINT32_C(0x500E0000) };
26+
constexpr std::uint32_t lp_io_mux_base { UINT32_C(0x5012B000) };
27+
constexpr std::uint32_t io_mux_base { UINT32_C(0x500E1000) };
2428
}
2529
}
2630

‎ref_app/target.vcxproj‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1287,6 +1287,9 @@
12871287
<ClCompile Include="target\micros\xtensa_esp32_p4\startup\Code\Appli\main_cores.cpp" />
12881288
<ClCompile Include="target\micros\xtensa_esp32_p4\startup\Code\Startup\intvect.c" />
12891289
<ClCompile Include="target\micros\xtensa_esp32_p4\startup\Code\Startup\Startup.c" />
1290+
<ClCompile Include="target\micros\xtensa_esp32_p4\startup\Code\StdLib\StdLib.cpp" />
1291+
<ClCompile Include="target\micros\xtensa_esp32_p4\startup\crt0_init_ram.cpp" />
1292+
<ClCompile Include="target\micros\xtensa_esp32_p4\startup\crt1.cpp" />
12901293
<ClCompile Include="target\micros\xtensa_esp32_s3\startup\crt0.cpp" />
12911294
<ClCompile Include="target\micros\xtensa_esp32_s3\startup\crt0_init_ram.cpp" />
12921295
<ClCompile Include="target\micros\xtensa_esp32_s3\startup\crt1.cpp" />

‎ref_app/target.vcxproj.filters‎

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Original file line numberDiff line numberDiff line change
@@ -358,6 +358,9 @@
358358
<Filter Include="micros\xtensa_esp32_p4\startup\Code\Startup">
359359
<UniqueIdentifier>{17889d6f-9174-40cb-bcad-01e3995207e5}</UniqueIdentifier>
360360
</Filter>
361+
<Filter Include="micros\xtensa_esp32_p4\startup\Code\StdLib">
362+
<UniqueIdentifier>{65c5c603-a019-41d0-8a19-3cadaca7fd3c}</UniqueIdentifier>
363+
</Filter>
361364
</ItemGroup>
362365
<ItemGroup>
363366
<None Include="target\app\make\app_files.gmk">
@@ -1175,6 +1178,15 @@
11751178
<ClCompile Include="target\micros\xtensa_esp32_p4\startup\Code\Appli\main_cores.cpp">
11761179
<Filter>micros\xtensa_esp32_p4\startup\Code\Appli</Filter>
11771180
</ClCompile>
1181+
<ClCompile Include="target\micros\xtensa_esp32_p4\startup\crt1.cpp">
1182+
<Filter>micros\xtensa_esp32_p4\startup</Filter>
1183+
</ClCompile>
1184+
<ClCompile Include="target\micros\xtensa_esp32_p4\startup\crt0_init_ram.cpp">
1185+
<Filter>micros\xtensa_esp32_p4\startup</Filter>
1186+
</ClCompile>
1187+
<ClCompile Include="target\micros\xtensa_esp32_p4\startup\Code\StdLib\StdLib.cpp">
1188+
<Filter>micros\xtensa_esp32_p4\startup\Code\StdLib</Filter>
1189+
</ClCompile>
11781190
</ItemGroup>
11791191
<ItemGroup>
11801192
<Text Include="target\micros\bcm2835_raspi_b\startup\SD_CARD\PiZero\config.txt">

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