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Merge pull request #625 from ckormanyos/cpp_ify_esp32s3_riscv
Fixes #624 via cpp-ify esp32s3 riscv
2 parents 425e2fb + 65a662d commit ffb5997

14 files changed

Lines changed: 159 additions & 39364 deletions

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‎readme.md‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -402,14 +402,14 @@ The Espressif (`target xtensa_esp32_s3`) port for NodeMCU ESP32-S3
402402
features a bare-metal startup _without_ using any of the SDK.
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The bare-metal startup was taken from the work of
404404
[Chalandi/Baremetal_esp32s3_nosdk](https://github.com/Chalandi/Baremetal_esp32s3_nosdk).
405-
The dual-core system first boots core0 which subsequently
406-
starts up core1 and also starts up the RISC-V coprocessor core.
405+
The multicore system first boots core0 which subsequently
406+
starts up core1 and also starts up the RISCV coprocessor core.
407407
Blinky runs in the standard `ref_app`
408408
on core0 toggling `port7` while an endless timer loop on core1
409409
toggles `port6`. The LED ports togle in near unison at $\frac{1}{2}~\text{Hz}$.
410410
Self-procured LEDs and resistors need to be fitted in order to observe
411-
blinky on this particular board. The RISC-V coprocessor
412-
toggles `port17` at a randomly selected frequency of $\sim\frac{2}{3}~\text{Hz}$.
411+
blinky on this particular board. The RISCV coprocessor
412+
toggles `port17` at a randomly chosen, visible frequency.
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414414
The NXP(R) OM13093 LPC11C24 board ARM(R) Cortex(R)-M0+ configuration
415415
called `target lpc11c24` toggles the LED on `port0.8`.

‎ref_app/src/mcal/xtensa_esp32_s3/esp32s3.h‎

Lines changed: 0 additions & 39052 deletions
This file was deleted.

‎ref_app/src/mcal/xtensa_esp32_s3/mcal_cpu.cpp‎

Lines changed: 21 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -14,8 +14,6 @@
1414
#include <mcal_reg.h>
1515
#include <mcal_wdg.h>
1616

17-
#include <esp32s3.h>
18-
1917
extern "C"
2018
{
2119
auto main_c1() -> void;
@@ -89,14 +87,27 @@ auto Mcu_StartCore1() -> void
8987
extern "C"
9088
auto Mcu_StartCoProcessorRiscV() -> void
9189
{
92-
RTC_CNTL->COCPU_CTRL.bit.COCPU_SHUT_RESET_EN = 1;
93-
RTC_CNTL->ULP_CP_TIMER.reg = 0;
94-
RTC_CNTL->COCPU_CTRL.bit.COCPU_CLK_FO = 1;
95-
RTC_CNTL->COCPU_CTRL.bit.COCPU_DONE_FORCE = 1;
96-
RTC_CNTL->COCPU_CTRL.bit.COCPU_CLKGATE_EN = 1;
97-
RTC_CNTL->COCPU_CTRL.bit.COCPU_SEL = 0;
98-
RTC_CNTL->ULP_CP_CTRL.bit.ULP_CP_FORCE_START_TOP = 0;
99-
RTC_CNTL->ULP_CP_TIMER.bit.ULP_CP_SLP_TIMER_EN = 1;
90+
// RTC_CNTL->COCPU_CTRL.bit.COCPU_SHUT_RESET_EN = 1;
91+
mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, mcal::reg::rtc_cntl::cocpu_ctrl, std::uint32_t { UINT8_C(22) }>::bit_set();
92+
93+
// RTC_CNTL->ULP_CP_TIMER.reg = 0;
94+
mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, mcal::reg::rtc_cntl::ulp_cp_timer, std::uint32_t { UINT8_C(0) }>::reg_set();
95+
96+
// RTC_CNTL->COCPU_CTRL.bit.COCPU_CLK_FO = 1;
97+
// RTC_CNTL->COCPU_CTRL.bit.COCPU_DONE_FORCE = 1;
98+
// RTC_CNTL->COCPU_CTRL.bit.COCPU_CLKGATE_EN = 1;
99+
// RTC_CNTL->COCPU_CTRL.bit.COCPU_SEL = 0;
100+
101+
mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, mcal::reg::rtc_cntl::cocpu_ctrl, std::uint32_t { UINT8_C( 0) }>::bit_set();
102+
mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, mcal::reg::rtc_cntl::cocpu_ctrl, std::uint32_t { UINT8_C(24) }>::bit_set();
103+
mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, mcal::reg::rtc_cntl::cocpu_ctrl, std::uint32_t { UINT8_C(27) }>::bit_set();
104+
mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, mcal::reg::rtc_cntl::cocpu_ctrl, std::uint32_t { UINT8_C(23) }>::bit_clr();
105+
106+
// RTC_CNTL->ULP_CP_CTRL.bit.ULP_CP_FORCE_START_TOP = 0;
107+
mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, mcal::reg::rtc_cntl::ulp_cp_ctrl, std::uint32_t { UINT8_C(30) }>::bit_clr();
108+
109+
// RTC_CNTL->ULP_CP_TIMER.bit.ULP_CP_SLP_TIMER_EN = 1;
110+
mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, mcal::reg::rtc_cntl::ulp_cp_timer, std::uint32_t { UINT8_C(31) }>::bit_set();
100111
}
101112

102113
extern "C"

‎ref_app/src/mcal/xtensa_esp32_s3/mcal_port.h‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -25,38 +25,38 @@
2525
static constexpr std::uint32_t bit_pos { bpos };
2626

2727
public:
28-
static void set_direction_output()
28+
static auto set_direction_output() -> void
2929
{
3030
mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, mcal::reg::gpio::out, bit_pos>::bit_clr();
3131
mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, mcal::reg::gpio::out1, bit_pos>::bit_clr();
3232
mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, mcal::reg::gpio::enable_w1ts, bit_pos>::bit_set();
3333
mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, mcal::reg::gpio::enable1_w1ts, bit_pos>::bit_set();
3434
}
3535

36-
static void set_direction_input()
36+
static auto set_direction_input() -> void
3737
{
3838
mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, mcal::reg::gpio::enable_w1ts, bit_pos>::bit_clr();
3939
mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, mcal::reg::gpio::enable1_w1ts, bit_pos>::bit_clr();
4040
mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, mcal::reg::gpio::out, bit_pos>::bit_clr();
4141
mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, mcal::reg::gpio::out1, bit_pos>::bit_clr();
4242
}
4343

44-
static void set_pin_high()
44+
static auto set_pin_high() -> void
4545
{
4646
mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, mcal::reg::gpio::out, bit_pos>::bit_set();
4747
}
4848

49-
static void set_pin_low()
49+
static auto set_pin_low() -> void
5050
{
5151
mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, mcal::reg::gpio::out, bit_pos>::bit_clr();
5252
}
5353

54-
static bool read_input_value()
54+
static auto read_input_value() -> bool
5555
{
5656
return false;
5757
}
5858

59-
static void toggle_pin()
59+
static auto toggle_pin() -> void
6060
{
6161
mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, mcal::reg::gpio::out, bit_pos>::bit_not();
6262
}

‎ref_app/src/mcal/xtensa_esp32_s3_riscv_cop/mcal_port.h‎

Lines changed: 23 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -5,8 +5,8 @@
55
// or copy at http://www.boost.org/LICENSE_1_0.txt)
66
//
77

8-
#ifndef MCAL_PORT_2025_02_22_H
9-
#define MCAL_PORT_2025_02_22_H
8+
#ifndef MCAL_PORT_2025_03_15_H
9+
#define MCAL_PORT_2025_03_15_H
1010

1111
#include <mcal_reg.h>
1212

@@ -16,48 +16,53 @@
1616
{
1717
typedef void config_type;
1818

19-
void init(const config_type*);
19+
inline auto init(const config_type*) -> void { }
2020

2121
template<const std::uint32_t bpos>
2222
class port_pin
2323
{
2424
private:
25-
static constexpr std::uint32_t bit_pos { bpos };
25+
static constexpr std::uint32_t gpio_base { mcal::reg::gpio::rtc_gpio_base };
26+
static constexpr std::uint32_t gpio_pinxx_reg { gpio_base + std::uint32_t { (UINT32_C(10) + bpos) * UINT32_C(4) } };
27+
static constexpr std::uint32_t io_rtc_padxx_reg { gpio_base + std::uint32_t { UINT32_C(0x5C) + (UINT32_C(10) + bpos) * UINT32_C(4) } };
2628

2729
public:
28-
static void set_direction_output()
30+
static auto set_direction_output() -> void
2931
{
30-
mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, mcal::reg::gpio::out, bit_pos>::bit_clr();
31-
mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, mcal::reg::gpio::out1, bit_pos>::bit_clr();
32-
mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, mcal::reg::gpio::enable_w1ts, bit_pos>::bit_set();
33-
mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, mcal::reg::gpio::enable1_w1ts, bit_pos>::bit_set();
32+
//RTC_IO_RTC_PAD17_REG |= (1ul << 19);
33+
//RTC_GPIO_PIN17_REG = 0;
34+
//RTC_GPIO_ENABLE_REG |= (1ul << (10 + 17));
35+
36+
mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, io_rtc_padxx_reg, UINT32_C(19)>::bit_set();
37+
mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, gpio_pinxx_reg, UINT32_C(0)>::reg_set();
38+
mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, mcal::reg::gpio::rtc_gpio_enable_reg, std::uint32_t { UINT32_C(10) + bpos }>::bit_set();
3439
}
3540

36-
static void set_direction_input()
41+
static auto set_direction_input() -> void
3742
{
3843
}
3944

40-
static void set_pin_high()
45+
static auto set_pin_high() -> void
4146
{
42-
mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, mcal::reg::gpio::out, bit_pos>::bit_set();
47+
mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, mcal::reg::gpio::rtc_gpio_out_reg, std::uint32_t { UINT32_C(10) + bpos }>::bit_set();
4348
}
4449

45-
static void set_pin_low()
50+
static auto set_pin_low() -> void
4651
{
47-
mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, mcal::reg::gpio::out, bit_pos>::bit_clr();
52+
mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, mcal::reg::gpio::rtc_gpio_out_reg, std::uint32_t { UINT32_C(10) + bpos }>::bit_set();
4853
}
4954

50-
static bool read_input_value()
55+
static auto read_input_value() -> bool
5156
{
5257
return false;
5358
}
5459

55-
static void toggle_pin()
60+
static auto toggle_pin() -> void
5661
{
57-
mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, mcal::reg::gpio::out, bit_pos>::bit_not();
62+
mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, mcal::reg::gpio::rtc_gpio_out_reg, std::uint32_t { UINT32_C(10) + bpos }>::bit_not();
5863
}
5964
};
6065
}
6166
}
6267

63-
#endif // MCAL_PORT_2025_02_22_H
68+
#endif // MCAL_PORT_2025_03_15_H

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