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Merged
ckormanyos merged 9 commits into from
Mar 14, 2025
Merged

Esp32s3 riscv cop #623

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2084657
Merge branch 'master' into esp32s3_riscv_cop
ckormanyos Mar 9, 2025
e2233da
First preparations riscv core and some cleanup
ckormanyos Mar 9, 2025
e47e69b
Dummy compiler run and stubbed funcs
ckormanyos Mar 9, 2025
4f847ac
Add more files and prelim build in CI
ckormanyos Mar 9, 2025
f7002b0
esp32s3 cleanup and add cop main
ckormanyos Mar 10, 2025
7891c39
Get RISC-V coprocessor booting and running
ckormanyos Mar 14, 2025
2fcb08c
Further cleanup of RISC-V coprocessor
ckormanyos Mar 14, 2025
25f9691
Closer to booting and running
ckormanyos Mar 14, 2025
91122fe
Simplify and repair RISCV boot and run
ckormanyos Mar 14, 2025
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2 changes: 1 addition & 1 deletion .github/workflows/real-time-cpp.yml
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Expand Up @@ -213,7 +213,7 @@ jobs:
strategy:
fail-fast: false
matrix:
suite: [ riscvfe310, wch_ch32v307 ]
suite: [ riscvfe310, wch_ch32v307, xtensa_esp32_s3_riscv_cop ]
steps:
- uses: actions/checkout@v4
with:
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6 changes: 4 additions & 2 deletions readme.md
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Expand Up @@ -403,11 +403,13 @@ features a bare-metal startup _without_ using any of the SDK.
The bare-metal startup was taken from the work of
[Chalandi/Baremetal_esp32s3_nosdk](https://github.com/Chalandi/Baremetal_esp32s3_nosdk).
The dual-core system first boots core0 which subsequently
starts up core1. Blinky runs in the standard `ref_app`
starts up core1 and also starts up the RISC-V coprocessor core.
Blinky runs in the standard `ref_app`
on core0 toggling `port7` while an endless timer loop on core1
toggles `port6`. The LED ports togle in near unison at $\frac{1}{2}~\text{Hz}$.
Self-procured LEDs and resistors need to be fitted in order to observe
blinky on this particular board.
blinky on this particular board. The RISC-V coprocessor
toggles `port17` at a randomly selected frequency of $\sim\frac{2}{3}~\text{Hz}$.

The NXP(R) OM13093 LPC11C24 board ARM(R) Cortex(R)-M0+ configuration
called `target lpc11c24` toggles the LED on `port0.8`.
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4 changes: 4 additions & 0 deletions ref_app/ref_app.sln
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Expand Up @@ -70,6 +70,7 @@ Global
target wch_ch32v307_llvm|x64 = target wch_ch32v307_llvm|x64
target wch_ch32v307|x64 = target wch_ch32v307|x64
target x86_64-w64-mingw32|x64 = target x86_64-w64-mingw32|x64
target xtensa_esp32_s3_riscv_cop|x64 = target xtensa_esp32_s3_riscv_cop|x64
target xtensa_esp32_s3|x64 = target xtensa_esp32_s3|x64
target xtensa32|x64 = target xtensa32|x64
EndGlobalSection
Expand Down Expand Up @@ -102,6 +103,7 @@ Global
{C8B59726-9319-45C3-8F11-F9F388FB6A2C}.target wch_ch32v307_llvm|x64.ActiveCfg = Release|x64
{C8B59726-9319-45C3-8F11-F9F388FB6A2C}.target wch_ch32v307|x64.ActiveCfg = Release|x64
{C8B59726-9319-45C3-8F11-F9F388FB6A2C}.target x86_64-w64-mingw32|x64.ActiveCfg = Release|x64
{C8B59726-9319-45C3-8F11-F9F388FB6A2C}.target xtensa_esp32_s3_riscv_cop|x64.ActiveCfg = Release|x64
{C8B59726-9319-45C3-8F11-F9F388FB6A2C}.target xtensa_esp32_s3|x64.ActiveCfg = Release|x64
{C8B59726-9319-45C3-8F11-F9F388FB6A2C}.target xtensa32|x64.ActiveCfg = Release|x64
{30CE370B-40F3-4BCD-8986-64AAFF8971BD}.Debug|x64.ActiveCfg = target avr|x64
Expand Down Expand Up @@ -154,6 +156,8 @@ Global
{30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target wch_ch32v307|x64.Build.0 = target wch_ch32v307|x64
{30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target x86_64-w64-mingw32|x64.ActiveCfg = target x86_64-w64-mingw32|x64
{30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target x86_64-w64-mingw32|x64.Build.0 = target x86_64-w64-mingw32|x64
{30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target xtensa_esp32_s3_riscv_cop|x64.ActiveCfg = target xtensa_esp32_s3_riscv_cop|x64
{30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target xtensa_esp32_s3_riscv_cop|x64.Build.0 = target xtensa_esp32_s3_riscv_cop|x64
{30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target xtensa_esp32_s3|x64.ActiveCfg = target xtensa_esp32_s3|x64
{30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target xtensa_esp32_s3|x64.Build.0 = target xtensa_esp32_s3|x64
{30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target xtensa32|x64.ActiveCfg = target xtensa32|x64
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96 changes: 96 additions & 0 deletions ref_app/ref_app.vcxproj
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Expand Up @@ -1317,6 +1317,46 @@
<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Debug|x64'">true</ExcludedFromBuild>
<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Release|x64'">true</ExcludedFromBuild>
</ClCompile>
<ClCompile Include="src\mcal\xtensa_esp32_s3_riscv_cop\mcal_cpu.cpp">
<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Debug|x64'">true</ExcludedFromBuild>
<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Release|x64'">true</ExcludedFromBuild>
</ClCompile>
<ClCompile Include="src\mcal\xtensa_esp32_s3_riscv_cop\mcal_eep.cpp">
<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Debug|x64'">true</ExcludedFromBuild>
<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Release|x64'">true</ExcludedFromBuild>
</ClCompile>
<ClCompile Include="src\mcal\xtensa_esp32_s3_riscv_cop\mcal_gpt.cpp">
<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Debug|x64'">true</ExcludedFromBuild>
<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Release|x64'">true</ExcludedFromBuild>
</ClCompile>
<ClCompile Include="src\mcal\xtensa_esp32_s3_riscv_cop\mcal_irq.cpp">
<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Debug|x64'">true</ExcludedFromBuild>
<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Release|x64'">true</ExcludedFromBuild>
</ClCompile>
<ClCompile Include="src\mcal\xtensa_esp32_s3_riscv_cop\mcal_led.cpp">
<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Debug|x64'">true</ExcludedFromBuild>
<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Release|x64'">true</ExcludedFromBuild>
</ClCompile>
<ClCompile Include="src\mcal\xtensa_esp32_s3_riscv_cop\mcal_osc.cpp">
<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Debug|x64'">true</ExcludedFromBuild>
<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Release|x64'">true</ExcludedFromBuild>
</ClCompile>
<ClCompile Include="src\mcal\xtensa_esp32_s3_riscv_cop\mcal_port.cpp">
<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Debug|x64'">true</ExcludedFromBuild>
<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Release|x64'">true</ExcludedFromBuild>
</ClCompile>
<ClCompile Include="src\mcal\xtensa_esp32_s3_riscv_cop\mcal_pwm.cpp">
<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Debug|x64'">true</ExcludedFromBuild>
<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Release|x64'">true</ExcludedFromBuild>
</ClCompile>
<ClCompile Include="src\mcal\xtensa_esp32_s3_riscv_cop\mcal_spi.cpp">
<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Debug|x64'">true</ExcludedFromBuild>
<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Release|x64'">true</ExcludedFromBuild>
</ClCompile>
<ClCompile Include="src\mcal\xtensa_esp32_s3_riscv_cop\mcal_wdg.cpp">
<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Debug|x64'">true</ExcludedFromBuild>
<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Release|x64'">true</ExcludedFromBuild>
</ClCompile>
<ClCompile Include="src\os\os.cpp" />
<ClCompile Include="src\sys\idle\sys_idle.cpp" />
<ClCompile Include="src\sys\mon\sys_mon.cpp" />
Expand Down Expand Up @@ -2956,6 +2996,62 @@
<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Debug|x64'">true</ExcludedFromBuild>
<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Release|x64'">true</ExcludedFromBuild>
</ClInclude>
<ClInclude Include="src\mcal\xtensa_esp32_s3_riscv_cop\mcal_benchmark.h">
<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Debug|x64'">true</ExcludedFromBuild>
<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Release|x64'">true</ExcludedFromBuild>
</ClInclude>
<ClInclude Include="src\mcal\xtensa_esp32_s3_riscv_cop\mcal_cpu.h">
<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Debug|x64'">true</ExcludedFromBuild>
<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Release|x64'">true</ExcludedFromBuild>
</ClInclude>
<ClInclude Include="src\mcal\xtensa_esp32_s3_riscv_cop\mcal_eep.h">
<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Debug|x64'">true</ExcludedFromBuild>
<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Release|x64'">true</ExcludedFromBuild>
</ClInclude>
<ClInclude Include="src\mcal\xtensa_esp32_s3_riscv_cop\mcal_gpt.h">
<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Debug|x64'">true</ExcludedFromBuild>
<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Release|x64'">true</ExcludedFromBuild>
</ClInclude>
<ClInclude Include="src\mcal\xtensa_esp32_s3_riscv_cop\mcal_irq.h">
<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Debug|x64'">true</ExcludedFromBuild>
<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Release|x64'">true</ExcludedFromBuild>
</ClInclude>
<ClInclude Include="src\mcal\xtensa_esp32_s3_riscv_cop\mcal_led.h">
<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Debug|x64'">true</ExcludedFromBuild>
<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Release|x64'">true</ExcludedFromBuild>
</ClInclude>
<ClInclude Include="src\mcal\xtensa_esp32_s3_riscv_cop\mcal_memory_progmem.h">
<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Debug|x64'">true</ExcludedFromBuild>
<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Release|x64'">true</ExcludedFromBuild>
</ClInclude>
<ClInclude Include="src\mcal\xtensa_esp32_s3_riscv_cop\mcal_osc.h">
<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Debug|x64'">true</ExcludedFromBuild>
<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Release|x64'">true</ExcludedFromBuild>
</ClInclude>
<ClInclude Include="src\mcal\xtensa_esp32_s3_riscv_cop\mcal_port.h">
<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Debug|x64'">true</ExcludedFromBuild>
<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Release|x64'">true</ExcludedFromBuild>
</ClInclude>
<ClInclude Include="src\mcal\xtensa_esp32_s3_riscv_cop\mcal_pwm.h">
<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Debug|x64'">true</ExcludedFromBuild>
<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Release|x64'">true</ExcludedFromBuild>
</ClInclude>
<ClInclude Include="src\mcal\xtensa_esp32_s3_riscv_cop\mcal_reg.h">
<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Debug|x64'">true</ExcludedFromBuild>
<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Release|x64'">true</ExcludedFromBuild>
</ClInclude>
<ClInclude Include="src\mcal\xtensa_esp32_s3_riscv_cop\mcal_ser.h">
<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Debug|x64'">true</ExcludedFromBuild>
<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Release|x64'">true</ExcludedFromBuild>
</ClInclude>
<ClInclude Include="src\mcal\xtensa_esp32_s3_riscv_cop\mcal_spi.h">
<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Debug|x64'">true</ExcludedFromBuild>
<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Release|x64'">true</ExcludedFromBuild>
</ClInclude>
<ClInclude Include="src\mcal\xtensa_esp32_s3_riscv_cop\mcal_wdg.h">
<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Debug|x64'">true</ExcludedFromBuild>
<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Release|x64'">true</ExcludedFromBuild>
</ClInclude>
<ClInclude Include="src\mcal_lcd\mcal_lcd_base.h" />
<ClInclude Include="src\mcal_lcd\mcal_lcd_buffered_instance.h" />
<ClInclude Include="src\mcal_lcd\mcal_lcd_console.h" />
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75 changes: 75 additions & 0 deletions ref_app/ref_app.vcxproj.filters
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Expand Up @@ -230,6 +230,9 @@
<Filter Include="src\mcal\xtensa_esp32_s3">
<UniqueIdentifier>{66987aaa-84ee-4911-aa5c-efd3108b55f0}</UniqueIdentifier>
</Filter>
<Filter Include="src\mcal\xtensa_esp32_s3_riscv_cop">
<UniqueIdentifier>{fb4f50c3-b34c-4150-ae05-342dc3721eed}</UniqueIdentifier>
</Filter>
</ItemGroup>
<ItemGroup>
<ClCompile Include="src\app\led\app_led.cpp">
Expand Down Expand Up @@ -1189,6 +1192,36 @@
<ClCompile Include="src\mcal\xtensa_esp32_s3\mcal_wdg.cpp">
<Filter>src\mcal\xtensa_esp32_s3</Filter>
</ClCompile>
<ClCompile Include="src\mcal\xtensa_esp32_s3_riscv_cop\mcal_gpt.cpp">
<Filter>src\mcal\xtensa_esp32_s3_riscv_cop</Filter>
</ClCompile>
<ClCompile Include="src\mcal\xtensa_esp32_s3_riscv_cop\mcal_irq.cpp">
<Filter>src\mcal\xtensa_esp32_s3_riscv_cop</Filter>
</ClCompile>
<ClCompile Include="src\mcal\xtensa_esp32_s3_riscv_cop\mcal_led.cpp">
<Filter>src\mcal\xtensa_esp32_s3_riscv_cop</Filter>
</ClCompile>
<ClCompile Include="src\mcal\xtensa_esp32_s3_riscv_cop\mcal_osc.cpp">
<Filter>src\mcal\xtensa_esp32_s3_riscv_cop</Filter>
</ClCompile>
<ClCompile Include="src\mcal\xtensa_esp32_s3_riscv_cop\mcal_port.cpp">
<Filter>src\mcal\xtensa_esp32_s3_riscv_cop</Filter>
</ClCompile>
<ClCompile Include="src\mcal\xtensa_esp32_s3_riscv_cop\mcal_pwm.cpp">
<Filter>src\mcal\xtensa_esp32_s3_riscv_cop</Filter>
</ClCompile>
<ClCompile Include="src\mcal\xtensa_esp32_s3_riscv_cop\mcal_spi.cpp">
<Filter>src\mcal\xtensa_esp32_s3_riscv_cop</Filter>
</ClCompile>
<ClCompile Include="src\mcal\xtensa_esp32_s3_riscv_cop\mcal_wdg.cpp">
<Filter>src\mcal\xtensa_esp32_s3_riscv_cop</Filter>
</ClCompile>
<ClCompile Include="src\mcal\xtensa_esp32_s3_riscv_cop\mcal_cpu.cpp">
<Filter>src\mcal\xtensa_esp32_s3_riscv_cop</Filter>
</ClCompile>
<ClCompile Include="src\mcal\xtensa_esp32_s3_riscv_cop\mcal_eep.cpp">
<Filter>src\mcal\xtensa_esp32_s3_riscv_cop</Filter>
</ClCompile>
</ItemGroup>
<ItemGroup>
<ClInclude Include="src\math\calculus\derivative.h">
Expand Down Expand Up @@ -2751,6 +2784,48 @@
<ClInclude Include="src\mcal_led\mcal_led_dummy.h">
<Filter>src\mcal_led</Filter>
</ClInclude>
<ClInclude Include="src\mcal\xtensa_esp32_s3_riscv_cop\mcal_gpt.h">
<Filter>src\mcal\xtensa_esp32_s3_riscv_cop</Filter>
</ClInclude>
<ClInclude Include="src\mcal\xtensa_esp32_s3_riscv_cop\mcal_irq.h">
<Filter>src\mcal\xtensa_esp32_s3_riscv_cop</Filter>
</ClInclude>
<ClInclude Include="src\mcal\xtensa_esp32_s3_riscv_cop\mcal_led.h">
<Filter>src\mcal\xtensa_esp32_s3_riscv_cop</Filter>
</ClInclude>
<ClInclude Include="src\mcal\xtensa_esp32_s3_riscv_cop\mcal_memory_progmem.h">
<Filter>src\mcal\xtensa_esp32_s3_riscv_cop</Filter>
</ClInclude>
<ClInclude Include="src\mcal\xtensa_esp32_s3_riscv_cop\mcal_osc.h">
<Filter>src\mcal\xtensa_esp32_s3_riscv_cop</Filter>
</ClInclude>
<ClInclude Include="src\mcal\xtensa_esp32_s3_riscv_cop\mcal_port.h">
<Filter>src\mcal\xtensa_esp32_s3_riscv_cop</Filter>
</ClInclude>
<ClInclude Include="src\mcal\xtensa_esp32_s3_riscv_cop\mcal_pwm.h">
<Filter>src\mcal\xtensa_esp32_s3_riscv_cop</Filter>
</ClInclude>
<ClInclude Include="src\mcal\xtensa_esp32_s3_riscv_cop\mcal_reg.h">
<Filter>src\mcal\xtensa_esp32_s3_riscv_cop</Filter>
</ClInclude>
<ClInclude Include="src\mcal\xtensa_esp32_s3_riscv_cop\mcal_ser.h">
<Filter>src\mcal\xtensa_esp32_s3_riscv_cop</Filter>
</ClInclude>
<ClInclude Include="src\mcal\xtensa_esp32_s3_riscv_cop\mcal_spi.h">
<Filter>src\mcal\xtensa_esp32_s3_riscv_cop</Filter>
</ClInclude>
<ClInclude Include="src\mcal\xtensa_esp32_s3_riscv_cop\mcal_wdg.h">
<Filter>src\mcal\xtensa_esp32_s3_riscv_cop</Filter>
</ClInclude>
<ClInclude Include="src\mcal\xtensa_esp32_s3_riscv_cop\mcal_benchmark.h">
<Filter>src\mcal\xtensa_esp32_s3_riscv_cop</Filter>
</ClInclude>
<ClInclude Include="src\mcal\xtensa_esp32_s3_riscv_cop\mcal_cpu.h">
<Filter>src\mcal\xtensa_esp32_s3_riscv_cop</Filter>
</ClInclude>
<ClInclude Include="src\mcal\xtensa_esp32_s3_riscv_cop\mcal_eep.h">
<Filter>src\mcal\xtensa_esp32_s3_riscv_cop</Filter>
</ClInclude>
</ItemGroup>
<ItemGroup>
<None Include="src\util\STL\algorithm">
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