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Merged
ckormanyos merged 6 commits into from
Mar 15, 2025
Merged

Cpp-ify esp32s3 riscv #625

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1a57963
[ci skip] Update and repair docs
ckormanyos Mar 14, 2025
0c773db
[ci skip] Update readme.md
ckormanyos Mar 14, 2025
e6a71d1
[ci skip] Update readme.md
ckormanyos Mar 14, 2025
84d07e0
[ci skip] Update readme.md
ckormanyos Mar 14, 2025
533f9aa
Update readme.md
ckormanyos Mar 14, 2025
65a662d
Preliminary C++-ificaion esp32s3 and riscv cop
ckormanyos Mar 15, 2025
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8 changes: 4 additions & 4 deletions readme.md
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Expand Up @@ -402,14 +402,14 @@ The Espressif (`target xtensa_esp32_s3`) port for NodeMCU ESP32-S3
features a bare-metal startup _without_ using any of the SDK.
The bare-metal startup was taken from the work of
[Chalandi/Baremetal_esp32s3_nosdk](https://github.com/Chalandi/Baremetal_esp32s3_nosdk).
The dual-core system first boots core0 which subsequently
starts up core1 and also starts up the RISC-V coprocessor core.
The multicore system first boots core0 which subsequently
starts up core1 and also starts up the RISCV coprocessor core.
Blinky runs in the standard `ref_app`
on core0 toggling `port7` while an endless timer loop on core1
toggles `port6`. The LED ports togle in near unison at $\frac{1}{2}~\text{Hz}$.
Self-procured LEDs and resistors need to be fitted in order to observe
blinky on this particular board. The RISC-V coprocessor
toggles `port17` at a randomly selected frequency of $\sim\frac{2}{3}~\text{Hz}$.
blinky on this particular board. The RISCV coprocessor
toggles `port17` at a randomly chosen, visible frequency.

The NXP(R) OM13093 LPC11C24 board ARM(R) Cortex(R)-M0+ configuration
called `target lpc11c24` toggles the LED on `port0.8`.
Expand Down
39,052 changes: 0 additions & 39,052 deletions ref_app/src/mcal/xtensa_esp32_s3/esp32s3.h
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This file was deleted.

31 changes: 21 additions & 10 deletions ref_app/src/mcal/xtensa_esp32_s3/mcal_cpu.cpp
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Expand Up @@ -14,8 +14,6 @@
#include <mcal_reg.h>
#include <mcal_wdg.h>

#include <esp32s3.h>

extern "C"
{
auto main_c1() -> void;
Expand Down Expand Up @@ -89,14 +87,27 @@ auto Mcu_StartCore1() -> void
extern "C"
auto Mcu_StartCoProcessorRiscV() -> void
{
RTC_CNTL->COCPU_CTRL.bit.COCPU_SHUT_RESET_EN = 1;
RTC_CNTL->ULP_CP_TIMER.reg = 0;
RTC_CNTL->COCPU_CTRL.bit.COCPU_CLK_FO = 1;
RTC_CNTL->COCPU_CTRL.bit.COCPU_DONE_FORCE = 1;
RTC_CNTL->COCPU_CTRL.bit.COCPU_CLKGATE_EN = 1;
RTC_CNTL->COCPU_CTRL.bit.COCPU_SEL = 0;
RTC_CNTL->ULP_CP_CTRL.bit.ULP_CP_FORCE_START_TOP = 0;
RTC_CNTL->ULP_CP_TIMER.bit.ULP_CP_SLP_TIMER_EN = 1;
// RTC_CNTL->COCPU_CTRL.bit.COCPU_SHUT_RESET_EN = 1;
mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, mcal::reg::rtc_cntl::cocpu_ctrl, std::uint32_t { UINT8_C(22) }>::bit_set();

// RTC_CNTL->ULP_CP_TIMER.reg = 0;
mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, mcal::reg::rtc_cntl::ulp_cp_timer, std::uint32_t { UINT8_C(0) }>::reg_set();

// RTC_CNTL->COCPU_CTRL.bit.COCPU_CLK_FO = 1;
// RTC_CNTL->COCPU_CTRL.bit.COCPU_DONE_FORCE = 1;
// RTC_CNTL->COCPU_CTRL.bit.COCPU_CLKGATE_EN = 1;
// RTC_CNTL->COCPU_CTRL.bit.COCPU_SEL = 0;

mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, mcal::reg::rtc_cntl::cocpu_ctrl, std::uint32_t { UINT8_C( 0) }>::bit_set();
mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, mcal::reg::rtc_cntl::cocpu_ctrl, std::uint32_t { UINT8_C(24) }>::bit_set();
mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, mcal::reg::rtc_cntl::cocpu_ctrl, std::uint32_t { UINT8_C(27) }>::bit_set();
mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, mcal::reg::rtc_cntl::cocpu_ctrl, std::uint32_t { UINT8_C(23) }>::bit_clr();

// RTC_CNTL->ULP_CP_CTRL.bit.ULP_CP_FORCE_START_TOP = 0;
mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, mcal::reg::rtc_cntl::ulp_cp_ctrl, std::uint32_t { UINT8_C(30) }>::bit_clr();

// RTC_CNTL->ULP_CP_TIMER.bit.ULP_CP_SLP_TIMER_EN = 1;
mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, mcal::reg::rtc_cntl::ulp_cp_timer, std::uint32_t { UINT8_C(31) }>::bit_set();
}

extern "C"
Expand Down
12 changes: 6 additions & 6 deletions ref_app/src/mcal/xtensa_esp32_s3/mcal_port.h
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Expand Up @@ -25,38 +25,38 @@
static constexpr std::uint32_t bit_pos { bpos };

public:
static void set_direction_output()
static auto set_direction_output() -> void
{
mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, mcal::reg::gpio::out, bit_pos>::bit_clr();
mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, mcal::reg::gpio::out1, bit_pos>::bit_clr();
mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, mcal::reg::gpio::enable_w1ts, bit_pos>::bit_set();
mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, mcal::reg::gpio::enable1_w1ts, bit_pos>::bit_set();
}

static void set_direction_input()
static auto set_direction_input() -> void
{
mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, mcal::reg::gpio::enable_w1ts, bit_pos>::bit_clr();
mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, mcal::reg::gpio::enable1_w1ts, bit_pos>::bit_clr();
mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, mcal::reg::gpio::out, bit_pos>::bit_clr();
mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, mcal::reg::gpio::out1, bit_pos>::bit_clr();
}

static void set_pin_high()
static auto set_pin_high() -> void
{
mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, mcal::reg::gpio::out, bit_pos>::bit_set();
}

static void set_pin_low()
static auto set_pin_low() -> void
{
mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, mcal::reg::gpio::out, bit_pos>::bit_clr();
}

static bool read_input_value()
static auto read_input_value() -> bool
{
return false;
}

static void toggle_pin()
static auto toggle_pin() -> void
{
mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, mcal::reg::gpio::out, bit_pos>::bit_not();
}
Expand Down
41 changes: 23 additions & 18 deletions ref_app/src/mcal/xtensa_esp32_s3_riscv_cop/mcal_port.h
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Expand Up @@ -5,8 +5,8 @@
// or copy at http://www.boost.org/LICENSE_1_0.txt)
//

#ifndef MCAL_PORT_2025_02_22_H
#define MCAL_PORT_2025_02_22_H
#ifndef MCAL_PORT_2025_03_15_H
#define MCAL_PORT_2025_03_15_H

#include <mcal_reg.h>

Expand All @@ -16,48 +16,53 @@
{
typedef void config_type;

void init(const config_type*);
inline auto init(const config_type*) -> void { }

template<const std::uint32_t bpos>
class port_pin
{
private:
static constexpr std::uint32_t bit_pos { bpos };
static constexpr std::uint32_t gpio_base { mcal::reg::gpio::rtc_gpio_base };
static constexpr std::uint32_t gpio_pinxx_reg { gpio_base + std::uint32_t { (UINT32_C(10) + bpos) * UINT32_C(4) } };
static constexpr std::uint32_t io_rtc_padxx_reg { gpio_base + std::uint32_t { UINT32_C(0x5C) + (UINT32_C(10) + bpos) * UINT32_C(4) } };

public:
static void set_direction_output()
static auto set_direction_output() -> void
{
mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, mcal::reg::gpio::out, bit_pos>::bit_clr();
mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, mcal::reg::gpio::out1, bit_pos>::bit_clr();
mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, mcal::reg::gpio::enable_w1ts, bit_pos>::bit_set();
mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, mcal::reg::gpio::enable1_w1ts, bit_pos>::bit_set();
//RTC_IO_RTC_PAD17_REG |= (1ul << 19);
//RTC_GPIO_PIN17_REG = 0;
//RTC_GPIO_ENABLE_REG |= (1ul << (10 + 17));

mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, io_rtc_padxx_reg, UINT32_C(19)>::bit_set();
mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, gpio_pinxx_reg, UINT32_C(0)>::reg_set();
mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, mcal::reg::gpio::rtc_gpio_enable_reg, std::uint32_t { UINT32_C(10) + bpos }>::bit_set();
}

static void set_direction_input()
static auto set_direction_input() -> void
{
}

static void set_pin_high()
static auto set_pin_high() -> void
{
mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, mcal::reg::gpio::out, bit_pos>::bit_set();
mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, mcal::reg::gpio::rtc_gpio_out_reg, std::uint32_t { UINT32_C(10) + bpos }>::bit_set();
}

static void set_pin_low()
static auto set_pin_low() -> void
{
mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, mcal::reg::gpio::out, bit_pos>::bit_clr();
mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, mcal::reg::gpio::rtc_gpio_out_reg, std::uint32_t { UINT32_C(10) + bpos }>::bit_set();
}

static bool read_input_value()
static auto read_input_value() -> bool
{
return false;
}

static void toggle_pin()
static auto toggle_pin() -> void
{
mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, mcal::reg::gpio::out, bit_pos>::bit_not();
mcal::reg::reg_access_static<std::uint32_t, std::uint32_t, mcal::reg::gpio::rtc_gpio_out_reg, std::uint32_t { UINT32_C(10) + bpos }>::bit_not();
}
};
}
}

#endif // MCAL_PORT_2025_02_22_H
#endif // MCAL_PORT_2025_03_15_H
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