BL602 startup and get benches running

ref_app/src/app/benchmark/readme.md

@@ -81,16 +81,17 @@ template class.
 A very wide range of microcontroller performance classes is shown in the following table.
 The benchmark used is a ${\sim}100$ decimal digit AGM $\pi$ calculation.
 
-| Target             |  runtime $[ms]$ |  relative  |
-|--------------------|-----------------|------------|
-| `am6254_soc`       |  0.37           |    1.0     |
-| `am335x`           |  1.5            |    4.1     |
-| `stm32f446`        |  5.1            |    14      |
-| `rpi_pico2_rp2350` |  6.3            |    17      |
-| `wch_ch32v307`     |  8.0            |    22      |
-| `xtensa_esp32_s3`  |  9.1            |    25      |
-| `rpi_pico_rp2040`  |  19             |    51      |
-| `avr`              |  410            |   1100     |
+| Target                    |  runtime $[ms]$ |  relative  |
+|---------------------------|-----------------|------------|
+| `am6254_soc`              |  0.37           |    1.0     |
+| `am335x`                  |  1.5            |    4.1     |
+| `stm32f446`               |  5.1            |    14      |
+| `rpi_pico2_rp2350`        |  6.3            |    17      |
+| `wch_ch32v307`            |  8.0            |    22      |
+| `xtensa_esp32_s3`         |  9.1            |    25      |
+| `bl602_sifive_e24_riscv`  |  11             |    30      |
+| `rpi_pico_rp2040`         |  19             |    51      |
+| `avr`                     |  410            |   1100     |
 
 There are strikingly differing performance classes
 for the $8$-bit MICROCHIP(R) AVR controller of the ARDUINO
@@ -113,7 +114,9 @@ with a result of $5.1~{\text{ms}}$.
 
 The $32$-bit RISC-V controller (having a novel _open-source_ core)
 on the `wch_ch32v307` board boasts a quite respectable
-time of $8.0~{\text{ms}}$.
+time of $8.0~{\text{ms}}$. A different $32$-bit RISC-V controller
+on target `bl602_sifive_e24_riscv` has similar performance,
+running the benchmark in about $11~{\text{ms}}$.
 
 Running on only one core (core0) of the $32$-bit
 controller of the `xtensa_esp32_s3` board results in

ref_app/src/mcal/bl602_sifive_e24_riscv/mcal_port.h

@@ -73,12 +73,12 @@
 
         static auto set_pin_high() noexcept -> void
         {
-          // Not yet implemented.
+          mcal::reg::reg_access_static<std::uintptr_t, std::uint32_t, mcal::reg::gpio_cfgctl32, port_index>::bit_set();
         }
 
         static auto set_pin_low() noexcept -> void
         {
-          // Not yet implemented.
+          mcal::reg::reg_access_static<std::uintptr_t, std::uint32_t, mcal::reg::gpio_cfgctl32, port_index>::bit_clr();
         }
 
         static auto read_input_value() noexcept -> bool

ref_app/target.vcxproj

@@ -1132,8 +1132,10 @@
     <ClCompile Include="target\micros\bcm2835_raspi_b\startup\crt0_init_ram.cpp" />
     <ClCompile Include="target\micros\bcm2835_raspi_b\startup\crt1.cpp" />
     <ClCompile Include="Target\Micros\AVR\Startup\int_vect.cpp" />
+    <ClCompile Include="target\micros\bl602_sifive_e24_riscv\startup\crt0.cpp" />
+    <ClCompile Include="target\micros\bl602_sifive_e24_riscv\startup\crt0_init_ram.cpp" />
+    <ClCompile Include="target\micros\bl602_sifive_e24_riscv\startup\crt1.cpp" />
     <ClCompile Include="target\micros\bl602_sifive_e24_riscv\startup\intvect.c" />
-    <ClCompile Include="target\micros\bl602_sifive_e24_riscv\startup\Startup.c" />
     <ClCompile Include="target\micros\lpc11c24\startup\crt0.cpp" />
     <ClCompile Include="target\micros\lpc11c24\startup\crt0_init_ram.cpp" />
     <ClCompile Include="target\micros\lpc11c24\startup\crt1.cpp" />

ref_app/target.vcxproj.filters

@@ -1094,7 +1094,13 @@
     <ClCompile Include="target\micros\bl602_sifive_e24_riscv\startup\intvect.c">
       <Filter>micros\bl602_sifive_e24_riscv\startup</Filter>
     </ClCompile>
-    <ClCompile Include="target\micros\bl602_sifive_e24_riscv\startup\Startup.c">
+    <ClCompile Include="target\micros\bl602_sifive_e24_riscv\startup\crt1.cpp">
+      <Filter>micros\bl602_sifive_e24_riscv\startup</Filter>
+    </ClCompile>
+    <ClCompile Include="target\micros\bl602_sifive_e24_riscv\startup\crt0.cpp">
+      <Filter>micros\bl602_sifive_e24_riscv\startup</Filter>
+    </ClCompile>
+    <ClCompile Include="target\micros\bl602_sifive_e24_riscv\startup\crt0_init_ram.cpp">
       <Filter>micros\bl602_sifive_e24_riscv\startup</Filter>
     </ClCompile>
   </ItemGroup>

ref_app/target/micros/bl602_sifive_e24_riscv/make/bl602_sifive_e24_riscv.ld

@@ -15,6 +15,8 @@
 
 ******************************************************************************************/
 
+INPUT(libc.a libm.a libgcc.a)
+
 /******************************************************************************************
  ELF Entrypoint
 ******************************************************************************************/
@@ -23,137 +25,164 @@ ENTRY(_start)
 /******************************************************************************************
  Globals
 ******************************************************************************************/
-__FLASH_START_ADDRESS = 0x23000000;
-__FLASH_SIZE          = 2M;
 
-__ITCM_START_ADDRESS = 0x22008000;
-__ITCM_SIZE          = 48K;
+__STACK_SIZE = 4K;
 
-__DTCM_START_ADDRESS = 0x42014000;
-__DTCM_SIZE          = 48K;
+__RAM_START_ADDRESS = 0x42020000;
+__RAM_SIZE =  64K - __STACK_SIZE;
 
-__STACK_START_ADDRESS = 0x42020000;
-__STACK_SIZE = 1K;
+__STACK_START_ADDRESS = __RAM_START_ADDRESS + __RAM_SIZE;
 
-__RAM_START_ADDRESS = 0x42020000 + __STACK_SIZE;
-__RAM_SIZE =  64K - __STACK_SIZE;
+__ROM_START_ADDRESS = 0x23000000;
 
 /******************************************************************************************
  Memory configuration
 ******************************************************************************************/
 
 MEMORY
 {
-  FLASH(rx)   : ORIGIN = __FLASH_START_ADDRESS, LENGTH = __FLASH_SIZE
-  ITCM(rx)    : ORIGIN = __ITCM_START_ADDRESS,  LENGTH = __ITCM_SIZE
-  DTCM(rx)    : ORIGIN = __DTCM_START_ADDRESS,  LENGTH = __DTCM_SIZE
-  STACK(rw)   : ORIGIN = __STACK_START_ADDRESS, LENGTH = __STACK_SIZE
-  RAM(rwx)    : ORIGIN = __RAM_START_ADDRESS,   LENGTH = __RAM_SIZE
+  BOOT(rx)    : ORIGIN = 0x23000000,                 LENGTH = 0x100
+  START(rx)   : ORIGIN = 0x23000100,                 LENGTH = 0x300
+  ROM(rx)     : ORIGIN = 0x23000400,                 LENGTH = 256K - 0x400
+  SRAM(rwx)   : ORIGIN = __RAM_START_ADDRESS,        LENGTH = 32K
+  RAM(rwx)    : ORIGIN = __RAM_START_ADDRESS + 32K,  LENGTH = __RAM_SIZE - 32K
+  STACK(rw)   : ORIGIN = __STACK_START_ADDRESS,      LENGTH = __STACK_SIZE
 }
 
 /******************************************************************************************
  Sections definition
 ******************************************************************************************/
 SECTIONS
 {
-  /* Program code (text) */
-  .text : ALIGN(4)
+  . = __ROM_START_ADDRESS;
+
+  .boot : ALIGN(0x10)
   {
-    PROVIDE(__CODE_BASE_ADDRESS = .);
     *(.boot)
-    *(.text)
-    . = ALIGN(4);
-  } > FLASH
+    . = ALIGN(0x10);
+    *(.boot*)
+    . = ALIGN(0x10);
+  } > BOOT = 0x5555
 
-  /* Read-only data (.rodata) */
-  .rodata : ALIGN(4)
+  .startup : ALIGN(0x10)
   {
-    PROVIDE(__RODATA_BASE_ADDRESS = .);
-    *(.rodata)
-  } > FLASH
+    *(.startup)
+    . = ALIGN(0x10);
+    *(.startup*)
+    . = ALIGN(0x10);
+  } > START = 0x5555
 
- /* Section for constructors */
-  .ctors : ALIGN(4)
+  /* Program code (text) */
+  .text : ALIGN(0x100)
   {
-    PROVIDE(__CTOR_LIST__  = .);
-    KEEP (*(SORT(.ctors.*)))
-    KEEP (*(.ctors))
-    KEEP (*(SORT(.init_array.*)))
-    KEEP (*(.init_array))
-    LONG(-1) ;
-    PROVIDE(__CTOR_END__  = .);
+    _ctors_begin = .;
+    KEEP(*(SORT(.init_array.*)))
+    KEEP(*(.init_array*))
+    _ctors_end = .;
+    *(.progmem*)
     . = ALIGN(4);
-  }  > FLASH
-
+    *(.text)
+    . = ALIGN(4);
+    *(.text*)
+    . = ALIGN(4);
+    *(.rodata)
+    . = ALIGN(4);
+    *(.rodata*)
+    . = ALIGN(4);
+    *(.srodata)
+    . = ALIGN(4);
+    *(.srodata*)
+    . = ALIGN(4);
+    *(.glue_7)
+    . = ALIGN(4);
+    *(.glue_7t)
+    . = ALIGN(4);
+  } > ROM
 
-  /* Section for destructors */
-  .dtors : ALIGN(4)
+  .riscv.extab :
   {
-    PROVIDE(__DTOR_LIST__  = .);
-    KEEP (*(SORT(.dtors.*)))
-    KEEP (*(.dtors))
-    KEEP (*(SORT(.fini_array.*)))
-    KEEP (*(.fini_array))
-    LONG(-1) ;
-    PROVIDE(__DTOR_END__  = .);
-    . = ALIGN(4);
-  } > FLASH
-
-  /* Runtime clear table */
-  .clear_sec : ALIGN(4)
+    . = ALIGN(4);
+    *(.riscv.extab)
+    *(.gnu.linkonce.riscvextab.*)
+    . = ALIGN(4);
+  } > ROM
+
+  .exidx :
   {
-    PROVIDE(__RUNTIME_CLEAR_TABLE = .) ;
-    LONG(0 + ADDR(.bss));   LONG(SIZEOF(.bss));
-    LONG(-1);                 LONG(-1);
     . = ALIGN(4);
-  } > FLASH
+    PROVIDE(__exidx_start = .);
+    *(.riscv.exidx*)
+    . = ALIGN(4);
+    PROVIDE(__exidx_end = .);
+  } > ROM
+
+  . = __RAM_START_ADDRESS;
+  . = ALIGN(4);
 
-  /* Runtime copy table */
-  .copy_sec : ALIGN(4)
+  /* The ROM-to-RAM initialized sdata section */
+  .sdata : ALIGN(4)
   {
-    PROVIDE(__RUNTIME_COPY_TABLE = .) ;
-    LONG(LOADADDR(.data));   LONG(0 + ADDR(.data));   LONG(SIZEOF(.data));
-    LONG(LOADADDR(.sdata));  LONG(0 + ADDR(.sdata));  LONG(SIZEOF(.sdata));
-    LONG(-1);                LONG(-1);                LONG(-1);
+    _sdata_begin = .;
+    *(.sdata)
     . = ALIGN(4);
-    PROVIDE(__CODE_END_ADDRESS = .);
-  } > FLASH 
+    KEEP (*(.sdata))
+    *(.sdata*)
+    . = ALIGN(4);
+    KEEP (*(.sdata*))
+    _sdata_end = .;
+  } > SRAM AT > ROM
 
-  /* The ROM-to-RAM initialized data sections */
-  .data : ALIGN(4) 
+  /* The ROM-to-RAM initialized data section */
+  .data : ALIGN(4)
   {
+    _data_begin = .;
     *(.data)
+    . = ALIGN(4);
+    KEEP (*(.data))
     *(.data*)
     . = ALIGN(4);
-  } > RAM  AT>FLASH
-
-  .sdata : ALIGN(4) 
+    KEEP (*(.data*))
+    _data_end = .;
+  } > RAM AT > ROM
+
+  /* The uninitialized (zero-cleared) sbss section */
+  .sbss : ALIGN(4)
   {
-    *(.sdata)
+    _sbss_begin = .;
+    *(.sbss)
     . = ALIGN(4);
-  } > RAM  AT>FLASH
-
-
+    KEEP (*(.sbss))
+    *(.sbss*)
+    . = ALIGN(4);
+    KEEP (*(.sbss*))
+    _sbss_end = .;
+  } > SRAM
 
-  /* The uninitialized (zero-cleared) data sections */
+  /* The uninitialized (zero-cleared) bss section */
   .bss : ALIGN(4)
   {
+    _bss_begin = .;
     *(.bss)
-    *(.bss*)
     . = ALIGN(4);
-  } > RAM
-
-  .sbss : ALIGN(4)
-  {
-    *(.sbss)
+    KEEP (*(.bss))
+    *(.bss*)
     . = ALIGN(4);
+    KEEP (*(.bss*))
+    _bss_end = .;
   } > RAM
 
+  PROVIDE(end = .);
+  PROVIDE(_fini = .);
+
+  . = __STACK_START_ADDRESS;
+
   /* stack definition */
   .stack :
   {
     . = ALIGN(MAX(__STACK_SIZE , .), 8);
-    PROVIDE(__STACK_TOP = .) ;
+    PROVIDE(__initial_stack_pointer = .) ;
   } > STACK
 
+  _srom_data_begin = LOADADDR(.sdata);
+  _rom_data_begin = LOADADDR(.data);
 }

ref_app/target/micros/bl602_sifive_e24_riscv/make/bl602_sifive_e24_riscv_files.gmk

@@ -9,7 +9,9 @@
 # File list of the target-specific files in the project
 # ------------------------------------------------------------------------------
 
-FILES_TGT  = $(PATH_APP)/mcal/mcal_gcc_cxx_completion                        \
-             $(PATH_TGT)/Code/Startup/boot                                   \
-             $(PATH_TGT)/startup/intvect                                     \
-             $(PATH_TGT)/startup/Startup
+FILES_TGT  = $(PATH_APP)/mcal/mcal_gcc_cxx_completion                                \
+             $(PATH_TGT)/Code/Startup/boot                                           \
+             $(PATH_TGT)/startup/crt0                                                \
+             $(PATH_TGT)/startup/crt0_init_ram                                       \
+             $(PATH_TGT)/startup/crt1                                                \
+             $(PATH_TGT)/startup/intvect

ref_app/target/micros/bl602_sifive_e24_riscv/make/bl602_sifive_e24_riscv_flags.gmk

@@ -15,17 +15,12 @@ GCC_VERSION  := 15.2.0
 
 TGT_SUFFIX    = elf
 
-ARCH         :=  -mcpu=sifive-e24                              \
-                 -mabi=ilp32                                   \
-                 -msmall-data-limit=0                          \
-                 -falign-functions=4
-
 TGT_ALLFLAGS  = -O2                                            \
-                $(ARCH)                                        \
-                -DPRINTF_INCLUDE_CONFIG_H                      \
-                -fomit-frame-pointer                           \
-                -fno-reorder-blocks-and-partition              \
-                -fno-reorder-functions
+                -ffast-math                                    \
+                -mcpu=sifive-e24                               \
+                -mabi=ilp32                                    \
+                -msmall-data-limit=32                          \
+                -falign-functions=4
 
 
 TGT_CFLAGS    = -std=c11                                       \