From 406d00bda29df020541763b731fa78b5bf8fea95 Mon Sep 17 00:00:00 2001 From: ckormanyos Date: Mon, 9 Feb 2026 21:09:56 +0100 Subject: [PATCH 01/11] Initial commit Chalandi-based code running --- ref_app/ref_app.sln | 4 + ref_app/ref_app.vcxproj | 3 + ref_app/ref_app.vcxproj.filters | 6 + .../mcal/xtensa_esp32_p4/xtensa_esp32_p4.txt | 1 + ref_app/target.vcxproj | 39 + ref_app/target.vcxproj.filters | 57 + .../xtensa_esp32_p4/make/xtensa_esp32_p4.ld | 151 + .../make/xtensa_esp32_p4_files.gmk | 18 + .../make/xtensa_esp32_p4_flags.gmk | 100 + .../xtensa_esp32_p4/startup/Code/Appli/main.c | 131 + .../startup/Code/Mcal/esp32p4.h | 63864 +++++++ .../startup/Code/Mcal/esp32p4.svd | 133701 +++++++++++++++ .../xtensa_esp32_p4/startup/Code/Mcal/gpio.c | 148 + .../xtensa_esp32_p4/startup/Code/Mcal/gpio.h | 31 + .../startup/Code/Mcal/interrupt.h | 85 + .../startup/Code/Mcal/riscv-csr.h | 3791 + .../startup/Code/SBL/Output/SBL.bin | Bin 0 -> 4400 bytes .../startup/Code/SBL/Output/SBL.elf | Bin 0 -> 160668 bytes .../startup/Code/SBL/Output/SBL.hex | 274 + .../startup/Code/SBL/Output/SBL.map | 167 + .../startup/Code/SBL/Output/SBL.readelf | 1754 + .../startup/Code/Startup/Startup.c | 187 + .../startup/Code/Startup/boot.s | 199 + .../startup/Code/Startup/intvect.c | 119 + 24 files changed, 204830 insertions(+) create mode 100644 ref_app/src/mcal/xtensa_esp32_p4/xtensa_esp32_p4.txt create mode 100644 ref_app/target/micros/xtensa_esp32_p4/make/xtensa_esp32_p4.ld create mode 100644 ref_app/target/micros/xtensa_esp32_p4/make/xtensa_esp32_p4_files.gmk create mode 100644 ref_app/target/micros/xtensa_esp32_p4/make/xtensa_esp32_p4_flags.gmk create mode 100644 ref_app/target/micros/xtensa_esp32_p4/startup/Code/Appli/main.c create mode 100644 ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/esp32p4.h create mode 100644 ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/esp32p4.svd create mode 100644 ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/gpio.c create mode 100644 ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/gpio.h create mode 100644 ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/interrupt.h create mode 100644 ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/riscv-csr.h create mode 100644 ref_app/target/micros/xtensa_esp32_p4/startup/Code/SBL/Output/SBL.bin create mode 100644 ref_app/target/micros/xtensa_esp32_p4/startup/Code/SBL/Output/SBL.elf create mode 100644 ref_app/target/micros/xtensa_esp32_p4/startup/Code/SBL/Output/SBL.hex create mode 100644 ref_app/target/micros/xtensa_esp32_p4/startup/Code/SBL/Output/SBL.map create mode 100644 ref_app/target/micros/xtensa_esp32_p4/startup/Code/SBL/Output/SBL.readelf create mode 100644 ref_app/target/micros/xtensa_esp32_p4/startup/Code/Startup/Startup.c create mode 100644 ref_app/target/micros/xtensa_esp32_p4/startup/Code/Startup/boot.s create mode 100644 ref_app/target/micros/xtensa_esp32_p4/startup/Code/Startup/intvect.c diff --git a/ref_app/ref_app.sln b/ref_app/ref_app.sln index aaca043fe..bc2dabede 100644 --- a/ref_app/ref_app.sln +++ b/ref_app/ref_app.sln @@ -73,6 +73,7 @@ Global target wch_ch32v307_llvm|x64 = target wch_ch32v307_llvm|x64 target wch_ch32v307|x64 = target wch_ch32v307|x64 target x86_64-w64-mingw32|x64 = target x86_64-w64-mingw32|x64 + target xtensa_esp32_p4|x64 = target xtensa_esp32_p4|x64 target xtensa_esp32_s3_riscv_cop|x64 = target xtensa_esp32_s3_riscv_cop|x64 target xtensa_esp32_s3|x64 = target xtensa_esp32_s3|x64 target xtensa32|x64 = target xtensa32|x64 @@ -109,6 +110,7 @@ Global {C8B59726-9319-45C3-8F11-F9F388FB6A2C}.target wch_ch32v307_llvm|x64.ActiveCfg = Release|x64 {C8B59726-9319-45C3-8F11-F9F388FB6A2C}.target wch_ch32v307|x64.ActiveCfg = Release|x64 {C8B59726-9319-45C3-8F11-F9F388FB6A2C}.target x86_64-w64-mingw32|x64.ActiveCfg = Release|x64 + {C8B59726-9319-45C3-8F11-F9F388FB6A2C}.target xtensa_esp32_p4|x64.ActiveCfg = Release|x64 {C8B59726-9319-45C3-8F11-F9F388FB6A2C}.target xtensa_esp32_s3_riscv_cop|x64.ActiveCfg = Release|x64 {C8B59726-9319-45C3-8F11-F9F388FB6A2C}.target xtensa_esp32_s3|x64.ActiveCfg = Release|x64 {C8B59726-9319-45C3-8F11-F9F388FB6A2C}.target xtensa32|x64.ActiveCfg = Release|x64 @@ -168,6 +170,8 @@ Global {30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target wch_ch32v307|x64.Build.0 = target wch_ch32v307|x64 {30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target x86_64-w64-mingw32|x64.ActiveCfg = target x86_64-w64-mingw32|x64 {30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target x86_64-w64-mingw32|x64.Build.0 = target x86_64-w64-mingw32|x64 + {30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target xtensa_esp32_p4|x64.ActiveCfg = target xtensa_esp32_p4|x64 + {30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target xtensa_esp32_p4|x64.Build.0 = target xtensa_esp32_p4|x64 {30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target xtensa_esp32_s3_riscv_cop|x64.ActiveCfg = target xtensa_esp32_s3_riscv_cop|x64 {30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target xtensa_esp32_s3_riscv_cop|x64.Build.0 = target xtensa_esp32_s3_riscv_cop|x64 {30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target xtensa_esp32_s3|x64.ActiveCfg = target xtensa_esp32_s3|x64 diff --git a/ref_app/ref_app.vcxproj b/ref_app/ref_app.vcxproj index 34c6b0128..ca04871fe 100644 --- a/ref_app/ref_app.vcxproj +++ b/ref_app/ref_app.vcxproj @@ -3733,6 +3733,9 @@ true true + + true + diff --git a/ref_app/ref_app.vcxproj.filters b/ref_app/ref_app.vcxproj.filters index 1e1e2e869..414c0eb0a 100644 --- a/ref_app/ref_app.vcxproj.filters +++ b/ref_app/ref_app.vcxproj.filters @@ -287,6 +287,9 @@ {40be70da-9086-46f9-b158-4dc468860fc7} + + {cc6519dd-1588-4aed-9bd1-c4cc22a5e560} + @@ -3365,5 +3368,8 @@ tools\Util\msys64\usr\bin + + src\mcal\xtensa_esp32_p4 + \ No newline at end of file diff --git a/ref_app/src/mcal/xtensa_esp32_p4/xtensa_esp32_p4.txt b/ref_app/src/mcal/xtensa_esp32_p4/xtensa_esp32_p4.txt new file mode 100644 index 000000000..86696a278 --- /dev/null +++ b/ref_app/src/mcal/xtensa_esp32_p4/xtensa_esp32_p4.txt @@ -0,0 +1 @@ +xtensa_esp32_p4.txt diff --git a/ref_app/target.vcxproj b/ref_app/target.vcxproj index 8e4b50703..06bd2b8e0 100644 --- a/ref_app/target.vcxproj +++ b/ref_app/target.vcxproj @@ -113,6 +113,10 @@ target xtensa32 x64 + + target xtensa_esp32_p4 + x64 + target xtensa_esp32_s3_riscv_cop x64 @@ -262,6 +266,12 @@ true v143 + + Makefile + Unicode + true + v143 + Makefile Unicode @@ -416,6 +426,9 @@ + + + @@ -463,6 +476,7 @@ target\build\build.bat stm32h7a3 target\build\build.bat xtensa32 target\build\build.bat xtensa_esp32_s3 + target\build\build.bat xtensa_esp32_p4 target\build\build.bat xtensa_esp32_s3_riscv_cop target\build\build.bat stm32f429 target\build\build.bat am335x @@ -493,6 +507,7 @@ target\build\build.bat stm32h7a3 rebuild target\build\build.bat xtensa32 rebuild target\build\build.bat xtensa_esp32_s3 rebuild + target\build\build.bat xtensa_esp32_p4 rebuild target\build\build.bat xtensa_esp32_s3_riscv_cop rebuild target\build\build.bat stm32f429 rebuild @@ -524,6 +539,7 @@ target\build\build.bat stm32h7a3 clean_all target\build\build.bat xtensa32 clean_all target\build\build.bat xtensa_esp32_s3 clean_all + target\build\build.bat xtensa_esp32_p4 clean_all target\build\build.bat xtensa_esp32_s3_riscv_cop clean_all target\build\build.bat stm32f429 clean_all @@ -555,6 +571,7 @@ $(SolutionDir)bin\ref_app.hex $(SolutionDir)bin\ref_app.hex $(SolutionDir)bin\ref_app.hex + $(SolutionDir)bin\ref_app.hex $(SolutionDir)bin\ref_app.hex $(SolutionDir)bin\ref_app.hex $(SolutionDir)bin\ref_app.hex @@ -586,6 +603,7 @@ ESP_PLATFORM; MBEDTLS_CONFIG_FILE="mbedtls/esp_config.h"; HAVE_CONFIG_H; GCC_NOT_5_2_0=1; WITH_POSIX; F_CPU=240000000L; ARDUINO=10813; ARDUINO_ESP32_DEV; ARDUINO_ARCH_ESP32; ARDUINO_BOARD="ESP32_DEV"; ARDUINO_VARIANT="esp32"; ESP32; CORE_DEBUG_LEVEL=0 + @@ -616,6 +634,7 @@ $(SolutionDir)src\util\STL_C++XX_stdfloat;$(SolutionDir)src\util\STL;$(SolutionDir)/src;$(SolutionDir)/src/mcal/stm32f446 $(ProjectDir)/src/util/STL_C++XX_stdfloat; $(ProjectDir)/src/util/STL; $(ProjectDir)/src; $(ProjectDir)/src/mcal/xtensa32; $(ProjectDir)/src/util/STL_C++XX_stdfloat; $(ProjectDir)/src/util/STL; $(ProjectDir)/src; $(ProjectDir)/src/mcal/xtensa_esp32_s3; + $(ProjectDir)/src/util/STL_C++XX_stdfloat; $(ProjectDir)/src/util/STL; $(ProjectDir)/src; $(ProjectDir)/src/mcal/xtensa_esp32_p4; $(ProjectDir)/src/util/STL_C++XX_stdfloat; $(ProjectDir)/src/util/STL; $(ProjectDir)/src; $(ProjectDir)/src/mcal/xtensa_esp32_s3; $(SolutionDir)src\util\STL_C++XX_stdfloat;$(SolutionDir)src\util\STL;$(SolutionDir)/src;$(SolutionDir)/src/mcal/stm32f429 $(SolutionDir)/src;$(SolutionDir)/src/mcal/am335x @@ -646,6 +665,7 @@ + @@ -676,6 +696,7 @@ + @@ -706,6 +727,7 @@ + @@ -949,6 +971,11 @@ $(SolutionDir)tmp\log\ref_app.log + + + $(SolutionDir)tmp\log\ref_app.log + + $(SolutionDir)tmp\log\ref_app.log @@ -1126,6 +1153,10 @@ + + + + @@ -1252,6 +1283,10 @@ + + + + @@ -1268,6 +1303,10 @@ + + + + diff --git a/ref_app/target.vcxproj.filters b/ref_app/target.vcxproj.filters index c723efc3d..0454f1c37 100644 --- a/ref_app/target.vcxproj.filters +++ b/ref_app/target.vcxproj.filters @@ -340,6 +340,27 @@ {e85df680-7e70-4f5d-87c0-73dbb822c1ba} + + {4ce9fafb-0c5d-4593-b8f8-c16c3fc11c9c} + + + {c72d0dcc-9b1a-4a96-b2e4-0d2f5b65711c} + + + {cdb1aef0-d686-4790-8231-17b7cd6185cf} + + + {b2aaad4e-1735-4de1-a6dc-ac965b62d05e} + + + {a4e34517-143d-491c-925b-5d3e7d7bd195} + + + {98fa75e2-bb60-4a37-9e72-f609821f0859} + + + {17889d6f-9174-40cb-bcad-01e3995207e5} + @@ -780,6 +801,18 @@ micros\r7fa4m1ab\make + + micros\xtensa_esp32_p4\make + + + micros\xtensa_esp32_p4\make + + + micros\xtensa_esp32_p4\make + + + micros\xtensa_esp32_p4\startup\Code\Startup + @@ -1133,6 +1166,18 @@ micros\r7fa4m1ab\startup + + micros\xtensa_esp32_p4\startup\Code\Appli + + + micros\xtensa_esp32_p4\startup\Code\Mcal + + + micros\xtensa_esp32_p4\startup\Code\Startup + + + micros\xtensa_esp32_p4\startup\Code\Startup + @@ -1152,6 +1197,18 @@ micros\am6254_soc\Code\Startup\Core\a53 + + micros\xtensa_esp32_p4\startup\Code\Mcal + + + micros\xtensa_esp32_p4\startup\Code\Mcal + + + micros\xtensa_esp32_p4\startup\Code\Mcal + + + micros\xtensa_esp32_p4\startup\Code\Mcal + diff --git a/ref_app/target/micros/xtensa_esp32_p4/make/xtensa_esp32_p4.ld b/ref_app/target/micros/xtensa_esp32_p4/make/xtensa_esp32_p4.ld new file mode 100644 index 000000000..0685130e3 --- /dev/null +++ b/ref_app/target/micros/xtensa_esp32_p4/make/xtensa_esp32_p4.ld @@ -0,0 +1,151 @@ +/****************************************************************************************** + Filename : Memory_Map.ld + + Core : RISC-V + + MCU : ESP32-P4 + + Author : Chalandi Amine + + Owner : Chalandi Amine + + Date : 25.01.2026 + + Description : Linker descriptor file + +******************************************************************************************/ + +/****************************************************************************************** + ELF Entrypoint +******************************************************************************************/ +ENTRY(_start) + +/****************************************************************************************** + Link librariess +******************************************************************************************/ +/* INPUT(libc.a libm.a libgcc.a) */ + +/****************************************************************************************** + Globals +******************************************************************************************/ +__STACK_SIZE_CORE0 = 1K; +__STACK_SIZE_CORE1 = 1K; + +/****************************************************************************************** + Memory configuration +******************************************************************************************/ + +MEMORY +{ + HP_TCM(rwx) : ORIGIN = 0x20000000, LENGTH = 8k + FLASH(rx) : ORIGIN = 0x40005000, LENGTH = 31M + LP_FLASH(rx) : ORIGIN = 0x41F00000, LENGTH = 1M + RAM(rwx) : ORIGIN = 0x48000000, LENGTH = 31M + HP_L2MEM(rwx) : ORIGIN = 0x4FF00000, LENGTH = 768K + LP_SRAM(rwx) : ORIGIN = 0x50108000, LENGTH = 32K +} + +/****************************************************************************************** + Sections definition +******************************************************************************************/ +SECTIONS +{ + /* Program code (text) */ + .text : ALIGN(4) + { + PROVIDE(__CODE_BASE_ADDRESS = .); + *(.boot) + *(.text) + . = ALIGN(4); + } > FLASH + + /* Read-only data (.rodata) */ + .rodata : ALIGN(4) + { + PROVIDE(__RODATA_BASE_ADDRESS = .); + *(.rodata) + } > FLASH + + /* Section for constructors */ + .ctors : ALIGN(4) + { + PROVIDE(__CTOR_LIST__ = .); + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + LONG(-1) ; + PROVIDE(__CTOR_END__ = .); + . = ALIGN(4); + } > FLASH + + + /* Section for destructors */ + .dtors : ALIGN(4) + { + PROVIDE(__DTOR_LIST__ = .); + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array)) + LONG(-1) ; + PROVIDE(__DTOR_END__ = .); + . = ALIGN(4); + } > FLASH + + /* Runtime clear table */ + .clear_sec : ALIGN(4) + { + PROVIDE(__RUNTIME_CLEAR_TABLE = .) ; + LONG(0 + ADDR(.bss)); LONG(SIZEOF(.bss)); + LONG(-1); LONG(-1); + . = ALIGN(4); + } > FLASH + + /* Runtime copy table */ + .copy_sec : ALIGN(4) + { + PROVIDE(__RUNTIME_COPY_TABLE = .) ; + LONG(LOADADDR(.data)); LONG(0 + ADDR(.data)); LONG(SIZEOF(.data)); + LONG(-1); LONG(-1); LONG(-1); + . = ALIGN(4); + PROVIDE(__CODE_END_ADDRESS = .); + } > FLASH + + /* The ROM-to-RAM initialized data sections */ + .data : ALIGN(4) + { + *(.data) + *(.data*) + . = ALIGN(4); + } > RAM AT>FLASH + + /* The uninitialized (zero-cleared) data sections */ + .bss : ALIGN(4) + { + *(.bss) + *(.bss*) + . = ALIGN(4); + } > RAM + + /* stack definition */ + .stack_core0 : + { + PROVIDE(__CORE0_STACK_BOTTOM = .) ; + . = ALIGN(MAX(__STACK_SIZE_CORE0 , .), 8); + PROVIDE(__CORE0_STACK_TOP = .) ; + } > RAM + + .stack_core1 : + { + PROVIDE(__CORE1_STACK_BOTTOM = .) ; + . = ALIGN(MAX(__STACK_SIZE_CORE1 , .), 8); + PROVIDE(__CORE1_STACK_TOP = .) ; + } > RAM + + __ULP_CODE_BASE = 0x40008000; + + /* ROM APIs */ + printf = 0x4fc00024; + +} diff --git a/ref_app/target/micros/xtensa_esp32_p4/make/xtensa_esp32_p4_files.gmk b/ref_app/target/micros/xtensa_esp32_p4/make/xtensa_esp32_p4_files.gmk new file mode 100644 index 000000000..d8463cb19 --- /dev/null +++ b/ref_app/target/micros/xtensa_esp32_p4/make/xtensa_esp32_p4_files.gmk @@ -0,0 +1,18 @@ +# +# Copyright Christopher Kormanyos 2025. +# Distributed under the Boost Software License, +# Version 1.0. (See accompanying file LICENSE_1_0.txt +# or copy at http://www.boost.org/LICENSE_1_0.txt) +# + +# ------------------------------------------------------------------------------ +# File list of the target-specific files in the project +# ------------------------------------------------------------------------------ + +FILES_CPP := + +FILES_TGT := $(PATH_TGT)/startup/Code/Appli/main \ + $(PATH_TGT)/startup/Code/Mcal/gpio \ + $(PATH_TGT)/startup/Code/Startup/boot \ + $(PATH_TGT)/startup/Code/Startup/intvect \ + $(PATH_TGT)/startup/Code/Startup/Startup diff --git a/ref_app/target/micros/xtensa_esp32_p4/make/xtensa_esp32_p4_flags.gmk b/ref_app/target/micros/xtensa_esp32_p4/make/xtensa_esp32_p4_flags.gmk new file mode 100644 index 000000000..a205b0bc5 --- /dev/null +++ b/ref_app/target/micros/xtensa_esp32_p4/make/xtensa_esp32_p4_flags.gmk @@ -0,0 +1,100 @@ +# +# Copyright Christopher Kormanyos 2018 - 2025. +# Distributed under the Boost Software License, +# Version 1.0. (See accompanying file LICENSE_1_0.txt +# or copy at http://www.boost.org/LICENSE_1_0.txt) +# + +# ------------------------------------------------------------------------------ +# compiler flags for the target architecture +# ------------------------------------------------------------------------------ + +GCC_VERSION = 14.2.0 +GCC_TARGET = riscv32-esp-elf +GCC_PREFIX = riscv32-esp-elf + +TGT_SUFFIX = elf + +WARN_FLAGS := + +TGT_ALLFLAGS = -O2 \ + -march=rv32imafc_zicsr_zifencei_xesppie \ + -mabi=ilp32f \ + -msmall-data-limit=0 \ + -ffreestanding \ + -falign-functions=4 \ + -fomit-frame-pointer + + +TGT_CFLAGS = -std=c23 \ + -nostdlib \ + $(TGT_ALLFLAGS) + +TGT_CXXFLAGS = -std=c++23 \ + $(TGT_ALLFLAGS) + +TGT_INCLUDES = -I$(PATH_TGT)/startup/Code \ + -I$(PATH_TGT)/startup/Code/Appli \ + -I$(PATH_TGT)/startup/Code/Mcal \ + -I$(PATH_TGT)/startup/Code/Startup + + +TGT_AFLAGS = + +TGT_LDFLAGS = -nostdlib \ + -nostartfiles \ + -Wl,--no-warn-rwx-segments \ + -Wl,-z,max-page-size=4096 \ + -Wl,-Map,$(APP).map \ + -T $(LINKER_DEFINITION_FILE) \ + --specs=nano.specs \ + --specs=nosys.specs + + +# ------------------------------------------------------------------------------ +# Rule to assemble source file (*.S) to object file (*.o). +# ------------------------------------------------------------------------------ + +ifeq ($(TYP_OS),WIN) +TGT_GCC := $(PATH_TOOLS_CC)/$(GCC_PREFIX)-gcc.exe +TGT_GCC := $(subst /,\,$(TGT_GCC)) +else +TGT_GCC := $(GCC_PREFIX)-gcc +endif + + +# ------------------------------------------------------------------------------ +# Image file and flash batch file. +# ------------------------------------------------------------------------------ + +RULE_SPECIAL_MAKE_IMAGE_FILE := + +ifeq ($(TYP_OS),WIN) + +ESP32S3_ESP_TOOL_DIR := $(PATH_TOOLS)/espressif/esptool-v4.11.0-windows-amd64 + +ESP32S3_ESP_TOOL_FLAGS_PROG := --chip esp32p4 \ + -p COM5 -b 460800 \ + --before=default_reset \ + --after=hard_reset write_flash \ + --flash_mode dio \ + --flash_freq 80m \ + --flash_size 32MB \ + 0x2000 $(CURDIR)/$(PATH_TGT)/startup/Code/SBL/Output/SBL.bin \ + 0x5000 $(CURDIR)/$(basename $(APP).$(TGT_SUFFIX)).bin + + +OBJCOPY := $(subst /,\,$(PATH_TOOLS_CC)/$(GCC_PREFIX)-objcopy.exe) + + +RULE_SPECIAL_MAKE_IMAGE_FILE := $(OBJCOPY) $(APP).$(TGT_SUFFIX) -O binary $(APP).bin + + +ESP32S3_ESP_TOOL_CMD_COPY_PART2 := copy /Y $(subst /,\\,$(ESP32S3_ESP_TOOL_DIR)\*.*) $(subst /,\,$(CURDIR)/bin) > 2 > NUL +ESP32S3_ESP_TOOL_CMD_ECHO := $(ECHO) esptool.exe $(subst /,\\,$(ESP32S3_ESP_TOOL_FLAGS_PROG)) > $(subst /,\,$(CURDIR)/bin/flash.bat) + + +RULE_SPECIAL_MAKE_FLASH_BATCH := $(ESP32S3_ESP_TOOL_CMD_COPY_PART2) \ + && $(ESP32S3_ESP_TOOL_CMD_ECHO) + +endif diff --git a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Appli/main.c b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Appli/main.c new file mode 100644 index 000000000..1742764f1 --- /dev/null +++ b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Appli/main.c @@ -0,0 +1,131 @@ +/****************************************************************************************** + Filename : main.c + + Core : RISC-V + + MCU : ESP32-P4 + + Author : Chalandi Amine + + Owner : Chalandi Amine + + Date : 25.01.2026 + + Description : Application main function + +******************************************************************************************/ + +//----------------------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------------------- +#include +#include +#include "riscv-csr.h" +#include "esp32p4.h" +#include "interrupt.h" +#include "gpio.h" + +//----------------------------------------------------------------------------------------- +// Defines +//----------------------------------------------------------------------------------------- +#define TIMEOUT_500MS 160000000ull +#define TIMEOUT_1S 320000000ull + +//----------------------------------------------------------------------------------------- +// Macros +//----------------------------------------------------------------------------------------- + +//----------------------------------------------------------------------------------------- +// Globals +//----------------------------------------------------------------------------------------- +uint32_t sync_lock = 0; + +//----------------------------------------------------------------------------------------- +// Function Prototypes +//----------------------------------------------------------------------------------------- +void osHwAcquireSpinLock(uint32_t* lock); +void osHwReleaseSpinLock(uint32_t* lock); +uint32_t osGetActiveCore(void); +void __attribute__((interrupt)) Isr_TIMER_Interrupt(void); + +//----------------------------------------------------------------------------------------- +/// \brief +/// +/// \param +/// +/// \return +//----------------------------------------------------------------------------------------- +int main(void); + +int main(void) +{ + osHwAcquireSpinLock(&sync_lock); + /* output a text message on the uart console */ + printf("BareMetal ESP32-P4 SW is Alive on HP core%ld!\n\r", osGetActiveCore()); + osHwReleaseSpinLock(&sync_lock); + + if(0 == osGetActiveCore()) + { + gpio_cfg_output(7); + gpio_cfg_output(8); + gpio_cfg_output(24); + gpio_cfg_output(25); + gpio_cfg_output(46); + gpio_cfg_output(47); + gpio_cfg_output(48); + gpio_cfg_output(54); + gpio_cfg_output(20); + gpio_cfg_output(19); + gpio_cfg_output(18); + gpio_cfg_output(17); + gpio_cfg_output(16); + gpio_cfg_output(15); + gpio_cfg_output(14); + gpio_cfg_output(33); + gpio_cfg_output(32); + gpio_cfg_output(27); + gpio_cfg_output(26); + gpio_cfg_output(23); + gpio_cfg_output(32); + gpio_cfg_output(21); + } + + /* set the timer interrupt as hardware vectored in the CLIC */ + CLIC->interrupt[INT_TIMER_ID].clicintattr = 1; + + /* enable timer machine interrupt in the CLIC */ + CLIC->interrupt[INT_TIMER_ID].clicintie = 1; + + /* configure the sampling mode of MTIME */ + CLINT_MTIMECTL |= (3ul << 4); + + /* set MTIME timeout to 500ms */ + CLINT_MTIMECMP = (uint64_t)(CLINT_MTIME + (TIMEOUT_500MS + TIMEOUT_500MS)); + + /* endless loop */ + while(1); + + return 0; +} + +//----------------------------------------------------------------------------------------- +/// \brief +/// +/// \param +/// +/// \return +//----------------------------------------------------------------------------------------- +void Isr_TIMER_Interrupt(void) +{ + CLINT_MTIMECMP = (uint64_t)(CLINT_MTIME + (TIMEOUT_500MS + TIMEOUT_500MS)); + + if(0 == osGetActiveCore()) + { + gpio_toggle_output_level(54); + } + else + { + gpio_toggle_output_level(19); + } +} + diff --git a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/esp32p4.h b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/esp32p4.h new file mode 100644 index 000000000..d4c2d5dc2 --- /dev/null +++ b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/esp32p4.h @@ -0,0 +1,63864 @@ + +#ifndef ESP32_P4_H +#define ESP32_P4_H + +#ifdef __cplusplus +extern "C" { +#endif + + +#include +#include +#include + +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum { +/* ======================================= RISC-V Specific Interrupt Numbers ======================================= */ +/* ========================================== ESP32_P4 Specific Interrupt Numbers ========================================== */ + LP_WDT_IRQn = 1, /*!< 1 LP_WDT */ + LP_TIMER0_IRQn = 2, /*!< 2 LP_TIMER0 */ + LP_TIMER1_IRQn = 3, /*!< 3 LP_TIMER1 */ + PMU0_IRQn = 6, /*!< 6 PMU0 */ + PMU1_IRQn = 7, /*!< 7 PMU1 */ + LP_ANA_IRQn = 8, /*!< 8 LP_ANA */ + LP_ADC_IRQn = 9, /*!< 9 LP_ADC */ + LP_GPIO_IRQn = 10, /*!< 10 LP_GPIO */ + LP_I2C0_IRQn = 11, /*!< 11 LP_I2C0 */ + LP_I2S0_IRQn = 12, /*!< 12 LP_I2S0 */ + LP_TOUCH_IRQn = 14, /*!< 14 LP_TOUCH */ + LP_TSENS_IRQn = 15, /*!< 15 LP_TSENS */ + LP_UART_IRQn = 16, /*!< 16 LP_UART */ + LP_SYS_IRQn = 19, /*!< 19 LP_SYS */ + LP_HUK_IRQn = 20, /*!< 20 LP_HUK */ + USB_DEVICE_IRQn = 22, /*!< 22 USB_DEVICE */ + DMA_IRQn = 24, /*!< 24 DMA */ + SPI2_IRQn = 25, /*!< 25 SPI2 */ + SPI3_IRQn = 26, /*!< 26 SPI3 */ + I2S0_IRQn = 27, /*!< 27 I2S0 */ + I2S1_IRQn = 28, /*!< 28 I2S1 */ + I2S2_IRQn = 29, /*!< 29 I2S2 */ + UHCI0_IRQn = 30, /*!< 30 UHCI0 */ + UART0_IRQn = 31, /*!< 31 UART0 */ + UART1_IRQn = 32, /*!< 32 UART1 */ + UART2_IRQn = 33, /*!< 33 UART2 */ + UART3_IRQn = 34, /*!< 34 UART3 */ + UART4_IRQn = 35, /*!< 35 UART4 */ + PWM0_IRQn = 38, /*!< 38 PWM0 */ + PWM1_IRQn = 39, /*!< 39 PWM1 */ + TWAI0_IRQn = 40, /*!< 40 TWAI0 */ + TWAI1_IRQn = 41, /*!< 41 TWAI1 */ + TWAI2_IRQn = 42, /*!< 42 TWAI2 */ + RMT_IRQn = 43, /*!< 43 RMT */ + I2C0_IRQn = 44, /*!< 44 I2C0 */ + I2C1_IRQn = 45, /*!< 45 I2C1 */ + TG0_T0_IRQn = 46, /*!< 46 TG0_T0 */ + TG0_T1_IRQn = 47, /*!< 47 TG0_T1 */ + TG0_WDT_IRQn = 48, /*!< 48 TG0_WDT */ + TG1_T0_IRQn = 49, /*!< 49 TG1_T0 */ + TG1_T1_IRQn = 50, /*!< 50 TG1_T1 */ + TG1_WDT_IRQn = 51, /*!< 51 TG1_WDT */ + LEDC_IRQn = 52, /*!< 52 LEDC */ + SYSTIMER_TARGET0_IRQn = 53, /*!< 53 SYSTIMER_TARGET0 */ + SYSTIMER_TARGET1_IRQn = 54, /*!< 54 SYSTIMER_TARGET1 */ + SYSTIMER_TARGET2_IRQn = 55, /*!< 55 SYSTIMER_TARGET2 */ + AHB_PDMA_IN_CH0_IRQn = 56, /*!< 56 AHB_PDMA_IN_CH0 */ + AHB_PDMA_IN_CH1_IRQn = 57, /*!< 57 AHB_PDMA_IN_CH1 */ + AHB_PDMA_IN_CH2_IRQn = 58, /*!< 58 AHB_PDMA_IN_CH2 */ + AHB_PDMA_OUT_CH0_IRQn = 59, /*!< 59 AHB_PDMA_OUT_CH0 */ + AHB_PDMA_OUT_CH1_IRQn = 60, /*!< 60 AHB_PDMA_OUT_CH1 */ + AHB_PDMA_OUT_CH2_IRQn = 61, /*!< 61 AHB_PDMA_OUT_CH2 */ + AXI_PDMA_IN_CH0_IRQn = 62, /*!< 62 AXI_PDMA_IN_CH0 */ + AXI_PDMA_IN_CH1_IRQn = 63, /*!< 63 AXI_PDMA_IN_CH1 */ + AXI_PDMA_IN_CH2_IRQn = 64, /*!< 64 AXI_PDMA_IN_CH2 */ + AXI_PDMA_OUT_CH0_IRQn = 65, /*!< 65 AXI_PDMA_OUT_CH0 */ + AXI_PDMA_OUT_CH1_IRQn = 66, /*!< 66 AXI_PDMA_OUT_CH1 */ + AXI_PDMA_OUT_CH2_IRQn = 67, /*!< 67 AXI_PDMA_OUT_CH2 */ + RSA_IRQn = 68, /*!< 68 RSA */ + AES_IRQn = 69, /*!< 69 AES */ + SHA_IRQn = 70, /*!< 70 SHA */ + ECC_IRQn = 71, /*!< 71 ECC */ + GPIO_INT0_IRQn = 74, /*!< 74 GPIO_INT0 */ + GPIO_INT1_IRQn = 75, /*!< 75 GPIO_INT1 */ + GPIO_INT2_IRQn = 76, /*!< 76 GPIO_INT2 */ + GPIO_INT3_IRQn = 77, /*!< 77 GPIO_INT3 */ + GPIO_PAD_COMP_IRQn = 78, /*!< 78 GPIO_PAD_COMP */ + CACHE_IRQn = 83, /*!< 83 CACHE */ + CSI_BRIDGE_IRQn = 85, /*!< 85 CSI_BRIDGE */ + DSI_BRIDGE_IRQn = 86, /*!< 86 DSI_BRIDGE */ + CSI_IRQn = 87, /*!< 87 CSI */ + DSI_IRQn = 88, /*!< 88 DSI */ + JPEG_IRQn = 95, /*!< 95 JPEG */ + PPA_IRQn = 96, /*!< 96 PPA */ + ISP_IRQn = 100, /*!< 100 ISP */ + I3C_IRQn = 101, /*!< 101 I3C */ + I3C_SLV_IRQn = 102, /*!< 102 I3C_SLV */ + HP_SYS_IRQn = 110, /*!< 110 HP_SYS */ + PCNT_IRQn = 111, /*!< 111 PCNT */ + PAU_IRQn = 112, /*!< 112 PAU */ + PARLIO_RX_IRQn = 113, /*!< 113 PARLIO_RX */ + PARLIO_TX_IRQn = 114, /*!< 114 PARLIO_TX */ + H264_DMA2D_OUT_CH0_IRQn = 115, /*!< 115 H264_DMA2D_OUT_CH0 */ + H264_DMA2D_OUT_CH1_IRQn = 116, /*!< 116 H264_DMA2D_OUT_CH1 */ + H264_DMA2D_OUT_CH2_IRQn = 117, /*!< 117 H264_DMA2D_OUT_CH2 */ + H264_DMA2D_OUT_CH3_IRQn = 118, /*!< 118 H264_DMA2D_OUT_CH3 */ + H264_DMA2D_OUT_CH4_IRQn = 119, /*!< 119 H264_DMA2D_OUT_CH4 */ + H264_DMA2D_IN_CH0_IRQn = 120, /*!< 120 H264_DMA2D_IN_CH0 */ + H264_DMA2D_IN_CH1_IRQn = 121, /*!< 121 H264_DMA2D_IN_CH1 */ + H264_DMA2D_IN_CH2_IRQn = 122, /*!< 122 H264_DMA2D_IN_CH2 */ + H264_DMA2D_IN_CH3_IRQn = 123, /*!< 123 H264_DMA2D_IN_CH3 */ + H264_DMA2D_IN_CH4_IRQn = 124, /*!< 124 H264_DMA2D_IN_CH4 */ + H264_DMA2D_IN_CH5_IRQn = 125, /*!< 125 H264_DMA2D_IN_CH5 */ + H264_REG_IRQn = 126, /*!< 126 H264_REG */ + ASSIST_DEBUG_IRQn = 127 /*!< 127 ASSIST_DEBUG */ +} IRQn_Type; + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ ADC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief ADC (Analog to Digital Converter) (ADC) + */ + +typedef struct { /*!< ADC Structure */ + + union { + __IOM uint32_t reg; /*!< Register */ + + struct { + __IOM uint32_t START_FORCE : 1; /*!< need_des */ + __IOM uint32_t START : 1; /*!< need_des */ + __IOM uint32_t WORK_MODE : 2; /*!< 0: single mode, 1: double mode, 2: alternate mode */ + __IOM uint32_t SAR_SEL : 1; /*!< 0: SAR1, 1: SAR2, only work for single SAR mode */ + __IOM uint32_t SAR_CLK_GATED : 1; /*!< need_des */ + __IOM uint32_t SAR_CLK_DIV : 8; /*!< SAR clock divider */ + __IOM uint32_t SAR1_PATT_LEN : 4; /*!< 0 ~ 15 means length 1 ~ 16 */ + __IOM uint32_t SAR2_PATT_LEN : 4; /*!< 0 ~ 15 means length 1 ~ 16 */ + __IOM uint32_t SAR1_PATT_P_CLEAR : 1; /*!< clear the pointer of pattern table for DIG ADC1 CTRL */ + __IOM uint32_t SAR2_PATT_P_CLEAR : 1; /*!< clear the pointer of pattern table for DIG ADC2 CTRL */ + __IOM uint32_t DATA_SAR_SEL : 1; /*!< 1: sar_sel will be coded by the MSB of the 16-bit output data, + in this case the resolution should not be larger than 11 + bits. */ + __IOM uint32_t DATA_TO_I2S : 1; /*!< 1: I2S input data is from SAR ADC (for DMA), 0: I2S input data + is from GPIO matrix */ + __IOM uint32_t XPD_SAR1_FORCE : 2; /*!< force option to xpd sar1 blocks */ + __IOM uint32_t XPD_SAR2_FORCE : 2; /*!< force option to xpd sar2 blocks */ + __IOM uint32_t WAIT_ARB_CYCLE : 2; /*!< wait arbit signal stable after sar_done */ + } bit; + } CTRL; + + union { + __IOM uint32_t reg; /*!< Register */ + + struct { + __IOM uint32_t MEAS_NUM_LIMIT : 1; /*!< need_des */ + __IOM uint32_t MAX_MEAS_NUM : 8; /*!< max conversion number */ + __IOM uint32_t SAR1_INV : 1; /*!< 1: data to DIG ADC1 CTRL is inverted, otherwise not */ + __IOM uint32_t SAR2_INV : 1; /*!< 1: data to DIG ADC2 CTRL is inverted, otherwise not */ + __IOM uint32_t TIMER_SEL : 1; /*!< 1: select saradc timer 0: i2s_ws trigger */ + __IOM uint32_t TIMER_TARGET : 12; /*!< to set saradc timer target */ + __IOM uint32_t TIMER_EN : 1; /*!< to enable saradc timer trigger */ + uint32_t : 7; + } bit; + } CTRL2; + + union { + __IOM uint32_t reg; /*!< Register */ + + struct { + uint32_t : 26; + __IOM uint32_t FILTER_FACTOR1 : 3; /*!< need_des */ + __IOM uint32_t FILTER_FACTOR0 : 3; /*!< need_des */ + } bit; + } FILTER_CTRL1; + + union { + __IOM uint32_t reg; /*!< Register */ + + struct { + __IOM uint32_t XPD_WAIT : 8; /*!< need_des */ + __IOM uint32_t RSTB_WAIT : 8; /*!< need_des */ + __IOM uint32_t STANDBY_WAIT : 8; /*!< need_des */ + uint32_t : 8; + } bit; + } FSM_WAIT; + + union { + __IOM uint32_t reg; /*!< Register */ + + struct { + __IM uint32_t SAR1_STATUS : 32; /*!< SAR1_STATUS */ + } bit; + } SAR1_STATUS; + + union { + __IOM uint32_t reg; /*!< Register */ + + struct { + __IM uint32_t SAR2_STATUS : 32; /*!< SAR2_STATUS */ + } bit; + } SAR2_STATUS; + + union { + __IOM uint32_t reg; /*!< Register */ + + struct { + __IOM uint32_t SAR1_PATT_TAB1 : 24; /*!< item 0 ~ 3 for pattern table 1 (each item one byte) */ + uint32_t : 8; + } bit; + } SAR1_PATT_TAB1; + + union { + __IOM uint32_t reg; /*!< Register */ + + struct { + __IOM uint32_t SAR1_PATT_TAB2 : 24; /*!< Item 4 ~ 7 for pattern table 1 (each item one byte) */ + uint32_t : 8; + } bit; + } SAR1_PATT_TAB2; + + union { + __IOM uint32_t reg; /*!< Register */ + + struct { + __IOM uint32_t SAR1_PATT_TAB3 : 24; /*!< Item 8 ~ 11 for pattern table 1 (each item one byte) */ + uint32_t : 8; + } bit; + } SAR1_PATT_TAB3; + + union { + __IOM uint32_t reg; /*!< Register */ + + struct { + __IOM uint32_t SAR1_PATT_TAB4 : 24; /*!< Item 12 ~ 15 for pattern table 1 (each item one byte) */ + uint32_t : 8; + } bit; + } SAR1_PATT_TAB4; + + union { + __IOM uint32_t reg; /*!< Register */ + + struct { + __IOM uint32_t SAR2_PATT_TAB1 : 24; /*!< item 0 ~ 3 for pattern table 2 (each item one byte) */ + uint32_t : 8; + } bit; + } SAR2_PATT_TAB1; + + union { + __IOM uint32_t reg; /*!< Register */ + + struct { + __IOM uint32_t SAR2_PATT_TAB2 : 24; /*!< Item 4 ~ 7 for pattern table 2 (each item one byte) */ + uint32_t : 8; + } bit; + } SAR2_PATT_TAB2; + + union { + __IOM uint32_t reg; /*!< Register */ + + struct { + __IOM uint32_t SAR2_PATT_TAB3 : 24; /*!< Item 8 ~ 11 for pattern table 2 (each item one byte) */ + uint32_t : 8; + } bit; + } SAR2_PATT_TAB3; + + union { + __IOM uint32_t reg; /*!< Register */ + + struct { + __IOM uint32_t SAR2_PATT_TAB4 : 24; /*!< Item 12 ~ 15 for pattern table 2 (each item one byte) */ + uint32_t : 8; + } bit; + } SAR2_PATT_TAB4; + + union { + __IOM uint32_t reg; /*!< Register */ + + struct { + uint32_t : 2; + __IOM uint32_t ARB_APB_FORCE : 1; /*!< adc2 arbiter force to enableapb controller */ + __IOM uint32_t ARB_RTC_FORCE : 1; /*!< adc2 arbiter force to enable rtc controller */ + __IOM uint32_t ARB_WIFI_FORCE : 1; /*!< adc2 arbiter force to enable wifi controller */ + __IOM uint32_t ARB_GRANT_FORCE : 1; /*!< adc2 arbiter force grant */ + __IOM uint32_t ARB_APB_PRIORITY : 2; /*!< Set adc2 arbiterapb priority */ + __IOM uint32_t ARB_RTC_PRIORITY : 2; /*!< Set adc2 arbiter rtc priority */ + __IOM uint32_t ARB_WIFI_PRIORITY : 2; /*!< Set adc2 arbiter wifi priority */ + __IOM uint32_t ARB_FIX_PRIORITY : 1; /*!< adc2 arbiter uses fixed priority */ + uint32_t : 19; + } bit; + } ARB_CTRL; + + union { + __IOM uint32_t reg; /*!< Register */ + + struct { + uint32_t : 14; + __IOM uint32_t FILTER_CHANNEL1 : 5; /*!< need_des */ + __IOM uint32_t FILTER_CHANNEL0 : 5; /*!< apb_adc1_filter_factor */ + uint32_t : 7; + __IOM uint32_t FILTER_RESET : 1; /*!< enable apb_adc1_filter */ + } bit; + } FILTER_CTRL0; + + union { + __IOM uint32_t reg; /*!< Register */ + + struct { + __IM uint32_t APB_SARADC1_DATA : 17; /*!< need_des */ + uint32_t : 15; + } bit; + } SAR1_DATA_STATUS; + + union { + __IOM uint32_t reg; /*!< Register */ + + struct { + __IOM uint32_t THRES0_CHANNEL : 5; /*!< need_des */ + __IOM uint32_t THRES0_HIGH : 13; /*!< saradc1's thres0 monitor thres */ + __IOM uint32_t THRES0_LOW : 13; /*!< saradc1's thres0 monitor thres */ + uint32_t : 1; + } bit; + } THRES0_CTRL; + + union { + __IOM uint32_t reg; /*!< Register */ + + struct { + __IOM uint32_t THRES1_CHANNEL : 5; /*!< need_des */ + __IOM uint32_t THRES1_HIGH : 13; /*!< saradc1's thres0 monitor thres */ + __IOM uint32_t THRES1_LOW : 13; /*!< saradc1's thres0 monitor thres */ + uint32_t : 1; + } bit; + } THRES1_CTRL; + + union { + __IOM uint32_t reg; /*!< Register */ + + struct { + uint32_t : 27; + __IOM uint32_t THRES_ALL_EN : 1; /*!< need_des */ + __IOM uint32_t THRES3_EN : 1; /*!< need_des */ + __IOM uint32_t THRES2_EN : 1; /*!< need_des */ + __IOM uint32_t THRES1_EN : 1; /*!< need_des */ + __IOM uint32_t THRES0_EN : 1; /*!< need_des */ + } bit; + } THRES_CTRL; + + union { + __IOM uint32_t reg; /*!< Register */ + + struct { + uint32_t : 26; + __IOM uint32_t THRES1_LOW_INT_ENA : 1; /*!< need_des */ + __IOM uint32_t THRES0_LOW_INT_ENA : 1; /*!< need_des */ + __IOM uint32_t THRES1_HIGH_INT_ENA : 1; /*!< need_des */ + __IOM uint32_t THRES0_HIGH_INT_ENA : 1; /*!< need_des */ + __IOM uint32_t SAR2_DONE_INT_ENA : 1; /*!< need_des */ + __IOM uint32_t SAR1_DONE_INT_ENA : 1; /*!< need_des */ + } bit; + } INT_ENA; + + union { + __IOM uint32_t reg; /*!< Register */ + + struct { + uint32_t : 26; + __IOM uint32_t THRES1_LOW_INT_RAW : 1; /*!< need_des */ + __IOM uint32_t THRES0_LOW_INT_RAW : 1; /*!< need_des */ + __IOM uint32_t THRES1_HIGH_INT_RAW : 1; /*!< need_des */ + __IOM uint32_t THRES0_HIGH_INT_RAW : 1; /*!< need_des */ + __IOM uint32_t SAR2_DONE_INT_RAW : 1; /*!< need_des */ + __IOM uint32_t SAR1_DONE_INT_RAW : 1; /*!< need_des */ + } bit; + } INT_RAW; + + union { + __IOM uint32_t reg; /*!< Register */ + + struct { + uint32_t : 26; + __IM uint32_t THRES1_LOW_INT_ST : 1; /*!< need_des */ + __IM uint32_t THRES0_LOW_INT_ST : 1; /*!< need_des */ + __IM uint32_t THRES1_HIGH_INT_ST : 1; /*!< need_des */ + __IM uint32_t THRES0_HIGH_INT_ST : 1; /*!< need_des */ + __IM uint32_t APB_SARADC2_DONE_INT_ST : 1;/*!< need_des */ + __IM uint32_t APB_SARADC1_DONE_INT_ST : 1;/*!< need_des */ + } bit; + } INT_ST; + + union { + __IOM uint32_t reg; /*!< Register */ + + struct { + uint32_t : 26; + __OM uint32_t THRES1_LOW_INT_CLR : 1; /*!< need_des */ + __OM uint32_t THRES0_LOW_INT_CLR : 1; /*!< need_des */ + __OM uint32_t THRES1_HIGH_INT_CLR : 1; /*!< need_des */ + __OM uint32_t THRES0_HIGH_INT_CLR : 1; /*!< need_des */ + __OM uint32_t APB_SARADC2_DONE_INT_CLR : 1;/*!< need_des */ + __OM uint32_t APB_SARADC1_DONE_INT_CLR : 1;/*!< need_des */ + } bit; + } INT_CLR; + + union { + __IOM uint32_t reg; /*!< Register */ + + struct { + __IOM uint32_t APB_ADC_EOF_NUM : 16; /*!< the dma_in_suc_eof gen when sample cnt = spi_eof_num */ + uint32_t : 14; + __IOM uint32_t APB_ADC_RESET_FSM : 1; /*!< reset_apb_adc_state */ + __IOM uint32_t APB_ADC_TRANS : 1; /*!< enable apb_adc use spi_dma */ + } bit; + } DMA_CONF; + + union { + __IOM uint32_t reg; /*!< Register */ + + struct { + __IM uint32_t APB_SARADC2_DATA : 17; /*!< need_des */ + uint32_t : 15; + } bit; + } SAR2_DATA_STATUS; + + union { + __IOM uint32_t reg; /*!< Register */ + + struct { + __IOM uint32_t CFG : 17; /*!< need_des */ + uint32_t : 15; + } bit; + } CALI; + + union { + __IOM uint32_t reg; /*!< Register */ + + struct { + __IOM uint32_t RND_ECO_LOW : 32; /*!< rnd eco low */ + } bit; + } RND_ECO_LOW; + + union { + __IOM uint32_t reg; /*!< Register */ + + struct { + __IOM uint32_t RND_ECO_HIGH : 32; /*!< rnd eco high */ + } bit; + } RND_ECO_HIGH; + + union { + __IOM uint32_t reg; /*!< Register */ + + struct { + __IOM uint32_t RND_ECO_EN : 1; /*!< need_des */ + __IM uint32_t RND_ECO_RESULT : 1; /*!< need_des */ + uint32_t : 30; + } bit; + } RND_ECO_CS; + __IM uint32_t RESERVED[225]; + + union { + __IOM uint32_t reg; /*!< Register */ + + struct { + __IOM uint32_t CTRL_DATE : 31; /*!< need_des */ + __IOM uint32_t CLK_EN : 1; /*!< need_des */ + } bit; + } CTRL_DATE; +} ADC_Type; /*!< Size = 1024 (0x400) */ + + + +/* =========================================================================================================================== */ +/* ================ AES ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief AES (Advanced Encryption Standard) Accelerator (AES) + */ + +typedef struct { /*!< AES Structure */ + + union { + __IOM uint32_t reg; /*!< Key material key_0 configure register */ + + struct { + __IOM uint32_t KEY_0 : 32; /*!< This bits stores key_0 that is a part of key material. */ + } bit; + } KEY_0; + + union { + __IOM uint32_t reg; /*!< Key material key_1 configure register */ + + struct { + __IOM uint32_t KEY_1 : 32; /*!< This bits stores key_1 that is a part of key material. */ + } bit; + } KEY_1; + + union { + __IOM uint32_t reg; /*!< Key material key_2 configure register */ + + struct { + __IOM uint32_t KEY_2 : 32; /*!< This bits stores key_2 that is a part of key material. */ + } bit; + } KEY_2; + + union { + __IOM uint32_t reg; /*!< Key material key_3 configure register */ + + struct { + __IOM uint32_t KEY_3 : 32; /*!< This bits stores key_3 that is a part of key material. */ + } bit; + } KEY_3; + + union { + __IOM uint32_t reg; /*!< Key material key_4 configure register */ + + struct { + __IOM uint32_t KEY_4 : 32; /*!< This bits stores key_4 that is a part of key material. */ + } bit; + } KEY_4; + + union { + __IOM uint32_t reg; /*!< Key material key_5 configure register */ + + struct { + __IOM uint32_t KEY_5 : 32; /*!< This bits stores key_5 that is a part of key material. */ + } bit; + } KEY_5; + + union { + __IOM uint32_t reg; /*!< Key material key_6 configure register */ + + struct { + __IOM uint32_t KEY_6 : 32; /*!< This bits stores key_6 that is a part of key material. */ + } bit; + } KEY_6; + + union { + __IOM uint32_t reg; /*!< Key material key_7 configure register */ + + struct { + __IOM uint32_t KEY_7 : 32; /*!< This bits stores key_7 that is a part of key material. */ + } bit; + } KEY_7; + + union { + __IOM uint32_t reg; /*!< source text material text_in_0 configure register */ + + struct { + __IOM uint32_t TEXT_IN_0 : 32; /*!< This bits stores text_in_0 that is a part of source text material. */ + } bit; + } TEXT_IN_0; + + union { + __IOM uint32_t reg; /*!< source text material text_in_1 configure register */ + + struct { + __IOM uint32_t TEXT_IN_1 : 32; /*!< This bits stores text_in_1 that is a part of source text material. */ + } bit; + } TEXT_IN_1; + + union { + __IOM uint32_t reg; /*!< source text material text_in_2 configure register */ + + struct { + __IOM uint32_t TEXT_IN_2 : 32; /*!< This bits stores text_in_2 that is a part of source text material. */ + } bit; + } TEXT_IN_2; + + union { + __IOM uint32_t reg; /*!< source text material text_in_3 configure register */ + + struct { + __IOM uint32_t TEXT_IN_3 : 32; /*!< This bits stores text_in_3 that is a part of source text material. */ + } bit; + } TEXT_IN_3; + + union { + __IOM uint32_t reg; /*!< result text material text_out_0 configure register */ + + struct { + __IOM uint32_t TEXT_OUT_0 : 32; /*!< This bits stores text_out_0 that is a part of result text material. */ + } bit; + } TEXT_OUT_0; + + union { + __IOM uint32_t reg; /*!< result text material text_out_1 configure register */ + + struct { + __IOM uint32_t TEXT_OUT_1 : 32; /*!< This bits stores text_out_1 that is a part of result text material. */ + } bit; + } TEXT_OUT_1; + + union { + __IOM uint32_t reg; /*!< result text material text_out_2 configure register */ + + struct { + __IOM uint32_t TEXT_OUT_2 : 32; /*!< This bits stores text_out_2 that is a part of result text material. */ + } bit; + } TEXT_OUT_2; + + union { + __IOM uint32_t reg; /*!< result text material text_out_3 configure register */ + + struct { + __IOM uint32_t TEXT_OUT_3 : 32; /*!< This bits stores text_out_3 that is a part of result text material. */ + } bit; + } TEXT_OUT_3; + + union { + __IOM uint32_t reg; /*!< AES Mode register */ + + struct { + __IOM uint32_t MODE : 3; /*!< This bits decides which one operation mode will be used. 3'd0: + AES-EN-128, 3'd1: AES-EN-192, 3'd2: AES-EN-256, 3'd4: AES-DE-128, + 3'd5: AES-DE-192, 3'd6: AES-DE-256. */ + uint32_t : 29; + } bit; + } MODE; + + union { + __IOM uint32_t reg; /*!< AES Endian configure register */ + + struct { + __IOM uint32_t ENDIAN : 6; /*!< endian. [1:0] key endian, [3:2] text_in endian or in_stream + endian, [5:4] text_out endian or out_stream endian */ + uint32_t : 26; + } bit; + } ENDIAN; + + union { + __IOM uint32_t reg; /*!< AES trigger register */ + + struct { + __OM uint32_t TRIGGER : 1; /*!< Set this bit to start AES calculation. */ + uint32_t : 31; + } bit; + } TRIGGER; + + union { + __IOM uint32_t reg; /*!< AES state register */ + + struct { + __IM uint32_t STATE : 2; /*!< Those bits shows AES status. For typical AES, 0: idle, 1: busy. + For DMA-AES, 0: idle, 1: busy, 2: calculation_done. */ + uint32_t : 30; + } bit; + } STATE; + __IOM uint32_t IV_MEM[4]; /*!< The memory that stores initialization vector */ + __IOM uint32_t H_MEM[4]; /*!< The memory that stores GCM hash subkey */ + __IOM uint32_t J0_MEM[4]; /*!< The memory that stores J0 */ + __IOM uint32_t T0_MEM[4]; /*!< The memory that stores T0 */ + + union { + __IOM uint32_t reg; /*!< DMA-AES working mode register */ + + struct { + __IOM uint32_t DMA_ENABLE : 1; /*!< 1'b0: typical AES working mode, 1'b1: DMA-AES working mode. */ + uint32_t : 31; + } bit; + } DMA_ENABLE; + + union { + __IOM uint32_t reg; /*!< AES cipher block mode register */ + + struct { + __IOM uint32_t BLOCK_MODE : 3; /*!< Those bits decides which block mode will be used. 0x0: ECB, + 0x1: CBC, 0x2: OFB, 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, + 0x6: GCM, 0x7: reserved. */ + uint32_t : 29; + } bit; + } BLOCK_MODE; + + union { + __IOM uint32_t reg; /*!< AES block number register */ + + struct { + __IOM uint32_t BLOCK_NUM : 32; /*!< Those bits stores the number of Plaintext/ciphertext block. */ + } bit; + } BLOCK_NUM; + + union { + __IOM uint32_t reg; /*!< Standard incrementing function configure register */ + + struct { + __IOM uint32_t INC_SEL : 1; /*!< This bit decides the standard incrementing function. 0: INC32. + 1: INC128. */ + uint32_t : 31; + } bit; + } INC_SEL; + + union { + __IOM uint32_t reg; /*!< Additional Authential Data block number register */ + + struct { + __IOM uint32_t AAD_BLOCK_NUM : 32; /*!< Those bits stores the number of AAD block. */ + } bit; + } AAD_BLOCK_NUM; + + union { + __IOM uint32_t reg; /*!< AES remainder bit number register */ + + struct { + __IOM uint32_t REMAINDER_BIT_NUM : 7; /*!< Those bits stores the number of remainder bit. */ + uint32_t : 25; + } bit; + } REMAINDER_BIT_NUM; + + union { + __IOM uint32_t reg; /*!< AES continue register */ + + struct { + __OM uint32_t CONTINUE : 1; /*!< Set this bit to continue GCM operation. */ + uint32_t : 31; + } bit; + } CONTINUE; + + union { + __IOM uint32_t reg; /*!< AES Interrupt clear register */ + + struct { + __OM uint32_t INT_CLEAR : 1; /*!< Set this bit to clear the AES interrupt. */ + uint32_t : 31; + } bit; + } INT_CLEAR; + + union { + __IOM uint32_t reg; /*!< AES Interrupt enable register */ + + struct { + __IOM uint32_t INT_ENA : 1; /*!< Set this bit to enable interrupt that occurs when DMA-AES calculation + is done. */ + uint32_t : 31; + } bit; + } INT_ENA; + + union { + __IOM uint32_t reg; /*!< AES version control register */ + + struct { + __IOM uint32_t DATE : 30; /*!< This bits stores the version information of AES. */ + uint32_t : 2; + } bit; + } DATE; + + union { + __IOM uint32_t reg; /*!< AES-DMA exit config */ + + struct { + __OM uint32_t DMA_EXIT : 1; /*!< Set this register to leave calculation done stage. Recommend + to use it after software finishes reading DMA's output + buffer. */ + uint32_t : 31; + } bit; + } DMA_EXIT; +} AES_Type; /*!< Size = 188 (0xbc) */ + + + +/* =========================================================================================================================== */ +/* ================ AHB_DMA ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief AHB_DMA Peripheral (AHB_DMA) + */ + +typedef struct { /*!< AHB_DMA Structure */ + + union { + __IOM uint32_t reg; /*!< Raw status interrupt of channel 0 */ + + struct { + __IOM uint32_t IN_DONE_CH_INT_RAW : 1; /*!< The raw interrupt bit turns to high level when the last data + pointed by one inlink descriptor has been received for + Rx channel 0. */ + __IOM uint32_t IN_SUC_EOF_CH_INT_RAW : 1; /*!< The raw interrupt bit turns to high level when the last data + pointed by one inlink descriptor has been received for + Rx channel 0. For UHCI0 the raw interrupt bit turns to + high level when the last data pointed by one inlink descriptor + has been received and no data error is detected for Rx + channel 0. */ + __IOM uint32_t IN_ERR_EOF_CH_INT_RAW : 1; /*!< The raw interrupt bit turns to high level when data error is + detected only in the case that the peripheral is UHCI0 + for Rx channel 0. For other peripherals this raw interrupt + is reserved. */ + __IOM uint32_t IN_DSCR_ERR_CH_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when detecting inlink + descriptor error including owner error and the second and + third word error of inlink descriptor for Rx channel 0. */ + __IOM uint32_t IN_DSCR_EMPTY_CH_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when Rx buffer pointed + by inlink is full and receiving data is not completed but + there is no more inlink for Rx channel 0. */ + __IOM uint32_t INFIFO_OVF_CH_INT_RAW : 1; /*!< This raw interrupt bit turns to high level when level 1 fifo + of Rx channel 0 is overflow. */ + __IOM uint32_t INFIFO_UDF_CH_INT_RAW : 1; /*!< This raw interrupt bit turns to high level when level 1 fifo + of Rx channel 0 is underflow. */ + uint32_t : 25; + } bit; + } IN_INT_RAW_CH0; + + union { + __IOM uint32_t reg; /*!< Masked interrupt of channel 0 */ + + struct { + __IM uint32_t IN_DONE_CH_INT_ST : 1; /*!< The raw interrupt status bit for the IN_DONE_CH_INT interrupt. */ + __IM uint32_t IN_SUC_EOF_CH_INT_ST : 1; /*!< The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. */ + __IM uint32_t IN_ERR_EOF_CH_INT_ST : 1; /*!< The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. */ + __IM uint32_t IN_DSCR_ERR_CH_INT_ST : 1; /*!< The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. */ + __IM uint32_t IN_DSCR_EMPTY_CH_INT_ST : 1;/*!< The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. */ + __IM uint32_t INFIFO_OVF_CH_INT_ST : 1; /*!< The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. */ + __IM uint32_t INFIFO_UDF_CH_INT_ST : 1; /*!< The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. */ + uint32_t : 25; + } bit; + } IN_INT_ST_CH0; + + union { + __IOM uint32_t reg; /*!< Interrupt enable bits of channel 0 */ + + struct { + __IOM uint32_t IN_DONE_CH_INT_ENA : 1; /*!< The interrupt enable bit for the IN_DONE_CH_INT interrupt. */ + __IOM uint32_t IN_SUC_EOF_CH_INT_ENA : 1; /*!< The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. */ + __IOM uint32_t IN_ERR_EOF_CH_INT_ENA : 1; /*!< The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. */ + __IOM uint32_t IN_DSCR_ERR_CH_INT_ENA : 1;/*!< The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. */ + __IOM uint32_t IN_DSCR_EMPTY_CH_INT_ENA : 1;/*!< The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. */ + __IOM uint32_t INFIFO_OVF_CH_INT_ENA : 1; /*!< The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. */ + __IOM uint32_t INFIFO_UDF_CH_INT_ENA : 1; /*!< The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. */ + uint32_t : 25; + } bit; + } IN_INT_ENA_CH0; + + union { + __IOM uint32_t reg; /*!< Interrupt clear bits of channel 0 */ + + struct { + __OM uint32_t IN_DONE_CH_INT_CLR : 1; /*!< Set this bit to clear the IN_DONE_CH_INT interrupt. */ + __OM uint32_t IN_SUC_EOF_CH_INT_CLR : 1; /*!< Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. */ + __OM uint32_t IN_ERR_EOF_CH_INT_CLR : 1; /*!< Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. */ + __OM uint32_t IN_DSCR_ERR_CH_INT_CLR : 1;/*!< Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. */ + __OM uint32_t IN_DSCR_EMPTY_CH_INT_CLR : 1;/*!< Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. */ + __OM uint32_t INFIFO_OVF_CH_INT_CLR : 1; /*!< Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. */ + __OM uint32_t INFIFO_UDF_CH_INT_CLR : 1; /*!< Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. */ + uint32_t : 25; + } bit; + } IN_INT_CLR_CH0; + __IM uint32_t RESERVED[8]; + + union { + __IOM uint32_t reg; /*!< Raw status interrupt of channel 0 */ + + struct { + __IOM uint32_t OUT_DONE_CH_INT_RAW : 1; /*!< The raw interrupt bit turns to high level when the last data + pointed by one outlink descriptor has been transmitted + to peripherals for Tx channel 0. */ + __IOM uint32_t OUT_EOF_CH_INT_RAW : 1; /*!< The raw interrupt bit turns to high level when the last data + pointed by one outlink descriptor has been read from memory + for Tx channel 0. */ + __IOM uint32_t OUT_DSCR_ERR_CH_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when detecting outlink + descriptor error including owner error and the second and + third word error of outlink descriptor for Tx channel 0. */ + __IOM uint32_t OUT_TOTAL_EOF_CH_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when data corresponding + a outlink (includes one link descriptor or few link descriptors) + is transmitted out for Tx channel 0. */ + __IOM uint32_t OUTFIFO_OVF_CH_INT_RAW : 1;/*!< This raw interrupt bit turns to high level when level 1 fifo + of Tx channel 0 is overflow. */ + __IOM uint32_t OUTFIFO_UDF_CH_INT_RAW : 1;/*!< This raw interrupt bit turns to high level when level 1 fifo + of Tx channel 0 is underflow. */ + uint32_t : 26; + } bit; + } OUT_INT_RAW_CH0; + + union { + __IOM uint32_t reg; /*!< Masked interrupt of channel 0 */ + + struct { + __IM uint32_t OUT_DONE_CH_INT_ST : 1; /*!< The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. */ + __IM uint32_t OUT_EOF_CH_INT_ST : 1; /*!< The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. */ + __IM uint32_t OUT_DSCR_ERR_CH_INT_ST : 1;/*!< The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. */ + __IM uint32_t OUT_TOTAL_EOF_CH_INT_ST : 1;/*!< The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. */ + __IM uint32_t OUTFIFO_OVF_CH_INT_ST : 1; /*!< The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. */ + __IM uint32_t OUTFIFO_UDF_CH_INT_ST : 1; /*!< The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. */ + uint32_t : 26; + } bit; + } OUT_INT_ST_CH0; + + union { + __IOM uint32_t reg; /*!< Interrupt enable bits of channel 0 */ + + struct { + __IOM uint32_t OUT_DONE_CH_INT_ENA : 1; /*!< The interrupt enable bit for the OUT_DONE_CH_INT interrupt. */ + __IOM uint32_t OUT_EOF_CH_INT_ENA : 1; /*!< The interrupt enable bit for the OUT_EOF_CH_INT interrupt. */ + __IOM uint32_t OUT_DSCR_ERR_CH_INT_ENA : 1;/*!< The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. */ + __IOM uint32_t OUT_TOTAL_EOF_CH_INT_ENA : 1;/*!< The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. */ + __IOM uint32_t OUTFIFO_OVF_CH_INT_ENA : 1;/*!< The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. */ + __IOM uint32_t OUTFIFO_UDF_CH_INT_ENA : 1;/*!< The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. */ + uint32_t : 26; + } bit; + } OUT_INT_ENA_CH0; + + union { + __IOM uint32_t reg; /*!< Interrupt clear bits of channel 0 */ + + struct { + __OM uint32_t OUT_DONE_CH_INT_CLR : 1; /*!< Set this bit to clear the OUT_DONE_CH_INT interrupt. */ + __OM uint32_t OUT_EOF_CH_INT_CLR : 1; /*!< Set this bit to clear the OUT_EOF_CH_INT interrupt. */ + __OM uint32_t OUT_DSCR_ERR_CH_INT_CLR : 1;/*!< Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. */ + __OM uint32_t OUT_TOTAL_EOF_CH_INT_CLR : 1;/*!< Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. */ + __OM uint32_t OUTFIFO_OVF_CH_INT_CLR : 1;/*!< Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. */ + __OM uint32_t OUTFIFO_UDF_CH_INT_CLR : 1;/*!< Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. */ + uint32_t : 26; + } bit; + } OUT_INT_CLR_CH0; + + union { + __IOM uint32_t reg; /*!< Raw status interrupt of channel 0 */ + + struct { + __IOM uint32_t IN_DONE_CH_INT_RAW : 1; /*!< The raw interrupt bit turns to high level when the last data + pointed by one inlink descriptor has been received for + Rx channel 0. */ + __IOM uint32_t IN_SUC_EOF_CH_INT_RAW : 1; /*!< The raw interrupt bit turns to high level when the last data + pointed by one inlink descriptor has been received for + Rx channel 0. For UHCI0 the raw interrupt bit turns to + high level when the last data pointed by one inlink descriptor + has been received and no data error is detected for Rx + channel 0. */ + __IOM uint32_t IN_ERR_EOF_CH_INT_RAW : 1; /*!< The raw interrupt bit turns to high level when data error is + detected only in the case that the peripheral is UHCI0 + for Rx channel 0. For other peripherals this raw interrupt + is reserved. */ + __IOM uint32_t IN_DSCR_ERR_CH_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when detecting inlink + descriptor error including owner error and the second and + third word error of inlink descriptor for Rx channel 0. */ + __IOM uint32_t IN_DSCR_EMPTY_CH_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when Rx buffer pointed + by inlink is full and receiving data is not completed but + there is no more inlink for Rx channel 0. */ + __IOM uint32_t INFIFO_OVF_CH_INT_RAW : 1; /*!< This raw interrupt bit turns to high level when level 1 fifo + of Rx channel 0 is overflow. */ + __IOM uint32_t INFIFO_UDF_CH_INT_RAW : 1; /*!< This raw interrupt bit turns to high level when level 1 fifo + of Rx channel 0 is underflow. */ + uint32_t : 25; + } bit; + } IN_INT_RAW_CH1; + + union { + __IOM uint32_t reg; /*!< Masked interrupt of channel 0 */ + + struct { + __IM uint32_t IN_DONE_CH_INT_ST : 1; /*!< The raw interrupt status bit for the IN_DONE_CH_INT interrupt. */ + __IM uint32_t IN_SUC_EOF_CH_INT_ST : 1; /*!< The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. */ + __IM uint32_t IN_ERR_EOF_CH_INT_ST : 1; /*!< The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. */ + __IM uint32_t IN_DSCR_ERR_CH_INT_ST : 1; /*!< The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. */ + __IM uint32_t IN_DSCR_EMPTY_CH_INT_ST : 1;/*!< The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. */ + __IM uint32_t INFIFO_OVF_CH_INT_ST : 1; /*!< The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. */ + __IM uint32_t INFIFO_UDF_CH_INT_ST : 1; /*!< The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. */ + uint32_t : 25; + } bit; + } IN_INT_ST_CH1; + + union { + __IOM uint32_t reg; /*!< Interrupt enable bits of channel 0 */ + + struct { + __IOM uint32_t IN_DONE_CH_INT_ENA : 1; /*!< The interrupt enable bit for the IN_DONE_CH_INT interrupt. */ + __IOM uint32_t IN_SUC_EOF_CH_INT_ENA : 1; /*!< The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. */ + __IOM uint32_t IN_ERR_EOF_CH_INT_ENA : 1; /*!< The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. */ + __IOM uint32_t IN_DSCR_ERR_CH_INT_ENA : 1;/*!< The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. */ + __IOM uint32_t IN_DSCR_EMPTY_CH_INT_ENA : 1;/*!< The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. */ + __IOM uint32_t INFIFO_OVF_CH_INT_ENA : 1; /*!< The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. */ + __IOM uint32_t INFIFO_UDF_CH_INT_ENA : 1; /*!< The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. */ + uint32_t : 25; + } bit; + } IN_INT_ENA_CH1; + + union { + __IOM uint32_t reg; /*!< Interrupt clear bits of channel 0 */ + + struct { + __OM uint32_t IN_DONE_CH_INT_CLR : 1; /*!< Set this bit to clear the IN_DONE_CH_INT interrupt. */ + __OM uint32_t IN_SUC_EOF_CH_INT_CLR : 1; /*!< Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. */ + __OM uint32_t IN_ERR_EOF_CH_INT_CLR : 1; /*!< Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. */ + __OM uint32_t IN_DSCR_ERR_CH_INT_CLR : 1;/*!< Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. */ + __OM uint32_t IN_DSCR_EMPTY_CH_INT_CLR : 1;/*!< Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. */ + __OM uint32_t INFIFO_OVF_CH_INT_CLR : 1; /*!< Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. */ + __OM uint32_t INFIFO_UDF_CH_INT_CLR : 1; /*!< Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. */ + uint32_t : 25; + } bit; + } IN_INT_CLR_CH1; + __IM uint32_t RESERVED1[4]; + + union { + __IOM uint32_t reg; /*!< reserved */ + + struct { + __IOM uint32_t AHB_TESTMODE : 3; /*!< reserved */ + uint32_t : 1; + __IOM uint32_t AHB_TESTADDR : 2; /*!< reserved */ + uint32_t : 26; + } bit; + } AHB_TEST; + + union { + __IOM uint32_t reg; /*!< MISC register */ + + struct { + __IOM uint32_t AHBM_RST_INTER : 1; /*!< Set this bit then clear this bit to reset the internal ahb FSM. */ + uint32_t : 1; + __IOM uint32_t ARB_PRI_DIS : 1; /*!< Set this bit to disable priority arbitration function. */ + __IOM uint32_t CLK_EN : 1; /*!< 1'h1: Force clock on for register. 1'h0: Support clock only + when application writes registers. */ + uint32_t : 28; + } bit; + } MISC_CONF; + + union { + __IOM uint32_t reg; /*!< Version control register */ + + struct { + __IOM uint32_t DATE : 32; /*!< register version. */ + } bit; + } DATE; + __IM uint32_t RESERVED2; + + union { + union { + __IOM uint32_t reg; /*!< Raw status interrupt of channel 0 */ + + struct { + __IOM uint32_t OUT_DONE_CH_INT_RAW : 1; /*!< The raw interrupt bit turns to high level when the last data + pointed by one outlink descriptor has been transmitted + to peripherals for Tx channel 0. */ + __IOM uint32_t OUT_EOF_CH_INT_RAW : 1; /*!< The raw interrupt bit turns to high level when the last data + pointed by one outlink descriptor has been read from memory + for Tx channel 0. */ + __IOM uint32_t OUT_DSCR_ERR_CH_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when detecting outlink + descriptor error including owner error and the second and + third word error of outlink descriptor for Tx channel 0. */ + __IOM uint32_t OUT_TOTAL_EOF_CH_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when data corresponding + a outlink (includes one link descriptor or few link descriptors) + is transmitted out for Tx channel 0. */ + __IOM uint32_t OUTFIFO_OVF_CH_INT_RAW : 1;/*!< This raw interrupt bit turns to high level when level 1 fifo + of Tx channel 0 is overflow. */ + __IOM uint32_t OUTFIFO_UDF_CH_INT_RAW : 1;/*!< This raw interrupt bit turns to high level when level 1 fifo + of Tx channel 0 is underflow. */ + uint32_t : 26; + } bit; + } OUT_INT_RAW_CH1; + + union { + __IOM uint32_t reg; /*!< Configure 0 register of Rx channel 0 */ + + struct { + __IOM uint32_t IN_RST_CH : 1; /*!< This bit is used to reset AHB_DMA channel 0 Rx FSM and Rx FIFO + pointer. */ + __IOM uint32_t IN_LOOP_TEST_CH : 1; /*!< reserved */ + __IOM uint32_t INDSCR_BURST_EN_CH : 1; /*!< Set this bit to 1 to enable INCR burst transfer for Rx channel + 0 reading link descriptor when accessing internal SRAM. */ + __IOM uint32_t IN_DATA_BURST_EN_CH : 1; /*!< Set this bit to 1 to enable INCR burst transfer for Rx channel + 0 receiving data when accessing internal SRAM. */ + __IOM uint32_t MEM_TRANS_EN_CH : 1; /*!< Set this bit 1 to enable automatic transmitting data from memory + to memory via AHB_DMA. */ + __IOM uint32_t IN_ETM_EN_CH : 1; /*!< Set this bit to 1 to enable etm control mode, dma Rx channel + 0 is triggered by etm task. */ + uint32_t : 26; + } bit; + } IN_CONF0_CH0; + }; + + union { + union { + __IOM uint32_t reg; /*!< Masked interrupt of channel 0 */ + + struct { + __IM uint32_t OUT_DONE_CH_INT_ST : 1; /*!< The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. */ + __IM uint32_t OUT_EOF_CH_INT_ST : 1; /*!< The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. */ + __IM uint32_t OUT_DSCR_ERR_CH_INT_ST : 1;/*!< The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. */ + __IM uint32_t OUT_TOTAL_EOF_CH_INT_ST : 1;/*!< The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. */ + __IM uint32_t OUTFIFO_OVF_CH_INT_ST : 1;/*!< The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. */ + __IM uint32_t OUTFIFO_UDF_CH_INT_ST : 1;/*!< The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. */ + uint32_t : 26; + } bit; + } OUT_INT_ST_CH1; + + union { + __IOM uint32_t reg; /*!< Configure 1 register of Rx channel 0 */ + + struct { + uint32_t : 12; + __IOM uint32_t IN_CHECK_OWNER_CH : 1; /*!< Set this bit to enable checking the owner attribute of the link + descriptor. */ + uint32_t : 19; + } bit; + } IN_CONF1_CH0; + }; + + union { + union { + __IOM uint32_t reg; /*!< Interrupt enable bits of channel 0 */ + + struct { + __IOM uint32_t OUT_DONE_CH_INT_ENA : 1; /*!< The interrupt enable bit for the OUT_DONE_CH_INT interrupt. */ + __IOM uint32_t OUT_EOF_CH_INT_ENA : 1; /*!< The interrupt enable bit for the OUT_EOF_CH_INT interrupt. */ + __IOM uint32_t OUT_DSCR_ERR_CH_INT_ENA : 1;/*!< The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. */ + __IOM uint32_t OUT_TOTAL_EOF_CH_INT_ENA : 1;/*!< The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. */ + __IOM uint32_t OUTFIFO_OVF_CH_INT_ENA : 1;/*!< The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. */ + __IOM uint32_t OUTFIFO_UDF_CH_INT_ENA : 1;/*!< The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. */ + uint32_t : 26; + } bit; + } OUT_INT_ENA_CH1; + + union { + __IOM uint32_t reg; /*!< Receive FIFO status of Rx channel 0 */ + + struct { + __IM uint32_t INFIFO_FULL_CH : 1; /*!< L1 Rx FIFO full signal for Rx channel 0. */ + __IM uint32_t INFIFO_EMPTY_CH : 1; /*!< L1 Rx FIFO empty signal for Rx channel 0. */ + __IM uint32_t INFIFO_CNT_CH : 6; /*!< The register stores the byte number of the data in L1 Rx FIFO + for Rx channel 0. */ + uint32_t : 15; + __IM uint32_t IN_REMAIN_UNDER_1B_CH : 1;/*!< reserved */ + __IM uint32_t IN_REMAIN_UNDER_2B_CH : 1;/*!< reserved */ + __IM uint32_t IN_REMAIN_UNDER_3B_CH : 1;/*!< reserved */ + __IM uint32_t IN_REMAIN_UNDER_4B_CH : 1;/*!< reserved */ + __IM uint32_t IN_BUF_HUNGRY_CH : 1; /*!< reserved */ + uint32_t : 4; + } bit; + } INFIFO_STATUS_CH0; + }; + + union { + union { + __IOM uint32_t reg; /*!< Interrupt clear bits of channel 0 */ + + struct { + __OM uint32_t OUT_DONE_CH_INT_CLR : 1; /*!< Set this bit to clear the OUT_DONE_CH_INT interrupt. */ + __OM uint32_t OUT_EOF_CH_INT_CLR : 1; /*!< Set this bit to clear the OUT_EOF_CH_INT interrupt. */ + __OM uint32_t OUT_DSCR_ERR_CH_INT_CLR : 1;/*!< Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. */ + __OM uint32_t OUT_TOTAL_EOF_CH_INT_CLR : 1;/*!< Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. */ + __OM uint32_t OUTFIFO_OVF_CH_INT_CLR : 1;/*!< Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. */ + __OM uint32_t OUTFIFO_UDF_CH_INT_CLR : 1;/*!< Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. */ + uint32_t : 26; + } bit; + } OUT_INT_CLR_CH1; + + union { + __IOM uint32_t reg; /*!< Pop control register of Rx channel 0 */ + + struct { + __IM uint32_t INFIFO_RDATA_CH : 12; /*!< This register stores the data popping from AHB_DMA FIFO. */ + __OM uint32_t INFIFO_POP_CH : 1; /*!< Set this bit to pop data from AHB_DMA FIFO. */ + uint32_t : 19; + } bit; + } IN_POP_CH0; + }; + + union { + union { + __IOM uint32_t reg; /*!< Raw status interrupt of channel 0 */ + + struct { + __IOM uint32_t IN_DONE_CH_INT_RAW : 1; /*!< The raw interrupt bit turns to high level when the last data + pointed by one inlink descriptor has been received for + Rx channel 0. */ + __IOM uint32_t IN_SUC_EOF_CH_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when the last data + pointed by one inlink descriptor has been received for + Rx channel 0. For UHCI0 the raw interrupt bit turns to + high level when the last data pointed by one inlink descriptor + has been received and no data error is detected for Rx + channel 0. */ + __IOM uint32_t IN_ERR_EOF_CH_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when data error is + detected only in the case that the peripheral is UHCI0 + for Rx channel 0. For other peripherals this raw interrupt + is reserved. */ + __IOM uint32_t IN_DSCR_ERR_CH_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when detecting inlink + descriptor error including owner error and the second and + third word error of inlink descriptor for Rx channel 0. */ + __IOM uint32_t IN_DSCR_EMPTY_CH_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when Rx buffer pointed + by inlink is full and receiving data is not completed but + there is no more inlink for Rx channel 0. */ + __IOM uint32_t INFIFO_OVF_CH_INT_RAW : 1;/*!< This raw interrupt bit turns to high level when level 1 fifo + of Rx channel 0 is overflow. */ + __IOM uint32_t INFIFO_UDF_CH_INT_RAW : 1;/*!< This raw interrupt bit turns to high level when level 1 fifo + of Rx channel 0 is underflow. */ + uint32_t : 25; + } bit; + } IN_INT_RAW_CH2; + + union { + __IOM uint32_t reg; /*!< Link descriptor configure and control register of Rx channel + 0 */ + + struct { + __IOM uint32_t INLINK_AUTO_RET_CH : 1; /*!< Set this bit to return to current inlink descriptor's address + when there are some errors in current receiving data. */ + __OM uint32_t INLINK_STOP_CH : 1; /*!< Set this bit to stop dealing with the inlink descriptors. */ + __OM uint32_t INLINK_START_CH : 1; /*!< Set this bit to start dealing with the inlink descriptors. */ + __OM uint32_t INLINK_RESTART_CH : 1; /*!< Set this bit to mount a new inlink descriptor. */ + __IM uint32_t INLINK_PARK_CH : 1; /*!< 1: the inlink descriptor's FSM is in idle state. 0: the inlink + descriptor's FSM is working. */ + uint32_t : 27; + } bit; + } IN_LINK_CH0; + }; + + union { + union { + __IOM uint32_t reg; /*!< Masked interrupt of channel 0 */ + + struct { + __IM uint32_t IN_DONE_CH_INT_ST : 1; /*!< The raw interrupt status bit for the IN_DONE_CH_INT interrupt. */ + __IM uint32_t IN_SUC_EOF_CH_INT_ST : 1;/*!< The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. */ + __IM uint32_t IN_ERR_EOF_CH_INT_ST : 1;/*!< The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. */ + __IM uint32_t IN_DSCR_ERR_CH_INT_ST : 1;/*!< The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. */ + __IM uint32_t IN_DSCR_EMPTY_CH_INT_ST : 1;/*!< The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. */ + __IM uint32_t INFIFO_OVF_CH_INT_ST : 1;/*!< The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. */ + __IM uint32_t INFIFO_UDF_CH_INT_ST : 1;/*!< The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. */ + uint32_t : 25; + } bit; + } IN_INT_ST_CH2; + + union { + __IOM uint32_t reg; /*!< Receive status of Rx channel 0 */ + + struct { + __IM uint32_t INLINK_DSCR_ADDR_CH : 18;/*!< This register stores the current inlink descriptor's address. */ + __IM uint32_t IN_DSCR_STATE_CH : 2; /*!< reserved */ + __IM uint32_t IN_STATE_CH : 3; /*!< reserved */ + uint32_t : 9; + } bit; + } IN_STATE_CH0; + }; + + union { + union { + __IOM uint32_t reg; /*!< Interrupt enable bits of channel 0 */ + + struct { + __IOM uint32_t IN_DONE_CH_INT_ENA : 1; /*!< The interrupt enable bit for the IN_DONE_CH_INT interrupt. */ + __IOM uint32_t IN_SUC_EOF_CH_INT_ENA : 1;/*!< The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. */ + __IOM uint32_t IN_ERR_EOF_CH_INT_ENA : 1;/*!< The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. */ + __IOM uint32_t IN_DSCR_ERR_CH_INT_ENA : 1;/*!< The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. */ + __IOM uint32_t IN_DSCR_EMPTY_CH_INT_ENA : 1;/*!< The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. */ + __IOM uint32_t INFIFO_OVF_CH_INT_ENA : 1;/*!< The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. */ + __IOM uint32_t INFIFO_UDF_CH_INT_ENA : 1;/*!< The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. */ + uint32_t : 25; + } bit; + } IN_INT_ENA_CH2; + + union { + __IOM uint32_t reg; /*!< Inlink descriptor address when EOF occurs of Rx channel 0 */ + + struct { + __IM uint32_t IN_SUC_EOF_DES_ADDR_CH : 32;/*!< This register stores the address of the inlink descriptor when + the EOF bit in this descriptor is 1. */ + } bit; + } IN_SUC_EOF_DES_ADDR_CH0; + }; + + union { + union { + __IOM uint32_t reg; /*!< Interrupt clear bits of channel 0 */ + + struct { + __OM uint32_t IN_DONE_CH_INT_CLR : 1; /*!< Set this bit to clear the IN_DONE_CH_INT interrupt. */ + __OM uint32_t IN_SUC_EOF_CH_INT_CLR : 1;/*!< Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. */ + __OM uint32_t IN_ERR_EOF_CH_INT_CLR : 1;/*!< Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. */ + __OM uint32_t IN_DSCR_ERR_CH_INT_CLR : 1;/*!< Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. */ + __OM uint32_t IN_DSCR_EMPTY_CH_INT_CLR : 1;/*!< Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. */ + __OM uint32_t INFIFO_OVF_CH_INT_CLR : 1;/*!< Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. */ + __OM uint32_t INFIFO_UDF_CH_INT_CLR : 1;/*!< Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. */ + uint32_t : 25; + } bit; + } IN_INT_CLR_CH2; + + union { + __IOM uint32_t reg; /*!< Inlink descriptor address when errors occur of Rx channel 0 */ + + struct { + __IM uint32_t IN_ERR_EOF_DES_ADDR_CH : 32;/*!< This register stores the address of the inlink descriptor when + there are some errors in current receiving data. Only used + when peripheral is UHCI0. */ + } bit; + } IN_ERR_EOF_DES_ADDR_CH0; + }; + + union { + __IOM uint32_t reg; /*!< Current inlink descriptor address of Rx channel 0 */ + + struct { + __IM uint32_t INLINK_DSCR_CH : 32; /*!< The address of the current inlink descriptor x. */ + } bit; + } IN_DSCR_CH0; + + union { + __IOM uint32_t reg; /*!< The last inlink descriptor address of Rx channel 0 */ + + struct { + __IM uint32_t INLINK_DSCR_BF0_CH : 32; /*!< The address of the last inlink descriptor x-1. */ + } bit; + } IN_DSCR_BF0_CH0; + + union { + __IOM uint32_t reg; /*!< The second-to-last inlink descriptor address of Rx channel 0 */ + + struct { + __IM uint32_t INLINK_DSCR_BF1_CH : 32; /*!< The address of the second-to-last inlink descriptor x-2. */ + } bit; + } IN_DSCR_BF1_CH0; + + union { + __IOM uint32_t reg; /*!< Priority register of Rx channel 0 */ + + struct { + __IOM uint32_t RX_PRI_CH : 4; /*!< The priority of Rx channel 0. The larger of the value the higher + of the priority. */ + uint32_t : 28; + } bit; + } IN_PRI_CH0; + + union { + __IOM uint32_t reg; /*!< Peripheral selection of Rx channel 0 */ + + struct { + __IOM uint32_t PERI_IN_SEL_CH : 6; /*!< This register is used to select peripheral for Rx channel 0. + I3C. 1: Dummy. 2: UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: + Dummy. 7: Dummy. 8: ADC_DAC. 9: Dummy. 10: RMT,11~15: Dummy */ + uint32_t : 26; + } bit; + } IN_PERI_SEL_CH0; + __IM uint32_t RESERVED3[3]; + + union { + __IOM uint32_t reg; /*!< Raw status interrupt of channel 0 */ + + struct { + __IOM uint32_t OUT_DONE_CH_INT_RAW : 1; /*!< The raw interrupt bit turns to high level when the last data + pointed by one outlink descriptor has been transmitted + to peripherals for Tx channel 0. */ + __IOM uint32_t OUT_EOF_CH_INT_RAW : 1; /*!< The raw interrupt bit turns to high level when the last data + pointed by one outlink descriptor has been read from memory + for Tx channel 0. */ + __IOM uint32_t OUT_DSCR_ERR_CH_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when detecting outlink + descriptor error including owner error and the second and + third word error of outlink descriptor for Tx channel 0. */ + __IOM uint32_t OUT_TOTAL_EOF_CH_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when data corresponding + a outlink (includes one link descriptor or few link descriptors) + is transmitted out for Tx channel 0. */ + __IOM uint32_t OUTFIFO_OVF_CH_INT_RAW : 1;/*!< This raw interrupt bit turns to high level when level 1 fifo + of Tx channel 0 is overflow. */ + __IOM uint32_t OUTFIFO_UDF_CH_INT_RAW : 1;/*!< This raw interrupt bit turns to high level when level 1 fifo + of Tx channel 0 is underflow. */ + uint32_t : 26; + } bit; + } OUT_INT_RAW_CH2; + + union { + __IOM uint32_t reg; /*!< Masked interrupt of channel 0 */ + + struct { + __IM uint32_t OUT_DONE_CH_INT_ST : 1; /*!< The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. */ + __IM uint32_t OUT_EOF_CH_INT_ST : 1; /*!< The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. */ + __IM uint32_t OUT_DSCR_ERR_CH_INT_ST : 1;/*!< The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. */ + __IM uint32_t OUT_TOTAL_EOF_CH_INT_ST : 1;/*!< The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. */ + __IM uint32_t OUTFIFO_OVF_CH_INT_ST : 1; /*!< The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. */ + __IM uint32_t OUTFIFO_UDF_CH_INT_ST : 1; /*!< The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. */ + uint32_t : 26; + } bit; + } OUT_INT_ST_CH2; + + union { + __IOM uint32_t reg; /*!< Interrupt enable bits of channel 0 */ + + struct { + __IOM uint32_t OUT_DONE_CH_INT_ENA : 1; /*!< The interrupt enable bit for the OUT_DONE_CH_INT interrupt. */ + __IOM uint32_t OUT_EOF_CH_INT_ENA : 1; /*!< The interrupt enable bit for the OUT_EOF_CH_INT interrupt. */ + __IOM uint32_t OUT_DSCR_ERR_CH_INT_ENA : 1;/*!< The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. */ + __IOM uint32_t OUT_TOTAL_EOF_CH_INT_ENA : 1;/*!< The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. */ + __IOM uint32_t OUTFIFO_OVF_CH_INT_ENA : 1;/*!< The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. */ + __IOM uint32_t OUTFIFO_UDF_CH_INT_ENA : 1;/*!< The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. */ + uint32_t : 26; + } bit; + } OUT_INT_ENA_CH2; + + union { + __IOM uint32_t reg; /*!< Interrupt clear bits of channel 0 */ + + struct { + __OM uint32_t OUT_DONE_CH_INT_CLR : 1; /*!< Set this bit to clear the OUT_DONE_CH_INT interrupt. */ + __OM uint32_t OUT_EOF_CH_INT_CLR : 1; /*!< Set this bit to clear the OUT_EOF_CH_INT interrupt. */ + __OM uint32_t OUT_DSCR_ERR_CH_INT_CLR : 1;/*!< Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. */ + __OM uint32_t OUT_TOTAL_EOF_CH_INT_CLR : 1;/*!< Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. */ + __OM uint32_t OUTFIFO_OVF_CH_INT_CLR : 1;/*!< Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. */ + __OM uint32_t OUTFIFO_UDF_CH_INT_CLR : 1;/*!< Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. */ + uint32_t : 26; + } bit; + } OUT_INT_CLR_CH2; + __IM uint32_t RESERVED4[4]; + + union { + __IOM uint32_t reg; /*!< Configure 0 register of Tx channel 0 */ + + struct { + __IOM uint32_t OUT_RST_CH0 : 1; /*!< This bit is used to reset AHB_DMA channel 0 Tx FSM and Tx FIFO + pointer. */ + __IOM uint32_t OUT_LOOP_TEST_CH0 : 1; /*!< reserved */ + __IOM uint32_t OUT_AUTO_WRBACK_CH0 : 1; /*!< Set this bit to enable automatic outlink-writeback when all + the data in tx buffer has been transmitted. */ + __IOM uint32_t OUT_EOF_MODE_CH0 : 1; /*!< EOF flag generation mode when transmitting data. 1: EOF flag + for Tx channel 0 is generated when data need to transmit + has been popped from FIFO in AHB_DMA */ + __IOM uint32_t OUTDSCR_BURST_EN_CH0 : 1; /*!< Set this bit to 1 to enable INCR burst transfer for Tx channel + 0 reading link descriptor when accessing internal SRAM. */ + __IOM uint32_t OUT_DATA_BURST_EN_CH0 : 1; /*!< Set this bit to 1 to enable INCR burst transfer for Tx channel + 0 transmitting data when accessing internal SRAM. */ + __IOM uint32_t OUT_ETM_EN_CH0 : 1; /*!< Set this bit to 1 to enable etm control mode, dma Tx channel + 0 is triggered by etm task. */ + uint32_t : 25; + } bit; + } OUT_CONF0_CH0; + + union { + __IOM uint32_t reg; /*!< Configure 1 register of Tx channel 0 */ + + struct { + uint32_t : 12; + __IOM uint32_t OUT_CHECK_OWNER_CH : 1; /*!< Set this bit to enable checking the owner attribute of the link + descriptor. */ + uint32_t : 19; + } bit; + } OUT_CONF1_CH0; + + union { + __IOM uint32_t reg; /*!< Transmit FIFO status of Tx channel 0 */ + + struct { + __IM uint32_t OUTFIFO_FULL_CH : 1; /*!< L1 Tx FIFO full signal for Tx channel 0. */ + __IM uint32_t OUTFIFO_EMPTY_CH : 1; /*!< L1 Tx FIFO empty signal for Tx channel 0. */ + __IM uint32_t OUTFIFO_CNT_CH : 6; /*!< The register stores the byte number of the data in L1 Tx FIFO + for Tx channel 0. */ + uint32_t : 15; + __IM uint32_t OUT_REMAIN_UNDER_1B_CH : 1;/*!< reserved */ + __IM uint32_t OUT_REMAIN_UNDER_2B_CH : 1;/*!< reserved */ + __IM uint32_t OUT_REMAIN_UNDER_3B_CH : 1;/*!< reserved */ + __IM uint32_t OUT_REMAIN_UNDER_4B_CH : 1;/*!< reserved */ + uint32_t : 5; + } bit; + } OUTFIFO_STATUS_CH0; + + union { + __IOM uint32_t reg; /*!< Push control register of Rx channel 0 */ + + struct { + __IOM uint32_t OUTFIFO_WDATA_CH : 9; /*!< This register stores the data that need to be pushed into AHB_DMA + FIFO. */ + __OM uint32_t OUTFIFO_PUSH_CH : 1; /*!< Set this bit to push data into AHB_DMA FIFO. */ + uint32_t : 22; + } bit; + } OUT_PUSH_CH0; + + union { + __IOM uint32_t reg; /*!< Link descriptor configure and control register of Tx channel + 0 */ + + struct { + __OM uint32_t OUTLINK_STOP_CH : 1; /*!< Set this bit to stop dealing with the outlink descriptors. */ + __OM uint32_t OUTLINK_START_CH : 1; /*!< Set this bit to start dealing with the outlink descriptors. */ + __OM uint32_t OUTLINK_RESTART_CH : 1; /*!< Set this bit to restart a new outlink from the last address. */ + __IM uint32_t OUTLINK_PARK_CH : 1; /*!< 1: the outlink descriptor's FSM is in idle state. 0: the outlink + descriptor's FSM is working. */ + uint32_t : 28; + } bit; + } OUT_LINK_CH0; + + union { + __IOM uint32_t reg; /*!< Transmit status of Tx channel 0 */ + + struct { + __IM uint32_t OUTLINK_DSCR_ADDR_CH : 18; /*!< This register stores the current outlink descriptor's address. */ + __IM uint32_t OUT_DSCR_STATE_CH : 2; /*!< reserved */ + __IM uint32_t OUT_STATE_CH : 3; /*!< reserved */ + uint32_t : 9; + } bit; + } OUT_STATE_CH0; + + union { + __IOM uint32_t reg; /*!< Outlink descriptor address when EOF occurs of Tx channel 0 */ + + struct { + __IM uint32_t OUT_EOF_DES_ADDR_CH : 32; /*!< This register stores the address of the outlink descriptor when + the EOF bit in this descriptor is 1. */ + } bit; + } OUT_EOF_DES_ADDR_CH0; + + union { + __IOM uint32_t reg; /*!< The last outlink descriptor address when EOF occurs of Tx channel + 0 */ + + struct { + __IM uint32_t OUT_EOF_BFR_DES_ADDR_CH : 32;/*!< This register stores the address of the outlink descriptor before + the last outlink descriptor. */ + } bit; + } OUT_EOF_BFR_DES_ADDR_CH0; + + union { + __IOM uint32_t reg; /*!< Current inlink descriptor address of Tx channel 0 */ + + struct { + __IM uint32_t OUTLINK_DSCR_CH : 32; /*!< The address of the current outlink descriptor y. */ + } bit; + } OUT_DSCR_CH0; + + union { + __IOM uint32_t reg; /*!< The last inlink descriptor address of Tx channel 0 */ + + struct { + __IM uint32_t OUTLINK_DSCR_BF0_CH : 32; /*!< The address of the last outlink descriptor y-1. */ + } bit; + } OUT_DSCR_BF0_CH0; + + union { + __IOM uint32_t reg; /*!< The second-to-last inlink descriptor address of Tx channel 0 */ + + struct { + __IM uint32_t OUTLINK_DSCR_BF1_CH : 32; /*!< The address of the second-to-last inlink descriptor x-2. */ + } bit; + } OUT_DSCR_BF1_CH0; + + union { + __IOM uint32_t reg; /*!< Priority register of Tx channel 0. */ + + struct { + __IOM uint32_t TX_PRI_CH : 4; /*!< The priority of Tx channel 0. The larger of the value the higher + of the priority. */ + uint32_t : 28; + } bit; + } OUT_PRI_CH0; + + union { + __IOM uint32_t reg; /*!< Peripheral selection of Tx channel 0 */ + + struct { + __IOM uint32_t PERI_OUT_SEL_CH : 6; /*!< This register is used to select peripheral for Tx channel 0. + I3C. 1: Dummy. 2: UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: + Dummy. 7: Dummy. 8: ADC_DAC. 9: Dummy. 10: RMT,11~15: Dummy */ + uint32_t : 26; + } bit; + } OUT_PERI_SEL_CH0; + __IM uint32_t RESERVED5[110]; + + union { + __IOM uint32_t reg; /*!< This register is used to config ch0 crc initial data(max 32 + bit) */ + + struct { + __IOM uint32_t OUT_CRC_INIT_DATA_CH : 32; /*!< This register is used to config ch0 of tx crc initial value */ + } bit; + } OUT_CRC_INIT_DATA_CH0; + + union { + __IOM uint32_t reg; /*!< This register is used to confiig tx ch0 crc result width,2'b00 + mean crc_width <=8bit,2'b01 8 reg_vdisp+reg_vsync+reg_vbank */ + uint32_t : 4; + __IOM uint32_t VDISP : 12; /*!< this field configures the length of valid line (by line) for + dpi output */ + uint32_t : 4; + } bit; + } DPI_V_CFG0; + + union { + __IOM uint32_t reg; /*!< dsi bridge dpi v config register 1 */ + + struct { + __IOM uint32_t VBANK : 12; /*!< this field configures the length between vsync and valid line + (by line) for dpi output */ + uint32_t : 4; + __IOM uint32_t VSYNC : 12; /*!< this field configures the length of vsync (by line) for dpi + output */ + uint32_t : 4; + } bit; + } DPI_V_CFG1; + + union { + __IOM uint32_t reg; /*!< dsi bridge dpi h config register 0 */ + + struct { + __IOM uint32_t HTOTAL : 12; /*!< this field configures the total length of one line (by pixel + num) for dpi output, must meet: reg_htotal > reg_hdisp+reg_hsync+reg_hban + */ + uint32_t : 4; + __IOM uint32_t HDISP : 12; /*!< this field configures the length of valid pixel data (by pixel + num) for dpi output */ + uint32_t : 4; + } bit; + } DPI_H_CFG0; + + union { + __IOM uint32_t reg; /*!< dsi bridge dpi h config register 1 */ + + struct { + __IOM uint32_t HBANK : 12; /*!< this field configures the length between hsync and pixel data + valid (by pixel num) for dpi output */ + uint32_t : 4; + __IOM uint32_t HSYNC : 12; /*!< this field configures the length of hsync (by pixel num) for + dpi output */ + uint32_t : 4; + } bit; + } DPI_H_CFG1; + + union { + __IOM uint32_t reg; /*!< dsi_bridge dpi misc config register */ + + struct { + __IOM uint32_t DPI_EN : 1; /*!< this bit configures enable of dpi output, 0: disable, 1: enable */ + uint32_t : 3; + __IOM uint32_t FIFO_UNDERRUN_DISCARD_VCNT : 12;/*!< this field configures the underrun interrupt musk, when underrun + occurs and line cnt is less then this field */ + uint32_t : 16; + } bit; + } DPI_MISC_CONFIG; + + union { + __IOM uint32_t reg; /*!< dsi_bridge dpi config update register */ + + struct { + __OM uint32_t DPI_CONFIG_UPDATE : 1; /*!< write 1 to this bit to update dpi config register MIPI_DSI_BRG_DPI_* */ + uint32_t : 31; + } bit; + } DPI_CONFIG_UPDATE; + __IM uint32_t RESERVED1[2]; + + union { + __IOM uint32_t reg; /*!< dsi_bridge interrupt enable register */ + + struct { + __IOM uint32_t UNDERRUN_INT_ENA : 1; /*!< write 1 to enables dpi_underrun_int_st field of MIPI_DSI_BRG_INT_ST_REG + controlled by dpi_underrun interrupt signal */ + uint32_t : 31; + } bit; + } INT_ENA; + + union { + __IOM uint32_t reg; /*!< dsi_bridge interrupt clear register */ + + struct { + __OM uint32_t UNDERRUN_INT_CLR : 1; /*!< write 1 to this bit to clear dpi_underrun_int_raw field of MIPI_DSI_BRG_INT_RA + _REG */ + uint32_t : 31; + } bit; + } INT_CLR; + + union { + __IOM uint32_t reg; /*!< dsi_bridge raw interrupt register */ + + struct { + __IOM uint32_t UNDERRUN_INT_RAW : 1; /*!< the raw interrupt status of dpi_underrun */ + uint32_t : 31; + } bit; + } INT_RAW; + + union { + __IOM uint32_t reg; /*!< dsi_bridge masked interrupt register */ + + struct { + __IM uint32_t UNDERRUN_INT_ST : 1; /*!< the masked interrupt status of dpi_underrun */ + uint32_t : 31; + } bit; + } INT_ST; + + union { + __IOM uint32_t reg; /*!< dsi_bridge host bist control register */ + + struct { + __IM uint32_t BISTOK : 1; /*!< bistok */ + __IOM uint32_t BISTON : 1; /*!< biston */ + uint32_t : 30; + } bit; + } HOST_BIST_CTL; + + union { + __IOM uint32_t reg; /*!< dsi_bridge host trigger reverse control register */ + + struct { + __IOM uint32_t TX_TRIGGER_REV_EN : 1; /*!< tx_trigger reverse. 0: disable, 1: enable */ + __IOM uint32_t RX_TRIGGER_REV_EN : 1; /*!< rx_trigger reverse. 0: disable, 1: enable */ + uint32_t : 30; + } bit; + } HOST_TRIGGER_REV; + + union { + __IOM uint32_t reg; /*!< dsi_bridge block raw number control register */ + + struct { + __IOM uint32_t BLK_RAW_NUM_TOTAL : 22; /*!< this field configures number of total block pix bits/64 */ + uint32_t : 9; + __OM uint32_t BLK_RAW_NUM_TOTAL_SET : 1; /*!< write 1 to reload reg_blk_raw_num_total to internal cnt */ + } bit; + } BLK_RAW_NUM_CFG; + + union { + __IOM uint32_t reg; /*!< dsi_bridge dam frame interval control register */ + + struct { + __IOM uint32_t DMA_FRAME_SLOT : 10; /*!< this field configures the max frame_slot_cnt */ + __IOM uint32_t DMA_FRAME_INTERVAL : 18; /*!< this field configures the max frame_interval_cnt, frame_interval_cnt + increased by 1 when frame_slot_cnt if full */ + __IOM uint32_t DMA_MULTIBLK_EN : 1; /*!< this bit configures enable multi-blk transfer, 0: disable, 1: + enable */ + __IOM uint32_t EN : 1; /*!< this bit configures enable interval between frame transfer, + 0: disable, 1: enable */ + uint32_t : 2; + } bit; + } DMA_FRAME_INTERVAL; + + union { + __IOM uint32_t reg; /*!< dsi_bridge mem aux control register */ + + struct { + __IOM uint32_t DSI_MEM_AUX_CTRL : 14; /*!< this field configures dsi_bridge fifo memory aux ctrl */ + uint32_t : 18; + } bit; + } MEM_AUX_CTRL; + + union { + __IOM uint32_t reg; /*!< dsi_bridge rdn eco cs register */ + + struct { + __IOM uint32_t RDN_ECO_EN : 1; /*!< rdn_eco_en */ + __IM uint32_t RDN_ECO_RESULT : 1; /*!< rdn_eco_result */ + uint32_t : 30; + } bit; + } RDN_ECO_CS; + + union { + __IOM uint32_t reg; /*!< dsi_bridge rdn eco all low register */ + + struct { + __IOM uint32_t RDN_ECO_LOW : 32; /*!< rdn_eco_low */ + } bit; + } RDN_ECO_LOW; + + union { + __IOM uint32_t reg; /*!< dsi_bridge rdn eco all high register */ + + struct { + __IOM uint32_t RDN_ECO_HIGH : 32; /*!< rdn_eco_high */ + } bit; + } RDN_ECO_HIGH; + + union { + __IOM uint32_t reg; /*!< dsi_bridge host control register */ + + struct { + __IOM uint32_t DSI_CFG_REF_CLK_EN : 1; /*!< this bit configures the clk enable refclk and cfg_clk of dsi_host. + 0: disable, 1: enable */ + uint32_t : 31; + } bit; + } HOST_CTRL; + + union { + __IOM uint32_t reg; /*!< dsi_bridge mem force on control register */ + + struct { + __IOM uint32_t DSI_BRIDGE_MEM_CLK_FORCE_ON : 1;/*!< this bit configures the clock force on of dsi_bridge fifo memory. + 0: disable, 1: force on */ + __IOM uint32_t DSI_MEM_CLK_FORCE_ON : 1; /*!< this bit configures the clock force on of dpi fifo memory. 0: + disable, 1: force on */ + uint32_t : 30; + } bit; + } MEM_CLK_CTRL; + + union { + __IOM uint32_t reg; /*!< dsi_bridge dma flow controller register */ + + struct { + __IOM uint32_t DSI_DMA_FLOW_CONTROLLER : 1;/*!< this bit configures the flow controller, 0: dmac as flow controller, + 1:dsi_bridge as flow controller */ + uint32_t : 3; + __IOM uint32_t DMA_FLOW_MULTIBLK_NUM : 4; /*!< this field configures the num of blocks when multi-blk is enable + and dmac as flow controller */ + uint32_t : 24; + } bit; + } DMA_FLOW_CTRL; + + union { + __IOM uint32_t reg; /*!< dsi_bridge buffer empty threshold register */ + + struct { + __IOM uint32_t DSI_RAW_BUF_ALMOST_EMPTY_THRD : 11;/*!< this field configures the fifo almost empty threshold, is valid + only when dmac as flow controller */ + uint32_t : 21; + } bit; + } RAW_BUF_ALMOST_EMPTY_THRD; + + union { + __IOM uint32_t reg; /*!< dsi_bridge yuv format config register */ + + struct { + __IOM uint32_t PROTOCAL : 1; /*!< this bit configures yuv protoocl, 0: bt.601, 1: bt.709 */ + __IOM uint32_t YUV_PIX_ENDIAN : 1; /*!< this bit configures yuv pixel endian, 0: y0u0y1v1y2u2y3v3, 1: + y3u3y2v2y1u1y0v0 */ + __IOM uint32_t YUV422_FORMAT : 2; /*!< this field configures yuv422 store format, 0: yuyv, 1: yvyu, + 2: uyvy, 3: vyuy */ + uint32_t : 28; + } bit; + } YUV_CFG; + + union { + __IOM uint32_t reg; /*!< dsi phy lp_loopback test ctrl */ + + struct { + __IOM uint32_t PHY_LP_TXDATAESC_1 : 8; /*!< txdataesc_1 ctrl when enable dsi phy lp_loopback_test */ + __IOM uint32_t PHY_LP_TXREQUESTESC_1 : 1; /*!< txrequestesc_1 ctrl when enable dsi phy lp_loopback_test */ + __IOM uint32_t PHY_LP_TXVALIDESC_1 : 1; /*!< txvalidesc_1 ctrl when enable dsi phy lp_loopback_test */ + __IOM uint32_t PHY_LP_TXLPDTESC_1 : 1; /*!< txlpdtesc_1 ctrl when enable dsi phy lp_loopback_test */ + __IOM uint32_t PHY_LP_BASEDIR_1 : 1; /*!< basedir_1 ctrl when enable dsi phy lp_loopback_test */ + uint32_t : 4; + __IOM uint32_t PHY_LP_TXDATAESC_0 : 8; /*!< txdataesc_0 ctrl when enable dsi phy lp_loopback_test */ + __IOM uint32_t PHY_LP_TXREQUESTESC_0 : 1; /*!< txrequestesc_0 ctrl when enable dsi phy lp_loopback_test */ + __IOM uint32_t PHY_LP_TXVALIDESC_0 : 1; /*!< txvalidesc_0 ctrl when enable dsi phy lp_loopback_test */ + __IOM uint32_t PHY_LP_TXLPDTESC_0 : 1; /*!< txlpdtesc_0 ctrl when enable dsi phy lp_loopback_test */ + __IOM uint32_t PHY_LP_BASEDIR_0 : 1; /*!< basedir_0 ctrl when enable dsi phy lp_loopback_test */ + __OM uint32_t PHY_LP_LOOPBACK_CHECK : 1; /*!< dsi phy lp_loopback test start check */ + __IM uint32_t PHY_LP_LOOPBACK_CHECK_DONE : 1;/*!< dsi phy lp_loopback test check done */ + __IOM uint32_t PHY_LP_LOOPBACK_EN : 1; /*!< dsi phy lp_loopback ctrl en */ + __IM uint32_t PHY_LP_LOOPBACK_OK : 1; /*!< result of dsi phy lp_loopback test */ + } bit; + } PHY_LP_LOOPBACK_CTRL; + + union { + __IOM uint32_t reg; /*!< dsi phy hp_loopback test ctrl */ + + struct { + __IOM uint32_t PHY_HS_TXDATAHS_1 : 8; /*!< txdatahs_1 ctrl when enable dsi phy hs_loopback_test */ + __IOM uint32_t PHY_HS_TXREQUESTDATAHS_1 : 1;/*!< txrequestdatahs_1 ctrl when enable dsi phy hs_loopback_test */ + __IOM uint32_t PHY_HS_BASEDIR_1 : 1; /*!< basedir_1 ctrl when enable dsi phy hs_loopback_test */ + uint32_t : 6; + __IOM uint32_t PHY_HS_TXDATAHS_0 : 8; /*!< txdatahs_0 ctrl when enable dsi phy hs_loopback_test */ + __IOM uint32_t PHY_HS_TXREQUESTDATAHS_0 : 1;/*!< txrequestdatahs_0 ctrl when enable dsi phy hs_loopback_test */ + __IOM uint32_t PHY_HS_BASEDIR_0 : 1; /*!< basedir_0 ctrl when enable dsi phy hs_loopback_test */ + uint32_t : 1; + __IOM uint32_t PHY_HS_TXREQUESTHSCLK : 1; /*!< txrequesthsclk when enable dsi phy hs_loopback_test */ + __OM uint32_t PHY_HS_LOOPBACK_CHECK : 1; /*!< dsi phy hs_loopback test start check */ + __IM uint32_t PHY_HS_LOOPBACK_CHECK_DONE : 1;/*!< dsi phy hs_loopback test check done */ + __IOM uint32_t PHY_HS_LOOPBACK_EN : 1; /*!< dsi phy hs_loopback ctrl en */ + __IM uint32_t PHY_HS_LOOPBACK_OK : 1; /*!< result of dsi phy hs_loopback test */ + } bit; + } PHY_HS_LOOPBACK_CTRL; + + union { + __IOM uint32_t reg; /*!< loopback test cnt */ + + struct { + __IOM uint32_t PHY_HS_CHECK_CNT_TH : 8; /*!< hs_loopback test check cnt */ + uint32_t : 8; + __IOM uint32_t PHY_LP_CHECK_CNT_TH : 8; /*!< lp_loopback test check cnt */ + uint32_t : 8; + } bit; + } PHY_LOOPBACK_CNT; +} MIPI_DSI_BRIDGE_Type; /*!< Size = 160 (0xa0) */ + + + +/* =========================================================================================================================== */ +/* ================ MIPI_DSI_HOST ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief MIPI Display Interface Host (MIPI_DSI_HOST) + */ + +typedef struct { /*!< MIPI_DSI_HOST Structure */ + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t VERSION : 32; /*!< NA */ + } bit; + } VERSION; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t SHUTDOWNZ : 1; /*!< NA */ + uint32_t : 31; + } bit; + } PWR_UP; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t TX_ESC_CLK_DIVISION : 8; /*!< NA */ + __IOM uint32_t TO_CLK_DIVISION : 8; /*!< NA */ + uint32_t : 16; + } bit; + } CLKMGR_CFG; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t DPI_VCID : 2; /*!< NA */ + uint32_t : 30; + } bit; + } DPI_VCID; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t DPI_COLOR_CODING : 4; /*!< NA */ + uint32_t : 4; + __IOM uint32_t LOOSELY18_EN : 1; /*!< NA */ + uint32_t : 23; + } bit; + } DPI_COLOR_CODING; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t DATAEN_ACTIVE_LOW : 1; /*!< NA */ + __IOM uint32_t VSYNC_ACTIVE_LOW : 1; /*!< NA */ + __IOM uint32_t HSYNC_ACTIVE_LOW : 1; /*!< NA */ + __IOM uint32_t SHUTD_ACTIVE_LOW : 1; /*!< NA */ + __IOM uint32_t COLORM_ACTIVE_LOW : 1; /*!< NA */ + uint32_t : 27; + } bit; + } DPI_CFG_POL; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t INVACT_LPCMD_TIME : 8; /*!< NA */ + uint32_t : 8; + __IOM uint32_t OUTVACT_LPCMD_TIME : 8; /*!< NA */ + uint32_t : 8; + } bit; + } DPI_LP_CMD_TIM; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t DBI_VCID : 2; /*!< NA */ + uint32_t : 30; + } bit; + } DBI_VCID; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t IN_DBI_CONF : 4; /*!< NA */ + uint32_t : 4; + __IOM uint32_t OUT_DBI_CONF : 4; /*!< NA */ + uint32_t : 4; + __IOM uint32_t LUT_SIZE_CONF : 2; /*!< NA */ + uint32_t : 14; + } bit; + } DBI_CFG; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t PARTITIONING_EN : 1; /*!< NA */ + uint32_t : 31; + } bit; + } DBI_PARTITIONING_EN; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t WR_CMD_SIZE : 16; /*!< NA */ + __IOM uint32_t ALLOWED_CMD_SIZE : 16; /*!< NA */ + } bit; + } DBI_CMDSIZE; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t EOTP_TX_EN : 1; /*!< NA */ + __IOM uint32_t EOTP_RX_EN : 1; /*!< NA */ + __IOM uint32_t BTA_EN : 1; /*!< NA */ + __IOM uint32_t ECC_RX_EN : 1; /*!< NA */ + __IOM uint32_t CRC_RX_EN : 1; /*!< NA */ + __IOM uint32_t EOTP_TX_LP_EN : 1; /*!< NA */ + uint32_t : 26; + } bit; + } PCKHDL_CFG; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t RX : 2; /*!< NA */ + uint32_t : 6; + __IOM uint32_t TEAR_AUTO : 2; /*!< NA */ + uint32_t : 6; + __IOM uint32_t TX_AUTO : 2; /*!< NA */ + uint32_t : 14; + } bit; + } GEN_VCID; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t CMD_VIDEO_MODE : 1; /*!< NA */ + uint32_t : 31; + } bit; + } MODE_CFG; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t VID_MODE_TYPE : 2; /*!< NA */ + uint32_t : 6; + __IOM uint32_t LP_VSA_EN : 1; /*!< NA */ + __IOM uint32_t LP_VBP_EN : 1; /*!< NA */ + __IOM uint32_t LP_VFP_EN : 1; /*!< NA */ + __IOM uint32_t LP_VACT_EN : 1; /*!< NA */ + __IOM uint32_t LP_HBP_EN : 1; /*!< NA */ + __IOM uint32_t LP_HFP_EN : 1; /*!< NA */ + __IOM uint32_t FRAME_BTA_ACK_EN : 1; /*!< NA */ + __IOM uint32_t LP_CMD_EN : 1; /*!< NA */ + __IOM uint32_t VPG_EN : 1; /*!< NA */ + uint32_t : 3; + __IOM uint32_t VPG_MODE : 1; /*!< NA */ + uint32_t : 3; + __IOM uint32_t VPG_ORIENTATION : 1; /*!< NA */ + uint32_t : 7; + } bit; + } VID_MODE_CFG; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t VID_PKT_SIZE : 14; /*!< NA */ + uint32_t : 18; + } bit; + } VID_PKT_SIZE; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t VID_NUM_CHUNKS : 13; /*!< NA */ + uint32_t : 19; + } bit; + } VID_NUM_CHUNKS; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t VID_NULL_SIZE : 13; /*!< NA */ + uint32_t : 19; + } bit; + } VID_NULL_SIZE; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t VID_HSA_TIME : 12; /*!< NA */ + uint32_t : 20; + } bit; + } VID_HSA_TIME; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t VID_HBP_TIME : 12; /*!< NA */ + uint32_t : 20; + } bit; + } VID_HBP_TIME; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t VID_HLINE_TIME : 15; /*!< NA */ + uint32_t : 17; + } bit; + } VID_HLINE_TIME; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t VSA_LINES : 10; /*!< NA */ + uint32_t : 22; + } bit; + } VID_VSA_LINES; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t VBP_LINES : 10; /*!< NA */ + uint32_t : 22; + } bit; + } VID_VBP_LINES; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t VFP_LINES : 10; /*!< NA */ + uint32_t : 22; + } bit; + } VID_VFP_LINES; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t V_ACTIVE_LINES : 14; /*!< NA */ + uint32_t : 18; + } bit; + } VID_VACTIVE_LINES; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t EDPI_ALLOWED_CMD_SIZE : 16;/*!< NA */ + uint32_t : 16; + } bit; + } EDPI_CMD_SIZE; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t TEAR_FX_EN : 1; /*!< NA */ + __IOM uint32_t ACK_RQST_EN : 1; /*!< NA */ + uint32_t : 6; + __IOM uint32_t GEN_SW_0P_TX : 1; /*!< NA */ + __IOM uint32_t GEN_SW_1P_TX : 1; /*!< NA */ + __IOM uint32_t GEN_SW_2P_TX : 1; /*!< NA */ + __IOM uint32_t GEN_SR_0P_TX : 1; /*!< NA */ + __IOM uint32_t GEN_SR_1P_TX : 1; /*!< NA */ + __IOM uint32_t GEN_SR_2P_TX : 1; /*!< NA */ + __IOM uint32_t GEN_LW_TX : 1; /*!< NA */ + uint32_t : 1; + __IOM uint32_t DCS_SW_0P_TX : 1; /*!< NA */ + __IOM uint32_t DCS_SW_1P_TX : 1; /*!< NA */ + __IOM uint32_t DCS_SR_0P_TX : 1; /*!< NA */ + __IOM uint32_t DCS_LW_TX : 1; /*!< NA */ + uint32_t : 4; + __IOM uint32_t MAX_RD_PKT_SIZE : 1; /*!< NA */ + uint32_t : 7; + } bit; + } CMD_MODE_CFG; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t GEN_DT : 6; /*!< NA */ + __IOM uint32_t GEN_VC : 2; /*!< NA */ + __IOM uint32_t GEN_WC_LSBYTE : 8; /*!< NA */ + __IOM uint32_t GEN_WC_MSBYTE : 8; /*!< NA */ + uint32_t : 8; + } bit; + } GEN_HDR; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t GEN_PLD_B1 : 8; /*!< NA */ + __IOM uint32_t GEN_PLD_B2 : 8; /*!< NA */ + __IOM uint32_t GEN_PLD_B3 : 8; /*!< NA */ + __IOM uint32_t GEN_PLD_B4 : 8; /*!< NA */ + } bit; + } GEN_PLD_DATA; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t GEN_CMD_EMPTY : 1; /*!< NA */ + __IM uint32_t GEN_CMD_FULL : 1; /*!< NA */ + __IM uint32_t GEN_PLD_W_EMPTY : 1; /*!< NA */ + __IM uint32_t GEN_PLD_W_FULL : 1; /*!< NA */ + __IM uint32_t GEN_PLD_R_EMPTY : 1; /*!< NA */ + __IM uint32_t GEN_PLD_R_FULL : 1; /*!< NA */ + __IM uint32_t GEN_RD_CMD_BUSY : 1; /*!< NA */ + uint32_t : 9; + __IM uint32_t GEN_BUFF_CMD_EMPTY : 1; /*!< NA */ + __IM uint32_t GEN_BUFF_CMD_FULL : 1; /*!< NA */ + __IM uint32_t GEN_BUFF_PLD_EMPTY : 1; /*!< NA */ + __IM uint32_t GEN_BUFF_PLD_FULL : 1; /*!< NA */ + uint32_t : 12; + } bit; + } CMD_PKT_STATUS; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t LPRX_TO_CNT : 16; /*!< NA */ + __IOM uint32_t HSTX_TO_CNT : 16; /*!< NA */ + } bit; + } TO_CNT_CFG; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t HS_RD_TO_CNT : 16; /*!< NA */ + uint32_t : 16; + } bit; + } HS_RD_TO_CNT; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t LP_RD_TO_CNT : 16; /*!< NA */ + uint32_t : 16; + } bit; + } LP_RD_TO_CNT; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t HS_WR_TO_CNT : 16; /*!< NA */ + uint32_t : 16; + } bit; + } HS_WR_TO_CNT; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t LP_WR_TO_CNT : 16; /*!< NA */ + uint32_t : 16; + } bit; + } LP_WR_TO_CNT; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t BTA_TO_CNT : 16; /*!< NA */ + uint32_t : 16; + } bit; + } BTA_TO_CNT; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t MODE_3D : 2; /*!< NA */ + __IOM uint32_t FORMAT_3D : 2; /*!< NA */ + __IOM uint32_t SECOND_VSYNC : 1; /*!< NA */ + __IOM uint32_t RIGHT_FIRST : 1; /*!< NA */ + uint32_t : 10; + __IOM uint32_t SEND_3D_CFG : 1; /*!< NA */ + uint32_t : 15; + } bit; + } SDF_3D; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t PHY_TXREQUESTCLKHS : 1; /*!< NA */ + __IOM uint32_t AUTO_CLKLANE_CTRL : 1; /*!< NA */ + uint32_t : 30; + } bit; + } LPCLK_CTRL; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t PHY_CLKLP2HS_TIME : 10; /*!< NA */ + uint32_t : 6; + __IOM uint32_t PHY_CLKHS2LP_TIME : 10; /*!< NA */ + uint32_t : 6; + } bit; + } PHY_TMR_LPCLK_CFG; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t PHY_LP2HS_TIME : 10; /*!< NA */ + uint32_t : 6; + __IOM uint32_t PHY_HS2LP_TIME : 10; /*!< NA */ + uint32_t : 6; + } bit; + } PHY_TMR_CFG; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t PHY_SHUTDOWNZ : 1; /*!< NA */ + __IOM uint32_t PHY_RSTZ : 1; /*!< NA */ + __IOM uint32_t PHY_ENABLECLK : 1; /*!< NA */ + __IOM uint32_t PHY_FORCEPLL : 1; /*!< NA */ + uint32_t : 28; + } bit; + } PHY_RSTZ; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t N_LANES : 2; /*!< NA */ + uint32_t : 6; + __IOM uint32_t PHY_STOP_WAIT_TIME : 8; /*!< NA */ + uint32_t : 16; + } bit; + } PHY_IF_CFG; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t PHY_TXREQULPSCLK : 1; /*!< NA */ + __IOM uint32_t PHY_TXEXITULPSCLK : 1; /*!< NA */ + __IOM uint32_t PHY_TXREQULPSLAN : 1; /*!< NA */ + __IOM uint32_t PHY_TXEXITULPSLAN : 1; /*!< NA */ + uint32_t : 28; + } bit; + } PHY_ULPS_CTRL; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t PHY_TX_TRIGGERS : 4; /*!< NA */ + uint32_t : 28; + } bit; + } PHY_TX_TRIGGERS; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t PHY_LOCK : 1; /*!< NA */ + __IM uint32_t PHY_DIRECTION : 1; /*!< NA */ + __IM uint32_t PHY_STOPSTATECLKLANE : 1; /*!< NA */ + __IM uint32_t PHY_ULPSACTIVENOTCLK : 1; /*!< NA */ + __IM uint32_t PHY_STOPSTATE0LANE : 1; /*!< NA */ + __IM uint32_t PHY_ULPSACTIVENOT0LANE : 1;/*!< NA */ + __IM uint32_t PHY_RXULPSESC0LANE : 1; /*!< NA */ + __IM uint32_t PHY_STOPSTATE1LANE : 1; /*!< NA */ + __IM uint32_t PHY_ULPSACTIVENOT1LANE : 1;/*!< NA */ + uint32_t : 23; + } bit; + } PHY_STATUS; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t PHY_TESTCLR : 1; /*!< NA */ + __IOM uint32_t PHY_TESTCLK : 1; /*!< NA */ + uint32_t : 30; + } bit; + } PHY_TST_CTRL0; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t PHY_TESTDIN : 8; /*!< NA */ + __IM uint32_t PHT_TESTDOUT : 8; /*!< NA */ + __IOM uint32_t PHY_TESTEN : 1; /*!< NA */ + uint32_t : 15; + } bit; + } PHY_TST_CTRL1; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t ACK_WITH_ERR_0 : 1; /*!< NA */ + __IM uint32_t ACK_WITH_ERR_1 : 1; /*!< NA */ + __IM uint32_t ACK_WITH_ERR_2 : 1; /*!< NA */ + __IM uint32_t ACK_WITH_ERR_3 : 1; /*!< NA */ + __IM uint32_t ACK_WITH_ERR_4 : 1; /*!< NA */ + __IM uint32_t ACK_WITH_ERR_5 : 1; /*!< NA */ + __IM uint32_t ACK_WITH_ERR_6 : 1; /*!< NA */ + __IM uint32_t ACK_WITH_ERR_7 : 1; /*!< NA */ + __IM uint32_t ACK_WITH_ERR_8 : 1; /*!< NA */ + __IM uint32_t ACK_WITH_ERR_9 : 1; /*!< NA */ + __IM uint32_t ACK_WITH_ERR_10 : 1; /*!< NA */ + __IM uint32_t ACK_WITH_ERR_11 : 1; /*!< NA */ + __IM uint32_t ACK_WITH_ERR_12 : 1; /*!< NA */ + __IM uint32_t ACK_WITH_ERR_13 : 1; /*!< NA */ + __IM uint32_t ACK_WITH_ERR_14 : 1; /*!< NA */ + __IM uint32_t ACK_WITH_ERR_15 : 1; /*!< NA */ + __IM uint32_t DPHY_ERRORS_0 : 1; /*!< NA */ + __IM uint32_t DPHY_ERRORS_1 : 1; /*!< NA */ + __IM uint32_t DPHY_ERRORS_2 : 1; /*!< NA */ + __IM uint32_t DPHY_ERRORS_3 : 1; /*!< NA */ + __IM uint32_t DPHY_ERRORS_4 : 1; /*!< NA */ + uint32_t : 11; + } bit; + } INT_ST0; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t TO_HS_TX : 1; /*!< NA */ + __IM uint32_t TO_LP_RX : 1; /*!< NA */ + __IM uint32_t ECC_SINGLE_ERR : 1; /*!< NA */ + __IM uint32_t ECC_MILTI_ERR : 1; /*!< NA */ + __IM uint32_t CRC_ERR : 1; /*!< NA */ + __IM uint32_t PKT_SIZE_ERR : 1; /*!< NA */ + __IM uint32_t EOPT_ERR : 1; /*!< NA */ + __IM uint32_t DPI_PLD_WR_ERR : 1; /*!< NA */ + __IM uint32_t GEN_CMD_WR_ERR : 1; /*!< NA */ + __IM uint32_t GEN_PLD_WR_ERR : 1; /*!< NA */ + __IM uint32_t GEN_PLD_SEND_ERR : 1; /*!< NA */ + __IM uint32_t GEN_PLD_RD_ERR : 1; /*!< NA */ + __IM uint32_t GEN_PLD_RECEV_ERR : 1; /*!< NA */ + uint32_t : 6; + __IM uint32_t DPI_BUFF_PLD_UNDER : 1; /*!< NA */ + uint32_t : 12; + } bit; + } INT_ST1; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t MASK_ACK_WITH_ERR_0 : 1; /*!< NA */ + __IOM uint32_t MASK_ACK_WITH_ERR_1 : 1; /*!< NA */ + __IOM uint32_t MASK_ACK_WITH_ERR_2 : 1; /*!< NA */ + __IOM uint32_t MASK_ACK_WITH_ERR_3 : 1; /*!< NA */ + __IOM uint32_t MASK_ACK_WITH_ERR_4 : 1; /*!< NA */ + __IOM uint32_t MASK_ACK_WITH_ERR_5 : 1; /*!< NA */ + __IOM uint32_t MASK_ACK_WITH_ERR_6 : 1; /*!< NA */ + __IOM uint32_t MASK_ACK_WITH_ERR_7 : 1; /*!< NA */ + __IOM uint32_t MASK_ACK_WITH_ERR_8 : 1; /*!< NA */ + __IOM uint32_t MASK_ACK_WITH_ERR_9 : 1; /*!< NA */ + __IOM uint32_t MASK_ACK_WITH_ERR_10 : 1; /*!< NA */ + __IOM uint32_t MASK_ACK_WITH_ERR_11 : 1; /*!< NA */ + __IOM uint32_t MASK_ACK_WITH_ERR_12 : 1; /*!< NA */ + __IOM uint32_t MASK_ACK_WITH_ERR_13 : 1; /*!< NA */ + __IOM uint32_t MASK_ACK_WITH_ERR_14 : 1; /*!< NA */ + __IOM uint32_t MASK_ACK_WITH_ERR_15 : 1; /*!< NA */ + __IOM uint32_t MASK_DPHY_ERRORS_0 : 1; /*!< NA */ + __IOM uint32_t MASK_DPHY_ERRORS_1 : 1; /*!< NA */ + __IOM uint32_t MASK_DPHY_ERRORS_2 : 1; /*!< NA */ + __IOM uint32_t MASK_DPHY_ERRORS_3 : 1; /*!< NA */ + __IOM uint32_t MASK_DPHY_ERRORS_4 : 1; /*!< NA */ + uint32_t : 11; + } bit; + } INT_MSK0; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t MASK_TO_HS_TX : 1; /*!< NA */ + __IOM uint32_t MASK_TO_LP_RX : 1; /*!< NA */ + __IOM uint32_t MASK_ECC_SINGLE_ERR : 1; /*!< NA */ + __IOM uint32_t MASK_ECC_MILTI_ERR : 1; /*!< NA */ + __IOM uint32_t MASK_CRC_ERR : 1; /*!< NA */ + __IOM uint32_t MASK_PKT_SIZE_ERR : 1; /*!< NA */ + __IOM uint32_t MASK_EOPT_ERR : 1; /*!< NA */ + __IOM uint32_t MASK_DPI_PLD_WR_ERR : 1; /*!< NA */ + __IOM uint32_t MASK_GEN_CMD_WR_ERR : 1; /*!< NA */ + __IOM uint32_t MASK_GEN_PLD_WR_ERR : 1; /*!< NA */ + __IOM uint32_t MASK_GEN_PLD_SEND_ERR : 1; /*!< NA */ + __IOM uint32_t MASK_GEN_PLD_RD_ERR : 1; /*!< NA */ + __IOM uint32_t MASK_GEN_PLD_RECEV_ERR : 1;/*!< NA */ + uint32_t : 6; + __IOM uint32_t MASK_DPI_BUFF_PLD_UNDER : 1;/*!< NA */ + uint32_t : 12; + } bit; + } INT_MSK1; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t TXSKEWCALHS : 1; /*!< NA */ + uint32_t : 31; + } bit; + } PHY_CAL; + __IM uint32_t RESERVED[2]; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t FORCE_ACK_WITH_ERR_0 : 1; /*!< NA */ + __IOM uint32_t FORCE_ACK_WITH_ERR_1 : 1; /*!< NA */ + __IOM uint32_t FORCE_ACK_WITH_ERR_2 : 1; /*!< NA */ + __IOM uint32_t FORCE_ACK_WITH_ERR_3 : 1; /*!< NA */ + __IOM uint32_t FORCE_ACK_WITH_ERR_4 : 1; /*!< NA */ + __IOM uint32_t FORCE_ACK_WITH_ERR_5 : 1; /*!< NA */ + __IOM uint32_t FORCE_ACK_WITH_ERR_6 : 1; /*!< NA */ + __IOM uint32_t FORCE_ACK_WITH_ERR_7 : 1; /*!< NA */ + __IOM uint32_t FORCE_ACK_WITH_ERR_8 : 1; /*!< NA */ + __IOM uint32_t FORCE_ACK_WITH_ERR_9 : 1; /*!< NA */ + __IOM uint32_t FORCE_ACK_WITH_ERR_10 : 1; /*!< NA */ + __IOM uint32_t FORCE_ACK_WITH_ERR_11 : 1; /*!< NA */ + __IOM uint32_t FORCE_ACK_WITH_ERR_12 : 1; /*!< NA */ + __IOM uint32_t FORCE_ACK_WITH_ERR_13 : 1; /*!< NA */ + __IOM uint32_t FORCE_ACK_WITH_ERR_14 : 1; /*!< NA */ + __IOM uint32_t FORCE_ACK_WITH_ERR_15 : 1; /*!< NA */ + __IOM uint32_t FORCE_DPHY_ERRORS_0 : 1; /*!< NA */ + __IOM uint32_t FORCE_DPHY_ERRORS_1 : 1; /*!< NA */ + __IOM uint32_t FORCE_DPHY_ERRORS_2 : 1; /*!< NA */ + __IOM uint32_t FORCE_DPHY_ERRORS_3 : 1; /*!< NA */ + __IOM uint32_t FORCE_DPHY_ERRORS_4 : 1; /*!< NA */ + uint32_t : 11; + } bit; + } INT_FORCE0; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t FORCE_TO_HS_TX : 1; /*!< NA */ + __IOM uint32_t FORCE_TO_LP_RX : 1; /*!< NA */ + __IOM uint32_t FORCE_ECC_SINGLE_ERR : 1; /*!< NA */ + __IOM uint32_t FORCE_ECC_MILTI_ERR : 1; /*!< NA */ + __IOM uint32_t FORCE_CRC_ERR : 1; /*!< NA */ + __IOM uint32_t FORCE_PKT_SIZE_ERR : 1; /*!< NA */ + __IOM uint32_t FORCE_EOPT_ERR : 1; /*!< NA */ + __IOM uint32_t FORCE_DPI_PLD_WR_ERR : 1; /*!< NA */ + __IOM uint32_t FORCE_GEN_CMD_WR_ERR : 1; /*!< NA */ + __IOM uint32_t FORCE_GEN_PLD_WR_ERR : 1; /*!< NA */ + __IOM uint32_t FORCE_GEN_PLD_SEND_ERR : 1;/*!< NA */ + __IOM uint32_t FORCE_GEN_PLD_RD_ERR : 1; /*!< NA */ + __IOM uint32_t FORCE_GEN_PLD_RECEV_ERR : 1;/*!< NA */ + uint32_t : 6; + __IOM uint32_t FORCE_DPI_BUFF_PLD_UNDER : 1;/*!< NA */ + uint32_t : 12; + } bit; + } INT_FORCE1; + __IM uint32_t RESERVED1[4]; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t COMPRESSION_MODE : 1; /*!< NA */ + uint32_t : 7; + __IOM uint32_t COMPRESS_ALGO : 2; /*!< NA */ + uint32_t : 6; + __IOM uint32_t PPS_SEL : 2; /*!< NA */ + uint32_t : 14; + } bit; + } DSC_PARAMETER; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t MAX_RD_TIME : 15; /*!< NA */ + uint32_t : 17; + } bit; + } PHY_TMR_RD_CFG; + __IM uint32_t RESERVED2[2]; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t VID_SHADOW_EN : 1; /*!< NA */ + uint32_t : 7; + __IOM uint32_t VID_SHADOW_REQ : 1; /*!< NA */ + uint32_t : 7; + __IOM uint32_t VID_SHADOW_PIN_REQ : 1; /*!< NA */ + uint32_t : 15; + } bit; + } VID_SHADOW_CTRL; + __IM uint32_t RESERVED3[2]; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t DPI_VCID_ACT : 2; /*!< NA */ + uint32_t : 30; + } bit; + } DPI_VCID_ACT; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t DPI_COLOR_CODING_ACT : 4; /*!< NA */ + uint32_t : 4; + __IM uint32_t LOOSELY18_EN_ACT : 1; /*!< NA */ + uint32_t : 23; + } bit; + } DPI_COLOR_CODING_ACT; + __IM uint32_t RESERVED4; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t INVACT_LPCMD_TIME_ACT : 8; /*!< NA */ + uint32_t : 8; + __IM uint32_t OUTVACT_LPCMD_TIME_ACT : 8;/*!< NA */ + uint32_t : 8; + } bit; + } DPI_LP_CMD_TIM_ACT; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t HW_TEAR_EFFECT_ON : 1; /*!< NA */ + __IOM uint32_t HW_TEAR_EFFECT_GEN : 1; /*!< NA */ + uint32_t : 2; + __IOM uint32_t HW_SET_SCAN_LINE : 1; /*!< NA */ + uint32_t : 11; + __IOM uint32_t SCAN_LINE_PARAMETER : 16; /*!< NA */ + } bit; + } EDPI_TE_HW_CFG; + __IM uint32_t RESERVED5[6]; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t VID_MODE_TYPE_ACT : 2; /*!< NA */ + __IM uint32_t LP_VSA_EN_ACT : 1; /*!< NA */ + __IM uint32_t LP_VBP_EN_ACT : 1; /*!< NA */ + __IM uint32_t LP_VFP_EN_ACT : 1; /*!< NA */ + __IM uint32_t LP_VACT_EN_ACT : 1; /*!< NA */ + __IM uint32_t LP_HBP_EN_ACT : 1; /*!< NA */ + __IM uint32_t LP_HFP_EN_ACT : 1; /*!< NA */ + __IM uint32_t FRAME_BTA_ACK_EN_ACT : 1; /*!< NA */ + __IM uint32_t LP_CMD_EN_ACT : 1; /*!< NA */ + uint32_t : 22; + } bit; + } VID_MODE_CFG_ACT; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t VID_PKT_SIZE_ACT : 14; /*!< NA */ + uint32_t : 18; + } bit; + } VID_PKT_SIZE_ACT; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t VID_NUM_CHUNKS_ACT : 13; /*!< NA */ + uint32_t : 19; + } bit; + } VID_NUM_CHUNKS_ACT; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t VID_NULL_SIZE_ACT : 13; /*!< NA */ + uint32_t : 19; + } bit; + } VID_NULL_SIZE_ACT; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t VID_HSA_TIME_ACT : 12; /*!< NA */ + uint32_t : 20; + } bit; + } VID_HSA_TIME_ACT; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t VID_HBP_TIME_ACT : 12; /*!< NA */ + uint32_t : 20; + } bit; + } VID_HBP_TIME_ACT; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t VID_HLINE_TIME_ACT : 15; /*!< NA */ + uint32_t : 17; + } bit; + } VID_HLINE_TIME_ACT; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t VSA_LINES_ACT : 10; /*!< NA */ + uint32_t : 22; + } bit; + } VID_VSA_LINES_ACT; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t VBP_LINES_ACT : 10; /*!< NA */ + uint32_t : 22; + } bit; + } VID_VBP_LINES_ACT; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t VFP_LINES_ACT : 10; /*!< NA */ + uint32_t : 22; + } bit; + } VID_VFP_LINES_ACT; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t V_ACTIVE_LINES_ACT : 14; /*!< NA */ + uint32_t : 18; + } bit; + } VID_VACTIVE_LINES_ACT; + __IM uint32_t RESERVED6; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t DPI_CMD_W_EMPTY : 1; /*!< NA */ + __IM uint32_t DPI_CMD_W_FULL : 1; /*!< NA */ + __IM uint32_t DPI_PLD_W_EMPTY : 1; /*!< NA */ + __IM uint32_t DPI_PLD_W_FULL : 1; /*!< NA */ + uint32_t : 12; + __IM uint32_t DPI_BUFF_PLD_EMPTY : 1; /*!< NA */ + __IM uint32_t DPI_BUFF_PLD_FULL : 1; /*!< NA */ + uint32_t : 14; + } bit; + } VID_PKT_STATUS; + __IM uint32_t RESERVED7[9]; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t MODE_3D_ACT : 2; /*!< NA */ + __IM uint32_t FORMAT_3D_ACT : 2; /*!< NA */ + __IM uint32_t SECOND_VSYNC_ACT : 1; /*!< NA */ + __IM uint32_t RIGHT_FIRST_ACT : 1; /*!< NA */ + uint32_t : 10; + __IM uint32_t SEND_3D_CFG_ACT : 1; /*!< NA */ + uint32_t : 15; + } bit; + } SDF_3D_ACT; +} MIPI_DSI_HOST_Type; /*!< Size = 404 (0x194) */ + + + +/* =========================================================================================================================== */ +/* ================ ECC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief ECC (ECC Hardware Accelerator) (ECC) + */ + +typedef struct { /*!< ECC Structure */ + __IM uint32_t RESERVED[3]; + + union { + __IOM uint32_t reg; /*!< ECC interrupt raw register, valid in level. */ + + struct { + __IM uint32_t CALC_DONE_INT_RAW : 1; /*!< The raw interrupt status bit for the ecc_calc_done_int interrupt */ + uint32_t : 31; + } bit; + } MULT_INT_RAW; + + union { + __IOM uint32_t reg; /*!< ECC interrupt status register. */ + + struct { + __IM uint32_t CALC_DONE_INT_ST : 1; /*!< The masked interrupt status bit for the ecc_calc_done_int interrupt */ + uint32_t : 31; + } bit; + } MULT_INT_ST; + + union { + __IOM uint32_t reg; /*!< ECC interrupt enable register. */ + + struct { + __IOM uint32_t CALC_DONE_INT_ENA : 1; /*!< The interrupt enable bit for the ecc_calc_done_int interrupt */ + uint32_t : 31; + } bit; + } MULT_INT_ENA; + + union { + __IOM uint32_t reg; /*!< ECC interrupt clear register. */ + + struct { + __OM uint32_t CALC_DONE_INT_CLR : 1; /*!< Set this bit to clear the ecc_calc_done_int interrupt */ + uint32_t : 31; + } bit; + } MULT_INT_CLR; + + union { + __IOM uint32_t reg; /*!< ECC configure register */ + + struct { + __IOM uint32_t START : 1; /*!< Write 1 to start caculation of ECC Accelerator. This bit will + be self-cleared after the caculatrion is done. */ + __OM uint32_t RESET : 1; /*!< Write 1 to reset ECC Accelerator. */ + __IOM uint32_t KEY_LENGTH : 1; /*!< The key length mode bit of ECC Accelerator. 0: P-192. 1: P-256. */ + __IOM uint32_t MOD_BASE : 1; /*!< The mod base of mod operation, only valid in work_mode 8-11. + 0: n(order of curve). 1: p(mod base of curve) */ + __IOM uint32_t WORK_MODE : 4; /*!< The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: + Reserved. 2: Point verification mode. 3: Point Verif+mult + mode. 4: Jacobian Point Mult Mode. 5: Point Add Mode. 6: + Jacobian Point Verification Mode. 7: Point Verif + Jacobian + Mult Mode. 8: mod addition. 9. mod substraction. 10: mod + multiplication. 11: mod division. */ + __IOM uint32_t SECURITY_MODE : 1; /*!< Reserved */ + uint32_t : 20; + __IM uint32_t VERIFICATION_RESULT : 1; /*!< The verification result bit of ECC Accelerator, only valid when + calculation is done. */ + __IOM uint32_t CLK_EN : 1; /*!< Write 1 to force on register clock gate. */ + __IOM uint32_t MEM_CLOCK_GATE_FORCE_ON : 1;/*!< ECC memory clock gate force on register */ + } bit; + } MULT_CONF; + __IM uint32_t RESERVED1[55]; + + union { + __IOM uint32_t reg; /*!< Version control register */ + + struct { + __IOM uint32_t DATE : 28; /*!< ECC mult version control register */ + uint32_t : 4; + } bit; + } MULT_DATE; + __IOM uint32_t K_MEM[8]; /*!< The memory that stores k. */ + __IOM uint32_t PX_MEM[8]; /*!< The memory that stores Px. */ + __IOM uint32_t PY_MEM[8]; /*!< The memory that stores Py. */ +} ECC_Type; /*!< Size = 352 (0x160) */ + + + +/* =========================================================================================================================== */ +/* ================ ECDSA ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief ECDSA (Elliptic Curve Digital Signature Algorithm) Accelerator (ECDSA) + */ + +typedef struct { /*!< ECDSA Structure */ + __IM uint32_t RESERVED; + + union { + __IOM uint32_t reg; /*!< ECDSA configure register */ + + struct { + __IOM uint32_t WORK_MODE : 2; /*!< The work mode bits of ECDSA Accelerator. 0: Signature Verify + Mode. 1: Signature Generate Mode. 2: Export Public Key + Mode. 3: invalid. */ + __IOM uint32_t ECC_CURVE : 1; /*!< The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: + P-256. */ + __IOM uint32_t SOFTWARE_SET_K : 1; /*!< The source of k select bit. 0: k is automatically generated + by hardware. 1: k is written by software. */ + __IOM uint32_t SOFTWARE_SET_Z : 1; /*!< The source of z select bit. 0: z is generated from SHA result. + 1: z is written by software. */ + __IOM uint32_t DETERMINISTIC_K : 1; /*!< The source of hardware generated k. 0: k is generated by TRNG. + 1: k is generated by deterministic derivation algorithm. */ + __IOM uint32_t DETERMINISTIC_LOOP : 16; /*!< The (loop number - 1) value in the deterministic derivation + algorithm to derive k. */ + uint32_t : 10; + } bit; + } CONF; + + union { + __IOM uint32_t reg; /*!< ECDSA clock gate register */ + + struct { + __IOM uint32_t GATE_FORCE_ON : 1; /*!< Write 1 to force on register clock gate. */ + uint32_t : 31; + } bit; + } CLK; + + union { + __IOM uint32_t reg; /*!< ECDSA interrupt raw register, valid in level. */ + + struct { + __IM uint32_t CALC_DONE_INT_RAW : 1; /*!< The raw interrupt status bit for the ecdsa_calc_done_int interrupt */ + __IM uint32_t SHA_RELEASE_INT_RAW : 1; /*!< The raw interrupt status bit for the ecdsa_sha_release_int interrupt */ + uint32_t : 30; + } bit; + } INT_RAW; + + union { + __IOM uint32_t reg; /*!< ECDSA interrupt status register. */ + + struct { + __IM uint32_t CALC_DONE_INT_ST : 1; /*!< The masked interrupt status bit for the ecdsa_calc_done_int + interrupt */ + __IM uint32_t SHA_RELEASE_INT_ST : 1; /*!< The masked interrupt status bit for the ecdsa_sha_release_int + interrupt */ + uint32_t : 30; + } bit; + } INT_ST; + + union { + __IOM uint32_t reg; /*!< ECDSA interrupt enable register. */ + + struct { + __IOM uint32_t CALC_DONE_INT_ENA : 1; /*!< The interrupt enable bit for the ecdsa_calc_done_int interrupt */ + __IOM uint32_t SHA_RELEASE_INT_ENA : 1; /*!< The interrupt enable bit for the ecdsa_sha_release_int interrupt */ + uint32_t : 30; + } bit; + } INT_ENA; + + union { + __IOM uint32_t reg; /*!< ECDSA interrupt clear register. */ + + struct { + __OM uint32_t CALC_DONE_INT_CLR : 1; /*!< Set this bit to clear the ecdsa_calc_done_int interrupt */ + __OM uint32_t SHA_RELEASE_INT_CLR : 1; /*!< Set this bit to clear the ecdsa_sha_release_int interrupt */ + uint32_t : 30; + } bit; + } INT_CLR; + + union { + __IOM uint32_t reg; /*!< ECDSA start register */ + + struct { + __OM uint32_t START : 1; /*!< Write 1 to start caculation of ECDSA Accelerator. This bit will + be self-cleared after configuration. */ + __OM uint32_t LOAD_DONE : 1; /*!< Write 1 to input load done signal of ECDSA Accelerator. This + bit will be self-cleared after configuration. */ + __OM uint32_t GET_DONE : 1; /*!< Write 1 to input get done signal of ECDSA Accelerator. This + bit will be self-cleared after configuration. */ + uint32_t : 29; + } bit; + } START; + + union { + __IOM uint32_t reg; /*!< ECDSA status register */ + + struct { + __IM uint32_t BUSY : 2; /*!< The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: + LOAD, 2: GET, 3: BUSY state. */ + uint32_t : 30; + } bit; + } STATE; + + union { + __IOM uint32_t reg; /*!< ECDSA result register */ + + struct { + __IM uint32_t OPERATION_RESULT : 1; /*!< The operation result bit of ECDSA Accelerator, only valid when + ECDSA calculation is done. */ + __IM uint32_t K_VALUE_WARNING : 1; /*!< The k value warning bit of ECDSA Accelerator, valid when k value + is bigger than the curve order, then actually taken k = + k mod n. */ + uint32_t : 30; + } bit; + } RESULT; + __IM uint32_t RESERVED1[53]; + + union { + __IOM uint32_t reg; /*!< Version control register */ + + struct { + __IOM uint32_t DATE : 28; /*!< ECDSA version control register */ + uint32_t : 4; + } bit; + } DATE; + __IM uint32_t RESERVED2[64]; + + union { + __IOM uint32_t reg; /*!< ECDSA control SHA register */ + + struct { + __IOM uint32_t SHA_MODE : 3; /*!< The work mode bits of SHA Calculator in ECDSA Accelerator. 1: + SHA-224. 2: SHA-256. Others: invalid. */ + uint32_t : 29; + } bit; + } SHA_MODE; + __IM uint32_t RESERVED3[3]; + + union { + __IOM uint32_t reg; /*!< ECDSA control SHA register */ + + struct { + __OM uint32_t SHA_START : 1; /*!< Write 1 to start the first caculation of SHA Calculator in ECDSA + Accelerator. This bit will be self-cleared after configuration. */ + uint32_t : 31; + } bit; + } SHA_START; + + union { + __IOM uint32_t reg; /*!< ECDSA control SHA register */ + + struct { + __OM uint32_t SHA_CONTINUE : 1; /*!< Write 1 to start the latter caculation of SHA Calculator in + ECDSA Accelerator. This bit will be self-cleared after + configuration. */ + uint32_t : 31; + } bit; + } SHA_CONTINUE; + + union { + __IOM uint32_t reg; /*!< ECDSA status register */ + + struct { + __IM uint32_t SHA_BUSY : 1; /*!< The busy status bit of SHA Calculator in ECDSA Accelerator. + 1:SHA is in calculation. 0: SHA is idle. */ + uint32_t : 31; + } bit; + } SHA_BUSY; + __IM uint32_t RESERVED4[25]; + __IOM uint32_t MESSAGE_MEM[8]; /*!< The memory that stores message. */ + __IM uint32_t RESERVED5[472]; + __IOM uint32_t R_MEM[8]; /*!< The memory that stores r. */ + __IOM uint32_t S_MEM[8]; /*!< The memory that stores s. */ + __IOM uint32_t Z_MEM[8]; /*!< The memory that stores software written z. */ + __IOM uint32_t QAX_MEM[8]; /*!< The memory that stores x coordinates of QA or software written + k. */ + __IOM uint32_t QAY_MEM[8]; /*!< The memory that stores y coordinates of QA. */ +} ECDSA_Type; /*!< Size = 2720 (0xaa0) */ + + + +/* =========================================================================================================================== */ +/* ================ EFUSE ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief eFuse Controller (EFUSE) + */ + +typedef struct { /*!< EFUSE Structure */ + + union { + __IOM uint32_t reg; /*!< Register 0 that stores data to be programmed. */ + + struct { + __IOM uint32_t PGM_DATA_0 : 32; /*!< Configures the 0th 32-bit data to be programmed. */ + } bit; + } PGM_DATA0; + + union { + __IOM uint32_t reg; /*!< Register 1 that stores data to be programmed. */ + + struct { + __IOM uint32_t PGM_DATA_1 : 32; /*!< Configures the 1st 32-bit data to be programmed. */ + } bit; + } PGM_DATA1; + + union { + __IOM uint32_t reg; /*!< Register 2 that stores data to be programmed. */ + + struct { + __IOM uint32_t PGM_DATA_2 : 32; /*!< Configures the 2nd 32-bit data to be programmed. */ + } bit; + } PGM_DATA2; + + union { + __IOM uint32_t reg; /*!< Register 3 that stores data to be programmed. */ + + struct { + __IOM uint32_t PGM_DATA_3 : 32; /*!< Configures the 3rd 32-bit data to be programmed. */ + } bit; + } PGM_DATA3; + + union { + __IOM uint32_t reg; /*!< Register 4 that stores data to be programmed. */ + + struct { + __IOM uint32_t PGM_DATA_4 : 32; /*!< Configures the 4th 32-bit data to be programmed. */ + } bit; + } PGM_DATA4; + + union { + __IOM uint32_t reg; /*!< Register 5 that stores data to be programmed. */ + + struct { + __IOM uint32_t PGM_DATA_5 : 32; /*!< Configures the 5th 32-bit data to be programmed. */ + } bit; + } PGM_DATA5; + + union { + __IOM uint32_t reg; /*!< Register 6 that stores data to be programmed. */ + + struct { + __IOM uint32_t PGM_DATA_6 : 32; /*!< Configures the 6th 32-bit data to be programmed. */ + } bit; + } PGM_DATA6; + + union { + __IOM uint32_t reg; /*!< Register 7 that stores data to be programmed. */ + + struct { + __IOM uint32_t PGM_DATA_7 : 32; /*!< Configures the 7th 32-bit data to be programmed. */ + } bit; + } PGM_DATA7; + + union { + __IOM uint32_t reg; /*!< Register 0 that stores the RS code to be programmed. */ + + struct { + __IOM uint32_t PGM_RS_DATA_0 : 32; /*!< Configures the 0th 32-bit RS code to be programmed. */ + } bit; + } PGM_CHECK_VALUE0; + + union { + __IOM uint32_t reg; /*!< Register 1 that stores the RS code to be programmed. */ + + struct { + __IOM uint32_t PGM_RS_DATA_1 : 32; /*!< Configures the 1st 32-bit RS code to be programmed. */ + } bit; + } PGM_CHECK_VALUE1; + + union { + __IOM uint32_t reg; /*!< Register 2 that stores the RS code to be programmed. */ + + struct { + __IOM uint32_t PGM_RS_DATA_2 : 32; /*!< Configures the 2nd 32-bit RS code to be programmed. */ + } bit; + } PGM_CHECK_VALUE2; + + union { + __IOM uint32_t reg; /*!< BLOCK0 data register 0. */ + + struct { + __IM uint32_t WR_DIS : 32; /*!< Represents whether programming of individual eFuse memory bit + is disabled or enabled. 1: Disabled. 0 Enabled. */ + } bit; + } RD_WR_DIS; + + union { + __IOM uint32_t reg; /*!< BLOCK0 data register 1. */ + + struct { + __IM uint32_t RD_DIS : 7; /*!< Represents whether reading of individual eFuse block(block4~block10) + is disabled or enabled. 1: disabled. 0: enabled. */ + __IM uint32_t USB_DEVICE_EXCHG_PINS : 1; /*!< Enable usb device exchange pins of D+ and D-. */ + __IM uint32_t USB_OTG11_EXCHG_PINS : 1; /*!< Enable usb otg11 exchange pins of D+ and D-. */ + __IM uint32_t DIS_USB_JTAG : 1; /*!< Represents whether the function of usb switch to jtag is disabled + or enabled. 1: disabled. 0: enabled. */ + __IM uint32_t POWERGLITCH_EN : 1; /*!< Represents whether power glitch function is enabled. 1: enabled. + 0: disabled. */ + __IM uint32_t DIS_USB_SERIAL_JTAG : 1; /*!< Represents whether USB-Serial-JTAG is disabled or enabled. 1: + disabled. 0: enabled. */ + __IM uint32_t DIS_FORCE_DOWNLOAD : 1; /*!< Represents whether the function that forces chip into download + mode is disabled or enabled. 1: disabled. 0: enabled. */ + __IM uint32_t SPI_DOWNLOAD_MSPI_DIS : 1; /*!< Set this bit to disable accessing MSPI flash/MSPI ram by SYS + AXI matrix during boot_mode_download. */ + __IM uint32_t DIS_TWAI : 1; /*!< Represents whether TWAI function is disabled or enabled. 1: + disabled. 0: enabled. */ + __IM uint32_t JTAG_SEL_ENABLE : 1; /*!< Represents whether the selection between usb_to_jtag and pad_to_jtag + through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and + EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. + 1: enabled. 0: disabled. */ + __IM uint32_t SOFT_DIS_JTAG : 3; /*!< Represents whether JTAG is disabled in soft way. Odd number: + disabled. Even number: enabled. */ + __IM uint32_t DIS_PAD_JTAG : 1; /*!< Represents whether JTAG is disabled in the hard way(permanently). + 1: disabled. 0: enabled. */ + __IM uint32_t DIS_DOWNLOAD_MANUAL_ENCRYPT : 1;/*!< Represents whether flash encrypt function is disabled or enabled(except + in SPI boot mode). 1: disabled. 0: enabled. */ + __IM uint32_t USB_DEVICE_DREFH : 2; /*!< USB intphy of usb device signle-end input high threshold, 1.76V + to 2V. Step by 80mV */ + __IM uint32_t USB_OTG11_DREFH : 2; /*!< USB intphy of usb otg11 signle-end input high threshold, 1.76V + to 2V. Step by 80mV */ + __IM uint32_t USB_PHY_SEL : 1; /*!< TBD */ + __IM uint32_t KM_HUK_GEN_STATE_LOW : 6; /*!< Set this bit to control validation of HUK generate mode. Odd + of 1 is invalid, even of 1 is valid. */ + } bit; + } RD_REPEAT_DATA0; + + union { + __IOM uint32_t reg; /*!< BLOCK0 data register 2. */ + + struct { + __IM uint32_t KM_HUK_GEN_STATE_HIGH : 3; /*!< Set this bit to control validation of HUK generate mode. Odd + of 1 is invalid, even of 1 is valid. */ + __IM uint32_t KM_RND_SWITCH_CYCLE : 2; /*!< Set bits to control key manager random number switch cycle. + 0: control by register. 1: 8 km clk cycles. 2: 16 km cycles. + 3: 32 km cycles. */ + __IM uint32_t KM_DEPLOY_ONLY_ONCE : 4; /*!< Set each bit to control whether corresponding key can only be + deployed once. 1 is true, 0 is false. Bit0: ecdsa. Bit1: + xts. Bit2: hmac. Bit3: ds. */ + __IM uint32_t FORCE_USE_KEY_MANAGER_KEY : 4;/*!< Set each bit to control whether corresponding key must come + from key manager.. 1 is true, 0 is false. Bit0: ecdsa. + Bit1: xts. Bit2: hmac. Bit3: ds. */ + __IM uint32_t FORCE_DISABLE_SW_INIT_KEY : 1;/*!< Set this bit to disable software written init key, and force + use efuse_init_key. */ + __IM uint32_t XTS_KEY_LENGTH_256 : 1; /*!< Set this bit to configure flash encryption use xts-128 key, + else use xts-256 key. */ + uint32_t : 1; + __IM uint32_t WDT_DELAY_SEL : 2; /*!< Represents whether RTC watchdog timeout threshold is selected + at startup. 1: selected. 0: not selected. */ + __IM uint32_t SPI_BOOT_CRYPT_CNT : 3; /*!< Represents whether SPI boot encrypt/decrypt is disabled or enabled. + Odd number of 1: enabled. Even number of 1: disabled. */ + __IM uint32_t SECURE_BOOT_KEY_REVOKE0 : 1;/*!< Represents whether revoking first secure boot key is enabled + or disabled. 1: enabled. 0: disabled. */ + __IM uint32_t SECURE_BOOT_KEY_REVOKE1 : 1;/*!< Represents whether revoking second secure boot key is enabled + or disabled. 1: enabled. 0: disabled. */ + __IM uint32_t SECURE_BOOT_KEY_REVOKE2 : 1;/*!< Represents whether revoking third secure boot key is enabled + or disabled. 1: enabled. 0: disabled. */ + __IM uint32_t KEY_PURPOSE_0 : 4; /*!< Represents the purpose of Key0. */ + __IM uint32_t KEY_PURPOSE_1 : 4; /*!< Represents the purpose of Key1. */ + } bit; + } RD_REPEAT_DATA1; + + union { + __IOM uint32_t reg; /*!< BLOCK0 data register 3. */ + + struct { + __IM uint32_t KEY_PURPOSE_2 : 4; /*!< Represents the purpose of Key2. */ + __IM uint32_t KEY_PURPOSE_3 : 4; /*!< Represents the purpose of Key3. */ + __IM uint32_t KEY_PURPOSE_4 : 4; /*!< Represents the purpose of Key4. */ + __IM uint32_t KEY_PURPOSE_5 : 4; /*!< Represents the purpose of Key5. */ + __IM uint32_t SEC_DPA_LEVEL : 2; /*!< Represents the spa secure level by configuring the clock random + divide mode. */ + __IM uint32_t ECDSA_ENABLE_SOFT_K : 1; /*!< Represents whether hardware random number k is forced used in + ESDCA. 1: force used. 0: not force used. */ + __IM uint32_t CRYPT_DPA_ENABLE : 1; /*!< Represents whether anti-dpa attack is enabled. 1:enabled. 0: + disabled. */ + __IM uint32_t SECURE_BOOT_EN : 1; /*!< Represents whether secure boot is enabled or disabled. 1: enabled. + 0: disabled. */ + __IM uint32_t SECURE_BOOT_AGGRESSIVE_REVOKE : 1;/*!< Represents whether revoking aggressive secure boot is enabled + or disabled. 1: enabled. 0: disabled. */ + uint32_t : 1; + __IM uint32_t FLASH_TYPE : 1; /*!< The type of interfaced flash. 0: four data lines, 1: eight data + lines. */ + __IM uint32_t FLASH_PAGE_SIZE : 2; /*!< Set flash page size. */ + __IM uint32_t FLASH_ECC_EN : 1; /*!< Set this bit to enable ecc for flash boot. */ + __IM uint32_t DIS_USB_OTG_DOWNLOAD_MODE : 1;/*!< Set this bit to disable download via USB-OTG. */ + __IM uint32_t FLASH_TPUW : 4; /*!< Represents the flash waiting time after power-up, in unit of + ms. When the value less than 15, the waiting time is the + programmed value. Otherwise, the waiting time is 2 times + the programmed value. */ + } bit; + } RD_REPEAT_DATA2; + + union { + __IOM uint32_t reg; /*!< BLOCK0 data register 4. */ + + struct { + __IM uint32_t DIS_DOWNLOAD_MODE : 1; /*!< Represents whether Download mode is disabled or enabled. 1: + disabled. 0: enabled. */ + __IM uint32_t DIS_DIRECT_BOOT : 1; /*!< Represents whether direct boot mode is disabled or enabled. + 1: disabled. 0: enabled. */ + __IM uint32_t DIS_USB_SERIAL_JTAG_ROM_PRINT : 1;/*!< Represents whether print from USB-Serial-JTAG is disabled or + enabled. 1: disabled. 0: enabled. */ + __IM uint32_t LOCK_KM_KEY : 1; /*!< TBD */ + __IM uint32_t DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE : 1;/*!< Represents whether the USB-Serial-JTAG download function is + disabled or enabled. 1: disabled. 0: enabled. */ + __IM uint32_t ENABLE_SECURITY_DOWNLOAD : 1;/*!< Represents whether security download is enabled or disabled. + 1: enabled. 0: disabled. */ + __IM uint32_t UART_PRINT_CONTROL : 2; /*!< Represents the type of UART printing. 00: force enable printing. + 01: enable printing when GPIO8 is reset at low level. 10: + enable printing when GPIO8 is reset at high level. 11: + force disable printing. */ + __IM uint32_t FORCE_SEND_RESUME : 1; /*!< Represents whether ROM code is forced to send a resume command + during SPI boot. 1: forced. 0:not forced. */ + __IM uint32_t SECURE_VERSION : 16; /*!< Represents the version used by ESP-IDF anti-rollback feature. */ + __IM uint32_t SECURE_BOOT_DISABLE_FAST_WAKE : 1;/*!< Represents whether FAST VERIFY ON WAKE is disabled or enabled + when Secure Boot is enabled. 1: disabled. 0: enabled. */ + __IM uint32_t HYS_EN_PAD : 1; /*!< Represents whether the hysteresis function of corresponding + PAD is enabled. 1: enabled. 0:disabled. */ + __IM uint32_t DCDC_VSET : 5; /*!< Set the dcdc voltage default. */ + } bit; + } RD_REPEAT_DATA3; + + union { + __IOM uint32_t reg; /*!< BLOCK0 data register 5. */ + + struct { + __IM uint32_t _0PXA_TIEH_SEL_0 : 2; /*!< TBD */ + __IM uint32_t _0PXA_TIEH_SEL_1 : 2; /*!< TBD. */ + __IM uint32_t _0PXA_TIEH_SEL_2 : 2; /*!< TBD. */ + __IM uint32_t _0PXA_TIEH_SEL_3 : 2; /*!< TBD. */ + __IM uint32_t KM_DISABLE_DEPLOY_MODE : 4;/*!< TBD. */ + __IM uint32_t USB_DEVICE_DREFL : 2; /*!< Represents the usb device single-end input low threhold, 0.8 + V to 1.04 V with step of 80 mV. */ + __IM uint32_t USB_OTG11_DREFL : 2; /*!< Represents the usb otg11 single-end input low threhold, 0.8 + V to 1.04 V with step of 80 mV. */ + uint32_t : 2; + __IM uint32_t HP_PWR_SRC_SEL : 1; /*!< HP system power source select. 0:LDO. 1: DCDC. */ + __IM uint32_t DCDC_VSET_EN : 1; /*!< Select dcdc vset use efuse_dcdc_vset. */ + __IM uint32_t DIS_WDT : 1; /*!< Set this bit to disable watch dog. */ + __IM uint32_t DIS_SWD : 1; /*!< Set this bit to disable super-watchdog. */ + uint32_t : 10; + } bit; + } RD_REPEAT_DATA4; + + union { + __IOM uint32_t reg; /*!< BLOCK1 data register $n. */ + + struct { + __IM uint32_t MAC_0 : 32; /*!< Stores the low 32 bits of MAC address. */ + } bit; + } RD_MAC_SYS_0; + + union { + __IOM uint32_t reg; /*!< BLOCK1 data register $n. */ + + struct { + __IM uint32_t MAC_1 : 16; /*!< Stores the high 16 bits of MAC address. */ + __IM uint32_t MAC_EXT : 16; /*!< Stores the extended bits of MAC address. */ + } bit; + } RD_MAC_SYS_1; + + union { + __IOM uint32_t reg; /*!< BLOCK1 data register $n. */ + + struct { + __IM uint32_t MAC_RESERVED_1 : 14; /*!< Reserved. */ + __IM uint32_t MAC_RESERVED_0 : 18; /*!< Reserved. */ + } bit; + } RD_MAC_SYS_2; + + union { + __IOM uint32_t reg; /*!< BLOCK1 data register $n. */ + + struct { + __IM uint32_t MAC_RESERVED_2 : 18; /*!< Reserved. */ + __IM uint32_t SYS_DATA_PART0_0 : 14; /*!< Stores the first 14 bits of the zeroth part of system data. */ + } bit; + } RD_MAC_SYS_3; + + union { + __IOM uint32_t reg; /*!< BLOCK1 data register $n. */ + + struct { + __IM uint32_t SYS_DATA_PART0_1 : 32; /*!< Stores the first 32 bits of the zeroth part of system data. */ + } bit; + } RD_MAC_SYS_4; + + union { + __IOM uint32_t reg; /*!< BLOCK1 data register $n. */ + + struct { + __IM uint32_t SYS_DATA_PART0_2 : 32; /*!< Stores the second 32 bits of the zeroth part of system data. */ + } bit; + } RD_MAC_SYS_5; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK2 (system). */ + + struct { + __IM uint32_t SYS_DATA_PART1_0 : 32; /*!< Stores the zeroth 32 bits of the first part of system data. */ + } bit; + } RD_SYS_PART1_DATA0; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK2 (system). */ + + struct { + __IM uint32_t SYS_DATA_PART1_1 : 32; /*!< Stores the first 32 bits of the first part of system data. */ + } bit; + } RD_SYS_PART1_DATA1; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK2 (system). */ + + struct { + __IM uint32_t SYS_DATA_PART1_2 : 32; /*!< Stores the second 32 bits of the first part of system data. */ + } bit; + } RD_SYS_PART1_DATA2; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK2 (system). */ + + struct { + __IM uint32_t SYS_DATA_PART1_3 : 32; /*!< Stores the third 32 bits of the first part of system data. */ + } bit; + } RD_SYS_PART1_DATA3; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK2 (system). */ + + struct { + __IM uint32_t SYS_DATA_PART1_4 : 32; /*!< Stores the fourth 32 bits of the first part of system data. */ + } bit; + } RD_SYS_PART1_DATA4; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK2 (system). */ + + struct { + __IM uint32_t SYS_DATA_PART1_5 : 32; /*!< Stores the fifth 32 bits of the first part of system data. */ + } bit; + } RD_SYS_PART1_DATA5; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK2 (system). */ + + struct { + __IM uint32_t SYS_DATA_PART1_6 : 32; /*!< Stores the sixth 32 bits of the first part of system data. */ + } bit; + } RD_SYS_PART1_DATA6; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK2 (system). */ + + struct { + __IM uint32_t SYS_DATA_PART1_7 : 32; /*!< Stores the seventh 32 bits of the first part of system data. */ + } bit; + } RD_SYS_PART1_DATA7; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK3 (user). */ + + struct { + __IM uint32_t USR_DATA0 : 32; /*!< Stores the zeroth 32 bits of BLOCK3 (user). */ + } bit; + } RD_USR_DATA0; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK3 (user). */ + + struct { + __IM uint32_t USR_DATA1 : 32; /*!< Stores the first 32 bits of BLOCK3 (user). */ + } bit; + } RD_USR_DATA1; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK3 (user). */ + + struct { + __IM uint32_t USR_DATA2 : 32; /*!< Stores the second 32 bits of BLOCK3 (user). */ + } bit; + } RD_USR_DATA2; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK3 (user). */ + + struct { + __IM uint32_t USR_DATA3 : 32; /*!< Stores the third 32 bits of BLOCK3 (user). */ + } bit; + } RD_USR_DATA3; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK3 (user). */ + + struct { + __IM uint32_t USR_DATA4 : 32; /*!< Stores the fourth 32 bits of BLOCK3 (user). */ + } bit; + } RD_USR_DATA4; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK3 (user). */ + + struct { + __IM uint32_t USR_DATA5 : 32; /*!< Stores the fifth 32 bits of BLOCK3 (user). */ + } bit; + } RD_USR_DATA5; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK3 (user). */ + + struct { + __IM uint32_t USR_DATA6 : 32; /*!< Stores the sixth 32 bits of BLOCK3 (user). */ + } bit; + } RD_USR_DATA6; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK3 (user). */ + + struct { + __IM uint32_t USR_DATA7 : 32; /*!< Stores the seventh 32 bits of BLOCK3 (user). */ + } bit; + } RD_USR_DATA7; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK4 (KEY0). */ + + struct { + __IM uint32_t KEY0_DATA0 : 32; /*!< Stores the zeroth 32 bits of KEY0. */ + } bit; + } RD_KEY0_DATA0; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK4 (KEY0). */ + + struct { + __IM uint32_t KEY0_DATA1 : 32; /*!< Stores the first 32 bits of KEY0. */ + } bit; + } RD_KEY0_DATA1; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK4 (KEY0). */ + + struct { + __IM uint32_t KEY0_DATA2 : 32; /*!< Stores the second 32 bits of KEY0. */ + } bit; + } RD_KEY0_DATA2; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK4 (KEY0). */ + + struct { + __IM uint32_t KEY0_DATA3 : 32; /*!< Stores the third 32 bits of KEY0. */ + } bit; + } RD_KEY0_DATA3; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK4 (KEY0). */ + + struct { + __IM uint32_t KEY0_DATA4 : 32; /*!< Stores the fourth 32 bits of KEY0. */ + } bit; + } RD_KEY0_DATA4; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK4 (KEY0). */ + + struct { + __IM uint32_t KEY0_DATA5 : 32; /*!< Stores the fifth 32 bits of KEY0. */ + } bit; + } RD_KEY0_DATA5; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK4 (KEY0). */ + + struct { + __IM uint32_t KEY0_DATA6 : 32; /*!< Stores the sixth 32 bits of KEY0. */ + } bit; + } RD_KEY0_DATA6; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK4 (KEY0). */ + + struct { + __IM uint32_t KEY0_DATA7 : 32; /*!< Stores the seventh 32 bits of KEY0. */ + } bit; + } RD_KEY0_DATA7; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK5 (KEY1). */ + + struct { + __IM uint32_t KEY1_DATA0 : 32; /*!< Stores the zeroth 32 bits of KEY1. */ + } bit; + } RD_KEY1_DATA0; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK5 (KEY1). */ + + struct { + __IM uint32_t KEY1_DATA1 : 32; /*!< Stores the first 32 bits of KEY1. */ + } bit; + } RD_KEY1_DATA1; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK5 (KEY1). */ + + struct { + __IM uint32_t KEY1_DATA2 : 32; /*!< Stores the second 32 bits of KEY1. */ + } bit; + } RD_KEY1_DATA2; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK5 (KEY1). */ + + struct { + __IM uint32_t KEY1_DATA3 : 32; /*!< Stores the third 32 bits of KEY1. */ + } bit; + } RD_KEY1_DATA3; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK5 (KEY1). */ + + struct { + __IM uint32_t KEY1_DATA4 : 32; /*!< Stores the fourth 32 bits of KEY1. */ + } bit; + } RD_KEY1_DATA4; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK5 (KEY1). */ + + struct { + __IM uint32_t KEY1_DATA5 : 32; /*!< Stores the fifth 32 bits of KEY1. */ + } bit; + } RD_KEY1_DATA5; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK5 (KEY1). */ + + struct { + __IM uint32_t KEY1_DATA6 : 32; /*!< Stores the sixth 32 bits of KEY1. */ + } bit; + } RD_KEY1_DATA6; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK5 (KEY1). */ + + struct { + __IM uint32_t KEY1_DATA7 : 32; /*!< Stores the seventh 32 bits of KEY1. */ + } bit; + } RD_KEY1_DATA7; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK6 (KEY2). */ + + struct { + __IM uint32_t KEY2_DATA0 : 32; /*!< Stores the zeroth 32 bits of KEY2. */ + } bit; + } RD_KEY2_DATA0; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK6 (KEY2). */ + + struct { + __IM uint32_t KEY2_DATA1 : 32; /*!< Stores the first 32 bits of KEY2. */ + } bit; + } RD_KEY2_DATA1; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK6 (KEY2). */ + + struct { + __IM uint32_t KEY2_DATA2 : 32; /*!< Stores the second 32 bits of KEY2. */ + } bit; + } RD_KEY2_DATA2; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK6 (KEY2). */ + + struct { + __IM uint32_t KEY2_DATA3 : 32; /*!< Stores the third 32 bits of KEY2. */ + } bit; + } RD_KEY2_DATA3; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK6 (KEY2). */ + + struct { + __IM uint32_t KEY2_DATA4 : 32; /*!< Stores the fourth 32 bits of KEY2. */ + } bit; + } RD_KEY2_DATA4; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK6 (KEY2). */ + + struct { + __IM uint32_t KEY2_DATA5 : 32; /*!< Stores the fifth 32 bits of KEY2. */ + } bit; + } RD_KEY2_DATA5; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK6 (KEY2). */ + + struct { + __IM uint32_t KEY2_DATA6 : 32; /*!< Stores the sixth 32 bits of KEY2. */ + } bit; + } RD_KEY2_DATA6; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK6 (KEY2). */ + + struct { + __IM uint32_t KEY2_DATA7 : 32; /*!< Stores the seventh 32 bits of KEY2. */ + } bit; + } RD_KEY2_DATA7; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK7 (KEY3). */ + + struct { + __IM uint32_t KEY3_DATA0 : 32; /*!< Stores the zeroth 32 bits of KEY3. */ + } bit; + } RD_KEY3_DATA0; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK7 (KEY3). */ + + struct { + __IM uint32_t KEY3_DATA1 : 32; /*!< Stores the first 32 bits of KEY3. */ + } bit; + } RD_KEY3_DATA1; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK7 (KEY3). */ + + struct { + __IM uint32_t KEY3_DATA2 : 32; /*!< Stores the second 32 bits of KEY3. */ + } bit; + } RD_KEY3_DATA2; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK7 (KEY3). */ + + struct { + __IM uint32_t KEY3_DATA3 : 32; /*!< Stores the third 32 bits of KEY3. */ + } bit; + } RD_KEY3_DATA3; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK7 (KEY3). */ + + struct { + __IM uint32_t KEY3_DATA4 : 32; /*!< Stores the fourth 32 bits of KEY3. */ + } bit; + } RD_KEY3_DATA4; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK7 (KEY3). */ + + struct { + __IM uint32_t KEY3_DATA5 : 32; /*!< Stores the fifth 32 bits of KEY3. */ + } bit; + } RD_KEY3_DATA5; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK7 (KEY3). */ + + struct { + __IM uint32_t KEY3_DATA6 : 32; /*!< Stores the sixth 32 bits of KEY3. */ + } bit; + } RD_KEY3_DATA6; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK7 (KEY3). */ + + struct { + __IM uint32_t KEY3_DATA7 : 32; /*!< Stores the seventh 32 bits of KEY3. */ + } bit; + } RD_KEY3_DATA7; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK8 (KEY4). */ + + struct { + __IM uint32_t KEY4_DATA0 : 32; /*!< Stores the zeroth 32 bits of KEY4. */ + } bit; + } RD_KEY4_DATA0; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK8 (KEY4). */ + + struct { + __IM uint32_t KEY4_DATA1 : 32; /*!< Stores the first 32 bits of KEY4. */ + } bit; + } RD_KEY4_DATA1; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK8 (KEY4). */ + + struct { + __IM uint32_t KEY4_DATA2 : 32; /*!< Stores the second 32 bits of KEY4. */ + } bit; + } RD_KEY4_DATA2; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK8 (KEY4). */ + + struct { + __IM uint32_t KEY4_DATA3 : 32; /*!< Stores the third 32 bits of KEY4. */ + } bit; + } RD_KEY4_DATA3; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK8 (KEY4). */ + + struct { + __IM uint32_t KEY4_DATA4 : 32; /*!< Stores the fourth 32 bits of KEY4. */ + } bit; + } RD_KEY4_DATA4; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK8 (KEY4). */ + + struct { + __IM uint32_t KEY4_DATA5 : 32; /*!< Stores the fifth 32 bits of KEY4. */ + } bit; + } RD_KEY4_DATA5; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK8 (KEY4). */ + + struct { + __IM uint32_t KEY4_DATA6 : 32; /*!< Stores the sixth 32 bits of KEY4. */ + } bit; + } RD_KEY4_DATA6; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK8 (KEY4). */ + + struct { + __IM uint32_t KEY4_DATA7 : 32; /*!< Stores the seventh 32 bits of KEY4. */ + } bit; + } RD_KEY4_DATA7; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK9 (KEY5). */ + + struct { + __IM uint32_t KEY5_DATA0 : 32; /*!< Stores the zeroth 32 bits of KEY5. */ + } bit; + } RD_KEY5_DATA0; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK9 (KEY5). */ + + struct { + __IM uint32_t KEY5_DATA1 : 32; /*!< Stores the first 32 bits of KEY5. */ + } bit; + } RD_KEY5_DATA1; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK9 (KEY5). */ + + struct { + __IM uint32_t KEY5_DATA2 : 32; /*!< Stores the second 32 bits of KEY5. */ + } bit; + } RD_KEY5_DATA2; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK9 (KEY5). */ + + struct { + __IM uint32_t KEY5_DATA3 : 32; /*!< Stores the third 32 bits of KEY5. */ + } bit; + } RD_KEY5_DATA3; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK9 (KEY5). */ + + struct { + __IM uint32_t KEY5_DATA4 : 32; /*!< Stores the fourth 32 bits of KEY5. */ + } bit; + } RD_KEY5_DATA4; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK9 (KEY5). */ + + struct { + __IM uint32_t KEY5_DATA5 : 32; /*!< Stores the fifth 32 bits of KEY5. */ + } bit; + } RD_KEY5_DATA5; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK9 (KEY5). */ + + struct { + __IM uint32_t KEY5_DATA6 : 32; /*!< Stores the sixth 32 bits of KEY5. */ + } bit; + } RD_KEY5_DATA6; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK9 (KEY5). */ + + struct { + __IM uint32_t KEY5_DATA7 : 32; /*!< Stores the seventh 32 bits of KEY5. */ + } bit; + } RD_KEY5_DATA7; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK10 (system). */ + + struct { + __IM uint32_t SYS_DATA_PART2_0 : 32; /*!< Stores the 0th 32 bits of the 2nd part of system data. */ + } bit; + } RD_SYS_PART2_DATA0; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK9 (KEY5). */ + + struct { + __IM uint32_t SYS_DATA_PART2_1 : 32; /*!< Stores the 0th 32 bits of the 2nd part of system data. */ + } bit; + } RD_SYS_PART2_DATA1; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK10 (system). */ + + struct { + __IM uint32_t SYS_DATA_PART2_2 : 32; /*!< Stores the 0th 32 bits of the 2nd part of system data. */ + } bit; + } RD_SYS_PART2_DATA2; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK10 (system). */ + + struct { + __IM uint32_t SYS_DATA_PART2_3 : 32; /*!< Stores the 0th 32 bits of the 2nd part of system data. */ + } bit; + } RD_SYS_PART2_DATA3; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK10 (system). */ + + struct { + __IM uint32_t SYS_DATA_PART2_4 : 32; /*!< Stores the 0th 32 bits of the 2nd part of system data. */ + } bit; + } RD_SYS_PART2_DATA4; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK10 (system). */ + + struct { + __IM uint32_t SYS_DATA_PART2_5 : 32; /*!< Stores the 0th 32 bits of the 2nd part of system data. */ + } bit; + } RD_SYS_PART2_DATA5; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK10 (system). */ + + struct { + __IM uint32_t SYS_DATA_PART2_6 : 32; /*!< Stores the 0th 32 bits of the 2nd part of system data. */ + } bit; + } RD_SYS_PART2_DATA6; + + union { + __IOM uint32_t reg; /*!< Register $n of BLOCK10 (system). */ + + struct { + __IM uint32_t SYS_DATA_PART2_7 : 32; /*!< Stores the 0th 32 bits of the 2nd part of system data. */ + } bit; + } RD_SYS_PART2_DATA7; + + union { + __IOM uint32_t reg; /*!< Programming error record register 0 of BLOCK0. */ + + struct { + __IM uint32_t RD_DIS_ERR : 7; /*!< Indicates a programming error of RD_DIS. */ + __IM uint32_t DIS_USB_DEVICE_EXCHG_PINS_ERR : 1;/*!< Indicates a programming error of DIS_USB_DEVICE_EXCHG_PINS. */ + __IM uint32_t DIS_USB_OTG11_EXCHG_PINS_ERR : 1;/*!< Indicates a programming error of DIS_USB_OTG11_EXCHG_PINS. */ + __IM uint32_t DIS_USB_JTAG_ERR : 1; /*!< Indicates a programming error of DIS_USB_JTAG. */ + __IM uint32_t POWERGLITCH_EN_ERR : 1; /*!< Indicates a programming error of POWERGLITCH_EN. */ + __IM uint32_t DIS_USB_SERIAL_JTAG_ERR : 1;/*!< Indicates a programming error of DIS_USB_SERIAL_JTAG. */ + __IM uint32_t DIS_FORCE_DOWNLOAD_ERR : 1;/*!< Indicates a programming error of DIS_FORCE_DOWNLOAD. */ + __IM uint32_t SPI_DOWNLOAD_MSPI_DIS_ERR : 1;/*!< Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS. */ + __IM uint32_t DIS_TWAI_ERR : 1; /*!< Indicates a programming error of DIS_TWAI. */ + __IM uint32_t JTAG_SEL_ENABLE_ERR : 1; /*!< Indicates a programming error of JTAG_SEL_ENABLE. */ + __IM uint32_t SOFT_DIS_JTAG_ERR : 3; /*!< Indicates a programming error of SOFT_DIS_JTAG. */ + __IM uint32_t DIS_PAD_JTAG_ERR : 1; /*!< Indicates a programming error of DIS_PAD_JTAG. */ + __IM uint32_t DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : 1;/*!< Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT. */ + __IM uint32_t USB_DEVICE_DREFH_ERR : 2; /*!< Indicates a programming error of USB_DEVICE_DREFH. */ + __IM uint32_t USB_OTG11_DREFH_ERR : 2; /*!< Indicates a programming error of USB_OTG11_DREFH. */ + __IM uint32_t USB_PHY_SEL_ERR : 1; /*!< Indicates a programming error of USB_PHY_SEL. */ + __IM uint32_t HUK_GEN_STATE_LOW_ERR : 6; /*!< Indicates a programming error of HUK_GEN_STATE_LOW. */ + } bit; + } RD_REPEAT_ERR0; + + union { + __IOM uint32_t reg; /*!< Programming error record register 1 of BLOCK0. */ + + struct { + __IM uint32_t KM_HUK_GEN_STATE_HIGH_ERR : 3;/*!< Indicates a programming error of HUK_GEN_STATE_HIGH. */ + __IM uint32_t KM_RND_SWITCH_CYCLE_ERR : 2;/*!< Indicates a programming error of KM_RND_SWITCH_CYCLE. */ + __IM uint32_t KM_DEPLOY_ONLY_ONCE_ERR : 4;/*!< Indicates a programming error of KM_DEPLOY_ONLY_ONCE. */ + __IM uint32_t FORCE_USE_KEY_MANAGER_KEY_ERR : 4;/*!< Indicates a programming error of FORCE_USE_KEY_MANAGER_KEY. */ + __IM uint32_t FORCE_DISABLE_SW_INIT_KEY_ERR : 1;/*!< Indicates a programming error of FORCE_DISABLE_SW_INIT_KEY. */ + __IM uint32_t XTS_KEY_LENGTH_256_ERR : 1;/*!< Indicates a programming error of XTS_KEY_LENGTH_256. */ + uint32_t : 1; + __IM uint32_t WDT_DELAY_SEL_ERR : 2; /*!< Indicates a programming error of WDT_DELAY_SEL. */ + __IM uint32_t SPI_BOOT_CRYPT_CNT_ERR : 3;/*!< Indicates a programming error of SPI_BOOT_CRYPT_CNT. */ + __IM uint32_t SECURE_BOOT_KEY_REVOKE0_ERR : 1;/*!< Indicates a programming error of SECURE_BOOT_KEY_REVOKE0. */ + __IM uint32_t SECURE_BOOT_KEY_REVOKE1_ERR : 1;/*!< Indicates a programming error of SECURE_BOOT_KEY_REVOKE1. */ + __IM uint32_t SECURE_BOOT_KEY_REVOKE2_ERR : 1;/*!< Indicates a programming error of SECURE_BOOT_KEY_REVOKE2. */ + __IM uint32_t KEY_PURPOSE_0_ERR : 4; /*!< Indicates a programming error of KEY_PURPOSE_0. */ + __IM uint32_t KEY_PURPOSE_1_ERR : 4; /*!< Indicates a programming error of KEY_PURPOSE_1. */ + } bit; + } RD_REPEAT_ERR1; + + union { + __IOM uint32_t reg; /*!< Programming error record register 2 of BLOCK0. */ + + struct { + __IM uint32_t KEY_PURPOSE_2_ERR : 4; /*!< Indicates a programming error of KEY_PURPOSE_2. */ + __IM uint32_t KEY_PURPOSE_3_ERR : 4; /*!< Indicates a programming error of KEY_PURPOSE_3. */ + __IM uint32_t KEY_PURPOSE_4_ERR : 4; /*!< Indicates a programming error of KEY_PURPOSE_4. */ + __IM uint32_t KEY_PURPOSE_5_ERR : 4; /*!< Indicates a programming error of KEY_PURPOSE_5. */ + __IM uint32_t SEC_DPA_LEVEL_ERR : 2; /*!< Indicates a programming error of SEC_DPA_LEVEL. */ + __IM uint32_t ECDSA_ENABLE_SOFT_K_ERR : 1;/*!< Indicates a programming error of ECDSA_FORCE_USE_HARDWARE_K. */ + __IM uint32_t CRYPT_DPA_ENABLE_ERR : 1; /*!< Indicates a programming error of CRYPT_DPA_ENABLE. */ + __IM uint32_t SECURE_BOOT_EN_ERR : 1; /*!< Indicates a programming error of SECURE_BOOT_EN. */ + __IM uint32_t SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : 1;/*!< Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE. */ + uint32_t : 1; + __IM uint32_t FLASH_TYPE_ERR : 1; /*!< Indicates a programming error of FLASH_TYPE. */ + __IM uint32_t FLASH_PAGE_SIZE_ERR : 2; /*!< Indicates a programming error of FLASH_PAGE_SIZE. */ + __IM uint32_t FLASH_ECC_EN_ERR : 1; /*!< Indicates a programming error of FLASH_ECC_EN. */ + __IM uint32_t DIS_USB_OTG_DOWNLOAD_MODE_ERR : 1;/*!< Indicates a programming error of DIS_USB_OTG_DOWNLOAD_MODE. */ + __IM uint32_t FLASH_TPUW_ERR : 4; /*!< Indicates a programming error of FLASH_TPUW. */ + } bit; + } RD_REPEAT_ERR2; + + union { + __IOM uint32_t reg; /*!< Programming error record register 3 of BLOCK0. */ + + struct { + __IM uint32_t DIS_DOWNLOAD_MODE_ERR : 1; /*!< Indicates a programming error of DIS_DOWNLOAD_MODE. */ + __IM uint32_t DIS_DIRECT_BOOT_ERR : 1; /*!< Indicates a programming error of DIS_DIRECT_BOOT. */ + __IM uint32_t DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR : 1;/*!< Indicates a programming error of DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR. */ + __IM uint32_t LOCK_KM_KEY_ERR : 1; /*!< TBD */ + __IM uint32_t DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR : 1;/*!< Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE. */ + __IM uint32_t ENABLE_SECURITY_DOWNLOAD_ERR : 1;/*!< Indicates a programming error of ENABLE_SECURITY_DOWNLOAD. */ + __IM uint32_t UART_PRINT_CONTROL_ERR : 2;/*!< Indicates a programming error of UART_PRINT_CONTROL. */ + __IM uint32_t FORCE_SEND_RESUME_ERR : 1; /*!< Indicates a programming error of FORCE_SEND_RESUME. */ + __IM uint32_t SECURE_VERSION_ERR : 16; /*!< Indicates a programming error of SECURE VERSION. */ + __IM uint32_t SECURE_BOOT_DISABLE_FAST_WAKE_ERR : 1;/*!< Indicates a programming error of SECURE_BOOT_DISABLE_FAST_WAKE. */ + __IM uint32_t HYS_EN_PAD_ERR : 1; /*!< Indicates a programming error of HYS_EN_PAD. */ + __IM uint32_t DCDC_VSET_ERR : 5; /*!< Indicates a programming error of DCDC_VSET. */ + } bit; + } RD_REPEAT_ERR3; + + union { + __IOM uint32_t reg; /*!< Programming error record register 4 of BLOCK0. */ + + struct { + __IM uint32_t _0PXA_TIEH_SEL_0_ERR : 2; /*!< Indicates a programming error of 0PXA_TIEH_SEL_0. */ + __IM uint32_t _0PXA_TIEH_SEL_1_ERR : 2; /*!< Indicates a programming error of 0PXA_TIEH_SEL_1. */ + __IM uint32_t _0PXA_TIEH_SEL_2_ERR : 2; /*!< Indicates a programming error of 0PXA_TIEH_SEL_2. */ + __IM uint32_t _0PXA_TIEH_SEL_3_ERR : 2; /*!< Indicates a programming error of 0PXA_TIEH_SEL_3. */ + __IM uint32_t KM_DISABLE_DEPLOY_MODE_ERR : 4;/*!< TBD. */ + __IM uint32_t USB_DEVICE_DREFL_ERR : 2; /*!< Indicates a programming error of USB_DEVICE_DREFL. */ + __IM uint32_t USB_OTG11_DREFL_ERR : 2; /*!< Indicates a programming error of USB_OTG11_DREFL. */ + uint32_t : 2; + __IM uint32_t HP_PWR_SRC_SEL_ERR : 1; /*!< Indicates a programming error of HP_PWR_SRC_SEL. */ + __IM uint32_t DCDC_VSET_EN_ERR : 1; /*!< Indicates a programming error of DCDC_VSET_EN. */ + __IM uint32_t DIS_WDT_ERR : 1; /*!< Indicates a programming error of DIS_WDT. */ + __IM uint32_t DIS_SWD_ERR : 1; /*!< Indicates a programming error of DIS_SWD. */ + uint32_t : 10; + } bit; + } RD_REPEAT_ERR4; + __IM uint32_t RESERVED[12]; + + union { + __IOM uint32_t reg; /*!< Programming error record register 0 of BLOCK1-10. */ + + struct { + __IM uint32_t MAC_SYS_ERR_NUM : 3; /*!< The value of this signal means the number of error bytes. */ + __IM uint32_t MAC_SYS_FAIL : 1; /*!< 0: Means no failure and that the data of MAC_SPI_8M is reliable + 1: Means that programming user data failed and the number + of error bytes is over 6. */ + __IM uint32_t SYS_PART1_ERR_NUM : 3; /*!< The value of this signal means the number of error bytes. */ + __IM uint32_t SYS_PART1_FAIL : 1; /*!< 0: Means no failure and that the data of system part1 is reliable + 1: Means that programming user data failed and the number + of error bytes is over 6. */ + __IM uint32_t USR_DATA_ERR_NUM : 3; /*!< The value of this signal means the number of error bytes. */ + __IM uint32_t USR_DATA_FAIL : 1; /*!< 0: Means no failure and that the user data is reliable 1: Means + that programming user data failed and the number of error + bytes is over 6. */ + __IM uint32_t KEY0_ERR_NUM : 3; /*!< The value of this signal means the number of error bytes. */ + __IM uint32_t KEY0_FAIL : 1; /*!< 0: Means no failure and that the data of key0 is reliable 1: + Means that programming key0 failed and the number of error + bytes is over 6. */ + __IM uint32_t KEY1_ERR_NUM : 3; /*!< The value of this signal means the number of error bytes. */ + __IM uint32_t KEY1_FAIL : 1; /*!< 0: Means no failure and that the data of key1 is reliable 1: + Means that programming key1 failed and the number of error + bytes is over 6. */ + __IM uint32_t KEY2_ERR_NUM : 3; /*!< The value of this signal means the number of error bytes. */ + __IM uint32_t KEY2_FAIL : 1; /*!< 0: Means no failure and that the data of key2 is reliable 1: + Means that programming key2 failed and the number of error + bytes is over 6. */ + __IM uint32_t KEY3_ERR_NUM : 3; /*!< The value of this signal means the number of error bytes. */ + __IM uint32_t KEY3_FAIL : 1; /*!< 0: Means no failure and that the data of key3 is reliable 1: + Means that programming key3 failed and the number of error + bytes is over 6. */ + __IM uint32_t KEY4_ERR_NUM : 3; /*!< The value of this signal means the number of error bytes. */ + __IM uint32_t KEY4_FAIL : 1; /*!< 0: Means no failure and that the data of key4 is reliable 1: + Means that programming key4 failed and the number of error + bytes is over 6. */ + } bit; + } RD_RS_ERR0; + + union { + __IOM uint32_t reg; /*!< Programming error record register 1 of BLOCK1-10. */ + + struct { + __IM uint32_t KEY5_ERR_NUM : 3; /*!< The value of this signal means the number of error bytes. */ + __IM uint32_t KEY5_FAIL : 1; /*!< 0: Means no failure and that the data of key5 is reliable 1: + Means that programming key5 failed and the number of error + bytes is over 6. */ + __IM uint32_t SYS_PART2_ERR_NUM : 3; /*!< The value of this signal means the number of error bytes. */ + __IM uint32_t SYS_PART2_FAIL : 1; /*!< 0: Means no failure and that the data of system part2 is reliable + 1: Means that programming user data failed and the number + of error bytes is over 6. */ + uint32_t : 24; + } bit; + } RD_RS_ERR1; + + union { + __IOM uint32_t reg; /*!< eFuse clcok configuration register. */ + + struct { + __IOM uint32_t MEM_FORCE_PD : 1; /*!< Set this bit to force eFuse SRAM into power-saving mode. */ + __IOM uint32_t MEM_CLK_FORCE_ON : 1; /*!< Set this bit and force to activate clock signal of eFuse SRAM. */ + __IOM uint32_t MEM_FORCE_PU : 1; /*!< Set this bit to force eFuse SRAM into working mode. */ + uint32_t : 13; + __IOM uint32_t EN : 1; /*!< Set this bit to force enable eFuse register configuration clock + signal. */ + uint32_t : 15; + } bit; + } CLK; + + union { + __IOM uint32_t reg; /*!< eFuse operation mode configuraiton register */ + + struct { + __IOM uint32_t OP_CODE : 16; /*!< 0x5A5A: programming operation command 0x5AA5: read operation + command. */ + __IOM uint32_t CFG_ECDSA_BLK : 4; /*!< Configures which block to use for ECDSA key output. */ + uint32_t : 12; + } bit; + } CONF; + + union { + __IOM uint32_t reg; /*!< eFuse status register. */ + + struct { + __IM uint32_t STATE : 4; /*!< Indicates the state of the eFuse state machine. */ + __IM uint32_t OTP_LOAD_SW : 1; /*!< The value of OTP_LOAD_SW. */ + __IM uint32_t OTP_VDDQ_C_SYNC2 : 1; /*!< The value of OTP_VDDQ_C_SYNC2. */ + __IM uint32_t OTP_STROBE_SW : 1; /*!< The value of OTP_STROBE_SW. */ + __IM uint32_t OTP_CSB_SW : 1; /*!< The value of OTP_CSB_SW. */ + __IM uint32_t OTP_PGENB_SW : 1; /*!< The value of OTP_PGENB_SW. */ + __IM uint32_t OTP_VDDQ_IS_SW : 1; /*!< The value of OTP_VDDQ_IS_SW. */ + __IM uint32_t BLK0_VALID_BIT_CNT : 10; /*!< Indicates the number of block valid bit. */ + __IM uint32_t CUR_ECDSA_BLK : 4; /*!< Indicates which block is used for ECDSA key output. */ + uint32_t : 8; + } bit; + } STATUS; + + union { + __IOM uint32_t reg; /*!< eFuse command register. */ + + struct { + __IOM uint32_t READ_CMD : 1; /*!< Set this bit to send read command. */ + __IOM uint32_t PGM_CMD : 1; /*!< Set this bit to send programming command. */ + __IOM uint32_t BLK_NUM : 4; /*!< The serial number of the block to be programmed. Value 0-10 + corresponds to block number 0-10, respectively. */ + uint32_t : 26; + } bit; + } CMD; + + union { + __IOM uint32_t reg; /*!< eFuse raw interrupt register. */ + + struct { + __IM uint32_t READ_DONE_INT_RAW : 1; /*!< The raw bit signal for read_done interrupt. */ + __IM uint32_t PGM_DONE_INT_RAW : 1; /*!< The raw bit signal for pgm_done interrupt. */ + uint32_t : 30; + } bit; + } INT_RAW; + + union { + __IOM uint32_t reg; /*!< eFuse interrupt status register. */ + + struct { + __IM uint32_t READ_DONE_INT_ST : 1; /*!< The status signal for read_done interrupt. */ + __IM uint32_t PGM_DONE_INT_ST : 1; /*!< The status signal for pgm_done interrupt. */ + uint32_t : 30; + } bit; + } INT_ST; + + union { + __IOM uint32_t reg; /*!< eFuse interrupt enable register. */ + + struct { + __IOM uint32_t READ_DONE_INT_ENA : 1; /*!< The enable signal for read_done interrupt. */ + __IOM uint32_t PGM_DONE_INT_ENA : 1; /*!< The enable signal for pgm_done interrupt. */ + uint32_t : 30; + } bit; + } INT_ENA; + + union { + __IOM uint32_t reg; /*!< eFuse interrupt clear register. */ + + struct { + __OM uint32_t READ_DONE_INT_CLR : 1; /*!< The clear signal for read_done interrupt. */ + __OM uint32_t PGM_DONE_INT_CLR : 1; /*!< The clear signal for pgm_done interrupt. */ + uint32_t : 30; + } bit; + } INT_CLR; + + union { + __IOM uint32_t reg; /*!< Controls the eFuse programming voltage. */ + + struct { + __IOM uint32_t DAC_CLK_DIV : 8; /*!< Controls the division factor of the rising clock of the programming + voltage. */ + __IOM uint32_t DAC_CLK_PAD_SEL : 1; /*!< Don't care. */ + __IOM uint32_t DAC_NUM : 8; /*!< Controls the rising period of the programming voltage. */ + __IOM uint32_t OE_CLR : 1; /*!< Reduces the power supply of the programming voltage. */ + uint32_t : 14; + } bit; + } DAC_CONF; + + union { + __IOM uint32_t reg; /*!< Configures read timing parameters. */ + + struct { + __IOM uint32_t THR_A : 8; /*!< Configures the read hold time. */ + __IOM uint32_t TRD : 8; /*!< Configures the read time. */ + __IOM uint32_t TSUR_A : 8; /*!< Configures the read setup time. */ + __IOM uint32_t READ_INIT_NUM : 8; /*!< Configures the waiting time of reading eFuse memory. */ + } bit; + } RD_TIM_CONF; + + union { + __IOM uint32_t reg; /*!< Configurarion register 1 of eFuse programming timing parameters. */ + + struct { + __IOM uint32_t TSUP_A : 8; /*!< Configures the programming setup time. */ + __IOM uint32_t PWR_ON_NUM : 16; /*!< Configures the power up time for VDDQ. */ + __IOM uint32_t THP_A : 8; /*!< Configures the programming hold time. */ + } bit; + } WR_TIM_CONF1; + + union { + __IOM uint32_t reg; /*!< Configurarion register 2 of eFuse programming timing parameters. */ + + struct { + __IOM uint32_t PWR_OFF_NUM : 16; /*!< Configures the power outage time for VDDQ. */ + __IOM uint32_t TPGM : 16; /*!< Configures the active programming time. */ + } bit; + } WR_TIM_CONF2; + + union { + __IOM uint32_t reg; /*!< Configurarion register0 of eFuse programming time parameters + and rs bypass operation. */ + + struct { + __IOM uint32_t BYPASS_RS_CORRECTION : 1; /*!< Set this bit to bypass reed solomon correction step. */ + __IOM uint32_t BYPASS_RS_BLK_NUM : 11; /*!< Configures block number of programming twice operation. */ + __OM uint32_t UPDATE : 1; /*!< Set this bit to update multi-bit register signals. */ + __IOM uint32_t TPGM_INACTIVE : 8; /*!< Configures the inactive programming time. */ + uint32_t : 11; + } bit; + } WR_TIM_CONF0_RS_BYPASS; + + union { + __IOM uint32_t reg; /*!< eFuse version register. */ + + struct { + __IOM uint32_t DATE : 28; /*!< Stores eFuse version. */ + uint32_t : 4; + } bit; + } DATE; + __IM uint32_t RESERVED1[384]; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block0 data register1. */ + + struct { + __IM uint32_t APB2OTP_BLOCK0_WR_DIS : 32;/*!< Otp block0 write disable data. */ + } bit; + } APB2OTP_WR_DIS; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block0 data register2. */ + + struct { + __IM uint32_t APB2OTP_BLOCK0_BACKUP1_W1 : 32;/*!< Otp block0 backup1 word1 data. */ + } bit; + } APB2OTP_BLK0_BACKUP1_W1; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block0 data register3. */ + + struct { + __IM uint32_t APB2OTP_BLOCK0_BACKUP1_W2 : 32;/*!< Otp block0 backup1 word2 data. */ + } bit; + } APB2OTP_BLK0_BACKUP1_W2; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block0 data register4. */ + + struct { + __IM uint32_t APB2OTP_BLOCK0_BACKUP1_W3 : 32;/*!< Otp block0 backup1 word3 data. */ + } bit; + } APB2OTP_BLK0_BACKUP1_W3; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block0 data register5. */ + + struct { + __IM uint32_t APB2OTP_BLOCK0_BACKUP1_W4 : 32;/*!< Otp block0 backup1 word4 data. */ + } bit; + } APB2OTP_BLK0_BACKUP1_W4; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block0 data register6. */ + + struct { + __IM uint32_t APB2OTP_BLOCK0_BACKUP1_W5 : 32;/*!< Otp block0 backup1 word5 data. */ + } bit; + } APB2OTP_BLK0_BACKUP1_W5; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block0 data register7. */ + + struct { + __IM uint32_t APB2OTP_BLOCK0_BACKUP2_W1 : 32;/*!< Otp block0 backup2 word1 data. */ + } bit; + } APB2OTP_BLK0_BACKUP2_W1; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block0 data register8. */ + + struct { + __IM uint32_t APB2OTP_BLOCK0_BACKUP2_W2 : 32;/*!< Otp block0 backup2 word2 data. */ + } bit; + } APB2OTP_BLK0_BACKUP2_W2; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block0 data register9. */ + + struct { + __IM uint32_t APB2OTP_BLOCK0_BACKUP2_W3 : 32;/*!< Otp block0 backup2 word3 data. */ + } bit; + } APB2OTP_BLK0_BACKUP2_W3; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block0 data register10. */ + + struct { + __IM uint32_t APB2OTP_BLOCK0_BACKUP2_W4 : 32;/*!< Otp block0 backup2 word4 data. */ + } bit; + } APB2OTP_BLK0_BACKUP2_W4; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block0 data register11. */ + + struct { + __IM uint32_t APB2OTP_BLOCK0_BACKUP2_W5 : 32;/*!< Otp block0 backup2 word5 data. */ + } bit; + } APB2OTP_BLK0_BACKUP2_W5; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block0 data register12. */ + + struct { + __IM uint32_t APB2OTP_BLOCK0_BACKUP3_W1 : 32;/*!< Otp block0 backup3 word1 data. */ + } bit; + } APB2OTP_BLK0_BACKUP3_W1; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block0 data register13. */ + + struct { + __IM uint32_t APB2OTP_BLOCK0_BACKUP3_W2 : 32;/*!< Otp block0 backup3 word2 data. */ + } bit; + } APB2OTP_BLK0_BACKUP3_W2; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block0 data register14. */ + + struct { + __IM uint32_t APB2OTP_BLOCK0_BACKUP3_W3 : 32;/*!< Otp block0 backup3 word3 data. */ + } bit; + } APB2OTP_BLK0_BACKUP3_W3; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block0 data register15. */ + + struct { + __IM uint32_t APB2OTP_BLOCK0_BACKUP3_W4 : 32;/*!< Otp block0 backup3 word4 data. */ + } bit; + } APB2OTP_BLK0_BACKUP3_W4; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block0 data register16. */ + + struct { + __IM uint32_t APB2OTP_BLOCK0_BACKUP3_W5 : 32;/*!< Otp block0 backup3 word5 data. */ + } bit; + } APB2OTP_BLK0_BACKUP3_W5; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block0 data register17. */ + + struct { + __IM uint32_t APB2OTP_BLOCK0_BACKUP4_W1 : 32;/*!< Otp block0 backup4 word1 data. */ + } bit; + } APB2OTP_BLK0_BACKUP4_W1; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block0 data register18. */ + + struct { + __IM uint32_t APB2OTP_BLOCK0_BACKUP4_W2 : 32;/*!< Otp block0 backup4 word2 data. */ + } bit; + } APB2OTP_BLK0_BACKUP4_W2; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block0 data register19. */ + + struct { + __IM uint32_t APB2OTP_BLOCK0_BACKUP4_W3 : 32;/*!< Otp block0 backup4 word3 data. */ + } bit; + } APB2OTP_BLK0_BACKUP4_W3; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block0 data register20. */ + + struct { + __IM uint32_t APB2OTP_BLOCK0_BACKUP4_W4 : 32;/*!< Otp block0 backup4 word4 data. */ + } bit; + } APB2OTP_BLK0_BACKUP4_W4; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block0 data register21. */ + + struct { + __IM uint32_t APB2OTP_BLOCK0_BACKUP4_W5 : 32;/*!< Otp block0 backup4 word5 data. */ + } bit; + } APB2OTP_BLK0_BACKUP4_W5; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block1 data register1. */ + + struct { + __IM uint32_t APB2OTP_BLOCK1_W1 : 32; /*!< Otp block1 word1 data. */ + } bit; + } APB2OTP_BLK1_W1; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block1 data register2. */ + + struct { + __IM uint32_t APB2OTP_BLOCK1_W2 : 32; /*!< Otp block1 word2 data. */ + } bit; + } APB2OTP_BLK1_W2; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block1 data register3. */ + + struct { + __IM uint32_t APB2OTP_BLOCK1_W3 : 32; /*!< Otp block1 word3 data. */ + } bit; + } APB2OTP_BLK1_W3; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block1 data register4. */ + + struct { + __IM uint32_t APB2OTP_BLOCK1_W4 : 32; /*!< Otp block1 word4 data. */ + } bit; + } APB2OTP_BLK1_W4; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block1 data register5. */ + + struct { + __IM uint32_t APB2OTP_BLOCK1_W5 : 32; /*!< Otp block1 word5 data. */ + } bit; + } APB2OTP_BLK1_W5; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block1 data register6. */ + + struct { + __IM uint32_t APB2OTP_BLOCK1_W6 : 32; /*!< Otp block1 word6 data. */ + } bit; + } APB2OTP_BLK1_W6; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block1 data register7. */ + + struct { + __IM uint32_t APB2OTP_BLOCK1_W7 : 32; /*!< Otp block1 word7 data. */ + } bit; + } APB2OTP_BLK1_W7; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block1 data register8. */ + + struct { + __IM uint32_t APB2OTP_BLOCK1_W8 : 32; /*!< Otp block1 word8 data. */ + } bit; + } APB2OTP_BLK1_W8; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block1 data register9. */ + + struct { + __IM uint32_t APB2OTP_BLOCK1_W9 : 32; /*!< Otp block1 word9 data. */ + } bit; + } APB2OTP_BLK1_W9; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block2 data register1. */ + + struct { + __IM uint32_t APB2OTP_BLOCK2_W1 : 32; /*!< Otp block2 word1 data. */ + } bit; + } APB2OTP_BLK2_W1; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block2 data register2. */ + + struct { + __IM uint32_t APB2OTP_BLOCK2_W2 : 32; /*!< Otp block2 word2 data. */ + } bit; + } APB2OTP_BLK2_W2; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block2 data register3. */ + + struct { + __IM uint32_t APB2OTP_BLOCK2_W3 : 32; /*!< Otp block2 word3 data. */ + } bit; + } APB2OTP_BLK2_W3; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block2 data register4. */ + + struct { + __IM uint32_t APB2OTP_BLOCK2_W4 : 32; /*!< Otp block2 word4 data. */ + } bit; + } APB2OTP_BLK2_W4; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block2 data register5. */ + + struct { + __IM uint32_t APB2OTP_BLOCK2_W5 : 32; /*!< Otp block2 word5 data. */ + } bit; + } APB2OTP_BLK2_W5; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block2 data register6. */ + + struct { + __IM uint32_t APB2OTP_BLOCK2_W6 : 32; /*!< Otp block2 word6 data. */ + } bit; + } APB2OTP_BLK2_W6; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block2 data register7. */ + + struct { + __IM uint32_t APB2OTP_BLOCK2_W7 : 32; /*!< Otp block2 word7 data. */ + } bit; + } APB2OTP_BLK2_W7; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block2 data register8. */ + + struct { + __IM uint32_t APB2OTP_BLOCK2_W8 : 32; /*!< Otp block2 word8 data. */ + } bit; + } APB2OTP_BLK2_W8; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block2 data register9. */ + + struct { + __IM uint32_t APB2OTP_BLOCK2_W9 : 32; /*!< Otp block2 word9 data. */ + } bit; + } APB2OTP_BLK2_W9; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block2 data register10. */ + + struct { + __IM uint32_t APB2OTP_BLOCK2_W10 : 32; /*!< Otp block2 word10 data. */ + } bit; + } APB2OTP_BLK2_W10; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block2 data register11. */ + + struct { + __IM uint32_t APB2OTP_BLOCK2_W11 : 32; /*!< Otp block2 word11 data. */ + } bit; + } APB2OTP_BLK2_W11; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block3 data register1. */ + + struct { + __IM uint32_t APB2OTP_BLOCK3_W1 : 32; /*!< Otp block3 word1 data. */ + } bit; + } APB2OTP_BLK3_W1; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block3 data register2. */ + + struct { + __IM uint32_t APB2OTP_BLOCK3_W2 : 32; /*!< Otp block3 word2 data. */ + } bit; + } APB2OTP_BLK3_W2; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block3 data register3. */ + + struct { + __IM uint32_t APB2OTP_BLOCK3_W3 : 32; /*!< Otp block3 word3 data. */ + } bit; + } APB2OTP_BLK3_W3; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block3 data register4. */ + + struct { + __IM uint32_t APB2OTP_BLOCK3_W4 : 32; /*!< Otp block3 word4 data. */ + } bit; + } APB2OTP_BLK3_W4; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block3 data register5. */ + + struct { + __IM uint32_t APB2OTP_BLOCK3_W5 : 32; /*!< Otp block3 word5 data. */ + } bit; + } APB2OTP_BLK3_W5; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block3 data register6. */ + + struct { + __IM uint32_t APB2OTP_BLOCK3_W6 : 32; /*!< Otp block3 word6 data. */ + } bit; + } APB2OTP_BLK3_W6; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block3 data register7. */ + + struct { + __IM uint32_t APB2OTP_BLOCK3_W7 : 32; /*!< Otp block3 word7 data. */ + } bit; + } APB2OTP_BLK3_W7; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block3 data register8. */ + + struct { + __IM uint32_t APB2OTP_BLOCK3_W8 : 32; /*!< Otp block3 word8 data. */ + } bit; + } APB2OTP_BLK3_W8; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block3 data register9. */ + + struct { + __IM uint32_t APB2OTP_BLOCK3_W9 : 32; /*!< Otp block3 word9 data. */ + } bit; + } APB2OTP_BLK3_W9; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block3 data register10. */ + + struct { + __IM uint32_t APB2OTP_BLOCK3_W10 : 32; /*!< Otp block3 word10 data. */ + } bit; + } APB2OTP_BLK3_W10; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block3 data register11. */ + + struct { + __IM uint32_t APB2OTP_BLOCK3_W11 : 32; /*!< Otp block3 word11 data. */ + } bit; + } APB2OTP_BLK3_W11; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block4 data register1. */ + + struct { + __IM uint32_t APB2OTP_BLOCK4_W1 : 32; /*!< Otp block4 word1 data. */ + } bit; + } APB2OTP_BLK4_W1; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block4 data register2. */ + + struct { + __IM uint32_t APB2OTP_BLOCK4_W2 : 32; /*!< Otp block4 word2 data. */ + } bit; + } APB2OTP_BLK4_W2; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block4 data register3. */ + + struct { + __IM uint32_t APB2OTP_BLOCK4_W3 : 32; /*!< Otp block4 word3 data. */ + } bit; + } APB2OTP_BLK4_W3; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block4 data register4. */ + + struct { + __IM uint32_t APB2OTP_BLOCK4_W4 : 32; /*!< Otp block4 word4 data. */ + } bit; + } APB2OTP_BLK4_W4; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block4 data register5. */ + + struct { + __IM uint32_t APB2OTP_BLOCK4_W5 : 32; /*!< Otp block4 word5 data. */ + } bit; + } APB2OTP_BLK4_W5; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block4 data register6. */ + + struct { + __IM uint32_t APB2OTP_BLOCK4_W6 : 32; /*!< Otp block4 word6 data. */ + } bit; + } APB2OTP_BLK4_W6; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block4 data register7. */ + + struct { + __IM uint32_t APB2OTP_BLOCK4_W7 : 32; /*!< Otp block4 word7 data. */ + } bit; + } APB2OTP_BLK4_W7; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block4 data register8. */ + + struct { + __IM uint32_t APB2OTP_BLOCK4_W8 : 32; /*!< Otp block4 word8 data. */ + } bit; + } APB2OTP_BLK4_W8; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block4 data register9. */ + + struct { + __IM uint32_t APB2OTP_BLOCK4_W9 : 32; /*!< Otp block4 word9 data. */ + } bit; + } APB2OTP_BLK4_W9; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block4 data registe10. */ + + struct { + __IM uint32_t APB2OTP_BLOCK4_W10 : 32; /*!< Otp block4 word10 data. */ + } bit; + } APB2OTP_BLK4_W10; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block4 data register11. */ + + struct { + __IM uint32_t APB2OTP_BLOCK4_W11 : 32; /*!< Otp block4 word11 data. */ + } bit; + } APB2OTP_BLK4_W11; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block5 data register1. */ + + struct { + __IM uint32_t APB2OTP_BLOCK5_W1 : 32; /*!< Otp block5 word1 data. */ + } bit; + } APB2OTP_BLK5_W1; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block5 data register2. */ + + struct { + __IM uint32_t APB2OTP_BLOCK5_W2 : 32; /*!< Otp block5 word2 data. */ + } bit; + } APB2OTP_BLK5_W2; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block5 data register3. */ + + struct { + __IM uint32_t APB2OTP_BLOCK5_W3 : 32; /*!< Otp block5 word3 data. */ + } bit; + } APB2OTP_BLK5_W3; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block5 data register4. */ + + struct { + __IM uint32_t APB2OTP_BLOCK5_W4 : 32; /*!< Otp block5 word4 data. */ + } bit; + } APB2OTP_BLK5_W4; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block5 data register5. */ + + struct { + __IM uint32_t APB2OTP_BLOCK5_W5 : 32; /*!< Otp block5 word5 data. */ + } bit; + } APB2OTP_BLK5_W5; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block5 data register6. */ + + struct { + __IM uint32_t APB2OTP_BLOCK5_W6 : 32; /*!< Otp block5 word6 data. */ + } bit; + } APB2OTP_BLK5_W6; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block5 data register7. */ + + struct { + __IM uint32_t APB2OTP_BLOCK5_W7 : 32; /*!< Otp block5 word7 data. */ + } bit; + } APB2OTP_BLK5_W7; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block5 data register8. */ + + struct { + __IM uint32_t APB2OTP_BLOCK5_W8 : 32; /*!< Otp block5 word8 data. */ + } bit; + } APB2OTP_BLK5_W8; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block5 data register9. */ + + struct { + __IM uint32_t APB2OTP_BLOCK5_W9 : 32; /*!< Otp block5 word9 data. */ + } bit; + } APB2OTP_BLK5_W9; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block5 data register10. */ + + struct { + __IM uint32_t APB2OTP_BLOCK5_W10 : 32; /*!< Otp block5 word10 data. */ + } bit; + } APB2OTP_BLK5_W10; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block5 data register11. */ + + struct { + __IM uint32_t APB2OTP_BLOCK5_W11 : 32; /*!< Otp block5 word11 data. */ + } bit; + } APB2OTP_BLK5_W11; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block6 data register1. */ + + struct { + __IM uint32_t APB2OTP_BLOCK6_W1 : 32; /*!< Otp block6 word1 data. */ + } bit; + } APB2OTP_BLK6_W1; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block6 data register2. */ + + struct { + __IM uint32_t APB2OTP_BLOCK6_W2 : 32; /*!< Otp block6 word2 data. */ + } bit; + } APB2OTP_BLK6_W2; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block6 data register3. */ + + struct { + __IM uint32_t APB2OTP_BLOCK6_W3 : 32; /*!< Otp block6 word3 data. */ + } bit; + } APB2OTP_BLK6_W3; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block6 data register4. */ + + struct { + __IM uint32_t APB2OTP_BLOCK6_W4 : 32; /*!< Otp block6 word4 data. */ + } bit; + } APB2OTP_BLK6_W4; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block6 data register5. */ + + struct { + __IM uint32_t APB2OTP_BLOCK6_W5 : 32; /*!< Otp block6 word5 data. */ + } bit; + } APB2OTP_BLK6_W5; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block6 data register6. */ + + struct { + __IM uint32_t APB2OTP_BLOCK6_W6 : 32; /*!< Otp block6 word6 data. */ + } bit; + } APB2OTP_BLK6_W6; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block6 data register7. */ + + struct { + __IM uint32_t APB2OTP_BLOCK6_W7 : 32; /*!< Otp block6 word7 data. */ + } bit; + } APB2OTP_BLK6_W7; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block6 data register8. */ + + struct { + __IM uint32_t APB2OTP_BLOCK6_W8 : 32; /*!< Otp block6 word8 data. */ + } bit; + } APB2OTP_BLK6_W8; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block6 data register9. */ + + struct { + __IM uint32_t APB2OTP_BLOCK6_W9 : 32; /*!< Otp block6 word9 data. */ + } bit; + } APB2OTP_BLK6_W9; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block6 data register10. */ + + struct { + __IM uint32_t APB2OTP_BLOCK6_W10 : 32; /*!< Otp block6 word10 data. */ + } bit; + } APB2OTP_BLK6_W10; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block6 data register11. */ + + struct { + __IM uint32_t APB2OTP_BLOCK6_W11 : 32; /*!< Otp block6 word11 data. */ + } bit; + } APB2OTP_BLK6_W11; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block7 data register1. */ + + struct { + __IM uint32_t APB2OTP_BLOCK7_W1 : 32; /*!< Otp block7 word1 data. */ + } bit; + } APB2OTP_BLK7_W1; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block7 data register2. */ + + struct { + __IM uint32_t APB2OTP_BLOCK7_W2 : 32; /*!< Otp block7 word2 data. */ + } bit; + } APB2OTP_BLK7_W2; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block7 data register3. */ + + struct { + __IM uint32_t APB2OTP_BLOCK7_W3 : 32; /*!< Otp block7 word3 data. */ + } bit; + } APB2OTP_BLK7_W3; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block7 data register4. */ + + struct { + __IM uint32_t APB2OTP_BLOCK7_W4 : 32; /*!< Otp block7 word4 data. */ + } bit; + } APB2OTP_BLK7_W4; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block7 data register5. */ + + struct { + __IM uint32_t APB2OTP_BLOCK7_W5 : 32; /*!< Otp block7 word5 data. */ + } bit; + } APB2OTP_BLK7_W5; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block7 data register6. */ + + struct { + __IM uint32_t APB2OTP_BLOCK7_W6 : 32; /*!< Otp block7 word6 data. */ + } bit; + } APB2OTP_BLK7_W6; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block7 data register7. */ + + struct { + __IM uint32_t APB2OTP_BLOCK7_W7 : 32; /*!< Otp block7 word7 data. */ + } bit; + } APB2OTP_BLK7_W7; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block7 data register8. */ + + struct { + __IM uint32_t APB2OTP_BLOCK7_W8 : 32; /*!< Otp block7 word8 data. */ + } bit; + } APB2OTP_BLK7_W8; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block7 data register9. */ + + struct { + __IM uint32_t APB2OTP_BLOCK7_W9 : 32; /*!< Otp block7 word9 data. */ + } bit; + } APB2OTP_BLK7_W9; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block7 data register10. */ + + struct { + __IM uint32_t APB2OTP_BLOCK7_W10 : 32; /*!< Otp block7 word10 data. */ + } bit; + } APB2OTP_BLK7_W10; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block7 data register11. */ + + struct { + __IM uint32_t APB2OTP_BLOCK7_W11 : 32; /*!< Otp block7 word11 data. */ + } bit; + } APB2OTP_BLK7_W11; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block8 data register1. */ + + struct { + __IM uint32_t APB2OTP_BLOCK8_W1 : 32; /*!< Otp block8 word1 data. */ + } bit; + } APB2OTP_BLK8_W1; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block8 data register2. */ + + struct { + __IM uint32_t APB2OTP_BLOCK8_W2 : 32; /*!< Otp block8 word2 data. */ + } bit; + } APB2OTP_BLK8_W2; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block8 data register3. */ + + struct { + __IM uint32_t APB2OTP_BLOCK8_W3 : 32; /*!< Otp block8 word3 data. */ + } bit; + } APB2OTP_BLK8_W3; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block8 data register4. */ + + struct { + __IM uint32_t APB2OTP_BLOCK8_W4 : 32; /*!< Otp block8 word4 data. */ + } bit; + } APB2OTP_BLK8_W4; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block8 data register5. */ + + struct { + __IM uint32_t APB2OTP_BLOCK8_W5 : 32; /*!< Otp block8 word5 data. */ + } bit; + } APB2OTP_BLK8_W5; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block8 data register6. */ + + struct { + __IM uint32_t APB2OTP_BLOCK8_W6 : 32; /*!< Otp block8 word6 data. */ + } bit; + } APB2OTP_BLK8_W6; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block8 data register7. */ + + struct { + __IM uint32_t APB2OTP_BLOCK8_W7 : 32; /*!< Otp block8 word7 data. */ + } bit; + } APB2OTP_BLK8_W7; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block8 data register8. */ + + struct { + __IM uint32_t APB2OTP_BLOCK8_W8 : 32; /*!< Otp block8 word8 data. */ + } bit; + } APB2OTP_BLK8_W8; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block8 data register9. */ + + struct { + __IM uint32_t APB2OTP_BLOCK8_W9 : 32; /*!< Otp block8 word9 data. */ + } bit; + } APB2OTP_BLK8_W9; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block8 data register10. */ + + struct { + __IM uint32_t APB2OTP_BLOCK8_W10 : 32; /*!< Otp block8 word10 data. */ + } bit; + } APB2OTP_BLK8_W10; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block8 data register11. */ + + struct { + __IM uint32_t APB2OTP_BLOCK8_W11 : 32; /*!< Otp block8 word11 data. */ + } bit; + } APB2OTP_BLK8_W11; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block9 data register1. */ + + struct { + __IM uint32_t APB2OTP_BLOCK9_W1 : 32; /*!< Otp block9 word1 data. */ + } bit; + } APB2OTP_BLK9_W1; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block9 data register2. */ + + struct { + __IM uint32_t APB2OTP_BLOCK9_W2 : 32; /*!< Otp block9 word2 data. */ + } bit; + } APB2OTP_BLK9_W2; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block9 data register3. */ + + struct { + __IM uint32_t APB2OTP_BLOCK9_W3 : 32; /*!< Otp block9 word3 data. */ + } bit; + } APB2OTP_BLK9_W3; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block9 data register4. */ + + struct { + __IM uint32_t APB2OTP_BLOCK9_W4 : 32; /*!< Otp block9 word4 data. */ + } bit; + } APB2OTP_BLK9_W4; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block9 data register5. */ + + struct { + __IM uint32_t APB2OTP_BLOCK9_W5 : 32; /*!< Otp block9 word5 data. */ + } bit; + } APB2OTP_BLK9_W5; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block9 data register6. */ + + struct { + __IM uint32_t APB2OTP_BLOCK9_W6 : 32; /*!< Otp block9 word6 data. */ + } bit; + } APB2OTP_BLK9_W6; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block9 data register7. */ + + struct { + __IM uint32_t APB2OTP_BLOCK9_W7 : 32; /*!< Otp block9 word7 data. */ + } bit; + } APB2OTP_BLK9_W7; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block9 data register8. */ + + struct { + __IM uint32_t APB2OTP_BLOCK9_W8 : 32; /*!< Otp block9 word8 data. */ + } bit; + } APB2OTP_BLK9_W8; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block9 data register9. */ + + struct { + __IM uint32_t APB2OTP_BLOCK9_W9 : 32; /*!< Otp block9 word9 data. */ + } bit; + } APB2OTP_BLK9_W9; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block9 data register10. */ + + struct { + __IM uint32_t APB2OTP_BLOCK9_W10 : 32; /*!< Otp block9 word10 data. */ + } bit; + } APB2OTP_BLK9_W10; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block9 data register11. */ + + struct { + __IM uint32_t APB2OTP_BLOCK9_W11 : 32; /*!< Otp block9 word11 data. */ + } bit; + } APB2OTP_BLK9_W11; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block10 data register1. */ + + struct { + __IM uint32_t APB2OTP_BLOCK10_W1 : 32; /*!< Otp block10 word1 data. */ + } bit; + } APB2OTP_BLK10_W1; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block10 data register2. */ + + struct { + __IM uint32_t APB2OTP_BLOCK10_W2 : 32; /*!< Otp block10 word2 data. */ + } bit; + } APB2OTP_BLK10_W2; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block10 data register3. */ + + struct { + __IM uint32_t APB2OTP_BLOCK10_W3 : 32; /*!< Otp block10 word3 data. */ + } bit; + } APB2OTP_BLK10_W3; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block10 data register4. */ + + struct { + __IM uint32_t APB2OTP_BLOCK10_W4 : 32; /*!< Otp block10 word4 data. */ + } bit; + } APB2OTP_BLK10_W4; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block10 data register5. */ + + struct { + __IM uint32_t APB2OTP_BLOCK10_W5 : 32; /*!< Otp block10 word5 data. */ + } bit; + } APB2OTP_BLK10_W5; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block10 data register6. */ + + struct { + __IM uint32_t APB2OTP_BLOCK10_W6 : 32; /*!< Otp block10 word6 data. */ + } bit; + } APB2OTP_BLK10_W6; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block10 data register7. */ + + struct { + __IM uint32_t APB2OTP_BLOCK10_W7 : 32; /*!< Otp block10 word7 data. */ + } bit; + } APB2OTP_BLK10_W7; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block10 data register8. */ + + struct { + __IM uint32_t APB2OTP_BLOCK10_W8 : 32; /*!< Otp block10 word8 data. */ + } bit; + } APB2OTP_BLK10_W8; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block10 data register9. */ + + struct { + __IM uint32_t APB2OTP_BLOCK10_W9 : 32; /*!< Otp block10 word9 data. */ + } bit; + } APB2OTP_BLK10_W9; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block10 data register10. */ + + struct { + __IM uint32_t APB2OTP_BLOCK19_W10 : 32; /*!< Otp block10 word10 data. */ + } bit; + } APB2OTP_BLK10_W10; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp block10 data register11. */ + + struct { + __IM uint32_t APB2OTP_BLOCK10_W11 : 32; /*!< Otp block10 word11 data. */ + } bit; + } APB2OTP_BLK10_W11; + __IM uint32_t RESERVED2; + + union { + __IOM uint32_t reg; /*!< eFuse apb2otp enable configuration register. */ + + struct { + __IOM uint32_t APB2OTP_APB2OTP_EN : 1; /*!< Apb2otp mode enable signal. */ + uint32_t : 31; + } bit; + } APB2OTP_EN; +} EFUSE_Type; /*!< Size = 2572 (0xa0c) */ + + + +/* =========================================================================================================================== */ +/* ================ GPIO ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief General Purpose Input/Output (GPIO) + */ + +typedef struct { /*!< GPIO Structure */ + + union { + __IOM uint32_t reg; /*!< GPIO bit select register */ + + struct { + __IOM uint32_t BT_SEL : 32; /*!< GPIO bit select register */ + } bit; + } BT_SELECT; + + union { + __IOM uint32_t reg; /*!< GPIO output register for GPIO0-31 */ + + struct { + __IOM uint32_t DATA_ORIG : 32; /*!< GPIO output register for GPIO0-31 */ + } bit; + } OUT; + + union { + __IOM uint32_t reg; /*!< GPIO output set register for GPIO0-31 */ + + struct { + __OM uint32_t OUT_W1TS : 32; /*!< GPIO output set register for GPIO0-31 */ + } bit; + } OUT_W1TS; + + union { + __IOM uint32_t reg; /*!< GPIO output clear register for GPIO0-31 */ + + struct { + __OM uint32_t OUT_W1TC : 32; /*!< GPIO output clear register for GPIO0-31 */ + } bit; + } OUT_W1TC; + + union { + __IOM uint32_t reg; /*!< GPIO output register for GPIO32-56 */ + + struct { + __IOM uint32_t DATA_ORIG : 25; /*!< GPIO output register for GPIO32-56 */ + uint32_t : 7; + } bit; + } OUT1; + + union { + __IOM uint32_t reg; /*!< GPIO output set register for GPIO32-56 */ + + struct { + __OM uint32_t OUT1_W1TS : 25; /*!< GPIO output set register for GPIO32-56 */ + uint32_t : 7; + } bit; + } OUT1_W1TS; + + union { + __IOM uint32_t reg; /*!< GPIO output clear register for GPIO32-56 */ + + struct { + __OM uint32_t OUT1_W1TC : 25; /*!< GPIO output clear register for GPIO32-56 */ + uint32_t : 7; + } bit; + } OUT1_W1TC; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t reg; /*!< GPIO output enable register for GPIO0-31 */ + + struct { + __IOM uint32_t DATA : 32; /*!< GPIO output enable register for GPIO0-31 */ + } bit; + } ENABLE; + + union { + __IOM uint32_t reg; /*!< GPIO output enable set register for GPIO0-31 */ + + struct { + __OM uint32_t ENABLE_W1TS : 32; /*!< GPIO output enable set register for GPIO0-31 */ + } bit; + } ENABLE_W1TS; + + union { + __IOM uint32_t reg; /*!< GPIO output enable clear register for GPIO0-31 */ + + struct { + __OM uint32_t ENABLE_W1TC : 32; /*!< GPIO output enable clear register for GPIO0-31 */ + } bit; + } ENABLE_W1TC; + + union { + __IOM uint32_t reg; /*!< GPIO output enable register for GPIO32-56 */ + + struct { + __IOM uint32_t DATA : 25; /*!< GPIO output enable register for GPIO32-56 */ + uint32_t : 7; + } bit; + } ENABLE1; + + union { + __IOM uint32_t reg; /*!< GPIO output enable set register for GPIO32-56 */ + + struct { + __OM uint32_t ENABLE1_W1TS : 25; /*!< GPIO output enable set register for GPIO32-56 */ + uint32_t : 7; + } bit; + } ENABLE1_W1TS; + + union { + __IOM uint32_t reg; /*!< GPIO output enable clear register for GPIO32-56 */ + + struct { + __OM uint32_t ENABLE1_W1TC : 25; /*!< GPIO output enable clear register for GPIO32-56 */ + uint32_t : 7; + } bit; + } ENABLE1_W1TC; + + union { + __IOM uint32_t reg; /*!< pad strapping register */ + + struct { + __IM uint32_t STRAPPING : 16; /*!< pad strapping register */ + uint32_t : 16; + } bit; + } STRAP; + + union { + __IOM uint32_t reg; /*!< GPIO input register for GPIO0-31 */ + + struct { + __IM uint32_t DATA_NEXT : 32; /*!< GPIO input register for GPIO0-31 */ + } bit; + } IN; + + union { + __IOM uint32_t reg; /*!< GPIO input register for GPIO32-56 */ + + struct { + __IM uint32_t DATA_NEXT : 25; /*!< GPIO input register for GPIO32-56 */ + uint32_t : 7; + } bit; + } IN1; + + union { + __IOM uint32_t reg; /*!< GPIO interrupt status register for GPIO0-31 */ + + struct { + __IOM uint32_t INTERRUPT : 32; /*!< GPIO interrupt status register for GPIO0-31 */ + } bit; + } STATUS; + + union { + __IOM uint32_t reg; /*!< GPIO interrupt status set register for GPIO0-31 */ + + struct { + __OM uint32_t STATUS_W1TS : 32; /*!< GPIO interrupt status set register for GPIO0-31 */ + } bit; + } STATUS_W1TS; + + union { + __IOM uint32_t reg; /*!< GPIO interrupt status clear register for GPIO0-31 */ + + struct { + __OM uint32_t STATUS_W1TC : 32; /*!< GPIO interrupt status clear register for GPIO0-31 */ + } bit; + } STATUS_W1TC; + + union { + __IOM uint32_t reg; /*!< GPIO interrupt status register for GPIO32-56 */ + + struct { + __IOM uint32_t INTERRUPT : 25; /*!< GPIO interrupt status register for GPIO32-56 */ + uint32_t : 7; + } bit; + } STATUS1; + + union { + __IOM uint32_t reg; /*!< GPIO interrupt status set register for GPIO32-56 */ + + struct { + __OM uint32_t STATUS1_W1TS : 25; /*!< GPIO interrupt status set register for GPIO32-56 */ + uint32_t : 7; + } bit; + } STATUS1_W1TS; + + union { + __IOM uint32_t reg; /*!< GPIO interrupt status clear register for GPIO32-56 */ + + struct { + __OM uint32_t STATUS1_W1TC : 25; /*!< GPIO interrupt status clear register for GPIO32-56 */ + uint32_t : 7; + } bit; + } STATUS1_W1TC; + + union { + __IOM uint32_t reg; /*!< GPIO interrupt 0 status register for GPIO0-31 */ + + struct { + __IM uint32_t INT_0 : 32; /*!< GPIO interrupt 0 status register for GPIO0-31 */ + } bit; + } INTR_0; + + union { + __IOM uint32_t reg; /*!< GPIO interrupt 0 status register for GPIO32-56 */ + + struct { + __IM uint32_t INT1_0 : 25; /*!< GPIO interrupt 0 status register for GPIO32-56 */ + uint32_t : 7; + } bit; + } INTR1_0; + + union { + __IOM uint32_t reg; /*!< GPIO interrupt 1 status register for GPIO0-31 */ + + struct { + __IM uint32_t INT_1 : 32; /*!< GPIO interrupt 1 status register for GPIO0-31 */ + } bit; + } INTR_1; + + union { + __IOM uint32_t reg; /*!< GPIO interrupt 1 status register for GPIO32-56 */ + + struct { + __IM uint32_t INT1_1 : 25; /*!< GPIO interrupt 1 status register for GPIO32-56 */ + uint32_t : 7; + } bit; + } INTR1_1; + + union { + __IOM uint32_t reg; /*!< GPIO interrupt source register for GPIO0-31 */ + + struct { + __IM uint32_t STATUS_INTERRUPT_NEXT : 32;/*!< GPIO interrupt source register for GPIO0-31 */ + } bit; + } STATUS_NEXT; + + union { + __IOM uint32_t reg; /*!< GPIO interrupt source register for GPIO32-56 */ + + struct { + __IM uint32_t STATUS_INTERRUPT_NEXT1 : 25;/*!< GPIO interrupt source register for GPIO32-56 */ + uint32_t : 7; + } bit; + } STATUS_NEXT1; + + union { + __IOM uint32_t reg; /*!< GPIO pin configuration register */ + + struct { + __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ + __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + uint32_t : 2; + __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. + 1:trigger at posedge. 2:trigger at negedge. 3:trigger at + any edge. 4:valid at low level. 5:valid at high level */ + __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from + Light-sleep Mode) */ + __IOM uint32_t CONFIG : 2; /*!< reserved */ + __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not + shielded) interrupt. */ + uint32_t : 14; + } bit; + } PIN0; + __IM uint32_t RESERVED1[3]; + + union { + __IOM uint32_t reg; /*!< GPIO pin configuration register */ + + struct { + __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ + __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + uint32_t : 2; + __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. + 1:trigger at posedge. 2:trigger at negedge. 3:trigger at + any edge. 4:valid at low level. 5:valid at high level */ + __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from + Light-sleep Mode) */ + __IOM uint32_t CONFIG : 2; /*!< reserved */ + __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not + shielded) interrupt. */ + uint32_t : 14; + } bit; + } PIN1; + __IM uint32_t RESERVED2[3]; + + union { + __IOM uint32_t reg; /*!< GPIO pin configuration register */ + + struct { + __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ + __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + uint32_t : 2; + __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. + 1:trigger at posedge. 2:trigger at negedge. 3:trigger at + any edge. 4:valid at low level. 5:valid at high level */ + __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from + Light-sleep Mode) */ + __IOM uint32_t CONFIG : 2; /*!< reserved */ + __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not + shielded) interrupt. */ + uint32_t : 14; + } bit; + } PIN2; + __IM uint32_t RESERVED3[3]; + + union { + __IOM uint32_t reg; /*!< GPIO pin configuration register */ + + struct { + __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ + __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + uint32_t : 2; + __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. + 1:trigger at posedge. 2:trigger at negedge. 3:trigger at + any edge. 4:valid at low level. 5:valid at high level */ + __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from + Light-sleep Mode) */ + __IOM uint32_t CONFIG : 2; /*!< reserved */ + __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not + shielded) interrupt. */ + uint32_t : 14; + } bit; + } PIN3; + __IM uint32_t RESERVED4[3]; + + union { + __IOM uint32_t reg; /*!< GPIO pin configuration register */ + + struct { + __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ + __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + uint32_t : 2; + __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. + 1:trigger at posedge. 2:trigger at negedge. 3:trigger at + any edge. 4:valid at low level. 5:valid at high level */ + __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from + Light-sleep Mode) */ + __IOM uint32_t CONFIG : 2; /*!< reserved */ + __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not + shielded) interrupt. */ + uint32_t : 14; + } bit; + } PIN4; + __IM uint32_t RESERVED5[3]; + + union { + __IOM uint32_t reg; /*!< GPIO pin configuration register */ + + struct { + __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ + __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + uint32_t : 2; + __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. + 1:trigger at posedge. 2:trigger at negedge. 3:trigger at + any edge. 4:valid at low level. 5:valid at high level */ + __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from + Light-sleep Mode) */ + __IOM uint32_t CONFIG : 2; /*!< reserved */ + __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not + shielded) interrupt. */ + uint32_t : 14; + } bit; + } PIN5; + __IM uint32_t RESERVED6[3]; + + union { + __IOM uint32_t reg; /*!< GPIO pin configuration register */ + + struct { + __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ + __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + uint32_t : 2; + __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. + 1:trigger at posedge. 2:trigger at negedge. 3:trigger at + any edge. 4:valid at low level. 5:valid at high level */ + __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from + Light-sleep Mode) */ + __IOM uint32_t CONFIG : 2; /*!< reserved */ + __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not + shielded) interrupt. */ + uint32_t : 14; + } bit; + } PIN6; + __IM uint32_t RESERVED7[3]; + + union { + __IOM uint32_t reg; /*!< GPIO pin configuration register */ + + struct { + __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ + __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + uint32_t : 2; + __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. + 1:trigger at posedge. 2:trigger at negedge. 3:trigger at + any edge. 4:valid at low level. 5:valid at high level */ + __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from + Light-sleep Mode) */ + __IOM uint32_t CONFIG : 2; /*!< reserved */ + __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not + shielded) interrupt. */ + uint32_t : 14; + } bit; + } PIN7; + __IM uint32_t RESERVED8[3]; + + union { + __IOM uint32_t reg; /*!< GPIO pin configuration register */ + + struct { + __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ + __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + uint32_t : 2; + __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. + 1:trigger at posedge. 2:trigger at negedge. 3:trigger at + any edge. 4:valid at low level. 5:valid at high level */ + __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from + Light-sleep Mode) */ + __IOM uint32_t CONFIG : 2; /*!< reserved */ + __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not + shielded) interrupt. */ + uint32_t : 14; + } bit; + } PIN8; + __IM uint32_t RESERVED9[3]; + + union { + __IOM uint32_t reg; /*!< GPIO pin configuration register */ + + struct { + __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ + __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + uint32_t : 2; + __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. + 1:trigger at posedge. 2:trigger at negedge. 3:trigger at + any edge. 4:valid at low level. 5:valid at high level */ + __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from + Light-sleep Mode) */ + __IOM uint32_t CONFIG : 2; /*!< reserved */ + __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not + shielded) interrupt. */ + uint32_t : 14; + } bit; + } PIN9; + __IM uint32_t RESERVED10[3]; + + union { + __IOM uint32_t reg; /*!< GPIO pin configuration register */ + + struct { + __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ + __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + uint32_t : 2; + __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. + 1:trigger at posedge. 2:trigger at negedge. 3:trigger at + any edge. 4:valid at low level. 5:valid at high level */ + __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from + Light-sleep Mode) */ + __IOM uint32_t CONFIG : 2; /*!< reserved */ + __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not + shielded) interrupt. */ + uint32_t : 14; + } bit; + } PIN10; + __IM uint32_t RESERVED11[3]; + + union { + __IOM uint32_t reg; /*!< GPIO pin configuration register */ + + struct { + __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ + __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + uint32_t : 2; + __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. + 1:trigger at posedge. 2:trigger at negedge. 3:trigger at + any edge. 4:valid at low level. 5:valid at high level */ + __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from + Light-sleep Mode) */ + __IOM uint32_t CONFIG : 2; /*!< reserved */ + __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not + shielded) interrupt. */ + uint32_t : 14; + } bit; + } PIN11; + __IM uint32_t RESERVED12[3]; + + union { + __IOM uint32_t reg; /*!< GPIO pin configuration register */ + + struct { + __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ + __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + uint32_t : 2; + __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. + 1:trigger at posedge. 2:trigger at negedge. 3:trigger at + any edge. 4:valid at low level. 5:valid at high level */ + __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from + Light-sleep Mode) */ + __IOM uint32_t CONFIG : 2; /*!< reserved */ + __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not + shielded) interrupt. */ + uint32_t : 14; + } bit; + } PIN12; + __IM uint32_t RESERVED13[3]; + + union { + __IOM uint32_t reg; /*!< GPIO pin configuration register */ + + struct { + __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ + __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + uint32_t : 2; + __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. + 1:trigger at posedge. 2:trigger at negedge. 3:trigger at + any edge. 4:valid at low level. 5:valid at high level */ + __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from + Light-sleep Mode) */ + __IOM uint32_t CONFIG : 2; /*!< reserved */ + __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not + shielded) interrupt. */ + uint32_t : 14; + } bit; + } PIN13; + __IM uint32_t RESERVED14[3]; + + union { + __IOM uint32_t reg; /*!< GPIO pin configuration register */ + + struct { + __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ + __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + uint32_t : 2; + __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. + 1:trigger at posedge. 2:trigger at negedge. 3:trigger at + any edge. 4:valid at low level. 5:valid at high level */ + __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from + Light-sleep Mode) */ + __IOM uint32_t CONFIG : 2; /*!< reserved */ + __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not + shielded) interrupt. */ + uint32_t : 14; + } bit; + } PIN14; + __IM uint32_t RESERVED15; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC1_IN_SEL_CFG; + __IM uint32_t RESERVED16; + + union { + __IOM uint32_t reg; /*!< GPIO pin configuration register */ + + struct { + __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ + __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + uint32_t : 2; + __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. + 1:trigger at posedge. 2:trigger at negedge. 3:trigger at + any edge. 4:valid at low level. 5:valid at high level */ + __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from + Light-sleep Mode) */ + __IOM uint32_t CONFIG : 2; /*!< reserved */ + __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not + shielded) interrupt. */ + uint32_t : 14; + } bit; + } PIN15; + __IM uint32_t RESERVED17; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC2_IN_SEL_CFG; + __IM uint32_t RESERVED18; + + union { + __IOM uint32_t reg; /*!< GPIO pin configuration register */ + + struct { + __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ + __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + uint32_t : 2; + __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. + 1:trigger at posedge. 2:trigger at negedge. 3:trigger at + any edge. 4:valid at low level. 5:valid at high level */ + __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from + Light-sleep Mode) */ + __IOM uint32_t CONFIG : 2; /*!< reserved */ + __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not + shielded) interrupt. */ + uint32_t : 14; + } bit; + } PIN16; + __IM uint32_t RESERVED19; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC3_IN_SEL_CFG; + __IM uint32_t RESERVED20; + + union { + __IOM uint32_t reg; /*!< GPIO pin configuration register */ + + struct { + __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ + __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + uint32_t : 2; + __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. + 1:trigger at posedge. 2:trigger at negedge. 3:trigger at + any edge. 4:valid at low level. 5:valid at high level */ + __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from + Light-sleep Mode) */ + __IOM uint32_t CONFIG : 2; /*!< reserved */ + __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not + shielded) interrupt. */ + uint32_t : 14; + } bit; + } PIN17; + __IM uint32_t RESERVED21; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC4_IN_SEL_CFG; + __IM uint32_t RESERVED22; + + union { + __IOM uint32_t reg; /*!< GPIO pin configuration register */ + + struct { + __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ + __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + uint32_t : 2; + __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. + 1:trigger at posedge. 2:trigger at negedge. 3:trigger at + any edge. 4:valid at low level. 5:valid at high level */ + __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from + Light-sleep Mode) */ + __IOM uint32_t CONFIG : 2; /*!< reserved */ + __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not + shielded) interrupt. */ + uint32_t : 14; + } bit; + } PIN18; + __IM uint32_t RESERVED23; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC5_IN_SEL_CFG; + __IM uint32_t RESERVED24; + + union { + __IOM uint32_t reg; /*!< GPIO pin configuration register */ + + struct { + __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ + __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + uint32_t : 2; + __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. + 1:trigger at posedge. 2:trigger at negedge. 3:trigger at + any edge. 4:valid at low level. 5:valid at high level */ + __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from + Light-sleep Mode) */ + __IOM uint32_t CONFIG : 2; /*!< reserved */ + __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not + shielded) interrupt. */ + uint32_t : 14; + } bit; + } PIN19; + __IM uint32_t RESERVED25; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC6_IN_SEL_CFG; + __IM uint32_t RESERVED26; + + union { + __IOM uint32_t reg; /*!< GPIO pin configuration register */ + + struct { + __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ + __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + uint32_t : 2; + __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. + 1:trigger at posedge. 2:trigger at negedge. 3:trigger at + any edge. 4:valid at low level. 5:valid at high level */ + __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from + Light-sleep Mode) */ + __IOM uint32_t CONFIG : 2; /*!< reserved */ + __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not + shielded) interrupt. */ + uint32_t : 14; + } bit; + } PIN20; + __IM uint32_t RESERVED27; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC7_IN_SEL_CFG; + __IM uint32_t RESERVED28; + + union { + __IOM uint32_t reg; /*!< GPIO pin configuration register */ + + struct { + __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ + __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + uint32_t : 2; + __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. + 1:trigger at posedge. 2:trigger at negedge. 3:trigger at + any edge. 4:valid at low level. 5:valid at high level */ + __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from + Light-sleep Mode) */ + __IOM uint32_t CONFIG : 2; /*!< reserved */ + __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not + shielded) interrupt. */ + uint32_t : 14; + } bit; + } PIN21; + __IM uint32_t RESERVED29; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC8_IN_SEL_CFG; + __IM uint32_t RESERVED30; + + union { + __IOM uint32_t reg; /*!< GPIO pin configuration register */ + + struct { + __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ + __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + uint32_t : 2; + __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. + 1:trigger at posedge. 2:trigger at negedge. 3:trigger at + any edge. 4:valid at low level. 5:valid at high level */ + __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from + Light-sleep Mode) */ + __IOM uint32_t CONFIG : 2; /*!< reserved */ + __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not + shielded) interrupt. */ + uint32_t : 14; + } bit; + } PIN22; + __IM uint32_t RESERVED31; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC9_IN_SEL_CFG; + __IM uint32_t RESERVED32; + + union { + __IOM uint32_t reg; /*!< GPIO pin configuration register */ + + struct { + __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ + __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + uint32_t : 2; + __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. + 1:trigger at posedge. 2:trigger at negedge. 3:trigger at + any edge. 4:valid at low level. 5:valid at high level */ + __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from + Light-sleep Mode) */ + __IOM uint32_t CONFIG : 2; /*!< reserved */ + __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not + shielded) interrupt. */ + uint32_t : 14; + } bit; + } PIN23; + __IM uint32_t RESERVED33; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC10_IN_SEL_CFG; + __IM uint32_t RESERVED34; + + union { + __IOM uint32_t reg; /*!< GPIO pin configuration register */ + + struct { + __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ + __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + uint32_t : 2; + __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. + 1:trigger at posedge. 2:trigger at negedge. 3:trigger at + any edge. 4:valid at low level. 5:valid at high level */ + __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from + Light-sleep Mode) */ + __IOM uint32_t CONFIG : 2; /*!< reserved */ + __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not + shielded) interrupt. */ + uint32_t : 14; + } bit; + } PIN24; + __IM uint32_t RESERVED35; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC11_IN_SEL_CFG; + __IM uint32_t RESERVED36; + + union { + __IOM uint32_t reg; /*!< GPIO pin configuration register */ + + struct { + __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ + __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + uint32_t : 2; + __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. + 1:trigger at posedge. 2:trigger at negedge. 3:trigger at + any edge. 4:valid at low level. 5:valid at high level */ + __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from + Light-sleep Mode) */ + __IOM uint32_t CONFIG : 2; /*!< reserved */ + __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not + shielded) interrupt. */ + uint32_t : 14; + } bit; + } PIN25; + __IM uint32_t RESERVED37; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC12_IN_SEL_CFG; + __IM uint32_t RESERVED38; + + union { + __IOM uint32_t reg; /*!< GPIO pin configuration register */ + + struct { + __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ + __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + uint32_t : 2; + __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. + 1:trigger at posedge. 2:trigger at negedge. 3:trigger at + any edge. 4:valid at low level. 5:valid at high level */ + __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from + Light-sleep Mode) */ + __IOM uint32_t CONFIG : 2; /*!< reserved */ + __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not + shielded) interrupt. */ + uint32_t : 14; + } bit; + } PIN26; + __IM uint32_t RESERVED39; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC13_IN_SEL_CFG; + __IM uint32_t RESERVED40; + + union { + __IOM uint32_t reg; /*!< GPIO pin configuration register */ + + struct { + __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ + __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + uint32_t : 2; + __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. + 1:trigger at posedge. 2:trigger at negedge. 3:trigger at + any edge. 4:valid at low level. 5:valid at high level */ + __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from + Light-sleep Mode) */ + __IOM uint32_t CONFIG : 2; /*!< reserved */ + __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not + shielded) interrupt. */ + uint32_t : 14; + } bit; + } PIN27; + __IM uint32_t RESERVED41; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC14_IN_SEL_CFG; + __IM uint32_t RESERVED42; + + union { + __IOM uint32_t reg; /*!< GPIO pin configuration register */ + + struct { + __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ + __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + uint32_t : 2; + __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. + 1:trigger at posedge. 2:trigger at negedge. 3:trigger at + any edge. 4:valid at low level. 5:valid at high level */ + __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from + Light-sleep Mode) */ + __IOM uint32_t CONFIG : 2; /*!< reserved */ + __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not + shielded) interrupt. */ + uint32_t : 14; + } bit; + } PIN28; + __IM uint32_t RESERVED43; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC15_IN_SEL_CFG; + __IM uint32_t RESERVED44; + + union { + __IOM uint32_t reg; /*!< GPIO pin configuration register */ + + struct { + __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ + __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + uint32_t : 2; + __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. + 1:trigger at posedge. 2:trigger at negedge. 3:trigger at + any edge. 4:valid at low level. 5:valid at high level */ + __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from + Light-sleep Mode) */ + __IOM uint32_t CONFIG : 2; /*!< reserved */ + __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not + shielded) interrupt. */ + uint32_t : 14; + } bit; + } PIN29; + __IM uint32_t RESERVED45; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC16_IN_SEL_CFG; + __IM uint32_t RESERVED46; + + union { + __IOM uint32_t reg; /*!< GPIO pin configuration register */ + + struct { + __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ + __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + uint32_t : 2; + __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. + 1:trigger at posedge. 2:trigger at negedge. 3:trigger at + any edge. 4:valid at low level. 5:valid at high level */ + __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from + Light-sleep Mode) */ + __IOM uint32_t CONFIG : 2; /*!< reserved */ + __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not + shielded) interrupt. */ + uint32_t : 14; + } bit; + } PIN30; + __IM uint32_t RESERVED47; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC17_IN_SEL_CFG; + __IM uint32_t RESERVED48; + + union { + __IOM uint32_t reg; /*!< GPIO pin configuration register */ + + struct { + __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ + __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + uint32_t : 2; + __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. + 1:trigger at posedge. 2:trigger at negedge. 3:trigger at + any edge. 4:valid at low level. 5:valid at high level */ + __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from + Light-sleep Mode) */ + __IOM uint32_t CONFIG : 2; /*!< reserved */ + __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not + shielded) interrupt. */ + uint32_t : 14; + } bit; + } PIN31; + __IM uint32_t RESERVED49; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC18_IN_SEL_CFG; + __IM uint32_t RESERVED50; + + union { + __IOM uint32_t reg; /*!< GPIO pin configuration register */ + + struct { + __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ + __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + uint32_t : 2; + __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. + 1:trigger at posedge. 2:trigger at negedge. 3:trigger at + any edge. 4:valid at low level. 5:valid at high level */ + __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from + Light-sleep Mode) */ + __IOM uint32_t CONFIG : 2; /*!< reserved */ + __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not + shielded) interrupt. */ + uint32_t : 14; + } bit; + } PIN32; + __IM uint32_t RESERVED51; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC19_IN_SEL_CFG; + __IM uint32_t RESERVED52; + + union { + __IOM uint32_t reg; /*!< GPIO pin configuration register */ + + struct { + __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ + __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + uint32_t : 2; + __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. + 1:trigger at posedge. 2:trigger at negedge. 3:trigger at + any edge. 4:valid at low level. 5:valid at high level */ + __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from + Light-sleep Mode) */ + __IOM uint32_t CONFIG : 2; /*!< reserved */ + __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not + shielded) interrupt. */ + uint32_t : 14; + } bit; + } PIN33; + __IM uint32_t RESERVED53; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC20_IN_SEL_CFG; + __IM uint32_t RESERVED54; + + union { + __IOM uint32_t reg; /*!< GPIO pin configuration register */ + + struct { + __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ + __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + uint32_t : 2; + __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. + 1:trigger at posedge. 2:trigger at negedge. 3:trigger at + any edge. 4:valid at low level. 5:valid at high level */ + __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from + Light-sleep Mode) */ + __IOM uint32_t CONFIG : 2; /*!< reserved */ + __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not + shielded) interrupt. */ + uint32_t : 14; + } bit; + } PIN34; + __IM uint32_t RESERVED55; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC21_IN_SEL_CFG; + __IM uint32_t RESERVED56; + + union { + __IOM uint32_t reg; /*!< GPIO pin configuration register */ + + struct { + __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ + __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + uint32_t : 2; + __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. + 1:trigger at posedge. 2:trigger at negedge. 3:trigger at + any edge. 4:valid at low level. 5:valid at high level */ + __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from + Light-sleep Mode) */ + __IOM uint32_t CONFIG : 2; /*!< reserved */ + __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not + shielded) interrupt. */ + uint32_t : 14; + } bit; + } PIN35; + __IM uint32_t RESERVED57; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC22_IN_SEL_CFG; + __IM uint32_t RESERVED58; + + union { + __IOM uint32_t reg; /*!< GPIO pin configuration register */ + + struct { + __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ + __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + uint32_t : 2; + __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. + 1:trigger at posedge. 2:trigger at negedge. 3:trigger at + any edge. 4:valid at low level. 5:valid at high level */ + __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from + Light-sleep Mode) */ + __IOM uint32_t CONFIG : 2; /*!< reserved */ + __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not + shielded) interrupt. */ + uint32_t : 14; + } bit; + } PIN36; + __IM uint32_t RESERVED59; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC23_IN_SEL_CFG; + __IM uint32_t RESERVED60; + + union { + __IOM uint32_t reg; /*!< GPIO pin configuration register */ + + struct { + __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ + __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + uint32_t : 2; + __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. + 1:trigger at posedge. 2:trigger at negedge. 3:trigger at + any edge. 4:valid at low level. 5:valid at high level */ + __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from + Light-sleep Mode) */ + __IOM uint32_t CONFIG : 2; /*!< reserved */ + __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not + shielded) interrupt. */ + uint32_t : 14; + } bit; + } PIN37; + __IM uint32_t RESERVED61; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC24_IN_SEL_CFG; + __IM uint32_t RESERVED62; + + union { + __IOM uint32_t reg; /*!< GPIO pin configuration register */ + + struct { + __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ + __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + uint32_t : 2; + __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. + 1:trigger at posedge. 2:trigger at negedge. 3:trigger at + any edge. 4:valid at low level. 5:valid at high level */ + __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from + Light-sleep Mode) */ + __IOM uint32_t CONFIG : 2; /*!< reserved */ + __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not + shielded) interrupt. */ + uint32_t : 14; + } bit; + } PIN38; + __IM uint32_t RESERVED63; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC25_IN_SEL_CFG; + __IM uint32_t RESERVED64; + + union { + __IOM uint32_t reg; /*!< GPIO pin configuration register */ + + struct { + __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ + __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + uint32_t : 2; + __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. + 1:trigger at posedge. 2:trigger at negedge. 3:trigger at + any edge. 4:valid at low level. 5:valid at high level */ + __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from + Light-sleep Mode) */ + __IOM uint32_t CONFIG : 2; /*!< reserved */ + __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not + shielded) interrupt. */ + uint32_t : 14; + } bit; + } PIN39; + __IM uint32_t RESERVED65; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC26_IN_SEL_CFG; + __IM uint32_t RESERVED66; + + union { + __IOM uint32_t reg; /*!< GPIO pin configuration register */ + + struct { + __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ + __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + uint32_t : 2; + __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. + 1:trigger at posedge. 2:trigger at negedge. 3:trigger at + any edge. 4:valid at low level. 5:valid at high level */ + __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from + Light-sleep Mode) */ + __IOM uint32_t CONFIG : 2; /*!< reserved */ + __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not + shielded) interrupt. */ + uint32_t : 14; + } bit; + } PIN40; + __IM uint32_t RESERVED67; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC27_IN_SEL_CFG; + __IM uint32_t RESERVED68; + + union { + __IOM uint32_t reg; /*!< GPIO pin configuration register */ + + struct { + __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ + __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + uint32_t : 2; + __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. + 1:trigger at posedge. 2:trigger at negedge. 3:trigger at + any edge. 4:valid at low level. 5:valid at high level */ + __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from + Light-sleep Mode) */ + __IOM uint32_t CONFIG : 2; /*!< reserved */ + __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not + shielded) interrupt. */ + uint32_t : 14; + } bit; + } PIN41; + __IM uint32_t RESERVED69; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC28_IN_SEL_CFG; + __IM uint32_t RESERVED70; + + union { + __IOM uint32_t reg; /*!< GPIO pin configuration register */ + + struct { + __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ + __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + uint32_t : 2; + __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. + 1:trigger at posedge. 2:trigger at negedge. 3:trigger at + any edge. 4:valid at low level. 5:valid at high level */ + __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from + Light-sleep Mode) */ + __IOM uint32_t CONFIG : 2; /*!< reserved */ + __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not + shielded) interrupt. */ + uint32_t : 14; + } bit; + } PIN42; + __IM uint32_t RESERVED71; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC29_IN_SEL_CFG; + __IM uint32_t RESERVED72; + + union { + __IOM uint32_t reg; /*!< GPIO pin configuration register */ + + struct { + __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ + __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + uint32_t : 2; + __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. + 1:trigger at posedge. 2:trigger at negedge. 3:trigger at + any edge. 4:valid at low level. 5:valid at high level */ + __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from + Light-sleep Mode) */ + __IOM uint32_t CONFIG : 2; /*!< reserved */ + __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not + shielded) interrupt. */ + uint32_t : 14; + } bit; + } PIN43; + __IM uint32_t RESERVED73; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC30_IN_SEL_CFG; + __IM uint32_t RESERVED74; + + union { + __IOM uint32_t reg; /*!< GPIO pin configuration register */ + + struct { + __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ + __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + uint32_t : 2; + __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. + 1:trigger at posedge. 2:trigger at negedge. 3:trigger at + any edge. 4:valid at low level. 5:valid at high level */ + __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from + Light-sleep Mode) */ + __IOM uint32_t CONFIG : 2; /*!< reserved */ + __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not + shielded) interrupt. */ + uint32_t : 14; + } bit; + } PIN44; + __IM uint32_t RESERVED75; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC31_IN_SEL_CFG; + __IM uint32_t RESERVED76; + + union { + __IOM uint32_t reg; /*!< GPIO pin configuration register */ + + struct { + __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ + __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + uint32_t : 2; + __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. + 1:trigger at posedge. 2:trigger at negedge. 3:trigger at + any edge. 4:valid at low level. 5:valid at high level */ + __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from + Light-sleep Mode) */ + __IOM uint32_t CONFIG : 2; /*!< reserved */ + __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not + shielded) interrupt. */ + uint32_t : 14; + } bit; + } PIN45; + __IM uint32_t RESERVED77; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC32_IN_SEL_CFG; + __IM uint32_t RESERVED78; + + union { + __IOM uint32_t reg; /*!< GPIO pin configuration register */ + + struct { + __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ + __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + uint32_t : 2; + __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. + 1:trigger at posedge. 2:trigger at negedge. 3:trigger at + any edge. 4:valid at low level. 5:valid at high level */ + __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from + Light-sleep Mode) */ + __IOM uint32_t CONFIG : 2; /*!< reserved */ + __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not + shielded) interrupt. */ + uint32_t : 14; + } bit; + } PIN46; + __IM uint32_t RESERVED79; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC33_IN_SEL_CFG; + __IM uint32_t RESERVED80; + + union { + __IOM uint32_t reg; /*!< GPIO pin configuration register */ + + struct { + __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ + __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + uint32_t : 2; + __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. + 1:trigger at posedge. 2:trigger at negedge. 3:trigger at + any edge. 4:valid at low level. 5:valid at high level */ + __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from + Light-sleep Mode) */ + __IOM uint32_t CONFIG : 2; /*!< reserved */ + __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not + shielded) interrupt. */ + uint32_t : 14; + } bit; + } PIN47; + __IM uint32_t RESERVED81; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC34_IN_SEL_CFG; + __IM uint32_t RESERVED82; + + union { + __IOM uint32_t reg; /*!< GPIO pin configuration register */ + + struct { + __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ + __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + uint32_t : 2; + __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. + 1:trigger at posedge. 2:trigger at negedge. 3:trigger at + any edge. 4:valid at low level. 5:valid at high level */ + __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from + Light-sleep Mode) */ + __IOM uint32_t CONFIG : 2; /*!< reserved */ + __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not + shielded) interrupt. */ + uint32_t : 14; + } bit; + } PIN48; + __IM uint32_t RESERVED83; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC35_IN_SEL_CFG; + __IM uint32_t RESERVED84; + + union { + __IOM uint32_t reg; /*!< GPIO pin configuration register */ + + struct { + __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ + __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + uint32_t : 2; + __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. + 1:trigger at posedge. 2:trigger at negedge. 3:trigger at + any edge. 4:valid at low level. 5:valid at high level */ + __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from + Light-sleep Mode) */ + __IOM uint32_t CONFIG : 2; /*!< reserved */ + __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not + shielded) interrupt. */ + uint32_t : 14; + } bit; + } PIN49; + __IM uint32_t RESERVED85; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC36_IN_SEL_CFG; + __IM uint32_t RESERVED86; + + union { + __IOM uint32_t reg; /*!< GPIO pin configuration register */ + + struct { + __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ + __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + uint32_t : 2; + __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. + 1:trigger at posedge. 2:trigger at negedge. 3:trigger at + any edge. 4:valid at low level. 5:valid at high level */ + __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from + Light-sleep Mode) */ + __IOM uint32_t CONFIG : 2; /*!< reserved */ + __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not + shielded) interrupt. */ + uint32_t : 14; + } bit; + } PIN50; + __IM uint32_t RESERVED87; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC37_IN_SEL_CFG; + __IM uint32_t RESERVED88; + + union { + __IOM uint32_t reg; /*!< GPIO pin configuration register */ + + struct { + __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ + __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + uint32_t : 2; + __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. + 1:trigger at posedge. 2:trigger at negedge. 3:trigger at + any edge. 4:valid at low level. 5:valid at high level */ + __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from + Light-sleep Mode) */ + __IOM uint32_t CONFIG : 2; /*!< reserved */ + __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not + shielded) interrupt. */ + uint32_t : 14; + } bit; + } PIN51; + __IM uint32_t RESERVED89; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC38_IN_SEL_CFG; + __IM uint32_t RESERVED90; + + union { + __IOM uint32_t reg; /*!< GPIO pin configuration register */ + + struct { + __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ + __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + uint32_t : 2; + __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. + 1:trigger at posedge. 2:trigger at negedge. 3:trigger at + any edge. 4:valid at low level. 5:valid at high level */ + __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from + Light-sleep Mode) */ + __IOM uint32_t CONFIG : 2; /*!< reserved */ + __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not + shielded) interrupt. */ + uint32_t : 14; + } bit; + } PIN52; + __IM uint32_t RESERVED91; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC39_IN_SEL_CFG; + __IM uint32_t RESERVED92; + + union { + __IOM uint32_t reg; /*!< GPIO pin configuration register */ + + struct { + __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ + __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + uint32_t : 2; + __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. + 1:trigger at posedge. 2:trigger at negedge. 3:trigger at + any edge. 4:valid at low level. 5:valid at high level */ + __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from + Light-sleep Mode) */ + __IOM uint32_t CONFIG : 2; /*!< reserved */ + __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not + shielded) interrupt. */ + uint32_t : 14; + } bit; + } PIN53; + __IM uint32_t RESERVED93; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC40_IN_SEL_CFG; + __IM uint32_t RESERVED94; + + union { + __IOM uint32_t reg; /*!< GPIO pin configuration register */ + + struct { + __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ + __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + uint32_t : 2; + __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. + 1:trigger at posedge. 2:trigger at negedge. 3:trigger at + any edge. 4:valid at low level. 5:valid at high level */ + __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from + Light-sleep Mode) */ + __IOM uint32_t CONFIG : 2; /*!< reserved */ + __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not + shielded) interrupt. */ + uint32_t : 14; + } bit; + } PIN54; + __IM uint32_t RESERVED95; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC41_IN_SEL_CFG; + __IM uint32_t RESERVED96; + + union { + __IOM uint32_t reg; /*!< GPIO pin configuration register */ + + struct { + __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ + __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + uint32_t : 2; + __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. + 1:trigger at posedge. 2:trigger at negedge. 3:trigger at + any edge. 4:valid at low level. 5:valid at high level */ + __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from + Light-sleep Mode) */ + __IOM uint32_t CONFIG : 2; /*!< reserved */ + __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not + shielded) interrupt. */ + uint32_t : 14; + } bit; + } PIN55; + __IM uint32_t RESERVED97; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC42_IN_SEL_CFG; + __IM uint32_t RESERVED98; + + union { + __IOM uint32_t reg; /*!< GPIO pin configuration register */ + + struct { + __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ + __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. + 2or3:trigger at posedge. */ + uint32_t : 2; + __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. + 1:trigger at posedge. 2:trigger at negedge. 3:trigger at + any edge. 4:valid at low level. 5:valid at high level */ + __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from + Light-sleep Mode) */ + __IOM uint32_t CONFIG : 2; /*!< reserved */ + __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not + shielded) interrupt. */ + uint32_t : 14; + } bit; + } PIN56; + __IM uint32_t RESERVED99; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC43_IN_SEL_CFG; + __IM uint32_t RESERVED100[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC44_IN_SEL_CFG; + __IM uint32_t RESERVED101[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC45_IN_SEL_CFG; + __IM uint32_t RESERVED102[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC46_IN_SEL_CFG; + __IM uint32_t RESERVED103[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC47_IN_SEL_CFG; + __IM uint32_t RESERVED104[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC48_IN_SEL_CFG; + __IM uint32_t RESERVED105[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC49_IN_SEL_CFG; + __IM uint32_t RESERVED106[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC50_IN_SEL_CFG; + __IM uint32_t RESERVED107[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC51_IN_SEL_CFG; + __IM uint32_t RESERVED108[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC52_IN_SEL_CFG; + __IM uint32_t RESERVED109[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC53_IN_SEL_CFG; + __IM uint32_t RESERVED110[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC54_IN_SEL_CFG; + __IM uint32_t RESERVED111[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC55_IN_SEL_CFG; + __IM uint32_t RESERVED112[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC56_IN_SEL_CFG; + __IM uint32_t RESERVED113[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC57_IN_SEL_CFG; + __IM uint32_t RESERVED114[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC58_IN_SEL_CFG; + __IM uint32_t RESERVED115[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC59_IN_SEL_CFG; + __IM uint32_t RESERVED116[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC60_IN_SEL_CFG; + __IM uint32_t RESERVED117[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC61_IN_SEL_CFG; + __IM uint32_t RESERVED118[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC62_IN_SEL_CFG; + __IM uint32_t RESERVED119[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC63_IN_SEL_CFG; + __IM uint32_t RESERVED120[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC64_IN_SEL_CFG; + __IM uint32_t RESERVED121[2]; + + union { + __IOM uint32_t reg; /*!< GPIO output function select register */ + + struct { + __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output + signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. + s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ + __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ + __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] + as output enable signal.0:use peripheral output enable + signal. */ + __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ + uint32_t : 20; + } bit; + } FUNC0_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC65_IN_SEL_CFG; + __IM uint32_t RESERVED122[2]; + + union { + __IOM uint32_t reg; /*!< GPIO output function select register */ + + struct { + __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output + signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. + s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ + __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ + __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] + as output enable signal.0:use peripheral output enable + signal. */ + __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ + uint32_t : 20; + } bit; + } FUNC1_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC66_IN_SEL_CFG; + __IM uint32_t RESERVED123[2]; + + union { + __IOM uint32_t reg; /*!< GPIO output function select register */ + + struct { + __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output + signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. + s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ + __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ + __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] + as output enable signal.0:use peripheral output enable + signal. */ + __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ + uint32_t : 20; + } bit; + } FUNC2_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC67_IN_SEL_CFG; + __IM uint32_t RESERVED124[2]; + + union { + __IOM uint32_t reg; /*!< GPIO output function select register */ + + struct { + __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output + signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. + s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ + __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ + __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] + as output enable signal.0:use peripheral output enable + signal. */ + __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ + uint32_t : 20; + } bit; + } FUNC3_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC68_IN_SEL_CFG; + __IM uint32_t RESERVED125[2]; + + union { + __IOM uint32_t reg; /*!< GPIO output function select register */ + + struct { + __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output + signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. + s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ + __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ + __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] + as output enable signal.0:use peripheral output enable + signal. */ + __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ + uint32_t : 20; + } bit; + } FUNC4_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC69_IN_SEL_CFG; + __IM uint32_t RESERVED126[2]; + + union { + __IOM uint32_t reg; /*!< GPIO output function select register */ + + struct { + __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output + signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. + s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ + __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ + __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] + as output enable signal.0:use peripheral output enable + signal. */ + __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ + uint32_t : 20; + } bit; + } FUNC5_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC70_IN_SEL_CFG; + __IM uint32_t RESERVED127[2]; + + union { + __IOM uint32_t reg; /*!< GPIO output function select register */ + + struct { + __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output + signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. + s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ + __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ + __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] + as output enable signal.0:use peripheral output enable + signal. */ + __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ + uint32_t : 20; + } bit; + } FUNC6_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC71_IN_SEL_CFG; + __IM uint32_t RESERVED128[2]; + + union { + __IOM uint32_t reg; /*!< GPIO output function select register */ + + struct { + __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output + signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. + s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ + __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ + __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] + as output enable signal.0:use peripheral output enable + signal. */ + __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ + uint32_t : 20; + } bit; + } FUNC7_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC72_IN_SEL_CFG; + __IM uint32_t RESERVED129[2]; + + union { + __IOM uint32_t reg; /*!< GPIO output function select register */ + + struct { + __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output + signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. + s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ + __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ + __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] + as output enable signal.0:use peripheral output enable + signal. */ + __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ + uint32_t : 20; + } bit; + } FUNC8_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC73_IN_SEL_CFG; + __IM uint32_t RESERVED130[2]; + + union { + __IOM uint32_t reg; /*!< GPIO output function select register */ + + struct { + __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output + signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. + s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ + __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ + __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] + as output enable signal.0:use peripheral output enable + signal. */ + __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ + uint32_t : 20; + } bit; + } FUNC9_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC74_IN_SEL_CFG; + __IM uint32_t RESERVED131[2]; + + union { + __IOM uint32_t reg; /*!< GPIO output function select register */ + + struct { + __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output + signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. + s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ + __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ + __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] + as output enable signal.0:use peripheral output enable + signal. */ + __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ + uint32_t : 20; + } bit; + } FUNC10_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC75_IN_SEL_CFG; + __IM uint32_t RESERVED132[2]; + + union { + __IOM uint32_t reg; /*!< GPIO output function select register */ + + struct { + __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output + signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. + s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ + __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ + __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] + as output enable signal.0:use peripheral output enable + signal. */ + __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ + uint32_t : 20; + } bit; + } FUNC11_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC76_IN_SEL_CFG; + __IM uint32_t RESERVED133[2]; + + union { + __IOM uint32_t reg; /*!< GPIO output function select register */ + + struct { + __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output + signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. + s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ + __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ + __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] + as output enable signal.0:use peripheral output enable + signal. */ + __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ + uint32_t : 20; + } bit; + } FUNC12_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC77_IN_SEL_CFG; + __IM uint32_t RESERVED134[2]; + + union { + __IOM uint32_t reg; /*!< GPIO output function select register */ + + struct { + __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output + signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. + s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ + __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ + __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] + as output enable signal.0:use peripheral output enable + signal. */ + __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ + uint32_t : 20; + } bit; + } FUNC13_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC78_IN_SEL_CFG; + __IM uint32_t RESERVED135[2]; + + union { + __IOM uint32_t reg; /*!< GPIO output function select register */ + + struct { + __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output + signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. + s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ + __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ + __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] + as output enable signal.0:use peripheral output enable + signal. */ + __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ + uint32_t : 20; + } bit; + } FUNC14_OUT_SEL_CFG; + + union { + union { + __IOM uint32_t reg; /*!< GPIO interrupt 2 status register for GPIO0-31 */ + + struct { + __IM uint32_t INT_2 : 32; /*!< GPIO interrupt 2 status register for GPIO0-31 */ + } bit; + } INTR_2; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC79_IN_SEL_CFG; + }; + + union { + __IOM uint32_t reg; /*!< GPIO interrupt 2 status register for GPIO32-56 */ + + struct { + __IM uint32_t INT1_2 : 25; /*!< GPIO interrupt 2 status register for GPIO32-56 */ + uint32_t : 7; + } bit; + } INTR1_2; + + union { + __IOM uint32_t reg; /*!< GPIO interrupt 3 status register for GPIO0-31 */ + + struct { + __IM uint32_t INT_3 : 32; /*!< GPIO interrupt 3 status register for GPIO0-31 */ + } bit; + } INTR_3; + + union { + union { + __IOM uint32_t reg; /*!< GPIO output function select register */ + + struct { + __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output + signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. + s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ + __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ + __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] + as output enable signal.0:use peripheral output enable + signal. */ + __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ + uint32_t : 20; + } bit; + } FUNC15_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< GPIO interrupt 3 status register for GPIO32-56 */ + + struct { + __IM uint32_t INT1_3 : 25; /*!< GPIO interrupt 3 status register for GPIO32-56 */ + uint32_t : 7; + } bit; + } INTR1_3; + }; + + union { + union { + __IOM uint32_t reg; /*!< GPIO clock gate register */ + + struct { + __IOM uint32_t CLK_EN : 1; /*!< set this bit to enable GPIO clock gate */ + uint32_t : 31; + } bit; + } CLOCK_GATE; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC80_IN_SEL_CFG; + }; + __IM uint32_t RESERVED136[2]; + + union { + __IOM uint32_t reg; /*!< GPIO output function select register */ + + struct { + __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output + signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. + s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ + __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ + __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] + as output enable signal.0:use peripheral output enable + signal. */ + __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ + uint32_t : 20; + } bit; + } FUNC16_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC81_IN_SEL_CFG; + __IM uint32_t RESERVED137[2]; + + union { + __IOM uint32_t reg; /*!< GPIO output function select register */ + + struct { + __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output + signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. + s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ + __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ + __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] + as output enable signal.0:use peripheral output enable + signal. */ + __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ + uint32_t : 20; + } bit; + } FUNC17_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC82_IN_SEL_CFG; + __IM uint32_t RESERVED138[2]; + + union { + __IOM uint32_t reg; /*!< GPIO output function select register */ + + struct { + __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output + signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. + s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ + __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ + __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] + as output enable signal.0:use peripheral output enable + signal. */ + __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ + uint32_t : 20; + } bit; + } FUNC18_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC83_IN_SEL_CFG; + __IM uint32_t RESERVED139[2]; + + union { + __IOM uint32_t reg; /*!< GPIO output function select register */ + + struct { + __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output + signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. + s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ + __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ + __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] + as output enable signal.0:use peripheral output enable + signal. */ + __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ + uint32_t : 20; + } bit; + } FUNC19_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC84_IN_SEL_CFG; + __IM uint32_t RESERVED140[2]; + + union { + __IOM uint32_t reg; /*!< GPIO output function select register */ + + struct { + __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output + signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. + s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ + __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ + __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] + as output enable signal.0:use peripheral output enable + signal. */ + __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ + uint32_t : 20; + } bit; + } FUNC20_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC85_IN_SEL_CFG; + __IM uint32_t RESERVED141[2]; + + union { + __IOM uint32_t reg; /*!< GPIO output function select register */ + + struct { + __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output + signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. + s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ + __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ + __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] + as output enable signal.0:use peripheral output enable + signal. */ + __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ + uint32_t : 20; + } bit; + } FUNC21_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC86_IN_SEL_CFG; + __IM uint32_t RESERVED142[2]; + + union { + __IOM uint32_t reg; /*!< GPIO output function select register */ + + struct { + __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output + signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. + s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ + __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ + __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] + as output enable signal.0:use peripheral output enable + signal. */ + __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ + uint32_t : 20; + } bit; + } FUNC22_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC87_IN_SEL_CFG; + __IM uint32_t RESERVED143[2]; + + union { + __IOM uint32_t reg; /*!< GPIO output function select register */ + + struct { + __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output + signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. + s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ + __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ + __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] + as output enable signal.0:use peripheral output enable + signal. */ + __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ + uint32_t : 20; + } bit; + } FUNC23_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC88_IN_SEL_CFG; + __IM uint32_t RESERVED144[2]; + + union { + __IOM uint32_t reg; /*!< GPIO output function select register */ + + struct { + __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output + signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. + s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ + __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ + __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] + as output enable signal.0:use peripheral output enable + signal. */ + __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ + uint32_t : 20; + } bit; + } FUNC24_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC89_IN_SEL_CFG; + __IM uint32_t RESERVED145[2]; + + union { + __IOM uint32_t reg; /*!< GPIO output function select register */ + + struct { + __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output + signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. + s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ + __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ + __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] + as output enable signal.0:use peripheral output enable + signal. */ + __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ + uint32_t : 20; + } bit; + } FUNC25_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC90_IN_SEL_CFG; + __IM uint32_t RESERVED146[2]; + + union { + __IOM uint32_t reg; /*!< GPIO output function select register */ + + struct { + __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output + signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. + s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ + __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ + __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] + as output enable signal.0:use peripheral output enable + signal. */ + __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ + uint32_t : 20; + } bit; + } FUNC26_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC91_IN_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< analog comparator interrupt raw */ + + struct { + __IOM uint32_t COMP0_NEG_INT_RAW : 1; /*!< analog comparator pos edge interrupt raw */ + __IOM uint32_t COMP0_POS_INT_RAW : 1; /*!< analog comparator neg edge interrupt raw */ + __IOM uint32_t COMP0_ALL_INT_RAW : 1; /*!< analog comparator neg or pos edge interrupt raw */ + __IOM uint32_t COMP1_NEG_INT_RAW : 1; /*!< analog comparator pos edge interrupt raw */ + __IOM uint32_t COMP1_POS_INT_RAW : 1; /*!< analog comparator neg edge interrupt raw */ + __IOM uint32_t COMP1_ALL_INT_RAW : 1; /*!< analog comparator neg or pos edge interrupt raw */ + __IOM uint32_t BISTOK_INT_RAW : 1; /*!< pad bistok interrupt raw */ + __IOM uint32_t BISTFAIL_INT_RAW : 1; /*!< pad bistfail interrupt raw */ + uint32_t : 24; + } bit; + } INT_RAW; + + union { + __IOM uint32_t reg; /*!< analog comparator interrupt status */ + + struct { + __IM uint32_t COMP0_NEG_INT_ST : 1; /*!< analog comparator pos edge interrupt status */ + __IM uint32_t COMP0_POS_INT_ST : 1; /*!< analog comparator neg edge interrupt status */ + __IM uint32_t COMP0_ALL_INT_ST : 1; /*!< analog comparator neg or pos edge interrupt status */ + __IM uint32_t COMP1_NEG_INT_ST : 1; /*!< analog comparator pos edge interrupt status */ + __IM uint32_t COMP1_POS_INT_ST : 1; /*!< analog comparator neg edge interrupt status */ + __IM uint32_t COMP1_ALL_INT_ST : 1; /*!< analog comparator neg or pos edge interrupt status */ + __IM uint32_t BISTOK_INT_ST : 1; /*!< pad bistok interrupt status */ + __IM uint32_t BISTFAIL_INT_ST : 1; /*!< pad bistfail interrupt status */ + uint32_t : 24; + } bit; + } INT_ST; + + union { + union { + __IOM uint32_t reg; /*!< GPIO output function select register */ + + struct { + __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output + signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. + s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ + __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ + __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] + as output enable signal.0:use peripheral output enable + signal. */ + __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ + uint32_t : 20; + } bit; + } FUNC27_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< analog comparator interrupt enable */ + + struct { + __IOM uint32_t COMP0_NEG_INT_ENA : 1; /*!< analog comparator pos edge interrupt enable */ + __IOM uint32_t COMP0_POS_INT_ENA : 1; /*!< analog comparator neg edge interrupt enable */ + __IOM uint32_t COMP0_ALL_INT_ENA : 1; /*!< analog comparator neg or pos edge interrupt enable */ + __IOM uint32_t COMP1_NEG_INT_ENA : 1; /*!< analog comparator pos edge interrupt enable */ + __IOM uint32_t COMP1_POS_INT_ENA : 1; /*!< analog comparator neg edge interrupt enable */ + __IOM uint32_t COMP1_ALL_INT_ENA : 1; /*!< analog comparator neg or pos edge interrupt enable */ + __IOM uint32_t BISTOK_INT_ENA : 1; /*!< pad bistok interrupt enable */ + __IOM uint32_t BISTFAIL_INT_ENA : 1; /*!< pad bistfail interrupt enable */ + uint32_t : 24; + } bit; + } INT_ENA; + }; + + union { + union { + __IOM uint32_t reg; /*!< analog comparator interrupt clear */ + + struct { + __OM uint32_t COMP0_NEG_INT_CLR : 1; /*!< analog comparator pos edge interrupt clear */ + __OM uint32_t COMP0_POS_INT_CLR : 1; /*!< analog comparator neg edge interrupt clear */ + __OM uint32_t COMP0_ALL_INT_CLR : 1; /*!< analog comparator neg or pos edge interrupt clear */ + __OM uint32_t COMP1_NEG_INT_CLR : 1; /*!< analog comparator pos edge interrupt clear */ + __OM uint32_t COMP1_POS_INT_CLR : 1; /*!< analog comparator neg edge interrupt clear */ + __OM uint32_t COMP1_ALL_INT_CLR : 1; /*!< analog comparator neg or pos edge interrupt clear */ + __OM uint32_t BISTOK_INT_CLR : 1; /*!< pad bistok interrupt enable */ + __OM uint32_t BISTFAIL_INT_CLR : 1; /*!< pad bistfail interrupt enable */ + uint32_t : 24; + } bit; + } INT_CLR; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC92_IN_SEL_CFG; + }; + + union { + __IOM uint32_t reg; /*!< GPIO analog comparator zero detect filter count */ + + struct { + __IOM uint32_t ZERO_DET0_FILTER_CNT : 32; /*!< GPIO analog comparator zero detect filter count */ + } bit; + } ZERO_DET0_FILTER_CNT; + + union { + __IOM uint32_t reg; /*!< GPIO analog comparator zero detect filter count */ + + struct { + __IOM uint32_t ZERO_DET1_FILTER_CNT : 32; /*!< GPIO analog comparator zero detect filter count */ + } bit; + } ZERO_DET1_FILTER_CNT; + + union { + union { + __IOM uint32_t reg; /*!< GPIO output function select register */ + + struct { + __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output + signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. + s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ + __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ + __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] + as output enable signal.0:use peripheral output enable + signal. */ + __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ + uint32_t : 20; + } bit; + } FUNC28_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< High speed sdio pad bist send sequence */ + + struct { + __IOM uint32_t SEND_SEQ : 32; /*!< High speed sdio pad bist send sequence */ + } bit; + } SEND_SEQ; + }; + + union { + union { + __IOM uint32_t reg; /*!< High speed sdio pad bist recive sequence */ + + struct { + __IM uint32_t RECIVE_SEQ : 32; /*!< High speed sdio pad bist recive sequence */ + } bit; + } RECIVE_SEQ; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC93_IN_SEL_CFG; + }; + + union { + __IOM uint32_t reg; /*!< High speed sdio pad bist in pad sel */ + + struct { + __IOM uint32_t BISTIN_SEL : 4; /*!< High speed sdio pad bist in pad sel 0:pad39, 1: pad40... */ + uint32_t : 28; + } bit; + } BISTIN_SEL; + + union { + __IOM uint32_t reg; /*!< High speed sdio pad bist control */ + + struct { + __IOM uint32_t BIST_PAD_OE : 1; /*!< High speed sdio pad bist out pad oe */ + __OM uint32_t BIST_START : 1; /*!< High speed sdio pad bist start */ + uint32_t : 30; + } bit; + } BIST_CTRL; + + union { + __IOM uint32_t reg; /*!< GPIO output function select register */ + + struct { + __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output + signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. + s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ + __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ + __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] + as output enable signal.0:use peripheral output enable + signal. */ + __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ + uint32_t : 20; + } bit; + } FUNC29_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC94_IN_SEL_CFG; + __IM uint32_t RESERVED147[2]; + + union { + __IOM uint32_t reg; /*!< GPIO output function select register */ + + struct { + __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output + signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. + s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ + __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ + __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] + as output enable signal.0:use peripheral output enable + signal. */ + __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ + uint32_t : 20; + } bit; + } FUNC30_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC95_IN_SEL_CFG; + __IM uint32_t RESERVED148[2]; + + union { + __IOM uint32_t reg; /*!< GPIO output function select register */ + + struct { + __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output + signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. + s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ + __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ + __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] + as output enable signal.0:use peripheral output enable + signal. */ + __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ + uint32_t : 20; + } bit; + } FUNC31_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC96_IN_SEL_CFG; + __IM uint32_t RESERVED149[2]; + + union { + __IOM uint32_t reg; /*!< GPIO output function select register */ + + struct { + __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output + signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. + s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ + __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ + __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] + as output enable signal.0:use peripheral output enable + signal. */ + __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ + uint32_t : 20; + } bit; + } FUNC32_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC97_IN_SEL_CFG; + __IM uint32_t RESERVED150[2]; + + union { + __IOM uint32_t reg; /*!< GPIO output function select register */ + + struct { + __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output + signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. + s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ + __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ + __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] + as output enable signal.0:use peripheral output enable + signal. */ + __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ + uint32_t : 20; + } bit; + } FUNC33_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC98_IN_SEL_CFG; + __IM uint32_t RESERVED151[2]; + + union { + __IOM uint32_t reg; /*!< GPIO output function select register */ + + struct { + __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output + signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. + s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ + __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ + __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] + as output enable signal.0:use peripheral output enable + signal. */ + __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ + uint32_t : 20; + } bit; + } FUNC34_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC99_IN_SEL_CFG; + __IM uint32_t RESERVED152[2]; + + union { + __IOM uint32_t reg; /*!< GPIO output function select register */ + + struct { + __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output + signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. + s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ + __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ + __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] + as output enable signal.0:use peripheral output enable + signal. */ + __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ + uint32_t : 20; + } bit; + } FUNC35_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC100_IN_SEL_CFG; + __IM uint32_t RESERVED153[2]; + + union { + __IOM uint32_t reg; /*!< GPIO output function select register */ + + struct { + __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output + signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. + s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ + __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ + __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] + as output enable signal.0:use peripheral output enable + signal. */ + __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ + uint32_t : 20; + } bit; + } FUNC36_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC101_IN_SEL_CFG; + __IM uint32_t RESERVED154[2]; + + union { + __IOM uint32_t reg; /*!< GPIO output function select register */ + + struct { + __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output + signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. + s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ + __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ + __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] + as output enable signal.0:use peripheral output enable + signal. */ + __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ + uint32_t : 20; + } bit; + } FUNC37_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC102_IN_SEL_CFG; + __IM uint32_t RESERVED155[2]; + + union { + __IOM uint32_t reg; /*!< GPIO output function select register */ + + struct { + __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output + signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. + s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ + __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ + __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] + as output enable signal.0:use peripheral output enable + signal. */ + __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ + uint32_t : 20; + } bit; + } FUNC38_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC103_IN_SEL_CFG; + __IM uint32_t RESERVED156[2]; + + union { + __IOM uint32_t reg; /*!< GPIO output function select register */ + + struct { + __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output + signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. + s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ + __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ + __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] + as output enable signal.0:use peripheral output enable + signal. */ + __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ + uint32_t : 20; + } bit; + } FUNC39_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC104_IN_SEL_CFG; + __IM uint32_t RESERVED157[2]; + + union { + __IOM uint32_t reg; /*!< GPIO output function select register */ + + struct { + __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output + signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. + s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ + __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ + __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] + as output enable signal.0:use peripheral output enable + signal. */ + __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ + uint32_t : 20; + } bit; + } FUNC40_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC105_IN_SEL_CFG; + __IM uint32_t RESERVED158[2]; + + union { + __IOM uint32_t reg; /*!< GPIO output function select register */ + + struct { + __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output + signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. + s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ + __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ + __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] + as output enable signal.0:use peripheral output enable + signal. */ + __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ + uint32_t : 20; + } bit; + } FUNC41_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC106_IN_SEL_CFG; + __IM uint32_t RESERVED159[2]; + + union { + __IOM uint32_t reg; /*!< GPIO output function select register */ + + struct { + __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output + signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. + s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ + __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ + __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] + as output enable signal.0:use peripheral output enable + signal. */ + __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ + uint32_t : 20; + } bit; + } FUNC42_OUT_SEL_CFG; + + union { + union { + __IOM uint32_t reg; /*!< GPIO version register */ + + struct { + __IOM uint32_t DATE : 28; /*!< version register */ + uint32_t : 4; + } bit; + } DATE; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC107_IN_SEL_CFG; + }; + __IM uint32_t RESERVED160[2]; + + union { + __IOM uint32_t reg; /*!< GPIO output function select register */ + + struct { + __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output + signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. + s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ + __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ + __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] + as output enable signal.0:use peripheral output enable + signal. */ + __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ + uint32_t : 20; + } bit; + } FUNC43_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC108_IN_SEL_CFG; + __IM uint32_t RESERVED161[2]; + + union { + __IOM uint32_t reg; /*!< GPIO output function select register */ + + struct { + __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output + signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. + s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ + __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ + __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] + as output enable signal.0:use peripheral output enable + signal. */ + __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ + uint32_t : 20; + } bit; + } FUNC44_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC109_IN_SEL_CFG; + __IM uint32_t RESERVED162[2]; + + union { + __IOM uint32_t reg; /*!< GPIO output function select register */ + + struct { + __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output + signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. + s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ + __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ + __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] + as output enable signal.0:use peripheral output enable + signal. */ + __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ + uint32_t : 20; + } bit; + } FUNC45_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC110_IN_SEL_CFG; + __IM uint32_t RESERVED163[2]; + + union { + __IOM uint32_t reg; /*!< GPIO output function select register */ + + struct { + __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output + signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. + s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ + __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ + __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] + as output enable signal.0:use peripheral output enable + signal. */ + __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ + uint32_t : 20; + } bit; + } FUNC46_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC111_IN_SEL_CFG; + __IM uint32_t RESERVED164[2]; + + union { + __IOM uint32_t reg; /*!< GPIO output function select register */ + + struct { + __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output + signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. + s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ + __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ + __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] + as output enable signal.0:use peripheral output enable + signal. */ + __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ + uint32_t : 20; + } bit; + } FUNC47_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC112_IN_SEL_CFG; + __IM uint32_t RESERVED165[2]; + + union { + __IOM uint32_t reg; /*!< GPIO output function select register */ + + struct { + __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output + signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. + s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ + __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ + __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] + as output enable signal.0:use peripheral output enable + signal. */ + __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ + uint32_t : 20; + } bit; + } FUNC48_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC113_IN_SEL_CFG; + __IM uint32_t RESERVED166[2]; + + union { + __IOM uint32_t reg; /*!< GPIO output function select register */ + + struct { + __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output + signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. + s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ + __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ + __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] + as output enable signal.0:use peripheral output enable + signal. */ + __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ + uint32_t : 20; + } bit; + } FUNC49_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC114_IN_SEL_CFG; + __IM uint32_t RESERVED167[2]; + + union { + __IOM uint32_t reg; /*!< GPIO output function select register */ + + struct { + __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output + signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. + s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ + __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ + __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] + as output enable signal.0:use peripheral output enable + signal. */ + __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ + uint32_t : 20; + } bit; + } FUNC50_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC115_IN_SEL_CFG; + __IM uint32_t RESERVED168[2]; + + union { + __IOM uint32_t reg; /*!< GPIO output function select register */ + + struct { + __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output + signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. + s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ + __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ + __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] + as output enable signal.0:use peripheral output enable + signal. */ + __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ + uint32_t : 20; + } bit; + } FUNC51_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC116_IN_SEL_CFG; + __IM uint32_t RESERVED169[2]; + + union { + __IOM uint32_t reg; /*!< GPIO output function select register */ + + struct { + __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output + signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. + s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ + __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ + __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] + as output enable signal.0:use peripheral output enable + signal. */ + __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ + uint32_t : 20; + } bit; + } FUNC52_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC117_IN_SEL_CFG; + __IM uint32_t RESERVED170[2]; + + union { + __IOM uint32_t reg; /*!< GPIO output function select register */ + + struct { + __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output + signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. + s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ + __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ + __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] + as output enable signal.0:use peripheral output enable + signal. */ + __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ + uint32_t : 20; + } bit; + } FUNC53_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC118_IN_SEL_CFG; + __IM uint32_t RESERVED171[2]; + + union { + __IOM uint32_t reg; /*!< GPIO output function select register */ + + struct { + __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output + signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. + s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ + __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ + __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] + as output enable signal.0:use peripheral output enable + signal. */ + __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ + uint32_t : 20; + } bit; + } FUNC54_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC119_IN_SEL_CFG; + __IM uint32_t RESERVED172[2]; + + union { + __IOM uint32_t reg; /*!< GPIO output function select register */ + + struct { + __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output + signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. + s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ + __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ + __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] + as output enable signal.0:use peripheral output enable + signal. */ + __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ + uint32_t : 20; + } bit; + } FUNC55_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC120_IN_SEL_CFG; + __IM uint32_t RESERVED173[2]; + + union { + __IOM uint32_t reg; /*!< GPIO output function select register */ + + struct { + __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output + signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. + s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ + __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ + __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] + as output enable signal.0:use peripheral output enable + signal. */ + __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ + uint32_t : 20; + } bit; + } FUNC56_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC121_IN_SEL_CFG; + __IM uint32_t RESERVED174[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC122_IN_SEL_CFG; + __IM uint32_t RESERVED175[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC123_IN_SEL_CFG; + __IM uint32_t RESERVED176[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC124_IN_SEL_CFG; + __IM uint32_t RESERVED177[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC125_IN_SEL_CFG; + __IM uint32_t RESERVED178[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC126_IN_SEL_CFG; + __IM uint32_t RESERVED179[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC127_IN_SEL_CFG; + __IM uint32_t RESERVED180[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC128_IN_SEL_CFG; + __IM uint32_t RESERVED181[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC129_IN_SEL_CFG; + __IM uint32_t RESERVED182[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC130_IN_SEL_CFG; + __IM uint32_t RESERVED183[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC131_IN_SEL_CFG; + __IM uint32_t RESERVED184[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC132_IN_SEL_CFG; + __IM uint32_t RESERVED185[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC133_IN_SEL_CFG; + __IM uint32_t RESERVED186[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC134_IN_SEL_CFG; + __IM uint32_t RESERVED187[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC135_IN_SEL_CFG; + __IM uint32_t RESERVED188[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC136_IN_SEL_CFG; + __IM uint32_t RESERVED189[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC137_IN_SEL_CFG; + __IM uint32_t RESERVED190[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC138_IN_SEL_CFG; + __IM uint32_t RESERVED191[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC139_IN_SEL_CFG; + __IM uint32_t RESERVED192[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC140_IN_SEL_CFG; + __IM uint32_t RESERVED193[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC141_IN_SEL_CFG; + __IM uint32_t RESERVED194[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC142_IN_SEL_CFG; + __IM uint32_t RESERVED195[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC143_IN_SEL_CFG; + __IM uint32_t RESERVED196[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC144_IN_SEL_CFG; + __IM uint32_t RESERVED197[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC145_IN_SEL_CFG; + __IM uint32_t RESERVED198[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC146_IN_SEL_CFG; + __IM uint32_t RESERVED199[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC147_IN_SEL_CFG; + __IM uint32_t RESERVED200[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC148_IN_SEL_CFG; + __IM uint32_t RESERVED201[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC149_IN_SEL_CFG; + __IM uint32_t RESERVED202[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC150_IN_SEL_CFG; + __IM uint32_t RESERVED203[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC151_IN_SEL_CFG; + __IM uint32_t RESERVED204[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC152_IN_SEL_CFG; + __IM uint32_t RESERVED205[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC153_IN_SEL_CFG; + __IM uint32_t RESERVED206[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC154_IN_SEL_CFG; + __IM uint32_t RESERVED207[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC155_IN_SEL_CFG; + __IM uint32_t RESERVED208[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC156_IN_SEL_CFG; + __IM uint32_t RESERVED209[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC157_IN_SEL_CFG; + __IM uint32_t RESERVED210[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC158_IN_SEL_CFG; + __IM uint32_t RESERVED211[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC159_IN_SEL_CFG; + __IM uint32_t RESERVED212[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC160_IN_SEL_CFG; + __IM uint32_t RESERVED213[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC161_IN_SEL_CFG; + __IM uint32_t RESERVED214[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC162_IN_SEL_CFG; + __IM uint32_t RESERVED215[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC163_IN_SEL_CFG; + __IM uint32_t RESERVED216[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC164_IN_SEL_CFG; + __IM uint32_t RESERVED217[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC165_IN_SEL_CFG; + __IM uint32_t RESERVED218[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC166_IN_SEL_CFG; + __IM uint32_t RESERVED219[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC167_IN_SEL_CFG; + __IM uint32_t RESERVED220[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC168_IN_SEL_CFG; + __IM uint32_t RESERVED221[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC169_IN_SEL_CFG; + __IM uint32_t RESERVED222[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC170_IN_SEL_CFG; + __IM uint32_t RESERVED223[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC171_IN_SEL_CFG; + __IM uint32_t RESERVED224[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC172_IN_SEL_CFG; + __IM uint32_t RESERVED225[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC173_IN_SEL_CFG; + __IM uint32_t RESERVED226[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC174_IN_SEL_CFG; + __IM uint32_t RESERVED227[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC175_IN_SEL_CFG; + __IM uint32_t RESERVED228[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC176_IN_SEL_CFG; + __IM uint32_t RESERVED229[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC177_IN_SEL_CFG; + __IM uint32_t RESERVED230[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC178_IN_SEL_CFG; + __IM uint32_t RESERVED231[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC179_IN_SEL_CFG; + __IM uint32_t RESERVED232[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC180_IN_SEL_CFG; + __IM uint32_t RESERVED233[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC181_IN_SEL_CFG; + __IM uint32_t RESERVED234[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC182_IN_SEL_CFG; + __IM uint32_t RESERVED235[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC183_IN_SEL_CFG; + __IM uint32_t RESERVED236[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC184_IN_SEL_CFG; + __IM uint32_t RESERVED237[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC185_IN_SEL_CFG; + __IM uint32_t RESERVED238[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC186_IN_SEL_CFG; + __IM uint32_t RESERVED239[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC187_IN_SEL_CFG; + __IM uint32_t RESERVED240[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC188_IN_SEL_CFG; + __IM uint32_t RESERVED241[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC189_IN_SEL_CFG; + __IM uint32_t RESERVED242[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC190_IN_SEL_CFG; + __IM uint32_t RESERVED243[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC191_IN_SEL_CFG; + __IM uint32_t RESERVED244[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC192_IN_SEL_CFG; + __IM uint32_t RESERVED245[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC193_IN_SEL_CFG; + __IM uint32_t RESERVED246[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC194_IN_SEL_CFG; + __IM uint32_t RESERVED247[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC195_IN_SEL_CFG; + __IM uint32_t RESERVED248[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC196_IN_SEL_CFG; + __IM uint32_t RESERVED249[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC197_IN_SEL_CFG; + __IM uint32_t RESERVED250[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC198_IN_SEL_CFG; + __IM uint32_t RESERVED251[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC199_IN_SEL_CFG; + __IM uint32_t RESERVED252[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC200_IN_SEL_CFG; + __IM uint32_t RESERVED253[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC201_IN_SEL_CFG; + __IM uint32_t RESERVED254[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC202_IN_SEL_CFG; + __IM uint32_t RESERVED255[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC203_IN_SEL_CFG; + __IM uint32_t RESERVED256[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC204_IN_SEL_CFG; + __IM uint32_t RESERVED257[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC205_IN_SEL_CFG; + __IM uint32_t RESERVED258[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC206_IN_SEL_CFG; + __IM uint32_t RESERVED259[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC207_IN_SEL_CFG; + __IM uint32_t RESERVED260[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC208_IN_SEL_CFG; + __IM uint32_t RESERVED261[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC209_IN_SEL_CFG; + __IM uint32_t RESERVED262[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC210_IN_SEL_CFG; + __IM uint32_t RESERVED263[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC211_IN_SEL_CFG; + __IM uint32_t RESERVED264[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC212_IN_SEL_CFG; + __IM uint32_t RESERVED265[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC213_IN_SEL_CFG; + __IM uint32_t RESERVED266[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC214_IN_SEL_CFG; + __IM uint32_t RESERVED267[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC215_IN_SEL_CFG; + __IM uint32_t RESERVED268[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC216_IN_SEL_CFG; + __IM uint32_t RESERVED269[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC217_IN_SEL_CFG; + __IM uint32_t RESERVED270[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC218_IN_SEL_CFG; + __IM uint32_t RESERVED271[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC219_IN_SEL_CFG; + __IM uint32_t RESERVED272[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC220_IN_SEL_CFG; + __IM uint32_t RESERVED273[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC221_IN_SEL_CFG; + __IM uint32_t RESERVED274[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC222_IN_SEL_CFG; + __IM uint32_t RESERVED275[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC223_IN_SEL_CFG; + __IM uint32_t RESERVED276[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC224_IN_SEL_CFG; + __IM uint32_t RESERVED277[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC225_IN_SEL_CFG; + __IM uint32_t RESERVED278[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC226_IN_SEL_CFG; + __IM uint32_t RESERVED279[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC227_IN_SEL_CFG; + __IM uint32_t RESERVED280[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC228_IN_SEL_CFG; + __IM uint32_t RESERVED281[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC229_IN_SEL_CFG; + __IM uint32_t RESERVED282[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC230_IN_SEL_CFG; + __IM uint32_t RESERVED283[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC231_IN_SEL_CFG; + __IM uint32_t RESERVED284[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC232_IN_SEL_CFG; + __IM uint32_t RESERVED285[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC233_IN_SEL_CFG; + __IM uint32_t RESERVED286[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC234_IN_SEL_CFG; + __IM uint32_t RESERVED287[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC235_IN_SEL_CFG; + __IM uint32_t RESERVED288[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC236_IN_SEL_CFG; + __IM uint32_t RESERVED289[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC237_IN_SEL_CFG; + __IM uint32_t RESERVED290[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC238_IN_SEL_CFG; + __IM uint32_t RESERVED291[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC239_IN_SEL_CFG; + __IM uint32_t RESERVED292[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC240_IN_SEL_CFG; + __IM uint32_t RESERVED293[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC241_IN_SEL_CFG; + __IM uint32_t RESERVED294[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC242_IN_SEL_CFG; + __IM uint32_t RESERVED295[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC243_IN_SEL_CFG; + __IM uint32_t RESERVED296[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC244_IN_SEL_CFG; + __IM uint32_t RESERVED297[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC245_IN_SEL_CFG; + __IM uint32_t RESERVED298[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC246_IN_SEL_CFG; + __IM uint32_t RESERVED299[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC247_IN_SEL_CFG; + __IM uint32_t RESERVED300[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC248_IN_SEL_CFG; + __IM uint32_t RESERVED301[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC249_IN_SEL_CFG; + __IM uint32_t RESERVED302[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC250_IN_SEL_CFG; + __IM uint32_t RESERVED303[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC251_IN_SEL_CFG; + __IM uint32_t RESERVED304[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC252_IN_SEL_CFG; + __IM uint32_t RESERVED305[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC253_IN_SEL_CFG; + __IM uint32_t RESERVED306[3]; + + union { + __IOM uint32_t reg; /*!< GPIO input function configuration register */ + + struct { + __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: + set this port always high level. s=0x3E: set this port + always low level. */ + __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ + __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass + GPIO. */ + uint32_t : 24; + } bit; + } FUNC254_IN_SEL_CFG; +} GPIO_Type; /*!< Size = 4400 (0x1130) */ + + + +/* =========================================================================================================================== */ +/* ================ GPIO_SD ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Sigma-Delta Modulation (GPIO_SD) + */ + +typedef struct { /*!< GPIO_SD Structure */ + + union { + __IOM uint32_t reg; /*!< Duty Cycle Configure Register of SDM0 */ + + struct { + __IOM uint32_t SD_IN : 8; /*!< This field is used to configure the duty cycle of sigma delta + modulation output. */ + __IOM uint32_t SD_PRESCALE : 8; /*!< This field is used to set a divider value to divide APB clock. */ + uint32_t : 16; + } bit; + } SIGMADELTA0; + __IM uint32_t RESERVED[3]; + + union { + __IOM uint32_t reg; /*!< Duty Cycle Configure Register of SDM1 */ + + struct { + __IOM uint32_t SD_IN : 8; /*!< This field is used to configure the duty cycle of sigma delta + modulation output. */ + __IOM uint32_t SD_PRESCALE : 8; /*!< This field is used to set a divider value to divide APB clock. */ + uint32_t : 16; + } bit; + } SIGMADELTA1; + __IM uint32_t RESERVED1[3]; + + union { + union { + __IOM uint32_t reg; /*!< Duty Cycle Configure Register of SDM2 */ + + struct { + __IOM uint32_t SD_IN : 8; /*!< This field is used to configure the duty cycle of sigma delta + modulation output. */ + __IOM uint32_t SD_PRESCALE : 8; /*!< This field is used to set a divider value to divide APB clock. */ + uint32_t : 16; + } bit; + } SIGMADELTA2; + + union { + __IOM uint32_t reg; /*!< Clock Gating Configure Register */ + + struct { + __IOM uint32_t CLK_EN : 1; /*!< Clock enable bit of configuration registers for sigma delta + modulation. */ + uint32_t : 31; + } bit; + } CLOCK_GATE; + }; + + union { + __IOM uint32_t reg; /*!< MISC Register */ + + struct { + uint32_t : 30; + __IOM uint32_t FUNCTION_CLK_EN : 1; /*!< Clock enable bit of sigma delta modulation. */ + __IOM uint32_t SPI_SWAP : 1; /*!< Reserved. */ + } bit; + } SIGMADELTA_MISC; + __IM uint32_t RESERVED2[2]; + + union { + union { + __IOM uint32_t reg; /*!< Duty Cycle Configure Register of SDM3 */ + + struct { + __IOM uint32_t SD_IN : 8; /*!< This field is used to configure the duty cycle of sigma delta + modulation output. */ + __IOM uint32_t SD_PRESCALE : 8; /*!< This field is used to set a divider value to divide APB clock. */ + uint32_t : 16; + } bit; + } SIGMADELTA3; + + union { + __IOM uint32_t reg; /*!< Glitch Filter Configure Register of Channel0 */ + + struct { + __IOM uint32_t FILTER_CH0_EN : 1; /*!< Glitch Filter channel enable bit. */ + __IOM uint32_t FILTER_CH0_INPUT_IO_NUM : 6;/*!< Glitch Filter input io number. */ + __IOM uint32_t FILTER_CH0_WINDOW_THRES : 6;/*!< Glitch Filter window threshold. */ + __IOM uint32_t FILTER_CH0_WINDOW_WIDTH : 6;/*!< Glitch Filter window width. */ + uint32_t : 13; + } bit; + } GLITCH_FILTER_CH0; + }; + __IM uint32_t RESERVED3[3]; + + union { + union { + __IOM uint32_t reg; /*!< Duty Cycle Configure Register of SDM4 */ + + struct { + __IOM uint32_t SD_IN : 8; /*!< This field is used to configure the duty cycle of sigma delta + modulation output. */ + __IOM uint32_t SD_PRESCALE : 8; /*!< This field is used to set a divider value to divide APB clock. */ + uint32_t : 16; + } bit; + } SIGMADELTA4; + + union { + __IOM uint32_t reg; /*!< Glitch Filter Configure Register of Channel1 */ + + struct { + __IOM uint32_t FILTER_CH0_EN : 1; /*!< Glitch Filter channel enable bit. */ + __IOM uint32_t FILTER_CH0_INPUT_IO_NUM : 6;/*!< Glitch Filter input io number. */ + __IOM uint32_t FILTER_CH0_WINDOW_THRES : 6;/*!< Glitch Filter window threshold. */ + __IOM uint32_t FILTER_CH0_WINDOW_WIDTH : 6;/*!< Glitch Filter window width. */ + uint32_t : 13; + } bit; + } GLITCH_FILTER_CH1; + }; + __IM uint32_t RESERVED4[3]; + + union { + union { + __IOM uint32_t reg; /*!< Duty Cycle Configure Register of SDM5 */ + + struct { + __IOM uint32_t SD_IN : 8; /*!< This field is used to configure the duty cycle of sigma delta + modulation output. */ + __IOM uint32_t SD_PRESCALE : 8; /*!< This field is used to set a divider value to divide APB clock. */ + uint32_t : 16; + } bit; + } SIGMADELTA5; + + union { + __IOM uint32_t reg; /*!< Glitch Filter Configure Register of Channel2 */ + + struct { + __IOM uint32_t FILTER_CH0_EN : 1; /*!< Glitch Filter channel enable bit. */ + __IOM uint32_t FILTER_CH0_INPUT_IO_NUM : 6;/*!< Glitch Filter input io number. */ + __IOM uint32_t FILTER_CH0_WINDOW_THRES : 6;/*!< Glitch Filter window threshold. */ + __IOM uint32_t FILTER_CH0_WINDOW_WIDTH : 6;/*!< Glitch Filter window width. */ + uint32_t : 13; + } bit; + } GLITCH_FILTER_CH2; + }; + __IM uint32_t RESERVED5[3]; + + union { + union { + __IOM uint32_t reg; /*!< Duty Cycle Configure Register of SDM6 */ + + struct { + __IOM uint32_t SD_IN : 8; /*!< This field is used to configure the duty cycle of sigma delta + modulation output. */ + __IOM uint32_t SD_PRESCALE : 8; /*!< This field is used to set a divider value to divide APB clock. */ + uint32_t : 16; + } bit; + } SIGMADELTA6; + + union { + __IOM uint32_t reg; /*!< Glitch Filter Configure Register of Channel3 */ + + struct { + __IOM uint32_t FILTER_CH0_EN : 1; /*!< Glitch Filter channel enable bit. */ + __IOM uint32_t FILTER_CH0_INPUT_IO_NUM : 6;/*!< Glitch Filter input io number. */ + __IOM uint32_t FILTER_CH0_WINDOW_THRES : 6;/*!< Glitch Filter window threshold. */ + __IOM uint32_t FILTER_CH0_WINDOW_WIDTH : 6;/*!< Glitch Filter window width. */ + uint32_t : 13; + } bit; + } GLITCH_FILTER_CH3; + + union { + __IOM uint32_t reg; /*!< Etm Config register of Channel0 */ + + struct { + __IOM uint32_t ETM_CH0_EVENT_SEL : 6; /*!< Etm event channel select gpio. */ + uint32_t : 1; + __IOM uint32_t ETM_CH0_EVENT_EN : 1; /*!< Etm event send enable bit. */ + uint32_t : 24; + } bit; + } ETM_EVENT_CH0_CFG; + }; + __IM uint32_t RESERVED6[3]; + + union { + union { + __IOM uint32_t reg; /*!< Duty Cycle Configure Register of SDM7 */ + + struct { + __IOM uint32_t SD_IN : 8; /*!< This field is used to configure the duty cycle of sigma delta + modulation output. */ + __IOM uint32_t SD_PRESCALE : 8; /*!< This field is used to set a divider value to divide APB clock. */ + uint32_t : 16; + } bit; + } SIGMADELTA7; + + union { + __IOM uint32_t reg; /*!< Glitch Filter Configure Register of Channel4 */ + + struct { + __IOM uint32_t FILTER_CH0_EN : 1; /*!< Glitch Filter channel enable bit. */ + __IOM uint32_t FILTER_CH0_INPUT_IO_NUM : 6;/*!< Glitch Filter input io number. */ + __IOM uint32_t FILTER_CH0_WINDOW_THRES : 6;/*!< Glitch Filter window threshold. */ + __IOM uint32_t FILTER_CH0_WINDOW_WIDTH : 6;/*!< Glitch Filter window width. */ + uint32_t : 13; + } bit; + } GLITCH_FILTER_CH4; + + union { + __IOM uint32_t reg; /*!< Etm Config register of Channel1 */ + + struct { + __IOM uint32_t ETM_CH0_EVENT_SEL : 6; /*!< Etm event channel select gpio. */ + uint32_t : 1; + __IOM uint32_t ETM_CH0_EVENT_EN : 1; /*!< Etm event send enable bit. */ + uint32_t : 24; + } bit; + } ETM_EVENT_CH1_CFG; + }; + __IM uint32_t RESERVED7[3]; + + union { + union { + __IOM uint32_t reg; /*!< Glitch Filter Configure Register of Channel5 */ + + struct { + __IOM uint32_t FILTER_CH0_EN : 1; /*!< Glitch Filter channel enable bit. */ + __IOM uint32_t FILTER_CH0_INPUT_IO_NUM : 6;/*!< Glitch Filter input io number. */ + __IOM uint32_t FILTER_CH0_WINDOW_THRES : 6;/*!< Glitch Filter window threshold. */ + __IOM uint32_t FILTER_CH0_WINDOW_WIDTH : 6;/*!< Glitch Filter window width. */ + uint32_t : 13; + } bit; + } GLITCH_FILTER_CH5; + + union { + __IOM uint32_t reg; /*!< Etm Config register of Channel2 */ + + struct { + __IOM uint32_t ETM_CH0_EVENT_SEL : 6; /*!< Etm event channel select gpio. */ + uint32_t : 1; + __IOM uint32_t ETM_CH0_EVENT_EN : 1; /*!< Etm event send enable bit. */ + uint32_t : 24; + } bit; + } ETM_EVENT_CH2_CFG; + }; + __IM uint32_t RESERVED8[3]; + + union { + union { + __IOM uint32_t reg; /*!< Glitch Filter Configure Register of Channel6 */ + + struct { + __IOM uint32_t FILTER_CH0_EN : 1; /*!< Glitch Filter channel enable bit. */ + __IOM uint32_t FILTER_CH0_INPUT_IO_NUM : 6;/*!< Glitch Filter input io number. */ + __IOM uint32_t FILTER_CH0_WINDOW_THRES : 6;/*!< Glitch Filter window threshold. */ + __IOM uint32_t FILTER_CH0_WINDOW_WIDTH : 6;/*!< Glitch Filter window width. */ + uint32_t : 13; + } bit; + } GLITCH_FILTER_CH6; + + union { + __IOM uint32_t reg; /*!< Etm Config register of Channel3 */ + + struct { + __IOM uint32_t ETM_CH0_EVENT_SEL : 6; /*!< Etm event channel select gpio. */ + uint32_t : 1; + __IOM uint32_t ETM_CH0_EVENT_EN : 1; /*!< Etm event send enable bit. */ + uint32_t : 24; + } bit; + } ETM_EVENT_CH3_CFG; + }; + __IM uint32_t RESERVED9[3]; + + union { + union { + __IOM uint32_t reg; /*!< Glitch Filter Configure Register of Channel7 */ + + struct { + __IOM uint32_t FILTER_CH0_EN : 1; /*!< Glitch Filter channel enable bit. */ + __IOM uint32_t FILTER_CH0_INPUT_IO_NUM : 6;/*!< Glitch Filter input io number. */ + __IOM uint32_t FILTER_CH0_WINDOW_THRES : 6;/*!< Glitch Filter window threshold. */ + __IOM uint32_t FILTER_CH0_WINDOW_WIDTH : 6;/*!< Glitch Filter window width. */ + uint32_t : 13; + } bit; + } GLITCH_FILTER_CH7; + + union { + __IOM uint32_t reg; /*!< Etm Config register of Channel4 */ + + struct { + __IOM uint32_t ETM_CH0_EVENT_SEL : 6; /*!< Etm event channel select gpio. */ + uint32_t : 1; + __IOM uint32_t ETM_CH0_EVENT_EN : 1; /*!< Etm event send enable bit. */ + uint32_t : 24; + } bit; + } ETM_EVENT_CH4_CFG; + + union { + __IOM uint32_t reg; /*!< Etm Configure Register to decide which GPIO been chosen */ + + struct { + __IOM uint32_t ETM_TASK_GPIO0_EN : 1; /*!< Enable bit of GPIO response etm task. */ + __IOM uint32_t ETM_TASK_GPIO0_SEL : 3; /*!< GPIO choose a etm task channel. */ + uint32_t : 4; + __IOM uint32_t ETM_TASK_GPIO1_EN : 1; /*!< Enable bit of GPIO response etm task. */ + __IOM uint32_t ETM_TASK_GPIO1_SEL : 3; /*!< GPIO choose a etm task channel. */ + uint32_t : 4; + __IOM uint32_t ETM_TASK_GPIO2_EN : 1; /*!< Enable bit of GPIO response etm task. */ + __IOM uint32_t ETM_TASK_GPIO2_SEL : 3; /*!< GPIO choose a etm task channel. */ + uint32_t : 4; + __IOM uint32_t ETM_TASK_GPIO3_EN : 1; /*!< Enable bit of GPIO response etm task. */ + __IOM uint32_t ETM_TASK_GPIO3_SEL : 3; /*!< GPIO choose a etm task channel. */ + uint32_t : 4; + } bit; + } ETM_TASK_P0_CFG; + }; + + union { + __IOM uint32_t reg; /*!< Etm Configure Register to decide which GPIO been chosen */ + + struct { + __IOM uint32_t ETM_TASK_GPIO4_EN : 1; /*!< Enable bit of GPIO response etm task. */ + __IOM uint32_t ETM_TASK_GPIO4_SEL : 3; /*!< GPIO choose a etm task channel. */ + uint32_t : 4; + __IOM uint32_t ETM_TASK_GPIO5_EN : 1; /*!< Enable bit of GPIO response etm task. */ + __IOM uint32_t ETM_TASK_GPIO5_SEL : 3; /*!< GPIO choose a etm task channel. */ + uint32_t : 4; + __IOM uint32_t ETM_TASK_GPIO6_EN : 1; /*!< Enable bit of GPIO response etm task. */ + __IOM uint32_t ETM_TASK_GPIO6_SEL : 3; /*!< GPIO choose a etm task channel. */ + uint32_t : 4; + __IOM uint32_t ETM_TASK_GPIO7_EN : 1; /*!< Enable bit of GPIO response etm task. */ + __IOM uint32_t ETM_TASK_GPIO7_SEL : 3; /*!< GPIO choose a etm task channel. */ + uint32_t : 4; + } bit; + } ETM_TASK_P1_CFG; + + union { + __IOM uint32_t reg; /*!< Etm Configure Register to decide which GPIO been chosen */ + + struct { + __IOM uint32_t ETM_TASK_GPIO8_EN : 1; /*!< Enable bit of GPIO response etm task. */ + __IOM uint32_t ETM_TASK_GPIO8_SEL : 3; /*!< GPIO choose a etm task channel. */ + uint32_t : 4; + __IOM uint32_t ETM_TASK_GPIO9_EN : 1; /*!< Enable bit of GPIO response etm task. */ + __IOM uint32_t ETM_TASK_GPIO9_SEL : 3; /*!< GPIO choose a etm task channel. */ + uint32_t : 4; + __IOM uint32_t ETM_TASK_GPIO10_EN : 1; /*!< Enable bit of GPIO response etm task. */ + __IOM uint32_t ETM_TASK_GPIO10_SEL : 3; /*!< GPIO choose a etm task channel. */ + uint32_t : 4; + __IOM uint32_t ETM_TASK_GPIO11_EN : 1; /*!< Enable bit of GPIO response etm task. */ + __IOM uint32_t ETM_TASK_GPIO11_SEL : 3; /*!< GPIO choose a etm task channel. */ + uint32_t : 4; + } bit; + } ETM_TASK_P2_CFG; + + union { + __IOM uint32_t reg; /*!< Etm Configure Register to decide which GPIO been chosen */ + + struct { + __IOM uint32_t ETM_TASK_GPIO12_EN : 1; /*!< Enable bit of GPIO response etm task. */ + __IOM uint32_t ETM_TASK_GPIO12_SEL : 3; /*!< GPIO choose a etm task channel. */ + uint32_t : 4; + __IOM uint32_t ETM_TASK_GPIO13_EN : 1; /*!< Enable bit of GPIO response etm task. */ + __IOM uint32_t ETM_TASK_GPIO13_SEL : 3; /*!< GPIO choose a etm task channel. */ + uint32_t : 4; + __IOM uint32_t ETM_TASK_GPIO14_EN : 1; /*!< Enable bit of GPIO response etm task. */ + __IOM uint32_t ETM_TASK_GPIO14_SEL : 3; /*!< GPIO choose a etm task channel. */ + uint32_t : 4; + __IOM uint32_t ETM_TASK_GPIO15_EN : 1; /*!< Enable bit of GPIO response etm task. */ + __IOM uint32_t ETM_TASK_GPIO15_SEL : 3; /*!< GPIO choose a etm task channel. */ + uint32_t : 4; + } bit; + } ETM_TASK_P3_CFG; + + union { + union { + __IOM uint32_t reg; /*!< Etm Config register of Channel5 */ + + struct { + __IOM uint32_t ETM_CH0_EVENT_SEL : 6; /*!< Etm event channel select gpio. */ + uint32_t : 1; + __IOM uint32_t ETM_CH0_EVENT_EN : 1; /*!< Etm event send enable bit. */ + uint32_t : 24; + } bit; + } ETM_EVENT_CH5_CFG; + + union { + __IOM uint32_t reg; /*!< Etm Configure Register to decide which GPIO been chosen */ + + struct { + __IOM uint32_t ETM_TASK_GPIO16_EN : 1; /*!< Enable bit of GPIO response etm task. */ + __IOM uint32_t ETM_TASK_GPIO16_SEL : 3; /*!< GPIO choose a etm task channel. */ + uint32_t : 4; + __IOM uint32_t ETM_TASK_GPIO17_EN : 1; /*!< Enable bit of GPIO response etm task. */ + __IOM uint32_t ETM_TASK_GPIO17_SEL : 3; /*!< GPIO choose a etm task channel. */ + uint32_t : 4; + __IOM uint32_t ETM_TASK_GPIO18_EN : 1; /*!< Enable bit of GPIO response etm task. */ + __IOM uint32_t ETM_TASK_GPIO18_SEL : 3; /*!< GPIO choose a etm task channel. */ + uint32_t : 4; + __IOM uint32_t ETM_TASK_GPIO19_EN : 1; /*!< Enable bit of GPIO response etm task. */ + __IOM uint32_t ETM_TASK_GPIO19_SEL : 3; /*!< GPIO choose a etm task channel. */ + uint32_t : 4; + } bit; + } ETM_TASK_P4_CFG; + }; + + union { + __IOM uint32_t reg; /*!< Etm Configure Register to decide which GPIO been chosen */ + + struct { + __IOM uint32_t ETM_TASK_GPIO20_EN : 1; /*!< Enable bit of GPIO response etm task. */ + __IOM uint32_t ETM_TASK_GPIO20_SEL : 3; /*!< GPIO choose a etm task channel. */ + uint32_t : 4; + __IOM uint32_t ETM_TASK_GPIO21_EN : 1; /*!< Enable bit of GPIO response etm task. */ + __IOM uint32_t ETM_TASK_GPIO21_SEL : 3; /*!< GPIO choose a etm task channel. */ + uint32_t : 4; + __IOM uint32_t ETM_TASK_GPIO22_EN : 1; /*!< Enable bit of GPIO response etm task. */ + __IOM uint32_t ETM_TASK_GPIO22_SEL : 3; /*!< GPIO choose a etm task channel. */ + uint32_t : 4; + __IOM uint32_t ETM_TASK_GPIO23_EN : 1; /*!< Enable bit of GPIO response etm task. */ + __IOM uint32_t ETM_TASK_GPIO23_SEL : 3; /*!< GPIO choose a etm task channel. */ + uint32_t : 4; + } bit; + } ETM_TASK_P5_CFG; + + union { + __IOM uint32_t reg; /*!< Etm Configure Register to decide which GPIO been chosen */ + + struct { + __IOM uint32_t ETM_TASK_GPIO24_EN : 1; /*!< Enable bit of GPIO response etm task. */ + __IOM uint32_t ETM_TASK_GPIO24_SEL : 3; /*!< GPIO choose a etm task channel. */ + uint32_t : 4; + __IOM uint32_t ETM_TASK_GPIO25_EN : 1; /*!< Enable bit of GPIO response etm task. */ + __IOM uint32_t ETM_TASK_GPIO25_SEL : 3; /*!< GPIO choose a etm task channel. */ + uint32_t : 4; + __IOM uint32_t ETM_TASK_GPIO26_EN : 1; /*!< Enable bit of GPIO response etm task. */ + __IOM uint32_t ETM_TASK_GPIO26_SEL : 3; /*!< GPIO choose a etm task channel. */ + uint32_t : 4; + __IOM uint32_t ETM_TASK_GPIO27_EN : 1; /*!< Enable bit of GPIO response etm task. */ + __IOM uint32_t ETM_TASK_GPIO27_SEL : 3; /*!< GPIO choose a etm task channel. */ + uint32_t : 4; + } bit; + } ETM_TASK_P6_CFG; + + union { + __IOM uint32_t reg; /*!< Etm Configure Register to decide which GPIO been chosen */ + + struct { + __IOM uint32_t ETM_TASK_GPIO28_EN : 1; /*!< Enable bit of GPIO response etm task. */ + __IOM uint32_t ETM_TASK_GPIO28_SEL : 3; /*!< GPIO choose a etm task channel. */ + uint32_t : 4; + __IOM uint32_t ETM_TASK_GPIO29_EN : 1; /*!< Enable bit of GPIO response etm task. */ + __IOM uint32_t ETM_TASK_GPIO29_SEL : 3; /*!< GPIO choose a etm task channel. */ + uint32_t : 4; + __IOM uint32_t ETM_TASK_GPIO30_EN : 1; /*!< Enable bit of GPIO response etm task. */ + __IOM uint32_t ETM_TASK_GPIO30_SEL : 3; /*!< GPIO choose a etm task channel. */ + uint32_t : 4; + __IOM uint32_t ETM_TASK_GPIO31_EN : 1; /*!< Enable bit of GPIO response etm task. */ + __IOM uint32_t ETM_TASK_GPIO31_SEL : 3; /*!< GPIO choose a etm task channel. */ + uint32_t : 4; + } bit; + } ETM_TASK_P7_CFG; + + union { + union { + __IOM uint32_t reg; /*!< Etm Config register of Channel6 */ + + struct { + __IOM uint32_t ETM_CH0_EVENT_SEL : 6; /*!< Etm event channel select gpio. */ + uint32_t : 1; + __IOM uint32_t ETM_CH0_EVENT_EN : 1; /*!< Etm event send enable bit. */ + uint32_t : 24; + } bit; + } ETM_EVENT_CH6_CFG; + + union { + __IOM uint32_t reg; /*!< Etm Configure Register to decide which GPIO been chosen */ + + struct { + __IOM uint32_t ETM_TASK_GPIO32_EN : 1; /*!< Enable bit of GPIO response etm task. */ + __IOM uint32_t ETM_TASK_GPIO32_SEL : 3; /*!< GPIO choose a etm task channel. */ + uint32_t : 4; + __IOM uint32_t ETM_TASK_GPIO33_EN : 1; /*!< Enable bit of GPIO response etm task. */ + __IOM uint32_t ETM_TASK_GPIO33_SEL : 3; /*!< GPIO choose a etm task channel. */ + uint32_t : 4; + __IOM uint32_t ETM_TASK_GPIO34_EN : 1; /*!< Enable bit of GPIO response etm task. */ + __IOM uint32_t ETM_TASK_GPIO34_SEL : 3; /*!< GPIO choose a etm task channel. */ + uint32_t : 4; + __IOM uint32_t ETM_TASK_GPIO35_EN : 1; /*!< Enable bit of GPIO response etm task. */ + __IOM uint32_t ETM_TASK_GPIO35_SEL : 3; /*!< GPIO choose a etm task channel. */ + uint32_t : 4; + } bit; + } ETM_TASK_P8_CFG; + }; + + union { + __IOM uint32_t reg; /*!< Etm Configure Register to decide which GPIO been chosen */ + + struct { + __IOM uint32_t ETM_TASK_GPIO36_EN : 1; /*!< Enable bit of GPIO response etm task. */ + __IOM uint32_t ETM_TASK_GPIO36_SEL : 3; /*!< GPIO choose a etm task channel. */ + uint32_t : 4; + __IOM uint32_t ETM_TASK_GPIO37_EN : 1; /*!< Enable bit of GPIO response etm task. */ + __IOM uint32_t ETM_TASK_GPIO37_SEL : 3; /*!< GPIO choose a etm task channel. */ + uint32_t : 4; + __IOM uint32_t ETM_TASK_GPIO38_EN : 1; /*!< Enable bit of GPIO response etm task. */ + __IOM uint32_t ETM_TASK_GPIO38_SEL : 3; /*!< GPIO choose a etm task channel. */ + uint32_t : 4; + __IOM uint32_t ETM_TASK_GPIO39_EN : 1; /*!< Enable bit of GPIO response etm task. */ + __IOM uint32_t ETM_TASK_GPIO39_SEL : 3; /*!< GPIO choose a etm task channel. */ + uint32_t : 4; + } bit; + } ETM_TASK_P9_CFG; + + union { + __IOM uint32_t reg; /*!< Etm Configure Register to decide which GPIO been chosen */ + + struct { + __IOM uint32_t ETM_TASK_GPIO40_EN : 1; /*!< Enable bit of GPIO response etm task. */ + __IOM uint32_t ETM_TASK_GPIO40_SEL : 3; /*!< GPIO choose a etm task channel. */ + uint32_t : 4; + __IOM uint32_t ETM_TASK_GPIO41_EN : 1; /*!< Enable bit of GPIO response etm task. */ + __IOM uint32_t ETM_TASK_GPIO41_SEL : 3; /*!< GPIO choose a etm task channel. */ + uint32_t : 4; + __IOM uint32_t ETM_TASK_GPIO42_EN : 1; /*!< Enable bit of GPIO response etm task. */ + __IOM uint32_t ETM_TASK_GPIO42_SEL : 3; /*!< GPIO choose a etm task channel. */ + uint32_t : 4; + __IOM uint32_t ETM_TASK_GPIO43_EN : 1; /*!< Enable bit of GPIO response etm task. */ + __IOM uint32_t ETM_TASK_GPIO43_SEL : 3; /*!< GPIO choose a etm task channel. */ + uint32_t : 4; + } bit; + } ETM_TASK_P10_CFG; + + union { + __IOM uint32_t reg; /*!< Etm Configure Register to decide which GPIO been chosen */ + + struct { + __IOM uint32_t ETM_TASK_GPIO44_EN : 1; /*!< Enable bit of GPIO response etm task. */ + __IOM uint32_t ETM_TASK_GPIO44_SEL : 3; /*!< GPIO choose a etm task channel. */ + uint32_t : 4; + __IOM uint32_t ETM_TASK_GPIO45_EN : 1; /*!< Enable bit of GPIO response etm task. */ + __IOM uint32_t ETM_TASK_GPIO45_SEL : 3; /*!< GPIO choose a etm task channel. */ + uint32_t : 4; + __IOM uint32_t ETM_TASK_GPIO46_EN : 1; /*!< Enable bit of GPIO response etm task. */ + __IOM uint32_t ETM_TASK_GPIO46_SEL : 3; /*!< GPIO choose a etm task channel. */ + uint32_t : 4; + __IOM uint32_t ETM_TASK_GPIO47_EN : 1; /*!< Enable bit of GPIO response etm task. */ + __IOM uint32_t ETM_TASK_GPIO47_SEL : 3; /*!< GPIO choose a etm task channel. */ + uint32_t : 4; + } bit; + } ETM_TASK_P11_CFG; + + union { + union { + __IOM uint32_t reg; /*!< Etm Config register of Channel7 */ + + struct { + __IOM uint32_t ETM_CH0_EVENT_SEL : 6; /*!< Etm event channel select gpio. */ + uint32_t : 1; + __IOM uint32_t ETM_CH0_EVENT_EN : 1; /*!< Etm event send enable bit. */ + uint32_t : 24; + } bit; + } ETM_EVENT_CH7_CFG; + + union { + __IOM uint32_t reg; /*!< Etm Configure Register to decide which GPIO been chosen */ + + struct { + __IOM uint32_t ETM_TASK_GPIO48_EN : 1; /*!< Enable bit of GPIO response etm task. */ + __IOM uint32_t ETM_TASK_GPIO48_SEL : 3; /*!< GPIO choose a etm task channel. */ + uint32_t : 4; + __IOM uint32_t ETM_TASK_GPIO49_EN : 1; /*!< Enable bit of GPIO response etm task. */ + __IOM uint32_t ETM_TASK_GPIO49_SEL : 3; /*!< GPIO choose a etm task channel. */ + uint32_t : 4; + __IOM uint32_t ETM_TASK_GPIO50_EN : 1; /*!< Enable bit of GPIO response etm task. */ + __IOM uint32_t ETM_TASK_GPIO50_SEL : 3; /*!< GPIO choose a etm task channel. */ + uint32_t : 4; + __IOM uint32_t ETM_TASK_GPIO51_EN : 1; /*!< Enable bit of GPIO response etm task. */ + __IOM uint32_t ETM_TASK_GPIO51_SEL : 3; /*!< GPIO choose a etm task channel. */ + uint32_t : 4; + } bit; + } ETM_TASK_P12_CFG; + }; + + union { + __IOM uint32_t reg; /*!< Etm Configure Register to decide which GPIO been chosen */ + + struct { + __IOM uint32_t ETM_TASK_GPIO52_EN : 1; /*!< Enable bit of GPIO response etm task. */ + __IOM uint32_t ETM_TASK_GPIO52_SEL : 3; /*!< GPIO choose a etm task channel. */ + uint32_t : 4; + __IOM uint32_t ETM_TASK_GPIO53_EN : 1; /*!< Enable bit of GPIO response etm task. */ + __IOM uint32_t ETM_TASK_GPIO53_SEL : 3; /*!< GPIO choose a etm task channel. */ + uint32_t : 4; + __IOM uint32_t ETM_TASK_GPIO54_EN : 1; /*!< Enable bit of GPIO response etm task. */ + __IOM uint32_t ETM_TASK_GPIO54_SEL : 3; /*!< GPIO choose a etm task channel. */ + uint32_t : 12; + } bit; + } ETM_TASK_P13_CFG; + __IM uint32_t RESERVED10[9]; + + union { + __IOM uint32_t reg; /*!< Version Control Register */ + + struct { + __IOM uint32_t GPIO_SD_DATE : 28; /*!< Version control register. */ + uint32_t : 4; + } bit; + } VERSION; +} GPIO_SD_Type; /*!< Size = 256 (0x100) */ + + + +/* =========================================================================================================================== */ +/* ================ H264 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief H264 Encoder (Core) (H264) + */ + +typedef struct { /*!< H264 Structure */ + + union { + __IOM uint32_t reg; /*!< H264 system level control register. */ + + struct { + __OM uint32_t FRAME_START : 1; /*!< Configures whether or not to start encoding one frame.\\0: Invalid. + No effect\\1: Start encoding one frame */ + __OM uint32_t DMA_MOVE_START : 1; /*!< Configures whether or not to start moving reference data from + external mem.\\0: Invalid. No effect\\1: H264 start moving + two MB lines of reference frame from external mem to internal + mem */ + __IOM uint32_t FRAME_MODE : 1; /*!< Configures H264 running mode. When field H264_DUAL_STREAM_MODE + is set to 1, this field must be set to 1 too.\\0: GOP mode. + Before every GOP first frame start, need reconfig reference + frame DMA\\1: Frame mode. Before every frame start, need + reconfig reference frame DMA */ + __OM uint32_t SYS_RST_PULSE : 1; /*!< Configures whether or not to reset H264 ip.\\0: Invalid. No + effect\\1: Reset H264 ip */ + uint32_t : 28; + } bit; + } SYS_CTRL; + + union { + __IOM uint32_t reg; /*!< GOP related configuration register. */ + + struct { + __IOM uint32_t DUAL_STREAM_MODE : 1; /*!< Configures whether or not to enable dual stream mode. When this + field is set to 1, H264_FRAME_MODE field must be set to + 1 too.\\0: Normal mode\\1: Dual stream mode */ + __IOM uint32_t GOP_NUM : 8; /*!< Configures the frame number of one GOP.\\0: The frame number + of one GOP is infinite\\Others: Actual frame number of + one GOP */ + uint32_t : 23; + } bit; + } GOP_CONF; + + union { + __IOM uint32_t reg; /*!< Video A horizontal and vertical MB resolution register. */ + + struct { + __IOM uint32_t A_SYS_TOTAL_MB_Y : 7; /*!< Configures video A vertical MB resolution. */ + __IOM uint32_t A_SYS_TOTAL_MB_X : 7; /*!< Configures video A horizontal MB resolution. */ + uint32_t : 18; + } bit; + } A_SYS_MB_RES; + + union { + __IOM uint32_t reg; /*!< Video A system level configuration register. */ + + struct { + __IOM uint32_t A_DB_TMP_READY_TRIGGER_MB_NUM : 7;/*!< Configures when to trigger video A H264_DB_TMP_READY_INT. When + the (MB number of written db temp+1) is greater than this + filed in first MB line, trigger H264_DB_TMP_READY_INT. + Min is 3. */ + __IOM uint32_t A_REC_READY_TRIGGER_MB_LINES : 7;/*!< Configures when to trigger video A H264_REC_READY_INT. When + the MB line number of generated reconstruct pixel is greater + than this filed, trigger H264_REC_READY_INT. Min is 4. */ + __IOM uint32_t A_INTRA_COST_CMP_OFFSET : 16;/*!< Configures video A intra cost offset when I MB compared with + P MB. */ + uint32_t : 2; + } bit; + } A_SYS_CONF; + + union { + __IOM uint32_t reg; /*!< Video A luma and chroma MB decimate score Register. */ + + struct { + __IOM uint32_t A_C_DECI_SCORE : 10; /*!< Configures video A chroma MB decimate score. When chroma score + is smaller than it, chroma decimate will be enable. */ + __IOM uint32_t A_L_DECI_SCORE : 10; /*!< Configures video A luma MB decimate score. When luma score is + smaller than it, luma decimate will be enable. */ + uint32_t : 12; + } bit; + } A_DECI_SCORE; + + union { + __IOM uint32_t reg; /*!< Video A luma and chroma MB decimate score offset Register. */ + + struct { + __IOM uint32_t A_I16X16_DECI_SCORE_OFFSET : 6;/*!< Configures video A i16x16 MB decimate score offset. This offset + will be added to i16x16 MB score. */ + __IOM uint32_t A_I_CHROMA_DECI_SCORE_OFFSET : 6;/*!< Configures video A I chroma MB decimate score offset. This offset + will be added to I chroma MB score. */ + __IOM uint32_t A_P16X16_DECI_SCORE_OFFSET : 6;/*!< Configures video A p16x16 MB decimate score offset. This offset + will be added to p16x16 MB score. */ + __IOM uint32_t A_P_CHROMA_DECI_SCORE_OFFSET : 6;/*!< Configures video A p chroma MB decimate score offset. This offset + will be added to p chroma MB score. */ + uint32_t : 8; + } bit; + } A_DECI_SCORE_OFFSET; + + union { + __IOM uint32_t reg; /*!< Video A rate control configuration register0. */ + + struct { + __IOM uint32_t A_QP : 6; /*!< Configures video A frame level initial luma QP value. */ + __IOM uint32_t A_RATE_CTRL_U : 16; /*!< Configures video A parameter U value. U = int((float) u << 8). */ + __IOM uint32_t A_MB_RATE_CTRL_EN : 1; /*!< Configures video A whether or not to open macro block rate ctrl.\\1:Open + the macro block rate ctrl\\1:Close the macro block rate + ctrl. */ + uint32_t : 9; + } bit; + } A_RC_CONF0; + + union { + __IOM uint32_t reg; /*!< Video A rate control configuration register1. */ + + struct { + __IOM uint32_t A_CHROMA_DC_QP_DELTA : 3; /*!< Configures video A chroma DC QP offset based on Chroma QP. Chroma + DC QP = Chroma QP(after map) + reg_chroma_dc_qp_delta. */ + __IOM uint32_t A_CHROMA_QP_DELTA : 4; /*!< Configures video A chroma QP offset based on luma QP. Chroma + QP(before map) = Luma QP + reg_chroma_qp_delta. */ + __IOM uint32_t A_QP_MIN : 6; /*!< Configures video A allowed luma QP min value. */ + __IOM uint32_t A_QP_MAX : 6; /*!< Configures video A allowed luma QP max value. */ + __IOM uint32_t A_MAD_FRAME_PRED : 12; /*!< Configures vdieo A frame level predicted MB MAD value. */ + uint32_t : 1; + } bit; + } A_RC_CONF1; + + union { + __IOM uint32_t reg; /*!< Video A Deblocking bypass register */ + + struct { + __IOM uint32_t A_BYPASS_DB_FILTER : 1; /*!< Configures whether or not to bypass video A deblcoking filter. + \\0: Open the deblock filter\\1: Close the deblock filter */ + uint32_t : 31; + } bit; + } A_DB_BYPASS; + + union { + __IOM uint32_t reg; /*!< Video A H264 ROI region0 range configure register. */ + + struct { + __IOM uint32_t X : 7; /*!< Configures the horizontal start macroblocks of region 0 in Video + A. */ + __IOM uint32_t Y : 7; /*!< Configures the vertical start macroblocks of region 0 in Video + A. */ + __IOM uint32_t X_LEN : 7; /*!< Configures the number of macroblocks in horizontal direction + of the region 0 in Video A. */ + __IOM uint32_t Y_LEN : 7; /*!< Configures the number of macroblocks in vertical direction of + the region 0 in Video A. */ + __IOM uint32_t EN : 1; /*!< Configures whether or not to open Video A ROI of region 0 .\\0:Close + ROI\\1:Open ROI. */ + uint32_t : 3; + } bit; + } A_ROI_REGION0; + + union { + __IOM uint32_t reg; /*!< Video A H264 ROI region1 range configure register. */ + + struct { + __IOM uint32_t X : 7; /*!< Configures the horizontal start macroblocks of region 1 in Video + A. */ + __IOM uint32_t Y : 7; /*!< Configures the vertical start macroblocks of region 1 in Video + A. */ + __IOM uint32_t X_LEN : 7; /*!< Configures the number of macroblocks in horizontal direction + of the region 1 in Video A. */ + __IOM uint32_t Y_LEN : 7; /*!< Configures the number of macroblocks in vertical direction of + the region 1 in Video A. */ + __IOM uint32_t EN : 1; /*!< Configures whether or not to open Video A ROI of region 1 .\\0:Close + ROI\\1:Open ROI. */ + uint32_t : 3; + } bit; + } A_ROI_REGION1; + + union { + __IOM uint32_t reg; /*!< Video A H264 ROI region2 range configure register. */ + + struct { + __IOM uint32_t X : 7; /*!< Configures the horizontal start macroblocks of region 2 in Video + A. */ + __IOM uint32_t Y : 7; /*!< Configures the vertical start macroblocks of region 2 in Video + A. */ + __IOM uint32_t X_LEN : 7; /*!< Configures the number of macroblocks in horizontal direction + of the region 2 in Video A. */ + __IOM uint32_t Y_LEN : 7; /*!< Configures the number of macroblocks in vertical direction of + the region 2 in Video A. */ + __IOM uint32_t EN : 1; /*!< Configures whether or not to open Video A ROI of region 2 .\\0:Close + ROI\\1:Open ROI. */ + uint32_t : 3; + } bit; + } A_ROI_REGION2; + + union { + __IOM uint32_t reg; /*!< Video A H264 ROI region3 range configure register. */ + + struct { + __IOM uint32_t X : 7; /*!< Configures the horizontal start macroblocks of region 3 in Video + A. */ + __IOM uint32_t Y : 7; /*!< Configures the vertical start macroblocks of region 3 in Video + A. */ + __IOM uint32_t X_LEN : 7; /*!< Configures the number of macroblocks in horizontal direction + of the region 3 in video A. */ + __IOM uint32_t Y_LEN : 7; /*!< Configures the number of macroblocks in vertical direction of + the region 3 in video A. */ + __IOM uint32_t EN : 1; /*!< Configures whether or not to open Video A ROI of region 3 .\\0:Close + ROI\\1:Open ROI. */ + uint32_t : 3; + } bit; + } A_ROI_REGION3; + + union { + __IOM uint32_t reg; /*!< Video A H264 ROI region4 range configure register. */ + + struct { + __IOM uint32_t X : 7; /*!< Configures the horizontal start macroblocks of region 4 in Video + A. */ + __IOM uint32_t Y : 7; /*!< Configures the vertical start macroblocks of region 4 in Video + A. */ + __IOM uint32_t X_LEN : 7; /*!< Configures the number of macroblocks in horizontal direction + of the region 4 in video A. */ + __IOM uint32_t Y_LEN : 7; /*!< Configures the number of macroblocks in vertical direction of + the region 4 in video A. */ + __IOM uint32_t EN : 1; /*!< Configures whether or not to open Video A ROI of region 4 .\\0:Close + ROI\\1:Open ROI. */ + uint32_t : 3; + } bit; + } A_ROI_REGION4; + + union { + __IOM uint32_t reg; /*!< Video A H264 ROI region5 range configure register. */ + + struct { + __IOM uint32_t X : 7; /*!< Configures the horizontial start macroblocks of region 5 video + A. */ + __IOM uint32_t Y : 7; /*!< Configures the vertical start macroblocks of region 5 video + A. */ + __IOM uint32_t X_LEN : 7; /*!< Configures the number of macroblocks in horizontal direction + of the region 5 video A. */ + __IOM uint32_t Y_LEN : 7; /*!< Configures the number of macroblocks in vertical direction of + the region 5 in video A. */ + __IOM uint32_t EN : 1; /*!< Configures whether or not to open Video A ROI of region 5 .\\0:Close + ROI\\1:Open ROI. */ + uint32_t : 3; + } bit; + } A_ROI_REGION5; + + union { + __IOM uint32_t reg; /*!< Video A H264 ROI region6 range configure register. */ + + struct { + __IOM uint32_t X : 7; /*!< Configures the horizontial start macroblocks of region 6 video + A. */ + __IOM uint32_t Y : 7; /*!< Configures the vertical start macroblocks of region 6 in video + A. */ + __IOM uint32_t X_LEN : 7; /*!< Configures the number of macroblocks in horizontal direction + of the region 6 in video A. */ + __IOM uint32_t Y_LEN : 7; /*!< Configures the number of macroblocks in vertical direction of + the region 6 in video A. */ + __IOM uint32_t EN : 1; /*!< Configures whether or not to open Video A ROI of region 6 .\\0:Close + ROI\\1:Open ROI. */ + uint32_t : 3; + } bit; + } A_ROI_REGION6; + + union { + __IOM uint32_t reg; /*!< Video A H264 ROI region7 range configure register. */ + + struct { + __IOM uint32_t X : 7; /*!< Configures the horizontal start macroblocks of region 7 in video + A. */ + __IOM uint32_t Y : 7; /*!< Configures the vertical start macroblocks of region 7 in video + A. */ + __IOM uint32_t X_LEN : 7; /*!< Configures the number of macroblocks in horizontal direction + of the region 7 in video A. */ + __IOM uint32_t Y_LEN : 7; /*!< Configures the number of macroblocks in vertical direction of + the region 7 in video A. */ + __IOM uint32_t EN : 1; /*!< Configures whether or not to open Video A ROI of region 7 .\\0:Close + ROI\\1:Open ROI. */ + uint32_t : 3; + } bit; + } A_ROI_REGION7; + + union { + __IOM uint32_t reg; /*!< Video A H264 ROI region0, region1,region2,region3 QP register. */ + + struct { + __IOM uint32_t A_ROI_REGION0_QP : 7; /*!< Configure H264 ROI region0 qp in video A,fixed qp or delta qp. */ + __IOM uint32_t A_ROI_REGION1_QP : 7; /*!< Configure H264 ROI region1 qp in video A,fixed qp or delta qp. */ + __IOM uint32_t A_ROI_REGION2_QP : 7; /*!< Configure H264 ROI region2 qp in video A,fixed qp or delta qp. */ + __IOM uint32_t A_ROI_REGION3_QP : 7; /*!< Configure H264 ROI region3 qp in video A,fixed qp or delta qp. */ + uint32_t : 4; + } bit; + } A_ROI_REGION0_3_QP; + + union { + __IOM uint32_t reg; /*!< Video A H264 ROI region4, region5,region6,region7 QP register. */ + + struct { + __IOM uint32_t A_ROI_REGION4_QP : 7; /*!< Configure H264 ROI region4 qp in video A,fixed qp or delta qp. */ + __IOM uint32_t A_ROI_REGION5_QP : 7; /*!< Configure H264 ROI region5 qp in video A,fixed qp or delta qp. */ + __IOM uint32_t A_ROI_REGION6_QP : 7; /*!< Configure H264 ROI region6 qp in video A,fixed qp or delta qp. */ + __IOM uint32_t A_ROI_REGION7_QP : 7; /*!< Configure H264 ROI region7 qp in video A,fixed qp or delta qp. */ + uint32_t : 4; + } bit; + } A_ROI_REGION4_7_QP; + + union { + __IOM uint32_t reg; /*!< Video A H264 no roi region QP register. */ + + struct { + __IOM uint32_t A_NO_ROI_REGION_QP : 7; /*!< Configure H264 no region qp in video A, delta qp. */ + uint32_t : 25; + } bit; + } A_NO_ROI_REGION_QP_OFFSET; + + union { + __IOM uint32_t reg; /*!< Video A H264 ROI configure register. */ + + struct { + __IOM uint32_t A_ROI_EN : 1; /*!< Configure whether or not to enable ROI in video A.\\0:not enable + ROI\\1:enable ROI. */ + __IOM uint32_t A_ROI_MODE : 1; /*!< Configure the mode of ROI in video A.\\0:fixed qp\\1:delta qp. */ + uint32_t : 30; + } bit; + } A_ROI_CONFIG; + + union { + __IOM uint32_t reg; /*!< Video B horizontal and vertical MB resolution register. */ + + struct { + __IOM uint32_t B_SYS_TOTAL_MB_Y : 7; /*!< Configures video B vertical MB resolution. */ + __IOM uint32_t B_SYS_TOTAL_MB_X : 7; /*!< Configures video B horizontal MB resolution. */ + uint32_t : 18; + } bit; + } B_SYS_MB_RES; + + union { + __IOM uint32_t reg; /*!< Video B system level configuration register. */ + + struct { + __IOM uint32_t B_DB_TMP_READY_TRIGGER_MB_NUM : 7;/*!< Configures when to trigger video B H264_DB_TMP_READY_INT. When + the (MB number of written db temp+1) is greater than this + filed in first MB line, trigger H264_DB_TMP_READY_INT. + Min is 3. */ + __IOM uint32_t B_REC_READY_TRIGGER_MB_LINES : 7;/*!< Configures when to trigger video B H264_REC_READY_INT. When + the MB line number of generated reconstruct pixel is greater + than this filed, trigger H264_REC_READY_INT. Min is 4. */ + __IOM uint32_t B_INTRA_COST_CMP_OFFSET : 16;/*!< Configures video B intra cost offset when I MB compared with + P MB. */ + uint32_t : 2; + } bit; + } B_SYS_CONF; + + union { + __IOM uint32_t reg; /*!< Video B luma and chroma MB decimate score Register. */ + + struct { + __IOM uint32_t B_C_DECI_SCORE : 10; /*!< Configures video B chroma MB decimate score. When chroma score + is smaller than it, chroma decimate will be enable. */ + __IOM uint32_t B_L_DECI_SCORE : 10; /*!< Configures video B luma MB decimate score. When luma score is + smaller than it, luma decimate will be enable. */ + uint32_t : 12; + } bit; + } B_DECI_SCORE; + + union { + __IOM uint32_t reg; /*!< Video B luma and chroma MB decimate score offset Register. */ + + struct { + __IOM uint32_t B_I16X16_DECI_SCORE_OFFSET : 6;/*!< Configures video B i16x16 MB decimate score offset. This offset + will be added to i16x16 MB score. */ + __IOM uint32_t B_I_CHROMA_DECI_SCORE_OFFSET : 6;/*!< Configures video B I chroma MB decimate score offset. This offset + will be added to I chroma MB score. */ + __IOM uint32_t B_P16X16_DECI_SCORE_OFFSET : 6;/*!< Configures video B p16x16 MB decimate score offset. This offset + will be added to p16x16 MB score. */ + __IOM uint32_t B_P_CHROMA_DECI_SCORE_OFFSET : 6;/*!< Configures video B p chroma MB decimate score offset. This offset + will be added to p chroma MB score. */ + uint32_t : 8; + } bit; + } B_DECI_SCORE_OFFSET; + + union { + __IOM uint32_t reg; /*!< Video B rate control configuration register0. */ + + struct { + __IOM uint32_t B_QP : 6; /*!< Configures video B frame level initial luma QP value. */ + __IOM uint32_t B_RATE_CTRL_U : 16; /*!< Configures video B parameter U value. U = int((float) u << 8). */ + __IOM uint32_t B_MB_RATE_CTRL_EN : 1; /*!< Configures video A whether or not to open macro block rate ctrl.\\1:Open + the macro block rate ctrl\\1:Close the macro block rate + ctrl. */ + uint32_t : 9; + } bit; + } B_RC_CONF0; + + union { + __IOM uint32_t reg; /*!< Video B rate control configuration register1. */ + + struct { + __IOM uint32_t B_CHROMA_DC_QP_DELTA : 3; /*!< Configures video B chroma DC QP offset based on Chroma QP. Chroma + DC QP = Chroma QP(after map) + reg_chroma_dc_qp_delta. */ + __IOM uint32_t B_CHROMA_QP_DELTA : 4; /*!< Configures video B chroma QP offset based on luma QP. Chroma + QP(before map) = Luma QP + reg_chroma_qp_delta. */ + __IOM uint32_t B_QP_MIN : 6; /*!< Configures video B allowed luma QP min value. */ + __IOM uint32_t B_QP_MAX : 6; /*!< Configures video B allowed luma QP max value. */ + __IOM uint32_t B_MAD_FRAME_PRED : 12; /*!< Configures vdieo B frame level predicted MB MAD value. */ + uint32_t : 1; + } bit; + } B_RC_CONF1; + + union { + __IOM uint32_t reg; /*!< Video B Deblocking bypass register */ + + struct { + __IOM uint32_t B_BYPASS_DB_FILTER : 1; /*!< Configures whether or not to bypass video B deblcoking filter. + \\0: Open the deblock filter\\1: Close the deblock filter */ + uint32_t : 31; + } bit; + } B_DB_BYPASS; + + union { + __IOM uint32_t reg; /*!< Video B H264 ROI region0 range configure register. */ + + struct { + __IOM uint32_t X : 7; /*!< Configures the horizontal start macroblocks of region 0 in Video + B. */ + __IOM uint32_t Y : 7; /*!< Configures the vertical start macroblocks of region 0 in Video + B. */ + __IOM uint32_t X_LEN : 7; /*!< Configures the number of macroblocks in horizontal direction + of the region 0 in Video B. */ + __IOM uint32_t Y_LEN : 7; /*!< Configures the number of macroblocks in vertical direction of + the region 0 in Video B. */ + __IOM uint32_t EN : 1; /*!< Configures whether or not to open Video B ROI of region 0 .\\0:Close + ROI\\1:Open ROI. */ + uint32_t : 3; + } bit; + } B_ROI_REGION0; + + union { + __IOM uint32_t reg; /*!< Video B H264 ROI region1 range configure register. */ + + struct { + __IOM uint32_t X : 7; /*!< Configures the horizontal start macroblocks of region 1 in Video + B. */ + __IOM uint32_t Y : 7; /*!< Configures the vertical start macroblocks of region 1 in Video + B. */ + __IOM uint32_t X_LEN : 7; /*!< Configures the number of macroblocks in horizontal direction + of the region 1 in Video B. */ + __IOM uint32_t Y_LEN : 7; /*!< Configures the number of macroblocks in vertical direction of + the region 1 in Video B. */ + __IOM uint32_t EN : 1; /*!< Configures whether or not to open Video B ROI of region 1 .\\0:Close + ROI\\1:Open ROI. */ + uint32_t : 3; + } bit; + } B_ROI_REGION1; + + union { + __IOM uint32_t reg; /*!< Video B H264 ROI region2 range configure register. */ + + struct { + __IOM uint32_t X : 7; /*!< Configures the horizontal start macroblocks of region 2 in Video + B. */ + __IOM uint32_t Y : 7; /*!< Configures the vertical start macroblocks of region 2 in Video + B. */ + __IOM uint32_t X_LEN : 7; /*!< Configures the number of macroblocks in horizontal direction + of the region 2 in Video B. */ + __IOM uint32_t Y_LEN : 7; /*!< Configures the number of macroblocks in vertical direction of + the region 2 in Video B. */ + __IOM uint32_t EN : 1; /*!< Configures whether or not to open Video B ROI of region 2 .\\0:Close + ROI\\1:Open ROI. */ + uint32_t : 3; + } bit; + } B_ROI_REGION2; + + union { + __IOM uint32_t reg; /*!< Video B H264 ROI region3 range configure register. */ + + struct { + __IOM uint32_t X : 7; /*!< Configures the horizontal start macroblocks of region 3 in Video + B. */ + __IOM uint32_t Y : 7; /*!< Configures the vertical start macroblocks of region 3 in Video + B. */ + __IOM uint32_t X_LEN : 7; /*!< Configures the number of macroblocks in horizontal direction + of the region 3 in video B. */ + __IOM uint32_t Y_LEN : 7; /*!< Configures the number of macroblocks in vertical direction of + the region 3 in video B. */ + __IOM uint32_t EN : 1; /*!< Configures whether or not to open Video B ROI of region 3 .\\0:Close + ROI\\1:Open ROI. */ + uint32_t : 3; + } bit; + } B_ROI_REGION3; + + union { + __IOM uint32_t reg; /*!< Video B H264 ROI region4 range configure register. */ + + struct { + __IOM uint32_t X : 7; /*!< Configures the horizontal start macroblocks of region 4 in Video + B. */ + __IOM uint32_t Y : 7; /*!< Configures the vertical start macroblocks of region 4 in Video + B. */ + __IOM uint32_t X_LEN : 7; /*!< Configures the number of macroblocks in horizontal direction + of the region 4 in video B. */ + __IOM uint32_t Y_LEN : 7; /*!< Configures the number of macroblocks in vertical direction of + the region 4 in video B. */ + __IOM uint32_t EN : 1; /*!< Configures whether or not to open Video B ROI of region 4 .\\0:Close + ROI\\1:Open ROI. */ + uint32_t : 3; + } bit; + } B_ROI_REGION4; + + union { + __IOM uint32_t reg; /*!< Video B H264 ROI region5 range configure register. */ + + struct { + __IOM uint32_t X : 7; /*!< Configures the horizontial start macroblocks of region 5 video + B. */ + __IOM uint32_t Y : 7; /*!< Configures the vertical start macroblocks of region 5 video + B. */ + __IOM uint32_t X_LEN : 7; /*!< Configures the number of macroblocks in horizontal direction + of the region 5 video B. */ + __IOM uint32_t Y_LEN : 7; /*!< Configures the number of macroblocks in vertical direction of + the region 5 in video B. */ + __IOM uint32_t EN : 1; /*!< Configures whether or not to open Video B ROI of region 5 .\\0:Close + ROI\\1:Open ROI. */ + uint32_t : 3; + } bit; + } B_ROI_REGION5; + + union { + __IOM uint32_t reg; /*!< Video B H264 ROI region6 range configure register. */ + + struct { + __IOM uint32_t X : 7; /*!< Configures the horizontial start macroblocks of region 6 video + B. */ + __IOM uint32_t Y : 7; /*!< Configures the vertical start macroblocks of region 6 in video + B. */ + __IOM uint32_t X_LEN : 7; /*!< Configures the number of macroblocks in horizontal direction + of the region 6 in video B. */ + __IOM uint32_t Y_LEN : 7; /*!< Configures the number of macroblocks in vertical direction of + the region 6 in video B. */ + __IOM uint32_t EN : 1; /*!< Configures whether or not to open Video B ROI of region 6 .\\0:Close + ROI\\1:Open ROI. */ + uint32_t : 3; + } bit; + } B_ROI_REGION6; + + union { + __IOM uint32_t reg; /*!< Video B H264 ROI region7 range configure register. */ + + struct { + __IOM uint32_t X : 7; /*!< Configures the horizontal start macroblocks of region 7 in video + B. */ + __IOM uint32_t Y : 7; /*!< Configures the vertical start macroblocks of region 7 in video + B. */ + __IOM uint32_t X_LEN : 7; /*!< Configures the number of macroblocks in horizontal direction + of the region 7 in video B. */ + __IOM uint32_t Y_LEN : 7; /*!< Configures the number of macroblocks in vertical direction of + the region 7 in video B. */ + __IOM uint32_t EN : 1; /*!< Configures whether or not to open Video B ROI of region 7 .\\0:Close + ROI\\1:Open ROI. */ + uint32_t : 3; + } bit; + } B_ROI_REGION7; + + union { + __IOM uint32_t reg; /*!< Video B H264 ROI region0, region1,region2,region3 QP register. */ + + struct { + __IOM uint32_t B_ROI_REGION0_QP : 7; /*!< Configure H264 ROI region0 qp in video B,fixed qp or delta qp. */ + __IOM uint32_t B_ROI_REGION1_QP : 7; /*!< Configure H264 ROI region1 qp in video B,fixed qp or delta qp. */ + __IOM uint32_t B_ROI_REGION2_QP : 7; /*!< Configure H264 ROI region2 qp in video B,fixed qp or delta qp. */ + __IOM uint32_t B_ROI_REGION3_QP : 7; /*!< Configure H264 ROI region3 qp in video B,fixed qp or delta qp. */ + uint32_t : 4; + } bit; + } B_ROI_REGION0_3_QP; + + union { + __IOM uint32_t reg; /*!< Video B H264 ROI region4, region5,region6,region7 QP register. */ + + struct { + __IOM uint32_t B_ROI_REGION4_QP : 7; /*!< Configure H264 ROI region4 qp in video B,fixed qp or delta qp. */ + __IOM uint32_t B_ROI_REGION5_QP : 7; /*!< Configure H264 ROI region5 qp in video B,fixed qp or delta qp. */ + __IOM uint32_t B_ROI_REGION6_QP : 7; /*!< Configure H264 ROI region6 qp in video B,fixed qp or delta qp. */ + __IOM uint32_t B_ROI_REGION7_QP : 7; /*!< Configure H264 ROI region7 qp in video B,fixed qp or delta qp. */ + uint32_t : 4; + } bit; + } B_ROI_REGION4_7_QP; + + union { + __IOM uint32_t reg; /*!< Video B H264 no roi region QP register. */ + + struct { + __IOM uint32_t B_NO_ROI_REGION_QP : 7; /*!< Configure H264 no region qp in video B, delta qp. */ + uint32_t : 25; + } bit; + } B_NO_ROI_REGION_QP_OFFSET; + + union { + __IOM uint32_t reg; /*!< Video B H264 ROI configure register. */ + + struct { + __IOM uint32_t B_ROI_EN : 1; /*!< Configure whether or not to enable ROI in video B.\\0:not enable + ROI\\1:enable ROI. */ + __IOM uint32_t B_ROI_MODE : 1; /*!< Configure the mode of ROI in video B.\\0:fixed qp\\1:delta qp. */ + uint32_t : 30; + } bit; + } B_ROI_CONFIG; + + union { + __IOM uint32_t reg; /*!< Rate control status register0. */ + + struct { + __IM uint32_t FRAME_MAD_SUM : 21; /*!< Represents all MB actual MAD sum value of one frame. */ + uint32_t : 11; + } bit; + } RC_STATUS0; + + union { + __IOM uint32_t reg; /*!< Rate control status register1. */ + + struct { + __IM uint32_t FRAME_ENC_BITS : 27; /*!< Represents all MB actual encoding bits sum value of one frame. */ + uint32_t : 5; + } bit; + } RC_STATUS1; + + union { + __IOM uint32_t reg; /*!< Rate control status register2. */ + + struct { + __IM uint32_t FRAME_QP_SUM : 19; /*!< Represents all MB actual luma QP sum value of one frame. */ + uint32_t : 13; + } bit; + } RC_STATUS2; + + union { + __IOM uint32_t reg; /*!< Frame Slice Header remain bit register. */ + + struct { + __IOM uint32_t SLICE_REMAIN_BITLENGTH : 3;/*!< Configures Slice Header remain bit number */ + __IOM uint32_t SLICE_REMAIN_BIT : 8; /*!< Configures Slice Header remain bit */ + uint32_t : 21; + } bit; + } SLICE_HEADER_REMAIN; + + union { + __IOM uint32_t reg; /*!< Frame Slice Header byte length register. */ + + struct { + __IOM uint32_t SLICE_BYTE_LENGTH : 4; /*!< Configures Slice Header byte number */ + uint32_t : 28; + } bit; + } SLICE_HEADER_BYTE_LENGTH; + + union { + __IOM uint32_t reg; /*!< Bitstream buffer overflow threshold register */ + + struct { + __IOM uint32_t BS_BUFFER_THRESHOLD : 7; /*!< Configures bitstream buffer overflow threshold. This value should + be bigger than the encode bytes of one 4x4 submb. */ + uint32_t : 25; + } bit; + } BS_THRESHOLD; + + union { + __IOM uint32_t reg; /*!< Frame Slice Header byte low 32 bit register. */ + + struct { + __IOM uint32_t SLICE_BYTE_LSB : 32; /*!< Configures Slice Header low 32 bit */ + } bit; + } SLICE_HEADER_BYTE0; + + union { + __IOM uint32_t reg; /*!< Frame Slice Header byte high 32 bit register. */ + + struct { + __IOM uint32_t SLICE_BYTE_MSB : 32; /*!< Configures Slice Header high 32 bit */ + } bit; + } SLICE_HEADER_BYTE1; + + union { + __IOM uint32_t reg; /*!< Interrupt raw status register */ + + struct { + __IOM uint32_t DB_TMP_READY_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of H264_DB_TMP_READY_INT. + Triggered when H264 written enough db tmp pixel. */ + __IOM uint32_t REC_READY_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of H264_REC_READY_INT. + Triggered when H264 encoding enough reconstruct pixel. */ + __IOM uint32_t FRAME_DONE_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of H264_FRAME_DONE_INT. + Triggered when H264 encoding one frame done. */ + __IOM uint32_t DMA_MOVE_2MB_LINE_DONE_INT_RAW : 1;/*!< Raw status bit: The raw interrupt status of H264_DMA_MOVE_2MB_LINE_DONE_INT. + Triggered when H264 move two MB lines of reference frame + from external mem to internal mem done. */ + uint32_t : 28; + } bit; + } INT_RAW; + + union { + __IOM uint32_t reg; /*!< Interrupt masked status register */ + + struct { + __IM uint32_t DB_TMP_READY_INT_ST : 1; /*!< The masked interrupt status of H264_DB_TMP_READY_INT. Valid + only when the H264_DB_TMP_READY_INT_ENA is set to 1. */ + __IM uint32_t REC_READY_INT_ST : 1; /*!< The masked interrupt status of H264_REC_READY_INT. Valid only + when the H264_REC_READY_INT_ENA is set to 1. */ + __IM uint32_t FRAME_DONE_INT_ST : 1; /*!< The masked interrupt status of H264_FRAME_DONE_INT. Valid only + when the H264_FRAME_DONE_INT_ENA is set to 1. */ + __IM uint32_t DMA_MOVE_2MB_LINE_DONE_INT_ST : 1;/*!< Masked status bit: The masked interrupt status of H264_DMA_MOVE_2MB_LINE_DONE_ + NT. Valid only when the H264_DMA_MOVE_2MB_LINE_DONE_INT_ENA + is set to 1. */ + uint32_t : 28; + } bit; + } INT_ST; + + union { + __IOM uint32_t reg; /*!< Interrupt enable register */ + + struct { + __IOM uint32_t DB_TMP_READY_INT_ENA : 1; /*!< Write 1 to enable H264_DB_TMP_READY_INT. */ + __IOM uint32_t REC_READY_INT_ENA : 1; /*!< Write 1 to enable H264_REC_READY_INT. */ + __IOM uint32_t FRAME_DONE_INT_ENA : 1; /*!< Write 1 to enable H264_FRAME_DONE_INT. */ + __IOM uint32_t DMA_MOVE_2MB_LINE_DONE_INT_ENA : 1;/*!< Enable bit: Write 1 to enable H264_DMA_MOVE_2MB_LINE_DONE_INT. */ + uint32_t : 28; + } bit; + } INT_ENA; + + union { + __IOM uint32_t reg; /*!< Interrupt clear register */ + + struct { + __OM uint32_t DB_TMP_READY_INT_CLR : 1; /*!< Write 1 to clear H264_DB_TMP_READY_INT. */ + __OM uint32_t REC_READY_INT_CLR : 1; /*!< Write 1 to clear H264_REC_READY_INT. */ + __OM uint32_t FRAME_DONE_INT_CLR : 1; /*!< Write 1 to clear H264_FRAME_DONE_INT. */ + __OM uint32_t DMA_MOVE_2MB_LINE_DONE_INT_CLR : 1;/*!< Clear bit: Write 1 to clear H264_DMA_MOVE_2MB_LINE_DONE_INT. */ + uint32_t : 28; + } bit; + } INT_CLR; + + union { + __IOM uint32_t reg; /*!< General configuration register. */ + + struct { + __IOM uint32_t CLK_EN : 1; /*!< Configures whether or not to open register clock gate.\\0: Open + the clock gate only when application writes registers\\1: + Force open the clock gate for register */ + __IOM uint32_t REC_RAM_CLK_EN2 : 1; /*!< Configures whether or not to open the clock gate for rec ram2.\\0: + Open the clock gate only when application writes or reads + rec ram2\\1: Force open the clock gate for rec ram2 */ + __IOM uint32_t REC_RAM_CLK_EN1 : 1; /*!< Configures whether or not to open the clock gate for rec ram1.\\0: + Open the clock gate only when application writes or reads + rec ram1\\1: Force open the clock gate for rec ram1 */ + __IOM uint32_t QUANT_RAM_CLK_EN2 : 1; /*!< Configures whether or not to open the clock gate for quant ram2.\\0: + Open the clock gate only when application writes or reads + quant ram2\\1: Force open the clock gate for quant ram2 */ + __IOM uint32_t QUANT_RAM_CLK_EN1 : 1; /*!< Configures whether or not to open the clock gate for quant ram1.\\0: + Open the clock gate only when application writes or reads + quant ram1\\1: Force open the clock gate for quant ram1 */ + __IOM uint32_t PRE_RAM_CLK_EN : 1; /*!< Configures whether or not to open the clock gate for pre ram.\\0: + Open the clock gate only when application writes or reads + pre ram\\1: Force open the clock gate for pre ram */ + __IOM uint32_t MVD_RAM_CLK_EN : 1; /*!< Configures whether or not to open the clock gate for mvd ram.\\0: + Open the clock gate only when application writes or reads + mvd ram\\1: Force open the clock gate for mvd ram */ + __IOM uint32_t MC_RAM_CLK_EN : 1; /*!< Configures whether or not to open the clock gate for mc ram.\\0: + Open the clock gate only when application writes or reads + mc ram\\1: Force open the clock gate for mc ram */ + __IOM uint32_t REF_RAM_CLK_EN : 1; /*!< Configures whether or not to open the clock gate for ref ram.\\0: + Open the clock gate only when application writes or reads + ref ram\\1: Force open the clock gate for ref ram */ + __IOM uint32_t I4X4_REF_RAM_CLK_EN : 1; /*!< Configures whether or not to open the clock gate for i4x4_mode + ram.\\0: Open the clock gate only when application writes + or reads i4x4_mode ram\\1: Force open the clock gate for + i4x4_mode ram */ + __IOM uint32_t IME_RAM_CLK_EN : 1; /*!< Configures whether or not to open the clock gate for ime ram.\\0: + Open the clock gate only when application writes or reads + ime ram\\1: Force open the clock gate for ime ram */ + __IOM uint32_t FME_RAM_CLK_EN : 1; /*!< Configures whether or not to open the clock gate for fme ram.\\0: + Open the clock gate only when application writes or readsfme + ram\\1: Force open the clock gate for fme ram */ + __IOM uint32_t FETCH_RAM_CLK_EN : 1; /*!< Configures whether or not to open the clock gate for fetch ram.\\0: + Open the clock gate only when application writes or reads + fetch ram\\1: Force open the clock gate for fetch ram */ + __IOM uint32_t DB_RAM_CLK_EN : 1; /*!< Configures whether or not to open the clock gate for db ram.\\0: + Open the clock gate only when application writes or reads + db ram\\1: Force open the clock gate for db ram */ + __IOM uint32_t CUR_MB_RAM_CLK_EN : 1; /*!< Configures whether or not to open the clock gate for cur_mb + ram.\\0: Open the clock gate only when application writes + or reads cur_mb ram\\1: Force open the clock gate for cur_mb + ram */ + __IOM uint32_t CAVLC_RAM_CLK_EN : 1; /*!< Configures whether or not to open the clock gate for cavlc ram.\\0: + Open the clock gate only when application writes or reads + cavlc ram\\1: Force open the clock gate for cavlc ram */ + __IOM uint32_t IME_CLK_EN : 1; /*!< Configures whether or not to open the clock gate for ime.\\0: + Open the clock gate only when ime work\\1: Force open the + clock gate for ime */ + __IOM uint32_t FME_CLK_EN : 1; /*!< Configures whether or not to open the clock gate for fme.\\0: + Open the clock gate only when fme work\\1: Force open the + clock gate for fme */ + __IOM uint32_t MC_CLK_EN : 1; /*!< Configures whether or not to open the clock gate for mc.\\0: + Open the clock gate only when mc work\\1: Force open the + clock gate for mc */ + __IOM uint32_t INTERPOLATOR_CLK_EN : 1; /*!< Configures whether or not to open the clock gate for interpolator.\\0: + Open the clock gate only when interpolator work\\1: Force + open the clock gate for interpolator */ + __IOM uint32_t DB_CLK_EN : 1; /*!< Configures whether or not to open the clock gate for deblocking + filter.\\0: Open the clock gate only when deblocking filter + work\\1: Force open the clock gate for deblocking filter */ + __IOM uint32_t CLAVLC_CLK_EN : 1; /*!< Configures whether or not to open the clock gate for cavlc.\\0: + Open the clock gate only when cavlc work\\1: Force open + the clock gate for cavlc */ + __IOM uint32_t INTRA_CLK_EN : 1; /*!< Configures whether or not to open the clock gate for intra.\\0: + Open the clock gate only when intra work\\1: Force open + the clock gate for intra */ + __IOM uint32_t DECI_CLK_EN : 1; /*!< Configures whether or not to open the clock gate for decimate.\\0: + Open the clock gate only when decimate work\\1: Force open + the clock gate for decimate */ + __IOM uint32_t BS_CLK_EN : 1; /*!< Configures whether or not to open the clock gate for bs buffer.\\0: + Open the clock gate only when bs buffer work\\1: Force + open the clock gate for bs buffer */ + __IOM uint32_t MV_MERGE_CLK_EN : 1; /*!< Configures whether or not to open the clock gate for mv merge.\\0: + Open the clock gate only when mv merge work\\1: Force open + the clock gate for mv merge */ + uint32_t : 6; + } bit; + } CONF; + + union { + __IOM uint32_t reg; /*!< Mv merge configuration register. */ + + struct { + __IOM uint32_t MV_MERGE_TYPE : 2; /*!< Configure mv merge type.\\0: merge p16x16 mv\\1: merge min mv\\2: + merge max mv\\3: not valid. */ + __IOM uint32_t INT_MV_OUT_EN : 1; /*!< Configure mv merge output integer part not zero mv or all part + not zero mv.\\0: output all part not zero mv\\1: output + integer part not zero mv. */ + __IOM uint32_t A_MV_MERGE_EN : 1; /*!< Configure whether or not to enable video A mv merge.\\0: disable\\1: + enable. */ + __IOM uint32_t B_MV_MERGE_EN : 1; /*!< Configure whether or not to enable video B mv merge.\\0: disable\\1: + enable. */ + __IM uint32_t MB_VALID_NUM : 13; /*!< Represents the valid mb number of mv merge output. */ + uint32_t : 14; + } bit; + } MV_MERGE_CONFIG; + + union { + __IOM uint32_t reg; /*!< Debug H264 DMA select register */ + + struct { + __IOM uint32_t DBG_DMA_SEL : 8; /*!< Every bit represents a dma in h264 */ + uint32_t : 24; + } bit; + } DEBUG_DMA_SEL; + + union { + __IOM uint32_t reg; /*!< System status register. */ + + struct { + __IM uint32_t FRAME_NUM : 9; /*!< Represents current frame number. */ + __IM uint32_t DUAL_STREAM_SEL : 1; /*!< Represents which register group is used for cur frame.\\0: Register + group A is used\\1: Register group B is used. */ + __IM uint32_t INTRA_FLAG : 1; /*!< Represents the type of current encoding frame.\\0: P frame\\1: + I frame. */ + uint32_t : 21; + } bit; + } SYS_STATUS; + + union { + __IOM uint32_t reg; /*!< Frame code byte length register. */ + + struct { + __IM uint32_t FRAME_CODE_LENGTH : 24; /*!< Represents current frame code byte length. */ + uint32_t : 8; + } bit; + } FRAME_CODE_LENGTH; + + union { + __IOM uint32_t reg; /*!< Debug information register0. */ + + struct { + __IM uint32_t TOP_CTRL_INTER_DEBUG_STATE : 4;/*!< Represents top_ctrl_inter module FSM info. */ + __IM uint32_t TOP_CTRL_INTRA_DEBUG_STATE : 3;/*!< Represents top_ctrl_intra module FSM info. */ + __IM uint32_t P_I_CMP_DEBUG_STATE : 3; /*!< Represents p_i_cmp module FSM info. */ + __IM uint32_t MVD_DEBUG_STATE : 3; /*!< Represents mvd module FSM info. */ + __IM uint32_t MC_CHROMA_IP_DEBUG_STATE : 1;/*!< Represents mc_chroma_ip module FSM info. */ + __IM uint32_t INTRA_16X16_CHROMA_CTRL_DEBUG_STATE : 4;/*!< Represents intra_16x16_chroma_ctrl module FSM info. */ + __IM uint32_t INTRA_4X4_CTRL_DEBUG_STATE : 4;/*!< Represents intra_4x4_ctrl module FSM info. */ + __IM uint32_t INTRA_TOP_CTRL_DEBUG_STATE : 3;/*!< Represents intra_top_ctrl module FSM info. */ + __IM uint32_t IME_CTRL_DEBUG_STATE : 3; /*!< Represents ime_ctrl module FSM info. */ + uint32_t : 4; + } bit; + } DEBUG_INFO0; + + union { + __IOM uint32_t reg; /*!< Debug information register1. */ + + struct { + __IM uint32_t FME_CTRL_DEBUG_STATE : 3; /*!< Represents fme_ctrl module FSM info. */ + __IM uint32_t DECI_CALC_DEBUG_STATE : 2; /*!< Represents deci_calc module's FSM info. DEV use only. */ + __IM uint32_t DB_DEBUG_STATE : 3; /*!< Represents db module FSM info. */ + __IM uint32_t CAVLC_ENC_DEBUG_STATE : 4; /*!< Represents cavlc module enc FSM info. */ + __IM uint32_t CAVLC_SCAN_DEBUG_STATE : 4;/*!< Represents cavlc module scan FSM info. */ + __IM uint32_t CAVLC_CTRL_DEBUG_STATE : 2;/*!< Represents cavlc module ctrl FSM info. */ + __IM uint32_t BS_BUFFER_DEBUG_STATE : 1; /*!< Represents bs buffer overflow info. */ + uint32_t : 13; + } bit; + } DEBUG_INFO1; + + union { + __IOM uint32_t reg; /*!< Debug information register2. */ + + struct { + __IM uint32_t P_RC_DONE_DEBUG_FLAG : 1; /*!< Represents p rate ctrl done status.\\0: not done\\1: done. */ + __IM uint32_t P_P_I_CMP_DONE_DEBUG_FLAG : 1;/*!< Represents p p_i_cmp done status.\\0: not done\\1: done. */ + __IM uint32_t P_MV_MERGE_DONE_DEBUG_FLAG : 1;/*!< Represents p mv merge done status.\\0: not done\\1: done. */ + __IM uint32_t P_MOVE_ORI_DONE_DEBUG_FLAG : 1;/*!< Represents p move origin done status.\\0: not done\\1: done. */ + __IM uint32_t P_MC_DONE_DEBUG_FLAG : 1; /*!< Represents p mc done status.\\0: not done\\1: done. */ + __IM uint32_t P_IME_DONE_DEBUG_FLAG : 1; /*!< Represents p ime done status.\\0: not done\\1: done. */ + __IM uint32_t P_GET_ORI_DONE_DEBUG_FLAG : 1;/*!< Represents p get origin done status.\\0: not done\\1: done. */ + __IM uint32_t P_FME_DONE_DEBUG_FLAG : 1; /*!< Represents p fme done status.\\0: not done\\1: done. */ + __IM uint32_t P_FETCH_DONE_DEBUG_FLAG : 1;/*!< Represents p fetch done status.\\0: not done\\1: done. */ + __IM uint32_t P_DB_DONE_DEBUG_FLAG : 1; /*!< Represents p deblocking done status.\\0: not done\\1: done. */ + __IM uint32_t P_BS_BUF_DONE_DEBUG_FLAG : 1;/*!< Represents p bitstream buffer done status.\\0: not done\\1: + done. */ + __IM uint32_t REF_MOVE_2MB_LINE_DONE_DEBUG_FLAG : 1;/*!< Represents dma move 2 ref mb line done status.\\0: not done\\1: + done. */ + __IM uint32_t I_P_I_CMP_DONE_DEBUG_FLAG : 1;/*!< Represents I p_i_cmp done status.\\0: not done\\1: done. */ + __IM uint32_t I_MOVE_ORI_DONE_DEBUG_FLAG : 1;/*!< Represents I move origin done status.\\0: not done\\1: done. */ + __IM uint32_t I_GET_ORI_DONE_DEBUG_FLAG : 1;/*!< Represents I get origin done status.\\0: not done\\1: done. */ + __IM uint32_t I_EC_DONE_DEBUG_FLAG : 1; /*!< Represents I encoder done status.\\0: not done\\1: done. */ + __IM uint32_t I_DB_DONE_DEBUG_FLAG : 1; /*!< Represents I deblocking done status.\\0: not done\\1: done. */ + __IM uint32_t I_BS_BUF_DONE_DEBUG_FLAG : 1;/*!< Represents I bitstream buffer done status.\\0: not done\\1: + done. */ + uint32_t : 14; + } bit; + } DEBUG_INFO2; + + union { + __IOM uint32_t reg; /*!< Version control register */ + + struct { + __IOM uint32_t LEDC_DATE : 28; /*!< Configures the version. */ + uint32_t : 4; + } bit; + } DATE; +} H264_Type; /*!< Size = 244 (0xf4) */ + + + +/* =========================================================================================================================== */ +/* ================ H264_DMA ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief H264 Encoder (DMA) (H264_DMA) + */ + +typedef struct { /*!< H264_DMA Structure */ + + union { + __IOM uint32_t reg; /*!< TX CH0 config0 register */ + + struct { + __IOM uint32_t OUT_AUTO_WRBACK_CH0 : 1; /*!< Set this bit to enable automatic outlink-writeback when all + the data pointed by outlink descriptor has been received. */ + __IOM uint32_t OUT_EOF_MODE_CH0 : 1; /*!< EOF flag generation mode when receiving data. 1: EOF flag for + Tx channel 0 is generated when data need to read has been + popped from FIFO in DMA */ + __IOM uint32_t OUTDSCR_BURST_EN_CH0 : 1; /*!< Set this bit to 1 to enable INCR burst transfer for Tx channel + 0 reading link descriptor when accessing internal SRAM. */ + __IOM uint32_t OUT_ECC_AES_EN_CH0 : 1; /*!< When access address space is ecc/aes area, this bit should be + set to 1. In this case, the start address of square should + be 16-bit aligned. The width of square multiply byte number + of one pixel should be 16-bit aligned. */ + __IOM uint32_t OUT_CHECK_OWNER_CH0 : 1; /*!< Set this bit to enable checking the owner attribute of the link + descriptor. */ + uint32_t : 1; + __IOM uint32_t OUT_MEM_BURST_LENGTH_CH0 : 3;/*!< Block size of Tx channel 0. 0: single 1: 16 bytes 2: 32 bytes + 3: 64 bytes 4: 128 bytes */ + uint32_t : 3; + __IOM uint32_t OUT_PAGE_BOUND_EN_CH0 : 1; /*!< Set this bit to 1 to make sure AXI read data don't cross the + address boundary which define by mem_burst_length */ + uint32_t : 3; + __IOM uint32_t OUT_REORDER_EN_CH0 : 1; /*!< Enable TX channel 0 macro block reorder when set to 1, only + channel0 have this selection */ + uint32_t : 7; + __IOM uint32_t OUT_RST_CH0 : 1; /*!< Write 1 then write 0 to this bit to reset TX channel */ + __IOM uint32_t OUT_CMD_DISABLE_CH0 : 1; /*!< Write 1 before reset and write 0 after reset */ + __IOM uint32_t OUT_ARB_WEIGHT_OPT_DIS_CH0 : 1;/*!< Set this bit to 1 to disable arbiter optimum weight function. */ + uint32_t : 5; + } bit; + } OUT_CONF0_CH0; + + union { + __IOM uint32_t reg; /*!< TX CH0 interrupt raw register */ + + struct { + __IOM uint32_t OUT_DONE_CH0_INT_RAW : 1; /*!< The raw interrupt bit turns to high level when the last data + pointed by one outlink descriptor has been transmitted + to peripherals for Tx channel 0. */ + __IOM uint32_t OUT_EOF_CH0_INT_RAW : 1; /*!< The raw interrupt bit turns to high level when the last data + pointed by one outlink descriptor has been read from memory + for Tx channel 0. */ + __IOM uint32_t OUT_DSCR_ERR_CH0_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when detecting outlink + descriptor error, including owner error, the second and + third word error of outlink descriptor for Tx channel 0. */ + __IOM uint32_t OUT_TOTAL_EOF_CH0_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when data corresponding + a outlink (includes one link descriptor or few link descriptors) + is transmitted out for Tx channel 0. */ + __IOM uint32_t OUTFIFO_OVF_L1_CH0_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when fifo is overflow. */ + __IOM uint32_t OUTFIFO_UDF_L1_CH0_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when fifo is underflow. */ + __IOM uint32_t OUTFIFO_OVF_L2_CH0_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when fifo is overflow. */ + __IOM uint32_t OUTFIFO_UDF_L2_CH0_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when fifo is underflow. */ + __IOM uint32_t OUT_DSCR_TASK_OVF_CH0_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when dscr ready task + fifo is overflow. */ + uint32_t : 23; + } bit; + } OUT_INT_RAW_CH0; + + union { + __IOM uint32_t reg; /*!< TX CH0 interrupt ena register */ + + struct { + __IOM uint32_t OUT_DONE_CH0_INT_ENA : 1; /*!< The interrupt enable bit for the OUT_DONE_CH_INT interrupt. */ + __IOM uint32_t OUT_EOF_CH0_INT_ENA : 1; /*!< The interrupt enable bit for the OUT_EOF_CH_INT interrupt. */ + __IOM uint32_t OUT_DSCR_ERR_CH0_INT_ENA : 1;/*!< The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. */ + __IOM uint32_t OUT_TOTAL_EOF_CH0_INT_ENA : 1;/*!< The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. */ + __IOM uint32_t OUTFIFO_OVF_L1_CH0_INT_ENA : 1;/*!< The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. */ + __IOM uint32_t OUTFIFO_UDF_L1_CH0_INT_ENA : 1;/*!< The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. */ + __IOM uint32_t OUTFIFO_OVF_L2_CH0_INT_ENA : 1;/*!< The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. */ + __IOM uint32_t OUTFIFO_UDF_L2_CH0_INT_ENA : 1;/*!< The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. */ + __IOM uint32_t OUT_DSCR_TASK_OVF_CH0_INT_ENA : 1;/*!< The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. */ + uint32_t : 23; + } bit; + } OUT_INT_ENA_CH0; + + union { + __IOM uint32_t reg; /*!< TX CH0 interrupt st register */ + + struct { + __IM uint32_t OUT_DONE_CH0_INT_ST : 1; /*!< The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. */ + __IM uint32_t OUT_EOF_CH0_INT_ST : 1; /*!< The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. */ + __IM uint32_t OUT_DSCR_ERR_CH0_INT_ST : 1;/*!< The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. */ + __IM uint32_t OUT_TOTAL_EOF_CH0_INT_ST : 1;/*!< The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. */ + __IM uint32_t OUTFIFO_OVF_L1_CH0_INT_ST : 1;/*!< The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. */ + __IM uint32_t OUTFIFO_UDF_L1_CH0_INT_ST : 1;/*!< The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. */ + __IM uint32_t OUTFIFO_OVF_L2_CH0_INT_ST : 1;/*!< The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. */ + __IM uint32_t OUTFIFO_UDF_L2_CH0_INT_ST : 1;/*!< The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. */ + __IM uint32_t OUT_DSCR_TASK_OVF_CH0_INT_ST : 1;/*!< The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT + interrupt. */ + uint32_t : 23; + } bit; + } OUT_INT_ST_CH0; + + union { + __IOM uint32_t reg; /*!< TX CH0 interrupt clr register */ + + struct { + __OM uint32_t OUT_DONE_CH0_INT_CLR : 1; /*!< Set this bit to clear the OUT_DONE_CH_INT interrupt. */ + __OM uint32_t OUT_EOF_CH0_INT_CLR : 1; /*!< Set this bit to clear the OUT_EOF_CH_INT interrupt. */ + __OM uint32_t OUT_DSCR_ERR_CH0_INT_CLR : 1;/*!< Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. */ + __OM uint32_t OUT_TOTAL_EOF_CH0_INT_CLR : 1;/*!< Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. */ + __OM uint32_t OUTFIFO_OVF_L1_CH0_INT_CLR : 1;/*!< Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. */ + __OM uint32_t OUTFIFO_UDF_L1_CH0_INT_CLR : 1;/*!< Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. */ + __OM uint32_t OUTFIFO_OVF_L2_CH0_INT_CLR : 1;/*!< Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. */ + __OM uint32_t OUTFIFO_UDF_L2_CH0_INT_CLR : 1;/*!< Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. */ + __OM uint32_t OUT_DSCR_TASK_OVF_CH0_INT_CLR : 1;/*!< Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. */ + uint32_t : 23; + } bit; + } OUT_INT_CLR_CH0; + + union { + __IOM uint32_t reg; /*!< TX CH0 outfifo status register */ + + struct { + __IM uint32_t OUTFIFO_FULL_L2_CH0 : 1; /*!< Tx FIFO full signal for Tx channel 0. */ + __IM uint32_t OUTFIFO_EMPTY_L2_CH0 : 1; /*!< Tx FIFO empty signal for Tx channel 0. */ + __IM uint32_t OUTFIFO_CNT_L2_CH0 : 4; /*!< The register stores the byte number of the data in Tx FIFO for + Tx channel 0. */ + __IM uint32_t OUTFIFO_FULL_L1_CH0 : 1; /*!< Tx FIFO full signal for Tx channel 0. */ + __IM uint32_t OUTFIFO_EMPTY_L1_CH0 : 1; /*!< Tx FIFO empty signal for Tx channel 0. */ + __IM uint32_t OUTFIFO_CNT_L1_CH0 : 5; /*!< The register stores the byte number of the data in Tx FIFO for + Tx channel 0. */ + uint32_t : 3; + __IM uint32_t OUTFIFO_FULL_L3_CH0 : 1; /*!< Tx FIFO full signal for Tx channel 0. */ + __IM uint32_t OUTFIFO_EMPTY_L3_CH0 : 1; /*!< Tx FIFO empty signal for Tx channel 0. */ + __IM uint32_t OUTFIFO_CNT_L3_CH0 : 2; /*!< The register stores the 8byte number of the data in Tx FIFO + for Tx channel 0. */ + uint32_t : 12; + } bit; + } OUTFIFO_STATUS_CH0; + + union { + __IOM uint32_t reg; /*!< TX CH0 outfifo push register */ + + struct { + __IOM uint32_t OUTFIFO_WDATA_CH0 : 10; /*!< This register stores the data that need to be pushed into DMA + Tx FIFO. */ + __IOM uint32_t OUTFIFO_PUSH_CH0 : 1; /*!< Set this bit to push data into DMA Tx FIFO. */ + uint32_t : 21; + } bit; + } OUT_PUSH_CH0; + + union { + __IOM uint32_t reg; /*!< TX CH0 out_link dscr ctrl register */ + + struct { + uint32_t : 20; + __IOM uint32_t OUTLINK_STOP_CH0 : 1; /*!< Set this bit to stop dealing with the outlink descriptors. */ + __IOM uint32_t OUTLINK_START_CH0 : 1; /*!< Set this bit to start dealing with the outlink descriptors. */ + __IOM uint32_t OUTLINK_RESTART_CH0 : 1; /*!< Set this bit to restart a new outlink from the last address. */ + __IM uint32_t OUTLINK_PARK_CH0 : 1; /*!< 1: the outlink descriptor's FSM is in idle state. 0: the outlink + descriptor's FSM is working. */ + uint32_t : 8; + } bit; + } OUT_LINK_CONF_CH0; + + union { + __IOM uint32_t reg; /*!< TX CH0 out_link dscr addr register */ + + struct { + __IOM uint32_t OUTLINK_ADDR_CH0 : 32; /*!< This register stores the first outlink descriptor's address. */ + } bit; + } OUT_LINK_ADDR_CH0; + + union { + __IOM uint32_t reg; /*!< TX CH0 state register */ + + struct { + __IM uint32_t OUTLINK_DSCR_ADDR_CH0 : 18;/*!< This register stores the current outlink descriptor's address. */ + __IM uint32_t OUT_DSCR_STATE_CH0 : 2; /*!< This register stores the current descriptor state machine state. */ + __IM uint32_t OUT_STATE_CH0 : 4; /*!< This register stores the current control module state machine + state. */ + __IM uint32_t OUT_RESET_AVAIL_CH0 : 1; /*!< This register indicate that if the channel reset is safety. */ + uint32_t : 7; + } bit; + } OUT_STATE_CH0; + + union { + __IOM uint32_t reg; /*!< TX CH0 eof des addr register */ + + struct { + __IM uint32_t OUT_EOF_DES_ADDR_CH0 : 32; /*!< This register stores the address of the outlink descriptor when + the EOF bit in this descriptor is 1. */ + } bit; + } OUT_EOF_DES_ADDR_CH0; + + union { + __IOM uint32_t reg; /*!< TX CH0 next dscr addr register */ + + struct { + __IM uint32_t OUTLINK_DSCR_CH0 : 32; /*!< The address of the next outlink descriptor address y. */ + } bit; + } OUT_DSCR_CH0; + + union { + __IOM uint32_t reg; /*!< TX CH0 last dscr addr register */ + + struct { + __IM uint32_t OUTLINK_DSCR_BF0_CH0 : 32; /*!< The address of the last outlink descriptor's next address y-1. */ + } bit; + } OUT_DSCR_BF0_CH0; + + union { + __IOM uint32_t reg; /*!< TX CH0 second-to-last dscr addr register */ + + struct { + __IM uint32_t OUTLINK_DSCR_BF1_CH0 : 32; /*!< The address of the second-to-last outlink descriptor's next + address y-2. */ + } bit; + } OUT_DSCR_BF1_CH0; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t reg; /*!< TX CH0 arb register */ + + struct { + __IOM uint32_t OUT_ARB_TOKEN_NUM_CH0 : 4; /*!< Set the max number of token count of arbiter */ + __IOM uint32_t EXTER_OUT_ARB_PRIORITY_CH0 : 2;/*!< Set the priority of channel */ + uint32_t : 26; + } bit; + } OUT_ARB_CH0; + + union { + __IOM uint32_t reg; /*!< TX CH0 reorder status register */ + + struct { + __IM uint32_t OUTFIFO_RO_CNT_CH0 : 2; /*!< The register stores the 8byte number of the data in reorder + Tx FIFO for channel 0. */ + uint32_t : 4; + __IM uint32_t OUT_RO_WR_STATE_CH0 : 2; /*!< The register stores the state of read ram of reorder */ + __IM uint32_t OUT_RO_RD_STATE_CH0 : 2; /*!< The register stores the state of write ram of reorder */ + __IM uint32_t OUT_PIXEL_BYTE_CH0 : 4; /*!< the number of bytes contained in a pixel at TX channel 0: 1byte + 1: 1.5bytes 2 : 2bytes 3: 2.5bytes 4: 3bytes 5: 4bytes */ + __IM uint32_t OUT_BURST_BLOCK_NUM_CH0 : 4;/*!< the number of macro blocks contained in a burst of data at TX + channel */ + uint32_t : 14; + } bit; + } OUT_RO_STATUS_CH0; + + union { + __IOM uint32_t reg; /*!< TX CH0 reorder power config register */ + + struct { + uint32_t : 4; + __IOM uint32_t OUT_RO_RAM_FORCE_PD_CH0 : 1;/*!< dma reorder ram power down */ + __IOM uint32_t OUT_RO_RAM_FORCE_PU_CH0 : 1;/*!< dma reorder ram power up */ + __IOM uint32_t OUT_RO_RAM_CLK_FO_CH0 : 1; /*!< 1: Force to open the clock and bypass the gate-clock when accessing + the RAM in DMA. 0: A gate-clock will be used when accessing + the RAM in DMA. */ + uint32_t : 25; + } bit; + } OUT_RO_PD_CONF_CH0; + __IM uint32_t RESERVED1[2]; + + union { + __IOM uint32_t reg; /*!< tx CH0 mode enable register */ + + struct { + __IOM uint32_t OUT_TEST_MODE_ENABLE_CH0 : 1;/*!< tx CH0 test mode enable.0 : H264_DMA work in normal mode.1 : + H264_DMA work in test mode */ + uint32_t : 31; + } bit; + } OUT_MODE_ENABLE_CH0; + + union { + __IOM uint32_t reg; /*!< tx CH0 test mode yuv value register */ + + struct { + __IOM uint32_t OUT_TEST_Y_VALUE_CH0 : 8; /*!< tx CH0 test mode y value */ + __IOM uint32_t OUT_TEST_U_VALUE_CH0 : 8; /*!< tx CH0 test mode u value */ + __IOM uint32_t OUT_TEST_V_VALUE_CH0 : 8; /*!< tx CH0 test mode v value */ + uint32_t : 8; + } bit; + } OUT_MODE_YUV_CH0; + __IM uint32_t RESERVED2[4]; + + union { + __IOM uint32_t reg; /*!< TX CH0 ETM config register */ + + struct { + __IOM uint32_t OUT_ETM_EN_CH0 : 1; /*!< Set this bit to 1 to enable ETM task function */ + __IOM uint32_t OUT_ETM_LOOP_EN_CH0 : 1; /*!< when this bit is 1, dscr can be processed after receiving a + task */ + __IOM uint32_t OUT_DSCR_TASK_MAK_CH0 : 2; /*!< ETM dscr_ready maximum cache numbers */ + uint32_t : 28; + } bit; + } OUT_ETM_CONF_CH0; + __IM uint32_t RESERVED3; + + union { + __IOM uint32_t reg; /*!< tx CH0 buf len register */ + + struct { + __IM uint32_t OUT_CMDFIFO_BUF_LEN_HB_CH0 : 13;/*!< only for debug */ + uint32_t : 19; + } bit; + } OUT_BUF_LEN_CH0; + + union { + __IOM uint32_t reg; /*!< tx CH0 fifo byte cnt register */ + + struct { + __IM uint32_t OUT_CMDFIFO_OUTFIFO_BCNT_CH0 : 10;/*!< only for debug */ + uint32_t : 22; + } bit; + } OUT_FIFO_BCNT_CH0; + + union { + __IOM uint32_t reg; /*!< tx CH0 push byte cnt register */ + + struct { + __IM uint32_t OUT_CMDFIFO_PUSH_BYTECNT_CH0 : 8;/*!< only for debug */ + uint32_t : 24; + } bit; + } OUT_PUSH_BYTECNT_CH0; + + union { + __IOM uint32_t reg; /*!< tx CH0 xaddr register */ + + struct { + __IM uint32_t OUT_CMDFIFO_XADDR_CH0 : 32;/*!< only for debug */ + } bit; + } OUT_XADDR_CH0; + __IM uint32_t RESERVED4[32]; + + union { + __IOM uint32_t reg; /*!< TX CH1 config0 register */ + + struct { + __IOM uint32_t OUT_AUTO_WRBACK_CH1 : 1; /*!< Set this bit to enable automatic outlink-writeback when all + the data pointed by outlink descriptor has been received. */ + __IOM uint32_t OUT_EOF_MODE_CH1 : 1; /*!< EOF flag generation mode when receiving data. 1: EOF flag for + Tx channel 0 is generated when data need to read has been + popped from FIFO in DMA */ + __IOM uint32_t OUTDSCR_BURST_EN_CH1 : 1; /*!< Set this bit to 1 to enable INCR burst transfer for Tx channel + 0 reading link descriptor when accessing internal SRAM. */ + __IOM uint32_t OUT_ECC_AES_EN_CH1 : 1; /*!< When access address space is ecc/aes area, this bit should be + set to 1. In this case, the start address of square should + be 16-bit aligned. The width of square multiply byte number + of one pixel should be 16-bit aligned. */ + __IOM uint32_t OUT_CHECK_OWNER_CH1 : 1; /*!< Set this bit to enable checking the owner attribute of the link + descriptor. */ + uint32_t : 1; + __IOM uint32_t OUT_MEM_BURST_LENGTH_CH1 : 3;/*!< Block size of Tx channel 1. 0: single 1: 16 bytes 2: 32 bytes + 3: 64 bytes 4: 128 64 bytes */ + uint32_t : 3; + __IOM uint32_t OUT_PAGE_BOUND_EN_CH1 : 1; /*!< Set this bit to 1 to make sure AXI read data don't cross the + address boundary which define by mem_burst_length */ + uint32_t : 11; + __IOM uint32_t OUT_RST_CH1 : 1; /*!< Write 1 then write 0 to this bit to reset TX channel */ + __IOM uint32_t OUT_CMD_DISABLE_CH1 : 1; /*!< Write 1 before reset and write 0 after reset */ + __IOM uint32_t OUT_ARB_WEIGHT_OPT_DIS_CH1 : 1;/*!< Set this bit to 1 to disable arbiter optimum weight function. */ + uint32_t : 5; + } bit; + } OUT_CONF0_CH1; + + union { + __IOM uint32_t reg; /*!< TX CH1 interrupt raw register */ + + struct { + __IOM uint32_t OUT_DONE_CH1_INT_RAW : 1; /*!< The raw interrupt bit turns to high level when the last data + pointed by one outlink descriptor has been transmitted + to peripherals for Tx channel 0. */ + __IOM uint32_t OUT_EOF_CH1_INT_RAW : 1; /*!< The raw interrupt bit turns to high level when the last data + pointed by one outlink descriptor has been read from memory + for Tx channel 0. */ + __IOM uint32_t OUT_DSCR_ERR_CH1_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when detecting outlink + descriptor error, including owner error, the second and + third word error of outlink descriptor for Tx channel 0. */ + __IOM uint32_t OUT_TOTAL_EOF_CH1_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when data corresponding + a outlink (includes one link descriptor or few link descriptors) + is transmitted out for Tx channel 0. */ + __IOM uint32_t OUTFIFO_OVF_L1_CH1_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when fifo is overflow. */ + __IOM uint32_t OUTFIFO_UDF_L1_CH1_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when fifo is underflow. */ + __IOM uint32_t OUTFIFO_OVF_L2_CH1_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when fifo is overflow. */ + __IOM uint32_t OUTFIFO_UDF_L2_CH1_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when fifo is underflow. */ + __IOM uint32_t OUT_DSCR_TASK_OVF_CH1_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when dscr ready task + fifo is overflow. */ + uint32_t : 23; + } bit; + } OUT_INT_RAW_CH1; + + union { + __IOM uint32_t reg; /*!< TX CH1 interrupt ena register */ + + struct { + __IOM uint32_t OUT_DONE_CH1_INT_ENA : 1; /*!< The interrupt enable bit for the OUT_DONE_CH_INT interrupt. */ + __IOM uint32_t OUT_EOF_CH1_INT_ENA : 1; /*!< The interrupt enable bit for the OUT_EOF_CH_INT interrupt. */ + __IOM uint32_t OUT_DSCR_ERR_CH1_INT_ENA : 1;/*!< The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. */ + __IOM uint32_t OUT_TOTAL_EOF_CH1_INT_ENA : 1;/*!< The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. */ + __IOM uint32_t OUTFIFO_OVF_L1_CH1_INT_ENA : 1;/*!< The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. */ + __IOM uint32_t OUTFIFO_UDF_L1_CH1_INT_ENA : 1;/*!< The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. */ + __IOM uint32_t OUTFIFO_OVF_L2_CH1_INT_ENA : 1;/*!< The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. */ + __IOM uint32_t OUTFIFO_UDF_L2_CH1_INT_ENA : 1;/*!< The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. */ + __IOM uint32_t OUT_DSCR_TASK_OVF_CH1_INT_ENA : 1;/*!< The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. */ + uint32_t : 23; + } bit; + } OUT_INT_ENA_CH1; + + union { + __IOM uint32_t reg; /*!< TX CH1 interrupt st register */ + + struct { + __IM uint32_t OUT_DONE_CH1_INT_ST : 1; /*!< The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. */ + __IM uint32_t OUT_EOF_CH1_INT_ST : 1; /*!< The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. */ + __IM uint32_t OUT_DSCR_ERR_CH1_INT_ST : 1;/*!< The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. */ + __IM uint32_t OUT_TOTAL_EOF_CH1_INT_ST : 1;/*!< The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. */ + __IM uint32_t OUTFIFO_OVF_L1_CH1_INT_ST : 1;/*!< The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. */ + __IM uint32_t OUTFIFO_UDF_L1_CH1_INT_ST : 1;/*!< The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. */ + __IM uint32_t OUTFIFO_OVF_L2_CH1_INT_ST : 1;/*!< The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. */ + __IM uint32_t OUTFIFO_UDF_L2_CH1_INT_ST : 1;/*!< The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. */ + __IM uint32_t OUT_DSCR_TASK_OVF_CH1_INT_ST : 1;/*!< The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT + interrupt. */ + uint32_t : 23; + } bit; + } OUT_INT_ST_CH1; + + union { + __IOM uint32_t reg; /*!< TX CH1 interrupt clr register */ + + struct { + __OM uint32_t OUT_DONE_CH1_INT_CLR : 1; /*!< Set this bit to clear the OUT_DONE_CH_INT interrupt. */ + __OM uint32_t OUT_EOF_CH1_INT_CLR : 1; /*!< Set this bit to clear the OUT_EOF_CH_INT interrupt. */ + __OM uint32_t OUT_DSCR_ERR_CH1_INT_CLR : 1;/*!< Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. */ + __OM uint32_t OUT_TOTAL_EOF_CH1_INT_CLR : 1;/*!< Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. */ + __OM uint32_t OUTFIFO_OVF_L1_CH1_INT_CLR : 1;/*!< Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. */ + __OM uint32_t OUTFIFO_UDF_L1_CH1_INT_CLR : 1;/*!< Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. */ + __OM uint32_t OUTFIFO_OVF_L2_CH1_INT_CLR : 1;/*!< Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. */ + __OM uint32_t OUTFIFO_UDF_L2_CH1_INT_CLR : 1;/*!< Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. */ + __OM uint32_t OUT_DSCR_TASK_OVF_CH1_INT_CLR : 1;/*!< Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. */ + uint32_t : 23; + } bit; + } OUT_INT_CLR_CH1; + + union { + __IOM uint32_t reg; /*!< TX CH1 outfifo status register */ + + struct { + __IM uint32_t OUTFIFO_FULL_L2_CH1 : 1; /*!< Tx FIFO full signal for Tx channel 1. */ + __IM uint32_t OUTFIFO_EMPTY_L2_CH1 : 1; /*!< Tx FIFO empty signal for Tx channel 1. */ + __IM uint32_t OUTFIFO_CNT_L2_CH1 : 4; /*!< The register stores the byte number of the data in Tx FIFO for + Tx channel 1. */ + __IM uint32_t OUTFIFO_FULL_L1_CH1 : 1; /*!< Tx FIFO full signal for Tx channel 1. */ + __IM uint32_t OUTFIFO_EMPTY_L1_CH1 : 1; /*!< Tx FIFO empty signal for Tx channel 1. */ + __IM uint32_t OUTFIFO_CNT_L1_CH1 : 5; /*!< The register stores the byte number of the data in Tx FIFO for + Tx channel 1. */ + uint32_t : 3; + __IM uint32_t OUTFIFO_FULL_L3_CH1 : 1; /*!< Tx FIFO full signal for Tx channel 1. */ + __IM uint32_t OUTFIFO_EMPTY_L3_CH1 : 1; /*!< Tx FIFO empty signal for Tx channel 1. */ + __IM uint32_t OUTFIFO_CNT_L3_CH1 : 2; /*!< The register stores the byte number of the data in Tx FIFO for + Tx channel 1. */ + uint32_t : 12; + } bit; + } OUTFIFO_STATUS_CH1; + + union { + __IOM uint32_t reg; /*!< TX CH1 outfifo push register */ + + struct { + __IOM uint32_t OUTFIFO_WDATA_CH1 : 10; /*!< This register stores the data that need to be pushed into DMA + Tx FIFO. */ + __IOM uint32_t OUTFIFO_PUSH_CH1 : 1; /*!< Set this bit to push data into DMA Tx FIFO. */ + uint32_t : 21; + } bit; + } OUT_PUSH_CH1; + + union { + __IOM uint32_t reg; /*!< TX CH1 out_link dscr ctrl register */ + + struct { + uint32_t : 20; + __IOM uint32_t OUTLINK_STOP_CH1 : 1; /*!< Set this bit to stop dealing with the outlink descriptors. */ + __IOM uint32_t OUTLINK_START_CH1 : 1; /*!< Set this bit to start dealing with the outlink descriptors. */ + __IOM uint32_t OUTLINK_RESTART_CH1 : 1; /*!< Set this bit to restart a new outlink from the last address. */ + __IM uint32_t OUTLINK_PARK_CH1 : 1; /*!< 1: the outlink descriptor's FSM is in idle state. 0: the outlink + descriptor's FSM is working. */ + uint32_t : 8; + } bit; + } OUT_LINK_CONF_CH1; + + union { + __IOM uint32_t reg; /*!< TX CH1 out_link dscr addr register */ + + struct { + __IOM uint32_t OUTLINK_ADDR_CH1 : 32; /*!< This register stores the first outlink descriptor's address. */ + } bit; + } OUT_LINK_ADDR_CH1; + + union { + __IOM uint32_t reg; /*!< TX CH1 state register */ + + struct { + __IM uint32_t OUTLINK_DSCR_ADDR_CH1 : 18;/*!< This register stores the current outlink descriptor's address. */ + __IM uint32_t OUT_DSCR_STATE_CH1 : 2; /*!< This register stores the current descriptor state machine state. */ + __IM uint32_t OUT_STATE_CH1 : 4; /*!< This register stores the current control module state machine + state. */ + __IM uint32_t OUT_RESET_AVAIL_CH1 : 1; /*!< This register indicate that if the channel reset is safety. */ + uint32_t : 7; + } bit; + } OUT_STATE_CH1; + + union { + __IOM uint32_t reg; /*!< TX CH1 eof des addr register */ + + struct { + __IM uint32_t OUT_EOF_DES_ADDR_CH1 : 32; /*!< This register stores the address of the outlink descriptor when + the EOF bit in this descriptor is 1. */ + } bit; + } OUT_EOF_DES_ADDR_CH1; + + union { + __IOM uint32_t reg; /*!< TX CH1 next dscr addr register */ + + struct { + __IM uint32_t OUTLINK_DSCR_CH1 : 32; /*!< The address of the next outlink descriptor address y. */ + } bit; + } OUT_DSCR_CH1; + + union { + __IOM uint32_t reg; /*!< TX CH1 last dscr addr register */ + + struct { + __IM uint32_t OUTLINK_DSCR_BF0_CH1 : 32; /*!< The address of the last outlink descriptor's next address y-1. */ + } bit; + } OUT_DSCR_BF0_CH1; + + union { + __IOM uint32_t reg; /*!< TX CH1 second-to-last dscr addr register */ + + struct { + __IM uint32_t OUTLINK_DSCR_BF1_CH1 : 32; /*!< The address of the second-to-last outlink descriptor's next + address y-2. */ + } bit; + } OUT_DSCR_BF1_CH1; + __IM uint32_t RESERVED5; + + union { + __IOM uint32_t reg; /*!< TX CH1 arb register */ + + struct { + __IOM uint32_t OUT_ARB_TOKEN_NUM_CH1 : 4; /*!< Set the max number of token count of arbiter */ + uint32_t : 2; + __IOM uint32_t INTER_OUT_ARB_PRIORITY_CH1 : 1;/*!< Set the priority of channel */ + uint32_t : 25; + } bit; + } OUT_ARB_CH1; + __IM uint32_t RESERVED6[10]; + + union { + __IOM uint32_t reg; /*!< TX CH1 ETM config register */ + + struct { + __IOM uint32_t OUT_ETM_EN_CH1 : 1; /*!< Set this bit to 1 to enable ETM task function */ + __IOM uint32_t OUT_ETM_LOOP_EN_CH1 : 1; /*!< when this bit is 1, dscr can be processed after receiving a + task */ + __IOM uint32_t OUT_DSCR_TASK_MAK_CH1 : 2; /*!< ETM dscr_ready maximum cache numbers */ + uint32_t : 28; + } bit; + } OUT_ETM_CONF_CH1; + __IM uint32_t RESERVED7; + + union { + __IOM uint32_t reg; /*!< tx CH1 buf len register */ + + struct { + __IM uint32_t OUT_CMDFIFO_BUF_LEN_HB_CH1 : 13;/*!< only for debug */ + uint32_t : 19; + } bit; + } OUT_BUF_LEN_CH1; + + union { + __IOM uint32_t reg; /*!< tx CH1 fifo byte cnt register */ + + struct { + __IM uint32_t OUT_CMDFIFO_OUTFIFO_BCNT_CH1 : 10;/*!< only for debug */ + uint32_t : 22; + } bit; + } OUT_FIFO_BCNT_CH1; + + union { + __IOM uint32_t reg; /*!< tx CH1 push byte cnt register */ + + struct { + __IM uint32_t OUT_CMDFIFO_PUSH_BYTECNT_CH1 : 8;/*!< only for debug */ + uint32_t : 24; + } bit; + } OUT_PUSH_BYTECNT_CH1; + + union { + __IOM uint32_t reg; /*!< tx CH1 xaddr register */ + + struct { + __IM uint32_t OUT_CMDFIFO_XADDR_CH1 : 32;/*!< only for debug */ + } bit; + } OUT_XADDR_CH1; + __IM uint32_t RESERVED8[32]; + + union { + __IOM uint32_t reg; /*!< TX CH2 config0 register */ + + struct { + __IOM uint32_t OUT_AUTO_WRBACK_CH2 : 1; /*!< Set this bit to enable automatic outlink-writeback when all + the data pointed by outlink descriptor has been received. */ + __IOM uint32_t OUT_EOF_MODE_CH2 : 1; /*!< EOF flag generation mode when receiving data. 1: EOF flag for + Tx channel 0 is generated when data need to read has been + popped from FIFO in DMA */ + __IOM uint32_t OUTDSCR_BURST_EN_CH2 : 1; /*!< Set this bit to 1 to enable INCR burst transfer for Tx channel + 0 reading link descriptor when accessing internal SRAM. */ + __IOM uint32_t OUT_ECC_AES_EN_CH2 : 1; /*!< When access address space is ecc/aes area, this bit should be + set to 1. In this case, the start address of square should + be 16-bit aligned. The width of square multiply byte number + of one pixel should be 16-bit aligned. */ + __IOM uint32_t OUT_CHECK_OWNER_CH2 : 1; /*!< Set this bit to enable checking the owner attribute of the link + descriptor. */ + uint32_t : 1; + __IOM uint32_t OUT_MEM_BURST_LENGTH_CH2 : 3;/*!< Block size of Tx channel 2. 0: single 1: 16 bytes 2: 32 bytes + 3: 64 bytes 4: 128 bytes */ + uint32_t : 3; + __IOM uint32_t OUT_PAGE_BOUND_EN_CH2 : 1; /*!< Set this bit to 1 to make sure AXI read data don't cross the + address boundary which define by mem_burst_length */ + uint32_t : 11; + __IOM uint32_t OUT_RST_CH2 : 1; /*!< Write 1 then write 0 to this bit to reset TX channel */ + __IOM uint32_t OUT_CMD_DISABLE_CH2 : 1; /*!< Write 1 before reset and write 0 after reset */ + __IOM uint32_t OUT_ARB_WEIGHT_OPT_DIS_CH2 : 1;/*!< Set this bit to 1 to disable arbiter optimum weight function. */ + uint32_t : 5; + } bit; + } OUT_CONF0_CH2; + + union { + __IOM uint32_t reg; /*!< TX CH2 interrupt raw register */ + + struct { + __IOM uint32_t OUT_DONE_CH2_INT_RAW : 1; /*!< The raw interrupt bit turns to high level when the last data + pointed by one outlink descriptor has been transmitted + to peripherals for Tx channel 0. */ + __IOM uint32_t OUT_EOF_CH2_INT_RAW : 1; /*!< The raw interrupt bit turns to high level when the last data + pointed by one outlink descriptor has been read from memory + for Tx channel 0. */ + __IOM uint32_t OUT_DSCR_ERR_CH2_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when detecting outlink + descriptor error, including owner error, the second and + third word error of outlink descriptor for Tx channel 0. */ + __IOM uint32_t OUT_TOTAL_EOF_CH2_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when data corresponding + a outlink (includes one link descriptor or few link descriptors) + is transmitted out for Tx channel 0. */ + __IOM uint32_t OUTFIFO_OVF_L1_CH2_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when fifo is overflow. */ + __IOM uint32_t OUTFIFO_UDF_L1_CH2_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when fifo is underflow. */ + __IOM uint32_t OUTFIFO_OVF_L2_CH2_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when fifo is overflow. */ + __IOM uint32_t OUTFIFO_UDF_L2_CH2_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when fifo is underflow. */ + __IOM uint32_t OUT_DSCR_TASK_OVF_CH2_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when dscr ready task + fifo is overflow. */ + uint32_t : 23; + } bit; + } OUT_INT_RAW_CH2; + + union { + __IOM uint32_t reg; /*!< TX CH2 interrupt ena register */ + + struct { + __IOM uint32_t OUT_DONE_CH2_INT_ENA : 1; /*!< The interrupt enable bit for the OUT_DONE_CH_INT interrupt. */ + __IOM uint32_t OUT_EOF_CH2_INT_ENA : 1; /*!< The interrupt enable bit for the OUT_EOF_CH_INT interrupt. */ + __IOM uint32_t OUT_DSCR_ERR_CH2_INT_ENA : 1;/*!< The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. */ + __IOM uint32_t OUT_TOTAL_EOF_CH2_INT_ENA : 1;/*!< The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. */ + __IOM uint32_t OUTFIFO_OVF_L1_CH2_INT_ENA : 1;/*!< The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. */ + __IOM uint32_t OUTFIFO_UDF_L1_CH2_INT_ENA : 1;/*!< The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. */ + __IOM uint32_t OUTFIFO_OVF_L2_CH2_INT_ENA : 1;/*!< The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. */ + __IOM uint32_t OUTFIFO_UDF_L2_CH2_INT_ENA : 1;/*!< The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. */ + __IOM uint32_t OUT_DSCR_TASK_OVF_CH2_INT_ENA : 1;/*!< The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. */ + uint32_t : 23; + } bit; + } OUT_INT_ENA_CH2; + + union { + __IOM uint32_t reg; /*!< TX CH2 interrupt st register */ + + struct { + __IM uint32_t OUT_DONE_CH2_INT_ST : 1; /*!< The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. */ + __IM uint32_t OUT_EOF_CH2_INT_ST : 1; /*!< The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. */ + __IM uint32_t OUT_DSCR_ERR_CH2_INT_ST : 1;/*!< The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. */ + __IM uint32_t OUT_TOTAL_EOF_CH2_INT_ST : 1;/*!< The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. */ + __IM uint32_t OUTFIFO_OVF_L1_CH2_INT_ST : 1;/*!< The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. */ + __IM uint32_t OUTFIFO_UDF_L1_CH2_INT_ST : 1;/*!< The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. */ + __IM uint32_t OUTFIFO_OVF_L2_CH2_INT_ST : 1;/*!< The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. */ + __IM uint32_t OUTFIFO_UDF_L2_CH2_INT_ST : 1;/*!< The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. */ + __IM uint32_t OUT_DSCR_TASK_OVF_CH2_INT_ST : 1;/*!< The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT + interrupt. */ + uint32_t : 23; + } bit; + } OUT_INT_ST_CH2; + + union { + __IOM uint32_t reg; /*!< TX CH2 interrupt clr register */ + + struct { + __OM uint32_t OUT_DONE_CH2_INT_CLR : 1; /*!< Set this bit to clear the OUT_DONE_CH_INT interrupt. */ + __OM uint32_t OUT_EOF_CH2_INT_CLR : 1; /*!< Set this bit to clear the OUT_EOF_CH_INT interrupt. */ + __OM uint32_t OUT_DSCR_ERR_CH2_INT_CLR : 1;/*!< Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. */ + __OM uint32_t OUT_TOTAL_EOF_CH2_INT_CLR : 1;/*!< Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. */ + __OM uint32_t OUTFIFO_OVF_L1_CH2_INT_CLR : 1;/*!< Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. */ + __OM uint32_t OUTFIFO_UDF_L1_CH2_INT_CLR : 1;/*!< Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. */ + __OM uint32_t OUTFIFO_OVF_L2_CH2_INT_CLR : 1;/*!< Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. */ + __OM uint32_t OUTFIFO_UDF_L2_CH2_INT_CLR : 1;/*!< Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. */ + __OM uint32_t OUT_DSCR_TASK_OVF_CH2_INT_CLR : 1;/*!< Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. */ + uint32_t : 23; + } bit; + } OUT_INT_CLR_CH2; + + union { + __IOM uint32_t reg; /*!< TX CH2 outfifo status register */ + + struct { + __IM uint32_t OUTFIFO_FULL_L2_CH2 : 1; /*!< Tx FIFO full signal for Tx channel 2. */ + __IM uint32_t OUTFIFO_EMPTY_L2_CH2 : 1; /*!< Tx FIFO empty signal for Tx channel 2. */ + __IM uint32_t OUTFIFO_CNT_L2_CH2 : 4; /*!< The register stores the byte number of the data in Tx FIFO for + Tx channel 2. */ + __IM uint32_t OUTFIFO_FULL_L1_CH2 : 1; /*!< Tx FIFO full signal for Tx channel 2. */ + __IM uint32_t OUTFIFO_EMPTY_L1_CH2 : 1; /*!< Tx FIFO empty signal for Tx channel 2. */ + __IM uint32_t OUTFIFO_CNT_L1_CH2 : 5; /*!< The register stores the byte number of the data in Tx FIFO for + Tx channel 2. */ + uint32_t : 3; + __IM uint32_t OUTFIFO_FULL_L3_CH2 : 1; /*!< Tx FIFO full signal for Tx channel 2. */ + __IM uint32_t OUTFIFO_EMPTY_L3_CH2 : 1; /*!< Tx FIFO empty signal for Tx channel 2. */ + __IM uint32_t OUTFIFO_CNT_L3_CH2 : 2; /*!< The register stores the byte number of the data in Tx FIFO for + Tx channel 2. */ + uint32_t : 12; + } bit; + } OUTFIFO_STATUS_CH2; + + union { + __IOM uint32_t reg; /*!< TX CH2 outfifo push register */ + + struct { + __IOM uint32_t OUTFIFO_WDATA_CH2 : 10; /*!< This register stores the data that need to be pushed into DMA + Tx FIFO. */ + __IOM uint32_t OUTFIFO_PUSH_CH2 : 1; /*!< Set this bit to push data into DMA Tx FIFO. */ + uint32_t : 21; + } bit; + } OUT_PUSH_CH2; + + union { + __IOM uint32_t reg; /*!< TX CH2 out_link dscr ctrl register */ + + struct { + uint32_t : 20; + __IOM uint32_t OUTLINK_STOP_CH2 : 1; /*!< Set this bit to stop dealing with the outlink descriptors. */ + __IOM uint32_t OUTLINK_START_CH2 : 1; /*!< Set this bit to start dealing with the outlink descriptors. */ + __IOM uint32_t OUTLINK_RESTART_CH2 : 1; /*!< Set this bit to restart a new outlink from the last address. */ + __IM uint32_t OUTLINK_PARK_CH2 : 1; /*!< 1: the outlink descriptor's FSM is in idle state. 0: the outlink + descriptor's FSM is working. */ + uint32_t : 8; + } bit; + } OUT_LINK_CONF_CH2; + + union { + __IOM uint32_t reg; /*!< TX CH2 out_link dscr addr register */ + + struct { + __IOM uint32_t OUTLINK_ADDR_CH2 : 32; /*!< This register stores the first outlink descriptor's address. */ + } bit; + } OUT_LINK_ADDR_CH2; + + union { + __IOM uint32_t reg; /*!< TX CH2 state register */ + + struct { + __IM uint32_t OUTLINK_DSCR_ADDR_CH2 : 18;/*!< This register stores the current outlink descriptor's address. */ + __IM uint32_t OUT_DSCR_STATE_CH2 : 2; /*!< This register stores the current descriptor state machine state. */ + __IM uint32_t OUT_STATE_CH2 : 4; /*!< This register stores the current control module state machine + state. */ + __IM uint32_t OUT_RESET_AVAIL_CH2 : 1; /*!< This register indicate that if the channel reset is safety. */ + uint32_t : 7; + } bit; + } OUT_STATE_CH2; + + union { + __IOM uint32_t reg; /*!< TX CH2 eof des addr register */ + + struct { + __IM uint32_t OUT_EOF_DES_ADDR_CH2 : 32; /*!< This register stores the address of the inlink descriptor when + the EOF bit in this descriptor is 1. */ + } bit; + } OUT_EOF_DES_ADDR_CH2; + + union { + __IOM uint32_t reg; /*!< TX CH2 next dscr addr register */ + + struct { + __IM uint32_t OUTLINK_DSCR_CH2 : 32; /*!< The address of the next outlink descriptor address y. */ + } bit; + } OUT_DSCR_CH2; + + union { + __IOM uint32_t reg; /*!< TX CH2 last dscr addr register */ + + struct { + __IM uint32_t OUTLINK_DSCR_BF0_CH2 : 32; /*!< The address of the last outlink descriptor's next address y-1. */ + } bit; + } OUT_DSCR_BF0_CH2; + + union { + __IOM uint32_t reg; /*!< TX CH2 second-to-last dscr addr register */ + + struct { + __IM uint32_t OUTLINK_DSCR_BF1_CH2 : 32; /*!< The address of the second-to-last outlink descriptor's next + address y-2. */ + } bit; + } OUT_DSCR_BF1_CH2; + __IM uint32_t RESERVED9; + + union { + __IOM uint32_t reg; /*!< TX CH2 arb register */ + + struct { + __IOM uint32_t OUT_ARB_TOKEN_NUM_CH2 : 4; /*!< Set the max number of token count of arbiter */ + uint32_t : 2; + __IOM uint32_t INTER_OUT_ARB_PRIORITY_CH2 : 1;/*!< Set the priority of channel */ + uint32_t : 25; + } bit; + } OUT_ARB_CH2; + __IM uint32_t RESERVED10[10]; + + union { + __IOM uint32_t reg; /*!< TX CH2 ETM config register */ + + struct { + __IOM uint32_t OUT_ETM_EN_CH2 : 1; /*!< Set this bit to 1 to enable ETM task function */ + __IOM uint32_t OUT_ETM_LOOP_EN_CH2 : 1; /*!< when this bit is 1, dscr can be processed after receiving a + task */ + __IOM uint32_t OUT_DSCR_TASK_MAK_CH2 : 2; /*!< ETM dscr_ready maximum cache numbers */ + uint32_t : 28; + } bit; + } OUT_ETM_CONF_CH2; + __IM uint32_t RESERVED11; + + union { + __IOM uint32_t reg; /*!< tx CH2 buf len register */ + + struct { + __IM uint32_t OUT_CMDFIFO_BUF_LEN_HB_CH2 : 13;/*!< only for debug */ + uint32_t : 19; + } bit; + } OUT_BUF_LEN_CH2; + + union { + __IOM uint32_t reg; /*!< tx CH2 fifo byte cnt register */ + + struct { + __IM uint32_t OUT_CMDFIFO_OUTFIFO_BCNT_CH2 : 10;/*!< only for debug */ + uint32_t : 22; + } bit; + } OUT_FIFO_BCNT_CH2; + + union { + __IOM uint32_t reg; /*!< tx CH2 push byte cnt register */ + + struct { + __IM uint32_t OUT_CMDFIFO_PUSH_BYTECNT_CH2 : 8;/*!< only for debug */ + uint32_t : 24; + } bit; + } OUT_PUSH_BYTECNT_CH2; + + union { + __IOM uint32_t reg; /*!< tx CH2 xaddr register */ + + struct { + __IM uint32_t OUT_CMDFIFO_XADDR_CH2 : 32;/*!< only for debug */ + } bit; + } OUT_XADDR_CH2; + __IM uint32_t RESERVED12[32]; + + union { + __IOM uint32_t reg; /*!< TX CH3 config0 register */ + + struct { + __IOM uint32_t OUT_AUTO_WRBACK_CH3 : 1; /*!< Set this bit to enable automatic outlink-writeback when all + the data pointed by outlink descriptor has been received. */ + __IOM uint32_t OUT_EOF_MODE_CH3 : 1; /*!< EOF flag generation mode when receiving data. 1: EOF flag for + Tx channel 0 is generated when data need to read has been + popped from FIFO in DMA */ + __IOM uint32_t OUTDSCR_BURST_EN_CH3 : 1; /*!< Set this bit to 1 to enable INCR burst transfer for Tx channel + 0 reading link descriptor when accessing internal SRAM. */ + __IOM uint32_t OUT_ECC_AES_EN_CH3 : 1; /*!< When access address space is ecc/aes area, this bit should be + set to 1. In this case, the start address of square should + be 16-bit aligned. The width of square multiply byte number + of one pixel should be 16-bit aligned. */ + __IOM uint32_t OUT_CHECK_OWNER_CH3 : 1; /*!< Set this bit to enable checking the owner attribute of the link + descriptor. */ + uint32_t : 1; + __IOM uint32_t OUT_MEM_BURST_LENGTH_CH3 : 3;/*!< Block size of Tx channel 3. 0: single 1: 16 bytes 2: 32 bytes + 3: 64 bytes 4: 128 bytes */ + uint32_t : 3; + __IOM uint32_t OUT_PAGE_BOUND_EN_CH3 : 1; /*!< Set this bit to 1 to make sure AXI read data don't cross the + address boundary which define by mem_burst_length */ + uint32_t : 13; + __IOM uint32_t OUT_ARB_WEIGHT_OPT_DIS_CH3 : 1;/*!< Set this bit to 1 to disable arbiter optimum weight function. */ + uint32_t : 5; + } bit; + } OUT_CONF0_CH3; + + union { + __IOM uint32_t reg; /*!< TX CH3 interrupt raw register */ + + struct { + __IOM uint32_t OUT_DONE_CH3_INT_RAW : 1; /*!< The raw interrupt bit turns to high level when the last data + pointed by one outlink descriptor has been transmitted + to peripherals for Tx channel 0. */ + __IOM uint32_t OUT_EOF_CH3_INT_RAW : 1; /*!< The raw interrupt bit turns to high level when the last data + pointed by one outlink descriptor has been read from memory + for Tx channel 0. */ + __IOM uint32_t OUT_DSCR_ERR_CH3_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when detecting outlink + descriptor error, including owner error, the second and + third word error of outlink descriptor for Tx channel 0. */ + __IOM uint32_t OUT_TOTAL_EOF_CH3_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when data corresponding + a outlink (includes one link descriptor or few link descriptors) + is transmitted out for Tx channel 0. */ + __IOM uint32_t OUTFIFO_OVF_L1_CH3_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when fifo is overflow. */ + __IOM uint32_t OUTFIFO_UDF_L1_CH3_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when fifo is underflow. */ + __IOM uint32_t OUTFIFO_OVF_L2_CH3_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when fifo is overflow. */ + __IOM uint32_t OUTFIFO_UDF_L2_CH3_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when fifo is underflow. */ + __IOM uint32_t OUT_DSCR_TASK_OVF_CH3_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when dscr ready task + fifo is overflow. */ + uint32_t : 23; + } bit; + } OUT_INT_RAW_CH3; + + union { + __IOM uint32_t reg; /*!< TX CH3 interrupt ena register */ + + struct { + __IOM uint32_t OUT_DONE_CH3_INT_ENA : 1; /*!< The interrupt enable bit for the OUT_DONE_CH_INT interrupt. */ + __IOM uint32_t OUT_EOF_CH3_INT_ENA : 1; /*!< The interrupt enable bit for the OUT_EOF_CH_INT interrupt. */ + __IOM uint32_t OUT_DSCR_ERR_CH3_INT_ENA : 1;/*!< The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. */ + __IOM uint32_t OUT_TOTAL_EOF_CH3_INT_ENA : 1;/*!< The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. */ + __IOM uint32_t OUTFIFO_OVF_L1_CH3_INT_ENA : 1;/*!< The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. */ + __IOM uint32_t OUTFIFO_UDF_L1_CH3_INT_ENA : 1;/*!< The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. */ + __IOM uint32_t OUTFIFO_OVF_L2_CH3_INT_ENA : 1;/*!< The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. */ + __IOM uint32_t OUTFIFO_UDF_L2_CH3_INT_ENA : 1;/*!< The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. */ + __IOM uint32_t OUT_DSCR_TASK_OVF_CH3_INT_ENA : 1;/*!< The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. */ + uint32_t : 23; + } bit; + } OUT_INT_ENA_CH3; + + union { + __IOM uint32_t reg; /*!< TX CH3 interrupt st register */ + + struct { + __IM uint32_t OUT_DONE_CH3_INT_ST : 1; /*!< The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. */ + __IM uint32_t OUT_EOF_CH3_INT_ST : 1; /*!< The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. */ + __IM uint32_t OUT_DSCR_ERR_CH3_INT_ST : 1;/*!< The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. */ + __IM uint32_t OUT_TOTAL_EOF_CH3_INT_ST : 1;/*!< The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. */ + __IM uint32_t OUTFIFO_OVF_L1_CH3_INT_ST : 1;/*!< The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. */ + __IM uint32_t OUTFIFO_UDF_L1_CH3_INT_ST : 1;/*!< The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. */ + __IM uint32_t OUTFIFO_OVF_L2_CH3_INT_ST : 1;/*!< The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. */ + __IM uint32_t OUTFIFO_UDF_L2_CH3_INT_ST : 1;/*!< The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. */ + __IM uint32_t OUT_DSCR_TASK_OVF_CH3_INT_ST : 1;/*!< The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT + interrupt. */ + uint32_t : 23; + } bit; + } OUT_INT_ST_CH3; + + union { + __IOM uint32_t reg; /*!< TX CH3 interrupt clr register */ + + struct { + __OM uint32_t OUT_DONE_CH3_INT_CLR : 1; /*!< Set this bit to clear the OUT_DONE_CH_INT interrupt. */ + __OM uint32_t OUT_EOF_CH3_INT_CLR : 1; /*!< Set this bit to clear the OUT_EOF_CH_INT interrupt. */ + __OM uint32_t OUT_DSCR_ERR_CH3_INT_CLR : 1;/*!< Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. */ + __OM uint32_t OUT_TOTAL_EOF_CH3_INT_CLR : 1;/*!< Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. */ + __OM uint32_t OUTFIFO_OVF_L1_CH3_INT_CLR : 1;/*!< Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. */ + __OM uint32_t OUTFIFO_UDF_L1_CH3_INT_CLR : 1;/*!< Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. */ + __OM uint32_t OUTFIFO_OVF_L2_CH3_INT_CLR : 1;/*!< Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. */ + __OM uint32_t OUTFIFO_UDF_L2_CH3_INT_CLR : 1;/*!< Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. */ + __OM uint32_t OUT_DSCR_TASK_OVF_CH3_INT_CLR : 1;/*!< Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. */ + uint32_t : 23; + } bit; + } OUT_INT_CLR_CH3; + + union { + __IOM uint32_t reg; /*!< TX CH3 outfifo status register */ + + struct { + __IM uint32_t OUTFIFO_FULL_L2_CH3 : 1; /*!< Tx FIFO full signal for Tx channel 2. */ + __IM uint32_t OUTFIFO_EMPTY_L2_CH3 : 1; /*!< Tx FIFO empty signal for Tx channel 2. */ + __IM uint32_t OUTFIFO_CNT_L2_CH3 : 4; /*!< The register stores the byte number of the data in Tx FIFO for + Tx channel 2. */ + __IM uint32_t OUTFIFO_FULL_L1_CH3 : 1; /*!< Tx FIFO full signal for Tx channel 2. */ + __IM uint32_t OUTFIFO_EMPTY_L1_CH3 : 1; /*!< Tx FIFO empty signal for Tx channel 2. */ + __IM uint32_t OUTFIFO_CNT_L1_CH3 : 5; /*!< The register stores the byte number of the data in Tx FIFO for + Tx channel 2. */ + uint32_t : 3; + __IM uint32_t OUTFIFO_FULL_L3_CH3 : 1; /*!< Tx FIFO full signal for Tx channel 2. */ + __IM uint32_t OUTFIFO_EMPTY_L3_CH3 : 1; /*!< Tx FIFO empty signal for Tx channel 2. */ + __IM uint32_t OUTFIFO_CNT_L3_CH3 : 2; /*!< The register stores the byte number of the data in Tx FIFO for + Tx channel 2. */ + uint32_t : 12; + } bit; + } OUTFIFO_STATUS_CH3; + + union { + __IOM uint32_t reg; /*!< TX CH3 outfifo push register */ + + struct { + __IOM uint32_t OUTFIFO_WDATA_CH3 : 10; /*!< This register stores the data that need to be pushed into DMA + Tx FIFO. */ + __IOM uint32_t OUTFIFO_PUSH_CH3 : 1; /*!< Set this bit to push data into DMA Tx FIFO. */ + uint32_t : 21; + } bit; + } OUT_PUSH_CH3; + + union { + __IOM uint32_t reg; /*!< TX CH3 out_link dscr ctrl register */ + + struct { + uint32_t : 20; + __IOM uint32_t OUTLINK_STOP_CH3 : 1; /*!< Set this bit to stop dealing with the outlink descriptors. */ + __IOM uint32_t OUTLINK_START_CH3 : 1; /*!< Set this bit to start dealing with the outlink descriptors. */ + __IOM uint32_t OUTLINK_RESTART_CH3 : 1; /*!< Set this bit to restart a new outlink from the last address. */ + __IM uint32_t OUTLINK_PARK_CH3 : 1; /*!< 1: the outlink descriptor's FSM is in idle state. 0: the outlink + descriptor's FSM is working. */ + uint32_t : 8; + } bit; + } OUT_LINK_CONF_CH3; + + union { + __IOM uint32_t reg; /*!< TX CH3 out_link dscr addr register */ + + struct { + __IOM uint32_t OUTLINK_ADDR_CH3 : 32; /*!< This register stores the first outlink descriptor's address. */ + } bit; + } OUT_LINK_ADDR_CH3; + + union { + __IOM uint32_t reg; /*!< TX CH3 state register */ + + struct { + __IM uint32_t OUTLINK_DSCR_ADDR_CH3 : 18;/*!< This register stores the current outlink descriptor's address. */ + __IM uint32_t OUT_DSCR_STATE_CH3 : 2; /*!< This register stores the current descriptor state machine state. */ + __IM uint32_t OUT_STATE_CH3 : 4; /*!< This register stores the current control module state machine + state. */ + uint32_t : 8; + } bit; + } OUT_STATE_CH3; + + union { + __IOM uint32_t reg; /*!< TX CH3 eof des addr register */ + + struct { + __IM uint32_t OUT_EOF_DES_ADDR_CH3 : 32; /*!< This register stores the address of the inlink descriptor when + the EOF bit in this descriptor is 1. */ + } bit; + } OUT_EOF_DES_ADDR_CH3; + + union { + __IOM uint32_t reg; /*!< TX CH3 next dscr addr register */ + + struct { + __IM uint32_t OUTLINK_DSCR_CH3 : 32; /*!< The address of the next outlink descriptor address y. */ + } bit; + } OUT_DSCR_CH3; + + union { + __IOM uint32_t reg; /*!< TX CH3 last dscr addr register */ + + struct { + __IM uint32_t OUTLINK_DSCR_BF0_CH3 : 32; /*!< The address of the last outlink descriptor's next address y-1. */ + } bit; + } OUT_DSCR_BF0_CH3; + + union { + __IOM uint32_t reg; /*!< TX CH3 second-to-last dscr addr register */ + + struct { + __IM uint32_t OUTLINK_DSCR_BF1_CH3 : 32; /*!< The address of the second-to-last outlink descriptor's next + address y-2. */ + } bit; + } OUT_DSCR_BF1_CH3; + __IM uint32_t RESERVED13; + + union { + __IOM uint32_t reg; /*!< TX CH3 arb register */ + + struct { + __IOM uint32_t OUT_ARB_TOKEN_NUM_CH3 : 4; /*!< Set the max number of token count of arbiter */ + __IOM uint32_t EXTER_OUT_ARB_PRIORITY_CH3 : 2;/*!< Set the priority of channel */ + uint32_t : 26; + } bit; + } OUT_ARB_CH3; + __IM uint32_t RESERVED14[10]; + + union { + __IOM uint32_t reg; /*!< TX CH3 ETM config register */ + + struct { + __IOM uint32_t OUT_ETM_EN_CH3 : 1; /*!< Set this bit to 1 to enable ETM task function */ + __IOM uint32_t OUT_ETM_LOOP_EN_CH3 : 1; /*!< when this bit is 1, dscr can be processed after receiving a + task */ + __IOM uint32_t OUT_DSCR_TASK_MAK_CH3 : 2; /*!< ETM dscr_ready maximum cache numbers */ + uint32_t : 28; + } bit; + } OUT_ETM_CONF_CH3; + __IM uint32_t RESERVED15; + + union { + __IOM uint32_t reg; /*!< tx CH3 buf len register */ + + struct { + __IM uint32_t OUT_CMDFIFO_BUF_LEN_HB_CH3 : 13;/*!< only for debug */ + uint32_t : 19; + } bit; + } OUT_BUF_LEN_CH3; + + union { + __IOM uint32_t reg; /*!< tx CH3 fifo byte cnt register */ + + struct { + __IM uint32_t OUT_CMDFIFO_OUTFIFO_BCNT_CH3 : 10;/*!< only for debug */ + uint32_t : 22; + } bit; + } OUT_FIFO_BCNT_CH3; + + union { + __IOM uint32_t reg; /*!< tx CH3 push byte cnt register */ + + struct { + __IM uint32_t OUT_CMDFIFO_PUSH_BYTECNT_CH3 : 8;/*!< only for debug */ + uint32_t : 24; + } bit; + } OUT_PUSH_BYTECNT_CH3; + + union { + __IOM uint32_t reg; /*!< tx CH3 xaddr register */ + + struct { + __IM uint32_t OUT_CMDFIFO_XADDR_CH3 : 32;/*!< only for debug */ + } bit; + } OUT_XADDR_CH3; + + union { + __IOM uint32_t reg; /*!< tx CH3 block buf len register */ + + struct { + __IM uint32_t OUT_BLOCK_BUF_LEN_CH3 : 28;/*!< only for debug */ + uint32_t : 4; + } bit; + } OUT_BLOCK_BUF_LEN_CH3; + __IM uint32_t RESERVED16[31]; + + union { + __IOM uint32_t reg; /*!< TX CH4 config0 register */ + + struct { + __IOM uint32_t OUT_AUTO_WRBACK_CH4 : 1; /*!< Set this bit to enable automatic outlink-writeback when all + the data pointed by outlink descriptor has been received. */ + __IOM uint32_t OUT_EOF_MODE_CH4 : 1; /*!< EOF flag generation mode when receiving data. 1: EOF flag for + Tx channel 0 is generated when data need to read has been + popped from FIFO in DMA */ + __IOM uint32_t OUTDSCR_BURST_EN_CH4 : 1; /*!< Set this bit to 1 to enable INCR burst transfer for Tx channel + 0 reading link descriptor when accessing internal SRAM. */ + __IOM uint32_t OUT_ECC_AES_EN_CH4 : 1; /*!< When access address space is ecc/aes area, this bit should be + set to 1. In this case, the start address of square should + be 16-bit aligned. The width of square multiply byte number + of one pixel should be 16-bit aligned. */ + __IOM uint32_t OUT_CHECK_OWNER_CH4 : 1; /*!< Set this bit to enable checking the owner attribute of the link + descriptor. */ + uint32_t : 1; + __IOM uint32_t OUT_MEM_BURST_LENGTH_CH4 : 3;/*!< Block size of Tx channel 4. 0: single 1: 16 bytes 2: 32 bytes + 3: 64 bytes 4: 128 bytes */ + uint32_t : 3; + __IOM uint32_t OUT_PAGE_BOUND_EN_CH4 : 1; /*!< Set this bit to 1 to make sure AXI read data don't cross the + address boundary which define by mem_burst_length */ + uint32_t : 13; + __IOM uint32_t OUT_ARB_WEIGHT_OPT_DIS_CH4 : 1;/*!< Set this bit to 1 to disable arbiter optimum weight function. */ + uint32_t : 5; + } bit; + } OUT_CONF0_CH4; + + union { + __IOM uint32_t reg; /*!< TX CH4 interrupt raw register */ + + struct { + __IOM uint32_t OUT_DONE_CH4_INT_RAW : 1; /*!< The raw interrupt bit turns to high level when the last data + pointed by one outlink descriptor has been transmitted + to peripherals for Tx channel 0. */ + __IOM uint32_t OUT_EOF_CH4_INT_RAW : 1; /*!< The raw interrupt bit turns to high level when the last data + pointed by one outlink descriptor has been read from memory + for Tx channel 0. */ + __IOM uint32_t OUT_DSCR_ERR_CH4_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when detecting outlink + descriptor error, including owner error, the second and + third word error of outlink descriptor for Tx channel 0. */ + __IOM uint32_t OUT_TOTAL_EOF_CH4_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when data corresponding + a outlink (includes one link descriptor or few link descriptors) + is transmitted out for Tx channel 0. */ + __IOM uint32_t OUTFIFO_OVF_L1_CH4_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when fifo is overflow. */ + __IOM uint32_t OUTFIFO_UDF_L1_CH4_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when fifo is underflow. */ + __IOM uint32_t OUTFIFO_OVF_L2_CH4_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when fifo is overflow. */ + __IOM uint32_t OUTFIFO_UDF_L2_CH4_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when fifo is underflow. */ + __IOM uint32_t OUT_DSCR_TASK_OVF_CH4_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when dscr ready task + fifo is overflow. */ + uint32_t : 23; + } bit; + } OUT_INT_RAW_CH4; + + union { + __IOM uint32_t reg; /*!< TX CH4 interrupt ena register */ + + struct { + __IOM uint32_t OUT_DONE_CH4_INT_ENA : 1; /*!< The interrupt enable bit for the OUT_DONE_CH_INT interrupt. */ + __IOM uint32_t OUT_EOF_CH4_INT_ENA : 1; /*!< The interrupt enable bit for the OUT_EOF_CH_INT interrupt. */ + __IOM uint32_t OUT_DSCR_ERR_CH4_INT_ENA : 1;/*!< The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. */ + __IOM uint32_t OUT_TOTAL_EOF_CH4_INT_ENA : 1;/*!< The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. */ + __IOM uint32_t OUTFIFO_OVF_L1_CH4_INT_ENA : 1;/*!< The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. */ + __IOM uint32_t OUTFIFO_UDF_L1_CH4_INT_ENA : 1;/*!< The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. */ + __IOM uint32_t OUTFIFO_OVF_L2_CH4_INT_ENA : 1;/*!< The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. */ + __IOM uint32_t OUTFIFO_UDF_L2_CH4_INT_ENA : 1;/*!< The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. */ + __IOM uint32_t OUT_DSCR_TASK_OVF_CH4_INT_ENA : 1;/*!< The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. */ + uint32_t : 23; + } bit; + } OUT_INT_ENA_CH4; + + union { + __IOM uint32_t reg; /*!< TX CH4 interrupt st register */ + + struct { + __IM uint32_t OUT_DONE_CH4_INT_ST : 1; /*!< The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. */ + __IM uint32_t OUT_EOF_CH4_INT_ST : 1; /*!< The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. */ + __IM uint32_t OUT_DSCR_ERR_CH4_INT_ST : 1;/*!< The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. */ + __IM uint32_t OUT_TOTAL_EOF_CH4_INT_ST : 1;/*!< The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. */ + __IM uint32_t OUTFIFO_OVF_L1_CH4_INT_ST : 1;/*!< The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. */ + __IM uint32_t OUTFIFO_UDF_L1_CH4_INT_ST : 1;/*!< The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. */ + __IM uint32_t OUTFIFO_OVF_L2_CH4_INT_ST : 1;/*!< The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. */ + __IM uint32_t OUTFIFO_UDF_L2_CH4_INT_ST : 1;/*!< The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. */ + __IM uint32_t OUT_DSCR_TASK_OVF_CH4_INT_ST : 1;/*!< The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT + interrupt. */ + uint32_t : 23; + } bit; + } OUT_INT_ST_CH4; + + union { + __IOM uint32_t reg; /*!< TX CH4 interrupt clr register */ + + struct { + __OM uint32_t OUT_DONE_CH4_INT_CLR : 1; /*!< Set this bit to clear the OUT_DONE_CH_INT interrupt. */ + __OM uint32_t OUT_EOF_CH4_INT_CLR : 1; /*!< Set this bit to clear the OUT_EOF_CH_INT interrupt. */ + __OM uint32_t OUT_DSCR_ERR_CH4_INT_CLR : 1;/*!< Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. */ + __OM uint32_t OUT_TOTAL_EOF_CH4_INT_CLR : 1;/*!< Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. */ + __OM uint32_t OUTFIFO_OVF_L1_CH4_INT_CLR : 1;/*!< Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. */ + __OM uint32_t OUTFIFO_UDF_L1_CH4_INT_CLR : 1;/*!< Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. */ + __OM uint32_t OUTFIFO_OVF_L2_CH4_INT_CLR : 1;/*!< Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. */ + __OM uint32_t OUTFIFO_UDF_L2_CH4_INT_CLR : 1;/*!< Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. */ + __OM uint32_t OUT_DSCR_TASK_OVF_CH4_INT_CLR : 1;/*!< Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. */ + uint32_t : 23; + } bit; + } OUT_INT_CLR_CH4; + + union { + __IOM uint32_t reg; /*!< TX CH4 outfifo status register */ + + struct { + __IM uint32_t OUTFIFO_FULL_L2_CH4 : 1; /*!< Tx FIFO full signal for Tx channel 2. */ + __IM uint32_t OUTFIFO_EMPTY_L2_CH4 : 1; /*!< Tx FIFO empty signal for Tx channel 2. */ + __IM uint32_t OUTFIFO_CNT_L2_CH4 : 4; /*!< The register stores the byte number of the data in Tx FIFO for + Tx channel 2. */ + __IM uint32_t OUTFIFO_FULL_L1_CH4 : 1; /*!< Tx FIFO full signal for Tx channel 2. */ + __IM uint32_t OUTFIFO_EMPTY_L1_CH4 : 1; /*!< Tx FIFO empty signal for Tx channel 2. */ + __IM uint32_t OUTFIFO_CNT_L1_CH4 : 5; /*!< The register stores the byte number of the data in Tx FIFO for + Tx channel 2. */ + uint32_t : 3; + __IM uint32_t OUTFIFO_FULL_L3_CH4 : 1; /*!< Tx FIFO full signal for Tx channel 2. */ + __IM uint32_t OUTFIFO_EMPTY_L3_CH4 : 1; /*!< Tx FIFO empty signal for Tx channel 2. */ + __IM uint32_t OUTFIFO_CNT_L3_CH4 : 2; /*!< The register stores the byte number of the data in Tx FIFO for + Tx channel 2. */ + uint32_t : 12; + } bit; + } OUTFIFO_STATUS_CH4; + + union { + __IOM uint32_t reg; /*!< TX CH4 outfifo push register */ + + struct { + __IOM uint32_t OUTFIFO_WDATA_CH4 : 10; /*!< This register stores the data that need to be pushed into DMA + Tx FIFO. */ + __IOM uint32_t OUTFIFO_PUSH_CH4 : 1; /*!< Set this bit to push data into DMA Tx FIFO. */ + uint32_t : 21; + } bit; + } OUT_PUSH_CH4; + + union { + __IOM uint32_t reg; /*!< TX CH4 out_link dscr ctrl register */ + + struct { + uint32_t : 20; + __IOM uint32_t OUTLINK_STOP_CH4 : 1; /*!< Set this bit to stop dealing with the outlink descriptors. */ + __IOM uint32_t OUTLINK_START_CH4 : 1; /*!< Set this bit to start dealing with the outlink descriptors. */ + __IOM uint32_t OUTLINK_RESTART_CH4 : 1; /*!< Set this bit to restart a new outlink from the last address. */ + __IM uint32_t OUTLINK_PARK_CH4 : 1; /*!< 1: the outlink descriptor's FSM is in idle state. 0: the outlink + descriptor's FSM is working. */ + uint32_t : 8; + } bit; + } OUT_LINK_CONF_CH4; + + union { + __IOM uint32_t reg; /*!< TX CH4 out_link dscr addr register */ + + struct { + __IOM uint32_t OUTLINK_ADDR_CH4 : 32; /*!< This register stores the first outlink descriptor's address. */ + } bit; + } OUT_LINK_ADDR_CH4; + + union { + __IOM uint32_t reg; /*!< TX CH4 state register */ + + struct { + __IM uint32_t OUTLINK_DSCR_ADDR_CH4 : 18;/*!< This register stores the current outlink descriptor's address. */ + __IM uint32_t OUT_DSCR_STATE_CH4 : 2; /*!< This register stores the current descriptor state machine state. */ + __IM uint32_t OUT_STATE_CH4 : 4; /*!< This register stores the current control module state machine + state. */ + uint32_t : 8; + } bit; + } OUT_STATE_CH4; + + union { + __IOM uint32_t reg; /*!< TX CH4 eof des addr register */ + + struct { + __IM uint32_t OUT_EOF_DES_ADDR_CH4 : 32; /*!< This register stores the address of the inlink descriptor when + the EOF bit in this descriptor is 1. */ + } bit; + } OUT_EOF_DES_ADDR_CH4; + + union { + __IOM uint32_t reg; /*!< TX CH4 next dscr addr register */ + + struct { + __IM uint32_t OUTLINK_DSCR_CH4 : 32; /*!< The address of the next outlink descriptor address y. */ + } bit; + } OUT_DSCR_CH4; + + union { + __IOM uint32_t reg; /*!< TX CH4 last dscr addr register */ + + struct { + __IM uint32_t OUTLINK_DSCR_BF0_CH4 : 32; /*!< The address of the last outlink descriptor's next address y-1. */ + } bit; + } OUT_DSCR_BF0_CH4; + + union { + __IOM uint32_t reg; /*!< TX CH4 second-to-last dscr addr register */ + + struct { + __IM uint32_t OUTLINK_DSCR_BF1_CH4 : 32; /*!< The address of the second-to-last outlink descriptor's next + address y-2. */ + } bit; + } OUT_DSCR_BF1_CH4; + __IM uint32_t RESERVED17; + + union { + __IOM uint32_t reg; /*!< TX CH4 arb register */ + + struct { + __IOM uint32_t OUT_ARB_TOKEN_NUM_CH4 : 4; /*!< Set the max number of token count of arbiter */ + __IOM uint32_t EXTER_OUT_ARB_PRIORITY_CH4 : 2;/*!< Set the priority of channel */ + uint32_t : 26; + } bit; + } OUT_ARB_CH4; + __IM uint32_t RESERVED18[10]; + + union { + __IOM uint32_t reg; /*!< TX CH4 ETM config register */ + + struct { + __IOM uint32_t OUT_ETM_EN_CH4 : 1; /*!< Set this bit to 1 to enable ETM task function */ + __IOM uint32_t OUT_ETM_LOOP_EN_CH4 : 1; /*!< when this bit is 1, dscr can be processed after receiving a + task */ + __IOM uint32_t OUT_DSCR_TASK_MAK_CH4 : 2; /*!< ETM dscr_ready maximum cache numbers */ + uint32_t : 28; + } bit; + } OUT_ETM_CONF_CH4; + __IM uint32_t RESERVED19; + + union { + __IOM uint32_t reg; /*!< tx CH4 buf len register */ + + struct { + __IM uint32_t OUT_CMDFIFO_BUF_LEN_HB_CH4 : 13;/*!< only for debug */ + uint32_t : 19; + } bit; + } OUT_BUF_LEN_CH4; + + union { + __IOM uint32_t reg; /*!< tx CH4 fifo byte cnt register */ + + struct { + __IM uint32_t OUT_CMDFIFO_OUTFIFO_BCNT_CH4 : 10;/*!< only for debug */ + uint32_t : 22; + } bit; + } OUT_FIFO_BCNT_CH4; + + union { + __IOM uint32_t reg; /*!< tx CH4 push byte cnt register */ + + struct { + __IM uint32_t OUT_CMDFIFO_PUSH_BYTECNT_CH4 : 8;/*!< only for debug */ + uint32_t : 24; + } bit; + } OUT_PUSH_BYTECNT_CH4; + + union { + __IOM uint32_t reg; /*!< tx CH4 xaddr register */ + + struct { + __IM uint32_t OUT_CMDFIFO_XADDR_CH4 : 32;/*!< only for debug */ + } bit; + } OUT_XADDR_CH4; + + union { + __IOM uint32_t reg; /*!< tx CH4 block buf len register */ + + struct { + __IM uint32_t OUT_BLOCK_BUF_LEN_CH4 : 28;/*!< only for debug */ + uint32_t : 4; + } bit; + } OUT_BLOCK_BUF_LEN_CH4; + __IM uint32_t RESERVED20[31]; + + union { + __IOM uint32_t reg; /*!< RX CH0 config0 register */ + + struct { + uint32_t : 2; + __IOM uint32_t INDSCR_BURST_EN_CH0 : 1; /*!< Set this bit to 1 to enable INCR burst transfer for Rx transmitting + link descriptor when accessing SRAM. */ + __IOM uint32_t IN_ECC_AES_EN_CH0 : 1; /*!< When access address space is ecc/aes area, this bit should be + set to 1. In this case, the start address of square should + be 16-bit aligned. The width of square multiply byte number + of one pixel should be 16-bit aligned. */ + __IOM uint32_t IN_CHECK_OWNER_CH0 : 1; /*!< Set this bit to enable checking the owner attribute of the link + descriptor. */ + uint32_t : 1; + __IOM uint32_t IN_MEM_BURST_LENGTH_CH0 : 3;/*!< Block size of Rx channel 0. 0: single 1: 16 bytes 2: 32 bytes + 3: 64 bytes 4: 128 bytes */ + uint32_t : 3; + __IOM uint32_t IN_PAGE_BOUND_EN_CH0 : 1; /*!< Set this bit to 1 to make sure AXI write data don't cross the + address boundary which define by mem_burst_length */ + uint32_t : 11; + __IOM uint32_t IN_RST_CH0 : 1; /*!< Write 1 then write 0 to this bit to reset Rx channel */ + __IOM uint32_t IN_CMD_DISABLE_CH0 : 1; /*!< Write 1 before reset and write 0 after reset */ + __IOM uint32_t IN_ARB_WEIGHT_OPT_DIS_CH0 : 1;/*!< Set this bit to 1 to disable arbiter optimum weight function. */ + uint32_t : 5; + } bit; + } IN_CONF0_CH0; + + union { + __IOM uint32_t reg; /*!< RX CH0 interrupt raw register */ + + struct { + __IOM uint32_t IN_DONE_CH0_INT_RAW : 1; /*!< The raw interrupt bit turns to high level when the last data + pointed by one inlink descriptor has been transmitted to + peripherals for Rx channel 0. */ + __IOM uint32_t IN_SUC_EOF_CH0_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when the last data + pointed by one inlink descriptor has been received and + no data error is detected for Rx channel 0. */ + __IOM uint32_t IN_ERR_EOF_CH0_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when the last data + pointed by one inlink descriptor has been received and + data error is detected */ + __IOM uint32_t IN_DSCR_ERR_CH0_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when detecting inlink + descriptor error, including owner error, the second and + third word error of inlink descriptor for Rx channel 0. */ + __IOM uint32_t INFIFO_OVF_L1_CH0_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when fifo of Rx channel + is overflow. */ + __IOM uint32_t INFIFO_UDF_L1_CH0_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when fifo of Rx channel + is underflow. */ + __IOM uint32_t INFIFO_OVF_L2_CH0_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when fifo of Rx channel + is overflow. */ + __IOM uint32_t INFIFO_UDF_L2_CH0_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when fifo of Rx channel + is underflow. */ + __IOM uint32_t IN_DSCR_EMPTY_CH0_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when the last descriptor + is done but fifo also remain data. */ + __IOM uint32_t IN_DSCR_TASK_OVF_CH0_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when dscr ready task + fifo is overflow. */ + uint32_t : 22; + } bit; + } IN_INT_RAW_CH0; + + union { + __IOM uint32_t reg; /*!< RX CH0 interrupt ena register */ + + struct { + __IOM uint32_t IN_DONE_CH0_INT_ENA : 1; /*!< The interrupt enable bit for the IN_DONE_CH_INT interrupt. */ + __IOM uint32_t IN_SUC_EOF_CH0_INT_ENA : 1;/*!< The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. */ + __IOM uint32_t IN_ERR_EOF_CH0_INT_ENA : 1;/*!< The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. */ + __IOM uint32_t IN_DSCR_ERR_CH0_INT_ENA : 1;/*!< The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. */ + __IOM uint32_t INFIFO_OVF_L1_CH0_INT_ENA : 1;/*!< The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. */ + __IOM uint32_t INFIFO_UDF_L1_CH0_INT_ENA : 1;/*!< The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. */ + __IOM uint32_t INFIFO_OVF_L2_CH0_INT_ENA : 1;/*!< The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. */ + __IOM uint32_t INFIFO_UDF_L2_CH0_INT_ENA : 1;/*!< The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. */ + __IOM uint32_t IN_DSCR_EMPTY_CH0_INT_ENA : 1;/*!< The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. */ + __IOM uint32_t IN_DSCR_TASK_OVF_CH0_INT_ENA : 1;/*!< The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. */ + uint32_t : 22; + } bit; + } IN_INT_ENA_CH0; + + union { + __IOM uint32_t reg; /*!< RX CH0 interrupt st register */ + + struct { + __IM uint32_t IN_DONE_CH0_INT_ST : 1; /*!< The raw interrupt status bit for the IN_DONE_CH_INT interrupt. */ + __IM uint32_t IN_SUC_EOF_CH0_INT_ST : 1; /*!< The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. */ + __IM uint32_t IN_ERR_EOF_CH0_INT_ST : 1; /*!< The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. */ + __IM uint32_t IN_DSCR_ERR_CH0_INT_ST : 1;/*!< The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. */ + __IM uint32_t INFIFO_OVF_L1_CH0_INT_ST : 1;/*!< The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. */ + __IM uint32_t INFIFO_UDF_L1_CH0_INT_ST : 1;/*!< The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. */ + __IM uint32_t INFIFO_OVF_L2_CH0_INT_ST : 1;/*!< The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. */ + __IM uint32_t INFIFO_UDF_L2_CH0_INT_ST : 1;/*!< The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. */ + __IM uint32_t IN_DSCR_EMPTY_CH0_INT_ST : 1;/*!< The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. */ + __IM uint32_t IN_DSCR_TASK_OVF_CH0_INT_ST : 1;/*!< The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT + interrupt. */ + uint32_t : 22; + } bit; + } IN_INT_ST_CH0; + + union { + __IOM uint32_t reg; /*!< RX CH0 interrupt clr register */ + + struct { + __OM uint32_t IN_DONE_CH0_INT_CLR : 1; /*!< Set this bit to clear the IN_DONE_CH_INT interrupt. */ + __OM uint32_t IN_SUC_EOF_CH0_INT_CLR : 1;/*!< Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. */ + __OM uint32_t IN_ERR_EOF_CH0_INT_CLR : 1;/*!< Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. */ + __OM uint32_t IN_DSCR_ERR_CH0_INT_CLR : 1;/*!< Set this bit to clear the INDSCR_ERR_CH_INT interrupt. */ + __OM uint32_t INFIFO_OVF_L1_CH0_INT_CLR : 1;/*!< Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. */ + __OM uint32_t INFIFO_UDF_L1_CH0_INT_CLR : 1;/*!< Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. */ + __OM uint32_t INFIFO_OVF_L2_CH0_INT_CLR : 1;/*!< Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. */ + __OM uint32_t INFIFO_UDF_L2_CH0_INT_CLR : 1;/*!< Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. */ + __OM uint32_t IN_DSCR_EMPTY_CH0_INT_CLR : 1;/*!< Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. */ + __OM uint32_t IN_DSCR_TASK_OVF_CH0_INT_CLR : 1;/*!< Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. */ + uint32_t : 22; + } bit; + } IN_INT_CLR_CH0; + + union { + __IOM uint32_t reg; /*!< RX CH0 INFIFO status register */ + + struct { + __IM uint32_t INFIFO_FULL_L2_CH0 : 1; /*!< Rx FIFO full signal for Rx channel. */ + __IM uint32_t INFIFO_EMPTY_L2_CH0 : 1; /*!< Rx FIFO empty signal for Rx channel. */ + __IM uint32_t INFIFO_CNT_L2_CH0 : 4; /*!< The register stores the byte number of the data in Rx FIFO for + Rx channel. */ + __IM uint32_t INFIFO_FULL_L1_CH0 : 1; /*!< Tx FIFO full signal for Tx channel 0. */ + __IM uint32_t INFIFO_EMPTY_L1_CH0 : 1; /*!< Tx FIFO empty signal for Tx channel 0. */ + __IM uint32_t INFIFO_CNT_L1_CH0 : 5; /*!< The register stores the byte number of the data in Tx FIFO for + Tx channel 0. */ + uint32_t : 3; + __IM uint32_t INFIFO_FULL_L3_CH0 : 1; /*!< Tx FIFO full signal for Tx channel 0. */ + __IM uint32_t INFIFO_EMPTY_L3_CH0 : 1; /*!< Tx FIFO empty signal for Tx channel 0. */ + __IM uint32_t INFIFO_CNT_L3_CH0 : 2; /*!< The register stores the 8byte number of the data in Tx FIFO + for Tx channel 0. */ + uint32_t : 12; + } bit; + } INFIFO_STATUS_CH0; + + union { + __IOM uint32_t reg; /*!< RX CH0 INFIFO pop register */ + + struct { + __IM uint32_t INFIFO_RDATA_CH0 : 11; /*!< This register stores the data popping from DMA Rx FIFO. */ + __IOM uint32_t INFIFO_POP_CH0 : 1; /*!< Set this bit to pop data from DMA Rx FIFO. */ + uint32_t : 20; + } bit; + } IN_POP_CH0; + + union { + __IOM uint32_t reg; /*!< RX CH0 in_link dscr ctrl register */ + + struct { + uint32_t : 20; + __IOM uint32_t INLINK_AUTO_RET_CH0 : 1; /*!< Set this bit to return to current inlink descriptor's address, + when there are some errors in current receiving data. */ + __IOM uint32_t INLINK_STOP_CH0 : 1; /*!< Set this bit to stop dealing with the inlink descriptors. */ + __IOM uint32_t INLINK_START_CH0 : 1; /*!< Set this bit to start dealing with the inlink descriptors. */ + __IOM uint32_t INLINK_RESTART_CH0 : 1; /*!< Set this bit to mount a new inlink descriptor. */ + __IM uint32_t INLINK_PARK_CH0 : 1; /*!< 1: the inlink descriptor's FSM is in idle state. 0: the inlink + descriptor's FSM is working. */ + uint32_t : 7; + } bit; + } IN_LINK_CONF_CH0; + + union { + __IOM uint32_t reg; /*!< RX CH0 in_link dscr addr register */ + + struct { + __IOM uint32_t INLINK_ADDR_CH0 : 32; /*!< This register stores the first inlink descriptor's address. */ + } bit; + } IN_LINK_ADDR_CH0; + + union { + __IOM uint32_t reg; /*!< RX CH0 state register */ + + struct { + __IM uint32_t INLINK_DSCR_ADDR_CH0 : 18; /*!< This register stores the current inlink descriptor's address. */ + __IM uint32_t IN_DSCR_STATE_CH0 : 2; /*!< This register stores the current descriptor state machine state. */ + __IM uint32_t IN_STATE_CH0 : 3; /*!< This register stores the current control module state machine + state. */ + __IM uint32_t IN_RESET_AVAIL_CH0 : 1; /*!< This register indicate that if the channel reset is safety. */ + uint32_t : 8; + } bit; + } IN_STATE_CH0; + + union { + __IOM uint32_t reg; /*!< RX CH0 eof des addr register */ + + struct { + __IM uint32_t IN_SUC_EOF_DES_ADDR_CH0 : 32;/*!< This register stores the address of the inlink descriptor when + the EOF bit in this descriptor is 1. */ + } bit; + } IN_SUC_EOF_DES_ADDR_CH0; + + union { + __IOM uint32_t reg; /*!< RX CH0 err eof des addr register */ + + struct { + __IM uint32_t IN_ERR_EOF_DES_ADDR_CH0 : 32;/*!< This register stores the address of the inlink descriptor when + there are some errors in current receiving data. */ + } bit; + } IN_ERR_EOF_DES_ADDR_CH0; + + union { + __IOM uint32_t reg; /*!< RX CH0 next dscr addr register */ + + struct { + __IM uint32_t INLINK_DSCR_CH0 : 32; /*!< The address of the next inlink descriptor address x. */ + } bit; + } IN_DSCR_CH0; + + union { + __IOM uint32_t reg; /*!< RX CH0 last dscr addr register */ + + struct { + __IM uint32_t INLINK_DSCR_BF0_CH0 : 32; /*!< The address of the last inlink descriptor's next address x-1. */ + } bit; + } IN_DSCR_BF0_CH0; + + union { + __IOM uint32_t reg; /*!< RX CH0 second-to-last dscr addr register */ + + struct { + __IM uint32_t INLINK_DSCR_BF1_CH0 : 32; /*!< The address of the second-to-last inlink descriptor's next address + x-2. */ + } bit; + } IN_DSCR_BF1_CH0; + __IM uint32_t RESERVED21; + + union { + __IOM uint32_t reg; /*!< RX CH0 arb register */ + + struct { + __IOM uint32_t IN_ARB_TOKEN_NUM_CH0 : 4; /*!< Set the max number of token count of arbiter */ + __IOM uint32_t EXTER_IN_ARB_PRIORITY_CH0 : 2;/*!< Set the priority of channel */ + __IOM uint32_t INTER_IN_ARB_PRIORITY_CH0 : 3;/*!< Set the priority of channel */ + uint32_t : 23; + } bit; + } IN_ARB_CH0; + __IM uint32_t RESERVED22; + + union { + __IOM uint32_t reg; /*!< RX CH0 reorder power config register */ + + struct { + uint32_t : 6; + __IOM uint32_t IN_RO_RAM_CLK_FO_CH0 : 1; /*!< 1: Force to open the clock and bypass the gate-clock when accessing + the RAM in DMA. 0: A gate-clock will be used when accessing + the RAM in DMA. */ + uint32_t : 25; + } bit; + } IN_RO_PD_CONF_CH0; + __IM uint32_t RESERVED23[8]; + + union { + __IOM uint32_t reg; /*!< RX CH0 ETM config register */ + + struct { + __IOM uint32_t IN_ETM_EN_CH0 : 1; /*!< Set this bit to 1 to enable ETM task function */ + __IOM uint32_t IN_ETM_LOOP_EN_CH0 : 1; /*!< when this bit is 1, dscr can be processed after receiving a + task */ + __IOM uint32_t IN_DSCR_TASK_MAK_CH0 : 2; /*!< ETM dscr_ready maximum cache numbers */ + uint32_t : 28; + } bit; + } IN_ETM_CONF_CH0; + __IM uint32_t RESERVED24[4]; + + union { + __IOM uint32_t reg; /*!< rx CH0 fifo cnt register */ + + struct { + __IM uint32_t IN_CMDFIFO_INFIFO_CNT_CH0 : 10;/*!< only for debug */ + uint32_t : 22; + } bit; + } IN_FIFO_CNT_CH0; + + union { + __IOM uint32_t reg; /*!< rx CH0 pop data cnt register */ + + struct { + __IM uint32_t IN_CMDFIFO_POP_DATA_CNT_CH0 : 8;/*!< only for debug */ + uint32_t : 24; + } bit; + } IN_POP_DATA_CNT_CH0; + + union { + __IOM uint32_t reg; /*!< rx CH0 xaddr register */ + + struct { + __IM uint32_t IN_CMDFIFO_XADDR_CH0 : 32; /*!< only for debug */ + } bit; + } IN_XADDR_CH0; + + union { + __IOM uint32_t reg; /*!< rx CH0 buf len hb rcv register */ + + struct { + __IM uint32_t IN_CMDFIFO_BUF_HB_RCV_CH0 : 29;/*!< only for debug */ + uint32_t : 3; + } bit; + } IN_BUF_HB_RCV_CH0; + __IM uint32_t RESERVED25[28]; + + union { + __IOM uint32_t reg; /*!< RX CH1 config0 register */ + + struct { + uint32_t : 2; + __IOM uint32_t INDSCR_BURST_EN_CH1 : 1; /*!< Set this bit to 1 to enable INCR burst transfer for Rx transmitting + link descriptor when accessing SRAM. */ + __IOM uint32_t IN_ECC_AES_EN_CH1 : 1; /*!< When access address space is ecc/aes area, this bit should be + set to 1. In this case, the start address of square should + be 16-bit aligned. The width of square multiply byte number + of one pixel should be 16-bit aligned. */ + __IOM uint32_t IN_CHECK_OWNER_CH1 : 1; /*!< Set this bit to enable checking the owner attribute of the link + descriptor. */ + uint32_t : 1; + __IOM uint32_t IN_MEM_BURST_LENGTH_CH1 : 3;/*!< Block size of Rx channel 1. 0: single 1: 16 bytes 2: 32 bytes + 3: 64 bytes 4: 128 bytes */ + uint32_t : 3; + __IOM uint32_t IN_PAGE_BOUND_EN_CH1 : 1; /*!< Set this bit to 1 to make sure AXI write data don't cross the + address boundary which define by mem_burst_length */ + uint32_t : 11; + __IOM uint32_t IN_RST_CH1 : 1; /*!< Write 1 then write 0 to this bit to reset Rx channel */ + __IOM uint32_t IN_CMD_DISABLE_CH1 : 1; /*!< Write 1 before reset and write 0 after reset */ + __IOM uint32_t IN_ARB_WEIGHT_OPT_DIS_CH1 : 1;/*!< Set this bit to 1 to disable arbiter optimum weight function. */ + uint32_t : 5; + } bit; + } IN_CONF0_CH1; + + union { + __IOM uint32_t reg; /*!< RX CH1 interrupt raw register */ + + struct { + __IOM uint32_t IN_DONE_CH1_INT_RAW : 1; /*!< The raw interrupt bit turns to high level when the last data + pointed by one inlink descriptor has been transmitted to + peripherals for Rx channel 1. */ + __IOM uint32_t IN_SUC_EOF_CH1_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when the last data + pointed by one inlink descriptor has been received and + no data error is detected for Rx channel 1. */ + __IOM uint32_t IN_ERR_EOF_CH1_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when the last data + pointed by one inlink descriptor has been received and + data error is detected */ + __IOM uint32_t IN_DSCR_ERR_CH1_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when detecting inlink + descriptor error, including owner error, the second and + third word error of inlink descriptor for Rx channel 1. */ + __IOM uint32_t INFIFO_OVF_L1_CH1_INT_RAW : 1;/*!< This raw interrupt bit turns to high level when fifo of Rx channel + is overflow. */ + __IOM uint32_t INFIFO_UDF_L1_CH1_INT_RAW : 1;/*!< This raw interrupt bit turns to high level when fifo of Rx channel + is underflow. */ + __IOM uint32_t INFIFO_OVF_L2_CH1_INT_RAW : 1;/*!< This raw interrupt bit turns to high level when fifo of Rx channel + is overflow. */ + __IOM uint32_t INFIFO_UDF_L2_CH1_INT_RAW : 1;/*!< This raw interrupt bit turns to high level when fifo of Rx channel + is underflow. */ + __IOM uint32_t IN_DSCR_EMPTY_CH1_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when the last descriptor + is done but fifo also remain data. */ + __IOM uint32_t IN_DSCR_TASK_OVF_CH1_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when dscr ready task + fifo is overflow. */ + uint32_t : 22; + } bit; + } IN_INT_RAW_CH1; + + union { + __IOM uint32_t reg; /*!< RX CH1 interrupt ena register */ + + struct { + __IOM uint32_t IN_DONE_CH1_INT_ENA : 1; /*!< The interrupt enable bit for the IN_DONE_CH_INT interrupt. */ + __IOM uint32_t IN_SUC_EOF_CH1_INT_ENA : 1;/*!< The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. */ + __IOM uint32_t IN_ERR_EOF_CH1_INT_ENA : 1;/*!< The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. */ + __IOM uint32_t IN_DSCR_ERR_CH1_INT_ENA : 1;/*!< The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. */ + __IOM uint32_t INFIFO_OVF_L1_CH1_INT_ENA : 1;/*!< The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. */ + __IOM uint32_t INFIFO_UDF_L1_CH1_INT_ENA : 1;/*!< The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. */ + __IOM uint32_t INFIFO_OVF_L2_CH1_INT_ENA : 1;/*!< The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. */ + __IOM uint32_t INFIFO_UDF_L2_CH1_INT_ENA : 1;/*!< The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. */ + __IOM uint32_t IN_DSCR_EMPTY_CH1_INT_ENA : 1;/*!< The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. */ + __IOM uint32_t IN_DSCR_TASK_OVF_CH1_INT_ENA : 1;/*!< The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. */ + uint32_t : 22; + } bit; + } IN_INT_ENA_CH1; + + union { + __IOM uint32_t reg; /*!< RX CH1 interrupt st register */ + + struct { + __IM uint32_t IN_DONE_CH1_INT_ST : 1; /*!< The raw interrupt status bit for the IN_DONE_CH_INT interrupt. */ + __IM uint32_t IN_SUC_EOF_CH1_INT_ST : 1; /*!< The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. */ + __IM uint32_t IN_ERR_EOF_CH1_INT_ST : 1; /*!< The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. */ + __IM uint32_t IN_DSCR_ERR_CH1_INT_ST : 1;/*!< The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. */ + __IM uint32_t INFIFO_OVF_L1_CH1_INT_ST : 1;/*!< The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. */ + __IM uint32_t INFIFO_UDF_L1_CH1_INT_ST : 1;/*!< The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. */ + __IM uint32_t INFIFO_OVF_L2_CH1_INT_ST : 1;/*!< The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. */ + __IM uint32_t INFIFO_UDF_L2_CH1_INT_ST : 1;/*!< The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. */ + __IM uint32_t IN_DSCR_EMPTY_CH1_INT_ST : 1;/*!< The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. */ + __IM uint32_t IN_DSCR_TASK_OVF_CH1_INT_ST : 1;/*!< The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT + interrupt. */ + uint32_t : 22; + } bit; + } IN_INT_ST_CH1; + + union { + __IOM uint32_t reg; /*!< RX CH1 interrupt clr register */ + + struct { + __OM uint32_t IN_DONE_CH1_INT_CLR : 1; /*!< Set this bit to clear the IN_DONE_CH_INT interrupt. */ + __OM uint32_t IN_SUC_EOF_CH1_INT_CLR : 1;/*!< Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. */ + __OM uint32_t IN_ERR_EOF_CH1_INT_CLR : 1;/*!< Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. */ + __OM uint32_t IN_DSCR_ERR_CH1_INT_CLR : 1;/*!< Set this bit to clear the INDSCR_ERR_CH_INT interrupt. */ + __OM uint32_t INFIFO_OVF_L1_CH1_INT_CLR : 1;/*!< Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. */ + __OM uint32_t INFIFO_UDF_L1_CH1_INT_CLR : 1;/*!< Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. */ + __OM uint32_t INFIFO_OVF_L2_CH1_INT_CLR : 1;/*!< Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. */ + __OM uint32_t INFIFO_UDF_L2_CH1_INT_CLR : 1;/*!< Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. */ + __OM uint32_t IN_DSCR_EMPTY_CH1_INT_CLR : 1;/*!< Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. */ + __OM uint32_t IN_DSCR_TASK_OVF_CH1_INT_CLR : 1;/*!< Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. */ + uint32_t : 22; + } bit; + } IN_INT_CLR_CH1; + + union { + __IOM uint32_t reg; /*!< RX CH1 INFIFO status register */ + + struct { + __IM uint32_t INFIFO_FULL_L2_CH1 : 1; /*!< Rx FIFO full signal for Rx channel. */ + __IM uint32_t INFIFO_EMPTY_L2_CH1 : 1; /*!< Rx FIFO empty signal for Rx channel. */ + __IM uint32_t INFIFO_CNT_L2_CH1 : 4; /*!< The register stores the byte number of the data in Rx FIFO for + Rx channel. */ + __IM uint32_t INFIFO_FULL_L1_CH1 : 1; /*!< Tx FIFO full signal for Tx channel 1. */ + __IM uint32_t INFIFO_EMPTY_L1_CH1 : 1; /*!< Tx FIFO empty signal for Tx channel 1. */ + __IM uint32_t INFIFO_CNT_L1_CH1 : 5; /*!< The register stores the byte number of the data in Tx FIFO for + Tx channel 1. */ + uint32_t : 3; + __IM uint32_t INFIFO_FULL_L3_CH1 : 1; /*!< Tx FIFO full signal for Tx channel 1. */ + __IM uint32_t INFIFO_EMPTY_L3_CH1 : 1; /*!< Tx FIFO empty signal for Tx channel 1. */ + __IM uint32_t INFIFO_CNT_L3_CH1 : 2; /*!< The register stores the byte number of the data in Tx FIFO for + Tx channel 1. */ + uint32_t : 12; + } bit; + } INFIFO_STATUS_CH1; + + union { + __IOM uint32_t reg; /*!< RX CH1 INFIFO pop register */ + + struct { + __IM uint32_t INFIFO_RDATA_CH1 : 11; /*!< This register stores the data popping from DMA Rx FIFO. */ + __IOM uint32_t INFIFO_POP_CH1 : 1; /*!< Set this bit to pop data from DMA Rx FIFO. */ + uint32_t : 20; + } bit; + } IN_POP_CH1; + + union { + __IOM uint32_t reg; /*!< RX CH1 in_link dscr ctrl register */ + + struct { + uint32_t : 20; + __IOM uint32_t INLINK_AUTO_RET_CH1 : 1; /*!< Set this bit to return to current inlink descriptor's address, + when there are some errors in current receiving data. */ + __IOM uint32_t INLINK_STOP_CH1 : 1; /*!< Set this bit to stop dealing with the inlink descriptors. */ + __IOM uint32_t INLINK_START_CH1 : 1; /*!< Set this bit to start dealing with the inlink descriptors. */ + __IOM uint32_t INLINK_RESTART_CH1 : 1; /*!< Set this bit to mount a new inlink descriptor. */ + __IM uint32_t INLINK_PARK_CH1 : 1; /*!< 1: the inlink descriptor's FSM is in idle state. 0: the inlink + descriptor's FSM is working. */ + uint32_t : 7; + } bit; + } IN_LINK_CONF_CH1; + + union { + __IOM uint32_t reg; /*!< RX CH1 in_link dscr addr register */ + + struct { + __IOM uint32_t INLINK_ADDR_CH1 : 32; /*!< This register stores the first inlink descriptor's address. */ + } bit; + } IN_LINK_ADDR_CH1; + + union { + __IOM uint32_t reg; /*!< RX CH1 state register */ + + struct { + __IM uint32_t INLINK_DSCR_ADDR_CH1 : 18; /*!< This register stores the current inlink descriptor's address. */ + __IM uint32_t IN_DSCR_STATE_CH1 : 2; /*!< This register stores the current descriptor state machine state. */ + __IM uint32_t IN_STATE_CH1 : 3; /*!< This register stores the current control module state machine + state. */ + __IM uint32_t IN_RESET_AVAIL_CH1 : 1; /*!< This register indicate that if the channel reset is safety. */ + uint32_t : 8; + } bit; + } IN_STATE_CH1; + + union { + __IOM uint32_t reg; /*!< RX CH1 eof des addr register */ + + struct { + __IM uint32_t IN_SUC_EOF_DES_ADDR_CH1 : 32;/*!< This register stores the address of the inlink descriptor when + the EOF bit in this descriptor is 1. */ + } bit; + } IN_SUC_EOF_DES_ADDR_CH1; + + union { + __IOM uint32_t reg; /*!< RX CH1 err eof des addr register */ + + struct { + __IM uint32_t IN_ERR_EOF_DES_ADDR_CH1 : 32;/*!< This register stores the address of the inlink descriptor when + there are some errors in current receiving data. */ + } bit; + } IN_ERR_EOF_DES_ADDR_CH1; + + union { + __IOM uint32_t reg; /*!< RX CH1 next dscr addr register */ + + struct { + __IM uint32_t INLINK_DSCR_CH1 : 32; /*!< The address of the next inlink descriptor address x. */ + } bit; + } IN_DSCR_CH1; + + union { + __IOM uint32_t reg; /*!< RX CH1 last dscr addr register */ + + struct { + __IM uint32_t INLINK_DSCR_BF0_CH1 : 32; /*!< The address of the last inlink descriptor's next address x-1. */ + } bit; + } IN_DSCR_BF0_CH1; + + union { + __IOM uint32_t reg; /*!< RX CH1 second-to-last dscr addr register */ + + struct { + __IM uint32_t INLINK_DSCR_BF1_CH1 : 32; /*!< The address of the second-to-last inlink descriptor's next address + x-2. */ + } bit; + } IN_DSCR_BF1_CH1; + __IM uint32_t RESERVED26; + + union { + __IOM uint32_t reg; /*!< RX CH1 arb register */ + + struct { + __IOM uint32_t IN_ARB_TOKEN_NUM_CH1 : 4; /*!< Set the max number of token count of arbiter */ + __IOM uint32_t EXTER_IN_ARB_PRIORITY_CH1 : 2;/*!< Set the priority of channel */ + __IOM uint32_t INTER_IN_ARB_PRIORITY_CH1 : 3;/*!< Set the priority of channel */ + uint32_t : 23; + } bit; + } IN_ARB_CH1; + __IM uint32_t RESERVED27; + + union { + __IOM uint32_t reg; /*!< RX CH1 ETM config register */ + + struct { + __IOM uint32_t IN_ETM_EN_CH1 : 1; /*!< Set this bit to 1 to enable ETM task function */ + __IOM uint32_t IN_ETM_LOOP_EN_CH1 : 1; /*!< when this bit is 1, dscr can be processed after receiving a + task */ + __IOM uint32_t IN_DSCR_TASK_MAK_CH1 : 2; /*!< ETM dscr_ready maximum cache numbers */ + uint32_t : 28; + } bit; + } IN_ETM_CONF_CH1; + __IM uint32_t RESERVED28[13]; + + union { + __IOM uint32_t reg; /*!< rx CH1 fifo cnt register */ + + struct { + __IM uint32_t IN_CMDFIFO_INFIFO_CNT_CH1 : 10;/*!< only for debug */ + uint32_t : 22; + } bit; + } IN_FIFO_CNT_CH1; + + union { + __IOM uint32_t reg; /*!< rx CH1 pop data cnt register */ + + struct { + __IM uint32_t IN_CMDFIFO_POP_DATA_CNT_CH1 : 8;/*!< only for debug */ + uint32_t : 24; + } bit; + } IN_POP_DATA_CNT_CH1; + + union { + __IOM uint32_t reg; /*!< rx CH1 xaddr register */ + + struct { + __IM uint32_t IN_CMDFIFO_XADDR_CH1 : 32; /*!< only for debug */ + } bit; + } IN_XADDR_CH1; + + union { + __IOM uint32_t reg; /*!< rx CH1 buf len hb rcv register */ + + struct { + __IM uint32_t IN_CMDFIFO_BUF_HB_RCV_CH1 : 29;/*!< only for debug */ + uint32_t : 3; + } bit; + } IN_BUF_HB_RCV_CH1; + __IM uint32_t RESERVED29[28]; + + union { + __IOM uint32_t reg; /*!< RX CH2 config0 register */ + + struct { + uint32_t : 2; + __IOM uint32_t INDSCR_BURST_EN_CH2 : 1; /*!< Set this bit to 1 to enable INCR burst transfer for Rx transmitting + link descriptor when accessing SRAM. */ + __IOM uint32_t IN_ECC_AES_EN_CH2 : 1; /*!< When access address space is ecc/aes area, this bit should be + set to 1. In this case, the start address of square should + be 16-bit aligned. The width of square multiply byte number + of one pixel should be 16-bit aligned. */ + __IOM uint32_t IN_CHECK_OWNER_CH2 : 1; /*!< Set this bit to enable checking the owner attribute of the link + descriptor. */ + uint32_t : 1; + __IOM uint32_t IN_MEM_BURST_LENGTH_CH2 : 3;/*!< Block size of Rx channel 2. 0: single 1: 16 bytes 2: 32 bytes + 3: 64 bytes 4: 128 bytes */ + uint32_t : 3; + __IOM uint32_t IN_PAGE_BOUND_EN_CH2 : 1; /*!< Set this bit to 1 to make sure AXI write data don't cross the + address boundary which define by mem_burst_length */ + uint32_t : 11; + __IOM uint32_t IN_RST_CH2 : 1; /*!< Write 1 then write 0 to this bit to reset Rx channel */ + __IOM uint32_t IN_CMD_DISABLE_CH2 : 1; /*!< Write 1 before reset and write 0 after reset */ + __IOM uint32_t IN_ARB_WEIGHT_OPT_DIS_CH2 : 1;/*!< Set this bit to 1 to disable arbiter optimum weight function. */ + uint32_t : 5; + } bit; + } IN_CONF0_CH2; + + union { + __IOM uint32_t reg; /*!< RX CH2 interrupt raw register */ + + struct { + __IOM uint32_t IN_DONE_CH2_INT_RAW : 1; /*!< The raw interrupt bit turns to high level when the last data + pointed by one inlink descriptor has been transmitted to + peripherals for Rx channel 1. */ + __IOM uint32_t IN_SUC_EOF_CH2_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when the last data + pointed by one inlink descriptor has been received and + no data error is detected for Rx channel 1. */ + __IOM uint32_t IN_ERR_EOF_CH2_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when the last data + pointed by one inlink descriptor has been received and + data error is detected */ + __IOM uint32_t IN_DSCR_ERR_CH2_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when detecting inlink + descriptor error, including owner error, the second and + third word error of inlink descriptor for Rx channel 1. */ + __IOM uint32_t INFIFO_OVF_L1_CH2_INT_RAW : 1;/*!< This raw interrupt bit turns to high level when fifo of Rx channel + is overflow. */ + __IOM uint32_t INFIFO_UDF_L1_CH2_INT_RAW : 1;/*!< This raw interrupt bit turns to high level when fifo of Rx channel + is underflow. */ + __IOM uint32_t INFIFO_OVF_L2_CH2_INT_RAW : 1;/*!< This raw interrupt bit turns to high level when fifo of Rx channel + is overflow. */ + __IOM uint32_t INFIFO_UDF_L2_CH2_INT_RAW : 1;/*!< This raw interrupt bit turns to high level when fifo of Rx channel + is underflow. */ + __IOM uint32_t IN_DSCR_EMPTY_CH2_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when the last descriptor + is done but fifo also remain data. */ + __IOM uint32_t IN_DSCR_TASK_OVF_CH2_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when dscr ready task + fifo is overflow. */ + uint32_t : 22; + } bit; + } IN_INT_RAW_CH2; + + union { + __IOM uint32_t reg; /*!< RX CH2 interrupt ena register */ + + struct { + __IOM uint32_t IN_DONE_CH2_INT_ENA : 1; /*!< The interrupt enable bit for the IN_DONE_CH_INT interrupt. */ + __IOM uint32_t IN_SUC_EOF_CH2_INT_ENA : 1;/*!< The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. */ + __IOM uint32_t IN_ERR_EOF_CH2_INT_ENA : 1;/*!< The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. */ + __IOM uint32_t IN_DSCR_ERR_CH2_INT_ENA : 1;/*!< The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. */ + __IOM uint32_t INFIFO_OVF_L1_CH2_INT_ENA : 1;/*!< The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. */ + __IOM uint32_t INFIFO_UDF_L1_CH2_INT_ENA : 1;/*!< The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. */ + __IOM uint32_t INFIFO_OVF_L2_CH2_INT_ENA : 1;/*!< The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. */ + __IOM uint32_t INFIFO_UDF_L2_CH2_INT_ENA : 1;/*!< The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. */ + __IOM uint32_t IN_DSCR_EMPTY_CH2_INT_ENA : 1;/*!< The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. */ + __IOM uint32_t IN_DSCR_TASK_OVF_CH2_INT_ENA : 1;/*!< The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. */ + uint32_t : 22; + } bit; + } IN_INT_ENA_CH2; + + union { + __IOM uint32_t reg; /*!< RX CH2 interrupt st register */ + + struct { + __IM uint32_t IN_DONE_CH2_INT_ST : 1; /*!< The raw interrupt status bit for the IN_DONE_CH_INT interrupt. */ + __IM uint32_t IN_SUC_EOF_CH2_INT_ST : 1; /*!< The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. */ + __IM uint32_t IN_ERR_EOF_CH2_INT_ST : 1; /*!< The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. */ + __IM uint32_t IN_DSCR_ERR_CH2_INT_ST : 1;/*!< The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. */ + __IM uint32_t INFIFO_OVF_L1_CH2_INT_ST : 1;/*!< The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. */ + __IM uint32_t INFIFO_UDF_L1_CH2_INT_ST : 1;/*!< The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. */ + __IM uint32_t INFIFO_OVF_L2_CH2_INT_ST : 1;/*!< The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. */ + __IM uint32_t INFIFO_UDF_L2_CH2_INT_ST : 1;/*!< The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. */ + __IM uint32_t IN_DSCR_EMPTY_CH2_INT_ST : 1;/*!< The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. */ + __IM uint32_t IN_DSCR_TASK_OVF_CH2_INT_ST : 1;/*!< The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT + interrupt. */ + uint32_t : 22; + } bit; + } IN_INT_ST_CH2; + + union { + __IOM uint32_t reg; /*!< RX CH2 interrupt clr register */ + + struct { + __OM uint32_t IN_DONE_CH2_INT_CLR : 1; /*!< Set this bit to clear the IN_DONE_CH_INT interrupt. */ + __OM uint32_t IN_SUC_EOF_CH2_INT_CLR : 1;/*!< Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. */ + __OM uint32_t IN_ERR_EOF_CH2_INT_CLR : 1;/*!< Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. */ + __OM uint32_t IN_DSCR_ERR_CH2_INT_CLR : 1;/*!< Set this bit to clear the INDSCR_ERR_CH_INT interrupt. */ + __OM uint32_t INFIFO_OVF_L1_CH2_INT_CLR : 1;/*!< Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. */ + __OM uint32_t INFIFO_UDF_L1_CH2_INT_CLR : 1;/*!< Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. */ + __OM uint32_t INFIFO_OVF_L2_CH2_INT_CLR : 1;/*!< Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. */ + __OM uint32_t INFIFO_UDF_L2_CH2_INT_CLR : 1;/*!< Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. */ + __OM uint32_t IN_DSCR_EMPTY_CH2_INT_CLR : 1;/*!< Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. */ + __OM uint32_t IN_DSCR_TASK_OVF_CH2_INT_CLR : 1;/*!< Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. */ + uint32_t : 22; + } bit; + } IN_INT_CLR_CH2; + + union { + __IOM uint32_t reg; /*!< RX CH2 INFIFO status register */ + + struct { + __IM uint32_t INFIFO_FULL_L2_CH2 : 1; /*!< Rx FIFO full signal for Rx channel. */ + __IM uint32_t INFIFO_EMPTY_L2_CH2 : 1; /*!< Rx FIFO empty signal for Rx channel. */ + __IM uint32_t INFIFO_CNT_L2_CH2 : 4; /*!< The register stores the byte number of the data in Rx FIFO for + Rx channel. */ + __IM uint32_t INFIFO_FULL_L1_CH2 : 1; /*!< Tx FIFO full signal for Tx channel 1. */ + __IM uint32_t INFIFO_EMPTY_L1_CH2 : 1; /*!< Tx FIFO empty signal for Tx channel 1. */ + __IM uint32_t INFIFO_CNT_L1_CH2 : 5; /*!< The register stores the byte number of the data in Tx FIFO for + Tx channel 1. */ + uint32_t : 3; + __IM uint32_t INFIFO_FULL_L3_CH2 : 1; /*!< Tx FIFO full signal for Tx channel 1. */ + __IM uint32_t INFIFO_EMPTY_L3_CH2 : 1; /*!< Tx FIFO empty signal for Tx channel 1. */ + __IM uint32_t INFIFO_CNT_L3_CH2 : 2; /*!< The register stores the byte number of the data in Tx FIFO for + Tx channel 1. */ + uint32_t : 12; + } bit; + } INFIFO_STATUS_CH2; + + union { + __IOM uint32_t reg; /*!< RX CH2 INFIFO pop register */ + + struct { + __IM uint32_t INFIFO_RDATA_CH2 : 11; /*!< This register stores the data popping from DMA Rx FIFO. */ + __IOM uint32_t INFIFO_POP_CH2 : 1; /*!< Set this bit to pop data from DMA Rx FIFO. */ + uint32_t : 20; + } bit; + } IN_POP_CH2; + + union { + __IOM uint32_t reg; /*!< RX CH2 in_link dscr ctrl register */ + + struct { + uint32_t : 20; + __IOM uint32_t INLINK_AUTO_RET_CH2 : 1; /*!< Set this bit to return to current inlink descriptor's address, + when there are some errors in current receiving data. */ + __IOM uint32_t INLINK_STOP_CH2 : 1; /*!< Set this bit to stop dealing with the inlink descriptors. */ + __IOM uint32_t INLINK_START_CH2 : 1; /*!< Set this bit to start dealing with the inlink descriptors. */ + __IOM uint32_t INLINK_RESTART_CH2 : 1; /*!< Set this bit to mount a new inlink descriptor. */ + __IM uint32_t INLINK_PARK_CH2 : 1; /*!< 1: the inlink descriptor's FSM is in idle state. 0: the inlink + descriptor's FSM is working. */ + uint32_t : 7; + } bit; + } IN_LINK_CONF_CH2; + + union { + __IOM uint32_t reg; /*!< RX CH2 in_link dscr addr register */ + + struct { + __IOM uint32_t INLINK_ADDR_CH2 : 32; /*!< This register stores the first inlink descriptor's address. */ + } bit; + } IN_LINK_ADDR_CH2; + + union { + __IOM uint32_t reg; /*!< RX CH2 state register */ + + struct { + __IM uint32_t INLINK_DSCR_ADDR_CH2 : 18; /*!< This register stores the current inlink descriptor's address. */ + __IM uint32_t IN_DSCR_STATE_CH2 : 2; /*!< This register stores the current descriptor state machine state. */ + __IM uint32_t IN_STATE_CH2 : 3; /*!< This register stores the current control module state machine + state. */ + __IM uint32_t IN_RESET_AVAIL_CH2 : 1; /*!< This register indicate that if the channel reset is safety. */ + uint32_t : 8; + } bit; + } IN_STATE_CH2; + + union { + __IOM uint32_t reg; /*!< RX CH2 eof des addr register */ + + struct { + __IM uint32_t IN_SUC_EOF_DES_ADDR_CH2 : 32;/*!< This register stores the address of the inlink descriptor when + the EOF bit in this descriptor is 1. */ + } bit; + } IN_SUC_EOF_DES_ADDR_CH2; + + union { + __IOM uint32_t reg; /*!< RX CH2 err eof des addr register */ + + struct { + __IM uint32_t IN_ERR_EOF_DES_ADDR_CH2 : 32;/*!< This register stores the address of the inlink descriptor when + there are some errors in current receiving data. */ + } bit; + } IN_ERR_EOF_DES_ADDR_CH2; + + union { + __IOM uint32_t reg; /*!< RX CH2 next dscr addr register */ + + struct { + __IM uint32_t INLINK_DSCR_CH2 : 32; /*!< The address of the next inlink descriptor address x. */ + } bit; + } IN_DSCR_CH2; + + union { + __IOM uint32_t reg; /*!< RX CH2 last dscr addr register */ + + struct { + __IM uint32_t INLINK_DSCR_BF0_CH2 : 32; /*!< The address of the last inlink descriptor's next address x-1. */ + } bit; + } IN_DSCR_BF0_CH2; + + union { + __IOM uint32_t reg; /*!< RX CH2 second-to-last dscr addr register */ + + struct { + __IM uint32_t INLINK_DSCR_BF1_CH2 : 32; /*!< The address of the second-to-last inlink descriptor's next address + x-2. */ + } bit; + } IN_DSCR_BF1_CH2; + __IM uint32_t RESERVED30; + + union { + __IOM uint32_t reg; /*!< RX CH2 arb register */ + + struct { + __IOM uint32_t IN_ARB_TOKEN_NUM_CH2 : 4; /*!< Set the max number of token count of arbiter */ + uint32_t : 2; + __IOM uint32_t INTER_IN_ARB_PRIORITY_CH2 : 3;/*!< Set the priority of channel */ + uint32_t : 23; + } bit; + } IN_ARB_CH2; + __IM uint32_t RESERVED31; + + union { + __IOM uint32_t reg; /*!< RX CH2 ETM config register */ + + struct { + __IOM uint32_t IN_ETM_EN_CH2 : 1; /*!< Set this bit to 1 to enable ETM task function */ + __IOM uint32_t IN_ETM_LOOP_EN_CH2 : 1; /*!< when this bit is 1, dscr can be processed after receiving a + task */ + __IOM uint32_t IN_DSCR_TASK_MAK_CH2 : 2; /*!< ETM dscr_ready maximum cache numbers */ + uint32_t : 28; + } bit; + } IN_ETM_CONF_CH2; + __IM uint32_t RESERVED32[13]; + + union { + __IOM uint32_t reg; /*!< rx CH2 fifo cnt register */ + + struct { + __IM uint32_t IN_CMDFIFO_INFIFO_CNT_CH2 : 10;/*!< only for debug */ + uint32_t : 22; + } bit; + } IN_FIFO_CNT_CH2; + + union { + __IOM uint32_t reg; /*!< rx CH2 pop data cnt register */ + + struct { + __IM uint32_t IN_CMDFIFO_POP_DATA_CNT_CH2 : 8;/*!< only for debug */ + uint32_t : 24; + } bit; + } IN_POP_DATA_CNT_CH2; + + union { + __IOM uint32_t reg; /*!< rx CH2 xaddr register */ + + struct { + __IM uint32_t IN_CMDFIFO_XADDR_CH2 : 32; /*!< only for debug */ + } bit; + } IN_XADDR_CH2; + + union { + __IOM uint32_t reg; /*!< rx CH2 buf len hb rcv register */ + + struct { + __IM uint32_t IN_CMDFIFO_BUF_HB_RCV_CH2 : 29;/*!< only for debug */ + uint32_t : 3; + } bit; + } IN_BUF_HB_RCV_CH2; + __IM uint32_t RESERVED33[28]; + + union { + __IOM uint32_t reg; /*!< RX CH3 config0 register */ + + struct { + uint32_t : 2; + __IOM uint32_t INDSCR_BURST_EN_CH3 : 1; /*!< Set this bit to 1 to enable INCR burst transfer for Rx transmitting + link descriptor when accessing SRAM. */ + __IOM uint32_t IN_ECC_AES_EN_CH3 : 1; /*!< When access address space is ecc/aes area, this bit should be + set to 1. In this case, the start address of square should + be 16-bit aligned. The width of square multiply byte number + of one pixel should be 16-bit aligned. */ + __IOM uint32_t IN_CHECK_OWNER_CH3 : 1; /*!< Set this bit to enable checking the owner attribute of the link + descriptor. */ + uint32_t : 1; + __IOM uint32_t IN_MEM_BURST_LENGTH_CH3 : 3;/*!< Block size of Rx channel 1. 0: single 1: 16 bytes 2: 32 bytes + 3: 64 bytes 4: 128 bytes */ + uint32_t : 3; + __IOM uint32_t IN_PAGE_BOUND_EN_CH3 : 1; /*!< Set this bit to 1 to make sure AXI write data don't cross the + address boundary which define by mem_burst_length */ + uint32_t : 11; + __IOM uint32_t IN_RST_CH3 : 1; /*!< Write 1 then write 0 to this bit to reset Rx channel */ + __IOM uint32_t IN_CMD_DISABLE_CH3 : 1; /*!< Write 1 before reset and write 0 after reset */ + __IOM uint32_t IN_ARB_WEIGHT_OPT_DIS_CH3 : 1;/*!< Set this bit to 1 to disable arbiter optimum weight function. */ + uint32_t : 5; + } bit; + } IN_CONF0_CH3; + + union { + __IOM uint32_t reg; /*!< RX CH3 interrupt raw register */ + + struct { + __IOM uint32_t IN_DONE_CH3_INT_RAW : 1; /*!< The raw interrupt bit turns to high level when the last data + pointed by one inlink descriptor has been transmitted to + peripherals for Rx channel 1. */ + __IOM uint32_t IN_SUC_EOF_CH3_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when the last data + pointed by one inlink descriptor has been received and + no data error is detected for Rx channel 1. */ + __IOM uint32_t IN_ERR_EOF_CH3_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when the last data + pointed by one inlink descriptor has been received and + data error is detected */ + __IOM uint32_t IN_DSCR_ERR_CH3_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when detecting inlink + descriptor error, including owner error, the second and + third word error of inlink descriptor for Rx channel 1. */ + __IOM uint32_t INFIFO_OVF_L1_CH3_INT_RAW : 1;/*!< This raw interrupt bit turns to high level when fifo of Rx channel + is overflow. */ + __IOM uint32_t INFIFO_UDF_L1_CH3_INT_RAW : 1;/*!< This raw interrupt bit turns to high level when fifo of Rx channel + is underflow. */ + __IOM uint32_t INFIFO_OVF_L2_CH3_INT_RAW : 1;/*!< This raw interrupt bit turns to high level when fifo of Rx channel + is overflow. */ + __IOM uint32_t INFIFO_UDF_L2_CH3_INT_RAW : 1;/*!< This raw interrupt bit turns to high level when fifo of Rx channel + is underflow. */ + __IOM uint32_t IN_DSCR_EMPTY_CH3_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when the last descriptor + is done but fifo also remain data. */ + __IOM uint32_t IN_DSCR_TASK_OVF_CH3_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when dscr ready task + fifo is overflow. */ + uint32_t : 22; + } bit; + } IN_INT_RAW_CH3; + + union { + __IOM uint32_t reg; /*!< RX CH3 interrupt ena register */ + + struct { + __IOM uint32_t IN_DONE_CH3_INT_ENA : 1; /*!< The interrupt enable bit for the IN_DONE_CH_INT interrupt. */ + __IOM uint32_t IN_SUC_EOF_CH3_INT_ENA : 1;/*!< The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. */ + __IOM uint32_t IN_ERR_EOF_CH3_INT_ENA : 1;/*!< The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. */ + __IOM uint32_t IN_DSCR_ERR_CH3_INT_ENA : 1;/*!< The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. */ + __IOM uint32_t INFIFO_OVF_L1_CH3_INT_ENA : 1;/*!< The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. */ + __IOM uint32_t INFIFO_UDF_L1_CH3_INT_ENA : 1;/*!< The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. */ + __IOM uint32_t INFIFO_OVF_L2_CH3_INT_ENA : 1;/*!< The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. */ + __IOM uint32_t INFIFO_UDF_L2_CH3_INT_ENA : 1;/*!< The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. */ + __IOM uint32_t IN_DSCR_EMPTY_CH3_INT_ENA : 1;/*!< The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. */ + __IOM uint32_t IN_DSCR_TASK_OVF_CH3_INT_ENA : 1;/*!< The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. */ + uint32_t : 22; + } bit; + } IN_INT_ENA_CH3; + + union { + __IOM uint32_t reg; /*!< RX CH3 interrupt st register */ + + struct { + __IM uint32_t IN_DONE_CH3_INT_ST : 1; /*!< The raw interrupt status bit for the IN_DONE_CH_INT interrupt. */ + __IM uint32_t IN_SUC_EOF_CH3_INT_ST : 1; /*!< The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. */ + __IM uint32_t IN_ERR_EOF_CH3_INT_ST : 1; /*!< The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. */ + __IM uint32_t IN_DSCR_ERR_CH3_INT_ST : 1;/*!< The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. */ + __IM uint32_t INFIFO_OVF_L1_CH3_INT_ST : 1;/*!< The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. */ + __IM uint32_t INFIFO_UDF_L1_CH3_INT_ST : 1;/*!< The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. */ + __IM uint32_t INFIFO_OVF_L2_CH3_INT_ST : 1;/*!< The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. */ + __IM uint32_t INFIFO_UDF_L2_CH3_INT_ST : 1;/*!< The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. */ + __IM uint32_t IN_DSCR_EMPTY_CH3_INT_ST : 1;/*!< The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. */ + __IM uint32_t IN_DSCR_TASK_OVF_CH3_INT_ST : 1;/*!< The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT + interrupt. */ + uint32_t : 22; + } bit; + } IN_INT_ST_CH3; + + union { + __IOM uint32_t reg; /*!< RX CH3 interrupt clr register */ + + struct { + __OM uint32_t IN_DONE_CH3_INT_CLR : 1; /*!< Set this bit to clear the IN_DONE_CH_INT interrupt. */ + __OM uint32_t IN_SUC_EOF_CH3_INT_CLR : 1;/*!< Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. */ + __OM uint32_t IN_ERR_EOF_CH3_INT_CLR : 1;/*!< Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. */ + __OM uint32_t IN_DSCR_ERR_CH3_INT_CLR : 1;/*!< Set this bit to clear the INDSCR_ERR_CH_INT interrupt. */ + __OM uint32_t INFIFO_OVF_L1_CH3_INT_CLR : 1;/*!< Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. */ + __OM uint32_t INFIFO_UDF_L1_CH3_INT_CLR : 1;/*!< Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. */ + __OM uint32_t INFIFO_OVF_L2_CH3_INT_CLR : 1;/*!< Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. */ + __OM uint32_t INFIFO_UDF_L2_CH3_INT_CLR : 1;/*!< Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. */ + __OM uint32_t IN_DSCR_EMPTY_CH3_INT_CLR : 1;/*!< Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. */ + __OM uint32_t IN_DSCR_TASK_OVF_CH3_INT_CLR : 1;/*!< Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. */ + uint32_t : 22; + } bit; + } IN_INT_CLR_CH3; + + union { + __IOM uint32_t reg; /*!< RX CH3 INFIFO status register */ + + struct { + __IM uint32_t INFIFO_FULL_L2_CH3 : 1; /*!< Rx FIFO full signal for Rx channel. */ + __IM uint32_t INFIFO_EMPTY_L2_CH3 : 1; /*!< Rx FIFO empty signal for Rx channel. */ + __IM uint32_t INFIFO_CNT_L2_CH3 : 4; /*!< The register stores the byte number of the data in Rx FIFO for + Rx channel. */ + __IM uint32_t INFIFO_FULL_L1_CH3 : 1; /*!< Tx FIFO full signal for Tx channel 1. */ + __IM uint32_t INFIFO_EMPTY_L1_CH3 : 1; /*!< Tx FIFO empty signal for Tx channel 1. */ + __IM uint32_t INFIFO_CNT_L1_CH3 : 5; /*!< The register stores the byte number of the data in Tx FIFO for + Tx channel 1. */ + uint32_t : 3; + __IM uint32_t INFIFO_FULL_L3_CH3 : 1; /*!< Tx FIFO full signal for Tx channel 1. */ + __IM uint32_t INFIFO_EMPTY_L3_CH3 : 1; /*!< Tx FIFO empty signal for Tx channel 1. */ + __IM uint32_t INFIFO_CNT_L3_CH3 : 2; /*!< The register stores the byte number of the data in Tx FIFO for + Tx channel 1. */ + uint32_t : 12; + } bit; + } INFIFO_STATUS_CH3; + + union { + __IOM uint32_t reg; /*!< RX CH3 INFIFO pop register */ + + struct { + __IM uint32_t INFIFO_RDATA_CH3 : 11; /*!< This register stores the data popping from DMA Rx FIFO. */ + __IOM uint32_t INFIFO_POP_CH3 : 1; /*!< Set this bit to pop data from DMA Rx FIFO. */ + uint32_t : 20; + } bit; + } IN_POP_CH3; + + union { + __IOM uint32_t reg; /*!< RX CH3 in_link dscr ctrl register */ + + struct { + uint32_t : 20; + __IOM uint32_t INLINK_AUTO_RET_CH3 : 1; /*!< Set this bit to return to current inlink descriptor's address, + when there are some errors in current receiving data. */ + __IOM uint32_t INLINK_STOP_CH3 : 1; /*!< Set this bit to stop dealing with the inlink descriptors. */ + __IOM uint32_t INLINK_START_CH3 : 1; /*!< Set this bit to start dealing with the inlink descriptors. */ + __IOM uint32_t INLINK_RESTART_CH3 : 1; /*!< Set this bit to mount a new inlink descriptor. */ + __IM uint32_t INLINK_PARK_CH3 : 1; /*!< 1: the inlink descriptor's FSM is in idle state. 0: the inlink + descriptor's FSM is working. */ + uint32_t : 7; + } bit; + } IN_LINK_CONF_CH3; + + union { + __IOM uint32_t reg; /*!< RX CH3 in_link dscr addr register */ + + struct { + __IOM uint32_t INLINK_ADDR_CH3 : 32; /*!< This register stores the first inlink descriptor's address. */ + } bit; + } IN_LINK_ADDR_CH3; + + union { + __IOM uint32_t reg; /*!< RX CH3 state register */ + + struct { + __IM uint32_t INLINK_DSCR_ADDR_CH3 : 18; /*!< This register stores the current inlink descriptor's address. */ + __IM uint32_t IN_DSCR_STATE_CH3 : 2; /*!< This register stores the current descriptor state machine state. */ + __IM uint32_t IN_STATE_CH3 : 3; /*!< This register stores the current control module state machine + state. */ + __IM uint32_t IN_RESET_AVAIL_CH3 : 1; /*!< This register indicate that if the channel reset is safety. */ + uint32_t : 8; + } bit; + } IN_STATE_CH3; + + union { + __IOM uint32_t reg; /*!< RX CH3 eof des addr register */ + + struct { + __IM uint32_t IN_SUC_EOF_DES_ADDR_CH3 : 32;/*!< This register stores the address of the inlink descriptor when + the EOF bit in this descriptor is 1. */ + } bit; + } IN_SUC_EOF_DES_ADDR_CH3; + + union { + __IOM uint32_t reg; /*!< RX CH3 err eof des addr register */ + + struct { + __IM uint32_t IN_ERR_EOF_DES_ADDR_CH3 : 32;/*!< This register stores the address of the inlink descriptor when + there are some errors in current receiving data. */ + } bit; + } IN_ERR_EOF_DES_ADDR_CH3; + + union { + __IOM uint32_t reg; /*!< RX CH3 next dscr addr register */ + + struct { + __IM uint32_t INLINK_DSCR_CH3 : 32; /*!< The address of the next inlink descriptor address x. */ + } bit; + } IN_DSCR_CH3; + + union { + __IOM uint32_t reg; /*!< RX CH3 last dscr addr register */ + + struct { + __IM uint32_t INLINK_DSCR_BF0_CH3 : 32; /*!< The address of the last inlink descriptor's next address x-1. */ + } bit; + } IN_DSCR_BF0_CH3; + + union { + __IOM uint32_t reg; /*!< RX CH3 second-to-last dscr addr register */ + + struct { + __IM uint32_t INLINK_DSCR_BF1_CH3 : 32; /*!< The address of the second-to-last inlink descriptor's next address + x-2. */ + } bit; + } IN_DSCR_BF1_CH3; + __IM uint32_t RESERVED34; + + union { + __IOM uint32_t reg; /*!< RX CH3 arb register */ + + struct { + __IOM uint32_t IN_ARB_TOKEN_NUM_CH3 : 4; /*!< Set the max number of token count of arbiter */ + uint32_t : 2; + __IOM uint32_t INTER_IN_ARB_PRIORITY_CH3 : 3;/*!< Set the priority of channel */ + uint32_t : 23; + } bit; + } IN_ARB_CH3; + __IM uint32_t RESERVED35; + + union { + __IOM uint32_t reg; /*!< RX CH3 ETM config register */ + + struct { + __IOM uint32_t IN_ETM_EN_CH3 : 1; /*!< Set this bit to 1 to enable ETM task function */ + __IOM uint32_t IN_ETM_LOOP_EN_CH3 : 1; /*!< when this bit is 1, dscr can be processed after receiving a + task */ + __IOM uint32_t IN_DSCR_TASK_MAK_CH3 : 2; /*!< ETM dscr_ready maximum cache numbers */ + uint32_t : 28; + } bit; + } IN_ETM_CONF_CH3; + __IM uint32_t RESERVED36[13]; + + union { + __IOM uint32_t reg; /*!< rx CH3 fifo cnt register */ + + struct { + __IM uint32_t IN_CMDFIFO_INFIFO_CNT_CH3 : 10;/*!< only for debug */ + uint32_t : 22; + } bit; + } IN_FIFO_CNT_CH3; + + union { + __IOM uint32_t reg; /*!< rx CH3 pop data cnt register */ + + struct { + __IM uint32_t IN_CMDFIFO_POP_DATA_CNT_CH3 : 8;/*!< only for debug */ + uint32_t : 24; + } bit; + } IN_POP_DATA_CNT_CH3; + + union { + __IOM uint32_t reg; /*!< rx CH3 xaddr register */ + + struct { + __IM uint32_t IN_CMDFIFO_XADDR_CH3 : 32; /*!< only for debug */ + } bit; + } IN_XADDR_CH3; + + union { + __IOM uint32_t reg; /*!< rx CH3 buf len hb rcv register */ + + struct { + __IM uint32_t IN_CMDFIFO_BUF_HB_RCV_CH3 : 29;/*!< only for debug */ + uint32_t : 3; + } bit; + } IN_BUF_HB_RCV_CH3; + __IM uint32_t RESERVED37[28]; + + union { + __IOM uint32_t reg; /*!< RX CH4 config0 register */ + + struct { + uint32_t : 2; + __IOM uint32_t INDSCR_BURST_EN_CH4 : 1; /*!< Set this bit to 1 to enable INCR burst transfer for Rx transmitting + link descriptor when accessing SRAM. */ + __IOM uint32_t IN_ECC_AES_EN_CH4 : 1; /*!< When access address space is ecc/aes area, this bit should be + set to 1. In this case, the start address of square should + be 16-bit aligned. The width of square multiply byte number + of one pixel should be 16-bit aligned. */ + __IOM uint32_t IN_CHECK_OWNER_CH4 : 1; /*!< Set this bit to enable checking the owner attribute of the link + descriptor. */ + uint32_t : 1; + __IOM uint32_t IN_MEM_BURST_LENGTH_CH4 : 3;/*!< Block size of Rx channel 1. 0: single 1: 16 bytes 2: 32 bytes + 3: 64 bytes 4: 128 bytes */ + uint32_t : 3; + __IOM uint32_t IN_PAGE_BOUND_EN_CH4 : 1; /*!< Set this bit to 1 to make sure AXI write data don't cross the + address boundary which define by mem_burst_length */ + uint32_t : 11; + __IOM uint32_t IN_RST_CH4 : 1; /*!< Write 1 then write 0 to this bit to reset Rx channel */ + __IOM uint32_t IN_CMD_DISABLE_CH4 : 1; /*!< Write 1 before reset and write 0 after reset */ + __IOM uint32_t IN_ARB_WEIGHT_OPT_DIS_CH4 : 1;/*!< Set this bit to 1 to disable arbiter optimum weight function. */ + uint32_t : 5; + } bit; + } IN_CONF0_CH4; + + union { + __IOM uint32_t reg; /*!< RX CH4 interrupt raw register */ + + struct { + __IOM uint32_t IN_DONE_CH4_INT_RAW : 1; /*!< The raw interrupt bit turns to high level when the last data + pointed by one inlink descriptor has been transmitted to + peripherals for Rx channel 1. */ + __IOM uint32_t IN_SUC_EOF_CH4_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when the last data + pointed by one inlink descriptor has been received and + no data error is detected for Rx channel 1. */ + __IOM uint32_t IN_ERR_EOF_CH4_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when the last data + pointed by one inlink descriptor has been received and + data error is detected */ + __IOM uint32_t IN_DSCR_ERR_CH4_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when detecting inlink + descriptor error, including owner error, the second and + third word error of inlink descriptor for Rx channel 1. */ + __IOM uint32_t INFIFO_OVF_L1_CH4_INT_RAW : 1;/*!< This raw interrupt bit turns to high level when fifo of Rx channel + is overflow. */ + __IOM uint32_t INFIFO_UDF_L1_CH4_INT_RAW : 1;/*!< This raw interrupt bit turns to high level when fifo of Rx channel + is underflow. */ + __IOM uint32_t INFIFO_OVF_L2_CH4_INT_RAW : 1;/*!< This raw interrupt bit turns to high level when fifo of Rx channel + is overflow. */ + __IOM uint32_t INFIFO_UDF_L2_CH4_INT_RAW : 1;/*!< This raw interrupt bit turns to high level when fifo of Rx channel + is underflow. */ + __IOM uint32_t IN_DSCR_EMPTY_CH4_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when the last descriptor + is done but fifo also remain data. */ + __IOM uint32_t IN_DSCR_TASK_OVF_CH4_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when dscr ready task + fifo is overflow. */ + uint32_t : 22; + } bit; + } IN_INT_RAW_CH4; + + union { + __IOM uint32_t reg; /*!< RX CH4 interrupt ena register */ + + struct { + __IOM uint32_t IN_DONE_CH4_INT_ENA : 1; /*!< The interrupt enable bit for the IN_DONE_CH_INT interrupt. */ + __IOM uint32_t IN_SUC_EOF_CH4_INT_ENA : 1;/*!< The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. */ + __IOM uint32_t IN_ERR_EOF_CH4_INT_ENA : 1;/*!< The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. */ + __IOM uint32_t IN_DSCR_ERR_CH4_INT_ENA : 1;/*!< The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. */ + __IOM uint32_t INFIFO_OVF_L1_CH4_INT_ENA : 1;/*!< The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. */ + __IOM uint32_t INFIFO_UDF_L1_CH4_INT_ENA : 1;/*!< The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. */ + __IOM uint32_t INFIFO_OVF_L2_CH4_INT_ENA : 1;/*!< The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. */ + __IOM uint32_t INFIFO_UDF_L2_CH4_INT_ENA : 1;/*!< The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. */ + __IOM uint32_t IN_DSCR_EMPTY_CH4_INT_ENA : 1;/*!< The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. */ + __IOM uint32_t IN_DSCR_TASK_OVF_CH4_INT_ENA : 1;/*!< The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. */ + uint32_t : 22; + } bit; + } IN_INT_ENA_CH4; + + union { + __IOM uint32_t reg; /*!< RX CH4 interrupt st register */ + + struct { + __IM uint32_t IN_DONE_CH4_INT_ST : 1; /*!< The raw interrupt status bit for the IN_DONE_CH_INT interrupt. */ + __IM uint32_t IN_SUC_EOF_CH4_INT_ST : 1; /*!< The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. */ + __IM uint32_t IN_ERR_EOF_CH4_INT_ST : 1; /*!< The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. */ + __IM uint32_t IN_DSCR_ERR_CH4_INT_ST : 1;/*!< The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. */ + __IM uint32_t INFIFO_OVF_L1_CH4_INT_ST : 1;/*!< The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. */ + __IM uint32_t INFIFO_UDF_L1_CH4_INT_ST : 1;/*!< The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. */ + __IM uint32_t INFIFO_OVF_L2_CH4_INT_ST : 1;/*!< The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. */ + __IM uint32_t INFIFO_UDF_L2_CH4_INT_ST : 1;/*!< The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. */ + __IM uint32_t IN_DSCR_EMPTY_CH4_INT_ST : 1;/*!< The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. */ + __IM uint32_t IN_DSCR_TASK_OVF_CH4_INT_ST : 1;/*!< The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT + interrupt. */ + uint32_t : 22; + } bit; + } IN_INT_ST_CH4; + + union { + __IOM uint32_t reg; /*!< RX CH4 interrupt clr register */ + + struct { + __OM uint32_t IN_DONE_CH4_INT_CLR : 1; /*!< Set this bit to clear the IN_DONE_CH_INT interrupt. */ + __OM uint32_t IN_SUC_EOF_CH4_INT_CLR : 1;/*!< Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. */ + __OM uint32_t IN_ERR_EOF_CH4_INT_CLR : 1;/*!< Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. */ + __OM uint32_t IN_DSCR_ERR_CH4_INT_CLR : 1;/*!< Set this bit to clear the INDSCR_ERR_CH_INT interrupt. */ + __OM uint32_t INFIFO_OVF_L1_CH4_INT_CLR : 1;/*!< Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. */ + __OM uint32_t INFIFO_UDF_L1_CH4_INT_CLR : 1;/*!< Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. */ + __OM uint32_t INFIFO_OVF_L2_CH4_INT_CLR : 1;/*!< Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. */ + __OM uint32_t INFIFO_UDF_L2_CH4_INT_CLR : 1;/*!< Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. */ + __OM uint32_t IN_DSCR_EMPTY_CH4_INT_CLR : 1;/*!< Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. */ + __OM uint32_t IN_DSCR_TASK_OVF_CH4_INT_CLR : 1;/*!< Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. */ + uint32_t : 22; + } bit; + } IN_INT_CLR_CH4; + + union { + __IOM uint32_t reg; /*!< RX CH4 INFIFO status register */ + + struct { + __IM uint32_t INFIFO_FULL_L2_CH4 : 1; /*!< Rx FIFO full signal for Rx channel. */ + __IM uint32_t INFIFO_EMPTY_L2_CH4 : 1; /*!< Rx FIFO empty signal for Rx channel. */ + __IM uint32_t INFIFO_CNT_L2_CH4 : 4; /*!< The register stores the byte number of the data in Rx FIFO for + Rx channel. */ + __IM uint32_t INFIFO_FULL_L1_CH4 : 1; /*!< Tx FIFO full signal for Tx channel 1. */ + __IM uint32_t INFIFO_EMPTY_L1_CH4 : 1; /*!< Tx FIFO empty signal for Tx channel 1. */ + __IM uint32_t INFIFO_CNT_L1_CH4 : 5; /*!< The register stores the byte number of the data in Tx FIFO for + Tx channel 1. */ + uint32_t : 3; + __IM uint32_t INFIFO_FULL_L3_CH4 : 1; /*!< Tx FIFO full signal for Tx channel 1. */ + __IM uint32_t INFIFO_EMPTY_L3_CH4 : 1; /*!< Tx FIFO empty signal for Tx channel 1. */ + __IM uint32_t INFIFO_CNT_L3_CH4 : 2; /*!< The register stores the byte number of the data in Tx FIFO for + Tx channel 1. */ + uint32_t : 12; + } bit; + } INFIFO_STATUS_CH4; + + union { + __IOM uint32_t reg; /*!< RX CH4 INFIFO pop register */ + + struct { + __IM uint32_t INFIFO_RDATA_CH4 : 11; /*!< This register stores the data popping from DMA Rx FIFO. */ + __IOM uint32_t INFIFO_POP_CH4 : 1; /*!< Set this bit to pop data from DMA Rx FIFO. */ + uint32_t : 20; + } bit; + } IN_POP_CH4; + + union { + __IOM uint32_t reg; /*!< RX CH4 in_link dscr ctrl register */ + + struct { + uint32_t : 20; + __IOM uint32_t INLINK_AUTO_RET_CH4 : 1; /*!< Set this bit to return to current inlink descriptor's address, + when there are some errors in current receiving data. */ + __IOM uint32_t INLINK_STOP_CH4 : 1; /*!< Set this bit to stop dealing with the inlink descriptors. */ + __IOM uint32_t INLINK_START_CH4 : 1; /*!< Set this bit to start dealing with the inlink descriptors. */ + __IOM uint32_t INLINK_RESTART_CH4 : 1; /*!< Set this bit to mount a new inlink descriptor. */ + __IM uint32_t INLINK_PARK_CH4 : 1; /*!< 1: the inlink descriptor's FSM is in idle state. 0: the inlink + descriptor's FSM is working. */ + uint32_t : 7; + } bit; + } IN_LINK_CONF_CH4; + + union { + __IOM uint32_t reg; /*!< RX CH4 in_link dscr addr register */ + + struct { + __IOM uint32_t INLINK_ADDR_CH4 : 32; /*!< This register stores the first inlink descriptor's address. */ + } bit; + } IN_LINK_ADDR_CH4; + + union { + __IOM uint32_t reg; /*!< RX CH4 state register */ + + struct { + __IM uint32_t INLINK_DSCR_ADDR_CH4 : 18; /*!< This register stores the current inlink descriptor's address. */ + __IM uint32_t IN_DSCR_STATE_CH4 : 2; /*!< This register stores the current descriptor state machine state. */ + __IM uint32_t IN_STATE_CH4 : 3; /*!< This register stores the current control module state machine + state. */ + __IM uint32_t IN_RESET_AVAIL_CH4 : 1; /*!< This register indicate that if the channel reset is safety. */ + uint32_t : 8; + } bit; + } IN_STATE_CH4; + + union { + __IOM uint32_t reg; /*!< RX CH4 eof des addr register */ + + struct { + __IM uint32_t IN_SUC_EOF_DES_ADDR_CH4 : 32;/*!< This register stores the address of the inlink descriptor when + the EOF bit in this descriptor is 1. */ + } bit; + } IN_SUC_EOF_DES_ADDR_CH4; + + union { + __IOM uint32_t reg; /*!< RX CH4 err eof des addr register */ + + struct { + __IM uint32_t IN_ERR_EOF_DES_ADDR_CH4 : 32;/*!< This register stores the address of the inlink descriptor when + there are some errors in current receiving data. */ + } bit; + } IN_ERR_EOF_DES_ADDR_CH4; + + union { + __IOM uint32_t reg; /*!< RX CH4 next dscr addr register */ + + struct { + __IM uint32_t INLINK_DSCR_CH4 : 32; /*!< The address of the next inlink descriptor address x. */ + } bit; + } IN_DSCR_CH4; + + union { + __IOM uint32_t reg; /*!< RX CH4 last dscr addr register */ + + struct { + __IM uint32_t INLINK_DSCR_BF0_CH4 : 32; /*!< The address of the last inlink descriptor's next address x-1. */ + } bit; + } IN_DSCR_BF0_CH4; + + union { + __IOM uint32_t reg; /*!< RX CH4 second-to-last dscr addr register */ + + struct { + __IM uint32_t INLINK_DSCR_BF1_CH4 : 32; /*!< The address of the second-to-last inlink descriptor's next address + x-2. */ + } bit; + } IN_DSCR_BF1_CH4; + __IM uint32_t RESERVED38; + + union { + __IOM uint32_t reg; /*!< RX CH4 arb register */ + + struct { + __IOM uint32_t IN_ARB_TOKEN_NUM_CH4 : 4; /*!< Set the max number of token count of arbiter */ + __IOM uint32_t EXTER_IN_ARB_PRIORITY_CH4 : 2;/*!< Set the priority of channel */ + __IOM uint32_t INTER_IN_ARB_PRIORITY_CH4 : 3;/*!< Set the priority of channel */ + uint32_t : 23; + } bit; + } IN_ARB_CH4; + __IM uint32_t RESERVED39; + + union { + __IOM uint32_t reg; /*!< RX CH4 ETM config register */ + + struct { + __IOM uint32_t IN_ETM_EN_CH4 : 1; /*!< Set this bit to 1 to enable ETM task function */ + __IOM uint32_t IN_ETM_LOOP_EN_CH4 : 1; /*!< when this bit is 1, dscr can be processed after receiving a + task */ + __IOM uint32_t IN_DSCR_TASK_MAK_CH4 : 2; /*!< ETM dscr_ready maximum cache numbers */ + uint32_t : 28; + } bit; + } IN_ETM_CONF_CH4; + __IM uint32_t RESERVED40[13]; + + union { + __IOM uint32_t reg; /*!< rx CH4 fifo cnt register */ + + struct { + __IM uint32_t IN_CMDFIFO_INFIFO_CNT_CH4 : 10;/*!< only for debug */ + uint32_t : 22; + } bit; + } IN_FIFO_CNT_CH4; + + union { + __IOM uint32_t reg; /*!< rx CH4 pop data cnt register */ + + struct { + __IM uint32_t IN_CMDFIFO_POP_DATA_CNT_CH4 : 8;/*!< only for debug */ + uint32_t : 24; + } bit; + } IN_POP_DATA_CNT_CH4; + + union { + __IOM uint32_t reg; /*!< rx CH4 xaddr register */ + + struct { + __IM uint32_t IN_CMDFIFO_XADDR_CH4 : 32; /*!< only for debug */ + } bit; + } IN_XADDR_CH4; + + union { + __IOM uint32_t reg; /*!< rx CH4 buf len hb rcv register */ + + struct { + __IM uint32_t IN_CMDFIFO_BUF_HB_RCV_CH4 : 29;/*!< only for debug */ + uint32_t : 3; + } bit; + } IN_BUF_HB_RCV_CH4; + __IM uint32_t RESERVED41[28]; + + union { + __IOM uint32_t reg; /*!< RX CH5 config0 register */ + + struct { + uint32_t : 3; + __IOM uint32_t IN_ECC_AES_EN_CH5 : 1; /*!< When access address space is ecc/aes area, this bit should be + set to 1. In this case, the start address of square should + be 16-bit aligned. The width of square multiply byte number + of one pixel should be 16-bit aligned. */ + uint32_t : 2; + __IOM uint32_t IN_MEM_BURST_LENGTH_CH5 : 3;/*!< Block size of Rx channel 1. 0: single 1: 16 bytes 2: 32 bytes + 3: 64 bytes 4: 128 bytes */ + uint32_t : 3; + __IOM uint32_t IN_PAGE_BOUND_EN_CH5 : 1; /*!< Set this bit to 1 to make sure AXI write data don't cross the + address boundary which define by mem_burst_length */ + uint32_t : 11; + __IOM uint32_t IN_RST_CH5 : 1; /*!< Write 1 then write 0 to this bit to reset Rx channel */ + __IOM uint32_t IN_CMD_DISABLE_CH5 : 1; /*!< Write 1 before reset and write 0 after reset */ + uint32_t : 6; + } bit; + } IN_CONF0_CH5; + + union { + __IOM uint32_t reg; /*!< RX CH5 config1 register */ + + struct { + __IOM uint32_t BLOCK_START_ADDR_CH5 : 32; /*!< RX Channel 5 destination start address */ + } bit; + } IN_CONF1_CH5; + + union { + __IOM uint32_t reg; /*!< RX CH5 config2 register */ + + struct { + __IOM uint32_t BLOCK_ROW_LENGTH_12LINE_CH5 : 16;/*!< The number of bytes contained in a row block 12line in RX channel + 5 */ + __IOM uint32_t BLOCK_ROW_LENGTH_4LINE_CH5 : 16;/*!< The number of bytes contained in a row block 4line in RX channel + 5 */ + } bit; + } IN_CONF2_CH5; + + union { + __IOM uint32_t reg; /*!< RX CH5 config3 register */ + + struct { + __IOM uint32_t BLOCK_LENGTH_12LINE_CH5 : 14;/*!< The number of bytes contained in a block 12line */ + __IOM uint32_t BLOCK_LENGTH_4LINE_CH5 : 14;/*!< The number of bytes contained in a block 4line */ + uint32_t : 4; + } bit; + } IN_CONF3_CH5; + + union { + __IOM uint32_t reg; /*!< RX CH5 interrupt raw register */ + + struct { + __IOM uint32_t IN_DONE_CH5_INT_RAW : 1; /*!< The raw interrupt bit turns to high level when the last data + pointed by one inlink descriptor has been transmitted to + peripherals for Rx channel 1. */ + __IOM uint32_t IN_SUC_EOF_CH5_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when the last data + pointed by one inlink descriptor has been received and + no data error is detected for Rx channel 1. */ + __IOM uint32_t INFIFO_OVF_L1_CH5_INT_RAW : 1;/*!< This raw interrupt bit turns to high level when fifo of Rx channel + is overflow. */ + __IOM uint32_t INFIFO_UDF_L1_CH5_INT_RAW : 1;/*!< This raw interrupt bit turns to high level when fifo of Rx channel + is underflow. */ + __IOM uint32_t FETCH_MB_COL_CNT_OVF_CH5_INT_RAW : 1;/*!< This raw interrupt bit turns to high level when fifo of Rx channel + is underflow. */ + uint32_t : 27; + } bit; + } IN_INT_RAW_CH5; + + union { + __IOM uint32_t reg; /*!< RX CH5 interrupt ena register */ + + struct { + __IOM uint32_t IN_DONE_CH5_INT_ENA : 1; /*!< The interrupt enable bit for the IN_DONE_CH_INT interrupt. */ + __IOM uint32_t IN_SUC_EOF_CH5_INT_ENA : 1;/*!< The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. */ + __IOM uint32_t INFIFO_OVF_L1_CH5_INT_ENA : 1;/*!< The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. */ + __IOM uint32_t INFIFO_UDF_L1_CH5_INT_ENA : 1;/*!< The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. */ + __IOM uint32_t FETCH_MB_COL_CNT_OVF_CH5_INT_ENA : 1;/*!< The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. */ + uint32_t : 27; + } bit; + } IN_INT_ENA_CH5; + + union { + __IOM uint32_t reg; /*!< RX CH5 interrupt st register */ + + struct { + __IM uint32_t IN_DONE_CH5_INT_ST : 1; /*!< The raw interrupt status bit for the IN_DONE_CH_INT interrupt. */ + __IM uint32_t IN_SUC_EOF_CH5_INT_ST : 1; /*!< The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. */ + __IM uint32_t INFIFO_OVF_L1_CH5_INT_ST : 1;/*!< The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. */ + __IM uint32_t INFIFO_UDF_L1_CH5_INT_ST : 1;/*!< The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. */ + __IM uint32_t FETCH_MB_COL_CNT_OVF_CH5_INT_ST : 1;/*!< The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. */ + uint32_t : 27; + } bit; + } IN_INT_ST_CH5; + + union { + __IOM uint32_t reg; /*!< RX CH5 interrupt clr register */ + + struct { + __OM uint32_t IN_DONE_CH5_INT_CLR : 1; /*!< Set this bit to clear the IN_DONE_CH_INT interrupt. */ + __OM uint32_t IN_SUC_EOF_CH5_INT_CLR : 1;/*!< Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. */ + __OM uint32_t INFIFO_OVF_L1_CH5_INT_CLR : 1;/*!< Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. */ + __OM uint32_t INFIFO_UDF_L1_CH5_INT_CLR : 1;/*!< Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. */ + __OM uint32_t FETCH_MB_COL_CNT_OVF_CH5_INT_CLR : 1;/*!< Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. */ + uint32_t : 27; + } bit; + } IN_INT_CLR_CH5; + + union { + __IOM uint32_t reg; /*!< RX CH5 INFIFO status register */ + + struct { + __IM uint32_t INFIFO_FULL_L1_CH5 : 1; /*!< Tx FIFO full signal for Tx channel 1. */ + __IM uint32_t INFIFO_EMPTY_L1_CH5 : 1; /*!< Tx FIFO empty signal for Tx channel 1. */ + __IM uint32_t INFIFO_CNT_L1_CH5 : 5; /*!< The register stores the byte number of the data in Tx FIFO for + Tx channel 1. */ + uint32_t : 25; + } bit; + } INFIFO_STATUS_CH5; + + union { + __IOM uint32_t reg; /*!< RX CH5 INFIFO pop register */ + + struct { + __IM uint32_t INFIFO_RDATA_CH5 : 11; /*!< This register stores the data popping from DMA Rx FIFO. */ + __IOM uint32_t INFIFO_POP_CH5 : 1; /*!< Set this bit to pop data from DMA Rx FIFO. */ + uint32_t : 20; + } bit; + } IN_POP_CH5; + + union { + __IOM uint32_t reg; /*!< RX CH5 state register */ + + struct { + __IM uint32_t IN_STATE_CH5 : 3; /*!< This register stores the current control module state machine + state. */ + __IM uint32_t IN_RESET_AVAIL_CH5 : 1; /*!< This register indicate that if the channel reset is safety. */ + uint32_t : 28; + } bit; + } IN_STATE_CH5; + __IM uint32_t RESERVED42[5]; + + union { + __IOM uint32_t reg; /*!< RX CH5 arb register */ + + struct { + __IOM uint32_t IN_ARB_TOKEN_NUM_CH5 : 4; /*!< Set the max number of token count of arbiter */ + uint32_t : 2; + __IOM uint32_t INTER_IN_ARB_PRIORITY_CH5 : 3;/*!< Set the priority of channel */ + uint32_t : 23; + } bit; + } IN_ARB_CH5; + __IM uint32_t RESERVED43[15]; + + union { + __IOM uint32_t reg; /*!< rx CH5 fifo cnt register */ + + struct { + __IM uint32_t IN_CMDFIFO_INFIFO_CNT_CH5 : 10;/*!< only for debug */ + uint32_t : 22; + } bit; + } IN_FIFO_CNT_CH5; + + union { + __IOM uint32_t reg; /*!< rx CH5 pop data cnt register */ + + struct { + __IM uint32_t IN_CMDFIFO_POP_DATA_CNT_CH5 : 8;/*!< only for debug */ + uint32_t : 24; + } bit; + } IN_POP_DATA_CNT_CH5; + + union { + __IOM uint32_t reg; /*!< rx CH5 xaddr register */ + + struct { + __IM uint32_t IN_CMDFIFO_XADDR_CH5 : 32; /*!< only for debug */ + } bit; + } IN_XADDR_CH5; + + union { + __IOM uint32_t reg; /*!< rx CH5 buf len hb rcv register */ + + struct { + __IM uint32_t IN_CMDFIFO_BUF_HB_RCV_CH5 : 29;/*!< only for debug */ + uint32_t : 3; + } bit; + } IN_BUF_HB_RCV_CH5; + __IM uint32_t RESERVED44[28]; + + union { + __IOM uint32_t reg; /*!< inter memory axi err register */ + + struct { + __IM uint32_t INTER_RID_ERR_CNT : 4; /*!< AXI read id err cnt */ + __IM uint32_t INTER_RRESP_ERR_CNT : 4; /*!< AXI read resp err cnt */ + __IM uint32_t INTER_WRESP_ERR_CNT : 4; /*!< AXI write resp err cnt */ + __IM uint32_t INTER_RD_FIFO_CNT : 3; /*!< AXI read cmd fifo remain cmd count */ + __IM uint32_t INTER_RD_BAK_FIFO_CNT : 4; /*!< AXI read backup cmd fifo remain cmd count */ + __IM uint32_t INTER_WR_FIFO_CNT : 3; /*!< AXI write cmd fifo remain cmd count */ + __IM uint32_t INTER_WR_BAK_FIFO_CNT : 4; /*!< AXI write backup cmd fifo remain cmd count */ + uint32_t : 6; + } bit; + } INTER_AXI_ERR; + + union { + __IOM uint32_t reg; /*!< exter memory axi err register */ + + struct { + __IM uint32_t EXTER_RID_ERR_CNT : 4; /*!< AXI read id err cnt */ + __IM uint32_t EXTER_RRESP_ERR_CNT : 4; /*!< AXI read resp err cnt */ + __IM uint32_t EXTER_WRESP_ERR_CNT : 4; /*!< AXI write resp err cnt */ + __IM uint32_t EXTER_RD_FIFO_CNT : 3; /*!< AXI read cmd fifo remain cmd count */ + __IM uint32_t EXTER_RD_BAK_FIFO_CNT : 4; /*!< AXI read backup cmd fifo remain cmd count */ + __IM uint32_t EXTER_WR_FIFO_CNT : 3; /*!< AXI write cmd fifo remain cmd count */ + __IM uint32_t EXTER_WR_BAK_FIFO_CNT : 4; /*!< AXI write backup cmd fifo remain cmd count */ + uint32_t : 6; + } bit; + } EXTER_AXI_ERR; + + union { + __IOM uint32_t reg; /*!< axi reset config register */ + + struct { + __IOM uint32_t INTER_AXIM_RD_RST : 1; /*!< Write 1 then write 0 to this bit to reset axi master read data + FIFO. */ + __IOM uint32_t INTER_AXIM_WR_RST : 1; /*!< Write 1 then write 0 to this bit to reset axi master write data + FIFO. */ + __IOM uint32_t EXTER_AXIM_RD_RST : 1; /*!< Write 1 then write 0 to this bit to reset axi master read data + FIFO. */ + __IOM uint32_t EXTER_AXIM_WR_RST : 1; /*!< Write 1 then write 0 to this bit to reset axi master write data + FIFO. */ + __IOM uint32_t CLK_EN : 1; /*!< 1'h1: Force clock on for register. 1'h0: Support clock only + when application writes registers. */ + uint32_t : 27; + } bit; + } RST_CONF; + + union { + __IOM uint32_t reg; /*!< Start address of inter memory range0 register */ + + struct { + __IOM uint32_t ACCESS_INTER_MEM_START_ADDR0 : 32;/*!< The start address of accessible address space. */ + } bit; + } INTER_MEM_START_ADDR0; + + union { + __IOM uint32_t reg; /*!< end address of inter memory range0 register */ + + struct { + __IOM uint32_t ACCESS_INTER_MEM_END_ADDR0 : 32;/*!< The end address of accessible address space. The access address + beyond this range would lead to descriptor error. */ + } bit; + } INTER_MEM_END_ADDR0; + + union { + __IOM uint32_t reg; /*!< Start address of inter memory range1 register */ + + struct { + __IOM uint32_t ACCESS_INTER_MEM_START_ADDR1 : 32;/*!< The start address of accessible address space. */ + } bit; + } INTER_MEM_START_ADDR1; + + union { + __IOM uint32_t reg; /*!< end address of inter memory range1 register */ + + struct { + __IOM uint32_t ACCESS_INTER_MEM_END_ADDR1 : 32;/*!< The end address of accessible address space. The access address + beyond this range would lead to descriptor error. */ + } bit; + } INTER_MEM_END_ADDR1; + __IM uint32_t RESERVED45; + + union { + __IOM uint32_t reg; /*!< Start address of exter memory range0 register */ + + struct { + __IOM uint32_t ACCESS_EXTER_MEM_START_ADDR0 : 32;/*!< The start address of accessible address space. */ + } bit; + } EXTER_MEM_START_ADDR0; + + union { + __IOM uint32_t reg; /*!< end address of exter memory range0 register */ + + struct { + __IOM uint32_t ACCESS_EXTER_MEM_END_ADDR0 : 32;/*!< The end address of accessible address space. The access address + beyond this range would lead to descriptor error. */ + } bit; + } EXTER_MEM_END_ADDR0; + + union { + __IOM uint32_t reg; /*!< Start address of exter memory range1 register */ + + struct { + __IOM uint32_t ACCESS_EXTER_MEM_START_ADDR1 : 32;/*!< The start address of accessible address space. */ + } bit; + } EXTER_MEM_START_ADDR1; + + union { + __IOM uint32_t reg; /*!< end address of exter memory range1 register */ + + struct { + __IOM uint32_t ACCESS_EXTER_MEM_END_ADDR1 : 32;/*!< The end address of accessible address space. The access address + beyond this range would lead to descriptor error. */ + } bit; + } EXTER_MEM_END_ADDR1; + + union { + __IOM uint32_t reg; /*!< reserved */ + + struct { + __IOM uint32_t OUT_ARB_TIMEOUT_NUM : 16; /*!< Set the max number of timeout count of arbiter */ + __IOM uint32_t OUT_WEIGHT_EN : 1; /*!< reserved */ + uint32_t : 15; + } bit; + } OUT_ARB_CONFIG; + + union { + __IOM uint32_t reg; /*!< reserved */ + + struct { + __IOM uint32_t IN_ARB_TIMEOUT_NUM : 16; /*!< Set the max number of timeout count of arbiter */ + __IOM uint32_t IN_WEIGHT_EN : 1; /*!< reserved */ + uint32_t : 15; + } bit; + } IN_ARB_CONFIG; + __IM uint32_t RESERVED46; + + union { + __IOM uint32_t reg; /*!< reserved */ + + struct { + __IOM uint32_t DATE : 32; /*!< register version. */ + } bit; + } DATE; + __IM uint32_t RESERVED47[4]; + + union { + __IOM uint32_t reg; /*!< counter reset register */ + + struct { + __IOM uint32_t RX_CH0_EXTER_COUNTER_RST : 1;/*!< Write 1 then write 0 to this bit to reset rx ch0 counter. */ + __IOM uint32_t RX_CH1_EXTER_COUNTER_RST : 1;/*!< Write 1 then write 0 to this bit to reset rx ch1 counter. */ + __IOM uint32_t RX_CH2_INTER_COUNTER_RST : 1;/*!< Write 1 then write 0 to this bit to reset rx ch2 counter. */ + __IOM uint32_t RX_CH5_INTER_COUNTER_RST : 1;/*!< Write 1 then write 0 to this bit to reset rx ch5 counter. */ + uint32_t : 28; + } bit; + } COUNTER_RST; + + union { + __IOM uint32_t reg; /*!< rx ch0 counter register */ + + struct { + __IM uint32_t RX_CH0_CNT : 23; /*!< rx ch0 counter register */ + uint32_t : 9; + } bit; + } RX_CH0_COUNTER; + + union { + __IOM uint32_t reg; /*!< rx ch1 counter register */ + + struct { + __IM uint32_t RX_CH1_CNT : 21; /*!< rx ch1 counter register */ + uint32_t : 11; + } bit; + } RX_CH1_COUNTER; + + union { + __IOM uint32_t reg; /*!< rx ch2 counter register */ + + struct { + __IM uint32_t RX_CH2_CNT : 11; /*!< rx ch2 counter register */ + uint32_t : 21; + } bit; + } RX_CH2_COUNTER; + + union { + __IOM uint32_t reg; /*!< rx ch5 counter register */ + + struct { + __IM uint32_t RX_CH5_CNT : 17; /*!< rx ch5 counter register */ + uint32_t : 15; + } bit; + } RX_CH5_COUNTER; +} H264_DMA_Type; /*!< Size = 2916 (0xb64) */ + + + +/* =========================================================================================================================== */ +/* ================ HMAC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief HMAC (Hash-based Message Authentication Code) Accelerator (HMAC) + */ + +typedef struct { /*!< HMAC Structure */ + __IM uint32_t RESERVED[16]; + + union { + __IOM uint32_t reg; /*!< Process control register 0. */ + + struct { + __OM uint32_t SET_START : 1; /*!< Start hmac operation. */ + uint32_t : 31; + } bit; + } SET_START; + + union { + __IOM uint32_t reg; /*!< Configure purpose. */ + + struct { + __OM uint32_t PURPOSE_SET : 4; /*!< Set hmac parameter purpose. */ + uint32_t : 28; + } bit; + } SET_PARA_PURPOSE; + + union { + __IOM uint32_t reg; /*!< Configure key. */ + + struct { + __OM uint32_t KEY_SET : 3; /*!< Set hmac parameter key. */ + uint32_t : 29; + } bit; + } SET_PARA_KEY; + + union { + __IOM uint32_t reg; /*!< Finish initial configuration. */ + + struct { + __OM uint32_t SET_PARA_END : 1; /*!< Finish hmac configuration. */ + uint32_t : 31; + } bit; + } SET_PARA_FINISH; + + union { + __IOM uint32_t reg; /*!< Process control register 1. */ + + struct { + __OM uint32_t SET_TEXT_ONE : 1; /*!< Call SHA to calculate one message block. */ + uint32_t : 31; + } bit; + } SET_MESSAGE_ONE; + + union { + __IOM uint32_t reg; /*!< Process control register 2. */ + + struct { + __OM uint32_t SET_TEXT_ING : 1; /*!< Continue typical hmac. */ + uint32_t : 31; + } bit; + } SET_MESSAGE_ING; + + union { + __IOM uint32_t reg; /*!< Process control register 3. */ + + struct { + __OM uint32_t SET_TEXT_END : 1; /*!< Start hardware padding. */ + uint32_t : 31; + } bit; + } SET_MESSAGE_END; + + union { + __IOM uint32_t reg; /*!< Process control register 4. */ + + struct { + __OM uint32_t SET_RESULT_END : 1; /*!< After read result from upstream, then let hmac back to idle. */ + uint32_t : 31; + } bit; + } SET_RESULT_FINISH; + + union { + __IOM uint32_t reg; /*!< Invalidate register 0. */ + + struct { + __OM uint32_t SET_INVALIDATE_JTAG : 1; /*!< Clear result from hmac downstream JTAG. */ + uint32_t : 31; + } bit; + } SET_INVALIDATE_JTAG; + + union { + __IOM uint32_t reg; /*!< Invalidate register 1. */ + + struct { + __OM uint32_t SET_INVALIDATE_DS : 1; /*!< Clear result from hmac downstream DS. */ + uint32_t : 31; + } bit; + } SET_INVALIDATE_DS; + + union { + __IOM uint32_t reg; /*!< Error register. */ + + struct { + __IM uint32_t QUERY_CHECK : 1; /*!< Hmac configuration state. 0: key are agree with purpose. 1: + error */ + uint32_t : 31; + } bit; + } QUERY_ERROR; + + union { + __IOM uint32_t reg; /*!< Busy register. */ + + struct { + __IM uint32_t BUSY_STATE : 1; /*!< Hmac state. 1'b0: idle. 1'b1: busy */ + uint32_t : 31; + } bit; + } QUERY_BUSY; + __IM uint32_t RESERVED1[4]; + __IOM uint32_t WR_MESSAGE_MEM[16]; /*!< Message block memory. */ + __IOM uint32_t RD_RESULT_MEM[8]; /*!< Result from upstream. */ + __IM uint32_t RESERVED2[4]; + + union { + __IOM uint32_t reg; /*!< Process control register 5. */ + + struct { + __OM uint32_t SET_TEXT_PAD : 1; /*!< Start software padding. */ + uint32_t : 31; + } bit; + } SET_MESSAGE_PAD; + + union { + __IOM uint32_t reg; /*!< Process control register 6. */ + + struct { + __OM uint32_t SET_ONE_BLOCK : 1; /*!< Don't have to do padding. */ + uint32_t : 31; + } bit; + } ONE_BLOCK; + + union { + __IOM uint32_t reg; /*!< Jtag register 0. */ + + struct { + __OM uint32_t SOFT_JTAG_CTRL : 1; /*!< Turn on JTAG verification. */ + uint32_t : 31; + } bit; + } SOFT_JTAG_CTRL; + + union { + __IOM uint32_t reg; /*!< Jtag register 1. */ + + struct { + __OM uint32_t WR_JTAG : 32; /*!< 32-bit of key to be compared. */ + } bit; + } WR_JTAG; + __IM uint32_t RESERVED3[63]; + + union { + __IOM uint32_t reg; /*!< Date register. */ + + struct { + __IOM uint32_t DATE : 30; /*!< Hmac date information/ hmac version information. */ + uint32_t : 2; + } bit; + } DATE; +} HMAC_Type; /*!< Size = 512 (0x200) */ + + + +/* =========================================================================================================================== */ +/* ================ HP_SYS ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief High-Power System (HP_SYS) + */ + +typedef struct { /*!< HP_SYS Structure */ + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_VER_DATE : 32; /*!< NA */ + } bit; + } VER_DATE; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_CLK_EN : 1; /*!< NA */ + uint32_t : 31; + } bit; + } CLK_EN; + __IM uint32_t RESERVED[2]; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t CPU_INTR_FROM_CPU_0 : 1; /*!< set 1 will triger a interrupt */ + uint32_t : 31; + } bit; + } CPU_INTR_FROM_CPU_0; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t CPU_INTR_FROM_CPU_1 : 1; /*!< set 1 will triger a interrupt */ + uint32_t : 31; + } bit; + } CPU_INTR_FROM_CPU_1; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t CPU_INTR_FROM_CPU_2 : 1; /*!< set 1 will triger a interrupt */ + uint32_t : 31; + } bit; + } CPU_INTR_FROM_CPU_2; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t CPU_INTR_FROM_CPU_3 : 1; /*!< set 1 will triger a interrupt */ + uint32_t : 31; + } bit; + } CPU_INTR_FROM_CPU_3; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_L2_CACHE_CLK_ON : 1; /*!< l2 cahce clk enable */ + __IOM uint32_t REG_L1_D_CACHE_CLK_ON : 1; /*!< l1 dcahce clk enable */ + uint32_t : 2; + __IOM uint32_t REG_L1_I1_CACHE_CLK_ON : 1;/*!< l1 icahce1 clk enable */ + __IOM uint32_t REG_L1_I0_CACHE_CLK_ON : 1;/*!< l1 icahce0 clk enable */ + uint32_t : 26; + } bit; + } CACHE_CLK_CONFIG; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + uint32_t : 1; + __IOM uint32_t REG_L1_D_CACHE_RESET : 1; /*!< set 1 to reset l1 dcahce */ + uint32_t : 2; + __IOM uint32_t REG_L1_I1_CACHE_RESET : 1; /*!< set 1 to reset l1 icahce1 */ + __IOM uint32_t REG_L1_I0_CACHE_RESET : 1; /*!< set 1 to reset l1 icahce0 */ + uint32_t : 26; + } bit; + } CACHE_RESET_CONFIG; + __IM uint32_t RESERVED1; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_SYS_DMA_ADDR_SEL : 1; /*!< 0 means dma access extmem use 8xxx_xxxx else use 4xxx_xxxx */ + uint32_t : 31; + } bit; + } DMA_ADDR_CTRL; + __IM uint32_t RESERVED2; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_TCM_RAM_IBUS0_WT : 3; /*!< weight value of ibus0 */ + __IOM uint32_t REG_TCM_RAM_IBUS1_WT : 3; /*!< weight value of ibus1 */ + __IOM uint32_t REG_TCM_RAM_IBUS2_WT : 3; /*!< weight value of ibus2 */ + __IOM uint32_t REG_TCM_RAM_IBUS3_WT : 3; /*!< weight value of ibus3 */ + __IOM uint32_t REG_TCM_RAM_DBUS0_WT : 3; /*!< weight value of dbus0 */ + __IOM uint32_t REG_TCM_RAM_DBUS1_WT : 3; /*!< weight value of dbus1 */ + __IOM uint32_t REG_TCM_RAM_DBUS2_WT : 3; /*!< weight value of dbus2 */ + __IOM uint32_t REG_TCM_RAM_DBUS3_WT : 3; /*!< weight value of dbus3 */ + __IOM uint32_t REG_TCM_RAM_DMA_WT : 3; /*!< weight value of dma */ + uint32_t : 4; + __IOM uint32_t REG_TCM_RAM_WRR_HIGH : 1; /*!< enable weighted round robin arbitration */ + } bit; + } TCM_RAM_WRR_CONFIG; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_TCM_SW_PARITY_BWE_MASK_CTRL : 1;/*!< Set 1 to mask tcm bwe parity code bit */ + uint32_t : 31; + } bit; + } TCM_SW_PARITY_BWE_MASK; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_HP_TCM_CLK_FORCE_ON : 1;/*!< hp_tcm clk gatig force on */ + uint32_t : 31; + } bit; + } TCM_RAM_PWR_CTRL0; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_L2_ROM_CLK_FORCE_ON : 1;/*!< l2_rom clk gating force on */ + uint32_t : 31; + } bit; + } L2_ROM_PWR_CTRL0; + __IM uint32_t RESERVED3[3]; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_PROBE_A_MOD_SEL : 16; /*!< Tihs field is used to selec probe_group from probe_group0 to + probe_group15 for module's probe_out[31:0] in a mode */ + __IOM uint32_t REG_PROBE_A_TOP_SEL : 8; /*!< Tihs field is used to selec module's probe_out[31:0] as probe + out in a mode */ + __IOM uint32_t REG_PROBE_L_SEL : 2; /*!< Tihs field is used to selec probe_out[31:16] */ + __IOM uint32_t REG_PROBE_H_SEL : 2; /*!< Tihs field is used to selec probe_out[31:16] */ + __IOM uint32_t REG_PROBE_GLOBAL_EN : 1; /*!< Set this bit to enable global debug probe in hp system. */ + uint32_t : 3; + } bit; + } PROBEA_CTRL; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_PROBE_B_MOD_SEL : 16; /*!< Tihs field is used to selec probe_group from probe_group0 to + probe_group15 for module's probe_out[31:0] in b mode. */ + __IOM uint32_t REG_PROBE_B_TOP_SEL : 8; /*!< Tihs field is used to select module's probe_out[31:0] as probe_out + in b mode */ + __IOM uint32_t REG_PROBE_B_EN : 1; /*!< Set this bit to enable b mode for debug probe. 1: b mode, 0: + a mode. */ + uint32_t : 7; + } bit; + } PROBEB_CTRL; + __IM uint32_t RESERVED4; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t REG_PROBE_TOP_OUT : 32; /*!< NA */ + } bit; + } PROBE_OUT; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_L2_MEM_CLK_FORCE_ON : 1;/*!< l2ram clk_gating force on */ + uint32_t : 31; + } bit; + } L2_MEM_RAM_PWR_CTRL0; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t REG_CORE0_CORESTALLED_ST : 1;/*!< hp core0 corestalled status */ + __IM uint32_t REG_CORE1_CORESTALLED_ST : 1;/*!< hp core1 corestalled status */ + uint32_t : 30; + } bit; + } CPU_CORESTALLED_ST; + __IM uint32_t RESERVED5[2]; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_ENABLE_SPI_MANUAL_ENCRYPT : 1;/*!< NA */ + __IOM uint32_t REG_ENABLE_DOWNLOAD_DB_ENCRYPT : 1;/*!< NA */ + __IOM uint32_t REG_ENABLE_DOWNLOAD_G0CB_DECRYPT : 1;/*!< NA */ + __IOM uint32_t REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : 1;/*!< NA */ + uint32_t : 28; + } bit; + } CRYPTO_CTRL; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_GPIO_0_HOLD_LOW : 32; /*!< hold control for gpio47~16 */ + } bit; + } GPIO_O_HOLD_CTRL0; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_GPIO_0_HOLD_HIGH : 9; /*!< hold control for gpio56~48 */ + uint32_t : 23; + } bit; + } GPIO_O_HOLD_CTRL1; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_HP_SYS_RDN_ECO_EN : 1; /*!< NA */ + __IM uint32_t REG_HP_SYS_RDN_ECO_RESULT : 1;/*!< NA */ + uint32_t : 30; + } bit; + } RDN_ECO_CS; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_CACHE_APB_POSTW_EN : 1;/*!< cache apb register interface post write enable, 1 will speed + up write, but will take some time to update value to register */ + uint32_t : 31; + } bit; + } CACHE_APB_POSTW_EN; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_L2_MEM_SUB_BLKSIZE : 2;/*!< l2mem sub block size 00=>32 01=>64 10=>128 11=>256 */ + uint32_t : 30; + } bit; + } L2_MEM_SUBSIZE; + __IM uint32_t RESERVED6[5]; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_L2_MEM_ECC_ERR_INT_RAW : 1;/*!< intr triggered when two bit error detected and corrected from + ecc */ + __IOM uint32_t REG_L2_MEM_EXCEED_ADDR_INT_RAW : 1;/*!< intr triggered when access addr exceeds 0xff9ffff at bypass + mode or exceeds 0xff80000 at l2cache 128kb mode or exceeds + 0xff60000 at l2cache 256kb mode */ + __IOM uint32_t REG_L2_MEM_ERR_RESP_INT_RAW : 1;/*!< intr triggered when err response occurs */ + uint32_t : 29; + } bit; + } L2_MEM_INT_RAW; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t REG_L2_MEM_ECC_ERR_INT_ST : 1;/*!< NA */ + __IM uint32_t REG_L2_MEM_EXCEED_ADDR_INT_ST : 1;/*!< NA */ + __IM uint32_t REG_L2_MEM_ERR_RESP_INT_ST : 1;/*!< NA */ + uint32_t : 29; + } bit; + } L2_MEM_INT_ST; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_L2_MEM_ECC_ERR_INT_ENA : 1;/*!< NA */ + __IOM uint32_t REG_L2_MEM_EXCEED_ADDR_INT_ENA : 1;/*!< NA */ + __IOM uint32_t REG_L2_MEM_ERR_RESP_INT_ENA : 1;/*!< NA */ + uint32_t : 29; + } bit; + } L2_MEM_INT_ENA; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __OM uint32_t REG_L2_MEM_ECC_ERR_INT_CLR : 1;/*!< NA */ + __OM uint32_t REG_L2_MEM_EXCEED_ADDR_INT_CLR : 1;/*!< NA */ + __OM uint32_t REG_L2_MEM_ERR_RESP_INT_CLR : 1;/*!< NA */ + uint32_t : 29; + } bit; + } L2_MEM_INT_CLR; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_L2_RAM_UNIT0_ECC_EN : 1;/*!< NA */ + __IOM uint32_t REG_L2_RAM_UNIT1_ECC_EN : 1;/*!< NA */ + __IOM uint32_t REG_L2_RAM_UNIT2_ECC_EN : 1;/*!< NA */ + __IOM uint32_t REG_L2_RAM_UNIT3_ECC_EN : 1;/*!< NA */ + __IOM uint32_t REG_L2_RAM_UNIT4_ECC_EN : 1;/*!< NA */ + __IOM uint32_t REG_L2_RAM_UNIT5_ECC_EN : 1;/*!< NA */ + uint32_t : 26; + } bit; + } L2_MEM_L2_RAM_ECC; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t REG_L2_MEM_EXCEED_ADDR_INT_ADDR : 21;/*!< NA */ + __IM uint32_t REG_L2_MEM_EXCEED_ADDR_INT_WE : 1;/*!< NA */ + __IM uint32_t REG_L2_MEM_EXCEED_ADDR_INT_MASTER : 3;/*!< NA */ + uint32_t : 7; + } bit; + } L2_MEM_INT_RECORD0; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t REG_L2_MEM_ECC_ERR_INT_ADDR : 15;/*!< NA */ + __IM uint32_t REG_L2_MEM_ECC_ONE_BIT_ERR : 1;/*!< NA */ + __IM uint32_t REG_L2_MEM_ECC_TWO_BIT_ERR : 1;/*!< NA */ + __IM uint32_t REG_L2_MEM_ECC_ERR_BIT : 9;/*!< NA */ + __IM uint32_t REG_L2_CACHE_ERR_BANK : 1; /*!< NA */ + uint32_t : 5; + } bit; + } L2_MEM_INT_RECORD1; + __IM uint32_t RESERVED7[3]; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_L2_CACHE_ECC_EN : 1; /*!< NA */ + uint32_t : 31; + } bit; + } L2_MEM_L2_CACHE_ECC; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_L1_CACHE_BUS0_ID : 4; /*!< NA */ + uint32_t : 28; + } bit; + } L1CACHE_BUS0_ID; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_L1_CACHE_BUS1_ID : 4; /*!< NA */ + uint32_t : 28; + } bit; + } L1CACHE_BUS1_ID; + __IM uint32_t RESERVED8[2]; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_L2_MEM_RDN_ECO_EN : 1; /*!< NA */ + __IM uint32_t REG_L2_MEM_RDN_ECO_RESULT : 1;/*!< NA */ + uint32_t : 30; + } bit; + } L2_MEM_RDN_ECO_CS; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_L2_MEM_RDN_ECO_LOW : 32;/*!< NA */ + } bit; + } L2_MEM_RDN_ECO_LOW; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_L2_MEM_RDN_ECO_HIGH : 32;/*!< NA */ + } bit; + } L2_MEM_RDN_ECO_HIGH; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_HP_TCM_RDN_ECO_EN : 1; /*!< NA */ + __IM uint32_t REG_HP_TCM_RDN_ECO_RESULT : 1;/*!< NA */ + uint32_t : 30; + } bit; + } TCM_RDN_ECO_CS; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_HP_TCM_RDN_ECO_LOW : 32;/*!< NA */ + } bit; + } TCM_RDN_ECO_LOW; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_HP_TCM_RDN_ECO_HIGH : 32;/*!< NA */ + } bit; + } TCM_RDN_ECO_HIGH; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_GPIO_DED_HOLD : 26; /*!< hold control for gpio63~56 */ + uint32_t : 6; + } bit; + } GPIO_DED_HOLD_CTRL; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_L2_MEM_SW_ECC_BWE_MASK_CTRL : 1;/*!< Set 1 to mask bwe hamming code bit */ + uint32_t : 31; + } bit; + } L2_MEM_SW_ECC_BWE_MASK; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_USB20_MEM_CLK_FORCE_ON : 1;/*!< NA */ + uint32_t : 31; + } bit; + } USB20OTG_MEM_CTRL; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 31; + __IOM uint32_t TCM_PARITY_ERR_INT_RAW : 1;/*!< need_des */ + } bit; + } TCM_INT_RAW; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 31; + __IM uint32_t TCM_PARITY_ERR_INT_ST : 1; /*!< need_des */ + } bit; + } TCM_INT_ST; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 31; + __IOM uint32_t TCM_PARITY_ERR_INT_ENA : 1;/*!< need_des */ + } bit; + } TCM_INT_ENA; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 31; + __OM uint32_t TCM_PARITY_ERR_INT_CLR : 1;/*!< need_des */ + } bit; + } TCM_INT_CLR; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IM uint32_t TCM_PARITY_ERR_INT_ADDR : 13;/*!< hp tcm_parity_err_addr */ + uint32_t : 19; + } bit; + } TCM_PARITY_INT_RECORD; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_L1_CACHE_MEM_FO : 6; /*!< need_des */ + uint32_t : 26; + } bit; + } L1_CACHE_PWR_CTRL; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_L2_CACHE_MEM_FO : 2; /*!< need_des */ + uint32_t : 30; + } bit; + } L2_CACHE_PWR_CTRL; + + union { + __IOM uint32_t reg; /*!< CPU_WAITI configuration register */ + + struct { + __IOM uint32_t CPU_WAIT_MODE_FORCE_ON : 1;/*!< Set 1 to force cpu_waiti_clk enable. */ + __IOM uint32_t CPU_WAITI_DELAY_NUM : 4; /*!< This field used to set delay cycle when cpu enter waiti mode, + after delay waiti_clk will close */ + uint32_t : 27; + } bit; + } CPU_WAITI_CONF; + + union { + __IOM uint32_t reg; /*!< Core Debug runstall configure register */ + + struct { + __IOM uint32_t CORE_DEBUG_RUNSTALL_ENABLE : 1;/*!< Set this field to 1 to enable debug runstall feature between + HP-core and LP-core. */ + uint32_t : 31; + } bit; + } CORE_DEBUG_RUNSTALL_CONF; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t EN : 1; /*!< set this field to 1 to enable hp core0&1 ahb timeout handle */ + __IOM uint32_t THRES : 16; /*!< This field used to set hp core0&1 ahb bus timeout threshold */ + uint32_t : 15; + } bit; + } CORE_AHB_TIMEOUT; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t EN : 1; /*!< set this field to 1 to enable hp core0&1 ibus timeout handle */ + __IOM uint32_t THRES : 16; /*!< This field used to set hp core0&1 ibus timeout threshold */ + uint32_t : 15; + } bit; + } CORE_IBUS_TIMEOUT; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t EN : 1; /*!< set this field to 1 to enable hp core0&1 dbus timeout handle */ + __IOM uint32_t THRES : 16; /*!< This field used to set hp core0&1 dbus timeout threshold */ + uint32_t : 15; + } bit; + } CORE_DBUS_TIMEOUT; + __IM uint32_t RESERVED9[3]; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t CPU_ICM_H2X_POST_WR_EN : 1;/*!< need_des */ + __IOM uint32_t CPU_ICM_H2X_CUT_THROUGH_EN : 1;/*!< need_des */ + __IM uint32_t CPU_ICM_H2X_BRIDGE_BUSY : 1;/*!< need_des */ + uint32_t : 29; + } bit; + } ICM_CPU_H2X_CFG; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t PERI1_APB_POSTW_EN : 1; /*!< hp_peri1 apb register interface post write enable, 1 will speed + up write, but will take some time to update value to register */ + uint32_t : 31; + } bit; + } PERI1_APB_POSTW_EN; + + union { + __IOM uint32_t reg; /*!< Bitscrambler Peri Sel */ + + struct { + __IOM uint32_t BITSCRAMBLER_PERI_RX_SEL : 4;/*!< Set this field to sel peri with DMA RX interface to connec with + bitscrambler: 4'h0 : lcd_cam, 4'h1: gpspi2, 4'h2: gpspi3, + 4'h3: parl_io, 4'h4: aes, 4'h5: sha, 4'h6: adc, 4'h7: i2s0, + 4'h8: i2s1, 4'h9: i2s2, 4'ha: i3c_mst, 4'hb: uhci0, 4'hc: + RMT, else : none */ + __IOM uint32_t BITSCRAMBLER_PERI_TX_SEL : 4;/*!< Set this field to sel peri with DMA TX interface to connec with + bitscrambler: 4'h0 : lcd_cam, 4'h1: gpspi2, 4'h2: gpspi3, + 4'h3: parl_io, 4'h4: aes, 4'h5: sha, 4'h6: adc, 4'h7: i2s0, + 4'h8: i2s1, 4'h9: i2s2, 4'ha: i3c_mst, 4'hb: uhci0, 4'hc: + RMT, else : none */ + uint32_t : 24; + } bit; + } BITSCRAMBLER_PERI_SEL; + + union { + __IOM uint32_t reg; /*!< N/A */ + + struct { + __IOM uint32_t GMAC_APB_POSTW_EN : 1; /*!< N/A */ + __IOM uint32_t DSI_HOST_APB_POSTW_EN : 1; /*!< N/A */ + __IOM uint32_t CSI_HOST_APB_SYNC_POSTW_EN : 1;/*!< N/A */ + __IOM uint32_t CSI_HOST_APB_ASYNC_POSTW_EN : 1;/*!< N/A */ + uint32_t : 28; + } bit; + } APB_SYNC_POSTW_EN; + + union { + __IOM uint32_t reg; /*!< N/A */ + + struct { + __IOM uint32_t DEBUG_CH_NUM : 2; /*!< N/A */ + uint32_t : 30; + } bit; + } GDMA_CTRL; + + union { + __IOM uint32_t reg; /*!< N/A */ + + struct { + __IM uint32_t PTP_PPS : 1; /*!< N/A */ + __IOM uint32_t SBD_FLOWCTRL : 1; /*!< N/A */ + __IOM uint32_t PHY_INTF_SEL : 3; /*!< N/A */ + __IOM uint32_t GMAC_MEM_CLK_FORCE_ON : 1; /*!< N/A */ + __IM uint32_t GMAC_RST_CLK_TX_N : 1; /*!< N/A */ + __IM uint32_t GMAC_RST_CLK_RX_N : 1; /*!< N/A */ + uint32_t : 24; + } bit; + } GMAC_CTRL0; + + union { + __IOM uint32_t reg; /*!< N/A */ + + struct { + __IM uint32_t PTP_TIMESTAMP_L : 32; /*!< N/A */ + } bit; + } GMAC_CTRL1; + + union { + __IOM uint32_t reg; /*!< N/A */ + + struct { + __IM uint32_t PTP_TIMESTAMP_H : 32; /*!< N/A */ + } bit; + } GMAC_CTRL2; + + union { + __IOM uint32_t reg; /*!< N/A */ + + struct { + __IOM uint32_t PPA_LSLP_MEM_PD : 1; /*!< N/A */ + __IOM uint32_t JPEG_SDSLP_MEM_PD : 1; /*!< N/A */ + __IOM uint32_t JPEG_LSLP_MEM_PD : 1; /*!< N/A */ + __IOM uint32_t JPEG_DSLP_MEM_PD : 1; /*!< N/A */ + __IOM uint32_t DMA2D_LSLP_MEM_PD : 1; /*!< N/A */ + uint32_t : 27; + } bit; + } VPU_CTRL; + + union { + __IOM uint32_t reg; /*!< N/A */ + + struct { + __IM uint32_t OTG_PHY_TEST_DONE : 1; /*!< N/A */ + __IOM uint32_t USB_MEM_AUX_CTRL : 14; /*!< N/A */ + __IOM uint32_t PHY_SUSPENDM : 1; /*!< N/A */ + __IOM uint32_t PHY_SUSPEND_FORCE_EN : 1; /*!< N/A */ + __IOM uint32_t PHY_RSTN : 1; /*!< N/A */ + __IOM uint32_t PHY_RESET_FORCE_EN : 1; /*!< N/A */ + __IOM uint32_t PHY_PLL_FORCE_EN : 1; /*!< N/A */ + __IOM uint32_t PHY_PLL_EN : 1; /*!< N/A */ + __IOM uint32_t OTG_SUSPENDM : 1; /*!< N/A */ + __IOM uint32_t OTG_PHY_TXBITSTUFF_EN : 1; /*!< N/A */ + __IOM uint32_t OTG_PHY_REFCLK_MODE : 1; /*!< N/A */ + __IOM uint32_t OTG_PHY_BISTEN : 1; /*!< N/A */ + uint32_t : 7; + } bit; + } USBOTG20_CTRL; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t TCM_ERR_RESP_EN : 1; /*!< Set 1 to turn on tcm error response */ + uint32_t : 31; + } bit; + } TCM_ERR_RESP_CTRL; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_L2_MEM_UNIT0_REFERSH_EN : 1;/*!< NA */ + __IOM uint32_t REG_L2_MEM_UNIT1_REFERSH_EN : 1;/*!< NA */ + __IOM uint32_t REG_L2_MEM_UNIT2_REFERSH_EN : 1;/*!< NA */ + __IOM uint32_t REG_L2_MEM_UNIT3_REFERSH_EN : 1;/*!< NA */ + __IOM uint32_t REG_L2_MEM_UNIT4_REFERSH_EN : 1;/*!< NA */ + __IOM uint32_t REG_L2_MEM_UNIT5_REFERSH_EN : 1;/*!< NA */ + __IOM uint32_t REG_L2_MEM_REFERSH_CNT_RESET : 1;/*!< Set 1 to reset l2mem_refresh_cnt */ + __IM uint32_t REG_L2_MEM_UNIT0_REFRESH_DONE : 1;/*!< NA */ + __IM uint32_t REG_L2_MEM_UNIT1_REFRESH_DONE : 1;/*!< NA */ + __IM uint32_t REG_L2_MEM_UNIT2_REFRESH_DONE : 1;/*!< NA */ + __IM uint32_t REG_L2_MEM_UNIT3_REFRESH_DONE : 1;/*!< NA */ + __IM uint32_t REG_L2_MEM_UNIT4_REFRESH_DONE : 1;/*!< NA */ + __IM uint32_t REG_L2_MEM_UNIT5_REFRESH_DONE : 1;/*!< NA */ + uint32_t : 19; + } bit; + } L2_MEM_REFRESH; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_TCM_INIT_EN : 1; /*!< NA */ + __IOM uint32_t REG_TCM_INIT_CNT_RESET : 1;/*!< Set 1 to reset tcm init cnt */ + __IM uint32_t REG_TCM_INIT_DONE : 1; /*!< NA */ + uint32_t : 29; + } bit; + } TCM_INIT; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t TCM_PARITY_CHECK_EN : 1; /*!< Set 1 to turn on tcm parity check */ + uint32_t : 31; + } bit; + } TCM_PARITY_CHECK_CTRL; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t DFV0 : 32; /*!< register for DV */ + } bit; + } DESIGN_FOR_VERIFICATION0; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t DFV1 : 32; /*!< register for DV */ + } bit; + } DESIGN_FOR_VERIFICATION1; + __IM uint32_t RESERVED10[2]; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t CPU : 1; /*!< Set 1 to enable addr interchange between psram and flash in + axi matrix when hp cpu access through cache */ + __IOM uint32_t DMA : 1; /*!< Set 1 to enable addr interchange between psram and flash in + axi matrix when dma device access, lp core access and hp + core access through ahb */ + uint32_t : 30; + } bit; + } PSRAM_FLASH_ADDR_INTERCHANGE; + __IM uint32_t RESERVED11; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t CPU_ICM_H2X_BRESP_ERR_INT_RAW : 1;/*!< the raw interrupt status of bresp error, triggered when if bresp + err occurs in post write mode in ahb2axi. */ + uint32_t : 31; + } bit; + } AHB2AXI_BRESP_ERR_INT_RAW; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 31; + __IM uint32_t CPU_ICM_H2X_BRESP_ERR_INT_ST : 1;/*!< the masked interrupt status of cpu_icm_h2x_bresp_err */ + } bit; + } AHB2AXI_BRESP_ERR_INT_ST; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 31; + __IOM uint32_t CPU_ICM_H2X_BRESP_ERR_INT_ENA : 1;/*!< Write 1 to enable cpu_icm_h2x_bresp_err int */ + } bit; + } AHB2AXI_BRESP_ERR_INT_ENA; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 31; + __OM uint32_t CPU_ICM_H2X_BRESP_ERR_INT_CLR : 1;/*!< Write 1 to clear cpu_icm_h2x_bresp_err int */ + } bit; + } AHB2AXI_BRESP_ERR_INT_CLR; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t L2_MEM_ERR_RESP_EN : 1; /*!< Set 1 to turn on l2mem error response */ + uint32_t : 31; + } bit; + } L2_MEM_ERR_RESP_CTRL; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t L2_MEM_AHB_WRBUFFER_EN : 1;/*!< Set 1 to turn on l2mem ahb wr buffer */ + __IOM uint32_t L2_MEM_AHB_RDBUFFER_EN : 1;/*!< Set 1 to turn on l2mem ahb rd buffer */ + uint32_t : 30; + } bit; + } L2_MEM_AHB_BUFFER_CTRL; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IM uint32_t CORE_DMACTIVE_LPCORE : 1; /*!< hp core dmactive_lpcore value */ + uint32_t : 31; + } bit; + } CORE_DMACTIVE_LPCORE; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t CORE_ERR_RESP_DIS : 3; /*!< Set bit0 to disable ibus err resp. Set bit1 to disable dbus + err resp. Set bit 2 to disable ahb err resp. */ + uint32_t : 29; + } bit; + } CORE_ERR_RESP_DIS; + + union { + __IOM uint32_t reg; /*!< Hp core bus timeout interrupt raw register */ + + struct { + __IOM uint32_t CORE0_AHB_TIMEOUT_INT_RAW : 1;/*!< the raw interrupt status of hp core0 ahb timeout */ + __IOM uint32_t CORE1_AHB_TIMEOUT_INT_RAW : 1;/*!< the raw interrupt status of hp core1 ahb timeout */ + __IOM uint32_t CORE0_IBUS_TIMEOUT_INT_RAW : 1;/*!< the raw interrupt status of hp core0 ibus timeout */ + __IOM uint32_t CORE1_IBUS_TIMEOUT_INT_RAW : 1;/*!< the raw interrupt status of hp core1 ibus timeout */ + __IOM uint32_t CORE0_DBUS_TIMEOUT_INT_RAW : 1;/*!< the raw interrupt status of hp core0 dbus timeout */ + __IOM uint32_t CORE1_DBUS_TIMEOUT_INT_RAW : 1;/*!< the raw interrupt status of hp core1 dbus timeout */ + uint32_t : 26; + } bit; + } CORE_TIMEOUT_INT_RAW; + + union { + __IOM uint32_t reg; /*!< masked interrupt register */ + + struct { + __IM uint32_t CORE0_AHB_TIMEOUT_INT_ST : 1;/*!< the masked interrupt status of hp core0 ahb timeout */ + __IM uint32_t CORE1_AHB_TIMEOUT_INT_ST : 1;/*!< the masked interrupt status of hp core1 ahb timeout */ + __IM uint32_t CORE0_IBUS_TIMEOUT_INT_ST : 1;/*!< the masked interrupt status of hp core0 ibus timeout */ + __IM uint32_t CORE1_IBUS_TIMEOUT_INT_ST : 1;/*!< the masked interrupt status of hp core1 ibus timeout */ + __IM uint32_t CORE0_DBUS_TIMEOUT_INT_ST : 1;/*!< the masked interrupt status of hp core0 dbus timeout */ + __IM uint32_t CORE1_DBUS_TIMEOUT_INT_ST : 1;/*!< the masked interrupt status of hp core1 dbus timeout */ + uint32_t : 26; + } bit; + } CORE_TIMEOUT_INT_ST; + + union { + __IOM uint32_t reg; /*!< masked interrupt register */ + + struct { + __IOM uint32_t CORE0_AHB_TIMEOUT_INT_ENA : 1;/*!< Write 1 to enable hp_core0_ahb_timeout int */ + __IOM uint32_t CORE1_AHB_TIMEOUT_INT_ENA : 1;/*!< Write 1 to enable hp_core1_ahb_timeout int */ + __IOM uint32_t CORE0_IBUS_TIMEOUT_INT_ENA : 1;/*!< Write 1 to enable hp_core0_ibus_timeout int */ + __IOM uint32_t CORE1_IBUS_TIMEOUT_INT_ENA : 1;/*!< Write 1 to enable hp_core1_ibus_timeout int */ + __IOM uint32_t CORE0_DBUS_TIMEOUT_INT_ENA : 1;/*!< Write 1 to enable hp_core0_dbus_timeout int */ + __IOM uint32_t CORE1_DBUS_TIMEOUT_INT_ENA : 1;/*!< Write 1 to enable hp_core1_dbus_timeout int */ + uint32_t : 26; + } bit; + } CORE_TIMEOUT_INT_ENA; + + union { + __IOM uint32_t reg; /*!< interrupt clear register */ + + struct { + __OM uint32_t CORE0_AHB_TIMEOUT_INT_CLR : 1;/*!< Write 1 to clear hp_core0_ahb_timeout int */ + __OM uint32_t CORE1_AHB_TIMEOUT_INT_CLR : 1;/*!< Write 1 to clear hp_core1_ahb_timeout int */ + __OM uint32_t CORE0_IBUS_TIMEOUT_INT_CLR : 1;/*!< Write 1 to clear hp_core0_ibus_timeout int */ + __OM uint32_t CORE1_IBUS_TIMEOUT_INT_CLR : 1;/*!< Write 1 to clear hp_core1_ibus_timeout int */ + __OM uint32_t CORE0_DBUS_TIMEOUT_INT_CLR : 1;/*!< Write 1 to clear hp_core0_dbus_timeout int */ + __OM uint32_t CORE1_DBUS_TIMEOUT_INT_CLR : 1;/*!< Write 1 to clear hp_core1_dbus_timeout int */ + uint32_t : 26; + } bit; + } CORE_TIMEOUT_INT_CLR; + __IM uint32_t RESERVED12[2]; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_GPIO_0_HYS_LOW : 32; /*!< hys control for gpio47~16 */ + } bit; + } GPIO_O_HYS_CTRL0; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_GPIO_0_HYS_HIGH : 9; /*!< hys control for gpio56~48 */ + uint32_t : 23; + } bit; + } GPIO_O_HYS_CTRL1; + __IM uint32_t RESERVED13[2]; + + union { + __IOM uint32_t reg; /*!< rsa pd ctrl register */ + + struct { + __IOM uint32_t RSA_MEM_FORCE_PD : 1; /*!< Set this bit to power down rsa internal memory. */ + __IOM uint32_t RSA_MEM_FORCE_PU : 1; /*!< Set this bit to force power up rsa internal memory */ + __IOM uint32_t RSA_MEM_PD : 1; /*!< Set this bit to force power down rsa internal memory. */ + uint32_t : 29; + } bit; + } RSA_PD_CTRL; + + union { + __IOM uint32_t reg; /*!< ecc pd ctrl register */ + + struct { + __IOM uint32_t ECC_MEM_FORCE_PD : 1; /*!< Set this bit to power down ecc internal memory. */ + __IOM uint32_t ECC_MEM_FORCE_PU : 1; /*!< Set this bit to force power up ecc internal memory */ + __IOM uint32_t ECC_MEM_PD : 1; /*!< Set this bit to force power down ecc internal memory. */ + uint32_t : 29; + } bit; + } ECC_PD_CTRL; + + union { + __IOM uint32_t reg; /*!< rng cfg register */ + + struct { + __IOM uint32_t RNG_SAMPLE_ENABLE : 1; /*!< enable rng sample chain */ + uint32_t : 15; + __IOM uint32_t RNG_CHAIN_CLK_DIV_NUM : 8; /*!< chain clk div num to pad for debug */ + __IM uint32_t RNG_SAMPLE_CNT : 8; /*!< debug rng sample cnt */ + } bit; + } RNG_CFG; + + union { + __IOM uint32_t reg; /*!< ecc pd ctrl register */ + + struct { + __IOM uint32_t UART_MEM_FORCE_PD : 1; /*!< Set this bit to power down hp uart internal memory. */ + __IOM uint32_t UART_MEM_FORCE_PU : 1; /*!< Set this bit to force power up hp uart internal memory */ + uint32_t : 30; + } bit; + } UART_PD_CTRL; + + union { + __IOM uint32_t reg; /*!< hp peri mem clk force on regpster */ + + struct { + __IOM uint32_t RMT_MEM_CLK_FORCE_ON : 1; /*!< Set this bit to force on mem clk in rmt */ + __IOM uint32_t BITSCRAMBLER_TX_MEM_CLK_FORCE_ON : 1;/*!< Set this bit to force on tx mem clk in bitscrambler */ + __IOM uint32_t BITSCRAMBLER_RX_MEM_CLK_FORCE_ON : 1;/*!< Set this bit to force on rx mem clk in bitscrambler */ + __IOM uint32_t GDMA_MEM_CLK_FORCE_ON : 1; /*!< Set this bit to force on mem clk in gdma */ + uint32_t : 28; + } bit; + } PERI_MEM_CLK_FORCE_ON; +} HP_SYS_Type; /*!< Size = 484 (0x1e4) */ + + + +/* =========================================================================================================================== */ +/* ================ HP_SYS_CLKRST ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief HP_SYS_CLKRST Peripheral (HP_SYS_CLKRST) + */ + +typedef struct { /*!< HP_SYS_CLKRST Structure */ + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_CLK_EN : 1; /*!< Reserved */ + uint32_t : 31; + } bit; + } CLK_EN0; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_CPUICM_DELAY_NUM : 4; /*!< Reserved */ + __OM uint32_t REG_SOC_CLK_DIV_UPDATE : 1;/*!< Reserved */ + __IOM uint32_t REG_CPU_CLK_DIV_NUM : 8; /*!< Reserved */ + __IOM uint32_t REG_CPU_CLK_DIV_NUMERATOR : 8;/*!< Reserved */ + __IOM uint32_t REG_CPU_CLK_DIV_DENOMINATOR : 8;/*!< Reserved */ + uint32_t : 3; + } bit; + } ROOT_CLK_CTRL0; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_MEM_CLK_DIV_NUM : 8; /*!< Reserved */ + __IOM uint32_t REG_MEM_CLK_DIV_NUMERATOR : 8;/*!< Reserved */ + __IOM uint32_t REG_MEM_CLK_DIV_DENOMINATOR : 8;/*!< Reserved */ + __IOM uint32_t REG_SYS_CLK_DIV_NUM : 8; /*!< Reserved */ + } bit; + } ROOT_CLK_CTRL1; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_SYS_CLK_DIV_NUMERATOR : 8;/*!< Reserved */ + __IOM uint32_t REG_SYS_CLK_DIV_DENOMINATOR : 8;/*!< Reserved */ + __IOM uint32_t REG_APB_CLK_DIV_NUM : 8; /*!< Reserved */ + __IOM uint32_t REG_APB_CLK_DIV_NUMERATOR : 8;/*!< Reserved */ + } bit; + } ROOT_CLK_CTRL2; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_APB_CLK_DIV_DENOMINATOR : 8;/*!< Reserved */ + uint32_t : 24; + } bit; + } ROOT_CLK_CTRL3; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_CORE0_CLIC_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_CORE1_CLIC_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_MISC_CPU_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_CORE0_CPU_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_CORE1_CPU_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_TCM_CPU_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_BUSMON_CPU_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_L1CACHE_CPU_CLK_EN : 1;/*!< Reserved */ + __IOM uint32_t REG_L1CACHE_D_CPU_CLK_EN : 1;/*!< Reserved */ + __IOM uint32_t REG_L1CACHE_I0_CPU_CLK_EN : 1;/*!< Reserved */ + __IOM uint32_t REG_L1CACHE_I1_CPU_CLK_EN : 1;/*!< Reserved */ + __IOM uint32_t REG_TRACE_CPU_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_ICM_CPU_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_GDMA_CPU_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_VPU_CPU_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_L1CACHE_MEM_CLK_EN : 1;/*!< Reserved */ + __IOM uint32_t REG_L1CACHE_D_MEM_CLK_EN : 1;/*!< Reserved */ + __IOM uint32_t REG_L1CACHE_I0_MEM_CLK_EN : 1;/*!< Reserved */ + __IOM uint32_t REG_L1CACHE_I1_MEM_CLK_EN : 1;/*!< Reserved */ + __IOM uint32_t REG_L2CACHE_MEM_CLK_EN : 1;/*!< Reserved */ + __IOM uint32_t REG_L2MEM_MEM_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_L2MEMMON_MEM_CLK_EN : 1;/*!< Reserved */ + __IOM uint32_t REG_ICM_MEM_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_MISC_SYS_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_TRACE_SYS_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_L2CACHE_SYS_CLK_EN : 1;/*!< Reserved */ + __IOM uint32_t REG_L2MEM_SYS_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_L2MEMMON_SYS_CLK_EN : 1;/*!< Reserved */ + __IOM uint32_t REG_TCMMON_SYS_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_ICM_SYS_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_FLASH_SYS_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_PSRAM_SYS_CLK_EN : 1; /*!< Reserved */ + } bit; + } SOC_CLK_CTRL0; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_GPSPI2_SYS_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_GPSPI3_SYS_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_REGDMA_SYS_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_AHB_PDMA_SYS_CLK_EN : 1;/*!< Reserved */ + __IOM uint32_t REG_AXI_PDMA_SYS_CLK_EN : 1;/*!< Reserved */ + __IOM uint32_t REG_GDMA_SYS_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_DMA2D_SYS_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_VPU_SYS_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_JPEG_SYS_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_PPA_SYS_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_CSI_BRG_SYS_CLK_EN : 1;/*!< Reserved */ + __IOM uint32_t REG_CSI_HOST_SYS_CLK_EN : 1;/*!< Reserved */ + __IOM uint32_t REG_DSI_SYS_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_EMAC_SYS_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_SDMMC_SYS_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_USB_OTG11_SYS_CLK_EN : 1;/*!< Reserved */ + __IOM uint32_t REG_USB_OTG20_SYS_CLK_EN : 1;/*!< Reserved */ + __IOM uint32_t REG_UHCI_SYS_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_UART0_SYS_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_UART1_SYS_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_UART2_SYS_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_UART3_SYS_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_UART4_SYS_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_PARLIO_SYS_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_ETM_SYS_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_PVT_SYS_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_CRYPTO_SYS_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_KEY_MANAGER_SYS_CLK_EN : 1;/*!< Reserved */ + __IOM uint32_t REG_BITSRAMBLER_SYS_CLK_EN : 1;/*!< Reserved */ + __IOM uint32_t REG_BITSRAMBLER_RX_SYS_CLK_EN : 1;/*!< Reserved */ + __IOM uint32_t REG_BITSRAMBLER_TX_SYS_CLK_EN : 1;/*!< Reserved */ + __IOM uint32_t REG_H264_SYS_CLK_EN : 1; /*!< Reserved */ + } bit; + } SOC_CLK_CTRL1; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_RMT_SYS_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_HP_CLKRST_APB_CLK_EN : 1;/*!< Reserved */ + __IOM uint32_t REG_SYSREG_APB_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_ICM_APB_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_INTRMTX_APB_CLK_EN : 1;/*!< Reserved */ + __IOM uint32_t REG_ADC_APB_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_UHCI_APB_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_UART0_APB_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_UART1_APB_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_UART2_APB_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_UART3_APB_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_UART4_APB_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_I2C0_APB_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_I2C1_APB_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_I2S0_APB_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_I2S1_APB_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_I2S2_APB_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_I3C_MST_APB_CLK_EN : 1;/*!< Reserved */ + __IOM uint32_t REG_I3C_SLV_APB_CLK_EN : 1;/*!< Reserved */ + __IOM uint32_t REG_GPSPI2_APB_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_GPSPI3_APB_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_TIMERGRP0_APB_CLK_EN : 1;/*!< Reserved */ + __IOM uint32_t REG_TIMERGRP1_APB_CLK_EN : 1;/*!< Reserved */ + __IOM uint32_t REG_SYSTIMER_APB_CLK_EN : 1;/*!< Reserved */ + __IOM uint32_t REG_TWAI0_APB_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_TWAI1_APB_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_TWAI2_APB_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_MCPWM0_APB_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_MCPWM1_APB_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_USB_DEVICE_APB_CLK_EN : 1;/*!< Reserved */ + __IOM uint32_t REG_PCNT_APB_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_PARLIO_APB_CLK_EN : 1; /*!< Reserved */ + } bit; + } SOC_CLK_CTRL2; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_LEDC_APB_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_LCDCAM_APB_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_ETM_APB_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_IOMUX_APB_CLK_EN : 1; /*!< Reserved */ + uint32_t : 28; + } bit; + } SOC_CLK_CTRL3; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_REF_50M_CLK_DIV_NUM : 8;/*!< Reserved */ + __IOM uint32_t REG_REF_25M_CLK_DIV_NUM : 8;/*!< Reserved */ + __IOM uint32_t REG_REF_240M_CLK_DIV_NUM : 8;/*!< Reserved */ + __IOM uint32_t REG_REF_160M_CLK_DIV_NUM : 8;/*!< Reserved */ + } bit; + } REF_CLK_CTRL0; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_REF_120M_CLK_DIV_NUM : 8;/*!< Reserved */ + __IOM uint32_t REG_REF_80M_CLK_DIV_NUM : 8;/*!< Reserved */ + __IOM uint32_t REG_REF_20M_CLK_DIV_NUM : 8;/*!< Reserved */ + __IOM uint32_t REG_TM_400M_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_TM_200M_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_TM_100M_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_REF_50M_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_REF_25M_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_TM_480M_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_REF_240M_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_TM_240M_CLK_EN : 1; /*!< Reserved */ + } bit; + } REF_CLK_CTRL1; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_REF_160M_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_TM_160M_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_REF_120M_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_TM_120M_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_REF_80M_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_TM_80M_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_TM_60M_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_TM_48M_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_REF_20M_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_TM_20M_CLK_EN : 1; /*!< Reserved */ + uint32_t : 22; + } bit; + } REF_CLK_CTRL2; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_FLASH_CLK_SRC_SEL : 2; /*!< Reserved */ + __IOM uint32_t REG_FLASH_PLL_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_FLASH_CORE_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_FLASH_CORE_CLK_DIV_NUM : 8;/*!< Reserved */ + __IOM uint32_t REG_PSRAM_CLK_SRC_SEL : 2; /*!< Reserved */ + __IOM uint32_t REG_PSRAM_PLL_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_PSRAM_CORE_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_PSRAM_CORE_CLK_DIV_NUM : 8;/*!< Reserved */ + __IOM uint32_t REG_PAD_EMAC_REF_CLK_EN : 1;/*!< Reserved */ + __IOM uint32_t REG_EMAC_RMII_CLK_SRC_SEL : 2;/*!< Reserved */ + __IOM uint32_t REG_EMAC_RMII_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_EMAC_RX_CLK_SRC_SEL : 1;/*!< Reserved */ + __IOM uint32_t REG_EMAC_RX_CLK_EN : 1; /*!< Reserved */ + uint32_t : 2; + } bit; + } PERI_CLK_CTRL00; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_EMAC_RX_CLK_DIV_NUM : 8;/*!< Reserved */ + __IOM uint32_t REG_EMAC_TX_CLK_SRC_SEL : 1;/*!< Reserved */ + __IOM uint32_t REG_EMAC_TX_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_EMAC_TX_CLK_DIV_NUM : 8;/*!< Reserved */ + __IOM uint32_t REG_EMAC_PTP_REF_CLK_SRC_SEL : 1;/*!< Reserved */ + __IOM uint32_t REG_EMAC_PTP_REF_CLK_EN : 1;/*!< Reserved */ + __IOM uint32_t REG_EMAC_UNUSED0_CLK_EN : 1;/*!< Reserved */ + __IOM uint32_t REG_EMAC_UNUSED1_CLK_EN : 1;/*!< Reserved */ + __IOM uint32_t REG_SDIO_HS_MODE : 1; /*!< Reserved */ + __IOM uint32_t REG_SDIO_LS_CLK_SRC_SEL : 1;/*!< Reserved */ + __IOM uint32_t REG_SDIO_LS_CLK_EN : 1; /*!< Reserved */ + uint32_t : 7; + } bit; + } PERI_CLK_CTRL01; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_SDIO_LS_CLK_DIV_NUM : 8;/*!< Reserved */ + __OM uint32_t REG_SDIO_LS_CLK_EDGE_CFG_UPDATE : 1;/*!< Reserved */ + __IOM uint32_t REG_SDIO_LS_CLK_EDGE_L : 4;/*!< Reserved */ + __IOM uint32_t REG_SDIO_LS_CLK_EDGE_H : 4;/*!< Reserved */ + __IOM uint32_t REG_SDIO_LS_CLK_EDGE_N : 4;/*!< Reserved */ + __IOM uint32_t REG_SDIO_LS_SLF_CLK_EDGE_SEL : 2;/*!< Reserved */ + __IOM uint32_t REG_SDIO_LS_DRV_CLK_EDGE_SEL : 2;/*!< Reserved */ + __IOM uint32_t REG_SDIO_LS_SAM_CLK_EDGE_SEL : 2;/*!< Reserved */ + __IOM uint32_t REG_SDIO_LS_SLF_CLK_EN : 1;/*!< Reserved */ + __IOM uint32_t REG_SDIO_LS_DRV_CLK_EN : 1;/*!< Reserved */ + __IOM uint32_t REG_SDIO_LS_SAM_CLK_EN : 1;/*!< Reserved */ + __IOM uint32_t REG_MIPI_DSI_DPHY_CLK_SRC_SEL : 2;/*!< Reserved */ + } bit; + } PERI_CLK_CTRL02; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_MIPI_DSI_DPHY_CFG_CLK_EN : 1;/*!< Reserved */ + __IOM uint32_t REG_MIPI_DSI_DPHY_PLL_REFCLK_EN : 1;/*!< Reserved */ + __IOM uint32_t REG_MIPI_CSI_DPHY_CLK_SRC_SEL : 2;/*!< Reserved */ + __IOM uint32_t REG_MIPI_CSI_DPHY_CFG_CLK_EN : 1;/*!< Reserved */ + __IOM uint32_t REG_MIPI_DSI_DPICLK_SRC_SEL : 2;/*!< Reserved */ + __IOM uint32_t REG_MIPI_DSI_DPICLK_EN : 1;/*!< Reserved */ + __IOM uint32_t REG_MIPI_DSI_DPICLK_DIV_NUM : 8;/*!< Reserved */ + uint32_t : 16; + } bit; + } PERI_CLK_CTRL03; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_I2C0_CLK_SRC_SEL : 1; /*!< Reserved */ + __IOM uint32_t REG_I2C0_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_I2C0_CLK_DIV_NUM : 8; /*!< Reserved */ + __IOM uint32_t REG_I2C0_CLK_DIV_NUMERATOR : 8;/*!< Reserved */ + __IOM uint32_t REG_I2C0_CLK_DIV_DENOMINATOR : 8;/*!< Reserved */ + __IOM uint32_t REG_I2C1_CLK_SRC_SEL : 1; /*!< Reserved */ + __IOM uint32_t REG_I2C1_CLK_EN : 1; /*!< Reserved */ + uint32_t : 4; + } bit; + } PERI_CLK_CTRL10; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_I2C1_CLK_DIV_NUM : 8; /*!< Reserved */ + __IOM uint32_t REG_I2C1_CLK_DIV_NUMERATOR : 8;/*!< Reserved */ + __IOM uint32_t REG_I2C1_CLK_DIV_DENOMINATOR : 8;/*!< Reserved */ + __IOM uint32_t REG_I2S0_RX_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_I2S0_RX_CLK_SRC_SEL : 2;/*!< Reserved */ + uint32_t : 5; + } bit; + } PERI_CLK_CTRL11; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_I2S0_RX_DIV_N : 8; /*!< Reserved */ + __IOM uint32_t REG_I2S0_RX_DIV_X : 9; /*!< Reserved */ + __IOM uint32_t REG_I2S0_RX_DIV_Y : 9; /*!< Reserved */ + uint32_t : 6; + } bit; + } PERI_CLK_CTRL12; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_I2S0_RX_DIV_Z : 9; /*!< Reserved */ + __IOM uint32_t REG_I2S0_RX_DIV_YN1 : 1; /*!< Reserved */ + __IOM uint32_t REG_I2S0_TX_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_I2S0_TX_CLK_SRC_SEL : 2;/*!< Reserved */ + __IOM uint32_t REG_I2S0_TX_DIV_N : 8; /*!< Reserved */ + __IOM uint32_t REG_I2S0_TX_DIV_X : 9; /*!< Reserved */ + uint32_t : 2; + } bit; + } PERI_CLK_CTRL13; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_I2S0_TX_DIV_Y : 9; /*!< Reserved */ + __IOM uint32_t REG_I2S0_TX_DIV_Z : 9; /*!< Reserved */ + __IOM uint32_t REG_I2S0_TX_DIV_YN1 : 1; /*!< Reserved */ + __IOM uint32_t REG_I2S0_MST_CLK_SEL : 1; /*!< Reserved */ + __IOM uint32_t REG_I2S1_RX_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_I2S1_RX_CLK_SRC_SEL : 2;/*!< Reserved */ + __IOM uint32_t REG_I2S1_RX_DIV_N : 8; /*!< Reserved */ + uint32_t : 1; + } bit; + } PERI_CLK_CTRL14; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_I2S1_RX_DIV_X : 9; /*!< Reserved */ + __IOM uint32_t REG_I2S1_RX_DIV_Y : 9; /*!< Reserved */ + __IOM uint32_t REG_I2S1_RX_DIV_Z : 9; /*!< Reserved */ + __IOM uint32_t REG_I2S1_RX_DIV_YN1 : 1; /*!< Reserved */ + __IOM uint32_t REG_I2S1_TX_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_I2S1_TX_CLK_SRC_SEL : 2;/*!< Reserved */ + uint32_t : 1; + } bit; + } PERI_CLK_CTRL15; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_I2S1_TX_DIV_N : 8; /*!< Reserved */ + __IOM uint32_t REG_I2S1_TX_DIV_X : 9; /*!< Reserved */ + __IOM uint32_t REG_I2S1_TX_DIV_Y : 9; /*!< Reserved */ + uint32_t : 6; + } bit; + } PERI_CLK_CTRL16; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_I2S1_TX_DIV_Z : 9; /*!< Reserved */ + __IOM uint32_t REG_I2S1_TX_DIV_YN1 : 1; /*!< Reserved */ + __IOM uint32_t REG_I2S1_MST_CLK_SEL : 1; /*!< Reserved */ + __IOM uint32_t REG_I2S2_RX_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_I2S2_RX_CLK_SRC_SEL : 2;/*!< Reserved */ + __IOM uint32_t REG_I2S2_RX_DIV_N : 8; /*!< Reserved */ + __IOM uint32_t REG_I2S2_RX_DIV_X : 9; /*!< Reserved */ + uint32_t : 1; + } bit; + } PERI_CLK_CTRL17; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_I2S2_RX_DIV_Y : 9; /*!< Reserved */ + __IOM uint32_t REG_I2S2_RX_DIV_Z : 9; /*!< Reserved */ + __IOM uint32_t REG_I2S2_RX_DIV_YN1 : 1; /*!< Reserved */ + __IOM uint32_t REG_I2S2_TX_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_I2S2_TX_CLK_SRC_SEL : 2;/*!< Reserved */ + __IOM uint32_t REG_I2S2_TX_DIV_N : 8; /*!< Reserved */ + uint32_t : 2; + } bit; + } PERI_CLK_CTRL18; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_I2S2_TX_DIV_X : 9; /*!< Reserved */ + __IOM uint32_t REG_I2S2_TX_DIV_Y : 9; /*!< Reserved */ + __IOM uint32_t REG_I2S2_TX_DIV_Z : 9; /*!< Reserved */ + __IOM uint32_t REG_I2S2_TX_DIV_YN1 : 1; /*!< Reserved */ + __IOM uint32_t REG_I2S2_MST_CLK_SEL : 1; /*!< Reserved */ + __IOM uint32_t REG_LCD_CLK_SRC_SEL : 2; /*!< Reserved */ + __IOM uint32_t REG_LCD_CLK_EN : 1; /*!< Reserved */ + } bit; + } PERI_CLK_CTRL19; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_LCD_CLK_DIV_NUM : 8; /*!< Reserved */ + __IOM uint32_t REG_LCD_CLK_DIV_NUMERATOR : 8;/*!< Reserved */ + __IOM uint32_t REG_LCD_CLK_DIV_DENOMINATOR : 8;/*!< Reserved */ + __IOM uint32_t REG_UART0_CLK_SRC_SEL : 2; /*!< Reserved */ + __IOM uint32_t REG_UART0_CLK_EN : 1; /*!< Reserved */ + uint32_t : 5; + } bit; + } PERI_CLK_CTRL110; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_UART0_SCLK_DIV_NUM : 8;/*!< Reserved */ + __IOM uint32_t REG_UART0_SCLK_DIV_NUMERATOR : 8;/*!< Reserved */ + __IOM uint32_t REG_UART0_SCLK_DIV_DENOMINATOR : 8;/*!< Reserved */ + __IOM uint32_t REG_UART1_CLK_SRC_SEL : 2; /*!< Reserved */ + __IOM uint32_t REG_UART1_CLK_EN : 1; /*!< Reserved */ + uint32_t : 5; + } bit; + } PERI_CLK_CTRL111; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_UART1_SCLK_DIV_NUM : 8;/*!< Reserved */ + __IOM uint32_t REG_UART1_SCLK_DIV_NUMERATOR : 8;/*!< Reserved */ + __IOM uint32_t REG_UART1_SCLK_DIV_DENOMINATOR : 8;/*!< Reserved */ + __IOM uint32_t REG_UART2_CLK_SRC_SEL : 2; /*!< Reserved */ + __IOM uint32_t REG_UART2_CLK_EN : 1; /*!< Reserved */ + uint32_t : 5; + } bit; + } PERI_CLK_CTRL112; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_UART2_SCLK_DIV_NUM : 8;/*!< Reserved */ + __IOM uint32_t REG_UART2_SCLK_DIV_NUMERATOR : 8;/*!< Reserved */ + __IOM uint32_t REG_UART2_SCLK_DIV_DENOMINATOR : 8;/*!< Reserved */ + __IOM uint32_t REG_UART3_CLK_SRC_SEL : 2; /*!< Reserved */ + __IOM uint32_t REG_UART3_CLK_EN : 1; /*!< Reserved */ + uint32_t : 5; + } bit; + } PERI_CLK_CTRL113; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_UART3_SCLK_DIV_NUM : 8;/*!< Reserved */ + __IOM uint32_t REG_UART3_SCLK_DIV_NUMERATOR : 8;/*!< Reserved */ + __IOM uint32_t REG_UART3_SCLK_DIV_DENOMINATOR : 8;/*!< Reserved */ + __IOM uint32_t REG_UART4_CLK_SRC_SEL : 2; /*!< Reserved */ + __IOM uint32_t REG_UART4_CLK_EN : 1; /*!< Reserved */ + uint32_t : 5; + } bit; + } PERI_CLK_CTRL114; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_UART4_SCLK_DIV_NUM : 8;/*!< Reserved */ + __IOM uint32_t REG_UART4_SCLK_DIV_NUMERATOR : 8;/*!< Reserved */ + __IOM uint32_t REG_UART4_SCLK_DIV_DENOMINATOR : 8;/*!< Reserved */ + __IOM uint32_t REG_TWAI0_CLK_SRC_SEL : 1; /*!< Reserved */ + __IOM uint32_t REG_TWAI0_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_TWAI1_CLK_SRC_SEL : 1; /*!< Reserved */ + __IOM uint32_t REG_TWAI1_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_TWAI2_CLK_SRC_SEL : 1; /*!< Reserved */ + __IOM uint32_t REG_TWAI2_CLK_EN : 1; /*!< Reserved */ + uint32_t : 2; + } bit; + } PERI_CLK_CTRL115; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_GPSPI2_CLK_SRC_SEL : 3;/*!< Reserved */ + __IOM uint32_t REG_GPSPI2_HS_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_GPSPI2_HS_CLK_DIV_NUM : 8;/*!< Reserved */ + __IOM uint32_t REG_GPSPI2_MST_CLK_DIV_NUM : 8;/*!< Reserved */ + __IOM uint32_t REG_GPSPI2_MST_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_GPSPI3_CLK_SRC_SEL : 3;/*!< Reserved */ + __IOM uint32_t REG_GPSPI3_HS_CLK_EN : 1; /*!< Reserved */ + uint32_t : 7; + } bit; + } PERI_CLK_CTRL116; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_GPSPI3_HS_CLK_DIV_NUM : 8;/*!< Reserved */ + __IOM uint32_t REG_GPSPI3_MST_CLK_DIV_NUM : 8;/*!< Reserved */ + __IOM uint32_t REG_GPSPI3_MST_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_PARLIO_RX_CLK_SRC_SEL : 2;/*!< Reserved */ + __IOM uint32_t REG_PARLIO_RX_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_PARLIO_RX_CLK_DIV_NUM : 8;/*!< Reserved */ + uint32_t : 4; + } bit; + } PERI_CLK_CTRL117; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_PARLIO_RX_CLK_DIV_NUMERATOR : 8;/*!< Reserved */ + __IOM uint32_t REG_PARLIO_RX_CLK_DIV_DENOMINATOR : 8;/*!< Reserved */ + __IOM uint32_t REG_PARLIO_TX_CLK_SRC_SEL : 2;/*!< Reserved */ + __IOM uint32_t REG_PARLIO_TX_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_PARLIO_TX_CLK_DIV_NUM : 8;/*!< Reserved */ + uint32_t : 5; + } bit; + } PERI_CLK_CTRL118; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_PARLIO_TX_CLK_DIV_NUMERATOR : 8;/*!< Reserved */ + __IOM uint32_t REG_PARLIO_TX_CLK_DIV_DENOMINATOR : 8;/*!< Reserved */ + __IOM uint32_t REG_I3C_MST_CLK_SRC_SEL : 2;/*!< Reserved */ + __IOM uint32_t REG_I3C_MST_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_I3C_MST_CLK_DIV_NUM : 8;/*!< Reserved */ + __IOM uint32_t REG_CAM_CLK_SRC_SEL : 2; /*!< Reserved */ + __IOM uint32_t REG_CAM_CLK_EN : 1; /*!< Reserved */ + uint32_t : 2; + } bit; + } PERI_CLK_CTRL119; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_CAM_CLK_DIV_NUM : 8; /*!< Reserved */ + __IOM uint32_t REG_CAM_CLK_DIV_NUMERATOR : 8;/*!< Reserved */ + __IOM uint32_t REG_CAM_CLK_DIV_DENOMINATOR : 8;/*!< Reserved */ + uint32_t : 8; + } bit; + } PERI_CLK_CTRL120; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_MCPWM0_CLK_SRC_SEL : 2;/*!< Reserved */ + __IOM uint32_t REG_MCPWM0_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_MCPWM0_CLK_DIV_NUM : 8;/*!< Reserved */ + __IOM uint32_t REG_MCPWM1_CLK_SRC_SEL : 2;/*!< Reserved */ + __IOM uint32_t REG_MCPWM1_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_MCPWM1_CLK_DIV_NUM : 8;/*!< Reserved */ + __IOM uint32_t REG_TIMERGRP0_T0_SRC_SEL : 2;/*!< Reserved */ + __IOM uint32_t REG_TIMERGRP0_T0_CLK_EN : 1;/*!< Reserved */ + __IOM uint32_t REG_TIMERGRP0_T1_SRC_SEL : 2;/*!< Reserved */ + __IOM uint32_t REG_TIMERGRP0_T1_CLK_EN : 1;/*!< Reserved */ + __IOM uint32_t REG_TIMERGRP0_WDT_SRC_SEL : 2;/*!< Reserved */ + __IOM uint32_t REG_TIMERGRP0_WDT_CLK_EN : 1;/*!< Reserved */ + __IOM uint32_t REG_TIMERGRP0_TGRT_CLK_EN : 1;/*!< Reserved */ + } bit; + } PERI_CLK_CTRL20; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_TIMERGRP0_TGRT_CLK_SRC_SEL : 4;/*!< Reserved */ + __IOM uint32_t REG_TIMERGRP0_TGRT_CLK_DIV_NUM : 16;/*!< Reserved */ + __IOM uint32_t REG_TIMERGRP1_T0_SRC_SEL : 2;/*!< Reserved */ + __IOM uint32_t REG_TIMERGRP1_T0_CLK_EN : 1;/*!< Reserved */ + __IOM uint32_t REG_TIMERGRP1_T1_SRC_SEL : 2;/*!< Reserved */ + __IOM uint32_t REG_TIMERGRP1_T1_CLK_EN : 1;/*!< Reserved */ + __IOM uint32_t REG_TIMERGRP1_WDT_SRC_SEL : 2;/*!< Reserved */ + __IOM uint32_t REG_TIMERGRP1_WDT_CLK_EN : 1;/*!< Reserved */ + __IOM uint32_t REG_SYSTIMER_CLK_SRC_SEL : 1;/*!< Reserved */ + __IOM uint32_t REG_SYSTIMER_CLK_EN : 1; /*!< Reserved */ + uint32_t : 1; + } bit; + } PERI_CLK_CTRL21; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_LEDC_CLK_SRC_SEL : 2; /*!< Reserved */ + __IOM uint32_t REG_LEDC_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_RMT_CLK_SRC_SEL : 2; /*!< Reserved */ + __IOM uint32_t REG_RMT_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_RMT_CLK_DIV_NUM : 8; /*!< Reserved */ + __IOM uint32_t REG_RMT_CLK_DIV_NUMERATOR : 8;/*!< Reserved */ + __IOM uint32_t REG_RMT_CLK_DIV_DENOMINATOR : 8;/*!< Reserved */ + __IOM uint32_t REG_ADC_CLK_SRC_SEL : 2; /*!< Reserved */ + } bit; + } PERI_CLK_CTRL22; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_ADC_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_ADC_CLK_DIV_NUM : 8; /*!< Reserved */ + __IOM uint32_t REG_ADC_CLK_DIV_NUMERATOR : 8;/*!< Reserved */ + __IOM uint32_t REG_ADC_CLK_DIV_DENOMINATOR : 8;/*!< Reserved */ + uint32_t : 7; + } bit; + } PERI_CLK_CTRL23; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_ADC_SAR1_CLK_DIV_NUM : 8;/*!< Reserved */ + __IOM uint32_t REG_ADC_SAR2_CLK_DIV_NUM : 8;/*!< Reserved */ + __IOM uint32_t REG_PVT_CLK_DIV_NUM : 8; /*!< Reserved */ + __IOM uint32_t REG_PVT_CLK_EN : 1; /*!< Reserved */ + uint32_t : 7; + } bit; + } PERI_CLK_CTRL24; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_PVT_PERI_GROUP_CLK_DIV_NUM : 8;/*!< Reserved */ + __IOM uint32_t REG_PVT_PERI_GROUP1_CLK_EN : 1;/*!< Reserved */ + __IOM uint32_t REG_PVT_PERI_GROUP2_CLK_EN : 1;/*!< Reserved */ + __IOM uint32_t REG_PVT_PERI_GROUP3_CLK_EN : 1;/*!< Reserved */ + __IOM uint32_t REG_PVT_PERI_GROUP4_CLK_EN : 1;/*!< Reserved */ + __IOM uint32_t REG_CRYPTO_CLK_SRC_SEL : 2;/*!< Reserved */ + __IOM uint32_t REG_CRYPTO_AES_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_CRYPTO_DS_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_CRYPTO_ECC_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_CRYPTO_HMAC_CLK_EN : 1;/*!< Reserved */ + __IOM uint32_t REG_CRYPTO_RSA_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_CRYPTO_SEC_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_CRYPTO_SHA_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_CRYPTO_ECDSA_CLK_EN : 1;/*!< Reserved */ + __IOM uint32_t REG_CRYPTO_KM_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_ISP_CLK_SRC_SEL : 2; /*!< Reserved */ + __IOM uint32_t REG_ISP_CLK_EN : 1; /*!< Reserved */ + uint32_t : 6; + } bit; + } PERI_CLK_CTRL25; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_ISP_CLK_DIV_NUM : 8; /*!< Reserved */ + __IOM uint32_t REG_IOMUX_CLK_SRC_SEL : 1; /*!< Reserved */ + __IOM uint32_t REG_IOMUX_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_IOMUX_CLK_DIV_NUM : 8; /*!< Reserved */ + __IOM uint32_t REG_H264_CLK_SRC_SEL : 1; /*!< Reserved */ + __IOM uint32_t REG_H264_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_H264_CLK_DIV_NUM : 8; /*!< Reserved */ + __IOM uint32_t REG_PADBIST_RX_CLK_SRC_SEL : 1;/*!< Reserved */ + __IOM uint32_t REG_PADBIST_RX_CLK_EN : 1; /*!< Reserved */ + uint32_t : 2; + } bit; + } PERI_CLK_CTRL26; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_PADBIST_RX_CLK_DIV_NUM : 8;/*!< Reserved */ + __IOM uint32_t REG_PADBIST_TX_CLK_SRC_SEL : 1;/*!< Reserved */ + __IOM uint32_t REG_PADBIST_TX_CLK_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_PADBIST_TX_CLK_DIV_NUM : 8;/*!< Reserved */ + uint32_t : 14; + } bit; + } PERI_CLK_CTRL27; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_CPUICM_GATED_CLK_FORCE_ON : 1;/*!< Reserved */ + __IOM uint32_t REG_TCM_CPU_CLK_FORCE_ON : 1;/*!< Reserved */ + __IOM uint32_t REG_BUSMON_CPU_CLK_FORCE_ON : 1;/*!< Reserved */ + __IOM uint32_t REG_L1CACHE_CPU_CLK_FORCE_ON : 1;/*!< Reserved */ + __IOM uint32_t REG_L1CACHE_D_CPU_CLK_FORCE_ON : 1;/*!< Reserved */ + __IOM uint32_t REG_L1CACHE_I0_CPU_CLK_FORCE_ON : 1;/*!< Reserved */ + __IOM uint32_t REG_L1CACHE_I1_CPU_CLK_FORCE_ON : 1;/*!< Reserved */ + __IOM uint32_t REG_TRACE_CPU_CLK_FORCE_ON : 1;/*!< Reserved */ + __IOM uint32_t REG_TRACE_SYS_CLK_FORCE_ON : 1;/*!< Reserved */ + __IOM uint32_t REG_L1CACHE_MEM_CLK_FORCE_ON : 1;/*!< Reserved */ + __IOM uint32_t REG_L1CACHE_D_MEM_CLK_FORCE_ON : 1;/*!< Reserved */ + __IOM uint32_t REG_L1CACHE_I0_MEM_CLK_FORCE_ON : 1;/*!< Reserved */ + __IOM uint32_t REG_L1CACHE_I1_MEM_CLK_FORCE_ON : 1;/*!< Reserved */ + __IOM uint32_t REG_L2CACHE_MEM_CLK_FORCE_ON : 1;/*!< Reserved */ + __IOM uint32_t REG_L2MEM_MEM_CLK_FORCE_ON : 1;/*!< Reserved */ + __IOM uint32_t REG_SAR1_CLK_FORCE_ON : 1; /*!< Reserved */ + __IOM uint32_t REG_SAR2_CLK_FORCE_ON : 1; /*!< Reserved */ + __IOM uint32_t REG_GMAC_TX_CLK_FORCE_ON : 1;/*!< Reserved */ + uint32_t : 14; + } bit; + } CLK_FORCE_ON_CTRL0; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_SEC_DPA_LEVEL : 2; /*!< Reserved */ + __IOM uint32_t REG_SEC_DPA_CFG_SEL : 1; /*!< Reserved */ + uint32_t : 29; + } bit; + } DPA_CTRL0; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IM uint32_t REG_PLLA_CAL_END : 1; /*!< Reserved */ + __IOM uint32_t REG_PLLA_CAL_STOP : 1; /*!< Reserved */ + __IM uint32_t REG_CPU_PLL_CAL_END : 1; /*!< Reserved */ + __IOM uint32_t REG_CPU_PLL_CAL_STOP : 1; /*!< Reserved */ + __IM uint32_t REG_SDIO_PLL_CAL_END : 1; /*!< Reserved */ + __IOM uint32_t REG_SDIO_PLL_CAL_STOP : 1; /*!< Reserved */ + __IM uint32_t REG_SYS_PLL_CAL_END : 1; /*!< Reserved */ + __IOM uint32_t REG_SYS_PLL_CAL_STOP : 1; /*!< Reserved */ + __IM uint32_t REG_MSPI_CAL_END : 1; /*!< Reserved */ + __IOM uint32_t REG_MSPI_CAL_STOP : 1; /*!< Reserved */ + uint32_t : 22; + } bit; + } ANA_PLL_CTRL0; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_RST_EN_CORECTRL : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_PVT_TOP : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_PVT_PERI_GROUP1 : 1;/*!< Reserved */ + __IOM uint32_t REG_RST_EN_PVT_PERI_GROUP2 : 1;/*!< Reserved */ + __IOM uint32_t REG_RST_EN_PVT_PERI_GROUP3 : 1;/*!< Reserved */ + __IOM uint32_t REG_RST_EN_PVT_PERI_GROUP4 : 1;/*!< Reserved */ + __IOM uint32_t REG_RST_EN_REGDMA : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_CORE0_GLOBAL : 1;/*!< Reserved */ + __IOM uint32_t REG_RST_EN_CORE1_GLOBAL : 1;/*!< Reserved */ + __IOM uint32_t REG_RST_EN_CORETRACE0 : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_CORETRACE1 : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_HP_TCM : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_HP_CACHE : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_L1_I0_CACHE : 1;/*!< Reserved */ + __IOM uint32_t REG_RST_EN_L1_I1_CACHE : 1;/*!< Reserved */ + __IOM uint32_t REG_RST_EN_L1_D_CACHE : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_L2_CACHE : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_L2_MEM : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_L2MEMMON : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_TCMMON : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_PVT_APB : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_GDMA : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_MSPI_AXI : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_DUAL_MSPI_AXI : 1;/*!< Reserved */ + __IOM uint32_t REG_RST_EN_MSPI_APB : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_DUAL_MSPI_APB : 1;/*!< Reserved */ + __IOM uint32_t REG_RST_EN_DSI_BRG : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_CSI_HOST : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_CSI_BRG : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_ISP : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_JPEG : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_DMA2D : 1; /*!< Reserved */ + } bit; + } HP_RST_EN0; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_RST_EN_PPA : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_AHB_PDMA : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_AXI_PDMA : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_IOMUX : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_PADBIST : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_STIMER : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_TIMERGRP0 : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_TIMERGRP1 : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_UART0_CORE : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_UART1_CORE : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_UART2_CORE : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_UART3_CORE : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_UART4_CORE : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_UART0_APB : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_UART1_APB : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_UART2_APB : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_UART3_APB : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_UART4_APB : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_UHCI : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_I3CMST : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_I3CSLV : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_I2C1 : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_I2C0 : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_RMT : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_PWM0 : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_PWM1 : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_CAN0 : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_CAN1 : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_CAN2 : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_LEDC : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_PCNT : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_ETM : 1; /*!< Reserved */ + } bit; + } HP_RST_EN1; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_RST_EN_INTRMTX : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_PARLIO : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_PARLIO_RX : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_PARLIO_TX : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_I2S0_APB : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_I2S1_APB : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_I2S2_APB : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_SPI2 : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_SPI3 : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_LCDCAM : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_ADC : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_BITSRAMBLER : 1;/*!< Reserved */ + __IOM uint32_t REG_RST_EN_BITSRAMBLER_RX : 1;/*!< Reserved */ + __IOM uint32_t REG_RST_EN_BITSRAMBLER_TX : 1;/*!< Reserved */ + __IOM uint32_t REG_RST_EN_CRYPTO : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_SEC : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_AES : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_DS : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_SHA : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_HMAC : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_ECDSA : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_RSA : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_ECC : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_KM : 1; /*!< Reserved */ + __IOM uint32_t REG_RST_EN_H264 : 1; /*!< Reserved */ + uint32_t : 7; + } bit; + } HP_RST_EN2; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_FORCE_NORST_CORE0 : 1; /*!< Reserved */ + __IOM uint32_t REG_FORCE_NORST_CORE1 : 1; /*!< Reserved */ + __IOM uint32_t REG_FORCE_NORST_CORETRACE0 : 1;/*!< Reserved */ + __IOM uint32_t REG_FORCE_NORST_CORETRACE1 : 1;/*!< Reserved */ + __IOM uint32_t REG_FORCE_NORST_L2MEMMON : 1;/*!< Reserved */ + __IOM uint32_t REG_FORCE_NORST_TCMMON : 1;/*!< Reserved */ + __IOM uint32_t REG_FORCE_NORST_GDMA : 1; /*!< Reserved */ + __IOM uint32_t REG_FORCE_NORST_MSPI_AXI : 1;/*!< Reserved */ + __IOM uint32_t REG_FORCE_NORST_DUAL_MSPI_AXI : 1;/*!< Reserved */ + __IOM uint32_t REG_FORCE_NORST_MSPI_APB : 1;/*!< Reserved */ + __IOM uint32_t REG_FORCE_NORST_DUAL_MSPI_APB : 1;/*!< Reserved */ + __IOM uint32_t REG_FORCE_NORST_DSI_BRG : 1;/*!< Reserved */ + __IOM uint32_t REG_FORCE_NORST_CSI_HOST : 1;/*!< Reserved */ + __IOM uint32_t REG_FORCE_NORST_CSI_BRG : 1;/*!< Reserved */ + __IOM uint32_t REG_FORCE_NORST_ISP : 1; /*!< Reserved */ + __IOM uint32_t REG_FORCE_NORST_JPEG : 1; /*!< Reserved */ + __IOM uint32_t REG_FORCE_NORST_DMA2D : 1; /*!< Reserved */ + __IOM uint32_t REG_FORCE_NORST_PPA : 1; /*!< Reserved */ + __IOM uint32_t REG_FORCE_NORST_AHB_PDMA : 1;/*!< Reserved */ + __IOM uint32_t REG_FORCE_NORST_AXI_PDMA : 1;/*!< Reserved */ + __IOM uint32_t REG_FORCE_NORST_IOMUX : 1; /*!< Reserved */ + __IOM uint32_t REG_FORCE_NORST_PADBIST : 1;/*!< Reserved */ + __IOM uint32_t REG_FORCE_NORST_STIMER : 1;/*!< Reserved */ + __IOM uint32_t REG_FORCE_NORST_TIMERGRP0 : 1;/*!< Reserved */ + __IOM uint32_t REG_FORCE_NORST_TIMERGRP1 : 1;/*!< Reserved */ + __IOM uint32_t REG_FORCE_NORST_UART0 : 1; /*!< Reserved */ + __IOM uint32_t REG_FORCE_NORST_UART1 : 1; /*!< Reserved */ + __IOM uint32_t REG_FORCE_NORST_UART2 : 1; /*!< Reserved */ + __IOM uint32_t REG_FORCE_NORST_UART3 : 1; /*!< Reserved */ + __IOM uint32_t REG_FORCE_NORST_UART4 : 1; /*!< Reserved */ + __IOM uint32_t REG_FORCE_NORST_UHCI : 1; /*!< Reserved */ + __IOM uint32_t REG_FORCE_NORST_I3CMST : 1;/*!< Reserved */ + } bit; + } HP_FORCE_NORST0; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_FORCE_NORST_I3CSLV : 1;/*!< Reserved */ + __IOM uint32_t REG_FORCE_NORST_I2C1 : 1; /*!< Reserved */ + __IOM uint32_t REG_FORCE_NORST_I2C0 : 1; /*!< Reserved */ + __IOM uint32_t REG_FORCE_NORST_RMT : 1; /*!< Reserved */ + __IOM uint32_t REG_FORCE_NORST_PWM0 : 1; /*!< Reserved */ + __IOM uint32_t REG_FORCE_NORST_PWM1 : 1; /*!< Reserved */ + __IOM uint32_t REG_FORCE_NORST_CAN0 : 1; /*!< Reserved */ + __IOM uint32_t REG_FORCE_NORST_CAN1 : 1; /*!< Reserved */ + __IOM uint32_t REG_FORCE_NORST_CAN2 : 1; /*!< Reserved */ + __IOM uint32_t REG_FORCE_NORST_LEDC : 1; /*!< Reserved */ + __IOM uint32_t REG_FORCE_NORST_PCNT : 1; /*!< Reserved */ + __IOM uint32_t REG_FORCE_NORST_ETM : 1; /*!< Reserved */ + __IOM uint32_t REG_FORCE_NORST_INTRMTX : 1;/*!< Reserved */ + __IOM uint32_t REG_FORCE_NORST_PARLIO : 1;/*!< Reserved */ + __IOM uint32_t REG_FORCE_NORST_PARLIO_RX : 1;/*!< Reserved */ + __IOM uint32_t REG_FORCE_NORST_PARLIO_TX : 1;/*!< Reserved */ + __IOM uint32_t REG_FORCE_NORST_I2S0 : 1; /*!< Reserved */ + __IOM uint32_t REG_FORCE_NORST_I2S1 : 1; /*!< Reserved */ + __IOM uint32_t REG_FORCE_NORST_I2S2 : 1; /*!< Reserved */ + __IOM uint32_t REG_FORCE_NORST_SPI2 : 1; /*!< Reserved */ + __IOM uint32_t REG_FORCE_NORST_SPI3 : 1; /*!< Reserved */ + __IOM uint32_t REG_FORCE_NORST_LCDCAM : 1;/*!< Reserved */ + __IOM uint32_t REG_FORCE_NORST_ADC : 1; /*!< Reserved */ + __IOM uint32_t REG_FORCE_NORST_BITSRAMBLER : 1;/*!< Reserved */ + __IOM uint32_t REG_FORCE_NORST_BITSRAMBLER_RX : 1;/*!< Reserved */ + __IOM uint32_t REG_FORCE_NORST_BITSRAMBLER_TX : 1;/*!< Reserved */ + __IOM uint32_t REG_FORCE_NORST_H264 : 1; /*!< Reserved */ + uint32_t : 5; + } bit; + } HP_FORCE_NORST1; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_HPCORE0_STALL_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_HPCORE0_STALL_WAIT_NUM : 8;/*!< Reserved */ + __IOM uint32_t REG_WDT_HPCORE0_RST_LEN : 8;/*!< Reserved */ + uint32_t : 15; + } bit; + } HPWDT_CORE0_RST_CTRL0; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_HPCORE1_STALL_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_HPCORE1_STALL_WAIT_NUM : 8;/*!< Reserved */ + __IOM uint32_t REG_WDT_HPCORE1_RST_LEN : 8;/*!< Reserved */ + uint32_t : 15; + } bit; + } HPWDT_CORE1_RST_CTRL0; + + union { + __IOM uint32_t reg; /*!< CPU Source Frequency */ + + struct { + __IM uint32_t REG_CPU_SRC_FREQ : 32; /*!< cpu source clock frequency, step by 0.25MHz */ + } bit; + } CPU_SRC_FREQ0; + + union { + __IOM uint32_t reg; /*!< CPU Clock Status */ + + struct { + __IM uint32_t REG_ASIC_OR_FPGA : 1; /*!< 0: ASIC mode, 1: FPGA mode */ + __IM uint32_t REG_CPU_DIV_EFFECT : 1; /*!< 0: Divider bypass, 1: Divider takes effect */ + __IM uint32_t REG_CPU_SRC_IS_CPLL : 1; /*!< 0: CPU source isn't cpll_400m, 1: CPU Source is cll_400m */ + __IM uint32_t REG_CPU_DIV_NUM_CUR : 8; /*!< cpu current div number */ + __IM uint32_t REG_CPU_DIV_NUMERATOR_CUR : 8;/*!< cpu current div numerator */ + __IM uint32_t REG_CPU_DIV_DENOMINATOR_CUR : 8;/*!< cpu current div denominator */ + uint32_t : 5; + } bit; + } CPU_CLK_STATUS0; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_DBG_CH0_SEL : 8; /*!< Reserved */ + __IOM uint32_t REG_DBG_CH1_SEL : 8; /*!< Reserved */ + __IOM uint32_t REG_DBG_CH2_SEL : 8; /*!< Reserved */ + __IOM uint32_t REG_DBG_CH0_DIV_NUM : 8; /*!< Reserved */ + } bit; + } DBG_CLK_CTRL0; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_DBG_CH1_DIV_NUM : 8; /*!< Reserved */ + __IOM uint32_t REG_DBG_CH2_DIV_NUM : 8; /*!< Reserved */ + __IOM uint32_t REG_DBG_CH0_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_DBG_CH1_EN : 1; /*!< Reserved */ + __IOM uint32_t REG_DBG_CH2_EN : 1; /*!< Reserved */ + uint32_t : 13; + } bit; + } DBG_CLK_CTRL1; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_HPCORE0_WDT_RESET_SOURCE_SEL : 1;/*!< 1'b0: use wdt0 to reset hpcore0, 1'b1: use wdt1 to reset hpcore0 */ + __IOM uint32_t REG_HPCORE1_WDT_RESET_SOURCE_SEL : 1;/*!< 1'b0: use wdt0 to reset hpcore1, 1'b1: use wdt1 to reset hpcore1 */ + uint32_t : 30; + } bit; + } HPCORE_WDT_RESET_SOURCE0; +} HP_SYS_CLKRST_Type; /*!< Size = 240 (0xf0) */ + + + +/* =========================================================================================================================== */ +/* ================ LP_HUK ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief LP_HUK Peripheral (LP_HUK) + */ + +typedef struct { /*!< LP_HUK Structure */ + __IM uint32_t RESERVED; + + union { + __IOM uint32_t reg; /*!< HUK Generator clock gate control register */ + + struct { + __IOM uint32_t EN : 1; /*!< Write 1 to force on register clock gate. */ + __IOM uint32_t MEM_CG_FORCE_ON : 1; /*!< Write 1 to force on memory clock gate. */ + uint32_t : 30; + } bit; + } CLK; + + union { + __IOM uint32_t reg; /*!< HUK Generator interrupt raw register, valid in level. */ + + struct { + __IM uint32_t PREP_DONE_INT_RAW : 1; /*!< The raw interrupt status bit for the huk_prep_done_int interrupt */ + __IM uint32_t PROC_DONE_INT_RAW : 1; /*!< The raw interrupt status bit for the huk_proc_done_int interrupt */ + __IM uint32_t POST_DONE_INT_RAW : 1; /*!< The raw interrupt status bit for the huk_post_done_int interrupt */ + uint32_t : 29; + } bit; + } INT_RAW; + + union { + __IOM uint32_t reg; /*!< HUK Generator interrupt status register. */ + + struct { + __IM uint32_t PREP_DONE_INT_ST : 1; /*!< The masked interrupt status bit for the huk_prep_done_int interrupt */ + __IM uint32_t PROC_DONE_INT_ST : 1; /*!< The masked interrupt status bit for the huk_proc_done_int interrupt */ + __IM uint32_t POST_DONE_INT_ST : 1; /*!< The masked interrupt status bit for the huk_post_done_int interrupt */ + uint32_t : 29; + } bit; + } INT_ST; + + union { + __IOM uint32_t reg; /*!< HUK Generator interrupt enable register. */ + + struct { + __IOM uint32_t PREP_DONE_INT_ENA : 1; /*!< The interrupt enable bit for the huk_prep_done_int interrupt */ + __IOM uint32_t PROC_DONE_INT_ENA : 1; /*!< The interrupt enable bit for the huk_proc_done_int interrupt */ + __IOM uint32_t POST_DONE_INT_ENA : 1; /*!< The interrupt enable bit for the huk_post_done_int interrupt */ + uint32_t : 29; + } bit; + } INT_ENA; + + union { + __IOM uint32_t reg; /*!< HUK Generator interrupt clear register. */ + + struct { + __OM uint32_t PREP_DONE_INT_CLR : 1; /*!< Set this bit to clear the huk_prep_done_int interrupt */ + __OM uint32_t PROC_DONE_INT_CLR : 1; /*!< Set this bit to clear the huk_proc_done_int interrupt */ + __OM uint32_t POST_DONE_INT_CLR : 1; /*!< Set this bit to clear the huk_post_done_int interrupt */ + uint32_t : 29; + } bit; + } INT_CLR; + __IM uint32_t RESERVED1[2]; + + union { + __IOM uint32_t reg; /*!< HUK Generator configuration register */ + + struct { + __IOM uint32_t MODE : 1; /*!< Set this field to choose the huk process. 1: process huk generate + mode. 0: process huk recovery mode. */ + uint32_t : 31; + } bit; + } CONF; + + union { + __IOM uint32_t reg; /*!< HUK Generator control register */ + + struct { + __OM uint32_t START : 1; /*!< Write 1 to continue HUK Generator operation at LOAD/GAIN state. */ + __OM uint32_t CONTINUE : 1; /*!< Write 1 to start HUK Generator at IDLE state. */ + uint32_t : 30; + } bit; + } START; + + union { + __IOM uint32_t reg; /*!< HUK Generator state register */ + + struct { + __IM uint32_t STATE : 2; /*!< The state of HUK Generator. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY. */ + uint32_t : 30; + } bit; + } STATE; + __IM uint32_t RESERVED2[2]; + + union { + __IOM uint32_t reg; /*!< HUK Generator HUK status register */ + + struct { + __IM uint32_t STATUS : 2; /*!< The HUK generation status. 0: HUK is not generated. 1: HUK is + generated and valid. 2: HUK is generated but invalid. 3: + reserved. */ + __IM uint32_t RISK_LEVEL : 3; /*!< The risk level of HUK. 0-6: the higher the risk level is, the + more error bits there are in the PUF SRAM. 7: Error Level, + HUK is invalid. */ + uint32_t : 27; + } bit; + } STATUS; + __IM uint32_t RESERVED3[49]; + + union { + __IOM uint32_t reg; /*!< Version control register */ + + struct { + __IOM uint32_t DATE : 28; /*!< HUK Generator version control register. */ + uint32_t : 4; + } bit; + } DATE; + __IOM uint32_t INFO_MEM[96]; /*!< The memory that stores HUK info. */ +} LP_HUK_Type; /*!< Size = 640 (0x280) */ + + + +/* =========================================================================================================================== */ +/* ================ I2C0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief I2C (Inter-Integrated Circuit) Controller 0 (I2C0) + */ + +typedef struct { /*!< I2C0 Structure */ + + union { + __IOM uint32_t reg; /*!< Configures the low level width of the SCL Clock. */ + + struct { + __IOM uint32_t SCL_LOW_PERIOD : 9; /*!< Configures the low level width of the SCL Clock. Measurement + unit: i2c_sclk. */ + uint32_t : 23; + } bit; + } SCL_LOW_PERIOD; + + union { + __IOM uint32_t reg; /*!< Transmission setting */ + + struct { + __IOM uint32_t SDA_FORCE_OUT : 1; /*!< Configures the SDA output mode1: Direct output,0: Open drain + output. */ + __IOM uint32_t SCL_FORCE_OUT : 1; /*!< Configures the SCL output mode1: Direct output,0: Open drain + output. */ + __IOM uint32_t SAMPLE_SCL_LEVEL : 1; /*!< Configures the sample mode for SDA.1: Sample SDA data on the + SCL low level.0: Sample SDA data on the SCL high level. */ + __IOM uint32_t RX_FULL_ACK_LEVEL : 1; /*!< Configures the ACK value that needs to be sent by master when + the rx_fifo_cnt has reached the threshold. */ + __IOM uint32_t MS_MODE : 1; /*!< Configures the module as an I2C Master or Slave. 0: Slave1: + Master */ + __OM uint32_t TRANS_START : 1; /*!< Configures to start sending the data in txfifo for slave. 0: + No effect1: Start */ + __IOM uint32_t TX_LSB_FIRST : 1; /*!< Configures to control the sending order for data needing to + be sent. 1: send data from the least significant bit,0: + send data from the most significant bit. */ + __IOM uint32_t RX_LSB_FIRST : 1; /*!< Configures to control the storage order for received data.1: + receive data from the least significant bit0: receive data + from the most significant bit. */ + __IOM uint32_t CLK_EN : 1; /*!< Configures whether to gate clock signal for registers.0: Force + clock on for registers 1: Support clock only when registers + are read or written to by software. */ + __IOM uint32_t ARBITRATION_EN : 1; /*!< Configures to enable I2C bus arbitration detection.0: No effect1: + Enable */ + __OM uint32_t FSM_RST : 1; /*!< Configures to reset the SCL_FSM.0: No effect1: Reset */ + __OM uint32_t CONF_UPGATE : 1; /*!< Configures this bit for synchronization0: No effect1: Synchronize */ + __IOM uint32_t SLV_TX_AUTO_START_EN : 1; /*!< Configures to enable slave to send data automatically0: Disable1: + Enable */ + __IOM uint32_t ADDR_10BIT_RW_CHECK_EN : 1;/*!< Configures to check if the r/w bit of 10bit addressing consists + with I2C protocol.0: Not check1: Check */ + __IOM uint32_t ADDR_BROADCASTING_EN : 1; /*!< Configures to support the 7bit general call function. 0: Not + support1: Support */ + uint32_t : 17; + } bit; + } CTR; + + union { + __IOM uint32_t reg; /*!< Describe I2C work status. */ + + struct { + __IM uint32_t RESP_REC : 1; /*!< Represents the received ACK value in master mode or slave mode.0: + ACK,1: NACK. */ + __IM uint32_t SLAVE_RW : 1; /*!< Represents the transfer direction in slave mode,.1: Master reads + from slave,0: Master writes to slave. */ + uint32_t : 1; + __IM uint32_t ARB_LOST : 1; /*!< Represents whether the I2C controller loses control of SCL line.0: + No arbitration lost1: Arbitration lost */ + __IM uint32_t BUS_BUSY : 1; /*!< Represents the I2C bus state.1: The I2C bus is busy transferring + data, 0: The I2C bus is in idle state. */ + __IM uint32_t SLAVE_ADDRESSED : 1; /*!< Represents whether the address sent by the master is equal to + the address of the slave.Valid only when the module is + configured as an I2C Slave.0: Not equal1: Equal */ + uint32_t : 2; + __IM uint32_t RXFIFO_CNT : 6; /*!< Represents the number of data bytes to be sent. */ + __IM uint32_t STRETCH_CAUSE : 2; /*!< Represents the cause of SCL clocking stretching in slave mode.0: + Stretching SCL low when the master starts to read data.1: + Stretching SCL low when I2C TX FIFO is empty in slave mode.2: + Stretching SCL low when I2C RX FIFO is full in slave mode. */ + uint32_t : 2; + __IM uint32_t TXFIFO_CNT : 6; /*!< Represents the number of data bytes received in RAM. */ + __IM uint32_t SCL_MAIN_STATE_LAST : 3; /*!< Represents the states of the I2C module state machine. 0: Idle,1: + Address shift,2: ACK address,3: Rx data,4: Tx data,5: Send + ACK,6: Wait ACK */ + uint32_t : 1; + __IM uint32_t SCL_STATE_LAST : 3; /*!< Represents the states of the state machine used to produce SCL.0: + Idle,1: Start,2: Negative edge,3: Low,4: Positive edge,5: + High,6: Stop */ + uint32_t : 1; + } bit; + } SR; + + union { + __IOM uint32_t reg; /*!< Setting time out control for receiving data. */ + + struct { + __IOM uint32_t TIME_OUT_VALUE : 5; /*!< Configures the timeout threshold period for SCL stucking at + high or low level. The actual period is 2^(reg_time_out_value).Measuremen + unit: i2c_sclk. */ + __IOM uint32_t TIME_OUT_EN : 1; /*!< Configures to enable time out control.0: No effect1: Enable */ + uint32_t : 26; + } bit; + } TO; + + union { + __IOM uint32_t reg; /*!< Local slave address setting */ + + struct { + __IOM uint32_t SLAVE_ADDR : 15; /*!< Configure the slave address of I2C Slave. */ + uint32_t : 16; + __IOM uint32_t ADDR_10BIT_EN : 1; /*!< Configures to enable the slave 10-bit addressing mode in master + mode. 0: No effect1: Enable */ + } bit; + } SLAVE_ADDR; + + union { + __IOM uint32_t reg; /*!< FIFO status register. */ + + struct { + __IM uint32_t RXFIFO_RADDR : 5; /*!< Represents the offset address of the APB reading from RXFIFO */ + __IM uint32_t RXFIFO_WADDR : 5; /*!< Represents the offset address of i2c module receiving data and + writing to RXFIFO. */ + __IM uint32_t TXFIFO_RADDR : 5; /*!< Represents the offset address of i2c module reading from TXFIFO. */ + __IM uint32_t TXFIFO_WADDR : 5; /*!< Represents the offset address of APB bus writing to TXFIFO. */ + uint32_t : 2; + __IM uint32_t SLAVE_RW_POINT : 8; /*!< Represents the offset address in the I2C Slave RAM addressed + by I2C Master when in I2C slave mode. */ + uint32_t : 2; + } bit; + } FIFO_ST; + + union { + __IOM uint32_t reg; /*!< FIFO configuration register. */ + + struct { + __IOM uint32_t RXFIFO_WM_THRHD : 5; /*!< Configures the water mark threshold of RXFIFO in nonfifo access + mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter + is bigger than reg_rxfifo_wm_thrhd[4:0], reg_rxfifo_wm_int_raw + bit will be valid. */ + __IOM uint32_t TXFIFO_WM_THRHD : 5; /*!< Configures the water mark threshold of TXFIFO in nonfifo access + mode. When reg_reg_fifo_prt_en is 1 and tx FIFO counter + is smaller than reg_txfifo_wm_thrhd[4:0], reg_txfifo_wm_int_raw + bit will be valid. */ + __IOM uint32_t NONFIFO_EN : 1; /*!< Configures to enable APB nonfifo access. */ + __IOM uint32_t FIFO_ADDR_CFG_EN : 1; /*!< Configures to enable double addressing mode. When this mode + is enabled, the byte received after the I2C address byte + represents the offset address in the I2C Slave RAM. 0: + Disable1: Enable */ + __IOM uint32_t RX_FIFO_RST : 1; /*!< Configures to reset RXFIFO.0: No effect1: Reset */ + __IOM uint32_t TX_FIFO_RST : 1; /*!< Configures to reset TXFIFO.0: No effect1: Reset */ + __IOM uint32_t FIFO_PRT_EN : 1; /*!< Configures to enable FIFO pointer in non-fifo access mode. This + bit controls the valid bits and the TX/RX FIFO overflow, + underflow, full and empty interrupts.0: No effect1: Enable */ + uint32_t : 17; + } bit; + } FIFO_CONF; + + union { + __IOM uint32_t reg; /*!< Rx FIFO read data. */ + + struct { + __IM uint32_t FIFO_RDATA : 8; /*!< Represents the value of RXFIFO read data. */ + uint32_t : 24; + } bit; + } DATA; + + union { + __IOM uint32_t reg; /*!< Raw interrupt status */ + + struct { + __IM uint32_t RXFIFO_WM_INT_RAW : 1; /*!< The raw interrupt status of I2C_RXFIFO_WM_INT interrupt. */ + __IM uint32_t TXFIFO_WM_INT_RAW : 1; /*!< The raw interrupt status of I2C_TXFIFO_WM_INT interrupt. */ + __IM uint32_t RXFIFO_OVF_INT_RAW : 1; /*!< The raw interrupt status of I2C_RXFIFO_OVF_INT interrupt. */ + __IM uint32_t END_DETECT_INT_RAW : 1; /*!< The raw interrupt status of the I2C_END_DETECT_INT interrupt. */ + __IM uint32_t BYTE_TRANS_DONE_INT_RAW : 1;/*!< The raw interrupt status of the I2C_END_DETECT_INT interrupt. */ + __IM uint32_t ARBITRATION_LOST_INT_RAW : 1;/*!< The raw interrupt status of the I2C_ARBITRATION_LOST_INT interrupt. */ + __IM uint32_t MST_TXFIFO_UDF_INT_RAW : 1;/*!< The raw interrupt status of I2C_TRANS_COMPLETE_INT interrupt. */ + __IM uint32_t TRANS_COMPLETE_INT_RAW : 1;/*!< The raw interrupt status of the I2C_TRANS_COMPLETE_INT interrupt. */ + __IM uint32_t TIME_OUT_INT_RAW : 1; /*!< The raw interrupt status of the I2C_TIME_OUT_INT interrupt. */ + __IM uint32_t TRANS_START_INT_RAW : 1; /*!< The raw interrupt status of the I2C_TRANS_START_INT interrupt. */ + __IM uint32_t NACK_INT_RAW : 1; /*!< The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt. */ + __IM uint32_t TXFIFO_OVF_INT_RAW : 1; /*!< The raw interrupt status of I2C_TXFIFO_OVF_INT interrupt. */ + __IM uint32_t RXFIFO_UDF_INT_RAW : 1; /*!< The raw interrupt status of I2C_RXFIFO_UDF_INT interrupt. */ + __IM uint32_t SCL_ST_TO_INT_RAW : 1; /*!< The raw interrupt status of I2C_SCL_ST_TO_INT interrupt. */ + __IM uint32_t SCL_MAIN_ST_TO_INT_RAW : 1;/*!< The raw interrupt status of I2C_SCL_MAIN_ST_TO_INT interrupt. */ + __IM uint32_t DET_START_INT_RAW : 1; /*!< The raw interrupt status of I2C_DET_START_INT interrupt. */ + __IM uint32_t SLAVE_STRETCH_INT_RAW : 1; /*!< The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt. */ + __IM uint32_t GENERAL_CALL_INT_RAW : 1; /*!< The raw interrupt status of I2C_GENARAL_CALL_INT interrupt. */ + __IM uint32_t SLAVE_ADDR_UNMATCH_INT_RAW : 1;/*!< The raw interrupt status of I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt. */ + uint32_t : 13; + } bit; + } INT_RAW; + + union { + __IOM uint32_t reg; /*!< Interrupt clear bits */ + + struct { + __OM uint32_t RXFIFO_WM_INT_CLR : 1; /*!< Write 1 to clear I2C_RXFIFO_WM_INT interrupt. */ + __OM uint32_t TXFIFO_WM_INT_CLR : 1; /*!< Write 1 to clear I2C_TXFIFO_WM_INT interrupt. */ + __OM uint32_t RXFIFO_OVF_INT_CLR : 1; /*!< Write 1 to clear I2C_RXFIFO_OVF_INT interrupt. */ + __OM uint32_t END_DETECT_INT_CLR : 1; /*!< Write 1 to clear the I2C_END_DETECT_INT interrupt. */ + __OM uint32_t BYTE_TRANS_DONE_INT_CLR : 1;/*!< Write 1 to clear the I2C_END_DETECT_INT interrupt. */ + __OM uint32_t ARBITRATION_LOST_INT_CLR : 1;/*!< Write 1 to clear the I2C_ARBITRATION_LOST_INT interrupt. */ + __OM uint32_t MST_TXFIFO_UDF_INT_CLR : 1;/*!< Write 1 to clear I2C_TRANS_COMPLETE_INT interrupt. */ + __OM uint32_t TRANS_COMPLETE_INT_CLR : 1;/*!< Write 1 to clear the I2C_TRANS_COMPLETE_INT interrupt. */ + __OM uint32_t TIME_OUT_INT_CLR : 1; /*!< Write 1 to clear the I2C_TIME_OUT_INT interrupt. */ + __OM uint32_t TRANS_START_INT_CLR : 1; /*!< Write 1 to clear the I2C_TRANS_START_INT interrupt. */ + __OM uint32_t NACK_INT_CLR : 1; /*!< Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt. */ + __OM uint32_t TXFIFO_OVF_INT_CLR : 1; /*!< Write 1 to clear I2C_TXFIFO_OVF_INT interrupt. */ + __OM uint32_t RXFIFO_UDF_INT_CLR : 1; /*!< Write 1 to clear I2C_RXFIFO_UDF_INT interrupt. */ + __OM uint32_t SCL_ST_TO_INT_CLR : 1; /*!< Write 1 to clear I2C_SCL_ST_TO_INT interrupt. */ + __OM uint32_t SCL_MAIN_ST_TO_INT_CLR : 1;/*!< Write 1 to clear I2C_SCL_MAIN_ST_TO_INT interrupt. */ + __OM uint32_t DET_START_INT_CLR : 1; /*!< Write 1 to clear I2C_DET_START_INT interrupt. */ + __OM uint32_t SLAVE_STRETCH_INT_CLR : 1; /*!< Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt. */ + __OM uint32_t GENERAL_CALL_INT_CLR : 1; /*!< Write 1 to clear I2C_GENARAL_CALL_INT interrupt. */ + __OM uint32_t SLAVE_ADDR_UNMATCH_INT_CLR : 1;/*!< Write 1 to clear I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt. */ + uint32_t : 13; + } bit; + } INT_CLR; + + union { + __IOM uint32_t reg; /*!< Interrupt enable bits */ + + struct { + __IOM uint32_t RXFIFO_WM_INT_ENA : 1; /*!< Write 1 to enable I2C_RXFIFO_WM_INT interrupt. */ + __IOM uint32_t TXFIFO_WM_INT_ENA : 1; /*!< Write 1 to enable I2C_TXFIFO_WM_INT interrupt. */ + __IOM uint32_t RXFIFO_OVF_INT_ENA : 1; /*!< Write 1 to enable I2C_RXFIFO_OVF_INT interrupt. */ + __IOM uint32_t END_DETECT_INT_ENA : 1; /*!< Write 1 to enable the I2C_END_DETECT_INT interrupt. */ + __IOM uint32_t BYTE_TRANS_DONE_INT_ENA : 1;/*!< Write 1 to enable the I2C_END_DETECT_INT interrupt. */ + __IOM uint32_t ARBITRATION_LOST_INT_ENA : 1;/*!< Write 1 to enable the I2C_ARBITRATION_LOST_INT interrupt. */ + __IOM uint32_t MST_TXFIFO_UDF_INT_ENA : 1;/*!< Write 1 to enable I2C_TRANS_COMPLETE_INT interrupt. */ + __IOM uint32_t TRANS_COMPLETE_INT_ENA : 1;/*!< Write 1 to enable the I2C_TRANS_COMPLETE_INT interrupt. */ + __IOM uint32_t TIME_OUT_INT_ENA : 1; /*!< Write 1 to enable the I2C_TIME_OUT_INT interrupt. */ + __IOM uint32_t TRANS_START_INT_ENA : 1; /*!< Write 1 to enable the I2C_TRANS_START_INT interrupt. */ + __IOM uint32_t NACK_INT_ENA : 1; /*!< Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt. */ + __IOM uint32_t TXFIFO_OVF_INT_ENA : 1; /*!< Write 1 to enable I2C_TXFIFO_OVF_INT interrupt. */ + __IOM uint32_t RXFIFO_UDF_INT_ENA : 1; /*!< Write 1 to enable I2C_RXFIFO_UDF_INT interrupt. */ + __IOM uint32_t SCL_ST_TO_INT_ENA : 1; /*!< Write 1 to enable I2C_SCL_ST_TO_INT interrupt. */ + __IOM uint32_t SCL_MAIN_ST_TO_INT_ENA : 1;/*!< Write 1 to enable I2C_SCL_MAIN_ST_TO_INT interrupt. */ + __IOM uint32_t DET_START_INT_ENA : 1; /*!< Write 1 to enable I2C_DET_START_INT interrupt. */ + __IOM uint32_t SLAVE_STRETCH_INT_ENA : 1; /*!< Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt. */ + __IOM uint32_t GENERAL_CALL_INT_ENA : 1; /*!< Write 1 to enable I2C_GENARAL_CALL_INT interrupt. */ + __IOM uint32_t SLAVE_ADDR_UNMATCH_INT_ENA : 1;/*!< Write 1 to enable I2C_SLAVE_ADDR_UNMATCH_INT interrupt. */ + uint32_t : 13; + } bit; + } INT_ENA; + + union { + __IOM uint32_t reg; /*!< Status of captured I2C communication events */ + + struct { + __IM uint32_t RXFIFO_WM_INT_ST : 1; /*!< The masked interrupt status status of I2C_RXFIFO_WM_INT interrupt. */ + __IM uint32_t TXFIFO_WM_INT_ST : 1; /*!< The masked interrupt status status of I2C_TXFIFO_WM_INT interrupt. */ + __IM uint32_t RXFIFO_OVF_INT_ST : 1; /*!< The masked interrupt status status of I2C_RXFIFO_OVF_INT interrupt. */ + __IM uint32_t END_DETECT_INT_ST : 1; /*!< The masked interrupt status status of the I2C_END_DETECT_INT + interrupt. */ + __IM uint32_t BYTE_TRANS_DONE_INT_ST : 1;/*!< The masked interrupt status status of the I2C_END_DETECT_INT + interrupt. */ + __IM uint32_t ARBITRATION_LOST_INT_ST : 1;/*!< The masked interrupt status status of the I2C_ARBITRATION_LOST_INT + interrupt. */ + __IM uint32_t MST_TXFIFO_UDF_INT_ST : 1; /*!< The masked interrupt status status of I2C_TRANS_COMPLETE_INT + interrupt. */ + __IM uint32_t TRANS_COMPLETE_INT_ST : 1; /*!< The masked interrupt status status of the I2C_TRANS_COMPLETE_INT + interrupt. */ + __IM uint32_t TIME_OUT_INT_ST : 1; /*!< The masked interrupt status status of the I2C_TIME_OUT_INT interrupt. */ + __IM uint32_t TRANS_START_INT_ST : 1; /*!< The masked interrupt status status of the I2C_TRANS_START_INT + interrupt. */ + __IM uint32_t NACK_INT_ST : 1; /*!< The masked interrupt status status of I2C_SLAVE_STRETCH_INT + interrupt. */ + __IM uint32_t TXFIFO_OVF_INT_ST : 1; /*!< The masked interrupt status status of I2C_TXFIFO_OVF_INT interrupt. */ + __IM uint32_t RXFIFO_UDF_INT_ST : 1; /*!< The masked interrupt status status of I2C_RXFIFO_UDF_INT interrupt. */ + __IM uint32_t SCL_ST_TO_INT_ST : 1; /*!< The masked interrupt status status of I2C_SCL_ST_TO_INT interrupt. */ + __IM uint32_t SCL_MAIN_ST_TO_INT_ST : 1; /*!< The masked interrupt status status of I2C_SCL_MAIN_ST_TO_INT + interrupt. */ + __IM uint32_t DET_START_INT_ST : 1; /*!< The masked interrupt status status of I2C_DET_START_INT interrupt. */ + __IM uint32_t SLAVE_STRETCH_INT_ST : 1; /*!< The masked interrupt status status of I2C_SLAVE_STRETCH_INT + interrupt. */ + __IM uint32_t GENERAL_CALL_INT_ST : 1; /*!< The masked interrupt status status of I2C_GENARAL_CALL_INT interrupt. */ + __IM uint32_t SLAVE_ADDR_UNMATCH_INT_ST : 1;/*!< The masked interrupt status status of I2C_SLAVE_ADDR_UNMATCH_INT + interrupt. */ + uint32_t : 13; + } bit; + } INT_STATUS; + + union { + __IOM uint32_t reg; /*!< Configures the hold time after a negative SCL edge. */ + + struct { + __IOM uint32_t TIME : 9; /*!< Configures the time to hold the data after the falling edge + of SCL.Measurement unit: i2c_sclk */ + uint32_t : 23; + } bit; + } SDA_HOLD; + + union { + __IOM uint32_t reg; /*!< Configures the sample time after a positive SCL edge. */ + + struct { + __IOM uint32_t TIME : 9; /*!< Configures the sample time after a positive SCL edge.Measurement + unit: i2c_sclk */ + uint32_t : 23; + } bit; + } SDA_SAMPLE; + + union { + __IOM uint32_t reg; /*!< Configures the high level width of SCL */ + + struct { + __IOM uint32_t SCL_HIGH_PERIOD : 9; /*!< Configures for how long SCL remains high in master mode.Measurement + unit: i2c_sclk */ + __IOM uint32_t SCL_WAIT_HIGH_PERIOD : 7; /*!< Configures the SCL_FSM's waiting period for SCL high level in + master mode.Measurement unit: i2c_sclk */ + uint32_t : 16; + } bit; + } SCL_HIGH_PERIOD; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t reg; /*!< Configures the delay between the SDA and SCL negative edge for + a start condition */ + + struct { + __IOM uint32_t TIME : 9; /*!< Configures the time between the falling edge of SDA and the + falling edge of SCL for a START condition.Measurement unit: + i2c_sclk. */ + uint32_t : 23; + } bit; + } SCL_START_HOLD; + + union { + __IOM uint32_t reg; /*!< Configures the delay between the positive edge of SCL and the + negative edge of SDA */ + + struct { + __IOM uint32_t TIME : 9; /*!< Configures the time between the positive edge of SCL and the + negative edge of SDA for a RESTART condition.Measurement + unit: i2c_sclk */ + uint32_t : 23; + } bit; + } SCL_RSTART_SETUP; + + union { + __IOM uint32_t reg; /*!< Configures the delay after the SCL clock edge for a stop condition */ + + struct { + __IOM uint32_t TIME : 9; /*!< Configures the delay after the STOP condition.Measurement unit: + i2c_sclk */ + uint32_t : 23; + } bit; + } SCL_STOP_HOLD; + + union { + __IOM uint32_t reg; /*!< Configures the delay between the SDA and SCL rising edge for + a stop condition.Measurement unit: i2c_sclk */ + + struct { + __IOM uint32_t TIME : 9; /*!< Configures the time between the rising edge of SCL and the rising + edge of SDA.Measurement unit: i2c_sclk */ + uint32_t : 23; + } bit; + } SCL_STOP_SETUP; + + union { + __IOM uint32_t reg; /*!< SCL and SDA filter configuration register */ + + struct { + __IOM uint32_t SCL_FILTER_THRES : 4; /*!< Configures the threshold pulse width to be filtered on SCL. + When a pulse on the SCL input has smaller width than this + register value, the I2C controller will ignore that pulse. + Measurement unit: i2c_sclk */ + __IOM uint32_t SDA_FILTER_THRES : 4; /*!< Configures the threshold pulse width to be filtered on SDA. + When a pulse on the SDA input has smaller width than this + register value, the I2C controller will ignore that pulse. + Measurement unit: i2c_sclk */ + __IOM uint32_t SCL_FILTER_EN : 1; /*!< Configures to enable the filter function for SCL. */ + __IOM uint32_t SDA_FILTER_EN : 1; /*!< Configures to enable the filter function for SDA. */ + uint32_t : 22; + } bit; + } FILTER_CFG; + + union { + __IOM uint32_t reg; /*!< I2C CLK configuration register */ + + struct { + __IOM uint32_t SCLK_DIV_NUM : 8; /*!< the integral part of the fractional divisor for i2c module */ + __IOM uint32_t SCLK_DIV_A : 6; /*!< the numerator of the fractional part of the fractional divisor + for i2c module */ + __IOM uint32_t SCLK_DIV_B : 6; /*!< the denominator of the fractional part of the fractional divisor + for i2c module */ + __IOM uint32_t SCLK_SEL : 1; /*!< The clock selection for i2c module:0-XTAL,1-CLK_8MHz. */ + __IOM uint32_t SCLK_ACTIVE : 1; /*!< The clock switch for i2c module */ + uint32_t : 10; + } bit; + } CLK_CONF; + + union { + __IOM uint32_t reg; /*!< I2C command register 0 */ + + struct { + __IOM uint32_t COMMAND0 : 14; /*!< Configures command 0. It consists of three parts: op_code is + the command,0: RSTART, 1: WRITE,2: READ,3: STOP,4: END.Byte_num + represents the number of bytes that need to be sent or + received.ack_check_en, ack_exp and ack are used to control + the ACK bit. See I2C cmd structure for more information. */ + uint32_t : 17; + __IOM uint32_t COMMAND0_DONE : 1; /*!< Represents whether command 0 is done in I2C Master mode.0: Not + done1: Done */ + } bit; + } COMD0; + + union { + __IOM uint32_t reg; /*!< I2C command register 1 */ + + struct { + __IOM uint32_t COMMAND1 : 14; /*!< Configures command 1. See details in I2C_CMD0_REG[13:0]. */ + uint32_t : 17; + __IOM uint32_t COMMAND1_DONE : 1; /*!< Represents whether command 1 is done in I2C Master mode.0: Not + done1: Done */ + } bit; + } COMD1; + + union { + __IOM uint32_t reg; /*!< I2C command register 2 */ + + struct { + __IOM uint32_t COMMAND2 : 14; /*!< Configures command 2. See details in I2C_CMD0_REG[13:0]. */ + uint32_t : 17; + __IOM uint32_t COMMAND2_DONE : 1; /*!< Represents whether command 2 is done in I2C Master mode.0: Not + done1: Done */ + } bit; + } COMD2; + + union { + __IOM uint32_t reg; /*!< I2C command register 3 */ + + struct { + __IOM uint32_t COMMAND3 : 14; /*!< Configures command 3. See details in I2C_CMD0_REG[13:0]. */ + uint32_t : 17; + __IOM uint32_t COMMAND3_DONE : 1; /*!< Represents whether command 3 is done in I2C Master mode.0: Not + done1: Done */ + } bit; + } COMD3; + + union { + __IOM uint32_t reg; /*!< I2C command register 4 */ + + struct { + __IOM uint32_t COMMAND4 : 14; /*!< Configures command 4. See details in I2C_CMD0_REG[13:0]. */ + uint32_t : 17; + __IOM uint32_t COMMAND4_DONE : 1; /*!< Represents whether command 4 is done in I2C Master mode.0: Not + done1: Done */ + } bit; + } COMD4; + + union { + __IOM uint32_t reg; /*!< I2C command register 5 */ + + struct { + __IOM uint32_t COMMAND5 : 14; /*!< Configures command 5. See details in I2C_CMD0_REG[13:0]. */ + uint32_t : 17; + __IOM uint32_t COMMAND5_DONE : 1; /*!< Represents whether command 5 is done in I2C Master mode.0: Not + done1: Done */ + } bit; + } COMD5; + + union { + __IOM uint32_t reg; /*!< I2C command register 6 */ + + struct { + __IOM uint32_t COMMAND6 : 14; /*!< Configures command 6. See details in I2C_CMD0_REG[13:0]. */ + uint32_t : 17; + __IOM uint32_t COMMAND6_DONE : 1; /*!< Represents whether command 6 is done in I2C Master mode.0: Not + done1: Done */ + } bit; + } COMD6; + + union { + __IOM uint32_t reg; /*!< I2C command register 7 */ + + struct { + __IOM uint32_t COMMAND7 : 14; /*!< Configures command 7. See details in I2C_CMD0_REG[13:0]. */ + uint32_t : 17; + __IOM uint32_t COMMAND7_DONE : 1; /*!< Represents whether command 7 is done in I2C Master mode.0: Not + done1: Done */ + } bit; + } COMD7; + + union { + __IOM uint32_t reg; /*!< SCL status time out register */ + + struct { + __IOM uint32_t SCL_ST_TO_I2C : 5; /*!< Configures the threshold value of SCL_FSM state unchanged period. + It should be no more than 23.Measurement unit: i2c_sclk */ + uint32_t : 27; + } bit; + } SCL_ST_TIME_OUT; + + union { + __IOM uint32_t reg; /*!< SCL main status time out register */ + + struct { + __IOM uint32_t SCL_MAIN_ST_TO_I2C : 5; /*!< Configures the threshold value of SCL_MAIN_FSM state unchanged + period.nIt should be no more than 23.Measurement unit: + i2c_sclk */ + uint32_t : 27; + } bit; + } SCL_MAIN_ST_TIME_OUT; + + union { + __IOM uint32_t reg; /*!< Power configuration register */ + + struct { + __IOM uint32_t SCL_RST_SLV_EN : 1; /*!< Configures to send out SCL pulses when I2C master is IDLE. The + number of pulses equals to reg_scl_rst_slv_num[4:0]. */ + __IOM uint32_t SCL_RST_SLV_NUM : 5; /*!< Configure the pulses of SCL generated in I2C master mode. Valid + when reg_scl_rst_slv_en is 1.Measurement unit: i2c_sclk */ + __IOM uint32_t SCL_PD_EN : 1; /*!< Configures to power down the I2C output SCL line. 0: Not power + down.1: Power down.Valid only when reg_scl_force_out is + 1. */ + __IOM uint32_t SDA_PD_EN : 1; /*!< Configures to power down the I2C output SDA line. 0: Not power + down.1: Power down.Valid only when reg_sda_force_out is + 1. */ + uint32_t : 24; + } bit; + } SCL_SP_CONF; + + union { + __IOM uint32_t reg; /*!< Set SCL stretch of I2C slave */ + + struct { + __IOM uint32_t STRETCH_PROTECT_NUM : 10; /*!< Configures the time period to release the SCL line from stretching + to avoid timing violation. Usually it should be larger + than the SDA setup time.Measurement unit: i2c_sclk */ + __IOM uint32_t SLAVE_SCL_STRETCH_EN : 1; /*!< Configures to enable slave SCL stretch function.0: Disable1: + EnableThe SCL output line will be stretched low when reg_slave_scl_stretc + _en is 1 and stretch event happens. The stretch cause can + be seen in reg_stretch_cause. */ + __OM uint32_t SLAVE_SCL_STRETCH_CLR : 1; /*!< Configures to clear the I2C slave SCL stretch function.0: No + effect1: Clear */ + __IOM uint32_t SLAVE_BYTE_ACK_CTL_EN : 1; /*!< Configures to enable the function for slave to control ACK level.0: + Disable1: Enable */ + __IOM uint32_t SLAVE_BYTE_ACK_LVL : 1; /*!< Set the ACK level when slave controlling ACK level function + enables.0: Low level1: High level */ + uint32_t : 18; + } bit; + } SCL_STRETCH_CONF; + __IM uint32_t RESERVED1[28]; + + union { + __IOM uint32_t reg; /*!< Version register */ + + struct { + __IOM uint32_t DATE : 32; /*!< Version control register. */ + } bit; + } DATE; + __IM uint32_t RESERVED2; + + union { + __IOM uint32_t reg; /*!< I2C TXFIFO base address register */ + + struct { + __IM uint32_t TXFIFO_START_ADDR : 32; /*!< Represents the I2C txfifo first address. */ + } bit; + } TXFIFO_START_ADDR; + __IM uint32_t RESERVED3[31]; + + union { + __IOM uint32_t reg; /*!< I2C RXFIFO base address register */ + + struct { + __IM uint32_t RXFIFO_START_ADDR : 32; /*!< Represents the I2C rxfifo first address. */ + } bit; + } RXFIFO_START_ADDR; +} I2C0_Type; /*!< Size = 388 (0x184) */ + + + +/* =========================================================================================================================== */ +/* ================ I2S0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief I2S (Inter-IC Sound) Controller 0 (I2S0) + */ + +typedef struct { /*!< I2S0 Structure */ + __IM uint32_t RESERVED[3]; + + union { + __IOM uint32_t reg; /*!< I2S interrupt raw register, valid in level. */ + + struct { + __IM uint32_t RX_DONE_INT_RAW : 1; /*!< The raw interrupt status bit for the i2s_rx_done_int interrupt */ + __IM uint32_t TX_DONE_INT_RAW : 1; /*!< The raw interrupt status bit for the i2s_tx_done_int interrupt */ + __IM uint32_t RX_HUNG_INT_RAW : 1; /*!< The raw interrupt status bit for the i2s_rx_hung_int interrupt */ + __IM uint32_t TX_HUNG_INT_RAW : 1; /*!< The raw interrupt status bit for the i2s_tx_hung_int interrupt */ + uint32_t : 28; + } bit; + } INT_RAW; + + union { + __IOM uint32_t reg; /*!< I2S interrupt status register. */ + + struct { + __IM uint32_t RX_DONE_INT_ST : 1; /*!< The masked interrupt status bit for the i2s_rx_done_int interrupt */ + __IM uint32_t TX_DONE_INT_ST : 1; /*!< The masked interrupt status bit for the i2s_tx_done_int interrupt */ + __IM uint32_t RX_HUNG_INT_ST : 1; /*!< The masked interrupt status bit for the i2s_rx_hung_int interrupt */ + __IM uint32_t TX_HUNG_INT_ST : 1; /*!< The masked interrupt status bit for the i2s_tx_hung_int interrupt */ + uint32_t : 28; + } bit; + } INT_ST; + + union { + __IOM uint32_t reg; /*!< I2S interrupt enable register. */ + + struct { + __IOM uint32_t RX_DONE_INT_ENA : 1; /*!< The interrupt enable bit for the i2s_rx_done_int interrupt */ + __IOM uint32_t TX_DONE_INT_ENA : 1; /*!< The interrupt enable bit for the i2s_tx_done_int interrupt */ + __IOM uint32_t RX_HUNG_INT_ENA : 1; /*!< The interrupt enable bit for the i2s_rx_hung_int interrupt */ + __IOM uint32_t TX_HUNG_INT_ENA : 1; /*!< The interrupt enable bit for the i2s_tx_hung_int interrupt */ + uint32_t : 28; + } bit; + } INT_ENA; + + union { + __IOM uint32_t reg; /*!< I2S interrupt clear register. */ + + struct { + __OM uint32_t RX_DONE_INT_CLR : 1; /*!< Set this bit to clear the i2s_rx_done_int interrupt */ + __OM uint32_t TX_DONE_INT_CLR : 1; /*!< Set this bit to clear the i2s_tx_done_int interrupt */ + __OM uint32_t RX_HUNG_INT_CLR : 1; /*!< Set this bit to clear the i2s_rx_hung_int interrupt */ + __OM uint32_t TX_HUNG_INT_CLR : 1; /*!< Set this bit to clear the i2s_tx_hung_int interrupt */ + uint32_t : 28; + } bit; + } INT_CLR; + __IM uint32_t RESERVED1; + + union { + __IOM uint32_t reg; /*!< I2S RX configure register */ + + struct { + __OM uint32_t RX_RESET : 1; /*!< Set this bit to reset receiver */ + __OM uint32_t RX_FIFO_RESET : 1; /*!< Set this bit to reset Rx AFIFO */ + __IOM uint32_t RX_START : 1; /*!< Set this bit to start receiving data */ + __IOM uint32_t RX_SLAVE_MOD : 1; /*!< Set this bit to enable slave receiver mode */ + __IOM uint32_t RX_STOP_MODE : 2; /*!< 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when + reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when + reg_rx_start is 0 or RX FIFO is full. */ + __IOM uint32_t RX_MONO : 1; /*!< Set this bit to enable receiver in mono mode */ + __IOM uint32_t RX_BIG_ENDIAN : 1; /*!< I2S Rx byte endian, 1: low addr value to high addr. 0: low addr + with low addr value. */ + __IOM uint32_t RX_UPDATE : 1; /*!< Set 1 to update I2S RX registers from APB clock domain to I2S + RX clock domain. This bit will be cleared by hardware after + update register done. */ + __IOM uint32_t RX_MONO_FST_VLD : 1; /*!< 1: The first channel data value is valid in I2S RX mono mode. + 0: The second channel data value is valid in I2S RX mono + mode. */ + __IOM uint32_t RX_PCM_CONF : 2; /*!< I2S RX compress/decompress configuration bit. & 0 (atol): A-Law + decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law + decompress, 3 (ltou) : u-Law compress. & */ + __IOM uint32_t RX_PCM_BYPASS : 1; /*!< Set this bit to bypass Compress/Decompress module for received + data. */ + __IOM uint32_t RX_MSB_SHIFT : 1; /*!< Set this bit to enable receiver in Phillips standard mode */ + uint32_t : 1; + __IOM uint32_t RX_LEFT_ALIGN : 1; /*!< 1: I2S RX left alignment mode. 0: I2S RX right alignment mode. */ + __IOM uint32_t RX_24_FILL_EN : 1; /*!< 1: store 24 channel bits to 32 bits. 0:store 24 channel bits + to 24 bits. */ + __IOM uint32_t RX_WS_IDLE_POL : 1; /*!< 0: WS should be 0 when receiving left channel data, and WS is + 1in right channel. 1: WS should be 1 when receiving left + channel data, and WS is 0in right channel. */ + __IOM uint32_t RX_BIT_ORDER : 1; /*!< I2S Rx bit endian. 1:small endian, the LSB is received first. + 0:big endian, the MSB is received first. */ + __IOM uint32_t RX_TDM_EN : 1; /*!< 1: Enable I2S TDM Rx mode . 0: Disable. */ + __IOM uint32_t RX_PDM_EN : 1; /*!< 1: Enable I2S PDM Rx mode . 0: Disable. */ + __IOM uint32_t RX_BCK_DIV_NUM : 6; /*!< Bit clock configuration bits in receiver mode. */ + uint32_t : 5; + } bit; + } RX_CONF; + + union { + __IOM uint32_t reg; /*!< I2S TX configure register */ + + struct { + __OM uint32_t TX_RESET : 1; /*!< Set this bit to reset transmitter */ + __OM uint32_t TX_FIFO_RESET : 1; /*!< Set this bit to reset Tx AFIFO */ + __IOM uint32_t TX_START : 1; /*!< Set this bit to start transmitting data */ + __IOM uint32_t TX_SLAVE_MOD : 1; /*!< Set this bit to enable slave transmitter mode */ + __IOM uint32_t TX_STOP_EN : 1; /*!< Set this bit to stop disable output BCK signal and WS signal + when tx FIFO is emtpy */ + __IOM uint32_t TX_CHAN_EQUAL : 1; /*!< 1: The value of Left channel data is equal to the value of right + channel data in I2S TX mono mode or TDM channel select + mode. 0: The invalid channel data is reg_i2s_single_data + in I2S TX mono mode or TDM channel select mode. */ + __IOM uint32_t TX_MONO : 1; /*!< Set this bit to enable transmitter in mono mode */ + __IOM uint32_t TX_BIG_ENDIAN : 1; /*!< I2S Tx byte endian, 1: low addr value to high addr. 0: low addr + with low addr value. */ + __IOM uint32_t TX_UPDATE : 1; /*!< Set 1 to update I2S TX registers from APB clock domain to I2S + TX clock domain. This bit will be cleared by hardware after + update register done. */ + __IOM uint32_t TX_MONO_FST_VLD : 1; /*!< 1: The first channel data value is valid in I2S TX mono mode. + 0: The second channel data value is valid in I2S TX mono + mode. */ + __IOM uint32_t TX_PCM_CONF : 2; /*!< I2S TX compress/decompress configuration bit. & 0 (atol): A-Law + decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law + decompress, 3 (ltou) : u-Law compress. & */ + __IOM uint32_t TX_PCM_BYPASS : 1; /*!< Set this bit to bypass Compress/Decompress module for transmitted + data. */ + __IOM uint32_t TX_MSB_SHIFT : 1; /*!< Set this bit to enable transmitter in Phillips standard mode */ + __IOM uint32_t TX_BCK_NO_DLY : 1; /*!< 1: BCK is not delayed to generate pos/neg edge in master mode. + 0: BCK is delayed to generate pos/neg edge in master mode. */ + __IOM uint32_t TX_LEFT_ALIGN : 1; /*!< 1: I2S TX left alignment mode. 0: I2S TX right alignment mode. */ + __IOM uint32_t TX_24_FILL_EN : 1; /*!< 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in + 24 channel bits mode */ + __IOM uint32_t TX_WS_IDLE_POL : 1; /*!< 0: WS should be 0 when sending left channel data, and WS is + 1in right channel. 1: WS should be 1 when sending left + channel data, and WS is 0in right channel. */ + __IOM uint32_t TX_BIT_ORDER : 1; /*!< I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big + endian, the MSB is sent first. */ + __IOM uint32_t TX_TDM_EN : 1; /*!< 1: Enable I2S TDM Tx mode . 0: Disable. */ + __IOM uint32_t TX_PDM_EN : 1; /*!< 1: Enable I2S PDM Tx mode . 0: Disable. */ + __IOM uint32_t TX_BCK_DIV_NUM : 6; /*!< Bit clock configuration bits in transmitter mode. */ + __IOM uint32_t TX_CHAN_MOD : 3; /*!< I2S transmitter channel mode configuration bits. */ + __IOM uint32_t SIG_LOOPBACK : 1; /*!< Enable signal loop back mode with transmitter module and receiver + module sharing the same WS and BCK signals. */ + uint32_t : 1; + } bit; + } TX_CONF; + + union { + __IOM uint32_t reg; /*!< I2S RX configure register 1 */ + + struct { + __IOM uint32_t RX_TDM_WS_WIDTH : 9; /*!< The width of rx_ws_out at idle level in TDM mode is (I2S_RX_TDM_WS_WIDTH[8:0] + +1) * T_bck */ + uint32_t : 5; + __IOM uint32_t RX_BITS_MOD : 5; /*!< Set the bits to configure the valid data bit length of I2S receiver + channel. 7: all the valid channel data is in 8-bit-mode. + 15: all the valid channel data is in 16-bit-mode. 23: all + the valid channel data is in 24-bit-mode. 31:all the valid + channel data is in 32-bit-mode. */ + __IOM uint32_t RX_HALF_SAMPLE_BITS : 8; /*!< I2S Rx half sample bits -1. */ + __IOM uint32_t RX_TDM_CHAN_BITS : 5; /*!< The Rx bit number for each channel minus 1in TDM mode. */ + } bit; + } RX_CONF1; + + union { + __IOM uint32_t reg; /*!< I2S TX configure register 1 */ + + struct { + __IOM uint32_t TX_TDM_WS_WIDTH : 9; /*!< The width of tx_ws_out at idle level in TDM mode is (I2S_TX_TDM_WS_WIDTH[8:0] + +1) * T_bck */ + uint32_t : 5; + __IOM uint32_t TX_BITS_MOD : 5; /*!< Set the bits to configure the valid data bit length of I2S transmitter + channel. 7: all the valid channel data is in 8-bit-mode. + 15: all the valid channel data is in 16-bit-mode. 23: all + the valid channel data is in 24-bit-mode. 31:all the valid + channel data is in 32-bit-mode. */ + __IOM uint32_t TX_HALF_SAMPLE_BITS : 8; /*!< I2S Tx half sample bits -1. */ + __IOM uint32_t TX_TDM_CHAN_BITS : 5; /*!< The Tx bit number for each channel minus 1in TDM mode. */ + } bit; + } TX_CONF1; + __IM uint32_t RESERVED2[4]; + + union { + __IOM uint32_t reg; /*!< I2S TX PCM2PDM configuration register */ + + struct { + __IOM uint32_t TX_PDM_HP_BYPASS : 1; /*!< I2S TX PDM bypass hp filter or not. The option has been removed. */ + __IOM uint32_t TX_PDM_SINC_OSR2 : 4; /*!< I2S TX PDM OSR2 value */ + __IOM uint32_t TX_PDM_PRESCALE : 8; /*!< I2S TX PDM prescale for sigmadelta */ + __IOM uint32_t TX_PDM_HP_IN_SHIFT : 2; /*!< I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 + , 3: x4 */ + __IOM uint32_t TX_PDM_LP_IN_SHIFT : 2; /*!< I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 + , 3: x4 */ + __IOM uint32_t TX_PDM_SINC_IN_SHIFT : 2; /*!< I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 + , 3: x4 */ + __IOM uint32_t TX_PDM_SIGMADELTA_IN_SHIFT : 2;/*!< I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 + , 3: x4 */ + __IOM uint32_t TX_PDM_SIGMADELTA_DITHER2 : 1;/*!< I2S TX PDM sigmadelta dither2 value */ + __IOM uint32_t TX_PDM_SIGMADELTA_DITHER : 1;/*!< I2S TX PDM sigmadelta dither value */ + __IOM uint32_t TX_PDM_DAC_2OUT_EN : 1; /*!< I2S TX PDM dac mode enable */ + __IOM uint32_t TX_PDM_DAC_MODE_EN : 1; /*!< I2S TX PDM dac 2channel enable */ + __IOM uint32_t PCM2PDM_CONV_EN : 1; /*!< I2S TX PDM Converter enable */ + uint32_t : 6; + } bit; + } TX_PCM2PDM_CONF; + + union { + __IOM uint32_t reg; /*!< I2S TX PCM2PDM configuration register */ + + struct { + __IOM uint32_t TX_PDM_FP : 10; /*!< I2S TX PDM Fp */ + __IOM uint32_t TX_PDM_FS : 10; /*!< I2S TX PDM Fs */ + __IOM uint32_t TX_IIR_HP_MULT12_5 : 3; /*!< The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + + I2S_TX_IIR_HP_MULT12_5[2:0]) */ + __IOM uint32_t TX_IIR_HP_MULT12_0 : 3; /*!< The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + + I2S_TX_IIR_HP_MULT12_0[2:0]) */ + uint32_t : 6; + } bit; + } TX_PCM2PDM_CONF1; + + union { + __IOM uint32_t reg; /*!< I2S RX configure register */ + + struct { + uint32_t : 19; + __IOM uint32_t RX_PDM2PCM_EN : 1; /*!< 1: Enable PDM2PCM RX mode. 0: DIsable. */ + __IOM uint32_t RX_PDM_SINC_DSR_16_EN : 1; /*!< Configure the down sampling rate of PDM RX filter group1 module. + 1: The down sampling rate is 128. 0: down sampling rate + is 64. */ + __IOM uint32_t RX_PDM2PCM_AMPLIFY_NUM : 4;/*!< Configure PDM RX amplify number. */ + __IOM uint32_t RX_PDM_HP_BYPASS : 1; /*!< I2S PDM RX bypass hp filter or not. */ + __IOM uint32_t RX_IIR_HP_MULT12_5 : 3; /*!< The fourth parameter of PDM RX IIR_HP filter stage 2 is (504 + + LP_I2S_RX_IIR_HP_MULT12_5[2:0]) */ + __IOM uint32_t RX_IIR_HP_MULT12_0 : 3; /*!< The fourth parameter of PDM RX IIR_HP filter stage 1 is (504 + + LP_I2S_RX_IIR_HP_MULT12_0[2:0]) */ + } bit; + } RX_PDM2PCM_CONF; + __IM uint32_t RESERVED3; + + union { + __IOM uint32_t reg; /*!< I2S TX TDM mode control register */ + + struct { + __IOM uint32_t RX_TDM_PDM_CHAN0_EN : 1; /*!< 1: Enable the valid data input of I2S RX TDM or PDM channel + 0. 0: Disable, just input 0 in this channel. */ + __IOM uint32_t RX_TDM_PDM_CHAN1_EN : 1; /*!< 1: Enable the valid data input of I2S RX TDM or PDM channel + 1. 0: Disable, just input 0 in this channel. */ + __IOM uint32_t RX_TDM_PDM_CHAN2_EN : 1; /*!< 1: Enable the valid data input of I2S RX TDM or PDM channel + 2. 0: Disable, just input 0 in this channel. */ + __IOM uint32_t RX_TDM_PDM_CHAN3_EN : 1; /*!< 1: Enable the valid data input of I2S RX TDM or PDM channel + 3. 0: Disable, just input 0 in this channel. */ + __IOM uint32_t RX_TDM_PDM_CHAN4_EN : 1; /*!< 1: Enable the valid data input of I2S RX TDM or PDM channel + 4. 0: Disable, just input 0 in this channel. */ + __IOM uint32_t RX_TDM_PDM_CHAN5_EN : 1; /*!< 1: Enable the valid data input of I2S RX TDM or PDM channel + 5. 0: Disable, just input 0 in this channel. */ + __IOM uint32_t RX_TDM_PDM_CHAN6_EN : 1; /*!< 1: Enable the valid data input of I2S RX TDM or PDM channel + 6. 0: Disable, just input 0 in this channel. */ + __IOM uint32_t RX_TDM_PDM_CHAN7_EN : 1; /*!< 1: Enable the valid data input of I2S RX TDM or PDM channel + 7. 0: Disable, just input 0 in this channel. */ + __IOM uint32_t RX_TDM_CHAN8_EN : 1; /*!< 1: Enable the valid data input of I2S RX TDM channel 8. 0: Disable, + just input 0 in this channel. */ + __IOM uint32_t RX_TDM_CHAN9_EN : 1; /*!< 1: Enable the valid data input of I2S RX TDM channel 9. 0: Disable, + just input 0 in this channel. */ + __IOM uint32_t RX_TDM_CHAN10_EN : 1; /*!< 1: Enable the valid data input of I2S RX TDM channel 10. 0: + Disable, just input 0 in this channel. */ + __IOM uint32_t RX_TDM_CHAN11_EN : 1; /*!< 1: Enable the valid data input of I2S RX TDM channel 11. 0: + Disable, just input 0 in this channel. */ + __IOM uint32_t RX_TDM_CHAN12_EN : 1; /*!< 1: Enable the valid data input of I2S RX TDM channel 12. 0: + Disable, just input 0 in this channel. */ + __IOM uint32_t RX_TDM_CHAN13_EN : 1; /*!< 1: Enable the valid data input of I2S RX TDM channel 13. 0: + Disable, just input 0 in this channel. */ + __IOM uint32_t RX_TDM_CHAN14_EN : 1; /*!< 1: Enable the valid data input of I2S RX TDM channel 14. 0: + Disable, just input 0 in this channel. */ + __IOM uint32_t RX_TDM_CHAN15_EN : 1; /*!< 1: Enable the valid data input of I2S RX TDM channel 15. 0: + Disable, just input 0 in this channel. */ + __IOM uint32_t RX_TDM_TOT_CHAN_NUM : 4; /*!< The total channel number of I2S TX TDM mode. */ + uint32_t : 12; + } bit; + } RX_TDM_CTRL; + + union { + __IOM uint32_t reg; /*!< I2S TX TDM mode control register */ + + struct { + __IOM uint32_t TX_TDM_CHAN0_EN : 1; /*!< 1: Enable the valid data output of I2S TX TDM channel 0. 0: + Disable, just output 0 in this channel. */ + __IOM uint32_t TX_TDM_CHAN1_EN : 1; /*!< 1: Enable the valid data output of I2S TX TDM channel 1. 0: + Disable, just output 0 in this channel. */ + __IOM uint32_t TX_TDM_CHAN2_EN : 1; /*!< 1: Enable the valid data output of I2S TX TDM channel 2. 0: + Disable, just output 0 in this channel. */ + __IOM uint32_t TX_TDM_CHAN3_EN : 1; /*!< 1: Enable the valid data output of I2S TX TDM channel 3. 0: + Disable, just output 0 in this channel. */ + __IOM uint32_t TX_TDM_CHAN4_EN : 1; /*!< 1: Enable the valid data output of I2S TX TDM channel 4. 0: + Disable, just output 0 in this channel. */ + __IOM uint32_t TX_TDM_CHAN5_EN : 1; /*!< 1: Enable the valid data output of I2S TX TDM channel 5. 0: + Disable, just output 0 in this channel. */ + __IOM uint32_t TX_TDM_CHAN6_EN : 1; /*!< 1: Enable the valid data output of I2S TX TDM channel 6. 0: + Disable, just output 0 in this channel. */ + __IOM uint32_t TX_TDM_CHAN7_EN : 1; /*!< 1: Enable the valid data output of I2S TX TDM channel 7. 0: + Disable, just output 0 in this channel. */ + __IOM uint32_t TX_TDM_CHAN8_EN : 1; /*!< 1: Enable the valid data output of I2S TX TDM channel 8. 0: + Disable, just output 0 in this channel. */ + __IOM uint32_t TX_TDM_CHAN9_EN : 1; /*!< 1: Enable the valid data output of I2S TX TDM channel 9. 0: + Disable, just output 0 in this channel. */ + __IOM uint32_t TX_TDM_CHAN10_EN : 1; /*!< 1: Enable the valid data output of I2S TX TDM channel 10. 0: + Disable, just output 0 in this channel. */ + __IOM uint32_t TX_TDM_CHAN11_EN : 1; /*!< 1: Enable the valid data output of I2S TX TDM channel 11. 0: + Disable, just output 0 in this channel. */ + __IOM uint32_t TX_TDM_CHAN12_EN : 1; /*!< 1: Enable the valid data output of I2S TX TDM channel 12. 0: + Disable, just output 0 in this channel. */ + __IOM uint32_t TX_TDM_CHAN13_EN : 1; /*!< 1: Enable the valid data output of I2S TX TDM channel 13. 0: + Disable, just output 0 in this channel. */ + __IOM uint32_t TX_TDM_CHAN14_EN : 1; /*!< 1: Enable the valid data output of I2S TX TDM channel 14. 0: + Disable, just output 0 in this channel. */ + __IOM uint32_t TX_TDM_CHAN15_EN : 1; /*!< 1: Enable the valid data output of I2S TX TDM channel 15. 0: + Disable, just output 0 in this channel. */ + __IOM uint32_t TX_TDM_TOT_CHAN_NUM : 4; /*!< The total channel number of I2S TX TDM mode. */ + __IOM uint32_t TX_TDM_SKIP_MSK_EN : 1; /*!< When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + + 1) channels, and only the data of the enabled channels + is sent, then this bit should be set. Clear it when all + the data stored in DMA TX buffer is for enabled channels. */ + uint32_t : 11; + } bit; + } TX_TDM_CTRL; + + union { + __IOM uint32_t reg; /*!< I2S RX timing control register */ + + struct { + __IOM uint32_t RX_SD_IN_DM : 2; /*!< The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay + by pos edge. 2: delay by neg edge. 3: not used. */ + uint32_t : 2; + __IOM uint32_t RX_SD1_IN_DM : 2; /*!< The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay + by pos edge. 2: delay by neg edge. 3: not used. */ + uint32_t : 2; + __IOM uint32_t RX_SD2_IN_DM : 2; /*!< The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay + by pos edge. 2: delay by neg edge. 3: not used. */ + uint32_t : 2; + __IOM uint32_t RX_SD3_IN_DM : 2; /*!< The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay + by pos edge. 2: delay by neg edge. 3: not used. */ + uint32_t : 2; + __IOM uint32_t RX_WS_OUT_DM : 2; /*!< The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay + by pos edge. 2: delay by neg edge. 3: not used. */ + uint32_t : 2; + __IOM uint32_t RX_BCK_OUT_DM : 2; /*!< The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay + by pos edge. 2: delay by neg edge. 3: not used. */ + uint32_t : 2; + __IOM uint32_t RX_WS_IN_DM : 2; /*!< The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay + by pos edge. 2: delay by neg edge. 3: not used. */ + uint32_t : 2; + __IOM uint32_t RX_BCK_IN_DM : 2; /*!< The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay + by pos edge. 2: delay by neg edge. 3: not used. */ + uint32_t : 2; + } bit; + } RX_TIMING; + + union { + __IOM uint32_t reg; /*!< I2S TX timing control register */ + + struct { + __IOM uint32_t TX_SD_OUT_DM : 2; /*!< The delay mode of I2S TX SD output signal. 0: bypass. 1: delay + by pos edge. 2: delay by neg edge. 3: not used. */ + uint32_t : 2; + __IOM uint32_t TX_SD1_OUT_DM : 2; /*!< The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay + by pos edge. 2: delay by neg edge. 3: not used. */ + uint32_t : 10; + __IOM uint32_t TX_WS_OUT_DM : 2; /*!< The delay mode of I2S TX WS output signal. 0: bypass. 1: delay + by pos edge. 2: delay by neg edge. 3: not used. */ + uint32_t : 2; + __IOM uint32_t TX_BCK_OUT_DM : 2; /*!< The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay + by pos edge. 2: delay by neg edge. 3: not used. */ + uint32_t : 2; + __IOM uint32_t TX_WS_IN_DM : 2; /*!< The delay mode of I2S TX WS input signal. 0: bypass. 1: delay + by pos edge. 2: delay by neg edge. 3: not used. */ + uint32_t : 2; + __IOM uint32_t TX_BCK_IN_DM : 2; /*!< The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay + by pos edge. 2: delay by neg edge. 3: not used. */ + uint32_t : 2; + } bit; + } TX_TIMING; + + union { + __IOM uint32_t reg; /*!< I2S HUNG configure register. */ + + struct { + __IOM uint32_t LC_FIFO_TIMEOUT : 8; /*!< the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt + will be triggered when fifo hung counter is equal to this + value */ + __IOM uint32_t LC_FIFO_TIMEOUT_SHIFT : 3; /*!< The bits are used to scale tick counter threshold. The tick + counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift */ + __IOM uint32_t LC_FIFO_TIMEOUT_ENA : 1; /*!< The enable bit for FIFO timeout */ + uint32_t : 20; + } bit; + } LC_HUNG_CONF; + + union { + __IOM uint32_t reg; /*!< I2S RX data number control register. */ + + struct { + __IOM uint32_t RX_EOF_NUM : 12; /*!< The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * + (REG_RX_EOF_NUM[11:0] + 1) . It will trigger in_suc_eof + interrupt in the configured DMA RX channel. */ + uint32_t : 20; + } bit; + } RXEOF_NUM; + + union { + __IOM uint32_t reg; /*!< I2S signal data register */ + + struct { + __IOM uint32_t SINGLE_DATA : 32; /*!< The configured constant channel data to be sent out. */ + } bit; + } CONF_SIGLE_DATA; + + union { + __IOM uint32_t reg; /*!< I2S TX status register */ + + struct { + __IM uint32_t TX_IDLE : 1; /*!< 1: i2s_tx is idle state. 0: i2s_tx is working. */ + uint32_t : 31; + } bit; + } STATE; + + union { + __IOM uint32_t reg; /*!< I2S ETM configure register */ + + struct { + __IOM uint32_t ETM_TX_SEND_WORD_NUM : 10; /*!< I2S ETM send x words event. When sending word number of reg_etm_tx_send_word_n + m[9:0], i2s will trigger an etm event. */ + __IOM uint32_t ETM_RX_RECEIVE_WORD_NUM : 10;/*!< I2S ETM receive x words event. When receiving word number of + reg_etm_rx_receive_word_num[9:0], i2s will trigger an etm + event. */ + uint32_t : 12; + } bit; + } ETM_CONF; + + union { + __IOM uint32_t reg; /*!< I2S sync counter register */ + + struct { + __IM uint32_t TX_FIFO_CNT : 31; /*!< tx fifo counter value. */ + __OM uint32_t TX_FIFO_CNT_RST : 1; /*!< Set this bit to reset tx fifo counter. */ + } bit; + } FIFO_CNT; + + union { + __IOM uint32_t reg; /*!< I2S sync counter register */ + + struct { + __IM uint32_t TX_BCK_CNT : 31; /*!< tx bck counter value. */ + __OM uint32_t TX_BCK_CNT_RST : 1; /*!< Set this bit to reset tx bck counter. */ + } bit; + } BCK_CNT; + + union { + __IOM uint32_t reg; /*!< Clock gate register */ + + struct { + __IOM uint32_t CLK_EN : 1; /*!< set this bit to enable clock gate */ + uint32_t : 31; + } bit; + } CLK_GATE; + + union { + __IOM uint32_t reg; /*!< Version control register */ + + struct { + __IOM uint32_t DATE : 28; /*!< I2S version control register */ + uint32_t : 4; + } bit; + } DATE; +} I2S0_Type; /*!< Size = 132 (0x84) */ + + + +/* =========================================================================================================================== */ +/* ================ I3C_MST ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief I3C Controller (Master) (I3C_MST) + */ + +typedef struct { /*!< I3C_MST Structure */ + + union { + __IOM uint32_t reg; /*!< DEVICE_CTRL register controls the transfer properties and disposition + of controllers capabilities. */ + + struct { + uint32_t : 1; + __IOM uint32_t REG_BA_INCLUDE : 1; /*!< This bit is used to include I3C broadcast address(0x7E) for + private transfer.(If I3C broadcast address is not include + for the private transfer, In-Band Interrupts driven from + Slaves may not win address arbitration. Hence IBIs will + get delayed) */ + __IOM uint32_t REG_TRANS_START : 1; /*!< Transfer Start */ + __IOM uint32_t REG_CLK_EN : 1; /*!< NA */ + __IOM uint32_t REG_IBI_RSTART_TRANS_EN : 1;/*!< NA */ + __IOM uint32_t REG_AUTO_DIS_IBI_EN : 1; /*!< NA */ + __IOM uint32_t REG_DMA_RX_EN : 1; /*!< NA */ + __IOM uint32_t REG_DMA_TX_EN : 1; /*!< NA */ + __IOM uint32_t REG_MULTI_SLV_SINGLE_CCC_EN : 1;/*!< 0: rx high bit first, 1: rx low bit first */ + __IOM uint32_t REG_RX_BIT_ORDER : 1; /*!< 0: rx low byte fist, 1: rx high byte first */ + __IOM uint32_t REG_RX_BYTE_ORDER : 1; /*!< NA */ + __IOM uint32_t REG_SCL_PULLUP_FORCE_EN : 1;/*!< This bit is used to force scl_pullup_en */ + __IOM uint32_t REG_SCL_OE_FORCE_EN : 1; /*!< This bit is used to force scl_oe */ + __IOM uint32_t REG_SDA_PP_RD_PULLUP_EN : 1;/*!< NA */ + __IOM uint32_t REG_SDA_RD_TBIT_HLVL_PULLUP_EN : 1;/*!< NA */ + __IOM uint32_t REG_SDA_PP_WR_PULLUP_EN : 1;/*!< NA */ + __IOM uint32_t REG_DATA_BYTE_CNT_UNLATCH : 1;/*!< 1: read current real-time updated value 0: read latch data byte + cnt value */ + __IOM uint32_t REG_MEM_CLK_FORCE_ON : 1; /*!< 1: dev characteristic and address table memory clk date force + on . 0 : clock gating by rd/wr. */ + uint32_t : 14; + } bit; + } DEVICE_CTRL; + __IM uint32_t RESERVED[6]; + + union { + __IOM uint32_t reg; /*!< In-Band Interrupt Status Threshold Value . Every In Band Interrupt + received by I3C controller generates an IBI status. This + field controls the number of IBI status entries in the + IBI buffer that trigger the IBI_STATUS_THLD_STAT interrupt. */ + + struct { + __IOM uint32_t REG_CMD_BUF_EMPTY_THLD : 4;/*!< Command Buffer Empty Threshold Value is used to control the + number of empty locations(or greater) in the Command Buffer + that trigger CMD_BUFFER_READY_STAT interrupt. */ + uint32_t : 2; + __IOM uint32_t REG_RESP_BUF_THLD : 3; /*!< Response Buffer Threshold Value is used to control the number + of entries in the Response Buffer that trigger the RESP_READY_STAT_INTR. */ + uint32_t : 3; + __IOM uint32_t REG_IBI_DATA_BUF_THLD : 3; /*!< In-Band Interrupt Data Threshold Value . Every In Band Interrupt + received by I3C controller generates an IBI status. This + field controls the number of IBI data entries in the IBI + buffer that trigger the IBI_DATA_THLD_STAT interrupt. */ + uint32_t : 3; + __IOM uint32_t REG_IBI_STATUS_BUF_THLD : 3;/*!< NA */ + uint32_t : 11; + } bit; + } BUFFER_THLD_CTRL; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_TX_DATA_BUF_THLD : 3; /*!< Transmit Buffer Threshold Value. This field controls the number + of empty locations in the Transmit FIFO that trigger the + TX_THLD_STAT interrupt. Supports values: 000:2 001:4 010:8 + 011:16 100:31, else:31 */ + __IOM uint32_t REG_RX_DATA_BUF_THLD : 3; /*!< Receive Buffer Threshold Value. This field controls the number + of empty locations in the Receive FIFO that trigger the + RX_THLD_STAT interrupt. Supports: 000:2 001:4 010:8 011:16 + 100:31, else:31 */ + uint32_t : 26; + } bit; + } DATA_BUFFER_THLD_CTRL; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + uint32_t : 2; + __IOM uint32_t REG_NOTIFY_SIR_REJECTED : 1;/*!< Notify Rejected Slave Interrupt Request Control. This bit is + used to suppress reporting to the application about Slave + Interrupt Request. 0:Suppress passing the IBI Status to + the IBI FIFO(hence not notifying the application) when + a SIR request is NACKed and auto-disabled base on the IBI_SIR_REQ_REJECT + register. 1: Writes IBI Status to the IBI FIFO(hence notifying + the application) when SIR request is NACKed and auto-disabled + based on the IBI_SIR_REQ_REJECT registerl. */ + uint32_t : 29; + } bit; + } IBI_NOTIFY_CTRL; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_SIR_REQ_PAYLOAD : 32; /*!< NA */ + } bit; + } IBI_SIR_REQ_PAYLOAD; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_SIR_REQ_REJECT : 32; /*!< The application of controller can decide whether to send ACK + or NACK for Slave request received from any I3C device. + A device specific response control bit is provided to select + the response option, Master will ACK/NACK the Master Request + based on programming of control bit, corresponding to the + interrupting device. 0:ACK the SIR Request 1:NACK and send + direct auto disable CCC */ + } bit; + } IBI_SIR_REQ_REJECT; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __OM uint32_t TX_DATA_BUF_THLD_INT_CLR : 1;/*!< NA */ + __OM uint32_t RX_DATA_BUF_THLD_INT_CLR : 1;/*!< NA */ + __OM uint32_t IBI_STATUS_THLD_INT_CLR : 1;/*!< NA */ + __OM uint32_t CMD_BUF_EMPTY_THLD_INT_CLR : 1;/*!< NA */ + __OM uint32_t RESP_READY_INT_CLR : 1; /*!< NA */ + __OM uint32_t NXT_CMD_REQ_ERR_INT_CLR : 1;/*!< NA */ + __OM uint32_t TRANSFER_ERR_INT_CLR : 1; /*!< NA */ + __OM uint32_t TRANSFER_COMPLETE_INT_CLR : 1;/*!< NA */ + __OM uint32_t COMMAND_DONE_INT_CLR : 1; /*!< NA */ + __OM uint32_t DETECT_START_INT_CLR : 1; /*!< NA */ + __OM uint32_t RESP_BUF_OVF_INT_CLR : 1; /*!< NA */ + __OM uint32_t IBI_DATA_BUF_OVF_INT_CLR : 1;/*!< NA */ + __OM uint32_t IBI_STATUS_BUF_OVF_INT_CLR : 1;/*!< NA */ + __OM uint32_t IBI_HANDLE_DONE_INT_CLR : 1;/*!< NA */ + __OM uint32_t IBI_DETECT_INT_CLR : 1; /*!< NA */ + __OM uint32_t CMD_CCC_MISMATCH_INT_CLR : 1;/*!< NA */ + uint32_t : 16; + } bit; + } INT_CLR; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t TX_DATA_BUF_THLD_INT_RAW : 1;/*!< NA */ + __IOM uint32_t RX_DATA_BUF_THLD_INT_RAW : 1;/*!< NA */ + __IOM uint32_t IBI_STATUS_THLD_INT_RAW : 1;/*!< NA */ + __IOM uint32_t CMD_BUF_EMPTY_THLD_INT_RAW : 1;/*!< NA */ + __IOM uint32_t RESP_READY_INT_RAW : 1; /*!< NA */ + __IOM uint32_t NXT_CMD_REQ_ERR_INT_RAW : 1;/*!< NA */ + __IOM uint32_t TRANSFER_ERR_INT_RAW : 1; /*!< NA */ + __IOM uint32_t TRANSFER_COMPLETE_INT_RAW : 1;/*!< NA */ + __IOM uint32_t COMMAND_DONE_INT_RAW : 1; /*!< NA */ + __IOM uint32_t DETECT_START_INT_RAW : 1; /*!< NA */ + __IOM uint32_t RESP_BUF_OVF_INT_RAW : 1; /*!< NA */ + __IOM uint32_t IBI_DATA_BUF_OVF_INT_RAW : 1;/*!< NA */ + __IOM uint32_t IBI_STATUS_BUF_OVF_INT_RAW : 1;/*!< NA */ + __IOM uint32_t IBI_HANDLE_DONE_INT_RAW : 1;/*!< NA */ + __IOM uint32_t IBI_DETECT_INT_RAW : 1; /*!< NA */ + __IOM uint32_t CMD_CCC_MISMATCH_INT_RAW : 1;/*!< NA */ + uint32_t : 16; + } bit; + } INT_RAW; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t TX_DATA_BUF_THLD_INT_ST : 1;/*!< This interrupt is generated when number of empty locations in + transmit buffer is greater than or equal to threshold value + specified by TX_EMPTY_BUS_THLD field in DATA_BUFFER_THLD_CTRL + register. This interrupt will be cleared automatically + when number of empty locations in transmit buffer is less + than threshold value. */ + __IM uint32_t RX_DATA_BUF_THLD_INT_ST : 1;/*!< This interrupt is generated when number of entries in receive + buffer is greater than or equal to threshold value specified + by RX_BUF_THLD field in DATA_BUFFER_THLD_CTRL register. + This interrupt will be cleared automatically when number + of entries in receive buffer is less than threshold value. */ + __IM uint32_t IBI_STATUS_THLD_INT_ST : 1;/*!< Only used in master mode. This interrupt is generated when number + of entries in IBI buffer is greater than or equal to threshold + value specified by IBI_BUF_THLD field in BUFFER_THLD_CTRL + register. This interrupt will be cleared automatically + when number of entries in IBI buffer is less than threshold + value. */ + __IM uint32_t CMD_BUF_EMPTY_THLD_INT_ST : 1;/*!< This interrupt is generated when number of empty locations in + command buffer is greater than or equal to threshold value + specified by CMD_EMPTY_BUF_THLD field in BUFFER_THLD_CTRL + register. This interrupt will be cleared automatically + when number of empty locations in command buffer is less + than threshold value. */ + __IM uint32_t RESP_READY_INT_ST : 1; /*!< This interrupt is generated when number of entries in response + buffer is greater than or equal to threshold value specified + by RESP_BUF_THLD field in BUFFER_THLD_CTRL register. This + interrupt will be cleared automatically when number of + entries in response buffer is less than threshold value. */ + __IM uint32_t NXT_CMD_REQ_ERR_INT_ST : 1;/*!< This interrupt is generated if toc is 0(master will restart + next command), but command buf is empty. */ + __IM uint32_t TRANSFER_ERR_INT_ST : 1; /*!< This interrupt is generated if any error occurs during transfer. + The error type will be specified in the response packet + associated with the command (in ERR_STATUS field of RESPONSE_BUFFER_PORT + register). This bit can be cleared by writing 1'h1. */ + __IM uint32_t TRANSFER_COMPLETE_INT_ST : 1;/*!< NA */ + __IM uint32_t COMMAND_DONE_INT_ST : 1; /*!< NA */ + __IM uint32_t DETECT_START_INT_ST : 1; /*!< NA */ + __IM uint32_t RESP_BUF_OVF_INT_ST : 1; /*!< NA */ + __IM uint32_t IBI_DATA_BUF_OVF_INT_ST : 1;/*!< NA */ + __IM uint32_t IBI_STATUS_BUF_OVF_INT_ST : 1;/*!< NA */ + __IM uint32_t IBI_HANDLE_DONE_INT_ST : 1;/*!< NA */ + __IM uint32_t IBI_DETECT_INT_ST : 1; /*!< NA */ + __IM uint32_t CMD_CCC_MISMATCH_INT_ST : 1;/*!< NA */ + uint32_t : 16; + } bit; + } INT_ST; + + union { + __IOM uint32_t reg; /*!< The Interrupt status will be updated in INTR_STATUS register + if corresponding Status Enable bit set. */ + + struct { + __IOM uint32_t TX_DATA_BUF_THLD_INT_ENA : 1;/*!< Transmit Buffer threshold status enable. */ + __IOM uint32_t RX_DATA_BUF_THLD_INT_ENA : 1;/*!< Receive Buffer threshold status enable. */ + __IOM uint32_t IBI_STATUS_THLD_INT_ENA : 1;/*!< Only used in master mode. IBI Buffer threshold status enable. */ + __IOM uint32_t CMD_BUF_EMPTY_THLD_INT_ENA : 1;/*!< Command buffer ready status enable. */ + __IOM uint32_t RESP_READY_INT_ENA : 1; /*!< Response buffer ready status enable. */ + __IOM uint32_t NXT_CMD_REQ_ERR_INT_ENA : 1;/*!< next command request error status enable */ + __IOM uint32_t TRANSFER_ERR_INT_ENA : 1; /*!< Transfer error status enable */ + __IOM uint32_t TRANSFER_COMPLETE_INT_ENA : 1;/*!< NA */ + __IOM uint32_t COMMAND_DONE_INT_ENA : 1; /*!< NA */ + __IOM uint32_t DETECT_START_INT_ENA : 1; /*!< NA */ + __IOM uint32_t RESP_BUF_OVF_INT_ENA : 1; /*!< NA */ + __IOM uint32_t IBI_DATA_BUF_OVF_INT_ENA : 1;/*!< NA */ + __IOM uint32_t IBI_STATUS_BUF_OVF_INT_ENA : 1;/*!< NA */ + __IOM uint32_t IBI_HANDLE_DONE_INT_ENA : 1;/*!< NA */ + __IOM uint32_t IBI_DETECT_INT_ENA : 1; /*!< NA */ + __IOM uint32_t CMD_CCC_MISMATCH_INT_ENA : 1;/*!< NA */ + uint32_t : 16; + } bit; + } INT_ST_ENA; + __IM uint32_t RESERVED1; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __OM uint32_t REG_CORE_SOFT_RST : 1; /*!< NA */ + __IOM uint32_t REG_CMD_BUF_RST : 1; /*!< NA */ + __IOM uint32_t REG_RESP_BUF_RST : 1; /*!< NA */ + __IOM uint32_t REG_TX_DATA_BUF_BUF_RST : 1;/*!< NA */ + __IOM uint32_t REG_RX_DATA_BUF_RST : 1; /*!< NA */ + __IOM uint32_t REG_IBI_DATA_BUF_RST : 1; /*!< NA */ + __IOM uint32_t REG_IBI_STATUS_BUF_RST : 1;/*!< NA */ + uint32_t : 25; + } bit; + } RESET_CTRL; + + union { + __IOM uint32_t reg; /*!< BUFFER_STATUS_LEVEL reflects the status level of Buffers in + the controller. */ + + struct { + __IM uint32_t CMD_BUF_EMPTY_CNT : 5; /*!< Command Buffer Empty Locations contains the number of empty + locations in the command buffer. */ + uint32_t : 3; + __IM uint32_t RESP_BUF_CNT : 4; /*!< Response Buffer Level Value contains the number of valid data + entries in the response buffer. */ + uint32_t : 4; + __IM uint32_t IBI_DATA_BUF_CNT : 4; /*!< IBI Buffer Level Value contains the number of valid entries + in the IBI Buffer. This is field is used in master mode. */ + uint32_t : 4; + __IM uint32_t IBI_STATUS_BUF_CNT : 4; /*!< IBI Buffer Status Count contains the number of IBI status entries + in the IBI Buffer. This field is used in master mode. */ + uint32_t : 4; + } bit; + } BUFFER_STATUS_LEVEL; + + union { + __IOM uint32_t reg; /*!< DATA_BUFFER_STATUS_LEVEL reflects the status level of the Buffers + in the controller. */ + + struct { + __IM uint32_t TX_DATA_BUF_EMPTY_CNT : 6; /*!< Transmit Buffer Empty Level Value contains the number of empty + locations in the transmit Buffer. */ + uint32_t : 10; + __IM uint32_t RX_DATA_BUF_CNT : 6; /*!< Receive Buffer Level value contains the number of valid data + entries in the receive buffer. */ + uint32_t : 10; + } bit; + } DATA_BUFFER_STATUS_LEVEL; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t SDA_LVL : 1; /*!< This bit is used to check the SCL line level to recover from + error and for debugging. This bit reflects the value of + synchronized scl_in_a. */ + __IM uint32_t SCL_LVL : 1; /*!< This bit is used to check the SDA line level to recover from + error and for debugging. This bit reflects the value of + synchronized sda_in_a. */ + __IM uint32_t BUS_BUSY : 1; /*!< NA */ + __IM uint32_t BUS_FREE : 1; /*!< NA */ + uint32_t : 5; + __IM uint32_t CMD_TID : 4; /*!< NA */ + __IM uint32_t SCL_GEN_FSM_STATE : 3; /*!< NA */ + __IM uint32_t IBI_EV_HANDLE_FSM_STATE : 3;/*!< NA */ + __IM uint32_t I2C_MODE_FSM_STATE : 3; /*!< NA */ + __IM uint32_t SDR_MODE_FSM_STATE : 4; /*!< NA */ + __IM uint32_t DAA_MODE_FSM_STATE : 3; /*!< Reflects whether the Master Controller is in IDLE or not. This + bit will be set when all the buffer(Command, Response, + IBI, Transmit, Receive) are empty along with the Master + State machine is in idle state. 0X0: not in idle 0x1: in + idle */ + __IM uint32_t MAIN_FSM_STATE : 3; /*!< NA */ + } bit; + } PRESENT_STATE0; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t DATA_BYTE_CNT : 16; /*!< Present transfer data byte cnt: tx data byte cnt if write rx + data byte cnt if read ibi data byte cnt if IBI handle. */ + uint32_t : 16; + } bit; + } PRESENT_STATE1; + + union { + __IOM uint32_t reg; /*!< Pointer for Device Address Table */ + + struct { + __IOM uint32_t REG_DCT_DAA_INIT_INDEX : 4;/*!< Reserved */ + __IOM uint32_t REG_DAT_DAA_INIT_INDEX : 4;/*!< NA */ + __IM uint32_t PRESENT_DCT_INDEX : 4; /*!< NA */ + __IM uint32_t PRESENT_DAT_INDEX : 4; /*!< NA */ + uint32_t : 16; + } bit; + } DEVICE_TABLE; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_RESP_BUF_TO_VALUE : 5; /*!< NA */ + __IOM uint32_t REG_RESP_BUF_TO_EN : 1; /*!< NA */ + __IOM uint32_t REG_IBI_DATA_BUF_TO_VALUE : 5;/*!< NA */ + __IOM uint32_t REG_IBI_DATA_BUF_TO_EN : 1;/*!< NA */ + __IOM uint32_t REG_IBI_STATUS_BUF_TO_VALUE : 5;/*!< NA */ + __IOM uint32_t REG_IBI_STATUS_BUF_TO_EN : 1;/*!< NA */ + __IOM uint32_t REG_RX_DATA_BUF_TO_VALUE : 5;/*!< NA */ + __IOM uint32_t REG_RX_DATA_BUF_TO_EN : 1; /*!< NA */ + uint32_t : 8; + } bit; + } TIME_OUT_VALUE; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_I3C_MST_OD_LOW_PERIOD : 16;/*!< SCL Open-Drain low count for I3C transfers targeted to I3C devices. */ + __IOM uint32_t REG_I3C_MST_OD_HIGH_PERIOD : 16;/*!< SCL Open-Drain High count for I3C transfers targeted to I3C + devices. */ + } bit; + } SCL_I3C_MST_OD_TIME; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_I3C_MST_PP_LOW_PERIOD : 8;/*!< NA */ + uint32_t : 8; + __IOM uint32_t REG_I3C_MST_PP_HIGH_PERIOD : 8;/*!< NA */ + uint32_t : 8; + } bit; + } SCL_I3C_MST_PP_TIME; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_I2C_FM_LOW_PERIOD : 16;/*!< NA */ + __IOM uint32_t REG_I2C_FM_HIGH_PERIOD : 16;/*!< The SCL open-drain low count timing for I2C Fast Mode transfers. */ + } bit; + } SCL_I2C_FM_TIME; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_I2C_FMP_LOW_PERIOD : 16;/*!< NA */ + __IOM uint32_t REG_I2C_FMP_HIGH_PERIOD : 8;/*!< NA */ + uint32_t : 8; + } bit; + } SCL_I2C_FMP_TIME; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_I3C_MST_EXT_LOW_PERIOD1 : 8;/*!< NA */ + __IOM uint32_t REG_I3C_MST_EXT_LOW_PERIOD2 : 8;/*!< NA */ + __IOM uint32_t REG_I3C_MST_EXT_LOW_PERIOD3 : 8;/*!< NA */ + __IOM uint32_t REG_I3C_MST_EXT_LOW_PERIOD4 : 8;/*!< NA */ + } bit; + } SCL_EXT_LOW_TIME; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_SDA_OD_SAMPLE_TIME : 9;/*!< It is used to adjust sda sample point when scl high under open + drain speed */ + __IOM uint32_t REG_SDA_PP_SAMPLE_TIME : 5;/*!< It is used to adjust sda sample point when scl high under push + pull speed */ + uint32_t : 18; + } bit; + } SDA_SAMPLE_TIME; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_SDA_OD_TX_HOLD_TIME : 9;/*!< It is used to adjust sda drive point after scl neg under open + drain speed */ + __IOM uint32_t REG_SDA_PP_TX_HOLD_TIME : 5;/*!< It is used to adjust sda dirve point after scl neg under push + pull speed */ + uint32_t : 18; + } bit; + } SDA_HOLD_TIME; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_SCL_START_HOLD_TIME : 9;/*!< I2C_SCL_START_HOLD_TIME */ + __IOM uint32_t REG_START_DET_HOLD_TIME : 2;/*!< NA */ + uint32_t : 21; + } bit; + } SCL_START_HOLD; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_SCL_RSTART_SETUP_TIME : 9;/*!< I2C_SCL_RSTART_SETUP_TIME */ + uint32_t : 23; + } bit; + } SCL_RSTART_SETUP; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_SCL_STOP_HOLD_TIME : 9;/*!< I2C_SCL_STOP_HOLD_TIME */ + uint32_t : 23; + } bit; + } SCL_STOP_HOLD; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_SCL_STOP_SETUP_TIME : 9;/*!< I2C_SCL_STOP_SETUP_TIME */ + uint32_t : 23; + } bit; + } SCL_STOP_SETUP; + __IM uint32_t RESERVED2; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_BUS_FREE_TIME : 16; /*!< I3C Bus Free Count Value. This field is used only in Master + mode. In pure Bus System, this field represents tCAS. In + Mixed Bus System, this field is expected to be programmed + to tLOW of I2C Timing. */ + uint32_t : 16; + } bit; + } BUS_FREE_TIME; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_I3C_MST_TERMN_T_EXT_LOW_TIME : 8;/*!< NA */ + uint32_t : 24; + } bit; + } SCL_TERMN_T_EXT_LOW_TIME; + __IM uint32_t RESERVED3[2]; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_I3C_MST_VER_ID : 32; /*!< This field indicates the controller current release number that + is read by an application. */ + } bit; + } VER_ID; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_I3C_MST_VER_TYPE : 32; /*!< This field indicates the controller current release type that + is read by an application. */ + } bit; + } VER_TYPE; + __IM uint32_t RESERVED4; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_I3C_MST_FPGA_DEBUG_PROBE : 32;/*!< For Debug Probe Test on FPGA */ + } bit; + } FPGA_DEBUG_PROBE; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_RND_ECO_EN : 1; /*!< NA */ + __IM uint32_t RND_ECO_RESULT : 1; /*!< NA */ + uint32_t : 30; + } bit; + } RND_ECO_CS; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_RND_ECO_LOW : 32; /*!< NA */ + } bit; + } RND_ECO_LOW; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_RND_ECO_HIGH : 32; /*!< NA */ + } bit; + } RND_ECO_HIGH; +} I3C_MST_Type; /*!< Size = 188 (0xbc) */ + + + +/* =========================================================================================================================== */ +/* ================ I3C_MST_MEM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief I3C_MST_MEM Peripheral (I3C_MST_MEM) + */ + +typedef struct { /*!< I3C_MST_MEM Structure */ + __IM uint32_t RESERVED[2]; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_COMMAND : 32; /*!< Contains a Command Descriptor structure that depends on the + requested transfer type. Command Descriptor structure is + used to schedule the transfers to devices on I3C bus. */ + } bit; + } COMMAND_BUF_PORT; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t RESPONSE : 32; /*!< The Response Buffer can be read through this register. The response + status for each Command is written into the Response Buffer + by the controller if ROC (Response On Completion) bit is + set or if transfer error has occurred. The response buffer + can be read through this register. */ + } bit; + } RESPONSE_BUF_PORT; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t RX_DATA_PORT : 32; /*!< Receive Data Port. Receive data is mapped to the Rx-data buffer + and receive data is always packed in 4-byte aligned data + words. If the length of data transfer is not aligned to + 4-bytes boundary, then there will be extra(unused) bytes(the + additional data bytes have to be ignored) at the end of + the transferred data. The valid data must be identified + using the DATA_LENGTH filed in the Response Descriptor. */ + } bit; + } RX_DATA_PORT; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_TX_DATA_PORT : 32; /*!< Transmit Data Port. Transmit data is mapped to the Tx-data buffer + and transmit data is always packed in 4-byte aligned data + words. If the length of data transfer is not aligned to + 4-bytes boundary, then there will be extra(unused) bytes(the + additional data bytes have to be ignored) at the end of + the transferred data. The valid data must be identified + using the DATA_LENGTH filed in the Response Descriptor. */ + } bit; + } TX_DATA_PORT; + + union { + __IOM uint32_t reg; /*!< In-Band Interrupt Buffer Status/Data Register. When receiving + an IBI, IBI_PORT is used to both: Read the IBI Status Read + the IBI Data(which is raw/opaque data) */ + + struct { + __IM uint32_t DATA_LENGTH : 8; /*!< This field represents the length of data received along with + IBI, in bytes. */ + __IM uint32_t IBI_ID : 8; /*!< IBI Identifier. The byte received after START which includes + the address the R/W bit: Device address and R/W bit in + case of Slave Interrupt or Master Request. */ + uint32_t : 12; + __IM uint32_t IBI_STS : 1; /*!< IBI received data/status. IBI Data register is mapped to the + IBI Buffer. The IBI Data is always packed in4-byte aligned + and put to the IBI Buffer. This register When read from, + reads the data from the IBI buffer. IBI Status register + when read from, returns the data from the IBI Buffer and + indicates how the controller responded to incoming IBI(SIR, + MR and HJ). */ + uint32_t : 3; + } bit; + } IBI_STATUS_BUF; + __IM uint32_t RESERVED1[9]; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t IBI_DATA : 32; /*!< NA */ + } bit; + } IBI_DATA_BUF; + __IM uint32_t RESERVED2[31]; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_DAT_DEV1_STATIC_ADDR : 7;/*!< NA */ + uint32_t : 9; + __IOM uint32_t REG_DAT_DEV1_DYNAMIC_ADDR : 8;/*!< Device Dynamic Address with parity, The MSB,bit[23], should + be programmed with parity of dynamic address. */ + uint32_t : 5; + __IOM uint32_t REG_DAT_DEV1_NACK_RETRY_CNT : 2;/*!< This field is used to set the Device NACK Retry count for the + particular device. If the Device NACK's for the device + address, the controller automatically retries the same + device until this count expires. If the Slave does not + ACK for the mentioned number of retries, then controller + generates an error response and move to the Halt state. */ + __IOM uint32_t REG_DAT_DEV1_I2C : 1; /*!< Legacy I2C device or not. This bit should be set to 1 if the + device is a legacy I2C device. */ + } bit; + } DEV_ADDR_TABLE1_LOC; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_DAT_DEV2_STATIC_ADDR : 7;/*!< NA */ + uint32_t : 9; + __IOM uint32_t REG_DAT_DEV2_DYNAMIC_ADDR : 8;/*!< Device Dynamic Address with parity, The MSB,bit[23], should + be programmed with parity of dynamic address. */ + uint32_t : 5; + __IOM uint32_t REG_DAT_DEV2_NACK_RETRY_CNT : 2;/*!< This field is used to set the Device NACK Retry count for the + particular device. If the Device NACK's for the device + address, the controller automatically retries the same + device until this count expires. If the Slave does not + ACK for the mentioned number of retries, then controller + generates an error response and move to the Halt state. */ + __IOM uint32_t REG_DAT_DEV2_I2C : 1; /*!< Legacy I2C device or not. This bit should be set to 1 if the + device is a legacy I2C device. */ + } bit; + } DEV_ADDR_TABLE2_LOC; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_DAT_DEV3_STATIC_ADDR : 7;/*!< NA */ + uint32_t : 9; + __IOM uint32_t REG_DAT_DEV3_DYNAMIC_ADDR : 8;/*!< Device Dynamic Address with parity, The MSB,bit[23], should + be programmed with parity of dynamic address. */ + uint32_t : 5; + __IOM uint32_t REG_DAT_DEV3_NACK_RETRY_CNT : 2;/*!< This field is used to set the Device NACK Retry count for the + particular device. If the Device NACK's for the device + address, the controller automatically retries the same + device until this count expires. If the Slave does not + ACK for the mentioned number of retries, then controller + generates an error response and move to the Halt state. */ + __IOM uint32_t REG_DAT_DEV3_I2C : 1; /*!< Legacy I2C device or not. This bit should be set to 1 if the + device is a legacy I2C device. */ + } bit; + } DEV_ADDR_TABLE3_LOC; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_DAT_DEV4_STATIC_ADDR : 7;/*!< NA */ + uint32_t : 9; + __IOM uint32_t REG_DAT_DEV4_DYNAMIC_ADDR : 8;/*!< Device Dynamic Address with parity, The MSB,bit[23], should + be programmed with parity of dynamic address. */ + uint32_t : 5; + __IOM uint32_t REG_DAT_DEV4_NACK_RETRY_CNT : 2;/*!< This field is used to set the Device NACK Retry count for the + particular device. If the Device NACK's for the device + address, the controller automatically retries the same + device until this count expires. If the Slave does not + ACK for the mentioned number of retries, then controller + generates an error response and move to the Halt state. */ + __IOM uint32_t REG_DAT_DEV4_I2C : 1; /*!< Legacy I2C device or not. This bit should be set to 1 if the + device is a legacy I2C device. */ + } bit; + } DEV_ADDR_TABLE4_LOC; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_DAT_DEV5_STATIC_ADDR : 7;/*!< NA */ + uint32_t : 9; + __IOM uint32_t REG_DAT_DEV5_DYNAMIC_ADDR : 8;/*!< Device Dynamic Address with parity, The MSB,bit[23], should + be programmed with parity of dynamic address. */ + uint32_t : 5; + __IOM uint32_t REG_DAT_DEV5_NACK_RETRY_CNT : 2;/*!< This field is used to set the Device NACK Retry count for the + particular device. If the Device NACK's for the device + address, the controller automatically retries the same + device until this count expires. If the Slave does not + ACK for the mentioned number of retries, then controller + generates an error response and move to the Halt state. */ + __IOM uint32_t REG_DAT_DEV5_I2C : 1; /*!< Legacy I2C device or not. This bit should be set to 1 if the + device is a legacy I2C device. */ + } bit; + } DEV_ADDR_TABLE5_LOC; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_DAT_DEV6_STATIC_ADDR : 7;/*!< NA */ + uint32_t : 9; + __IOM uint32_t REG_DAT_DEV6_DYNAMIC_ADDR : 8;/*!< Device Dynamic Address with parity, The MSB,bit[23], should + be programmed with parity of dynamic address. */ + uint32_t : 5; + __IOM uint32_t REG_DAT_DEV6_NACK_RETRY_CNT : 2;/*!< This field is used to set the Device NACK Retry count for the + particular device. If the Device NACK's for the device + address, the controller automatically retries the same + device until this count expires. If the Slave does not + ACK for the mentioned number of retries, then controller + generates an error response and move to the Halt state. */ + __IOM uint32_t REG_DAT_DEV6_I2C : 1; /*!< Legacy I2C device or not. This bit should be set to 1 if the + device is a legacy I2C device. */ + } bit; + } DEV_ADDR_TABLE6_LOC; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_DAT_DEV7_STATIC_ADDR : 7;/*!< NA */ + uint32_t : 9; + __IOM uint32_t REG_DAT_DEV7_DYNAMIC_ADDR : 8;/*!< Device Dynamic Address with parity, The MSB,bit[23], should + be programmed with parity of dynamic address. */ + uint32_t : 5; + __IOM uint32_t REG_DAT_DEV7_NACK_RETRY_CNT : 2;/*!< This field is used to set the Device NACK Retry count for the + particular device. If the Device NACK's for the device + address, the controller automatically retries the same + device until this count expires. If the Slave does not + ACK for the mentioned number of retries, then controller + generates an error response and move to the Halt state. */ + __IOM uint32_t REG_DAT_DEV7_I2C : 1; /*!< Legacy I2C device or not. This bit should be set to 1 if the + device is a legacy I2C device. */ + } bit; + } DEV_ADDR_TABLE7_LOC; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_DAT_DEV8_STATIC_ADDR : 7;/*!< NA */ + uint32_t : 9; + __IOM uint32_t REG_DAT_DEV8_DYNAMIC_ADDR : 8;/*!< Device Dynamic Address with parity, The MSB,bit[23], should + be programmed with parity of dynamic address. */ + uint32_t : 5; + __IOM uint32_t REG_DAT_DEV8_NACK_RETRY_CNT : 2;/*!< This field is used to set the Device NACK Retry count for the + particular device. If the Device NACK's for the device + address, the controller automatically retries the same + device until this count expires. If the Slave does not + ACK for the mentioned number of retries, then controller + generates an error response and move to the Halt state. */ + __IOM uint32_t REG_DAT_DEV8_I2C : 1; /*!< Legacy I2C device or not. This bit should be set to 1 if the + device is a legacy I2C device. */ + } bit; + } DEV_ADDR_TABLE8_LOC; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_DAT_DEV9_STATIC_ADDR : 7;/*!< NA */ + uint32_t : 9; + __IOM uint32_t REG_DAT_DEV9_DYNAMIC_ADDR : 8;/*!< Device Dynamic Address with parity, The MSB,bit[23], should + be programmed with parity of dynamic address. */ + uint32_t : 5; + __IOM uint32_t REG_DAT_DEV9_NACK_RETRY_CNT : 2;/*!< This field is used to set the Device NACK Retry count for the + particular device. If the Device NACK's for the device + address, the controller automatically retries the same + device until this count expires. If the Slave does not + ACK for the mentioned number of retries, then controller + generates an error response and move to the Halt state. */ + __IOM uint32_t REG_DAT_DEV9_I2C : 1; /*!< Legacy I2C device or not. This bit should be set to 1 if the + device is a legacy I2C device. */ + } bit; + } DEV_ADDR_TABLE9_LOC; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_DAT_DEV10_STATIC_ADDR : 7;/*!< NA */ + uint32_t : 9; + __IOM uint32_t REG_DAT_DEV10_DYNAMIC_ADDR : 8;/*!< Device Dynamic Address with parity, The MSB,bit[23], should + be programmed with parity of dynamic address. */ + uint32_t : 5; + __IOM uint32_t REG_DAT_DEV10_NACK_RETRY_CNT : 2;/*!< This field is used to set the Device NACK Retry count for the + particular device. If the Device NACK's for the device + address, the controller automatically retries the same + device until this count expires. If the Slave does not + ACK for the mentioned number of retries, then controller + generates an error response and move to the Halt state. */ + __IOM uint32_t REG_DAT_DEV10_I2C : 1; /*!< Legacy I2C device or not. This bit should be set to 1 if the + device is a legacy I2C device. */ + } bit; + } DEV_ADDR_TABLE10_LOC; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_DAT_DEV11_STATIC_ADDR : 7;/*!< NA */ + uint32_t : 9; + __IOM uint32_t REG_DAT_DEV11_DYNAMIC_ADDR : 8;/*!< Device Dynamic Address with parity, The MSB,bit[23], should + be programmed with parity of dynamic address. */ + uint32_t : 5; + __IOM uint32_t REG_DAT_DEV11_NACK_RETRY_CNT : 2;/*!< This field is used to set the Device NACK Retry count for the + particular device. If the Device NACK's for the device + address, the controller automatically retries the same + device until this count expires. If the Slave does not + ACK for the mentioned number of retries, then controller + generates an error response and move to the Halt state. */ + __IOM uint32_t REG_DAT_DEV11_I2C : 1; /*!< Legacy I2C device or not. This bit should be set to 1 if the + device is a legacy I2C device. */ + } bit; + } DEV_ADDR_TABLE11_LOC; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t REG_DAT_DEV12_STATIC_ADDR : 7;/*!< NA */ + uint32_t : 9; + __IOM uint32_t REG_DAT_DEV12_DYNAMIC_ADDR : 8;/*!< Device Dynamic Address with parity, The MSB,bit[23], should + be programmed with parity of dynamic address. */ + uint32_t : 5; + __IOM uint32_t REG_DAT_DEV12_NACK_RETRY_CNT : 2;/*!< This field is used to set the Device NACK Retry count for the + particular device. If the Device NACK's for the device + address, the controller automatically retries the same + device until this count expires. If the Slave does not + ACK for the mentioned number of retries, then controller + generates an error response and move to the Halt state. */ + __IOM uint32_t REG_DAT_DEV12_I2C : 1; /*!< Legacy I2C device or not. This bit should be set to 1 if the + device is a legacy I2C device. */ + } bit; + } DEV_ADDR_TABLE12_LOC; + __IM uint32_t RESERVED3[4]; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t DCT_DEV1_LOC1 : 32; /*!< NA */ + } bit; + } DEV_CHAR_TABLE1_LOC1; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t DCT_DEV1_LOC2 : 32; /*!< NA */ + } bit; + } DEV_CHAR_TABLE1_LOC2; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t DCT_DEV1_LOC3 : 32; /*!< NA */ + } bit; + } DEV_CHAR_TABLE1_LOC3; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t DCT_DEV1_LOC4 : 32; /*!< NA */ + } bit; + } DEV_CHAR_TABLE1_LOC4; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t DCT_DEV2_LOC1 : 32; /*!< NA */ + } bit; + } DEV_CHAR_TABLE2_LOC1; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t DCT_DEV2_LOC2 : 32; /*!< NA */ + } bit; + } DEV_CHAR_TABLE2_LOC2; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t DCT_DEV2_LOC3 : 32; /*!< NA */ + } bit; + } DEV_CHAR_TABLE2_LOC3; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t DCT_DEV2_LOC4 : 32; /*!< NA */ + } bit; + } DEV_CHAR_TABLE2_LOC4; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t DCT_DEV3_LOC1 : 32; /*!< NA */ + } bit; + } DEV_CHAR_TABLE3_LOC1; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t DCT_DEV3_LOC2 : 32; /*!< NA */ + } bit; + } DEV_CHAR_TABLE3_LOC2; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t DCT_DEV3_LOC3 : 32; /*!< NA */ + } bit; + } DEV_CHAR_TABLE3_LOC3; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t DCT_DEV3_LOC4 : 32; /*!< NA */ + } bit; + } DEV_CHAR_TABLE3_LOC4; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t DCT_DEV4_LOC1 : 32; /*!< NA */ + } bit; + } DEV_CHAR_TABLE4_LOC1; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t DCT_DEV4_LOC2 : 32; /*!< NA */ + } bit; + } DEV_CHAR_TABLE4_LOC2; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t DCT_DEV4_LOC3 : 32; /*!< NA */ + } bit; + } DEV_CHAR_TABLE4_LOC3; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t DCT_DEV4_LOC4 : 32; /*!< NA */ + } bit; + } DEV_CHAR_TABLE4_LOC4; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t DCT_DEV5_LOC1 : 32; /*!< NA */ + } bit; + } DEV_CHAR_TABLE5_LOC1; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t DCT_DEV5_LOC2 : 32; /*!< NA */ + } bit; + } DEV_CHAR_TABLE5_LOC2; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t DCT_DEV5_LOC3 : 32; /*!< NA */ + } bit; + } DEV_CHAR_TABLE5_LOC3; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t DCT_DEV5_LOC4 : 32; /*!< NA */ + } bit; + } DEV_CHAR_TABLE5_LOC4; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t DCT_DEV6_LOC1 : 32; /*!< NA */ + } bit; + } DEV_CHAR_TABLE6_LOC1; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t DCT_DEV6_LOC2 : 32; /*!< NA */ + } bit; + } DEV_CHAR_TABLE6_LOC2; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t DCT_DEV6_LOC3 : 32; /*!< NA */ + } bit; + } DEV_CHAR_TABLE6_LOC3; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t DCT_DEV6_LOC4 : 32; /*!< NA */ + } bit; + } DEV_CHAR_TABLE6_LOC4; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t DCT_DEV7_LOC1 : 32; /*!< NA */ + } bit; + } DEV_CHAR_TABLE7_LOC1; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t DCT_DEV7_LOC2 : 32; /*!< NA */ + } bit; + } DEV_CHAR_TABLE7_LOC2; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t DCT_DEV7_LOC3 : 32; /*!< NA */ + } bit; + } DEV_CHAR_TABLE7_LOC3; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t DCT_DEV7_LOC4 : 32; /*!< NA */ + } bit; + } DEV_CHAR_TABLE7_LOC4; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t DCT_DEV8_LOC1 : 32; /*!< NA */ + } bit; + } DEV_CHAR_TABLE8_LOC1; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t DCT_DEV8_LOC2 : 32; /*!< NA */ + } bit; + } DEV_CHAR_TABLE8_LOC2; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t DCT_DEV8_LOC3 : 32; /*!< NA */ + } bit; + } DEV_CHAR_TABLE8_LOC3; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t DCT_DEV8_LOC4 : 32; /*!< NA */ + } bit; + } DEV_CHAR_TABLE8_LOC4; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t DCT_DEV9_LOC1 : 32; /*!< NA */ + } bit; + } DEV_CHAR_TABLE9_LOC1; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t DCT_DEV9_LOC2 : 32; /*!< NA */ + } bit; + } DEV_CHAR_TABLE9_LOC2; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t DCT_DEV9_LOC3 : 32; /*!< NA */ + } bit; + } DEV_CHAR_TABLE9_LOC3; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t DCT_DEV9_LOC4 : 32; /*!< NA */ + } bit; + } DEV_CHAR_TABLE9_LOC4; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t DCT_DEV10_LOC1 : 32; /*!< NA */ + } bit; + } DEV_CHAR_TABLE10_LOC1; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t DCT_DEV10_LOC2 : 32; /*!< NA */ + } bit; + } DEV_CHAR_TABLE10_LOC2; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t DCT_DEV10_LOC3 : 32; /*!< NA */ + } bit; + } DEV_CHAR_TABLE10_LOC3; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t DCT_DEV10_LOC4 : 32; /*!< NA */ + } bit; + } DEV_CHAR_TABLE10_LOC4; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t DCT_DEV11_LOC1 : 32; /*!< NA */ + } bit; + } DEV_CHAR_TABLE11_LOC1; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t DCT_DEV11_LOC2 : 32; /*!< NA */ + } bit; + } DEV_CHAR_TABLE11_LOC2; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t DCT_DEV11_LOC3 : 32; /*!< NA */ + } bit; + } DEV_CHAR_TABLE11_LOC3; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t DCT_DEV11_LOC4 : 32; /*!< NA */ + } bit; + } DEV_CHAR_TABLE11_LOC4; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t DCT_DEV12_LOC1 : 32; /*!< NA */ + } bit; + } DEV_CHAR_TABLE12_LOC1; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t DCT_DEV12_LOC2 : 32; /*!< NA */ + } bit; + } DEV_CHAR_TABLE12_LOC2; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t DCT_DEV12_LOC3 : 32; /*!< NA */ + } bit; + } DEV_CHAR_TABLE12_LOC3; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t DCT_DEV12_LOC4 : 32; /*!< NA */ + } bit; + } DEV_CHAR_TABLE12_LOC4; +} I3C_MST_MEM_Type; /*!< Size = 448 (0x1c0) */ + + + +/* =========================================================================================================================== */ +/* ================ I3C_SLV ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief I3C Controller (Slave) (I3C_SLV) + */ + +typedef struct { /*!< I3C_SLV Structure */ + __IM uint32_t RESERVED; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t SLVENA : 1; /*!< 1: allow the slave to operate on i2c or i3c bus. 0: the slave + will ignore the bus. This should be not set until registers + such as PARTNO, IDEXT and the like are set 1st -if used- + since they impact data to the master */ + __IOM uint32_t NACK : 1; /*!< 1:the slave will NACK all requests to it except CCC broadcast. + This should be used with caution as the Master may determine + the slave is missing if overused. */ + __IOM uint32_t MATCHSS : 1; /*!< 1: the START and STOP sticky STATUS bits will only be set if + MATCHED is set..This allows START and STOP to be used to + detect end of a message to /from this slave. */ + __IOM uint32_t S0IGNORE : 1; /*!< If 1, the Slave will not detect S0 or S1 errors and so not lock + up waiting on an Exit Pattern. This should only be used + when the bus will not use HDR. */ + __IOM uint32_t DDROK : 1; /*!< NA */ + uint32_t : 3; + __IOM uint32_t IDRAND : 1; /*!< NA */ + __IOM uint32_t OFFLINE : 1; /*!< NA */ + uint32_t : 6; + __IOM uint32_t BAMATCH : 8; /*!< Bus Available condition match value for current ???Slow clock???. + This provides the count of the slow clock to count out + 1us (or more) to allow an IBI to drive SDA Low when the + Master is not doing so. The max width , and so max value, + is controlled by the block. Only if enabled for events + such IBI or MR or HJ, and if enabled to provide this as + a register. With is limited to CLK_SLOW_BITS */ + uint32_t : 1; + __IOM uint32_t SADDR : 7; /*!< If allowed by the block:sets i2c 7 bits static address,else + should be 0. If enabled to use one and to be provided by + SW. Block may provide in HW as well. */ + } bit; + } CONFIG; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t STNOTSTOP : 1; /*!< Is 1 if bus is busy(activity) and 0 when in a STOP condition. + Other bits may also set when busy. Note that this can also + be true from an S0 or S1 error, which waits for an Exit + Pattern. */ + __IM uint32_t STMSG : 1; /*!< Is 1 if this bus Slave is listening to the bus traffic or repsonding, + If STNOSTOP=1, then this will be 0 when a non-matching + address seen until next respeated START it STOP. */ + __IM uint32_t STCCCH : 1; /*!< Is 1 if a CCC message is being handled automatically. */ + __IM uint32_t STREQRD : 1; /*!< 1 if the req in process is an sdr read from this slave or an + IBI is being pushed out, */ + __IM uint32_t STREQWR : 1; /*!< NA */ + __IM uint32_t STDAA : 1; /*!< NA */ + __IM uint32_t STHDR : 1; /*!< NA */ + uint32_t : 1; + __IOM uint32_t START : 1; /*!< NA */ + __IOM uint32_t MATCHED : 1; /*!< NA */ + __IOM uint32_t STOP : 1; /*!< NA */ + __IM uint32_t RXPEND : 1; /*!< Receiving a message from master,which is not being handled by + block(not a CCC internally processed). For all but External + FIFO, this uses DATACTRL RXTRIG, which defaults to not-empty. + If DMA is enabled for RX, DMA will be signaled as well. + Will self-clear if data is read(FIFO and non-FIFO) */ + __IM uint32_t TXNOTFULL : 1; /*!< Is 1 when the To-bus buffer/FIFO can accept more data to go + out. Defau:1. For all but External FIFO, this uses DATACTRL + TXTRIG,which defaults to not-full. If DMA is enabled for + TX, it will also be signaled to provide more. */ + __IOM uint32_t DACHG : 1; /*!< The Slv Dynamic Address has been assigned, reassigned, or reset(lost) + and is now in that state of being valid or none. Actual + DA can be seen in the DYNADDR register. Note that this + will also be used when MAP Auto feature is configured. + This will be changing one or more MAP items. See DYNADDR + and/or MAPCTRLn. DYNAADDR for the main DA(0) will indicate + if last change was due to Auto MAP. */ + __IOM uint32_t CCC : 1; /*!< A common -command-code(CCC), not handled by block, has been + received. This acts differently between: *Broadcasted ones, + which will then also correspond with RXPEND and the 1st + byte will be the CCC(command) . *Direct ones, which may + never be directed to this device. If it is, then the TXSEND + or RXPEND will be triggered with this end the RXPEND will + contain the command. */ + __IM uint32_t ERRWARN : 1; /*!< NA */ + __IOM uint32_t HDRMATCH : 1; /*!< NA */ + uint32_t : 15; + } bit; + } STATUS; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t SLV_EVENT : 2; /*!< If set to non-0, will request an event. Once requested, STATUS.EVENT + and EVDET will show the status as it progresses. Once completed, + the field will automatically return to 0. Once non-0, only + 0 can be written(to cancel) until done. 0: Normal mode. + If set to 0 after was a non-0 value, will cancel if not + already in flight. 1: start an IBI. This will try to push + through an IBI on the bus. If data associate with the IBI, + it will be drawn from the IBIDATA field. Note that if Time + control is enabled, this will include anytime control related + bytes further, the IBIDATA byte will have bit7 set to 1. */ + uint32_t : 1; + __IOM uint32_t EXTDATA : 1; /*!< reserved */ + __IOM uint32_t MAPIDX : 4; /*!< Index of Dynamic Address that IBI is for. This is 0 for the + main or base Dynamic Address, or can be any valid index. */ + __IOM uint32_t IBIDATA : 8; /*!< Data byte to go with an IBI, if enabled for it. If enabled (was + in BCR), then it is required. */ + __IOM uint32_t PENDINT : 4; /*!< Should be set to the pending interrupt that GETSTATUS CCC will + return. This should be maintained by the application if + used and configured, as the Master will read this. If not + configured, the GETSTATUS field will return 1 if an IBI + is pending, and 0 otherwise. */ + __IOM uint32_t ACTSTATE : 2; /*!< NA */ + uint32_t : 2; + __IOM uint32_t VENDINFO : 8; /*!< NA */ + } bit; + } CTRL; + + union { + __IOM uint32_t reg; /*!< INSET allows setting enables for interrupts(connecting the corresponding + STATUS source to causing an IRQ to the processor) */ + + struct { + uint32_t : 10; + __IOM uint32_t STOP_ENA : 1; /*!< Interrupt on STOP state on the bus. See Start as the preferred + interrupt when needed. This interrupt may not trigger for + quick STOP/START combination, as it relates to the state + of being stopped. */ + __IOM uint32_t RXPEND_ENA : 1; /*!< Interrupt when receiving a message from Master, which is not + being handled by the block (excludes CCCs being handled + automatically). If FIFO, then RX fullness trigger. If DMA, + then message end. */ + __IOM uint32_t TXSEND_ENA : 1; /*!< NA */ + uint32_t : 19; + } bit; + } INTSET; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + uint32_t : 10; + __OM uint32_t STOP_CLR : 1; /*!< Interrupt on STOP state on the bus. See Start as the preferred + interrupt when needed. This interrupt may not trigger for + quick STOP/START combination, as it relates to the state + of being stopped. */ + __OM uint32_t RXPEND_CLR : 1; /*!< Interrupt when receiving a message from Master, which is not + being handled by the block (excludes CCCs being handled + automatically). If FIFO, then RX fullness trigger. If DMA, + then message end. */ + __OM uint32_t TXSEND_CLR : 1; /*!< NA */ + uint32_t : 19; + } bit; + } INTCLR; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + uint32_t : 10; + __IM uint32_t STOP_MASK : 1; /*!< Interrupt on STOP state on the bus. See Start as the preferred + interrupt when needed. This interrupt may not trigger for + quick STOP/START combination, as it relates to the state + of being stopped. */ + __IM uint32_t RXPEND_MASK : 1; /*!< Interrupt when receiving a message from Master, which is not + being handled by the block (excludes CCCs being handled + automatically). If FIFO, then RX fullness trigger. If DMA, + then message end. */ + __IM uint32_t TXSEND_MASK : 1; /*!< NA */ + uint32_t : 19; + } bit; + } INTMASKED; + __IM uint32_t RESERVED1[4]; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __OM uint32_t FLUSHTB : 1; /*!< Flushes the from-bus buffer/FIFO. Not normally used */ + __OM uint32_t FLUSHFB : 1; /*!< Flushes the to-bus buffer/FIFO. Used when Master terminates + a to-bus (read) message prematurely */ + uint32_t : 1; + __OM uint32_t UNLOCK : 1; /*!< If this bit is not written 1, the register bits from 7 to 4 + are not changed on write. */ + __IOM uint32_t TXTRIG : 2; /*!< Trigger level for tx emptiness when FIFOed, Affects interrupt + and DMA(if enabled). The defaults is 3 */ + __IOM uint32_t RXTRIG : 2; /*!< Trigger level for rx fulless when FIFOed, Affects interrupt + and DMA(if enabled). The defaults is 3 */ + uint32_t : 8; + __IM uint32_t TXCOUNT : 5; /*!< NA */ + uint32_t : 3; + __IM uint32_t RXCOUNT : 5; /*!< NA */ + uint32_t : 1; + __IM uint32_t TXFULL : 1; /*!< NA */ + __IM uint32_t RXEMPTY : 1; /*!< NA */ + } bit; + } DATACTRL; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __OM uint32_t WDATAB : 8; /*!< NA */ + __OM uint32_t WDATA_END : 1; /*!< NA */ + uint32_t : 23; + } bit; + } WDATAB; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __OM uint32_t WDATABE : 8; /*!< NA */ + uint32_t : 24; + } bit; + } WDATABE; + __IM uint32_t RESERVED2[2]; + + union { + __IOM uint32_t reg; /*!< Read Byte Data (from-bus) register */ + + struct { + __IM uint32_t DATA0 : 8; /*!< This register allows reading a byte from the bus unless external + FIFO is used. A byte should not be read unless there is + data waiting, as indicated by the RXPEND bit being set + in the STATUS register */ + uint32_t : 24; + } bit; + } RDARAB; + __IM uint32_t RESERVED3; + + union { + __IOM uint32_t reg; /*!< Read Half-word Data (from-bus) register */ + + struct { + __IM uint32_t DATA_LSB : 8; /*!< NA */ + __IM uint32_t DATA_MSB : 8; /*!< This register allows reading a Half-word (byte pair) from the + bus unless external FIFO is used. A Half-word should not + be read unless there is at least 2 bytes of data waiting, + as indicated by the RX FIFO level trigger or RXCOUNT available + space in the DATACTRL register */ + uint32_t : 16; + } bit; + } RDATAH; + __IM uint32_t RESERVED4[4]; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t CAPABLITIES2 : 32; /*!< NA */ + } bit; + } CAPABILITIES2; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t CAPABLITIES : 32; /*!< NA */ + } bit; + } CAPABILITIES; + __IM uint32_t RESERVED5[2]; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t PARTNO : 32; /*!< NA */ + } bit; + } IDPARTNO; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t IDEXT : 32; /*!< NA */ + } bit; + } IDEXT; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t VID : 15; /*!< NA */ + uint32_t : 17; + } bit; + } VENDORID; +} I3C_SLV_Type; /*!< Size = 120 (0x78) */ + + + +/* =========================================================================================================================== */ +/* ================ AXI_ICM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief AXI_ICM Peripheral (AXI_ICM) + */ + +typedef struct { /*!< AXI_ICM Structure */ + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t ICM_REG_VERID : 32; /*!< NA */ + } bit; + } VERID_FILEDS; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IM uint32_t ICM_REG_AXI_HWCFG_QOS_SUPPORT : 1;/*!< NA */ + __IM uint32_t ICM_REG_AXI_HWCFG_APB3_SUPPORT : 1;/*!< NA */ + __IM uint32_t ICM_REG_AXI_HWCFG_AXI4_SUPPORT : 1;/*!< NA */ + __IM uint32_t ICM_REG_AXI_HWCFG_LOCK_EN : 1;/*!< NA */ + __IM uint32_t ICM_REG_AXI_HWCFG_TRUST_ZONE_EN : 1;/*!< NA */ + __IM uint32_t ICM_REG_AXI_HWCFG_DECODER_TYPE : 1;/*!< NA */ + __IM uint32_t ICM_REG_AXI_HWCFG_REMAP_EN : 1;/*!< NA */ + __IM uint32_t ICM_REG_AXI_HWCFG_BI_DIR_CMD_EN : 1;/*!< NA */ + __IM uint32_t ICM_REG_AXI_HWCFG_LOW_POWER_INF_EN : 1;/*!< NA */ + uint32_t : 3; + __IM uint32_t ICM_REG_AXI_HWCFG_AXI_NUM_MASTERS : 5;/*!< NA */ + uint32_t : 3; + __IM uint32_t ICM_REG_AXI_HWCFG_AXI_NUM_SLAVES : 5;/*!< NA */ + uint32_t : 7; + } bit; + } HW_CFG; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t ICM_REG_AXI_CMD : 3; /*!< NA */ + uint32_t : 4; + __IOM uint32_t ICM_REG_RD_WR_CHAN : 1; /*!< NA */ + __IOM uint32_t ICM_REG_AXI_MASTER_PORT : 4;/*!< NA */ + uint32_t : 16; + __IM uint32_t ICM_REG_AXI_ERR_BIT : 1; /*!< NA */ + __IOM uint32_t ICM_REG_AXI_SOFT_RESET_BIT : 1;/*!< NA */ + __IOM uint32_t ICM_REG_AXI_RD_WR_CMD : 1; /*!< NA */ + __IOM uint32_t ICM_REG_AXI_CMD_EN : 1; /*!< NA */ + } bit; + } CMD; + + union { + __IOM uint32_t reg; /*!< NA */ + + struct { + __IOM uint32_t ICM_REG_DATA : 32; /*!< NA */ + } bit; + } DATA; +} AXI_ICM_Type; /*!< Size = 16 (0x10) */ + + + +/* =========================================================================================================================== */ +/* ================ IO_MUX ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Input/Output Multiplexer (IO_MUX) + */ + +typedef struct { /*!< IO_MUX Structure */ + __IM uint32_t RESERVED; + + union { + __IOM uint32_t reg; /*!< IO_MUX Control Register */ + + struct { + __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep + mode. 0: Disable 1: Enable */ + __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: + Not enter 1: Enter */ + __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during + sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: + ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ + __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable + 1: Enable */ + __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: + ~20 mA 3: ~40 mA */ + __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select + Function 0 1: Select Function 1 ...... */ + __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. + 0: Disable 1: Enable */ + uint32_t : 16; + } bit; + } GPIO0; + __IM uint32_t RESERVED1[3]; + + union { + __IOM uint32_t reg; /*!< IO_MUX Control Register */ + + struct { + __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep + mode. 0: Disable 1: Enable */ + __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: + Not enter 1: Enter */ + __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during + sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: + ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ + __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable + 1: Enable */ + __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: + ~20 mA 3: ~40 mA */ + __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select + Function 0 1: Select Function 1 ...... */ + __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. + 0: Disable 1: Enable */ + uint32_t : 16; + } bit; + } GPIO1; + __IM uint32_t RESERVED2[3]; + + union { + __IOM uint32_t reg; /*!< IO_MUX Control Register */ + + struct { + __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep + mode. 0: Disable 1: Enable */ + __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: + Not enter 1: Enter */ + __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during + sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: + ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ + __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable + 1: Enable */ + __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: + ~20 mA 3: ~40 mA */ + __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select + Function 0 1: Select Function 1 ...... */ + __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. + 0: Disable 1: Enable */ + uint32_t : 16; + } bit; + } GPIO2; + __IM uint32_t RESERVED3[3]; + + union { + __IOM uint32_t reg; /*!< IO_MUX Control Register */ + + struct { + __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep + mode. 0: Disable 1: Enable */ + __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: + Not enter 1: Enter */ + __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during + sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: + ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ + __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable + 1: Enable */ + __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: + ~20 mA 3: ~40 mA */ + __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select + Function 0 1: Select Function 1 ...... */ + __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. + 0: Disable 1: Enable */ + uint32_t : 16; + } bit; + } GPIO3; + __IM uint32_t RESERVED4[3]; + + union { + __IOM uint32_t reg; /*!< IO_MUX Control Register */ + + struct { + __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep + mode. 0: Disable 1: Enable */ + __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: + Not enter 1: Enter */ + __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during + sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: + ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ + __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable + 1: Enable */ + __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: + ~20 mA 3: ~40 mA */ + __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select + Function 0 1: Select Function 1 ...... */ + __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. + 0: Disable 1: Enable */ + uint32_t : 16; + } bit; + } GPIO4; + __IM uint32_t RESERVED5[3]; + + union { + __IOM uint32_t reg; /*!< IO_MUX Control Register */ + + struct { + __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep + mode. 0: Disable 1: Enable */ + __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: + Not enter 1: Enter */ + __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during + sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: + ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ + __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable + 1: Enable */ + __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: + ~20 mA 3: ~40 mA */ + __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select + Function 0 1: Select Function 1 ...... */ + __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. + 0: Disable 1: Enable */ + uint32_t : 16; + } bit; + } GPIO5; + __IM uint32_t RESERVED6[3]; + + union { + __IOM uint32_t reg; /*!< IO_MUX Control Register */ + + struct { + __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep + mode. 0: Disable 1: Enable */ + __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: + Not enter 1: Enter */ + __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during + sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: + ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ + __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable + 1: Enable */ + __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: + ~20 mA 3: ~40 mA */ + __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select + Function 0 1: Select Function 1 ...... */ + __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. + 0: Disable 1: Enable */ + uint32_t : 16; + } bit; + } GPIO6; + __IM uint32_t RESERVED7[3]; + + union { + __IOM uint32_t reg; /*!< IO_MUX Control Register */ + + struct { + __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep + mode. 0: Disable 1: Enable */ + __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: + Not enter 1: Enter */ + __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during + sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: + ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ + __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable + 1: Enable */ + __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: + ~20 mA 3: ~40 mA */ + __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select + Function 0 1: Select Function 1 ...... */ + __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. + 0: Disable 1: Enable */ + uint32_t : 16; + } bit; + } GPIO7; + __IM uint32_t RESERVED8[3]; + + union { + __IOM uint32_t reg; /*!< IO_MUX Control Register */ + + struct { + __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep + mode. 0: Disable 1: Enable */ + __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: + Not enter 1: Enter */ + __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during + sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: + ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ + __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable + 1: Enable */ + __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: + ~20 mA 3: ~40 mA */ + __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select + Function 0 1: Select Function 1 ...... */ + __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. + 0: Disable 1: Enable */ + uint32_t : 16; + } bit; + } GPIO8; + __IM uint32_t RESERVED9[3]; + + union { + __IOM uint32_t reg; /*!< IO_MUX Control Register */ + + struct { + __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep + mode. 0: Disable 1: Enable */ + __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: + Not enter 1: Enter */ + __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during + sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: + ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ + __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable + 1: Enable */ + __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: + ~20 mA 3: ~40 mA */ + __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select + Function 0 1: Select Function 1 ...... */ + __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. + 0: Disable 1: Enable */ + uint32_t : 16; + } bit; + } GPIO9; + __IM uint32_t RESERVED10[3]; + + union { + __IOM uint32_t reg; /*!< IO_MUX Control Register */ + + struct { + __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep + mode. 0: Disable 1: Enable */ + __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: + Not enter 1: Enter */ + __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during + sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: + ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ + __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable + 1: Enable */ + __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: + ~20 mA 3: ~40 mA */ + __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select + Function 0 1: Select Function 1 ...... */ + __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. + 0: Disable 1: Enable */ + uint32_t : 16; + } bit; + } GPIO10; + __IM uint32_t RESERVED11[3]; + + union { + __IOM uint32_t reg; /*!< IO_MUX Control Register */ + + struct { + __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep + mode. 0: Disable 1: Enable */ + __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: + Not enter 1: Enter */ + __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during + sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: + ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ + __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable + 1: Enable */ + __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: + ~20 mA 3: ~40 mA */ + __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select + Function 0 1: Select Function 1 ...... */ + __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. + 0: Disable 1: Enable */ + uint32_t : 16; + } bit; + } GPIO11; + __IM uint32_t RESERVED12[3]; + + union { + __IOM uint32_t reg; /*!< IO_MUX Control Register */ + + struct { + __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep + mode. 0: Disable 1: Enable */ + __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: + Not enter 1: Enter */ + __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during + sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: + ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ + __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable + 1: Enable */ + __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: + ~20 mA 3: ~40 mA */ + __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select + Function 0 1: Select Function 1 ...... */ + __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. + 0: Disable 1: Enable */ + uint32_t : 16; + } bit; + } GPIO12; + __IM uint32_t RESERVED13[3]; + + union { + __IOM uint32_t reg; /*!< IO_MUX Control Register */ + + struct { + __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep + mode. 0: Disable 1: Enable */ + __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: + Not enter 1: Enter */ + __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during + sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: + ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ + __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable + 1: Enable */ + __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: + ~20 mA 3: ~40 mA */ + __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select + Function 0 1: Select Function 1 ...... */ + __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. + 0: Disable 1: Enable */ + uint32_t : 16; + } bit; + } GPIO13; + __IM uint32_t RESERVED14[3]; + + union { + __IOM uint32_t reg; /*!< IO_MUX Control Register */ + + struct { + __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep + mode. 0: Disable 1: Enable */ + __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: + Not enter 1: Enter */ + __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during + sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: + ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ + __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable + 1: Enable */ + __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: + ~20 mA 3: ~40 mA */ + __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select + Function 0 1: Select Function 1 ...... */ + __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. + 0: Disable 1: Enable */ + uint32_t : 16; + } bit; + } GPIO14; + __IM uint32_t RESERVED15[3]; + + union { + __IOM uint32_t reg; /*!< IO_MUX Control Register */ + + struct { + __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep + mode. 0: Disable 1: Enable */ + __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: + Not enter 1: Enter */ + __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during + sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: + ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ + __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable + 1: Enable */ + __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: + ~20 mA 3: ~40 mA */ + __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select + Function 0 1: Select Function 1 ...... */ + __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. + 0: Disable 1: Enable */ + uint32_t : 16; + } bit; + } GPIO15; + __IM uint32_t RESERVED16[3]; + + union { + union { + __IOM uint32_t reg; /*!< iomux version */ + + struct { + __IOM uint32_t DATE : 28; /*!< csv date */ + uint32_t : 4; + } bit; + } DATE; + + union { + __IOM uint32_t reg; /*!< IO_MUX Control Register */ + + struct { + __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep + mode. 0: Disable 1: Enable */ + __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: + Not enter 1: Enter */ + __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during + sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: + ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ + __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable + 1: Enable */ + __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: + ~20 mA 3: ~40 mA */ + __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select + Function 0 1: Select Function 1 ...... */ + __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. + 0: Disable 1: Enable */ + uint32_t : 16; + } bit; + } GPIO16; + }; + __IM uint32_t RESERVED17[3]; + + union { + __IOM uint32_t reg; /*!< IO_MUX Control Register */ + + struct { + __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep + mode. 0: Disable 1: Enable */ + __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: + Not enter 1: Enter */ + __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during + sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: + ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ + __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable + 1: Enable */ + __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: + ~20 mA 3: ~40 mA */ + __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select + Function 0 1: Select Function 1 ...... */ + __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. + 0: Disable 1: Enable */ + uint32_t : 16; + } bit; + } GPIO17; + __IM uint32_t RESERVED18[3]; + + union { + __IOM uint32_t reg; /*!< IO_MUX Control Register */ + + struct { + __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep + mode. 0: Disable 1: Enable */ + __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: + Not enter 1: Enter */ + __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during + sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: + ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ + __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable + 1: Enable */ + __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: + ~20 mA 3: ~40 mA */ + __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select + Function 0 1: Select Function 1 ...... */ + __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. + 0: Disable 1: Enable */ + uint32_t : 16; + } bit; + } GPIO18; + __IM uint32_t RESERVED19[3]; + + union { + __IOM uint32_t reg; /*!< IO_MUX Control Register */ + + struct { + __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep + mode. 0: Disable 1: Enable */ + __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: + Not enter 1: Enter */ + __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during + sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: + ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ + __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable + 1: Enable */ + __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: + ~20 mA 3: ~40 mA */ + __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select + Function 0 1: Select Function 1 ...... */ + __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. + 0: Disable 1: Enable */ + uint32_t : 16; + } bit; + } GPIO19; + __IM uint32_t RESERVED20[3]; + + union { + __IOM uint32_t reg; /*!< IO_MUX Control Register */ + + struct { + __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep + mode. 0: Disable 1: Enable */ + __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: + Not enter 1: Enter */ + __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during + sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: + ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ + __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable + 1: Enable */ + __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: + ~20 mA 3: ~40 mA */ + __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select + Function 0 1: Select Function 1 ...... */ + __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. + 0: Disable 1: Enable */ + uint32_t : 16; + } bit; + } GPIO20; + __IM uint32_t RESERVED21[3]; + + union { + __IOM uint32_t reg; /*!< IO_MUX Control Register */ + + struct { + __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep + mode. 0: Disable 1: Enable */ + __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: + Not enter 1: Enter */ + __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during + sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: + ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ + __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable + 1: Enable */ + __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: + ~20 mA 3: ~40 mA */ + __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select + Function 0 1: Select Function 1 ...... */ + __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. + 0: Disable 1: Enable */ + uint32_t : 16; + } bit; + } GPIO21; + __IM uint32_t RESERVED22[3]; + + union { + __IOM uint32_t reg; /*!< IO_MUX Control Register */ + + struct { + __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep + mode. 0: Disable 1: Enable */ + __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: + Not enter 1: Enter */ + __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during + sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: + ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ + __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable + 1: Enable */ + __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: + ~20 mA 3: ~40 mA */ + __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select + Function 0 1: Select Function 1 ...... */ + __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. + 0: Disable 1: Enable */ + uint32_t : 16; + } bit; + } GPIO22; + __IM uint32_t RESERVED23[3]; + + union { + __IOM uint32_t reg; /*!< IO_MUX Control Register */ + + struct { + __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep + mode. 0: Disable 1: Enable */ + __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: + Not enter 1: Enter */ + __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during + sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: + ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ + __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable + 1: Enable */ + __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: + ~20 mA 3: ~40 mA */ + __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select + Function 0 1: Select Function 1 ...... */ + __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. + 0: Disable 1: Enable */ + uint32_t : 16; + } bit; + } GPIO23; + __IM uint32_t RESERVED24[3]; + + union { + __IOM uint32_t reg; /*!< IO_MUX Control Register */ + + struct { + __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep + mode. 0: Disable 1: Enable */ + __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: + Not enter 1: Enter */ + __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during + sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: + ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ + __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable + 1: Enable */ + __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: + ~20 mA 3: ~40 mA */ + __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select + Function 0 1: Select Function 1 ...... */ + __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. + 0: Disable 1: Enable */ + uint32_t : 16; + } bit; + } GPIO24; + __IM uint32_t RESERVED25[3]; + + union { + __IOM uint32_t reg; /*!< IO_MUX Control Register */ + + struct { + __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep + mode. 0: Disable 1: Enable */ + __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: + Not enter 1: Enter */ + __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during + sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: + ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ + __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable + 1: Enable */ + __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: + ~20 mA 3: ~40 mA */ + __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select + Function 0 1: Select Function 1 ...... */ + __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. + 0: Disable 1: Enable */ + uint32_t : 16; + } bit; + } GPIO25; + __IM uint32_t RESERVED26[3]; + + union { + __IOM uint32_t reg; /*!< IO_MUX Control Register */ + + struct { + __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep + mode. 0: Disable 1: Enable */ + __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: + Not enter 1: Enter */ + __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during + sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: + ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ + __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable + 1: Enable */ + __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: + ~20 mA 3: ~40 mA */ + __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select + Function 0 1: Select Function 1 ...... */ + __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. + 0: Disable 1: Enable */ + uint32_t : 16; + } bit; + } GPIO26; + __IM uint32_t RESERVED27[3]; + + union { + __IOM uint32_t reg; /*!< IO_MUX Control Register */ + + struct { + __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep + mode. 0: Disable 1: Enable */ + __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: + Not enter 1: Enter */ + __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during + sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: + ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ + __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable + 1: Enable */ + __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: + ~20 mA 3: ~40 mA */ + __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select + Function 0 1: Select Function 1 ...... */ + __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. + 0: Disable 1: Enable */ + uint32_t : 16; + } bit; + } GPIO27; + __IM uint32_t RESERVED28[3]; + + union { + __IOM uint32_t reg; /*!< IO_MUX Control Register */ + + struct { + __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep + mode. 0: Disable 1: Enable */ + __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: + Not enter 1: Enter */ + __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during + sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: + ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ + __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable + 1: Enable */ + __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: + ~20 mA 3: ~40 mA */ + __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select + Function 0 1: Select Function 1 ...... */ + __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. + 0: Disable 1: Enable */ + uint32_t : 16; + } bit; + } GPIO28; + __IM uint32_t RESERVED29[3]; + + union { + __IOM uint32_t reg; /*!< IO_MUX Control Register */ + + struct { + __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep + mode. 0: Disable 1: Enable */ + __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: + Not enter 1: Enter */ + __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during + sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: + ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ + __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable + 1: Enable */ + __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: + ~20 mA 3: ~40 mA */ + __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select + Function 0 1: Select Function 1 ...... */ + __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. + 0: Disable 1: Enable */ + uint32_t : 16; + } bit; + } GPIO29; + __IM uint32_t RESERVED30[3]; + + union { + __IOM uint32_t reg; /*!< IO_MUX Control Register */ + + struct { + __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep + mode. 0: Disable 1: Enable */ + __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: + Not enter 1: Enter */ + __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during + sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: + ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ + __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable + 1: Enable */ + __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: + ~20 mA 3: ~40 mA */ + __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select + Function 0 1: Select Function 1 ...... */ + __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. + 0: Disable 1: Enable */ + uint32_t : 16; + } bit; + } GPIO30; + __IM uint32_t RESERVED31[3]; + + union { + __IOM uint32_t reg; /*!< IO_MUX Control Register */ + + struct { + __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep + mode. 0: Disable 1: Enable */ + __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: + Not enter 1: Enter */ + __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during + sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: + ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ + __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable + 1: Enable */ + __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: + ~20 mA 3: ~40 mA */ + __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select + Function 0 1: Select Function 1 ...... */ + __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. + 0: Disable 1: Enable */ + uint32_t : 16; + } bit; + } GPIO31; + __IM uint32_t RESERVED32[3]; + + union { + __IOM uint32_t reg; /*!< IO_MUX Control Register */ + + struct { + __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep + mode. 0: Disable 1: Enable */ + __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: + Not enter 1: Enter */ + __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during + sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: + ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ + __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable + 1: Enable */ + __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: + ~20 mA 3: ~40 mA */ + __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select + Function 0 1: Select Function 1 ...... */ + __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. + 0: Disable 1: Enable */ + uint32_t : 16; + } bit; + } GPIO32; + __IM uint32_t RESERVED33[3]; + + union { + __IOM uint32_t reg; /*!< IO_MUX Control Register */ + + struct { + __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep + mode. 0: Disable 1: Enable */ + __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: + Not enter 1: Enter */ + __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during + sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: + ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ + __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable + 1: Enable */ + __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: + ~20 mA 3: ~40 mA */ + __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select + Function 0 1: Select Function 1 ...... */ + __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. + 0: Disable 1: Enable */ + uint32_t : 16; + } bit; + } GPIO33; + __IM uint32_t RESERVED34[3]; + + union { + __IOM uint32_t reg; /*!< IO_MUX Control Register */ + + struct { + __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep + mode. 0: Disable 1: Enable */ + __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: + Not enter 1: Enter */ + __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during + sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: + ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ + __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable + 1: Enable */ + __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: + ~20 mA 3: ~40 mA */ + __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select + Function 0 1: Select Function 1 ...... */ + __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. + 0: Disable 1: Enable */ + uint32_t : 16; + } bit; + } GPIO34; + __IM uint32_t RESERVED35[3]; + + union { + __IOM uint32_t reg; /*!< IO_MUX Control Register */ + + struct { + __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep + mode. 0: Disable 1: Enable */ + __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: + Not enter 1: Enter */ + __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during + sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: + ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ + __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable + 1: Enable */ + __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: + ~20 mA 3: ~40 mA */ + __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select + Function 0 1: Select Function 1 ...... */ + __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. + 0: Disable 1: Enable */ + uint32_t : 16; + } bit; + } GPIO35; + __IM uint32_t RESERVED36[3]; + + union { + __IOM uint32_t reg; /*!< IO_MUX Control Register */ + + struct { + __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep + mode. 0: Disable 1: Enable */ + __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: + Not enter 1: Enter */ + __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during + sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: + ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ + __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable + 1: Enable */ + __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: + ~20 mA 3: ~40 mA */ + __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select + Function 0 1: Select Function 1 ...... */ + __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. + 0: Disable 1: Enable */ + uint32_t : 16; + } bit; + } GPIO36; + __IM uint32_t RESERVED37[3]; + + union { + __IOM uint32_t reg; /*!< IO_MUX Control Register */ + + struct { + __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep + mode. 0: Disable 1: Enable */ + __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: + Not enter 1: Enter */ + __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during + sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: + ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ + __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable + 1: Enable */ + __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: + ~20 mA 3: ~40 mA */ + __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select + Function 0 1: Select Function 1 ...... */ + __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. + 0: Disable 1: Enable */ + uint32_t : 16; + } bit; + } GPIO37; + __IM uint32_t RESERVED38[3]; + + union { + __IOM uint32_t reg; /*!< IO_MUX Control Register */ + + struct { + __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep + mode. 0: Disable 1: Enable */ + __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: + Not enter 1: Enter */ + __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during + sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: + ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ + __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable + 1: Enable */ + __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: + ~20 mA 3: ~40 mA */ + __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select + Function 0 1: Select Function 1 ...... */ + __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. + 0: Disable 1: Enable */ + uint32_t : 16; + } bit; + } GPIO38; + __IM uint32_t RESERVED39[3]; + + union { + __IOM uint32_t reg; /*!< IO_MUX Control Register */ + + struct { + __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep + mode. 0: Disable 1: Enable */ + __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: + Not enter 1: Enter */ + __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during + sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: + ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ + __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable + 1: Enable */ + __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: + ~20 mA 3: ~40 mA */ + __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select + Function 0 1: Select Function 1 ...... */ + __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. + 0: Disable 1: Enable */ + uint32_t : 16; + } bit; + } GPIO39; + __IM uint32_t RESERVED40[3]; + + union { + __IOM uint32_t reg; /*!< IO_MUX Control Register */ + + struct { + __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep + mode. 0: Disable 1: Enable */ + __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: + Not enter 1: Enter */ + __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during + sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: + ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ + __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable + 1: Enable */ + __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: + ~20 mA 3: ~40 mA */ + __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select + Function 0 1: Select Function 1 ...... */ + __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. + 0: Disable 1: Enable */ + uint32_t : 16; + } bit; + } GPIO40; + __IM uint32_t RESERVED41[3]; + + union { + __IOM uint32_t reg; /*!< IO_MUX Control Register */ + + struct { + __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep + mode. 0: Disable 1: Enable */ + __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: + Not enter 1: Enter */ + __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during + sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: + ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ + __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable + 1: Enable */ + __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: + ~20 mA 3: ~40 mA */ + __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select + Function 0 1: Select Function 1 ...... */ + __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. + 0: Disable 1: Enable */ + uint32_t : 16; + } bit; + } GPIO41; + __IM uint32_t RESERVED42[3]; + + union { + __IOM uint32_t reg; /*!< IO_MUX Control Register */ + + struct { + __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep + mode. 0: Disable 1: Enable */ + __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: + Not enter 1: Enter */ + __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during + sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: + ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ + __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable + 1: Enable */ + __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: + ~20 mA 3: ~40 mA */ + __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select + Function 0 1: Select Function 1 ...... */ + __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. + 0: Disable 1: Enable */ + uint32_t : 16; + } bit; + } GPIO42; + __IM uint32_t RESERVED43[3]; + + union { + __IOM uint32_t reg; /*!< IO_MUX Control Register */ + + struct { + __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep + mode. 0: Disable 1: Enable */ + __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: + Not enter 1: Enter */ + __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during + sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: + ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ + __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable + 1: Enable */ + __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: + ~20 mA 3: ~40 mA */ + __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select + Function 0 1: Select Function 1 ...... */ + __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. + 0: Disable 1: Enable */ + uint32_t : 16; + } bit; + } GPIO43; + __IM uint32_t RESERVED44[3]; + + union { + __IOM uint32_t reg; /*!< IO_MUX Control Register */ + + struct { + __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep + mode. 0: Disable 1: Enable */ + __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: + Not enter 1: Enter */ + __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during + sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: + ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ + __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable + 1: Enable */ + __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: + ~20 mA 3: ~40 mA */ + __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select + Function 0 1: Select Function 1 ...... */ + __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. + 0: Disable 1: Enable */ + uint32_t : 16; + } bit; + } GPIO44; + __IM uint32_t RESERVED45[3]; + + union { + __IOM uint32_t reg; /*!< IO_MUX Control Register */ + + struct { + __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep + mode. 0: Disable 1: Enable */ + __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: + Not enter 1: Enter */ + __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during + sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: + ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ + __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable + 1: Enable */ + __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: + ~20 mA 3: ~40 mA */ + __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select + Function 0 1: Select Function 1 ...... */ + __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. + 0: Disable 1: Enable */ + uint32_t : 16; + } bit; + } GPIO45; + __IM uint32_t RESERVED46[3]; + + union { + __IOM uint32_t reg; /*!< IO_MUX Control Register */ + + struct { + __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep + mode. 0: Disable 1: Enable */ + __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: + Not enter 1: Enter */ + __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during + sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: + ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ + __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable + 1: Enable */ + __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: + ~20 mA 3: ~40 mA */ + __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select + Function 0 1: Select Function 1 ...... */ + __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. + 0: Disable 1: Enable */ + uint32_t : 16; + } bit; + } GPIO46; + __IM uint32_t RESERVED47[3]; + + union { + __IOM uint32_t reg; /*!< IO_MUX Control Register */ + + struct { + __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep + mode. 0: Disable 1: Enable */ + __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: + Not enter 1: Enter */ + __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during + sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: + ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ + __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable + 1: Enable */ + __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: + ~20 mA 3: ~40 mA */ + __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select + Function 0 1: Select Function 1 ...... */ + __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. + 0: Disable 1: Enable */ + uint32_t : 16; + } bit; + } GPIO47; + __IM uint32_t RESERVED48[3]; + + union { + __IOM uint32_t reg; /*!< IO_MUX Control Register */ + + struct { + __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep + mode. 0: Disable 1: Enable */ + __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: + Not enter 1: Enter */ + __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during + sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: + ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ + __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable + 1: Enable */ + __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: + ~20 mA 3: ~40 mA */ + __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select + Function 0 1: Select Function 1 ...... */ + __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. + 0: Disable 1: Enable */ + uint32_t : 16; + } bit; + } GPIO48; + __IM uint32_t RESERVED49[3]; + + union { + __IOM uint32_t reg; /*!< IO_MUX Control Register */ + + struct { + __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep + mode. 0: Disable 1: Enable */ + __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: + Not enter 1: Enter */ + __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during + sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: + ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ + __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable + 1: Enable */ + __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: + ~20 mA 3: ~40 mA */ + __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select + Function 0 1: Select Function 1 ...... */ + __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. + 0: Disable 1: Enable */ + uint32_t : 16; + } bit; + } GPIO49; + __IM uint32_t RESERVED50[3]; + + union { + __IOM uint32_t reg; /*!< IO_MUX Control Register */ + + struct { + __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep + mode. 0: Disable 1: Enable */ + __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: + Not enter 1: Enter */ + __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during + sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: + ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ + __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable + 1: Enable */ + __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: + ~20 mA 3: ~40 mA */ + __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select + Function 0 1: Select Function 1 ...... */ + __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. + 0: Disable 1: Enable */ + uint32_t : 16; + } bit; + } GPIO50; + __IM uint32_t RESERVED51[3]; + + union { + __IOM uint32_t reg; /*!< IO_MUX Control Register */ + + struct { + __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep + mode. 0: Disable 1: Enable */ + __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: + Not enter 1: Enter */ + __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during + sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: + ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ + __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable + 1: Enable */ + __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: + ~20 mA 3: ~40 mA */ + __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select + Function 0 1: Select Function 1 ...... */ + __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. + 0: Disable 1: Enable */ + uint32_t : 16; + } bit; + } GPIO51; + __IM uint32_t RESERVED52[3]; + + union { + __IOM uint32_t reg; /*!< IO_MUX Control Register */ + + struct { + __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep + mode. 0: Disable 1: Enable */ + __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: + Not enter 1: Enter */ + __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during + sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: + ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ + __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable + 1: Enable */ + __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: + ~20 mA 3: ~40 mA */ + __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select + Function 0 1: Select Function 1 ...... */ + __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. + 0: Disable 1: Enable */ + uint32_t : 16; + } bit; + } GPIO52; + __IM uint32_t RESERVED53[3]; + + union { + __IOM uint32_t reg; /*!< IO_MUX Control Register */ + + struct { + __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep + mode. 0: Disable 1: Enable */ + __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: + Not enter 1: Enter */ + __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during + sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: + ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ + __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable + 1: Enable */ + __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: + ~20 mA 3: ~40 mA */ + __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select + Function 0 1: Select Function 1 ...... */ + __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. + 0: Disable 1: Enable */ + uint32_t : 16; + } bit; + } GPIO53; + union { + __IOM uint32_t reg; /*!< IO_MUX Control Register */ + + struct { + __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep + mode. 0: Disable 1: Enable */ + __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: + Not enter 1: Enter */ + __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn + during sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during + sleep mode. 0: Disable 1: Enable */ + __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: + ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ + __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. + 0: Disable 1: Enable */ + __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable + 1: Enable */ + __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: + ~20 mA 3: ~40 mA */ + __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select + Function 0 1: Select Function 1 ...... */ + __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. + 0: Disable 1: Enable */ + uint32_t : 16; + } bit; + } GPIO54; +} IO_MUX_Type; /*!< Size = 856 (0x358) */ + + + +/* =========================================================================================================================== */ +/* ================ ISP ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief ISP Peripheral (ISP) + */ + +typedef struct { /*!< ISP Structure */ + + union { + __IOM uint32_t reg; /*!< version control register */ + + struct { + __IOM uint32_t VER_DATA : 32; /*!< csv version */ + } bit; + } VER_DATE; + + union { + __IOM uint32_t reg; /*!< isp clk control register */ + + struct { + __IOM uint32_t CLK_EN : 1; /*!< this bit configures the clk force on of isp reg. 0: disable, + 1: enable */ + __IOM uint32_t CLK_BLC_FORCE_ON : 1; /*!< this bit configures the clk force on of blc. 0: disable, 1: + enable */ + __IOM uint32_t CLK_DPC_FORCE_ON : 1; /*!< this bit configures the clk force on of dpc. 0: disable, 1: + enable */ + __IOM uint32_t CLK_BF_FORCE_ON : 1; /*!< this bit configures the clk force on of bf. 0: disable, 1: enable */ + __IOM uint32_t CLK_LSC_FORCE_ON : 1; /*!< this bit configures the clk force on of lsc. 0: disable, 1: + enable */ + __IOM uint32_t CLK_DEMOSAIC_FORCE_ON : 1; /*!< this bit configures the clk force on of demosaic. 0: disable, + 1: enable */ + __IOM uint32_t CLK_MEDIAN_FORCE_ON : 1; /*!< this bit configures the clk force on of median. 0: disable, + 1: enable */ + __IOM uint32_t CLK_CCM_FORCE_ON : 1; /*!< this bit configures the clk force on of ccm. 0: disable, 1: + enable */ + __IOM uint32_t CLK_GAMMA_FORCE_ON : 1; /*!< this bit configures the clk force on of gamma. 0: disable, 1: + enable */ + __IOM uint32_t CLK_RGB2YUV_FORCE_ON : 1; /*!< this bit configures the clk force on of rgb2yuv. 0: disable, + 1: enable */ + __IOM uint32_t CLK_SHARP_FORCE_ON : 1; /*!< this bit configures the clk force on of sharp. 0: disable, 1: + enable */ + __IOM uint32_t CLK_COLOR_FORCE_ON : 1; /*!< this bit configures the clk force on of color. 0: disable, 1: + enable */ + __IOM uint32_t CLK_YUV2RGB_FORCE_ON : 1; /*!< this bit configures the clk force on of yuv2rgb. 0: disable, + 1: enable */ + __IOM uint32_t CLK_AE_FORCE_ON : 1; /*!< this bit configures the clk force on of ae. 0: disable, 1: enable */ + __IOM uint32_t CLK_AF_FORCE_ON : 1; /*!< this bit configures the clk force on of af. 0: disable, 1: enable */ + __IOM uint32_t CLK_AWB_FORCE_ON : 1; /*!< this bit configures the clk force on of awb. 0: disable, 1: + enable */ + __IOM uint32_t CLK_HIST_FORCE_ON : 1; /*!< this bit configures the clk force on of hist. 0: disable, 1: + enable */ + __IOM uint32_t CLK_MIPI_IDI_FORCE_ON : 1; /*!< this bit configures the clk force on of mipi idi input. 0: disable, + 1: enable */ + __IOM uint32_t ISP_MEM_CLK_FORCE_ON : 1; /*!< this bit configures the clk force on of all isp memory. 0: disable, + 1: enable */ + uint32_t : 13; + } bit; + } CLK_EN; + + union { + __IOM uint32_t reg; /*!< isp module enable control register */ + + struct { + __IOM uint32_t MIPI_DATA_EN : 1; /*!< this bit configures mipi input data enable. 0: disable, 1: enable */ + __IOM uint32_t ISP_EN : 1; /*!< this bit configures isp global enable. 0: disable, 1: enable */ + __IOM uint32_t BLC_EN : 1; /*!< this bit configures blc enable. 0: disable, 1: enable */ + __IOM uint32_t DPC_EN : 1; /*!< this bit configures dpc enable. 0: disable, 1: enable */ + __IOM uint32_t BF_EN : 1; /*!< this bit configures bf enable. 0: disable, 1: enable */ + __IOM uint32_t LSC_EN : 1; /*!< this bit configures lsc enable. 0: disable, 1: enable */ + __IOM uint32_t DEMOSAIC_EN : 1; /*!< this bit configures demosaic enable. 0: disable, 1: enable */ + __IOM uint32_t MEDIAN_EN : 1; /*!< this bit configures median enable. 0: disable, 1: enable */ + __IOM uint32_t CCM_EN : 1; /*!< this bit configures ccm enable. 0: disable, 1: enable */ + __IOM uint32_t GAMMA_EN : 1; /*!< this bit configures gamma enable. 0: disable, 1: enable */ + __IOM uint32_t RGB2YUV_EN : 1; /*!< this bit configures rgb2yuv enable. 0: disable, 1: enable */ + __IOM uint32_t SHARP_EN : 1; /*!< this bit configures sharp enable. 0: disable, 1: enable */ + __IOM uint32_t COLOR_EN : 1; /*!< this bit configures color enable. 0: disable, 1: enable */ + __IOM uint32_t YUV2RGB_EN : 1; /*!< this bit configures yuv2rgb enable. 0: disable, 1: enable */ + __IOM uint32_t AE_EN : 1; /*!< this bit configures ae enable. 0: disable, 1: enable */ + __IOM uint32_t AF_EN : 1; /*!< this bit configures af enable. 0: disable, 1: enable */ + __IOM uint32_t AWB_EN : 1; /*!< this bit configures awb enable. 0: disable, 1: enable */ + __IOM uint32_t HIST_EN : 1; /*!< this bit configures hist enable. 0: disable, 1: enable */ + uint32_t : 6; + __IOM uint32_t BYTE_ENDIAN_ORDER : 1; /*!< select input idi data byte_endian_order when isp is bypass, + 0: csi_data[31:0], 1: {[7:0], [15:8], [23:16], [31:24]} */ + __IOM uint32_t ISP_DATA_TYPE : 2; /*!< this field configures input data type, 0:RAW8 1:RAW10 2:RAW12 */ + __IOM uint32_t ISP_IN_SRC : 2; /*!< this field configures input data source, 0:CSI HOST 1:CAM 2:DMA */ + __IOM uint32_t ISP_OUT_TYPE : 3; /*!< this field configures pixel output type, 0: RAW8 1: YUV422 2: + RGB888 3: YUV420 4: RGB565 */ + } bit; + } CNTL; + + union { + __IOM uint32_t reg; /*!< header hsync interval control register */ + + struct { + __IOM uint32_t HSYNC_CNT : 8; /*!< this field configures the number of clock before hsync and after + vsync and line_end when decodes pix data from idi to isp */ + uint32_t : 24; + } bit; + } HSYNC_CNT; + + union { + __IOM uint32_t reg; /*!< frame control parameter register */ + + struct { + __IOM uint32_t VADR_NUM : 12; /*!< this field configures input image size in y-direction, image + row number - 1 */ + __IOM uint32_t HADR_NUM : 12; /*!< this field configures input image size in x-direction, image + line number - 1 */ + uint32_t : 3; + __IOM uint32_t BAYER_MODE : 2; /*!< this field configures the bayer mode of input pixel. 00 : BG/GR + 01 : GB/RG 10 : GR/BG 11 : RG/GB */ + __IOM uint32_t HSYNC_START_EXIST : 1; /*!< this bit configures the line end packet exist or not. 0: not + exist, 1: exist */ + __IOM uint32_t HSYNC_END_EXIST : 1; /*!< this bit configures the line start packet exist or not. 0: not + exist, 1: exist */ + uint32_t : 1; + } bit; + } FRAME_CFG; + + union { + __IOM uint32_t reg; /*!< ccm coef register 0 */ + + struct { + __IOM uint32_t CCM_RR : 13; /*!< this field configures the color correction matrix coefficient */ + __IOM uint32_t CCM_RG : 13; /*!< this field configures the color correction matrix coefficient */ + uint32_t : 6; + } bit; + } CCM_COEF0; + + union { + __IOM uint32_t reg; /*!< ccm coef register 1 */ + + struct { + __IOM uint32_t CCM_RB : 13; /*!< this field configures the color correction matrix coefficient */ + __IOM uint32_t CCM_GR : 13; /*!< this field configures the color correction matrix coefficient */ + uint32_t : 6; + } bit; + } CCM_COEF1; + + union { + __IOM uint32_t reg; /*!< ccm coef register 3 */ + + struct { + __IOM uint32_t CCM_GG : 13; /*!< this field configures the color correction matrix coefficient */ + __IOM uint32_t CCM_GB : 13; /*!< this field configures the color correction matrix coefficient */ + uint32_t : 6; + } bit; + } CCM_COEF3; + + union { + __IOM uint32_t reg; /*!< ccm coef register 4 */ + + struct { + __IOM uint32_t CCM_BR : 13; /*!< this field configures the color correction matrix coefficient */ + __IOM uint32_t CCM_BG : 13; /*!< this field configures the color correction matrix coefficient */ + uint32_t : 6; + } bit; + } CCM_COEF4; + + union { + __IOM uint32_t reg; /*!< ccm coef register 5 */ + + struct { + __IOM uint32_t CCM_BB : 13; /*!< this field configures the color correction matrix coefficient */ + uint32_t : 19; + } bit; + } CCM_COEF5; + + union { + __IOM uint32_t reg; /*!< bf pix2matrix ctrl */ + + struct { + __IOM uint32_t BF_TAIL_PIXEN_PULSE_TL : 8;/*!< matrix tail pixen low level threshold, should not to large to + prevent expanding to next frame, only reg_bf_tail_pixen_pulse_th!=0 + and reg_bf_tail_pixen_pulse_tl!=0 and reg_bf_tail_pixen_pulse_th + < reg_bf_tail_pixen_pulse_tl will enable tail pulse function */ + __IOM uint32_t BF_TAIL_PIXEN_PULSE_TH : 8;/*!< matrix tail pixen high level threshold, must < hnum-1, only + reg_bf_tail_pixen_pulse_th!=0 and reg_bf_tail_pixen_pulse_tl!=0 + and reg_bf_tail_pixen_pulse_th < reg_bf_tail_pixen_pulse_tl + will enable tail pulse function */ + __IOM uint32_t BF_PADDING_DATA : 8; /*!< this field configures bf matrix padding data */ + __IOM uint32_t BF_PADDING_MODE : 1; /*!< this bit configures the padding mode of bf matrix. 0: use pixel + in image to do padding 1: use reg_padding_data to do padding */ + uint32_t : 7; + } bit; + } BF_MATRIX_CTRL; + + union { + __IOM uint32_t reg; /*!< bf denoising level control register */ + + struct { + __IOM uint32_t SIGMA : 6; /*!< this field configures the bayer denoising level, valid data + from 2 to 20 */ + uint32_t : 26; + } bit; + } BF_SIGMA; + + union { + __IOM uint32_t reg; /*!< bf gau template register 0 */ + + struct { + __IOM uint32_t GAU_TEMPLATE21 : 4; /*!< this field configures index 21 of gausian template */ + __IOM uint32_t GAU_TEMPLATE20 : 4; /*!< this field configures index 20 of gausian template */ + __IOM uint32_t GAU_TEMPLATE12 : 4; /*!< this field configures index 12 of gausian template */ + __IOM uint32_t GAU_TEMPLATE11 : 4; /*!< this field configures index 11 of gausian template */ + __IOM uint32_t GAU_TEMPLATE10 : 4; /*!< this field configures index 10 of gausian template */ + __IOM uint32_t GAU_TEMPLATE02 : 4; /*!< this field configures index 02 of gausian template */ + __IOM uint32_t GAU_TEMPLATE01 : 4; /*!< this field configures index 01 of gausian template */ + __IOM uint32_t GAU_TEMPLATE00 : 4; /*!< this field configures index 00 of gausian template */ + } bit; + } BF_GAU0; + + union { + __IOM uint32_t reg; /*!< bf gau template register 1 */ + + struct { + __IOM uint32_t GAU_TEMPLATE22 : 4; /*!< this field configures index 22 of gausian template */ + uint32_t : 28; + } bit; + } BF_GAU1; + + union { + __IOM uint32_t reg; /*!< DPC mode control register */ + + struct { + __IOM uint32_t DPC_CHECK_EN : 1; /*!< this bit configures the check mode enable. 0: disable, 1: enable */ + __IOM uint32_t STA_EN : 1; /*!< this bit configures the sta dpc enable. 0: disable, 1: enable */ + __IOM uint32_t DYN_EN : 1; /*!< this bit configures the dyn dpc enable. 0: disable, 1: enable */ + __IOM uint32_t DPC_BLACK_EN : 1; /*!< this bit configures input image type select when in check mode, + 0: white img, 1: black img */ + __IOM uint32_t DPC_METHOD_SEL : 1; /*!< this bit configures dyn dpc method select. 0: simple method, + 1: hard method */ + __IOM uint32_t DPC_CHECK_OD_EN : 1; /*!< this bit configures output pixel data when in check mode or + not. 0: no data output, 1: data output */ + uint32_t : 26; + } bit; + } DPC_CTRL; + + union { + __IOM uint32_t reg; /*!< DPC parameter config register */ + + struct { + __IOM uint32_t DPC_THRESHOLD_L : 8; /*!< this bit configures the threshold to detect black img in check + mode, or the low threshold(use 8 bit 0~255) in dyn method + 0, or the low threshold factor (use 5 bit 10000-> 16/16, + 00001->1/16, 0/16~16/16) in dyn method 1 */ + __IOM uint32_t DPC_THRESHOLD_H : 8; /*!< this bit configures the threshold to detect white img in check + mode, or the high threshold(use 8 bit 0~255) in dyn method + 0, or the high threshold factor (use 5 bit 10000-> 16/16, + 00001->1/16, 0/16~16/16) in dyn method 1 */ + __IOM uint32_t DPC_FACTOR_DARK : 6; /*!< this field configures the dynamic correction method 1 dark factor */ + __IOM uint32_t DPC_FACTOR_BRIG : 6; /*!< this field configures the dynamic correction method 1 bright + factor */ + uint32_t : 4; + } bit; + } DPC_CONF; + + union { + __IOM uint32_t reg; /*!< dpc pix2matrix ctrl */ + + struct { + __IOM uint32_t DPC_TAIL_PIXEN_PULSE_TL : 8;/*!< matrix tail pixen low level threshold, should not to large to + prevent expanding to next frame, only reg_dpc_tail_pixen_pulse_th!=0 + and reg_dpc_tail_pixen_pulse_tl!=0 and reg_dpc_tail_pixen_pulse_th + < reg_dpc_tail_pixen_pulse_tl will enable tail pulse function */ + __IOM uint32_t DPC_TAIL_PIXEN_PULSE_TH : 8;/*!< matrix tail pixen high level threshold, must < hnum-1, only + reg_dpc_tail_pixen_pulse_th!=0 and reg_dpc_tail_pixen_pulse_tl!=0 + and reg_dpc_tail_pixen_pulse_th < reg_dpc_tail_pixen_pulse_tl + will enable tail pulse function */ + __IOM uint32_t DPC_PADDING_DATA : 8; /*!< this field configures dpc matrix padding data */ + __IOM uint32_t DPC_PADDING_MODE : 1; /*!< this bit configures the padding mode of dpc matrix. 0: use pixel + in image to do padding 1: use reg_padding_data to do padding */ + uint32_t : 7; + } bit; + } DPC_MATRIX_CTRL; + + union { + __IOM uint32_t reg; /*!< DPC dead-pix number register */ + + struct { + __IM uint32_t DPC_DEADPIX_CNT : 10; /*!< this field represents the dead pixel count */ + uint32_t : 22; + } bit; + } DPC_DEADPIX_CNT; + + union { + __IOM uint32_t reg; /*!< LUT command register */ + + struct { + __OM uint32_t LUT_ADDR : 12; /*!< this field configures the lut access addr, when select lsc lut, + [11:10]:00 sel gb_b lut, 01 sel r_gr lut */ + __OM uint32_t LUT_NUM : 4; /*!< this field configures the lut selection. 0000:LSC LUT 0001:DPC + LUT */ + __OM uint32_t LUT_CMD : 1; /*!< this bit configures the access event of lut. 0:rd 1: wr */ + uint32_t : 15; + } bit; + } LUT_CMD; + + union { + __IOM uint32_t reg; /*!< LUT write data register */ + + struct { + __IOM uint32_t LUT_WDATA : 32; /*!< this field configures the write data of lut. please initial + ISP_LUT_WDATA before write ISP_LUT_CMD register */ + } bit; + } LUT_WDATA; + + union { + __IOM uint32_t reg; /*!< LUT read data register */ + + struct { + __IM uint32_t LUT_RDATA : 32; /*!< this field represents the read data of lut. read ISP_LUT_RDATA + after write ISP_LUT_CMD register */ + } bit; + } LUT_RDATA; + + union { + __IOM uint32_t reg; /*!< LSC point in x-direction */ + + struct { + __IOM uint32_t LSC_XTABLESIZE : 5; /*!< this field configures lsc table size in x-direction */ + uint32_t : 27; + } bit; + } LSC_TABLESIZE; + + union { + __IOM uint32_t reg; /*!< demosaic pix2matrix ctrl */ + + struct { + __IOM uint32_t DEMOSAIC_TAIL_PIXEN_PULSE_TL : 8;/*!< matrix tail pixen low level threshold, should not to large to + prevent expanding to next frame, only reg_demosaic_tail_pixen_pulse_th!=0 + and reg_demosaic_tail_pixen_pulse_tl!=0 and reg_demosaic_tail_pixen_pulse + th < reg_demosaic_tail_pixen_pulse_tl will enable tail + pulse function */ + __IOM uint32_t DEMOSAIC_TAIL_PIXEN_PULSE_TH : 8;/*!< matrix tail pixen high level threshold, must < hnum-1, only + reg_demosaic_tail_pixen_pulse_th!=0 and reg_demosaic_tail_pixen_pulse_tl! + 0 and reg_demosaic_tail_pixen_pulse_th < reg_demosaic_tail_pixen_pulse_tl + will enable tail pulse function */ + __IOM uint32_t DEMOSAIC_PADDING_DATA : 8; /*!< this field configures demosaic matrix padding data */ + __IOM uint32_t DEMOSAIC_PADDING_MODE : 1; /*!< this bit configures the padding mode of demosaic matrix. 0: + use pixel in image to do padding 1: use reg_padding_data + to do padding */ + uint32_t : 7; + } bit; + } DEMOSAIC_MATRIX_CTRL; + + union { + __IOM uint32_t reg; /*!< demosaic gradient select ratio */ + + struct { + __IOM uint32_t DEMOSAIC_GRAD_RATIO : 6; /*!< this field configures demosaic gradient select ratio */ + uint32_t : 26; + } bit; + } DEMOSAIC_GRAD_RATIO; + + union { + __IOM uint32_t reg; /*!< median pix2matrix ctrl */ + + struct { + __IOM uint32_t MEDIAN_PADDING_DATA : 8; /*!< this field configures median matrix padding data */ + __IOM uint32_t MEDIAN_PADDING_MODE : 1; /*!< this bit configures the padding mode of median matrix. 0: use + pixel in image to do padding 1: use reg_padding_data to + do padding */ + uint32_t : 23; + } bit; + } MEDIAN_MATRIX_CTRL; + + union { + __IOM uint32_t reg; /*!< raw interrupt register */ + + struct { + __IM uint32_t ISP_DATA_TYPE_ERR_INT_RAW : 1;/*!< the raw interrupt status of input data type error. isp only + support RGB bayer data type, other type will report type_err_int */ + __IM uint32_t ISP_ASYNC_FIFO_OVF_INT_RAW : 1;/*!< the raw interrupt status of isp input fifo overflow */ + __IM uint32_t ISP_BUF_FULL_INT_RAW : 1; /*!< the raw interrupt status of isp input buffer full */ + __IM uint32_t ISP_HVNUM_SETTING_ERR_INT_RAW : 1;/*!< the raw interrupt status of hnum and vnum setting format error */ + __IM uint32_t ISP_DATA_TYPE_SETTING_ERR_INT_RAW : 1;/*!< the raw interrupt status of setting invalid reg_data_type */ + __IM uint32_t ISP_MIPI_HNUM_UNMATCH_INT_RAW : 1;/*!< the raw interrupt status of hnum setting unmatch with mipi input */ + __IM uint32_t DPC_CHECK_DONE_INT_RAW : 1;/*!< the raw interrupt status of dpc check done */ + __IM uint32_t GAMMA_XCOORD_ERR_INT_RAW : 1;/*!< the raw interrupt status of gamma setting error. it report the + sum of the lengths represented by reg_gamma_x00~x0F isn't + equal to 256 */ + __IM uint32_t AE_MONITOR_INT_RAW : 1; /*!< the raw interrupt status of ae monitor */ + __IM uint32_t AE_FRAME_DONE_INT_RAW : 1; /*!< the raw interrupt status of ae. */ + __IM uint32_t AF_FDONE_INT_RAW : 1; /*!< the raw interrupt status of af statistic. when auto_update enable, + each frame done will send one int pulse when manual_update, + each time when write 1 to reg_manual_update will send a + int pulse when next frame done */ + __IM uint32_t AF_ENV_INT_RAW : 1; /*!< the raw interrupt status of af monitor. send a int pulse when + env_det function enabled and environment changes detected */ + __IM uint32_t AWB_FDONE_INT_RAW : 1; /*!< the raw interrupt status of awb. send a int pulse when statistic + of one awb frame done */ + __IM uint32_t HIST_FDONE_INT_RAW : 1; /*!< the raw interrupt status of histogram. send a int pulse when + statistic of one frame histogram done */ + __IM uint32_t FRAME_INT_RAW : 1; /*!< the raw interrupt status of isp frame end */ + __IM uint32_t BLC_FRAME_INT_RAW : 1; /*!< the raw interrupt status of blc frame done */ + __IM uint32_t LSC_FRAME_INT_RAW : 1; /*!< the raw interrupt status of lsc frame done */ + __IM uint32_t DPC_FRAME_INT_RAW : 1; /*!< the raw interrupt status of dpc frame done */ + __IM uint32_t BF_FRAME_INT_RAW : 1; /*!< the raw interrupt status of bf frame done */ + __IM uint32_t DEMOSAIC_FRAME_INT_RAW : 1;/*!< the raw interrupt status of demosaic frame done */ + __IM uint32_t MEDIAN_FRAME_INT_RAW : 1; /*!< the raw interrupt status of median frame done */ + __IM uint32_t CCM_FRAME_INT_RAW : 1; /*!< the raw interrupt status of ccm frame done */ + __IM uint32_t GAMMA_FRAME_INT_RAW : 1; /*!< the raw interrupt status of gamma frame done */ + __IM uint32_t RGB2YUV_FRAME_INT_RAW : 1; /*!< the raw interrupt status of rgb2yuv frame done */ + __IM uint32_t SHARP_FRAME_INT_RAW : 1; /*!< the raw interrupt status of sharp frame done */ + __IM uint32_t COLOR_FRAME_INT_RAW : 1; /*!< the raw interrupt status of color frame done */ + __IM uint32_t YUV2RGB_FRAME_INT_RAW : 1; /*!< the raw interrupt status of yuv2rgb frame done */ + __IM uint32_t TAIL_IDI_FRAME_INT_RAW : 1;/*!< the raw interrupt status of isp_tail idi frame_end */ + __IM uint32_t HEADER_IDI_FRAME_INT_RAW : 1;/*!< the raw interrupt status of real input frame end of isp_input */ + uint32_t : 3; + } bit; + } INT_RAW; + + union { + __IOM uint32_t reg; /*!< masked interrupt register */ + + struct { + __IM uint32_t ISP_DATA_TYPE_ERR_INT_ST : 1;/*!< the masked interrupt status of input data type error */ + __IM uint32_t ISP_ASYNC_FIFO_OVF_INT_ST : 1;/*!< the masked interrupt status of isp input fifo overflow */ + __IM uint32_t ISP_BUF_FULL_INT_ST : 1; /*!< the masked interrupt status of isp input buffer full */ + __IM uint32_t ISP_HVNUM_SETTING_ERR_INT_ST : 1;/*!< the masked interrupt status of hnum and vnum setting format + error */ + __IM uint32_t ISP_DATA_TYPE_SETTING_ERR_INT_ST : 1;/*!< the masked interrupt status of setting invalid reg_data_type */ + __IM uint32_t ISP_MIPI_HNUM_UNMATCH_INT_ST : 1;/*!< the masked interrupt status of hnum setting unmatch with mipi + input */ + __IM uint32_t DPC_CHECK_DONE_INT_ST : 1; /*!< the masked interrupt status of dpc check done */ + __IM uint32_t GAMMA_XCOORD_ERR_INT_ST : 1;/*!< the masked interrupt status of gamma setting error */ + __IM uint32_t AE_MONITOR_INT_ST : 1; /*!< the masked interrupt status of ae monitor */ + __IM uint32_t AE_FRAME_DONE_INT_ST : 1; /*!< the masked interrupt status of ae */ + __IM uint32_t AF_FDONE_INT_ST : 1; /*!< the masked interrupt status of af statistic */ + __IM uint32_t AF_ENV_INT_ST : 1; /*!< the masked interrupt status of af monitor */ + __IM uint32_t AWB_FDONE_INT_ST : 1; /*!< the masked interrupt status of awb */ + __IM uint32_t HIST_FDONE_INT_ST : 1; /*!< the masked interrupt status of histogram */ + __IM uint32_t FRAME_INT_ST : 1; /*!< the masked interrupt status of isp frame end */ + __IM uint32_t BLC_FRAME_INT_ST : 1; /*!< the masked interrupt status of blc frame done */ + __IM uint32_t LSC_FRAME_INT_ST : 1; /*!< the masked interrupt status of lsc frame done */ + __IM uint32_t DPC_FRAME_INT_ST : 1; /*!< the masked interrupt status of dpc frame done */ + __IM uint32_t BF_FRAME_INT_ST : 1; /*!< the masked interrupt status of bf frame done */ + __IM uint32_t DEMOSAIC_FRAME_INT_ST : 1; /*!< the masked interrupt status of demosaic frame done */ + __IM uint32_t MEDIAN_FRAME_INT_ST : 1; /*!< the masked interrupt status of median frame done */ + __IM uint32_t CCM_FRAME_INT_ST : 1; /*!< the masked interrupt status of ccm frame done */ + __IM uint32_t GAMMA_FRAME_INT_ST : 1; /*!< the masked interrupt status of gamma frame done */ + __IM uint32_t RGB2YUV_FRAME_INT_ST : 1; /*!< the masked interrupt status of rgb2yuv frame done */ + __IM uint32_t SHARP_FRAME_INT_ST : 1; /*!< the masked interrupt status of sharp frame done */ + __IM uint32_t COLOR_FRAME_INT_ST : 1; /*!< the masked interrupt status of color frame done */ + __IM uint32_t YUV2RGB_FRAME_INT_ST : 1; /*!< the masked interrupt status of yuv2rgb frame done */ + __IM uint32_t TAIL_IDI_FRAME_INT_ST : 1; /*!< the masked interrupt status of isp_tail idi frame_end */ + __IM uint32_t HEADER_IDI_FRAME_INT_ST : 1;/*!< the masked interrupt status of real input frame end of isp_input */ + uint32_t : 3; + } bit; + } INT_ST; + + union { + __IOM uint32_t reg; /*!< interrupt enable register */ + + struct { + __IOM uint32_t ISP_DATA_TYPE_ERR_INT_ENA : 1;/*!< write 1 to enable input data type error */ + __IOM uint32_t ISP_ASYNC_FIFO_OVF_INT_ENA : 1;/*!< write 1 to enable isp input fifo overflow */ + __IOM uint32_t ISP_BUF_FULL_INT_ENA : 1; /*!< write 1 to enable isp input buffer full */ + __IOM uint32_t ISP_HVNUM_SETTING_ERR_INT_ENA : 1;/*!< write 1 to enable hnum and vnum setting format error */ + __IOM uint32_t ISP_DATA_TYPE_SETTING_ERR_INT_ENA : 1;/*!< write 1 to enable setting invalid reg_data_type */ + __IOM uint32_t ISP_MIPI_HNUM_UNMATCH_INT_ENA : 1;/*!< write 1 to enable hnum setting unmatch with mipi input */ + __IOM uint32_t DPC_CHECK_DONE_INT_ENA : 1;/*!< write 1 to enable dpc check done */ + __IOM uint32_t GAMMA_XCOORD_ERR_INT_ENA : 1;/*!< write 1 to enable gamma setting error */ + __IOM uint32_t AE_MONITOR_INT_ENA : 1; /*!< write 1 to enable ae monitor */ + __IOM uint32_t AE_FRAME_DONE_INT_ENA : 1; /*!< write 1 to enable ae */ + __IOM uint32_t AF_FDONE_INT_ENA : 1; /*!< write 1 to enable af statistic */ + __IOM uint32_t AF_ENV_INT_ENA : 1; /*!< write 1 to enable af monitor */ + __IOM uint32_t AWB_FDONE_INT_ENA : 1; /*!< write 1 to enable awb */ + __IOM uint32_t HIST_FDONE_INT_ENA : 1; /*!< write 1 to enable histogram */ + __IOM uint32_t FRAME_INT_ENA : 1; /*!< write 1 to enable isp frame end */ + __IOM uint32_t BLC_FRAME_INT_ENA : 1; /*!< write 1 to enable blc frame done */ + __IOM uint32_t LSC_FRAME_INT_ENA : 1; /*!< write 1 to enable lsc frame done */ + __IOM uint32_t DPC_FRAME_INT_ENA : 1; /*!< write 1 to enable dpc frame done */ + __IOM uint32_t BF_FRAME_INT_ENA : 1; /*!< write 1 to enable bf frame done */ + __IOM uint32_t DEMOSAIC_FRAME_INT_ENA : 1;/*!< write 1 to enable demosaic frame done */ + __IOM uint32_t MEDIAN_FRAME_INT_ENA : 1; /*!< write 1 to enable median frame done */ + __IOM uint32_t CCM_FRAME_INT_ENA : 1; /*!< write 1 to enable ccm frame done */ + __IOM uint32_t GAMMA_FRAME_INT_ENA : 1; /*!< write 1 to enable gamma frame done */ + __IOM uint32_t RGB2YUV_FRAME_INT_ENA : 1; /*!< write 1 to enable rgb2yuv frame done */ + __IOM uint32_t SHARP_FRAME_INT_ENA : 1; /*!< write 1 to enable sharp frame done */ + __IOM uint32_t COLOR_FRAME_INT_ENA : 1; /*!< write 1 to enable color frame done */ + __IOM uint32_t YUV2RGB_FRAME_INT_ENA : 1; /*!< write 1 to enable yuv2rgb frame done */ + __IOM uint32_t TAIL_IDI_FRAME_INT_ENA : 1;/*!< write 1 to enable isp_tail idi frame_end */ + __IOM uint32_t HEADER_IDI_FRAME_INT_ENA : 1;/*!< write 1 to enable real input frame end of isp_input */ + uint32_t : 3; + } bit; + } INT_ENA; + + union { + __IOM uint32_t reg; /*!< interrupt clear register */ + + struct { + __OM uint32_t ISP_DATA_TYPE_ERR_INT_CLR : 1;/*!< write 1 to clear input data type error */ + __OM uint32_t ISP_ASYNC_FIFO_OVF_INT_CLR : 1;/*!< write 1 to clear isp input fifo overflow */ + __OM uint32_t ISP_BUF_FULL_INT_CLR : 1; /*!< write 1 to clear isp input buffer full */ + __OM uint32_t ISP_HVNUM_SETTING_ERR_INT_CLR : 1;/*!< write 1 to clear hnum and vnum setting format error */ + __OM uint32_t ISP_DATA_TYPE_SETTING_ERR_INT_CLR : 1;/*!< write 1 to clear setting invalid reg_data_type */ + __OM uint32_t ISP_MIPI_HNUM_UNMATCH_INT_CLR : 1;/*!< write 1 to clear hnum setting unmatch with mipi input */ + __OM uint32_t DPC_CHECK_DONE_INT_CLR : 1;/*!< write 1 to clear dpc check done */ + __OM uint32_t GAMMA_XCOORD_ERR_INT_CLR : 1;/*!< write 1 to clear gamma setting error */ + __OM uint32_t AE_MONITOR_INT_CLR : 1; /*!< write 1 to clear ae monitor */ + __OM uint32_t AE_FRAME_DONE_INT_CLR : 1; /*!< write 1 to clear ae */ + __OM uint32_t AF_FDONE_INT_CLR : 1; /*!< write 1 to clear af statistic */ + __OM uint32_t AF_ENV_INT_CLR : 1; /*!< write 1 to clear af monitor */ + __OM uint32_t AWB_FDONE_INT_CLR : 1; /*!< write 1 to clear awb */ + __OM uint32_t HIST_FDONE_INT_CLR : 1; /*!< write 1 to clear histogram */ + __OM uint32_t FRAME_INT_CLR : 1; /*!< write 1 to clear isp frame end */ + __OM uint32_t BLC_FRAME_INT_CLR : 1; /*!< write 1 to clear blc frame done */ + __OM uint32_t LSC_FRAME_INT_CLR : 1; /*!< write 1 to clear lsc frame done */ + __OM uint32_t DPC_FRAME_INT_CLR : 1; /*!< write 1 to clear dpc frame done */ + __OM uint32_t BF_FRAME_INT_CLR : 1; /*!< write 1 to clear bf frame done */ + __OM uint32_t DEMOSAIC_FRAME_INT_CLR : 1;/*!< write 1 to clear demosaic frame done */ + __OM uint32_t MEDIAN_FRAME_INT_CLR : 1; /*!< write 1 to clear median frame done */ + __OM uint32_t CCM_FRAME_INT_CLR : 1; /*!< write 1 to clear ccm frame done */ + __OM uint32_t GAMMA_FRAME_INT_CLR : 1; /*!< write 1 to clear gamma frame done */ + __OM uint32_t RGB2YUV_FRAME_INT_CLR : 1; /*!< write 1 to clear rgb2yuv frame done */ + __OM uint32_t SHARP_FRAME_INT_CLR : 1; /*!< write 1 to clear sharp frame done */ + __OM uint32_t COLOR_FRAME_INT_CLR : 1; /*!< write 1 to clear color frame done */ + __OM uint32_t YUV2RGB_FRAME_INT_CLR : 1; /*!< write 1 to clear yuv2rgb frame done */ + __OM uint32_t TAIL_IDI_FRAME_INT_CLR : 1;/*!< write 1 to clear isp_tail idi frame_end */ + __OM uint32_t HEADER_IDI_FRAME_INT_CLR : 1;/*!< write 1 to clear real input frame end of isp_input */ + uint32_t : 3; + } bit; + } INT_CLR; + + union { + __IOM uint32_t reg; /*!< gamma control register */ + + struct { + __IOM uint32_t GAMMA_UPDATE : 1; /*!< Indicates that gamma register configuration is complete */ + __IOM uint32_t GAMMA_B_LAST_CORRECT : 1; /*!< this bit configures enable of last b segment correcction. 0: + disable, 1: enable */ + __IOM uint32_t GAMMA_G_LAST_CORRECT : 1; /*!< this bit configures enable of last g segment correcction. 0: + disable, 1: enable */ + __IOM uint32_t GAMMA_R_LAST_CORRECT : 1; /*!< this bit configures enable of last r segment correcction. 0: + disable, 1: enable */ + uint32_t : 28; + } bit; + } GAMMA_CTRL; + + union { + __IOM uint32_t reg; /*!< point of Y-axis of r channel gamma curve register 1 */ + + struct { + __IOM uint32_t GAMMA_R_Y03 : 8; /*!< this field configures the point 3 of Y-axis of r channel gamma + curve */ + __IOM uint32_t GAMMA_R_Y02 : 8; /*!< this field configures the point 2 of Y-axis of r channel gamma + curve */ + __IOM uint32_t GAMMA_R_Y01 : 8; /*!< this field configures the point 1 of Y-axis of r channel gamma + curve */ + __IOM uint32_t GAMMA_R_Y00 : 8; /*!< this field configures the point 0 of Y-axis of r channel gamma + curve */ + } bit; + } GAMMA_RY1; + + union { + __IOM uint32_t reg; /*!< point of Y-axis of r channel gamma curve register 2 */ + + struct { + __IOM uint32_t GAMMA_R_Y07 : 8; /*!< this field configures the point 7 of Y-axis of r channel gamma + curve */ + __IOM uint32_t GAMMA_R_Y06 : 8; /*!< this field configures the point 6 of Y-axis of r channel gamma + curve */ + __IOM uint32_t GAMMA_R_Y05 : 8; /*!< this field configures the point 5 of Y-axis of r channel gamma + curve */ + __IOM uint32_t GAMMA_R_Y04 : 8; /*!< this field configures the point 4 of Y-axis of r channel gamma + curve */ + } bit; + } GAMMA_RY2; + + union { + __IOM uint32_t reg; /*!< point of Y-axis of r channel gamma curve register 3 */ + + struct { + __IOM uint32_t GAMMA_R_Y0B : 8; /*!< this field configures the point 11 of Y-axis of r channel gamma + curve */ + __IOM uint32_t GAMMA_R_Y0A : 8; /*!< this field configures the point 10 of Y-axis of r channel gamma + curve */ + __IOM uint32_t GAMMA_R_Y09 : 8; /*!< this field configures the point 9 of Y-axis of r channel gamma + curve */ + __IOM uint32_t GAMMA_R_Y08 : 8; /*!< this field configures the point 8 of Y-axis of r channel gamma + curve */ + } bit; + } GAMMA_RY3; + + union { + __IOM uint32_t reg; /*!< point of Y-axis of r channel gamma curve register 4 */ + + struct { + __IOM uint32_t GAMMA_R_Y0F : 8; /*!< this field configures the point 15 of Y-axis of r channel gamma + curve */ + __IOM uint32_t GAMMA_R_Y0E : 8; /*!< this field configures the point 14 of Y-axis of r channel gamma + curve */ + __IOM uint32_t GAMMA_R_Y0D : 8; /*!< this field configures the point 13 of Y-axis of r channel gamma + curve */ + __IOM uint32_t GAMMA_R_Y0C : 8; /*!< this field configures the point 12 of Y-axis of r channel gamma + curve */ + } bit; + } GAMMA_RY4; + + union { + __IOM uint32_t reg; /*!< point of Y-axis of g channel gamma curve register 1 */ + + struct { + __IOM uint32_t GAMMA_G_Y03 : 8; /*!< this field configures the point 3 of Y-axis of g channel gamma + curve */ + __IOM uint32_t GAMMA_G_Y02 : 8; /*!< this field configures the point 2 of Y-axis of g channel gamma + curve */ + __IOM uint32_t GAMMA_G_Y01 : 8; /*!< this field configures the point 1 of Y-axis of g channel gamma + curve */ + __IOM uint32_t GAMMA_G_Y00 : 8; /*!< this field configures the point 0 of Y-axis of g channel gamma + curve */ + } bit; + } GAMMA_GY1; + + union { + __IOM uint32_t reg; /*!< point of Y-axis of g channel gamma curve register 2 */ + + struct { + __IOM uint32_t GAMMA_G_Y07 : 8; /*!< this field configures the point 7 of Y-axis of g channel gamma + curve */ + __IOM uint32_t GAMMA_G_Y06 : 8; /*!< this field configures the point 6 of Y-axis of g channel gamma + curve */ + __IOM uint32_t GAMMA_G_Y05 : 8; /*!< this field configures the point 5 of Y-axis of g channel gamma + curve */ + __IOM uint32_t GAMMA_G_Y04 : 8; /*!< this field configures the point 4 of Y-axis of g channel gamma + curve */ + } bit; + } GAMMA_GY2; + + union { + __IOM uint32_t reg; /*!< point of Y-axis of g channel gamma curve register 3 */ + + struct { + __IOM uint32_t GAMMA_G_Y0B : 8; /*!< this field configures the point 11 of Y-axis of g channel gamma + curve */ + __IOM uint32_t GAMMA_G_Y0A : 8; /*!< this field configures the point 10 of Y-axis of g channel gamma + curve */ + __IOM uint32_t GAMMA_G_Y09 : 8; /*!< this field configures the point 9 of Y-axis of g channel gamma + curve */ + __IOM uint32_t GAMMA_G_Y08 : 8; /*!< this field configures the point 8 of Y-axis of g channel gamma + curve */ + } bit; + } GAMMA_GY3; + + union { + __IOM uint32_t reg; /*!< point of Y-axis of g channel gamma curve register 4 */ + + struct { + __IOM uint32_t GAMMA_G_Y0F : 8; /*!< this field configures the point 15 of Y-axis of g channel gamma + curve */ + __IOM uint32_t GAMMA_G_Y0E : 8; /*!< this field configures the point 14 of Y-axis of g channel gamma + curve */ + __IOM uint32_t GAMMA_G_Y0D : 8; /*!< this field configures the point 13 of Y-axis of g channel gamma + curve */ + __IOM uint32_t GAMMA_G_Y0C : 8; /*!< this field configures the point 12 of Y-axis of g channel gamma + curve */ + } bit; + } GAMMA_GY4; + + union { + __IOM uint32_t reg; /*!< point of Y-axis of b channel gamma curve register 1 */ + + struct { + __IOM uint32_t GAMMA_B_Y03 : 8; /*!< this field configures the point 3 of Y-axis of b channel gamma + curve */ + __IOM uint32_t GAMMA_B_Y02 : 8; /*!< this field configures the point 2 of Y-axis of b channel gamma + curve */ + __IOM uint32_t GAMMA_B_Y01 : 8; /*!< this field configures the point 1 of Y-axis of b channel gamma + curve */ + __IOM uint32_t GAMMA_B_Y00 : 8; /*!< this field configures the point 0 of Y-axis of b channel gamma + curve */ + } bit; + } GAMMA_BY1; + + union { + __IOM uint32_t reg; /*!< point of Y-axis of b channel gamma curve register 2 */ + + struct { + __IOM uint32_t GAMMA_B_Y07 : 8; /*!< this field configures the point 7 of Y-axis of b channel gamma + curve */ + __IOM uint32_t GAMMA_B_Y06 : 8; /*!< this field configures the point 6 of Y-axis of b channel gamma + curve */ + __IOM uint32_t GAMMA_B_Y05 : 8; /*!< this field configures the point 5 of Y-axis of b channel gamma + curve */ + __IOM uint32_t GAMMA_B_Y04 : 8; /*!< this field configures the point 4 of Y-axis of b channel gamma + curve */ + } bit; + } GAMMA_BY2; + + union { + __IOM uint32_t reg; /*!< point of Y-axis of b channel gamma curve register 3 */ + + struct { + __IOM uint32_t GAMMA_B_Y0B : 8; /*!< this field configures the point 11 of Y-axis of b channel gamma + curve */ + __IOM uint32_t GAMMA_B_Y0A : 8; /*!< this field configures the point 10 of Y-axis of b channel gamma + curve */ + __IOM uint32_t GAMMA_B_Y09 : 8; /*!< this field configures the point 9 of Y-axis of b channel gamma + curve */ + __IOM uint32_t GAMMA_B_Y08 : 8; /*!< this field configures the point 8 of Y-axis of b channel gamma + curve */ + } bit; + } GAMMA_BY3; + + union { + __IOM uint32_t reg; /*!< point of Y-axis of b channel gamma curve register 4 */ + + struct { + __IOM uint32_t GAMMA_B_Y0F : 8; /*!< this field configures the point 15 of Y-axis of b channel gamma + curve */ + __IOM uint32_t GAMMA_B_Y0E : 8; /*!< this field configures the point 14 of Y-axis of b channel gamma + curve */ + __IOM uint32_t GAMMA_B_Y0D : 8; /*!< this field configures the point 13 of Y-axis of b channel gamma + curve */ + __IOM uint32_t GAMMA_B_Y0C : 8; /*!< this field configures the point 12 of Y-axis of b channel gamma + curve */ + } bit; + } GAMMA_BY4; + + union { + __IOM uint32_t reg; /*!< point of X-axis of r channel gamma curve register 1 */ + + struct { + __IOM uint32_t GAMMA_R_X07 : 3; /*!< this field configures the point 7 of X-axis of r channel gamma + curve, it represents the power of the distance from the + previous point */ + __IOM uint32_t GAMMA_R_X06 : 3; /*!< this field configures the point 6 of X-axis of r channel gamma + curve, it represents the power of the distance from the + previous point */ + __IOM uint32_t GAMMA_R_X05 : 3; /*!< this field configures the point 5 of X-axis of r channel gamma + curve, it represents the power of the distance from the + previous point */ + __IOM uint32_t GAMMA_R_X04 : 3; /*!< this field configures the point 4 of X-axis of r channel gamma + curve, it represents the power of the distance from the + previous point */ + __IOM uint32_t GAMMA_R_X03 : 3; /*!< this field configures the point 3 of X-axis of r channel gamma + curve, it represents the power of the distance from the + previous point */ + __IOM uint32_t GAMMA_R_X02 : 3; /*!< this field configures the point 2 of X-axis of r channel gamma + curve, it represents the power of the distance from the + previous point */ + __IOM uint32_t GAMMA_R_X01 : 3; /*!< this field configures the point 1 of X-axis of r channel gamma + curve, it represents the power of the distance from the + previous point */ + __IOM uint32_t GAMMA_R_X00 : 3; /*!< this field configures the point 0 of X-axis of r channel gamma + curve, it represents the power of the distance from the + previous point */ + uint32_t : 8; + } bit; + } GAMMA_RX1; + + union { + __IOM uint32_t reg; /*!< point of X-axis of r channel gamma curve register 2 */ + + struct { + __IOM uint32_t GAMMA_R_X0F : 3; /*!< this field configures the point 15 of X-axis of r channel gamma + curve, it represents the power of the distance from the + previous point */ + __IOM uint32_t GAMMA_R_X0E : 3; /*!< this field configures the point 14 of X-axis of r channel gamma + curve, it represents the power of the distance from the + previous point */ + __IOM uint32_t GAMMA_R_X0D : 3; /*!< this field configures the point 13 of X-axis of r channel gamma + curve, it represents the power of the distance from the + previous point */ + __IOM uint32_t GAMMA_R_X0C : 3; /*!< this field configures the point 12 of X-axis of r channel gamma + curve, it represents the power of the distance from the + previous point */ + __IOM uint32_t GAMMA_R_X0B : 3; /*!< this field configures the point 11 of X-axis of r channel gamma + curve, it represents the power of the distance from the + previous point */ + __IOM uint32_t GAMMA_R_X0A : 3; /*!< this field configures the point 10 of X-axis of r channel gamma + curve, it represents the power of the distance from the + previous point */ + __IOM uint32_t GAMMA_R_X09 : 3; /*!< this field configures the point 9 of X-axis of r channel gamma + curve, it represents the power of the distance from the + previous point */ + __IOM uint32_t GAMMA_R_X08 : 3; /*!< this field configures the point 8 of X-axis of r channel gamma + curve, it represents the power of the distance from the + previous point */ + uint32_t : 8; + } bit; + } GAMMA_RX2; + + union { + __IOM uint32_t reg; /*!< point of X-axis of g channel gamma curve register 1 */ + + struct { + __IOM uint32_t GAMMA_G_X07 : 3; /*!< this field configures the point 7 of X-axis of g channel gamma + curve, it represents the power of the distance from the + previous point */ + __IOM uint32_t GAMMA_G_X06 : 3; /*!< this field configures the point 6 of X-axis of g channel gamma + curve, it represents the power of the distance from the + previous point */ + __IOM uint32_t GAMMA_G_X05 : 3; /*!< this field configures the point 5 of X-axis of g channel gamma + curve, it represents the power of the distance from the + previous point */ + __IOM uint32_t GAMMA_G_X04 : 3; /*!< this field configures the point 4 of X-axis of g channel gamma + curve, it represents the power of the distance from the + previous point */ + __IOM uint32_t GAMMA_G_X03 : 3; /*!< this field configures the point 3 of X-axis of g channel gamma + curve, it represents the power of the distance from the + previous point */ + __IOM uint32_t GAMMA_G_X02 : 3; /*!< this field configures the point 2 of X-axis of g channel gamma + curve, it represents the power of the distance from the + previous point */ + __IOM uint32_t GAMMA_G_X01 : 3; /*!< this field configures the point 1 of X-axis of g channel gamma + curve, it represents the power of the distance from the + previous point */ + __IOM uint32_t GAMMA_G_X00 : 3; /*!< this field configures the point 0 of X-axis of g channel gamma + curve, it represents the power of the distance from the + previous point */ + uint32_t : 8; + } bit; + } GAMMA_GX1; + + union { + __IOM uint32_t reg; /*!< point of X-axis of g channel gamma curve register 2 */ + + struct { + __IOM uint32_t GAMMA_G_X0F : 3; /*!< this field configures the point 15 of X-axis of g channel gamma + curve, it represents the power of the distance from the + previous point */ + __IOM uint32_t GAMMA_G_X0E : 3; /*!< this field configures the point 14 of X-axis of g channel gamma + curve, it represents the power of the distance from the + previous point */ + __IOM uint32_t GAMMA_G_X0D : 3; /*!< this field configures the point 13 of X-axis of g channel gamma + curve, it represents the power of the distance from the + previous point */ + __IOM uint32_t GAMMA_G_X0C : 3; /*!< this field configures the point 12 of X-axis of g channel gamma + curve, it represents the power of the distance from the + previous point */ + __IOM uint32_t GAMMA_G_X0B : 3; /*!< this field configures the point 11 of X-axis of g channel gamma + curve, it represents the power of the distance from the + previous point */ + __IOM uint32_t GAMMA_G_X0A : 3; /*!< this field configures the point 10 of X-axis of g channel gamma + curve, it represents the power of the distance from the + previous point */ + __IOM uint32_t GAMMA_G_X09 : 3; /*!< this field configures the point 9 of X-axis of g channel gamma + curve, it represents the power of the distance from the + previous point */ + __IOM uint32_t GAMMA_G_X08 : 3; /*!< this field configures the point 8 of X-axis of g channel gamma + curve, it represents the power of the distance from the + previous point */ + uint32_t : 8; + } bit; + } GAMMA_GX2; + + union { + __IOM uint32_t reg; /*!< point of X-axis of b channel gamma curve register 1 */ + + struct { + __IOM uint32_t GAMMA_B_X07 : 3; /*!< this field configures the point 7 of X-axis of b channel gamma + curve, it represents the power of the distance from the + previous point */ + __IOM uint32_t GAMMA_B_X06 : 3; /*!< this field configures the point 6 of X-axis of b channel gamma + curve, it represents the power of the distance from the + previous point */ + __IOM uint32_t GAMMA_B_X05 : 3; /*!< this field configures the point 5 of X-axis of b channel gamma + curve, it represents the power of the distance from the + previous point */ + __IOM uint32_t GAMMA_B_X04 : 3; /*!< this field configures the point 4 of X-axis of b channel gamma + curve, it represents the power of the distance from the + previous point */ + __IOM uint32_t GAMMA_B_X03 : 3; /*!< this field configures the point 3 of X-axis of b channel gamma + curve, it represents the power of the distance from the + previous point */ + __IOM uint32_t GAMMA_B_X02 : 3; /*!< this field configures the point 2 of X-axis of b channel gamma + curve, it represents the power of the distance from the + previous point */ + __IOM uint32_t GAMMA_B_X01 : 3; /*!< this field configures the point 1 of X-axis of b channel gamma + curve, it represents the power of the distance from the + previous point */ + __IOM uint32_t GAMMA_B_X00 : 3; /*!< this field configures the point 0 of X-axis of b channel gamma + curve, it represents the power of the distance from the + previous point */ + uint32_t : 8; + } bit; + } GAMMA_BX1; + + union { + __IOM uint32_t reg; /*!< point of X-axis of b channel gamma curve register 2 */ + + struct { + __IOM uint32_t GAMMA_B_X0F : 3; /*!< this field configures the point 15 of X-axis of b channel gamma + curve, it represents the power of the distance from the + previous point */ + __IOM uint32_t GAMMA_B_X0E : 3; /*!< this field configures the point 14 of X-axis of b channel gamma + curve, it represents the power of the distance from the + previous point */ + __IOM uint32_t GAMMA_B_X0D : 3; /*!< this field configures the point 13 of X-axis of b channel gamma + curve, it represents the power of the distance from the + previous point */ + __IOM uint32_t GAMMA_B_X0C : 3; /*!< this field configures the point 12 of X-axis of b channel gamma + curve, it represents the power of the distance from the + previous point */ + __IOM uint32_t GAMMA_B_X0B : 3; /*!< this field configures the point 11 of X-axis of b channel gamma + curve, it represents the power of the distance from the + previous point */ + __IOM uint32_t GAMMA_B_X0A : 3; /*!< this field configures the point 10 of X-axis of b channel gamma + curve, it represents the power of the distance from the + previous point */ + __IOM uint32_t GAMMA_B_X09 : 3; /*!< this field configures the point 9 of X-axis of b channel gamma + curve, it represents the power of the distance from the + previous point */ + __IOM uint32_t GAMMA_B_X08 : 3; /*!< this field configures the point 8 of X-axis of b channel gamma + curve, it represents the power of the distance from the + previous point */ + uint32_t : 8; + } bit; + } GAMMA_BX2; + + union { + __IOM uint32_t reg; /*!< ae control register */ + + struct { + __OM uint32_t AE_UPDATE : 1; /*!< write 1 to this bit triggers one statistic event */ + __IOM uint32_t AE_SELECT : 1; /*!< this field configures ae input data source, 0: data from median, + 1: data from gama */ + uint32_t : 30; + } bit; + } AE_CTRL; + + union { + __IOM uint32_t reg; /*!< ae monitor control register */ + + struct { + __IOM uint32_t TL : 8; /*!< this field configures the lower lum threshold of ae monitor */ + __IOM uint32_t TH : 8; /*!< this field configures the higher lum threshold of ae monitor */ + __IOM uint32_t PERIOD : 6; /*!< this field cnfigures ae monitor frame period */ + uint32_t : 10; + } bit; + } AE_MONITOR; + + union { + __IOM uint32_t reg; /*!< ae window register in x-direction */ + + struct { + __IOM uint32_t AE_X_BSIZE : 11; /*!< this field configures every block x size */ + __IOM uint32_t AE_X_START : 11; /*!< this field configures first block start x address */ + uint32_t : 10; + } bit; + } AE_BX; + + union { + __IOM uint32_t reg; /*!< ae window register in y-direction */ + + struct { + __IOM uint32_t AE_Y_BSIZE : 11; /*!< this field configures every block y size */ + __IOM uint32_t AE_Y_START : 11; /*!< this field configures first block start y address */ + uint32_t : 10; + } bit; + } AE_BY; + + union { + __IOM uint32_t reg; /*!< ae sub-window pix num register */ + + struct { + __IOM uint32_t AE_SUBWIN_PIXNUM : 17; /*!< this field configures the pixel number of each sub win */ + uint32_t : 15; + } bit; + } AE_WINPIXNUM; + + union { + __IOM uint32_t reg; /*!< reciprocal of ae sub-window pixel number */ + + struct { + __IOM uint32_t AE_SUBWIN_RECIP : 20; /*!< this field configures the reciprocal of each subwin_pixnum, + 20bit fraction */ + uint32_t : 12; + } bit; + } AE_WIN_RECIPROCAL; + + union { + __IOM uint32_t reg; /*!< ae statistic result register 0 */ + + struct { + __IM uint32_t AE_B03_MEAN : 8; /*!< this field configures block03 Y mean data */ + __IM uint32_t AE_B02_MEAN : 8; /*!< this field configures block02 Y mean data */ + __IM uint32_t AE_B01_MEAN : 8; /*!< this field configures block01 Y mean data */ + __IM uint32_t AE_B00_MEAN : 8; /*!< this field configures block00 Y mean data */ + } bit; + } AE_BLOCK_MEAN_0; + + union { + __IOM uint32_t reg; /*!< ae statistic result register 1 */ + + struct { + __IM uint32_t AE_B12_MEAN : 8; /*!< this field configures block12 Y mean data */ + __IM uint32_t AE_B11_MEAN : 8; /*!< this field configures block11 Y mean data */ + __IM uint32_t AE_B10_MEAN : 8; /*!< this field configures block10 Y mean data */ + __IM uint32_t AE_B04_MEAN : 8; /*!< this field configures block04 Y mean data */ + } bit; + } AE_BLOCK_MEAN_1; + + union { + __IOM uint32_t reg; /*!< ae statistic result register 2 */ + + struct { + __IM uint32_t AE_B21_MEAN : 8; /*!< this field configures block21 Y mean data */ + __IM uint32_t AE_B20_MEAN : 8; /*!< this field configures block20 Y mean data */ + __IM uint32_t AE_B14_MEAN : 8; /*!< this field configures block14 Y mean data */ + __IM uint32_t AE_B13_MEAN : 8; /*!< this field configures block13 Y mean data */ + } bit; + } AE_BLOCK_MEAN_2; + + union { + __IOM uint32_t reg; /*!< ae statistic result register 3 */ + + struct { + __IM uint32_t AE_B30_MEAN : 8; /*!< this field configures block30 Y mean data */ + __IM uint32_t AE_B24_MEAN : 8; /*!< this field configures block24 Y mean data */ + __IM uint32_t AE_B23_MEAN : 8; /*!< this field configures block23 Y mean data */ + __IM uint32_t AE_B22_MEAN : 8; /*!< this field configures block22 Y mean data */ + } bit; + } AE_BLOCK_MEAN_3; + + union { + __IOM uint32_t reg; /*!< ae statistic result register 4 */ + + struct { + __IM uint32_t AE_B34_MEAN : 8; /*!< this field configures block34 Y mean data */ + __IM uint32_t AE_B33_MEAN : 8; /*!< this field configures block33 Y mean data */ + __IM uint32_t AE_B32_MEAN : 8; /*!< this field configures block32 Y mean data */ + __IM uint32_t AE_B31_MEAN : 8; /*!< this field configures block31 Y mean data */ + } bit; + } AE_BLOCK_MEAN_4; + + union { + __IOM uint32_t reg; /*!< ae statistic result register 5 */ + + struct { + __IM uint32_t AE_B43_MEAN : 8; /*!< this field configures block43 Y mean data */ + __IM uint32_t AE_B42_MEAN : 8; /*!< this field configures block42 Y mean data */ + __IM uint32_t AE_B41_MEAN : 8; /*!< this field configures block41 Y mean data */ + __IM uint32_t AE_B40_MEAN : 8; /*!< this field configures block40 Y mean data */ + } bit; + } AE_BLOCK_MEAN_5; + + union { + __IOM uint32_t reg; /*!< ae statistic result register 6 */ + + struct { + uint32_t : 24; + __IM uint32_t AE_B44_MEAN : 8; /*!< this field configures block44 Y mean data */ + } bit; + } AE_BLOCK_MEAN_6; + + union { + __IOM uint32_t reg; /*!< sharp control register 0 */ + + struct { + __IOM uint32_t SHARP_THRESHOLD_LOW : 8; /*!< this field configures sharpen threshold for detail */ + __IOM uint32_t SHARP_THRESHOLD_HIGH : 8; /*!< this field configures sharpen threshold for edge */ + __IOM uint32_t SHARP_AMOUNT_LOW : 8; /*!< this field configures sharpen amount for detail */ + __IOM uint32_t SHARP_AMOUNT_HIGH : 8; /*!< this field configures sharpen amount for edge */ + } bit; + } SHARP_CTRL0; + + union { + __IOM uint32_t reg; /*!< sharp usm config register 0 */ + + struct { + __IOM uint32_t SHARP_FILTER_COE00 : 5; /*!< this field configures unsharp masking(usm) filter coefficient */ + __IOM uint32_t SHARP_FILTER_COE01 : 5; /*!< this field configures usm filter coefficient */ + __IOM uint32_t SHARP_FILTER_COE02 : 5; /*!< this field configures usm filter coefficient */ + uint32_t : 17; + } bit; + } SHARP_FILTER0; + + union { + __IOM uint32_t reg; /*!< sharp usm config register 1 */ + + struct { + __IOM uint32_t SHARP_FILTER_COE10 : 5; /*!< this field configures usm filter coefficient */ + __IOM uint32_t SHARP_FILTER_COE11 : 5; /*!< this field configures usm filter coefficient */ + __IOM uint32_t SHARP_FILTER_COE12 : 5; /*!< this field configures usm filter coefficient */ + uint32_t : 17; + } bit; + } SHARP_FILTER1; + + union { + __IOM uint32_t reg; /*!< sharp usm config register 2 */ + + struct { + __IOM uint32_t SHARP_FILTER_COE20 : 5; /*!< this field configures usm filter coefficient */ + __IOM uint32_t SHARP_FILTER_COE21 : 5; /*!< this field configures usm filter coefficient */ + __IOM uint32_t SHARP_FILTER_COE22 : 5; /*!< this field configures usm filter coefficient */ + uint32_t : 17; + } bit; + } SHARP_FILTER2; + + union { + __IOM uint32_t reg; /*!< sharp pix2matrix ctrl */ + + struct { + __IOM uint32_t SHARP_TAIL_PIXEN_PULSE_TL : 8;/*!< matrix tail pixen low level threshold, should not to large to + prevent expanding to next frame, only reg_demosaic_tail_pixen_pulse_th!=0 + and reg_demosaic_tail_pixen_pulse_tl!=0 and reg_demosaic_tail_pixen_pulse + th < reg_demosaic_tail_pixen_pulse_tl will enable tail + pulse function */ + __IOM uint32_t SHARP_TAIL_PIXEN_PULSE_TH : 8;/*!< matrix tail pixen high level threshold, must < hnum-1, only + reg_sharp_tail_pixen_pulse_th!=0 and reg_sharp_tail_pixen_pulse_tl!=0 + and reg_sharp_tail_pixen_pulse_th < reg_sharp_tail_pixen_pulse_tl + will enable tail pulse function */ + __IOM uint32_t SHARP_PADDING_DATA : 8; /*!< this field configures sharp padding data */ + __IOM uint32_t SHARP_PADDING_MODE : 1; /*!< this field configures sharp padding mode */ + uint32_t : 7; + } bit; + } SHARP_MATRIX_CTRL; + + union { + __IOM uint32_t reg; /*!< sharp control register 1 */ + + struct { + __IM uint32_t SHARP_GRADIENT_MAX : 8; /*!< this field configures sharp max gradient, refresh at the end + of each frame end */ + uint32_t : 24; + } bit; + } SHARP_CTRL1; + + union { + __IOM uint32_t reg; /*!< isp dma source trans control register */ + + struct { + __OM uint32_t DMA_EN : 1; /*!< write 1 to triger dma to get 1 frame */ + __IOM uint32_t DMA_UPDATE : 1; /*!< write 1 to update reg_dma_burst_len & reg_dma_data_type */ + __IOM uint32_t DMA_DATA_TYPE : 6; /*!< this field configures the idi data type for image data */ + __IOM uint32_t DMA_BURST_LEN : 12; /*!< this field configures dma burst len when data source is dma. + set according to dma_msize, it is the number of 64bits + in a dma transfer */ + __IOM uint32_t DMA_INTERVAL : 12; /*!< this field configures dma req interval, 12'b1: 1 cycle, 12'b11 + 2 cycle ... */ + } bit; + } DMA_CNTL; + + union { + __IOM uint32_t reg; /*!< isp dma source total raw number set register */ + + struct { + __IOM uint32_t DMA_RAW_NUM_TOTAL : 22; /*!< this field configures the the number of 64bits in a frame */ + uint32_t : 9; + __OM uint32_t DMA_RAW_NUM_TOTAL_SET : 1; /*!< write 1 to update reg_dma_raw_num_total */ + } bit; + } DMA_RAW_DATA; + + union { + __IOM uint32_t reg; /*!< isp cam source control register */ + + struct { + __IOM uint32_t CAM_EN : 1; /*!< write 1 to start recive camera data, write 0 to disable */ + __IOM uint32_t CAM_UPDATE : 1; /*!< write 1 to update ISP_CAM_CONF */ + __IOM uint32_t CAM_RESET : 1; /*!< this bit configures cam clk domain reset, 1: reset cam input + logic, 0: release reset */ + __IOM uint32_t CAM_CLK_INV : 1; /*!< this bit configures the invertion of cam clk from pad. 0: not + invert cam clk, 1: invert cam clk */ + uint32_t : 28; + } bit; + } CAM_CNTL; + + union { + __IOM uint32_t reg; /*!< isp cam source config register */ + + struct { + __IOM uint32_t CAM_DATA_ORDER : 1; /*!< this field configures data order of cam port, 0: cam_data_in, + 1:{cam_data_in[7:0], cam_data_in[15:8]} */ + __IOM uint32_t CAM_2BYTE_MODE : 1; /*!< this field configures enable of cam 2 byte mode(input 2 bytes + each clock). 0: disable, 1: enable */ + __IOM uint32_t CAM_DATA_TYPE : 6; /*!< this field configures idi data type for image data, 0x2a: RAW8, + 0x2b: RAW10, 0x2c: RAW12 */ + __IOM uint32_t CAM_DE_INV : 1; /*!< this bit configures cam data enable invert. 0: not invert, 1: + invert */ + __IOM uint32_t CAM_HSYNC_INV : 1; /*!< this bit configures cam hsync invert. 0: not invert, 1: invert */ + __IOM uint32_t CAM_VSYNC_INV : 1; /*!< this bit configures cam vsync invert. 0: not invert, 1: invert */ + __IOM uint32_t CAM_VSYNC_FILTER_THRES : 3;/*!< this bit configures the number of clock of vsync filter length */ + __IOM uint32_t CAM_VSYNC_FILTER_EN : 1; /*!< this bit configures vsync filter en */ + uint32_t : 17; + } bit; + } CAM_CONF; + + union { + __IOM uint32_t reg; /*!< af control register 0 */ + + struct { + __IOM uint32_t AF_AUTO_UPDATE : 1; /*!< this bit configures auto_update enable. when set to 1, will + update sum and lum each frame */ + uint32_t : 3; + __OM uint32_t AF_MANUAL_UPDATE : 1; /*!< write 1 to this bit will update the sum and lum once */ + uint32_t : 3; + __IOM uint32_t AF_ENV_THRESHOLD : 4; /*!< this field configures env threshold. when both sum and lum changes + larger than this value, consider environment changes and + need to trigger a new autofocus. 4Bit fractional */ + uint32_t : 4; + __IOM uint32_t AF_ENV_PERIOD : 8; /*!< this field configures environment changes detection period (frame). + When set to 0, disable this function */ + uint32_t : 8; + } bit; + } AF_CTRL0; + + union { + __IOM uint32_t reg; /*!< af control register 1 */ + + struct { + __IOM uint32_t AF_THPIXNUM : 22; /*!< this field configures pixnum used when calculating the autofocus + threshold. Set to 0 to disable threshold calculation */ + uint32_t : 10; + } bit; + } AF_CTRL1; + + union { + __IOM uint32_t reg; /*!< af gen threshold control register */ + + struct { + __IOM uint32_t AF_GEN_THRESHOLD_MIN : 16; /*!< this field configures min threshold when use auto_threshold */ + __IOM uint32_t AF_GEN_THRESHOLD_MAX : 16; /*!< this field configures max threshold when use auto_threshold */ + } bit; + } AF_GEN_TH_CTRL; + + union { + __IOM uint32_t reg; /*!< af monitor user sum threshold register */ + + struct { + __IOM uint32_t AF_ENV_USER_THRESHOLD_SUM : 32;/*!< this field configures user setup env detect sum threshold */ + } bit; + } AF_ENV_USER_TH_SUM; + + union { + __IOM uint32_t reg; /*!< af monitor user lum threshold register */ + + struct { + __IOM uint32_t AF_ENV_USER_THRESHOLD_LUM : 30;/*!< this field configures user setup env detect lum threshold */ + uint32_t : 2; + } bit; + } AF_ENV_USER_TH_LUM; + + union { + __IOM uint32_t reg; /*!< af threshold register */ + + struct { + __IOM uint32_t AF_THRESHOLD : 16; /*!< this field configures user threshold. When set to non-zero, + autofocus will use this threshold */ + __IM uint32_t AF_GEN_THRESHOLD : 16; /*!< this field represents the last calculated threshold */ + } bit; + } AF_THRESHOLD; + + union { + __IOM uint32_t reg; /*!< h-scale of af window a register */ + + struct { + __IOM uint32_t AF_RPOINT_A : 12; /*!< this field configures left coordinate of focus window a, must + >= 2 */ + uint32_t : 4; + __IOM uint32_t AF_LPOINT_A : 12; /*!< this field configures top coordinate of focus window a, must + >= 2 */ + uint32_t : 4; + } bit; + } AF_HSCALE_A; + + union { + __IOM uint32_t reg; /*!< v-scale of af window a register */ + + struct { + __IOM uint32_t AF_BPOINT_A : 12; /*!< this field configures right coordinate of focus window a, must + <= hnum-2 */ + uint32_t : 4; + __IOM uint32_t AF_TPOINT_A : 12; /*!< this field configures bottom coordinate of focus window a, must + <= hnum-2 */ + uint32_t : 4; + } bit; + } AF_VSCALE_A; + + union { + __IOM uint32_t reg; /*!< h-scale of af window b register */ + + struct { + __IOM uint32_t AF_RPOINT_B : 12; /*!< this field configures left coordinate of focus window b, must + >= 2 */ + uint32_t : 4; + __IOM uint32_t AF_LPOINT_B : 12; /*!< this field configures top coordinate of focus window b, must + >= 2 */ + uint32_t : 4; + } bit; + } AF_HSCALE_B; + + union { + __IOM uint32_t reg; /*!< v-scale of af window b register */ + + struct { + __IOM uint32_t AF_BPOINT_B : 12; /*!< this field configures right coordinate of focus window b, must + <= hnum-2 */ + uint32_t : 4; + __IOM uint32_t AF_TPOINT_B : 12; /*!< this field configures bottom coordinate of focus window b, must + <= hnum-2 */ + uint32_t : 4; + } bit; + } AF_VSCALE_B; + + union { + __IOM uint32_t reg; /*!< v-scale of af window c register */ + + struct { + __IOM uint32_t AF_RPOINT_C : 12; /*!< this field configures left coordinate of focus window c, must + >= 2 */ + uint32_t : 4; + __IOM uint32_t AF_LPOINT_C : 12; /*!< this field configures top coordinate of focus window c, must + >= 2 */ + uint32_t : 4; + } bit; + } AF_HSCALE_C; + + union { + __IOM uint32_t reg; /*!< v-scale of af window c register */ + + struct { + __IOM uint32_t AF_BPOINT_C : 12; /*!< this field configures right coordinate of focus window c, must + <= hnum-2 */ + uint32_t : 4; + __IOM uint32_t AF_TPOINT_C : 12; /*!< this field configures bottom coordinate of focus window c, must + <= hnum-2 */ + uint32_t : 4; + } bit; + } AF_VSCALE_C; + + union { + __IOM uint32_t reg; /*!< result of sum of af window a */ + + struct { + __IM uint32_t AF_SUMA : 30; /*!< this field represents the result of accumulation of pix grad + of focus window a */ + uint32_t : 2; + } bit; + } AF_SUM_A; + + union { + __IOM uint32_t reg; /*!< result of sum of af window b */ + + struct { + __IM uint32_t AF_SUMB : 30; /*!< this field represents the result of accumulation of pix grad + of focus window b */ + uint32_t : 2; + } bit; + } AF_SUM_B; + + union { + __IOM uint32_t reg; /*!< result of sum of af window c */ + + struct { + __IM uint32_t AF_SUMC : 30; /*!< this field represents the result of accumulation of pix grad + of focus window c */ + uint32_t : 2; + } bit; + } AF_SUM_C; + + union { + __IOM uint32_t reg; /*!< result of lum of af window a */ + + struct { + __IM uint32_t AF_LUMA : 28; /*!< this field represents the result of accumulation of pix light + of focus window a */ + uint32_t : 4; + } bit; + } AF_LUM_A; + + union { + __IOM uint32_t reg; /*!< result of lum of af window b */ + + struct { + __IM uint32_t AF_LUMB : 28; /*!< this field represents the result of accumulation of pix light + of focus window b */ + uint32_t : 4; + } bit; + } AF_LUM_B; + + union { + __IOM uint32_t reg; /*!< result of lum of af window c */ + + struct { + __IM uint32_t AF_LUMC : 28; /*!< this field represents the result of accumulation of pix light + of focus window c */ + uint32_t : 4; + } bit; + } AF_LUM_C; + + union { + __IOM uint32_t reg; /*!< awb mode control register */ + + struct { + __IOM uint32_t AWB_MODE : 2; /*!< this field configures awb algo sel. 00: none sellected. 01: + sel algo0. 10: sel algo1. 11: sel both algo0 and algo1 */ + uint32_t : 2; + __IOM uint32_t AWB_SAMPLE : 1; /*!< this bit configures awb sample location, 0:before ccm, 1:after + ccm */ + uint32_t : 27; + } bit; + } AWB_MODE; + + union { + __IOM uint32_t reg; /*!< h-scale of awb window */ + + struct { + __IOM uint32_t AWB_RPOINT : 12; /*!< this field configures awb window right coordinate */ + uint32_t : 4; + __IOM uint32_t AWB_LPOINT : 12; /*!< this field configures awb window left coordinate */ + uint32_t : 4; + } bit; + } AWB_HSCALE; + + union { + __IOM uint32_t reg; /*!< v-scale of awb window */ + + struct { + __IOM uint32_t AWB_BPOINT : 12; /*!< this field configures awb window bottom coordinate */ + uint32_t : 4; + __IOM uint32_t AWB_TPOINT : 12; /*!< this field configures awb window top coordinate */ + uint32_t : 4; + } bit; + } AWB_VSCALE; + + union { + __IOM uint32_t reg; /*!< awb lum threshold register */ + + struct { + __IOM uint32_t AWB_MIN_LUM : 10; /*!< this field configures lower threshold of r+g+b */ + uint32_t : 6; + __IOM uint32_t AWB_MAX_LUM : 10; /*!< this field configures upper threshold of r+g+b */ + uint32_t : 6; + } bit; + } AWB_TH_LUM; + + union { + __IOM uint32_t reg; /*!< awb r/g threshold register */ + + struct { + __IOM uint32_t AWB_MIN_RG : 10; /*!< this field configures lower threshold of r/g, 2bit integer and + 8bit fraction */ + uint32_t : 6; + __IOM uint32_t AWB_MAX_RG : 10; /*!< this field configures upper threshold of r/g, 2bit integer and + 8bit fraction */ + uint32_t : 6; + } bit; + } AWB_TH_RG; + + union { + __IOM uint32_t reg; /*!< awb b/g threshold register */ + + struct { + __IOM uint32_t AWB_MIN_BG : 10; /*!< this field configures lower threshold of b/g, 2bit integer and + 8bit fraction */ + uint32_t : 6; + __IOM uint32_t AWB_MAX_BG : 10; /*!< this field configures upper threshold of b/g, 2bit integer and + 8bit fraction */ + uint32_t : 6; + } bit; + } AWB_TH_BG; + + union { + __IOM uint32_t reg; /*!< result of awb white point number */ + + struct { + __IM uint32_t AWB0_WHITE_CNT : 24; /*!< this field configures number of white point detected of algo0 */ + uint32_t : 8; + } bit; + } AWB0_WHITE_CNT; + + union { + __IOM uint32_t reg; /*!< result of accumulate of r channel of all white points */ + + struct { + __IM uint32_t AWB0_ACC_R : 32; /*!< this field represents accumulate of channel r of all white point + of algo0 */ + } bit; + } AWB0_ACC_R; + + union { + __IOM uint32_t reg; /*!< result of accumulate of g channel of all white points */ + + struct { + __IM uint32_t AWB0_ACC_G : 32; /*!< this field represents accumulate of channel g of all white point + of algo0 */ + } bit; + } AWB0_ACC_G; + + union { + __IOM uint32_t reg; /*!< result of accumulate of b channel of all white points */ + + struct { + __IM uint32_t AWB0_ACC_B : 32; /*!< this field represents accumulate of channel b of all white point + of algo0 */ + } bit; + } AWB0_ACC_B; + + union { + __IOM uint32_t reg; /*!< color control register */ + + struct { + __IOM uint32_t COLOR_SATURATION : 8; /*!< this field configures the color saturation value */ + __IOM uint32_t COLOR_HUE : 8; /*!< this field configures the color hue angle */ + __IOM uint32_t COLOR_CONTRAST : 8; /*!< this field configures the color contrast value */ + __IOM uint32_t COLOR_BRIGHTNESS : 8; /*!< this field configures the color brightness value, signed 2's + complement */ + } bit; + } COLOR_CTRL; + + union { + __IOM uint32_t reg; /*!< blc black level register */ + + struct { + __IOM uint32_t BLC_R3_VALUE : 8; /*!< this field configures the black level of bottom right channel + of bayer img */ + __IOM uint32_t BLC_R2_VALUE : 8; /*!< this field configures the black level of bottom left channel + of bayer img */ + __IOM uint32_t BLC_R1_VALUE : 8; /*!< this field configures the black level of top right channel of + bayer img */ + __IOM uint32_t BLC_R0_VALUE : 8; /*!< this field configures the black level of top left channel of + bayer img */ + } bit; + } BLC_VALUE; + + union { + __IOM uint32_t reg; /*!< blc stretch control register */ + + struct { + __IOM uint32_t BLC_R3_STRETCH : 1; /*!< this bit configures the stretch feature of bottom right channel. + 0: stretch disable, 1: stretch enable */ + __IOM uint32_t BLC_R2_STRETCH : 1; /*!< this bit configures the stretch feature of bottom left channel. + 0: stretch disable, 1: stretch enable */ + __IOM uint32_t BLC_R1_STRETCH : 1; /*!< this bit configures the stretch feature of top right channel. + 0: stretch disable, 1: stretch enable */ + __IOM uint32_t BLC_R0_STRETCH : 1; /*!< this bit configures the stretch feature of top left channel. + 0: stretch disable, 1: stretch enable */ + uint32_t : 28; + } bit; + } BLC_CTRL0; + + union { + __IOM uint32_t reg; /*!< blc window control register */ + + struct { + __IOM uint32_t BLC_WINDOW_TOP : 11; /*!< this field configures blc average calculation window top */ + __IOM uint32_t BLC_WINDOW_LEFT : 11; /*!< this field configures blc average calculation window left */ + __IOM uint32_t BLC_WINDOW_VNUM : 4; /*!< this field configures blc average calculation window vnum */ + __IOM uint32_t BLC_WINDOW_HNUM : 4; /*!< this field configures blc average calculation window hnum */ + __IOM uint32_t BLC_FILTER_EN : 1; /*!< this bit configures enable blc average input filter. 0: disable, + 1: enable */ + uint32_t : 1; + } bit; + } BLC_CTRL1; + + union { + __IOM uint32_t reg; /*!< blc black threshold control register */ + + struct { + __IOM uint32_t BLC_R3_TH : 8; /*!< this field configures black threshold when get blc average of + bottom right channel */ + __IOM uint32_t BLC_R2_TH : 8; /*!< this field configures black threshold when get blc average of + bottom left channel */ + __IOM uint32_t BLC_R1_TH : 8; /*!< this field configures black threshold when get blc average of + top right channel */ + __IOM uint32_t BLC_R0_TH : 8; /*!< this field configures black threshold when get blc average of + top left channel */ + } bit; + } BLC_CTRL2; + + union { + __IOM uint32_t reg; /*!< results of the average of black window */ + + struct { + __IM uint32_t BLC_R3_MEAN : 8; /*!< this field represents the average black value of bottom right + channel */ + __IM uint32_t BLC_R2_MEAN : 8; /*!< this field represents the average black value of bottom left + channel */ + __IM uint32_t BLC_R1_MEAN : 8; /*!< this field represents the average black value of top right channel */ + __IM uint32_t BLC_R0_MEAN : 8; /*!< this field represents the average black value of top left channel */ + } bit; + } BLC_MEAN; + + union { + __IOM uint32_t reg; /*!< histogram mode control register */ + + struct { + __IOM uint32_t HIST_MODE : 3; /*!< this field configures statistic mode. 0: RAW_B, 1: RAW_GB, 2: + RAW_GR 3: RAW_R, 4: RGB, 5:YUV_Y, 6:YUV_U, 7:YUV_V */ + uint32_t : 29; + } bit; + } HIST_MODE; + + union { + __IOM uint32_t reg; /*!< histogram rgb to gray coefficients register */ + + struct { + __IOM uint32_t B : 8; /*!< this field configures coefficient of B when set hist_mode to + RGB, sum of coeff_r and coeff_g and coeff_b should be 256 */ + __IOM uint32_t G : 8; /*!< this field configures coefficient of G when set hist_mode to + RGB, sum of coeff_r and coeff_g and coeff_b should be 256 */ + __IOM uint32_t R : 8; /*!< this field configures coefficient of R when set hist_mode to + RGB, sum of coeff_r and coeff_g and coeff_b should be 256 */ + uint32_t : 8; + } bit; + } HIST_COEFF; + + union { + __IOM uint32_t reg; /*!< histogram window offsets register */ + + struct { + __IOM uint32_t HIST_Y_OFFS : 12; /*!< this field configures y coordinate of first window */ + uint32_t : 4; + __IOM uint32_t HIST_X_OFFS : 12; /*!< this field configures x coordinate of first window */ + uint32_t : 4; + } bit; + } HIST_OFFS; + + union { + __IOM uint32_t reg; /*!< histogram sub-window size register */ + + struct { + __IOM uint32_t HIST_Y_SIZE : 9; /*!< this field configures y direction size of subwindow */ + uint32_t : 7; + __IOM uint32_t HIST_X_SIZE : 9; /*!< this field configures x direction size of subwindow */ + uint32_t : 7; + } bit; + } HIST_SIZE; + + union { + __IOM uint32_t reg; /*!< histogram bin control register 0 */ + + struct { + __IOM uint32_t HIST_SEG_3_4 : 8; /*!< this field configures threshold of histogram bin 3 and bin 4 */ + __IOM uint32_t HIST_SEG_2_3 : 8; /*!< this field configures threshold of histogram bin 2 and bin 3 */ + __IOM uint32_t HIST_SEG_1_2 : 8; /*!< this field configures threshold of histogram bin 1 and bin 2 */ + __IOM uint32_t HIST_SEG_0_1 : 8; /*!< this field configures threshold of histogram bin 0 and bin 1 */ + } bit; + } HIST_SEG0; + + union { + __IOM uint32_t reg; /*!< histogram bin control register 1 */ + + struct { + __IOM uint32_t HIST_SEG_7_8 : 8; /*!< this field configures threshold of histogram bin 7 and bin 8 */ + __IOM uint32_t HIST_SEG_6_7 : 8; /*!< this field configures threshold of histogram bin 6 and bin 7 */ + __IOM uint32_t HIST_SEG_5_6 : 8; /*!< this field configures threshold of histogram bin 5 and bin 6 */ + __IOM uint32_t HIST_SEG_4_5 : 8; /*!< this field configures threshold of histogram bin 4 and bin 5 */ + } bit; + } HIST_SEG1; + + union { + __IOM uint32_t reg; /*!< histogram bin control register 2 */ + + struct { + __IOM uint32_t HIST_SEG_11_12 : 8; /*!< this field configures threshold of histogram bin 11 and bin + 12 */ + __IOM uint32_t HIST_SEG_10_11 : 8; /*!< this field configures threshold of histogram bin 10 and bin + 11 */ + __IOM uint32_t HIST_SEG_9_10 : 8; /*!< this field configures threshold of histogram bin 9 and bin 10 */ + __IOM uint32_t HIST_SEG_8_9 : 8; /*!< this field configures threshold of histogram bin 8 and bin 9 */ + } bit; + } HIST_SEG2; + + union { + __IOM uint32_t reg; /*!< histogram bin control register 3 */ + + struct { + __IOM uint32_t HIST_SEG_14_15 : 8; /*!< this field configures threshold of histogram bin 14 and bin + 15 */ + __IOM uint32_t HIST_SEG_13_14 : 8; /*!< this field configures threshold of histogram bin 13 and bin + 14 */ + __IOM uint32_t HIST_SEG_12_13 : 8; /*!< this field configures threshold of histogram bin 12 and bin + 13 */ + uint32_t : 8; + } bit; + } HIST_SEG3; + + union { + __IOM uint32_t reg; /*!< histogram sub-window weight register 0 */ + + struct { + __IOM uint32_t HIST_WEIGHT_03 : 8; /*!< this field configures weight of subwindow 03 */ + __IOM uint32_t HIST_WEIGHT_02 : 8; /*!< this field configures weight of subwindow 02 */ + __IOM uint32_t HIST_WEIGHT_01 : 8; /*!< this field configures weight of subwindow 01 */ + __IOM uint32_t HIST_WEIGHT_00 : 8; /*!< this field configures weight of subwindow 00 and sum of all + weight should be 256 */ + } bit; + } HIST_WEIGHT0; + + union { + __IOM uint32_t reg; /*!< histogram sub-window weight register 1 */ + + struct { + __IOM uint32_t HIST_WEIGHT_12 : 8; /*!< this field configures weight of subwindow 12 */ + __IOM uint32_t HIST_WEIGHT_11 : 8; /*!< this field configures weight of subwindow 11 */ + __IOM uint32_t HIST_WEIGHT_10 : 8; /*!< this field configures weight of subwindow 10 */ + __IOM uint32_t HIST_WEIGHT_04 : 8; /*!< this field configures weight of subwindow 04 */ + } bit; + } HIST_WEIGHT1; + + union { + __IOM uint32_t reg; /*!< histogram sub-window weight register 2 */ + + struct { + __IOM uint32_t HIST_WEIGHT_21 : 8; /*!< this field configures weight of subwindow 21 */ + __IOM uint32_t HIST_WEIGHT_20 : 8; /*!< this field configures weight of subwindow 20 */ + __IOM uint32_t HIST_WEIGHT_14 : 8; /*!< this field configures weight of subwindow 04 */ + __IOM uint32_t HIST_WEIGHT_13 : 8; /*!< this field configures weight of subwindow 13 */ + } bit; + } HIST_WEIGHT2; + + union { + __IOM uint32_t reg; /*!< histogram sub-window weight register 3 */ + + struct { + __IOM uint32_t HIST_WEIGHT_30 : 8; /*!< this field configures weight of subwindow 30 */ + __IOM uint32_t HIST_WEIGHT_24 : 8; /*!< this field configures weight of subwindow 24 */ + __IOM uint32_t HIST_WEIGHT_23 : 8; /*!< this field configures weight of subwindow 23 */ + __IOM uint32_t HIST_WEIGHT_22 : 8; /*!< this field configures weight of subwindow 22 */ + } bit; + } HIST_WEIGHT3; + + union { + __IOM uint32_t reg; /*!< histogram sub-window weight register 4 */ + + struct { + __IOM uint32_t HIST_WEIGHT_34 : 8; /*!< this field configures weight of subwindow 34 */ + __IOM uint32_t HIST_WEIGHT_33 : 8; /*!< this field configures weight of subwindow 33 */ + __IOM uint32_t HIST_WEIGHT_32 : 8; /*!< this field configures weight of subwindow 32 */ + __IOM uint32_t HIST_WEIGHT_31 : 8; /*!< this field configures weight of subwindow 31 */ + } bit; + } HIST_WEIGHT4; + + union { + __IOM uint32_t reg; /*!< histogram sub-window weight register 5 */ + + struct { + __IOM uint32_t HIST_WEIGHT_43 : 8; /*!< this field configures weight of subwindow 43 */ + __IOM uint32_t HIST_WEIGHT_42 : 8; /*!< this field configures weight of subwindow 42 */ + __IOM uint32_t HIST_WEIGHT_41 : 8; /*!< this field configures weight of subwindow 41 */ + __IOM uint32_t HIST_WEIGHT_40 : 8; /*!< this field configures weight of subwindow 40 */ + } bit; + } HIST_WEIGHT5; + + union { + __IOM uint32_t reg; /*!< histogram sub-window weight register 6 */ + + struct { + __IOM uint32_t HIST_WEIGHT_44 : 8; /*!< this field configures weight of subwindow 44 */ + uint32_t : 24; + } bit; + } HIST_WEIGHT6; + + union { + __IOM uint32_t reg; /*!< result of histogram bin 0 */ + + struct { + __IM uint32_t HIST_BIN_0 : 17; /*!< this field represents result of histogram bin 0 */ + uint32_t : 15; + } bit; + } HIST_BIN0; + + union { + __IOM uint32_t reg; /*!< result of histogram bin 1 */ + + struct { + __IM uint32_t HIST_BIN_1 : 17; /*!< this field represents result of histogram bin 1 */ + uint32_t : 15; + } bit; + } HIST_BIN1; + + union { + __IOM uint32_t reg; /*!< result of histogram bin 2 */ + + struct { + __IM uint32_t HIST_BIN_2 : 17; /*!< this field represents result of histogram bin 2 */ + uint32_t : 15; + } bit; + } HIST_BIN2; + + union { + __IOM uint32_t reg; /*!< result of histogram bin 3 */ + + struct { + __IM uint32_t HIST_BIN_3 : 17; /*!< this field represents result of histogram bin 3 */ + uint32_t : 15; + } bit; + } HIST_BIN3; + + union { + __IOM uint32_t reg; /*!< result of histogram bin 4 */ + + struct { + __IM uint32_t HIST_BIN_4 : 17; /*!< this field represents result of histogram bin 4 */ + uint32_t : 15; + } bit; + } HIST_BIN4; + + union { + __IOM uint32_t reg; /*!< result of histogram bin 5 */ + + struct { + __IM uint32_t HIST_BIN_5 : 17; /*!< this field represents result of histogram bin 5 */ + uint32_t : 15; + } bit; + } HIST_BIN5; + + union { + __IOM uint32_t reg; /*!< result of histogram bin 6 */ + + struct { + __IM uint32_t HIST_BIN_6 : 17; /*!< this field represents result of histogram bin 6 */ + uint32_t : 15; + } bit; + } HIST_BIN6; + + union { + __IOM uint32_t reg; /*!< result of histogram bin 7 */ + + struct { + __IM uint32_t HIST_BIN_7 : 17; /*!< this field represents result of histogram bin 7 */ + uint32_t : 15; + } bit; + } HIST_BIN7; + + union { + __IOM uint32_t reg; /*!< result of histogram bin 8 */ + + struct { + __IM uint32_t HIST_BIN_8 : 17; /*!< this field represents result of histogram bin 8 */ + uint32_t : 15; + } bit; + } HIST_BIN8; + + union { + __IOM uint32_t reg; /*!< result of histogram bin 9 */ + + struct { + __IM uint32_t HIST_BIN_9 : 17; /*!< this field represents result of histogram bin 9 */ + uint32_t : 15; + } bit; + } HIST_BIN9; + + union { + __IOM uint32_t reg; /*!< result of histogram bin 10 */ + + struct { + __IM uint32_t HIST_BIN_10 : 17; /*!< this field represents result of histogram bin 10 */ + uint32_t : 15; + } bit; + } HIST_BIN10; + + union { + __IOM uint32_t reg; /*!< result of histogram bin 11 */ + + struct { + __IM uint32_t HIST_BIN_11 : 17; /*!< this field represents result of histogram bin 11 */ + uint32_t : 15; + } bit; + } HIST_BIN11; + + union { + __IOM uint32_t reg; /*!< result of histogram bin 12 */ + + struct { + __IM uint32_t HIST_BIN_12 : 17; /*!< this field represents result of histogram bin 12 */ + uint32_t : 15; + } bit; + } HIST_BIN12; + + union { + __IOM uint32_t reg; /*!< result of histogram bin 13 */ + + struct { + __IM uint32_t HIST_BIN_13 : 17; /*!< this field represents result of histogram bin 13 */ + uint32_t : 15; + } bit; + } HIST_BIN13; + + union { + __IOM uint32_t reg; /*!< result of histogram bin 14 */ + + struct { + __IM uint32_t HIST_BIN_14 : 17; /*!< this field represents result of histogram bin 14 */ + uint32_t : 15; + } bit; + } HIST_BIN14; + + union { + __IOM uint32_t reg; /*!< result of histogram bin 15 */ + + struct { + __IM uint32_t HIST_BIN_15 : 17; /*!< this field represents result of histogram bin 15 */ + uint32_t : 15; + } bit; + } HIST_BIN15; + + union { + __IOM uint32_t reg; /*!< mem aux control register 0 */ + + struct { + __IOM uint32_t HEADER_MEM_AUX_CTRL : 14; /*!< this field configures the mem_aux of isp input buffer memory */ + uint32_t : 2; + __IOM uint32_t DPC_LUT_MEM_AUX_CTRL : 14; /*!< this field represents this field configures the mem_aux of dpc + lut memory */ + uint32_t : 2; + } bit; + } MEM_AUX_CTRL_0; + + union { + __IOM uint32_t reg; /*!< mem aux control register 1 */ + + struct { + __IOM uint32_t LSC_LUT_R_GR_MEM_AUX_CTRL : 14;/*!< this field configures the mem_aux of lsc r gr lut memory */ + uint32_t : 2; + __IOM uint32_t LSC_LUT_GB_B_MEM_AUX_CTRL : 14;/*!< this field configures the mem_aux of lsc gb b lut memory */ + uint32_t : 2; + } bit; + } MEM_AUX_CTRL_1; + + union { + __IOM uint32_t reg; /*!< mem aux control register 2 */ + + struct { + __IOM uint32_t BF_MATRIX_MEM_AUX_CTRL : 14;/*!< this field configures the mem_aux of bf line buffer memory */ + uint32_t : 2; + __IOM uint32_t DPC_MATRIX_MEM_AUX_CTRL : 14;/*!< this field configures the mem_aux of dpc line buffer memory */ + uint32_t : 2; + } bit; + } MEM_AUX_CTRL_2; + + union { + __IOM uint32_t reg; /*!< mem aux control register 3 */ + + struct { + __IOM uint32_t SHARP_MATRIX_Y_MEM_AUX_CTRL : 14;/*!< this field configures the mem_aux of sharp y line buffer memory */ + uint32_t : 2; + __IOM uint32_t DEMOSAIC_MATRIX_MEM_AUX_CTRL : 14;/*!< this field configures the mem_aux of demosaic line buffer memory */ + uint32_t : 2; + } bit; + } MEM_AUX_CTRL_3; + + union { + __IOM uint32_t reg; /*!< mem aux control register 4 */ + + struct { + __IOM uint32_t SHARP_MATRIX_UV_MEM_AUX_CTRL : 14;/*!< this field configures the mem_aux of sharp uv line buffer memory */ + uint32_t : 18; + } bit; + } MEM_AUX_CTRL_4; + + union { + __IOM uint32_t reg; /*!< yuv format control register */ + + struct { + __IOM uint32_t YUV_MODE : 1; /*!< this bit configures the yuv mode. 0: ITU-R BT.601, 1: ITU-R + BT.709 */ + __IOM uint32_t YUV_RANGE : 1; /*!< this bit configures the yuv range. 0: full range, 1: limit range */ + uint32_t : 30; + } bit; + } YUV_FORMAT; + + union { + __IOM uint32_t reg; /*!< rdn eco cs register */ + + struct { + __IOM uint32_t RDN_ECO_EN : 1; /*!< rdn_eco_en */ + __IM uint32_t RDN_ECO_RESULT : 1; /*!< rdn_eco_result */ + uint32_t : 30; + } bit; + } RDN_ECO_CS; + + union { + __IOM uint32_t reg; /*!< rdn eco all low register */ + + struct { + __IOM uint32_t RDN_ECO_LOW : 32; /*!< rdn_eco_low */ + } bit; + } RDN_ECO_LOW; + + union { + __IOM uint32_t reg; /*!< rdn eco all high register */ + + struct { + __IOM uint32_t RDN_ECO_HIGH : 32; /*!< rdn_eco_high */ + } bit; + } RDN_ECO_HIGH; +} ISP_Type; /*!< Size = 580 (0x244) */ + + + +/* =========================================================================================================================== */ +/* ================ JPEG ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief JPEG Codec (JPEG) + */ + +typedef struct { /*!< JPEG Structure */ + + union { + __IOM uint32_t reg; /*!< Control and configuration registers */ + + struct { + __OM uint32_t FSM_RST : 1; /*!< fsm reset */ + __OM uint32_t JPEG_START : 1; /*!< start to compress a new pic(in dma reg mode) */ + __IOM uint32_t QNR_PRESITION : 1; /*!< 0:8bit qnr,1:12bit qnr(TBD) */ + __IOM uint32_t FF_CHECK_EN : 1; /*!< enable whether to add "00" after "ff" */ + __IOM uint32_t SAMPLE_SEL : 2; /*!< 0:yuv444,1:yuv422, 2:yuv420 */ + __IM uint32_t DMA_LINKLIST_MODE : 1; /*!< 1:use linklist to configure dma */ + __IOM uint32_t DEBUG_DIRECT_OUT_EN : 1; /*!< 0:normal mode,1:debug mode for direct output from input */ + __IOM uint32_t GRAY_SEL : 1; /*!< 0:use non-fifo way to access qnr ram,1:use fifo way to access + qnr ram */ + __IOM uint32_t LQNR_TBL_SEL : 2; /*!< choose luminance quntization table id(TBD) */ + __IOM uint32_t CQNR_TBL_SEL : 2; /*!< choose chrominance quntization table id (TBD) */ + __IOM uint32_t COLOR_SPACE : 2; /*!< configure picture's color space:0-rb888,1-yuv422,2-rgb565, 3-gray */ + __IOM uint32_t DHT_FIFO_EN : 1; /*!< 0:use non-fifo way to write dht len_total/codemin/value table,1:use + fifo way to write dht len_total/codemin/value table. Reading + dht len_total/codemin/value table only has nonfifo way */ + __IOM uint32_t MEM_CLK_FORCE_ON : 1; /*!< force memory's clock enabled */ + __IOM uint32_t JFIF_VER : 6; /*!< decode pause period to trigger decode_timeout int, the timeout + periods =2 power (reg_decode_timeout_thres) -1 */ + __IOM uint32_t DECODE_TIMEOUT_TASK_SEL : 1;/*!< 0: software use reset to abort decode process ,1: decoder abort + decode process by itself */ + __IOM uint32_t SOFT_RST : 1; /*!< when set to 1, soft reset JPEG module except jpeg_reg module */ + __IOM uint32_t FIFO_RST : 1; /*!< fifo reset */ + __IOM uint32_t PIXEL_REV : 1; /*!< reverse the source color pixel */ + __IOM uint32_t TAILER_EN : 1; /*!< set this bit to add EOI of "0xffd9" at the end of bitstream */ + __IOM uint32_t PAUSE_EN : 1; /*!< set this bit to pause jpeg encoding */ + __IOM uint32_t MEM_FORCE_PD : 1; /*!< 0: no operation,1:force jpeg memory to power down */ + __IOM uint32_t MEM_FORCE_PU : 1; /*!< 0: no operation,1:force jpeg memory to power up */ + __IOM uint32_t MODE : 1; /*!< 0:encoder mode, 1: decoder mode */ + } bit; + } CONFIG; + + union { + __IOM uint32_t reg; /*!< Control and configuration registers */ + + struct { + __IOM uint32_t T0_DQT_INFO : 8; /*!< Configure dqt table0's quantization coefficient precision in + bit[7:4], configure dqt table0's table id in bit[3:0] */ + __IOM uint32_t T1_DQT_INFO : 8; /*!< Configure dqt table1's quantization coefficient precision in + bit[7:4], configure dqt table1's table id in bit[3:0] */ + __IOM uint32_t T2_DQT_INFO : 8; /*!< Configure dqt table2's quantization coefficient precision in + bit[7:4], configure dqt table2's table id in bit[3:0] */ + __IOM uint32_t T3_DQT_INFO : 8; /*!< Configure dqt table3's quantization coefficient precision in + bit[7:4], configure dqt table3's table id in bit[3:0] */ + } bit; + } DQT_INFO; + + union { + __IOM uint32_t reg; /*!< Control and configuration registers */ + + struct { + __IOM uint32_t VA : 16; /*!< configure picture's height. when encode, the max configurable + bits is 14, when decode, the max configurable bits is 16 */ + __IOM uint32_t HA : 16; /*!< configure picture's width. when encode, the max configurable + bits is 14, when decode, the max configurable bits is 16 */ + } bit; + } PIC_SIZE; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t reg; /*!< Control and configuration registers */ + + struct { + __IM uint32_t T0_QNR_VAL : 32; /*!< write this reg to configure 64 quantization coefficient in t0 + table */ + } bit; + } T0QNR; + + union { + __IOM uint32_t reg; /*!< Control and configuration registers */ + + struct { + __IM uint32_t CHROMINANCE_QNR_VAL : 32; /*!< write this reg to configure 64 quantization coefficient in t1 + table */ + } bit; + } T1QNR; + + union { + __IOM uint32_t reg; /*!< Control and configuration registers */ + + struct { + __IM uint32_t T2_QNR_VAL : 32; /*!< write this reg to configure 64 quantization coefficient in t2 + table */ + } bit; + } T2QNR; + + union { + __IOM uint32_t reg; /*!< Control and configuration registers */ + + struct { + __IM uint32_t T3_QNR_VAL : 32; /*!< write this reg to configure 64 quantization coefficient in t3 + table */ + } bit; + } T3QNR; + + union { + __IOM uint32_t reg; /*!< Control and configuration registers */ + + struct { + __IOM uint32_t RESTART_INTERVAL : 16; /*!< configure restart interval in DRI marker when decode */ + __IOM uint32_t COMPONENT_NUM : 8; /*!< configure number of components in frame when decode */ + __IM uint32_t SW_DHT_EN : 1; /*!< software decode dht table enable */ + __IOM uint32_t SOS_CHECK_BYTE_NUM : 2; /*!< Configure the byte number to check next sos marker in the multi-scan + picture after one scan is decoded down. The real check + number is reg_sos_check_byte_num+1 */ + __IOM uint32_t RST_CHECK_BYTE_NUM : 2; /*!< Configure the byte number to check next rst marker after one + rst interval is decoded down. The real check number is + reg_rst_check_byte_num+1 */ + __IOM uint32_t MULTI_SCAN_ERR_CHECK : 1; /*!< reserved for decoder */ + __IOM uint32_t DEZIGZAG_READY_CTL : 1; /*!< reserved for decoder */ + uint32_t : 1; + } bit; + } DECODE_CONF; + + union { + __IOM uint32_t reg; /*!< Control and configuration registers */ + + struct { + __IOM uint32_t DQT_TBL_SEL : 8; /*!< choose c0 quntization table id (TBD) */ + __IOM uint32_t Y_FACTOR : 4; /*!< vertical sampling factor of c0 */ + __IOM uint32_t X_FACTOR : 4; /*!< horizontal sampling factor of c0 */ + __IOM uint32_t ID : 8; /*!< the identifier of c0 */ + uint32_t : 8; + } bit; + } C0; + + union { + __IOM uint32_t reg; /*!< Control and configuration registers */ + + struct { + __IOM uint32_t DQT_TBL_SEL : 8; /*!< choose c1 quntization table id (TBD) */ + __IOM uint32_t Y_FACTOR : 4; /*!< vertical sampling factor of c1 */ + __IOM uint32_t X_FACTOR : 4; /*!< horizontal sampling factor of c1 */ + __IOM uint32_t ID : 8; /*!< the identifier of c1 */ + uint32_t : 8; + } bit; + } C1; + + union { + __IOM uint32_t reg; /*!< Control and configuration registers */ + + struct { + __IOM uint32_t DQT_TBL_SEL : 8; /*!< choose c2 quntization table id (TBD) */ + __IOM uint32_t Y_FACTOR : 4; /*!< vertical sampling factor of c2 */ + __IOM uint32_t X_FACTOR : 4; /*!< horizontal sampling factor of c2 */ + __IOM uint32_t ID : 8; /*!< the identifier of c2 */ + uint32_t : 8; + } bit; + } C2; + + union { + __IOM uint32_t reg; /*!< Control and configuration registers */ + + struct { + __IOM uint32_t DQT_TBL_SEL : 8; /*!< choose c3 quntization table id (TBD) */ + __IOM uint32_t Y_FACTOR : 4; /*!< vertical sampling factor of c3 */ + __IOM uint32_t X_FACTOR : 4; /*!< horizontal sampling factor of c3 */ + __IOM uint32_t ID : 8; /*!< the identifier of c3 */ + uint32_t : 8; + } bit; + } C3; + + union { + __IOM uint32_t reg; /*!< Control and configuration registers */ + + struct { + __IOM uint32_t DC0_DHT_ID : 4; /*!< configure dht dc table 0 id */ + __IOM uint32_t DC1_DHT_ID : 4; /*!< configure dht dc table 1 id */ + __IOM uint32_t AC0_DHT_ID : 4; /*!< configure dht ac table 0 id */ + __IOM uint32_t AC1_DHT_ID : 4; /*!< configure dht ac table 1 id */ + uint32_t : 16; + } bit; + } DHT_INFO; + + union { + __IOM uint32_t reg; /*!< Interrupt raw registers */ + + struct { + __IOM uint32_t DONE_INT_RAW : 1; /*!< This raw interrupt bit turns to high level when JPEG finishes + encoding a picture.. */ + __IOM uint32_t RLE_PARALLEL_ERR_INT_RAW : 1;/*!< The raw interrupt bit to sign that rle parallel error when decoding. */ + __IOM uint32_t CID_ERR_INT_RAW : 1; /*!< The raw interrupt bit to sign that scan id check with component + fails when decoding. */ + __IOM uint32_t C_DHT_DC_ID_ERR_INT_RAW : 1;/*!< The raw interrupt bit to sign that scan component's dc dht id + check with dc dht table's id fails when decoding. */ + __IOM uint32_t C_DHT_AC_ID_ERR_INT_RAW : 1;/*!< The raw interrupt bit to sign that scan component's ac dht id + check with ac dht table's id fails when decoding. */ + __IOM uint32_t C_DQT_ID_ERR_INT_RAW : 1; /*!< The raw interrupt bit to sign that scan component's dqt id check + with dqt table's id fails when decoding. */ + __IOM uint32_t RST_UXP_ERR_INT_RAW : 1; /*!< The raw interrupt bit to sign that RST header marker is detected + but restart interval is 0 when decoding. */ + __IOM uint32_t RST_CHECK_NONE_ERR_INT_RAW : 1;/*!< The raw interrupt bit to sign that RST header marker is not + detected but restart interval is not 0 when decoding. */ + __IOM uint32_t RST_CHECK_POS_ERR_INT_RAW : 1;/*!< The raw interrupt bit to sign that RST header marker position + mismatches with restart interval when decoding. */ + __IOM uint32_t OUT_EOF_INT_RAW : 1; /*!< The raw interrupt bit turns to high level when the last pixel + of one square has been transmitted for Tx channel. */ + __IOM uint32_t SR_COLOR_MODE_ERR_INT_RAW : 1;/*!< The raw interrupt bit to sign that the selected source color + mode is not supported. */ + __IOM uint32_t DCT_DONE_INT_RAW : 1; /*!< The raw interrupt bit to sign that one dct calculation is finished. */ + __IOM uint32_t BS_LAST_BLOCK_EOF_INT_RAW : 1;/*!< The raw interrupt bit to sign that the coding process for last + block is finished. */ + __IOM uint32_t SCAN_CHECK_NONE_ERR_INT_RAW : 1;/*!< The raw interrupt bit to sign that SOS header marker is not + detected but there are still components left to be decoded. */ + __IOM uint32_t SCAN_CHECK_POS_ERR_INT_RAW : 1;/*!< The raw interrupt bit to sign that SOS header marker position + wrong when decoding. */ + __IOM uint32_t UXP_DET_INT_RAW : 1; /*!< The raw interrupt bit to sign that unsupported header marker + is detected when decoding. */ + __IOM uint32_t EN_FRAME_EOF_ERR_INT_RAW : 1;/*!< The raw interrupt bit to sign that received pixel blocks are + smaller than expected when encoding. */ + __IOM uint32_t EN_FRAME_EOF_LACK_INT_RAW : 1;/*!< The raw interrupt bit to sign that the frame eof sign bit from + dma input is missing when encoding. But the number of pixel + blocks is enough. */ + __IOM uint32_t DE_FRAME_EOF_ERR_INT_RAW : 1;/*!< The raw interrupt bit to sign that decoded blocks are smaller + than expected when decoding. */ + __IOM uint32_t DE_FRAME_EOF_LACK_INT_RAW : 1;/*!< The raw interrupt bit to sign that the either frame eof from + dma input or eoi marker is missing when encoding. But the + number of decoded blocks is enough. */ + __IOM uint32_t SOS_UNMATCH_ERR_INT_RAW : 1;/*!< The raw interrupt bit to sign that the component number of a + scan is 0 or does not match the sos marker's length when + decoding. */ + __IOM uint32_t MARKER_ERR_FST_SCAN_INT_RAW : 1;/*!< The raw interrupt bit to sign that the first scan has header + marker error when decoding. */ + __IOM uint32_t MARKER_ERR_OTHER_SCAN_INT_RAW : 1;/*!< The raw interrupt bit to sign that the following scans but not + the first scan have header marker error when decoding. */ + __IOM uint32_t UNDET_INT_RAW : 1; /*!< The raw interrupt bit to sign that JPEG format is not detected + at the eof data of a packet when decoding. */ + __IOM uint32_t DECODE_TIMEOUT_INT_RAW : 1;/*!< The raw interrupt bit to sign that decode pause time is longer + than the setting decode timeout time when decoding. */ + uint32_t : 7; + } bit; + } INT_RAW; + + union { + __IOM uint32_t reg; /*!< Interrupt enable registers */ + + struct { + __IOM uint32_t DONE_INT_ENA : 1; /*!< This enable interrupt bit turns to high level when JPEG finishes + encoding a picture.. */ + __IOM uint32_t RLE_PARALLEL_ERR_INT_ENA : 1;/*!< The enable interrupt bit to sign that rle parallel error when + decoding. */ + __IOM uint32_t CID_ERR_INT_ENA : 1; /*!< The enable interrupt bit to sign that scan id check with component + fails when decoding. */ + __IOM uint32_t C_DHT_DC_ID_ERR_INT_ENA : 1;/*!< The enable interrupt bit to sign that scan component's dc dht + id check with dc dht table's id fails when decoding. */ + __IOM uint32_t C_DHT_AC_ID_ERR_INT_ENA : 1;/*!< The enable interrupt bit to sign that scan component's ac dht + id check with ac dht table's id fails when decoding. */ + __IOM uint32_t C_DQT_ID_ERR_INT_ENA : 1; /*!< The enable interrupt bit to sign that scan component's dqt id + check with dqt table's id fails when decoding. */ + __IOM uint32_t RST_UXP_ERR_INT_ENA : 1; /*!< The enable interrupt bit to sign that RST header marker is detected + but restart interval is 0 when decoding. */ + __IOM uint32_t RST_CHECK_NONE_ERR_INT_ENA : 1;/*!< The enable interrupt bit to sign that RST header marker is not + detected but restart interval is not 0 when decoding. */ + __IOM uint32_t RST_CHECK_POS_ERR_INT_ENA : 1;/*!< The enable interrupt bit to sign that RST header marker position + mismatches with restart interval when decoding. */ + __IOM uint32_t OUT_EOF_INT_ENA : 1; /*!< The enable interrupt bit turns to high level when the last pixel + of one square has been transmitted for Tx channel. */ + __IOM uint32_t SR_COLOR_MODE_ERR_INT_ENA : 1;/*!< The enable interrupt bit to sign that the selected source color + mode is not supported. */ + __IOM uint32_t DCT_DONE_INT_ENA : 1; /*!< The enable interrupt bit to sign that one dct calculation is + finished. */ + __IOM uint32_t BS_LAST_BLOCK_EOF_INT_ENA : 1;/*!< The enable interrupt bit to sign that the coding process for + last block is finished. */ + __IOM uint32_t SCAN_CHECK_NONE_ERR_INT_ENA : 1;/*!< The enable interrupt bit to sign that SOS header marker is not + detected but there are still components left to be decoded. */ + __IOM uint32_t SCAN_CHECK_POS_ERR_INT_ENA : 1;/*!< The enable interrupt bit to sign that SOS header marker position + wrong when decoding. */ + __IOM uint32_t UXP_DET_INT_ENA : 1; /*!< The enable interrupt bit to sign that unsupported header marker + is detected when decoding. */ + __IOM uint32_t EN_FRAME_EOF_ERR_INT_ENA : 1;/*!< The enable interrupt bit to sign that received pixel blocks + are smaller than expected when encoding. */ + __IOM uint32_t EN_FRAME_EOF_LACK_INT_ENA : 1;/*!< The enable interrupt bit to sign that the frame eof sign bit + from dma input is missing when encoding. But the number + of pixel blocks is enough. */ + __IOM uint32_t DE_FRAME_EOF_ERR_INT_ENA : 1;/*!< The enable interrupt bit to sign that decoded blocks are smaller + than expected when decoding. */ + __IOM uint32_t DE_FRAME_EOF_LACK_INT_ENA : 1;/*!< The enable interrupt bit to sign that the either frame eof from + dma input or eoi marker is missing when encoding. But the + number of decoded blocks is enough. */ + __IOM uint32_t SOS_UNMATCH_ERR_INT_ENA : 1;/*!< The enable interrupt bit to sign that the component number of + a scan is 0 or does not match the sos marker's length when + decoding. */ + __IOM uint32_t MARKER_ERR_FST_SCAN_INT_ENA : 1;/*!< The enable interrupt bit to sign that the first scan has header + marker error when decoding. */ + __IOM uint32_t MARKER_ERR_OTHER_SCAN_INT_ENA : 1;/*!< The enable interrupt bit to sign that the following scans but + not the first scan have header marker error when decoding. */ + __IOM uint32_t UNDET_INT_ENA : 1; /*!< The enable interrupt bit to sign that JPEG format is not detected + at the eof data of a packet when decoding. */ + __IOM uint32_t DECODE_TIMEOUT_INT_ENA : 1;/*!< The enable interrupt bit to sign that decode pause time is longer + than the setting decode timeout time when decoding. */ + uint32_t : 7; + } bit; + } INT_ENA; + + union { + __IOM uint32_t reg; /*!< Interrupt status registers */ + + struct { + __IM uint32_t DONE_INT_ST : 1; /*!< This status interrupt bit turns to high level when JPEG finishes + encoding a picture.. */ + __IM uint32_t RLE_PARALLEL_ERR_INT_ST : 1;/*!< The status interrupt bit to sign that rle parallel error when + decoding. */ + __IM uint32_t CID_ERR_INT_ST : 1; /*!< The status interrupt bit to sign that scan id check with component + fails when decoding. */ + __IM uint32_t C_DHT_DC_ID_ERR_INT_ST : 1;/*!< The status interrupt bit to sign that scan component's dc dht + id check with dc dht table's id fails when decoding. */ + __IM uint32_t C_DHT_AC_ID_ERR_INT_ST : 1;/*!< The status interrupt bit to sign that scan component's ac dht + id check with ac dht table's id fails when decoding. */ + __IM uint32_t C_DQT_ID_ERR_INT_ST : 1; /*!< The status interrupt bit to sign that scan component's dqt id + check with dqt table's id fails when decoding. */ + __IM uint32_t RST_UXP_ERR_INT_ST : 1; /*!< The status interrupt bit to sign that RST header marker is detected + but restart interval is 0 when decoding. */ + __IM uint32_t RST_CHECK_NONE_ERR_INT_ST : 1;/*!< The status interrupt bit to sign that RST header marker is not + detected but restart interval is not 0 when decoding. */ + __IM uint32_t RST_CHECK_POS_ERR_INT_ST : 1;/*!< The status interrupt bit to sign that RST header marker position + mismatches with restart interval when decoding. */ + __IM uint32_t OUT_EOF_INT_ST : 1; /*!< The status interrupt bit turns to high level when the last pixel + of one square has been transmitted for Tx channel. */ + __IM uint32_t SR_COLOR_MODE_ERR_INT_ST : 1;/*!< The status interrupt bit to sign that the selected source color + mode is not supported. */ + __IM uint32_t DCT_DONE_INT_ST : 1; /*!< The status interrupt bit to sign that one dct calculation is + finished. */ + __IM uint32_t BS_LAST_BLOCK_EOF_INT_ST : 1;/*!< The status interrupt bit to sign that the coding process for + last block is finished. */ + __IM uint32_t SCAN_CHECK_NONE_ERR_INT_ST : 1;/*!< The status interrupt bit to sign that SOS header marker is not + detected but there are still components left to be decoded. */ + __IM uint32_t SCAN_CHECK_POS_ERR_INT_ST : 1;/*!< The status interrupt bit to sign that SOS header marker position + wrong when decoding. */ + __IM uint32_t UXP_DET_INT_ST : 1; /*!< The status interrupt bit to sign that unsupported header marker + is detected when decoding. */ + __IM uint32_t EN_FRAME_EOF_ERR_INT_ST : 1;/*!< The status interrupt bit to sign that received pixel blocks + are smaller than expected when encoding. */ + __IM uint32_t EN_FRAME_EOF_LACK_INT_ST : 1;/*!< The status interrupt bit to sign that the frame eof sign bit + from dma input is missing when encoding. But the number + of pixel blocks is enough. */ + __IM uint32_t DE_FRAME_EOF_ERR_INT_ST : 1;/*!< The status interrupt bit to sign that decoded blocks are smaller + than expected when decoding. */ + __IM uint32_t DE_FRAME_EOF_LACK_INT_ST : 1;/*!< The status interrupt bit to sign that the either frame eof from + dma input or eoi marker is missing when encoding. But the + number of decoded blocks is enough. */ + __IM uint32_t SOS_UNMATCH_ERR_INT_ST : 1;/*!< The status interrupt bit to sign that the component number of + a scan is 0 or does not match the sos marker's length when + decoding. */ + __IM uint32_t MARKER_ERR_FST_SCAN_INT_ST : 1;/*!< The status interrupt bit to sign that the first scan has header + marker error when decoding. */ + __IM uint32_t MARKER_ERR_OTHER_SCAN_INT_ST : 1;/*!< The status interrupt bit to sign that the following scans but + not the first scan have header marker error when decoding. */ + __IM uint32_t UNDET_INT_ST : 1; /*!< The status interrupt bit to sign that JPEG format is not detected + at the eof data of a packet when decoding. */ + __IM uint32_t DECODE_TIMEOUT_INT_ST : 1; /*!< The status interrupt bit to sign that decode pause time is longer + than the setting decode timeout time when decoding. */ + uint32_t : 7; + } bit; + } INT_ST; + + union { + __IOM uint32_t reg; /*!< Interrupt clear registers */ + + struct { + __OM uint32_t DONE_INT_CLR : 1; /*!< This clear interrupt bit turns to high level when JPEG finishes + encoding a picture.. */ + __OM uint32_t RLE_PARALLEL_ERR_INT_CLR : 1;/*!< The clear interrupt bit to sign that rle parallel error when + decoding. */ + __OM uint32_t CID_ERR_INT_CLR : 1; /*!< The clear interrupt bit to sign that scan id check with component + fails when decoding. */ + __OM uint32_t C_DHT_DC_ID_ERR_INT_CLR : 1;/*!< The clear interrupt bit to sign that scan component's dc dht + id check with dc dht table's id fails when decoding. */ + __OM uint32_t C_DHT_AC_ID_ERR_INT_CLR : 1;/*!< The clear interrupt bit to sign that scan component's ac dht + id check with ac dht table's id fails when decoding. */ + __OM uint32_t C_DQT_ID_ERR_INT_CLR : 1; /*!< The clear interrupt bit to sign that scan component's dqt id + check with dqt table's id fails when decoding. */ + __OM uint32_t RST_UXP_ERR_INT_CLR : 1; /*!< The clear interrupt bit to sign that RST header marker is detected + but restart interval is 0 when decoding. */ + __OM uint32_t RST_CHECK_NONE_ERR_INT_CLR : 1;/*!< The clear interrupt bit to sign that RST header marker is not + detected but restart interval is not 0 when decoding. */ + __OM uint32_t RST_CHECK_POS_ERR_INT_CLR : 1;/*!< The clear interrupt bit to sign that RST header marker position + mismatches with restart interval when decoding. */ + __OM uint32_t OUT_EOF_INT_CLR : 1; /*!< The clear interrupt bit turns to high level when the last pixel + of one square has been transmitted for Tx channel. */ + __OM uint32_t SR_COLOR_MODE_ERR_INT_CLR : 1;/*!< The clear interrupt bit to sign that the selected source color + mode is not supported. */ + __OM uint32_t DCT_DONE_INT_CLR : 1; /*!< The clear interrupt bit to sign that one dct calculation is + finished. */ + __OM uint32_t BS_LAST_BLOCK_EOF_INT_CLR : 1;/*!< The clear interrupt bit to sign that the coding process for + last block is finished. */ + __OM uint32_t SCAN_CHECK_NONE_ERR_INT_CLR : 1;/*!< The clear interrupt bit to sign that SOS header marker is not + detected but there are still components left to be decoded. */ + __OM uint32_t SCAN_CHECK_POS_ERR_INT_CLR : 1;/*!< The clear interrupt bit to sign that SOS header marker position + wrong when decoding. */ + __OM uint32_t UXP_DET_INT_CLR : 1; /*!< The clear interrupt bit to sign that unsupported header marker + is detected when decoding. */ + __OM uint32_t EN_FRAME_EOF_ERR_INT_CLR : 1;/*!< The clear interrupt bit to sign that received pixel blocks are + smaller than expected when encoding. */ + __OM uint32_t EN_FRAME_EOF_LACK_INT_CLR : 1;/*!< The clear interrupt bit to sign that the frame eof sign bit + from dma input is missing when encoding. But the number + of pixel blocks is enough. */ + __OM uint32_t DE_FRAME_EOF_ERR_INT_CLR : 1;/*!< The clear interrupt bit to sign that decoded blocks are smaller + than expected when decoding. */ + __OM uint32_t DE_FRAME_EOF_LACK_INT_CLR : 1;/*!< The clear interrupt bit to sign that the either frame eof from + dma input or eoi marker is missing when encoding. But the + number of decoded blocks is enough. */ + __OM uint32_t SOS_UNMATCH_ERR_INT_CLR : 1;/*!< The clear interrupt bit to sign that the component number of + a scan is 0 or does not match the sos marker's length when + decoding. */ + __OM uint32_t MARKER_ERR_FST_SCAN_INT_CLR : 1;/*!< The clear interrupt bit to sign that the first scan has header + marker error when decoding. */ + __OM uint32_t MARKER_ERR_OTHER_SCAN_INT_CLR : 1;/*!< The clear interrupt bit to sign that the following scans but + not the first scan have header marker error when decoding. */ + __OM uint32_t UNDET_INT_CLR : 1; /*!< The clear interrupt bit to sign that JPEG format is not detected + at the eof data of a packet when decoding. */ + __OM uint32_t DECODE_TIMEOUT_INT_CLR : 1;/*!< The clear interrupt bit to sign that decode pause time is longer + than the setting decode timeout time when decoding. */ + uint32_t : 7; + } bit; + } INT_CLR; + + union { + __IOM uint32_t reg; /*!< Trace and Debug registers */ + + struct { + uint32_t : 11; + __IM uint32_t BITSTREAM_EOF_VLD_CNT : 6; /*!< the valid bit count for last bitstream */ + __IM uint32_t DCTOUT_ZZSCAN_ADDR : 6; /*!< the zig-zag read addr from dctout_ram */ + __IM uint32_t QNRVAL_ZZSCAN_ADDR : 6; /*!< the zig-zag read addr from qnrval_ram */ + __IM uint32_t REG_STATE_YUV : 3; /*!< the state of jpeg fsm */ + } bit; + } STATUS0; + + union { + __IOM uint32_t reg; /*!< Trace and Debug registers */ + + struct { + __IM uint32_t SOURCE_PIXEL : 24; /*!< source pixels fetched from dma */ + __IM uint32_t LAST_BLOCK : 1; /*!< indicate the encoding process for the last mcu of the picture */ + __IM uint32_t LAST_MCU : 1; /*!< indicate the encoding process for the last block of the picture */ + __IM uint32_t LAST_DC : 1; /*!< indicate the encoding process is at the header of the last block + of the picture */ + __IM uint32_t PACKFIFO_READY : 1; /*!< the jpeg pack_fifo ready signal, high active */ + uint32_t : 4; + } bit; + } STATUS2; + + union { + __IOM uint32_t reg; /*!< Trace and Debug registers */ + + struct { + __IM uint32_t YO : 9; /*!< component y transferred from rgb input */ + __IM uint32_t Y_READY : 1; /*!< component y valid signal, high active */ + __IM uint32_t CBO : 9; /*!< component cb transferred from rgb input */ + __IM uint32_t CB_READY : 1; /*!< component cb valid signal, high active */ + __IM uint32_t CRO : 9; /*!< component cr transferred from rgb input */ + __IM uint32_t CR_READY : 1; /*!< component cr valid signal, high active */ + uint32_t : 2; + } bit; + } STATUS3; + + union { + __IOM uint32_t reg; /*!< Trace and Debug registers */ + + struct { + __IM uint32_t HFM_BITSTREAM : 32; /*!< the hufman bitstream during encoding process */ + } bit; + } STATUS4; + + union { + __IOM uint32_t reg; /*!< Trace and Debug registers */ + + struct { + __IM uint32_t DHT_TOTLEN_DC0 : 32; /*!< write the numbers of 1~n codeword length sum from 1~16 of dc0 + table */ + } bit; + } DHT_TOTLEN_DC0; + + union { + __IOM uint32_t reg; /*!< Trace and Debug registers */ + + struct { + __IM uint32_t DHT_VAL_DC0 : 32; /*!< write codeword corresponding huffman values of dc0 table */ + } bit; + } DHT_VAl_DC0; + + union { + __IOM uint32_t reg; /*!< Trace and Debug registers */ + + struct { + __IM uint32_t DHT_TOTLEN_AC0 : 32; /*!< write the numbers of 1~n codeword length sum from 1~16 of ac0 + table */ + } bit; + } DHT_TOTLEN_AC0; + + union { + __IOM uint32_t reg; /*!< Trace and Debug registers */ + + struct { + __IM uint32_t DHT_VAL_AC0 : 32; /*!< write codeword corresponding huffman values of ac0 table */ + } bit; + } DHT_VAl_AC0; + + union { + __IOM uint32_t reg; /*!< Trace and Debug registers */ + + struct { + __IM uint32_t DHT_TOTLEN_DC1 : 32; /*!< write the numbers of 1~n codeword length sum from 1~16 of dc1 + table */ + } bit; + } DHT_TOTLEN_DC1; + + union { + __IOM uint32_t reg; /*!< Trace and Debug registers */ + + struct { + __IM uint32_t DHT_VAL_DC1 : 32; /*!< write codeword corresponding huffman values of dc1 table */ + } bit; + } DHT_VAl_DC1; + + union { + __IOM uint32_t reg; /*!< Trace and Debug registers */ + + struct { + __IM uint32_t DHT_TOTLEN_AC1 : 32; /*!< write the numbers of 1~n codeword length sum from 1~16 of ac1 + table */ + } bit; + } DHT_TOTLEN_AC1; + + union { + __IOM uint32_t reg; /*!< Trace and Debug registers */ + + struct { + __IM uint32_t DHT_VAL_AC1 : 32; /*!< write codeword corresponding huffman values of ac1 table */ + } bit; + } DHT_VAl_AC1; + + union { + __IOM uint32_t reg; /*!< Trace and Debug registers */ + + struct { + __IM uint32_t DHT_CODEMIN_DC0 : 32; /*!< write the minimum codeword of code length from 1~16 of dc0 table. + The codeword is left shifted to the MSB position of a 16bit + word */ + } bit; + } DHT_CODEMIN_DC0; + + union { + __IOM uint32_t reg; /*!< Trace and Debug registers */ + + struct { + __IM uint32_t DHT_CODEMIN_AC0 : 32; /*!< write the minimum codeword of code length from 1~16 of ac0 table. + The codeword is left shifted to the MSB position of a 16bit + word */ + } bit; + } DHT_CODEMIN_AC0; + + union { + __IOM uint32_t reg; /*!< Trace and Debug registers */ + + struct { + __IM uint32_t DHT_CODEMIN_DC1 : 32; /*!< write the minimum codeword of code length from 1~16 of dc1 table. + The codeword is left shifted to the MSB position of a 16bit + word */ + } bit; + } DHT_CODEMIN_DC1; + + union { + __IOM uint32_t reg; /*!< Trace and Debug registers */ + + struct { + __IM uint32_t DHT_CODEMIN_AC1 : 32; /*!< write the minimum codeword of code length from 1~16 of ac1 table. + The codeword is left shifted to the MSB position of a 16bit + word */ + } bit; + } DHT_CODEMIN_AC1; + + union { + __IOM uint32_t reg; /*!< Trace and Debug registers */ + + struct { + __IM uint32_t DECODE_BYTE_CNT : 26; /*!< Reserved */ + __IM uint32_t HEADER_DEC_ST : 4; /*!< Reserved */ + __IM uint32_t DECODE_SAMPLE_SEL : 2; /*!< Reserved */ + } bit; + } DECODER_STATUS0; + + union { + __IOM uint32_t reg; /*!< Trace and Debug registers */ + + struct { + __IM uint32_t ENCODE_DATA : 16; /*!< Reserved */ + __IM uint32_t COUNT_Q : 7; /*!< Reserved */ + __IM uint32_t MCU_FSM_READY : 1; /*!< Reserved */ + __IM uint32_t DECODE_DATA : 8; /*!< Reserved */ + } bit; + } DECODER_STATUS1; + + union { + __IOM uint32_t reg; /*!< Trace and Debug registers */ + + struct { + __IM uint32_t COMP_BLOCK_NUM : 26; /*!< Reserved */ + __IM uint32_t SCAN_NUM : 3; /*!< Reserved */ + __IM uint32_t RST_CHECK_WAIT : 1; /*!< Reserved */ + __IM uint32_t SCAN_CHECK_WAIT : 1; /*!< Reserved */ + __IM uint32_t MCU_IN_PROC : 1; /*!< Reserved */ + } bit; + } DECODER_STATUS2; + + union { + __IOM uint32_t reg; /*!< Trace and Debug registers */ + + struct { + __IM uint32_t LOOKUP_DATA : 32; /*!< Reserved */ + } bit; + } DECODER_STATUS3; + + union { + __IOM uint32_t reg; /*!< Trace and Debug registers */ + + struct { + __IM uint32_t BLOCK_EOF_CNT : 26; /*!< Reserved */ + __IM uint32_t DEZIGZAG_READY : 1; /*!< Reserved */ + __IM uint32_t DE_FRAME_EOF_CHECK : 1; /*!< Reserved */ + __IM uint32_t DE_DMA2D_IN_PUSH : 1; /*!< Reserved */ + uint32_t : 3; + } bit; + } DECODER_STATUS4; + + union { + __IOM uint32_t reg; /*!< Trace and Debug registers */ + + struct { + __IM uint32_t IDCT_HFM_DATA : 16; /*!< Reserved */ + __IM uint32_t NS0 : 3; /*!< Reserved */ + __IM uint32_t NS1 : 3; /*!< Reserved */ + __IM uint32_t NS2 : 3; /*!< Reserved */ + __IM uint32_t NS3 : 3; /*!< Reserved */ + __IM uint32_t DATA_LAST_O : 1; /*!< Reserved */ + __IM uint32_t RDN_RESULT : 1; /*!< redundant registers for jpeg */ + __IOM uint32_t RDN_ENA : 1; /*!< redundant control registers for jpeg */ + uint32_t : 1; + } bit; + } DECODER_STATUS5; + + union { + __IOM uint32_t reg; /*!< Trace and Debug registers */ + + struct { + __IM uint32_t PIC_BLOCK_NUM : 24; /*!< Reserved */ + uint32_t : 8; + } bit; + } STATUS5; + + union { + __IOM uint32_t reg; /*!< Trace and Debug registers */ + + struct { + __IOM uint32_t RDN_ECO_LOW : 32; /*!< redundant registers for jpeg */ + } bit; + } ECO_LOW; + + union { + __IOM uint32_t reg; /*!< Trace and Debug registers */ + + struct { + __IOM uint32_t RDN_ECO_HIGH : 32; /*!< redundant registers for jpeg */ + } bit; + } ECO_HIGH; + __IM uint32_t RESERVED1[19]; + + union { + __IOM uint32_t reg; /*!< Trace and Debug registers */ + + struct { + uint32_t : 31; + __IOM uint32_t CLK_EN : 1; /*!< Reserved */ + } bit; + } SYS; + + union { + __IOM uint32_t reg; /*!< Trace and Debug registers */ + + struct { + __IOM uint32_t JPEG_VER : 28; /*!< Reserved */ + uint32_t : 4; + } bit; + } VERSION; +} JPEG_Type; /*!< Size = 256 (0x100) */ + + + +/* =========================================================================================================================== */ +/* ================ LCD_CAM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Camera/LCD Controller (LCD_CAM) + */ + +typedef struct { /*!< LCD_CAM Structure */ + + union { + __IOM uint32_t reg; /*!< LCD clock config register. */ + + struct { + __IOM uint32_t LCD_CLKCNT_N : 6; /*!< f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk + is 0. */ + __IOM uint32_t LCD_CLK_EQU_SYSCLK : 1; /*!< 1: f_LCD_PCLK = f_LCD_CLK. 0: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + + 1). */ + __IOM uint32_t LCD_CK_IDLE_EDGE : 1; /*!< 1: LCD_PCLK line is high when idle 0: LCD_PCLK line is low when + idle. */ + __IOM uint32_t LCD_CK_OUT_EDGE : 1; /*!< 1: LCD_PCLK line is high in the first half data cycle. 0: LCD_PCLK + line is low in the second half data cycle. */ + __IOM uint32_t LCD_CLKM_DIV_NUM : 8; /*!< Integral LCD clock divider value */ + __IOM uint32_t LCD_CLKM_DIV_B : 6; /*!< Fractional clock divider numerator value */ + __IOM uint32_t LCD_CLKM_DIV_A : 6; /*!< Fractional clock divider denominator value */ + __IOM uint32_t LCD_CLK_SEL : 2; /*!< Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. + 3: no clock. */ + __IOM uint32_t CLK_EN : 1; /*!< Set this bit to enable clk gate */ + } bit; + } LCD_CLOCK; + + union { + __IOM uint32_t reg; /*!< CAM config register. */ + + struct { + __IOM uint32_t CAM_STOP_EN : 1; /*!< Camera stop enable signal, 1: camera stops when DMA Rx FIFO + is full. 0: Not stop. */ + __IOM uint32_t CAM_VSYNC_FILTER_THRES : 3;/*!< Filter threshold value for CAM_VSYNC signal. */ + __IOM uint32_t CAM_UPDATE : 1; /*!< 1: Update Camera registers, will be cleared by hardware. 0 : + Not care. */ + __IOM uint32_t CAM_BYTE_ORDER : 1; /*!< 1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] + in one byte mode, and bits[15:0] to bits[0:15] in two byte + mode. 0: Not change. */ + __IOM uint32_t CAM_BIT_ORDER : 1; /*!< 1: invert data byte order, only valid in 2 byte mode. 0: Not + change. */ + __IOM uint32_t CAM_LINE_INT_EN : 1; /*!< 1: Enable to generate CAM_HS_INT. 0: Disable. */ + __IOM uint32_t CAM_VS_EOF_EN : 1; /*!< 1: CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled + by reg_cam_rec_data_cyclelen. */ + __IOM uint32_t CAM_CLKM_DIV_NUM : 8; /*!< Integral Camera clock divider value */ + __IOM uint32_t CAM_CLKM_DIV_B : 6; /*!< Fractional clock divider numerator value */ + __IOM uint32_t CAM_CLKM_DIV_A : 6; /*!< Fractional clock divider denominator value */ + __IOM uint32_t CAM_CLK_SEL : 2; /*!< Select Camera module source clock. 0: no clock. 1: APLL. 2: + CLK160. 3: no clock. */ + uint32_t : 1; + } bit; + } CAM_CTRL; + + union { + __IOM uint32_t reg; /*!< CAM config register. */ + + struct { + __IOM uint32_t CAM_REC_DATA_BYTELEN : 16; /*!< Camera receive data byte length minus 1 to set DMA in_suc_eof_int. */ + __IOM uint32_t CAM_LINE_INT_NUM : 6; /*!< The line number minus 1 to generate cam_hs_int. */ + __IOM uint32_t CAM_CLK_INV : 1; /*!< 1: Invert the input signal CAM_PCLK. 0: Not invert. */ + __IOM uint32_t CAM_VSYNC_FILTER_EN : 1; /*!< 1: Enable CAM_VSYNC filter function. 0: bypass. */ + __IOM uint32_t CAM_2BYTE_EN : 1; /*!< 1: The bit number of input data is 9~16. 0: The bit number of + input data is 0~8. */ + __IOM uint32_t CAM_DE_INV : 1; /*!< CAM_DE invert enable signal, valid in high level. */ + __IOM uint32_t CAM_HSYNC_INV : 1; /*!< CAM_HSYNC invert enable signal, valid in high level. */ + __IOM uint32_t CAM_VSYNC_INV : 1; /*!< CAM_VSYNC invert enable signal, valid in high level. */ + __IOM uint32_t CAM_VH_DE_MODE_EN : 1; /*!< 1: Input control signals are CAM_DE CAM_HSYNC and CAM_VSYNC. + 0: Input control signals are CAM_DE and CAM_VSYNC. */ + __IOM uint32_t CAM_START : 1; /*!< Camera module start signal. */ + __OM uint32_t CAM_RESET : 1; /*!< Camera module reset signal. */ + __OM uint32_t CAM_AFIFO_RESET : 1; /*!< Camera AFIFO reset signal. */ + } bit; + } CAM_CTRL1; + + union { + __IOM uint32_t reg; /*!< CAM YUV/RGB converter configuration register. */ + + struct { + uint32_t : 21; + __IOM uint32_t CAM_CONV_8BITS_DATA_INV : 1;/*!< 1:invert every two 8bits input data. 2. disabled. */ + __IOM uint32_t CAM_CONV_YUV2YUV_MODE : 2; /*!< 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable + yuv2yuv mode, trans_mode must be set to 1. */ + __IOM uint32_t CAM_CONV_YUV_MODE : 2; /*!< 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode + decides the yuv mode of Data_in */ + __IOM uint32_t CAM_CONV_PROTOCOL_MODE : 1;/*!< 0:BT601. 1:BT709. */ + __IOM uint32_t CAM_CONV_DATA_OUT_MODE : 1;/*!< LIMIT or FULL mode of Data out. 0: limit. 1: full */ + __IOM uint32_t CAM_CONV_DATA_IN_MODE : 1; /*!< LIMIT or FULL mode of Data in. 0: limit. 1: full */ + __IOM uint32_t CAM_CONV_MODE_8BITS_ON : 1;/*!< 0: 16bits mode. 1: 8bits mode. */ + __IOM uint32_t CAM_CONV_TRANS_MODE : 1; /*!< 0: YUV to RGB. 1: RGB to YUV. */ + __IOM uint32_t CAM_CONV_ENABLE : 1; /*!< 0: Bypass converter. 1: Enable converter. */ + } bit; + } CAM_RGB_YUV; + + union { + __IOM uint32_t reg; /*!< LCD YUV/RGB converter configuration register. */ + + struct { + uint32_t : 20; + __IOM uint32_t LCD_CONV_8BITS_DATA_INV : 1;/*!< 1:invert every two 8bits input data. 2. disabled. */ + __IOM uint32_t LCD_CONV_TXTORX : 1; /*!< 0: txtorx mode off. 1: txtorx mode on. */ + __IOM uint32_t LCD_CONV_YUV2YUV_MODE : 2; /*!< 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable + yuv2yuv mode, trans_mode must be set to 1. */ + __IOM uint32_t LCD_CONV_YUV_MODE : 2; /*!< 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode + decides the yuv mode of Data_in */ + __IOM uint32_t LCD_CONV_PROTOCOL_MODE : 1;/*!< 0:BT601. 1:BT709. */ + __IOM uint32_t LCD_CONV_DATA_OUT_MODE : 1;/*!< LIMIT or FULL mode of Data out. 0: limit. 1: full */ + __IOM uint32_t LCD_CONV_DATA_IN_MODE : 1; /*!< LIMIT or FULL mode of Data in. 0: limit. 1: full */ + __IOM uint32_t LCD_CONV_MODE_8BITS_ON : 1;/*!< 0: 16bits mode. 1: 8bits mode. */ + __IOM uint32_t LCD_CONV_TRANS_MODE : 1; /*!< 0: YUV to RGB. 1: RGB to YUV. */ + __IOM uint32_t LCD_CONV_ENABLE : 1; /*!< 0: Bypass converter. 1: Enable converter. */ + } bit; + } LCD_RGB_YUV; + + union { + __IOM uint32_t reg; /*!< LCD config register. */ + + struct { + __IOM uint32_t LCD_DOUT_CYCLELEN : 13; /*!< The output data cycles minus 1 of LCD module. */ + __IOM uint32_t LCD_ALWAYS_OUT_EN : 1; /*!< LCD always output when LCD is in LCD_DOUT state, unless reg_lcd_start + is cleared or reg_lcd_reset is set. */ + __IOM uint32_t LCD_DOUT_BYTE_SWIZZLE_MODE : 3;/*!< 0: ABAB->BABA. 1: ABC->ACB. 2: ABC->BAC. 3: ABC->BCA. 4:ABC->CAB. + 5:ABC->CBA */ + __IOM uint32_t LCD_DOUT_BYTE_SWIZZLE_ENABLE : 1;/*!< 1: enable byte swizzle 0: disable */ + __IOM uint32_t LCD_DOUT_BIT_ORDER : 1; /*!< 1: change bit order in every byte. 0: Not change. */ + __IOM uint32_t LCD_BYTE_MODE : 2; /*!< 2: 24bit mode. 1: 16bit mode. 0: 8bit mode */ + __IOM uint32_t LCD_UPDATE : 1; /*!< 1: Update LCD registers, will be cleared by hardware. 0 : Not + care. */ + __IOM uint32_t LCD_BIT_ORDER : 1; /*!< 1: Change data bit order, change LCD_DATA_out[7:0] to LCD_DATA_out[0:7] + in one byte mode, and bits[15:0] to bits[0:15] in two byte + mode. 0: Not change. */ + __IOM uint32_t LCD_BYTE_ORDER : 1; /*!< 1: invert data byte order, only valid in 2 byte mode. 0: Not + change. */ + __IOM uint32_t LCD_DOUT : 1; /*!< 1: Be able to send data out in LCD sequence when LCD starts. + 0: Disable. */ + __IOM uint32_t LCD_DUMMY : 1; /*!< 1: Enable DUMMY phase in LCD sequence when LCD starts. 0: Disable. */ + __IOM uint32_t LCD_CMD : 1; /*!< 1: Be able to send command in LCD sequence when LCD starts. + 0: Disable. */ + __IOM uint32_t LCD_START : 1; /*!< LCD start sending data enable signal, valid in high level. */ + __OM uint32_t LCD_RESET : 1; /*!< The value of command. */ + __IOM uint32_t LCD_DUMMY_CYCLELEN : 2; /*!< The dummy cycle length minus 1. */ + __IOM uint32_t LCD_CMD_2_CYCLE_EN : 1; /*!< The cycle length of command phase. 1: 2 cycles. 0: 1 cycle. */ + } bit; + } LCD_USER; + + union { + __IOM uint32_t reg; /*!< LCD config register. */ + + struct { + uint32_t : 4; + __IOM uint32_t LCD_WIRE_MODE : 2; /*!< The wire width of LCD output. 0: 8bit. 1: 16bit 2: 24bit */ + __IOM uint32_t LCD_VFK_CYCLELEN : 6; /*!< The setup cycle length minus 1 in LCD non-RGB mode. */ + __IOM uint32_t LCD_VBK_CYCLELEN : 13; /*!< The vertical back blank region cycle length minus 1 in LCD RGB + mode, or the hold time cycle length in LCD non-RGB mode. */ + __IOM uint32_t LCD_NEXT_FRAME_EN : 1; /*!< 1: Send the next frame data when the current frame is sent out. + 0: LCD stops when the current frame is sent out. */ + __IOM uint32_t LCD_BK_EN : 1; /*!< 1: Enable blank region when LCD sends data out. 0: No blank + region. */ + __OM uint32_t LCD_AFIFO_RESET : 1; /*!< LCD AFIFO reset signal. */ + __IOM uint32_t LCD_CD_DATA_SET : 1; /*!< 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DOUT + state. 0: LCD_CD = reg_cd_idle_edge. */ + __IOM uint32_t LCD_CD_DUMMY_SET : 1; /*!< 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DUMMY + state. 0: LCD_CD = reg_cd_idle_edge. */ + __IOM uint32_t LCD_CD_CMD_SET : 1; /*!< 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_CMD + state. 0: LCD_CD = reg_cd_idle_edge. */ + __IOM uint32_t LCD_CD_IDLE_EDGE : 1; /*!< The default value of LCD_CD. */ + } bit; + } LCD_MISC; + + union { + __IOM uint32_t reg; /*!< LCD config register. */ + + struct { + __IOM uint32_t LCD_HB_FRONT : 11; /*!< It is the horizontal blank front porch of a frame. */ + __IOM uint32_t LCD_VA_HEIGHT : 10; /*!< It is the vertical active height of a frame. */ + __IOM uint32_t LCD_VT_HEIGHT : 10; /*!< It is the vertical total height of a frame. */ + __IOM uint32_t LCD_RGB_MODE_EN : 1; /*!< 1: Enable LCD RGB mode. 0: Disable LCD RGB mode. */ + } bit; + } LCD_CTRL; + + union { + __IOM uint32_t reg; /*!< LCD config register. */ + + struct { + __IOM uint32_t LCD_VB_FRONT : 8; /*!< It is the vertical blank front porch of a frame. */ + __IOM uint32_t LCD_HA_WIDTH : 12; /*!< It is the horizontal active width of a frame. */ + __IOM uint32_t LCD_HT_WIDTH : 12; /*!< It is the horizontal total width of a frame. */ + } bit; + } LCD_CTRL1; + + union { + __IOM uint32_t reg; /*!< LCD config register. */ + + struct { + __IOM uint32_t LCD_VSYNC_WIDTH : 7; /*!< It is the position of LCD_VSYNC active pulse in a line. */ + __IOM uint32_t LCD_VSYNC_IDLE_POL : 1; /*!< It is the idle value of LCD_VSYNC. */ + __IOM uint32_t LCD_DE_IDLE_POL : 1; /*!< It is the idle value of LCD_DE. */ + __IOM uint32_t LCD_HS_BLANK_EN : 1; /*!< 1: The pulse of LCD_HSYNC is out in vertical blanking lines + RGB mode. 0: LCD_HSYNC pulse is valid only in active region + lines in RGB mode. */ + uint32_t : 6; + __IOM uint32_t LCD_HSYNC_WIDTH : 7; /*!< It is the position of LCD_HSYNC active pulse in a line. */ + __IOM uint32_t LCD_HSYNC_IDLE_POL : 1; /*!< It is the idle value of LCD_HSYNC. */ + __IOM uint32_t LCD_HSYNC_POSITION : 8; /*!< It is the position of LCD_HSYNC active pulse in a line. */ + } bit; + } LCD_CTRL2; + + union { + __IOM uint32_t reg; /*!< LCD config register. */ + + struct { + __IOM uint32_t LCD_FIRST_CMD_VALUE : 32; /*!< The LCD write command value of first cmd cycle. */ + } bit; + } LCD_FIRST_CMD_VAL; + + union { + __IOM uint32_t reg; /*!< LCD config register. */ + + struct { + __IOM uint32_t LCD_LATTER_CMD_VALUE : 32; /*!< The LCD write command value of latter cmd cycle. */ + } bit; + } LCD_LATTER_CMD_VAL; + + union { + __IOM uint32_t reg; /*!< LCD config register. */ + + struct { + __IOM uint32_t DOUT16_MODE : 2; /*!< The output data bit 0 is delayed by module clock LCD_CLK. 0: + output without delayed. 1: delay by the positive edge of + LCD_CLK. 2: delay by the negative edge of LCD_CLK. */ + __IOM uint32_t DOUT17_MODE : 2; /*!< The output data bit 2 is delayed by module clock LCD_CLK. 0: + output without delayed. 1: delay by the positive edge of + LCD_CLK. 2: delay by the negative edge of LCD_CLK. */ + __IOM uint32_t DOUT18_MODE : 2; /*!< The output data bit 4 is delayed by module clock LCD_CLK. 0: + output without delayed. 1: delay by the positive edge of + LCD_CLK. 2: delay by the negative edge of LCD_CLK. */ + __IOM uint32_t DOUT19_MODE : 2; /*!< The output data bit 6 is delayed by module clock LCD_CLK. 0: + output without delayed. 1: delay by the positive edge of + LCD_CLK. 2: delay by the negative edge of LCD_CLK. */ + __IOM uint32_t DOUT20_MODE : 2; /*!< The output data bit 8 is delayed by module clock LCD_CLK. 0: + output without delayed. 1: delay by the positive edge of + LCD_CLK. 2: delay by the negative edge of LCD_CLK. */ + __IOM uint32_t DOUT21_MODE : 2; /*!< The output data bit 10 is delayed by module clock LCD_CLK. 0: + output without delayed. 1: delay by the positive edge of + LCD_CLK. 2: delay by the negative edge of LCD_CLK. */ + __IOM uint32_t DOUT22_MODE : 2; /*!< The output data bit 12 is delayed by module clock LCD_CLK. 0: + output without delayed. 1: delay by the positive edge of + LCD_CLK. 2: delay by the negative edge of LCD_CLK. */ + __IOM uint32_t DOUT23_MODE : 2; /*!< The output data bit 14 is delayed by module clock LCD_CLK. 0: + output without delayed. 1: delay by the positive edge of + LCD_CLK. 2: delay by the negative edge of LCD_CLK. */ + __IOM uint32_t LCD_CD_MODE : 2; /*!< The output LCD_CD is delayed by module clock LCD_CLK. 0: output + without delayed. 1: delay by the positive edge of LCD_CLK. + 2: delay by the negative edge of LCD_CLK. */ + __IOM uint32_t LCD_DE_MODE : 2; /*!< The output LCD_DE is delayed by module clock LCD_CLK. 0: output + without delayed. 1: delay by the positive edge of LCD_CLK. + 2: delay by the negative edge of LCD_CLK. */ + __IOM uint32_t LCD_HSYNC_MODE : 2; /*!< The output LCD_HSYNC is delayed by module clock LCD_CLK. 0: + output without delayed. 1: delay by the positive edge of + LCD_CLK. 2: delay by the negative edge of LCD_CLK. */ + __IOM uint32_t LCD_VSYNC_MODE : 2; /*!< The output LCD_VSYNC is delayed by module clock LCD_CLK. 0: + output without delayed. 1: delay by the positive edge of + LCD_CLK. 2: delay by the negative edge of LCD_CLK. */ + uint32_t : 8; + } bit; + } LCD_DLY_MODE_CFG1; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t reg; /*!< LCD config register. */ + + struct { + __IOM uint32_t DOUT0_MODE : 2; /*!< The output data bit 0 is delayed by module clock LCD_CLK. 0: + output without delayed. 1: delay by the positive edge of + LCD_CLK. 2: delay by the negative edge of LCD_CLK. */ + __IOM uint32_t DOUT1_MODE : 2; /*!< The output data bit 2 is delayed by module clock LCD_CLK. 0: + output without delayed. 1: delay by the positive edge of + LCD_CLK. 2: delay by the negative edge of LCD_CLK. */ + __IOM uint32_t DOUT2_MODE : 2; /*!< The output data bit 4 is delayed by module clock LCD_CLK. 0: + output without delayed. 1: delay by the positive edge of + LCD_CLK. 2: delay by the negative edge of LCD_CLK. */ + __IOM uint32_t DOUT3_MODE : 2; /*!< The output data bit 6 is delayed by module clock LCD_CLK. 0: + output without delayed. 1: delay by the positive edge of + LCD_CLK. 2: delay by the negative edge of LCD_CLK. */ + __IOM uint32_t DOUT4_MODE : 2; /*!< The output data bit 8 is delayed by module clock LCD_CLK. 0: + output without delayed. 1: delay by the positive edge of + LCD_CLK. 2: delay by the negative edge of LCD_CLK. */ + __IOM uint32_t DOUT5_MODE : 2; /*!< The output data bit 10 is delayed by module clock LCD_CLK. 0: + output without delayed. 1: delay by the positive edge of + LCD_CLK. 2: delay by the negative edge of LCD_CLK. */ + __IOM uint32_t DOUT6_MODE : 2; /*!< The output data bit 12 is delayed by module clock LCD_CLK. 0: + output without delayed. 1: delay by the positive edge of + LCD_CLK. 2: delay by the negative edge of LCD_CLK. */ + __IOM uint32_t DOUT7_MODE : 2; /*!< The output data bit 14 is delayed by module clock LCD_CLK. 0: + output without delayed. 1: delay by the positive edge of + LCD_CLK. 2: delay by the negative edge of LCD_CLK. */ + __IOM uint32_t DOUT8_MODE : 2; /*!< The output data bit 16 is delayed by module clock LCD_CLK. 0: + output without delayed. 1: delay by the positive edge of + LCD_CLK. 2: delay by the negative edge of LCD_CLK. */ + __IOM uint32_t DOUT9_MODE : 2; /*!< The output data bit 18 is delayed by module clock LCD_CLK. 0: + output without delayed. 1: delay by the positive edge of + LCD_CLK. 2: delay by the negative edge of LCD_CLK. */ + __IOM uint32_t DOUT10_MODE : 2; /*!< The output data bit 20 is delayed by module clock LCD_CLK. 0: + output without delayed. 1: delay by the positive edge of + LCD_CLK. 2: delay by the negative edge of LCD_CLK. */ + __IOM uint32_t DOUT11_MODE : 2; /*!< The output data bit 22 is delayed by module clock LCD_CLK. 0: + output without delayed. 1: delay by the positive edge of + LCD_CLK. 2: delay by the negative edge of LCD_CLK. */ + __IOM uint32_t DOUT12_MODE : 2; /*!< The output data bit 24 is delayed by module clock LCD_CLK. 0: + output without delayed. 1: delay by the positive edge of + LCD_CLK. 2: delay by the negative edge of LCD_CLK. */ + __IOM uint32_t DOUT13_MODE : 2; /*!< The output data bit 26 is delayed by module clock LCD_CLK. 0: + output without delayed. 1: delay by the positive edge of + LCD_CLK. 2: delay by the negative edge of LCD_CLK. */ + __IOM uint32_t DOUT14_MODE : 2; /*!< The output data bit 28 is delayed by module clock LCD_CLK. 0: + output without delayed. 1: delay by the positive edge of + LCD_CLK. 2: delay by the negative edge of LCD_CLK. */ + __IOM uint32_t DOUT15_MODE : 2; /*!< The output data bit 30 is delayed by module clock LCD_CLK. 0: + output without delayed. 1: delay by the positive edge of + LCD_CLK. 2: delay by the negative edge of LCD_CLK. */ + } bit; + } LCD_DLY_MODE_CFG2; + __IM uint32_t RESERVED1[10]; + + union { + __IOM uint32_t reg; /*!< LCDCAM interrupt enable register. */ + + struct { + __IOM uint32_t LCD_VSYNC_INT_ENA : 1; /*!< The enable bit for LCD frame end interrupt. */ + __IOM uint32_t LCD_TRANS_DONE_INT_ENA : 1;/*!< The enable bit for lcd transfer end interrupt. */ + __IOM uint32_t CAM_VSYNC_INT_ENA : 1; /*!< The enable bit for Camera frame end interrupt. */ + __IOM uint32_t CAM_HS_INT_ENA : 1; /*!< The enable bit for Camera line interrupt. */ + uint32_t : 28; + } bit; + } LC_DMA_INT_ENA; + + union { + __IOM uint32_t reg; /*!< LCDCAM interrupt raw register, valid in level. */ + + struct { + __IM uint32_t LCD_VSYNC_INT_RAW : 1; /*!< The raw bit for LCD frame end interrupt. */ + __IM uint32_t LCD_TRANS_DONE_INT_RAW : 1;/*!< The raw bit for lcd transfer end interrupt. */ + __IM uint32_t CAM_VSYNC_INT_RAW : 1; /*!< The raw bit for Camera frame end interrupt. */ + __IM uint32_t CAM_HS_INT_RAW : 1; /*!< The raw bit for Camera line interrupt. */ + uint32_t : 28; + } bit; + } LC_DMA_INT_RAW; + + union { + __IOM uint32_t reg; /*!< LCDCAM interrupt status register. */ + + struct { + __IM uint32_t LCD_VSYNC_INT_ST : 1; /*!< The status bit for LCD frame end interrupt. */ + __IM uint32_t LCD_TRANS_DONE_INT_ST : 1; /*!< The status bit for lcd transfer end interrupt. */ + __IM uint32_t CAM_VSYNC_INT_ST : 1; /*!< The status bit for Camera frame end interrupt. */ + __IM uint32_t CAM_HS_INT_ST : 1; /*!< The status bit for Camera transfer end interrupt. */ + uint32_t : 28; + } bit; + } LC_DMA_INT_ST; + + union { + __IOM uint32_t reg; /*!< LCDCAM interrupt clear register. */ + + struct { + __OM uint32_t LCD_VSYNC_INT_CLR : 1; /*!< The clear bit for LCD frame end interrupt. */ + __OM uint32_t LCD_TRANS_DONE_INT_CLR : 1;/*!< The clear bit for lcd transfer end interrupt. */ + __OM uint32_t CAM_VSYNC_INT_CLR : 1; /*!< The clear bit for Camera frame end interrupt. */ + __OM uint32_t CAM_HS_INT_CLR : 1; /*!< The clear bit for Camera line interrupt. */ + uint32_t : 28; + } bit; + } LC_DMA_INT_CLR; + __IM uint32_t RESERVED2[34]; + + union { + __IOM uint32_t reg; /*!< Version register */ + + struct { + __IOM uint32_t LC_DATE : 28; /*!< LCD_CAM version control register */ + uint32_t : 4; + } bit; + } LC_REG_DATE; +} LCD_CAM_Type; /*!< Size = 256 (0x100) */ + + + +/* =========================================================================================================================== */ +/* ================ LEDC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief LED Control PWM (Pulse Width Modulation) (LEDC) + */ + +typedef struct { /*!< LEDC Structure */ + __IOM uint32_t CH0_CONF0; /*!< Configuration register 0 for channel 0 */ + __IOM uint32_t CH0_HPOINT; /*!< High point register for channel 0 */ + __IOM uint32_t CH0_DUTY; /*!< Initial duty cycle register for channel 0 */ + + union { + __IOM uint32_t reg; /*!< Configuration register 1 for channel 0 */ + + struct { + uint32_t : 31; + __IOM uint32_t DUTY_START_CH : 1; /*!< Configures whether the duty cycle fading configurations take + effect.\\0: Not take effect\\1: Take effect */ + } bit; + } CH0_CONF1; + __IOM uint32_t CH0_DUTY_R; /*!< Current duty cycle register for channel 0 */ + __IM uint32_t RESERVED[15]; + __IOM uint32_t CH1_CONF0; /*!< Configuration register 0 for channel 1 */ + __IOM uint32_t CH1_HPOINT; /*!< High point register for channel 1 */ + __IOM uint32_t CH1_DUTY; /*!< Initial duty cycle register for channel 1 */ + + union { + __IOM uint32_t reg; /*!< Configuration register 1 for channel 1 */ + + struct { + uint32_t : 31; + __IOM uint32_t DUTY_START_CH : 1; /*!< Configures whether the duty cycle fading configurations take + effect.\\0: Not take effect\\1: Take effect */ + } bit; + } CH1_CONF1; + __IOM uint32_t CH1_DUTY_R; /*!< Current duty cycle register for channel 1 */ + __IM uint32_t RESERVED1[15]; + + union { + __IOM uint32_t CH2_CONF0; /*!< Configuration register 0 for channel 2 */ + __IOM uint32_t TIMER0_CONF; /*!< Timer 0 configuration register */ + }; + + union { + __IOM uint32_t CH2_HPOINT; /*!< High point register for channel 2 */ + __IOM uint32_t TIMER0_VALUE; /*!< Timer 0 current counter value register */ + }; + __IOM uint32_t CH2_DUTY; /*!< Initial duty cycle register for channel 2 */ + + union { + __IOM uint32_t reg; /*!< Configuration register 1 for channel 2 */ + + struct { + uint32_t : 31; + __IOM uint32_t DUTY_START_CH : 1; /*!< Configures whether the duty cycle fading configurations take + effect.\\0: Not take effect\\1: Take effect */ + } bit; + } CH2_CONF1; + __IOM uint32_t CH2_DUTY_R; /*!< Current duty cycle register for channel 2 */ + __IM uint32_t RESERVED2[3]; + + union { + __IOM uint32_t TIMER1_CONF; /*!< Timer 1 configuration register */ + + union { + __IOM uint32_t reg; /*!< Interrupt raw status register */ + + struct { + __IOM uint32_t TIMER0_OVF_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of LEDC_TIMER0_OVF_INT. + Triggered when the timer0 has reached its maximum counter + value. */ + __IOM uint32_t TIMER1_OVF_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of LEDC_TIMER1_OVF_INT. + Triggered when the timer1 has reached its maximum counter + value. */ + __IOM uint32_t TIMER2_OVF_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of LEDC_TIMER2_OVF_INT. + Triggered when the timer2 has reached its maximum counter + value. */ + __IOM uint32_t TIMER3_OVF_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of LEDC_TIMER3_OVF_INT. + Triggered when the timer3 has reached its maximum counter + value. */ + __IOM uint32_t DUTY_CHNG_END_CH0_INT_RAW : 1;/*!< Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. + Triggered when the fading of duty has finished. */ + __IOM uint32_t DUTY_CHNG_END_CH1_INT_RAW : 1;/*!< Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. + Triggered when the fading of duty has finished. */ + __IOM uint32_t DUTY_CHNG_END_CH2_INT_RAW : 1;/*!< Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. + Triggered when the fading of duty has finished. */ + __IOM uint32_t DUTY_CHNG_END_CH3_INT_RAW : 1;/*!< Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. + Triggered when the fading of duty has finished. */ + __IOM uint32_t DUTY_CHNG_END_CH4_INT_RAW : 1;/*!< Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. + Triggered when the fading of duty has finished. */ + __IOM uint32_t DUTY_CHNG_END_CH5_INT_RAW : 1;/*!< Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. + Triggered when the fading of duty has finished. */ + __IOM uint32_t DUTY_CHNG_END_CH6_INT_RAW : 1;/*!< Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH6_INT. + Triggered when the fading of duty has finished. */ + __IOM uint32_t DUTY_CHNG_END_CH7_INT_RAW : 1;/*!< Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH7_INT. + Triggered when the fading of duty has finished. */ + __IOM uint32_t OVF_CNT_CH0_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH0_INT. + Triggered when the ovf_cnt has reached the value specified + by LEDC_OVF_NUM_CH0. */ + __IOM uint32_t OVF_CNT_CH1_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH1_INT. + Triggered when the ovf_cnt has reached the value specified + by LEDC_OVF_NUM_CH1. */ + __IOM uint32_t OVF_CNT_CH2_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH2_INT. + Triggered when the ovf_cnt has reached the value specified + by LEDC_OVF_NUM_CH2. */ + __IOM uint32_t OVF_CNT_CH3_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH3_INT. + Triggered when the ovf_cnt has reached the value specified + by LEDC_OVF_NUM_CH3. */ + __IOM uint32_t OVF_CNT_CH4_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH4_INT. + Triggered when the ovf_cnt has reached the value specified + by LEDC_OVF_NUM_CH4. */ + __IOM uint32_t OVF_CNT_CH5_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH5_INT. + Triggered when the ovf_cnt has reached the value specified + by LEDC_OVF_NUM_CH5. */ + __IOM uint32_t OVF_CNT_CH6_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH6_INT. + Triggered when the ovf_cnt has reached the value specified + by LEDC_OVF_NUM_CH6. */ + __IOM uint32_t OVF_CNT_CH7_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH7_INT. + Triggered when the ovf_cnt has reached the value specified + by LEDC_OVF_NUM_CH7. */ + uint32_t : 12; + } bit; + } INT_RAW; + }; + + union { + __IOM uint32_t TIMER1_VALUE; /*!< Timer 1 current counter value register */ + + union { + __IOM uint32_t reg; /*!< Interrupt masked status register */ + + struct { + __IM uint32_t TIMER0_OVF_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of LEDC_TIMER0_OVF_INT. + Valid only when LEDC_TIMER0_OVF_INT_ENA is set to 1. */ + __IM uint32_t TIMER1_OVF_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of LEDC_TIMER1_OVF_INT. + Valid only when LEDC_TIMER1_OVF_INT_ENA is set to 1. */ + __IM uint32_t TIMER2_OVF_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of LEDC_TIMER2_OVF_INT. + Valid only when LEDC_TIMER2_OVF_INT_ENA is set to 1. */ + __IM uint32_t TIMER3_OVF_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of LEDC_TIMER3_OVF_INT. + Valid only when LEDC_TIMER3_OVF_INT_ENA is set to 1. */ + __IM uint32_t DUTY_CHNG_END_CH0_INT_ST : 1;/*!< Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. + Valid only when LEDC_DUTY_CHNG_END_CH0_INT_ENA is set to + 1. */ + __IM uint32_t DUTY_CHNG_END_CH1_INT_ST : 1;/*!< Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. + Valid only when LEDC_DUTY_CHNG_END_CH1_INT_ENA is set to + 1. */ + __IM uint32_t DUTY_CHNG_END_CH2_INT_ST : 1;/*!< Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. + Valid only when LEDC_DUTY_CHNG_END_CH2_INT_ENA is set to + 1. */ + __IM uint32_t DUTY_CHNG_END_CH3_INT_ST : 1;/*!< Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. + Valid only when LEDC_DUTY_CHNG_END_CH3_INT_ENA is set to + 1. */ + __IM uint32_t DUTY_CHNG_END_CH4_INT_ST : 1;/*!< Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. + Valid only when LEDC_DUTY_CHNG_END_CH4_INT_ENA is set to + 1. */ + __IM uint32_t DUTY_CHNG_END_CH5_INT_ST : 1;/*!< Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. + Valid only when LEDC_DUTY_CHNG_END_CH5_INT_ENA is set to + 1. */ + __IM uint32_t DUTY_CHNG_END_CH6_INT_ST : 1;/*!< Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH6_INT. + Valid only when LEDC_DUTY_CHNG_END_CH6_INT_ENA is set to + 1. */ + __IM uint32_t DUTY_CHNG_END_CH7_INT_ST : 1;/*!< Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH7_INT. + Valid only when LEDC_DUTY_CHNG_END_CH7_INT_ENA is set to + 1. */ + __IM uint32_t OVF_CNT_CH0_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH0_INT. + Valid only when LEDC_OVF_CNT_CH0_INT_ENA is set to 1. */ + __IM uint32_t OVF_CNT_CH1_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH1_INT. + Valid only when LEDC_OVF_CNT_CH1_INT_ENA is set to 1. */ + __IM uint32_t OVF_CNT_CH2_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH2_INT. + Valid only when LEDC_OVF_CNT_CH2_INT_ENA is set to 1. */ + __IM uint32_t OVF_CNT_CH3_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH3_INT. + Valid only when LEDC_OVF_CNT_CH3_INT_ENA is set to 1. */ + __IM uint32_t OVF_CNT_CH4_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH4_INT. + Valid only when LEDC_OVF_CNT_CH4_INT_ENA is set to 1. */ + __IM uint32_t OVF_CNT_CH5_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH5_INT. + Valid only when LEDC_OVF_CNT_CH5_INT_ENA is set to 1. */ + __IM uint32_t OVF_CNT_CH6_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH6_INT. + Valid only when LEDC_OVF_CNT_CH6_INT_ENA is set to 1. */ + __IM uint32_t OVF_CNT_CH7_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH7_INT. + Valid only when LEDC_OVF_CNT_CH7_INT_ENA is set to 1. */ + uint32_t : 12; + } bit; + } INT_ST; + }; + + union { + __IOM uint32_t reg; /*!< Interrupt enable register */ + + struct { + __IOM uint32_t TIMER0_OVF_INT_ENA : 1; /*!< Enable bit: Write 1 to enable LEDC_TIMER0_OVF_INT. */ + __IOM uint32_t TIMER1_OVF_INT_ENA : 1; /*!< Enable bit: Write 1 to enable LEDC_TIMER1_OVF_INT. */ + __IOM uint32_t TIMER2_OVF_INT_ENA : 1; /*!< Enable bit: Write 1 to enable LEDC_TIMER2_OVF_INT. */ + __IOM uint32_t TIMER3_OVF_INT_ENA : 1; /*!< Enable bit: Write 1 to enable LEDC_TIMER3_OVF_INT. */ + __IOM uint32_t DUTY_CHNG_END_CH0_INT_ENA : 1;/*!< Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH0_INT. */ + __IOM uint32_t DUTY_CHNG_END_CH1_INT_ENA : 1;/*!< Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH1_INT. */ + __IOM uint32_t DUTY_CHNG_END_CH2_INT_ENA : 1;/*!< Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH2_INT. */ + __IOM uint32_t DUTY_CHNG_END_CH3_INT_ENA : 1;/*!< Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH3_INT. */ + __IOM uint32_t DUTY_CHNG_END_CH4_INT_ENA : 1;/*!< Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH4_INT. */ + __IOM uint32_t DUTY_CHNG_END_CH5_INT_ENA : 1;/*!< Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH5_INT. */ + __IOM uint32_t DUTY_CHNG_END_CH6_INT_ENA : 1;/*!< Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH6_INT. */ + __IOM uint32_t DUTY_CHNG_END_CH7_INT_ENA : 1;/*!< Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH7_INT. */ + __IOM uint32_t OVF_CNT_CH0_INT_ENA : 1; /*!< Enable bit: Write 1 to enable LEDC_OVF_CNT_CH0_INT. */ + __IOM uint32_t OVF_CNT_CH1_INT_ENA : 1; /*!< Enable bit: Write 1 to enable LEDC_OVF_CNT_CH1_INT. */ + __IOM uint32_t OVF_CNT_CH2_INT_ENA : 1; /*!< Enable bit: Write 1 to enable LEDC_OVF_CNT_CH2_INT. */ + __IOM uint32_t OVF_CNT_CH3_INT_ENA : 1; /*!< Enable bit: Write 1 to enable LEDC_OVF_CNT_CH3_INT. */ + __IOM uint32_t OVF_CNT_CH4_INT_ENA : 1; /*!< Enable bit: Write 1 to enable LEDC_OVF_CNT_CH4_INT. */ + __IOM uint32_t OVF_CNT_CH5_INT_ENA : 1; /*!< Enable bit: Write 1 to enable LEDC_OVF_CNT_CH5_INT. */ + __IOM uint32_t OVF_CNT_CH6_INT_ENA : 1; /*!< Enable bit: Write 1 to enable LEDC_OVF_CNT_CH6_INT. */ + __IOM uint32_t OVF_CNT_CH7_INT_ENA : 1; /*!< Enable bit: Write 1 to enable LEDC_OVF_CNT_CH7_INT. */ + uint32_t : 12; + } bit; + } INT_ENA; + + union { + __IOM uint32_t reg; /*!< Interrupt clear register */ + + struct { + __OM uint32_t TIMER0_OVF_INT_CLR : 1; /*!< Clear bit: Write 1 to clear LEDC_TIMER0_OVF_INT. */ + __OM uint32_t TIMER1_OVF_INT_CLR : 1; /*!< Clear bit: Write 1 to clear LEDC_TIMER1_OVF_INT. */ + __OM uint32_t TIMER2_OVF_INT_CLR : 1; /*!< Clear bit: Write 1 to clear LEDC_TIMER2_OVF_INT. */ + __OM uint32_t TIMER3_OVF_INT_CLR : 1; /*!< Clear bit: Write 1 to clear LEDC_TIMER3_OVF_INT. */ + __OM uint32_t DUTY_CHNG_END_CH0_INT_CLR : 1;/*!< Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH0_INT. */ + __OM uint32_t DUTY_CHNG_END_CH1_INT_CLR : 1;/*!< Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH1_INT. */ + __OM uint32_t DUTY_CHNG_END_CH2_INT_CLR : 1;/*!< Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH2_INT. */ + __OM uint32_t DUTY_CHNG_END_CH3_INT_CLR : 1;/*!< Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH3_INT. */ + __OM uint32_t DUTY_CHNG_END_CH4_INT_CLR : 1;/*!< Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH4_INT. */ + __OM uint32_t DUTY_CHNG_END_CH5_INT_CLR : 1;/*!< Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH5_INT. */ + __OM uint32_t DUTY_CHNG_END_CH6_INT_CLR : 1;/*!< Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH6_INT. */ + __OM uint32_t DUTY_CHNG_END_CH7_INT_CLR : 1;/*!< Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH7_INT. */ + __OM uint32_t OVF_CNT_CH0_INT_CLR : 1; /*!< Clear bit: Write 1 to clear LEDC_OVF_CNT_CH0_INT. */ + __OM uint32_t OVF_CNT_CH1_INT_CLR : 1; /*!< Clear bit: Write 1 to clear LEDC_OVF_CNT_CH1_INT. */ + __OM uint32_t OVF_CNT_CH2_INT_CLR : 1; /*!< Clear bit: Write 1 to clear LEDC_OVF_CNT_CH2_INT. */ + __OM uint32_t OVF_CNT_CH3_INT_CLR : 1; /*!< Clear bit: Write 1 to clear LEDC_OVF_CNT_CH3_INT. */ + __OM uint32_t OVF_CNT_CH4_INT_CLR : 1; /*!< Clear bit: Write 1 to clear LEDC_OVF_CNT_CH4_INT. */ + __OM uint32_t OVF_CNT_CH5_INT_CLR : 1; /*!< Clear bit: Write 1 to clear LEDC_OVF_CNT_CH5_INT. */ + __OM uint32_t OVF_CNT_CH6_INT_CLR : 1; /*!< Clear bit: Write 1 to clear LEDC_OVF_CNT_CH6_INT. */ + __OM uint32_t OVF_CNT_CH7_INT_CLR : 1; /*!< Clear bit: Write 1 to clear LEDC_OVF_CNT_CH7_INT. */ + uint32_t : 12; + } bit; + } INT_CLR; + __IM uint32_t RESERVED3[4]; + __IOM uint32_t TIMER2_CONF; /*!< Timer 2 configuration register */ + __IOM uint32_t TIMER2_VALUE; /*!< Timer 2 current counter value register */ + __IM uint32_t RESERVED4[2]; + __IOM uint32_t CH3_CONF0; /*!< Configuration register 0 for channel 3 */ + __IOM uint32_t CH3_HPOINT; /*!< High point register for channel 3 */ + __IOM uint32_t CH3_DUTY; /*!< Initial duty cycle register for channel 3 */ + + union { + __IOM uint32_t reg; /*!< Configuration register 1 for channel 3 */ + + struct { + uint32_t : 31; + __IOM uint32_t DUTY_START_CH : 1; /*!< Configures whether the duty cycle fading configurations take + effect.\\0: Not take effect\\1: Take effect */ + } bit; + } CH3_CONF1; + + union { + __IOM uint32_t CH3_DUTY_R; /*!< Current duty cycle register for channel 3 */ + __IOM uint32_t TIMER3_CONF; /*!< Timer 3 configuration register */ + __IOM uint32_t CH0_GAMMA_CONF; /*!< Ledc ch0 gamma config register. */ + }; + __IOM uint32_t TIMER3_VALUE; /*!< Timer 3 current counter value register */ + __IM uint32_t RESERVED5[2]; + __IOM uint32_t CH1_GAMMA_CONF; /*!< Ledc ch1 gamma config register. */ + __IM uint32_t RESERVED6[3]; + + union { + __IOM uint32_t CH2_GAMMA_CONF; /*!< Ledc ch2 gamma config register. */ + + union { + __IOM uint32_t reg; /*!< Ledc event task enable bit register0. */ + + struct { + __IOM uint32_t EVT_DUTY_CHNG_END_CH0_EN : 1;/*!< Configures whether or not to enable the ledc_ch0_duty_chng_end + event.\\0: Disable\\1: Enable */ + __IOM uint32_t EVT_DUTY_CHNG_END_CH1_EN : 1;/*!< Configures whether or not to enable the ledc_ch1_duty_chng_end + event.\\0: Disable\\1: Enable */ + __IOM uint32_t EVT_DUTY_CHNG_END_CH2_EN : 1;/*!< Configures whether or not to enable the ledc_ch2_duty_chng_end + event.\\0: Disable\\1: Enable */ + __IOM uint32_t EVT_DUTY_CHNG_END_CH3_EN : 1;/*!< Configures whether or not to enable the ledc_ch3_duty_chng_end + event.\\0: Disable\\1: Enable */ + __IOM uint32_t EVT_DUTY_CHNG_END_CH4_EN : 1;/*!< Configures whether or not to enable the ledc_ch4_duty_chng_end + event.\\0: Disable\\1: Enable */ + __IOM uint32_t EVT_DUTY_CHNG_END_CH5_EN : 1;/*!< Configures whether or not to enable the ledc_ch5_duty_chng_end + event.\\0: Disable\\1: Enable */ + __IOM uint32_t EVT_DUTY_CHNG_END_CH6_EN : 1;/*!< Configures whether or not to enable the ledc_ch6_duty_chng_end + event.\\0: Disable\\1: Enable */ + __IOM uint32_t EVT_DUTY_CHNG_END_CH7_EN : 1;/*!< Configures whether or not to enable the ledc_ch7_duty_chng_end + event.\\0: Disable\\1: Enable */ + __IOM uint32_t EVT_OVF_CNT_PLS_CH0_EN : 1;/*!< Configures whether or not to enable the ledc_ch0_ovf_cnt_pls + event.\\0: Disable\\1: Enable */ + __IOM uint32_t EVT_OVF_CNT_PLS_CH1_EN : 1;/*!< Configures whether or not to enable the ledc_ch1_ovf_cnt_pls + event.\\0: Disable\\1: Enable */ + __IOM uint32_t EVT_OVF_CNT_PLS_CH2_EN : 1;/*!< Configures whether or not to enable the ledc_ch2_ovf_cnt_pls + event.\\0: Disable\\1: Enable */ + __IOM uint32_t EVT_OVF_CNT_PLS_CH3_EN : 1;/*!< Configures whether or not to enable the ledc_ch3_ovf_cnt_pls + event.\\0: Disable\\1: Enable */ + __IOM uint32_t EVT_OVF_CNT_PLS_CH4_EN : 1;/*!< Configures whether or not to enable the ledc_ch4_ovf_cnt_pls + event.\\0: Disable\\1: Enable */ + __IOM uint32_t EVT_OVF_CNT_PLS_CH5_EN : 1;/*!< Configures whether or not to enable the ledc_ch5_ovf_cnt_pls + event.\\0: Disable\\1: Enable */ + __IOM uint32_t EVT_OVF_CNT_PLS_CH6_EN : 1;/*!< Configures whether or not to enable the ledc_ch6_ovf_cnt_pls + event.\\0: Disable\\1: Enable */ + __IOM uint32_t EVT_OVF_CNT_PLS_CH7_EN : 1;/*!< Configures whether or not to enable the ledc_ch7_ovf_cnt_pls + event.\\0: Disable\\1: Enable */ + __IOM uint32_t EVT_TIME_OVF_TIMER0_EN : 1;/*!< Configures whether or not to enable the ledc_timer0_ovf event.\\0: + Disable\\1: Enable */ + __IOM uint32_t EVT_TIME_OVF_TIMER1_EN : 1;/*!< Configures whether or not to enable the ledc_timer1_ovf event.\\0: + Disable\\1: Enable */ + __IOM uint32_t EVT_TIME_OVF_TIMER2_EN : 1;/*!< Configures whether or not to enable the ledc_timer2_ovf event.\\0: + Disable\\1: Enable */ + __IOM uint32_t EVT_TIME_OVF_TIMER3_EN : 1;/*!< Configures whether or not to enable the ledc_timer3_ovf event.\\0: + Disable\\1: Enable */ + __IOM uint32_t EVT_TIME0_CMP_EN : 1; /*!< Configures whether or not to enable the ledc_timer0_cmp event.\\0: + Disable\\1: Enable */ + __IOM uint32_t EVT_TIME1_CMP_EN : 1; /*!< Configures whether or not to enable the ledc_timer1_cmp event.\\0: + Disable\\1: Enable */ + __IOM uint32_t EVT_TIME2_CMP_EN : 1; /*!< Configures whether or not to enable the ledc_timer2_cmp event.\\0: + Disable\\1: Enable */ + __IOM uint32_t EVT_TIME3_CMP_EN : 1; /*!< Configures whether or not to enable the ledc_timer3_cmp event.\\0: + Disable\\1: Enable */ + __IOM uint32_t TASK_DUTY_SCALE_UPDATE_CH0_EN : 1;/*!< Configures whether or not to enable the ledc_ch0_duty_scale_update + task.\\0: Disable\\1: Enable */ + __IOM uint32_t TASK_DUTY_SCALE_UPDATE_CH1_EN : 1;/*!< Configures whether or not to enable the ledc_ch1_duty_scale_update + task.\\0: Disable\\1: Enable */ + __IOM uint32_t TASK_DUTY_SCALE_UPDATE_CH2_EN : 1;/*!< Configures whether or not to enable the ledc_ch2_duty_scale_update + task.\\0: Disable\\1: Enable */ + __IOM uint32_t TASK_DUTY_SCALE_UPDATE_CH3_EN : 1;/*!< Configures whether or not to enable the ledc_ch3_duty_scale_update + task.\\0: Disable\\1: Enable */ + __IOM uint32_t TASK_DUTY_SCALE_UPDATE_CH4_EN : 1;/*!< Configures whether or not to enable the ledc_ch4_duty_scale_update + task.\\0: Disable\\1: Enable */ + __IOM uint32_t TASK_DUTY_SCALE_UPDATE_CH5_EN : 1;/*!< Configures whether or not to enable the ledc_ch5_duty_scale_update + task.\\0: Disable\\1: Enable */ + __IOM uint32_t TASK_DUTY_SCALE_UPDATE_CH6_EN : 1;/*!< Configures whether or not to enable the ledc_ch6_duty_scale_update + task.\\0: Disable\\1: Enable */ + __IOM uint32_t TASK_DUTY_SCALE_UPDATE_CH7_EN : 1;/*!< Configures whether or not to enable the ledc_ch7_duty_scale_update + task.\\0: Disable\\1: Enable */ + } bit; + } EVT_TASK_EN0; + }; + + union { + __IOM uint32_t reg; /*!< Ledc event task enable bit register1. */ + + struct { + __IOM uint32_t TASK_TIMER0_RES_UPDATE_EN : 1;/*!< Configures whether or not to enable ledc_timer0_res_update task.\\0: + Disable\\1: Enable */ + __IOM uint32_t TASK_TIMER1_RES_UPDATE_EN : 1;/*!< Configures whether or not to enable ledc_timer1_res_update task.\\0: + Disable\\1: Enable */ + __IOM uint32_t TASK_TIMER2_RES_UPDATE_EN : 1;/*!< Configures whether or not to enable ledc_timer2_res_update task.\\0: + Disable\\1: Enable */ + __IOM uint32_t TASK_TIMER3_RES_UPDATE_EN : 1;/*!< Configures whether or not to enable ledc_timer3_res_update task.\\0: + Disable\\1: Enable */ + __IOM uint32_t TASK_TIMER0_CAP_EN : 1; /*!< Configures whether or not to enable ledc_timer0_cap task.\\0: + Disable\\1: Enable */ + __IOM uint32_t TASK_TIMER1_CAP_EN : 1; /*!< Configures whether or not to enable ledc_timer1_cap task.\\0: + Disable\\1: Enable */ + __IOM uint32_t TASK_TIMER2_CAP_EN : 1; /*!< Configures whether or not to enable ledc_timer2_cap task.\\0: + Disable\\1: Enable */ + __IOM uint32_t TASK_TIMER3_CAP_EN : 1; /*!< Configures whether or not to enable ledc_timer3_cap task.\\0: + Disable\\1: Enable */ + __IOM uint32_t TASK_SIG_OUT_DIS_CH0_EN : 1;/*!< Configures whether or not to enable ledc_ch0_sig_out_dis task.\\0: + Disable\\1: Enable */ + __IOM uint32_t TASK_SIG_OUT_DIS_CH1_EN : 1;/*!< Configures whether or not to enable ledc_ch1_sig_out_dis task.\\0: + Disable\\1: Enable */ + __IOM uint32_t TASK_SIG_OUT_DIS_CH2_EN : 1;/*!< Configures whether or not to enable ledc_ch2_sig_out_dis task.\\0: + Disable\\1: Enable */ + __IOM uint32_t TASK_SIG_OUT_DIS_CH3_EN : 1;/*!< Configures whether or not to enable ledc_ch3_sig_out_dis task.\\0: + Disable\\1: Enable */ + __IOM uint32_t TASK_SIG_OUT_DIS_CH4_EN : 1;/*!< Configures whether or not to enable ledc_ch4_sig_out_dis task.\\0: + Disable\\1: Enable */ + __IOM uint32_t TASK_SIG_OUT_DIS_CH5_EN : 1;/*!< Configures whether or not to enable ledc_ch5_sig_out_dis task.\\0: + Disable\\1: Enable */ + __IOM uint32_t TASK_SIG_OUT_DIS_CH6_EN : 1;/*!< Configures whether or not to enable ledc_ch6_sig_out_dis task.\\0: + Disable\\1: Enable */ + __IOM uint32_t TASK_SIG_OUT_DIS_CH7_EN : 1;/*!< Configures whether or not to enable ledc_ch7_sig_out_dis task.\\0: + Disable\\1: Enable */ + __IOM uint32_t TASK_OVF_CNT_RST_CH0_EN : 1;/*!< Configures whether or not to enable ledc_ch0_ovf_cnt_rst task.\\0: + Disable\\1: Enable */ + __IOM uint32_t TASK_OVF_CNT_RST_CH1_EN : 1;/*!< Configures whether or not to enable ledc_ch1_ovf_cnt_rst task.\\0: + Disable\\1: Enable */ + __IOM uint32_t TASK_OVF_CNT_RST_CH2_EN : 1;/*!< Configures whether or not to enable ledc_ch2_ovf_cnt_rst task.\\0: + Disable\\1: Enable */ + __IOM uint32_t TASK_OVF_CNT_RST_CH3_EN : 1;/*!< Configures whether or not to enable ledc_ch3_ovf_cnt_rst task.\\0: + Disable\\1: Enable */ + __IOM uint32_t TASK_OVF_CNT_RST_CH4_EN : 1;/*!< Configures whether or not to enable ledc_ch4_ovf_cnt_rst task.\\0: + Disable\\1: Enable */ + __IOM uint32_t TASK_OVF_CNT_RST_CH5_EN : 1;/*!< Configures whether or not to enable ledc_ch5_ovf_cnt_rst task.\\0: + Disable\\1: Enable */ + __IOM uint32_t TASK_OVF_CNT_RST_CH6_EN : 1;/*!< Configures whether or not to enable ledc_ch6_ovf_cnt_rst task.\\0: + Disable\\1: Enable */ + __IOM uint32_t TASK_OVF_CNT_RST_CH7_EN : 1;/*!< Configures whether or not to enable ledc_ch7_ovf_cnt_rst task.\\0: + Disable\\1: Enable */ + __IOM uint32_t TASK_TIMER0_RST_EN : 1; /*!< Configures whether or not to enable ledc_timer0_rst task.\\0: + Disable\\1: Enable */ + __IOM uint32_t TASK_TIMER1_RST_EN : 1; /*!< Configures whether or not to enable ledc_timer1_rst task.\\0: + Disable\\1: Enable */ + __IOM uint32_t TASK_TIMER2_RST_EN : 1; /*!< Configures whether or not to enable ledc_timer2_rst task.\\0: + Disable\\1: Enable */ + __IOM uint32_t TASK_TIMER3_RST_EN : 1; /*!< Configures whether or not to enable ledc_timer3_rst task.\\0: + Disable\\1: Enable */ + __IOM uint32_t TASK_TIMER0_PAUSE_RESUME_EN : 1;/*!< Configures whether or not to enable ledc_timer0_pause_resume + task.\\0: Disable\\1: Enable */ + __IOM uint32_t TASK_TIMER1_PAUSE_RESUME_EN : 1;/*!< Configures whether or not to enable ledc_timer1_pause_resume + task.\\0: Disable\\1: Enable */ + __IOM uint32_t TASK_TIMER2_PAUSE_RESUME_EN : 1;/*!< Configures whether or not to enable ledc_timer2_pause_resume + task.\\0: Disable\\1: Enable */ + __IOM uint32_t TASK_TIMER3_PAUSE_RESUME_EN : 1;/*!< Configures whether or not to enable ledc_timer3_pause_resume + task.\\0: Disable\\1: Enable */ + } bit; + } EVT_TASK_EN1; + + union { + __IOM uint32_t reg; /*!< Ledc event task enable bit register2. */ + + struct { + __IOM uint32_t TASK_GAMMA_RESTART_CH0_EN : 1;/*!< Configures whether or not to enable ledc_ch0_gamma_restart task.\\0: + Disable\\1: Enable */ + __IOM uint32_t TASK_GAMMA_RESTART_CH1_EN : 1;/*!< Configures whether or not to enable ledc_ch1_gamma_restart task.\\0: + Disable\\1: Enable */ + __IOM uint32_t TASK_GAMMA_RESTART_CH2_EN : 1;/*!< Configures whether or not to enable ledc_ch2_gamma_restart task.\\0: + Disable\\1: Enable */ + __IOM uint32_t TASK_GAMMA_RESTART_CH3_EN : 1;/*!< Configures whether or not to enable ledc_ch3_gamma_restart task.\\0: + Disable\\1: Enable */ + __IOM uint32_t TASK_GAMMA_RESTART_CH4_EN : 1;/*!< Configures whether or not to enable ledc_ch4_gamma_restart task.\\0: + Disable\\1: Enable */ + __IOM uint32_t TASK_GAMMA_RESTART_CH5_EN : 1;/*!< Configures whether or not to enable ledc_ch5_gamma_restart task.\\0: + Disable\\1: Enable */ + __IOM uint32_t TASK_GAMMA_RESTART_CH6_EN : 1;/*!< Configures whether or not to enable ledc_ch6_gamma_restart task.\\0: + Disable\\1: Enable */ + __IOM uint32_t TASK_GAMMA_RESTART_CH7_EN : 1;/*!< Configures whether or not to enable ledc_ch7_gamma_restart task.\\0: + Disable\\1: Enable */ + __IOM uint32_t TASK_GAMMA_PAUSE_CH0_EN : 1;/*!< Configures whether or not to enable ledc_ch0_gamma_pause task.\\0: + Disable\\1: Enable */ + __IOM uint32_t TASK_GAMMA_PAUSE_CH1_EN : 1;/*!< Configures whether or not to enable ledc_ch1_gamma_pause task.\\0: + Disable\\1: Enable */ + __IOM uint32_t TASK_GAMMA_PAUSE_CH2_EN : 1;/*!< Configures whether or not to enable ledc_ch2_gamma_pause task.\\0: + Disable\\1: Enable */ + __IOM uint32_t TASK_GAMMA_PAUSE_CH3_EN : 1;/*!< Configures whether or not to enable ledc_ch3_gamma_pause task.\\0: + Disable\\1: Enable */ + __IOM uint32_t TASK_GAMMA_PAUSE_CH4_EN : 1;/*!< Configures whether or not to enable ledc_ch4_gamma_pause task.\\0: + Disable\\1: Enable */ + __IOM uint32_t TASK_GAMMA_PAUSE_CH5_EN : 1;/*!< Configures whether or not to enable ledc_ch5_gamma_pause task.\\0: + Disable\\1: Enable */ + __IOM uint32_t TASK_GAMMA_PAUSE_CH6_EN : 1;/*!< Configures whether or not to enable ledc_ch6_gamma_pause task.\\0: + Disable\\1: Enable */ + __IOM uint32_t TASK_GAMMA_PAUSE_CH7_EN : 1;/*!< Configures whether or not to enable ledc_ch7_gamma_pause task.\\0: + Disable\\1: Enable */ + __IOM uint32_t TASK_GAMMA_RESUME_CH0_EN : 1;/*!< Configures whether or not to enable ledc_ch0_gamma_resume task.\\0: + Disable\\1: Enable */ + __IOM uint32_t TASK_GAMMA_RESUME_CH1_EN : 1;/*!< Configures whether or not to enable ledc_ch1_gamma_resume task.\\0: + Disable\\1: Enable */ + __IOM uint32_t TASK_GAMMA_RESUME_CH2_EN : 1;/*!< Configures whether or not to enable ledc_ch2_gamma_resume task.\\0: + Disable\\1: Enable */ + __IOM uint32_t TASK_GAMMA_RESUME_CH3_EN : 1;/*!< Configures whether or not to enable ledc_ch3_gamma_resume task.\\0: + Disable\\1: Enable */ + __IOM uint32_t TASK_GAMMA_RESUME_CH4_EN : 1;/*!< Configures whether or not to enable ledc_ch4_gamma_resume task.\\0: + Disable\\1: Enable */ + __IOM uint32_t TASK_GAMMA_RESUME_CH5_EN : 1;/*!< Configures whether or not to enable ledc_ch5_gamma_resume task.\\0: + Disable\\1: Enable */ + __IOM uint32_t TASK_GAMMA_RESUME_CH6_EN : 1;/*!< Configures whether or not to enable ledc_ch6_gamma_resume task.\\0: + Disable\\1: Enable */ + __IOM uint32_t TASK_GAMMA_RESUME_CH7_EN : 1;/*!< Configures whether or not to enable ledc_ch7_gamma_resume task.\\0: + Disable\\1: Enable */ + uint32_t : 8; + } bit; + } EVT_TASK_EN2; + __IM uint32_t RESERVED7; + __IOM uint32_t CH3_GAMMA_CONF; /*!< Ledc ch3 gamma config register. */ + __IM uint32_t RESERVED8[3]; + + union { + __IOM uint32_t CH4_CONF0; /*!< Configuration register 0 for channel 4 */ + __IOM uint32_t CH4_GAMMA_CONF; /*!< Ledc ch4 gamma config register. */ + __IOM uint32_t TIMER0_CMP; /*!< Ledc timer0 compare value register. */ + }; + __IOM uint32_t CH4_HPOINT; /*!< High point register for channel 4 */ + __IOM uint32_t CH4_DUTY; /*!< Initial duty cycle register for channel 4 */ + + union { + __IOM uint32_t reg; /*!< Configuration register 1 for channel 4 */ + + struct { + uint32_t : 31; + __IOM uint32_t DUTY_START_CH : 1; /*!< Configures whether the duty cycle fading configurations take + effect.\\0: Not take effect\\1: Take effect */ + } bit; + } CH4_CONF1; + + union { + __IOM uint32_t CH4_DUTY_R; /*!< Current duty cycle register for channel 4 */ + __IOM uint32_t CH5_GAMMA_CONF; /*!< Ledc ch5 gamma config register. */ + __IOM uint32_t TIMER1_CMP; /*!< Ledc timer1 compare value register. */ + __IOM uint32_t TIMER0_CNT_CAP; /*!< Ledc timer0 captured count value register. */ + }; + __IM uint32_t RESERVED9[3]; + + union { + __IOM uint32_t CH6_GAMMA_CONF; /*!< Ledc ch6 gamma config register. */ + __IOM uint32_t TIMER2_CMP; /*!< Ledc timer2 compare value register. */ + __IOM uint32_t TIMER1_CNT_CAP; /*!< Ledc timer1 captured count value register. */ + }; + __IM uint32_t RESERVED10[3]; + + union { + __IOM uint32_t CH7_GAMMA_CONF; /*!< Ledc ch7 gamma config register. */ + __IOM uint32_t TIMER3_CMP; /*!< Ledc timer3 compare value register. */ + __IOM uint32_t TIMER2_CNT_CAP; /*!< Ledc timer2 captured count value register. */ + + union { + __IOM uint32_t reg; /*!< LEDC global configuration register */ + + struct { + __IOM uint32_t APB_CLK_SEL : 2; /*!< Configures the clock source for the four timers.\\0: APB_CLK\\1: + RC_FAST_CLK\\2: XTAL_CLK\\3: Invalid. No clock */ + __IOM uint32_t GAMMA_RAM_CLK_EN_CH0 : 1;/*!< Configures whether or not to open LEDC ch0 gamma ram clock gate.\\0: + Open the clock gate only when application writes or reads + LEDC ch0 gamma ram\\1: Force open the clock gate for LEDC + ch0 gamma ram */ + __IOM uint32_t GAMMA_RAM_CLK_EN_CH1 : 1;/*!< Configures whether or not to open LEDC ch1 gamma ram clock gate.\\0: + Open the clock gate only when application writes or reads + LEDC ch1 gamma ram\\1: Force open the clock gate for LEDC + ch1 gamma ram */ + __IOM uint32_t GAMMA_RAM_CLK_EN_CH2 : 1;/*!< Configures whether or not to open LEDC ch2 gamma ram clock gate.\\0: + Open the clock gate only when application writes or reads + LEDC ch2 gamma ram\\1: Force open the clock gate for LEDC + ch2 gamma ram */ + __IOM uint32_t GAMMA_RAM_CLK_EN_CH3 : 1;/*!< Configures whether or not to open LEDC ch3 gamma ram clock gate.\\0: + Open the clock gate only when application writes or reads + LEDC ch3 gamma ram\\1: Force open the clock gate for LEDC + ch3 gamma ram */ + __IOM uint32_t GAMMA_RAM_CLK_EN_CH4 : 1;/*!< Configures whether or not to open LEDC ch4 gamma ram clock gate.\\0: + Open the clock gate only when application writes or reads + LEDC ch4 gamma ram\\1: Force open the clock gate for LEDC + ch4 gamma ram */ + __IOM uint32_t GAMMA_RAM_CLK_EN_CH5 : 1;/*!< Configures whether or not to open LEDC ch5 gamma ram clock gate.\\0: + Open the clock gate only when application writes or reads + LEDC ch5 gamma ram\\1: Force open the clock gate for LEDC + ch5 gamma ram */ + __IOM uint32_t GAMMA_RAM_CLK_EN_CH6 : 1;/*!< Configures whether or not to open LEDC ch6 gamma ram clock gate.\\0: + Open the clock gate only when application writes or reads + LEDC ch6 gamma ram\\1: Force open the clock gate for LEDC + ch6 gamma ram */ + __IOM uint32_t GAMMA_RAM_CLK_EN_CH7 : 1;/*!< Configures whether or not to open LEDC ch7 gamma ram clock gate.\\0: + Open the clock gate only when application writes or reads + LEDC ch7 gamma ram\\1: Force open the clock gate for LEDC + ch7 gamma ram */ + uint32_t : 21; + __IOM uint32_t CLK_EN : 1; /*!< Configures whether or not to open register clock gate.\\0: Open + the clock gate only when application writes registers\\1: + Force open the clock gate for register */ + } bit; + } CONF; + }; + + union { + __IOM uint32_t reg; /*!< Version control register */ + + struct { + __IOM uint32_t LEDC_DATE : 28; /*!< Configures the version. */ + uint32_t : 4; + } bit; + } DATE; + __IM uint32_t RESERVED11[2]; + __IOM uint32_t TIMER3_CNT_CAP; /*!< Ledc timer3 captured count value register. */ + __IM uint32_t RESERVED12[3]; + __IOM uint32_t CH5_CONF0; /*!< Configuration register 0 for channel 5 */ + __IOM uint32_t CH5_HPOINT; /*!< High point register for channel 5 */ + __IOM uint32_t CH5_DUTY; /*!< Initial duty cycle register for channel 5 */ + + union { + __IOM uint32_t reg; /*!< Configuration register 1 for channel 5 */ + + struct { + uint32_t : 31; + __IOM uint32_t DUTY_START_CH : 1; /*!< Configures whether the duty cycle fading configurations take + effect.\\0: Not take effect\\1: Take effect */ + } bit; + } CH5_CONF1; + __IOM uint32_t CH5_DUTY_R; /*!< Current duty cycle register for channel 5 */ + __IM uint32_t RESERVED13[15]; + __IOM uint32_t CH6_CONF0; /*!< Configuration register 0 for channel 6 */ + __IOM uint32_t CH6_HPOINT; /*!< High point register for channel 6 */ + __IOM uint32_t CH6_DUTY; /*!< Initial duty cycle register for channel 6 */ + + union { + __IOM uint32_t reg; /*!< Configuration register 1 for channel 6 */ + + struct { + uint32_t : 31; + __IOM uint32_t DUTY_START_CH : 1; /*!< Configures whether the duty cycle fading configurations take + effect.\\0: Not take effect\\1: Take effect */ + } bit; + } CH6_CONF1; + __IOM uint32_t CH6_DUTY_R; /*!< Current duty cycle register for channel 6 */ + __IM uint32_t RESERVED14[15]; + __IOM uint32_t CH7_CONF0; /*!< Configuration register 0 for channel 7 */ + __IOM uint32_t CH7_HPOINT; /*!< High point register for channel 7 */ + __IOM uint32_t CH7_DUTY; /*!< Initial duty cycle register for channel 7 */ + + union { + __IOM uint32_t reg; /*!< Configuration register 1 for channel 7 */ + + struct { + uint32_t : 31; + __IOM uint32_t DUTY_START_CH : 1; /*!< Configures whether the duty cycle fading configurations take + effect.\\0: Not take effect\\1: Take effect */ + } bit; + } CH7_CONF1; + __IOM uint32_t CH7_DUTY_R; /*!< Current duty cycle register for channel 7 */ +} LEDC_Type; /*!< Size = 580 (0x244) */ + + + +/* =========================================================================================================================== */ +/* ================ LP_INTR ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Low-power Interrupt Controller (LP_INTR) + */ + +typedef struct { /*!< LP_INTR Structure */ + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 31; + __IOM uint32_t LP_SW_INT_RAW : 1; /*!< need_des */ + } bit; + } SW_INT_RAW; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 31; + __IM uint32_t LP_SW_INT_ST : 1; /*!< need_des */ + } bit; + } SW_INT_ST; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 31; + __IOM uint32_t LP_SW_INT_ENA : 1; /*!< need_des */ + } bit; + } SW_INT_ENA; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 31; + __OM uint32_t LP_SW_INT_CLR : 1; /*!< need_des */ + } bit; + } SW_INT_CLR; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 10; + __IM uint32_t LP_HUK_INTR_ST : 1; /*!< need_des */ + __IM uint32_t SYSREG_INTR_ST : 1; /*!< need_des */ + __IM uint32_t LP_SW_INTR_ST : 1; /*!< need_des */ + __IM uint32_t LP_EFUSE_INTR_ST : 1; /*!< need_des */ + __IM uint32_t LP_UART_INTR_ST : 1; /*!< need_des */ + __IM uint32_t LP_TSENS_INTR_ST : 1; /*!< need_des */ + __IM uint32_t LP_TOUCH_INTR_ST : 1; /*!< need_des */ + __IM uint32_t LP_SPI_INTR_ST : 1; /*!< need_des */ + __IM uint32_t LP_I2S_INTR_ST : 1; /*!< need_des */ + __IM uint32_t LP_I2C_INTR_ST : 1; /*!< need_des */ + __IM uint32_t LP_GPIO_INTR_ST : 1; /*!< need_des */ + __IM uint32_t LP_ADC_INTR_ST : 1; /*!< need_des */ + __IM uint32_t ANAPERI_INTR_ST : 1; /*!< need_des */ + __IM uint32_t PMU_REG_1_INTR_ST : 1; /*!< need_des */ + __IM uint32_t PMU_REG_0_INTR_ST : 1; /*!< need_des */ + __IM uint32_t MB_LP_INTR_ST : 1; /*!< need_des */ + __IM uint32_t MB_HP_INTR_ST : 1; /*!< need_des */ + __IM uint32_t LP_TIMER_REG_1_INTR_ST : 1;/*!< need_des */ + __IM uint32_t LP_TIMER_REG_0_INTR_ST : 1;/*!< need_des */ + __IM uint32_t LP_WDT_INTR_ST : 1; /*!< need_des */ + __IM uint32_t LP_RTC_INTR_ST : 1; /*!< need_des */ + __IM uint32_t HP_INTR_ST : 1; /*!< need_des */ + } bit; + } STATUS; + __IM uint32_t RESERVED[250]; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 31; + __IOM uint32_t CLK_EN : 1; /*!< need_des */ + } bit; + } DATE; +} LP_INTR_Type; /*!< Size = 1024 (0x400) */ + + + +/* =========================================================================================================================== */ +/* ================ LP_PERI ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief LP_PERI Peripheral (LP_PERI) + */ + +typedef struct { /*!< LP_PERI Structure */ + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 16; + __IOM uint32_t CK_EN_RNG : 1; /*!< need_des */ + __IOM uint32_t CK_EN_LP_TSENS : 1; /*!< need_des */ + __IOM uint32_t CK_EN_LP_PMS : 1; /*!< need_des */ + __IOM uint32_t CK_EN_LP_EFUSE : 1; /*!< need_des */ + __IOM uint32_t CK_EN_LP_IOMUX : 1; /*!< need_des */ + __IOM uint32_t CK_EN_LP_TOUCH : 1; /*!< need_des */ + __IOM uint32_t CK_EN_LP_SPI : 1; /*!< need_des */ + __IOM uint32_t CK_EN_LP_ADC : 1; /*!< need_des */ + __IOM uint32_t CK_EN_LP_I2S_TX : 1; /*!< need_des */ + __IOM uint32_t CK_EN_LP_I2S_RX : 1; /*!< need_des */ + __IOM uint32_t CK_EN_LP_I2S : 1; /*!< need_des */ + __IOM uint32_t CK_EN_LP_I2CMST : 1; /*!< need_des */ + __IOM uint32_t CK_EN_LP_I2C : 1; /*!< need_des */ + __IOM uint32_t CK_EN_LP_UART : 1; /*!< need_des */ + __IOM uint32_t CK_EN_LP_INTR : 1; /*!< need_des */ + __IOM uint32_t CK_EN_LP_CORE : 1; /*!< write 1 to force on lp_core clk */ + } bit; + } CLK_EN; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 24; + __IOM uint32_t LP_I2S_TX_CLK_SEL : 2; /*!< need_des */ + __IOM uint32_t LP_I2S_RX_CLK_SEL : 2; /*!< need_des */ + __IOM uint32_t LP_I2C_CLK_SEL : 2; /*!< need_des */ + __IOM uint32_t LP_UART_CLK_SEL : 2; /*!< need_des */ + } bit; + } CORE_CLK_SEL; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 18; + __IOM uint32_t RST_EN_LP_TSENS : 1; /*!< need_des */ + __IOM uint32_t RST_EN_LP_PMS : 1; /*!< need_des */ + __IOM uint32_t RST_EN_LP_EFUSE : 1; /*!< need_des */ + __IOM uint32_t RST_EN_LP_IOMUX : 1; /*!< need_des */ + __IOM uint32_t RST_EN_LP_TOUCH : 1; /*!< need_des */ + __IOM uint32_t RST_EN_LP_SPI : 1; /*!< need_des */ + __IOM uint32_t RST_EN_LP_ADC : 1; /*!< need_des */ + __IOM uint32_t RST_EN_LP_I2S : 1; /*!< need_des */ + __IOM uint32_t RST_EN_LP_I2CMST : 1; /*!< need_des */ + __IOM uint32_t RST_EN_LP_I2C : 1; /*!< need_des */ + __IOM uint32_t RST_EN_LP_UART : 1; /*!< need_des */ + __IOM uint32_t RST_EN_LP_INTR : 1; /*!< need_des */ + __IOM uint32_t RST_EN_LP_ROM : 1; /*!< need_des */ + __OM uint32_t RST_EN_LP_CORE : 1; /*!< need_des */ + } bit; + } RESET_EN; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 31; + __IOM uint32_t LPCORE_DBGM_UNAVAILABLE : 1;/*!< need_des */ + } bit; + } CPU; + __IM uint32_t RESERVED[6]; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __OM uint32_t LP_UART_WAKEUP_FLAG_CLR : 1;/*!< need_des */ + __IOM uint32_t LP_UART_WAKEUP_FLAG : 1; /*!< need_des */ + uint32_t : 27; + __IOM uint32_t LP_UART_WAKEUP_EN : 1; /*!< need_des */ + __IOM uint32_t LP_UART_MEM_FORCE_PD : 1; /*!< need_des */ + __IOM uint32_t LP_UART_MEM_FORCE_PU : 1; /*!< need_des */ + } bit; + } MEM_CTRL; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 6; + __IOM uint32_t SAR2_CLK_FORCE_ON : 1; /*!< need_des */ + __IOM uint32_t SAR1_CLK_FORCE_ON : 1; /*!< need_des */ + __IOM uint32_t LPADC_FUNC_DIV_NUM : 8; /*!< need_des */ + __IOM uint32_t LPADC_SAR2_DIV_NUM : 8; /*!< need_des */ + __IOM uint32_t LPADC_SAR1_DIV_NUM : 8; /*!< need_des */ + } bit; + } ADC_CTRL; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 24; + __IOM uint32_t LP_I2S_RX_CLKM_DIV_NUM : 8;/*!< need_des */ + } bit; + } LP_I2S_RXCLK_DIV_NUM; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 4; + __IOM uint32_t LP_I2S_RX_CLKM_DIV_YN1 : 1;/*!< need_des */ + __IOM uint32_t LP_I2S_RX_CLKM_DIV_Z : 9; /*!< need_des */ + __IOM uint32_t LP_I2S_RX_CLKM_DIV_Y : 9; /*!< need_des */ + __IOM uint32_t LP_I2S_RX_CLKM_DIV_X : 9; /*!< need_des */ + } bit; + } LP_I2S_RXCLK_DIV_XYZ; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 24; + __IOM uint32_t LP_I2S_TX_CLKM_DIV_NUM : 8;/*!< need_des */ + } bit; + } LP_I2S_TXCLK_DIV_NUM; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 4; + __IOM uint32_t LP_I2S_TX_CLKM_DIV_YN1 : 1;/*!< need_des */ + __IOM uint32_t LP_I2S_TX_CLKM_DIV_Z : 9; /*!< need_des */ + __IOM uint32_t LP_I2S_TX_CLKM_DIV_Y : 9; /*!< need_des */ + __IOM uint32_t LP_I2S_TX_CLKM_DIV_X : 9; /*!< need_des */ + } bit; + } LP_I2S_TXCLK_DIV_XYZ; + __IM uint32_t RESERVED1[239]; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 31; + __IOM uint32_t CLK_EN : 1; /*!< need_des */ + } bit; + } DATE; +} LP_PERI_Type; /*!< Size = 1024 (0x400) */ + + + +/* =========================================================================================================================== */ +/* ================ LP_SYS ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief LP_SYS Peripheral (LP_SYS) + */ + +typedef struct { /*!< LP_SYS Structure */ + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t VER_DATE : 32; /*!< need_des */ + } bit; + } LP_SYS_VER_DATE; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 16; + __IOM uint32_t ENA_SW_SEL_SYS_CLK : 1; /*!< reserved */ + __IOM uint32_t SW_SYS_CLK_SRC_SEL : 1; /*!< reserved */ + uint32_t : 14; + } bit; + } CLK_SEL_CTRL; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t LP_CORE_DISABLE : 1; /*!< lp cpu disable */ + __OM uint32_t SYS_SW_RST : 1; /*!< digital system software reset bit */ + __IOM uint32_t FORCE_DOWNLOAD_BOOT : 1; /*!< need_des */ + __IOM uint32_t DIG_FIB : 8; /*!< need_des */ + __IOM uint32_t IO_MUX_RESET_DISABLE : 1; /*!< reset disable bit for LP IOMUX */ + uint32_t : 2; + __IM uint32_t ANA_FIB : 7; /*!< need_des */ + __IOM uint32_t LP_FIB_SEL : 8; /*!< need_des */ + __OM uint32_t LP_CORE_ETM_WAKEUP_FLAG_CLR : 1;/*!< need_des */ + __IOM uint32_t LP_CORE_ETM_WAKEUP_FLAG : 1;/*!< need_des */ + __IOM uint32_t SYSTIMER_STALL_SEL : 1; /*!< 0: use systimer_stall signal from hp_core0, 1: use systimer_stall + signal from hp_core1 */ + } bit; + } SYS_CTRL; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t CLK_EN : 1; /*!< need_des */ + uint32_t : 13; + __IOM uint32_t LP_FOSC_HP_CKEN : 1; /*!< reserved */ + uint32_t : 17; + } bit; + } LP_CLK_CTRL; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t ANA_RST_BYPASS : 1; /*!< analog source reset bypass : wdt,brown out,super wdt,glitch */ + __IOM uint32_t SYS_RST_BYPASS : 1; /*!< system source reset bypass : software reset,hp wdt,lp wdt,efuse */ + __IOM uint32_t EFUSE_FORCE_NORST : 1; /*!< efuse force no reset control */ + uint32_t : 29; + } bit; + } LP_RST_CTRL; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t LP_CPU_BOOT_ADDR : 32; /*!< need_des */ + } bit; + } LP_CORE_BOOT_ADDR; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t SEL : 16; /*!< Bitmap to select RTC pads for ext wakeup1 */ + __OM uint32_t STATUS_CLR : 1; /*!< clear ext wakeup1 status */ + uint32_t : 15; + } bit; + } EXT_WAKEUP1; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IM uint32_t EXT_WAKEUP1_STATUS : 16; /*!< ext wakeup1 status */ + uint32_t : 16; + } bit; + } EXT_WAKEUP1_STATUS; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 5; + __IOM uint32_t LP_TCM_ROM_CLK_FORCE_ON : 1;/*!< need_des */ + uint32_t : 1; + __IOM uint32_t LP_TCM_RAM_CLK_FORCE_ON : 1;/*!< need_des */ + uint32_t : 24; + } bit; + } LP_TCM_PWR_CTRL; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t BOOT_ADDR_HP_LP : 32; /*!< need_des */ + } bit; + } BOOT_ADDR_HP_LP; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t LP_SCRATCH0 : 32; /*!< need_des */ + } bit; + } LP_STORE0; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t LP_SCRATCH1 : 32; /*!< need_des */ + } bit; + } LP_STORE1; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t LP_SCRATCH2 : 32; /*!< need_des */ + } bit; + } LP_STORE2; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t LP_SCRATCH3 : 32; /*!< need_des */ + } bit; + } LP_STORE3; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t LP_SCRATCH4 : 32; /*!< need_des */ + } bit; + } LP_STORE4; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t LP_SCRATCH5 : 32; /*!< need_des */ + } bit; + } LP_STORE5; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t LP_SCRATCH6 : 32; /*!< need_des */ + } bit; + } LP_STORE6; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t LP_SCRATCH7 : 32; /*!< need_des */ + } bit; + } LP_STORE7; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t LP_SCRATCH8 : 32; /*!< need_des */ + } bit; + } LP_STORE8; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t LP_SCRATCH9 : 32; /*!< need_des */ + } bit; + } LP_STORE9; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t LP_SCRATCH10 : 32; /*!< need_des */ + } bit; + } LP_STORE10; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t LP_SCRATCH11 : 32; /*!< need_des */ + } bit; + } LP_STORE11; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t LP_SCRATCH12 : 32; /*!< need_des */ + } bit; + } LP_STORE12; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t LP_SCRATCH13 : 32; /*!< need_des */ + } bit; + } LP_STORE13; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t LP_SCRATCH14 : 32; /*!< need_des */ + } bit; + } LP_STORE14; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t LP_SCRATCH15 : 32; /*!< need_des */ + } bit; + } LP_STORE15; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t PROBE_A_MOD_SEL : 16; /*!< need_des */ + __IOM uint32_t PROBE_A_TOP_SEL : 8; /*!< need_des */ + __IOM uint32_t PROBE_L_SEL : 2; /*!< need_des */ + __IOM uint32_t PROBE_H_SEL : 2; /*!< need_des */ + __IOM uint32_t PROBE_GLOBAL_EN : 1; /*!< need_des */ + uint32_t : 3; + } bit; + } LP_PROBEA_CTRL; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t PROBE_B_MOD_SEL : 16; /*!< need_des */ + __IOM uint32_t PROBE_B_TOP_SEL : 8; /*!< need_des */ + __IOM uint32_t PROBE_B_EN : 1; /*!< need_des */ + uint32_t : 7; + } bit; + } LP_PROBEB_CTRL; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IM uint32_t PROBE_TOP_OUT : 32; /*!< need_des */ + } bit; + } LP_PROBE_OUT; + __IM uint32_t RESERVED1[9]; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t F2S_APB_POSTW_EN : 1; /*!< reserved */ + uint32_t : 31; + } bit; + } F2S_APB_BRG_CNTL; + __IM uint32_t RESERVED2[24]; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t SW_HW_USB_PHY_SEL : 1; /*!< need_des */ + __IOM uint32_t SW_USB_PHY_SEL : 1; /*!< need_des */ + __OM uint32_t USBOTG20_WAKEUP_CLR : 1; /*!< clear usb wakeup to PMU. */ + __IOM uint32_t USBOTG20_IN_SUSPEND : 1; /*!< indicate usb otg2.0 is in suspend state. */ + uint32_t : 28; + } bit; + } USB_CTRL; + __IM uint32_t RESERVED3[2]; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t ANA_REG_XPD_PAD_GROUP : 8; /*!< Set 1 to power up pad group */ + uint32_t : 24; + } bit; + } ANA_XPD_PAD_GROUP; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t LP_TCM_RAM_RDN_ECO_EN : 1; /*!< need_des */ + __IM uint32_t LP_TCM_RAM_RDN_ECO_RESULT : 1;/*!< need_des */ + uint32_t : 30; + } bit; + } LP_TCM_RAM_RDN_ECO_CS; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t LP_TCM_RAM_RDN_ECO_LOW : 32;/*!< need_des */ + } bit; + } LP_TCM_RAM_RDN_ECO_LOW; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t LP_TCM_RAM_RDN_ECO_HIGH : 32;/*!< need_des */ + } bit; + } LP_TCM_RAM_RDN_ECO_HIGH; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t LP_TCM_ROM_RDN_ECO_EN : 1; /*!< need_des */ + __IM uint32_t LP_TCM_ROM_RDN_ECO_RESULT : 1;/*!< need_des */ + uint32_t : 30; + } bit; + } LP_TCM_ROM_RDN_ECO_CS; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t LP_TCM_ROM_RDN_ECO_LOW : 32;/*!< need_des */ + } bit; + } LP_TCM_ROM_RDN_ECO_LOW; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t LP_TCM_ROM_RDN_ECO_HIGH : 32;/*!< need_des */ + } bit; + } LP_TCM_ROM_RDN_ECO_HIGH; + __IM uint32_t RESERVED4[2]; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t CPU_CLK_EN : 1; /*!< clock gate enable for hp cpu root 400M clk */ + __IOM uint32_t SYS_CLK_EN : 1; /*!< clock gate enable for hp sys root 480M clk */ + uint32_t : 30; + } bit; + } HP_ROOT_CLK_CTRL; + __IM uint32_t RESERVED5; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t PMU_RDN_ECO_LOW : 32; /*!< need_des */ + } bit; + } LP_PMU_RDN_ECO_LOW; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t PMU_RDN_ECO_HIGH : 32; /*!< need_des */ + } bit; + } LP_PMU_RDN_ECO_HIGH; + __IM uint32_t RESERVED6[2]; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t DREF_COMP0 : 3; /*!< pad comp dref */ + __IOM uint32_t MODE_COMP0 : 1; /*!< pad comp mode */ + __IOM uint32_t XPD_COMP0 : 1; /*!< pad comp xpd */ + uint32_t : 27; + } bit; + } PAD_COMP0; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t DREF_COMP1 : 3; /*!< pad comp dref */ + __IOM uint32_t MODE_COMP1 : 1; /*!< pad comp mode */ + __IOM uint32_t XPD_COMP1 : 1; /*!< pad comp xpd */ + uint32_t : 27; + } bit; + } PAD_COMP1; + __IM uint32_t RESERVED7; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t BURST_LIMIT_AON : 5; /*!< need_des */ + __IOM uint32_t READ_INTERVAL_AON : 7; /*!< need_des */ + __IOM uint32_t LINK_BACKUP_TOUT_THRES_AON : 10;/*!< need_des */ + __IOM uint32_t LINK_TOUT_THRES_AON : 10; /*!< need_des */ + } bit; + } BACKUP_DMA_CFG0; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 31; + __IOM uint32_t AON_BYPASS : 1; /*!< need_des */ + } bit; + } BACKUP_DMA_CFG1; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t LINK_ADDR_AON : 32; /*!< need_des */ + } bit; + } BACKUP_DMA_CFG2; + __IM uint32_t RESERVED8; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t BOOT_ADDR_HP_CORE1 : 32; /*!< need_des */ + } bit; + } BOOT_ADDR_HP_CORE1; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IM uint32_t LP_ADDRHOLE_ADDR : 32; /*!< need_des */ + } bit; + } LP_ADDRHOLE_ADDR; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IM uint32_t LP_ADDRHOLE_ID : 5; /*!< master id: 5'h0: hp core0, 5'h1:hp core1, 5'h2:lp core, 5'h3:usb + otg11, 5'h4: regdma, 5'h5: gmac, 5'h5 sdmmc, 5'h7: usbotg20, + 5'h8: trace0, 5'h9: trace1, 5'ha tcm monitor, 5'hb: l2mem + monitor. 5'h10~5'h1f: ahb pdma. */ + __IM uint32_t LP_ADDRHOLE_WR : 1; /*!< 1:write trans, 0: read trans. */ + __IM uint32_t LP_ADDRHOLE_SECURE : 1; /*!< 1: illegal address access, 0: access without permission */ + uint32_t : 25; + } bit; + } LP_ADDRHOLE_INFO; + + union { + __IOM uint32_t reg; /*!< raw interrupt register */ + + struct { + __IM uint32_t LP_ADDRHOLE_INT_RAW : 1; /*!< the raw interrupt status of lp addrhole(for lp peri and lp ram + tee apm, and lp matrix default slave) */ + __IM uint32_t IDBUS_ADDRHOLE_INT_RAW : 1;/*!< the raw interrupt status of idbus addrhole(only for lp cpu ibus + and dbus) */ + __IM uint32_t LP_CORE_AHB_TIMEOUT_INT_RAW : 1;/*!< the raw interrupt status of lp core ahb bus timeout */ + __IM uint32_t LP_CORE_IBUS_TIMEOUT_INT_RAW : 1;/*!< the raw interrupt status of lp core ibus timeout */ + __IM uint32_t LP_CORE_DBUS_TIMEOUT_INT_RAW : 1;/*!< the raw interrupt status of lp core dbus timeout */ + __IM uint32_t ETM_TASK_ULP_INT_RAW : 1; /*!< the raw interrupt status of etm task ulp */ + __IM uint32_t SLOW_CLK_TICK_INT_RAW : 1; /*!< the raw interrupt status of slow_clk_tick */ + uint32_t : 25; + } bit; + } INT_RAW; + + union { + __IOM uint32_t reg; /*!< masked interrupt register */ + + struct { + __IM uint32_t LP_ADDRHOLE_INT_ST : 1; /*!< the masked interrupt status of lp addrhole (for lp peri and + lp ram tee apm, and lp matrix default slave) */ + __IM uint32_t IDBUS_ADDRHOLE_INT_ST : 1; /*!< the masked interrupt status of idbus addrhole(only for lp cpu + ibus and dbus) */ + __IM uint32_t LP_CORE_AHB_TIMEOUT_INT_ST : 1;/*!< the masked interrupt status of lp core ahb bus timeout */ + __IM uint32_t LP_CORE_IBUS_TIMEOUT_INT_ST : 1;/*!< the masked interrupt status of lp core ibus timeout */ + __IM uint32_t LP_CORE_DBUS_TIMEOUT_INT_ST : 1;/*!< the masked interrupt status of lp core dbus timeout */ + __IM uint32_t ETM_TASK_ULP_INT_ST : 1; /*!< the masked interrupt status of etm task ulp */ + __IM uint32_t SLOW_CLK_TICK_INT_ST : 1; /*!< the masked interrupt status of slow_clk_tick */ + uint32_t : 25; + } bit; + } INT_ST; + + union { + __IOM uint32_t reg; /*!< masked interrupt register */ + + struct { + __IOM uint32_t LP_ADDRHOLE_INT_ENA : 1; /*!< Write 1 to enable lp addrhole int */ + __IOM uint32_t IDBUS_ADDRHOLE_INT_ENA : 1;/*!< Write 1 to enable idbus addrhole int */ + __IOM uint32_t LP_CORE_AHB_TIMEOUT_INT_ENA : 1;/*!< Write 1 to enable lp_core_ahb_timeout int */ + __IOM uint32_t LP_CORE_IBUS_TIMEOUT_INT_ENA : 1;/*!< Write 1 to enable lp_core_ibus_timeout int */ + __IOM uint32_t LP_CORE_DBUS_TIMEOUT_INT_ENA : 1;/*!< Write 1 to enable lp_core_dbus_timeout int */ + __IOM uint32_t ETM_TASK_ULP_INT_ENA : 1; /*!< Write 1 to enable etm task ulp int */ + __IOM uint32_t SLOW_CLK_TICK_INT_ENA : 1; /*!< Write 1 to enable slow_clk_tick int */ + uint32_t : 25; + } bit; + } INT_ENA; + + union { + __IOM uint32_t reg; /*!< interrupt clear register */ + + struct { + __OM uint32_t LP_ADDRHOLE_INT_CLR : 1; /*!< write 1 to clear lp addrhole int */ + __OM uint32_t IDBUS_ADDRHOLE_INT_CLR : 1;/*!< write 1 to clear idbus addrhole int */ + __OM uint32_t LP_CORE_AHB_TIMEOUT_INT_CLR : 1;/*!< Write 1 to clear lp_core_ahb_timeout int */ + __OM uint32_t LP_CORE_IBUS_TIMEOUT_INT_CLR : 1;/*!< Write 1 to clear lp_core_ibus_timeout int */ + __OM uint32_t LP_CORE_DBUS_TIMEOUT_INT_CLR : 1;/*!< Write 1 to clear lp_core_dbus_timeout int */ + __OM uint32_t ETM_TASK_ULP_INT_CLR : 1; /*!< Write 1 to clear etm tasl ulp int */ + __OM uint32_t SLOW_CLK_TICK_INT_CLR : 1; /*!< Write 1 to clear slow_clk_tick int */ + uint32_t : 25; + } bit; + } INT_CLR; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t HP_MEM_AUX_CTRL : 32; /*!< need_des */ + } bit; + } HP_MEM_AUX_CTRL; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t LP_MEM_AUX_CTRL : 32; /*!< need_des */ + } bit; + } LP_MEM_AUX_CTRL; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t HP_ROM_AUX_CTRL : 32; /*!< need_des */ + } bit; + } HP_ROM_AUX_CTRL; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t LP_ROM_AUX_CTRL : 32; /*!< need_des */ + } bit; + } LP_ROM_AUX_CTRL; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IM uint32_t LP_CPU_DBG_PC : 32; /*!< need_des */ + } bit; + } LP_CPU_DBG_PC; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IM uint32_t LP_CPU_EXC_PC : 32; /*!< need_des */ + } bit; + } LP_CPU_EXC_PC; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IM uint32_t IDBUS_ADDRHOLE_ADDR : 32; /*!< need_des */ + } bit; + } IDBUS_ADDRHOLE_ADDR; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IM uint32_t IDBUS_ADDRHOLE_ID : 5; /*!< need_des */ + __IM uint32_t IDBUS_ADDRHOLE_WR : 1; /*!< need_des */ + __IM uint32_t IDBUS_ADDRHOLE_SECURE : 1; /*!< need_des */ + uint32_t : 25; + } bit; + } IDBUS_ADDRHOLE_INFO; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 8; + __IOM uint32_t HP_PO_CNNT_RSTN_BYPASS_CTRL : 8;/*!< [15] 1'b1: po_cnnt_rstn bypass sys_sw_rstn[14] 1'b1: po_cnnt_rstn + bypass hp_wdt_sys_rstn[13] 1'b1: po_cnnt_rstn bypass hp_cpu_intrusion_rst + [12] 1'b1: po_cnnt_rstn bypass hp_sdio_sys_rstn[11] 1'b1: + po_cnnt_rstn bypass usb_jtag_chip_rst[10] 1'b1: po_cnnt_rstn + bypass usb_uart_chip_rst[9] 1'b1: po_cnnt_rstn bypass lp_wdt_hp_sys_rstn[ + ] 1'b1: po_cnnt_rstn bypass efuse_err_rstn */ + uint32_t : 8; + __IOM uint32_t HP_PO_RSTN_BYPASS_CTRL : 8;/*!< [31] 1'b1: po_rstn bypass sys_sw_rstn[30] 1'b1: po_rstn bypass + hp_wdt_sys_rstn[29] 1'b1: po_rstn bypass hp_cpu_intrusion_rstn[28] + 1'b1: po_rstn bypass hp_sdio_sys_rstn[27] 1'b1: po_rstn + bypass usb_jtag_chip_rst[26] 1'b1: po_rstn bypass usb_uart_chip_rst[25] + 1'b1: po_rstn bypass lp_wdt_hp_sys_rstn[24] 1'b1: po_rstn + bypass efuse_err_rstn */ + } bit; + } HP_POR_RST_BYPASS_CTRL; + + union { + __IOM uint32_t reg; /*!< rng data register */ + + struct { + __IM uint32_t RND_DATA : 32; /*!< result of rng output */ + } bit; + } RNG_DATA; + __IM uint32_t RESERVED9[2]; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t EN : 1; /*!< set this field to 1 to enable lp core ahb timeout handle */ + __IOM uint32_t THRES : 16; /*!< This field used to set lp core ahb bus timeout threshold */ + __IOM uint32_t LP2HP_AHB_TIMEOUT_EN : 1; /*!< set this field to 1 to enable lp2hp ahb timeout handle */ + __IOM uint32_t LP2HP_AHB_TIMEOUT_THRES : 5;/*!< This field used to set lp2hp ahb bus timeout threshold */ + uint32_t : 9; + } bit; + } LP_CORE_AHB_TIMEOUT; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t EN : 1; /*!< set this field to 1 to enable lp core ibus timeout handle */ + __IOM uint32_t THRES : 16; /*!< This field used to set lp core ibus timeout threshold */ + uint32_t : 15; + } bit; + } LP_CORE_IBUS_TIMEOUT; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t EN : 1; /*!< set this field to 1 to enable lp core dbus timeout handle */ + __IOM uint32_t THRES : 16; /*!< This field used to set lp core dbus timeout threshold */ + uint32_t : 15; + } bit; + } LP_CORE_DBUS_TIMEOUT; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t LP_CORE_ERR_RESP_DIS : 3; /*!< Set bit0 to disable ibus err resp;Set bit1 to disable dbus err + resp; Set bit 2 to disable ahb err resp. */ + uint32_t : 29; + } bit; + } LP_CORE_ERR_RESP_DIS; + + union { + __IOM uint32_t reg; /*!< rng cfg register */ + + struct { + __IOM uint32_t RNG_TIMER_EN : 1; /*!< enable rng timer */ + __IOM uint32_t RNG_TIMER_PSCALE : 8; /*!< configure ng timer pscale */ + __IOM uint32_t RNG_SAR_ENABLE : 1; /*!< enable rng_saradc */ + uint32_t : 6; + __IM uint32_t RNG_SAR_DATA : 13; /*!< debug rng sar sample cnt */ + uint32_t : 3; + } bit; + } RNG_CFG; +} LP_SYS_Type; /*!< Size = 452 (0x1c4) */ + + + +/* =========================================================================================================================== */ +/* ================ LP_ANA_PERI ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief LP_ANA_PERI Peripheral (LP_ANA_PERI) + */ + +typedef struct { /*!< LP_ANA_PERI Structure */ + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 6; + __IOM uint32_t LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA : 1;/*!< need_des */ + __IOM uint32_t LP_ANA_BOD_MODE0_PD_RF_ENA : 1;/*!< need_des */ + __IOM uint32_t LP_ANA_BOD_MODE0_INTR_WAIT : 10;/*!< need_des */ + __IOM uint32_t LP_ANA_BOD_MODE0_RESET_WAIT : 10;/*!< need_des */ + __IOM uint32_t LP_ANA_BOD_MODE0_CNT_CLR : 1;/*!< need_des */ + __IOM uint32_t LP_ANA_BOD_MODE0_INTR_ENA : 1;/*!< need_des */ + __IOM uint32_t LP_ANA_BOD_MODE0_RESET_SEL : 1;/*!< need_des */ + __IOM uint32_t LP_ANA_BOD_MODE0_RESET_ENA : 1;/*!< need_des */ + } bit; + } LP_ANA_BOD_MODE0_CNTL; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 31; + __IOM uint32_t LP_ANA_BOD_MODE1_RESET_ENA : 1;/*!< need_des */ + } bit; + } LP_ANA_BOD_MODE1_CNTL; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t LP_ANA_DETMODE_SEL : 8; /*!< need_des */ + __IM uint32_t LP_ANA_VGOOD_EVENT_RECORD : 8;/*!< need_des */ + __OM uint32_t LP_ANA_VBAT_EVENT_RECORD_CLR : 8;/*!< need_des */ + __IOM uint32_t LP_ANA_BOD_SOURCE_ENA : 8; /*!< need_des */ + } bit; + } LP_ANA_VDD_SOURCE_CNTL; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IM uint32_t LP_ANA_VDDBAT_UNDERVOLTAGE_FLAG : 1;/*!< need_des */ + uint32_t : 9; + __IOM uint32_t LP_ANA_VDDBAT_CHARGER : 1; /*!< need_des */ + __IOM uint32_t LP_ANA_VDDBAT_CNT_CLR : 1; /*!< need_des */ + __IOM uint32_t LP_ANA_VDDBAT_UPVOLTAGE_TARGET : 10;/*!< need_des */ + __IOM uint32_t LP_ANA_VDDBAT_UNDERVOLTAGE_TARGET : 10;/*!< need_des */ + } bit; + } LP_ANA_VDDBAT_BOD_CNTL; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IM uint32_t LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG : 1;/*!< need_des */ + uint32_t : 9; + __IOM uint32_t LP_ANA_VDDBAT_CHARGE_CHARGER : 1;/*!< need_des */ + __IOM uint32_t LP_ANA_VDDBAT_CHARGE_CNT_CLR : 1;/*!< need_des */ + __IOM uint32_t LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_TARGET : 10;/*!< need_des */ + __IOM uint32_t LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET : 10;/*!< need_des */ + } bit; + } LP_ANA_VDDBAT_CHARGE_CNTL; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 31; + __IOM uint32_t LP_ANA_CK_GLITCH_RESET_ENA : 1;/*!< need_des */ + } bit; + } LP_ANA_CK_GLITCH_CNTL; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 31; + __IOM uint32_t LP_ANA_POWER_GLITCH_RESET_ENA : 1;/*!< need_des */ + } bit; + } LP_ANA_PG_GLITCH_CNTL; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t LP_ANA_ANA_FIB_ENA : 32; /*!< need_des */ + } bit; + } LP_ANA_FIB_ENABLE; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 27; + __IOM uint32_t LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW : 1;/*!< need_des */ + __IOM uint32_t LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW : 1;/*!< need_des */ + __IOM uint32_t LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW : 1;/*!< need_des */ + __IOM uint32_t LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW : 1;/*!< need_des */ + __IOM uint32_t LP_ANA_BOD_MODE0_INT_RAW : 1;/*!< need_des */ + } bit; + } LP_ANA_INT_RAW; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 27; + __IM uint32_t LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ST : 1;/*!< need_des */ + __IM uint32_t LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST : 1;/*!< need_des */ + __IM uint32_t LP_ANA_VDDBAT_UPVOLTAGE_INT_ST : 1;/*!< need_des */ + __IM uint32_t LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ST : 1;/*!< need_des */ + __IM uint32_t LP_ANA_BOD_MODE0_INT_ST : 1;/*!< need_des */ + } bit; + } LP_ANA_INT_ST; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 27; + __IOM uint32_t LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA : 1;/*!< need_des */ + __IOM uint32_t LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA : 1;/*!< need_des */ + __IOM uint32_t LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA : 1;/*!< need_des */ + __IOM uint32_t LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA : 1;/*!< need_des */ + __IOM uint32_t LP_ANA_BOD_MODE0_INT_ENA : 1;/*!< need_des */ + } bit; + } LP_ANA_INT_ENA; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 27; + __OM uint32_t LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR : 1;/*!< need_des */ + __OM uint32_t LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR : 1;/*!< need_des */ + __OM uint32_t LP_ANA_VDDBAT_UPVOLTAGE_INT_CLR : 1;/*!< need_des */ + __OM uint32_t LP_ANA_VDDBAT_UNDERVOLTAGE_INT_CLR : 1;/*!< need_des */ + __OM uint32_t LP_ANA_BOD_MODE0_INT_CLR : 1;/*!< need_des */ + } bit; + } LP_ANA_INT_CLR; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 31; + __IOM uint32_t LP_ANA_BOD_MODE0_LP_INT_RAW : 1;/*!< need_des */ + } bit; + } LP_ANA_LP_INT_RAW; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 31; + __IM uint32_t LP_ANA_BOD_MODE0_LP_INT_ST : 1;/*!< need_des */ + } bit; + } LP_ANA_LP_INT_ST; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 31; + __IOM uint32_t LP_ANA_BOD_MODE0_LP_INT_ENA : 1;/*!< need_des */ + } bit; + } LP_ANA_LP_INT_ENA; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 31; + __OM uint32_t LP_ANA_BOD_MODE0_LP_INT_CLR : 1;/*!< need_des */ + } bit; + } LP_ANA_LP_INT_CLR; + __IM uint32_t RESERVED[47]; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t LP_ANA_TOUCH_APPROACH_MEAS_NUM2 : 10;/*!< need_des */ + __IOM uint32_t LP_ANA_TOUCH_APPROACH_MEAS_NUM1 : 10;/*!< need_des */ + __IOM uint32_t LP_ANA_TOUCH_APPROACH_MEAS_NUM0 : 10;/*!< need_des */ + uint32_t : 2; + } bit; + } LP_ANA_TOUCH_APPROACH_WORK_MEAS_NUM; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t LP_ANA_TOUCH_SHIELD_PAD_EN : 1;/*!< need_des */ + __IOM uint32_t LP_ANA_TOUCH_INACTIVE_CONNECTION : 1;/*!< need_des */ + __IOM uint32_t LP_ANA_TOUCH_SCAN_PAD_MAP : 15;/*!< need_des */ + __IOM uint32_t LP_ANA_TOUCH_XPD_WAIT : 15;/*!< need_des */ + } bit; + } LP_ANA_TOUCH_SCAN_CTRL1; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 6; + __IOM uint32_t LP_ANA_TOUCH_TIMEOUT_NUM : 16;/*!< need_des */ + __IOM uint32_t LP_ANA_TOUCH_TIMEOUT_EN : 1;/*!< need_des */ + __IOM uint32_t LP_ANA_TOUCH_OUT_RING : 4; /*!< need_des */ + __IOM uint32_t LP_ANA_FREQ_SCAN_EN : 1; /*!< need_des */ + __IOM uint32_t LP_ANA_FREQ_SCAN_CNT_LIMIT : 2;/*!< need_des */ + uint32_t : 2; + } bit; + } LP_ANA_TOUCH_SCAN_CTRL2; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 16; + __IOM uint32_t LP_ANA_DIV_NUM2 : 3; /*!< need_des */ + __IOM uint32_t LP_ANA_DIV_NUM1 : 3; /*!< need_des */ + __IOM uint32_t LP_ANA_DIV_NUM0 : 3; /*!< need_des */ + __IOM uint32_t LP_ANA_TOUCH_OUT_SEL : 1; /*!< need_des */ + __OM uint32_t LP_ANA_TOUCH_OUT_RESET : 1;/*!< need_des */ + __IOM uint32_t LP_ANA_TOUCH_OUT_GATE : 1; /*!< need_des */ + uint32_t : 4; + } bit; + } LP_ANA_TOUCH_WORK; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t LP_ANA_TOUCH_MEAS_NUM2 : 10;/*!< need_des */ + __IOM uint32_t LP_ANA_TOUCH_MEAS_NUM1 : 10;/*!< need_des */ + __IOM uint32_t LP_ANA_TOUCH_MEAS_NUM0 : 10;/*!< need_des */ + uint32_t : 2; + } bit; + } LP_ANA_TOUCH_WORK_MEAS_NUM; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t LP_ANA_TOUCH_NEG_NOISE_DISUPDATE_BASELINE_EN : 1;/*!< Reserved */ + __IOM uint32_t LP_ANA_TOUCH_HYSTERESIS : 2;/*!< need_des */ + __IOM uint32_t LP_ANA_TOUCH_NEG_NOISE_THRES : 2;/*!< need_des */ + __IOM uint32_t LP_ANA_TOUCH_NOISE_THRES : 2;/*!< need_des */ + __IOM uint32_t LP_ANA_TOUCH_SMOOTH_LVL : 2;/*!< need_des */ + __IOM uint32_t LP_ANA_TOUCH_JITTER_STEP : 4;/*!< need_des */ + __IOM uint32_t LP_ANA_TOUCH_FILTER_MODE : 3;/*!< need_des */ + __IOM uint32_t LP_ANA_TOUCH_FILTER_EN : 1;/*!< need_des */ + __IOM uint32_t LP_ANA_TOUCH_NEG_NOISE_LIMIT : 4;/*!< need_des */ + __IOM uint32_t LP_ANA_TOUCH_APPROACH_LIMIT : 8;/*!< need_des */ + __IOM uint32_t LP_ANA_TOUCH_DEBOUNCE_LIMIT : 3;/*!< need_des */ + } bit; + } LP_ANA_TOUCH_FILTER1; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 15; + __IOM uint32_t LP_ANA_TOUCH_OUTEN : 15; /*!< need_des */ + __IOM uint32_t LP_ANA_TOUCH_BYPASS_NOISE_THRES : 1;/*!< need_des */ + __IOM uint32_t LP_ANA_TOUCH_BYPASS_NEG_NOISE_THRES : 1;/*!< need_des */ + } bit; + } LP_ANA_TOUCH_FILTER2; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t LP_ANA_TOUCH_BASELINE_SW : 16;/*!< need_des */ + __OM uint32_t LP_ANA_TOUCH_UPDATE_BASELINE_SW : 1;/*!< need_des */ + uint32_t : 15; + } bit; + } LP_ANA_TOUCH_FILTER3; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t LP_ANA_TOUCH_SLP_TH0 : 16; /*!< need_des */ + __OM uint32_t LP_ANA_TOUCH_SLP_CHANNEL_CLR : 1;/*!< need_des */ + __IOM uint32_t LP_ANA_TOUCH_SLP_PAD : 4; /*!< need_des */ + uint32_t : 11; + } bit; + } LP_ANA_TOUCH_SLP0; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t LP_ANA_TOUCH_SLP_TH2 : 16; /*!< need_des */ + __IOM uint32_t LP_ANA_TOUCH_SLP_TH1 : 16; /*!< need_des */ + } bit; + } LP_ANA_TOUCH_SLP1; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __OM uint32_t LP_ANA_TOUCH_CHANNEL_CLR : 15;/*!< need_des */ + __OM uint32_t LP_ANA_TOUCH_STATUS_CLR : 1;/*!< need_des */ + uint32_t : 16; + } bit; + } LP_ANA_TOUCH_CLR; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t PAD0 : 4; /*!< need_des */ + __IOM uint32_t PAD1 : 4; /*!< need_des */ + __IOM uint32_t PAD2 : 4; /*!< need_des */ + __IOM uint32_t LP_ANA_TOUCH_SLP_APPROACH_EN : 1;/*!< need_des */ + uint32_t : 19; + } bit; + } LP_ANA_TOUCH_APPROACH; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t LP_ANA_TOUCH_FREQ0_DCAP_LPF : 7;/*!< need_des */ + __IOM uint32_t LP_ANA_TOUCH_FREQ0_DRES_LPF : 2;/*!< need_des */ + __IOM uint32_t LP_ANA_TOUCH_FREQ0_DRV_LS : 4;/*!< need_des */ + __IOM uint32_t LP_ANA_TOUCH_FREQ0_DRV_HS : 5;/*!< need_des */ + __IOM uint32_t LP_ANA_TOUCH_FREQ0_DBIAS : 5;/*!< need_des */ + uint32_t : 9; + } bit; + } LP_ANA_TOUCH_FREQ0_SCAN_PARA; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t LP_ANA_TOUCH_FREQ1_DCAP_LPF : 7;/*!< need_des */ + __IOM uint32_t LP_ANA_TOUCH_FREQ1_DRES_LPF : 2;/*!< need_des */ + __IOM uint32_t LP_ANA_TOUCH_FREQ1_DRV_LS : 4;/*!< need_des */ + __IOM uint32_t LP_ANA_TOUCH_FREQ1_DRV_HS : 5;/*!< need_des */ + __IOM uint32_t LP_ANA_TOUCH_FREQ1_DBIAS : 5;/*!< need_des */ + uint32_t : 9; + } bit; + } LP_ANA_TOUCH_FREQ1_SCAN_PARA; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t LP_ANA_TOUCH_FREQ2_DCAP_LPF : 7;/*!< need_des */ + __IOM uint32_t LP_ANA_TOUCH_FREQ2_DRES_LPF : 2;/*!< need_des */ + __IOM uint32_t LP_ANA_TOUCH_FREQ2_DRV_LS : 4;/*!< need_des */ + __IOM uint32_t LP_ANA_TOUCH_FREQ2_DRV_HS : 5;/*!< need_des */ + __IOM uint32_t LP_ANA_TOUCH_FREQ2_DBIAS : 5;/*!< need_des */ + uint32_t : 9; + } bit; + } LP_ANA_TOUCH_FREQ2_SCAN_PARA; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t LP_ANA_TOUCH_TOUCH_BUF_DRV : 3;/*!< need_des */ + __IOM uint32_t LP_ANA_TOUCH_TOUCH_EN_CAL : 1;/*!< need_des */ + __IOM uint32_t LP_ANA_TOUCH_TOUCH_DCAP_CAL : 7;/*!< need_des */ + uint32_t : 21; + } bit; + } LP_ANA_TOUCH_ANA_PARA; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 8; + __IOM uint32_t LP_ANA_TOUCH_DATA_SEL : 2; /*!< need_des */ + __IOM uint32_t LP_ANA_TOUCH_FREQ_SEL : 2; /*!< need_des */ + __IOM uint32_t LP_ANA_TOUCH_BUFSEL : 15; /*!< need_des */ + __IOM uint32_t LP_ANA_TOUCH_DONE_EN : 1; /*!< need_des */ + __IOM uint32_t LP_ANA_TOUCH_DONE_FORCE : 1;/*!< need_des */ + __IOM uint32_t LP_ANA_TOUCH_FSM_EN : 1; /*!< need_des */ + __IOM uint32_t LP_ANA_TOUCH_START_EN : 1; /*!< need_des */ + __IOM uint32_t LP_ANA_TOUCH_START_FORCE : 1;/*!< need_des */ + } bit; + } LP_ANA_TOUCH_MUX0; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t LP_ANA_TOUCH_START : 15; /*!< need_des */ + __IOM uint32_t LP_ANA_TOUCH_XPD : 15; /*!< need_des */ + uint32_t : 2; + } bit; + } LP_ANA_TOUCH_MUX1; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 16; + __IOM uint32_t LP_ANA_TOUCH_PAD0_TH0 : 16;/*!< Reserved */ + } bit; + } LP_ANA_TOUCH_PAD0_TH0; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 16; + __IOM uint32_t LP_ANA_TOUCH_PAD0_TH1 : 16;/*!< Reserved */ + } bit; + } LP_ANA_TOUCH_PAD0_TH1; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 16; + __IOM uint32_t LP_ANA_TOUCH_PAD0_TH2 : 16;/*!< Reserved */ + } bit; + } LP_ANA_TOUCH_PAD0_TH2; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 16; + __IOM uint32_t LP_ANA_TOUCH_PAD1_TH0 : 16;/*!< Reserved */ + } bit; + } LP_ANA_TOUCH_PAD1_TH0; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 16; + __IOM uint32_t LP_ANA_TOUCH_PAD1_TH1 : 16;/*!< Reserved */ + } bit; + } LP_ANA_TOUCH_PAD1_TH1; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 16; + __IOM uint32_t LP_ANA_TOUCH_PAD1_TH2 : 16;/*!< Reserved */ + } bit; + } LP_ANA_TOUCH_PAD1_TH2; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 16; + __IOM uint32_t LP_ANA_TOUCH_PAD2_TH0 : 16;/*!< Reserved */ + } bit; + } LP_ANA_TOUCH_PAD2_TH0; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 16; + __IOM uint32_t LP_ANA_TOUCH_PAD2_TH1 : 16;/*!< Reserved */ + } bit; + } LP_ANA_TOUCH_PAD2_TH1; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 16; + __IOM uint32_t LP_ANA_TOUCH_PAD2_TH2 : 16;/*!< Reserved */ + } bit; + } LP_ANA_TOUCH_PAD2_TH2; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 16; + __IOM uint32_t LP_ANA_TOUCH_PAD3_TH0 : 16;/*!< Reserved */ + } bit; + } LP_ANA_TOUCH_PAD3_TH0; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 16; + __IOM uint32_t LP_ANA_TOUCH_PAD3_TH1 : 16;/*!< Reserved */ + } bit; + } LP_ANA_TOUCH_PAD3_TH1; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 16; + __IOM uint32_t LP_ANA_TOUCH_PAD3_TH2 : 16;/*!< Reserved */ + } bit; + } LP_ANA_TOUCH_PAD3_TH2; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 16; + __IOM uint32_t LP_ANA_TOUCH_PAD4_TH0 : 16;/*!< Reserved */ + } bit; + } LP_ANA_TOUCH_PAD4_TH0; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 16; + __IOM uint32_t LP_ANA_TOUCH_PAD4_TH1 : 16;/*!< Reserved */ + } bit; + } LP_ANA_TOUCH_PAD4_TH1; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 16; + __IOM uint32_t LP_ANA_TOUCH_PAD4_TH2 : 16;/*!< Reserved */ + } bit; + } LP_ANA_TOUCH_PAD4_TH2; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 16; + __IOM uint32_t LP_ANA_TOUCH_PAD5_TH0 : 16;/*!< Reserved */ + } bit; + } LP_ANA_TOUCH_PAD5_TH0; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 16; + __IOM uint32_t LP_ANA_TOUCH_PAD5_TH1 : 16;/*!< Reserved */ + } bit; + } LP_ANA_TOUCH_PAD5_TH1; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 16; + __IOM uint32_t LP_ANA_TOUCH_PAD5_TH2 : 16;/*!< Reserved */ + } bit; + } LP_ANA_TOUCH_PAD5_TH2; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 16; + __IOM uint32_t LP_ANA_TOUCH_PAD6_TH0 : 16;/*!< Reserved */ + } bit; + } LP_ANA_TOUCH_PAD6_TH0; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 16; + __IOM uint32_t LP_ANA_TOUCH_PAD6_TH1 : 16;/*!< Reserved */ + } bit; + } LP_ANA_TOUCH_PAD6_TH1; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 16; + __IOM uint32_t LP_ANA_TOUCH_PAD6_TH2 : 16;/*!< Reserved */ + } bit; + } LP_ANA_TOUCH_PAD6_TH2; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 16; + __IOM uint32_t LP_ANA_TOUCH_PAD7_TH0 : 16;/*!< Reserved */ + } bit; + } LP_ANA_TOUCH_PAD7_TH0; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 16; + __IOM uint32_t LP_ANA_TOUCH_PAD7_TH1 : 16;/*!< Reserved */ + } bit; + } LP_ANA_TOUCH_PAD7_TH1; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 16; + __IOM uint32_t LP_ANA_TOUCH_PAD7_TH2 : 16;/*!< Reserved */ + } bit; + } LP_ANA_TOUCH_PAD7_TH2; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 16; + __IOM uint32_t LP_ANA_TOUCH_PAD8_TH0 : 16;/*!< Reserved */ + } bit; + } LP_ANA_TOUCH_PAD8_TH0; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 16; + __IOM uint32_t LP_ANA_TOUCH_PAD8_TH1 : 16;/*!< Reserved */ + } bit; + } LP_ANA_TOUCH_PAD8_TH1; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 16; + __IOM uint32_t LP_ANA_TOUCH_PAD8_TH2 : 16;/*!< Reserved */ + } bit; + } LP_ANA_TOUCH_PAD8_TH2; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 16; + __IOM uint32_t LP_ANA_TOUCH_PAD9_TH0 : 16;/*!< Reserved */ + } bit; + } LP_ANA_TOUCH_PAD9_TH0; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 16; + __IOM uint32_t LP_ANA_TOUCH_PAD9_TH1 : 16;/*!< Reserved */ + } bit; + } LP_ANA_TOUCH_PAD9_TH1; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 16; + __IOM uint32_t LP_ANA_TOUCH_PAD9_TH2 : 16;/*!< Reserved */ + } bit; + } LP_ANA_TOUCH_PAD9_TH2; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 16; + __IOM uint32_t LP_ANA_TOUCH_PAD10_TH0 : 16;/*!< Reserved */ + } bit; + } LP_ANA_TOUCH_PAD10_TH0; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 16; + __IOM uint32_t LP_ANA_TOUCH_PAD10_TH1 : 16;/*!< Reserved */ + } bit; + } LP_ANA_TOUCH_PAD10_TH1; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 16; + __IOM uint32_t LP_ANA_TOUCH_PAD10_TH2 : 16;/*!< Reserved */ + } bit; + } LP_ANA_TOUCH_PAD10_TH2; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 16; + __IOM uint32_t LP_ANA_TOUCH_PAD11_TH0 : 16;/*!< Reserved */ + } bit; + } LP_ANA_TOUCH_PAD11_TH0; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 16; + __IOM uint32_t LP_ANA_TOUCH_PAD11_TH1 : 16;/*!< Reserved */ + } bit; + } LP_ANA_TOUCH_PAD11_TH1; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 16; + __IOM uint32_t LP_ANA_TOUCH_PAD11_TH2 : 16;/*!< Reserved */ + } bit; + } LP_ANA_TOUCH_PAD11_TH2; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 16; + __IOM uint32_t LP_ANA_TOUCH_PAD12_TH0 : 16;/*!< Reserved */ + } bit; + } LP_ANA_TOUCH_PAD12_TH0; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 16; + __IOM uint32_t LP_ANA_TOUCH_PAD12_TH1 : 16;/*!< Reserved */ + } bit; + } LP_ANA_TOUCH_PAD12_TH1; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 16; + __IOM uint32_t LP_ANA_TOUCH_PAD12_TH2 : 16;/*!< Reserved */ + } bit; + } LP_ANA_TOUCH_PAD12_TH2; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 16; + __IOM uint32_t LP_ANA_TOUCH_PAD13_TH0 : 16;/*!< Reserved */ + } bit; + } LP_ANA_TOUCH_PAD13_TH0; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 16; + __IOM uint32_t LP_ANA_TOUCH_PAD13_TH1 : 16;/*!< Reserved */ + } bit; + } LP_ANA_TOUCH_PAD13_TH1; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 16; + __IOM uint32_t LP_ANA_TOUCH_PAD13_TH2 : 16;/*!< Reserved */ + } bit; + } LP_ANA_TOUCH_PAD13_TH2; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 16; + __IOM uint32_t LP_ANA_TOUCH_PAD14_TH0 : 16;/*!< Reserved */ + } bit; + } LP_ANA_TOUCH_PAD14_TH0; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 16; + __IOM uint32_t LP_ANA_TOUCH_PAD14_TH1 : 16;/*!< Reserved */ + } bit; + } LP_ANA_TOUCH_PAD14_TH1; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 16; + __IOM uint32_t LP_ANA_TOUCH_PAD14_TH2 : 16;/*!< Reserved */ + } bit; + } LP_ANA_TOUCH_PAD14_TH2; + __IM uint32_t RESERVED1[129]; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t LP_ANA_LP_ANA_DATE : 31; /*!< need_des */ + __IOM uint32_t LP_ANA_CLK_EN : 1; /*!< need_des */ + } bit; + } LP_ANA_DATE; +} LP_ANA_PERI_Type; /*!< Size = 1024 (0x400) */ + + + +/* =========================================================================================================================== */ +/* ================ LP_AON_CLKRST ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief LP_AON_CLKRST Peripheral (LP_AON_CLKRST) + */ + +typedef struct { /*!< LP_AON_CLKRST Structure */ + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t LP_AONCLKRST_SLOW_CLK_SEL : 2;/*!< need_des */ + __IOM uint32_t LP_AONCLKRST_FAST_CLK_SEL : 2;/*!< need_des */ + __IOM uint32_t LP_AONCLKRST_LP_PERI_DIV_NUM : 6;/*!< need_des */ + __IOM uint32_t LP_AONCLKRST_ANA_SEL_REF_PLL8M : 1;/*!< need_des */ + uint32_t : 21; + } bit; + } LP_AONCLKRST_LP_CLK_CONF; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t LP_AONCLKRST_CLK_CORE_EFUSE_OEN : 1;/*!< need_des */ + __IOM uint32_t LP_AONCLKRST_CLK_LP_BUS_OEN : 1;/*!< need_des */ + __IOM uint32_t LP_AONCLKRST_CLK_AON_SLOW_OEN : 1;/*!< need_des */ + __IOM uint32_t LP_AONCLKRST_CLK_AON_FAST_OEN : 1;/*!< need_des */ + __IOM uint32_t LP_AONCLKRST_CLK_SLOW_OEN : 1;/*!< need_des */ + __IOM uint32_t LP_AONCLKRST_CLK_FAST_OEN : 1;/*!< need_des */ + __IOM uint32_t LP_AONCLKRST_CLK_FOSC_OEN : 1;/*!< need_des */ + __IOM uint32_t LP_AONCLKRST_CLK_RC32K_OEN : 1;/*!< need_des */ + __IOM uint32_t LP_AONCLKRST_CLK_SXTAL_OEN : 1;/*!< need_des */ + __IOM uint32_t LP_AONCLKRST_CLK_SOSC_OEN : 1;/*!< 1'b1: probe sosc clk on1'b0: probe sosc clk off */ + uint32_t : 22; + } bit; + } LP_AONCLKRST_LP_CLK_PO_EN; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 26; + __IOM uint32_t LP_AONCLKRST_LP_RTC_XTAL_FORCE_ON : 1;/*!< need_des */ + __IOM uint32_t LP_AONCLKRST_CK_EN_LP_RAM : 1;/*!< need_des */ + __IOM uint32_t LP_AONCLKRST_ETM_EVENT_TICK_EN : 1;/*!< need_des */ + __IOM uint32_t LP_AONCLKRST_PLL8M_CLK_FORCE_ON : 1;/*!< need_des */ + __IOM uint32_t LP_AONCLKRST_XTAL_CLK_FORCE_ON : 1;/*!< need_des */ + __IOM uint32_t LP_AONCLKRST_FOSC_CLK_FORCE_ON : 1;/*!< need_des */ + } bit; + } LP_AONCLKRST_LP_CLK_EN; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 24; + __IOM uint32_t LP_AONCLKRST_RST_EN_LP_HUK : 1;/*!< need_des */ + __IOM uint32_t LP_AONCLKRST_RST_EN_LP_ANAPERI : 1;/*!< need_des */ + __IOM uint32_t LP_AONCLKRST_RST_EN_LP_WDT : 1;/*!< need_des */ + __IOM uint32_t LP_AONCLKRST_RST_EN_LP_TIMER : 1;/*!< need_des */ + __IOM uint32_t LP_AONCLKRST_RST_EN_LP_RTC : 1;/*!< need_des */ + __IOM uint32_t LP_AONCLKRST_RST_EN_LP_MAILBOX : 1;/*!< need_des */ + __IOM uint32_t LP_AONCLKRST_RST_EN_LP_AONEFUSEREG : 1;/*!< need_des */ + __IOM uint32_t LP_AONCLKRST_RST_EN_LP_RAM : 1;/*!< need_des */ + } bit; + } LP_AONCLKRST_LP_RST_EN; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IM uint32_t LP_AONCLKRST_LPCORE_RESET_CAUSE : 6;/*!< 6'h1: POR reset6'h9: PMU LP PERI power down reset6'ha: PMU LP + CPU reset6'hf: brown out reset6'h10: LP watchdog chip reset6'h12: + super watch dog reset6'h13: glitch reset6'h14: software + reset */ + __IM uint32_t LP_AONCLKRST_LPCORE_RESET_FLAG : 1;/*!< need_des */ + __IM uint32_t LP_AONCLKRST_HPCORE0_RESET_CAUSE : 6;/*!< 6'h1: POR reset6'h3: digital system software reset6'h5: PMU + HP system power down reset6'h7: HP system reset from HP + watchdog6'h9: HP system reset from LP watchdog6'hb: HP + core reset from HP watchdog6'hc: HP core software reset6'hd: + HP core reset from LP watchdog6'hf: brown out reset6'h10: + LP watchdog chip reset6'h12: super watch dog reset6'h13: + glitch reset6'h14: efuse crc error reset6'h16: HP usb jtag + chip reset6'h17: HP usb uart chip reset6'h18: HP jtag reset6'h1a: + HP core lockup */ + __IM uint32_t LP_AONCLKRST_HPCORE0_RESET_FLAG : 1;/*!< need_des */ + __IM uint32_t LP_AONCLKRST_HPCORE1_RESET_CAUSE : 6;/*!< 6'h1: POR reset6'h3: digital system software reset6'h5: PMU + HP system power down reset6'h7: HP system reset from HP + watchdog6'h9: HP system reset from LP watchdog6'hb: HP + core reset from HP watchdog6'hc: HP core software reset6'hd: + HP core reset from LP watchdog6'hf: brown out reset6'h10: + LP watchdog chip reset6'h12: super watch dog reset6'h13: + glitch reset6'h14: efuse crc error reset6'h16: HP usb jtag + chip reset6'h17: HP usb uart chip reset6'h18: HP jtag reset6'h1a: + HP core lockup */ + __IM uint32_t LP_AONCLKRST_HPCORE1_RESET_FLAG : 1;/*!< need_des */ + uint32_t : 4; + __IOM uint32_t LP_AONCLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK : 1;/*!< 1'b0: enable lpcore pmu_lp_cpu_reset reset_cause, 1'b1: disable + lpcore pmu_lp_cpu_reset reset_cause */ + __OM uint32_t LP_AONCLKRST_LPCORE_RESET_CAUSE_CLR : 1;/*!< need_des */ + __OM uint32_t LP_AONCLKRST_LPCORE_RESET_FLAG_CLR : 1;/*!< need_des */ + __OM uint32_t LP_AONCLKRST_HPCORE0_RESET_CAUSE_CLR : 1;/*!< need_des */ + __OM uint32_t LP_AONCLKRST_HPCORE0_RESET_FLAG_CLR : 1;/*!< need_des */ + __OM uint32_t LP_AONCLKRST_HPCORE1_RESET_CAUSE_CLR : 1;/*!< need_des */ + __OM uint32_t LP_AONCLKRST_HPCORE1_RESET_FLAG_CLR : 1;/*!< need_des */ + } bit; + } LP_AONCLKRST_RESET_CAUSE; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t LP_AONCLKRST_HPCORE0_LOCKUP_RESET_EN : 1;/*!< write 1 to enable hpcore0 lockup reset feature, write 0 to disable + hpcore0 lockup reset feature */ + __IOM uint32_t LP_AONCLKRST_LP_WDT_HPCORE0_RESET_LENGTH : 3;/*!< need_des */ + __IOM uint32_t LP_AONCLKRST_LP_WDT_HPCORE0_RESET_EN : 1;/*!< write 1 to enable lp_wdt reset hpcore0 feature, write 0 to disable + lp_wdt reset hpcore0 feature */ + __IOM uint32_t LP_AONCLKRST_HPCORE0_STALL_WAIT : 7;/*!< need_des */ + __IOM uint32_t LP_AONCLKRST_HPCORE0_STALL_EN : 1;/*!< need_des */ + __OM uint32_t LP_AONCLKRST_HPCORE0_SW_RESET : 1;/*!< need_des */ + __IOM uint32_t LP_AONCLKRST_HPCORE0_OCD_HALT_ON_RESET : 1;/*!< need_des */ + __IOM uint32_t LP_AONCLKRST_HPCORE0_STAT_VECTOR_SEL : 1;/*!< 1'b1: boot from HP TCM ROM: 0x4FC000001'b0: boot from LP TCM + RAM: 0x50108000 */ + __IOM uint32_t LP_AONCLKRST_HPCORE1_LOCKUP_RESET_EN : 1;/*!< write 1 to enable hpcore1 lockup reset feature, write 0 to disable + hpcore1 lockup reset feature */ + __IOM uint32_t LP_AONCLKRST_LP_WDT_HPCORE1_RESET_LENGTH : 3;/*!< need_des */ + __IOM uint32_t LP_AONCLKRST_LP_WDT_HPCORE1_RESET_EN : 1;/*!< write 1 to enable lp_wdt reset hpcore1 feature, write 0 to disable + lp_wdt reset hpcore1 feature */ + __IOM uint32_t LP_AONCLKRST_HPCORE1_STALL_WAIT : 7;/*!< need_des */ + __IOM uint32_t LP_AONCLKRST_HPCORE1_STALL_EN : 1;/*!< need_des */ + __OM uint32_t LP_AONCLKRST_HPCORE1_SW_RESET : 1;/*!< need_des */ + __IOM uint32_t LP_AONCLKRST_HPCORE1_OCD_HALT_ON_RESET : 1;/*!< need_des */ + __IOM uint32_t LP_AONCLKRST_HPCORE1_STAT_VECTOR_SEL : 1;/*!< 1'b1: boot from HP TCM ROM: 0x4FC000001'b0: boot from LP TCM + RAM: 0x50108000 */ + } bit; + } LP_AONCLKRST_HPCPU_RESET_CTRL0; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 16; + __IOM uint32_t LP_AONCLKRST_HPCORE0_SW_STALL_CODE : 8;/*!< HP core0 software stall when set to 8'h86 */ + __IOM uint32_t LP_AONCLKRST_HPCORE1_SW_STALL_CODE : 8;/*!< HP core1 software stall when set to 8'h86 */ + } bit; + } LP_AONCLKRST_HPCPU_RESET_CTRL1; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 22; + __IOM uint32_t LP_AONCLKRST_FOSC_DFREQ : 10;/*!< need_des */ + } bit; + } LP_AONCLKRST_FOSC_CNTL; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t LP_AONCLKRST_RC32K_DFREQ : 32;/*!< need_des */ + } bit; + } LP_AONCLKRST_RC32K_CNTL; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 22; + __IOM uint32_t LP_AONCLKRST_SOSC_DFREQ : 10;/*!< need_des */ + } bit; + } LP_AONCLKRST_SOSC_CNTL; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 28; + __IOM uint32_t LP_AONCLKRST_ICG_HP_XTAL32K : 1;/*!< reserved */ + __IOM uint32_t LP_AONCLKRST_ICG_HP_SOSC : 1;/*!< reserved */ + __IOM uint32_t LP_AONCLKRST_ICG_HP_OSC32K : 1;/*!< reserved */ + __IOM uint32_t LP_AONCLKRST_ICG_HP_FOSC : 1;/*!< reserved */ + } bit; + } LP_AONCLKRST_CLK_TO_HP; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 31; + __IOM uint32_t LP_AONCLKRST_LPMEM_CLK_FORCE_ON : 1;/*!< reserved */ + } bit; + } LP_AONCLKRST_LPMEM_FORCE; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 22; + __IOM uint32_t LP_AONCLKRST_DRES_XTAL32K : 3;/*!< need_des */ + __IOM uint32_t LP_AONCLKRST_DGM_XTAL32K : 3;/*!< need_des */ + __IOM uint32_t LP_AONCLKRST_DBUF_XTAL32K : 1;/*!< need_des */ + __IOM uint32_t LP_AONCLKRST_DAC_XTAL32K : 3;/*!< need_des */ + } bit; + } LP_AONCLKRST_XTAL32K; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS : 32;/*!< reserved */ + } bit; + } LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t LP_AONCLKRST_HPSYS_0_RESET_BYPASS : 32;/*!< reserved */ + } bit; + } LP_AONCLKRST_HPSYS_0_RESET_BYPASS; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t LP_AONCLKRST_HPSYS_APM_RESET_BYPASS : 32;/*!< reserved */ + } bit; + } LP_AONCLKRST_HPSYS_APM_RESET_BYPASS; + + union { + __IOM uint32_t reg; /*!< HP Clock Control Register. */ + + struct { + __IOM uint32_t LP_AONCLKRST_HP_ROOT_CLK_SRC_SEL : 2;/*!< HP SoC Root Clock Source Select. 2'd0: xtal_40m, 2'd1: cpll_400m, + 2'd2: fosc_20m. */ + __IOM uint32_t LP_AONCLKRST_HP_ROOT_CLK_EN : 1;/*!< HP SoC Root Clock Enable. */ + __IOM uint32_t LP_AONCLKRST_HP_PAD_PARLIO_TX_CLK_EN : 1;/*!< PARLIO TX Clock From Pad Enable. */ + __IOM uint32_t LP_AONCLKRST_HP_PAD_PARLIO_RX_CLK_EN : 1;/*!< PARLIO RX Clock From Pad Enable. */ + __IOM uint32_t LP_AONCLKRST_HP_PAD_UART4_SLP_CLK_EN : 1;/*!< UART4 SLP Clock From Pad Enable. */ + __IOM uint32_t LP_AONCLKRST_HP_PAD_UART3_SLP_CLK_EN : 1;/*!< UART3 SLP Clock From Pad Enable. */ + __IOM uint32_t LP_AONCLKRST_HP_PAD_UART2_SLP_CLK_EN : 1;/*!< UART2 SLP Clock From Pad Enable. */ + __IOM uint32_t LP_AONCLKRST_HP_PAD_UART1_SLP_CLK_EN : 1;/*!< UART1 SLP Clock From Pad Enable. */ + __IOM uint32_t LP_AONCLKRST_HP_PAD_UART0_SLP_CLK_EN : 1;/*!< UART0 SLP Clock From Pad Enable. */ + __IOM uint32_t LP_AONCLKRST_HP_PAD_I2S2_MCLK_EN : 1;/*!< I2S2 MCLK Clock From Pad Enable. */ + __IOM uint32_t LP_AONCLKRST_HP_PAD_I2S1_MCLK_EN : 1;/*!< I2S1 MCLK Clock From Pad Enable. */ + __IOM uint32_t LP_AONCLKRST_HP_PAD_I2S0_MCLK_EN : 1;/*!< I2S0 MCLK Clock From Pad Enable. */ + __IOM uint32_t LP_AONCLKRST_HP_PAD_EMAC_TX_CLK_EN : 1;/*!< EMAC RX Clock From Pad Enable. */ + __IOM uint32_t LP_AONCLKRST_HP_PAD_EMAC_RX_CLK_EN : 1;/*!< EMAC TX Clock From Pad Enable. */ + __IOM uint32_t LP_AONCLKRST_HP_PAD_EMAC_TXRX_CLK_EN : 1;/*!< EMAC TXRX Clock From Pad Enable. */ + __IOM uint32_t LP_AONCLKRST_HP_XTAL_32K_CLK_EN : 1;/*!< XTAL 32K Clock Enable. */ + __IOM uint32_t LP_AONCLKRST_HP_RC_32K_CLK_EN : 1;/*!< RC 32K Clock Enable. */ + __IOM uint32_t LP_AONCLKRST_HP_SOSC_150K_CLK_EN : 1;/*!< SOSC 150K Clock Enable. */ + __IOM uint32_t LP_AONCLKRST_HP_PLL_8M_CLK_EN : 1;/*!< PLL 8M Clock Enable. */ + __IOM uint32_t LP_AONCLKRST_HP_AUDIO_PLL_CLK_EN : 1;/*!< AUDIO PLL Clock Enable. */ + __IOM uint32_t LP_AONCLKRST_HP_SDIO_PLL2_CLK_EN : 1;/*!< SDIO PLL2 Clock Enable. */ + __IOM uint32_t LP_AONCLKRST_HP_SDIO_PLL1_CLK_EN : 1;/*!< SDIO PLL1 Clock Enable. */ + __IOM uint32_t LP_AONCLKRST_HP_SDIO_PLL0_CLK_EN : 1;/*!< SDIO PLL0 Clock Enable. */ + __IOM uint32_t LP_AONCLKRST_HP_FOSC_20M_CLK_EN : 1;/*!< FOSC 20M Clock Enable. */ + __IOM uint32_t LP_AONCLKRST_HP_XTAL_40M_CLK_EN : 1;/*!< XTAL 40M Clock Enalbe. */ + __IOM uint32_t LP_AONCLKRST_HP_CPLL_400M_CLK_EN : 1;/*!< CPLL 400M Clock Enable. */ + __IOM uint32_t LP_AONCLKRST_HP_SPLL_480M_CLK_EN : 1;/*!< SPLL 480M Clock Enable. */ + __IOM uint32_t LP_AONCLKRST_HP_MPLL_500M_CLK_EN : 1;/*!< MPLL 500M Clock Enable. */ + uint32_t : 3; + } bit; + } LP_AONCLKRST_HP_CLK_CTRL; + + union { + __IOM uint32_t reg; /*!< HP USB Clock Reset Control Register. */ + + struct { + __IOM uint32_t LP_AONCLKRST_USB_OTG20_SLEEP_MODE : 1;/*!< unused. */ + __IOM uint32_t LP_AONCLKRST_USB_OTG20_BK_SYS_CLK_EN : 1;/*!< unused. */ + __IOM uint32_t LP_AONCLKRST_USB_OTG11_SLEEP_MODE : 1;/*!< unused. */ + __IOM uint32_t LP_AONCLKRST_USB_OTG11_BK_SYS_CLK_EN : 1;/*!< unused. */ + __IOM uint32_t LP_AONCLKRST_USB_OTG11_48M_CLK_EN : 1;/*!< usb otg11 fs phy clock enable. */ + __IOM uint32_t LP_AONCLKRST_USB_DEVICE_48M_CLK_EN : 1;/*!< usb device fs phy clock enable. */ + __IOM uint32_t LP_AONCLKRST_USB_48M_DIV_NUM : 8;/*!< usb 480m to 25m divide number. */ + __IOM uint32_t LP_AONCLKRST_USB_25M_DIV_NUM : 8;/*!< usb 500m to 25m divide number. */ + __IOM uint32_t LP_AONCLKRST_USB_12M_DIV_NUM : 8;/*!< usb 480m to 12m divide number. */ + uint32_t : 2; + } bit; + } LP_AONCLKRST_HP_USB_CLKRST_CTRL0; + + union { + __IOM uint32_t reg; /*!< HP USB Clock Reset Control Register. */ + + struct { + __IOM uint32_t LP_AONCLKRST_RST_EN_USB_OTG20_ADP : 1;/*!< usb otg20 adp reset en */ + __IOM uint32_t LP_AONCLKRST_RST_EN_USB_OTG20_PHY : 1;/*!< usb otg20 phy reset en */ + __IOM uint32_t LP_AONCLKRST_RST_EN_USB_OTG20 : 1;/*!< usb otg20 reset en */ + __IOM uint32_t LP_AONCLKRST_RST_EN_USB_OTG11 : 1;/*!< usb org11 reset en */ + __IOM uint32_t LP_AONCLKRST_RST_EN_USB_DEVICE : 1;/*!< usb device reset en */ + uint32_t : 23; + __IOM uint32_t LP_AONCLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL : 2;/*!< usb otg20 hs phy src sel. 2'd0: 12m, 2'd1: 25m, 2'd2: pad_hsphy_refclk. */ + __IOM uint32_t LP_AONCLKRST_USB_OTG20_PHYREF_CLK_EN : 1;/*!< usb otg20 hs phy refclk enable. */ + __IOM uint32_t LP_AONCLKRST_USB_OTG20_ULPI_CLK_EN : 1;/*!< usb otg20 ulpi clock enable. */ + } bit; + } LP_AONCLKRST_HP_USB_CLKRST_CTRL1; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 28; + __IOM uint32_t LP_AONCLKRST_RST_EN_SDMMC : 1;/*!< hp sdmmc reset en */ + __IOM uint32_t LP_AONCLKRST_FORCE_NORST_SDMMC : 1;/*!< hp sdmmc force norst */ + __IOM uint32_t LP_AONCLKRST_RST_EN_EMAC : 1;/*!< hp emac reset en */ + __IOM uint32_t LP_AONCLKRST_FORCE_NORST_EMAC : 1;/*!< hp emac force norst */ + } bit; + } LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL; + __IM uint32_t RESERVED[235]; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 31; + __IOM uint32_t LP_AONCLKRST_CLK_EN : 1; /*!< need_des */ + } bit; + } LP_AONCLKRST_DATE; +} LP_AON_CLKRST_Type; /*!< Size = 1024 (0x400) */ + + + +/* =========================================================================================================================== */ +/* ================ LP_GPIO ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Low-power General Purpose Input/Output (LP_GPIO) + */ + +typedef struct { /*!< LP_GPIO Structure */ + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_CLK_EN : 1; /*!< Reserved */ + uint32_t : 31; + } bit; + } CLK_EN; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_VER_DATE : 28; /*!< Reserved */ + uint32_t : 4; + } bit; + } VER_DATE; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_GPIO_OUT_DATA : 16; /*!< Reserved */ + uint32_t : 16; + } bit; + } OUT; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __OM uint32_t REG_GPIO_OUT_DATA_W1TS : 16;/*!< Reserved */ + uint32_t : 16; + } bit; + } OUT_W1TS; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __OM uint32_t REG_GPIO_OUT_DATA_W1TC : 16;/*!< Reserved */ + uint32_t : 16; + } bit; + } OUT_W1TC; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_GPIO_ENABLE_DATA : 16; /*!< Reserved */ + uint32_t : 16; + } bit; + } ENABLE; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __OM uint32_t REG_GPIO_ENABLE_DATA_W1TS : 16;/*!< Reserved */ + uint32_t : 16; + } bit; + } ENABLE_W1TS; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __OM uint32_t REG_GPIO_ENABLE_DATA_W1TC : 16;/*!< Reserved */ + uint32_t : 16; + } bit; + } ENABLE_W1TC; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_GPIO_STATUS_DATA : 16; /*!< Reserved */ + uint32_t : 16; + } bit; + } STATUS; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __OM uint32_t REG_GPIO_STATUS_DATA_W1TS : 16;/*!< Reserved */ + uint32_t : 16; + } bit; + } STATUS_W1TS; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __OM uint32_t REG_GPIO_STATUS_DATA_W1TC : 16;/*!< Reserved */ + uint32_t : 16; + } bit; + } STATUS_W1TC; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IM uint32_t REG_GPIO_STATUS_INTERRUPT_NEXT : 16;/*!< Reserved */ + uint32_t : 16; + } bit; + } STATUS_NEXT; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IM uint32_t REG_GPIO_IN_DATA_NEXT : 16;/*!< Reserved */ + uint32_t : 16; + } bit; + } IN; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_GPIO_PIN0_WAKEUP_ENABLE : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_PIN0_INT_TYPE : 3;/*!< Reserved */ + __IOM uint32_t REG_GPIO_PIN0_PAD_DRIVER : 1;/*!< Reserved */ + __OM uint32_t REG_GPIO_PIN0_EDGE_WAKEUP_CLR : 1;/*!< need des */ + uint32_t : 26; + } bit; + } PIN0; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_GPIO_PIN1_WAKEUP_ENABLE : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_PIN1_INT_TYPE : 3;/*!< Reserved */ + __IOM uint32_t REG_GPIO_PIN1_PAD_DRIVER : 1;/*!< Reserved */ + __OM uint32_t REG_GPI1_PIN0_EDGE_WAKEUP_CLR : 1;/*!< need des */ + uint32_t : 26; + } bit; + } PIN1; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_GPIO_PIN2_WAKEUP_ENABLE : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_PIN2_INT_TYPE : 3;/*!< Reserved */ + __IOM uint32_t REG_GPIO_PIN2_PAD_DRIVER : 1;/*!< Reserved */ + __OM uint32_t REG_GPI2_PIN0_EDGE_WAKEUP_CLR : 1;/*!< need des */ + uint32_t : 26; + } bit; + } PIN2; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_GPIO_PIN3_WAKEUP_ENABLE : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_PIN3_INT_TYPE : 3;/*!< Reserved */ + __IOM uint32_t REG_GPIO_PIN3_PAD_DRIVER : 1;/*!< Reserved */ + __OM uint32_t REG_GPI3_PIN0_EDGE_WAKEUP_CLR : 1;/*!< need des */ + uint32_t : 26; + } bit; + } PIN3; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_GPIO_PIN4_WAKEUP_ENABLE : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_PIN4_INT_TYPE : 3;/*!< Reserved */ + __IOM uint32_t REG_GPIO_PIN4_PAD_DRIVER : 1;/*!< Reserved */ + __OM uint32_t REG_GPI4_PIN0_EDGE_WAKEUP_CLR : 1;/*!< need des */ + uint32_t : 26; + } bit; + } PIN4; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_GPIO_PIN5_WAKEUP_ENABLE : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_PIN5_INT_TYPE : 3;/*!< Reserved */ + __IOM uint32_t REG_GPIO_PIN5_PAD_DRIVER : 1;/*!< Reserved */ + __OM uint32_t REG_GPI5_PIN0_EDGE_WAKEUP_CLR : 1;/*!< need des */ + uint32_t : 26; + } bit; + } PIN5; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_GPIO_PIN6_WAKEUP_ENABLE : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_PIN6_INT_TYPE : 3;/*!< Reserved */ + __IOM uint32_t REG_GPIO_PIN6_PAD_DRIVER : 1;/*!< Reserved */ + __OM uint32_t REG_GPI6_PIN0_EDGE_WAKEUP_CLR : 1;/*!< need des */ + uint32_t : 26; + } bit; + } PIN6; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_GPIO_PIN7_WAKEUP_ENABLE : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_PIN7_INT_TYPE : 3;/*!< Reserved */ + __IOM uint32_t REG_GPIO_PIN7_PAD_DRIVER : 1;/*!< Reserved */ + __OM uint32_t REG_GPI7_PIN0_EDGE_WAKEUP_CLR : 1;/*!< need des */ + uint32_t : 26; + } bit; + } PIN7; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_GPIO_PIN8_WAKEUP_ENABLE : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_PIN8_INT_TYPE : 3;/*!< Reserved */ + __IOM uint32_t REG_GPIO_PIN8_PAD_DRIVER : 1;/*!< Reserved */ + __OM uint32_t REG_GPI8_PIN0_EDGE_WAKEUP_CLR : 1;/*!< need des */ + uint32_t : 26; + } bit; + } PIN8; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_GPIO_PIN9_WAKEUP_ENABLE : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_PIN9_INT_TYPE : 3;/*!< Reserved */ + __IOM uint32_t REG_GPIO_PIN9_PAD_DRIVER : 1;/*!< Reserved */ + __OM uint32_t REG_GPI9_PIN0_EDGE_WAKEUP_CLR : 1;/*!< need des */ + uint32_t : 26; + } bit; + } PIN9; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_GPIO_PIN10_WAKEUP_ENABLE : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_PIN10_INT_TYPE : 3;/*!< Reserved */ + __IOM uint32_t REG_GPIO_PIN10_PAD_DRIVER : 1;/*!< Reserved */ + __OM uint32_t REG_GPI10_PIN0_EDGE_WAKEUP_CLR : 1;/*!< need des */ + uint32_t : 26; + } bit; + } PIN10; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_GPIO_PIN11_WAKEUP_ENABLE : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_PIN11_INT_TYPE : 3;/*!< Reserved */ + __IOM uint32_t REG_GPIO_PIN11_PAD_DRIVER : 1;/*!< Reserved */ + __OM uint32_t REG_GPI11_PIN0_EDGE_WAKEUP_CLR : 1;/*!< need des */ + uint32_t : 26; + } bit; + } PIN11; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_GPIO_PIN12_WAKEUP_ENABLE : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_PIN12_INT_TYPE : 3;/*!< Reserved */ + __IOM uint32_t REG_GPIO_PIN12_PAD_DRIVER : 1;/*!< Reserved */ + __OM uint32_t REG_GPI12_PIN0_EDGE_WAKEUP_CLR : 1;/*!< need des */ + uint32_t : 26; + } bit; + } PIN12; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_GPIO_PIN13_WAKEUP_ENABLE : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_PIN13_INT_TYPE : 3;/*!< Reserved */ + __IOM uint32_t REG_GPIO_PIN13_PAD_DRIVER : 1;/*!< Reserved */ + __OM uint32_t REG_GPI13_PIN0_EDGE_WAKEUP_CLR : 1;/*!< need des */ + uint32_t : 26; + } bit; + } PIN13; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_GPIO_PIN14_WAKEUP_ENABLE : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_PIN14_INT_TYPE : 3;/*!< Reserved */ + __IOM uint32_t REG_GPIO_PIN14_PAD_DRIVER : 1;/*!< Reserved */ + __OM uint32_t REG_GPI14_PIN0_EDGE_WAKEUP_CLR : 1;/*!< need des */ + uint32_t : 26; + } bit; + } PIN14; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_GPIO_PIN15_WAKEUP_ENABLE : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_PIN15_INT_TYPE : 3;/*!< Reserved */ + __IOM uint32_t REG_GPIO_PIN15_PAD_DRIVER : 1;/*!< Reserved */ + __OM uint32_t REG_GPI15_PIN0_EDGE_WAKEUP_CLR : 1;/*!< need des */ + uint32_t : 26; + } bit; + } PIN15; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_GPIO_FUNC0_IN_INV_SEL : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_SIG0_IN_SEL : 1; /*!< Reserved */ + __IOM uint32_t REG_GPIO_FUNC0_IN_SEL : 6; /*!< reg_gpio_func0_in_sel[5:4]==2'b11->constant 1,reg_gpio_func0_in_sel[5:4]==2'b1 + ->constant 0 */ + uint32_t : 24; + } bit; + } FUNC0_IN_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_GPIO_FUNC1_IN_INV_SEL : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_SIG1_IN_SEL : 1; /*!< Reserved */ + __IOM uint32_t REG_GPIO_FUNC1_IN_SEL : 6; /*!< Reserved */ + uint32_t : 24; + } bit; + } FUNC1_IN_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_GPIO_FUNC2_IN_INV_SEL : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_SIG2_IN_SEL : 1; /*!< Reserved */ + __IOM uint32_t REG_GPIO_FUNC2_IN_SEL : 6; /*!< Reserved */ + uint32_t : 24; + } bit; + } FUNC2_IN_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_GPIO_FUNC3_IN_INV_SEL : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_SIG3_IN_SEL : 1; /*!< Reserved */ + __IOM uint32_t REG_GPIO_FUNC3_IN_SEL : 6; /*!< Reserved */ + uint32_t : 24; + } bit; + } FUNC3_IN_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_GPIO_FUNC4_IN_INV_SEL : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_SIG4_IN_SEL : 1; /*!< Reserved */ + __IOM uint32_t REG_GPIO_FUNC4_IN_SEL : 6; /*!< Reserved */ + uint32_t : 24; + } bit; + } FUNC4_IN_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_GPIO_FUNC5_IN_INV_SEL : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_SIG5_IN_SEL : 1; /*!< Reserved */ + __IOM uint32_t REG_GPIO_FUNC5_IN_SEL : 6; /*!< Reserved */ + uint32_t : 24; + } bit; + } FUNC5_IN_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_GPIO_FUNC6_IN_INV_SEL : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_SIG6_IN_SEL : 1; /*!< Reserved */ + __IOM uint32_t REG_GPIO_FUNC6_IN_SEL : 6; /*!< Reserved */ + uint32_t : 24; + } bit; + } FUNC6_IN_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_GPIO_FUNC7_IN_INV_SEL : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_SIG7_IN_SEL : 1; /*!< Reserved */ + __IOM uint32_t REG_GPIO_FUNC7_IN_SEL : 6; /*!< Reserved */ + uint32_t : 24; + } bit; + } FUNC7_IN_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_GPIO_FUNC8_IN_INV_SEL : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_SIG8_IN_SEL : 1; /*!< Reserved */ + __IOM uint32_t REG_GPIO_FUNC8_IN_SEL : 6; /*!< Reserved */ + uint32_t : 24; + } bit; + } FUNC8_IN_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_GPIO_FUNC9_IN_INV_SEL : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_SIG9_IN_SEL : 1; /*!< Reserved */ + __IOM uint32_t REG_GPIO_FUNC9_IN_SEL : 6; /*!< Reserved */ + uint32_t : 24; + } bit; + } FUNC9_IN_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_GPIO_FUNC10_IN_INV_SEL : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_SIG10_IN_SEL : 1; /*!< Reserved */ + __IOM uint32_t REG_GPIO_FUNC10_IN_SEL : 6;/*!< Reserved */ + uint32_t : 24; + } bit; + } FUNC10_IN_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_GPIO_FUNC11_IN_INV_SEL : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_SIG11_IN_SEL : 1; /*!< Reserved */ + __IOM uint32_t REG_GPIO_FUNC11_IN_SEL : 6;/*!< Reserved */ + uint32_t : 24; + } bit; + } FUNC11_IN_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_GPIO_FUNC12_IN_INV_SEL : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_SIG12_IN_SEL : 1; /*!< Reserved */ + __IOM uint32_t REG_GPIO_FUNC12_IN_SEL : 6;/*!< Reserved */ + uint32_t : 24; + } bit; + } FUNC12_IN_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_GPIO_FUNC13_IN_INV_SEL : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_SIG13_IN_SEL : 1; /*!< Reserved */ + __IOM uint32_t REG_GPIO_FUNC13_IN_SEL : 6;/*!< Reserved */ + uint32_t : 24; + } bit; + } FUNC13_IN_SEL_CFG; + __IM uint32_t RESERVED[18]; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_GPIO_FUNC0_OE_INV_SEL : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_FUNC0_OE_SEL : 1; /*!< Reserved */ + __IOM uint32_t REG_GPIO_FUNC0_OUT_INV_SEL : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_FUNC0_OUT_SEL : 6;/*!< reg_gpio_func0_out_sel[5:1]==16 -> output gpio register value + to pad */ + uint32_t : 23; + } bit; + } FUNC0_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_GPIO_FUNC1_OE_INV_SEL : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_FUNC1_OE_SEL : 1; /*!< Reserved */ + __IOM uint32_t REG_GPIO_FUNC1_OUT_INV_SEL : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_FUNC1_OUT_SEL : 6;/*!< Reserved */ + uint32_t : 23; + } bit; + } FUNC1_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_GPIO_FUNC2_OE_INV_SEL : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_FUNC2_OE_SEL : 1; /*!< Reserved */ + __IOM uint32_t REG_GPIO_FUNC2_OUT_INV_SEL : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_FUNC2_OUT_SEL : 6;/*!< Reserved */ + uint32_t : 23; + } bit; + } FUNC2_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_GPIO_FUNC3_OE_INV_SEL : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_FUNC3_OE_SEL : 1; /*!< Reserved */ + __IOM uint32_t REG_GPIO_FUNC3_OUT_INV_SEL : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_FUNC3_OUT_SEL : 6;/*!< Reserved */ + uint32_t : 23; + } bit; + } FUNC3_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_GPIO_FUNC4_OE_INV_SEL : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_FUNC4_OE_SEL : 1; /*!< Reserved */ + __IOM uint32_t REG_GPIO_FUNC4_OUT_INV_SEL : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_FUNC4_OUT_SEL : 6;/*!< Reserved */ + uint32_t : 23; + } bit; + } FUNC4_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_GPIO_FUNC5_OE_INV_SEL : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_FUNC5_OE_SEL : 1; /*!< Reserved */ + __IOM uint32_t REG_GPIO_FUNC5_OUT_INV_SEL : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_FUNC5_OUT_SEL : 6;/*!< Reserved */ + uint32_t : 23; + } bit; + } FUNC5_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_GPIO_FUNC6_OE_INV_SEL : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_FUNC6_OE_SEL : 1; /*!< Reserved */ + __IOM uint32_t REG_GPIO_FUNC6_OUT_INV_SEL : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_FUNC6_OUT_SEL : 6;/*!< Reserved */ + uint32_t : 23; + } bit; + } FUNC6_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_GPIO_FUNC7_OE_INV_SEL : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_FUNC7_OE_SEL : 1; /*!< Reserved */ + __IOM uint32_t REG_GPIO_FUNC7_OUT_INV_SEL : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_FUNC7_OUT_SEL : 6;/*!< Reserved */ + uint32_t : 23; + } bit; + } FUNC7_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_GPIO_FUNC8_OE_INV_SEL : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_FUNC8_OE_SEL : 1; /*!< Reserved */ + __IOM uint32_t REG_GPIO_FUNC8_OUT_INV_SEL : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_FUNC8_OUT_SEL : 6;/*!< Reserved */ + uint32_t : 23; + } bit; + } FUNC8_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_GPIO_FUNC9_OE_INV_SEL : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_FUNC9_OE_SEL : 1; /*!< Reserved */ + __IOM uint32_t REG_GPIO_FUNC9_OUT_INV_SEL : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_FUNC9_OUT_SEL : 6;/*!< Reserved */ + uint32_t : 23; + } bit; + } FUNC9_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_GPIO_FUNC10_OE_INV_SEL : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_FUNC10_OE_SEL : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_FUNC10_OUT_INV_SEL : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_FUNC10_OUT_SEL : 6;/*!< Reserved */ + uint32_t : 23; + } bit; + } FUNC10_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_GPIO_FUNC11_OE_INV_SEL : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_FUNC11_OE_SEL : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_FUNC11_OUT_INV_SEL : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_FUNC11_OUT_SEL : 6;/*!< Reserved */ + uint32_t : 23; + } bit; + } FUNC11_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_GPIO_FUNC12_OE_INV_SEL : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_FUNC12_OE_SEL : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_FUNC12_OUT_INV_SEL : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_FUNC12_OUT_SEL : 6;/*!< Reserved */ + uint32_t : 23; + } bit; + } FUNC12_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_GPIO_FUNC13_OE_INV_SEL : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_FUNC13_OE_SEL : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_FUNC13_OUT_INV_SEL : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_FUNC13_OUT_SEL : 6;/*!< Reserved */ + uint32_t : 23; + } bit; + } FUNC13_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_GPIO_FUNC14_OE_INV_SEL : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_FUNC14_OE_SEL : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_FUNC14_OUT_INV_SEL : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_FUNC14_OUT_SEL : 6;/*!< Reserved */ + uint32_t : 23; + } bit; + } FUNC14_OUT_SEL_CFG; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_GPIO_FUNC15_OE_INV_SEL : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_FUNC15_OE_SEL : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_FUNC15_OUT_INV_SEL : 1;/*!< Reserved */ + __IOM uint32_t REG_GPIO_FUNC15_OUT_SEL : 6;/*!< Reserved */ + uint32_t : 23; + } bit; + } FUNC15_OUT_SEL_CFG; +} LP_GPIO_Type; /*!< Size = 308 (0x134) */ + + + +/* =========================================================================================================================== */ +/* ================ LP_I2C0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Low-power I2C (Inter-Integrated Circuit) Controller 0 (LP_I2C0) + */ + +typedef struct { /*!< LP_I2C0 Structure */ + + union { + __IOM uint32_t reg; /*!< Configures the low level width of the SCLClock */ + + struct { + __IOM uint32_t SCL_LOW_PERIOD : 9; /*!< Configures the low level width of the SCL Clock. Measurement + unit: i2c_sclk. */ + uint32_t : 23; + } bit; + } SCL_LOW_PERIOD; + + union { + __IOM uint32_t reg; /*!< Transmission setting */ + + struct { + __IOM uint32_t SDA_FORCE_OUT : 1; /*!< Configures the SDA output mode1: Direct output,0: Open drain + output. */ + __IOM uint32_t SCL_FORCE_OUT : 1; /*!< Configures the SCL output mode1: Direct output,0: Open drain + output. */ + __IOM uint32_t SAMPLE_SCL_LEVEL : 1; /*!< Configures the sample mode for SDA.1: Sample SDA data on the + SCL low level.0: Sample SDA data on the SCL high level. */ + __IOM uint32_t RX_FULL_ACK_LEVEL : 1; /*!< Configures the ACK value that needs to be sent by master when + the rx_fifo_cnt has reached the threshold. */ + uint32_t : 1; + __OM uint32_t TRANS_START : 1; /*!< Configures to start sending the data in txfifo for slave. 0: + No effect1: Start */ + __IOM uint32_t TX_LSB_FIRST : 1; /*!< Configures to control the sending order for data needing to + be sent. 1: send data from the least significant bit,0: + send data from the most significant bit. */ + __IOM uint32_t RX_LSB_FIRST : 1; /*!< Configures to control the storage order for received data.1: + receive data from the least significant bit0: receive data + from the most significant bit. */ + __IOM uint32_t CLK_EN : 1; /*!< Configures whether to gate clock signal for registers.0: Force + clock on for registers 1: Support clock only when registers + are read or written to by software. */ + __IOM uint32_t ARBITRATION_EN : 1; /*!< Configures to enable I2C bus arbitration detection.0: No effect1: + Enable */ + __OM uint32_t FSM_RST : 1; /*!< Configures to reset the SCL_FSM.0: No effect1: Reset */ + __OM uint32_t CONF_UPGATE : 1; /*!< Configures this bit for synchronization0: No effect1: Synchronize */ + uint32_t : 20; + } bit; + } CTR; + + union { + __IOM uint32_t reg; /*!< Describe I2C work status. */ + + struct { + __IM uint32_t RESP_REC : 1; /*!< Represents the received ACK value in master mode or slave mode.0: + ACK,1: NACK. */ + uint32_t : 2; + __IM uint32_t ARB_LOST : 1; /*!< Represents whether the I2C controller loses control of SCL line.0: + No arbitration lost1: Arbitration lost */ + __IM uint32_t BUS_BUSY : 1; /*!< Represents the I2C bus state.1: The I2C bus is busy transferring + data, 0: The I2C bus is in idle state. */ + uint32_t : 3; + __IM uint32_t RXFIFO_CNT : 5; /*!< Represents the number of data bytes to be sent. */ + uint32_t : 5; + __IM uint32_t TXFIFO_CNT : 5; /*!< Represents the number of data bytes received in RAM. */ + uint32_t : 1; + __IM uint32_t SCL_MAIN_STATE_LAST : 3; /*!< Represents the states of the I2C module state machine. 0: Idle,1: + Address shift,2: ACK address,3: Rx data,4: Tx data,5: Send + ACK,6: Wait ACK */ + uint32_t : 1; + __IM uint32_t SCL_STATE_LAST : 3; /*!< Represents the states of the state machine used to produce SCL.0: + Idle,1: Start,2: Negative edge,3: Low,4: Positive edge,5: + High,6: Stop */ + uint32_t : 1; + } bit; + } SR; + + union { + __IOM uint32_t reg; /*!< Setting time out control for receiving data. */ + + struct { + __IOM uint32_t TIME_OUT_VALUE : 5; /*!< Configures the timeout threshold period for SCL stucking at + high or low level. The actual period is 2^(reg_time_out_value).Measuremen + unit: i2c_sclk. */ + __IOM uint32_t TIME_OUT_EN : 1; /*!< Configures to enable time out control.0: No effect1: Enable */ + uint32_t : 26; + } bit; + } TO; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t reg; /*!< FIFO status register. */ + + struct { + __IM uint32_t RXFIFO_RADDR : 4; /*!< Represents the offset address of the APB reading from RXFIFO */ + uint32_t : 1; + __IM uint32_t RXFIFO_WADDR : 4; /*!< Represents the offset address of i2c module receiving data and + writing to RXFIFO. */ + uint32_t : 1; + __IM uint32_t TXFIFO_RADDR : 4; /*!< Represents the offset address of i2c module reading from TXFIFO. */ + uint32_t : 1; + __IM uint32_t TXFIFO_WADDR : 4; /*!< Represents the offset address of APB bus writing to TXFIFO. */ + uint32_t : 13; + } bit; + } FIFO_ST; + + union { + __IOM uint32_t reg; /*!< FIFO configuration register. */ + + struct { + __IOM uint32_t RXFIFO_WM_THRHD : 4; /*!< Configures the water mark threshold of RXFIFO in nonfifo access + mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter + is bigger than reg_rxfifo_wm_thrhd[3:0], reg_rxfifo_wm_int_raw + bit will be valid. */ + uint32_t : 1; + __IOM uint32_t TXFIFO_WM_THRHD : 4; /*!< Configures the water mark threshold of TXFIFO in nonfifo access + mode. When reg_reg_fifo_prt_en is 1 and tx FIFO counter + is smaller than reg_txfifo_wm_thrhd[3:0], reg_txfifo_wm_int_raw + bit will be valid. */ + uint32_t : 1; + __IOM uint32_t NONFIFO_EN : 1; /*!< Configures to enable APB nonfifo access. */ + uint32_t : 1; + __IOM uint32_t RX_FIFO_RST : 1; /*!< Configures to reset RXFIFO.0: No effect1: Reset */ + __IOM uint32_t TX_FIFO_RST : 1; /*!< Configures to reset TXFIFO.0: No effect1: Reset */ + __IOM uint32_t FIFO_PRT_EN : 1; /*!< Configures to enable FIFO pointer in non-fifo access mode. This + bit controls the valid bits and the TX/RX FIFO overflow, + underflow, full and empty interrupts.0: No effect1: Enable */ + uint32_t : 17; + } bit; + } FIFO_CONF; + + union { + __IOM uint32_t reg; /*!< Rx FIFO read data. */ + + struct { + __IM uint32_t FIFO_RDATA : 8; /*!< Represents the value of RXFIFO read data. */ + uint32_t : 24; + } bit; + } DATA; + + union { + __IOM uint32_t reg; /*!< Raw interrupt status */ + + struct { + __IM uint32_t RXFIFO_WM_INT_RAW : 1; /*!< The raw interrupt status of I2C_RXFIFO_WM_INT interrupt. */ + __IM uint32_t TXFIFO_WM_INT_RAW : 1; /*!< The raw interrupt status of I2C_TXFIFO_WM_INT interrupt. */ + __IM uint32_t RXFIFO_OVF_INT_RAW : 1; /*!< The raw interrupt status of I2C_RXFIFO_OVF_INT interrupt. */ + __IM uint32_t END_DETECT_INT_RAW : 1; /*!< The raw interrupt status of the I2C_END_DETECT_INT interrupt. */ + __IM uint32_t BYTE_TRANS_DONE_INT_RAW : 1;/*!< The raw interrupt status of the I2C_END_DETECT_INT interrupt. */ + __IM uint32_t ARBITRATION_LOST_INT_RAW : 1;/*!< The raw interrupt status of the I2C_ARBITRATION_LOST_INT interrupt. */ + __IM uint32_t MST_TXFIFO_UDF_INT_RAW : 1;/*!< The raw interrupt status of I2C_TRANS_COMPLETE_INT interrupt. */ + __IM uint32_t TRANS_COMPLETE_INT_RAW : 1;/*!< The raw interrupt status of the I2C_TRANS_COMPLETE_INT interrupt. */ + __IM uint32_t TIME_OUT_INT_RAW : 1; /*!< The raw interrupt status of the I2C_TIME_OUT_INT interrupt. */ + __IM uint32_t TRANS_START_INT_RAW : 1; /*!< The raw interrupt status of the I2C_TRANS_START_INT interrupt. */ + __IM uint32_t NACK_INT_RAW : 1; /*!< The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt. */ + __IM uint32_t TXFIFO_OVF_INT_RAW : 1; /*!< The raw interrupt status of I2C_TXFIFO_OVF_INT interrupt. */ + __IM uint32_t RXFIFO_UDF_INT_RAW : 1; /*!< The raw interrupt status of I2C_RXFIFO_UDF_INT interrupt. */ + __IM uint32_t SCL_ST_TO_INT_RAW : 1; /*!< The raw interrupt status of I2C_SCL_ST_TO_INT interrupt. */ + __IM uint32_t SCL_MAIN_ST_TO_INT_RAW : 1;/*!< The raw interrupt status of I2C_SCL_MAIN_ST_TO_INT interrupt. */ + __IM uint32_t DET_START_INT_RAW : 1; /*!< The raw interrupt status of I2C_DET_START_INT interrupt. */ + uint32_t : 16; + } bit; + } INT_RAW; + + union { + __IOM uint32_t reg; /*!< Interrupt clear bits */ + + struct { + __OM uint32_t RXFIFO_WM_INT_CLR : 1; /*!< Write 1 to clear I2C_RXFIFO_WM_INT interrupt. */ + __OM uint32_t TXFIFO_WM_INT_CLR : 1; /*!< Write 1 to clear I2C_TXFIFO_WM_INT interrupt. */ + __OM uint32_t RXFIFO_OVF_INT_CLR : 1; /*!< Write 1 to clear I2C_RXFIFO_OVF_INT interrupt. */ + __OM uint32_t END_DETECT_INT_CLR : 1; /*!< Write 1 to clear the I2C_END_DETECT_INT interrupt. */ + __OM uint32_t BYTE_TRANS_DONE_INT_CLR : 1;/*!< Write 1 to clear the I2C_END_DETECT_INT interrupt. */ + __OM uint32_t ARBITRATION_LOST_INT_CLR : 1;/*!< Write 1 to clear the I2C_ARBITRATION_LOST_INT interrupt. */ + __OM uint32_t MST_TXFIFO_UDF_INT_CLR : 1;/*!< Write 1 to clear I2C_TRANS_COMPLETE_INT interrupt. */ + __OM uint32_t TRANS_COMPLETE_INT_CLR : 1;/*!< Write 1 to clear the I2C_TRANS_COMPLETE_INT interrupt. */ + __OM uint32_t TIME_OUT_INT_CLR : 1; /*!< Write 1 to clear the I2C_TIME_OUT_INT interrupt. */ + __OM uint32_t TRANS_START_INT_CLR : 1; /*!< Write 1 to clear the I2C_TRANS_START_INT interrupt. */ + __OM uint32_t NACK_INT_CLR : 1; /*!< Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt. */ + __OM uint32_t TXFIFO_OVF_INT_CLR : 1; /*!< Write 1 to clear I2C_TXFIFO_OVF_INT interrupt. */ + __OM uint32_t RXFIFO_UDF_INT_CLR : 1; /*!< Write 1 to clear I2C_RXFIFO_UDF_INT interrupt. */ + __OM uint32_t SCL_ST_TO_INT_CLR : 1; /*!< Write 1 to clear I2C_SCL_ST_TO_INT interrupt. */ + __OM uint32_t SCL_MAIN_ST_TO_INT_CLR : 1;/*!< Write 1 to clear I2C_SCL_MAIN_ST_TO_INT interrupt. */ + __OM uint32_t DET_START_INT_CLR : 1; /*!< Write 1 to clear I2C_DET_START_INT interrupt. */ + uint32_t : 16; + } bit; + } INT_CLR; + + union { + __IOM uint32_t reg; /*!< Interrupt enable bits */ + + struct { + __IOM uint32_t RXFIFO_WM_INT_ENA : 1; /*!< Write 1 to anable I2C_RXFIFO_WM_INT interrupt. */ + __IOM uint32_t TXFIFO_WM_INT_ENA : 1; /*!< Write 1 to anable I2C_TXFIFO_WM_INT interrupt. */ + __IOM uint32_t RXFIFO_OVF_INT_ENA : 1; /*!< Write 1 to anable I2C_RXFIFO_OVF_INT interrupt. */ + __IOM uint32_t END_DETECT_INT_ENA : 1; /*!< Write 1 to anable the I2C_END_DETECT_INT interrupt. */ + __IOM uint32_t BYTE_TRANS_DONE_INT_ENA : 1;/*!< Write 1 to anable the I2C_END_DETECT_INT interrupt. */ + __IOM uint32_t ARBITRATION_LOST_INT_ENA : 1;/*!< Write 1 to anable the I2C_ARBITRATION_LOST_INT interrupt. */ + __IOM uint32_t MST_TXFIFO_UDF_INT_ENA : 1;/*!< Write 1 to anable I2C_TRANS_COMPLETE_INT interrupt. */ + __IOM uint32_t TRANS_COMPLETE_INT_ENA : 1;/*!< Write 1 to anable the I2C_TRANS_COMPLETE_INT interrupt. */ + __IOM uint32_t TIME_OUT_INT_ENA : 1; /*!< Write 1 to anable the I2C_TIME_OUT_INT interrupt. */ + __IOM uint32_t TRANS_START_INT_ENA : 1; /*!< Write 1 to anable the I2C_TRANS_START_INT interrupt. */ + __IOM uint32_t NACK_INT_ENA : 1; /*!< Write 1 to anable I2C_SLAVE_STRETCH_INT interrupt. */ + __IOM uint32_t TXFIFO_OVF_INT_ENA : 1; /*!< Write 1 to anable I2C_TXFIFO_OVF_INT interrupt. */ + __IOM uint32_t RXFIFO_UDF_INT_ENA : 1; /*!< Write 1 to anable I2C_RXFIFO_UDF_INT interrupt. */ + __IOM uint32_t SCL_ST_TO_INT_ENA : 1; /*!< Write 1 to anable I2C_SCL_ST_TO_INT interrupt. */ + __IOM uint32_t SCL_MAIN_ST_TO_INT_ENA : 1;/*!< Write 1 to anable I2C_SCL_MAIN_ST_TO_INT interrupt. */ + __IOM uint32_t DET_START_INT_ENA : 1; /*!< Write 1 to anable I2C_DET_START_INT interrupt. */ + uint32_t : 16; + } bit; + } INT_ENA; + + union { + __IOM uint32_t reg; /*!< Status of captured I2C communication events */ + + struct { + __IM uint32_t RXFIFO_WM_INT_ST : 1; /*!< The masked interrupt status status of I2C_RXFIFO_WM_INT interrupt. */ + __IM uint32_t TXFIFO_WM_INT_ST : 1; /*!< The masked interrupt status status of I2C_TXFIFO_WM_INT interrupt. */ + __IM uint32_t RXFIFO_OVF_INT_ST : 1; /*!< The masked interrupt status status of I2C_RXFIFO_OVF_INT interrupt. */ + __IM uint32_t END_DETECT_INT_ST : 1; /*!< The masked interrupt status status of the I2C_END_DETECT_INT + interrupt. */ + __IM uint32_t BYTE_TRANS_DONE_INT_ST : 1;/*!< The masked interrupt status status of the I2C_END_DETECT_INT + interrupt. */ + __IM uint32_t ARBITRATION_LOST_INT_ST : 1;/*!< The masked interrupt status status of the I2C_ARBITRATION_LOST_INT + interrupt. */ + __IM uint32_t MST_TXFIFO_UDF_INT_ST : 1; /*!< The masked interrupt status status of I2C_TRANS_COMPLETE_INT + interrupt. */ + __IM uint32_t TRANS_COMPLETE_INT_ST : 1; /*!< The masked interrupt status status of the I2C_TRANS_COMPLETE_INT + interrupt. */ + __IM uint32_t TIME_OUT_INT_ST : 1; /*!< The masked interrupt status status of the I2C_TIME_OUT_INT interrupt. */ + __IM uint32_t TRANS_START_INT_ST : 1; /*!< The masked interrupt status status of the I2C_TRANS_START_INT + interrupt. */ + __IM uint32_t NACK_INT_ST : 1; /*!< The masked interrupt status status of I2C_SLAVE_STRETCH_INT + interrupt. */ + __IM uint32_t TXFIFO_OVF_INT_ST : 1; /*!< The masked interrupt status status of I2C_TXFIFO_OVF_INT interrupt. */ + __IM uint32_t RXFIFO_UDF_INT_ST : 1; /*!< The masked interrupt status status of I2C_RXFIFO_UDF_INT interrupt. */ + __IM uint32_t SCL_ST_TO_INT_ST : 1; /*!< The masked interrupt status status of I2C_SCL_ST_TO_INT interrupt. */ + __IM uint32_t SCL_MAIN_ST_TO_INT_ST : 1; /*!< The masked interrupt status status of I2C_SCL_MAIN_ST_TO_INT + interrupt. */ + __IM uint32_t DET_START_INT_ST : 1; /*!< The masked interrupt status status of I2C_DET_START_INT interrupt. */ + uint32_t : 16; + } bit; + } INT_STATUS; + + union { + __IOM uint32_t reg; /*!< Configures the hold time after a negative SCL edge. */ + + struct { + __IOM uint32_t TIME : 9; /*!< Configures the time to hold the data after the falling edge + of SCL.Measurement unit: i2c_sclk */ + uint32_t : 23; + } bit; + } SDA_HOLD; + + union { + __IOM uint32_t reg; /*!< Configures the sample time after a positive SCL edge. */ + + struct { + __IOM uint32_t TIME : 9; /*!< Configures the sample time after a positive SCL edge.Measurement + unit: i2c_sclk */ + uint32_t : 23; + } bit; + } SDA_SAMPLE; + + union { + __IOM uint32_t reg; /*!< Configures the high level width of SCL */ + + struct { + __IOM uint32_t SCL_HIGH_PERIOD : 9; /*!< Configures for how long SCL remains high in master mode.Measurement + unit: i2c_sclk */ + __IOM uint32_t SCL_WAIT_HIGH_PERIOD : 7; /*!< Configures the SCL_FSM's waiting period for SCL high level in + master mode.Measurement unit: i2c_sclk */ + uint32_t : 16; + } bit; + } SCL_HIGH_PERIOD; + __IM uint32_t RESERVED1; + + union { + __IOM uint32_t reg; /*!< Configures the delay between the SDA and SCL negative edge for + a start condition */ + + struct { + __IOM uint32_t TIME : 9; /*!< Configures the time between the falling edge of SDA and the + falling edge of SCL for a START condition.Measurement unit: + i2c_sclk. */ + uint32_t : 23; + } bit; + } SCL_START_HOLD; + + union { + __IOM uint32_t reg; /*!< Configures the delay between the positiveedge of SCL and the + negative edge of SDA */ + + struct { + __IOM uint32_t TIME : 9; /*!< Configures the time between the positive edge of SCL and the + negative edge of SDA for a RESTART condition.Measurement + unit: i2c_sclk */ + uint32_t : 23; + } bit; + } SCL_RSTART_SETUP; + + union { + __IOM uint32_t reg; /*!< Configures the delay after the SCL clockedge for a stop condition */ + + struct { + __IOM uint32_t TIME : 9; /*!< Configures the delay after the STOP condition.Measurement unit: + i2c_sclk */ + uint32_t : 23; + } bit; + } SCL_STOP_HOLD; + + union { + __IOM uint32_t reg; /*!< Configures the delay between the SDA andSCL positive edge for + a stop condition */ + + struct { + __IOM uint32_t TIME : 9; /*!< Configures the time between the rising edge of SCL and the rising + edge of SDA.Measurement unit: i2c_sclk */ + uint32_t : 23; + } bit; + } SCL_STOP_SETUP; + + union { + __IOM uint32_t reg; /*!< SCL and SDA filter configuration register */ + + struct { + __IOM uint32_t SCL_FILTER_THRES : 4; /*!< Configures the threshold pulse width to be filtered on SCL. + When a pulse on the SCL input has smaller width than this + register value, the I2C controller will ignore that pulse. + Measurement unit: i2c_sclk */ + __IOM uint32_t SDA_FILTER_THRES : 4; /*!< Configures the threshold pulse width to be filtered on SDA. + When a pulse on the SDA input has smaller width than this + register value, the I2C controller will ignore that pulse. + Measurement unit: i2c_sclk */ + __IOM uint32_t SCL_FILTER_EN : 1; /*!< Configures to enable the filter function for SCL. */ + __IOM uint32_t SDA_FILTER_EN : 1; /*!< Configures to enable the filter function for SDA. */ + uint32_t : 22; + } bit; + } FILTER_CFG; + + union { + __IOM uint32_t reg; /*!< I2C CLK configuration register */ + + struct { + __IOM uint32_t SCLK_DIV_NUM : 8; /*!< the integral part of the fractional divisor for i2c module */ + __IOM uint32_t SCLK_DIV_A : 6; /*!< the numerator of the fractional part of the fractional divisor + for i2c module */ + __IOM uint32_t SCLK_DIV_B : 6; /*!< the denominator of the fractional part of the fractional divisor + for i2c module */ + __IOM uint32_t SCLK_SEL : 1; /*!< The clock selection for i2c module:0-XTAL,1-CLK_8MHz. */ + __IOM uint32_t SCLK_ACTIVE : 1; /*!< The clock switch for i2c module */ + uint32_t : 10; + } bit; + } CLK_CONF; + + union { + __IOM uint32_t reg; /*!< I2C command register 0 */ + + struct { + __IOM uint32_t COMMAND0 : 14; /*!< Configures command 0. It consists of three parts: op_code is + the command,0: RSTART, 1: WRITE,2: READ,3: STOP,4: END.Byte_num + represents the number of bytes that need to be sent or + received.ack_check_en, ack_exp and ack are used to control + the ACK bit. See I2C cmd structure for more information. */ + uint32_t : 17; + __IOM uint32_t COMMAND0_DONE : 1; /*!< Represents whether command 0 is done in I2C Master mode.0: Not + done1: Done */ + } bit; + } COMD0; + + union { + __IOM uint32_t reg; /*!< I2C command register 1 */ + + struct { + __IOM uint32_t COMMAND1 : 14; /*!< Configures command 1. See details in I2C_CMD0_REG[13:0]. */ + uint32_t : 17; + __IOM uint32_t COMMAND1_DONE : 1; /*!< Represents whether command 1 is done in I2C Master mode.0: Not + done1: Done */ + } bit; + } COMD1; + + union { + __IOM uint32_t reg; /*!< I2C command register 2 */ + + struct { + __IOM uint32_t COMMAND2 : 14; /*!< Configures command 2. See details in I2C_CMD0_REG[13:0]. */ + uint32_t : 17; + __IOM uint32_t COMMAND2_DONE : 1; /*!< Represents whether command 2 is done in I2C Master mode.0: Not + done1: Done */ + } bit; + } COMD2; + + union { + __IOM uint32_t reg; /*!< I2C command register 3 */ + + struct { + __IOM uint32_t COMMAND3 : 14; /*!< Configures command 3. See details in I2C_CMD0_REG[13:0]. */ + uint32_t : 17; + __IOM uint32_t COMMAND3_DONE : 1; /*!< Represents whether command 3 is done in I2C Master mode.0: Not + done1: Done */ + } bit; + } COMD3; + + union { + __IOM uint32_t reg; /*!< I2C command register 4 */ + + struct { + __IOM uint32_t COMMAND4 : 14; /*!< Configures command 4. See details in I2C_CMD0_REG[13:0]. */ + uint32_t : 17; + __IOM uint32_t COMMAND4_DONE : 1; /*!< Represents whether command 4 is done in I2C Master mode.0: Not + done1: Done */ + } bit; + } COMD4; + + union { + __IOM uint32_t reg; /*!< I2C command register 5 */ + + struct { + __IOM uint32_t COMMAND5 : 14; /*!< Configures command 5. See details in I2C_CMD0_REG[13:0]. */ + uint32_t : 17; + __IOM uint32_t COMMAND5_DONE : 1; /*!< Represents whether command 5 is done in I2C Master mode.0: Not + done1: Done */ + } bit; + } COMD5; + + union { + __IOM uint32_t reg; /*!< I2C command register 6 */ + + struct { + __IOM uint32_t COMMAND6 : 14; /*!< Configures command 6. See details in I2C_CMD0_REG[13:0]. */ + uint32_t : 17; + __IOM uint32_t COMMAND6_DONE : 1; /*!< Represents whether command 6 is done in I2C Master mode.0: Not + done1: Done */ + } bit; + } COMD6; + + union { + __IOM uint32_t reg; /*!< I2C command register 7 */ + + struct { + __IOM uint32_t COMMAND7 : 14; /*!< Configures command 7. See details in I2C_CMD0_REG[13:0]. */ + uint32_t : 17; + __IOM uint32_t COMMAND7_DONE : 1; /*!< Represents whether command 7 is done in I2C Master mode.0: Not + done1: Done */ + } bit; + } COMD7; + + union { + __IOM uint32_t reg; /*!< SCL status time out register */ + + struct { + __IOM uint32_t SCL_ST_TO_I2C : 5; /*!< Configures the threshold value of SCL_FSM state unchanged period. + It should be no more than 23.Measurement unit: i2c_sclk */ + uint32_t : 27; + } bit; + } SCL_ST_TIME_OUT; + + union { + __IOM uint32_t reg; /*!< SCL main status time out register */ + + struct { + __IOM uint32_t SCL_MAIN_ST_TO_I2C : 5; /*!< Configures the threshold value of SCL_MAIN_FSM state unchanged + period.nIt should be no more than 23.Measurement unit: + i2c_sclk */ + uint32_t : 27; + } bit; + } SCL_MAIN_ST_TIME_OUT; + + union { + __IOM uint32_t reg; /*!< Power configuration register */ + + struct { + __IOM uint32_t SCL_RST_SLV_EN : 1; /*!< When I2C master is IDLE, set this bit to send out SCL pulses. + The number of pulses equals to reg_scl_rst_slv_num[4:0]. */ + __IOM uint32_t SCL_RST_SLV_NUM : 5; /*!< Configures to send out SCL pulses when I2C master is IDLE. The + number of pulses equals to reg_scl_rst_slv_num[4:0]. */ + __IOM uint32_t SCL_PD_EN : 1; /*!< Configure the pulses of SCL generated in I2C master mode. Valid + when reg_scl_rst_slv_en is 1.Measurement unit: i2c_sclk */ + __IOM uint32_t SDA_PD_EN : 1; /*!< Configures to power down the I2C output SCL line. 0: Not power + down.1: Power down.Valid only when reg_scl_force_out is + 1. */ + uint32_t : 24; + } bit; + } SCL_SP_CONF; + __IM uint32_t RESERVED2[29]; + + union { + __IOM uint32_t reg; /*!< Version register */ + + struct { + __IOM uint32_t DATE : 32; /*!< Version control register. */ + } bit; + } DATE; + __IM uint32_t RESERVED3; + + union { + __IOM uint32_t reg; /*!< I2C TXFIFO base address register */ + + struct { + __IM uint32_t TXFIFO_START_ADDR : 32; /*!< Represents the I2C txfifo first address. */ + } bit; + } TXFIFO_START_ADDR; + __IM uint32_t RESERVED4[31]; + + union { + __IOM uint32_t reg; /*!< I2C RXFIFO base address register */ + + struct { + __IM uint32_t RXFIFO_START_ADDR : 32; /*!< Represents the I2C rxfifo first address. */ + } bit; + } RXFIFO_START_ADDR; +} LP_I2C0_Type; /*!< Size = 388 (0x184) */ + + + +/* =========================================================================================================================== */ +/* ================ LP_I2S0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Low-power I2S (Inter-IC Sound) Controller 0 (LP_I2S0) + */ + +typedef struct { /*!< LP_I2S0 Structure */ + + union { + __IOM uint32_t reg; /*!< I2S VAD Configure register */ + + struct { + __IOM uint32_t VAD_EN : 1; /*!< VAD enable register */ + __OM uint32_t VAD_RESET : 1; /*!< VAD reset register */ + __OM uint32_t VAD_FORCE_START : 1; /*!< VAD force start register. */ + uint32_t : 29; + } bit; + } VAD_CONF; + + union { + __IOM uint32_t reg; /*!< I2S VAD Result register */ + + struct { + __IM uint32_t VAD_FLAG : 1; /*!< Reg vad flag observe signal */ + __IM uint32_t ENERGY_ENOUGH : 1; /*!< Reg energy enough observe signal */ + uint32_t : 30; + } bit; + } VAD_RESULT; + + union { + __IOM uint32_t reg; /*!< I2S VAD Observe register */ + + struct { + __IM uint32_t RX_MEM_FIFO_CNT : 9; /*!< The number of data in the rx mem */ + __IOM uint32_t RX_MEM_THRESHOLD : 8; /*!< I2S rx mem will trigger an interrupt when the data in the mem + is over(not including equal) reg_rx_mem_threshold */ + uint32_t : 15; + } bit; + } RX_MEM_CONF; + + union { + __IOM uint32_t reg; /*!< I2S interrupt raw register, valid in level. */ + + struct { + __IM uint32_t RX_DONE_INT_RAW : 1; /*!< The raw interrupt status bit for the i2s_rx_done_int interrupt */ + __IM uint32_t RX_HUNG_INT_RAW : 1; /*!< The raw interrupt status bit for the i2s_rx_hung_int interrupt */ + __IM uint32_t RX_FIFOMEM_UDF_INT_RAW : 1;/*!< The raw interrupt status bit for the i2s_rx_fifomem_udf_int + interrupt */ + __IM uint32_t VAD_DONE_INT_RAW : 1; /*!< The raw interrupt status bit for the vad_done_int interrupt */ + __IM uint32_t VAD_RESET_DONE_INT_RAW : 1;/*!< The raw interrupt status bit for the vad_reset_done_int interrupt */ + __IM uint32_t RX_MEM_THRESHOLD_INT_RAW : 1;/*!< The raw interrupt status bit for the rx_mem_threshold_int interrupt */ + uint32_t : 26; + } bit; + } INT_RAW; + + union { + __IOM uint32_t reg; /*!< I2S interrupt status register. */ + + struct { + __IM uint32_t RX_DONE_INT_ST : 1; /*!< The masked interrupt status bit for the i2s_rx_done_int interrupt */ + __IM uint32_t RX_HUNG_INT_ST : 1; /*!< The masked interrupt status bit for the i2s_rx_hung_int interrupt */ + __IM uint32_t RX_FIFOMEM_UDF_INT_ST : 1; /*!< The masked interrupt status bit for the i2s_rx_fifomem_udf_int + interrupt */ + __IM uint32_t LP_VAD_DONE_INT_ST : 1; /*!< The masked interrupt status bit for the vad_done_int interrupt */ + __IM uint32_t LP_VAD_RESET_DONE_INT_ST : 1;/*!< The masked interrupt status bit for the vad_reset_done_int interrupt */ + __IM uint32_t RX_MEM_THRESHOLD_INT_ST : 1;/*!< The masked interrupt status bit for the rx_mem_threshold_int + interrupt */ + uint32_t : 26; + } bit; + } INT_ST; + + union { + __IOM uint32_t reg; /*!< I2S interrupt enable register. */ + + struct { + __IOM uint32_t RX_DONE_INT_ENA : 1; /*!< The interrupt enable bit for the i2s_rx_done_int interrupt */ + __IOM uint32_t RX_HUNG_INT_ENA : 1; /*!< The interrupt enable bit for the i2s_rx_hung_int interrupt */ + __IOM uint32_t RX_FIFOMEM_UDF_INT_ENA : 1;/*!< The interrupt enable bit for the i2s_rx_fifomem_udf_int interrupt */ + __IOM uint32_t LP_VAD_DONE_INT_ENA : 1; /*!< The interrupt enable bit for the vad_done_int interrupt */ + __IOM uint32_t LP_VAD_RESET_DONE_INT_ENA : 1;/*!< The interrupt enable bit for the vad_reset_done_int interrupt */ + __IOM uint32_t RX_MEM_THRESHOLD_INT_ENA : 1;/*!< The interrupt enable bit for the rx_mem_threshold_int interrupt */ + uint32_t : 26; + } bit; + } INT_ENA; + + union { + __IOM uint32_t reg; /*!< I2S interrupt clear register. */ + + struct { + __OM uint32_t RX_DONE_INT_CLR : 1; /*!< Set this bit to clear the i2s_rx_done_int interrupt */ + __OM uint32_t RX_HUNG_INT_CLR : 1; /*!< Set this bit to clear the i2s_rx_hung_int interrupt */ + __OM uint32_t RX_FIFOMEM_UDF_INT_CLR : 1;/*!< Set this bit to clear the i2s_rx_fifomem_udf_int interrupt */ + __OM uint32_t LP_VAD_DONE_INT_CLR : 1; /*!< Set this bit to clear the vad_done_int interrupt */ + __OM uint32_t LP_VAD_RESET_DONE_INT_CLR : 1;/*!< Set this bit to clear the vad_reset_done_int interrupt */ + __OM uint32_t RX_MEM_THRESHOLD_INT_CLR : 1;/*!< Set this bit to clear the rx_mem_threshold_int interrupt */ + uint32_t : 26; + } bit; + } INT_CLR; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t reg; /*!< I2S RX configure register */ + + struct { + __OM uint32_t RX_RESET : 1; /*!< Set this bit to reset receiver */ + __OM uint32_t RX_FIFO_RESET : 1; /*!< Set this bit to reset Rx AFIFO */ + __IOM uint32_t RX_START : 1; /*!< Set this bit to start receiving data */ + __IOM uint32_t RX_SLAVE_MOD : 1; /*!< Set this bit to enable slave receiver mode */ + __OM uint32_t RX_FIFOMEM_RESET : 1; /*!< Set this bit to reset Rx Syncfifomem */ + __IOM uint32_t RX_MONO : 1; /*!< Set this bit to enable receiver in mono mode */ + uint32_t : 1; + __IOM uint32_t RX_BIG_ENDIAN : 1; /*!< I2S Rx byte endian, 1: low addr value to high addr. 0: low addr + with low addr value. */ + __IOM uint32_t RX_UPDATE : 1; /*!< Set 1 to update I2S RX registers from APB clock domain to I2S + RX clock domain. This bit will be cleared by hardware after + update register done. */ + __IOM uint32_t RX_MONO_FST_VLD : 1; /*!< 1: The first channel data value is valid in I2S RX mono mode. + 0: The second channel data value is valid in I2S RX mono + mode. */ + __IOM uint32_t RX_PCM_CONF : 2; /*!< I2S RX compress/decompress configuration bit. & 0 (atol): A-Law + decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law + decompress, 3 (ltou) : u-Law compress. & */ + __IOM uint32_t RX_PCM_BYPASS : 1; /*!< Set this bit to bypass Compress/Decompress module for received + data. */ + __IOM uint32_t RX_STOP_MODE : 2; /*!< 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when + reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when + reg_rx_start is 0 or RX FIFO is full. */ + __IOM uint32_t RX_LEFT_ALIGN : 1; /*!< 1: I2S RX left alignment mode. 0: I2S RX right alignment mode. */ + __IOM uint32_t RX_24_FILL_EN : 1; /*!< 1: store 24 channel bits to 32 bits. 0:store 24 channel bits + to 24 bits. */ + __IOM uint32_t RX_WS_IDLE_POL : 1; /*!< 0: WS should be 0 when receiving left channel data, and WS is + 1in right channel. 1: WS should be 1 when receiving left + channel data, and WS is 0in right channel. */ + __IOM uint32_t RX_BIT_ORDER : 1; /*!< I2S Rx bit endian. 1:small endian, the LSB is received first. + 0:big endian, the MSB is received first. */ + __IOM uint32_t RX_TDM_EN : 1; /*!< 1: Enable I2S TDM Rx mode . 0: Disable. */ + __IOM uint32_t RX_PDM_EN : 1; /*!< 1: Enable I2S PDM Rx mode . 0: Disable. */ + uint32_t : 11; + } bit; + } RX_CONF; + __IM uint32_t RESERVED1; + + union { + __IOM uint32_t reg; /*!< I2S RX configure register 1 */ + + struct { + __IOM uint32_t RX_TDM_WS_WIDTH : 7; /*!< The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH[6:0] + +1) * T_bck */ + __IOM uint32_t RX_BCK_DIV_NUM : 6; /*!< Bit clock configuration bits in receiver mode. */ + __IOM uint32_t RX_BITS_MOD : 5; /*!< Set the bits to configure the valid data bit length of I2S receiver + channel. 7: all the valid channel data is in 8-bit-mode. + 15: all the valid channel data is in 16-bit-mode. 23: all + the valid channel data is in 24-bit-mode. 31:all the valid + channel data is in 32-bit-mode. */ + __IOM uint32_t RX_HALF_SAMPLE_BITS : 6; /*!< I2S Rx half sample bits -1. */ + __IOM uint32_t RX_TDM_CHAN_BITS : 5; /*!< The Rx bit number for each channel minus 1in TDM mode. */ + __IOM uint32_t RX_MSB_SHIFT : 1; /*!< Set this bit to enable receiver in Phillips standard mode */ + uint32_t : 2; + } bit; + } RX_CONF1; + __IM uint32_t RESERVED2[9]; + + union { + __IOM uint32_t reg; /*!< I2S TX TDM mode control register */ + + struct { + __IOM uint32_t RX_TDM_PDM_CHAN0_EN : 1; /*!< 1: Enable the valid data input of I2S RX TDM or PDM channel + 0. 0: Disable, just input 0 in this channel. */ + __IOM uint32_t RX_TDM_PDM_CHAN1_EN : 1; /*!< 1: Enable the valid data input of I2S RX TDM or PDM channel + 1. 0: Disable, just input 0 in this channel. */ + uint32_t : 14; + __IOM uint32_t RX_TDM_TOT_CHAN_NUM : 4; /*!< The total channel number of I2S TX TDM mode. */ + uint32_t : 12; + } bit; + } RX_TDM_CTRL; + __IM uint32_t RESERVED3; + + union { + __IOM uint32_t reg; /*!< I2S RX timing control register */ + + struct { + __IOM uint32_t RX_SD_IN_DM : 2; /*!< The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay + by pos edge. 2: delay by neg edge. 3: not used. */ + uint32_t : 14; + __IOM uint32_t RX_WS_OUT_DM : 2; /*!< The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay + by pos edge. 2: delay by neg edge. 3: not used. */ + uint32_t : 2; + __IOM uint32_t RX_BCK_OUT_DM : 2; /*!< The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay + by pos edge. 2: delay by neg edge. 3: not used. */ + uint32_t : 2; + __IOM uint32_t RX_WS_IN_DM : 2; /*!< The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay + by pos edge. 2: delay by neg edge. 3: not used. */ + uint32_t : 2; + __IOM uint32_t RX_BCK_IN_DM : 2; /*!< The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay + by pos edge. 2: delay by neg edge. 3: not used. */ + uint32_t : 2; + } bit; + } RX_TIMING; + __IM uint32_t RESERVED4; + + union { + __IOM uint32_t reg; /*!< I2S HUNG configure register. */ + + struct { + __IOM uint32_t LC_FIFO_TIMEOUT : 8; /*!< the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt + will be triggered when fifo hung counter is equal to this + value */ + __IOM uint32_t LC_FIFO_TIMEOUT_SHIFT : 3; /*!< The bits are used to scale tick counter threshold. The tick + counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift */ + __IOM uint32_t LC_FIFO_TIMEOUT_ENA : 1; /*!< The enable bit for FIFO timeout */ + uint32_t : 20; + } bit; + } LC_HUNG_CONF; + + union { + __IOM uint32_t reg; /*!< I2S RX data number control register. */ + + struct { + __IOM uint32_t RX_EOF_NUM : 12; /*!< The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * + (REG_RX_EOF_NUM[11:0] + 1) . It will trigger in_suc_eof + interrupt in the configured DMA RX channel. */ + uint32_t : 20; + } bit; + } RXEOF_NUM; + + union { + __IOM uint32_t reg; /*!< I2S signal data register */ + + struct { + __IOM uint32_t SINGLE_DATA : 32; /*!< The configured constant channel data to be sent out. */ + } bit; + } CONF_SIGLE_DATA; + __IM uint32_t RESERVED5; + + union { + __IOM uint32_t reg; /*!< I2S RX configure register */ + + struct { + uint32_t : 19; + __IOM uint32_t RX_PDM2PCM_EN : 1; /*!< 1: Enable PDM2PCM RX mode. 0: DIsable. */ + __IOM uint32_t RX_PDM_SINC_DSR_16_EN : 1; /*!< Configure the down sampling rate of PDM RX filter group1 module. + 1: The down sampling rate is 128. 0: down sampling rate + is 64. */ + __IOM uint32_t RX_PDM2PCM_AMPLIFY_NUM : 4;/*!< Configure PDM RX amplify number. */ + __IOM uint32_t RX_PDM_HP_BYPASS : 1; /*!< I2S PDM RX bypass hp filter or not. */ + __IOM uint32_t RX_IIR_HP_MULT12_5 : 3; /*!< The fourth parameter of PDM RX IIR_HP filter stage 2 is (504 + + LP_I2S_RX_IIR_HP_MULT12_5[2:0]) */ + __IOM uint32_t RX_IIR_HP_MULT12_0 : 3; /*!< The fourth parameter of PDM RX IIR_HP filter stage 1 is (504 + + LP_I2S_RX_IIR_HP_MULT12_0[2:0]) */ + } bit; + } RX_PDM_CONF; + + union { + __IOM uint32_t reg; /*!< I2S ECO register */ + + struct { + __IOM uint32_t RDN_ECO_LOW : 32; /*!< logic low eco registers */ + } bit; + } ECO_LOW; + + union { + __IOM uint32_t reg; /*!< I2S ECO register */ + + struct { + __IOM uint32_t RDN_ECO_HIGH : 32; /*!< logic high eco registers */ + } bit; + } ECO_HIGH; + + union { + __IOM uint32_t reg; /*!< I2S ECO register */ + + struct { + __IOM uint32_t RDN_ENA : 1; /*!< enable rdn counter bit */ + __IM uint32_t RDN_RESULT : 1; /*!< rdn result */ + uint32_t : 30; + } bit; + } ECO_CONF; + + union { + __IOM uint32_t reg; /*!< I2S VAD Parameter register */ + + struct { + __IOM uint32_t PARAM_MIN_ENERGY : 16; /*!< VAD parameter */ + __IOM uint32_t PARAM_INIT_FRAME_NUM : 9; /*!< VAD parameter */ + uint32_t : 7; + } bit; + } VAD_PARAM0; + + union { + __IOM uint32_t reg; /*!< I2S VAD Parameter register */ + + struct { + __IOM uint32_t PARAM_MIN_SPEECH_COUNT : 4;/*!< VAD parameter */ + __IOM uint32_t PARAM_MAX_SPEECH_COUNT : 7;/*!< VAD parameter */ + __IOM uint32_t PARAM_HANGOVER_SPEECH : 5; /*!< VAD parameter */ + __IOM uint32_t PARAM_HANGOVER_SILENT : 8; /*!< VAD parameter */ + __IOM uint32_t PARAM_MAX_OFFSET : 7; /*!< VAD parameter */ + __IOM uint32_t PARAM_SKIP_BAND_ENERGY : 1;/*!< Set 1 to skip band energy check. */ + } bit; + } VAD_PARAM1; + + union { + __IOM uint32_t reg; /*!< I2S VAD Parameter register */ + + struct { + __IOM uint32_t PARAM_NOISE_AMP_DOWN : 16; /*!< VAD parameter */ + __IOM uint32_t PARAM_NOISE_AMP_UP : 16; /*!< VAD parameter */ + } bit; + } VAD_PARAM2; + + union { + __IOM uint32_t reg; /*!< I2S VAD Parameter register */ + + struct { + __IOM uint32_t PARAM_NOISE_SPE_UP0 : 16; /*!< VAD parameter */ + __IOM uint32_t PARAM_NOISE_SPE_UP1 : 16; /*!< VAD parameter */ + } bit; + } VAD_PARAM3; + + union { + __IOM uint32_t reg; /*!< I2S VAD Parameter register */ + + struct { + __IOM uint32_t PARAM_NOISE_SPE_DOWN : 16; /*!< VAD parameter */ + __IOM uint32_t PARAM_NOISE_MEAN_DOWN : 16;/*!< VAD parameter */ + } bit; + } VAD_PARAM4; + + union { + __IOM uint32_t reg; /*!< I2S VAD Parameter register */ + + struct { + __IOM uint32_t PARAM_NOISE_MEAN_UP0 : 16; /*!< VAD parameter */ + __IOM uint32_t PARAM_NOISE_MEAN_UP1 : 16; /*!< VAD parameter */ + } bit; + } VAD_PARAM5; + + union { + __IOM uint32_t reg; /*!< I2S VAD Parameter register */ + + struct { + __IOM uint32_t PARAM_NOISE_STD_FS_THSL : 16;/*!< Feature_sum threshold to determine noise_std max value when + vad_tag=1, equal to ((noise_std_max)>>11)^2*5 */ + __IOM uint32_t PARAM_NOISE_STD_FS_THSH : 16;/*!< Feature_sum threshold to determine noise_std max value when + vad_tag=0, equal to ((noise_std_max)>>11)^2*5 */ + } bit; + } VAD_PARAM6; + + union { + __IOM uint32_t reg; /*!< I2S VAD Parameter register */ + + struct { + __IOM uint32_t PARAM_THRES_UPD_BASE : 16; /*!< VAD parameter */ + __IOM uint32_t PARAM_THRES_UPD_VARY : 16; /*!< VAD parameter */ + } bit; + } VAD_PARAM7; + + union { + __IOM uint32_t reg; /*!< I2S VAD Parameter register */ + + struct { + __IOM uint32_t PARAM_THRES_UPD_BDL : 8; /*!< Noise_std boundary low when updating threshold. */ + __IOM uint32_t PARAM_THRES_UPD_BDH : 8; /*!< Noise_std boundary high when updating threshold. */ + __IOM uint32_t PARAM_FEATURE_BURST : 16; /*!< VAD parameter */ + } bit; + } VAD_PARAM8; + __IM uint32_t RESERVED6[3]; + + union { + __IOM uint32_t reg; /*!< I2S VAD Observe register */ + + struct { + __IM uint32_t SPEECH_COUNT_OB : 8; /*!< Reg silent count observe */ + __IM uint32_t SILENT_COUNT_OB : 8; /*!< Reg speech count observe */ + __IM uint32_t MAX_SIGNAL0_OB : 16; /*!< Reg max signal0 observe */ + } bit; + } VAD_OB0; + + union { + __IOM uint32_t reg; /*!< I2S VAD Observe register */ + + struct { + __IM uint32_t MAX_SIGNAL1_OB : 16; /*!< Reg max signal1 observe */ + __IM uint32_t MAX_SIGNAL2_OB : 16; /*!< Reg max signal2 observe */ + } bit; + } VAD_OB1; + + union { + __IOM uint32_t reg; /*!< I2S VAD Observe register */ + + struct { + __IM uint32_t NOISE_AMP_OB : 32; /*!< Reg noise_amp observe signal */ + } bit; + } VAD_OB2; + + union { + __IOM uint32_t reg; /*!< I2S VAD Observe register */ + + struct { + __IM uint32_t NOISE_MEAN_OB : 32; /*!< Reg noise_mean observe signal */ + } bit; + } VAD_OB3; + + union { + __IOM uint32_t reg; /*!< I2S VAD Observe register */ + + struct { + __IM uint32_t NOISE_STD_OB : 32; /*!< Reg noise_std observe signal */ + } bit; + } VAD_OB4; + + union { + __IOM uint32_t reg; /*!< I2S VAD Observe register */ + + struct { + __IM uint32_t OFFSET_OB : 32; /*!< Reg offset observe signal */ + } bit; + } VAD_OB5; + + union { + __IOM uint32_t reg; /*!< I2S VAD Observe register */ + + struct { + __IM uint32_t THRESHOLD_OB : 32; /*!< Reg threshold observe signal */ + } bit; + } VAD_OB6; + + union { + __IOM uint32_t reg; /*!< I2S VAD Observe register */ + + struct { + __IM uint32_t ENERGY_LOW_OB : 32; /*!< Reg energy bit 31~0 observe signal */ + } bit; + } VAD_OB7; + + union { + __IOM uint32_t reg; /*!< I2S VAD Observe register */ + + struct { + __IM uint32_t ENERGY_HIGH_OB : 32; /*!< Reg energy bit 63~32 observe signal */ + } bit; + } VAD_OB8; + __IM uint32_t RESERVED7[9]; + + union { + __IOM uint32_t reg; /*!< Clock gate register */ + + struct { + __IOM uint32_t CLK_EN : 1; /*!< set this bit to enable clock gate */ + __IOM uint32_t VAD_CG_FORCE_ON : 1; /*!< VAD clock gate force on register */ + __IOM uint32_t RX_MEM_CG_FORCE_ON : 1; /*!< I2S rx mem clock gate force on register */ + __IOM uint32_t RX_REG_CG_FORCE_ON : 1; /*!< I2S rx reg clock gate force on register */ + uint32_t : 28; + } bit; + } CLK_GATE; + + union { + __IOM uint32_t reg; /*!< Version control register */ + + struct { + __IOM uint32_t DATE : 28; /*!< I2S version control register */ + uint32_t : 4; + } bit; + } DATE; +} LP_I2S0_Type; /*!< Size = 256 (0x100) */ + + + +/* =========================================================================================================================== */ +/* ================ LP_IO_MUX ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Low-power Input/Output Multiplexer (LP_IO_MUX) + */ + +typedef struct { /*!< LP_IO_MUX Structure */ + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_CLK_EN : 1; /*!< Reserved */ + uint32_t : 31; + } bit; + } CLK_EN; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_VER_DATE : 28; /*!< Reserved */ + uint32_t : 4; + } bit; + } VER_DATE; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_PAD0_DRV : 2; /*!< Reserved */ + __IOM uint32_t REG_PAD0_RDE : 1; /*!< Reserved */ + __IOM uint32_t REG_PAD0_RUE : 1; /*!< Reserved */ + __IOM uint32_t REG_PAD0_MUX_SEL : 1; /*!< 1:use LP GPIO,0: use digital GPIO */ + __IOM uint32_t REG_PAD0_FUN_SEL : 2; /*!< function sel */ + __IOM uint32_t REG_PAD0_SLP_SEL : 1; /*!< 1: enable sleep mode during sleep,0: no sleep mode */ + __IOM uint32_t REG_PAD0_SLP_IE : 1; /*!< input enable in sleep mode */ + __IOM uint32_t REG_PAD0_SLP_OE : 1; /*!< output enable in sleep mode */ + __IOM uint32_t REG_PAD0_FUN_IE : 1; /*!< input enable in work mode */ + __IOM uint32_t REG_PAD0_FILTER_EN : 1; /*!< need des */ + uint32_t : 20; + } bit; + } PAD0; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_PAD1_DRV : 2; /*!< Reserved */ + __IOM uint32_t REG_PAD1_RDE : 1; /*!< Reserved */ + __IOM uint32_t REG_PAD1_RUE : 1; /*!< Reserved */ + __IOM uint32_t REG_PAD1_MUX_SEL : 1; /*!< 1:use LP GPIO,0: use digital GPIO */ + __IOM uint32_t REG_PAD1_FUN_SEL : 2; /*!< function sel */ + __IOM uint32_t REG_PAD1_SLP_SEL : 1; /*!< 1: enable sleep mode during sleep,0: no sleep mode */ + __IOM uint32_t REG_PAD1_SLP_IE : 1; /*!< input enable in sleep mode */ + __IOM uint32_t REG_PAD1_SLP_OE : 1; /*!< output enable in sleep mode */ + __IOM uint32_t REG_PAD1_FUN_IE : 1; /*!< input enable in work mode */ + __IOM uint32_t REG_PAD1_FILTER_EN : 1; /*!< need des */ + uint32_t : 20; + } bit; + } PAD1; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_PAD2_DRV : 2; /*!< Reserved */ + __IOM uint32_t REG_PAD2_RDE : 1; /*!< Reserved */ + __IOM uint32_t REG_PAD2_RUE : 1; /*!< Reserved */ + __IOM uint32_t REG_PAD2_MUX_SEL : 1; /*!< 1:use LP GPIO,0: use digital GPIO */ + __IOM uint32_t REG_PAD2_FUN_SEL : 2; /*!< function sel */ + __IOM uint32_t REG_PAD2_SLP_SEL : 1; /*!< 1: enable sleep mode during sleep,0: no sleep mode */ + __IOM uint32_t REG_PAD2_SLP_IE : 1; /*!< input enable in sleep mode */ + __IOM uint32_t REG_PAD2_SLP_OE : 1; /*!< output enable in sleep mode */ + __IOM uint32_t REG_PAD2_FUN_IE : 1; /*!< input enable in work mode */ + __IOM uint32_t REG_PAD2_FILTER_EN : 1; /*!< need des */ + uint32_t : 20; + } bit; + } PAD2; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_PAD3_DRV : 2; /*!< Reserved */ + __IOM uint32_t REG_PAD3_RDE : 1; /*!< Reserved */ + __IOM uint32_t REG_PAD3_RUE : 1; /*!< Reserved */ + __IOM uint32_t REG_PAD3_MUX_SEL : 1; /*!< 1:use LP GPIO,0: use digital GPIO */ + __IOM uint32_t REG_PAD3_FUN_SEL : 2; /*!< function sel */ + __IOM uint32_t REG_PAD3_SLP_SEL : 1; /*!< 1: enable sleep mode during sleep,0: no sleep mode */ + __IOM uint32_t REG_PAD3_SLP_IE : 1; /*!< input enable in sleep mode */ + __IOM uint32_t REG_PAD3_SLP_OE : 1; /*!< output enable in sleep mode */ + __IOM uint32_t REG_PAD3_FUN_IE : 1; /*!< input enable in work mode */ + __IOM uint32_t REG_PAD3_FILTER_EN : 1; /*!< need des */ + uint32_t : 20; + } bit; + } PAD3; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_PAD4_DRV : 2; /*!< Reserved */ + __IOM uint32_t REG_PAD4_RDE : 1; /*!< Reserved */ + __IOM uint32_t REG_PAD4_RUE : 1; /*!< Reserved */ + __IOM uint32_t REG_PAD4_MUX_SEL : 1; /*!< 1:use LP GPIO,0: use digital GPIO */ + __IOM uint32_t REG_PAD4_FUN_SEL : 2; /*!< function sel */ + __IOM uint32_t REG_PAD4_SLP_SEL : 1; /*!< 1: enable sleep mode during sleep,0: no sleep mode */ + __IOM uint32_t REG_PAD4_SLP_IE : 1; /*!< input enable in sleep mode */ + __IOM uint32_t REG_PAD4_SLP_OE : 1; /*!< output enable in sleep mode */ + __IOM uint32_t REG_PAD4_FUN_IE : 1; /*!< input enable in work mode */ + __IOM uint32_t REG_PAD4_FILTER_EN : 1; /*!< need des */ + uint32_t : 20; + } bit; + } PAD4; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_PAD5_DRV : 2; /*!< Reserved */ + __IOM uint32_t REG_PAD5_RDE : 1; /*!< Reserved */ + __IOM uint32_t REG_PAD5_RUE : 1; /*!< Reserved */ + __IOM uint32_t REG_PAD5_MUX_SEL : 1; /*!< 1:use LP GPIO,0: use digital GPIO */ + __IOM uint32_t REG_PAD5_FUN_SEL : 2; /*!< function sel */ + __IOM uint32_t REG_PAD5_SLP_SEL : 1; /*!< 1: enable sleep mode during sleep,0: no sleep mode */ + __IOM uint32_t REG_PAD5_SLP_IE : 1; /*!< input enable in sleep mode */ + __IOM uint32_t REG_PAD5_SLP_OE : 1; /*!< output enable in sleep mode */ + __IOM uint32_t REG_PAD5_FUN_IE : 1; /*!< input enable in work mode */ + __IOM uint32_t REG_PAD5_FILTER_EN : 1; /*!< need des */ + uint32_t : 20; + } bit; + } PAD5; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_PAD6_DRV : 2; /*!< Reserved */ + __IOM uint32_t REG_PAD6_RDE : 1; /*!< Reserved */ + __IOM uint32_t REG_PAD6_RUE : 1; /*!< Reserved */ + __IOM uint32_t REG_PAD6_MUX_SEL : 1; /*!< 1:use LP GPIO,0: use digital GPIO */ + __IOM uint32_t REG_PAD6_FUN_SEL : 2; /*!< function sel */ + __IOM uint32_t REG_PAD6_SLP_SEL : 1; /*!< 1: enable sleep mode during sleep,0: no sleep mode */ + __IOM uint32_t REG_PAD6_SLP_IE : 1; /*!< input enable in sleep mode */ + __IOM uint32_t REG_PAD6_SLP_OE : 1; /*!< output enable in sleep mode */ + __IOM uint32_t REG_PAD6_FUN_IE : 1; /*!< input enable in work mode */ + __IOM uint32_t REG_PAD6_FILTER_EN : 1; /*!< need des */ + uint32_t : 20; + } bit; + } PAD6; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_PAD7_DRV : 2; /*!< Reserved */ + __IOM uint32_t REG_PAD7_RDE : 1; /*!< Reserved */ + __IOM uint32_t REG_PAD7_RUE : 1; /*!< Reserved */ + __IOM uint32_t REG_PAD7_MUX_SEL : 1; /*!< 1:use LP GPIO,0: use digital GPIO */ + __IOM uint32_t REG_PAD7_FUN_SEL : 2; /*!< function sel */ + __IOM uint32_t REG_PAD7_SLP_SEL : 1; /*!< 1: enable sleep mode during sleep,0: no sleep mode */ + __IOM uint32_t REG_PAD7_SLP_IE : 1; /*!< input enable in sleep mode */ + __IOM uint32_t REG_PAD7_SLP_OE : 1; /*!< output enable in sleep mode */ + __IOM uint32_t REG_PAD7_FUN_IE : 1; /*!< input enable in work mode */ + __IOM uint32_t REG_PAD7_FILTER_EN : 1; /*!< need des */ + uint32_t : 20; + } bit; + } PAD7; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_PAD8_DRV : 2; /*!< Reserved */ + __IOM uint32_t REG_PAD8_RDE : 1; /*!< Reserved */ + __IOM uint32_t REG_PAD8_RUE : 1; /*!< Reserved */ + __IOM uint32_t REG_PAD8_MUX_SEL : 1; /*!< 1:use LP GPIO,0: use digital GPIO */ + __IOM uint32_t REG_PAD8_FUN_SEL : 2; /*!< function sel */ + __IOM uint32_t REG_PAD8_SLP_SEL : 1; /*!< 1: enable sleep mode during sleep,0: no sleep mode */ + __IOM uint32_t REG_PAD8_SLP_IE : 1; /*!< input enable in sleep mode */ + __IOM uint32_t REG_PAD8_SLP_OE : 1; /*!< output enable in sleep mode */ + __IOM uint32_t REG_PAD8_FUN_IE : 1; /*!< input enable in work mode */ + __IOM uint32_t REG_PAD8_FILTER_EN : 1; /*!< need des */ + uint32_t : 20; + } bit; + } PAD8; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_PAD9_DRV : 2; /*!< Reserved */ + __IOM uint32_t REG_PAD9_RDE : 1; /*!< Reserved */ + __IOM uint32_t REG_PAD9_RUE : 1; /*!< Reserved */ + __IOM uint32_t REG_PAD9_MUX_SEL : 1; /*!< 1:use LP GPIO,0: use digital GPIO */ + __IOM uint32_t REG_PAD9_FUN_SEL : 2; /*!< function sel */ + __IOM uint32_t REG_PAD9_SLP_SEL : 1; /*!< 1: enable sleep mode during sleep,0: no sleep mode */ + __IOM uint32_t REG_PAD9_SLP_IE : 1; /*!< input enable in sleep mode */ + __IOM uint32_t REG_PAD9_SLP_OE : 1; /*!< output enable in sleep mode */ + __IOM uint32_t REG_PAD9_FUN_IE : 1; /*!< input enable in work mode */ + __IOM uint32_t REG_PAD9_FILTER_EN : 1; /*!< need des */ + uint32_t : 20; + } bit; + } PAD9; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_PAD10_DRV : 2; /*!< Reserved */ + __IOM uint32_t REG_PAD10_RDE : 1; /*!< Reserved */ + __IOM uint32_t REG_PAD10_RUE : 1; /*!< Reserved */ + __IOM uint32_t REG_PAD10_MUX_SEL : 1; /*!< 1:use LP GPIO,0: use digital GPIO */ + __IOM uint32_t REG_PAD10_FUN_SEL : 2; /*!< function sel */ + __IOM uint32_t REG_PAD10_SLP_SEL : 1; /*!< 1: enable sleep mode during sleep,0: no sleep mode */ + __IOM uint32_t REG_PAD10_SLP_IE : 1; /*!< input enable in sleep mode */ + __IOM uint32_t REG_PAD10_SLP_OE : 1; /*!< output enable in sleep mode */ + __IOM uint32_t REG_PAD10_FUN_IE : 1; /*!< input enable in work mode */ + __IOM uint32_t REG_PAD10_FILTER_EN : 1; /*!< need des */ + uint32_t : 20; + } bit; + } PAD10; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_PAD11_DRV : 2; /*!< Reserved */ + __IOM uint32_t REG_PAD11_RDE : 1; /*!< Reserved */ + __IOM uint32_t REG_PAD11_RUE : 1; /*!< Reserved */ + __IOM uint32_t REG_PAD11_MUX_SEL : 1; /*!< 1:use LP GPIO,0: use digital GPIO */ + __IOM uint32_t REG_PAD11_FUN_SEL : 2; /*!< function sel */ + __IOM uint32_t REG_PAD11_SLP_SEL : 1; /*!< 1: enable sleep mode during sleep,0: no sleep mode */ + __IOM uint32_t REG_PAD11_SLP_IE : 1; /*!< input enable in sleep mode */ + __IOM uint32_t REG_PAD11_SLP_OE : 1; /*!< output enable in sleep mode */ + __IOM uint32_t REG_PAD11_FUN_IE : 1; /*!< input enable in work mode */ + __IOM uint32_t REG_PAD11_FILTER_EN : 1; /*!< need des */ + uint32_t : 20; + } bit; + } PAD11; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_PAD12_DRV : 2; /*!< Reserved */ + __IOM uint32_t REG_PAD12_RDE : 1; /*!< Reserved */ + __IOM uint32_t REG_PAD12_RUE : 1; /*!< Reserved */ + __IOM uint32_t REG_PAD12_MUX_SEL : 1; /*!< 1:use LP GPIO,0: use digital GPIO */ + __IOM uint32_t REG_PAD12_FUN_SEL : 2; /*!< function sel */ + __IOM uint32_t REG_PAD12_SLP_SEL : 1; /*!< 1: enable sleep mode during sleep,0: no sleep mode */ + __IOM uint32_t REG_PAD12_SLP_IE : 1; /*!< input enable in sleep mode */ + __IOM uint32_t REG_PAD12_SLP_OE : 1; /*!< output enable in sleep mode */ + __IOM uint32_t REG_PAD12_FUN_IE : 1; /*!< input enable in work mode */ + __IOM uint32_t REG_PAD12_FILTER_EN : 1; /*!< need des */ + uint32_t : 20; + } bit; + } PAD120; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_PAD13_DRV : 2; /*!< Reserved */ + __IOM uint32_t REG_PAD13_RDE : 1; /*!< Reserved */ + __IOM uint32_t REG_PAD13_RUE : 1; /*!< Reserved */ + __IOM uint32_t REG_PAD13_MUX_SEL : 1; /*!< 1:use LP GPIO,0: use digital GPIO */ + __IOM uint32_t REG_PAD13_FUN_SEL : 2; /*!< function sel */ + __IOM uint32_t REG_PAD13_SLP_SEL : 1; /*!< 1: enable sleep mode during sleep,0: no sleep mode */ + __IOM uint32_t REG_PAD13_SLP_IE : 1; /*!< input enable in sleep mode */ + __IOM uint32_t REG_PAD13_SLP_OE : 1; /*!< output enable in sleep mode */ + __IOM uint32_t REG_PAD13_FUN_IE : 1; /*!< input enable in work mode */ + __IOM uint32_t REG_PAD13_FILTER_EN : 1; /*!< need des */ + uint32_t : 20; + } bit; + } PAD13; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_PAD14_DRV : 2; /*!< Reserved */ + __IOM uint32_t REG_PAD14_RDE : 1; /*!< Reserved */ + __IOM uint32_t REG_PAD14_RUE : 1; /*!< Reserved */ + __IOM uint32_t REG_PAD14_MUX_SEL : 1; /*!< 1:use LP GPIO,0: use digital GPIO */ + __IOM uint32_t REG_PAD14_FUN_SEL : 2; /*!< function sel */ + __IOM uint32_t REG_PAD14_SLP_SEL : 1; /*!< 1: enable sleep mode during sleep,0: no sleep mode */ + __IOM uint32_t REG_PAD14_SLP_IE : 1; /*!< input enable in sleep mode */ + __IOM uint32_t REG_PAD14_SLP_OE : 1; /*!< output enable in sleep mode */ + __IOM uint32_t REG_PAD14_FUN_IE : 1; /*!< input enable in work mode */ + __IOM uint32_t REG_PAD14_FILTER_EN : 1; /*!< need des */ + uint32_t : 20; + } bit; + } PAD14; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_PAD15_DRV : 2; /*!< Reserved */ + __IOM uint32_t REG_PAD15_RDE : 1; /*!< Reserved */ + __IOM uint32_t REG_PAD15_RUE : 1; /*!< Reserved */ + __IOM uint32_t REG_PAD15_MUX_SEL : 1; /*!< 1:use LP GPIO,0: use digital GPIO */ + __IOM uint32_t REG_PAD15_FUN_SEL : 2; /*!< function sel */ + __IOM uint32_t REG_PAD15_SLP_SEL : 1; /*!< 1: enable sleep mode during sleep,0: no sleep mode */ + __IOM uint32_t REG_PAD15_SLP_IE : 1; /*!< input enable in sleep mode */ + __IOM uint32_t REG_PAD15_SLP_OE : 1; /*!< output enable in sleep mode */ + __IOM uint32_t REG_PAD15_FUN_IE : 1; /*!< input enable in work mode */ + __IOM uint32_t REG_PAD15_FILTER_EN : 1; /*!< need des */ + uint32_t : 20; + } bit; + } PAD15; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_XTL_EXT_CTR_SEL : 5; /*!< select LP GPIO 0 ~ 15 to control XTAL */ + __IOM uint32_t REG_EXT_WAKEUP0_SEL : 5; /*!< Reserved */ + uint32_t : 22; + } bit; + } EXT_WAKEUP0_SEL; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_LP_GPIO_HOLD : 16; /*!< Reserved */ + uint32_t : 16; + } bit; + } LP_PAD_HOLD; + + union { + __IOM uint32_t reg; /*!< Reserved */ + + struct { + __IOM uint32_t REG_LP_GPIO_HYS : 16; /*!< Reserved */ + uint32_t : 16; + } bit; + } LP_PAD_HYS; +} LP_IO_MUX_Type; /*!< Size = 84 (0x54) */ + + + +/* =========================================================================================================================== */ +/* ================ LP_UART ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Low-power UART (Universal Asynchronous Receiver-Transmitter) Controller (LP_UART) + */ + +typedef struct { /*!< LP_UART Structure */ + + union { + __IOM uint32_t reg; /*!< FIFO data register */ + + struct { + __IM uint32_t RXFIFO_RD_BYTE : 8; /*!< UART 0 accesses FIFO via this register. */ + uint32_t : 24; + } bit; + } FIFO; + + union { + __IOM uint32_t reg; /*!< Raw interrupt status */ + + struct { + __IOM uint32_t RXFIFO_FULL_INT_RAW : 1; /*!< This interrupt raw bit turns to high level when receiver receives + more data than what rxfifo_full_thrhd specifies. */ + __IOM uint32_t TXFIFO_EMPTY_INT_RAW : 1; /*!< This interrupt raw bit turns to high level when the amount of + data in Tx-FIFO is less than what txfifo_empty_thrhd specifies + . */ + __IOM uint32_t PARITY_ERR_INT_RAW : 1; /*!< This interrupt raw bit turns to high level when receiver detects + a parity error in the data. */ + __IOM uint32_t FRM_ERR_INT_RAW : 1; /*!< This interrupt raw bit turns to high level when receiver detects + a data frame error . */ + __IOM uint32_t RXFIFO_OVF_INT_RAW : 1; /*!< This interrupt raw bit turns to high level when receiver receives + more data than the FIFO can store. */ + __IOM uint32_t DSR_CHG_INT_RAW : 1; /*!< This interrupt raw bit turns to high level when receiver detects + the edge change of DSRn signal. */ + __IOM uint32_t CTS_CHG_INT_RAW : 1; /*!< This interrupt raw bit turns to high level when receiver detects + the edge change of CTSn signal. */ + __IOM uint32_t BRK_DET_INT_RAW : 1; /*!< This interrupt raw bit turns to high level when receiver detects + a 0 after the stop bit. */ + __IOM uint32_t RXFIFO_TOUT_INT_RAW : 1; /*!< This interrupt raw bit turns to high level when receiver takes + more time than rx_tout_thrhd to receive a byte. */ + __IOM uint32_t SW_XON_INT_RAW : 1; /*!< This interrupt raw bit turns to high level when receiver recevies + Xon char when uart_sw_flow_con_en is set to 1. */ + __IOM uint32_t SW_XOFF_INT_RAW : 1; /*!< This interrupt raw bit turns to high level when receiver receives + Xoff char when uart_sw_flow_con_en is set to 1. */ + __IOM uint32_t GLITCH_DET_INT_RAW : 1; /*!< This interrupt raw bit turns to high level when receiver detects + a glitch in the middle of a start bit. */ + __IOM uint32_t TX_BRK_DONE_INT_RAW : 1; /*!< This interrupt raw bit turns to high level when transmitter + completes sending NULL characters after all data in Tx-FIFO + are sent. */ + __IOM uint32_t TX_BRK_IDLE_DONE_INT_RAW : 1;/*!< This interrupt raw bit turns to high level when transmitter + has kept the shortest duration after sending the last data. */ + __IOM uint32_t TX_DONE_INT_RAW : 1; /*!< This interrupt raw bit turns to high level when transmitter + has send out all data in FIFO. */ + uint32_t : 3; + __IOM uint32_t AT_CMD_CHAR_DET_INT_RAW : 1;/*!< This interrupt raw bit turns to high level when receiver detects + the configured at_cmd char. */ + __IOM uint32_t WAKEUP_INT_RAW : 1; /*!< This interrupt raw bit turns to high level when input rxd edge + changes more times than what reg_active_threshold specifies + in light sleeping mode. */ + uint32_t : 12; + } bit; + } INT_RAW; + + union { + __IOM uint32_t reg; /*!< Masked interrupt status */ + + struct { + __IM uint32_t RXFIFO_FULL_INT_ST : 1; /*!< This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena + is set to 1. */ + __IM uint32_t TXFIFO_EMPTY_INT_ST : 1; /*!< This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena + is set to 1. */ + __IM uint32_t PARITY_ERR_INT_ST : 1; /*!< This is the status bit for parity_err_int_raw when parity_err_int_ena + is set to 1. */ + __IM uint32_t FRM_ERR_INT_ST : 1; /*!< This is the status bit for frm_err_int_raw when frm_err_int_ena + is set to 1. */ + __IM uint32_t RXFIFO_OVF_INT_ST : 1; /*!< This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena + is set to 1. */ + __IM uint32_t DSR_CHG_INT_ST : 1; /*!< This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena + is set to 1. */ + __IM uint32_t CTS_CHG_INT_ST : 1; /*!< This is the status bit for cts_chg_int_raw when cts_chg_int_ena + is set to 1. */ + __IM uint32_t BRK_DET_INT_ST : 1; /*!< This is the status bit for brk_det_int_raw when brk_det_int_ena + is set to 1. */ + __IM uint32_t RXFIFO_TOUT_INT_ST : 1; /*!< This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena + is set to 1. */ + __IM uint32_t SW_XON_INT_ST : 1; /*!< This is the status bit for sw_xon_int_raw when sw_xon_int_ena + is set to 1. */ + __IM uint32_t SW_XOFF_INT_ST : 1; /*!< This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena + is set to 1. */ + __IM uint32_t GLITCH_DET_INT_ST : 1; /*!< This is the status bit for glitch_det_int_raw when glitch_det_int_ena + is set to 1. */ + __IM uint32_t TX_BRK_DONE_INT_ST : 1; /*!< This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena + is set to 1. */ + __IM uint32_t TX_BRK_IDLE_DONE_INT_ST : 1;/*!< This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ + na is set to 1. */ + __IM uint32_t TX_DONE_INT_ST : 1; /*!< This is the status bit for tx_done_int_raw when tx_done_int_ena + is set to 1. */ + uint32_t : 3; + __IM uint32_t AT_CMD_CHAR_DET_INT_ST : 1;/*!< This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena + is set to 1. */ + __IM uint32_t WAKEUP_INT_ST : 1; /*!< This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena + is set to 1. */ + uint32_t : 12; + } bit; + } INT_ST; + + union { + __IOM uint32_t reg; /*!< Interrupt enable bits */ + + struct { + __IOM uint32_t RXFIFO_FULL_INT_ENA : 1; /*!< This is the enable bit for rxfifo_full_int_st register. */ + __IOM uint32_t TXFIFO_EMPTY_INT_ENA : 1; /*!< This is the enable bit for txfifo_empty_int_st register. */ + __IOM uint32_t PARITY_ERR_INT_ENA : 1; /*!< This is the enable bit for parity_err_int_st register. */ + __IOM uint32_t FRM_ERR_INT_ENA : 1; /*!< This is the enable bit for frm_err_int_st register. */ + __IOM uint32_t RXFIFO_OVF_INT_ENA : 1; /*!< This is the enable bit for rxfifo_ovf_int_st register. */ + __IOM uint32_t DSR_CHG_INT_ENA : 1; /*!< This is the enable bit for dsr_chg_int_st register. */ + __IOM uint32_t CTS_CHG_INT_ENA : 1; /*!< This is the enable bit for cts_chg_int_st register. */ + __IOM uint32_t BRK_DET_INT_ENA : 1; /*!< This is the enable bit for brk_det_int_st register. */ + __IOM uint32_t RXFIFO_TOUT_INT_ENA : 1; /*!< This is the enable bit for rxfifo_tout_int_st register. */ + __IOM uint32_t SW_XON_INT_ENA : 1; /*!< This is the enable bit for sw_xon_int_st register. */ + __IOM uint32_t SW_XOFF_INT_ENA : 1; /*!< This is the enable bit for sw_xoff_int_st register. */ + __IOM uint32_t GLITCH_DET_INT_ENA : 1; /*!< This is the enable bit for glitch_det_int_st register. */ + __IOM uint32_t TX_BRK_DONE_INT_ENA : 1; /*!< This is the enable bit for tx_brk_done_int_st register. */ + __IOM uint32_t TX_BRK_IDLE_DONE_INT_ENA : 1;/*!< This is the enable bit for tx_brk_idle_done_int_st register. */ + __IOM uint32_t TX_DONE_INT_ENA : 1; /*!< This is the enable bit for tx_done_int_st register. */ + uint32_t : 3; + __IOM uint32_t AT_CMD_CHAR_DET_INT_ENA : 1;/*!< This is the enable bit for at_cmd_char_det_int_st register. */ + __IOM uint32_t WAKEUP_INT_ENA : 1; /*!< This is the enable bit for uart_wakeup_int_st register. */ + uint32_t : 12; + } bit; + } INT_ENA; + + union { + __IOM uint32_t reg; /*!< Interrupt clear bits */ + + struct { + __OM uint32_t RXFIFO_FULL_INT_CLR : 1; /*!< Set this bit to clear the rxfifo_full_int_raw interrupt. */ + __OM uint32_t TXFIFO_EMPTY_INT_CLR : 1; /*!< Set this bit to clear txfifo_empty_int_raw interrupt. */ + __OM uint32_t PARITY_ERR_INT_CLR : 1; /*!< Set this bit to clear parity_err_int_raw interrupt. */ + __OM uint32_t FRM_ERR_INT_CLR : 1; /*!< Set this bit to clear frm_err_int_raw interrupt. */ + __OM uint32_t RXFIFO_OVF_INT_CLR : 1; /*!< Set this bit to clear rxfifo_ovf_int_raw interrupt. */ + __OM uint32_t DSR_CHG_INT_CLR : 1; /*!< Set this bit to clear the dsr_chg_int_raw interrupt. */ + __OM uint32_t CTS_CHG_INT_CLR : 1; /*!< Set this bit to clear the cts_chg_int_raw interrupt. */ + __OM uint32_t BRK_DET_INT_CLR : 1; /*!< Set this bit to clear the brk_det_int_raw interrupt. */ + __OM uint32_t RXFIFO_TOUT_INT_CLR : 1; /*!< Set this bit to clear the rxfifo_tout_int_raw interrupt. */ + __OM uint32_t SW_XON_INT_CLR : 1; /*!< Set this bit to clear the sw_xon_int_raw interrupt. */ + __OM uint32_t SW_XOFF_INT_CLR : 1; /*!< Set this bit to clear the sw_xoff_int_raw interrupt. */ + __OM uint32_t GLITCH_DET_INT_CLR : 1; /*!< Set this bit to clear the glitch_det_int_raw interrupt. */ + __OM uint32_t TX_BRK_DONE_INT_CLR : 1; /*!< Set this bit to clear the tx_brk_done_int_raw interrupt.. */ + __OM uint32_t TX_BRK_IDLE_DONE_INT_CLR : 1;/*!< Set this bit to clear the tx_brk_idle_done_int_raw interrupt. */ + __OM uint32_t TX_DONE_INT_CLR : 1; /*!< Set this bit to clear the tx_done_int_raw interrupt. */ + uint32_t : 3; + __OM uint32_t AT_CMD_CHAR_DET_INT_CLR : 1;/*!< Set this bit to clear the at_cmd_char_det_int_raw interrupt. */ + __OM uint32_t WAKEUP_INT_CLR : 1; /*!< Set this bit to clear the uart_wakeup_int_raw interrupt. */ + uint32_t : 12; + } bit; + } INT_CLR; + + union { + __IOM uint32_t reg; /*!< Clock divider configuration */ + + struct { + __IOM uint32_t CLKDIV : 12; /*!< The integral part of the frequency divider factor. */ + uint32_t : 8; + __IOM uint32_t CLKDIV_FRAG : 4; /*!< The decimal part of the frequency divider factor. */ + uint32_t : 8; + } bit; + } CLKDIV_SYNC; + + union { + __IOM uint32_t reg; /*!< Rx Filter configuration */ + + struct { + __IOM uint32_t GLITCH_FILT : 8; /*!< when input pulse width is lower than this value the pulse is + ignored. */ + __IOM uint32_t GLITCH_FILT_EN : 1; /*!< Set this bit to enable Rx signal filter. */ + uint32_t : 23; + } bit; + } RX_FILT; + + union { + __IOM uint32_t reg; /*!< UART status register */ + + struct { + uint32_t : 3; + __IM uint32_t RXFIFO_CNT : 5; /*!< Stores the byte number of valid data in Rx-FIFO. */ + uint32_t : 5; + __IM uint32_t DSRN : 1; /*!< The register represent the level value of the internal uart + dsr signal. */ + __IM uint32_t CTSN : 1; /*!< This register represent the level value of the internal uart + cts signal. */ + __IM uint32_t RXD : 1; /*!< This register represent the level value of the internal uart + rxd signal. */ + uint32_t : 3; + __IM uint32_t TXFIFO_CNT : 5; /*!< Stores the byte number of data in Tx-FIFO. */ + uint32_t : 5; + __IM uint32_t DTRN : 1; /*!< This bit represents the level of the internal uart dtr signal. */ + __IM uint32_t RTSN : 1; /*!< This bit represents the level of the internal uart rts signal. */ + __IM uint32_t TXD : 1; /*!< This bit represents the level of the internal uart txd signal. */ + } bit; + } STATUS; + + union { + __IOM uint32_t reg; /*!< Configuration register 0 */ + + struct { + __IOM uint32_t PARITY : 1; /*!< This register is used to configure the parity check mode. */ + __IOM uint32_t PARITY_EN : 1; /*!< Set this bit to enable uart parity check. */ + __IOM uint32_t BIT_NUM : 2; /*!< This register is used to set the length of data. */ + __IOM uint32_t STOP_BIT_NUM : 2; /*!< This register is used to set the length of stop bit. */ + __IOM uint32_t TXD_BRK : 1; /*!< Set this bit to enbale transmitter to send NULL when the process + of sending data is done. */ + uint32_t : 5; + __IOM uint32_t LOOPBACK : 1; /*!< Set this bit to enable uart loopback test mode. */ + __IOM uint32_t TX_FLOW_EN : 1; /*!< Set this bit to enable flow control function for transmitter. */ + uint32_t : 1; + __IOM uint32_t RXD_INV : 1; /*!< Set this bit to inverse the level value of uart rxd signal. */ + __IOM uint32_t TXD_INV : 1; /*!< Set this bit to inverse the level value of uart txd signal. */ + __IOM uint32_t DIS_RX_DAT_OVF : 1; /*!< Disable UART Rx data overflow detect. */ + __IOM uint32_t ERR_WR_MASK : 1; /*!< 1'h1: Receiver stops storing data into FIFO when data is wrong. + 1'h0: Receiver stores the data even if the received data + is wrong. */ + uint32_t : 1; + __IOM uint32_t MEM_CLK_EN : 1; /*!< UART memory clock gate enable signal. */ + __IOM uint32_t SW_RTS : 1; /*!< This register is used to configure the software rts signal which + is used in software flow control. */ + __IOM uint32_t RXFIFO_RST : 1; /*!< Set this bit to reset the uart receive-FIFO. */ + __IOM uint32_t TXFIFO_RST : 1; /*!< Set this bit to reset the uart transmit-FIFO. */ + uint32_t : 8; + } bit; + } CONF0_SYNC; + + union { + __IOM uint32_t reg; /*!< Configuration register 1 */ + + struct { + uint32_t : 3; + __IOM uint32_t RXFIFO_FULL_THRHD : 5; /*!< It will produce rxfifo_full_int interrupt when receiver receives + more data than this register value. */ + uint32_t : 3; + __IOM uint32_t TXFIFO_EMPTY_THRHD : 5; /*!< It will produce txfifo_empty_int interrupt when the data amount + in Tx-FIFO is less than this register value. */ + __IOM uint32_t CTS_INV : 1; /*!< Set this bit to inverse the level value of uart cts signal. */ + __IOM uint32_t DSR_INV : 1; /*!< Set this bit to inverse the level value of uart dsr signal. */ + __IOM uint32_t RTS_INV : 1; /*!< Set this bit to inverse the level value of uart rts signal. */ + __IOM uint32_t DTR_INV : 1; /*!< Set this bit to inverse the level value of uart dtr signal. */ + __IOM uint32_t SW_DTR : 1; /*!< This register is used to configure the software dtr signal which + is used in software flow control. */ + __IOM uint32_t CLK_EN : 1; /*!< 1'h1: Force clock on for register. 1'h0: Support clock only + when application writes registers. */ + uint32_t : 10; + } bit; + } CONF1; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t reg; /*!< Hardware flow-control configuration */ + + struct { + uint32_t : 3; + __IOM uint32_t RX_FLOW_THRHD : 5; /*!< This register is used to configure the maximum amount of data + that can be received when hardware flow control works. */ + __IOM uint32_t RX_FLOW_EN : 1; /*!< This is the flow enable bit for UART receiver. */ + uint32_t : 23; + } bit; + } HWFC_CONF_SYNC; + + union { + __IOM uint32_t reg; /*!< UART sleep configure register 0 */ + + struct { + __IOM uint32_t WK_CHAR1 : 8; /*!< This register restores the specified wake up char1 to wake up */ + __IOM uint32_t WK_CHAR2 : 8; /*!< This register restores the specified wake up char2 to wake up */ + __IOM uint32_t WK_CHAR3 : 8; /*!< This register restores the specified wake up char3 to wake up */ + __IOM uint32_t WK_CHAR4 : 8; /*!< This register restores the specified wake up char4 to wake up */ + } bit; + } SLEEP_CONF0; + + union { + __IOM uint32_t reg; /*!< UART sleep configure register 1 */ + + struct { + __IOM uint32_t WK_CHAR0 : 8; /*!< This register restores the specified char0 to wake up */ + uint32_t : 24; + } bit; + } SLEEP_CONF1; + + union { + __IOM uint32_t reg; /*!< UART sleep configure register 2 */ + + struct { + __IOM uint32_t ACTIVE_THRESHOLD : 10; /*!< The uart is activated from light sleeping mode when the input + rxd edge changes more times than this register value. */ + uint32_t : 3; + __IOM uint32_t RX_WAKE_UP_THRHD : 5; /*!< In wake up mode 1 this field is used to set the received data + number threshold to wake up chip. */ + __IOM uint32_t WK_CHAR_NUM : 3; /*!< This register is used to select number of wake up char. */ + __IOM uint32_t WK_CHAR_MASK : 5; /*!< This register is used to mask wake up char. */ + __IOM uint32_t WK_MODE_SEL : 2; /*!< This register is used to select wake up mode. 0: RXD toggling + to wake up. 1: received data number larger than */ + uint32_t : 4; + } bit; + } SLEEP_CONF2; + + union { + __IOM uint32_t reg; /*!< Software flow-control character configuration */ + + struct { + __IOM uint32_t XON_CHAR : 8; /*!< This register stores the Xon flow control char. */ + __IOM uint32_t XOFF_CHAR : 8; /*!< This register stores the Xoff flow control char. */ + __IOM uint32_t XON_XOFF_STILL_SEND : 1; /*!< In software flow control mode, UART Tx is disabled once UART + Rx receives XOFF. In this status, UART Tx can not transmit + XOFF even the received data number is larger than UART_XOFF_THRESHOLD. + Set this bit to enable UART Tx can transmit XON/XOFF when + UART Tx is disabled. */ + __IOM uint32_t SW_FLOW_CON_EN : 1; /*!< Set this bit to enable software flow control. It is used with + register sw_xon or sw_xoff. */ + __IOM uint32_t XONOFF_DEL : 1; /*!< Set this bit to remove flow control char from the received data. */ + __IOM uint32_t FORCE_XON : 1; /*!< Set this bit to enable the transmitter to go on sending data. */ + __IOM uint32_t FORCE_XOFF : 1; /*!< Set this bit to stop the transmitter from sending data. */ + __IOM uint32_t SEND_XON : 1; /*!< Set this bit to send Xon char. It is cleared by hardware automatically. */ + __IOM uint32_t SEND_XOFF : 1; /*!< Set this bit to send Xoff char. It is cleared by hardware automatically. */ + uint32_t : 9; + } bit; + } SWFC_CONF0_SYNC; + + union { + __IOM uint32_t reg; /*!< Software flow-control character configuration */ + + struct { + uint32_t : 3; + __IOM uint32_t XON_THRESHOLD : 5; /*!< When the data amount in Rx-FIFO is less than this register value + with uart_sw_flow_con_en set to 1 it will send a Xon char. */ + uint32_t : 3; + __IOM uint32_t XOFF_THRESHOLD : 5; /*!< When the data amount in Rx-FIFO is more than this register value + with uart_sw_flow_con_en set to 1 it will send a Xoff char. */ + uint32_t : 16; + } bit; + } SWFC_CONF1; + + union { + __IOM uint32_t reg; /*!< Tx Break character configuration */ + + struct { + __IOM uint32_t TX_BRK_NUM : 8; /*!< This register is used to configure the number of 0 to be sent + after the process of sending data is done. It is active + when txd_brk is set to 1. */ + uint32_t : 24; + } bit; + } TXBRK_CONF_SYNC; + + union { + __IOM uint32_t reg; /*!< Frame-end idle configuration */ + + struct { + __IOM uint32_t RX_IDLE_THRHD : 10; /*!< It will produce frame end signal when receiver takes more time + to receive one byte data than this register value. */ + __IOM uint32_t TX_IDLE_NUM : 10; /*!< This register is used to configure the duration time between + transfers. */ + uint32_t : 12; + } bit; + } IDLE_CONF_SYNC; + + union { + __IOM uint32_t reg; /*!< RS485 mode configuration */ + + struct { + uint32_t : 1; + __IOM uint32_t DL0_EN : 1; /*!< Set this bit to delay the stop bit by 1 bit. */ + __IOM uint32_t DL1_EN : 1; /*!< Set this bit to delay the stop bit by 1 bit. */ + uint32_t : 29; + } bit; + } RS485_CONF_SYNC; + + union { + __IOM uint32_t reg; /*!< Pre-sequence timing configuration */ + + struct { + __IOM uint32_t PRE_IDLE_NUM : 16; /*!< This register is used to configure the idle duration time before + the first at_cmd is received by receiver. */ + uint32_t : 16; + } bit; + } AT_CMD_PRECNT_SYNC; + + union { + __IOM uint32_t reg; /*!< Post-sequence timing configuration */ + + struct { + __IOM uint32_t POST_IDLE_NUM : 16; /*!< This register is used to configure the duration time between + the last at_cmd and the next data. */ + uint32_t : 16; + } bit; + } AT_CMD_POSTCNT_SYNC; + + union { + __IOM uint32_t reg; /*!< Timeout configuration */ + + struct { + __IOM uint32_t RX_GAP_TOUT : 16; /*!< This register is used to configure the duration time between + the at_cmd chars. */ + uint32_t : 16; + } bit; + } AT_CMD_GAPTOUT_SYNC; + + union { + __IOM uint32_t reg; /*!< AT escape sequence detection configuration */ + + struct { + __IOM uint32_t AT_CMD_CHAR : 8; /*!< This register is used to configure the content of at_cmd char. */ + __IOM uint32_t CHAR_NUM : 8; /*!< This register is used to configure the num of continuous at_cmd + chars received by receiver. */ + uint32_t : 16; + } bit; + } AT_CMD_CHAR_SYNC; + + union { + __IOM uint32_t reg; /*!< UART memory power configuration */ + + struct { + uint32_t : 25; + __IOM uint32_t MEM_FORCE_PD : 1; /*!< Set this bit to force power down UART memory. */ + __IOM uint32_t MEM_FORCE_PU : 1; /*!< Set this bit to force power up UART memory. */ + uint32_t : 5; + } bit; + } MEM_CONF; + + union { + __IOM uint32_t reg; /*!< UART threshold and allocation configuration */ + + struct { + __IOM uint32_t RX_TOUT_EN : 1; /*!< This is the enble bit for uart receiver's timeout function. */ + __IOM uint32_t RX_TOUT_FLOW_DIS : 1; /*!< Set this bit to stop accumulating idle_cnt when hardware flow + control works. */ + __IOM uint32_t RX_TOUT_THRHD : 10; /*!< This register is used to configure the threshold time that receiver + takes to receive one byte. The rxfifo_tout_int interrupt + will be trigger when the receiver takes more time to receive + one byte with rx_tout_en set to 1. */ + uint32_t : 20; + } bit; + } TOUT_CONF_SYNC; + + union { + __IOM uint32_t reg; /*!< Tx-SRAM write and read offset address. */ + + struct { + uint32_t : 3; + __IM uint32_t TX_SRAM_WADDR : 5; /*!< This register stores the offset write address in Tx-SRAM. */ + uint32_t : 4; + __IM uint32_t TX_SRAM_RADDR : 5; /*!< This register stores the offset read address in Tx-SRAM. */ + uint32_t : 15; + } bit; + } MEM_TX_STATUS; + + union { + __IOM uint32_t reg; /*!< Rx-SRAM write and read offset address. */ + + struct { + uint32_t : 3; + __IM uint32_t RX_SRAM_RADDR : 5; /*!< This register stores the offset read address in RX-SRAM. */ + uint32_t : 4; + __IM uint32_t RX_SRAM_WADDR : 5; /*!< This register stores the offset write address in Rx-SRAM. */ + uint32_t : 15; + } bit; + } MEM_RX_STATUS; + + union { + __IOM uint32_t reg; /*!< UART transmit and receive status. */ + + struct { + __IM uint32_t ST_URX_OUT : 4; /*!< This is the status register of receiver. */ + __IM uint32_t ST_UTX_OUT : 4; /*!< This is the status register of transmitter. */ + uint32_t : 24; + } bit; + } FSM_STATUS; + __IM uint32_t RESERVED1[5]; + + union { + __IOM uint32_t reg; /*!< UART core clock configuration */ + + struct { + uint32_t : 24; + __IOM uint32_t TX_SCLK_EN : 1; /*!< Set this bit to enable UART Tx clock. */ + __IOM uint32_t RX_SCLK_EN : 1; /*!< Set this bit to enable UART Rx clock. */ + __IOM uint32_t TX_RST_CORE : 1; /*!< Write 1 then write 0 to this bit to reset UART Tx. */ + __IOM uint32_t RX_RST_CORE : 1; /*!< Write 1 then write 0 to this bit to reset UART Rx. */ + uint32_t : 4; + } bit; + } CLK_CONF; + + union { + __IOM uint32_t reg; /*!< UART Version register */ + + struct { + __IOM uint32_t DATE : 32; /*!< This is the version register. */ + } bit; + } DATE; + + union { + __IOM uint32_t reg; /*!< UART AFIFO Status */ + + struct { + __IM uint32_t TX_AFIFO_FULL : 1; /*!< Full signal of APB TX AFIFO. */ + __IM uint32_t TX_AFIFO_EMPTY : 1; /*!< Empty signal of APB TX AFIFO. */ + __IM uint32_t RX_AFIFO_FULL : 1; /*!< Full signal of APB RX AFIFO. */ + __IM uint32_t RX_AFIFO_EMPTY : 1; /*!< Empty signal of APB RX AFIFO. */ + uint32_t : 28; + } bit; + } AFIFO_STATUS; + __IM uint32_t RESERVED2; + + union { + __IOM uint32_t reg; /*!< UART Registers Configuration Update register */ + + struct { + __IOM uint32_t REG_UPDATE : 1; /*!< Software write 1 would synchronize registers into UART Core + clock domain and would be cleared by hardware after synchronization + is done. */ + uint32_t : 31; + } bit; + } REG_UPDATE; + + union { + __IOM uint32_t reg; /*!< UART ID register */ + + struct { + __IOM uint32_t ID : 32; /*!< This register is used to configure the uart_id. */ + } bit; + } ID; +} LP_UART_Type; /*!< Size = 160 (0xa0) */ + + + +/* =========================================================================================================================== */ +/* ================ MCPWM0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Motor Control Pulse-Width Modulation 0 (MCPWM0) + */ + +typedef struct { /*!< MCPWM0 Structure */ + + union { + __IOM uint32_t reg; /*!< PWM clock prescaler register. */ + + struct { + __IOM uint32_t CLK_PRESCALE : 8; /*!< Configures the prescaler value of clock, so that the period + of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1). */ + uint32_t : 24; + } bit; + } CLK_CFG; + __IOM uint32_t TIMER0_CFG0; /*!< PWM timer0 period and update method configuration register. */ + __IOM uint32_t TIMER0_CFG1; /*!< PWM timer0 working mode and start/stop control register. */ + + union { + __IOM uint32_t reg; /*!< PWM timer0 sync function configuration register. */ + + struct { + uint32_t : 1; + __IOM uint32_t SW : 1; /*!< Configures the generation of software sync. Toggling this bit + will trigger a software sync. */ + uint32_t : 30; + } bit; + } TIMER0_SYNC; + __IOM uint32_t TIMER0_STATUS; /*!< PWM timer0 status register. */ + __IM uint32_t RESERVED[8]; + + union { + __IOM uint32_t reg; /*!< Synchronization input selection register for PWM timers. */ + + struct { + __IOM uint32_t TIMER0_SYNCISEL : 3; /*!< Configures the selection of sync input for PWM timer0.\\1: PWM + timer0 sync_out\\2: PWM timer1 sync_out\\3: PWM timer2 + sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1 from GPIO + matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync + input selected */ + __IOM uint32_t TIMER1_SYNCISEL : 3; /*!< Configures the selection of sync input for PWM timer1.\\1: PWM + timer0 sync_out\\2: PWM timer1 sync_out\\3: PWM timer2 + sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1 from GPIO + matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync + input selected */ + __IOM uint32_t TIMER2_SYNCISEL : 3; /*!< Configures the selection of sync input for PWM timer2.\\1: PWM + timer0 sync_out\\2: PWM timer1 sync_out\\3: PWM timer2 + sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1 from GPIO + matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync + input selected */ + __IOM uint32_t EXTERNAL_SYNCI0_INVERT : 1;/*!< Configures whether or not to invert SYNC0 from GPIO matrix.\\0: + Not invert\\1: Invert */ + __IOM uint32_t EXTERNAL_SYNCI1_INVERT : 1;/*!< Configures whether or not to invert SYNC1 from GPIO matrix.\\0: + Not invert\\1: Invert */ + __IOM uint32_t EXTERNAL_SYNCI2_INVERT : 1;/*!< Configures whether or not to invert SYNC2 from GPIO matrix.\\0: + Not invert\\1: Invert */ + uint32_t : 20; + } bit; + } TIMER_SYNCI_CFG; + + union { + __IOM uint32_t reg; /*!< PWM operator's timer select register */ + + struct { + __IOM uint32_t OPERATOR0_TIMERSEL : 2; /*!< Configures which PWM timer will be the timing reference for + PWM operator0.\\0: Timer0\\1: Timer1\\2: Timer2\\3: Invalid, + will select timer2 */ + __IOM uint32_t OPERATOR1_TIMERSEL : 2; /*!< Configures which PWM timer will be the timing reference for + PWM operator1.\\0: Timer0\\1: Timer1\\2: Timer2\\3: Invalid, + will select timer2 */ + __IOM uint32_t OPERATOR2_TIMERSEL : 2; /*!< Configures which PWM timer will be the timing reference for + PWM operator2.\\0: Timer0\\1: Timer1\\2: Timer2\\3: Invalid, + will select timer2 */ + uint32_t : 26; + } bit; + } OPERATOR_TIMERSEL; + __IOM uint32_t GEN0_STMP_CFG; /*!< Generator0 time stamp registers A and B transfer status and + update method register */ + __IOM uint32_t GEN0_TSTMP_A; /*!< Generator0 time stamp A's shadow register */ + + union { + __IOM uint32_t TIMER1_CFG0; /*!< PWM timer1 period and update method configuration register. */ + __IOM uint32_t GEN0_TSTMP_B; /*!< Generator0 time stamp B's shadow register */ + }; + + union { + __IOM uint32_t TIMER1_CFG1; /*!< PWM timer1 working mode and start/stop control register. */ + __IOM uint32_t GEN0_CFG0; /*!< Generator0 fault event T0 and T1 configuration register */ + }; + + union { + union { + __IOM uint32_t reg; /*!< PWM timer1 sync function configuration register. */ + + struct { + uint32_t : 1; + __IOM uint32_t SW : 1; /*!< Configures the generation of software sync. Toggling this bit + will trigger a software sync. */ + uint32_t : 30; + } bit; + } TIMER1_SYNC; + __IOM uint32_t GEN0_FORCE; /*!< Generator0 output signal force mode register. */ + }; + + union { + __IOM uint32_t TIMER1_STATUS; /*!< PWM timer1 status register. */ + __IOM uint32_t GEN0_A; /*!< PWM0 output signal A actions configuration register */ + }; + __IOM uint32_t GEN0_B; /*!< PWM0 output signal B actions configuration register */ + + union { + __IOM uint32_t reg; /*!< Dead time configuration register */ + + struct { + __IOM uint32_t DB_FED_UPMETHOD : 4; /*!< Configures update method for FED (Falling edge delay) active + register.\\0: Immediate\\Bit0 is set to 1: TEZ\\Bit1 is + set to 1: TEP\\Bit2 is set to 1: Sync\\Bit3 is set to 1: + Disable the update */ + __IOM uint32_t DB_RED_UPMETHOD : 4; /*!< Configures update method for RED (rising edge delay) active + register.\\0: Immediate\\Bit0 is set to 1: TEZ\\Bit1 is + set to 1: TEP\\Bit2 is set to 1: Sync\\Bit3 is set to 1: + Disable the update */ + __IOM uint32_t DB_DEB_MODE : 1; /*!< Configures S8 in table, dual-edge B mode.\\0: fed/red take effect + on different path separately\\1: fed/red take effect on + B path, A out is in bypass or dulpB mode */ + __IOM uint32_t DB_A_OUTSWAP : 1; /*!< Configures S6 in table. */ + __IOM uint32_t DB_B_OUTSWAP : 1; /*!< Configures S7 in table. */ + __IOM uint32_t DB_RED_INSEL : 1; /*!< Configures S4 in table. */ + __IOM uint32_t DB_FED_INSEL : 1; /*!< Configures S5 in table. */ + __IOM uint32_t DB_RED_OUTINVERT : 1; /*!< Configures S2 in table. */ + __IOM uint32_t DB_FED_OUTINVERT : 1; /*!< Configures S3 in table. */ + __IOM uint32_t DB_A_OUTBYPASS : 1; /*!< Configures S1 in table. */ + __IOM uint32_t DB_B_OUTBYPASS : 1; /*!< Configures S0 in table. */ + uint32_t : 15; + } bit; + } DT0_CFG; + + union { + __IOM uint32_t reg; /*!< Falling edge delay (FED) shadow register */ + + struct { + __IOM uint32_t DB_FED : 16; /*!< Configures shadow register for FED. */ + uint32_t : 16; + } bit; + } DT0_FED_CFG; + + union { + __IOM uint32_t reg; /*!< Rising edge delay (RED) shadow register */ + + struct { + __IOM uint32_t DB_RED : 16; /*!< Configures shadow register for RED. */ + uint32_t : 16; + } bit; + } DT0_RED_CFG; + + union { + __IOM uint32_t reg; /*!< Carrier0 configuration register */ + + struct { + uint32_t : 8; + __IOM uint32_t CHOPPER_OSHTWTH : 4; /*!< Configures width of the first pulse. Measurement unit: Periods + of the carrier. */ + uint32_t : 20; + } bit; + } CARRIER0_CFG; + __IM uint32_t RESERVED1; + + union { + __IOM uint32_t reg; /*!< Software triggers for fault handler actions configuration register */ + + struct { + __IOM uint32_t TZ_CLR_OST : 1; /*!< Configures the generation of software one-shot mode action clear. + A toggle (software negate its value) triggers a clear for + on going one-shot mode action. */ + __IOM uint32_t TZ_CBCPULSE : 2; /*!< Configures the refresh moment selection of cycle-by-cycle mode + action.\\0: Select nothing, will not refresh\\Bit0 is set + to 1: TEZ\\Bit1 is set to 1: TEP */ + __IOM uint32_t TZ_FORCE_CBC : 1; /*!< Configures the generation of software cycle-by-cycle mode action. + A toggle (software negate its value) triggers a cycle-by-cycle + mode action. */ + __IOM uint32_t TZ_FORCE_OST : 1; /*!< Configures the generation of software one-shot mode action. + A toggle (software negate its value) triggers a one-shot + mode action. */ + uint32_t : 27; + } bit; + } FH0_CFG1; + + union { + __IOM uint32_t reg; /*!< Fault events status register */ + + struct { + __IM uint32_t TZ_CBC_ON : 1; /*!< Represents whether or not an cycle-by-cycle mode action is on + going.\\0:No action\\1: On going */ + __IM uint32_t TZ_OST_ON : 1; /*!< Represents whether or not an one-shot mode action is on going.\\0:No + action\\1: On going */ + uint32_t : 30; + } bit; + } FH0_STATUS; + __IM uint32_t RESERVED2[4]; + __IOM uint32_t TIMER2_CFG0; /*!< PWM timer2 period and update method configuration register. */ + __IOM uint32_t TIMER2_CFG1; /*!< PWM timer2 working mode and start/stop control register. */ + + union { + __IOM uint32_t reg; /*!< PWM timer2 sync function configuration register. */ + + struct { + uint32_t : 1; + __IOM uint32_t SW : 1; /*!< Configures the generation of software sync. Toggling this bit + will trigger a software sync. */ + uint32_t : 30; + } bit; + } TIMER2_SYNC; + __IOM uint32_t TIMER2_STATUS; /*!< PWM timer2 status register. */ + __IM uint32_t RESERVED3[20]; + + union { + __IOM uint32_t reg; /*!< Fault detection configuration and status register */ + + struct { + __IOM uint32_t F0_EN : 1; /*!< Configures whether or not to enable event_f0 generation.\\0: + Disable\\1: Enable */ + __IOM uint32_t F1_EN : 1; /*!< Configures whether or not to enable event_f1 generation.\\0: + Disable\\1: Enable */ + __IOM uint32_t F2_EN : 1; /*!< Configures whether or not to enable event_f2 generation.\\0: + Disable\\1: Enable */ + __IOM uint32_t F0_POLE : 1; /*!< Configures event_f0 trigger polarity on FAULT0 source from GPIO + matrix.\\0: Level low\\1: Level high */ + __IOM uint32_t F1_POLE : 1; /*!< Configures event_f1 trigger polarity on FAULT1 source from GPIO + matrix.\\0: Level low\\1: Level high */ + __IOM uint32_t F2_POLE : 1; /*!< Configures event_f2 trigger polarity on FAULT2 source from GPIO + matrix.\\0: Level low\\1: Level high */ + __IM uint32_t EVENT_F0 : 1; /*!< Represents whether or not an event_f0 is on going.\\0: No action\\1: + On going */ + __IM uint32_t EVENT_F1 : 1; /*!< Represents whether or not an event_f1 is on going.\\0: No action\\1: + On going */ + __IM uint32_t EVENT_F2 : 1; /*!< Represents whether or not an event_f2 is on going.\\0: No action\\1: + On going */ + uint32_t : 23; + } bit; + } FAULT_DETECT; + + union { + __IOM uint32_t reg; /*!< Capture timer configuration register */ + + struct { + __IOM uint32_t CAP_TIMER_EN : 1; /*!< Configures whether or not to enable capture timer increment.\\0: + Disable\\1: Enable */ + __IOM uint32_t CAP_SYNCI_EN : 1; /*!< Configures whether or not to enable capture timer sync.\\0: + Disable\\1: Enable */ + __IOM uint32_t CAP_SYNCI_SEL : 3; /*!< Configures the selection of capture module sync input.\\0: None\\1: + Timer0 sync_out\\2: Timer1 sync_out\\3: Timer2 sync_out\\4: + SYNC0 from GPIO matrix\\5: SYNC1 from GPIO matrix\\6: SYNC2 + from GPIO matrix\\7: None */ + __OM uint32_t CAP_SYNC_SW : 1; /*!< Configures the generation of a capture timer sync when reg_cap_synci_en + is 1.\\0: Invalid, No effect\\1: Trigger a capture timer + sync, capture timer is loaded with value in phase register */ + uint32_t : 26; + } bit; + } CAP_TIMER_CFG; + + union { + __IOM uint32_t reg; /*!< Capture timer sync phase register */ + + struct { + __IOM uint32_t CAP_PHASE : 32; /*!< Configures phase value for capture timer sync operation. */ + } bit; + } CAP_TIMER_PHASE; + __IOM uint32_t CAP_CH0_CFG; /*!< Capture channel 0 configuration register */ + __IM uint32_t RESERVED4[2]; + __IOM uint32_t CAP_CH0; /*!< CAP0 capture value register */ + __IOM uint32_t CAP_CH1_CFG; /*!< Capture channel 1 configuration register */ + __IM uint32_t RESERVED5; + + union { + __IOM uint32_t reg; /*!< Last capture trigger edge information register */ + + struct { + __IM uint32_t CAP0_EDGE : 1; /*!< Represents edge of last capture trigger on channel0.\\0: Posedge\\1: + Negedge */ + __IM uint32_t CAP1_EDGE : 1; /*!< Represents edge of last capture trigger on channel1.\\0: Posedge\\1: + Negedge */ + __IM uint32_t CAP2_EDGE : 1; /*!< Represents edge of last capture trigger on channel2.\\0: Posedge\\1: + Negedge */ + uint32_t : 29; + } bit; + } CAP_STATUS; + + union { + __IOM uint32_t CAP_CH1; /*!< CAP1 capture value register */ + + union { + __IOM uint32_t reg; /*!< Generator Update configuration register */ + + struct { + __IOM uint32_t GLOBAL_UP_EN : 1; /*!< Configures whether or not to enable global update for all active + registers in MCPWM module.\\0: Disable\\1: Enable */ + __IOM uint32_t GLOBAL_FORCE_UP : 1; /*!< Configures the generation of global forced update for all active + registers in MCPWM module. A toggle (software invert its + value) will trigger a global forced update. Valid only + when MCPWM_GLOBAL_UP_EN and MCPWM_OP0/1/2_UP_EN are both + set to 1. */ + __IOM uint32_t OP0_UP_EN : 1; /*!< Configures whether or not to enable update of active registers + in PWM operator0. Valid only when PWM_GLOBAL_UP_EN is set + to 1.\\0: Disable\\1: Enable */ + __IOM uint32_t OP0_FORCE_UP : 1; /*!< Configures the generation of forced update for active registers + in PWM operator0. A toggle (software invert its value) + will trigger a forced update. Valid only when MCPWM_GLOBAL_UP_EN + and MCPWM_OP0_UP_EN are both set to 1. */ + __IOM uint32_t OP1_UP_EN : 1; /*!< Configures whether or not to enable update of active registers + in PWM operator1. Valid only when PWM_GLOBAL_UP_EN is set + to 1.\\0: Disable\\1: Enable */ + __IOM uint32_t OP1_FORCE_UP : 1; /*!< Configures the generation of forced update for active registers + in PWM operator1. A toggle (software invert its value) + will trigger a forced update. Valid only when MCPWM_GLOBAL_UP_EN + and MCPWM_OP1_UP_EN are both set to 1. */ + __IOM uint32_t OP2_UP_EN : 1; /*!< Configures whether or not to enable update of active registers + in PWM operator2. Valid only when PWM_GLOBAL_UP_EN is set + to 1.\\0: Disable\\1: Enable */ + __IOM uint32_t OP2_FORCE_UP : 1; /*!< Configures the generation of forced update for active registers + in PWM operator2. A toggle (software invert its value) + will trigger a forced update. Valid only when MCPWM_GLOBAL_UP_EN + and MCPWM_OP2_UP_EN are both set to 1. */ + uint32_t : 24; + } bit; + } UPDATE_CFG; + }; + + union { + __IOM uint32_t CAP_CH2_CFG; /*!< Capture channel 2 configuration register */ + + union { + __IOM uint32_t reg; /*!< Interrupt enable register */ + + struct { + __IOM uint32_t TIMER0_STOP_INT_ENA : 1; /*!< Enable bit: Write 1 to enable the interrupt triggered when the + timer 0 stops. */ + __IOM uint32_t TIMER1_STOP_INT_ENA : 1; /*!< Enable bit: Write 1 to enable the interrupt triggered when the + timer 1 stops. */ + __IOM uint32_t TIMER2_STOP_INT_ENA : 1; /*!< Enable bit: Write 1 to enable the interrupt triggered when the + timer 2 stops. */ + __IOM uint32_t TIMER0_TEZ_INT_ENA : 1; /*!< Enable bit: Write 1 to enable the interrupt triggered by a PWM + timer 0 TEZ event. */ + __IOM uint32_t TIMER1_TEZ_INT_ENA : 1; /*!< Enable bit: Write 1 to enable the interrupt triggered by a PWM + timer 1 TEZ event. */ + __IOM uint32_t TIMER2_TEZ_INT_ENA : 1; /*!< Enable bit: Write 1 to enable the interrupt triggered by a PWM + timer 2 TEZ event. */ + __IOM uint32_t TIMER0_TEP_INT_ENA : 1; /*!< Enable bit: Write 1 to enable the interrupt triggered by a PWM + timer 0 TEP event. */ + __IOM uint32_t TIMER1_TEP_INT_ENA : 1; /*!< Enable bit: Write 1 to enable the interrupt triggered by a PWM + timer 1 TEP event. */ + __IOM uint32_t TIMER2_TEP_INT_ENA : 1; /*!< Enable bit: Write 1 to enable the interrupt triggered by a PWM + timer 2 TEP event. */ + __IOM uint32_t FAULT0_INT_ENA : 1; /*!< Enable bit: Write 1 to enable the interrupt triggered when event_f0 + starts. */ + __IOM uint32_t FAULT1_INT_ENA : 1; /*!< Enable bit: Write 1 to enable the interrupt triggered when event_f1 + starts. */ + __IOM uint32_t FAULT2_INT_ENA : 1; /*!< Enable bit: Write 1 to enable the interrupt triggered when event_f2 + starts. */ + __IOM uint32_t FAULT0_CLR_INT_ENA : 1; /*!< Enable bit: Write 1 to enable the interrupt triggered when event_f0 + clears. */ + __IOM uint32_t FAULT1_CLR_INT_ENA : 1; /*!< Enable bit: Write 1 to enable the interrupt triggered when event_f1 + clears. */ + __IOM uint32_t FAULT2_CLR_INT_ENA : 1; /*!< Enable bit: Write 1 to enable the interrupt triggered when event_f2 + clears. */ + __IOM uint32_t CMPR0_TEA_INT_ENA : 1; /*!< Enable bit: Write 1 to enable the interrupt triggered by a PWM + operator 0 TEA event. */ + __IOM uint32_t CMPR1_TEA_INT_ENA : 1; /*!< Enable bit: Write 1 to enable the interrupt triggered by a PWM + operator 1 TEA event. */ + __IOM uint32_t CMPR2_TEA_INT_ENA : 1; /*!< Enable bit: Write 1 to enable the interrupt triggered by a PWM + operator 2 TEA event. */ + __IOM uint32_t CMPR0_TEB_INT_ENA : 1; /*!< Enable bit: Write 1 to enable the interrupt triggered by a PWM + operator 0 TEB event. */ + __IOM uint32_t CMPR1_TEB_INT_ENA : 1; /*!< Enable bit: Write 1 to enable the interrupt triggered by a PWM + operator 1 TEB event. */ + __IOM uint32_t CMPR2_TEB_INT_ENA : 1; /*!< Enable bit: Write 1 to enable the interrupt triggered by a PWM + operator 2 TEB event. */ + __IOM uint32_t TZ0_CBC_INT_ENA : 1; /*!< Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle + mode action on PWM0. */ + __IOM uint32_t TZ1_CBC_INT_ENA : 1; /*!< Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle + mode action on PWM1. */ + __IOM uint32_t TZ2_CBC_INT_ENA : 1; /*!< Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle + mode action on PWM2. */ + __IOM uint32_t TZ0_OST_INT_ENA : 1; /*!< Enable bit: Write 1 to enable the interrupt triggered by a one-shot + mode action on PWM0. */ + __IOM uint32_t TZ1_OST_INT_ENA : 1; /*!< Enable bit: Write 1 to enable the interrupt triggered by a one-shot + mode action on PWM1. */ + __IOM uint32_t TZ2_OST_INT_ENA : 1; /*!< Enable bit: Write 1 to enable the interrupt triggered by a one-shot + mode action on PWM2. */ + __IOM uint32_t CAP0_INT_ENA : 1; /*!< Enable bit: Write 1 to enable the interrupt triggered by capture + on CAP0. */ + __IOM uint32_t CAP1_INT_ENA : 1; /*!< Enable bit: Write 1 to enable the interrupt triggered by capture + on CAP1. */ + __IOM uint32_t CAP2_INT_ENA : 1; /*!< Enable bit: Write 1 to enable the interrupt triggered by capture + on CAP2. */ + uint32_t : 2; + } bit; + } INT_ENA; + }; + + union { + __IOM uint32_t reg; /*!< Interrupt raw status register */ + + struct { + __IOM uint32_t TIMER0_STOP_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of the interrupt triggered + when the timer 0 stops. */ + __IOM uint32_t TIMER1_STOP_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of the interrupt triggered + when the timer 1 stops. */ + __IOM uint32_t TIMER2_STOP_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of the interrupt triggered + when the timer 2 stops. */ + __IOM uint32_t TIMER0_TEZ_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of the interrupt triggered + by a PWM timer 0 TEZ event. */ + __IOM uint32_t TIMER1_TEZ_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of the interrupt triggered + by a PWM timer 1 TEZ event. */ + __IOM uint32_t TIMER2_TEZ_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of the interrupt triggered + by a PWM timer 2 TEZ event. */ + __IOM uint32_t TIMER0_TEP_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of the interrupt triggered + by a PWM timer 0 TEP event. */ + __IOM uint32_t TIMER1_TEP_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of the interrupt triggered + by a PWM timer 1 TEP event. */ + __IOM uint32_t TIMER2_TEP_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of the interrupt triggered + by a PWM timer 2 TEP event. */ + __IOM uint32_t FAULT0_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of the interrupt triggered + when event_f0 starts. */ + __IOM uint32_t FAULT1_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of the interrupt triggered + when event_f1 starts. */ + __IOM uint32_t FAULT2_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of the interrupt triggered + when event_f2 starts. */ + __IOM uint32_t FAULT0_CLR_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of the interrupt triggered + when event_f0 clears. */ + __IOM uint32_t FAULT1_CLR_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of the interrupt triggered + when event_f1 clears. */ + __IOM uint32_t FAULT2_CLR_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of the interrupt triggered + when event_f2 clears. */ + __IOM uint32_t CMPR0_TEA_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of the interrupt triggered + by a PWM operator 0 TEA event */ + __IOM uint32_t CMPR1_TEA_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of the interrupt triggered + by a PWM operator 1 TEA event */ + __IOM uint32_t CMPR2_TEA_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of the interrupt triggered + by a PWM operator 2 TEA event */ + __IOM uint32_t CMPR0_TEB_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of the interrupt triggered + by a PWM operator 0 TEB event */ + __IOM uint32_t CMPR1_TEB_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of the interrupt triggered + by a PWM operator 1 TEB event */ + __IOM uint32_t CMPR2_TEB_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of the interrupt triggered + by a PWM operator 2 TEB event */ + __IOM uint32_t TZ0_CBC_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of the interrupt triggered + by a cycle-by-cycle mode action on PWM0. */ + __IOM uint32_t TZ1_CBC_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of the interrupt triggered + by a cycle-by-cycle mode action on PWM1. */ + __IOM uint32_t TZ2_CBC_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of the interrupt triggered + by a cycle-by-cycle mode action on PWM2. */ + __IOM uint32_t TZ0_OST_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of the interrupt triggered + by a one-shot mode action on PWM0. */ + __IOM uint32_t TZ1_OST_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of the interrupt triggered + by a one-shot mode action on PWM1. */ + __IOM uint32_t TZ2_OST_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of the interrupt triggered + by a one-shot mode action on PWM2. */ + __IOM uint32_t CAP0_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of the interrupt triggered + by capture on CAP0. */ + __IOM uint32_t CAP1_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of the interrupt triggered + by capture on CAP1. */ + __IOM uint32_t CAP2_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of the interrupt triggered + by capture on CAP2. */ + uint32_t : 2; + } bit; + } INT_RAW; + + union { + __IOM uint32_t reg; /*!< Interrupt masked status register */ + + struct { + __IM uint32_t TIMER0_STOP_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of the interrupt + triggered when the timer 0 stops. */ + __IM uint32_t TIMER1_STOP_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of the interrupt + triggered when the timer 1 stops. */ + __IM uint32_t TIMER2_STOP_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of the interrupt + triggered when the timer 2 stops. */ + __IM uint32_t TIMER0_TEZ_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of the interrupt + triggered by a PWM timer 0 TEZ event. */ + __IM uint32_t TIMER1_TEZ_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of the interrupt + triggered by a PWM timer 1 TEZ event. */ + __IM uint32_t TIMER2_TEZ_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of the interrupt + triggered by a PWM timer 2 TEZ event. */ + __IM uint32_t TIMER0_TEP_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of the interrupt + triggered by a PWM timer 0 TEP event. */ + __IM uint32_t TIMER1_TEP_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of the interrupt + triggered by a PWM timer 1 TEP event. */ + __IM uint32_t TIMER2_TEP_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of the interrupt + triggered by a PWM timer 2 TEP event. */ + __IM uint32_t FAULT0_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of the interrupt + triggered when event_f0 starts. */ + __IM uint32_t FAULT1_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of the interrupt + triggered when event_f1 starts. */ + __IM uint32_t FAULT2_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of the interrupt + triggered when event_f2 starts. */ + __IM uint32_t FAULT0_CLR_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of the interrupt + triggered when event_f0 clears. */ + __IM uint32_t FAULT1_CLR_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of the interrupt + triggered when event_f1 clears. */ + __IM uint32_t FAULT2_CLR_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of the interrupt + triggered when event_f2 clears. */ + __IM uint32_t CMPR0_TEA_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of the interrupt + triggered by a PWM operator 0 TEA event */ + __IM uint32_t CMPR1_TEA_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of the interrupt + triggered by a PWM operator 1 TEA event */ + __IM uint32_t CMPR2_TEA_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of the interrupt + triggered by a PWM operator 2 TEA event */ + __IM uint32_t CMPR0_TEB_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of the interrupt + triggered by a PWM operator 0 TEB event */ + __IM uint32_t CMPR1_TEB_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of the interrupt + triggered by a PWM operator 1 TEB event */ + __IM uint32_t CMPR2_TEB_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of the interrupt + triggered by a PWM operator 2 TEB event */ + __IM uint32_t TZ0_CBC_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of the interrupt + triggered by a cycle-by-cycle mode action on PWM0. */ + __IM uint32_t TZ1_CBC_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of the interrupt + triggered by a cycle-by-cycle mode action on PWM1. */ + __IM uint32_t TZ2_CBC_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of the interrupt + triggered by a cycle-by-cycle mode action on PWM2. */ + __IM uint32_t TZ0_OST_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of the interrupt + triggered by a one-shot mode action on PWM0. */ + __IM uint32_t TZ1_OST_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of the interrupt + triggered by a one-shot mode action on PWM1. */ + __IM uint32_t TZ2_OST_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of the interrupt + triggered by a one-shot mode action on PWM2. */ + __IM uint32_t CAP0_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of the interrupt + triggered by capture on CAP0. */ + __IM uint32_t CAP1_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of the interrupt + triggered by capture on CAP1. */ + __IM uint32_t CAP2_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of the interrupt + triggered by capture on CAP2. */ + uint32_t : 2; + } bit; + } INT_ST; + + union { + __IOM uint32_t GEN1_STMP_CFG; /*!< Generator1 time stamp registers A and B transfer status and + update method register */ + __IOM uint32_t CAP_CH2; /*!< CAP2 capture value register */ + + union { + __IOM uint32_t reg; /*!< Interrupt clear register */ + + struct { + __OM uint32_t TIMER0_STOP_INT_CLR : 1; /*!< Clear bit: Write 1 to clear the interrupt triggered when the + timer 0 stops. */ + __OM uint32_t TIMER1_STOP_INT_CLR : 1; /*!< Clear bit: Write 1 to clear the interrupt triggered when the + timer 1 stops. */ + __OM uint32_t TIMER2_STOP_INT_CLR : 1; /*!< Clear bit: Write 1 to clear the interrupt triggered when the + timer 2 stops. */ + __OM uint32_t TIMER0_TEZ_INT_CLR : 1; /*!< Clear bit: Write 1 to clear the interrupt triggered by a PWM + timer 0 TEZ event. */ + __OM uint32_t TIMER1_TEZ_INT_CLR : 1; /*!< Clear bit: Write 1 to clear the interrupt triggered by a PWM + timer 1 TEZ event. */ + __OM uint32_t TIMER2_TEZ_INT_CLR : 1; /*!< Clear bit: Write 1 to clear the interrupt triggered by a PWM + timer 2 TEZ event. */ + __OM uint32_t TIMER0_TEP_INT_CLR : 1; /*!< Clear bit: Write 1 to clear the interrupt triggered by a PWM + timer 0 TEP event. */ + __OM uint32_t TIMER1_TEP_INT_CLR : 1; /*!< Clear bit: Write 1 to clear the interrupt triggered by a PWM + timer 1 TEP event. */ + __OM uint32_t TIMER2_TEP_INT_CLR : 1; /*!< Clear bit: Write 1 to clear the interrupt triggered by a PWM + timer 2 TEP event. */ + __OM uint32_t FAULT0_INT_CLR : 1; /*!< Clear bit: Write 1 to clear the interrupt triggered when event_f0 + starts. */ + __OM uint32_t FAULT1_INT_CLR : 1; /*!< Clear bit: Write 1 to clear the interrupt triggered when event_f1 + starts. */ + __OM uint32_t FAULT2_INT_CLR : 1; /*!< Clear bit: Write 1 to clear the interrupt triggered when event_f2 + starts. */ + __OM uint32_t FAULT0_CLR_INT_CLR : 1; /*!< Clear bit: Write 1 to clear the interrupt triggered when event_f0 + clears. */ + __OM uint32_t FAULT1_CLR_INT_CLR : 1; /*!< Clear bit: Write 1 to clear the interrupt triggered when event_f1 + clears. */ + __OM uint32_t FAULT2_CLR_INT_CLR : 1; /*!< Clear bit: Write 1 to clear the interrupt triggered when event_f2 + clears. */ + __OM uint32_t CMPR0_TEA_INT_CLR : 1; /*!< Clear bit: Write 1 to clear the interrupt triggered by a PWM + operator 0 TEA event */ + __OM uint32_t CMPR1_TEA_INT_CLR : 1; /*!< Clear bit: Write 1 to clear the interrupt triggered by a PWM + operator 1 TEA event */ + __OM uint32_t CMPR2_TEA_INT_CLR : 1; /*!< Clear bit: Write 1 to clear the interrupt triggered by a PWM + operator 2 TEA event */ + __OM uint32_t CMPR0_TEB_INT_CLR : 1; /*!< Clear bit: Write 1 to clear the interrupt triggered by a PWM + operator 0 TEB event */ + __OM uint32_t CMPR1_TEB_INT_CLR : 1; /*!< Clear bit: Write 1 to clear the interrupt triggered by a PWM + operator 1 TEB event */ + __OM uint32_t CMPR2_TEB_INT_CLR : 1; /*!< Clear bit: Write 1 to clear the interrupt triggered by a PWM + operator 2 TEB event */ + __OM uint32_t TZ0_CBC_INT_CLR : 1; /*!< Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle + mode action on PWM0. */ + __OM uint32_t TZ1_CBC_INT_CLR : 1; /*!< Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle + mode action on PWM1. */ + __OM uint32_t TZ2_CBC_INT_CLR : 1; /*!< Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle + mode action on PWM2. */ + __OM uint32_t TZ0_OST_INT_CLR : 1; /*!< Clear bit: Write 1 to clear the interrupt triggered by a one-shot + mode action on PWM0. */ + __OM uint32_t TZ1_OST_INT_CLR : 1; /*!< Clear bit: Write 1 to clear the interrupt triggered by a one-shot + mode action on PWM1. */ + __OM uint32_t TZ2_OST_INT_CLR : 1; /*!< Clear bit: Write 1 to clear the interrupt triggered by a one-shot + mode action on PWM2. */ + __OM uint32_t CAP0_INT_CLR : 1; /*!< Clear bit: Write 1 to clear the interrupt triggered by capture + on CAP0. */ + __OM uint32_t CAP1_INT_CLR : 1; /*!< Clear bit: Write 1 to clear the interrupt triggered by capture + on CAP1. */ + __OM uint32_t CAP2_INT_CLR : 1; /*!< Clear bit: Write 1 to clear the interrupt triggered by capture + on CAP2. */ + uint32_t : 2; + } bit; + } INT_CLR; + }; + + union { + __IOM uint32_t GEN1_TSTMP_A; /*!< Generator1 time stamp A's shadow register */ + + union { + __IOM uint32_t reg; /*!< Event enable register */ + + struct { + __IOM uint32_t EVT_TIMER0_STOP_EN : 1; /*!< Configures whether or not to enable timer0 stop event generate.\\0: + Disable\\1: Enable */ + __IOM uint32_t EVT_TIMER1_STOP_EN : 1; /*!< Configures whether or not to enable timer1 stop event generate.\\0: + Disable\\1: Enable */ + __IOM uint32_t EVT_TIMER2_STOP_EN : 1; /*!< Configures whether or not to enable timer2 stop event generate.\\0: + Disable\\1: Enable */ + __IOM uint32_t EVT_TIMER0_TEZ_EN : 1; /*!< Configures whether or not to enable timer0 equal zero event + generate.\\0: Disable\\1: Enable */ + __IOM uint32_t EVT_TIMER1_TEZ_EN : 1; /*!< Configures whether or not to enable timer1 equal zero event + generate.\\0: Disable\\1: Enable */ + __IOM uint32_t EVT_TIMER2_TEZ_EN : 1; /*!< Configures whether or not to enable timer2 equal zero event + generate.\\0: Disable\\1: Enable */ + __IOM uint32_t EVT_TIMER0_TEP_EN : 1; /*!< Configures whether or not to enable timer0 equal period event + generate.\\0: Disable\\1: Enable */ + __IOM uint32_t EVT_TIMER1_TEP_EN : 1; /*!< Configures whether or not to enable timer1 equal period event + generate.\\0: Disable\\1: Enable */ + __IOM uint32_t EVT_TIMER2_TEP_EN : 1; /*!< Configures whether or not to enable timer2 equal period event + generate.\\0: Disable\\1: Enable */ + __IOM uint32_t EVT_OP0_TEA_EN : 1; /*!< Configures whether or not to enable PWM generator0 timer equal + a event generate.\\0: Disable\\1: Enable */ + __IOM uint32_t EVT_OP1_TEA_EN : 1; /*!< Configures whether or not to enable PWM generator1 timer equal + a event generate.\\0: Disable\\1: Enable */ + __IOM uint32_t EVT_OP2_TEA_EN : 1; /*!< Configures whether or not to enable PWM generator2 timer equal + a event generate.\\0: Disable\\1: Enable */ + __IOM uint32_t EVT_OP0_TEB_EN : 1; /*!< Configures whether or not to enable PWM generator0 timer equal + b event generate.\\0: Disable\\1: Enable */ + __IOM uint32_t EVT_OP1_TEB_EN : 1; /*!< Configures whether or not to enable PWM generator1 timer equal + b event generate.\\0: Disable\\1: Enable */ + __IOM uint32_t EVT_OP2_TEB_EN : 1; /*!< Configures whether or not to enable PWM generator2 timer equal + b event generate.\\0: Disable\\1: Enable */ + __IOM uint32_t EVT_F0_EN : 1; /*!< Configures whether or not to enable fault0 event generate.\\0: + Disable\\1: Enable */ + __IOM uint32_t EVT_F1_EN : 1; /*!< Configures whether or not to enable fault1 event generate.\\0: + Disable\\1: Enable */ + __IOM uint32_t EVT_F2_EN : 1; /*!< Configures whether or not to enable fault2 event generate.\\0: + Disable\\1: Enable */ + __IOM uint32_t EVT_F0_CLR_EN : 1; /*!< Configures whether or not to enable fault0 clear event generate.\\0: + Disable\\1: Enable */ + __IOM uint32_t EVT_F1_CLR_EN : 1; /*!< Configures whether or not to enable fault1 clear event generate.\\0: + Disable\\1: Enable */ + __IOM uint32_t EVT_F2_CLR_EN : 1; /*!< Configures whether or not to enable fault2 clear event generate.\\0: + Disable\\1: Enable */ + __IOM uint32_t EVT_TZ0_CBC_EN : 1; /*!< Configures whether or not to enable cycle-by-cycle trip0 event + generate.\\0: Disable\\1: Enable */ + __IOM uint32_t EVT_TZ1_CBC_EN : 1; /*!< Configures whether or not to enable cycle-by-cycle trip1 event + generate.\\0: Disable\\1: Enable */ + __IOM uint32_t EVT_TZ2_CBC_EN : 1; /*!< Configures whether or not to enable cycle-by-cycle trip2 event + generate.\\0: Disable\\1: Enable */ + __IOM uint32_t EVT_TZ0_OST_EN : 1; /*!< Configures whether or not to enable one-shot trip0 event generate.\\0: + Disable\\1: Enable */ + __IOM uint32_t EVT_TZ1_OST_EN : 1; /*!< Configures whether or not to enable one-shot trip1 event generate.\\0: + Disable\\1: Enable */ + __IOM uint32_t EVT_TZ2_OST_EN : 1; /*!< Configures whether or not to enable one-shot trip2 event generate.\\0: + Disable\\1: Enable */ + __IOM uint32_t EVT_CAP0_EN : 1; /*!< Configures whether or not to enable capture0 event generate.\\0: + Disable\\1: Enable */ + __IOM uint32_t EVT_CAP1_EN : 1; /*!< Configures whether or not to enable capture1 event generate.\\0: + Disable\\1: Enable */ + __IOM uint32_t EVT_CAP2_EN : 1; /*!< Configures whether or not to enable capture2 event generate.\\0: + Disable\\1: Enable */ + uint32_t : 2; + } bit; + } EVT_EN; + }; + + union { + __IOM uint32_t GEN1_TSTMP_B; /*!< Generator1 time stamp B's shadow register */ + + union { + __IOM uint32_t reg; /*!< Task enable register */ + + struct { + __IOM uint32_t TASK_CMPR0_A_UP_EN : 1; /*!< Configures whether or not to enable PWM generator0 timer stamp + A's shadow register update task receive.\\0: Disable\\1: + Enable */ + __IOM uint32_t TASK_CMPR1_A_UP_EN : 1; /*!< Configures whether or not to enable PWM generator1 timer stamp + A's shadow register update task receive.\\0: Disable\\1: + Enable */ + __IOM uint32_t TASK_CMPR2_A_UP_EN : 1; /*!< Configures whether or not to enable PWM generator2 timer stamp + A's shadow register update task receive.\\0: Disable\\1: + Enable */ + __IOM uint32_t TASK_CMPR0_B_UP_EN : 1; /*!< Configures whether or not to enable PWM generator0 timer stamp + B's shadow register update task receive.\\0: Disable\\1: + Enable */ + __IOM uint32_t TASK_CMPR1_B_UP_EN : 1; /*!< Configures whether or not to enable PWM generator1 timer stamp + B's shadow register update task receive.\\0: Disable\\1: + Enable */ + __IOM uint32_t TASK_CMPR2_B_UP_EN : 1; /*!< Configures whether or not to enable PWM generator2 timer stamp + B's shadow register update task receive.\\0: Disable\\1: + Enable */ + __IOM uint32_t TASK_GEN_STOP_EN : 1; /*!< Configures whether or not to enable all PWM generate stop task + receive.\\0: Disable\\1: Enable */ + __IOM uint32_t TASK_TIMER0_SYNC_EN : 1; /*!< Configures whether or not to enable timer0 sync task receive.\\0: + Disable\\1: Enable */ + __IOM uint32_t TASK_TIMER1_SYNC_EN : 1; /*!< Configures whether or not to enable timer1 sync task receive.\\0: + Disable\\1: Enable */ + __IOM uint32_t TASK_TIMER2_SYNC_EN : 1; /*!< Configures whether or not to enable timer2 sync task receive.\\0: + Disable\\1: Enable */ + __IOM uint32_t TASK_TIMER0_PERIOD_UP_EN : 1;/*!< Configures whether or not to enable timer0 period update task + receive.\\0: Disable\\1: Enable */ + __IOM uint32_t TASK_TIMER1_PERIOD_UP_EN : 1;/*!< Configures whether or not to enable timer1 period update task + receive.\\0: Disable\\1: Enable */ + __IOM uint32_t TASK_TIMER2_PERIOD_UP_EN : 1;/*!< Configures whether or not to enable timer2 period update task + receive.\\0: Disable\\1: Enable */ + __IOM uint32_t TASK_TZ0_OST_EN : 1; /*!< Configures whether or not to enable one shot trip0 task receive.\\0: + Disable\\1: Enable */ + __IOM uint32_t TASK_TZ1_OST_EN : 1; /*!< Configures whether or not to enable one shot trip1 task receive.\\0: + Disable\\1: Enable */ + __IOM uint32_t TASK_TZ2_OST_EN : 1; /*!< Configures whether or not to enable one shot trip2 task receive.\\0: + Disable\\1: Enable */ + __IOM uint32_t TASK_CLR0_OST_EN : 1; /*!< Configures whether or not to enable one shot trip0 clear task + receive.\\0: Disable\\1: Enable */ + __IOM uint32_t TASK_CLR1_OST_EN : 1; /*!< Configures whether or not to enable one shot trip1 clear task + receive.\\0: Disable\\1: Enable */ + __IOM uint32_t TASK_CLR2_OST_EN : 1; /*!< Configures whether or not to enable one shot trip2 clear task + receive.\\0: Disable\\1: Enable */ + __IOM uint32_t TASK_CAP0_EN : 1; /*!< Configures whether or not to enable capture0 task receive.\\0: + Disable\\1: Enable */ + __IOM uint32_t TASK_CAP1_EN : 1; /*!< Configures whether or not to enable capture1 task receive.\\0: + Disable\\1: Enable */ + __IOM uint32_t TASK_CAP2_EN : 1; /*!< Configures whether or not to enable capture2 task receive.\\0: + Disable\\1: Enable */ + uint32_t : 10; + } bit; + } TASK_EN; + }; + + union { + __IOM uint32_t GEN1_CFG0; /*!< Generator1 fault event T0 and T1 configuration register */ + + union { + __IOM uint32_t reg; /*!< Event enable register2 */ + + struct { + __IOM uint32_t EVT_OP0_TEE1_EN : 1; /*!< Configures whether or not to enable PWM generator0 timer equal + OP0_TSTMP_E1_REG event generate.\\0: Disable\\1: Enable */ + __IOM uint32_t EVT_OP1_TEE1_EN : 1; /*!< Configures whether or not to enable PWM generator1 timer equal + OP1_TSTMP_E1_REG event generate.\\0: Disable\\1: Enable */ + __IOM uint32_t EVT_OP2_TEE1_EN : 1; /*!< Configures whether or not to enable PWM generator2 timer equal + OP2_TSTMP_E1_REG event generate.\\0: Disable\\1: Enable */ + __IOM uint32_t EVT_OP0_TEE2_EN : 1; /*!< Configures whether or not to enable PWM generator0 timer equal + OP0_TSTMP_E2_REG event generate.\\0: Disable\\1: Enable */ + __IOM uint32_t EVT_OP1_TEE2_EN : 1; /*!< Configures whether or not to enable PWM generator1 timer equal + OP1_TSTMP_E2_REG event generate.\\0: Disable\\1: Enable */ + __IOM uint32_t EVT_OP2_TEE2_EN : 1; /*!< Configures whether or not to enable PWM generator2 timer equal + OP2_TSTMP_E2_REG event generate.\\0: Disable\\1: Enable */ + uint32_t : 26; + } bit; + } EVT_EN2; + }; + + union { + __IOM uint32_t GEN1_FORCE; /*!< Generator1 output signal force mode register. */ + __IOM uint32_t OP0_TSTMP_E1; /*!< Generator0 timer stamp E1 value register */ + }; + + union { + __IOM uint32_t GEN1_A; /*!< PWM1 output signal A actions configuration register */ + __IOM uint32_t OP0_TSTMP_E2; /*!< Generator0 timer stamp E2 value register */ + }; + __IOM uint32_t GEN1_B; /*!< PWM1 output signal B actions configuration register */ + + union { + __IOM uint32_t reg; /*!< Dead time configuration register */ + + struct { + __IOM uint32_t DB_FED_UPMETHOD : 4; /*!< Configures update method for FED (Falling edge delay) active + register.\\0: Immediate\\Bit0 is set to 1: TEZ\\Bit1 is + set to 1: TEP\\Bit2 is set to 1: Sync\\Bit3 is set to 1: + Disable the update */ + __IOM uint32_t DB_RED_UPMETHOD : 4; /*!< Configures update method for RED (rising edge delay) active + register.\\0: Immediate\\Bit0 is set to 1: TEZ\\Bit1 is + set to 1: TEP\\Bit2 is set to 1: Sync\\Bit3 is set to 1: + Disable the update */ + __IOM uint32_t DB_DEB_MODE : 1; /*!< Configures S8 in table, dual-edge B mode.\\0: fed/red take effect + on different path separately\\1: fed/red take effect on + B path, A out is in bypass or dulpB mode */ + __IOM uint32_t DB_A_OUTSWAP : 1; /*!< Configures S6 in table. */ + __IOM uint32_t DB_B_OUTSWAP : 1; /*!< Configures S7 in table. */ + __IOM uint32_t DB_RED_INSEL : 1; /*!< Configures S4 in table. */ + __IOM uint32_t DB_FED_INSEL : 1; /*!< Configures S5 in table. */ + __IOM uint32_t DB_RED_OUTINVERT : 1; /*!< Configures S2 in table. */ + __IOM uint32_t DB_FED_OUTINVERT : 1; /*!< Configures S3 in table. */ + __IOM uint32_t DB_A_OUTBYPASS : 1; /*!< Configures S1 in table. */ + __IOM uint32_t DB_B_OUTBYPASS : 1; /*!< Configures S0 in table. */ + uint32_t : 15; + } bit; + } DT1_CFG; + + union { + __IOM uint32_t reg; /*!< Falling edge delay (FED) shadow register */ + + struct { + __IOM uint32_t DB_FED : 16; /*!< Configures shadow register for FED. */ + uint32_t : 16; + } bit; + } DT1_FED_CFG; + + union { + __IOM uint32_t reg; /*!< Rising edge delay (RED) shadow register */ + + struct { + __IOM uint32_t DB_RED : 16; /*!< Configures shadow register for RED. */ + uint32_t : 16; + } bit; + } DT1_RED_CFG; + + union { + union { + __IOM uint32_t reg; /*!< Carrier1 configuration register */ + + struct { + uint32_t : 8; + __IOM uint32_t CHOPPER_OSHTWTH : 4; /*!< Configures width of the first pulse. Measurement unit: Periods + of the carrier. */ + uint32_t : 20; + } bit; + } CARRIER1_CFG; + + union { + __IOM uint32_t reg; /*!< Global configuration register */ + + struct { + __IOM uint32_t EN : 1; /*!< Configures whether or not to open register clock gate.\\0: Open + the clock gate only when application writes registers\\1: + Force open the clock gate for register */ + uint32_t : 31; + } bit; + } CLK; + }; + + union { + __IOM uint32_t reg; /*!< Version register. */ + + struct { + __IOM uint32_t DATE : 28; /*!< Configures the version. */ + uint32_t : 4; + } bit; + } VERSION; + + union { + union { + __IOM uint32_t reg; /*!< Software triggers for fault handler actions configuration register */ + + struct { + __IOM uint32_t TZ_CLR_OST : 1; /*!< Configures the generation of software one-shot mode action clear. + A toggle (software negate its value) triggers a clear for + on going one-shot mode action. */ + __IOM uint32_t TZ_CBCPULSE : 2; /*!< Configures the refresh moment selection of cycle-by-cycle mode + action.\\0: Select nothing, will not refresh\\Bit0 is set + to 1: TEZ\\Bit1 is set to 1: TEP */ + __IOM uint32_t TZ_FORCE_CBC : 1; /*!< Configures the generation of software cycle-by-cycle mode action. + A toggle (software negate its value) triggers a cycle-by-cycle + mode action. */ + __IOM uint32_t TZ_FORCE_OST : 1; /*!< Configures the generation of software one-shot mode action. + A toggle (software negate its value) triggers a one-shot + mode action. */ + uint32_t : 27; + } bit; + } FH1_CFG1; + __IOM uint32_t OP1_TSTMP_E1; /*!< Generator1 timer stamp E1 value register */ + }; + + union { + union { + __IOM uint32_t reg; /*!< Fault events status register */ + + struct { + __IM uint32_t TZ_CBC_ON : 1; /*!< Represents whether or not an cycle-by-cycle mode action is on + going.\\0:No action\\1: On going */ + __IM uint32_t TZ_OST_ON : 1; /*!< Represents whether or not an one-shot mode action is on going.\\0:No + action\\1: On going */ + uint32_t : 30; + } bit; + } FH1_STATUS; + __IOM uint32_t OP1_TSTMP_E2; /*!< Generator1 timer stamp E2 value register */ + }; + __IM uint32_t RESERVED6[6]; + __IOM uint32_t OP2_TSTMP_E1; /*!< Generator2 timer stamp E1 value register */ + __IOM uint32_t OP2_TSTMP_E2; /*!< Generator2 timer stamp E2 value register */ + __IM uint32_t RESERVED7[34]; + __IOM uint32_t GEN2_STMP_CFG; /*!< Generator2 time stamp registers A and B transfer status and + update method register */ + __IOM uint32_t GEN2_TSTMP_A; /*!< Generator2 time stamp A's shadow register */ + __IOM uint32_t GEN2_TSTMP_B; /*!< Generator2 time stamp B's shadow register */ + __IOM uint32_t GEN2_CFG0; /*!< Generator2 fault event T0 and T1 configuration register */ + __IOM uint32_t GEN2_FORCE; /*!< Generator2 output signal force mode register. */ + __IOM uint32_t GEN2_A; /*!< PWM2 output signal A actions configuration register */ + __IOM uint32_t GEN2_B; /*!< PWM2 output signal B actions configuration register */ + + union { + __IOM uint32_t reg; /*!< Dead time configuration register */ + + struct { + __IOM uint32_t DB_FED_UPMETHOD : 4; /*!< Configures update method for FED (Falling edge delay) active + register.\\0: Immediate\\Bit0 is set to 1: TEZ\\Bit1 is + set to 1: TEP\\Bit2 is set to 1: Sync\\Bit3 is set to 1: + Disable the update */ + __IOM uint32_t DB_RED_UPMETHOD : 4; /*!< Configures update method for RED (rising edge delay) active + register.\\0: Immediate\\Bit0 is set to 1: TEZ\\Bit1 is + set to 1: TEP\\Bit2 is set to 1: Sync\\Bit3 is set to 1: + Disable the update */ + __IOM uint32_t DB_DEB_MODE : 1; /*!< Configures S8 in table, dual-edge B mode.\\0: fed/red take effect + on different path separately\\1: fed/red take effect on + B path, A out is in bypass or dulpB mode */ + __IOM uint32_t DB_A_OUTSWAP : 1; /*!< Configures S6 in table. */ + __IOM uint32_t DB_B_OUTSWAP : 1; /*!< Configures S7 in table. */ + __IOM uint32_t DB_RED_INSEL : 1; /*!< Configures S4 in table. */ + __IOM uint32_t DB_FED_INSEL : 1; /*!< Configures S5 in table. */ + __IOM uint32_t DB_RED_OUTINVERT : 1; /*!< Configures S2 in table. */ + __IOM uint32_t DB_FED_OUTINVERT : 1; /*!< Configures S3 in table. */ + __IOM uint32_t DB_A_OUTBYPASS : 1; /*!< Configures S1 in table. */ + __IOM uint32_t DB_B_OUTBYPASS : 1; /*!< Configures S0 in table. */ + uint32_t : 15; + } bit; + } DT2_CFG; + + union { + __IOM uint32_t reg; /*!< Falling edge delay (FED) shadow register */ + + struct { + __IOM uint32_t DB_FED : 16; /*!< Configures shadow register for FED. */ + uint32_t : 16; + } bit; + } DT2_FED_CFG; + + union { + __IOM uint32_t reg; /*!< Rising edge delay (RED) shadow register */ + + struct { + __IOM uint32_t DB_RED : 16; /*!< Configures shadow register for RED. */ + uint32_t : 16; + } bit; + } DT2_RED_CFG; + + union { + __IOM uint32_t reg; /*!< Carrier2 configuration register */ + + struct { + uint32_t : 8; + __IOM uint32_t CHOPPER_OSHTWTH : 4; /*!< Configures width of the first pulse. Measurement unit: Periods + of the carrier. */ + uint32_t : 20; + } bit; + } CARRIER2_CFG; + __IM uint32_t RESERVED8; + + union { + __IOM uint32_t reg; /*!< Software triggers for fault handler actions configuration register */ + + struct { + __IOM uint32_t TZ_CLR_OST : 1; /*!< Configures the generation of software one-shot mode action clear. + A toggle (software negate its value) triggers a clear for + on going one-shot mode action. */ + __IOM uint32_t TZ_CBCPULSE : 2; /*!< Configures the refresh moment selection of cycle-by-cycle mode + action.\\0: Select nothing, will not refresh\\Bit0 is set + to 1: TEZ\\Bit1 is set to 1: TEP */ + __IOM uint32_t TZ_FORCE_CBC : 1; /*!< Configures the generation of software cycle-by-cycle mode action. + A toggle (software negate its value) triggers a cycle-by-cycle + mode action. */ + __IOM uint32_t TZ_FORCE_OST : 1; /*!< Configures the generation of software one-shot mode action. + A toggle (software negate its value) triggers a one-shot + mode action. */ + uint32_t : 27; + } bit; + } FH2_CFG1; + + union { + __IOM uint32_t reg; /*!< Fault events status register */ + + struct { + __IM uint32_t TZ_CBC_ON : 1; /*!< Represents whether or not an cycle-by-cycle mode action is on + going.\\0:No action\\1: On going */ + __IM uint32_t TZ_OST_ON : 1; /*!< Represents whether or not an one-shot mode action is on going.\\0:No + action\\1: On going */ + uint32_t : 30; + } bit; + } FH2_STATUS; +} MCPWM0_Type; /*!< Size = 564 (0x234) */ + + + +/* =========================================================================================================================== */ +/* ================ PARL_IO ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Parallel IO Controller (PARL_IO) + */ + +typedef struct { /*!< PARL_IO Structure */ + + union { + __IOM uint32_t reg; /*!< Parallel RX Sampling mode configuration register. */ + + struct { + uint32_t : 21; + __IOM uint32_t RX_EXT_EN_SEL : 4; /*!< Configures rx external enable signal selection from IO PAD. */ + __IOM uint32_t RX_SW_EN : 1; /*!< Set this bit to enable data sampling by software. */ + __IOM uint32_t RX_EXT_EN_INV : 1; /*!< Set this bit to invert the external enable signal. */ + __IOM uint32_t RX_PULSE_SUBMODE_SEL : 3; /*!< Configures the rxd pulse sampling submode. 4'd0: positive pulse + start(data bit included) && positive pulse end(data bit + included)4'd1: positive pulse start(data bit included) + && positive pulse end (data bit excluded)4'd2: positive + pulse start(data bit excluded) && positive pulse end (data + bit included)4'd3: positive pulse start(data bit excluded) + && positive pulse end (data bit excluded)4'd4: positive + pulse start(data bit included) && length end4'd5: positive + pulse start(data bit excluded) && length end */ + __IOM uint32_t RX_SMP_MODE_SEL : 2; /*!< Configures the rxd sampling mode. 2'b00: external level enable + mode2'b01: external pulse enable mode 2'b10: internal software + enable mode */ + } bit; + } RX_MODE_CFG; + + union { + __IOM uint32_t reg; /*!< Parallel RX data configuration register. */ + + struct { + uint32_t : 9; + __IOM uint32_t RX_BITLEN : 19; /*!< Configures expected byte number of received data. */ + __IOM uint32_t RX_DATA_ORDER_INV : 1; /*!< Set this bit to invert bit order of one byte sent from RX_FIFO + to DMA. */ + __IOM uint32_t RX_BUS_WID_SEL : 3; /*!< Configures the rxd bus width. 3'd0: bus width is 1.3'd1: bus + width is 2.3'd2: bus width is 4.3'd3: bus width is 8. */ + } bit; + } RX_DATA_CFG; + + union { + __IOM uint32_t reg; /*!< Parallel RX general configuration register. */ + + struct { + uint32_t : 12; + __IOM uint32_t RX_GATING_EN : 1; /*!< Set this bit to enable the clock gating of output rx clock. */ + __IOM uint32_t RX_TIMEOUT_THRES : 16; /*!< Configures threshold of timeout counter. */ + __IOM uint32_t RX_TIMEOUT_EN : 1; /*!< Set this bit to enable timeout function to generate error eof. */ + __IOM uint32_t RX_EOF_GEN_SEL : 1; /*!< Configures the DMA eof generated mechanism. 1'b0: eof generated + by data bit length. 1'b1: eof generated by external enable + signal. */ + uint32_t : 1; + } bit; + } RX_GENRL_CFG; + + union { + __IOM uint32_t reg; /*!< Parallel RX Start configuration register. */ + + struct { + uint32_t : 31; + __IOM uint32_t RX_START : 1; /*!< Set this bit to start rx data sampling. */ + } bit; + } RX_START_CFG; + + union { + __IOM uint32_t reg; /*!< Parallel TX data configuration register. */ + + struct { + uint32_t : 9; + __IOM uint32_t TX_BITLEN : 19; /*!< Configures expected byte number of sent data. */ + __IOM uint32_t TX_DATA_ORDER_INV : 1; /*!< Set this bit to invert bit order of one byte sent from TX_FIFO + to IO data. */ + __IOM uint32_t TX_BUS_WID_SEL : 3; /*!< Configures the txd bus width. 3'd0: bus width is 1.3'd1: bus + width is 2.3'd2: bus width is 4.3'd3: bus width is 8. */ + } bit; + } TX_DATA_CFG; + + union { + __IOM uint32_t reg; /*!< Parallel TX Start configuration register. */ + + struct { + uint32_t : 31; + __IOM uint32_t TX_START : 1; /*!< Set this bit to start tx data transmit. */ + } bit; + } TX_START_CFG; + + union { + __IOM uint32_t reg; /*!< Parallel TX general configuration register. */ + + struct { + uint32_t : 13; + __IOM uint32_t TX_EOF_GEN_SEL : 1; /*!< Configures the tx eof generated mechanism. 1'b0: eof generated + by data bit length. 1'b1: eof generated by DMA eof. */ + __IOM uint32_t TX_IDLE_VALUE : 16; /*!< Configures bus value of transmitter in IDLE state. */ + __IOM uint32_t TX_GATING_EN : 1; /*!< Set this bit to enable the clock gating of output tx clock. */ + __IOM uint32_t TX_VALID_OUTPUT_EN : 1; /*!< Set this bit to enable the output of tx data valid signal. */ + } bit; + } TX_GENRL_CFG; + + union { + __IOM uint32_t reg; /*!< Parallel IO FIFO configuration register. */ + + struct { + uint32_t : 30; + __IOM uint32_t TX_FIFO_SRST : 1; /*!< Set this bit to reset async fifo in tx module. */ + __IOM uint32_t RX_FIFO_SRST : 1; /*!< Set this bit to reset async fifo in rx module. */ + } bit; + } FIFO_CFG; + + union { + __IOM uint32_t reg; /*!< Parallel IO FIFO configuration register. */ + + struct { + uint32_t : 31; + __OM uint32_t RX_REG_UPDATE : 1; /*!< Set this bit to update rx register configuration. */ + } bit; + } REG_UPDATE; + + union { + __IOM uint32_t reg; /*!< Parallel IO module status register0. */ + + struct { + uint32_t : 31; + __IM uint32_t TX_READY : 1; /*!< Represents the status that tx is ready to transmit. */ + } bit; + } ST; + + union { + __IOM uint32_t reg; /*!< Parallel IO interrupt enable singal configuration register. */ + + struct { + __IOM uint32_t TX_FIFO_REMPTY_INT_ENA : 1;/*!< Set this bit to enable TX_FIFO_REMPTY_INT. */ + __IOM uint32_t RX_FIFO_WOVF_INT_ENA : 1; /*!< Set this bit to enable RX_FIFO_WOVF_INT. */ + __IOM uint32_t TX_EOF_INT_ENA : 1; /*!< Set this bit to enable TX_EOF_INT. */ + uint32_t : 29; + } bit; + } INT_ENA; + + union { + __IOM uint32_t reg; /*!< Parallel IO interrupt raw singal status register. */ + + struct { + __IOM uint32_t TX_FIFO_REMPTY_INT_RAW : 1;/*!< The raw interrupt status of TX_FIFO_REMPTY_INT. */ + __IOM uint32_t RX_FIFO_WOVF_INT_RAW : 1; /*!< The raw interrupt status of RX_FIFO_WOVF_INT. */ + __IOM uint32_t TX_EOF_INT_RAW : 1; /*!< The raw interrupt status of TX_EOF_INT. */ + uint32_t : 29; + } bit; + } INT_RAW; + + union { + __IOM uint32_t reg; /*!< Parallel IO interrupt singal status register. */ + + struct { + __IM uint32_t TX_FIFO_REMPTY_INT_ST : 1; /*!< The masked interrupt status of TX_FIFO_REMPTY_INT. */ + __IM uint32_t RX_FIFO_WOVF_INT_ST : 1; /*!< The masked interrupt status of RX_FIFO_WOVF_INT. */ + __IM uint32_t TX_EOF_INT_ST : 1; /*!< The masked interrupt status of TX_EOF_INT. */ + uint32_t : 29; + } bit; + } INT_ST; + + union { + __IOM uint32_t reg; /*!< Parallel IO interrupt clear singal configuration register. */ + + struct { + __OM uint32_t TX_FIFO_REMPTY_INT_CLR : 1;/*!< Set this bit to clear TX_FIFO_REMPTY_INT. */ + __OM uint32_t RX_FIFO_WOVF_INT_CLR : 1; /*!< Set this bit to clear RX_FIFO_WOVF_INT. */ + __OM uint32_t TX_EOF_INT_CLR : 1; /*!< Set this bit to clear TX_EOF_INT. */ + uint32_t : 29; + } bit; + } INT_CLR; + + union { + __IOM uint32_t reg; /*!< Parallel IO RX status register0 */ + + struct { + uint32_t : 8; + __IM uint32_t RX_CNT : 5; /*!< Indicates the cycle number of reading Rx FIFO. */ + __IM uint32_t RX_FIFO_WR_BIT_CNT : 19; /*!< Indicates the current written bit number into Rx FIFO. */ + } bit; + } RX_ST0; + + union { + __IOM uint32_t reg; /*!< Parallel IO RX status register1 */ + + struct { + uint32_t : 13; + __IM uint32_t RX_FIFO_RD_BIT_CNT : 19; /*!< Indicates the current read bit number from Rx FIFO. */ + } bit; + } RX_ST1; + + union { + __IOM uint32_t reg; /*!< Parallel IO TX status register0 */ + + struct { + uint32_t : 6; + __IM uint32_t TX_CNT : 7; /*!< Indicates the cycle number of reading Tx FIFO. */ + __IM uint32_t TX_FIFO_RD_BIT_CNT : 19; /*!< Indicates the current read bit number from Tx FIFO. */ + } bit; + } TX_ST0; + + union { + __IOM uint32_t reg; /*!< Parallel IO RX clk configuration register */ + + struct { + uint32_t : 30; + __IOM uint32_t RX_CLK_I_INV : 1; /*!< Set this bit to invert the input Rx core clock. */ + __IOM uint32_t RX_CLK_O_INV : 1; /*!< Set this bit to invert the output Rx core clock. */ + } bit; + } RX_CLK_CFG; + + union { + __IOM uint32_t reg; /*!< Parallel IO TX clk configuration register */ + + struct { + uint32_t : 30; + __IOM uint32_t TX_CLK_I_INV : 1; /*!< Set this bit to invert the input Tx core clock. */ + __IOM uint32_t TX_CLK_O_INV : 1; /*!< Set this bit to invert the output Tx core clock. */ + } bit; + } TX_CLK_CFG; + __IM uint32_t RESERVED[53]; + + union { + __IOM uint32_t reg; /*!< Parallel IO clk configuration register */ + + struct { + uint32_t : 31; + __IOM uint32_t EN : 1; /*!< Force clock on for this register file */ + } bit; + } CLK; + __IM uint32_t RESERVED1[182]; + + union { + __IOM uint32_t reg; /*!< Version register. */ + + struct { + __IOM uint32_t DATE : 28; /*!< Version of this register file */ + uint32_t : 4; + } bit; + } VERSION; +} PARL_IO_Type; /*!< Size = 1024 (0x400) */ + + + +/* =========================================================================================================================== */ +/* ================ PAU ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief PAU Peripheral (PAU) + */ + +typedef struct { /*!< PAU Structure */ + + union { + __IOM uint32_t reg; /*!< Peri backup control register */ + + struct { + __IM uint32_t FLOW_ERR : 3; /*!< backup error type */ + __OM uint32_t START : 1; /*!< backup start signal */ + __IOM uint32_t TO_MEM : 1; /*!< backup direction(reg to mem / mem to reg) */ + __IOM uint32_t LINK_SEL : 2; /*!< Link select */ + __OM uint32_t START_MAC : 1; /*!< mac sw backup start signal */ + __IOM uint32_t TO_MEM_MAC : 1; /*!< mac sw backup direction(reg to mem / mem to reg) */ + __IOM uint32_t SEL_MAC : 1; /*!< mac hw/sw select */ + uint32_t : 22; + } bit; + } REGDMA_CONF; + + union { + __IOM uint32_t reg; /*!< Clock control register */ + + struct { + __IOM uint32_t CLK_EN : 1; /*!< clock enable */ + uint32_t : 31; + } bit; + } REGDMA_CLK_CONF; + + union { + __IOM uint32_t reg; /*!< ETM start ctrl reg */ + + struct { + __OM uint32_t ETM_START_0 : 1; /*!< etm_start_0 reg */ + __OM uint32_t ETM_START_1 : 1; /*!< etm_start_1 reg */ + __OM uint32_t ETM_START_2 : 1; /*!< etm_start_2 reg */ + __OM uint32_t ETM_START_3 : 1; /*!< etm_start_3 reg */ + uint32_t : 28; + } bit; + } REGDMA_ETM_CTRL; + + union { + __IOM uint32_t reg; /*!< link_0_addr */ + + struct { + __IOM uint32_t LINK_ADDR_0 : 32; /*!< link_0_addr reg */ + } bit; + } REGDMA_LINK_0_ADDR; + + union { + __IOM uint32_t reg; /*!< Link_1_addr */ + + struct { + __IOM uint32_t LINK_ADDR_1 : 32; /*!< Link_1_addr reg */ + } bit; + } REGDMA_LINK_1_ADDR; + + union { + __IOM uint32_t reg; /*!< Link_2_addr */ + + struct { + __IOM uint32_t LINK_ADDR_2 : 32; /*!< Link_2_addr reg */ + } bit; + } REGDMA_LINK_2_ADDR; + + union { + __IOM uint32_t reg; /*!< Link_3_addr */ + + struct { + __IOM uint32_t LINK_ADDR_3 : 32; /*!< Link_3_addr reg */ + } bit; + } REGDMA_LINK_3_ADDR; + + union { + __IOM uint32_t reg; /*!< Link_mac_addr */ + + struct { + __IOM uint32_t LINK_ADDR_MAC : 32; /*!< Link_mac_addr reg */ + } bit; + } REGDMA_LINK_MAC_ADDR; + + union { + __IOM uint32_t reg; /*!< current link addr */ + + struct { + __IM uint32_t CURRENT_LINK_ADDR : 32; /*!< current link addr reg */ + } bit; + } REGDMA_CURRENT_LINK_ADDR; + + union { + __IOM uint32_t reg; /*!< Backup addr */ + + struct { + __IM uint32_t BACKUP_ADDR : 32; /*!< backup addr reg */ + } bit; + } REGDMA_BACKUP_ADDR; + + union { + __IOM uint32_t reg; /*!< mem addr */ + + struct { + __IM uint32_t MEM_ADDR : 32; /*!< mem addr reg */ + } bit; + } REGDMA_MEM_ADDR; + + union { + __IOM uint32_t reg; /*!< backup config */ + + struct { + __IOM uint32_t READ_INTERVAL : 7; /*!< Link read_interval */ + __IOM uint32_t LINK_TOUT_THRES : 10; /*!< link wait timeout threshold */ + __IOM uint32_t BURST_LIMIT : 5; /*!< burst limit */ + __IOM uint32_t BACKUP_TOUT_THRES : 10; /*!< Backup timeout threshold */ + } bit; + } REGDMA_BKP_CONF; + + union { + __IOM uint32_t reg; /*!< Read only register for error and done */ + + struct { + __IOM uint32_t DONE_INT_ENA : 1; /*!< backup done flag */ + __IOM uint32_t ERROR_INT_ENA : 1; /*!< error flag */ + uint32_t : 30; + } bit; + } INT_ENA; + + union { + __IOM uint32_t reg; /*!< Read only register for error and done */ + + struct { + __IOM uint32_t DONE_INT_RAW : 1; /*!< backup done flag */ + __IOM uint32_t ERROR_INT_RAW : 1; /*!< error flag */ + uint32_t : 30; + } bit; + } INT_RAW; + + union { + __IOM uint32_t reg; /*!< Read only register for error and done */ + + struct { + __OM uint32_t DONE_INT_CLR : 1; /*!< backup done flag */ + __OM uint32_t ERROR_INT_CLR : 1; /*!< error flag */ + uint32_t : 30; + } bit; + } INT_CLR; + + union { + __IOM uint32_t reg; /*!< Read only register for error and done */ + + struct { + __IM uint32_t DONE_INT_ST : 1; /*!< backup done flag */ + __IM uint32_t ERROR_INT_ST : 1; /*!< error flag */ + uint32_t : 30; + } bit; + } INT_ST; + __IM uint32_t RESERVED[239]; + + union { + __IOM uint32_t reg; /*!< Date register. */ + + struct { + __IOM uint32_t DATE : 28; /*!< REGDMA date information/ REGDMA version information. */ + uint32_t : 4; + } bit; + } DATE; +} PAU_Type; /*!< Size = 1024 (0x400) */ + + + +/* =========================================================================================================================== */ +/* ================ PCNT ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Pulse Count Controller (PCNT) + */ + +typedef struct { /*!< PCNT Structure */ + + union { + __IOM uint32_t reg; /*!< Configuration register 0 for unit 0 */ + + struct { + __IOM uint32_t FILTER_THRES_U : 10; /*!< This sets the maximum threshold, in APB_CLK cycles, for the + filter.Any pulses with width less than this will be ignored + when the filter is enabled. */ + uint32_t : 6; + __IOM uint32_t CH0_NEG_MODE_U : 2; /*!< This register sets the behavior when the signal input of channel + 0 detects a negative edge.1: Increase the counter.2: Decrease + the counter.0, 3: No effect on counter */ + __IOM uint32_t CH0_POS_MODE_U : 2; /*!< This register sets the behavior when the signal input of channel + 0 detects a positive edge.1: Increase the counter.2: Decrease + the counter.0, 3: No effect on counter */ + uint32_t : 4; + __IOM uint32_t CH1_NEG_MODE_U : 2; /*!< This register sets the behavior when the signal input of channel + 1 detects a negative edge.1: Increment the counter.2: Decrement + the counter.0, 3: No effect on counter */ + __IOM uint32_t CH1_POS_MODE_U : 2; /*!< This register sets the behavior when the signal input of channel + 1 detects a positive edge.1: Increment the counter.2: Decrement + the counter.0, 3: No effect on counter */ + uint32_t : 4; + } bit; + } U0_CONF0; + __IOM uint32_t U0_CONF1; /*!< Configuration register 1 for unit 0 */ + __IOM uint32_t U0_CONF2; /*!< Configuration register 2 for unit 0 */ + __IM uint32_t RESERVED[9]; + + union { + union { + __IOM uint32_t reg; /*!< Configuration register 0 for unit 1 */ + + struct { + __IOM uint32_t FILTER_THRES_U : 10; /*!< This sets the maximum threshold, in APB_CLK cycles, for the + filter.Any pulses with width less than this will be ignored + when the filter is enabled. */ + uint32_t : 6; + __IOM uint32_t CH0_NEG_MODE_U : 2; /*!< This register sets the behavior when the signal input of channel + 0 detects a negative edge.1: Increase the counter.2: Decrease + the counter.0, 3: No effect on counter */ + __IOM uint32_t CH0_POS_MODE_U : 2; /*!< This register sets the behavior when the signal input of channel + 0 detects a positive edge.1: Increase the counter.2: Decrease + the counter.0, 3: No effect on counter */ + uint32_t : 4; + __IOM uint32_t CH1_NEG_MODE_U : 2; /*!< This register sets the behavior when the signal input of channel + 1 detects a negative edge.1: Increment the counter.2: Decrement + the counter.0, 3: No effect on counter */ + __IOM uint32_t CH1_POS_MODE_U : 2; /*!< This register sets the behavior when the signal input of channel + 1 detects a positive edge.1: Increment the counter.2: Decrement + the counter.0, 3: No effect on counter */ + uint32_t : 4; + } bit; + } U1_CONF0; + __IOM uint32_t U0_CNT; /*!< Counter value for unit 0 */ + }; + __IOM uint32_t U1_CONF1; /*!< Configuration register 1 for unit 1 */ + __IOM uint32_t U1_CONF2; /*!< Configuration register 2 for unit 1 */ + __IM uint32_t RESERVED1; + + union { + __IOM uint32_t U1_CNT; /*!< Counter value for unit 1 */ + + union { + __IOM uint32_t reg; /*!< Interrupt raw status register */ + + struct { + __IOM uint32_t CNT_THR_EVENT_U0_INT_RAW : 1;/*!< The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT + interrupt. */ + __IOM uint32_t CNT_THR_EVENT_U1_INT_RAW : 1;/*!< The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT + interrupt. */ + __IOM uint32_t CNT_THR_EVENT_U2_INT_RAW : 1;/*!< The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT + interrupt. */ + __IOM uint32_t CNT_THR_EVENT_U3_INT_RAW : 1;/*!< The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT + interrupt. */ + uint32_t : 28; + } bit; + } INT_RAW; + }; + + union { + __IOM uint32_t reg; /*!< Interrupt status register */ + + struct { + __IM uint32_t CNT_THR_EVENT_U0_INT_ST : 1;/*!< The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT + interrupt. */ + __IM uint32_t CNT_THR_EVENT_U1_INT_ST : 1;/*!< The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT + interrupt. */ + __IM uint32_t CNT_THR_EVENT_U2_INT_ST : 1;/*!< The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT + interrupt. */ + __IM uint32_t CNT_THR_EVENT_U3_INT_ST : 1;/*!< The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT + interrupt. */ + uint32_t : 28; + } bit; + } INT_ST; + + union { + __IOM uint32_t reg; /*!< Interrupt enable register */ + + struct { + __IOM uint32_t CNT_THR_EVENT_U0_INT_ENA : 1;/*!< The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. */ + __IOM uint32_t CNT_THR_EVENT_U1_INT_ENA : 1;/*!< The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. */ + __IOM uint32_t CNT_THR_EVENT_U2_INT_ENA : 1;/*!< The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. */ + __IOM uint32_t CNT_THR_EVENT_U3_INT_ENA : 1;/*!< The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. */ + uint32_t : 28; + } bit; + } INT_ENA; + + union { + __IOM uint32_t reg; /*!< Interrupt clear register */ + + struct { + __OM uint32_t CNT_THR_EVENT_U0_INT_CLR : 1;/*!< Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt. */ + __OM uint32_t CNT_THR_EVENT_U1_INT_CLR : 1;/*!< Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt. */ + __OM uint32_t CNT_THR_EVENT_U2_INT_CLR : 1;/*!< Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt. */ + __OM uint32_t CNT_THR_EVENT_U3_INT_CLR : 1;/*!< Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt. */ + uint32_t : 28; + } bit; + } INT_CLR; + + union { + __IOM uint32_t U2_CNT; /*!< Counter value for unit 2 */ + __IOM uint32_t U0_STATUS; /*!< PNCT UNIT0 status register */ + }; + __IM uint32_t RESERVED2[3]; + + union { + union { + __IOM uint32_t reg; /*!< Configuration register 0 for unit 2 */ + + struct { + __IOM uint32_t FILTER_THRES_U : 10; /*!< This sets the maximum threshold, in APB_CLK cycles, for the + filter.Any pulses with width less than this will be ignored + when the filter is enabled. */ + uint32_t : 6; + __IOM uint32_t CH0_NEG_MODE_U : 2; /*!< This register sets the behavior when the signal input of channel + 0 detects a negative edge.1: Increase the counter.2: Decrease + the counter.0, 3: No effect on counter */ + __IOM uint32_t CH0_POS_MODE_U : 2; /*!< This register sets the behavior when the signal input of channel + 0 detects a positive edge.1: Increase the counter.2: Decrease + the counter.0, 3: No effect on counter */ + uint32_t : 4; + __IOM uint32_t CH1_NEG_MODE_U : 2; /*!< This register sets the behavior when the signal input of channel + 1 detects a negative edge.1: Increment the counter.2: Decrement + the counter.0, 3: No effect on counter */ + __IOM uint32_t CH1_POS_MODE_U : 2; /*!< This register sets the behavior when the signal input of channel + 1 detects a positive edge.1: Increment the counter.2: Decrement + the counter.0, 3: No effect on counter */ + uint32_t : 4; + } bit; + } U2_CONF0; + __IOM uint32_t U3_CNT; /*!< Counter value for unit 3 */ + __IOM uint32_t U1_STATUS; /*!< PNCT UNIT1 status register */ + + union { + __IOM uint32_t reg; /*!< Control register for all counters */ + + struct { + __IOM uint32_t PULSE_CNT_RST_U0 : 1; /*!< Set this bit to clear unit 0's counter. */ + __IOM uint32_t CNT_PAUSE_U0 : 1; /*!< Set this bit to freeze unit 0's counter. */ + __IOM uint32_t PULSE_CNT_RST_U1 : 1; /*!< Set this bit to clear unit 1's counter. */ + __IOM uint32_t CNT_PAUSE_U1 : 1; /*!< Set this bit to freeze unit 1's counter. */ + __IOM uint32_t PULSE_CNT_RST_U2 : 1; /*!< Set this bit to clear unit 2's counter. */ + __IOM uint32_t CNT_PAUSE_U2 : 1; /*!< Set this bit to freeze unit 2's counter. */ + __IOM uint32_t PULSE_CNT_RST_U3 : 1; /*!< Set this bit to clear unit 3's counter. */ + __IOM uint32_t CNT_PAUSE_U3 : 1; /*!< Set this bit to freeze unit 3's counter. */ + __IOM uint32_t DALTA_CHANGE_EN_U0 : 1; /*!< Configures this bit to enable unit 0's step comparator. */ + __IOM uint32_t DALTA_CHANGE_EN_U1 : 1; /*!< Configures this bit to enable unit 1's step comparator. */ + __IOM uint32_t DALTA_CHANGE_EN_U2 : 1; /*!< Configures this bit to enable unit 2's step comparator. */ + __IOM uint32_t DALTA_CHANGE_EN_U3 : 1; /*!< Configures this bit to enable unit 3's step comparator. */ + uint32_t : 4; + __IOM uint32_t CLK_EN : 1; /*!< The registers clock gate enable signal of PCNT module. 1: the + registers can be read and written by application. 0: the + registers can not be read or written by application */ + uint32_t : 15; + } bit; + } CTRL; + }; + + union { + __IOM uint32_t U2_CONF1; /*!< Configuration register 1 for unit 2 */ + + union { + __IOM uint32_t reg; /*!< Configuration register for unit $n's step value. */ + + struct { + __IOM uint32_t CNT_STEP_U3 : 16; /*!< Configures the step value for unit 3. */ + __IOM uint32_t CNT_STEP_LIM_U3 : 16; /*!< Configures the step limit value for unit 3. */ + } bit; + } U3_CHANGE_CONF; + }; + + union { + __IOM uint32_t U2_CONF2; /*!< Configuration register 2 for unit 2 */ + + union { + __IOM uint32_t reg; /*!< Configuration register for unit $n's step value. */ + + struct { + __IOM uint32_t CNT_STEP_U2 : 16; /*!< Configures the step value for unit 2. */ + __IOM uint32_t CNT_STEP_LIM_U2 : 16; /*!< Configures the step limit value for unit 2. */ + } bit; + } U2_CHANGE_CONF; + }; + + union { + __IOM uint32_t reg; /*!< Configuration register for unit $n's step value. */ + + struct { + __IOM uint32_t CNT_STEP_U1 : 16; /*!< Configures the step value for unit 1. */ + __IOM uint32_t CNT_STEP_LIM_U1 : 16; /*!< Configures the step limit value for unit 1. */ + } bit; + } U1_CHANGE_CONF; + + union { + __IOM uint32_t U2_STATUS; /*!< PNCT UNIT2 status register */ + + union { + __IOM uint32_t reg; /*!< Configuration register for unit $n's step value. */ + + struct { + __IOM uint32_t CNT_STEP_U0 : 16; /*!< Configures the step value for unit 0. */ + __IOM uint32_t CNT_STEP_LIM_U0 : 16; /*!< Configures the step limit value for unit 0. */ + } bit; + } U0_CHANGE_CONF; + }; + __IM uint32_t RESERVED3[3]; + __IOM uint32_t U3_STATUS; /*!< PNCT UNIT3 status register */ + __IM uint32_t RESERVED4[3]; + + union { + __IOM uint32_t reg; /*!< Configuration register 0 for unit 3 */ + + struct { + __IOM uint32_t FILTER_THRES_U : 10; /*!< This sets the maximum threshold, in APB_CLK cycles, for the + filter.Any pulses with width less than this will be ignored + when the filter is enabled. */ + uint32_t : 6; + __IOM uint32_t CH0_NEG_MODE_U : 2; /*!< This register sets the behavior when the signal input of channel + 0 detects a negative edge.1: Increase the counter.2: Decrease + the counter.0, 3: No effect on counter */ + __IOM uint32_t CH0_POS_MODE_U : 2; /*!< This register sets the behavior when the signal input of channel + 0 detects a positive edge.1: Increase the counter.2: Decrease + the counter.0, 3: No effect on counter */ + uint32_t : 4; + __IOM uint32_t CH1_NEG_MODE_U : 2; /*!< This register sets the behavior when the signal input of channel + 1 detects a negative edge.1: Increment the counter.2: Decrement + the counter.0, 3: No effect on counter */ + __IOM uint32_t CH1_POS_MODE_U : 2; /*!< This register sets the behavior when the signal input of channel + 1 detects a positive edge.1: Increment the counter.2: Decrement + the counter.0, 3: No effect on counter */ + uint32_t : 4; + } bit; + } U3_CONF0; + __IOM uint32_t U3_CONF1; /*!< Configuration register 1 for unit 3 */ + __IOM uint32_t U3_CONF2; /*!< Configuration register 2 for unit 3 */ + __IM uint32_t RESERVED5[24]; + + union { + __IOM uint32_t reg; /*!< PCNT version control register */ + + struct { + __IOM uint32_t DATE : 32; /*!< This is the PCNT version control register. */ + } bit; + } DATE; +} PCNT_Type; /*!< Size = 256 (0x100) */ + + + +/* =========================================================================================================================== */ +/* ================ PMU ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief PMU Peripheral (PMU) + */ + +typedef struct { /*!< PMU Structure */ + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 21; + __IOM uint32_t HP_ACTIVE_DCDC_SWITCH_PD_EN : 1;/*!< need_des */ + __IOM uint32_t HP_ACTIVE_HP_MEM_DSLP : 1; /*!< need_des */ + __IOM uint32_t HP_ACTIVE_PD_HP_MEM_PD_EN : 1;/*!< need_des */ + uint32_t : 6; + __IOM uint32_t HP_ACTIVE_PD_CNNT_PD_EN : 1;/*!< need_des */ + __IOM uint32_t HP_ACTIVE_PD_TOP_PD_EN : 1;/*!< need_des */ + } bit; + } HP_ACTIVE_DIG_POWER; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t HP_ACTIVE_DIG_ICG_FUNC_EN : 32;/*!< need_des */ + } bit; + } HP_ACTIVE_ICG_HP_FUNC; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t HP_ACTIVE_DIG_ICG_APB_EN : 32;/*!< need_des */ + } bit; + } HP_ACTIVE_ICG_HP_APB; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 30; + __IOM uint32_t HP_ACTIVE_DIG_ICG_MODEM_CODE : 2;/*!< need_des */ + } bit; + } HP_ACTIVE_ICG_MODEM; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 23; + __IOM uint32_t HP_ACTIVE_HP_POWER_DET_BYPASS : 1;/*!< need_des */ + __IOM uint32_t HP_ACTIVE_UART_WAKEUP_EN : 1;/*!< need_des */ + __IOM uint32_t HP_ACTIVE_LP_PAD_HOLD_ALL : 1;/*!< need_des */ + __IOM uint32_t HP_ACTIVE_HP_PAD_HOLD_ALL : 1;/*!< need_des */ + __IOM uint32_t HP_ACTIVE_DIG_PAD_SLP_SEL : 1;/*!< need_des */ + __IOM uint32_t HP_ACTIVE_DIG_PAUSE_WDT : 1;/*!< need_des */ + __IOM uint32_t HP_ACTIVE_DIG_CPU_STALL : 1;/*!< need_des */ + uint32_t : 2; + } bit; + } HP_ACTIVE_HP_SYS_CNTL; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 21; + __IOM uint32_t HP_ACTIVE_I2C_ISO_EN : 1; /*!< need_des */ + __IOM uint32_t HP_ACTIVE_I2C_RETENTION : 1;/*!< need_des */ + __IOM uint32_t HP_ACTIVE_XPD_PLL_I2C : 4; /*!< need_des */ + __IOM uint32_t HP_ACTIVE_XPD_PLL : 4; /*!< need_des */ + uint32_t : 1; + } bit; + } HP_ACTIVE_HP_CK_POWER; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 18; + __IOM uint32_t HP_ACTIVE_DCM_VSET : 5; /*!< need_des */ + __IOM uint32_t HP_ACTIVE_DCM_MODE : 2; /*!< need_des */ + __IOM uint32_t HP_ACTIVE_XPD_BIAS : 1; /*!< need_des */ + __IOM uint32_t HP_ACTIVE_DBG_ATTEN : 4; /*!< need_des */ + __IOM uint32_t HP_ACTIVE_PD_CUR : 1; /*!< need_des */ + __IOM uint32_t SLEEP : 1; /*!< need_des */ + } bit; + } HP_ACTIVE_BIAS; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 4; + __IOM uint32_t HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE : 2;/*!< need_des */ + __IOM uint32_t HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE : 2;/*!< need_des */ + uint32_t : 2; + __IOM uint32_t HP_ACTIVE_RETENTION_MODE : 1;/*!< need_des */ + __IOM uint32_t HP_SLEEP2ACTIVE_RETENTION_EN : 1;/*!< need_des */ + __IOM uint32_t HP_MODEM2ACTIVE_RETENTION_EN : 1;/*!< need_des */ + uint32_t : 1; + __IOM uint32_t HP_SLEEP2ACTIVE_BACKUP_CLK_SEL : 2;/*!< need_des */ + __IOM uint32_t HP_MODEM2ACTIVE_BACKUP_CLK_SEL : 2;/*!< need_des */ + uint32_t : 2; + __IOM uint32_t HP_SLEEP2ACTIVE_BACKUP_MODE : 3;/*!< need_des */ + __IOM uint32_t HP_MODEM2ACTIVE_BACKUP_MODE : 3;/*!< need_des */ + uint32_t : 3; + __IOM uint32_t HP_SLEEP2ACTIVE_BACKUP_EN : 1;/*!< need_des */ + __IOM uint32_t HP_MODEM2ACTIVE_BACKUP_EN : 1;/*!< need_des */ + uint32_t : 1; + } bit; + } HP_ACTIVE_BACKUP; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t HP_ACTIVE_BACKUP_ICG_FUNC_EN : 32;/*!< need_des */ + } bit; + } HP_ACTIVE_BACKUP_CLK; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 26; + __IOM uint32_t HP_ACTIVE_DIG_SYS_CLK_NO_DIV : 1;/*!< need_des */ + __IOM uint32_t HP_ACTIVE_ICG_SYS_CLOCK_EN : 1;/*!< need_des */ + __IOM uint32_t HP_ACTIVE_SYS_CLK_SLP_SEL : 1;/*!< need_des */ + __IOM uint32_t HP_ACTIVE_ICG_SLP_SEL : 1; /*!< need_des */ + __IOM uint32_t HP_ACTIVE_DIG_SYS_CLK_SEL : 2;/*!< need_des */ + } bit; + } HP_ACTIVE_SYSCLK; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 4; + __IM uint32_t LP_DBIAS_VOL : 5; /*!< need_des */ + __IM uint32_t HP_DBIAS_VOL : 5; /*!< need_des */ + __IOM uint32_t DIG_REGULATOR0_DBIAS_SEL : 1;/*!< need_des */ + __OM uint32_t DIG_DBIAS_INIT : 1; /*!< need_des */ + __IOM uint32_t HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD : 1;/*!< need_des */ + __IOM uint32_t HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD : 1;/*!< need_des */ + __IOM uint32_t HP_ACTIVE_HP_REGULATOR_XPD : 1;/*!< need_des */ + __IOM uint32_t HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS : 4;/*!< need_des */ + __IOM uint32_t HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS : 4;/*!< need_des */ + __IOM uint32_t HP_ACTIVE_HP_REGULATOR_DBIAS : 5;/*!< need_des */ + } bit; + } HP_ACTIVE_HP_REGULATOR0; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 26; + __IOM uint32_t HP_ACTIVE_HP_REGULATOR_DRV_B : 6;/*!< need_des */ + } bit; + } HP_ACTIVE_HP_REGULATOR1; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 31; + __IOM uint32_t HP_ACTIVE_XPD_XTAL : 1; /*!< need_des */ + } bit; + } HP_ACTIVE_XTAL; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 21; + __IOM uint32_t HP_MODEM_DCDC_SWITCH_PD_EN : 1;/*!< need_des */ + __OM uint32_t HP_MODEM_HP_MEM_DSLP : 1; /*!< need_des */ + __OM uint32_t HP_MODEM_PD_HP_MEM_PD_EN : 4;/*!< need_des */ + __OM uint32_t HP_MODEM_PD_HP_WIFI_PD_EN : 1;/*!< need_des */ + uint32_t : 1; + __OM uint32_t HP_MODEM_PD_HP_CPU_PD_EN : 1;/*!< need_des */ + __OM uint32_t HP_MODEM_PD_CNNT_PD_EN : 1;/*!< need_des */ + __OM uint32_t HP_MODEM_PD_TOP_PD_EN : 1; /*!< need_des */ + } bit; + } HP_MODEM_DIG_POWER; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __OM uint32_t HP_MODEM_DIG_ICG_FUNC_EN : 32;/*!< need_des */ + } bit; + } HP_MODEM_ICG_HP_FUNC; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __OM uint32_t HP_MODEM_DIG_ICG_APB_EN : 32;/*!< need_des */ + } bit; + } HP_MODEM_ICG_HP_APB; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 30; + __OM uint32_t HP_MODEM_DIG_ICG_MODEM_CODE : 2;/*!< need_des */ + } bit; + } HP_MODEM_ICG_MODEM; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 23; + __OM uint32_t HP_MODEM_HP_POWER_DET_BYPASS : 1;/*!< need_des */ + __OM uint32_t HP_MODEM_UART_WAKEUP_EN : 1;/*!< need_des */ + __OM uint32_t HP_MODEM_LP_PAD_HOLD_ALL : 1;/*!< need_des */ + __OM uint32_t HP_MODEM_HP_PAD_HOLD_ALL : 1;/*!< need_des */ + __OM uint32_t HP_MODEM_DIG_PAD_SLP_SEL : 1;/*!< need_des */ + __OM uint32_t HP_MODEM_DIG_PAUSE_WDT : 1;/*!< need_des */ + __OM uint32_t HP_MODEM_DIG_CPU_STALL : 1;/*!< need_des */ + uint32_t : 2; + } bit; + } HP_MODEM_HP_SYS_CNTL; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 21; + __OM uint32_t HP_MODEM_I2C_ISO_EN : 1; /*!< need_des */ + __OM uint32_t HP_MODEM_I2C_RETENTION : 1;/*!< need_des */ + __OM uint32_t HP_MODEM_XPD_PLL_I2C : 4; /*!< need_des */ + __OM uint32_t HP_MODEM_XPD_PLL : 4; /*!< need_des */ + uint32_t : 1; + } bit; + } HP_MODEM_HP_CK_POWER; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 18; + __OM uint32_t HP_MODEM_DCM_VSET : 5; /*!< need_des */ + __OM uint32_t HP_MODEM_DCM_MODE : 2; /*!< need_des */ + __OM uint32_t HP_MODEM_XPD_BIAS : 1; /*!< need_des */ + __OM uint32_t HP_MODEM_DBG_ATTEN : 4; /*!< need_des */ + __OM uint32_t HP_MODEM_PD_CUR : 1; /*!< need_des */ + __OM uint32_t SLEEP : 1; /*!< need_des */ + } bit; + } HP_MODEM_BIAS; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 4; + __OM uint32_t HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE : 2;/*!< need_des */ + uint32_t : 4; + __OM uint32_t HP_MODEM_RETENTION_MODE : 1;/*!< need_des */ + __OM uint32_t HP_SLEEP2MODEM_RETENTION_EN : 1;/*!< need_des */ + uint32_t : 2; + __OM uint32_t HP_SLEEP2MODEM_BACKUP_CLK_SEL : 2;/*!< need_des */ + uint32_t : 4; + __OM uint32_t HP_SLEEP2MODEM_BACKUP_MODE : 3;/*!< need_des */ + uint32_t : 6; + __OM uint32_t HP_SLEEP2MODEM_BACKUP_EN : 1;/*!< need_des */ + uint32_t : 2; + } bit; + } HP_MODEM_BACKUP; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __OM uint32_t HP_MODEM_BACKUP_ICG_FUNC_EN : 32;/*!< need_des */ + } bit; + } HP_MODEM_BACKUP_CLK; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 26; + __OM uint32_t HP_MODEM_DIG_SYS_CLK_NO_DIV : 1;/*!< need_des */ + __OM uint32_t HP_MODEM_ICG_SYS_CLOCK_EN : 1;/*!< need_des */ + __OM uint32_t HP_MODEM_SYS_CLK_SLP_SEL : 1;/*!< need_des */ + __OM uint32_t HP_MODEM_ICG_SLP_SEL : 1; /*!< need_des */ + __OM uint32_t HP_MODEM_DIG_SYS_CLK_SEL : 2;/*!< need_des */ + } bit; + } HP_MODEM_SYSCLK; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 16; + __OM uint32_t HP_MODEM_HP_REGULATOR_SLP_MEM_XPD : 1;/*!< need_des */ + __OM uint32_t HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD : 1;/*!< need_des */ + __OM uint32_t HP_MODEM_HP_REGULATOR_XPD : 1;/*!< need_des */ + __OM uint32_t HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS : 4;/*!< need_des */ + __OM uint32_t HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS : 4;/*!< need_des */ + __OM uint32_t HP_MODEM_HP_REGULATOR_DBIAS : 5;/*!< need_des */ + } bit; + } HP_MODEM_HP_REGULATOR0; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 8; + __OM uint32_t HP_MODEM_HP_REGULATOR_DRV_B : 24;/*!< need_des */ + } bit; + } HP_MODEM_HP_REGULATOR1; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 31; + __OM uint32_t HP_MODEM_XPD_XTAL : 1; /*!< need_des */ + } bit; + } HP_MODEM_XTAL; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 21; + __IOM uint32_t HP_SLEEP_DCDC_SWITCH_PD_EN : 1;/*!< need_des */ + __IOM uint32_t HP_SLEEP_HP_MEM_DSLP : 1; /*!< need_des */ + __IOM uint32_t HP_SLEEP_PD_HP_MEM_PD_EN : 1;/*!< need_des */ + uint32_t : 6; + __IOM uint32_t HP_SLEEP_PD_CNNT_PD_EN : 1;/*!< need_des */ + __IOM uint32_t HP_SLEEP_PD_TOP_PD_EN : 1; /*!< need_des */ + } bit; + } HP_SLEEP_DIG_POWER; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t HP_SLEEP_DIG_ICG_FUNC_EN : 32;/*!< need_des */ + } bit; + } HP_SLEEP_ICG_HP_FUNC; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t HP_SLEEP_DIG_ICG_APB_EN : 32;/*!< need_des */ + } bit; + } HP_SLEEP_ICG_HP_APB; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 30; + __IOM uint32_t HP_SLEEP_DIG_ICG_MODEM_CODE : 2;/*!< need_des */ + } bit; + } HP_SLEEP_ICG_MODEM; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 23; + __IOM uint32_t HP_SLEEP_HP_POWER_DET_BYPASS : 1;/*!< need_des */ + __IOM uint32_t HP_SLEEP_UART_WAKEUP_EN : 1;/*!< need_des */ + __IOM uint32_t HP_SLEEP_LP_PAD_HOLD_ALL : 1;/*!< need_des */ + __IOM uint32_t HP_SLEEP_HP_PAD_HOLD_ALL : 1;/*!< need_des */ + __IOM uint32_t HP_SLEEP_DIG_PAD_SLP_SEL : 1;/*!< need_des */ + __IOM uint32_t HP_SLEEP_DIG_PAUSE_WDT : 1;/*!< need_des */ + __IOM uint32_t HP_SLEEP_DIG_CPU_STALL : 1;/*!< need_des */ + uint32_t : 2; + } bit; + } HP_SLEEP_HP_SYS_CNTL; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 21; + __IOM uint32_t HP_SLEEP_I2C_ISO_EN : 1; /*!< need_des */ + __IOM uint32_t HP_SLEEP_I2C_RETENTION : 1;/*!< need_des */ + __IOM uint32_t HP_SLEEP_XPD_PLL_I2C : 4; /*!< need_des */ + __IOM uint32_t HP_SLEEP_XPD_PLL : 4; /*!< need_des */ + uint32_t : 1; + } bit; + } HP_SLEEP_HP_CK_POWER; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 18; + __IOM uint32_t HP_SLEEP_DCM_VSET : 5; /*!< need_des */ + __IOM uint32_t HP_SLEEP_DCM_MODE : 2; /*!< need_des */ + __IOM uint32_t HP_SLEEP_XPD_BIAS : 1; /*!< need_des */ + __IOM uint32_t HP_SLEEP_DBG_ATTEN : 4; /*!< need_des */ + __IOM uint32_t HP_SLEEP_PD_CUR : 1; /*!< need_des */ + __IOM uint32_t SLEEP : 1; /*!< need_des */ + } bit; + } HP_SLEEP_BIAS; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 6; + __IOM uint32_t HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE : 2;/*!< need_des */ + __IOM uint32_t HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE : 2;/*!< need_des */ + __IOM uint32_t HP_SLEEP_RETENTION_MODE : 1;/*!< need_des */ + uint32_t : 1; + __IOM uint32_t HP_MODEM2SLEEP_RETENTION_EN : 1;/*!< need_des */ + __IOM uint32_t HP_ACTIVE2SLEEP_RETENTION_EN : 1;/*!< need_des */ + uint32_t : 2; + __IOM uint32_t HP_MODEM2SLEEP_BACKUP_CLK_SEL : 2;/*!< need_des */ + __IOM uint32_t HP_ACTIVE2SLEEP_BACKUP_CLK_SEL : 2;/*!< need_des */ + uint32_t : 3; + __IOM uint32_t HP_MODEM2SLEEP_BACKUP_MODE : 3;/*!< need_des */ + __IOM uint32_t HP_ACTIVE2SLEEP_BACKUP_MODE : 3;/*!< need_des */ + uint32_t : 1; + __IOM uint32_t HP_MODEM2SLEEP_BACKUP_EN : 1;/*!< need_des */ + __IOM uint32_t HP_ACTIVE2SLEEP_BACKUP_EN : 1;/*!< need_des */ + } bit; + } HP_SLEEP_BACKUP; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t HP_SLEEP_BACKUP_ICG_FUNC_EN : 32;/*!< need_des */ + } bit; + } HP_SLEEP_BACKUP_CLK; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 26; + __IOM uint32_t HP_SLEEP_DIG_SYS_CLK_NO_DIV : 1;/*!< need_des */ + __IOM uint32_t HP_SLEEP_ICG_SYS_CLOCK_EN : 1;/*!< need_des */ + __IOM uint32_t HP_SLEEP_SYS_CLK_SLP_SEL : 1;/*!< need_des */ + __IOM uint32_t HP_SLEEP_ICG_SLP_SEL : 1; /*!< need_des */ + __IOM uint32_t HP_SLEEP_DIG_SYS_CLK_SEL : 2;/*!< need_des */ + } bit; + } HP_SLEEP_SYSCLK; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 16; + __IOM uint32_t HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD : 1;/*!< need_des */ + __IOM uint32_t HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD : 1;/*!< need_des */ + __IOM uint32_t HP_SLEEP_HP_REGULATOR_XPD : 1;/*!< need_des */ + __IOM uint32_t HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS : 4;/*!< need_des */ + __IOM uint32_t HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS : 4;/*!< need_des */ + __IOM uint32_t HP_SLEEP_HP_REGULATOR_DBIAS : 5;/*!< need_des */ + } bit; + } HP_SLEEP_HP_REGULATOR0; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 26; + __IOM uint32_t HP_SLEEP_HP_REGULATOR_DRV_B : 6;/*!< need_des */ + } bit; + } HP_SLEEP_HP_REGULATOR1; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 31; + __IOM uint32_t HP_SLEEP_XPD_XTAL : 1; /*!< need_des */ + } bit; + } HP_SLEEP_XTAL; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 21; + __IOM uint32_t HP_SLEEP_LP_REGULATOR_SLP_XPD : 1;/*!< need_des */ + __IOM uint32_t HP_SLEEP_LP_REGULATOR_XPD : 1;/*!< need_des */ + __IOM uint32_t HP_SLEEP_LP_REGULATOR_SLP_DBIAS : 4;/*!< need_des */ + __IOM uint32_t HP_SLEEP_LP_REGULATOR_DBIAS : 5;/*!< need_des */ + } bit; + } HP_SLEEP_LP_REGULATOR0; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 26; + __IOM uint32_t HP_SLEEP_LP_REGULATOR_DRV_B : 6;/*!< need_des */ + } bit; + } HP_SLEEP_LP_REGULATOR1; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __OM uint32_t PMU_HP_SLEEP_LP_DCDC_RESERVE : 32;/*!< need_des */ + } bit; + } HP_SLEEP_LP_DCDC_RESERVE; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 26; + __IOM uint32_t HP_SLEEP_LP_PAD_SLP_SEL : 1;/*!< need_des */ + __IOM uint32_t HP_SLEEP_BOD_SOURCE_SEL : 1;/*!< need_des */ + __IOM uint32_t HP_SLEEP_VDDBAT_MODE : 2; /*!< need_des */ + __IOM uint32_t HP_SLEEP_LP_MEM_DSLP : 1; /*!< need_des */ + __IOM uint32_t HP_SLEEP_PD_LP_PERI_PD_EN : 1;/*!< need_des */ + } bit; + } HP_SLEEP_LP_DIG_POWER; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 27; + __IOM uint32_t HP_SLEEP_XPD_LPPLL : 1; /*!< need_des */ + __IOM uint32_t HP_SLEEP_XPD_XTAL32K : 1; /*!< need_des */ + __IOM uint32_t HP_SLEEP_XPD_RC32K : 1; /*!< need_des */ + __IOM uint32_t HP_SLEEP_XPD_FOSC_CLK : 1; /*!< need_des */ + __IOM uint32_t HP_SLEEP_PD_OSC_CLK : 1; /*!< need_des */ + } bit; + } HP_SLEEP_LP_CK_POWER; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __OM uint32_t PMU_LP_SLEEP_LP_BIAS_RESERVE : 32;/*!< need_des */ + } bit; + } LP_SLEEP_LP_BIAS_RESERVE; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 21; + __IOM uint32_t LP_SLEEP_LP_REGULATOR_SLP_XPD : 1;/*!< need_des */ + __IOM uint32_t LP_SLEEP_LP_REGULATOR_XPD : 1;/*!< need_des */ + __IOM uint32_t LP_SLEEP_LP_REGULATOR_SLP_DBIAS : 4;/*!< need_des */ + __IOM uint32_t LP_SLEEP_LP_REGULATOR_DBIAS : 5;/*!< need_des */ + } bit; + } LP_SLEEP_LP_REGULATOR0; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 26; + __IOM uint32_t LP_SLEEP_LP_REGULATOR_DRV_B : 6;/*!< need_des */ + } bit; + } LP_SLEEP_LP_REGULATOR1; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 31; + __IOM uint32_t LP_SLEEP_XPD_XTAL : 1; /*!< need_des */ + } bit; + } LP_SLEEP_XTAL; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 26; + __IOM uint32_t LP_SLEEP_LP_PAD_SLP_SEL : 1;/*!< need_des */ + __IOM uint32_t LP_SLEEP_BOD_SOURCE_SEL : 1;/*!< need_des */ + __IOM uint32_t LP_SLEEP_VDDBAT_MODE : 2; /*!< need_des */ + __IOM uint32_t LP_SLEEP_LP_MEM_DSLP : 1; /*!< need_des */ + __IOM uint32_t LP_SLEEP_PD_LP_PERI_PD_EN : 1;/*!< need_des */ + } bit; + } LP_SLEEP_LP_DIG_POWER; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 27; + __IOM uint32_t LP_SLEEP_XPD_LPPLL : 1; /*!< need_des */ + __IOM uint32_t LP_SLEEP_XPD_XTAL32K : 1; /*!< need_des */ + __IOM uint32_t LP_SLEEP_XPD_RC32K : 1; /*!< need_des */ + __IOM uint32_t LP_SLEEP_XPD_FOSC_CLK : 1; /*!< need_des */ + __IOM uint32_t LP_SLEEP_PD_OSC_CLK : 1; /*!< need_des */ + } bit; + } LP_SLEEP_LP_CK_POWER; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 25; + __IOM uint32_t LP_SLEEP_XPD_BIAS : 1; /*!< need_des */ + __IOM uint32_t LP_SLEEP_DBG_ATTEN : 4; /*!< need_des */ + __IOM uint32_t LP_SLEEP_PD_CUR : 1; /*!< need_des */ + __IOM uint32_t SLEEP : 1; /*!< need_des */ + } bit; + } LP_SLEEP_BIAS; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t TIE_LOW_CALI_XTAL_ICG : 1; /*!< need_des */ + __OM uint32_t TIE_LOW_GLOBAL_PLL_ICG : 4;/*!< need_des */ + __OM uint32_t TIE_LOW_GLOBAL_XTAL_ICG : 1;/*!< need_des */ + __OM uint32_t TIE_LOW_I2C_RETENTION : 1; /*!< need_des */ + __OM uint32_t TIE_LOW_XPD_PLL_I2C : 4; /*!< need_des */ + __OM uint32_t TIE_LOW_XPD_PLL : 4; /*!< need_des */ + __OM uint32_t TIE_LOW_XPD_XTAL : 1; /*!< need_des */ + __IOM uint32_t TIE_HIGH_CALI_XTAL_ICG : 1;/*!< need_des */ + __OM uint32_t TIE_HIGH_GLOBAL_PLL_ICG : 4;/*!< need_des */ + __OM uint32_t TIE_HIGH_GLOBAL_XTAL_ICG : 1;/*!< need_des */ + __OM uint32_t TIE_HIGH_I2C_RETENTION : 1;/*!< need_des */ + __OM uint32_t TIE_HIGH_XPD_PLL_I2C : 4; /*!< need_des */ + __OM uint32_t TIE_HIGH_XPD_PLL : 4; /*!< need_des */ + __OM uint32_t TIE_HIGH_XPD_XTAL : 1; /*!< need_des */ + } bit; + } IMM_HP_CK_POWER; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 28; + __OM uint32_t UPDATE_DIG_ICG_SWITCH : 1; /*!< need_des */ + __OM uint32_t TIE_LOW_ICG_SLP_SEL : 1; /*!< need_des */ + __OM uint32_t TIE_HIGH_ICG_SLP_SEL : 1; /*!< need_des */ + __OM uint32_t UPDATE_DIG_SYS_CLK_SEL : 1;/*!< need_des */ + } bit; + } IMM_SLEEP_SYSCLK; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 31; + __OM uint32_t UPDATE_DIG_ICG_FUNC_EN : 1;/*!< need_des */ + } bit; + } IMM_HP_FUNC_ICG; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 31; + __OM uint32_t UPDATE_DIG_ICG_APB_EN : 1; /*!< need_des */ + } bit; + } IMM_HP_APB_ICG; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 31; + __OM uint32_t UPDATE_DIG_ICG_MODEM_EN : 1;/*!< need_des */ + } bit; + } IMM_MODEM_ICG; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 30; + __OM uint32_t TIE_LOW_LP_ROOTCLK_SEL : 1;/*!< need_des */ + __OM uint32_t TIE_HIGH_LP_ROOTCLK_SEL : 1;/*!< need_des */ + } bit; + } IMM_LP_ICG; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IM uint32_t PAD_SLP_SEL : 1; /*!< need_des */ + __IM uint32_t LP_PAD_HOLD_ALL : 1; /*!< need_des */ + __IM uint32_t HP_PAD_HOLD_ALL : 1; /*!< need_des */ + uint32_t : 23; + __OM uint32_t TIE_HIGH_PAD_SLP_SEL : 1; /*!< need_des */ + __OM uint32_t TIE_LOW_PAD_SLP_SEL : 1; /*!< need_des */ + __OM uint32_t TIE_HIGH_LP_PAD_HOLD_ALL : 1;/*!< need_des */ + __OM uint32_t TIE_LOW_LP_PAD_HOLD_ALL : 1;/*!< need_des */ + __OM uint32_t TIE_HIGH_HP_PAD_HOLD_ALL : 1;/*!< need_des */ + __OM uint32_t TIE_LOW_HP_PAD_HOLD_ALL : 1;/*!< need_des */ + } bit; + } IMM_PAD_HOLD_ALL; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 30; + __OM uint32_t TIE_HIGH_I2C_ISO_EN : 1; /*!< need_des */ + __OM uint32_t TIE_LOW_I2C_ISO_EN : 1; /*!< need_des */ + } bit; + } IMM_I2C_ISO; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 5; + __IOM uint32_t DG_HP_POWERDOWN_TIMER : 9; /*!< need_des */ + __IOM uint32_t DG_HP_POWERUP_TIMER : 9; /*!< need_des */ + __IOM uint32_t DG_HP_WAIT_TIMER : 9; /*!< need_des */ + } bit; + } POWER_WAIT_TIMER0; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 5; + __IOM uint32_t DG_LP_POWERDOWN_TIMER : 9; /*!< need_des */ + __IOM uint32_t DG_LP_POWERUP_TIMER : 9; /*!< need_des */ + __IOM uint32_t DG_LP_WAIT_TIMER : 9; /*!< need_des */ + } bit; + } POWER_WAIT_TIMER1; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t FORCE_TOP_RESET : 1; /*!< need_des */ + __IOM uint32_t FORCE_TOP_ISO : 1; /*!< need_des */ + __IOM uint32_t FORCE_TOP_PU : 1; /*!< need_des */ + __IOM uint32_t FORCE_TOP_NO_RESET : 1; /*!< need_des */ + __IOM uint32_t FORCE_TOP_NO_ISO : 1; /*!< need_des */ + __IOM uint32_t FORCE_TOP_PD : 1; /*!< need_des */ + uint32_t : 26; + } bit; + } POWER_PD_TOP_CNTL; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t FORCE_CNNT_RESET : 1; /*!< need_des */ + __IOM uint32_t FORCE_CNNT_ISO : 1; /*!< need_des */ + __IOM uint32_t FORCE_CNNT_PU : 1; /*!< need_des */ + __IOM uint32_t FORCE_CNNT_NO_RESET : 1; /*!< need_des */ + __IOM uint32_t FORCE_CNNT_NO_ISO : 1; /*!< need_des */ + __IOM uint32_t FORCE_CNNT_PD : 1; /*!< need_des */ + uint32_t : 26; + } bit; + } POWER_PD_CNNT_CNTL; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t FORCE_HP_MEM_RESET : 1; /*!< need_des */ + __IOM uint32_t FORCE_HP_MEM_ISO : 1; /*!< need_des */ + __IOM uint32_t FORCE_HP_MEM_PU : 1; /*!< need_des */ + __IOM uint32_t FORCE_HP_MEM_NO_RESET : 1; /*!< need_des */ + __IOM uint32_t FORCE_HP_MEM_NO_ISO : 1; /*!< need_des */ + __IOM uint32_t FORCE_HP_MEM_PD : 1; /*!< need_des */ + uint32_t : 26; + } bit; + } POWER_PD_HPMEM_CNTL; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t XPD_TOP_MASK : 5; /*!< need_des */ + uint32_t : 22; + __IOM uint32_t PD_TOP_MASK : 5; /*!< need_des */ + } bit; + } POWER_PD_TOP_MASK; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t XPD_CNNT_MASK : 5; /*!< need_des */ + uint32_t : 22; + __IOM uint32_t PD_CNNT_MASK : 5; /*!< need_des */ + } bit; + } POWER_PD_CNNT_MASK; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t XPD_HP_MEM_MASK : 6; /*!< need_des */ + uint32_t : 20; + __IOM uint32_t PD_HP_MEM_MASK : 6; /*!< need_des */ + } bit; + } POWER_PD_HPMEM_MASK; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t FORCE_DCDC_SWITCH_PU : 1; /*!< need_des */ + __IOM uint32_t FORCE_DCDC_SWITCH_PD : 1; /*!< need_des */ + uint32_t : 30; + } bit; + } POWER_DCDC_SWITCH; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t FORCE_LP_PERI_RESET : 1; /*!< need_des */ + __IOM uint32_t FORCE_LP_PERI_ISO : 1; /*!< need_des */ + __IOM uint32_t FORCE_LP_PERI_PU : 1; /*!< need_des */ + __IOM uint32_t FORCE_LP_PERI_NO_RESET : 1;/*!< need_des */ + __IOM uint32_t FORCE_LP_PERI_NO_ISO : 1; /*!< need_des */ + __IOM uint32_t FORCE_LP_PERI_PD : 1; /*!< need_des */ + uint32_t : 26; + } bit; + } POWER_PD_LPPERI_CNTL; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t XPD_LP_PERI_MASK : 5; /*!< need_des */ + uint32_t : 22; + __IOM uint32_t PD_LP_PERI_MASK : 5; /*!< need_des */ + } bit; + } POWER_PD_LPPERI_MASK; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t FORCE_HP_PAD_NO_ISO_ALL : 1;/*!< need_des */ + __IOM uint32_t FORCE_HP_PAD_ISO_ALL : 1; /*!< need_des */ + uint32_t : 30; + } bit; + } POWER_HP_PAD; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t PMU_WAIT_XTL_STABLE : 16; /*!< need_des */ + __IOM uint32_t PMU_WAIT_PLL_STABLE : 16; /*!< need_des */ + } bit; + } POWER_CK_WAIT_CNTL; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 31; + __OM uint32_t SLEEP_REQ : 1; /*!< need_des */ + } bit; + } SLP_WAKEUP_CNTL0; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t SLEEP_REJECT_ENA : 31; /*!< need_des */ + __IOM uint32_t SLP_REJECT_EN : 1; /*!< need_des */ + } bit; + } SLP_WAKEUP_CNTL1; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t WAKEUP_ENA : 31; /*!< need_des */ + uint32_t : 1; + } bit; + } SLP_WAKEUP_CNTL2; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t LP_MIN_SLP_VAL : 8; /*!< need_des */ + __IOM uint32_t HP_MIN_SLP_VAL : 8; /*!< need_des */ + __IOM uint32_t SLEEP_PRT_SEL : 2; /*!< need_des */ + uint32_t : 14; + } bit; + } SLP_WAKEUP_CNTL3; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 31; + __OM uint32_t SLP_REJECT_CAUSE_CLR : 1; /*!< need_des */ + } bit; + } SLP_WAKEUP_CNTL4; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t MODEM_WAIT_TARGET : 20; /*!< need_des */ + uint32_t : 4; + __IOM uint32_t LP_ANA_WAIT_TARGET : 8; /*!< need_des */ + } bit; + } SLP_WAKEUP_CNTL5; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t SOC_WAKEUP_WAIT : 20; /*!< need_des */ + uint32_t : 10; + __IOM uint32_t SOC_WAKEUP_WAIT_CFG : 2; /*!< need_des */ + } bit; + } SLP_WAKEUP_CNTL6; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 16; + __IOM uint32_t ANA_WAIT_TARGET : 16; /*!< need_des */ + } bit; + } SLP_WAKEUP_CNTL7; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 31; + __IOM uint32_t LP_LITE_WAKEUP_ENA : 1; /*!< need_des */ + } bit; + } SLP_WAKEUP_CNTL8; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IM uint32_t WAKEUP_CAUSE : 31; /*!< need_des */ + uint32_t : 1; + } bit; + } SLP_WAKEUP_STATUS0; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IM uint32_t REJECT_CAUSE : 31; /*!< need_des */ + uint32_t : 1; + } bit; + } SLP_WAKEUP_STATUS1; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 31; + __IM uint32_t LP_LITE_WAKEUP_CAUSE : 1; /*!< need_des */ + } bit; + } SLP_WAKEUP_STATUS2; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t I2C_POR_WAIT_TARGET : 8; /*!< need_des */ + uint32_t : 24; + } bit; + } HP_CK_POWERON; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t MODIFY_ICG_CNTL_WAIT : 8; /*!< need_des */ + __IOM uint32_t SWITCH_ICG_CNTL_WAIT : 8; /*!< need_des */ + uint32_t : 16; + } bit; + } HP_CK_CNTL; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 31; + __IM uint32_t POR_DONE : 1; /*!< need_des */ + } bit; + } POR_STATUS; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 24; + __IOM uint32_t MSPI_PHY_XPD : 1; /*!< need_des */ + __IOM uint32_t SDIO_PLL_XPD : 1; /*!< need_des */ + __IOM uint32_t PERIF_I2C_RSTB : 1; /*!< need_des */ + __IOM uint32_t XPD_PERIF_I2C : 1; /*!< need_des */ + __IOM uint32_t XPD_TXRF_I2C : 1; /*!< need_des */ + __IOM uint32_t XPD_RFRX_PBUS : 1; /*!< need_des */ + __IOM uint32_t XPD_CKGEN_I2C : 1; /*!< need_des */ + uint32_t : 1; + } bit; + } RF_PWC; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 31; + __IOM uint32_t BACKUP_SYS_CLK_NO_DIV : 1; /*!< need_des */ + } bit; + } BACKUP_CFG; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 14; + __IOM uint32_t _0P1A_CNT_TARGET0_REACH_0_HP_INT_RAW : 1;/*!< reg_0p1a_0_counter after xpd reach target0 */ + __IOM uint32_t _0P1A_CNT_TARGET1_REACH_0_HP_INT_RAW : 1;/*!< reg_0p1a_1_counter after xpd reach target1 */ + __IOM uint32_t _0P1A_CNT_TARGET0_REACH_1_HP_INT_RAW : 1;/*!< reg_0p1a_0 counter after xpd reach target0 */ + __IOM uint32_t _0P1A_CNT_TARGET1_REACH_1_HP_INT_RAW : 1;/*!< reg_0p1a_1_counter after xpd reach target1 */ + __IOM uint32_t _0P2A_CNT_TARGET0_REACH_0_HP_INT_RAW : 1;/*!< reg_0p2a_0 counter after xpd reach target0 */ + __IOM uint32_t _0P2A_CNT_TARGET1_REACH_0_HP_INT_RAW : 1;/*!< reg_0p2a_1_counter after xpd reach target1 */ + __IOM uint32_t _0P2A_CNT_TARGET0_REACH_1_HP_INT_RAW : 1;/*!< reg_0p2a_0 counter after xpd reach target0 */ + __IOM uint32_t _0P2A_CNT_TARGET1_REACH_1_HP_INT_RAW : 1;/*!< reg_0p2a_1_counter after xpd reach target1 */ + __IOM uint32_t _0P3A_CNT_TARGET0_REACH_0_HP_INT_RAW : 1;/*!< reg_0p3a_0 counter after xpd reach target0 */ + __IOM uint32_t _0P3A_CNT_TARGET1_REACH_0_HP_INT_RAW : 1;/*!< reg_0p3a_1_counter after xpd reach target1 */ + __IOM uint32_t _0P3A_CNT_TARGET0_REACH_1_HP_INT_RAW : 1;/*!< reg_0p3a_0_counter after xpd reach target0 */ + __IOM uint32_t _0P3A_CNT_TARGET1_REACH_1_HP_INT_RAW : 1;/*!< reg_0p3a_1_counter after xpd reach target1 */ + uint32_t : 1; + __IOM uint32_t LP_CPU_EXC_INT_RAW : 1; /*!< need_des */ + __IOM uint32_t SDIO_IDLE_INT_RAW : 1; /*!< need_des */ + __IOM uint32_t SW_INT_RAW : 1; /*!< need_des */ + __IOM uint32_t SOC_SLEEP_REJECT_INT_RAW : 1;/*!< need_des */ + __IOM uint32_t SOC_WAKEUP_INT_RAW : 1; /*!< need_des */ + } bit; + } INT_RAW; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 14; + __IM uint32_t _0P1A_CNT_TARGET0_REACH_0_HP_INT_ST : 1;/*!< reg_0p1a_0_counter after xpd reach target0 */ + __IM uint32_t _0P1A_CNT_TARGET1_REACH_0_HP_INT_ST : 1;/*!< reg_0p1a_1_counter after xpd reach target1 */ + __IM uint32_t _0P1A_CNT_TARGET0_REACH_1_HP_INT_ST : 1;/*!< reg_0p1a_0 counter after xpd reach target0 */ + __IM uint32_t _0P1A_CNT_TARGET1_REACH_1_HP_INT_ST : 1;/*!< reg_0p1a_1_counter after xpd reach target1 */ + __IM uint32_t _0P2A_CNT_TARGET0_REACH_0_HP_INT_ST : 1;/*!< reg_0p2a_0 counter after xpd reach target0 */ + __IM uint32_t _0P2A_CNT_TARGET1_REACH_0_HP_INT_ST : 1;/*!< reg_0p2a_1_counter after xpd reach target1 */ + __IM uint32_t _0P2A_CNT_TARGET0_REACH_1_HP_INT_ST : 1;/*!< reg_0p2a_0 counter after xpd reach target0 */ + __IM uint32_t _0P2A_CNT_TARGET1_REACH_1_HP_INT_ST : 1;/*!< reg_0p2a_1_counter after xpd reach target1 */ + __IM uint32_t _0P3A_CNT_TARGET0_REACH_0_HP_INT_ST : 1;/*!< reg_0p3a_0 counter after xpd reach target0 */ + __IM uint32_t _0P3A_CNT_TARGET1_REACH_0_HP_INT_ST : 1;/*!< reg_0p3a_1_counter after xpd reach target1 */ + __IM uint32_t _0P3A_CNT_TARGET0_REACH_1_HP_INT_ST : 1;/*!< reg_0p3a_0_counter after xpd reach target0 */ + __IM uint32_t _0P3A_CNT_TARGET1_REACH_1_HP_INT_ST : 1;/*!< reg_0p3a_1_counter after xpd reach target1 */ + uint32_t : 1; + __IM uint32_t LP_CPU_EXC_INT_ST : 1; /*!< need_des */ + __IM uint32_t SDIO_IDLE_INT_ST : 1; /*!< need_des */ + __IM uint32_t SW_INT_ST : 1; /*!< need_des */ + __IM uint32_t SOC_SLEEP_REJECT_INT_ST : 1;/*!< need_des */ + __IM uint32_t SOC_WAKEUP_INT_ST : 1; /*!< need_des */ + } bit; + } HP_INT_ST; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 14; + __IOM uint32_t _0P1A_CNT_TARGET0_REACH_0_HP_INT_ENA : 1;/*!< reg_0p1a_0_counter after xpd reach target0 */ + __IOM uint32_t _0P1A_CNT_TARGET1_REACH_0_HP_INT_ENA : 1;/*!< reg_0p1a_1_counter after xpd reach target1 */ + __IOM uint32_t _0P1A_CNT_TARGET0_REACH_1_HP_INT_ENA : 1;/*!< reg_0p1a_0 counter after xpd reach target0 */ + __IOM uint32_t _0P1A_CNT_TARGET1_REACH_1_HP_INT_ENA : 1;/*!< reg_0p1a_1_counter after xpd reach target1 */ + __IOM uint32_t _0P2A_CNT_TARGET0_REACH_0_HP_INT_ENA : 1;/*!< reg_0p2a_0 counter after xpd reach target0 */ + __IOM uint32_t _0P2A_CNT_TARGET1_REACH_0_HP_INT_ENA : 1;/*!< reg_0p2a_1_counter after xpd reach target1 */ + __IOM uint32_t _0P2A_CNT_TARGET0_REACH_1_HP_INT_ENA : 1;/*!< reg_0p2a_0 counter after xpd reach target0 */ + __IOM uint32_t _0P2A_CNT_TARGET1_REACH_1_HP_INT_ENA : 1;/*!< reg_0p2a_1_counter after xpd reach target1 */ + __IOM uint32_t _0P3A_CNT_TARGET0_REACH_0_HP_INT_ENA : 1;/*!< reg_0p3a_0 counter after xpd reach target0 */ + __IOM uint32_t _0P3A_CNT_TARGET1_REACH_0_HP_INT_ENA : 1;/*!< reg_0p3a_1_counter after xpd reach target1 */ + __IOM uint32_t _0P3A_CNT_TARGET0_REACH_1_HP_INT_ENA : 1;/*!< reg_0p3a_0_counter after xpd reach target0 */ + __IOM uint32_t _0P3A_CNT_TARGET1_REACH_1_HP_INT_ENA : 1;/*!< reg_0p3a_1_counter after xpd reach target1 */ + uint32_t : 1; + __IOM uint32_t LP_CPU_EXC_INT_ENA : 1; /*!< need_des */ + __IOM uint32_t SDIO_IDLE_INT_ENA : 1; /*!< need_des */ + __IOM uint32_t SW_INT_ENA : 1; /*!< need_des */ + __IOM uint32_t SOC_SLEEP_REJECT_INT_ENA : 1;/*!< need_des */ + __IOM uint32_t SOC_WAKEUP_INT_ENA : 1; /*!< need_des */ + } bit; + } HP_INT_ENA; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 14; + __OM uint32_t _0P1A_CNT_TARGET0_REACH_0_HP_INT_CLR : 1;/*!< reg_0p1a_0_counter after xpd reach target0 */ + __OM uint32_t _0P1A_CNT_TARGET1_REACH_0_HP_INT_CLR : 1;/*!< reg_0p1a_1_counter after xpd reach target1 */ + __OM uint32_t _0P1A_CNT_TARGET0_REACH_1_HP_INT_CLR : 1;/*!< reg_0p1a_0 counter after xpd reach target0 */ + __OM uint32_t _0P1A_CNT_TARGET1_REACH_1_HP_INT_CLR : 1;/*!< reg_0p1a_1_counter after xpd reach target1 */ + __OM uint32_t _0P2A_CNT_TARGET0_REACH_0_HP_INT_CLR : 1;/*!< reg_0p2a_0 counter after xpd reach target0 */ + __OM uint32_t _0P2A_CNT_TARGET1_REACH_0_HP_INT_CLR : 1;/*!< reg_0p2a_1_counter after xpd reach target1 */ + __OM uint32_t _0P2A_CNT_TARGET0_REACH_1_HP_INT_CLR : 1;/*!< reg_0p2a_0 counter after xpd reach target0 */ + __OM uint32_t _0P2A_CNT_TARGET1_REACH_1_HP_INT_CLR : 1;/*!< reg_0p2a_1_counter after xpd reach target1 */ + __OM uint32_t _0P3A_CNT_TARGET0_REACH_0_HP_INT_CLR : 1;/*!< reg_0p3a_0 counter after xpd reach target0 */ + __OM uint32_t _0P3A_CNT_TARGET1_REACH_0_HP_INT_CLR : 1;/*!< reg_0p3a_1_counter after xpd reach target1 */ + __OM uint32_t _0P3A_CNT_TARGET0_REACH_1_HP_INT_CLR : 1;/*!< reg_0p3a_0_counter after xpd reach target0 */ + __OM uint32_t _0P3A_CNT_TARGET1_REACH_1_HP_INT_CLR : 1;/*!< reg_0p3a_1_counter after xpd reach target1 */ + uint32_t : 1; + __OM uint32_t LP_CPU_EXC_INT_CLR : 1; /*!< need_des */ + __OM uint32_t SDIO_IDLE_INT_CLR : 1; /*!< need_des */ + __OM uint32_t SW_INT_CLR : 1; /*!< need_des */ + __OM uint32_t SOC_SLEEP_REJECT_INT_CLR : 1;/*!< need_des */ + __OM uint32_t SOC_WAKEUP_INT_CLR : 1; /*!< need_des */ + } bit; + } HP_INT_CLR; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 13; + __IOM uint32_t LP_CPU_SLEEP_REJECT_INT_RAW : 1;/*!< need_des */ + __IOM uint32_t _0P1A_CNT_TARGET0_REACH_0_LP_INT_RAW : 1;/*!< reg_0p1a_0_counter after xpd reach target0 */ + __IOM uint32_t _0P1A_CNT_TARGET1_REACH_0_LP_INT_RAW : 1;/*!< reg_0p1a_1_counter after xpd reach target1 */ + __IOM uint32_t _0P1A_CNT_TARGET0_REACH_1_LP_INT_RAW : 1;/*!< reg_0p1a_0 counter after xpd reach target0 */ + __IOM uint32_t _0P1A_CNT_TARGET1_REACH_1_LP_INT_RAW : 1;/*!< reg_0p1a_1_counter after xpd reach target1 */ + __IOM uint32_t _0P2A_CNT_TARGET0_REACH_0_LP_INT_RAW : 1;/*!< reg_0p2a_0 counter after xpd reach target0 */ + __IOM uint32_t _0P2A_CNT_TARGET1_REACH_0_LP_INT_RAW : 1;/*!< reg_0p2a_1_counter after xpd reach target1 */ + __IOM uint32_t _0P2A_CNT_TARGET0_REACH_1_LP_INT_RAW : 1;/*!< reg_0p2a_0 counter after xpd reach target0 */ + __IOM uint32_t _0P2A_CNT_TARGET1_REACH_1_LP_INT_RAW : 1;/*!< reg_0p2a_1_counter after xpd reach target1 */ + __IOM uint32_t _0P3A_CNT_TARGET0_REACH_0_LP_INT_RAW : 1;/*!< reg_0p3a_0 counter after xpd reach target0 */ + __IOM uint32_t _0P3A_CNT_TARGET1_REACH_0_LP_INT_RAW : 1;/*!< reg_0p3a_1_counter after xpd reach target1 */ + __IOM uint32_t _0P3A_CNT_TARGET0_REACH_1_LP_INT_RAW : 1;/*!< reg_0p3a_0_counter after xpd reach target0 */ + __IOM uint32_t _0P3A_CNT_TARGET1_REACH_1_LP_INT_RAW : 1;/*!< reg_0p3a_1_counter after xpd reach target1 */ + __IOM uint32_t LP_CPU_WAKEUP_INT_RAW : 1; /*!< need_des */ + __IOM uint32_t SLEEP_SWITCH_ACTIVE_END_INT_RAW : 1;/*!< need_des */ + __IOM uint32_t ACTIVE_SWITCH_SLEEP_END_INT_RAW : 1;/*!< need_des */ + __IOM uint32_t SLEEP_SWITCH_ACTIVE_START_INT_RAW : 1;/*!< need_des */ + __IOM uint32_t ACTIVE_SWITCH_SLEEP_START_INT_RAW : 1;/*!< need_des */ + __IOM uint32_t HP_SW_TRIGGER_INT_RAW : 1; /*!< need_des */ + } bit; + } LP_INT_RAW; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 13; + __IM uint32_t LP_CPU_SLEEP_REJECT_INT_ST : 1;/*!< need_des */ + __IM uint32_t _0P1A_CNT_TARGET0_REACH_0_LP_INT_ST : 1;/*!< reg_0p1a_0_counter after xpd reach target0 */ + __IM uint32_t _0P1A_CNT_TARGET1_REACH_0_LP_INT_ST : 1;/*!< reg_0p1a_1_counter after xpd reach target1 */ + __IM uint32_t _0P1A_CNT_TARGET0_REACH_1_LP_INT_ST : 1;/*!< reg_0p1a_0 counter after xpd reach target0 */ + __IM uint32_t _0P1A_CNT_TARGET1_REACH_1_LP_INT_ST : 1;/*!< reg_0p1a_1_counter after xpd reach target1 */ + __IM uint32_t _0P2A_CNT_TARGET0_REACH_0_LP_INT_ST : 1;/*!< reg_0p2a_0 counter after xpd reach target0 */ + __IM uint32_t _0P2A_CNT_TARGET1_REACH_0_LP_INT_ST : 1;/*!< reg_0p2a_1_counter after xpd reach target1 */ + __IM uint32_t _0P2A_CNT_TARGET0_REACH_1_LP_INT_ST : 1;/*!< reg_0p2a_0 counter after xpd reach target0 */ + __IM uint32_t _0P2A_CNT_TARGET1_REACH_1_LP_INT_ST : 1;/*!< reg_0p2a_1_counter after xpd reach target1 */ + __IM uint32_t _0P3A_CNT_TARGET0_REACH_0_LP_INT_ST : 1;/*!< reg_0p3a_0 counter after xpd reach target0 */ + __IM uint32_t _0P3A_CNT_TARGET1_REACH_0_LP_INT_ST : 1;/*!< reg_0p3a_1_counter after xpd reach target1 */ + __IM uint32_t _0P3A_CNT_TARGET0_REACH_1_LP_INT_ST : 1;/*!< reg_0p3a_0_counter after xpd reach target0 */ + __IM uint32_t _0P3A_CNT_TARGET1_REACH_1_LP_INT_ST : 1;/*!< reg_0p3a_1_counter after xpd reach target1 */ + __IM uint32_t LP_CPU_WAKEUP_INT_ST : 1; /*!< need_des */ + __IM uint32_t SLEEP_SWITCH_ACTIVE_END_INT_ST : 1;/*!< need_des */ + __IM uint32_t ACTIVE_SWITCH_SLEEP_END_INT_ST : 1;/*!< need_des */ + __IM uint32_t SLEEP_SWITCH_ACTIVE_START_INT_ST : 1;/*!< need_des */ + __IM uint32_t ACTIVE_SWITCH_SLEEP_START_INT_ST : 1;/*!< need_des */ + __IM uint32_t HP_SW_TRIGGER_INT_ST : 1; /*!< need_des */ + } bit; + } LP_INT_ST; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 13; + __IOM uint32_t LP_CPU_SLEEP_REJECT_INT_ENA : 1;/*!< need_des */ + __IOM uint32_t _0P1A_CNT_TARGET0_REACH_0_LP_INT_ENA : 1;/*!< reg_0p1a_0_counter after xpd reach target0 */ + __IOM uint32_t _0P1A_CNT_TARGET1_REACH_0_LP_INT_ENA : 1;/*!< reg_0p1a_1_counter after xpd reach target1 */ + __IOM uint32_t _0P1A_CNT_TARGET0_REACH_1_LP_INT_ENA : 1;/*!< reg_0p1a_0 counter after xpd reach target0 */ + __IOM uint32_t _0P1A_CNT_TARGET1_REACH_1_LP_INT_ENA : 1;/*!< reg_0p1a_1_counter after xpd reach target1 */ + __IOM uint32_t _0P2A_CNT_TARGET0_REACH_0_LP_INT_ENA : 1;/*!< reg_0p2a_0 counter after xpd reach target0 */ + __IOM uint32_t _0P2A_CNT_TARGET1_REACH_0_LP_INT_ENA : 1;/*!< reg_0p2a_1_counter after xpd reach target1 */ + __IOM uint32_t _0P2A_CNT_TARGET0_REACH_1_LP_INT_ENA : 1;/*!< reg_0p2a_0 counter after xpd reach target0 */ + __IOM uint32_t _0P2A_CNT_TARGET1_REACH_1_LP_INT_ENA : 1;/*!< reg_0p2a_1_counter after xpd reach target1 */ + __IOM uint32_t _0P3A_CNT_TARGET0_REACH_0_LP_INT_ENA : 1;/*!< reg_0p3a_0 counter after xpd reach target0 */ + __IOM uint32_t _0P3A_CNT_TARGET1_REACH_0_LP_INT_ENA : 1;/*!< reg_0p3a_1_counter after xpd reach target1 */ + __IOM uint32_t _0P3A_CNT_TARGET0_REACH_1_LP_INT_ENA : 1;/*!< reg_0p3a_0_counter after xpd reach target0 */ + __IOM uint32_t _0P3A_CNT_TARGET1_REACH_1_LP_INT_ENA : 1;/*!< reg_0p3a_1_counter after xpd reach target1 */ + __IOM uint32_t LP_CPU_WAKEUP_INT_ENA : 1; /*!< need_des */ + __IOM uint32_t SLEEP_SWITCH_ACTIVE_END_INT_ENA : 1;/*!< need_des */ + __IOM uint32_t ACTIVE_SWITCH_SLEEP_END_INT_ENA : 1;/*!< need_des */ + __IOM uint32_t SLEEP_SWITCH_ACTIVE_START_INT_ENA : 1;/*!< need_des */ + __IOM uint32_t ACTIVE_SWITCH_SLEEP_START_INT_ENA : 1;/*!< need_des */ + __IOM uint32_t HP_SW_TRIGGER_INT_ENA : 1; /*!< need_des */ + } bit; + } LP_INT_ENA; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 13; + __OM uint32_t LP_CPU_SLEEP_REJECT_LP_INT_CLR : 1;/*!< need_des */ + __OM uint32_t _0P1A_CNT_TARGET0_REACH_0_LP_INT_CLR : 1;/*!< reg_0p1a_0_counter after xpd reach target0 */ + __OM uint32_t _0P1A_CNT_TARGET1_REACH_0_LP_INT_CLR : 1;/*!< reg_0p1a_1_counter after xpd reach target1 */ + __OM uint32_t _0P1A_CNT_TARGET0_REACH_1_LP_INT_CLR : 1;/*!< reg_0p1a_0 counter after xpd reach target0 */ + __OM uint32_t _0P1A_CNT_TARGET1_REACH_1_LP_INT_CLR : 1;/*!< reg_0p1a_1_counter after xpd reach target1 */ + __OM uint32_t _0P2A_CNT_TARGET0_REACH_0_LP_INT_CLR : 1;/*!< reg_0p2a_0 counter after xpd reach target0 */ + __OM uint32_t _0P2A_CNT_TARGET1_REACH_0_LP_INT_CLR : 1;/*!< reg_0p2a_1_counter after xpd reach target1 */ + __OM uint32_t _0P2A_CNT_TARGET0_REACH_1_LP_INT_CLR : 1;/*!< reg_0p2a_0 counter after xpd reach target0 */ + __OM uint32_t _0P2A_CNT_TARGET1_REACH_1_LP_INT_CLR : 1;/*!< reg_0p2a_1_counter after xpd reach target1 */ + __OM uint32_t _0P3A_CNT_TARGET0_REACH_0_LP_INT_CLR : 1;/*!< reg_0p3a_0 counter after xpd reach target0 */ + __OM uint32_t _0P3A_CNT_TARGET1_REACH_0_LP_INT_CLR : 1;/*!< reg_0p3a_1_counter after xpd reach target1 */ + __OM uint32_t _0P3A_CNT_TARGET0_REACH_1_LP_INT_CLR : 1;/*!< reg_0p3a_0_counter after xpd reach target0 */ + __OM uint32_t _0P3A_CNT_TARGET1_REACH_1_LP_INT_CLR : 1;/*!< reg_0p3a_1_counter after xpd reach target1 */ + __OM uint32_t LP_CPU_WAKEUP_INT_CLR : 1; /*!< need_des */ + __OM uint32_t SLEEP_SWITCH_ACTIVE_END_INT_CLR : 1;/*!< need_des */ + __OM uint32_t ACTIVE_SWITCH_SLEEP_END_INT_CLR : 1;/*!< need_des */ + __OM uint32_t SLEEP_SWITCH_ACTIVE_START_INT_CLR : 1;/*!< need_des */ + __OM uint32_t ACTIVE_SWITCH_SLEEP_START_INT_CLR : 1;/*!< need_des */ + __OM uint32_t HP_SW_TRIGGER_INT_CLR : 1; /*!< need_des */ + } bit; + } LP_INT_CLR; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IM uint32_t LP_CPU_WAITI_RDY : 1; /*!< need_des */ + __IM uint32_t LP_CPU_STALL_RDY : 1; /*!< need_des */ + uint32_t : 16; + __IOM uint32_t LP_CPU_FORCE_STALL : 1; /*!< need_des */ + __IOM uint32_t LP_CPU_SLP_WAITI_FLAG_EN : 1;/*!< need_des */ + __IOM uint32_t LP_CPU_SLP_STALL_FLAG_EN : 1;/*!< need_des */ + __IOM uint32_t LP_CPU_SLP_STALL_WAIT : 8; /*!< need_des */ + __IOM uint32_t LP_CPU_SLP_STALL_EN : 1; /*!< need_des */ + __IOM uint32_t LP_CPU_SLP_RESET_EN : 1; /*!< need_des */ + __IOM uint32_t LP_CPU_SLP_BYPASS_INTR_EN : 1;/*!< need_des */ + } bit; + } LP_CPU_PWR0; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 31; + __OM uint32_t LP_CPU_SLEEP_REQ : 1; /*!< need_des */ + } bit; + } LP_CPU_PWR1; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t LP_CPU_WAKEUP_EN : 31; /*!< need_des */ + uint32_t : 1; + } bit; + } LP_CPU_PWR2; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IM uint32_t LP_CPU_WAKEUP_CAUSE : 31; /*!< need_des */ + uint32_t : 1; + } bit; + } LP_CPU_PWR3; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t LP_CPU_REJECT_EN : 31; /*!< need_des */ + uint32_t : 1; + } bit; + } LP_CPU_PWR4; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IM uint32_t LP_CPU_REJECT_CAUSE : 31; /*!< need_des */ + uint32_t : 1; + } bit; + } LP_CPU_PWR5; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 30; + __OM uint32_t LP_TRIGGER_HP : 1; /*!< need_des */ + __OM uint32_t HP_TRIGGER_LP : 1; /*!< need_des */ + } bit; + } HP_LP_CPU_COMM; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 31; + __IOM uint32_t DIG_REGULATOR_EN_CAL : 1; /*!< need_des */ + } bit; + } HP_REGULATOR_CFG; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t ENABLE_CALI_PMU_CNTL : 1; /*!< need_des */ + uint32_t : 10; + __IM uint32_t PMU_MAIN_LAST_ST_STATE : 7;/*!< need_des */ + __IM uint32_t PMU_MAIN_TAR_ST_STATE : 7; /*!< need_des */ + __IM uint32_t PMU_MAIN_CUR_ST_STATE : 7; /*!< need_des */ + } bit; + } MAIN_STATE; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 13; + __IM uint32_t PMU_BACKUP_ST_STATE : 5; /*!< need_des */ + __IM uint32_t PMU_LP_PWR_ST_STATE : 5; /*!< need_des */ + __IM uint32_t PMU_HP_PWR_ST_STATE : 9; /*!< need_des */ + } bit; + } PWR_STATE; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IM uint32_t STABLE_XPD_PLL_STATE : 3; /*!< need_des */ + __IM uint32_t STABLE_XPD_XTAL_STATE : 1; /*!< need_des */ + __IM uint32_t PMU_ANA_XPD_PLL_I2C_STATE : 3;/*!< need_des */ + uint32_t : 3; + __IM uint32_t PMU_SYS_CLK_SLP_SEL_STATE : 1;/*!< need_des */ + __IM uint32_t PMU_SYS_CLK_SEL_STATE : 2; /*!< need_des */ + __IM uint32_t PMU_SYS_CLK_NO_DIV_STATE : 1;/*!< need_des */ + __IM uint32_t PMU_ICG_SYS_CLK_EN_STATE : 1;/*!< need_des */ + __IM uint32_t PMU_ICG_MODEM_SWITCH_STATE : 1;/*!< need_des */ + __IM uint32_t PMU_ICG_MODEM_CODE_STATE : 2;/*!< need_des */ + __IM uint32_t PMU_ICG_SLP_SEL_STATE : 1; /*!< need_des */ + __IM uint32_t PMU_ICG_GLOBAL_XTAL_STATE : 1;/*!< need_des */ + __IM uint32_t PMU_ICG_GLOBAL_PLL_STATE : 4;/*!< need_des */ + __IM uint32_t PMU_ANA_I2C_ISO_EN_STATE : 1;/*!< need_des */ + __IM uint32_t PMU_ANA_I2C_RETENTION_STATE : 1;/*!< need_des */ + uint32_t : 1; + __IM uint32_t PMU_ANA_XPD_PLL_STATE : 4; /*!< need_des */ + __IM uint32_t PMU_ANA_XPD_XTAL_STATE : 1;/*!< need_des */ + } bit; + } CLK_STATE0; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IM uint32_t PMU_ICG_FUNC_EN_STATE : 32;/*!< need_des */ + } bit; + } CLK_STATE1; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IM uint32_t PMU_ICG_APB_EN_STATE : 32; /*!< need_des */ + } bit; + } CLK_STATE2; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 7; + __IOM uint32_t _0P1A_FORCE_TIEH_SEL_0 : 1;/*!< need_des */ + __IOM uint32_t _0P1A_XPD_0 : 1; /*!< need_des */ + __IOM uint32_t _0P1A_TIEH_SEL_0 : 3; /*!< need_des */ + __IOM uint32_t _0P1A_TIEH_POS_EN_0 : 1; /*!< need_des */ + __IOM uint32_t _0P1A_TIEH_NEG_EN_0 : 1; /*!< need_des */ + __IOM uint32_t _0P1A_TIEH_0 : 1; /*!< need_des */ + __IOM uint32_t _0P1A_TARGET1_0 : 8; /*!< need_des */ + __IOM uint32_t _0P1A_TARGET0_0 : 8; /*!< need_des */ + __IOM uint32_t _0P1A_LDO_CNT_PRESCALER_SEL_0 : 1;/*!< need_des */ + } bit; + } EXT_LDO_P0_0P1A; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 23; + __IOM uint32_t ANA_0P1A_MUL_0 : 3; /*!< need_des */ + __IOM uint32_t ANA_0P1A_EN_VDET_0 : 1; /*!< need_des */ + __IOM uint32_t ANA_0P1A_EN_CUR_LIM_0 : 1; /*!< need_des */ + __IOM uint32_t ANA_0P1A_DREF_0 : 4; /*!< need_des */ + } bit; + } EXT_LDO_P0_0P1A_ANA; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 7; + __IOM uint32_t _0P2A_FORCE_TIEH_SEL_0 : 1;/*!< need_des */ + __IOM uint32_t _0P2A_XPD_0 : 1; /*!< need_des */ + __IOM uint32_t _0P2A_TIEH_SEL_0 : 3; /*!< need_des */ + __IOM uint32_t _0P2A_TIEH_POS_EN_0 : 1; /*!< need_des */ + __IOM uint32_t _0P2A_TIEH_NEG_EN_0 : 1; /*!< need_des */ + __IOM uint32_t _0P2A_TIEH_0 : 1; /*!< need_des */ + __IOM uint32_t _0P2A_TARGET1_0 : 8; /*!< need_des */ + __IOM uint32_t _0P2A_TARGET0_0 : 8; /*!< need_des */ + __IOM uint32_t _0P2A_LDO_CNT_PRESCALER_SEL_0 : 1;/*!< need_des */ + } bit; + } EXT_LDO_P0_0P2A; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 23; + __IOM uint32_t ANA_0P2A_MUL_0 : 3; /*!< need_des */ + __IOM uint32_t ANA_0P2A_EN_VDET_0 : 1; /*!< need_des */ + __IOM uint32_t ANA_0P2A_EN_CUR_LIM_0 : 1; /*!< need_des */ + __IOM uint32_t ANA_0P2A_DREF_0 : 4; /*!< need_des */ + } bit; + } EXT_LDO_P0_0P2A_ANA; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 7; + __IOM uint32_t _0P3A_FORCE_TIEH_SEL_0 : 1;/*!< need_des */ + __IOM uint32_t _0P3A_XPD_0 : 1; /*!< need_des */ + __IOM uint32_t _0P3A_TIEH_SEL_0 : 3; /*!< need_des */ + __IOM uint32_t _0P3A_TIEH_POS_EN_0 : 1; /*!< need_des */ + __IOM uint32_t _0P3A_TIEH_NEG_EN_0 : 1; /*!< need_des */ + __IOM uint32_t _0P3A_TIEH_0 : 1; /*!< need_des */ + __IOM uint32_t _0P3A_TARGET1_0 : 8; /*!< need_des */ + __IOM uint32_t _0P3A_TARGET0_0 : 8; /*!< need_des */ + __IOM uint32_t _0P3A_LDO_CNT_PRESCALER_SEL_0 : 1;/*!< need_des */ + } bit; + } EXT_LDO_P0_0P3A; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 23; + __IOM uint32_t ANA_0P3A_MUL_0 : 3; /*!< need_des */ + __IOM uint32_t ANA_0P3A_EN_VDET_0 : 1; /*!< need_des */ + __IOM uint32_t ANA_0P3A_EN_CUR_LIM_0 : 1; /*!< need_des */ + __IOM uint32_t ANA_0P3A_DREF_0 : 4; /*!< need_des */ + } bit; + } EXT_LDO_P0_0P3A_ANA; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 7; + __IOM uint32_t _0P1A_FORCE_TIEH_SEL_1 : 1;/*!< need_des */ + __IOM uint32_t _0P1A_XPD_1 : 1; /*!< need_des */ + __IOM uint32_t _0P1A_TIEH_SEL_1 : 3; /*!< need_des */ + __IOM uint32_t _0P1A_TIEH_POS_EN_1 : 1; /*!< need_des */ + __IOM uint32_t _0P1A_TIEH_NEG_EN_1 : 1; /*!< need_des */ + __IOM uint32_t _0P1A_TIEH_1 : 1; /*!< need_des */ + __IOM uint32_t _0P1A_TARGET1_1 : 8; /*!< need_des */ + __IOM uint32_t _0P1A_TARGET0_1 : 8; /*!< need_des */ + __IOM uint32_t _0P1A_LDO_CNT_PRESCALER_SEL_1 : 1;/*!< need_des */ + } bit; + } EXT_LDO_P1_0P1A; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 23; + __IOM uint32_t ANA_0P1A_MUL_1 : 3; /*!< need_des */ + __IOM uint32_t ANA_0P1A_EN_VDET_1 : 1; /*!< need_des */ + __IOM uint32_t ANA_0P1A_EN_CUR_LIM_1 : 1; /*!< need_des */ + __IOM uint32_t ANA_0P1A_DREF_1 : 4; /*!< need_des */ + } bit; + } EXT_LDO_P1_0P1A_ANA; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 7; + __IOM uint32_t _0P2A_FORCE_TIEH_SEL_1 : 1;/*!< need_des */ + __IOM uint32_t _0P2A_XPD_1 : 1; /*!< need_des */ + __IOM uint32_t _0P2A_TIEH_SEL_1 : 3; /*!< need_des */ + __IOM uint32_t _0P2A_TIEH_POS_EN_1 : 1; /*!< need_des */ + __IOM uint32_t _0P2A_TIEH_NEG_EN_1 : 1; /*!< need_des */ + __IOM uint32_t _0P2A_TIEH_1 : 1; /*!< need_des */ + __IOM uint32_t _0P2A_TARGET1_1 : 8; /*!< need_des */ + __IOM uint32_t _0P2A_TARGET0_1 : 8; /*!< need_des */ + __IOM uint32_t _0P2A_LDO_CNT_PRESCALER_SEL_1 : 1;/*!< need_des */ + } bit; + } EXT_LDO_P1_0P2A; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 23; + __IOM uint32_t ANA_0P2A_MUL_1 : 3; /*!< need_des */ + __IOM uint32_t ANA_0P2A_EN_VDET_1 : 1; /*!< need_des */ + __IOM uint32_t ANA_0P2A_EN_CUR_LIM_1 : 1; /*!< need_des */ + __IOM uint32_t ANA_0P2A_DREF_1 : 4; /*!< need_des */ + } bit; + } EXT_LDO_P1_0P2A_ANA; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 7; + __IOM uint32_t _0P3A_FORCE_TIEH_SEL_1 : 1;/*!< need_des */ + __IOM uint32_t _0P3A_XPD_1 : 1; /*!< need_des */ + __IOM uint32_t _0P3A_TIEH_SEL_1 : 3; /*!< need_des */ + __IOM uint32_t _0P3A_TIEH_POS_EN_1 : 1; /*!< need_des */ + __IOM uint32_t _0P3A_TIEH_NEG_EN_1 : 1; /*!< need_des */ + __IOM uint32_t _0P3A_TIEH_1 : 1; /*!< need_des */ + __IOM uint32_t _0P3A_TARGET1_1 : 8; /*!< need_des */ + __IOM uint32_t _0P3A_TARGET0_1 : 8; /*!< need_des */ + __IOM uint32_t _0P3A_LDO_CNT_PRESCALER_SEL_1 : 1;/*!< need_des */ + } bit; + } EXT_LDO_P1_0P3A; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 23; + __IOM uint32_t ANA_0P3A_MUL_1 : 3; /*!< need_des */ + __IOM uint32_t ANA_0P3A_EN_VDET_1 : 1; /*!< need_des */ + __IOM uint32_t ANA_0P3A_EN_CUR_LIM_1 : 1; /*!< need_des */ + __IOM uint32_t ANA_0P3A_DREF_1 : 4; /*!< need_des */ + } bit; + } EXT_LDO_P1_0P3A_ANA; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t EXT_WAKEUP_LV : 32; /*!< need_des */ + } bit; + } EXT_WAKEUP_LV; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t EXT_WAKEUP_SEL : 32; /*!< need_des */ + } bit; + } EXT_WAKEUP_SEL; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IM uint32_t EXT_WAKEUP_STATUS : 32; /*!< need_des */ + } bit; + } EXT_WAKEUP_ST; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 30; + __IOM uint32_t EXT_WAKEUP_STATUS_CLR : 1; /*!< need_des */ + __IOM uint32_t EXT_WAKEUP_FILTER : 1; /*!< need_des */ + } bit; + } EXT_WAKEUP_CNTL; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t SDIO_ACT_DNUM : 10; /*!< need_des */ + uint32_t : 22; + } bit; + } SDIO_WAKEUP_CNTL; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 16; + __IOM uint32_t CNT_TARGET : 16; /*!< need_des */ + } bit; + } XTAL_SLP; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 16; + __IOM uint32_t HPCORE1_SW_STALL_CODE : 8; /*!< need_des */ + __IOM uint32_t HPCORE0_SW_STALL_CODE : 8; /*!< need_des */ + } bit; + } CPU_SW_STALL; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __OM uint32_t DCDC_ON_REQ : 1; /*!< SW trigger dcdc on */ + __OM uint32_t DCDC_OFF_REQ : 1; /*!< SW trigger dcdc off */ + __OM uint32_t DCDC_LIGHTSLP_REQ : 1; /*!< SW trigger dcdc enter lightsleep */ + __OM uint32_t DCDC_DEEPSLP_REQ : 1; /*!< SW trigger dcdc enter deepsleep */ + uint32_t : 3; + __IOM uint32_t DCDC_DONE_FORCE : 1; /*!< need_des */ + __IOM uint32_t DCDC_ON_FORCE_PU : 1; /*!< need_des */ + __IOM uint32_t DCDC_ON_FORCE_PD : 1; /*!< need_des */ + __IOM uint32_t DCDC_FB_RES_FORCE_PU : 1; /*!< need_des */ + __IOM uint32_t DCDC_FB_RES_FORCE_PD : 1; /*!< need_des */ + __IOM uint32_t DCDC_LS_FORCE_PU : 1; /*!< need_des */ + __IOM uint32_t DCDC_LS_FORCE_PD : 1; /*!< need_des */ + __IOM uint32_t DCDC_DS_FORCE_PU : 1; /*!< need_des */ + __IOM uint32_t DCDC_DS_FORCE_PD : 1; /*!< need_des */ + __IM uint32_t DCM_CUR_ST : 8; /*!< need_des */ + uint32_t : 5; + __IOM uint32_t DCDC_EN_AMUX_TEST : 1; /*!< Enable analog mux to pull PAD TEST_DCDC voltage signal */ + uint32_t : 2; + } bit; + } DCM_CTRL; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t DCDC_PRE_DELAY : 8; /*!< DCDC pre-on/post off delay */ + __IOM uint32_t DCDC_RES_OFF_DELAY : 8; /*!< DCDC fb res off delay */ + __IOM uint32_t DCDC_STABLE_DELAY : 10; /*!< DCDC stable delay */ + uint32_t : 6; + } bit; + } DCM_WAIT_DELAY; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IM uint32_t ANA_VDDBAT_MODE : 2; /*!< need_des */ + uint32_t : 29; + __OM uint32_t VDDBAT_SW_UPDATE : 1; /*!< need_des */ + } bit; + } VDDBAT_CFG; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 5; + __IOM uint32_t TOUCH_WAIT_CYCLES : 9; /*!< need_des */ + __IOM uint32_t TOUCH_SLEEP_CYCLES : 16; /*!< need_des */ + __IOM uint32_t TOUCH_FORCE_DONE : 1; /*!< need_des */ + __IOM uint32_t TOUCH_SLEEP_TIMER_EN : 1; /*!< need_des */ + } bit; + } TOUCH_PWR_CNTL; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IM uint32_t PMU_RDN_ECO_RESULT : 1; /*!< need_des */ + uint32_t : 30; + __IOM uint32_t PMU_RDN_ECO_EN : 1; /*!< need_des */ + } bit; + } RDN_ECO; + __IM uint32_t RESERVED[121]; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t PMU_DATE : 31; /*!< need_des */ + __IOM uint32_t CLK_EN : 1; /*!< need_des */ + } bit; + } DATE; +} PMU_Type; /*!< Size = 1024 (0x400) */ + + + +/* =========================================================================================================================== */ +/* ================ PPA ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief PPA Peripheral (PPA) + */ + +typedef struct { /*!< PPA Structure */ + + union { + __IOM uint32_t reg; /*!< CLUT sram data read/write register in background plane of blender */ + + struct { + __IOM uint32_t RDWR_WORD_BLEND0_CLUT : 32;/*!< Write and read data to/from CLUT RAM in background plane of + blender engine through this field in fifo mode. */ + } bit; + } BLEND0_CLUT_DATA; + + union { + __IOM uint32_t reg; /*!< CLUT sram data read/write register in foreground plane of blender */ + + struct { + __IOM uint32_t RDWR_WORD_BLEND1_CLUT : 32;/*!< Write and read data to/from CLUT RAM in foreground plane of + blender engine through this field in fifo mode. */ + } bit; + } BLEND1_CLUT_DATA; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t reg; /*!< CLUT configure register */ + + struct { + __IOM uint32_t APB_FIFO_MASK : 1; /*!< 1'b0: fifo mode to wr/rd clut0/clut1 RAM through register PPA_SR_CLUT_DATA_REG + PPA_BLEND0_CLUT_DATA_REG/PPA_BLEND1_CLUT_DATA_REG. 1'b1: + memory mode to wr/rd sr/blend0/blend1 clut RAM. The bit + 11 and 10 of the waddr should be 01 to access sr clut and + should be 10 to access blend0 clut and should be 11 to + access blend 1 clut in memory mode. */ + __IOM uint32_t BLEND0_CLUT_MEM_RST : 1; /*!< Write 1 then write 0 to this bit to reset BLEND0 CLUT. */ + __IOM uint32_t BLEND1_CLUT_MEM_RST : 1; /*!< Write 1 then write 0 to this bit to reset BLEND1 CLUT. */ + __IOM uint32_t BLEND0_CLUT_MEM_RDADDR_RST : 1;/*!< Write 1 then write 0 to reset the read address of BLEND0 CLUT + in fifo mode. */ + __IOM uint32_t BLEND1_CLUT_MEM_RDADDR_RST : 1;/*!< Write 1 then write 0 to reset the read address of BLEND1 CLUT + in fifo mode. */ + __IOM uint32_t BLEND0_CLUT_MEM_FORCE_PD : 1;/*!< 1: force power down BLEND CLUT memory. */ + __IOM uint32_t BLEND0_CLUT_MEM_FORCE_PU : 1;/*!< 1: force power up BLEND CLUT memory. */ + __IOM uint32_t BLEND0_CLUT_MEM_CLK_ENA : 1;/*!< 1: Force clock on for BLEND CLUT memory. */ + uint32_t : 24; + } bit; + } CLUT_CONF; + + union { + __IOM uint32_t reg; /*!< Raw status interrupt */ + + struct { + __IOM uint32_t SR_EOF_INT_RAW : 1; /*!< The raw interrupt bit turns to high level when scaling and rotating + engine calculate one frame image. */ + __IOM uint32_t BLEND_EOF_INT_RAW : 1; /*!< The raw interrupt bit turns to high level when blending engine + calculate one frame image. */ + __IOM uint32_t SR_PARAM_CFG_ERR_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when the configured + scaling and rotating coefficient is wrong. User can check + the reasons through register PPA_SR_PARAM_ERR_ST_REG. */ + uint32_t : 29; + } bit; + } INT_RAW; + + union { + __IOM uint32_t reg; /*!< Masked interrupt */ + + struct { + __IM uint32_t SR_EOF_INT_ST : 1; /*!< The raw interrupt status bit for the PPA_SR_EOF_INT interrupt. */ + __IM uint32_t BLEND_EOF_INT_ST : 1; /*!< The raw interrupt status bit for the PPA_BLEND_EOF_INT interrupt. */ + __IM uint32_t SR_PARAM_CFG_ERR_INT_ST : 1;/*!< The raw interrupt status bit for the PPA_SR_RX_YSCAL_ERR_INT + interrupt. */ + uint32_t : 29; + } bit; + } INT_ST; + + union { + __IOM uint32_t reg; /*!< Interrupt enable bits */ + + struct { + __IOM uint32_t SR_EOF_INT_ENA : 1; /*!< The interrupt enable bit for the PPA_SR_EOF_INT interrupt. */ + __IOM uint32_t BLEND_EOF_INT_ENA : 1; /*!< The interrupt enable bit for the PPA_BLEND_EOF_INT interrupt. */ + __IOM uint32_t SR_PARAM_CFG_ERR_INT_ENA : 1;/*!< The interrupt enable bit for the PPA_SR_RX_YSCAL_ERR_INT interrupt. */ + uint32_t : 29; + } bit; + } INT_ENA; + + union { + __IOM uint32_t reg; /*!< Interrupt clear bits */ + + struct { + __OM uint32_t SR_EOF_INT_CLR : 1; /*!< Set this bit to clear the PPA_SR_EOF_INT interrupt. */ + __OM uint32_t BLEND_EOF_INT_CLR : 1; /*!< Set this bit to clear the PPA_BLEND_EOF_INT interrupt. */ + __OM uint32_t SR_PARAM_CFG_ERR_INT_CLR : 1;/*!< Set this bit to clear the PPA_SR_RX_YSCAL_ERR_INT interrupt. */ + uint32_t : 29; + } bit; + } INT_CLR; + + union { + __IOM uint32_t reg; /*!< Scaling and rotating engine color mode register */ + + struct { + __IOM uint32_t SR_RX_CM : 4; /*!< The source image color mode for Scaling and Rotating engine + Rx. 0: ARGB8888. 1: RGB888. 2: RGB565. 8: YUV420. others: + Reserved. */ + __IOM uint32_t SR_TX_CM : 4; /*!< The destination image color mode for Scaling and Rotating engine + Tx. 0: ARGB8888. 1: RGB888. 2: RGB565. 8: YUV420. others: + Reserved. */ + __IOM uint32_t YUV_RX_RANGE : 1; /*!< YUV input range when reg_sr_rx_cm is 4'd8. 0: limit range. 1: + full range */ + __IOM uint32_t YUV_TX_RANGE : 1; /*!< YUV output range when reg_sr_tx_cm is 4'd8. 0: limit range. + 1: full range */ + __IOM uint32_t YUV2RGB_PROTOCAL : 1; /*!< YUV to RGB protocal when reg_sr_rx_cm is 4'd8. 0: BT601. 1: + BT709 */ + __IOM uint32_t RGB2YUV_PROTOCAL : 1; /*!< RGB to YUV protocal when reg_sr_tx_cm is 4'd8. 0: BT601. 1: + BT709 */ + uint32_t : 20; + } bit; + } SR_COLOR_MODE; + + union { + __IOM uint32_t reg; /*!< blending engine color mode register */ + + struct { + __IOM uint32_t BLEND0_RX_CM : 4; /*!< The source image color mode for background plane. 0: ARGB8888. + 1: RGB888. 2: RGB565. 3: Reserved. 4: L8. 5: L4. */ + __IOM uint32_t BLEND1_RX_CM : 4; /*!< The source image color mode for foreground plane. 0: ARGB8888. + 1: RGB888. 2: RGB565. 3: Reserved. 4: L8. 5: L4. 6: A8. + 7: A4. */ + __IOM uint32_t BLEND_TX_CM : 4; /*!< The destination image color mode for output of blender. 0: ARGB8888. + 1: RGB888. 2: RGB565. 3: Reserved.. */ + uint32_t : 20; + } bit; + } BLEND_COLOR_MODE; + + union { + __IOM uint32_t reg; /*!< Scaling and rotating engine byte order register */ + + struct { + __IOM uint32_t SR_RX_BYTE_SWAP_EN : 1; /*!< Set this bit to 1 the data into Rx channel 0 would be swapped + in byte. The Byte0 and Byte1 would be swapped while byte + 2 and byte 3 would be swappped. */ + __IOM uint32_t SR_RX_RGB_SWAP_EN : 1; /*!< Set this bit to 1 the data into Rx channel 0 would be swapped + in rgb. It means rgb would be swap to bgr. */ + __IOM uint32_t SR_MACRO_BK_RO_BYPASS : 1; /*!< Set this bit to 1 to bypass the macro block order function. + This function is used to improve efficient accessing external + memory. */ + uint32_t : 29; + } bit; + } SR_BYTE_ORDER; + + union { + __IOM uint32_t reg; /*!< Blending engine byte order register */ + + struct { + __IOM uint32_t BLEND0_RX_BYTE_SWAP_EN : 1;/*!< Set this bit to 1 the data into Rx channel 0 would be swapped + in byte. The Byte0 and Byte1 would be swapped while byte + 2 and byte 3 would be swappped. */ + __IOM uint32_t BLEND1_RX_BYTE_SWAP_EN : 1;/*!< Set this bit to 1 the data into Rx channel 0 would be swapped + in byte. The Byte0 and Byte1 would be swapped while byte + 2 and byte 3 would be swappped. */ + __IOM uint32_t BLEND0_RX_RGB_SWAP_EN : 1; /*!< Set this bit to 1 the data into Rx channel 0 would be swapped + in rgb. It means rgb would be swap to bgr. */ + __IOM uint32_t BLEND1_RX_RGB_SWAP_EN : 1; /*!< Set this bit to 1 the data into Rx channel 0 would be swapped + in rgb. It means rgb would be swap to bgr. */ + uint32_t : 28; + } bit; + } BLEND_BYTE_ORDER; + __IM uint32_t RESERVED1; + + union { + __IOM uint32_t reg; /*!< Blending engine mode configure register */ + + struct { + __IOM uint32_t BLEND_EN : 1; /*!< Set this bit to enable alpha blending. */ + __IOM uint32_t BLEND_BYPASS : 1; /*!< Set this bit to bypass blender. Then background date would be + output. */ + __IOM uint32_t BLEND_FIX_PIXEL_FILL_EN : 1;/*!< This bit is used to enable fix pixel filling. When this mode + is enable only Tx channel is work and the output pixel + is configured by PPA_OUT_FIX_PIXEL. */ + __OM uint32_t UPDATE : 1; /*!< Set this bit to update the transfer mode. Only the bit is set + the transfer mode is valid. */ + __IOM uint32_t BLEND_RST : 1; /*!< write 1 then write 0 to reset blending engine. */ + uint32_t : 27; + } bit; + } BLEND_TRANS_MODE; + + union { + __IOM uint32_t reg; /*!< Scaling and rotating engine alpha override register */ + + struct { + __IOM uint32_t SR_RX_FIX_ALPHA : 8; /*!< The value would replace the alpha value in received pixel for + Scaling and Rotating engine when PPA_SR_RX_ALPHA_CONF_EN + is enabled. */ + __IOM uint32_t SR_RX_ALPHA_MOD : 2; /*!< Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_SR_FIX_ALPHA. + 2: Original alpha multiply with PPA_SR_FIX_ALPHA/256. */ + __IOM uint32_t SR_RX_ALPHA_INV : 1; /*!< Set this bit to invert the original alpha value. When RX color + mode is RGB565/RGB88. The original alpha value is 255. */ + uint32_t : 21; + } bit; + } SR_FIX_ALPHA; + + union { + __IOM uint32_t reg; /*!< Fix pixel filling mode image size register */ + + struct { + __IOM uint32_t BLEND_HB : 14; /*!< The horizontal width of image block that would be filled in + fix pixel filling mode. The unit is pixel */ + __IOM uint32_t BLEND_VB : 14; /*!< The vertical width of image block that would be filled in fix + pixel filling mode. The unit is pixel */ + uint32_t : 4; + } bit; + } BLEND_TX_SIZE; + + union { + __IOM uint32_t reg; /*!< Blending engine alpha override register */ + + struct { + __IOM uint32_t BLEND0_RX_FIX_ALPHA : 8; /*!< The value would replace the alpha value in received pixel for + background plane of blender when PPA_BLEND0_RX_ALPHA_CONF_EN + is enabled. */ + __IOM uint32_t BLEND1_RX_FIX_ALPHA : 8; /*!< The value would replace the alpha value in received pixel for + foreground plane of blender when PPA_BLEND1_RX_ALPHA_CONF_EN + is enabled. */ + __IOM uint32_t BLEND0_RX_ALPHA_MOD : 2; /*!< Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_SR_FIX_ALPHA. + 2: Original alpha multiply with PPA_SR_FIX_ALPHA/256. */ + __IOM uint32_t BLEND1_RX_ALPHA_MOD : 2; /*!< Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_SR_FIX_ALPHA. + 2: Original alpha multiply with PPA_SR_FIX_ALPHA/256. */ + __IOM uint32_t BLEND0_RX_ALPHA_INV : 1; /*!< Set this bit to invert the original alpha value. When RX color + mode is RGB565/RGB88. The original alpha value is 255. */ + __IOM uint32_t BLEND1_RX_ALPHA_INV : 1; /*!< Set this bit to invert the original alpha value. When RX color + mode is RGB565/RGB88. The original alpha value is 255. */ + uint32_t : 10; + } bit; + } BLEND_FIX_ALPHA; + __IM uint32_t RESERVED2; + + union { + __IOM uint32_t reg; /*!< RGB color register */ + + struct { + __IOM uint32_t BLEND1_RX_B : 8; /*!< blue color for A4/A8 mode. */ + __IOM uint32_t BLEND1_RX_G : 8; /*!< green color for A4/A8 mode. */ + __IOM uint32_t BLEND1_RX_R : 8; /*!< red color for A4/A8 mode. */ + uint32_t : 8; + } bit; + } BLEND_RGB; + + union { + __IOM uint32_t reg; /*!< Blending engine fix pixel register */ + + struct { + __IOM uint32_t BLEND_TX_FIX_PIXEL : 32; /*!< The configure fix pixel in fix pixel filling mode for blender + engine. */ + } bit; + } BLEND_FIX_PIXEL; + + union { + __IOM uint32_t reg; /*!< foreground color key lower threshold */ + + struct { + __IOM uint32_t COLORKEY_FG_B_LOW : 8; /*!< color key lower threshold of foreground b channel */ + __IOM uint32_t COLORKEY_FG_G_LOW : 8; /*!< color key lower threshold of foreground g channel */ + __IOM uint32_t COLORKEY_FG_R_LOW : 8; /*!< color key lower threshold of foreground r channel */ + uint32_t : 8; + } bit; + } CK_FG_LOW; + + union { + __IOM uint32_t reg; /*!< foreground color key higher threshold */ + + struct { + __IOM uint32_t COLORKEY_FG_B_HIGH : 8; /*!< color key higher threshold of foreground b channel */ + __IOM uint32_t COLORKEY_FG_G_HIGH : 8; /*!< color key higher threshold of foreground g channel */ + __IOM uint32_t COLORKEY_FG_R_HIGH : 8; /*!< color key higher threshold of foreground r channel */ + uint32_t : 8; + } bit; + } CK_FG_HIGH; + + union { + __IOM uint32_t reg; /*!< background color key lower threshold */ + + struct { + __IOM uint32_t COLORKEY_BG_B_LOW : 8; /*!< color key lower threshold of background b channel */ + __IOM uint32_t COLORKEY_BG_G_LOW : 8; /*!< color key lower threshold of background g channel */ + __IOM uint32_t COLORKEY_BG_R_LOW : 8; /*!< color key lower threshold of background r channel */ + uint32_t : 8; + } bit; + } CK_BG_LOW; + + union { + __IOM uint32_t reg; /*!< background color key higher threshold */ + + struct { + __IOM uint32_t COLORKEY_BG_B_HIGH : 8; /*!< color key higher threshold of background b channel */ + __IOM uint32_t COLORKEY_BG_G_HIGH : 8; /*!< color key higher threshold of background g channel */ + __IOM uint32_t COLORKEY_BG_R_HIGH : 8; /*!< color key higher threshold of background r channel */ + uint32_t : 8; + } bit; + } CK_BG_HIGH; + + union { + __IOM uint32_t reg; /*!< default value when foreground and background both in color key + range */ + + struct { + __IOM uint32_t COLORKEY_DEFAULT_B : 8; /*!< default B channle value of color key */ + __IOM uint32_t COLORKEY_DEFAULT_G : 8; /*!< default G channle value of color key */ + __IOM uint32_t COLORKEY_DEFAULT_R : 8; /*!< default R channle value of color key */ + __IOM uint32_t COLORKEY_FG_BG_REVERSE : 1;/*!< when pixel in bg ck range but not in fg ck range, 0: the result + is bg, 1: the result is fg */ + uint32_t : 7; + } bit; + } CK_DEFAULT; + + union { + __IOM uint32_t reg; /*!< Scaling and rotating coefficient register */ + + struct { + __IOM uint32_t SR_SCAL_X_INT : 8; /*!< The integrated part of scaling coefficient in X direction. */ + __IOM uint32_t SR_SCAL_X_FRAG : 4; /*!< The fragment part of scaling coefficient in X direction. */ + __IOM uint32_t SR_SCAL_Y_INT : 8; /*!< The integrated part of scaling coefficient in Y direction. */ + __IOM uint32_t SR_SCAL_Y_FRAG : 4; /*!< The fragment part of scaling coefficient in Y direction. */ + __IOM uint32_t SR_ROTATE_ANGLE : 2; /*!< The rotate angle. 0: 0 degree. 1: 90 degree. 2: 180 degree. + 3: 270 degree. */ + __IOM uint32_t SCAL_ROTATE_RST : 1; /*!< Write 1 then write 0 to this bit to reset scaling and rotating + engine. */ + __OM uint32_t SCAL_ROTATE_START : 1; /*!< Write 1 to enable scaling and rotating engine after parameter + is configured. */ + __IOM uint32_t SR_MIRROR_X : 1; /*!< Image mirror in X direction. 0: disable, 1: enable */ + __IOM uint32_t SR_MIRROR_Y : 1; /*!< Image mirror in Y direction. 0: disable, 1: enable */ + uint32_t : 2; + } bit; + } SR_SCAL_ROTATE; + + union { + __IOM uint32_t reg; /*!< SR memory power done register */ + + struct { + __IOM uint32_t SR_MEM_CLK_ENA : 1; /*!< Set this bit to force clock enable of scaling and rotating engine's + data memory. */ + __IOM uint32_t SR_MEM_FORCE_PD : 1; /*!< Set this bit to force power down scaling and rotating engine's + data memory. */ + __IOM uint32_t SR_MEM_FORCE_PU : 1; /*!< Set this bit to force power up scaling and rotating engine's + data memory. */ + uint32_t : 29; + } bit; + } SR_MEM_PD; + + union { + __IOM uint32_t reg; /*!< Register clock enable register */ + + struct { + __IOM uint32_t CLK_EN : 1; /*!< PPA register clock gate enable signal. */ + uint32_t : 31; + } bit; + } REG_CONF; + + union { + __IOM uint32_t reg; /*!< BLEND CLUT write counter register */ + + struct { + __IM uint32_t BLEND0_CLUT_CNT : 9; /*!< The write data counter of BLEND0 CLUT in fifo mode. */ + __IM uint32_t BLEND1_CLUT_CNT : 9; /*!< The write data counter of BLEND1 CLUT in fifo mode. */ + uint32_t : 14; + } bit; + } CLUT_CNT; + + union { + __IOM uint32_t reg; /*!< Blending engine status register */ + + struct { + __IM uint32_t BLEND_SIZE_DIFF_ST : 1; /*!< 1: indicate the size of two image is different. */ + uint32_t : 31; + } bit; + } BLEND_ST; + + union { + __IOM uint32_t reg; /*!< Scaling and rotating coefficient error register */ + + struct { + __IM uint32_t TX_DSCR_VB_ERR_ST : 1; /*!< The error is that the scaled VB plus the offset of Y coordinate + in 2DDMA receive descriptor is larger than VA in 2DDMA + receive descriptor. */ + __IM uint32_t TX_DSCR_HB_ERR_ST : 1; /*!< The error is that the scaled HB plus the offset of X coordinate + in 2DDMA receive descriptor is larger than HA in 2DDMA + receive descriptor. */ + __IM uint32_t Y_RX_SCAL_EQUAL_0_ERR_ST : 1;/*!< The error is that the PPA_SR_SCAL_Y_INT and PPA_SR_CAL_Y_FRAG + both are 0. */ + __IM uint32_t RX_DSCR_VB_ERR_ST : 1; /*!< The error is that VB in 2DDMA receive descriptor plus the offset + of Y coordinate in 2DDMA transmit descriptor is larger + than VA in 2DDMA transmit descriptor */ + __IM uint32_t YDST_LEN_TOO_SAMLL_ERR_ST : 1;/*!< The error is that the scaled image width is 0. For example. + when source width is 14. scaled value is 1/16. and no rotate + operation. then scaled width would be 0 as the result would + be floored. */ + __IM uint32_t YDST_LEN_TOO_LARGE_ERR_ST : 1;/*!< The error is that the scaled width is larger than (2^13 - 1). */ + __IM uint32_t X_RX_SCAL_EQUAL_0_ERR_ST : 1;/*!< The error is that the scaled image height is 0. */ + __IM uint32_t RX_DSCR_HB_ERR_ST : 1; /*!< The error is that the HB in 2DDMA transmit descriptor plus the + offset of X coordinate in 2DDMA transmit descriptor is + larger than HA in 2DDMA transmit descriptor. */ + __IM uint32_t XDST_LEN_TOO_SAMLL_ERR_ST : 1;/*!< The error is that the scaled image height is 0. For example. + when source height is 14. scaled value is 1/16. and no + rotate operation. then scaled height would be 0 as the + result would be floored. */ + __IM uint32_t XDST_LEN_TOO_LARGE_ERR_ST : 1;/*!< The error is that the scaled image height is larger than (2^13 + - 1). */ + __IM uint32_t X_YUV420_RX_SCALE_ERR_ST : 1;/*!< The error is that the ha/hb/x param in dma2d descriptor is an + odd num when enable yuv420 rx */ + __IM uint32_t Y_YUV420_RX_SCALE_ERR_ST : 1;/*!< The error is that the va/vb/y param in dma2d descriptor is an + odd num when enable yuv420 rx */ + __IM uint32_t X_YUV420_TX_SCALE_ERR_ST : 1;/*!< The error is that the ha/hb/x param in dma2d descriptor is an + odd num when enable yuv420 tx */ + __IM uint32_t Y_YUV420_TX_SCALE_ERR_ST : 1;/*!< The error is that the va/vb/y param in dma2d descriptor is an + odd num when enable yuv420 tx */ + uint32_t : 18; + } bit; + } SR_PARAM_ERR_ST; + + union { + __IOM uint32_t reg; /*!< SR FSM register */ + + struct { + __IM uint32_t SR_RX_DSCR_SAMPLE_STATE : 2;/*!< Reserved. */ + __IM uint32_t SR_RX_SCAN_STATE : 2; /*!< Reserved. */ + __IM uint32_t SR_TX_DSCR_SAMPLE_STATE : 2;/*!< Reserved. */ + __IM uint32_t SR_TX_SCAN_STATE : 3; /*!< Reserved. */ + uint32_t : 23; + } bit; + } SR_STATUS; + + union { + __IOM uint32_t reg; /*!< Reserved. */ + + struct { + __IOM uint32_t RND_ECO_LOW : 32; /*!< Reserved. */ + } bit; + } ECO_LOW; + + union { + __IOM uint32_t reg; /*!< Reserved. */ + + struct { + __IOM uint32_t RND_ECO_HIGH : 32; /*!< Reserved. */ + } bit; + } ECO_HIGH; + + union { + __IOM uint32_t reg; /*!< Reserved. */ + + struct { + __IM uint32_t RDN_RESULT : 1; /*!< Reserved. */ + __IOM uint32_t RDN_ENA : 1; /*!< Reserved. */ + uint32_t : 30; + } bit; + } ECO_CELL_CTRL; + + union { + __IOM uint32_t reg; /*!< PPA SRAM Control Register */ + + struct { + __IOM uint32_t MEM_AUX_CTRL : 14; /*!< Control signals */ + uint32_t : 18; + } bit; + } SRAM_CTRL; + __IM uint32_t RESERVED3[28]; + + union { + __IOM uint32_t reg; /*!< PPA Version register */ + + struct { + __IOM uint32_t DATE : 32; /*!< register version. */ + } bit; + } DATE; +} PPA_Type; /*!< Size = 260 (0x104) */ + + + +/* =========================================================================================================================== */ +/* ================ PVT ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief PVT Peripheral (PVT) + */ + +typedef struct { /*!< PVT Structure */ + + union { + __IOM uint32_t reg; /*!< select valid pvt channel */ + + struct { + __IOM uint32_t PUMP_BITMAP_HIGH0 : 32; /*!< select valid high channel0 */ + } bit; + } PMUP_BITMAP_HIGH0; + + union { + __IOM uint32_t reg; /*!< select valid pvt channel */ + + struct { + __IOM uint32_t PUMP_BITMAP_HIGH1 : 32; /*!< select valid high channel1 */ + } bit; + } PMUP_BITMAP_HIGH1; + + union { + __IOM uint32_t reg; /*!< select valid pvt channel */ + + struct { + __IOM uint32_t PUMP_BITMAP_HIGH2 : 32; /*!< select valid high channel2 */ + } bit; + } PMUP_BITMAP_HIGH2; + + union { + __IOM uint32_t reg; /*!< select valid pvt channel */ + + struct { + __IOM uint32_t PUMP_BITMAP_HIGH3 : 32; /*!< select valid high channel3 */ + } bit; + } PMUP_BITMAP_HIGH3; + + union { + __IOM uint32_t reg; /*!< select valid pvt channel */ + + struct { + __IOM uint32_t PUMP_BITMAP_HIGH4 : 32; /*!< select valid high channel4 */ + } bit; + } PMUP_BITMAP_HIGH4; + + union { + __IOM uint32_t reg; /*!< select valid pvt channel */ + + struct { + __IOM uint32_t PUMP_BITMAP_LOW0 : 32; /*!< select valid low channel0 */ + } bit; + } PMUP_BITMAP_LOW0; + + union { + __IOM uint32_t reg; /*!< select valid pvt channel */ + + struct { + __IOM uint32_t PUMP_BITMAP_LOW1 : 32; /*!< select valid low channel1 */ + } bit; + } PMUP_BITMAP_LOW1; + + union { + __IOM uint32_t reg; /*!< select valid pvt channel */ + + struct { + __IOM uint32_t PUMP_BITMAP_LOW2 : 32; /*!< select valid low channel2 */ + } bit; + } PMUP_BITMAP_LOW2; + + union { + __IOM uint32_t reg; /*!< select valid pvt channel */ + + struct { + __IOM uint32_t PUMP_BITMAP_LOW3 : 32; /*!< select valid low channel3 */ + } bit; + } PMUP_BITMAP_LOW3; + + union { + __IOM uint32_t reg; /*!< select valid pvt channel */ + + struct { + __IOM uint32_t PUMP_BITMAP_LOW4 : 32; /*!< select valid low channel4 */ + } bit; + } PMUP_BITMAP_LOW4; + + union { + __IOM uint32_t reg; /*!< configure pump drv */ + + struct { + uint32_t : 9; + __IOM uint32_t PUMP_EN : 1; /*!< configure pvt charge xpd */ + __IOM uint32_t CLK_EN : 1; /*!< force register clken */ + __IOM uint32_t PUMP_DRV4 : 4; /*!< configure cmd4 drv */ + __IOM uint32_t PUMP_DRV3 : 4; /*!< configure cmd3 drv */ + __IOM uint32_t PUMP_DRV2 : 4; /*!< configure cmd2 drv */ + __IOM uint32_t PUMP_DRV1 : 4; /*!< configure cmd1 drv */ + __IOM uint32_t PUMP_DRV0 : 4; /*!< configure cmd0 drv */ + uint32_t : 1; + } bit; + } PMUP_DRV_CFG; + + union { + __IOM uint32_t reg; /*!< configure the code of valid pump channel code */ + + struct { + uint32_t : 7; + __IOM uint32_t PUMP_CHANNEL_CODE4 : 5; /*!< configure cmd4 code */ + __IOM uint32_t PUMP_CHANNEL_CODE3 : 5; /*!< configure cmd3 code */ + __IOM uint32_t PUMP_CHANNEL_CODE2 : 5; /*!< configure cmd2 code */ + __IOM uint32_t PUMP_CHANNEL_CODE1 : 5; /*!< configure cmd1 code */ + __IOM uint32_t PUMP_CHANNEL_CODE0 : 5; /*!< configure cmd0 code */ + } bit; + } PMUP_CHANNEL_CFG; + + union { + __IOM uint32_t reg; /*!< configure pvt clk */ + + struct { + __IOM uint32_t PUMP_CLK_DIV_NUM : 8; /*!< needs field desc */ + __IOM uint32_t MONITOR_CLK_PVT_EN : 1; /*!< needs field desc */ + uint32_t : 22; + __IOM uint32_t CLK_SEL : 1; /*!< select pvt clk */ + } bit; + } CLK_CFG; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + uint32_t : 4; + __IOM uint32_t DBIAS_CHANNEL3_SEL : 7; /*!< needs field desc */ + __IOM uint32_t DBIAS_CHANNEL2_SEL : 7; /*!< needs field desc */ + __IOM uint32_t DBIAS_CHANNEL1_SEL : 7; /*!< needs field desc */ + __IOM uint32_t DBIAS_CHANNEL0_SEL : 7; /*!< needs field desc */ + } bit; + } DBIAS_CHANNEL_SEL0; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + uint32_t : 25; + __IOM uint32_t DBIAS_CHANNEL4_SEL : 7; /*!< needs field desc */ + } bit; + } DBIAS_CHANNEL_SEL1; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t DBIAS_CHANNEL0_CFG : 17; /*!< needs field desc */ + uint32_t : 15; + } bit; + } DBIAS_CHANNEL0_SEL; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t DBIAS_CHANNEL1_CFG : 17; /*!< needs field desc */ + uint32_t : 15; + } bit; + } DBIAS_CHANNEL1_SEL; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t DBIAS_CHANNEL2_CFG : 17; /*!< needs field desc */ + uint32_t : 15; + } bit; + } DBIAS_CHANNEL2_SEL; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t DBIAS_CHANNEL3_CFG : 17; /*!< needs field desc */ + uint32_t : 15; + } bit; + } DBIAS_CHANNEL3_SEL; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t DBIAS_CHANNEL4_CFG : 17; /*!< needs field desc */ + uint32_t : 15; + } bit; + } DBIAS_CHANNEL4_SEL; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t DBIAS_CMD0 : 17; /*!< needs field desc */ + uint32_t : 15; + } bit; + } DBIAS_CMD0; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t DBIAS_CMD1 : 17; /*!< needs field desc */ + uint32_t : 15; + } bit; + } DBIAS_CMD1; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t DBIAS_CMD2 : 17; /*!< needs field desc */ + uint32_t : 15; + } bit; + } DBIAS_CMD2; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t DBIAS_CMD3 : 17; /*!< needs field desc */ + uint32_t : 15; + } bit; + } DBIAS_CMD3; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t DBIAS_CMD4 : 17; /*!< needs field desc */ + uint32_t : 15; + } bit; + } DBIAS_CMD4; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + uint32_t : 15; + __IOM uint32_t TIMER_TARGET : 16; /*!< needs field desc */ + __IOM uint32_t TIMER_EN : 1; /*!< needs field desc */ + } bit; + } DBIAS_TIMER; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EN_VT0_PD_SITE0_UNIT0 : 1;/*!< needs field desc */ + __OM uint32_t TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT0 : 1;/*!< needs field desc */ + __IOM uint32_t DELAY_LIMIT_VT0_PD_SITE0_UNIT0 : 8;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_NUM_O_VT0_PD_SITE0_UNIT0 : 8;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_VT0_PD_SITE0_UNIT0 : 1;/*!< needs field desc */ + } bit; + } COMB_PD_SITE0_UNIT0_VT0_CONF1; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EN_VT0_PD_SITE0_UNIT1 : 1;/*!< needs field desc */ + __OM uint32_t TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT1 : 1;/*!< needs field desc */ + __IOM uint32_t DELAY_LIMIT_VT0_PD_SITE0_UNIT1 : 8;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_NUM_O_VT0_PD_SITE0_UNIT1 : 8;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_VT0_PD_SITE0_UNIT1 : 1;/*!< needs field desc */ + } bit; + } COMB_PD_SITE0_UNIT1_VT0_CONF1; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EN_VT0_PD_SITE0_UNIT2 : 1;/*!< needs field desc */ + __OM uint32_t TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT2 : 1;/*!< needs field desc */ + __IOM uint32_t DELAY_LIMIT_VT0_PD_SITE0_UNIT2 : 8;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_NUM_O_VT0_PD_SITE0_UNIT2 : 8;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_VT0_PD_SITE0_UNIT2 : 1;/*!< needs field desc */ + } bit; + } COMB_PD_SITE0_UNIT2_VT0_CONF1; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EN_VT0_PD_SITE0_UNIT3 : 1;/*!< needs field desc */ + __OM uint32_t TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT3 : 1;/*!< needs field desc */ + __IOM uint32_t DELAY_LIMIT_VT0_PD_SITE0_UNIT3 : 8;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_NUM_O_VT0_PD_SITE0_UNIT3 : 8;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_VT0_PD_SITE0_UNIT3 : 1;/*!< needs field desc */ + } bit; + } COMB_PD_SITE0_UNIT3_VT0_CONF1; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EN_VT1_PD_SITE0_UNIT0 : 1;/*!< needs field desc */ + __OM uint32_t TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT0 : 1;/*!< needs field desc */ + __IOM uint32_t DELAY_LIMIT_VT1_PD_SITE0_UNIT0 : 8;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_NUM_O_VT1_PD_SITE0_UNIT0 : 8;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_VT1_PD_SITE0_UNIT0 : 1;/*!< needs field desc */ + } bit; + } COMB_PD_SITE0_UNIT0_VT1_CONF1; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EN_VT1_PD_SITE0_UNIT1 : 1;/*!< needs field desc */ + __OM uint32_t TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT1 : 1;/*!< needs field desc */ + __IOM uint32_t DELAY_LIMIT_VT1_PD_SITE0_UNIT1 : 8;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_NUM_O_VT1_PD_SITE0_UNIT1 : 8;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_VT1_PD_SITE0_UNIT1 : 1;/*!< needs field desc */ + } bit; + } COMB_PD_SITE0_UNIT1_VT1_CONF1; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EN_VT1_PD_SITE0_UNIT2 : 1;/*!< needs field desc */ + __OM uint32_t TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT2 : 1;/*!< needs field desc */ + __IOM uint32_t DELAY_LIMIT_VT1_PD_SITE0_UNIT2 : 8;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_NUM_O_VT1_PD_SITE0_UNIT2 : 8;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_VT1_PD_SITE0_UNIT2 : 1;/*!< needs field desc */ + } bit; + } COMB_PD_SITE0_UNIT2_VT1_CONF1; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EN_VT1_PD_SITE0_UNIT3 : 1;/*!< needs field desc */ + __OM uint32_t TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT3 : 1;/*!< needs field desc */ + __IOM uint32_t DELAY_LIMIT_VT1_PD_SITE0_UNIT3 : 8;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_NUM_O_VT1_PD_SITE0_UNIT3 : 8;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_VT1_PD_SITE0_UNIT3 : 1;/*!< needs field desc */ + } bit; + } COMB_PD_SITE0_UNIT3_VT1_CONF1; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EN_VT2_PD_SITE0_UNIT0 : 1;/*!< needs field desc */ + __OM uint32_t TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT0 : 1;/*!< needs field desc */ + __IOM uint32_t DELAY_LIMIT_VT2_PD_SITE0_UNIT0 : 8;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_NUM_O_VT2_PD_SITE0_UNIT0 : 8;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_VT2_PD_SITE0_UNIT0 : 1;/*!< needs field desc */ + } bit; + } COMB_PD_SITE0_UNIT0_VT2_CONF1; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EN_VT2_PD_SITE0_UNIT1 : 1;/*!< needs field desc */ + __OM uint32_t TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT1 : 1;/*!< needs field desc */ + __IOM uint32_t DELAY_LIMIT_VT2_PD_SITE0_UNIT1 : 8;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_NUM_O_VT2_PD_SITE0_UNIT1 : 8;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_VT2_PD_SITE0_UNIT1 : 1;/*!< needs field desc */ + } bit; + } COMB_PD_SITE0_UNIT1_VT2_CONF1; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EN_VT2_PD_SITE0_UNIT2 : 1;/*!< needs field desc */ + __OM uint32_t TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT2 : 1;/*!< needs field desc */ + __IOM uint32_t DELAY_LIMIT_VT2_PD_SITE0_UNIT2 : 8;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_NUM_O_VT2_PD_SITE0_UNIT2 : 8;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_VT2_PD_SITE0_UNIT2 : 1;/*!< needs field desc */ + } bit; + } COMB_PD_SITE0_UNIT2_VT2_CONF1; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EN_VT2_PD_SITE0_UNIT3 : 1;/*!< needs field desc */ + __OM uint32_t TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT3 : 1;/*!< needs field desc */ + __IOM uint32_t DELAY_LIMIT_VT2_PD_SITE0_UNIT3 : 8;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_NUM_O_VT2_PD_SITE0_UNIT3 : 8;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_VT2_PD_SITE0_UNIT3 : 1;/*!< needs field desc */ + } bit; + } COMB_PD_SITE0_UNIT3_VT2_CONF1; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EN_VT0_PD_SITE1_UNIT0 : 1;/*!< needs field desc */ + __OM uint32_t TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT0 : 1;/*!< needs field desc */ + __IOM uint32_t DELAY_LIMIT_VT0_PD_SITE1_UNIT0 : 8;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_NUM_O_VT0_PD_SITE1_UNIT0 : 8;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_VT0_PD_SITE1_UNIT0 : 1;/*!< needs field desc */ + } bit; + } COMB_PD_SITE1_UNIT0_VT0_CONF1; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EN_VT0_PD_SITE1_UNIT1 : 1;/*!< needs field desc */ + __OM uint32_t TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT1 : 1;/*!< needs field desc */ + __IOM uint32_t DELAY_LIMIT_VT0_PD_SITE1_UNIT1 : 8;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_NUM_O_VT0_PD_SITE1_UNIT1 : 8;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_VT0_PD_SITE1_UNIT1 : 1;/*!< needs field desc */ + } bit; + } COMB_PD_SITE1_UNIT1_VT0_CONF1; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EN_VT0_PD_SITE1_UNIT2 : 1;/*!< needs field desc */ + __OM uint32_t TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT2 : 1;/*!< needs field desc */ + __IOM uint32_t DELAY_LIMIT_VT0_PD_SITE1_UNIT2 : 8;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_NUM_O_VT0_PD_SITE1_UNIT2 : 8;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_VT0_PD_SITE1_UNIT2 : 1;/*!< needs field desc */ + } bit; + } COMB_PD_SITE1_UNIT2_VT0_CONF1; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EN_VT0_PD_SITE1_UNIT3 : 1;/*!< needs field desc */ + __OM uint32_t TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT3 : 1;/*!< needs field desc */ + __IOM uint32_t DELAY_LIMIT_VT0_PD_SITE1_UNIT3 : 8;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_NUM_O_VT0_PD_SITE1_UNIT3 : 8;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_VT0_PD_SITE1_UNIT3 : 1;/*!< needs field desc */ + } bit; + } COMB_PD_SITE1_UNIT3_VT0_CONF1; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EN_VT1_PD_SITE1_UNIT0 : 1;/*!< needs field desc */ + __OM uint32_t TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT0 : 1;/*!< needs field desc */ + __IOM uint32_t DELAY_LIMIT_VT1_PD_SITE1_UNIT0 : 8;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_NUM_O_VT1_PD_SITE1_UNIT0 : 8;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_VT1_PD_SITE1_UNIT0 : 1;/*!< needs field desc */ + } bit; + } COMB_PD_SITE1_UNIT0_VT1_CONF1; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EN_VT1_PD_SITE1_UNIT1 : 1;/*!< needs field desc */ + __OM uint32_t TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT1 : 1;/*!< needs field desc */ + __IOM uint32_t DELAY_LIMIT_VT1_PD_SITE1_UNIT1 : 8;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_NUM_O_VT1_PD_SITE1_UNIT1 : 8;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_VT1_PD_SITE1_UNIT1 : 1;/*!< needs field desc */ + } bit; + } COMB_PD_SITE1_UNIT1_VT1_CONF1; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EN_VT1_PD_SITE1_UNIT2 : 1;/*!< needs field desc */ + __OM uint32_t TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT2 : 1;/*!< needs field desc */ + __IOM uint32_t DELAY_LIMIT_VT1_PD_SITE1_UNIT2 : 8;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_NUM_O_VT1_PD_SITE1_UNIT2 : 8;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_VT1_PD_SITE1_UNIT2 : 1;/*!< needs field desc */ + } bit; + } COMB_PD_SITE1_UNIT2_VT1_CONF1; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EN_VT1_PD_SITE1_UNIT3 : 1;/*!< needs field desc */ + __OM uint32_t TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT3 : 1;/*!< needs field desc */ + __IOM uint32_t DELAY_LIMIT_VT1_PD_SITE1_UNIT3 : 8;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_NUM_O_VT1_PD_SITE1_UNIT3 : 8;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_VT1_PD_SITE1_UNIT3 : 1;/*!< needs field desc */ + } bit; + } COMB_PD_SITE1_UNIT3_VT1_CONF1; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EN_VT2_PD_SITE1_UNIT0 : 1;/*!< needs field desc */ + __OM uint32_t TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT0 : 1;/*!< needs field desc */ + __IOM uint32_t DELAY_LIMIT_VT2_PD_SITE1_UNIT0 : 8;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_NUM_O_VT2_PD_SITE1_UNIT0 : 8;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_VT2_PD_SITE1_UNIT0 : 1;/*!< needs field desc */ + } bit; + } COMB_PD_SITE1_UNIT0_VT2_CONF1; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EN_VT2_PD_SITE1_UNIT1 : 1;/*!< needs field desc */ + __OM uint32_t TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT1 : 1;/*!< needs field desc */ + __IOM uint32_t DELAY_LIMIT_VT2_PD_SITE1_UNIT1 : 8;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_NUM_O_VT2_PD_SITE1_UNIT1 : 8;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_VT2_PD_SITE1_UNIT1 : 1;/*!< needs field desc */ + } bit; + } COMB_PD_SITE1_UNIT1_VT2_CONF1; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EN_VT2_PD_SITE1_UNIT2 : 1;/*!< needs field desc */ + __OM uint32_t TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT2 : 1;/*!< needs field desc */ + __IOM uint32_t DELAY_LIMIT_VT2_PD_SITE1_UNIT2 : 8;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_NUM_O_VT2_PD_SITE1_UNIT2 : 8;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_VT2_PD_SITE1_UNIT2 : 1;/*!< needs field desc */ + } bit; + } COMB_PD_SITE1_UNIT2_VT2_CONF1; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EN_VT2_PD_SITE1_UNIT3 : 1;/*!< needs field desc */ + __OM uint32_t TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT3 : 1;/*!< needs field desc */ + __IOM uint32_t DELAY_LIMIT_VT2_PD_SITE1_UNIT3 : 8;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_NUM_O_VT2_PD_SITE1_UNIT3 : 8;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_VT2_PD_SITE1_UNIT3 : 1;/*!< needs field desc */ + } bit; + } COMB_PD_SITE1_UNIT3_VT2_CONF1; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EN_VT0_PD_SITE2_UNIT0 : 1;/*!< needs field desc */ + __OM uint32_t TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT0 : 1;/*!< needs field desc */ + __IOM uint32_t DELAY_LIMIT_VT0_PD_SITE2_UNIT0 : 8;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_NUM_O_VT0_PD_SITE2_UNIT0 : 8;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_VT0_PD_SITE2_UNIT0 : 1;/*!< needs field desc */ + } bit; + } COMB_PD_SITE2_UNIT0_VT0_CONF1; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EN_VT0_PD_SITE2_UNIT1 : 1;/*!< needs field desc */ + __OM uint32_t TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT1 : 1;/*!< needs field desc */ + __IOM uint32_t DELAY_LIMIT_VT0_PD_SITE2_UNIT1 : 8;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_NUM_O_VT0_PD_SITE2_UNIT1 : 8;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_VT0_PD_SITE2_UNIT1 : 1;/*!< needs field desc */ + } bit; + } COMB_PD_SITE2_UNIT1_VT0_CONF1; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EN_VT0_PD_SITE2_UNIT2 : 1;/*!< needs field desc */ + __OM uint32_t TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT2 : 1;/*!< needs field desc */ + __IOM uint32_t DELAY_LIMIT_VT0_PD_SITE2_UNIT2 : 8;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_NUM_O_VT0_PD_SITE2_UNIT2 : 8;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_VT0_PD_SITE2_UNIT2 : 1;/*!< needs field desc */ + } bit; + } COMB_PD_SITE2_UNIT2_VT0_CONF1; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EN_VT0_PD_SITE2_UNIT3 : 1;/*!< needs field desc */ + __OM uint32_t TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT3 : 1;/*!< needs field desc */ + __IOM uint32_t DELAY_LIMIT_VT0_PD_SITE2_UNIT3 : 8;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_NUM_O_VT0_PD_SITE2_UNIT3 : 8;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_VT0_PD_SITE2_UNIT3 : 1;/*!< needs field desc */ + } bit; + } COMB_PD_SITE2_UNIT3_VT0_CONF1; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EN_VT1_PD_SITE2_UNIT0 : 1;/*!< needs field desc */ + __OM uint32_t TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT0 : 1;/*!< needs field desc */ + __IOM uint32_t DELAY_LIMIT_VT1_PD_SITE2_UNIT0 : 8;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_NUM_O_VT1_PD_SITE2_UNIT0 : 8;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_VT1_PD_SITE2_UNIT0 : 1;/*!< needs field desc */ + } bit; + } COMB_PD_SITE2_UNIT0_VT1_CONF1; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EN_VT1_PD_SITE2_UNIT1 : 1;/*!< needs field desc */ + __OM uint32_t TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT1 : 1;/*!< needs field desc */ + __IOM uint32_t DELAY_LIMIT_VT1_PD_SITE2_UNIT1 : 8;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_NUM_O_VT1_PD_SITE2_UNIT1 : 8;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_VT1_PD_SITE2_UNIT1 : 1;/*!< needs field desc */ + } bit; + } COMB_PD_SITE2_UNIT1_VT1_CONF1; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EN_VT1_PD_SITE2_UNIT2 : 1;/*!< needs field desc */ + __OM uint32_t TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT2 : 1;/*!< needs field desc */ + __IOM uint32_t DELAY_LIMIT_VT1_PD_SITE2_UNIT2 : 8;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_NUM_O_VT1_PD_SITE2_UNIT2 : 8;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_VT1_PD_SITE2_UNIT2 : 1;/*!< needs field desc */ + } bit; + } COMB_PD_SITE2_UNIT2_VT1_CONF1; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EN_VT1_PD_SITE2_UNIT3 : 1;/*!< needs field desc */ + __OM uint32_t TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT3 : 1;/*!< needs field desc */ + __IOM uint32_t DELAY_LIMIT_VT1_PD_SITE2_UNIT3 : 8;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_NUM_O_VT1_PD_SITE2_UNIT3 : 8;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_VT1_PD_SITE2_UNIT3 : 1;/*!< needs field desc */ + } bit; + } COMB_PD_SITE2_UNIT3_VT1_CONF1; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EN_VT2_PD_SITE2_UNIT0 : 1;/*!< needs field desc */ + __OM uint32_t TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT0 : 1;/*!< needs field desc */ + __IOM uint32_t DELAY_LIMIT_VT2_PD_SITE2_UNIT0 : 8;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_NUM_O_VT2_PD_SITE2_UNIT0 : 8;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_VT2_PD_SITE2_UNIT0 : 1;/*!< needs field desc */ + } bit; + } COMB_PD_SITE2_UNIT0_VT2_CONF1; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EN_VT2_PD_SITE2_UNIT1 : 1;/*!< needs field desc */ + __OM uint32_t TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT1 : 1;/*!< needs field desc */ + __IOM uint32_t DELAY_LIMIT_VT2_PD_SITE2_UNIT1 : 8;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_NUM_O_VT2_PD_SITE2_UNIT1 : 8;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_VT2_PD_SITE2_UNIT1 : 1;/*!< needs field desc */ + } bit; + } COMB_PD_SITE2_UNIT1_VT2_CONF1; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EN_VT2_PD_SITE2_UNIT2 : 1;/*!< needs field desc */ + __OM uint32_t TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT2 : 1;/*!< needs field desc */ + __IOM uint32_t DELAY_LIMIT_VT2_PD_SITE2_UNIT2 : 8;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_NUM_O_VT2_PD_SITE2_UNIT2 : 8;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_VT2_PD_SITE2_UNIT2 : 1;/*!< needs field desc */ + } bit; + } COMB_PD_SITE2_UNIT2_VT2_CONF1; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EN_VT2_PD_SITE2_UNIT3 : 1;/*!< needs field desc */ + __OM uint32_t TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT3 : 1;/*!< needs field desc */ + __IOM uint32_t DELAY_LIMIT_VT2_PD_SITE2_UNIT3 : 8;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_NUM_O_VT2_PD_SITE2_UNIT3 : 8;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_VT2_PD_SITE2_UNIT3 : 1;/*!< needs field desc */ + } bit; + } COMB_PD_SITE2_UNIT3_VT2_CONF1; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EN_VT0_PD_SITE3_UNIT0 : 1;/*!< needs field desc */ + __OM uint32_t TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT0 : 1;/*!< needs field desc */ + __IOM uint32_t DELAY_LIMIT_VT0_PD_SITE3_UNIT0 : 8;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_NUM_O_VT0_PD_SITE3_UNIT0 : 8;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_VT0_PD_SITE3_UNIT0 : 1;/*!< needs field desc */ + } bit; + } COMB_PD_SITE3_UNIT0_VT0_CONF1; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EN_VT0_PD_SITE3_UNIT1 : 1;/*!< needs field desc */ + __OM uint32_t TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT1 : 1;/*!< needs field desc */ + __IOM uint32_t DELAY_LIMIT_VT0_PD_SITE3_UNIT1 : 8;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_NUM_O_VT0_PD_SITE3_UNIT1 : 8;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_VT0_PD_SITE3_UNIT1 : 1;/*!< needs field desc */ + } bit; + } COMB_PD_SITE3_UNIT1_VT0_CONF1; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EN_VT0_PD_SITE3_UNIT2 : 1;/*!< needs field desc */ + __OM uint32_t TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT2 : 1;/*!< needs field desc */ + __IOM uint32_t DELAY_LIMIT_VT0_PD_SITE3_UNIT2 : 8;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_NUM_O_VT0_PD_SITE3_UNIT2 : 8;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_VT0_PD_SITE3_UNIT2 : 1;/*!< needs field desc */ + } bit; + } COMB_PD_SITE3_UNIT2_VT0_CONF1; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EN_VT0_PD_SITE3_UNIT3 : 1;/*!< needs field desc */ + __OM uint32_t TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT3 : 1;/*!< needs field desc */ + __IOM uint32_t DELAY_LIMIT_VT0_PD_SITE3_UNIT3 : 8;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_NUM_O_VT0_PD_SITE3_UNIT3 : 8;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_VT0_PD_SITE3_UNIT3 : 1;/*!< needs field desc */ + } bit; + } COMB_PD_SITE3_UNIT3_VT0_CONF1; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EN_VT1_PD_SITE3_UNIT0 : 1;/*!< needs field desc */ + __OM uint32_t TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT0 : 1;/*!< needs field desc */ + __IOM uint32_t DELAY_LIMIT_VT1_PD_SITE3_UNIT0 : 8;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_NUM_O_VT1_PD_SITE3_UNIT0 : 8;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_VT1_PD_SITE3_UNIT0 : 1;/*!< needs field desc */ + } bit; + } COMB_PD_SITE3_UNIT0_VT1_CONF1; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EN_VT1_PD_SITE3_UNIT1 : 1;/*!< needs field desc */ + __OM uint32_t TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT1 : 1;/*!< needs field desc */ + __IOM uint32_t DELAY_LIMIT_VT1_PD_SITE3_UNIT1 : 8;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_NUM_O_VT1_PD_SITE3_UNIT1 : 8;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_VT1_PD_SITE3_UNIT1 : 1;/*!< needs field desc */ + } bit; + } COMB_PD_SITE3_UNIT1_VT1_CONF1; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EN_VT1_PD_SITE3_UNIT2 : 1;/*!< needs field desc */ + __OM uint32_t TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT2 : 1;/*!< needs field desc */ + __IOM uint32_t DELAY_LIMIT_VT1_PD_SITE3_UNIT2 : 8;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_NUM_O_VT1_PD_SITE3_UNIT2 : 8;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_VT1_PD_SITE3_UNIT2 : 1;/*!< needs field desc */ + } bit; + } COMB_PD_SITE3_UNIT2_VT1_CONF1; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EN_VT1_PD_SITE3_UNIT3 : 1;/*!< needs field desc */ + __OM uint32_t TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT3 : 1;/*!< needs field desc */ + __IOM uint32_t DELAY_LIMIT_VT1_PD_SITE3_UNIT3 : 8;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_NUM_O_VT1_PD_SITE3_UNIT3 : 8;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_VT1_PD_SITE3_UNIT3 : 1;/*!< needs field desc */ + } bit; + } COMB_PD_SITE3_UNIT3_VT1_CONF1; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EN_VT2_PD_SITE3_UNIT0 : 1;/*!< needs field desc */ + __OM uint32_t TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT0 : 1;/*!< needs field desc */ + __IOM uint32_t DELAY_LIMIT_VT2_PD_SITE3_UNIT0 : 8;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_NUM_O_VT2_PD_SITE3_UNIT0 : 8;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_VT2_PD_SITE3_UNIT0 : 1;/*!< needs field desc */ + } bit; + } COMB_PD_SITE3_UNIT0_VT2_CONF1; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EN_VT2_PD_SITE3_UNIT1 : 1;/*!< needs field desc */ + __OM uint32_t TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT1 : 1;/*!< needs field desc */ + __IOM uint32_t DELAY_LIMIT_VT2_PD_SITE3_UNIT1 : 8;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_NUM_O_VT2_PD_SITE3_UNIT1 : 8;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_VT2_PD_SITE3_UNIT1 : 1;/*!< needs field desc */ + } bit; + } COMB_PD_SITE3_UNIT1_VT2_CONF1; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EN_VT2_PD_SITE3_UNIT2 : 1;/*!< needs field desc */ + __OM uint32_t TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT2 : 1;/*!< needs field desc */ + __IOM uint32_t DELAY_LIMIT_VT2_PD_SITE3_UNIT2 : 8;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_NUM_O_VT2_PD_SITE3_UNIT2 : 8;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_VT2_PD_SITE3_UNIT2 : 1;/*!< needs field desc */ + } bit; + } COMB_PD_SITE3_UNIT2_VT2_CONF1; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EN_VT2_PD_SITE3_UNIT3 : 1;/*!< needs field desc */ + __OM uint32_t TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT3 : 1;/*!< needs field desc */ + __IOM uint32_t DELAY_LIMIT_VT2_PD_SITE3_UNIT3 : 8;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_NUM_O_VT2_PD_SITE3_UNIT3 : 8;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_VT2_PD_SITE3_UNIT3 : 1;/*!< needs field desc */ + } bit; + } COMB_PD_SITE3_UNIT3_VT2_CONF1; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT0 : 2;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_OVF_VT0_PD_SITE0_UNIT0 : 1;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT0 : 16;/*!< needs field desc */ + } bit; + } COMB_PD_SITE0_UNIT0_VT0_CONF2; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT1 : 2;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_OVF_VT0_PD_SITE0_UNIT1 : 1;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT1 : 16;/*!< needs field desc */ + } bit; + } COMB_PD_SITE0_UNIT1_VT0_CONF2; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT2 : 2;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_OVF_VT0_PD_SITE0_UNIT2 : 1;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT2 : 16;/*!< needs field desc */ + } bit; + } COMB_PD_SITE0_UNIT2_VT0_CONF2; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT3 : 2;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_OVF_VT0_PD_SITE0_UNIT3 : 1;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT3 : 16;/*!< needs field desc */ + } bit; + } COMB_PD_SITE0_UNIT3_VT0_CONF2; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT0 : 2;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_OVF_VT1_PD_SITE0_UNIT0 : 1;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT0 : 16;/*!< needs field desc */ + } bit; + } COMB_PD_SITE0_UNIT0_VT1_CONF2; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT1 : 2;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_OVF_VT1_PD_SITE0_UNIT1 : 1;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT1 : 16;/*!< needs field desc */ + } bit; + } COMB_PD_SITE0_UNIT1_VT1_CONF2; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT2 : 2;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_OVF_VT1_PD_SITE0_UNIT2 : 1;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT2 : 16;/*!< needs field desc */ + } bit; + } COMB_PD_SITE0_UNIT2_VT1_CONF2; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT3 : 2;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_OVF_VT1_PD_SITE0_UNIT3 : 1;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT3 : 16;/*!< needs field desc */ + } bit; + } COMB_PD_SITE0_UNIT3_VT1_CONF2; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT0 : 2;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_OVF_VT2_PD_SITE0_UNIT0 : 1;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT0 : 16;/*!< needs field desc */ + } bit; + } COMB_PD_SITE0_UNIT0_VT2_CONF2; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT1 : 2;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_OVF_VT2_PD_SITE0_UNIT1 : 1;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT1 : 16;/*!< needs field desc */ + } bit; + } COMB_PD_SITE0_UNIT1_VT2_CONF2; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT2 : 2;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_OVF_VT2_PD_SITE0_UNIT2 : 1;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT2 : 16;/*!< needs field desc */ + } bit; + } COMB_PD_SITE0_UNIT2_VT2_CONF2; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT3 : 2;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_OVF_VT2_PD_SITE0_UNIT3 : 1;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT3 : 16;/*!< needs field desc */ + } bit; + } COMB_PD_SITE0_UNIT3_VT2_CONF2; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT0 : 2;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_OVF_VT0_PD_SITE1_UNIT0 : 1;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT0 : 16;/*!< needs field desc */ + } bit; + } COMB_PD_SITE1_UNIT0_VT0_CONF2; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT1 : 2;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_OVF_VT0_PD_SITE1_UNIT1 : 1;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT1 : 16;/*!< needs field desc */ + } bit; + } COMB_PD_SITE1_UNIT1_VT0_CONF2; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT2 : 2;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_OVF_VT0_PD_SITE1_UNIT2 : 1;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT2 : 16;/*!< needs field desc */ + } bit; + } COMB_PD_SITE1_UNIT2_VT0_CONF2; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT3 : 2;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_OVF_VT0_PD_SITE1_UNIT3 : 1;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT3 : 16;/*!< needs field desc */ + } bit; + } COMB_PD_SITE1_UNIT3_VT0_CONF2; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT0 : 2;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_OVF_VT1_PD_SITE1_UNIT0 : 1;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT0 : 16;/*!< needs field desc */ + } bit; + } COMB_PD_SITE1_UNIT0_VT1_CONF2; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT1 : 2;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_OVF_VT1_PD_SITE1_UNIT1 : 1;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT1 : 16;/*!< needs field desc */ + } bit; + } COMB_PD_SITE1_UNIT1_VT1_CONF2; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT2 : 2;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_OVF_VT1_PD_SITE1_UNIT2 : 1;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT2 : 16;/*!< needs field desc */ + } bit; + } COMB_PD_SITE1_UNIT2_VT1_CONF2; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT3 : 2;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_OVF_VT1_PD_SITE1_UNIT3 : 1;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT3 : 16;/*!< needs field desc */ + } bit; + } COMB_PD_SITE1_UNIT3_VT1_CONF2; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT0 : 2;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_OVF_VT2_PD_SITE1_UNIT0 : 1;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT0 : 16;/*!< needs field desc */ + } bit; + } COMB_PD_SITE1_UNIT0_VT2_CONF2; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT1 : 2;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_OVF_VT2_PD_SITE1_UNIT1 : 1;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT1 : 16;/*!< needs field desc */ + } bit; + } COMB_PD_SITE1_UNIT1_VT2_CONF2; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT2 : 2;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_OVF_VT2_PD_SITE1_UNIT2 : 1;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT2 : 16;/*!< needs field desc */ + } bit; + } COMB_PD_SITE1_UNIT2_VT2_CONF2; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT3 : 2;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_OVF_VT2_PD_SITE1_UNIT3 : 1;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT3 : 16;/*!< needs field desc */ + } bit; + } COMB_PD_SITE1_UNIT3_VT2_CONF2; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT0 : 2;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_OVF_VT0_PD_SITE2_UNIT0 : 1;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT0 : 16;/*!< needs field desc */ + } bit; + } COMB_PD_SITE2_UNIT0_VT0_CONF2; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT1 : 2;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_OVF_VT0_PD_SITE2_UNIT1 : 1;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT1 : 16;/*!< needs field desc */ + } bit; + } COMB_PD_SITE2_UNIT1_VT0_CONF2; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT2 : 2;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_OVF_VT0_PD_SITE2_UNIT2 : 1;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT2 : 16;/*!< needs field desc */ + } bit; + } COMB_PD_SITE2_UNIT2_VT0_CONF2; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT3 : 2;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_OVF_VT0_PD_SITE2_UNIT3 : 1;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT3 : 16;/*!< needs field desc */ + } bit; + } COMB_PD_SITE2_UNIT3_VT0_CONF2; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT0 : 2;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_OVF_VT1_PD_SITE2_UNIT0 : 1;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT0 : 16;/*!< needs field desc */ + } bit; + } COMB_PD_SITE2_UNIT0_VT1_CONF2; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT1 : 2;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_OVF_VT1_PD_SITE2_UNIT1 : 1;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT1 : 16;/*!< needs field desc */ + } bit; + } COMB_PD_SITE2_UNIT1_VT1_CONF2; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT2 : 2;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_OVF_VT1_PD_SITE2_UNIT2 : 1;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT2 : 16;/*!< needs field desc */ + } bit; + } COMB_PD_SITE2_UNIT2_VT1_CONF2; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT3 : 2;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_OVF_VT1_PD_SITE2_UNIT3 : 1;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT3 : 16;/*!< needs field desc */ + } bit; + } COMB_PD_SITE2_UNIT3_VT1_CONF2; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0 : 2;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_OVF_VT2_PD_SITE2_UNIT0 : 1;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT0 : 16;/*!< needs field desc */ + } bit; + } COMB_PD_SITE2_UNIT0_VT2_CONF2; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT1 : 2;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_OVF_VT2_PD_SITE2_UNIT1 : 1;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT1 : 16;/*!< needs field desc */ + } bit; + } COMB_PD_SITE2_UNIT1_VT2_CONF2; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT2 : 2;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_OVF_VT2_PD_SITE2_UNIT2 : 1;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT2 : 16;/*!< needs field desc */ + } bit; + } COMB_PD_SITE2_UNIT2_VT2_CONF2; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT3 : 2;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_OVF_VT2_PD_SITE2_UNIT3 : 1;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT3 : 16;/*!< needs field desc */ + } bit; + } COMB_PD_SITE2_UNIT3_VT2_CONF2; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT0 : 2;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_OVF_VT0_PD_SITE3_UNIT0 : 1;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT0 : 16;/*!< needs field desc */ + } bit; + } COMB_PD_SITE3_UNIT0_VT0_CONF2; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT1 : 2;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_OVF_VT0_PD_SITE3_UNIT1 : 1;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT1 : 16;/*!< needs field desc */ + } bit; + } COMB_PD_SITE3_UNIT1_VT0_CONF2; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT2 : 2;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_OVF_VT0_PD_SITE3_UNIT2 : 1;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT2 : 16;/*!< needs field desc */ + } bit; + } COMB_PD_SITE3_UNIT2_VT0_CONF2; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT3 : 2;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_OVF_VT0_PD_SITE3_UNIT3 : 1;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT3 : 16;/*!< needs field desc */ + } bit; + } COMB_PD_SITE3_UNIT3_VT0_CONF2; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT0 : 2;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_OVF_VT1_PD_SITE3_UNIT0 : 1;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT0 : 16;/*!< needs field desc */ + } bit; + } COMB_PD_SITE3_UNIT0_VT1_CONF2; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT1 : 2;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_OVF_VT1_PD_SITE3_UNIT1 : 1;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT1 : 16;/*!< needs field desc */ + } bit; + } COMB_PD_SITE3_UNIT1_VT1_CONF2; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT2 : 2;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_OVF_VT1_PD_SITE3_UNIT2 : 1;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT2 : 16;/*!< needs field desc */ + } bit; + } COMB_PD_SITE3_UNIT2_VT1_CONF2; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT3 : 2;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_OVF_VT1_PD_SITE3_UNIT3 : 1;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT3 : 16;/*!< needs field desc */ + } bit; + } COMB_PD_SITE3_UNIT3_VT1_CONF2; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT0 : 2;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_OVF_VT2_PD_SITE3_UNIT0 : 1;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT0 : 16;/*!< needs field desc */ + } bit; + } COMB_PD_SITE3_UNIT0_VT2_CONF2; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT1 : 2;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_OVF_VT2_PD_SITE3_UNIT1 : 1;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT1 : 16;/*!< needs field desc */ + } bit; + } COMB_PD_SITE3_UNIT1_VT2_CONF2; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT2 : 2;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_OVF_VT2_PD_SITE3_UNIT2 : 1;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT2 : 16;/*!< needs field desc */ + } bit; + } COMB_PD_SITE3_UNIT2_VT2_CONF2; + + union { + __IOM uint32_t reg; /*!< needs desc */ + + struct { + __IOM uint32_t MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT3 : 2;/*!< needs field desc */ + uint32_t : 13; + __IM uint32_t DELAY_OVF_VT2_PD_SITE3_UNIT3 : 1;/*!< needs field desc */ + __IM uint32_t TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT3 : 16;/*!< needs field desc */ + } bit; + } COMB_PD_SITE3_UNIT3_VT2_CONF2; + + union { + __IOM uint32_t reg; /*!< needs field desc */ + + struct { + __OM uint32_t VALUE_UPDATE : 1; /*!< needs field desc */ + __IOM uint32_t BYPASS : 1; /*!< needs field desc */ + uint32_t : 30; + } bit; + } VALUE_UPDATE; + __IM uint32_t RESERVED[900]; + + union { + __IOM uint32_t reg; /*!< version register */ + + struct { + __IOM uint32_t DATE : 32; /*!< version register */ + } bit; + } DATE; +} PVT_Type; /*!< Size = 4096 (0x1000) */ + + + +/* =========================================================================================================================== */ +/* ================ RMT ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Remote Control (RMT) + */ + +typedef struct { /*!< RMT Structure */ + __IOM uint32_t TX_CH0DATA; /*!< The read and write data register for CHANNEL0 by apb fifo access. */ + __IM uint32_t RESERVED[3]; + + union { + __IOM uint32_t TX_CH1DATA; /*!< The read and write data register for CHANNEL1 by apb fifo access. */ + + union { + __IOM uint32_t reg; /*!< The read and write data register for CHANNEL$n by apb fifo access. */ + + struct { + __IM uint32_t CHDATA : 32; /*!< Read and write data for channel 0 via APB FIFO. */ + } bit; + } RX_CH0DATA; + }; + __IM uint32_t RESERVED1[3]; + + union { + __IOM uint32_t TX_CH2DATA; /*!< The read and write data register for CHANNEL2 by apb fifo access. */ + + union { + __IOM uint32_t reg; /*!< The read and write data register for CHANNEL$n by apb fifo access. */ + + struct { + __IM uint32_t CHDATA : 32; /*!< Read and write data for channel 0 via APB FIFO. */ + } bit; + } RX_CH1DATA; + + union { + __IOM uint32_t reg; /*!< Channel 0 configure register 0 */ + + struct { + uint32_t : 23; + __OM uint32_t AFIFO_RST_CH0 : 1; /*!< Reserved */ + uint32_t : 8; + } bit; + } TX_CH0CONF0; + }; + __IM uint32_t RESERVED2[3]; + + union { + __IOM uint32_t TX_CH3DATA; /*!< The read and write data register for CHANNEL3 by apb fifo access. */ + + union { + __IOM uint32_t reg; /*!< The read and write data register for CHANNEL$n by apb fifo access. */ + + struct { + __IM uint32_t CHDATA : 32; /*!< Read and write data for channel 0 via APB FIFO. */ + } bit; + } RX_CH2DATA; + + union { + __IOM uint32_t reg; /*!< Channel 1 configure register 0 */ + + struct { + uint32_t : 23; + __OM uint32_t AFIFO_RST_CH0 : 1; /*!< Reserved */ + uint32_t : 8; + } bit; + } TX_CH1CONF0; + + union { + __IOM uint32_t reg; /*!< Channel 0 configure register 0 */ + + struct { + uint32_t : 8; + __IOM uint32_t IDLE_THRES_CH4 : 15; /*!< When no edge is detected on the input signal and continuous + clock cycles is longer than this register value, received + process is finished. */ + uint32_t : 9; + } bit; + } RX_CH0CONF0; + }; + + union { + __IOM uint32_t reg; /*!< Channel 0 configure register 1 */ + + struct { + uint32_t : 5; + __IOM uint32_t RX_FILTER_THRES_CH4 : 8; /*!< Ignores the input pulse when its width is smaller than this + register value in APB clock periods (in receive mode). */ + uint32_t : 1; + __OM uint32_t AFIFO_RST_CH4 : 1; /*!< Reserved */ + uint32_t : 17; + } bit; + } RX_CH0CONF1; + __IM uint32_t RESERVED3[2]; + + union { + union { + __IOM uint32_t reg; /*!< The read and write data register for CHANNEL$n by apb fifo access. */ + + struct { + __IM uint32_t CHDATA : 32; /*!< Read and write data for channel 0 via APB FIFO. */ + } bit; + } RX_CH3DATA; + + union { + __IOM uint32_t reg; /*!< Channel 2 configure register 0 */ + + struct { + uint32_t : 23; + __OM uint32_t AFIFO_RST_CH0 : 1; /*!< Reserved */ + uint32_t : 8; + } bit; + } TX_CH2CONF0; + }; + __IM uint32_t RESERVED4[3]; + + union { + union { + __IOM uint32_t reg; /*!< Channel 3 configure register 0 */ + + struct { + uint32_t : 23; + __OM uint32_t AFIFO_RST_CH0 : 1; /*!< Reserved */ + uint32_t : 8; + } bit; + } TX_CH3CONF0; + + union { + __IOM uint32_t reg; /*!< Channel 1 configure register 0 */ + + struct { + uint32_t : 8; + __IOM uint32_t IDLE_THRES_CH4 : 15; /*!< When no edge is detected on the input signal and continuous + clock cycles is longer than this register value, received + process is finished. */ + uint32_t : 9; + } bit; + } RX_CH1CONF0; + + union { + __IOM uint32_t reg; /*!< Channel 0 status register */ + + struct { + uint32_t : 11; + __IM uint32_t APB_MEM_WADDR_CH0 : 10; /*!< This register records the memory address offset when writes + RAM over APB bus. */ + uint32_t : 4; + __IM uint32_t MEM_EMPTY_CH0 : 1; /*!< This status bit will be set when the data to be set is more + than memory size and the wraparound mode is disabled. */ + __IM uint32_t APB_MEM_WR_ERR_CH0 : 1; /*!< This status bit will be set if the offset address out of memory + size when writes via APB bus. */ + uint32_t : 5; + } bit; + } TX_CH0STATUS; + }; + + union { + __IOM uint32_t reg; /*!< Channel 1 configure register 1 */ + + struct { + uint32_t : 5; + __IOM uint32_t RX_FILTER_THRES_CH4 : 8; /*!< Ignores the input pulse when its width is smaller than this + register value in APB clock periods (in receive mode). */ + uint32_t : 1; + __OM uint32_t AFIFO_RST_CH4 : 1; /*!< Reserved */ + uint32_t : 17; + } bit; + } RX_CH1CONF1; + __IM uint32_t RESERVED5[2]; + + union { + union { + __IOM uint32_t reg; /*!< Channel 1 status register */ + + struct { + uint32_t : 11; + __IM uint32_t APB_MEM_WADDR_CH0 : 10; /*!< This register records the memory address offset when writes + RAM over APB bus. */ + uint32_t : 4; + __IM uint32_t MEM_EMPTY_CH0 : 1; /*!< This status bit will be set when the data to be set is more + than memory size and the wraparound mode is disabled. */ + __IM uint32_t APB_MEM_WR_ERR_CH0 : 1; /*!< This status bit will be set if the offset address out of memory + size when writes via APB bus. */ + uint32_t : 5; + } bit; + } TX_CH1STATUS; + + union { + __IOM uint32_t reg; /*!< Channel 0 status register */ + + struct { + uint32_t : 11; + __IM uint32_t APB_MEM_RADDR_CH4 : 10; /*!< This register records the memory address offset when reads RAM + over APB bus. */ + uint32_t : 4; + __IM uint32_t MEM_OWNER_ERR_CH4 : 1; /*!< This status bit will be set when the ownership of memory block + is wrong. */ + __IM uint32_t MEM_FULL_CH4 : 1; /*!< This status bit will be set if the receiver receives more data + than the memory size. */ + __IM uint32_t APB_MEM_RD_ERR_CH4 : 1; /*!< This status bit will be set if the offset address out of memory + size when reads via APB bus. */ + uint32_t : 4; + } bit; + } RX_CH0STATUS; + }; + __IM uint32_t RESERVED6[3]; + + union { + union { + __IOM uint32_t reg; /*!< Channel 2 configure register 0 */ + + struct { + uint32_t : 8; + __IOM uint32_t IDLE_THRES_CH4 : 15; /*!< When no edge is detected on the input signal and continuous + clock cycles is longer than this register value, received + process is finished. */ + uint32_t : 9; + } bit; + } RX_CH2CONF0; + + union { + __IOM uint32_t reg; /*!< Channel 2 status register */ + + struct { + uint32_t : 11; + __IM uint32_t APB_MEM_WADDR_CH0 : 10; /*!< This register records the memory address offset when writes + RAM over APB bus. */ + uint32_t : 4; + __IM uint32_t MEM_EMPTY_CH0 : 1; /*!< This status bit will be set when the data to be set is more + than memory size and the wraparound mode is disabled. */ + __IM uint32_t APB_MEM_WR_ERR_CH0 : 1; /*!< This status bit will be set if the offset address out of memory + size when writes via APB bus. */ + uint32_t : 5; + } bit; + } TX_CH2STATUS; + + union { + __IOM uint32_t reg; /*!< Channel 1 status register */ + + struct { + uint32_t : 11; + __IM uint32_t APB_MEM_RADDR_CH4 : 10; /*!< This register records the memory address offset when reads RAM + over APB bus. */ + uint32_t : 4; + __IM uint32_t MEM_OWNER_ERR_CH4 : 1; /*!< This status bit will be set when the ownership of memory block + is wrong. */ + __IM uint32_t MEM_FULL_CH4 : 1; /*!< This status bit will be set if the receiver receives more data + than the memory size. */ + __IM uint32_t APB_MEM_RD_ERR_CH4 : 1; /*!< This status bit will be set if the offset address out of memory + size when reads via APB bus. */ + uint32_t : 4; + } bit; + } RX_CH1STATUS; + + union { + __IOM uint32_t reg; /*!< Raw interrupt status */ + + struct { + __IOM uint32_t CH0_TX_END_INT_RAW : 1; /*!< The interrupt raw bit for CHANNEL0. Triggered when transmission + done. */ + __IOM uint32_t CH1_TX_END_INT_RAW : 1; /*!< The interrupt raw bit for CHANNEL1. Triggered when transmission + done. */ + __IOM uint32_t CH2_TX_END_INT_RAW : 1; /*!< The interrupt raw bit for CHANNEL2. Triggered when transmission + done. */ + __IOM uint32_t CH3_TX_END_INT_RAW : 1; /*!< The interrupt raw bit for CHANNEL3. Triggered when transmission + done. */ + __IOM uint32_t TX_CH0_ERR_INT_RAW : 1; /*!< The interrupt raw bit for CHANNEL0. Triggered when error occurs. */ + __IOM uint32_t TX_CH1_ERR_INT_RAW : 1; /*!< The interrupt raw bit for CHANNEL1. Triggered when error occurs. */ + __IOM uint32_t TX_CH2_ERR_INT_RAW : 1; /*!< The interrupt raw bit for CHANNEL2. Triggered when error occurs. */ + __IOM uint32_t TX_CH3_ERR_INT_RAW : 1; /*!< The interrupt raw bit for CHANNEL3. Triggered when error occurs. */ + __IOM uint32_t CH0_TX_THR_EVENT_INT_RAW : 1;/*!< The interrupt raw bit for CHANNEL0. Triggered when transmitter + sent more data than configured value. */ + __IOM uint32_t CH1_TX_THR_EVENT_INT_RAW : 1;/*!< The interrupt raw bit for CHANNEL1. Triggered when transmitter + sent more data than configured value. */ + __IOM uint32_t CH2_TX_THR_EVENT_INT_RAW : 1;/*!< The interrupt raw bit for CHANNEL2. Triggered when transmitter + sent more data than configured value. */ + __IOM uint32_t CH3_TX_THR_EVENT_INT_RAW : 1;/*!< The interrupt raw bit for CHANNEL3. Triggered when transmitter + sent more data than configured value. */ + __IOM uint32_t CH0_TX_LOOP_INT_RAW : 1; /*!< The interrupt raw bit for CHANNEL0. Triggered when the loop + count reaches the configured threshold value. */ + __IOM uint32_t CH1_TX_LOOP_INT_RAW : 1; /*!< The interrupt raw bit for CHANNEL1. Triggered when the loop + count reaches the configured threshold value. */ + __IOM uint32_t CH2_TX_LOOP_INT_RAW : 1; /*!< The interrupt raw bit for CHANNEL2. Triggered when the loop + count reaches the configured threshold value. */ + __IOM uint32_t CH3_TX_LOOP_INT_RAW : 1; /*!< The interrupt raw bit for CHANNEL3. Triggered when the loop + count reaches the configured threshold value. */ + __IOM uint32_t CH4_RX_END_INT_RAW : 1; /*!< The interrupt raw bit for CHANNEL4. Triggered when reception + done. */ + __IOM uint32_t CH5_RX_END_INT_RAW : 1; /*!< The interrupt raw bit for CHANNEL5. Triggered when reception + done. */ + __IOM uint32_t CH6_RX_END_INT_RAW : 1; /*!< The interrupt raw bit for CHANNEL6. Triggered when reception + done. */ + __IOM uint32_t CH7_RX_END_INT_RAW : 1; /*!< The interrupt raw bit for CHANNEL7. Triggered when reception + done. */ + __IOM uint32_t RX_CH4_ERR_INT_RAW : 1; /*!< The interrupt raw bit for CHANNEL4. Triggered when error occurs. */ + __IOM uint32_t RX_CH5_ERR_INT_RAW : 1; /*!< The interrupt raw bit for CHANNEL5. Triggered when error occurs. */ + __IOM uint32_t RX_CH6_ERR_INT_RAW : 1; /*!< The interrupt raw bit for CHANNEL6. Triggered when error occurs. */ + __IOM uint32_t RX_CH7_ERR_INT_RAW : 1; /*!< The interrupt raw bit for CHANNEL7. Triggered when error occurs. */ + __IOM uint32_t CH4_RX_THR_EVENT_INT_RAW : 1;/*!< The interrupt raw bit for CHANNEL4. Triggered when receiver + receive more data than configured value. */ + __IOM uint32_t CH5_RX_THR_EVENT_INT_RAW : 1;/*!< The interrupt raw bit for CHANNEL5. Triggered when receiver + receive more data than configured value. */ + __IOM uint32_t CH6_RX_THR_EVENT_INT_RAW : 1;/*!< The interrupt raw bit for CHANNEL6. Triggered when receiver + receive more data than configured value. */ + __IOM uint32_t CH7_RX_THR_EVENT_INT_RAW : 1;/*!< The interrupt raw bit for CHANNEL7. Triggered when receiver + receive more data than configured value. */ + __IOM uint32_t TX_CH3_DMA_ACCESS_FAIL_INT_RAW : 1;/*!< The interrupt raw bit for CHANNEL3. Triggered when dma accessing + CHANNEL3 fails. */ + __IOM uint32_t RX_CH7_DMA_ACCESS_FAIL_INT_RAW : 1;/*!< The interrupt raw bit for CHANNEL7. Triggered when dma accessing + CHANNEL7 fails. */ + uint32_t : 2; + } bit; + } INT_RAW; + }; + + union { + union { + __IOM uint32_t reg; /*!< Channel 2 configure register 1 */ + + struct { + uint32_t : 5; + __IOM uint32_t RX_FILTER_THRES_CH4 : 8; /*!< Ignores the input pulse when its width is smaller than this + register value in APB clock periods (in receive mode). */ + uint32_t : 1; + __OM uint32_t AFIFO_RST_CH4 : 1; /*!< Reserved */ + uint32_t : 17; + } bit; + } RX_CH2CONF1; + + union { + __IOM uint32_t reg; /*!< Masked interrupt status */ + + struct { + __IM uint32_t CH0_TX_END_INT_ST : 1; /*!< The masked interrupt status bit for CH0_TX_END_INT. */ + __IM uint32_t CH1_TX_END_INT_ST : 1; /*!< The masked interrupt status bit for CH1_TX_END_INT. */ + __IM uint32_t CH2_TX_END_INT_ST : 1; /*!< The masked interrupt status bit for CH2_TX_END_INT. */ + __IM uint32_t CH3_TX_END_INT_ST : 1; /*!< The masked interrupt status bit for CH3_TX_END_INT. */ + __IM uint32_t TX_CH0_ERR_INT_ST : 1; /*!< The masked interrupt status bit for CH0_ERR_INT. */ + __IM uint32_t TX_CH1_ERR_INT_ST : 1; /*!< The masked interrupt status bit for CH1_ERR_INT. */ + __IM uint32_t TX_CH2_ERR_INT_ST : 1; /*!< The masked interrupt status bit for CH2_ERR_INT. */ + __IM uint32_t TX_CH3_ERR_INT_ST : 1; /*!< The masked interrupt status bit for CH3_ERR_INT. */ + __IM uint32_t CH0_TX_THR_EVENT_INT_ST : 1;/*!< The masked interrupt status bit for CH0_TX_THR_EVENT_INT. */ + __IM uint32_t CH1_TX_THR_EVENT_INT_ST : 1;/*!< The masked interrupt status bit for CH1_TX_THR_EVENT_INT. */ + __IM uint32_t CH2_TX_THR_EVENT_INT_ST : 1;/*!< The masked interrupt status bit for CH2_TX_THR_EVENT_INT. */ + __IM uint32_t CH3_TX_THR_EVENT_INT_ST : 1;/*!< The masked interrupt status bit for CH3_TX_THR_EVENT_INT. */ + __IM uint32_t CH0_TX_LOOP_INT_ST : 1; /*!< The masked interrupt status bit for CH0_TX_LOOP_INT. */ + __IM uint32_t CH1_TX_LOOP_INT_ST : 1; /*!< The masked interrupt status bit for CH1_TX_LOOP_INT. */ + __IM uint32_t CH2_TX_LOOP_INT_ST : 1; /*!< The masked interrupt status bit for CH2_TX_LOOP_INT. */ + __IM uint32_t CH3_TX_LOOP_INT_ST : 1; /*!< The masked interrupt status bit for CH3_TX_LOOP_INT. */ + __IM uint32_t CH4_RX_END_INT_ST : 1; /*!< The masked interrupt status bit for CH4_RX_END_INT. */ + __IM uint32_t CH5_RX_END_INT_ST : 1; /*!< The masked interrupt status bit for CH5_RX_END_INT. */ + __IM uint32_t CH6_RX_END_INT_ST : 1; /*!< The masked interrupt status bit for CH6_RX_END_INT. */ + __IM uint32_t CH7_RX_END_INT_ST : 1; /*!< The masked interrupt status bit for CH7_RX_END_INT. */ + __IM uint32_t RX_CH4_ERR_INT_ST : 1; /*!< The masked interrupt status bit for CH4_ERR_INT. */ + __IM uint32_t RX_CH5_ERR_INT_ST : 1; /*!< The masked interrupt status bit for CH5_ERR_INT. */ + __IM uint32_t RX_CH6_ERR_INT_ST : 1; /*!< The masked interrupt status bit for CH6_ERR_INT. */ + __IM uint32_t RX_CH7_ERR_INT_ST : 1; /*!< The masked interrupt status bit for CH7_ERR_INT. */ + __IM uint32_t CH4_RX_THR_EVENT_INT_ST : 1;/*!< The masked interrupt status bit for CH4_RX_THR_EVENT_INT. */ + __IM uint32_t CH5_RX_THR_EVENT_INT_ST : 1;/*!< The masked interrupt status bit for CH5_RX_THR_EVENT_INT. */ + __IM uint32_t CH6_RX_THR_EVENT_INT_ST : 1;/*!< The masked interrupt status bit for CH6_RX_THR_EVENT_INT. */ + __IM uint32_t CH7_RX_THR_EVENT_INT_ST : 1;/*!< The masked interrupt status bit for CH7_RX_THR_EVENT_INT. */ + __IM uint32_t TX_CH3_DMA_ACCESS_FAIL_INT_ST : 1;/*!< The masked interrupt status bit for CH3_DMA_ACCESS_FAIL_INT. */ + __IM uint32_t RX_CH7_DMA_ACCESS_FAIL_INT_ST : 1;/*!< The masked interrupt status bit for CH7_DMA_ACCESS_FAIL_INT. */ + uint32_t : 2; + } bit; + } INT_ST; + }; + + union { + __IOM uint32_t reg; /*!< Interrupt enable bits */ + + struct { + __IOM uint32_t CH0_TX_END_INT_ENA : 1; /*!< The interrupt enable bit for CH0_TX_END_INT. */ + __IOM uint32_t CH1_TX_END_INT_ENA : 1; /*!< The interrupt enable bit for CH1_TX_END_INT. */ + __IOM uint32_t CH2_TX_END_INT_ENA : 1; /*!< The interrupt enable bit for CH2_TX_END_INT. */ + __IOM uint32_t CH3_TX_END_INT_ENA : 1; /*!< The interrupt enable bit for CH3_TX_END_INT. */ + __IOM uint32_t TX_CH0_ERR_INT_ENA : 1; /*!< The interrupt enable bit for CH0_ERR_INT. */ + __IOM uint32_t TX_CH1_ERR_INT_ENA : 1; /*!< The interrupt enable bit for CH1_ERR_INT. */ + __IOM uint32_t TX_CH2_ERR_INT_ENA : 1; /*!< The interrupt enable bit for CH2_ERR_INT. */ + __IOM uint32_t TX_CH3_ERR_INT_ENA : 1; /*!< The interrupt enable bit for CH3_ERR_INT. */ + __IOM uint32_t CH0_TX_THR_EVENT_INT_ENA : 1;/*!< The interrupt enable bit for CH0_TX_THR_EVENT_INT. */ + __IOM uint32_t CH1_TX_THR_EVENT_INT_ENA : 1;/*!< The interrupt enable bit for CH1_TX_THR_EVENT_INT. */ + __IOM uint32_t CH2_TX_THR_EVENT_INT_ENA : 1;/*!< The interrupt enable bit for CH2_TX_THR_EVENT_INT. */ + __IOM uint32_t CH3_TX_THR_EVENT_INT_ENA : 1;/*!< The interrupt enable bit for CH3_TX_THR_EVENT_INT. */ + __IOM uint32_t CH0_TX_LOOP_INT_ENA : 1; /*!< The interrupt enable bit for CH0_TX_LOOP_INT. */ + __IOM uint32_t CH1_TX_LOOP_INT_ENA : 1; /*!< The interrupt enable bit for CH1_TX_LOOP_INT. */ + __IOM uint32_t CH2_TX_LOOP_INT_ENA : 1; /*!< The interrupt enable bit for CH2_TX_LOOP_INT. */ + __IOM uint32_t CH3_TX_LOOP_INT_ENA : 1; /*!< The interrupt enable bit for CH3_TX_LOOP_INT. */ + __IOM uint32_t CH4_RX_END_INT_ENA : 1; /*!< The interrupt enable bit for CH4_RX_END_INT. */ + __IOM uint32_t CH5_RX_END_INT_ENA : 1; /*!< The interrupt enable bit for CH5_RX_END_INT. */ + __IOM uint32_t CH6_RX_END_INT_ENA : 1; /*!< The interrupt enable bit for CH6_RX_END_INT. */ + __IOM uint32_t CH7_RX_END_INT_ENA : 1; /*!< The interrupt enable bit for CH7_RX_END_INT. */ + __IOM uint32_t CH4_ERR_INT_ENA : 1; /*!< The interrupt enable bit for CH4_ERR_INT. */ + __IOM uint32_t CH5_ERR_INT_ENA : 1; /*!< The interrupt enable bit for CH5_ERR_INT. */ + __IOM uint32_t CH6_ERR_INT_ENA : 1; /*!< The interrupt enable bit for CH6_ERR_INT. */ + __IOM uint32_t CH7_ERR_INT_ENA : 1; /*!< The interrupt enable bit for CH7_ERR_INT. */ + __IOM uint32_t CH4_RX_THR_EVENT_INT_ENA : 1;/*!< The interrupt enable bit for CH4_RX_THR_EVENT_INT. */ + __IOM uint32_t CH5_RX_THR_EVENT_INT_ENA : 1;/*!< The interrupt enable bit for CH5_RX_THR_EVENT_INT. */ + __IOM uint32_t CH6_RX_THR_EVENT_INT_ENA : 1;/*!< The interrupt enable bit for CH6_RX_THR_EVENT_INT. */ + __IOM uint32_t CH7_RX_THR_EVENT_INT_ENA : 1;/*!< The interrupt enable bit for CH7_RX_THR_EVENT_INT. */ + __IOM uint32_t TX_CH3_DMA_ACCESS_FAIL_INT_ENA : 1;/*!< The interrupt enable bit for CH3_DMA_ACCESS_FAIL_INT. */ + __IOM uint32_t RX_CH7_DMA_ACCESS_FAIL_INT_ENA : 1;/*!< The interrupt enable bit for CH7_DMA_ACCESS_FAIL_INT. */ + uint32_t : 2; + } bit; + } INT_ENA; + + union { + __IOM uint32_t reg; /*!< Interrupt clear bits */ + + struct { + __OM uint32_t CH0_TX_END_INT_CLR : 1; /*!< Set this bit to clear theCH0_TX_END_INT interrupt. */ + __OM uint32_t CH1_TX_END_INT_CLR : 1; /*!< Set this bit to clear theCH1_TX_END_INT interrupt. */ + __OM uint32_t CH2_TX_END_INT_CLR : 1; /*!< Set this bit to clear theCH2_TX_END_INT interrupt. */ + __OM uint32_t CH3_TX_END_INT_CLR : 1; /*!< Set this bit to clear theCH3_TX_END_INT interrupt. */ + __OM uint32_t TX_CH0_ERR_INT_CLR : 1; /*!< Set this bit to clear theCH0_ERR_INT interrupt. */ + __OM uint32_t TX_CH1_ERR_INT_CLR : 1; /*!< Set this bit to clear theCH1_ERR_INT interrupt. */ + __OM uint32_t TX_CH2_ERR_INT_CLR : 1; /*!< Set this bit to clear theCH2_ERR_INT interrupt. */ + __OM uint32_t TX_CH3_ERR_INT_CLR : 1; /*!< Set this bit to clear theCH3_ERR_INT interrupt. */ + __OM uint32_t CH0_TX_THR_EVENT_INT_CLR : 1;/*!< Set this bit to clear theCH0_TX_THR_EVENT_INT interrupt. */ + __OM uint32_t CH1_TX_THR_EVENT_INT_CLR : 1;/*!< Set this bit to clear theCH1_TX_THR_EVENT_INT interrupt. */ + __OM uint32_t CH2_TX_THR_EVENT_INT_CLR : 1;/*!< Set this bit to clear theCH2_TX_THR_EVENT_INT interrupt. */ + __OM uint32_t CH3_TX_THR_EVENT_INT_CLR : 1;/*!< Set this bit to clear theCH3_TX_THR_EVENT_INT interrupt. */ + __OM uint32_t CH0_TX_LOOP_INT_CLR : 1; /*!< Set this bit to clear theCH0_TX_LOOP_INT interrupt. */ + __OM uint32_t CH1_TX_LOOP_INT_CLR : 1; /*!< Set this bit to clear theCH1_TX_LOOP_INT interrupt. */ + __OM uint32_t CH2_TX_LOOP_INT_CLR : 1; /*!< Set this bit to clear theCH2_TX_LOOP_INT interrupt. */ + __OM uint32_t CH3_TX_LOOP_INT_CLR : 1; /*!< Set this bit to clear theCH3_TX_LOOP_INT interrupt. */ + __OM uint32_t CH4_RX_END_INT_CLR : 1; /*!< Set this bit to clear theCH4_RX_END_INT interrupt. */ + __OM uint32_t CH5_RX_END_INT_CLR : 1; /*!< Set this bit to clear theCH5_RX_END_INT interrupt. */ + __OM uint32_t CH6_RX_END_INT_CLR : 1; /*!< Set this bit to clear theCH6_RX_END_INT interrupt. */ + __OM uint32_t CH7_RX_END_INT_CLR : 1; /*!< Set this bit to clear theCH7_RX_END_INT interrupt. */ + __OM uint32_t RX_CH4_ERR_INT_CLR : 1; /*!< Set this bit to clear theCH4_ERR_INT interrupt. */ + __OM uint32_t RX_CH5_ERR_INT_CLR : 1; /*!< Set this bit to clear theCH5_ERR_INT interrupt. */ + __OM uint32_t RX_CH6_ERR_INT_CLR : 1; /*!< Set this bit to clear theCH6_ERR_INT interrupt. */ + __OM uint32_t RX_CH7_ERR_INT_CLR : 1; /*!< Set this bit to clear theCH7_ERR_INT interrupt. */ + __OM uint32_t CH4_RX_THR_EVENT_INT_CLR : 1;/*!< Set this bit to clear theCH4_RX_THR_EVENT_INT interrupt. */ + __OM uint32_t CH5_RX_THR_EVENT_INT_CLR : 1;/*!< Set this bit to clear theCH5_RX_THR_EVENT_INT interrupt. */ + __OM uint32_t CH6_RX_THR_EVENT_INT_CLR : 1;/*!< Set this bit to clear theCH6_RX_THR_EVENT_INT interrupt. */ + __OM uint32_t CH7_RX_THR_EVENT_INT_CLR : 1;/*!< Set this bit to clear theCH7_RX_THR_EVENT_INT interrupt. */ + __OM uint32_t TX_CH3_DMA_ACCESS_FAIL_INT_CLR : 1;/*!< Set this bit to clear the CH3_DMA_ACCESS_FAIL_INT interrupt. */ + __OM uint32_t RX_CH7_DMA_ACCESS_FAIL_INT_CLR : 1;/*!< Set this bit to clear the CH7_DMA_ACCESS_FAIL_INT interrupt. */ + uint32_t : 2; + } bit; + } INT_CLR; + + union { + union { + __IOM uint32_t reg; /*!< Channel 3 status register */ + + struct { + uint32_t : 11; + __IM uint32_t APB_MEM_WADDR_CH0 : 10; /*!< This register records the memory address offset when writes + RAM over APB bus. */ + uint32_t : 4; + __IM uint32_t MEM_EMPTY_CH0 : 1; /*!< This status bit will be set when the data to be set is more + than memory size and the wraparound mode is disabled. */ + __IM uint32_t APB_MEM_WR_ERR_CH0 : 1; /*!< This status bit will be set if the offset address out of memory + size when writes via APB bus. */ + uint32_t : 5; + } bit; + } TX_CH3STATUS; + + union { + __IOM uint32_t reg; /*!< Channel 2 status register */ + + struct { + uint32_t : 11; + __IM uint32_t APB_MEM_RADDR_CH4 : 10; /*!< This register records the memory address offset when reads RAM + over APB bus. */ + uint32_t : 4; + __IM uint32_t MEM_OWNER_ERR_CH4 : 1; /*!< This status bit will be set when the ownership of memory block + is wrong. */ + __IM uint32_t MEM_FULL_CH4 : 1; /*!< This status bit will be set if the receiver receives more data + than the memory size. */ + __IM uint32_t APB_MEM_RD_ERR_CH4 : 1; /*!< This status bit will be set if the offset address out of memory + size when reads via APB bus. */ + uint32_t : 4; + } bit; + } RX_CH2STATUS; + __IOM uint32_t CH0CARRIER_DUTY; /*!< Channel 0 duty cycle configuration register */ + }; + __IM uint32_t RESERVED7[3]; + + union { + union { + __IOM uint32_t reg; /*!< Channel 3 configure register 0 */ + + struct { + uint32_t : 8; + __IOM uint32_t IDLE_THRES_CH4 : 15; /*!< When no edge is detected on the input signal and continuous + clock cycles is longer than this register value, received + process is finished. */ + uint32_t : 9; + } bit; + } RX_CH3CONF0; + + union { + __IOM uint32_t reg; /*!< Channel 3 status register */ + + struct { + uint32_t : 11; + __IM uint32_t APB_MEM_RADDR_CH4 : 10; /*!< This register records the memory address offset when reads RAM + over APB bus. */ + uint32_t : 4; + __IM uint32_t MEM_OWNER_ERR_CH4 : 1; /*!< This status bit will be set when the ownership of memory block + is wrong. */ + __IM uint32_t MEM_FULL_CH4 : 1; /*!< This status bit will be set if the receiver receives more data + than the memory size. */ + __IM uint32_t APB_MEM_RD_ERR_CH4 : 1; /*!< This status bit will be set if the offset address out of memory + size when reads via APB bus. */ + uint32_t : 4; + } bit; + } RX_CH3STATUS; + __IOM uint32_t CH1CARRIER_DUTY; /*!< Channel 1 duty cycle configuration register */ + __IOM uint32_t CH0_RX_CARRIER_RM; /*!< Channel 0 carrier remove register */ + }; + + union { + __IOM uint32_t reg; /*!< Channel 3 configure register 1 */ + + struct { + uint32_t : 5; + __IOM uint32_t RX_FILTER_THRES_CH4 : 8; /*!< Ignores the input pulse when its width is smaller than this + register value in APB clock periods (in receive mode). */ + uint32_t : 1; + __OM uint32_t AFIFO_RST_CH4 : 1; /*!< Reserved */ + uint32_t : 17; + } bit; + } RX_CH3CONF1; + __IM uint32_t RESERVED8[2]; + + union { + __IOM uint32_t CH2CARRIER_DUTY; /*!< Channel 2 duty cycle configuration register */ + __IOM uint32_t CH1_RX_CARRIER_RM; /*!< Channel 1 carrier remove register */ + + union { + __IOM uint32_t reg; /*!< Channel 0 Tx event configuration register */ + + struct { + uint32_t : 9; + __IOM uint32_t TX_LOOP_NUM_CH : 10; /*!< This register is used to configure the maximum loop count when + tx_conti_mode is valid. */ + __IOM uint32_t TX_LOOP_CNT_EN_CH : 1; /*!< This register is the enabled bit for loop count. */ + __OM uint32_t LOOP_COUNT_RESET_CH : 1; /*!< This register is used to reset the loop count when tx_conti_mode + is valid. */ + uint32_t : 11; + } bit; + } CH0_TX_LIM; + }; + __IM uint32_t RESERVED9[3]; + + union { + __IOM uint32_t CH3CARRIER_DUTY; /*!< Channel 3 duty cycle configuration register */ + __IOM uint32_t CH2_RX_CARRIER_RM; /*!< Channel 2 carrier remove register */ + + union { + __IOM uint32_t reg; /*!< Channel 1 Tx event configuration register */ + + struct { + uint32_t : 9; + __IOM uint32_t TX_LOOP_NUM_CH : 10; /*!< This register is used to configure the maximum loop count when + tx_conti_mode is valid. */ + __IOM uint32_t TX_LOOP_CNT_EN_CH : 1; /*!< This register is the enabled bit for loop count. */ + __OM uint32_t LOOP_COUNT_RESET_CH : 1; /*!< This register is used to reset the loop count when tx_conti_mode + is valid. */ + uint32_t : 11; + } bit; + } CH1_TX_LIM; + __IOM uint32_t CH0_RX_LIM; /*!< Channel 0 Rx event configuration register */ + }; + __IM uint32_t RESERVED10[3]; + + union { + __IOM uint32_t CH3_RX_CARRIER_RM; /*!< Channel 3 carrier remove register */ + + union { + __IOM uint32_t reg; /*!< Channel 2 Tx event configuration register */ + + struct { + uint32_t : 9; + __IOM uint32_t TX_LOOP_NUM_CH : 10; /*!< This register is used to configure the maximum loop count when + tx_conti_mode is valid. */ + __IOM uint32_t TX_LOOP_CNT_EN_CH : 1; /*!< This register is the enabled bit for loop count. */ + __OM uint32_t LOOP_COUNT_RESET_CH : 1; /*!< This register is used to reset the loop count when tx_conti_mode + is valid. */ + uint32_t : 11; + } bit; + } CH2_TX_LIM; + __IOM uint32_t CH1_RX_LIM; /*!< Channel 1 Rx event configuration register */ + + union { + __IOM uint32_t reg; /*!< RMT apb configuration register */ + + struct { + __IOM uint32_t APB_FIFO_MASK : 1; /*!< 1'h1: access memory directly. 1'h0: access memory by FIFO. */ + __IOM uint32_t MEM_CLK_FORCE_ON : 1; /*!< Set this bit to enable the clock for RMT memory. */ + __IOM uint32_t MEM_FORCE_PD : 1; /*!< Set this bit to power down RMT memory. */ + __IOM uint32_t MEM_FORCE_PU : 1; /*!< 1: Disable RMT memory light sleep power down function. 0: Power + down RMT memory when RMT is in light sleep mode. */ + __IOM uint32_t SCLK_DIV_NUM : 8; /*!< the integral part of the fractional divisor */ + __IOM uint32_t SCLK_DIV_A : 6; /*!< the numerator of the fractional part of the fractional divisor */ + __IOM uint32_t SCLK_DIV_B : 6; /*!< the denominator of the fractional part of the fractional divisor */ + __IOM uint32_t SCLK_SEL : 2; /*!< choose the clock source of rmt_sclk. 1:CLK_80Mhz.2:CLK_8MHz.3:XTAL */ + __IOM uint32_t SCLK_ACTIVE : 1; /*!< rmt_sclk switch */ + uint32_t : 4; + __IOM uint32_t CLK_EN : 1; /*!< RMT register clock gate enable signal. 1: Power up the drive + clock of registers. 0: Power down the drive clock of registers */ + } bit; + } SYS_CONF; + }; + + union { + __IOM uint32_t reg; /*!< RMT TX synchronous register */ + + struct { + __IOM uint32_t CH0 : 1; /*!< Set this bit to enable CHANNEL0 to start sending data synchronously + with other enabled channels. */ + __IOM uint32_t CH1 : 1; /*!< Set this bit to enable CHANNEL1 to start sending data synchronously + with other enabled channels. */ + __IOM uint32_t CH2 : 1; /*!< Set this bit to enable CHANNEL2 to start sending data synchronously + with other enabled channels. */ + __IOM uint32_t CH3 : 1; /*!< Set this bit to enable CHANNEL3 to start sending data synchronously + with other enabled channels. */ + __IOM uint32_t EN : 1; /*!< This register is used to enable multiple of channels to start + sending data synchronously. */ + uint32_t : 27; + } bit; + } TX_SIM; + + union { + __IOM uint32_t reg; /*!< RMT clock divider reset register */ + + struct { + __OM uint32_t TX_REF_CNT_RST_CH0 : 1; /*!< This register is used to reset the clock divider of CHANNEL0. */ + __OM uint32_t TX_REF_CNT_RST_CH1 : 1; /*!< This register is used to reset the clock divider of CHANNEL1. */ + __OM uint32_t TX_REF_CNT_RST_CH2 : 1; /*!< This register is used to reset the clock divider of CHANNEL2. */ + __OM uint32_t TX_REF_CNT_RST_CH3 : 1; /*!< This register is used to reset the clock divider of CHANNEL3. */ + __OM uint32_t RX_REF_CNT_RST_CH4 : 1; /*!< This register is used to reset the clock divider of CHANNEL4. */ + __OM uint32_t RX_REF_CNT_RST_CH5 : 1; /*!< This register is used to reset the clock divider of CHANNEL5. */ + __OM uint32_t RX_REF_CNT_RST_CH6 : 1; /*!< This register is used to reset the clock divider of CHANNEL6. */ + __OM uint32_t RX_REF_CNT_RST_CH7 : 1; /*!< This register is used to reset the clock divider of CHANNEL7. */ + uint32_t : 24; + } bit; + } REF_CNT_RST; + + union { + __IOM uint32_t reg; /*!< RMT version register */ + + struct { + __IOM uint32_t DATE : 28; /*!< This is the version register. */ + uint32_t : 4; + } bit; + } DATE; + + union { + union { + __IOM uint32_t reg; /*!< Channel 3 Tx event configuration register */ + + struct { + uint32_t : 9; + __IOM uint32_t TX_LOOP_NUM_CH : 10; /*!< This register is used to configure the maximum loop count when + tx_conti_mode is valid. */ + __IOM uint32_t TX_LOOP_CNT_EN_CH : 1; /*!< This register is the enabled bit for loop count. */ + __OM uint32_t LOOP_COUNT_RESET_CH : 1; /*!< This register is used to reset the loop count when tx_conti_mode + is valid. */ + uint32_t : 11; + } bit; + } CH3_TX_LIM; + __IOM uint32_t CH2_RX_LIM; /*!< Channel 2 Rx event configuration register */ + }; + __IM uint32_t RESERVED11[3]; + __IOM uint32_t CH3_RX_LIM; /*!< Channel 3 Rx event configuration register */ +} RMT_Type; /*!< Size = 228 (0xe4) */ + + + +/* =========================================================================================================================== */ +/* ================ RSA ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief RSA (Rivest Shamir Adleman) Accelerator (RSA) + */ + +typedef struct { /*!< RSA Structure */ + __IOM uint32_t M_MEM[4]; /*!< Represents M */ + __IM uint32_t RESERVED[124]; + __IOM uint32_t Z_MEM[4]; /*!< Represents Z */ + __IM uint32_t RESERVED1[124]; + __IOM uint32_t Y_MEM[4]; /*!< Represents Y */ + __IM uint32_t RESERVED2[124]; + __IOM uint32_t X_MEM[4]; /*!< Represents X */ + __IM uint32_t RESERVED3[124]; + + union { + __IOM uint32_t reg; /*!< Represents M’ */ + + struct { + __IOM uint32_t M_PRIME : 32; /*!< Represents M’ */ + } bit; + } M_PRIME; + + union { + __IOM uint32_t reg; /*!< Configures RSA length */ + + struct { + __IOM uint32_t MODE : 7; /*!< Configures the RSA length. */ + uint32_t : 25; + } bit; + } MODE; + + union { + __IOM uint32_t reg; /*!< RSA clean register */ + + struct { + __IM uint32_t QUERY_CLEAN : 1; /*!< Represents whether or not the RSA memory completes initialization.0: + Not complete1: Completed */ + uint32_t : 31; + } bit; + } QUERY_CLEAN; + + union { + __IOM uint32_t reg; /*!< Starts modular exponentiation */ + + struct { + __OM uint32_t SET_START_MODEXP : 1; /*!< Configure whether or not to start the modular exponentiation.0: + No effect1: Start */ + uint32_t : 31; + } bit; + } SET_START_MODEXP; + + union { + __IOM uint32_t reg; /*!< Starts modular multiplication */ + + struct { + __OM uint32_t SET_START_MODMULT : 1; /*!< Configure whether or not to start the modular multiplication.0: + No effect1: Start */ + uint32_t : 31; + } bit; + } SET_START_MODMULT; + + union { + __IOM uint32_t reg; /*!< Starts multiplication */ + + struct { + __OM uint32_t SET_START_MULT : 1; /*!< Configure whether or not to start the multiplication.0: No effect1: + Start */ + uint32_t : 31; + } bit; + } SET_START_MULT; + + union { + __IOM uint32_t reg; /*!< Represents the RSA status */ + + struct { + __IM uint32_t QUERY_IDLE : 1; /*!< Represents the RSA status.0: Busy1: Idle */ + uint32_t : 31; + } bit; + } QUERY_IDLE; + + union { + __IOM uint32_t reg; /*!< Clears RSA interrupt */ + + struct { + __OM uint32_t CLEAR_INTERRUPT : 1; /*!< Write 1 to clear the RSA interrupt. */ + uint32_t : 31; + } bit; + } INT_CLR; + + union { + __IOM uint32_t reg; /*!< Configures the constant_time option */ + + struct { + __IOM uint32_t CONSTANT_TIME : 1; /*!< Configures the constant_time option. 0: Acceleration1: No acceleration + (default) */ + uint32_t : 31; + } bit; + } CONSTANT_TIME; + + union { + __IOM uint32_t reg; /*!< Configures the search option */ + + struct { + __IOM uint32_t SEARCH_ENABLE : 1; /*!< Configure the search option. 0: No acceleration (default)1: + AccelerationThis option should be used together with RSA_SEARCH_POS. */ + uint32_t : 31; + } bit; + } SEARCH_ENABLE; + + union { + __IOM uint32_t reg; /*!< Configures the search position */ + + struct { + __IOM uint32_t SEARCH_POS : 12; /*!< Configures the starting address to start search. This field + should be used together with RSA_SEARCH_ENABLE. The field + is only valid when RSA_SEARCH_ENABLE is high. */ + uint32_t : 20; + } bit; + } SEARCH_POS; + + union { + __IOM uint32_t reg; /*!< Enables the RSA interrupt */ + + struct { + __IOM uint32_t INT_ENA : 1; /*!< Write 1 to enable the RSA interrupt. */ + uint32_t : 31; + } bit; + } INT_ENA; + + union { + __IOM uint32_t reg; /*!< Version control register */ + + struct { + __IOM uint32_t DATE : 30; /*!< Version control register. */ + uint32_t : 2; + } bit; + } DATE; +} RSA_Type; /*!< Size = 2100 (0x834) */ + + + +/* =========================================================================================================================== */ +/* ================ LP_ADC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Low-power Analog to Digital Converter (LP_ADC) + */ + +typedef struct { /*!< LP_ADC Structure */ + + union { + __IOM uint32_t reg; /*!< Control the read operation of ADC1. */ + + struct { + __IOM uint32_t SAR1_CLK_DIV : 8; /*!< Clock divider. */ + uint32_t : 10; + __IOM uint32_t SAR1_CLK_GATED : 1; /*!< N/A */ + __IOM uint32_t SAR1_SAMPLE_NUM : 8; /*!< N/A */ + uint32_t : 1; + __IOM uint32_t SAR1_DATA_INV : 1; /*!< Invert SAR ADC1 data. */ + __IOM uint32_t SAR1_INT_EN : 1; /*!< Enable saradc1 to send out interrupt. */ + __IOM uint32_t SAR1_EN_PAD_FORCE_ENABLE : 2;/*!< Force enable adc en_pad to analog circuit 2'b11: force enable + . */ + } bit; + } READER1_CTRL; + + union { + __IOM uint32_t reg; /*!< N/A */ + + struct { + __IM uint32_t SAR1_READER_STATUS : 32; /*!< N/A */ + } bit; + } READER1_STATUS; + + union { + __IOM uint32_t reg; /*!< N/A */ + + struct { + uint32_t : 24; + __IOM uint32_t FORCE_XPD_AMP : 2; /*!< N/A */ + __IOM uint32_t AMP_RST_FB_FORCE : 2; /*!< N/A */ + __IOM uint32_t AMP_SHORT_REF_FORCE : 2; /*!< N/A */ + __IOM uint32_t AMP_SHORT_REF_GND_FORCE : 2;/*!< N/A */ + } bit; + } MEAS1_CTRL1; + + union { + __IOM uint32_t reg; /*!< ADC1 configuration registers. */ + + struct { + __IM uint32_t MEAS1_DATA_SAR : 16; /*!< SAR ADC1 data. */ + __IM uint32_t MEAS1_DONE_SAR : 1; /*!< SAR ADC1 conversion done indication. */ + __IOM uint32_t MEAS1_START_SAR : 1; /*!< SAR ADC1 controller (in RTC) starts conversion. */ + __IOM uint32_t MEAS1_START_FORCE : 1; /*!< 1: SAR ADC1 controller (in RTC) is started by SW. */ + __IOM uint32_t SAR1_EN_PAD : 12; /*!< SAR ADC1 pad enable bitmap. */ + __IOM uint32_t SAR1_EN_PAD_FORCE : 1; /*!< 1: SAR ADC1 pad enable bitmap is controlled by SW. */ + } bit; + } MEAS1_CTRL2; + + union { + __IOM uint32_t reg; /*!< SAR ADC1 MUX register. */ + + struct { + uint32_t : 31; + __IOM uint32_t SAR1_DIG_FORCE : 1; /*!< 1: SAR ADC1 controlled by DIG ADC1 CTRL. */ + } bit; + } MEAS1_MUX; + + union { + __IOM uint32_t reg; /*!< ADC1 attenuation registers. */ + + struct { + __IOM uint32_t SAR1_ATTEN : 32; /*!< 2-bit attenuation for each pad. */ + } bit; + } ATTEN1; + + union { + __IOM uint32_t reg; /*!< N/A */ + + struct { + __IOM uint32_t SAR_AMP_WAIT1 : 16; /*!< N/A */ + __IOM uint32_t SAR_AMP_WAIT2 : 16; /*!< N/A */ + } bit; + } AMP_CTRL1; + + union { + __IOM uint32_t reg; /*!< N/A */ + + struct { + __IOM uint32_t SAR1_DAC_XPD_FSM_IDLE : 1; /*!< N/A */ + __IOM uint32_t XPD_SAR_AMP_FSM_IDLE : 1; /*!< N/A */ + __IOM uint32_t AMP_RST_FB_FSM_IDLE : 1; /*!< N/A */ + __IOM uint32_t AMP_SHORT_REF_FSM_IDLE : 1;/*!< N/A */ + __IOM uint32_t AMP_SHORT_REF_GND_FSM_IDLE : 1;/*!< N/A */ + __IOM uint32_t XPD_SAR_FSM_IDLE : 1; /*!< N/A */ + __IOM uint32_t SAR_RSTB_FSM_IDLE : 1; /*!< N/A */ + uint32_t : 9; + __IOM uint32_t SAR_AMP_WAIT3 : 16; /*!< N/A */ + } bit; + } AMP_CTRL2; + + union { + __IOM uint32_t reg; /*!< N/A */ + + struct { + __IOM uint32_t SAR1_DAC_XPD_FSM : 4; /*!< N/A */ + __IOM uint32_t XPD_SAR_AMP_FSM : 4; /*!< N/A */ + __IOM uint32_t AMP_RST_FB_FSM : 4; /*!< N/A */ + __IOM uint32_t AMP_SHORT_REF_FSM : 4; /*!< N/A */ + __IOM uint32_t AMP_SHORT_REF_GND_FSM : 4; /*!< N/A */ + __IOM uint32_t XPD_SAR_FSM : 4; /*!< N/A */ + __IOM uint32_t SAR_RSTB_FSM : 4; /*!< N/A */ + uint32_t : 4; + } bit; + } AMP_CTRL3; + + union { + __IOM uint32_t reg; /*!< Control the read operation of ADC2. */ + + struct { + __IOM uint32_t SAR2_CLK_DIV : 8; /*!< Clock divider. */ + uint32_t : 8; + __IOM uint32_t SAR2_WAIT_ARB_CYCLE : 2; /*!< Wait arbit stable after sar_done. */ + __IOM uint32_t SAR2_CLK_GATED : 1; /*!< N/A */ + __IOM uint32_t SAR2_SAMPLE_NUM : 8; /*!< N/A */ + __IOM uint32_t SAR2_EN_PAD_FORCE_ENABLE : 2;/*!< Force enable adc en_pad to analog circuit 2'b11: force enable + . */ + __IOM uint32_t SAR2_DATA_INV : 1; /*!< Invert SAR ADC2 data. */ + __IOM uint32_t SAR2_INT_EN : 1; /*!< Enable saradc2 to send out interrupt. */ + uint32_t : 1; + } bit; + } READER2_CTRL; + + union { + __IOM uint32_t reg; /*!< N/A */ + + struct { + __IM uint32_t SAR2_READER_STATUS : 32; /*!< N/A */ + } bit; + } READER2_STATUS; + + union { + __IOM uint32_t reg; /*!< ADC2 configuration registers. */ + + struct { + __IM uint32_t SAR2_CNTL_STATE : 3; /*!< saradc2_cntl_fsm. */ + __IOM uint32_t SAR2_PWDET_CAL_EN : 1; /*!< RTC control pwdet enable. */ + __IOM uint32_t SAR2_PKDET_CAL_EN : 1; /*!< RTC control pkdet enable. */ + __IOM uint32_t SAR2_EN_TEST : 1; /*!< SAR2_EN_TEST. */ + __IOM uint32_t SAR2_RSTB_FORCE : 2; /*!< N/A */ + __IOM uint32_t SAR2_STANDBY_WAIT : 8; /*!< N/A */ + __IOM uint32_t SAR2_RSTB_WAIT : 8; /*!< N/A */ + __IOM uint32_t SAR2_XPD_WAIT : 8; /*!< N/A */ + } bit; + } MEAS2_CTRL1; + + union { + __IOM uint32_t reg; /*!< ADC2 configuration registers. */ + + struct { + __IM uint32_t MEAS2_DATA_SAR : 16; /*!< SAR ADC2 data. */ + __IM uint32_t MEAS2_DONE_SAR : 1; /*!< SAR ADC2 conversion done indication. */ + __IOM uint32_t MEAS2_START_SAR : 1; /*!< SAR ADC2 controller (in RTC) starts conversion. */ + __IOM uint32_t MEAS2_START_FORCE : 1; /*!< 1: SAR ADC2 controller (in RTC) is started by SW. */ + __IOM uint32_t SAR2_EN_PAD : 12; /*!< SAR ADC2 pad enable bitmap. */ + __IOM uint32_t SAR2_EN_PAD_FORCE : 1; /*!< 1: SAR ADC2 pad enable bitmap is controlled by SW. */ + } bit; + } MEAS2_CTRL2; + + union { + __IOM uint32_t reg; /*!< SAR ADC2 MUX register. */ + + struct { + uint32_t : 28; + __IOM uint32_t SAR2_PWDET_CCT : 3; /*!< SAR2_PWDET_CCT. */ + __IOM uint32_t SAR2_RTC_FORCE : 1; /*!< In sleep, force to use rtc to control ADC. */ + } bit; + } MEAS2_MUX; + + union { + __IOM uint32_t reg; /*!< ADC1 attenuation registers. */ + + struct { + __IOM uint32_t SAR2_ATTEN : 32; /*!< 2-bit attenuation for each pad. */ + } bit; + } ATTEN2; + + union { + __IOM uint32_t reg; /*!< In sleep, force to use rtc to control ADC */ + + struct { + __IOM uint32_t FORCE_XPD_SAR1 : 2; /*!< 2'b11:software control, force on. 2'b10:software control, force + off. 2'b0x:hardware control. */ + __IOM uint32_t FORCE_XPD_SAR2 : 2; /*!< 2'b11:software control, force on. 2'b10:software control, force + off. 2'b0x:hardware control. */ + uint32_t : 28; + } bit; + } FORCE_WPD_SAR; + + union { + __IOM uint32_t reg; /*!< N/A */ + + struct { + __IM uint32_t SARADC_MEAS_STATUS : 8; /*!< N/A */ + uint32_t : 24; + } bit; + } MEAS_STATUS; + + union { + __IOM uint32_t reg; /*!< N/A */ + + struct { + __IOM uint32_t CLK_EN : 1; /*!< N/A */ + uint32_t : 31; + } bit; + } REG_CLKEN; + + union { + __IOM uint32_t reg; /*!< Interrupt raw registers. */ + + struct { + __IOM uint32_t COCPU_SARADC1_INT_RAW : 1; /*!< ADC1 Conversion is done, int raw. */ + __IOM uint32_t COCPU_SARADC2_INT_RAW : 1; /*!< ADC2 Conversion is done, int raw. */ + __IOM uint32_t COCPU_SARADC1_ERROR_INT_RAW : 1;/*!< An errro occurs from ADC1, int raw. */ + __IOM uint32_t COCPU_SARADC2_ERROR_INT_RAW : 1;/*!< An errro occurs from ADC2, int raw. */ + __IOM uint32_t COCPU_SARADC1_WAKE_INT_RAW : 1;/*!< A wakeup event is triggered from ADC1, int raw. */ + __IOM uint32_t COCPU_SARADC2_WAKE_INT_RAW : 1;/*!< A wakeup event is triggered from ADC2, int raw. */ + uint32_t : 26; + } bit; + } COCPU_INT_RAW; + + union { + __IOM uint32_t reg; /*!< Interrupt enable registers. */ + + struct { + __IOM uint32_t COCPU_SARADC1_INT_ENA : 1; /*!< ADC1 Conversion is done, int enable. */ + __IOM uint32_t COCPU_SARADC2_INT_ENA : 1; /*!< ADC2 Conversion is done, int enable. */ + __IOM uint32_t COCPU_SARADC1_ERROR_INT_ENA : 1;/*!< An errro occurs from ADC1, int enable. */ + __IOM uint32_t COCPU_SARADC2_ERROR_INT_ENA : 1;/*!< An errro occurs from ADC2, int enable. */ + __IOM uint32_t COCPU_SARADC1_WAKE_INT_ENA : 1;/*!< A wakeup event is triggered from ADC1, int enable. */ + __IOM uint32_t COCPU_SARADC2_WAKE_INT_ENA : 1;/*!< A wakeup event is triggered from ADC2, int enable. */ + uint32_t : 26; + } bit; + } INT_ENA; + + union { + __IOM uint32_t reg; /*!< Interrupt status registers. */ + + struct { + __IM uint32_t COCPU_SARADC1_INT_ST : 1; /*!< ADC1 Conversion is done, int status. */ + __IM uint32_t COCPU_SARADC2_INT_ST : 1; /*!< ADC2 Conversion is done, int status. */ + __IM uint32_t COCPU_SARADC1_ERROR_INT_ST : 1;/*!< An errro occurs from ADC1, int status. */ + __IM uint32_t COCPU_SARADC2_ERROR_INT_ST : 1;/*!< An errro occurs from ADC2, int status. */ + __IM uint32_t COCPU_SARADC1_WAKE_INT_ST : 1;/*!< A wakeup event is triggered from ADC1, int status. */ + __IM uint32_t COCPU_SARADC2_WAKE_INT_ST : 1;/*!< A wakeup event is triggered from ADC2, int status. */ + uint32_t : 26; + } bit; + } INT_ST; + + union { + __IOM uint32_t reg; /*!< Interrupt clear registers. */ + + struct { + __OM uint32_t COCPU_SARADC1_INT_CLR : 1; /*!< ADC1 Conversion is done, int clear. */ + __OM uint32_t COCPU_SARADC2_INT_CLR : 1; /*!< ADC2 Conversion is done, int clear. */ + __OM uint32_t COCPU_SARADC1_ERROR_INT_CLR : 1;/*!< An errro occurs from ADC1, int clear. */ + __OM uint32_t COCPU_SARADC2_ERROR_INT_CLR : 1;/*!< An errro occurs from ADC2, int clear. */ + __OM uint32_t COCPU_SARADC1_WAKE_INT_CLR : 1;/*!< A wakeup event is triggered from ADC1, int clear. */ + __OM uint32_t COCPU_SARADC2_WAKE_INT_CLR : 1;/*!< A wakeup event is triggered from ADC2, int clear. */ + uint32_t : 26; + } bit; + } INT_CLR; + + union { + __IOM uint32_t reg; /*!< Interrupt enable assert registers. */ + + struct { + __OM uint32_t COCPU_SARADC1_INT_ENA_W1TS : 1;/*!< ADC1 Conversion is done, write 1 to assert int enable. */ + __OM uint32_t COCPU_SARADC2_INT_ENA_W1TS : 1;/*!< ADC2 Conversion is done, write 1 to assert int enable. */ + __OM uint32_t COCPU_SARADC1_ERROR_INT_ENA_W1TS : 1;/*!< An errro occurs from ADC1, write 1 to assert int enable. */ + __OM uint32_t COCPU_SARADC2_ERROR_INT_ENA_W1TS : 1;/*!< An errro occurs from ADC2, write 1 to assert int enable. */ + __OM uint32_t COCPU_SARADC1_WAKE_INT_ENA_W1TS : 1;/*!< A wakeup event is triggered from ADC1, write 1 to assert int + enable. */ + __OM uint32_t COCPU_SARADC2_WAKE_INT_ENA_W1TS : 1;/*!< A wakeup event is triggered from ADC2, write 1 to assert int + enable. */ + uint32_t : 26; + } bit; + } INT_ENA_W1TS; + + union { + __IOM uint32_t reg; /*!< Interrupt enable deassert registers. */ + + struct { + __OM uint32_t COCPU_SARADC1_INT_ENA_W1TC : 1;/*!< ADC1 Conversion is done, write 1 to deassert int enable. */ + __OM uint32_t COCPU_SARADC2_INT_ENA_W1TC : 1;/*!< ADC2 Conversion is done, write 1 to deassert int enable. */ + __OM uint32_t COCPU_SARADC1_ERROR_INT_ENA_W1TC : 1;/*!< An errro occurs from ADC1, write 1 to deassert int enable. */ + __OM uint32_t COCPU_SARADC2_ERROR_INT_ENA_W1TC : 1;/*!< An errro occurs from ADC2, write 1 to deassert int enable. */ + __OM uint32_t COCPU_SARADC1_WAKE_INT_ENA_W1TC : 1;/*!< A wakeup event is triggered from ADC1, write 1 to deassert int + enable. */ + __OM uint32_t COCPU_SARADC2_WAKE_INT_ENA_W1TC : 1;/*!< A wakeup event is triggered from ADC2, write 1 to deassert int + enable. */ + uint32_t : 26; + } bit; + } INT_ENA_W1TC; + + union { + __IOM uint32_t reg; /*!< ADC1 wakeup configuration registers. */ + + struct { + __IOM uint32_t SAR1_WAKEUP_TH_LOW : 12; /*!< Lower threshold. */ + uint32_t : 2; + __IOM uint32_t SAR1_WAKEUP_TH_HIGH : 12; /*!< Upper threshold. */ + uint32_t : 3; + __IM uint32_t SAR1_WAKEUP_OVER_UPPER_TH : 1;/*!< Indicates that this wakeup event arose from exceeding upper + threshold. */ + __IOM uint32_t SAR1_WAKEUP_EN : 1; /*!< Wakeup function enable. */ + __IOM uint32_t SAR1_WAKEUP_MODE : 1; /*!< 0:absolute value comparison mode. 1: relative value comparison + mode. */ + } bit; + } WAKEUP1; + + union { + __IOM uint32_t reg; /*!< ADC2 wakeup configuration registers. */ + + struct { + __IOM uint32_t SAR2_WAKEUP_TH_LOW : 12; /*!< Lower threshold. */ + uint32_t : 2; + __IOM uint32_t SAR2_WAKEUP_TH_HIGH : 12; /*!< Upper threshold. */ + uint32_t : 3; + __IM uint32_t SAR2_WAKEUP_OVER_UPPER_TH : 1;/*!< Indicates that this wakeup event arose from exceeding upper + threshold. */ + __IOM uint32_t SAR2_WAKEUP_EN : 1; /*!< Wakeup function enable. */ + __IOM uint32_t SAR2_WAKEUP_MODE : 1; /*!< 0:absolute value comparison mode. 1: relative value comparison + mode. */ + } bit; + } WAKEUP2; + + union { + __IOM uint32_t reg; /*!< Wakeup source select register. */ + + struct { + __IOM uint32_t SAR_WAKEUP_SEL : 1; /*!< 0: ADC1. 1: ADC2. */ + uint32_t : 31; + } bit; + } WAKEUP_SEL; + + union { + __IOM uint32_t reg; /*!< Hardware automatic sampling registers for wakeup function. */ + + struct { + __IOM uint32_t ADC1_HW_READ_EN_I : 1; /*!< Enable hardware automatic sampling. */ + __IOM uint32_t ADC1_HW_READ_RATE_I : 16; /*!< Hardware automatic sampling rate. */ + uint32_t : 15; + } bit; + } SAR1_HW_WAKEUP; + + union { + __IOM uint32_t reg; /*!< Hardware automatic sampling registers for wakeup function. */ + + struct { + __IOM uint32_t ADC2_HW_READ_EN_I : 1; /*!< Enable hardware automatic sampling. */ + __IOM uint32_t ADC2_HW_READ_RATE_I : 16; /*!< Hardware automatic sampling rate. */ + uint32_t : 15; + } bit; + } SAR2_HW_WAKEUP; + + union { + __IOM uint32_t reg; /*!< N/A */ + + struct { + __IOM uint32_t RND_ECO_LOW : 32; /*!< N/A */ + } bit; + } RND_ECO_LOW; + + union { + __IOM uint32_t reg; /*!< N/A */ + + struct { + __IOM uint32_t RND_ECO_HIGH : 32; /*!< N/A */ + } bit; + } RND_ECO_HIGH; + + union { + __IOM uint32_t reg; /*!< N/A */ + + struct { + __IOM uint32_t RND_ECO_EN : 1; /*!< N/A */ + __IM uint32_t RND_ECO_RESULT : 1; /*!< N/A */ + uint32_t : 30; + } bit; + } RND_ECO_CS; +} LP_ADC_Type; /*!< Size = 128 (0x80) */ + + + +/* =========================================================================================================================== */ +/* ================ LP_TIMER ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Low-power Timer (LP_TIMER) + */ + +typedef struct { /*!< LP_TIMER Structure */ + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t MAIN_TIMER_TAR_LOW0 : 32; /*!< need_des */ + } bit; + } TAR0_LOW; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t MAIN_TIMER_TAR_HIGH0 : 16; /*!< need_des */ + uint32_t : 15; + __OM uint32_t MAIN_TIMER_TAR_EN0 : 1; /*!< need_des */ + } bit; + } TAR0_HIGH; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t MAIN_TIMER_TAR_LOW1 : 32; /*!< need_des */ + } bit; + } TAR1_LOW; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t MAIN_TIMER_TAR_HIGH1 : 16; /*!< need_des */ + uint32_t : 15; + __OM uint32_t MAIN_TIMER_TAR_EN1 : 1; /*!< need_des */ + } bit; + } TAR1_HIGH; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 28; + __OM uint32_t MAIN_TIMER_UPDATE : 1; /*!< need_des */ + __IOM uint32_t MAIN_TIMER_XTAL_OFF : 1; /*!< need_des */ + __IOM uint32_t MAIN_TIMER_SYS_STALL : 1; /*!< need_des */ + __IOM uint32_t MAIN_TIMER_SYS_RST : 1; /*!< need_des */ + } bit; + } UPDATE; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IM uint32_t MAIN_TIMER_BUF0_LOW : 32; /*!< need_des */ + } bit; + } MAIN_BUF0_LOW; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IM uint32_t MAIN_TIMER_BUF0_HIGH : 16; /*!< need_des */ + uint32_t : 16; + } bit; + } MAIN_BUF0_HIGH; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IM uint32_t MAIN_TIMER_BUF1_LOW : 32; /*!< need_des */ + } bit; + } MAIN_BUF1_LOW; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IM uint32_t MAIN_TIMER_BUF1_HIGH : 16; /*!< need_des */ + uint32_t : 16; + } bit; + } MAIN_BUF1_HIGH; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 31; + __OM uint32_t MAIN_TIMER_ALARM_LOAD : 1; /*!< need_des */ + } bit; + } MAIN_OVERFLOW; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 30; + __IOM uint32_t OVERFLOW_RAW : 1; /*!< need_des */ + __IOM uint32_t SOC_WAKEUP_INT_RAW : 1; /*!< need_des */ + } bit; + } INT_RAW; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 30; + __IM uint32_t OVERFLOW_ST : 1; /*!< need_des */ + __IM uint32_t SOC_WAKEUP_INT_ST : 1; /*!< need_des */ + } bit; + } INT_ST; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 30; + __IOM uint32_t OVERFLOW_ENA : 1; /*!< need_des */ + __IOM uint32_t SOC_WAKEUP_INT_ENA : 1; /*!< need_des */ + } bit; + } INT_ENA; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 30; + __OM uint32_t OVERFLOW_CLR : 1; /*!< need_des */ + __OM uint32_t SOC_WAKEUP_INT_CLR : 1; /*!< need_des */ + } bit; + } INT_CLR; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 30; + __IOM uint32_t MAIN_TIMER_OVERFLOW_LP_INT_RAW : 1;/*!< need_des */ + __IOM uint32_t MAIN_TIMER_LP_INT_RAW : 1; /*!< need_des */ + } bit; + } LP_INT_RAW; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 30; + __IM uint32_t MAIN_TIMER_OVERFLOW_LP_INT_ST : 1;/*!< need_des */ + __IM uint32_t MAIN_TIMER_LP_INT_ST : 1; /*!< need_des */ + } bit; + } LP_INT_ST; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 30; + __IOM uint32_t MAIN_TIMER_OVERFLOW_LP_INT_ENA : 1;/*!< need_des */ + __IOM uint32_t MAIN_TIMER_LP_INT_ENA : 1; /*!< need_des */ + } bit; + } LP_INT_ENA; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 30; + __OM uint32_t MAIN_TIMER_OVERFLOW_LP_INT_CLR : 1;/*!< need_des */ + __OM uint32_t MAIN_TIMER_LP_INT_CLR : 1; /*!< need_des */ + } bit; + } LP_INT_CLR; + __IM uint32_t RESERVED[237]; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t DATE : 31; /*!< need_des */ + __IOM uint32_t CLK_EN : 1; /*!< need_des */ + } bit; + } DATE; +} LP_TIMER_Type; /*!< Size = 1024 (0x400) */ + + + +/* =========================================================================================================================== */ +/* ================ LP_TOUCH ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief LP_TOUCH Peripheral (LP_TOUCH) + */ + +typedef struct { /*!< LP_TOUCH Structure */ + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t SCAN_DONE_INT_RAW : 1; /*!< need_des */ + __IOM uint32_t DONE_INT_RAW : 1; /*!< need_des */ + __IOM uint32_t ACTIVE_INT_RAW : 1; /*!< need_des */ + __IOM uint32_t INACTIVE_INT_RAW : 1; /*!< need_des */ + __IOM uint32_t TIMEOUT_INT_RAW : 1; /*!< need_des */ + __IOM uint32_t APPROACH_LOOP_DONE_INT_RAW : 1;/*!< need_des */ + uint32_t : 26; + } bit; + } INT_RAW; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IM uint32_t SCAN_DONE_INT_ST : 1; /*!< need_des */ + __IM uint32_t DONE_INT_ST : 1; /*!< need_des */ + __IM uint32_t ACTIVE_INT_ST : 1; /*!< need_des */ + __IM uint32_t INACTIVE_INT_ST : 1; /*!< need_des */ + __IM uint32_t TIMEOUT_INT_ST : 1; /*!< need_des */ + __IM uint32_t APPROACH_LOOP_DONE_INT_ST : 1;/*!< need_des */ + uint32_t : 26; + } bit; + } INT_ST; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t SCAN_DONE_INT_ENA : 1; /*!< need_des */ + __IOM uint32_t DONE_INT_ENA : 1; /*!< need_des */ + __IOM uint32_t ACTIVE_INT_ENA : 1; /*!< need_des */ + __IOM uint32_t INACTIVE_INT_ENA : 1; /*!< need_des */ + __IOM uint32_t TIMEOUT_INT_ENA : 1; /*!< need_des */ + __IOM uint32_t APPROACH_LOOP_DONE_INT_ENA : 1;/*!< need_des */ + uint32_t : 26; + } bit; + } INT_ENA; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __OM uint32_t SCAN_DONE_INT_CLR : 1; /*!< need_des */ + __OM uint32_t DONE_INT_CLR : 1; /*!< need_des */ + __OM uint32_t ACTIVE_INT_CLR : 1; /*!< need_des */ + __OM uint32_t INACTIVE_INT_CLR : 1; /*!< need_des */ + __OM uint32_t TIMEOUT_INT_CLR : 1; /*!< need_des */ + __OM uint32_t APPROACH_LOOP_DONE_INT_CLR : 1;/*!< need_des */ + uint32_t : 26; + } bit; + } INT_CLR; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IM uint32_t PAD_ACTIVE : 15; /*!< need_des */ + __IM uint32_t MEAS_DONE : 1; /*!< need_des */ + __IM uint32_t SCAN_CURR : 4; /*!< need_des */ + uint32_t : 12; + } bit; + } CHN_STATUS; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IM uint32_t PAD0_DATA : 16; /*!< need_des */ + __IM uint32_t PAD0_DEBOUNCE_CNT : 3; /*!< need_des */ + __IM uint32_t PAD0_NEG_NOISE_CNT : 4; /*!< need_des */ + uint32_t : 9; + } bit; + } STATUS_0; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IM uint32_t PAD1_DATA : 16; /*!< need_des */ + __IM uint32_t PAD1_DEBOUNCE_CNT : 3; /*!< need_des */ + __IM uint32_t PAD1_NEG_NOISE_CNT : 4; /*!< need_des */ + uint32_t : 9; + } bit; + } STATUS_1; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IM uint32_t PAD2_DATA : 16; /*!< need_des */ + __IM uint32_t PAD2_DEBOUNCE_CNT : 3; /*!< need_des */ + __IM uint32_t PAD2_NEG_NOISE_CNT : 4; /*!< need_des */ + uint32_t : 9; + } bit; + } STATUS_2; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IM uint32_t PAD3_DATA : 16; /*!< need_des */ + __IM uint32_t PAD3_DEBOUNCE_CNT : 3; /*!< need_des */ + __IM uint32_t PAD3_NEG_NOISE_CNT : 4; /*!< need_des */ + uint32_t : 9; + } bit; + } STATUS_3; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IM uint32_t PAD4_DATA : 16; /*!< need_des */ + __IM uint32_t PAD4_DEBOUNCE_CNT : 3; /*!< need_des */ + __IM uint32_t PAD4_NEG_NOISE_CNT : 4; /*!< need_des */ + uint32_t : 9; + } bit; + } STATUS_4; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IM uint32_t PAD5_DATA : 16; /*!< need_des */ + __IM uint32_t PAD5_DEBOUNCE_CNT : 3; /*!< need_des */ + __IM uint32_t PAD5_NEG_NOISE_CNT : 4; /*!< need_des */ + uint32_t : 9; + } bit; + } STATUS_5; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IM uint32_t PAD6_DATA : 16; /*!< need_des */ + __IM uint32_t PAD6_DEBOUNCE_CNT : 3; /*!< need_des */ + __IM uint32_t PAD6_NEG_NOISE_CNT : 4; /*!< need_des */ + uint32_t : 9; + } bit; + } STATUS_6; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IM uint32_t PAD7_DATA : 16; /*!< need_des */ + __IM uint32_t PAD7_DEBOUNCE_CNT : 3; /*!< need_des */ + __IM uint32_t PAD7_NEG_NOISE_CNT : 4; /*!< need_des */ + uint32_t : 9; + } bit; + } STATUS_7; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IM uint32_t PAD8_DATA : 16; /*!< need_des */ + __IM uint32_t PAD8_DEBOUNCE_CNT : 3; /*!< need_des */ + __IM uint32_t PAD8_NEG_NOISE_CNT : 4; /*!< need_des */ + uint32_t : 9; + } bit; + } STATUS_8; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IM uint32_t PAD9_DATA : 16; /*!< need_des */ + __IM uint32_t PAD9_DEBOUNCE_CNT : 3; /*!< need_des */ + __IM uint32_t PAD9_NEG_NOISE_CNT : 4; /*!< need_des */ + uint32_t : 9; + } bit; + } STATUS_9; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IM uint32_t PAD10_DATA : 16; /*!< need_des */ + __IM uint32_t PAD10_DEBOUNCE_CNT : 3; /*!< need_des */ + __IM uint32_t PAD10_NEG_NOISE_CNT : 4; /*!< need_des */ + uint32_t : 9; + } bit; + } STATUS_10; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IM uint32_t PAD11_DATA : 16; /*!< need_des */ + __IM uint32_t PAD11_DEBOUNCE_CNT : 3; /*!< need_des */ + __IM uint32_t PAD11_NEG_NOISE_CNT : 4; /*!< need_des */ + uint32_t : 9; + } bit; + } STATUS_11; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IM uint32_t PAD12_DATA : 16; /*!< need_des */ + __IM uint32_t PAD12_DEBOUNCE_CNT : 3; /*!< need_des */ + __IM uint32_t PAD12_NEG_NOISE_CNT : 4; /*!< need_des */ + uint32_t : 9; + } bit; + } STATUS_12; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IM uint32_t PAD13_DATA : 16; /*!< need_des */ + __IM uint32_t PAD13_DEBOUNCE_CNT : 3; /*!< need_des */ + __IM uint32_t PAD13_NEG_NOISE_CNT : 4; /*!< need_des */ + uint32_t : 9; + } bit; + } STATUS_13; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IM uint32_t PAD14_DATA : 16; /*!< need_des */ + __IM uint32_t PAD14_DEBOUNCE_CNT : 3; /*!< need_des */ + __IM uint32_t PAD14_NEG_NOISE_CNT : 4; /*!< need_des */ + uint32_t : 9; + } bit; + } STATUS_14; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IM uint32_t SLP_DATA : 16; /*!< need_des */ + __IM uint32_t SLP_DEBOUNCE_CNT : 3; /*!< need_des */ + __IM uint32_t SLP_NEG_NOISE_CNT : 4; /*!< need_des */ + uint32_t : 9; + } bit; + } STATUS_15; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IM uint32_t APPROACH_PAD2_CNT : 8; /*!< need_des */ + __IM uint32_t APPROACH_PAD1_CNT : 8; /*!< need_des */ + __IM uint32_t APPROACH_PAD0_CNT : 8; /*!< need_des */ + __IM uint32_t SLP_APPROACH_CNT : 8; /*!< need_des */ + } bit; + } STATUS_16; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IM uint32_t DCAP_LPF : 7; /*!< Reserved */ + __IM uint32_t DRES_LPF : 2; /*!< need_des */ + __IM uint32_t DRV_LS : 4; /*!< need_des */ + __IM uint32_t DRV_HS : 5; /*!< need_des */ + __IM uint32_t DBIAS : 5; /*!< need_des */ + __IM uint32_t RTC_FREQ_SCAN_CNT : 2; /*!< need_des */ + uint32_t : 7; + } bit; + } STATUS_17; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IM uint32_t PAD_INACTIVE_STATUS : 15; /*!< need_des */ + __IM uint32_t PAD_ACTIVE_STATUS : 15; /*!< need_des */ + uint32_t : 2; + } bit; + } CHN_TMP_STATUS; + __IM uint32_t RESERVED[40]; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t RTC_DATE : 28; /*!< need_des */ + uint32_t : 3; + __IOM uint32_t RTC_CLK_EN : 1; /*!< need_des */ + } bit; + } DATE; +} LP_TOUCH_Type; /*!< Size = 260 (0x104) */ + + + +/* =========================================================================================================================== */ +/* ================ LP_WDT ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Low-power Watchdog Timer (LP_WDT) + */ + +typedef struct { /*!< LP_WDT Structure */ + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t WDT_CHIP_RESET_WIDTH : 8; /*!< need_des */ + __IOM uint32_t WDT_CHIP_RESET_EN : 1; /*!< need_des */ + __IOM uint32_t WDT_PAUSE_IN_SLP : 1; /*!< need_des */ + __IOM uint32_t WDT_APPCPU_RESET_EN : 1; /*!< need_des */ + __IOM uint32_t WDT_PROCPU_RESET_EN : 1; /*!< need_des */ + __IOM uint32_t WDT_FLASHBOOT_MOD_EN : 1; /*!< need_des */ + __IOM uint32_t WDT_SYS_RESET_LENGTH : 3; /*!< need_des */ + __IOM uint32_t WDT_CPU_RESET_LENGTH : 3; /*!< need_des */ + __IOM uint32_t WDT_STG3 : 3; /*!< need_des */ + __IOM uint32_t WDT_STG2 : 3; /*!< need_des */ + __IOM uint32_t WDT_STG1 : 3; /*!< need_des */ + __IOM uint32_t WDT_STG0 : 3; /*!< need_des */ + __IOM uint32_t WDT_EN : 1; /*!< need_des */ + } bit; + } CONFIG0; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t WDT_STG0_HOLD : 32; /*!< need_des */ + } bit; + } CONFIG1; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t WDT_STG1_HOLD : 32; /*!< need_des */ + } bit; + } CONFIG2; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t WDT_STG2_HOLD : 32; /*!< need_des */ + } bit; + } CONFIG3; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t WDT_STG3_HOLD : 32; /*!< need_des */ + } bit; + } CONFIG4; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 31; + __OM uint32_t FEED : 1; /*!< need_des */ + } bit; + } FEED; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t WDT_WKEY : 32; /*!< need_des */ + } bit; + } WPROTECT; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IM uint32_t SWD_RESET_FLAG : 1; /*!< need_des */ + uint32_t : 17; + __IOM uint32_t SWD_AUTO_FEED_EN : 1; /*!< need_des */ + __OM uint32_t SWD_RST_FLAG_CLR : 1; /*!< need_des */ + __IOM uint32_t SWD_SIGNAL_WIDTH : 10; /*!< need_des */ + __IOM uint32_t SWD_DISABLE : 1; /*!< need_des */ + __OM uint32_t SWD_FEED : 1; /*!< need_des */ + } bit; + } SWD_CONFIG; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t SWD_WKEY : 32; /*!< need_des */ + } bit; + } SWD_WPROTECT; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 30; + __IOM uint32_t SUPER_WDT_INT_RAW : 1; /*!< need_des */ + __IOM uint32_t LP_WDT_INT_RAW : 1; /*!< need_des */ + } bit; + } INT_RAW; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 30; + __IM uint32_t SUPER_WDT_INT_ST : 1; /*!< need_des */ + __IM uint32_t LP_WDT_INT_ST : 1; /*!< need_des */ + } bit; + } INT_ST; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 30; + __IOM uint32_t SUPER_WDT_INT_ENA : 1; /*!< need_des */ + __IOM uint32_t LP_WDT_INT_ENA : 1; /*!< need_des */ + } bit; + } INT_ENA; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + uint32_t : 30; + __OM uint32_t SUPER_WDT_INT_CLR : 1; /*!< need_des */ + __OM uint32_t LP_WDT_INT_CLR : 1; /*!< need_des */ + } bit; + } INT_CLR; + __IM uint32_t RESERVED[242]; + + union { + __IOM uint32_t reg; /*!< need_des */ + + struct { + __IOM uint32_t LP_WDT_DATE : 31; /*!< need_des */ + __IOM uint32_t CLK_EN : 1; /*!< need_des */ + } bit; + } DATE; +} LP_WDT_Type; /*!< Size = 1024 (0x400) */ + + + +/* =========================================================================================================================== */ +/* ================ SDHOST ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief SD/MMC Host Controller (SDHOST) + */ + +typedef struct { /*!< SDHOST Structure */ + + union { + __IOM uint32_t reg; /*!< Control register */ + + struct { + __IOM uint32_t CONTROLLER_RESET : 1; /*!< To reset controller, firmware should set this bit. This bit + is auto-cleared after two AHB and two sdhost_cclk_in clock + cycles. */ + __IOM uint32_t FIFO_RESET : 1; /*!< To reset FIFO, firmware should set bit to 1. This bit is auto-cleared + after completion of reset operation.Note: FIFO pointers + will be out of reset after 2 cycles of system clocks in + addition to synchronization delay (2 cycles of card clock), + after the fifo_reset is cleared. */ + __IOM uint32_t DMA_RESET : 1; /*!< To reset DMA interface, firmware should set bit to 1. This bit + is auto-cleared after two AHB clocks. */ + uint32_t : 1; + __IOM uint32_t INT_ENABLE : 1; /*!< Global interrupt enable/disable bit. 0: Disable; 1: Enable. */ + uint32_t : 1; + __IOM uint32_t READ_WAIT : 1; /*!< For sending read-wait to SDIO cards. */ + __IOM uint32_t SEND_IRQ_RESPONSE : 1; /*!< Bit automatically clears once response is sent. To wait for + MMC card interrupts, host issues CMD40 and waits for interrupt + response from MMC card(s). In the meantime, if host wants + SD/MMC to exit waiting for interrupt state, it can set + this bit, at which time SD/MMC command state-machine sends + CMD40 response on bus and returns to idle state. */ + __IOM uint32_t ABORT_READ_DATA : 1; /*!< After a suspend-command is issued during a read-operation, software + polls the card to find when the suspend-event occurred. + Once the suspend-event has occurred, software sets the + bit which will reset the data state machine that is waiting + for the next block of data. This bit is automatically cleared + once the data state machine is reset to idle. */ + __IOM uint32_t SEND_CCSD : 1; /*!< When set, SD/MMC sends CCSD to the CE-ATA device. Software sets + this bit only if the current command is expecting CCS (that + is, RW_BLK), and if interrupts are enabled for the CE-ATA + device. Once the CCSD pattern is sent to the device, SD/MMC + automatically clears the SDHOST_SEND_CCSD bit. It also + sets the Command Done (CD) bit in the SDHOST_RINTSTS_REG + register, and generates an interrupt for the host, in case + the Command Done interrupt is not masked. NOTE: Once the + SDHOST_SEND_CCSD bit is set, it takes two card clock cycles + to drive the CCSD on the CMD line. Due to this, within + the boundary conditions the CCSD may be sent to the CE-ATA + device, even if the device has signalled CCS. */ + __IOM uint32_t SEND_AUTO_STOP_CCSD : 1; /*!< Always Set SDHOST_SEND_AUTO_STOP_CCSD and SDHOST_SEND_CCSD bits + together; SDHOST_SEND_AUTO_STOP_CCSD should not be set + independently of send_ccsd. When set, SD/MMC automatically + sends an internally-generated STOP command (CMD12) to the + CE-ATA device. After sending this internally-generated + STOP command, the Auto Command Done (ACD) bit in SDHOST_RINTSTS_REG + is set and an interrupt is generated for the host, in case + the ACD interrupt is not masked. After sending the Command + Completion Signal Disable (CCSD), SD/MMC automatically + clears the SDHOST_SEND_AUTO_STOP_CCSD bit. */ + __IOM uint32_t CEATA_DEVICE_INTERRUPT_STATUS : 1;/*!< Software should appropriately write to this bit after the power-on + reset or any other reset to the CE-ATA device. After reset, + the CE-ATA device's interrupt is usually disabled (nIEN + = 1). If the host enables the CE-ATA device's interrupt, + then software should set this bit. */ + uint32_t : 20; + } bit; + } CTRL; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t reg; /*!< Clock divider configuration register */ + + struct { + __IOM uint32_t CLK_DIVIDER0 : 8; /*!< Clock divider0 value. Clock divisor is 2*n, where n = 0 bypasses + the divider (divisor of 1). For example, a value of 1 means + divided by 2*1 = 2, a value of 0xFF means divided by 2*255 + = 510, and so on. */ + __IOM uint32_t CLK_DIVIDER1 : 8; /*!< Clock divider1 value. Clock divisor is 2*n, where n = 0 bypasses + the divider (divisor of 1). For example, a value of 1 means + divided by 2*1 = 2, a value of 0xFF means divided by 2*255 + = 510, and so on. */ + __IOM uint32_t CLK_DIVIDER2 : 8; /*!< Clock divider2 value. Clock divisor is 2*n, where n = 0 bypasses + the divider (divisor of 1). For example, a value of 1 means + divided by 2*1 = 2, a value of 0xFF means divided by 2*255 + = 510, and so on. */ + __IOM uint32_t CLK_DIVIDER3 : 8; /*!< Clock divider3 value. Clock divisor is 2*n, where n = 0 bypasses + the divider (divisor of 1). For example, a value of 1 means + divided by 2*1 = 2, a value of 0xFF means divided by 2*255 + = 510, and so on. */ + } bit; + } CLKDIV; + + union { + __IOM uint32_t reg; /*!< Clock source selection register */ + + struct { + __IOM uint32_t CLKSRC : 4; /*!< Clock divider source for two SD cards is supported. Each card + has two bits assigned to it. For example, bit[1:0] are + assigned for card 0, bit[3:2] are assigned for card 1. + Card 0 maps and internally routes clock divider[0:3] outputs + to cclk_out[1:0] pins, depending on bit value.00 : Clock + divider 0;01 : Clock divider 1;10 : Clock divider 2;11 + : Clock divider 3. */ + uint32_t : 28; + } bit; + } CLKSRC; + + union { + __IOM uint32_t reg; /*!< Clock enable register */ + + struct { + __IOM uint32_t CCLK_ENABLE : 2; /*!< Clock-enable control for two SD card clocks and one MMC card + clock is supported. One bit per card.0: Clock disabled;1: + Clock enabled. */ + uint32_t : 14; + __IOM uint32_t LP_ENABLE : 2; /*!< Disable clock when the card is in IDLE state. One bit per card.0: + clock disabled;1: clock enabled. */ + uint32_t : 14; + } bit; + } CLKENA; + + union { + __IOM uint32_t reg; /*!< Data and response timeout configuration register */ + + struct { + __IOM uint32_t RESPONSE_TIMEOUT : 8; /*!< Response timeout value. Value is specified in terms of number + of card output clocks, i.e., sdhost_cclk_out. */ + __IOM uint32_t DATA_TIMEOUT : 24; /*!< Value for card data read timeout. This value is also used for + data starvation by host timeout. The timeout counter is + started only after the card clock is stopped. This value + is specified in number of card output clocks, i.e. sdhost_cclk_out + of the selected card.NOTE: The software timer should be + used if the timeout value is in the order of 100 ms. In + this case, read data timeout interrupt needs to be disabled. */ + } bit; + } TMOUT; + + union { + __IOM uint32_t reg; /*!< Card bus width configuration register */ + + struct { + __IOM uint32_t CARD_WIDTH4 : 2; /*!< One bit per card indicates if card is 1-bit or 4-bit mode.0: + 1-bit mode;1: 4-bit mode.Bit[1:0] correspond to card[1:0] + respectively. */ + uint32_t : 14; + __IOM uint32_t CARD_WIDTH8 : 2; /*!< One bit per card indicates if card is in 8-bit mode.0: Non 8-bit + mode;1: 8-bit mode.Bit[17:16] correspond to card[1:0] respectively. */ + uint32_t : 14; + } bit; + } CTYPE; + + union { + __IOM uint32_t reg; /*!< Card data block size configuration register */ + + struct { + __IOM uint32_t BLOCK_SIZE : 16; /*!< Block size. */ + uint32_t : 16; + } bit; + } BLKSIZ; + + union { + __IOM uint32_t reg; /*!< Data transfer length configuration register */ + + struct { + __IOM uint32_t BYTE_COUNT : 32; /*!< Number of bytes to be transferred, should be an integral multiple + of Block Size for block transfers. For data transfers of + undefined byte lengths, byte count should be set to 0. + When byte count is set to 0, it is the responsibility of + host to explicitly send stop/abort command to terminate + data transfer. */ + } bit; + } BYTCNT; + + union { + __IOM uint32_t reg; /*!< SDIO interrupt mask register */ + + struct { + __IOM uint32_t INT_MASK : 16; /*!< These bits used to mask unwanted interrupts. A value of 0 masks + interrupt, and a value of 1 enables the interrupt.Bit 15 + (EBE): End-bit error/no CRC error;Bit 14 (ACD): Auto command + done;Bit 13 (SBE/BCI): Rx Start Bit Error;Bit 12 (HLE): + Hardware locked write error;Bit 11 (FRUN): FIFO underrun/overrun + error;Bit 10 (HTO): Data starvation-by-host timeout;Bit + 9 (DRTO): Data read timeout;Bit 8 (RTO): Response timeout; + Bit 7 (DCRC): Data CRC error; Bit 6 (RCRC): Response CRC + error; Bit 5 (RXDR): Receive FIFO data request; Bit 4 (TXDR): + Transmit FIFO data request; Bit 3 (DTO): Data transfer + over; Bit 2 (CD): Command done; Bit 1 (RE): Response error;Bit + 0 (CD): Card detect. */ + __IOM uint32_t SDIO_INT_MASK : 2; /*!< SDIO interrupt mask, one bit for each card. Bit[17:16] correspond + to card[15:0] respectively. When masked, SDIO interrupt + detection for that card is disabled. 0 masks an interrupt, + and 1 enables an interrupt. */ + uint32_t : 14; + } bit; + } INTMASK; + + union { + __IOM uint32_t reg; /*!< Command argument data register */ + + struct { + __IOM uint32_t CMDARG : 32; /*!< Value indicates command argument to be passed to the card. */ + } bit; + } CMDARG; + + union { + __IOM uint32_t reg; /*!< Command and boot configuration register */ + + struct { + __IOM uint32_t INDEX : 6; /*!< Command index. */ + __IOM uint32_t RESPONSE_EXPECT : 1; /*!< 0: No response expected from card; 1: Response expected from + card. */ + __IOM uint32_t RESPONSE_LENGTH : 1; /*!< 0: Short response expected from card; 1: Long response expected + from card. */ + __IOM uint32_t CHECK_RESPONSE_CRC : 1; /*!< 0: Do not check; 1: Check response CRC.Some of command responses + do not return valid CRC bits. Software should disable CRC + checks for those commands in order to disable CRC checking + by controller. */ + __IOM uint32_t DATA_EXPECTED : 1; /*!< 0: No data transfer expected; 1: Data transfer expected. */ + __IOM uint32_t READ_WRITE : 1; /*!< 0: Read from card; 1: Write to card.Don't care if no data is + expected from card. */ + __IOM uint32_t TRANSFER_MODE : 1; /*!< 0: Block data transfer command; 1: Stream data transfer command.Don't + care if no data expected. */ + __IOM uint32_t SEND_AUTO_STOP : 1; /*!< 0: No stop command is sent at the end of data transfer; 1: Send + stop command at the end of data transfer. */ + __IOM uint32_t WAIT_PRVDATA_COMPLETE : 1; /*!< 0: Send command at once, even if previous data transfer has + not completed; 1: Wait for previous data transfer to complete + before sending Command.The SDHOST_WAIT_PRVDATA_COMPLETE] + = 0 option is typically used to query status of card during + data transfer or to stop current data transfer. SDHOST_CARD_NUMBERr + should be same as in previous command. */ + __IOM uint32_t STOP_ABORT_CMD : 1; /*!< 0: Neither stop nor abort command can stop current data transfer. + If abort is sent to function-number currently selected + or not in data-transfer mode, then bit should be set to + 0; 1: Stop or abort command intended to stop current data + transfer in progress.When open-ended or predefined data + transfer is in progress, and host issues stop or abort + command to stop data transfer, bit should be set so that + command/data state-machines of CIU can return correctly + to idle state. */ + __IOM uint32_t SEND_INITIALIZATION : 1; /*!< 0: Do not send initialization sequence (80 clocks of 1) before + sending this command; 1: Send initialization sequence before + sending this command.After powered on, 80 clocks must be + sent to card for initialization before sending any commands + to card. Bit should be set while sending first command + to card so that controller will initialize clocks before + sending command to card. */ + __IOM uint32_t CARD_NUMBER : 5; /*!< Card number in use. Represents physical slot number of card + being accessed. In SD-only mode, up to two cards are supported. */ + __IOM uint32_t UPDATE_CLOCK_REGISTERS_ONLY : 1;/*!< 0: Normal command sequence; 1: Do not send commands, just update + clock register value into card clock domain.Following register + values are transferred into card clock domain: CLKDIV, + CLRSRC, and CLKENA.Changes card clocks (change frequency, + truncate off or on, and set low-frequency mode). This is + provided in order to change clock frequency or stop clock + without having to send command to cards. During normal + command sequence, when sdhost_update_clock_registers_only + = 0, following control registers are transferred from BIU + to CIU: CMD, CMDARG, TMOUT, CTYPE, BLKSIZ, and BYTCNT. + CIU uses new register values for new command sequence to + card(s). When bit is set, there are no Command Done interrupts + because no command is sent to SD_MMC_CEATA cards. */ + __IOM uint32_t READ_CEATA_DEVICE : 1; /*!< Read access flag.0: Host is not performing read access (RW_REG + or RW_BLK)towards CE-ATA device;1: Host is performing read + access (RW_REG or RW_BLK) towards CE-ATA device.Software + should set this bit to indicate that CE-ATA device is being + accessed for read transfer. This bit is used to disable + read data timeout indication while performing CE-ATA read + transfers. Maximum value of I/O transmission delay can + be no less than 10 seconds. SD/MMC should not indicate + read data timeout while waiting for data from CE-ATA device. */ + __IOM uint32_t CCS_EXPECTED : 1; /*!< Expected Command Completion Signal (CCS) configuration.0: Interrupts + are not enabled in CE-ATA device (nIEN = 1 in ATA control + register), or command does not expect CCS from device;1: + Interrupts are enabled in CE-ATA device (nIEN = 0), and + RW_BLK command expects command completion signal from CE-ATA + device. If the command expects Command Completion Signal + (CCS) from the CE-ATA device, the software should set this + control bit. SD/MMC sets Data Transfer Over (DTO) bit in + RINTSTS register and generates interrupt to host if Data + Transfer Over interrupt is not masked. */ + uint32_t : 5; + __IOM uint32_t USE_HOLE : 1; /*!< Use Hold Register.0: CMD and DATA sent to card bypassing HOLD + Register;1: CMD and DATA sent to card through the HOLD + Register. */ + uint32_t : 1; + __IOM uint32_t START_CMD : 1; /*!< Start command. Once command is served by the CIU, this bit is + automatically cleared. When this bit is set, host should + not attempt to write to any command registers. If a write + is attempted, hardware lock error is set in raw interrupt + register. Once command is sent and a response is received + from SD_MMC_CEATA cards, Command Done bit is set in the + raw interrupt Register. */ + } bit; + } CMD; + + union { + __IOM uint32_t reg; /*!< Response data register */ + + struct { + __IM uint32_t RESPONSE0 : 32; /*!< Bit[31:0] of response. */ + } bit; + } RESP0; + + union { + __IOM uint32_t reg; /*!< Long response data register */ + + struct { + __IM uint32_t RESPONSE1 : 32; /*!< Bit[63:32] of long response. */ + } bit; + } RESP1; + + union { + __IOM uint32_t reg; /*!< Long response data register */ + + struct { + __IM uint32_t RESPONSE2 : 32; /*!< Bit[95:64] of long response. */ + } bit; + } RESP2; + + union { + __IOM uint32_t reg; /*!< Long response data register */ + + struct { + __IM uint32_t RESPONSE3 : 32; /*!< Bit[127:96] of long response. */ + } bit; + } RESP3; + + union { + __IOM uint32_t reg; /*!< Masked interrupt status register */ + + struct { + __IM uint32_t INT_STATUS_MSK : 16; /*!< Interrupt enabled only if corresponding bit in interrupt mask + register is set.Bit 15 (EBE): End-bit error/no CRC error;Bit + 14 (ACD): Auto command done;Bit 13 (SBE/BCI): RX Start + Bit Error;Bit 12 (HLE): Hardware locked write error; Bit + 11 (FRUN): FIFO underrun/overrun error;Bit 10 (HTO): Data + starvation by host timeout (HTO);Bit 9 (DTRO): Data read + timeout; Bit 8 (RTO): Response timeout; Bit 7 (DCRC): Data + CRC error; Bit 6 (RCRC): Response CRC error; Bit 5 (RXDR): + Receive FIFO data request; Bit 4 (TXDR): Transmit FIFO + data request;Bit 3 (DTO): Data transfer over; Bit 2 (CD): + Command done; Bit 1 (RE): Response error;Bit 0 (CD): Card + detect. */ + __IM uint32_t SDIO_INTERRUPT_MSK : 2; /*!< Interrupt from SDIO card, one bit for each card. Bit[17:16] + correspond to card1 and card0, respectively. SDIO interrupt + for card is enabled only if corresponding sdhost_sdio_int_mask + bit is set in Interrupt mask register (Setting mask bit + enables interrupt). */ + uint32_t : 14; + } bit; + } MINTSTS; + + union { + __IOM uint32_t reg; /*!< Raw interrupt status register */ + + struct { + __IOM uint32_t INT_STATUS_RAW : 16; /*!< Setting a bit clears the corresponding interrupt and writing + 0 has no effect. Bits are logged regardless of interrupt + mask status.Bit 15 (EBE): End-bit error/no CRC error;Bit + 14 (ACD): Auto command done;Bit 13 (SBE/BCI): RX Start + Bit Error;Bit 12 (HLE): Hardware locked write error; Bit + 11 (FRUN): FIFO underrun/overrun error;Bit 10 (HTO): Data + starvation by host timeout (HTO);Bit 9 (DTRO): Data read + timeout; Bit 8 (RTO): Response timeout; Bit 7 (DCRC): Data + CRC error; Bit 6 (RCRC): Response CRC error; Bit 5 (RXDR): + Receive FIFO data request; Bit 4 (TXDR): Transmit FIFO + data request;Bit 3 (DTO): Data transfer over; Bit 2 (CD): + Command done; Bit 1 (RE): Response error;Bit 0 (CD): Card + detect. */ + __IOM uint32_t SDIO_INTERRUPT_RAW : 2; /*!< Interrupt from SDIO card, one bit for each card. Bit[17:16] + correspond to card1 and card0, respectively. Setting a + bit clears the corresponding interrupt bit and writing + 0 has no effect.0: No SDIO interrupt from card;1: SDIO + interrupt from card. */ + uint32_t : 14; + } bit; + } RINTSTS; + + union { + __IOM uint32_t reg; /*!< SD/MMC status register */ + + struct { + __IM uint32_t FIFO_RX_WATERMARK : 1; /*!< FIFO reached Receive watermark level, not qualified with data + transfer. */ + __IM uint32_t FIFO_TX_WATERMARK : 1; /*!< FIFO reached Transmit watermark level, not qualified with data + transfer. */ + __IM uint32_t FIFO_EMPTY : 1; /*!< FIFO is empty status. */ + __IM uint32_t FIFO_FULL : 1; /*!< FIFO is full status. */ + __IM uint32_t COMMAND_FSM_STATES : 4; /*!< Command FSM states.0: Idle;1: Send init sequence; 2: Send cmd + start bit; 3: Send cmd tx bit;4: Send cmd index + arg;5: + Send cmd crc7;6: Send cmd end bit;7: Receive resp start + bit;8: Receive resp IRQ response;9: Receive resp tx bit;10: + Receive resp cmd idx;11: Receive resp data;12: Receive + resp crc7;13: Receive resp end bit;14: Cmd path wait NCC;15: + Wait, cmd-to-response turnaround. */ + __IM uint32_t DATA_3_STATUS : 1; /*!< Raw selected sdhost_card_data[3], checks whether card is present.0: + card not present;1: card present. */ + __IM uint32_t DATA_BUSY : 1; /*!< Inverted version of raw selected sdhost_card_data[0].0: Card + data not busy;1: Card data busy. */ + __IM uint32_t DATA_STATE_MC_BUSY : 1; /*!< Data transmit or receive state-machine is busy. */ + __IM uint32_t RESPONSE_INDEX : 6; /*!< Index of previous response, including any auto-stop sent by + core. */ + __IM uint32_t FIFO_COUNT : 13; /*!< FIFO count, number of filled locations in FIFO. */ + uint32_t : 2; + } bit; + } STATUS; + + union { + __IOM uint32_t reg; /*!< FIFO configuration register */ + + struct { + __IOM uint32_t TX_WMARK : 12; /*!< FIFO threshold watermark level when transmitting data to card. + When FIFO data count is less than or equal to this number, + DMA/FIFO request is raised. If Interrupt is enabled, then + interrupt occurs. During end of packet, request or interrupt + is generated, regardless of threshold programming.In non-DMA + mode, when transmit FIFO threshold (TXDR) interrupt is + enabled, then interrupt is generated instead of DMA request. + During end of packet, on last interrupt, host is responsible + for filling FIFO with only required remaining bytes (not + before FIFO is full or after CIU completes data transfers, + because FIFO may not be empty). In DMA mode, at end of + packet, if last transfer is less than burst size, DMA controller + does single cycles until required bytes are transferred. */ + uint32_t : 4; + __IOM uint32_t RX_WMARK : 11; /*!< FIFO threshold watermark level when receiving data to card.When + FIFO data count reaches greater than this number , DMA/FIFO + request is raised. During end of packet, request is generated + regardless of threshold programming in order to complete + any remaining data.In non-DMA mode, when receiver FIFO + threshold (RXDR) interrupt is enabled, then interrupt is + generated instead of DMA request.During end of packet, + interrupt is not generated if threshold programming is + larger than any remaining data. It is responsibility of + host to read remaining bytes on seeing Data Transfer Done + interrupt.In DMA mode, at end of packet, even if remaining + bytes are less than threshold, DMA request does single + transfers to flush out any remaining bytes before Data + Transfer Done interrupt is set. */ + uint32_t : 1; + __IOM uint32_t DMA_MULTIPLE_TRANSACTION_SIZE : 3;/*!< Burst size of multiple transaction, should be programmed same + as DMA controller multiple-transaction-size SDHOST_SRC/DEST_MSIZE.000: + 1-byte transfer; 001: 4-byte transfer; 010: 8-byte transfer; + 011: 16-byte transfer; 100: 32-byte transfer; 101: 64-byte + transfer; 110: 128-byte transfer; 111: 256-byte transfer. */ + uint32_t : 1; + } bit; + } FIFOTH; + + union { + __IOM uint32_t reg; /*!< Card detect register */ + + struct { + __IM uint32_t CARD_DETECT_N : 2; /*!< Value on sdhost_card_detect_n input ports (1 bit per card), + read-only bits. 0 represents presence of card. Only NUM_CARDS + number of bits are implemented. */ + uint32_t : 30; + } bit; + } CDETECT; + + union { + __IOM uint32_t reg; /*!< Card write protection (WP) status register */ + + struct { + __IM uint32_t WRITE_PROTECT : 2; /*!< Value on sdhost_card_write_prt input ports (1 bit per card). + 1 represents write protection. Only NUM_CARDS number of + bits are implemented. */ + uint32_t : 30; + } bit; + } WRTPRT; + __IM uint32_t RESERVED1; + + union { + __IOM uint32_t reg; /*!< Transferred byte count register */ + + struct { + __IM uint32_t TCBCNT : 32; /*!< Number of bytes transferred by CIU unit to card. */ + } bit; + } TCBCNT; + + union { + __IOM uint32_t reg; /*!< Transferred byte count register */ + + struct { + __IM uint32_t TBBCNT : 32; /*!< Number of bytes transferred between Host/DMA memory and BIU + FIFO. */ + } bit; + } TBBCNT; + + union { + __IOM uint32_t reg; /*!< Debounce filter time configuration register */ + + struct { + __IOM uint32_t DEBOUNCE_COUNT : 24; /*!< Number of host clocks (clk) used by debounce filter logic. The + typical debounce time is 5 \verb+~+ 25 ms to prevent the + card instability when the card is inserted or removed. */ + uint32_t : 8; + } bit; + } DEBNCE; + + union { + __IOM uint32_t reg; /*!< User ID (scratchpad) register */ + + struct { + __IOM uint32_t USRID : 32; /*!< User identification register, value set by user. Can also be + used as a scratchpad register by user. */ + } bit; + } USRID; + + union { + __IOM uint32_t reg; /*!< Version ID (scratchpad) register */ + + struct { + __IM uint32_t VERSIONID : 32; /*!< Hardware version register. Can also be read by fireware. */ + } bit; + } VERID; + + union { + __IOM uint32_t reg; /*!< Hardware feature register */ + + struct { + __IM uint32_t CARD_TYPE : 1; /*!< Hardware support SDIO and MMC. */ + __IM uint32_t CARD_NUM : 5; /*!< Support card number is 2. */ + __IM uint32_t BUS_TYPE : 1; /*!< Register config is APB bus. */ + __IM uint32_t DATA_WIDTH : 3; /*!< Regisger data widht is 32. */ + __IM uint32_t ADDR_WIDTH : 6; /*!< Register address width is 32. */ + uint32_t : 2; + __IM uint32_t DMA_WIDTH : 3; /*!< DMA data witdth is 32. */ + __IM uint32_t RAM_INDISE : 1; /*!< Inside RAM in SDMMC module. */ + __IM uint32_t HOLD : 1; /*!< Have a hold regiser in data path . */ + uint32_t : 1; + __IM uint32_t NUM_CLK_DIV : 2; /*!< Have 4 clk divider in design . */ + uint32_t : 6; + } bit; + } HCON; + + union { + __IOM uint32_t reg; /*!< UHS-1 register */ + + struct { + uint32_t : 16; + __IOM uint32_t DDR : 2; /*!< DDR mode selecton,1 bit for each card.0-Non-DDR mdoe.1-DDR mdoe. */ + uint32_t : 14; + } bit; + } UHS; + + union { + __IOM uint32_t reg; /*!< Card reset register */ + + struct { + __IOM uint32_t CARD_RESET : 2; /*!< Hardware reset.1: Active mode; 0: Reset. These bits cause the + cards to enter pre-idle state, which requires them to be + re-initialized. SDHOST_RST_CARD_RESET[0] should be set + to 1'b0 to reset card0, SDHOST_RST_CARD_RESET[1] should + be set to 1'b0 to reset card1. */ + uint32_t : 30; + } bit; + } RST_N; + __IM uint32_t RESERVED2; + + union { + __IOM uint32_t reg; /*!< Burst mode transfer configuration register */ + + struct { + __IOM uint32_t SWR : 1; /*!< Software Reset. When set, the DMA Controller resets all its + internal registers. It is automatically cleared after one + clock cycle. */ + __IOM uint32_t FB : 1; /*!< Fixed Burst. Controls whether the AHB Master interface performs + fixed burst transfers or not. When set, the AHB will use + only SINGLE, INCR4, INCR8 or INCR16 during start of normal + burst transfers. When reset, the AHB will use SINGLE and + INCR burst transfer operations. */ + uint32_t : 5; + __IOM uint32_t DE : 1; /*!< IDMAC Enable. When set, the IDMAC is enabled. */ + __IOM uint32_t PBL : 3; /*!< Programmable Burst Length. These bits indicate the maximum number + of beats to be performed in one IDMAC???Internal DMA Control???transactio + . The IDMAC will always attempt to burst as specified in + PBL each time it starts a burst transfer on the host bus. + The permissible values are 1, 4, 8, 16, 32, 64, 128 and + 256. This value is the mirror of MSIZE of FIFOTH register. + In order to change this value, write the required value + to FIFOTH register. This is an encode value as follows:000: + 1-byte transfer; 001: 4-byte transfer; 010: 8-byte transfer; + 011: 16-byte transfer; 100: 32-byte transfer; 101: 64-byte + transfer; 110: 128-byte transfer; 111: 256-byte transfer.PBL + is a read-only value and is applicable only for data access, + it does not apply to descriptor access. */ + uint32_t : 21; + } bit; + } BMOD; + + union { + __IOM uint32_t reg; /*!< Poll demand configuration register */ + + struct { + __OM uint32_t PD : 32; /*!< Poll Demand. If the OWNER bit of a descriptor is not set, the + FSM goes to the Suspend state. The host needs to write + any value into this register for the IDMAC FSM to resume + normal descriptor fetch operation. This is a write only + . */ + } bit; + } PLDMND; + + union { + __IOM uint32_t reg; /*!< Descriptor base address register */ + + struct { + __IOM uint32_t DBADDR : 32; /*!< Start of Descriptor List. Contains the base address of the First + Descriptor. The LSB bits [1:0] are ignored and taken as + all-zero by the IDMAC internally. Hence these LSB bits + may be treated as read-only. */ + } bit; + } DBADDR; + + union { + __IOM uint32_t reg; /*!< IDMAC status register */ + + struct { + __IOM uint32_t TI : 1; /*!< Transmit Interrupt. Indicates that data transmission is finished + for a descriptor. Writing 1 clears this bit. */ + __IOM uint32_t RI : 1; /*!< Receive Interrupt. Indicates the completion of data reception + for a descriptor. Writing 1 clears this bit. */ + __IOM uint32_t FBE : 1; /*!< Fatal Bus Error Interrupt. Indicates that a Bus Error occurred + (IDSTS[12:10]) . When this bit is set, the DMA disables + all its bus accesses. Writing 1 clears this bit. */ + uint32_t : 1; + __IOM uint32_t DU : 1; /*!< Descriptor Unavailable Interrupt. This bit is set when the descriptor + is unavailable due to OWNER bit = 0 (DES0[31] = 0). Writing + 1 clears this bit. */ + __IOM uint32_t CES : 1; /*!< Card Error Summary. Indicates the status of the transaction + to/from the card, also present in RINTSTS. Indicates the + logical OR of the following bits:EBE : End Bit Error; RTO + : Response Timeout/Boot Ack Timeout; RCRC : Response CRC; + SBE : Start Bit Error; DRTO : Data Read Timeout/BDS timeout; + DCRC : Data CRC for Receive; RE : Response Error.Writing + 1 clears this bit. The abort condition of the IDMAC depends + on the setting of this CES bit. If the CES bit is enabled, + then the IDMAC aborts on a response error. */ + uint32_t : 2; + __IOM uint32_t NIS : 1; /*!< Normal Interrupt Summary. Logical OR of the following: IDSTS[0] + : Transmit Interrupt, IDSTS[1] : Receive Interrupt. Only + unmasked bits affect this bit. This is a sticky bit and + must be cleared each time a corresponding bit that causes + NIS to be set is cleared. Writing 1 clears this bit. */ + __IOM uint32_t AIS : 1; /*!< Abnormal Interrupt Summary. Logical OR of the following: IDSTS[2] + : Fatal Bus Interrupt, IDSTS[4] : DU bit Interrupt. Only + unmasked bits affect this bit. This is a sticky bit and + must be cleared each time a corresponding bit that causes + AIS to be set is cleared. Writing 1 clears this bit. */ + __IOM uint32_t FBE_CODE : 3; /*!< Fatal Bus Error Code. Indicates the type of error that caused + a Bus Error. Valid only when the Fatal Bus Error bit IDSTS[2] + is set. This field does not generate an interrupt.001: + Host Abort received during transmission;010: Host Abort + received during reception;Others: Reserved. */ + __IOM uint32_t FSM : 4; /*!< DMAC FSM present state.0: DMA_IDLE (idle state); 1: DMA_SUSPEND + (suspend state); 2: DESC_RD (descriptor reading state); + 3: DESC_CHK (descriptor checking state); 4: DMA_RD_REQ_WAIT + (read-data request waiting state);5: DMA_WR_REQ_WAIT (write-data + request waiting state); 6: DMA_RD (data-read state); 7: + DMA_WR (data-write state); 8: DESC_CLOSE (descriptor close + state). */ + uint32_t : 15; + } bit; + } IDSTS; + + union { + __IOM uint32_t reg; /*!< IDMAC interrupt enable register */ + + struct { + __IOM uint32_t TI : 1; /*!< Transmit Interrupt Enable. When set with Normal Interrupt Summary + Enable, Transmit Interrupt is enabled. When reset, Transmit + Interrupt is disabled. */ + __IOM uint32_t RI : 1; /*!< Receive Interrupt Enable. When set with Normal Interrupt Summary + Enable, Receive Interrupt is enabled. When reset, Receive + Interrupt is disabled. */ + __IOM uint32_t FBE : 1; /*!< Fatal Bus Error Enable. When set with Abnormal Interrupt Summary + Enable, the Fatal Bus Error Interrupt is enabled. When + reset, Fatal Bus Error Enable Interrupt is disabled. */ + uint32_t : 1; + __IOM uint32_t DU : 1; /*!< Descriptor Unavailable Interrupt. When set along with Abnormal + Interrupt Summary Enable, the DU interrupt is enabled. */ + __IOM uint32_t CES : 1; /*!< Card Error summary Interrupt Enable. When set, it enables the + Card Interrupt summary. */ + uint32_t : 2; + __IOM uint32_t NI : 1; /*!< Normal Interrupt Summary Enable. When set, a normal interrupt + is enabled. When reset, a normal interrupt is disabled. + This bit enables the following bits:IDINTEN[0]: Transmit + Interrupt;IDINTEN[1]: Receive Interrupt. */ + __IOM uint32_t AI : 1; /*!< Abnormal Interrupt Summary Enable. When set, an abnormal interrupt + is enabled. This bit enables the following bits:IDINTEN[2]: + Fatal Bus Error Interrupt;IDINTEN[4]: DU Interrupt. */ + uint32_t : 22; + } bit; + } IDINTEN; + + union { + __IOM uint32_t reg; /*!< Host descriptor address pointer */ + + struct { + __IM uint32_t DSCADDR : 32; /*!< Host Descriptor Address Pointer, updated by IDMAC during operation + and cleared on reset. This register points to the start + address of the current descriptor read by the IDMAC. */ + } bit; + } DSCADDR; + + union { + __IOM uint32_t reg; /*!< Host buffer address pointer register */ + + struct { + __IM uint32_t BUFADDR : 32; /*!< Host Buffer Address Pointer, updated by IDMAC during operation + and cleared on reset. This register points to the current + Data Buffer Address being accessed by the IDMAC. */ + } bit; + } BUFADDR; + __IM uint32_t RESERVED3[25]; + + union { + __IOM uint32_t reg; /*!< Card Threshold Control register */ + + struct { + __IOM uint32_t CARDRDTHREN : 1; /*!< Card read threshold enable.1'b0-Card read threshold disabled.1'b1-Card + read threshold enabled. */ + __IOM uint32_t CARDCLRINTEN : 1; /*!< Busy clear interrupt generation:1'b0-Busy clear interrypt disabled.1'b1-Busy + clear interrypt enabled. */ + __IOM uint32_t CARDWRTHREN : 1; /*!< Applicable when HS400 mode is enabled.1'b0-Card write Threshold + disabled.1'b1-Card write Threshold enabled. */ + uint32_t : 13; + __IOM uint32_t CARDTHRESHOLD : 16; /*!< The inside FIFO size is 512,This register is applicable when + SDHOST_CARDERTHREN_REG is set to 1 or SDHOST_CARDRDTHREN_REG + set to 1. */ + } bit; + } CARDTHRCTL; + __IM uint32_t RESERVED4[2]; + + union { + __IOM uint32_t reg; /*!< eMMC DDR register */ + + struct { + __IOM uint32_t HALFSTARTBIT : 2; /*!< Control for start bit detection mechanism duration of start + bit.Each bit refers to one slot.Set this bit to 1 for eMMC4.5 + and above,set to 0 for SD applications.For eMMC4.5,start + bit can be:1'b0-Full cycle.1'b1-less than one full cycle. */ + uint32_t : 29; + __IOM uint32_t HS400_MODE : 1; /*!< Set 1 to enable HS400 mode. */ + } bit; + } EMMCDDR; + + union { + __IOM uint32_t reg; /*!< Enable Phase Shift register */ + + struct { + __IOM uint32_t ENABLE_SHIFT : 4; /*!< Control for the amount of phase shift provided on the default + enables in the design.Two bits assigned for each card.2'b00-Default + phase shift.2'b01-Enables shifted to next immediate positive + edge.2'b10-Enables shifted to next immediate negative edge.2'b11-Reserved + */ + uint32_t : 28; + } bit; + } ENSHIFT; + __IM uint32_t RESERVED5[59]; + + union { + __IOM uint32_t reg; /*!< CPU write and read transmit data by FIFO */ + + struct { + __IOM uint32_t BUFFIFO : 32; /*!< CPU write and read transmit data by FIFO. This register points + to the current Data FIFO . */ + } bit; + } BUFFIFO; + __IM uint32_t RESERVED6[383]; + + union { + __IOM uint32_t reg; /*!< SDIO control register. */ + + struct { + __IOM uint32_t CCLKIN_EDGE_DRV_SEL : 3; /*!< It's used to select the clock phase of the output signal from + phase 0, phase 90, phase 180, phase 270. */ + __IOM uint32_t CCLKIN_EDGE_SAM_SEL : 3; /*!< It's used to select the clock phase of the input signal from + phase 0, phase 90, phase 180, phase 270. */ + __IOM uint32_t CCLKIN_EDGE_SLF_SEL : 3; /*!< It's used to select the clock phase of the internal signal from + phase 0, phase 90, phase 180, phase 270. */ + __IOM uint32_t CCLLKIN_EDGE_H : 4; /*!< The high level of the divider clock. The value should be smaller + than CCLKIN_EDGE_L. */ + __IOM uint32_t CCLLKIN_EDGE_L : 4; /*!< The low level of the divider clock. The value should be larger + than CCLKIN_EDGE_H. */ + __IOM uint32_t CCLLKIN_EDGE_N : 4; /*!< The clock division of cclk_in. */ + __IOM uint32_t ESDIO_MODE : 1; /*!< Enable esdio mode. */ + __IOM uint32_t ESD_MODE : 1; /*!< Enable esd mode. */ + __IOM uint32_t CCLK_EN : 1; /*!< Sdio clock enable. */ + __IOM uint32_t ULTRA_HIGH_SPEED_MODE : 1; /*!< Enable ultra high speed mode, use dll to generate clk. */ + uint32_t : 7; + } bit; + } CLK_EDGE_SEL; + + union { + __IOM uint32_t reg; /*!< SDIO raw ints register. */ + + struct { + __IM uint32_t RAW_INTS : 32; /*!< It indicates raw ints. */ + } bit; + } RAW_INTS; + + union { + __IOM uint32_t reg; /*!< SDIO DLL clock control register. */ + + struct { + __IOM uint32_t DLL_CCLK_IN_SLF_EN : 1; /*!< Clock enable of cclk_in_slf when ULTRA_HIGH_SPEED_MODE==1. */ + __IOM uint32_t DLL_CCLK_IN_DRV_EN : 1; /*!< Clock enable of cclk_in_drv when ULTRA_HIGH_SPEED_MODE==1. */ + __IOM uint32_t DLL_CCLK_IN_SAM_EN : 1; /*!< Clock enable of cclk_in_sam when ULTRA_HIGH_SPEED_MODE==1. */ + __IOM uint32_t DLL_CCLK_IN_SLF_PHASE : 6; /*!< It's used to control the phase of cclk_in_slf when ULTRA_HIGH_SPEED_MODE==1. */ + __IOM uint32_t DLL_CCLK_IN_DRV_PHASE : 6; /*!< It's used to control the phase of cclk_in_drv when ULTRA_HIGH_SPEED_MODE==1. */ + __IOM uint32_t DLL_CCLK_IN_SAM_PHASE : 6; /*!< It's used to control the phase of cclk_in_sam when ULTRA_HIGH_SPEED_MODE==1. */ + uint32_t : 11; + } bit; + } DLL_CLK_CONF; + + union { + __IOM uint32_t reg; /*!< SDIO DLL configuration register. */ + + struct { + __IOM uint32_t DLL_CAL_STOP : 1; /*!< Set 1 to stop calibration. */ + __IM uint32_t DLL_CAL_END : 1; /*!< 1 means calibration finished. */ + uint32_t : 30; + } bit; + } DLL_CONF; +} SDHOST_Type; /*!< Size = 2064 (0x810) */ + + + +/* =========================================================================================================================== */ +/* ================ SHA ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief SHA (Secure Hash Algorithm) Accelerator (SHA) + */ + +typedef struct { /*!< SHA Structure */ + + union { + __IOM uint32_t reg; /*!< Initial configuration register. */ + + struct { + __IOM uint32_t MODE : 3; /*!< Sha mode. */ + uint32_t : 29; + } bit; + } MODE; + + union { + __IOM uint32_t reg; /*!< SHA 512/t configuration register 0. */ + + struct { + __IOM uint32_t T_STRING : 32; /*!< Sha t_string (used if and only if mode == SHA_512/t). */ + } bit; + } T_STRING; + + union { + __IOM uint32_t reg; /*!< SHA 512/t configuration register 1. */ + + struct { + __IOM uint32_t T_LENGTH : 6; /*!< Sha t_length (used if and only if mode == SHA_512/t). */ + uint32_t : 26; + } bit; + } T_LENGTH; + + union { + __IOM uint32_t reg; /*!< DMA configuration register 0. */ + + struct { + __IOM uint32_t DMA_BLOCK_NUM : 6; /*!< Dma-sha block number. */ + uint32_t : 26; + } bit; + } DMA_BLOCK_NUM; + + union { + __IOM uint32_t reg; /*!< Typical SHA configuration register 0. */ + + struct { + uint32_t : 1; + __IM uint32_t START : 31; /*!< Reserved. */ + } bit; + } START; + + union { + __IOM uint32_t reg; /*!< Typical SHA configuration register 1. */ + + struct { + uint32_t : 1; + __IM uint32_t CONTINUE : 31; /*!< Reserved. */ + } bit; + } CONTINUE; + + union { + __IOM uint32_t reg; /*!< Busy register. */ + + struct { + __IM uint32_t STATE : 1; /*!< Sha busy state. 1'b0: idle. 1'b1: busy. */ + uint32_t : 31; + } bit; + } BUSY; + + union { + __IOM uint32_t reg; /*!< DMA configuration register 1. */ + + struct { + __OM uint32_t DMA_START : 1; /*!< Start dma-sha. */ + uint32_t : 31; + } bit; + } DMA_START; + + union { + __IOM uint32_t reg; /*!< DMA configuration register 2. */ + + struct { + __OM uint32_t DMA_CONTINUE : 1; /*!< Continue dma-sha. */ + uint32_t : 31; + } bit; + } DMA_CONTINUE; + + union { + __IOM uint32_t reg; /*!< Interrupt clear register. */ + + struct { + __OM uint32_t CLEAR_INTERRUPT : 1; /*!< Clear sha interrupt. */ + uint32_t : 31; + } bit; + } CLEAR_IRQ; + + union { + __IOM uint32_t reg; /*!< Interrupt enable register. */ + + struct { + __IOM uint32_t INTERRUPT_ENA : 1; /*!< Sha interrupt enable register. 1'b0: disable(default). 1'b1: + enable. */ + uint32_t : 31; + } bit; + } IRQ_ENA; + + union { + __IOM uint32_t reg; /*!< Date register. */ + + struct { + __IOM uint32_t DATE : 30; /*!< Sha date information/ sha version information. */ + uint32_t : 2; + } bit; + } DATE; + __IM uint32_t RESERVED[4]; + __IOM uint32_t H_MEM[16]; /*!< Sha H memory which contains intermediate hash or finial hash. */ + __IOM uint32_t M_MEM[16]; /*!< Sha M memory which contains message. */ +} SHA_Type; /*!< Size = 192 (0xc0) */ + + + +/* =========================================================================================================================== */ +/* ================ SOC_ETM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Event Task Matrix (SOC_ETM) + */ + +typedef struct { /*!< SOC_ETM Structure */ + + union { + __IOM uint32_t reg; /*!< Channel enable status register */ + + struct { + __IOM uint32_t CH_ENA0 : 1; /*!< Represents ch0 enable status.\\0: Disable\\1: Enable */ + __IOM uint32_t CH_ENA1 : 1; /*!< Represents ch1 enable status.\\0: Disable\\1: Enable */ + __IOM uint32_t CH_ENA2 : 1; /*!< Represents ch2 enable status.\\0: Disable\\1: Enable */ + __IOM uint32_t CH_ENA3 : 1; /*!< Represents ch3 enable status.\\0: Disable\\1: Enable */ + __IOM uint32_t CH_ENA4 : 1; /*!< Represents ch4 enable status.\\0: Disable\\1: Enable */ + __IOM uint32_t CH_ENA5 : 1; /*!< Represents ch5 enable status.\\0: Disable\\1: Enable */ + __IOM uint32_t CH_ENA6 : 1; /*!< Represents ch6 enable status.\\0: Disable\\1: Enable */ + __IOM uint32_t CH_ENA7 : 1; /*!< Represents ch7 enable status.\\0: Disable\\1: Enable */ + __IOM uint32_t CH_ENA8 : 1; /*!< Represents ch8 enable status.\\0: Disable\\1: Enable */ + __IOM uint32_t CH_ENA9 : 1; /*!< Represents ch9 enable status.\\0: Disable\\1: Enable */ + __IOM uint32_t CH_ENA10 : 1; /*!< Represents ch10 enable status.\\0: Disable\\1: Enable */ + __IOM uint32_t CH_ENA11 : 1; /*!< Represents ch11 enable status.\\0: Disable\\1: Enable */ + __IOM uint32_t CH_ENA12 : 1; /*!< Represents ch12 enable status.\\0: Disable\\1: Enable */ + __IOM uint32_t CH_ENA13 : 1; /*!< Represents ch13 enable status.\\0: Disable\\1: Enable */ + __IOM uint32_t CH_ENA14 : 1; /*!< Represents ch14 enable status.\\0: Disable\\1: Enable */ + __IOM uint32_t CH_ENA15 : 1; /*!< Represents ch15 enable status.\\0: Disable\\1: Enable */ + __IOM uint32_t CH_ENA16 : 1; /*!< Represents ch16 enable status.\\0: Disable\\1: Enable */ + __IOM uint32_t CH_ENA17 : 1; /*!< Represents ch17 enable status.\\0: Disable\\1: Enable */ + __IOM uint32_t CH_ENA18 : 1; /*!< Represents ch18 enable status.\\0: Disable\\1: Enable */ + __IOM uint32_t CH_ENA19 : 1; /*!< Represents ch19 enable status.\\0: Disable\\1: Enable */ + __IOM uint32_t CH_ENA20 : 1; /*!< Represents ch20 enable status.\\0: Disable\\1: Enable */ + __IOM uint32_t CH_ENA21 : 1; /*!< Represents ch21 enable status.\\0: Disable\\1: Enable */ + __IOM uint32_t CH_ENA22 : 1; /*!< Represents ch22 enable status.\\0: Disable\\1: Enable */ + __IOM uint32_t CH_ENA23 : 1; /*!< Represents ch23 enable status.\\0: Disable\\1: Enable */ + __IOM uint32_t CH_ENA24 : 1; /*!< Represents ch24 enable status.\\0: Disable\\1: Enable */ + __IOM uint32_t CH_ENA25 : 1; /*!< Represents ch25 enable status.\\0: Disable\\1: Enable */ + __IOM uint32_t CH_ENA26 : 1; /*!< Represents ch26 enable status.\\0: Disable\\1: Enable */ + __IOM uint32_t CH_ENA27 : 1; /*!< Represents ch27 enable status.\\0: Disable\\1: Enable */ + __IOM uint32_t CH_ENA28 : 1; /*!< Represents ch28 enable status.\\0: Disable\\1: Enable */ + __IOM uint32_t CH_ENA29 : 1; /*!< Represents ch29 enable status.\\0: Disable\\1: Enable */ + __IOM uint32_t CH_ENA30 : 1; /*!< Represents ch30 enable status.\\0: Disable\\1: Enable */ + __IOM uint32_t CH_ENA31 : 1; /*!< Represents ch31 enable status.\\0: Disable\\1: Enable */ + } bit; + } CH_ENA_AD0; + + union { + __IOM uint32_t reg; /*!< Channel enable set register */ + + struct { + __OM uint32_t CH_SET0 : 1; /*!< Configures whether or not to enable ch0.\\0: Invalid, No effect\\1: + Enable */ + __OM uint32_t CH_SET1 : 1; /*!< Configures whether or not to enable ch1.\\0: Invalid, No effect\\1: + Enable */ + __OM uint32_t CH_SET2 : 1; /*!< Configures whether or not to enable ch2.\\0: Invalid, No effect\\1: + Enable */ + __OM uint32_t CH_SET3 : 1; /*!< Configures whether or not to enable ch3.\\0: Invalid, No effect\\1: + Enable */ + __OM uint32_t CH_SET4 : 1; /*!< Configures whether or not to enable ch4.\\0: Invalid, No effect\\1: + Enable */ + __OM uint32_t CH_SET5 : 1; /*!< Configures whether or not to enable ch5.\\0: Invalid, No effect\\1: + Enable */ + __OM uint32_t CH_SET6 : 1; /*!< Configures whether or not to enable ch6.\\0: Invalid, No effect\\1: + Enable */ + __OM uint32_t CH_SET7 : 1; /*!< Configures whether or not to enable ch7.\\0: Invalid, No effect\\1: + Enable */ + __OM uint32_t CH_SET8 : 1; /*!< Configures whether or not to enable ch8.\\0: Invalid, No effect\\1: + Enable */ + __OM uint32_t CH_SET9 : 1; /*!< Configures whether or not to enable ch9.\\0: Invalid, No effect\\1: + Enable */ + __OM uint32_t CH_SET10 : 1; /*!< Configures whether or not to enable ch10.\\0: Invalid, No effect\\1: + Enable */ + __OM uint32_t CH_SET11 : 1; /*!< Configures whether or not to enable ch11.\\0: Invalid, No effect\\1: + Enable */ + __OM uint32_t CH_SET12 : 1; /*!< Configures whether or not to enable ch12.\\0: Invalid, No effect\\1: + Enable */ + __OM uint32_t CH_SET13 : 1; /*!< Configures whether or not to enable ch13.\\0: Invalid, No effect\\1: + Enable */ + __OM uint32_t CH_SET14 : 1; /*!< Configures whether or not to enable ch14.\\0: Invalid, No effect\\1: + Enable */ + __OM uint32_t CH_SET15 : 1; /*!< Configures whether or not to enable ch15.\\0: Invalid, No effect\\1: + Enable */ + __OM uint32_t CH_SET16 : 1; /*!< Configures whether or not to enable ch16.\\0: Invalid, No effect\\1: + Enable */ + __OM uint32_t CH_SET17 : 1; /*!< Configures whether or not to enable ch17.\\0: Invalid, No effect\\1: + Enable */ + __OM uint32_t CH_SET18 : 1; /*!< Configures whether or not to enable ch18.\\0: Invalid, No effect\\1: + Enable */ + __OM uint32_t CH_SET19 : 1; /*!< Configures whether or not to enable ch19.\\0: Invalid, No effect\\1: + Enable */ + __OM uint32_t CH_SET20 : 1; /*!< Configures whether or not to enable ch20.\\0: Invalid, No effect\\1: + Enable */ + __OM uint32_t CH_SET21 : 1; /*!< Configures whether or not to enable ch21.\\0: Invalid, No effect\\1: + Enable */ + __OM uint32_t CH_SET22 : 1; /*!< Configures whether or not to enable ch22.\\0: Invalid, No effect\\1: + Enable */ + __OM uint32_t CH_SET23 : 1; /*!< Configures whether or not to enable ch23.\\0: Invalid, No effect\\1: + Enable */ + __OM uint32_t CH_SET24 : 1; /*!< Configures whether or not to enable ch24.\\0: Invalid, No effect\\1: + Enable */ + __OM uint32_t CH_SET25 : 1; /*!< Configures whether or not to enable ch25.\\0: Invalid, No effect\\1: + Enable */ + __OM uint32_t CH_SET26 : 1; /*!< Configures whether or not to enable ch26.\\0: Invalid, No effect\\1: + Enable */ + __OM uint32_t CH_SET27 : 1; /*!< Configures whether or not to enable ch27.\\0: Invalid, No effect\\1: + Enable */ + __OM uint32_t CH_SET28 : 1; /*!< Configures whether or not to enable ch28.\\0: Invalid, No effect\\1: + Enable */ + __OM uint32_t CH_SET29 : 1; /*!< Configures whether or not to enable ch29.\\0: Invalid, No effect\\1: + Enable */ + __OM uint32_t CH_SET30 : 1; /*!< Configures whether or not to enable ch30.\\0: Invalid, No effect\\1: + Enable */ + __OM uint32_t CH_SET31 : 1; /*!< Configures whether or not to enable ch31.\\0: Invalid, No effect\\1: + Enable */ + } bit; + } CH_ENA_AD0_SET; + + union { + __IOM uint32_t reg; /*!< Channel enable clear register */ + + struct { + __OM uint32_t CH_CLR0 : 1; /*!< Configures whether or not to clear ch0 enable.\\0: Invalid, + No effect\\1: Clear */ + __OM uint32_t CH_CLR1 : 1; /*!< Configures whether or not to clear ch1 enable.\\0: Invalid, + No effect\\1: Clear */ + __OM uint32_t CH_CLR2 : 1; /*!< Configures whether or not to clear ch2 enable.\\0: Invalid, + No effect\\1: Clear */ + __OM uint32_t CH_CLR3 : 1; /*!< Configures whether or not to clear ch3 enable.\\0: Invalid, + No effect\\1: Clear */ + __OM uint32_t CH_CLR4 : 1; /*!< Configures whether or not to clear ch4 enable.\\0: Invalid, + No effect\\1: Clear */ + __OM uint32_t CH_CLR5 : 1; /*!< Configures whether or not to clear ch5 enable.\\0: Invalid, + No effect\\1: Clear */ + __OM uint32_t CH_CLR6 : 1; /*!< Configures whether or not to clear ch6 enable.\\0: Invalid, + No effect\\1: Clear */ + __OM uint32_t CH_CLR7 : 1; /*!< Configures whether or not to clear ch7 enable.\\0: Invalid, + No effect\\1: Clear */ + __OM uint32_t CH_CLR8 : 1; /*!< Configures whether or not to clear ch8 enable.\\0: Invalid, + No effect\\1: Clear */ + __OM uint32_t CH_CLR9 : 1; /*!< Configures whether or not to clear ch9 enable.\\0: Invalid, + No effect\\1: Clear */ + __OM uint32_t CH_CLR10 : 1; /*!< Configures whether or not to clear ch10 enable.\\0: Invalid, + No effect\\1: Clear */ + __OM uint32_t CH_CLR11 : 1; /*!< Configures whether or not to clear ch11 enable.\\0: Invalid, + No effect\\1: Clear */ + __OM uint32_t CH_CLR12 : 1; /*!< Configures whether or not to clear ch12 enable.\\0: Invalid, + No effect\\1: Clear */ + __OM uint32_t CH_CLR13 : 1; /*!< Configures whether or not to clear ch13 enable.\\0: Invalid, + No effect\\1: Clear */ + __OM uint32_t CH_CLR14 : 1; /*!< Configures whether or not to clear ch14 enable.\\0: Invalid, + No effect\\1: Clear */ + __OM uint32_t CH_CLR15 : 1; /*!< Configures whether or not to clear ch15 enable.\\0: Invalid, + No effect\\1: Clear */ + __OM uint32_t CH_CLR16 : 1; /*!< Configures whether or not to clear ch16 enable.\\0: Invalid, + No effect\\1: Clear */ + __OM uint32_t CH_CLR17 : 1; /*!< Configures whether or not to clear ch17 enable.\\0: Invalid, + No effect\\1: Clear */ + __OM uint32_t CH_CLR18 : 1; /*!< Configures whether or not to clear ch18 enable.\\0: Invalid, + No effect\\1: Clear */ + __OM uint32_t CH_CLR19 : 1; /*!< Configures whether or not to clear ch19 enable.\\0: Invalid, + No effect\\1: Clear */ + __OM uint32_t CH_CLR20 : 1; /*!< Configures whether or not to clear ch20 enable.\\0: Invalid, + No effect\\1: Clear */ + __OM uint32_t CH_CLR21 : 1; /*!< Configures whether or not to clear ch21 enable.\\0: Invalid, + No effect\\1: Clear */ + __OM uint32_t CH_CLR22 : 1; /*!< Configures whether or not to clear ch22 enable.\\0: Invalid, + No effect\\1: Clear */ + __OM uint32_t CH_CLR23 : 1; /*!< Configures whether or not to clear ch23 enable.\\0: Invalid, + No effect\\1: Clear */ + __OM uint32_t CH_CLR24 : 1; /*!< Configures whether or not to clear ch24 enable.\\0: Invalid, + No effect\\1: Clear */ + __OM uint32_t CH_CLR25 : 1; /*!< Configures whether or not to clear ch25 enable.\\0: Invalid, + No effect\\1: Clear */ + __OM uint32_t CH_CLR26 : 1; /*!< Configures whether or not to clear ch26 enable.\\0: Invalid, + No effect\\1: Clear */ + __OM uint32_t CH_CLR27 : 1; /*!< Configures whether or not to clear ch27 enable.\\0: Invalid, + No effect\\1: Clear */ + __OM uint32_t CH_CLR28 : 1; /*!< Configures whether or not to clear ch28 enable.\\0: Invalid, + No effect\\1: Clear */ + __OM uint32_t CH_CLR29 : 1; /*!< Configures whether or not to clear ch29 enable.\\0: Invalid, + No effect\\1: Clear */ + __OM uint32_t CH_CLR30 : 1; /*!< Configures whether or not to clear ch30 enable.\\0: Invalid, + No effect\\1: Clear */ + __OM uint32_t CH_CLR31 : 1; /*!< Configures whether or not to clear ch31 enable.\\0: Invalid, + No effect\\1: Clear */ + } bit; + } CH_ENA_AD0_CLR; + + union { + __IOM uint32_t reg; /*!< Channel enable status register */ + + struct { + __IOM uint32_t CH_ENA32 : 1; /*!< Represents ch32 enable status.\\0: Disable\\1: Enable */ + __IOM uint32_t CH_ENA33 : 1; /*!< Represents ch33 enable status.\\0: Disable\\1: Enable */ + __IOM uint32_t CH_ENA34 : 1; /*!< Represents ch34 enable status.\\0: Disable\\1: Enable */ + __IOM uint32_t CH_ENA35 : 1; /*!< Represents ch35 enable status.\\0: Disable\\1: Enable */ + __IOM uint32_t CH_ENA36 : 1; /*!< Represents ch36 enable status.\\0: Disable\\1: Enable */ + __IOM uint32_t CH_ENA37 : 1; /*!< Represents ch37 enable status.\\0: Disable\\1: Enable */ + __IOM uint32_t CH_ENA38 : 1; /*!< Represents ch38 enable status.\\0: Disable\\1: Enable */ + __IOM uint32_t CH_ENA39 : 1; /*!< Represents ch39 enable status.\\0: Disable\\1: Enable */ + __IOM uint32_t CH_ENA40 : 1; /*!< Represents ch40 enable status.\\0: Disable\\1: Enable */ + __IOM uint32_t CH_ENA41 : 1; /*!< Represents ch41 enable status.\\0: Disable\\1: Enable */ + __IOM uint32_t CH_ENA42 : 1; /*!< Represents ch42 enable status.\\0: Disable\\1: Enable */ + __IOM uint32_t CH_ENA43 : 1; /*!< Represents ch43 enable status.\\0: Disable\\1: Enable */ + __IOM uint32_t CH_ENA44 : 1; /*!< Represents ch44 enable status.\\0: Disable\\1: Enable */ + __IOM uint32_t CH_ENA45 : 1; /*!< Represents ch45 enable status.\\0: Disable\\1: Enable */ + __IOM uint32_t CH_ENA46 : 1; /*!< Represents ch46 enable status.\\0: Disable\\1: Enable */ + __IOM uint32_t CH_ENA47 : 1; /*!< Represents ch47 enable status.\\0: Disable\\1: Enable */ + __IOM uint32_t CH_ENA48 : 1; /*!< Represents ch48 enable status.\\0: Disable\\1: Enable */ + __IOM uint32_t CH_ENA49 : 1; /*!< Represents ch49 enable status.\\0: Disable\\1: Enable */ + uint32_t : 14; + } bit; + } CH_ENA_AD1; + + union { + __IOM uint32_t reg; /*!< Channel enable set register */ + + struct { + __OM uint32_t CH_SET32 : 1; /*!< Configures whether or not to enable ch32.\\0: Invalid, No effect\\1: + Enable */ + __OM uint32_t CH_SET33 : 1; /*!< Configures whether or not to enable ch33.\\0: Invalid, No effect\\1: + Enable */ + __OM uint32_t CH_SET34 : 1; /*!< Configures whether or not to enable ch34.\\0: Invalid, No effect\\1: + Enable */ + __OM uint32_t CH_SET35 : 1; /*!< Configures whether or not to enable ch35.\\0: Invalid, No effect\\1: + Enable */ + __OM uint32_t CH_SET36 : 1; /*!< Configures whether or not to enable ch36.\\0: Invalid, No effect\\1: + Enable */ + __OM uint32_t CH_SET37 : 1; /*!< Configures whether or not to enable ch37.\\0: Invalid, No effect\\1: + Enable */ + __OM uint32_t CH_SET38 : 1; /*!< Configures whether or not to enable ch38.\\0: Invalid, No effect\\1: + Enable */ + __OM uint32_t CH_SET39 : 1; /*!< Configures whether or not to enable ch39.\\0: Invalid, No effect\\1: + Enable */ + __OM uint32_t CH_SET40 : 1; /*!< Configures whether or not to enable ch40.\\0: Invalid, No effect\\1: + Enable */ + __OM uint32_t CH_SET41 : 1; /*!< Configures whether or not to enable ch41.\\0: Invalid, No effect\\1: + Enable */ + __OM uint32_t CH_SET42 : 1; /*!< Configures whether or not to enable ch42.\\0: Invalid, No effect\\1: + Enable */ + __OM uint32_t CH_SET43 : 1; /*!< Configures whether or not to enable ch43.\\0: Invalid, No effect\\1: + Enable */ + __OM uint32_t CH_SET44 : 1; /*!< Configures whether or not to enable ch44.\\0: Invalid, No effect\\1: + Enable */ + __OM uint32_t CH_SET45 : 1; /*!< Configures whether or not to enable ch45.\\0: Invalid, No effect\\1: + Enable */ + __OM uint32_t CH_SET46 : 1; /*!< Configures whether or not to enable ch46.\\0: Invalid, No effect\\1: + Enable */ + __OM uint32_t CH_SET47 : 1; /*!< Configures whether or not to enable ch47.\\0: Invalid, No effect\\1: + Enable */ + __OM uint32_t CH_SET48 : 1; /*!< Configures whether or not to enable ch48.\\0: Invalid, No effect\\1: + Enable */ + __OM uint32_t CH_SET49 : 1; /*!< Configures whether or not to enable ch49.\\0: Invalid, No effect\\1: + Enable */ + uint32_t : 14; + } bit; + } CH_ENA_AD1_SET; + + union { + __IOM uint32_t reg; /*!< Channel enable clear register */ + + struct { + __OM uint32_t CH_CLR32 : 1; /*!< Configures whether or not to clear ch32 enable.\\0: Invalid, + No effect\\1: Clear */ + __OM uint32_t CH_CLR33 : 1; /*!< Configures whether or not to clear ch33 enable.\\0: Invalid, + No effect\\1: Clear */ + __OM uint32_t CH_CLR34 : 1; /*!< Configures whether or not to clear ch34 enable.\\0: Invalid, + No effect\\1: Clear */ + __OM uint32_t CH_CLR35 : 1; /*!< Configures whether or not to clear ch35 enable.\\0: Invalid, + No effect\\1: Clear */ + __OM uint32_t CH_CLR36 : 1; /*!< Configures whether or not to clear ch36 enable.\\0: Invalid, + No effect\\1: Clear */ + __OM uint32_t CH_CLR37 : 1; /*!< Configures whether or not to clear ch37 enable.\\0: Invalid, + No effect\\1: Clear */ + __OM uint32_t CH_CLR38 : 1; /*!< Configures whether or not to clear ch38 enable.\\0: Invalid, + No effect\\1: Clear */ + __OM uint32_t CH_CLR39 : 1; /*!< Configures whether or not to clear ch39 enable.\\0: Invalid, + No effect\\1: Clear */ + __OM uint32_t CH_CLR40 : 1; /*!< Configures whether or not to clear ch40 enable.\\0: Invalid, + No effect\\1: Clear */ + __OM uint32_t CH_CLR41 : 1; /*!< Configures whether or not to clear ch41 enable.\\0: Invalid, + No effect\\1: Clear */ + __OM uint32_t CH_CLR42 : 1; /*!< Configures whether or not to clear ch42 enable.\\0: Invalid, + No effect\\1: Clear */ + __OM uint32_t CH_CLR43 : 1; /*!< Configures whether or not to clear ch43 enable.\\0: Invalid, + No effect\\1: Clear */ + __OM uint32_t CH_CLR44 : 1; /*!< Configures whether or not to clear ch44 enable.\\0: Invalid, + No effect\\1: Clear */ + __OM uint32_t CH_CLR45 : 1; /*!< Configures whether or not to clear ch45 enable.\\0: Invalid, + No effect\\1: Clear */ + __OM uint32_t CH_CLR46 : 1; /*!< Configures whether or not to clear ch46 enable.\\0: Invalid, + No effect\\1: Clear */ + __OM uint32_t CH_CLR47 : 1; /*!< Configures whether or not to clear ch47 enable.\\0: Invalid, + No effect\\1: Clear */ + __OM uint32_t CH_CLR48 : 1; /*!< Configures whether or not to clear ch48 enable.\\0: Invalid, + No effect\\1: Clear */ + __OM uint32_t CH_CLR49 : 1; /*!< Configures whether or not to clear ch49 enable.\\0: Invalid, + No effect\\1: Clear */ + uint32_t : 14; + } bit; + } CH_ENA_AD1_CLR; + + union { + __IOM uint32_t reg; /*!< Channel0 event id register */ + + struct { + __IOM uint32_t CH0_EVT_ID : 8; /*!< Configures ch0_evt_id */ + uint32_t : 24; + } bit; + } CH0_EVT_ID; + + union { + __IOM uint32_t reg; /*!< Channel0 task id register */ + + struct { + __IOM uint32_t CH0_TASK_ID : 8; /*!< Configures ch0_task_id */ + uint32_t : 24; + } bit; + } CH0_TASK_ID; + + union { + __IOM uint32_t reg; /*!< Channel1 event id register */ + + struct { + __IOM uint32_t CH1_EVT_ID : 8; /*!< Configures ch1_evt_id */ + uint32_t : 24; + } bit; + } CH1_EVT_ID; + + union { + __IOM uint32_t reg; /*!< Channel1 task id register */ + + struct { + __IOM uint32_t CH1_TASK_ID : 8; /*!< Configures ch1_task_id */ + uint32_t : 24; + } bit; + } CH1_TASK_ID; + + union { + __IOM uint32_t reg; /*!< Channel2 event id register */ + + struct { + __IOM uint32_t CH2_EVT_ID : 8; /*!< Configures ch2_evt_id */ + uint32_t : 24; + } bit; + } CH2_EVT_ID; + + union { + __IOM uint32_t reg; /*!< Channel2 task id register */ + + struct { + __IOM uint32_t CH2_TASK_ID : 8; /*!< Configures ch2_task_id */ + uint32_t : 24; + } bit; + } CH2_TASK_ID; + + union { + __IOM uint32_t reg; /*!< Channel3 event id register */ + + struct { + __IOM uint32_t CH3_EVT_ID : 8; /*!< Configures ch3_evt_id */ + uint32_t : 24; + } bit; + } CH3_EVT_ID; + + union { + __IOM uint32_t reg; /*!< Channel3 task id register */ + + struct { + __IOM uint32_t CH3_TASK_ID : 8; /*!< Configures ch3_task_id */ + uint32_t : 24; + } bit; + } CH3_TASK_ID; + + union { + __IOM uint32_t reg; /*!< Channel4 event id register */ + + struct { + __IOM uint32_t CH4_EVT_ID : 8; /*!< Configures ch4_evt_id */ + uint32_t : 24; + } bit; + } CH4_EVT_ID; + + union { + __IOM uint32_t reg; /*!< Channel4 task id register */ + + struct { + __IOM uint32_t CH4_TASK_ID : 8; /*!< Configures ch4_task_id */ + uint32_t : 24; + } bit; + } CH4_TASK_ID; + + union { + __IOM uint32_t reg; /*!< Channel5 event id register */ + + struct { + __IOM uint32_t CH5_EVT_ID : 8; /*!< Configures ch5_evt_id */ + uint32_t : 24; + } bit; + } CH5_EVT_ID; + + union { + __IOM uint32_t reg; /*!< Channel5 task id register */ + + struct { + __IOM uint32_t CH5_TASK_ID : 8; /*!< Configures ch5_task_id */ + uint32_t : 24; + } bit; + } CH5_TASK_ID; + + union { + __IOM uint32_t reg; /*!< Channel6 event id register */ + + struct { + __IOM uint32_t CH6_EVT_ID : 8; /*!< Configures ch6_evt_id */ + uint32_t : 24; + } bit; + } CH6_EVT_ID; + + union { + __IOM uint32_t reg; /*!< Channel6 task id register */ + + struct { + __IOM uint32_t CH6_TASK_ID : 8; /*!< Configures ch6_task_id */ + uint32_t : 24; + } bit; + } CH6_TASK_ID; + + union { + __IOM uint32_t reg; /*!< Channel7 event id register */ + + struct { + __IOM uint32_t CH7_EVT_ID : 8; /*!< Configures ch7_evt_id */ + uint32_t : 24; + } bit; + } CH7_EVT_ID; + + union { + __IOM uint32_t reg; /*!< Channel7 task id register */ + + struct { + __IOM uint32_t CH7_TASK_ID : 8; /*!< Configures ch7_task_id */ + uint32_t : 24; + } bit; + } CH7_TASK_ID; + + union { + __IOM uint32_t reg; /*!< Channel8 event id register */ + + struct { + __IOM uint32_t CH8_EVT_ID : 8; /*!< Configures ch8_evt_id */ + uint32_t : 24; + } bit; + } CH8_EVT_ID; + + union { + __IOM uint32_t reg; /*!< Channel8 task id register */ + + struct { + __IOM uint32_t CH8_TASK_ID : 8; /*!< Configures ch8_task_id */ + uint32_t : 24; + } bit; + } CH8_TASK_ID; + + union { + __IOM uint32_t reg; /*!< Channel9 event id register */ + + struct { + __IOM uint32_t CH9_EVT_ID : 8; /*!< Configures ch9_evt_id */ + uint32_t : 24; + } bit; + } CH9_EVT_ID; + + union { + __IOM uint32_t reg; /*!< Channel9 task id register */ + + struct { + __IOM uint32_t CH9_TASK_ID : 8; /*!< Configures ch9_task_id */ + uint32_t : 24; + } bit; + } CH9_TASK_ID; + + union { + __IOM uint32_t reg; /*!< Channel10 event id register */ + + struct { + __IOM uint32_t CH10_EVT_ID : 8; /*!< Configures ch10_evt_id */ + uint32_t : 24; + } bit; + } CH10_EVT_ID; + + union { + __IOM uint32_t reg; /*!< Channel10 task id register */ + + struct { + __IOM uint32_t CH10_TASK_ID : 8; /*!< Configures ch10_task_id */ + uint32_t : 24; + } bit; + } CH10_TASK_ID; + + union { + __IOM uint32_t reg; /*!< Channel11 event id register */ + + struct { + __IOM uint32_t CH11_EVT_ID : 8; /*!< Configures ch11_evt_id */ + uint32_t : 24; + } bit; + } CH11_EVT_ID; + + union { + __IOM uint32_t reg; /*!< Channel11 task id register */ + + struct { + __IOM uint32_t CH11_TASK_ID : 8; /*!< Configures ch11_task_id */ + uint32_t : 24; + } bit; + } CH11_TASK_ID; + + union { + __IOM uint32_t reg; /*!< Channel12 event id register */ + + struct { + __IOM uint32_t CH12_EVT_ID : 8; /*!< Configures ch12_evt_id */ + uint32_t : 24; + } bit; + } CH12_EVT_ID; + + union { + __IOM uint32_t reg; /*!< Channel12 task id register */ + + struct { + __IOM uint32_t CH12_TASK_ID : 8; /*!< Configures ch12_task_id */ + uint32_t : 24; + } bit; + } CH12_TASK_ID; + + union { + __IOM uint32_t reg; /*!< Channel13 event id register */ + + struct { + __IOM uint32_t CH13_EVT_ID : 8; /*!< Configures ch13_evt_id */ + uint32_t : 24; + } bit; + } CH13_EVT_ID; + + union { + __IOM uint32_t reg; /*!< Channel13 task id register */ + + struct { + __IOM uint32_t CH13_TASK_ID : 8; /*!< Configures ch13_task_id */ + uint32_t : 24; + } bit; + } CH13_TASK_ID; + + union { + __IOM uint32_t reg; /*!< Channel14 event id register */ + + struct { + __IOM uint32_t CH14_EVT_ID : 8; /*!< Configures ch14_evt_id */ + uint32_t : 24; + } bit; + } CH14_EVT_ID; + + union { + __IOM uint32_t reg; /*!< Channel14 task id register */ + + struct { + __IOM uint32_t CH14_TASK_ID : 8; /*!< Configures ch14_task_id */ + uint32_t : 24; + } bit; + } CH14_TASK_ID; + + union { + __IOM uint32_t reg; /*!< Channel15 event id register */ + + struct { + __IOM uint32_t CH15_EVT_ID : 8; /*!< Configures ch15_evt_id */ + uint32_t : 24; + } bit; + } CH15_EVT_ID; + + union { + __IOM uint32_t reg; /*!< Channel15 task id register */ + + struct { + __IOM uint32_t CH15_TASK_ID : 8; /*!< Configures ch15_task_id */ + uint32_t : 24; + } bit; + } CH15_TASK_ID; + + union { + __IOM uint32_t reg; /*!< Channel16 event id register */ + + struct { + __IOM uint32_t CH16_EVT_ID : 8; /*!< Configures ch16_evt_id */ + uint32_t : 24; + } bit; + } CH16_EVT_ID; + + union { + __IOM uint32_t reg; /*!< Channel16 task id register */ + + struct { + __IOM uint32_t CH16_TASK_ID : 8; /*!< Configures ch16_task_id */ + uint32_t : 24; + } bit; + } CH16_TASK_ID; + + union { + __IOM uint32_t reg; /*!< Channel17 event id register */ + + struct { + __IOM uint32_t CH17_EVT_ID : 8; /*!< Configures ch17_evt_id */ + uint32_t : 24; + } bit; + } CH17_EVT_ID; + + union { + __IOM uint32_t reg; /*!< Channel17 task id register */ + + struct { + __IOM uint32_t CH17_TASK_ID : 8; /*!< Configures ch17_task_id */ + uint32_t : 24; + } bit; + } CH17_TASK_ID; + + union { + __IOM uint32_t reg; /*!< Channel18 event id register */ + + struct { + __IOM uint32_t CH18_EVT_ID : 8; /*!< Configures ch18_evt_id */ + uint32_t : 24; + } bit; + } CH18_EVT_ID; + + union { + __IOM uint32_t reg; /*!< Channel18 task id register */ + + struct { + __IOM uint32_t CH18_TASK_ID : 8; /*!< Configures ch18_task_id */ + uint32_t : 24; + } bit; + } CH18_TASK_ID; + + union { + __IOM uint32_t reg; /*!< Channel19 event id register */ + + struct { + __IOM uint32_t CH19_EVT_ID : 8; /*!< Configures ch19_evt_id */ + uint32_t : 24; + } bit; + } CH19_EVT_ID; + + union { + __IOM uint32_t reg; /*!< Channel19 task id register */ + + struct { + __IOM uint32_t CH19_TASK_ID : 8; /*!< Configures ch19_task_id */ + uint32_t : 24; + } bit; + } CH19_TASK_ID; + + union { + __IOM uint32_t reg; /*!< Channel20 event id register */ + + struct { + __IOM uint32_t CH20_EVT_ID : 8; /*!< Configures ch20_evt_id */ + uint32_t : 24; + } bit; + } CH20_EVT_ID; + + union { + __IOM uint32_t reg; /*!< Channel20 task id register */ + + struct { + __IOM uint32_t CH20_TASK_ID : 8; /*!< Configures ch20_task_id */ + uint32_t : 24; + } bit; + } CH20_TASK_ID; + + union { + __IOM uint32_t reg; /*!< Channel21 event id register */ + + struct { + __IOM uint32_t CH21_EVT_ID : 8; /*!< Configures ch21_evt_id */ + uint32_t : 24; + } bit; + } CH21_EVT_ID; + + union { + __IOM uint32_t reg; /*!< Channel21 task id register */ + + struct { + __IOM uint32_t CH21_TASK_ID : 8; /*!< Configures ch21_task_id */ + uint32_t : 24; + } bit; + } CH21_TASK_ID; + + union { + __IOM uint32_t reg; /*!< Channel22 event id register */ + + struct { + __IOM uint32_t CH22_EVT_ID : 8; /*!< Configures ch22_evt_id */ + uint32_t : 24; + } bit; + } CH22_EVT_ID; + + union { + __IOM uint32_t reg; /*!< Channel22 task id register */ + + struct { + __IOM uint32_t CH22_TASK_ID : 8; /*!< Configures ch22_task_id */ + uint32_t : 24; + } bit; + } CH22_TASK_ID; + + union { + __IOM uint32_t reg; /*!< Channel23 event id register */ + + struct { + __IOM uint32_t CH23_EVT_ID : 8; /*!< Configures ch23_evt_id */ + uint32_t : 24; + } bit; + } CH23_EVT_ID; + + union { + __IOM uint32_t reg; /*!< Channel23 task id register */ + + struct { + __IOM uint32_t CH23_TASK_ID : 8; /*!< Configures ch23_task_id */ + uint32_t : 24; + } bit; + } CH23_TASK_ID; + + union { + __IOM uint32_t reg; /*!< Channel24 event id register */ + + struct { + __IOM uint32_t CH24_EVT_ID : 8; /*!< Configures ch24_evt_id */ + uint32_t : 24; + } bit; + } CH24_EVT_ID; + + union { + __IOM uint32_t reg; /*!< Channel24 task id register */ + + struct { + __IOM uint32_t CH24_TASK_ID : 8; /*!< Configures ch24_task_id */ + uint32_t : 24; + } bit; + } CH24_TASK_ID; + + union { + __IOM uint32_t reg; /*!< Channel25 event id register */ + + struct { + __IOM uint32_t CH25_EVT_ID : 8; /*!< Configures ch25_evt_id */ + uint32_t : 24; + } bit; + } CH25_EVT_ID; + + union { + __IOM uint32_t reg; /*!< Channel25 task id register */ + + struct { + __IOM uint32_t CH25_TASK_ID : 8; /*!< Configures ch25_task_id */ + uint32_t : 24; + } bit; + } CH25_TASK_ID; + + union { + __IOM uint32_t reg; /*!< Channel26 event id register */ + + struct { + __IOM uint32_t CH26_EVT_ID : 8; /*!< Configures ch26_evt_id */ + uint32_t : 24; + } bit; + } CH26_EVT_ID; + + union { + __IOM uint32_t reg; /*!< Channel26 task id register */ + + struct { + __IOM uint32_t CH26_TASK_ID : 8; /*!< Configures ch26_task_id */ + uint32_t : 24; + } bit; + } CH26_TASK_ID; + + union { + __IOM uint32_t reg; /*!< Channel27 event id register */ + + struct { + __IOM uint32_t CH27_EVT_ID : 8; /*!< Configures ch27_evt_id */ + uint32_t : 24; + } bit; + } CH27_EVT_ID; + + union { + __IOM uint32_t reg; /*!< Channel27 task id register */ + + struct { + __IOM uint32_t CH27_TASK_ID : 8; /*!< Configures ch27_task_id */ + uint32_t : 24; + } bit; + } CH27_TASK_ID; + + union { + __IOM uint32_t reg; /*!< Channel28 event id register */ + + struct { + __IOM uint32_t CH28_EVT_ID : 8; /*!< Configures ch28_evt_id */ + uint32_t : 24; + } bit; + } CH28_EVT_ID; + + union { + __IOM uint32_t reg; /*!< Channel28 task id register */ + + struct { + __IOM uint32_t CH28_TASK_ID : 8; /*!< Configures ch28_task_id */ + uint32_t : 24; + } bit; + } CH28_TASK_ID; + + union { + __IOM uint32_t reg; /*!< Channel29 event id register */ + + struct { + __IOM uint32_t CH29_EVT_ID : 8; /*!< Configures ch29_evt_id */ + uint32_t : 24; + } bit; + } CH29_EVT_ID; + + union { + __IOM uint32_t reg; /*!< Channel29 task id register */ + + struct { + __IOM uint32_t CH29_TASK_ID : 8; /*!< Configures ch29_task_id */ + uint32_t : 24; + } bit; + } CH29_TASK_ID; + + union { + __IOM uint32_t reg; /*!< Channel30 event id register */ + + struct { + __IOM uint32_t CH30_EVT_ID : 8; /*!< Configures ch30_evt_id */ + uint32_t : 24; + } bit; + } CH30_EVT_ID; + + union { + __IOM uint32_t reg; /*!< Channel30 task id register */ + + struct { + __IOM uint32_t CH30_TASK_ID : 8; /*!< Configures ch30_task_id */ + uint32_t : 24; + } bit; + } CH30_TASK_ID; + + union { + __IOM uint32_t reg; /*!< Channel31 event id register */ + + struct { + __IOM uint32_t CH31_EVT_ID : 8; /*!< Configures ch31_evt_id */ + uint32_t : 24; + } bit; + } CH31_EVT_ID; + + union { + __IOM uint32_t reg; /*!< Channel31 task id register */ + + struct { + __IOM uint32_t CH31_TASK_ID : 8; /*!< Configures ch31_task_id */ + uint32_t : 24; + } bit; + } CH31_TASK_ID; + + union { + __IOM uint32_t reg; /*!< Channel32 event id register */ + + struct { + __IOM uint32_t CH32_EVT_ID : 8; /*!< Configures ch32_evt_id */ + uint32_t : 24; + } bit; + } CH32_EVT_ID; + + union { + __IOM uint32_t reg; /*!< Channel32 task id register */ + + struct { + __IOM uint32_t CH32_TASK_ID : 8; /*!< Configures ch32_task_id */ + uint32_t : 24; + } bit; + } CH32_TASK_ID; + + union { + __IOM uint32_t reg; /*!< Channel33 event id register */ + + struct { + __IOM uint32_t CH33_EVT_ID : 8; /*!< Configures ch33_evt_id */ + uint32_t : 24; + } bit; + } CH33_EVT_ID; + + union { + __IOM uint32_t reg; /*!< Channel33 task id register */ + + struct { + __IOM uint32_t CH33_TASK_ID : 8; /*!< Configures ch33_task_id */ + uint32_t : 24; + } bit; + } CH33_TASK_ID; + + union { + __IOM uint32_t reg; /*!< Channel34 event id register */ + + struct { + __IOM uint32_t CH34_EVT_ID : 8; /*!< Configures ch34_evt_id */ + uint32_t : 24; + } bit; + } CH34_EVT_ID; + + union { + __IOM uint32_t reg; /*!< Channel34 task id register */ + + struct { + __IOM uint32_t CH34_TASK_ID : 8; /*!< Configures ch34_task_id */ + uint32_t : 24; + } bit; + } CH34_TASK_ID; + + union { + __IOM uint32_t reg; /*!< Channel35 event id register */ + + struct { + __IOM uint32_t CH35_EVT_ID : 8; /*!< Configures ch35_evt_id */ + uint32_t : 24; + } bit; + } CH35_EVT_ID; + + union { + __IOM uint32_t reg; /*!< Channel35 task id register */ + + struct { + __IOM uint32_t CH35_TASK_ID : 8; /*!< Configures ch35_task_id */ + uint32_t : 24; + } bit; + } CH35_TASK_ID; + + union { + __IOM uint32_t reg; /*!< Channel36 event id register */ + + struct { + __IOM uint32_t CH36_EVT_ID : 8; /*!< Configures ch36_evt_id */ + uint32_t : 24; + } bit; + } CH36_EVT_ID; + + union { + __IOM uint32_t reg; /*!< Channel36 task id register */ + + struct { + __IOM uint32_t CH36_TASK_ID : 8; /*!< Configures ch36_task_id */ + uint32_t : 24; + } bit; + } CH36_TASK_ID; + + union { + __IOM uint32_t reg; /*!< Channel37 event id register */ + + struct { + __IOM uint32_t CH37_EVT_ID : 8; /*!< Configures ch37_evt_id */ + uint32_t : 24; + } bit; + } CH37_EVT_ID; + + union { + __IOM uint32_t reg; /*!< Channel37 task id register */ + + struct { + __IOM uint32_t CH37_TASK_ID : 8; /*!< Configures ch37_task_id */ + uint32_t : 24; + } bit; + } CH37_TASK_ID; + + union { + __IOM uint32_t reg; /*!< Channel38 event id register */ + + struct { + __IOM uint32_t CH38_EVT_ID : 8; /*!< Configures ch38_evt_id */ + uint32_t : 24; + } bit; + } CH38_EVT_ID; + + union { + __IOM uint32_t reg; /*!< Channel38 task id register */ + + struct { + __IOM uint32_t CH38_TASK_ID : 8; /*!< Configures ch38_task_id */ + uint32_t : 24; + } bit; + } CH38_TASK_ID; + + union { + __IOM uint32_t reg; /*!< Channel39 event id register */ + + struct { + __IOM uint32_t CH39_EVT_ID : 8; /*!< Configures ch39_evt_id */ + uint32_t : 24; + } bit; + } CH39_EVT_ID; + + union { + __IOM uint32_t reg; /*!< Channel39 task id register */ + + struct { + __IOM uint32_t CH39_TASK_ID : 8; /*!< Configures ch39_task_id */ + uint32_t : 24; + } bit; + } CH39_TASK_ID; + + union { + __IOM uint32_t reg; /*!< Channel40 event id register */ + + struct { + __IOM uint32_t CH40_EVT_ID : 8; /*!< Configures ch40_evt_id */ + uint32_t : 24; + } bit; + } CH40_EVT_ID; + + union { + __IOM uint32_t reg; /*!< Channel40 task id register */ + + struct { + __IOM uint32_t CH40_TASK_ID : 8; /*!< Configures ch40_task_id */ + uint32_t : 24; + } bit; + } CH40_TASK_ID; + + union { + __IOM uint32_t reg; /*!< Channel41 event id register */ + + struct { + __IOM uint32_t CH41_EVT_ID : 8; /*!< Configures ch41_evt_id */ + uint32_t : 24; + } bit; + } CH41_EVT_ID; + + union { + __IOM uint32_t reg; /*!< Channel41 task id register */ + + struct { + __IOM uint32_t CH41_TASK_ID : 8; /*!< Configures ch41_task_id */ + uint32_t : 24; + } bit; + } CH41_TASK_ID; + + union { + __IOM uint32_t reg; /*!< Channel42 event id register */ + + struct { + __IOM uint32_t CH42_EVT_ID : 8; /*!< Configures ch42_evt_id */ + uint32_t : 24; + } bit; + } CH42_EVT_ID; + + union { + __IOM uint32_t reg; /*!< Channel42 task id register */ + + struct { + __IOM uint32_t CH42_TASK_ID : 8; /*!< Configures ch42_task_id */ + uint32_t : 24; + } bit; + } CH42_TASK_ID; + + union { + __IOM uint32_t reg; /*!< Channel43 event id register */ + + struct { + __IOM uint32_t CH43_EVT_ID : 8; /*!< Configures ch43_evt_id */ + uint32_t : 24; + } bit; + } CH43_EVT_ID; + + union { + __IOM uint32_t reg; /*!< Channel43 task id register */ + + struct { + __IOM uint32_t CH43_TASK_ID : 8; /*!< Configures ch43_task_id */ + uint32_t : 24; + } bit; + } CH43_TASK_ID; + + union { + __IOM uint32_t reg; /*!< Channel44 event id register */ + + struct { + __IOM uint32_t CH44_EVT_ID : 8; /*!< Configures ch44_evt_id */ + uint32_t : 24; + } bit; + } CH44_EVT_ID; + + union { + __IOM uint32_t reg; /*!< Channel44 task id register */ + + struct { + __IOM uint32_t CH44_TASK_ID : 8; /*!< Configures ch44_task_id */ + uint32_t : 24; + } bit; + } CH44_TASK_ID; + + union { + __IOM uint32_t reg; /*!< Channel45 event id register */ + + struct { + __IOM uint32_t CH45_EVT_ID : 8; /*!< Configures ch45_evt_id */ + uint32_t : 24; + } bit; + } CH45_EVT_ID; + + union { + __IOM uint32_t reg; /*!< Channel45 task id register */ + + struct { + __IOM uint32_t CH45_TASK_ID : 8; /*!< Configures ch45_task_id */ + uint32_t : 24; + } bit; + } CH45_TASK_ID; + + union { + __IOM uint32_t reg; /*!< Channel46 event id register */ + + struct { + __IOM uint32_t CH46_EVT_ID : 8; /*!< Configures ch46_evt_id */ + uint32_t : 24; + } bit; + } CH46_EVT_ID; + + union { + __IOM uint32_t reg; /*!< Channel46 task id register */ + + struct { + __IOM uint32_t CH46_TASK_ID : 8; /*!< Configures ch46_task_id */ + uint32_t : 24; + } bit; + } CH46_TASK_ID; + + union { + __IOM uint32_t reg; /*!< Channel47 event id register */ + + struct { + __IOM uint32_t CH47_EVT_ID : 8; /*!< Configures ch47_evt_id */ + uint32_t : 24; + } bit; + } CH47_EVT_ID; + + union { + __IOM uint32_t reg; /*!< Channel47 task id register */ + + struct { + __IOM uint32_t CH47_TASK_ID : 8; /*!< Configures ch47_task_id */ + uint32_t : 24; + } bit; + } CH47_TASK_ID; + + union { + __IOM uint32_t reg; /*!< Channel48 event id register */ + + struct { + __IOM uint32_t CH48_EVT_ID : 8; /*!< Configures ch48_evt_id */ + uint32_t : 24; + } bit; + } CH48_EVT_ID; + + union { + __IOM uint32_t reg; /*!< Channel48 task id register */ + + struct { + __IOM uint32_t CH48_TASK_ID : 8; /*!< Configures ch48_task_id */ + uint32_t : 24; + } bit; + } CH48_TASK_ID; + + union { + __IOM uint32_t reg; /*!< Channel49 event id register */ + + struct { + __IOM uint32_t CH49_EVT_ID : 8; /*!< Configures ch49_evt_id */ + uint32_t : 24; + } bit; + } CH49_EVT_ID; + + union { + __IOM uint32_t reg; /*!< Channel49 task id register */ + + struct { + __IOM uint32_t CH49_TASK_ID : 8; /*!< Configures ch49_task_id */ + uint32_t : 24; + } bit; + } CH49_TASK_ID; + + union { + __IOM uint32_t reg; /*!< Events trigger status register */ + + struct { + __IOM uint32_t GPIO_EVT_CH0_RISE_EDGE_ST : 1;/*!< Represents GPIO_evt_ch0_rise_edge trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t GPIO_EVT_CH1_RISE_EDGE_ST : 1;/*!< Represents GPIO_evt_ch1_rise_edge trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t GPIO_EVT_CH2_RISE_EDGE_ST : 1;/*!< Represents GPIO_evt_ch2_rise_edge trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t GPIO_EVT_CH3_RISE_EDGE_ST : 1;/*!< Represents GPIO_evt_ch3_rise_edge trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t GPIO_EVT_CH4_RISE_EDGE_ST : 1;/*!< Represents GPIO_evt_ch4_rise_edge trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t GPIO_EVT_CH5_RISE_EDGE_ST : 1;/*!< Represents GPIO_evt_ch5_rise_edge trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t GPIO_EVT_CH6_RISE_EDGE_ST : 1;/*!< Represents GPIO_evt_ch6_rise_edge trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t GPIO_EVT_CH7_RISE_EDGE_ST : 1;/*!< Represents GPIO_evt_ch7_rise_edge trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t GPIO_EVT_CH0_FALL_EDGE_ST : 1;/*!< Represents GPIO_evt_ch0_fall_edge trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t GPIO_EVT_CH1_FALL_EDGE_ST : 1;/*!< Represents GPIO_evt_ch1_fall_edge trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t GPIO_EVT_CH2_FALL_EDGE_ST : 1;/*!< Represents GPIO_evt_ch2_fall_edge trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t GPIO_EVT_CH3_FALL_EDGE_ST : 1;/*!< Represents GPIO_evt_ch3_fall_edge trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t GPIO_EVT_CH4_FALL_EDGE_ST : 1;/*!< Represents GPIO_evt_ch4_fall_edge trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t GPIO_EVT_CH5_FALL_EDGE_ST : 1;/*!< Represents GPIO_evt_ch5_fall_edge trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t GPIO_EVT_CH6_FALL_EDGE_ST : 1;/*!< Represents GPIO_evt_ch6_fall_edge trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t GPIO_EVT_CH7_FALL_EDGE_ST : 1;/*!< Represents GPIO_evt_ch7_fall_edge trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t GPIO_EVT_CH0_ANY_EDGE_ST : 1;/*!< Represents GPIO_evt_ch0_any_edge trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t GPIO_EVT_CH1_ANY_EDGE_ST : 1;/*!< Represents GPIO_evt_ch1_any_edge trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t GPIO_EVT_CH2_ANY_EDGE_ST : 1;/*!< Represents GPIO_evt_ch2_any_edge trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t GPIO_EVT_CH3_ANY_EDGE_ST : 1;/*!< Represents GPIO_evt_ch3_any_edge trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t GPIO_EVT_CH4_ANY_EDGE_ST : 1;/*!< Represents GPIO_evt_ch4_any_edge trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t GPIO_EVT_CH5_ANY_EDGE_ST : 1;/*!< Represents GPIO_evt_ch5_any_edge trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t GPIO_EVT_CH6_ANY_EDGE_ST : 1;/*!< Represents GPIO_evt_ch6_any_edge trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t GPIO_EVT_CH7_ANY_EDGE_ST : 1;/*!< Represents GPIO_evt_ch7_any_edge trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t GPIO_EVT_ZERO_DET_POS0_ST : 1;/*!< Represents GPIO_evt_zero_det_pos0 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t GPIO_EVT_ZERO_DET_NEG0_ST : 1;/*!< Represents GPIO_evt_zero_det_neg0 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t GPIO_EVT_ZERO_DET_POS1_ST : 1;/*!< Represents GPIO_evt_zero_det_pos1 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t GPIO_EVT_ZERO_DET_NEG1_ST : 1;/*!< Represents GPIO_evt_zero_det_neg1 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t LEDC_EVT_DUTY_CHNG_END_CH0_ST : 1;/*!< Represents LEDC_evt_duty_chng_end_ch0 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t LEDC_EVT_DUTY_CHNG_END_CH1_ST : 1;/*!< Represents LEDC_evt_duty_chng_end_ch1 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t LEDC_EVT_DUTY_CHNG_END_CH2_ST : 1;/*!< Represents LEDC_evt_duty_chng_end_ch2 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t LEDC_EVT_DUTY_CHNG_END_CH3_ST : 1;/*!< Represents LEDC_evt_duty_chng_end_ch3 trigger status.\\0: Not + triggered\\1: Triggered */ + } bit; + } EVT_ST0; + + union { + __IOM uint32_t reg; /*!< Events trigger status clear register */ + + struct { + __OM uint32_t GPIO_EVT_CH0_RISE_EDGE_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_evt_ch0_rise_edge trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t GPIO_EVT_CH1_RISE_EDGE_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_evt_ch1_rise_edge trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t GPIO_EVT_CH2_RISE_EDGE_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_evt_ch2_rise_edge trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t GPIO_EVT_CH3_RISE_EDGE_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_evt_ch3_rise_edge trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t GPIO_EVT_CH4_RISE_EDGE_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_evt_ch4_rise_edge trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t GPIO_EVT_CH5_RISE_EDGE_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_evt_ch5_rise_edge trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t GPIO_EVT_CH6_RISE_EDGE_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_evt_ch6_rise_edge trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t GPIO_EVT_CH7_RISE_EDGE_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_evt_ch7_rise_edge trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t GPIO_EVT_CH0_FALL_EDGE_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_evt_ch0_fall_edge trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t GPIO_EVT_CH1_FALL_EDGE_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_evt_ch1_fall_edge trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t GPIO_EVT_CH2_FALL_EDGE_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_evt_ch2_fall_edge trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t GPIO_EVT_CH3_FALL_EDGE_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_evt_ch3_fall_edge trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t GPIO_EVT_CH4_FALL_EDGE_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_evt_ch4_fall_edge trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t GPIO_EVT_CH5_FALL_EDGE_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_evt_ch5_fall_edge trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t GPIO_EVT_CH6_FALL_EDGE_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_evt_ch6_fall_edge trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t GPIO_EVT_CH7_FALL_EDGE_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_evt_ch7_fall_edge trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t GPIO_EVT_CH0_ANY_EDGE_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_evt_ch0_any_edge trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t GPIO_EVT_CH1_ANY_EDGE_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_evt_ch1_any_edge trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t GPIO_EVT_CH2_ANY_EDGE_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_evt_ch2_any_edge trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t GPIO_EVT_CH3_ANY_EDGE_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_evt_ch3_any_edge trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t GPIO_EVT_CH4_ANY_EDGE_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_evt_ch4_any_edge trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t GPIO_EVT_CH5_ANY_EDGE_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_evt_ch5_any_edge trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t GPIO_EVT_CH6_ANY_EDGE_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_evt_ch6_any_edge trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t GPIO_EVT_CH7_ANY_EDGE_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_evt_ch7_any_edge trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t GPIO_EVT_ZERO_DET_POS0_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_evt_zero_det_pos0 trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t GPIO_EVT_ZERO_DET_NEG0_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_evt_zero_det_neg0 trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t GPIO_EVT_ZERO_DET_POS1_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_evt_zero_det_pos1 trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t GPIO_EVT_ZERO_DET_NEG1_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_evt_zero_det_neg1 trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_evt_duty_chng_end_ch0 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_evt_duty_chng_end_ch1 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_evt_duty_chng_end_ch2 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_evt_duty_chng_end_ch3 + trigger status.\\0: Invalid, No effect\\1: Clear */ + } bit; + } EVT_ST0_CLR; + + union { + __IOM uint32_t reg; /*!< Events trigger status register */ + + struct { + __IOM uint32_t LEDC_EVT_DUTY_CHNG_END_CH4_ST : 1;/*!< Represents LEDC_evt_duty_chng_end_ch4 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t LEDC_EVT_DUTY_CHNG_END_CH5_ST : 1;/*!< Represents LEDC_evt_duty_chng_end_ch5 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t LEDC_EVT_DUTY_CHNG_END_CH6_ST : 1;/*!< Represents LEDC_evt_duty_chng_end_ch6 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t LEDC_EVT_DUTY_CHNG_END_CH7_ST : 1;/*!< Represents LEDC_evt_duty_chng_end_ch7 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t LEDC_EVT_OVF_CNT_PLS_CH0_ST : 1;/*!< Represents LEDC_evt_ovf_cnt_pls_ch0 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t LEDC_EVT_OVF_CNT_PLS_CH1_ST : 1;/*!< Represents LEDC_evt_ovf_cnt_pls_ch1 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t LEDC_EVT_OVF_CNT_PLS_CH2_ST : 1;/*!< Represents LEDC_evt_ovf_cnt_pls_ch2 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t LEDC_EVT_OVF_CNT_PLS_CH3_ST : 1;/*!< Represents LEDC_evt_ovf_cnt_pls_ch3 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t LEDC_EVT_OVF_CNT_PLS_CH4_ST : 1;/*!< Represents LEDC_evt_ovf_cnt_pls_ch4 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t LEDC_EVT_OVF_CNT_PLS_CH5_ST : 1;/*!< Represents LEDC_evt_ovf_cnt_pls_ch5 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t LEDC_EVT_OVF_CNT_PLS_CH6_ST : 1;/*!< Represents LEDC_evt_ovf_cnt_pls_ch6 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t LEDC_EVT_OVF_CNT_PLS_CH7_ST : 1;/*!< Represents LEDC_evt_ovf_cnt_pls_ch7 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t LEDC_EVT_TIME_OVF_TIMER0_ST : 1;/*!< Represents LEDC_evt_time_ovf_timer0 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t LEDC_EVT_TIME_OVF_TIMER1_ST : 1;/*!< Represents LEDC_evt_time_ovf_timer1 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t LEDC_EVT_TIME_OVF_TIMER2_ST : 1;/*!< Represents LEDC_evt_time_ovf_timer2 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t LEDC_EVT_TIME_OVF_TIMER3_ST : 1;/*!< Represents LEDC_evt_time_ovf_timer3 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t LEDC_EVT_TIMER0_CMP_ST : 1;/*!< Represents LEDC_evt_timer0_cmp trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t LEDC_EVT_TIMER1_CMP_ST : 1;/*!< Represents LEDC_evt_timer1_cmp trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t LEDC_EVT_TIMER2_CMP_ST : 1;/*!< Represents LEDC_evt_timer2_cmp trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t LEDC_EVT_TIMER3_CMP_ST : 1;/*!< Represents LEDC_evt_timer3_cmp trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t TG0_EVT_CNT_CMP_TIMER0_ST : 1;/*!< Represents TG0_evt_cnt_cmp_timer0 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t TG0_EVT_CNT_CMP_TIMER1_ST : 1;/*!< Represents TG0_evt_cnt_cmp_timer1 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t TG1_EVT_CNT_CMP_TIMER0_ST : 1;/*!< Represents TG1_evt_cnt_cmp_timer0 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t TG1_EVT_CNT_CMP_TIMER1_ST : 1;/*!< Represents TG1_evt_cnt_cmp_timer1 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t SYSTIMER_EVT_CNT_CMP0_ST : 1;/*!< Represents SYSTIMER_evt_cnt_cmp0 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t SYSTIMER_EVT_CNT_CMP1_ST : 1;/*!< Represents SYSTIMER_evt_cnt_cmp1 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t SYSTIMER_EVT_CNT_CMP2_ST : 1;/*!< Represents SYSTIMER_evt_cnt_cmp2 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM0_EVT_TIMER0_STOP_ST : 1;/*!< Represents MCPWM0_evt_timer0_stop trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM0_EVT_TIMER1_STOP_ST : 1;/*!< Represents MCPWM0_evt_timer1_stop trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM0_EVT_TIMER2_STOP_ST : 1;/*!< Represents MCPWM0_evt_timer2_stop trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM0_EVT_TIMER0_TEZ_ST : 1;/*!< Represents MCPWM0_evt_timer0_tez trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM0_EVT_TIMER1_TEZ_ST : 1;/*!< Represents MCPWM0_evt_timer1_tez trigger status.\\0: Not triggered\\1: + Triggered */ + } bit; + } EVT_ST1; + + union { + __IOM uint32_t reg; /*!< Events trigger status clear register */ + + struct { + __OM uint32_t LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_evt_duty_chng_end_ch4 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_evt_duty_chng_end_ch5 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_EVT_DUTY_CHNG_END_CH6_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_evt_duty_chng_end_ch6 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_EVT_DUTY_CHNG_END_CH7_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_evt_duty_chng_end_ch7 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch0 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch1 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch2 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch3 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch4 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch5 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_EVT_OVF_CNT_PLS_CH6_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch6 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_EVT_OVF_CNT_PLS_CH7_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch7 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_EVT_TIME_OVF_TIMER0_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_evt_time_ovf_timer0 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_EVT_TIME_OVF_TIMER1_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_evt_time_ovf_timer1 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_EVT_TIME_OVF_TIMER2_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_evt_time_ovf_timer2 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_EVT_TIME_OVF_TIMER3_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_evt_time_ovf_timer3 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_EVT_TIMER0_CMP_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_evt_timer0_cmp trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_EVT_TIMER1_CMP_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_evt_timer1_cmp trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_EVT_TIMER2_CMP_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_evt_timer2_cmp trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_EVT_TIMER3_CMP_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_evt_timer3_cmp trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t TG0_EVT_CNT_CMP_TIMER0_ST_CLR : 1;/*!< Configures whether or not to clear TG0_evt_cnt_cmp_timer0 trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t TG0_EVT_CNT_CMP_TIMER1_ST_CLR : 1;/*!< Configures whether or not to clear TG0_evt_cnt_cmp_timer1 trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t TG1_EVT_CNT_CMP_TIMER0_ST_CLR : 1;/*!< Configures whether or not to clear TG1_evt_cnt_cmp_timer0 trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t TG1_EVT_CNT_CMP_TIMER1_ST_CLR : 1;/*!< Configures whether or not to clear TG1_evt_cnt_cmp_timer1 trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t SYSTIMER_EVT_CNT_CMP0_ST_CLR : 1;/*!< Configures whether or not to clear SYSTIMER_evt_cnt_cmp0 trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t SYSTIMER_EVT_CNT_CMP1_ST_CLR : 1;/*!< Configures whether or not to clear SYSTIMER_evt_cnt_cmp1 trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t SYSTIMER_EVT_CNT_CMP2_ST_CLR : 1;/*!< Configures whether or not to clear SYSTIMER_evt_cnt_cmp2 trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM0_EVT_TIMER0_STOP_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_timer0_stop trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM0_EVT_TIMER1_STOP_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_timer1_stop trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM0_EVT_TIMER2_STOP_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_timer2_stop trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM0_EVT_TIMER0_TEZ_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_timer0_tez trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM0_EVT_TIMER1_TEZ_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_timer1_tez trigger + status.\\0: Invalid, No effect\\1: Clear */ + } bit; + } EVT_ST1_CLR; + + union { + __IOM uint32_t reg; /*!< Events trigger status register */ + + struct { + __IOM uint32_t MCPWM0_EVT_TIMER2_TEZ_ST : 1;/*!< Represents MCPWM0_evt_timer2_tez trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM0_EVT_TIMER0_TEP_ST : 1;/*!< Represents MCPWM0_evt_timer0_tep trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM0_EVT_TIMER1_TEP_ST : 1;/*!< Represents MCPWM0_evt_timer1_tep trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM0_EVT_TIMER2_TEP_ST : 1;/*!< Represents MCPWM0_evt_timer2_tep trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM0_EVT_OP0_TEA_ST : 1; /*!< Represents MCPWM0_evt_op0_tea trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM0_EVT_OP1_TEA_ST : 1; /*!< Represents MCPWM0_evt_op1_tea trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM0_EVT_OP2_TEA_ST : 1; /*!< Represents MCPWM0_evt_op2_tea trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM0_EVT_OP0_TEB_ST : 1; /*!< Represents MCPWM0_evt_op0_teb trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM0_EVT_OP1_TEB_ST : 1; /*!< Represents MCPWM0_evt_op1_teb trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM0_EVT_OP2_TEB_ST : 1; /*!< Represents MCPWM0_evt_op2_teb trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM0_EVT_F0_ST : 1; /*!< Represents MCPWM0_evt_f0 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM0_EVT_F1_ST : 1; /*!< Represents MCPWM0_evt_f1 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM0_EVT_F2_ST : 1; /*!< Represents MCPWM0_evt_f2 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM0_EVT_F0_CLR_ST : 1; /*!< Represents MCPWM0_evt_f0_clr trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM0_EVT_F1_CLR_ST : 1; /*!< Represents MCPWM0_evt_f1_clr trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM0_EVT_F2_CLR_ST : 1; /*!< Represents MCPWM0_evt_f2_clr trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM0_EVT_TZ0_CBC_ST : 1; /*!< Represents MCPWM0_evt_tz0_cbc trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM0_EVT_TZ1_CBC_ST : 1; /*!< Represents MCPWM0_evt_tz1_cbc trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM0_EVT_TZ2_CBC_ST : 1; /*!< Represents MCPWM0_evt_tz2_cbc trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM0_EVT_TZ0_OST_ST : 1; /*!< Represents MCPWM0_evt_tz0_ost trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM0_EVT_TZ1_OST_ST : 1; /*!< Represents MCPWM0_evt_tz1_ost trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM0_EVT_TZ2_OST_ST : 1; /*!< Represents MCPWM0_evt_tz2_ost trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM0_EVT_CAP0_ST : 1; /*!< Represents MCPWM0_evt_cap0 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM0_EVT_CAP1_ST : 1; /*!< Represents MCPWM0_evt_cap1 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM0_EVT_CAP2_ST : 1; /*!< Represents MCPWM0_evt_cap2 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM0_EVT_OP0_TEE1_ST : 1;/*!< Represents MCPWM0_evt_op0_tee1 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM0_EVT_OP1_TEE1_ST : 1;/*!< Represents MCPWM0_evt_op1_tee1 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM0_EVT_OP2_TEE1_ST : 1;/*!< Represents MCPWM0_evt_op2_tee1 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM0_EVT_OP0_TEE2_ST : 1;/*!< Represents MCPWM0_evt_op0_tee2 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM0_EVT_OP1_TEE2_ST : 1;/*!< Represents MCPWM0_evt_op1_tee2 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM0_EVT_OP2_TEE2_ST : 1;/*!< Represents MCPWM0_evt_op2_tee2 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM1_EVT_TIMER0_STOP_ST : 1;/*!< Represents MCPWM1_evt_timer0_stop trigger status.\\0: Not triggered\\1: + Triggered */ + } bit; + } EVT_ST2; + + union { + __IOM uint32_t reg; /*!< Events trigger status clear register */ + + struct { + __OM uint32_t MCPWM0_EVT_TIMER2_TEZ_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_timer2_tez trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM0_EVT_TIMER0_TEP_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_timer0_tep trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM0_EVT_TIMER1_TEP_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_timer1_tep trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM0_EVT_TIMER2_TEP_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_timer2_tep trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM0_EVT_OP0_TEA_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_op0_tea trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM0_EVT_OP1_TEA_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_op1_tea trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM0_EVT_OP2_TEA_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_op2_tea trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM0_EVT_OP0_TEB_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_op0_teb trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM0_EVT_OP1_TEB_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_op1_teb trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM0_EVT_OP2_TEB_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_op2_teb trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM0_EVT_F0_ST_CLR : 1; /*!< Configures whether or not to clear MCPWM0_evt_f0 trigger status.\\0: + Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM0_EVT_F1_ST_CLR : 1; /*!< Configures whether or not to clear MCPWM0_evt_f1 trigger status.\\0: + Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM0_EVT_F2_ST_CLR : 1; /*!< Configures whether or not to clear MCPWM0_evt_f2 trigger status.\\0: + Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM0_EVT_F0_CLR_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_f0_clr trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM0_EVT_F1_CLR_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_f1_clr trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM0_EVT_F2_CLR_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_f2_clr trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM0_EVT_TZ0_CBC_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_tz0_cbc trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM0_EVT_TZ1_CBC_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_tz1_cbc trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM0_EVT_TZ2_CBC_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_tz2_cbc trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM0_EVT_TZ0_OST_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_tz0_ost trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM0_EVT_TZ1_OST_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_tz1_ost trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM0_EVT_TZ2_OST_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_tz2_ost trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM0_EVT_CAP0_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_cap0 trigger status.\\0: + Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM0_EVT_CAP1_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_cap1 trigger status.\\0: + Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM0_EVT_CAP2_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_cap2 trigger status.\\0: + Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM0_EVT_OP0_TEE1_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_op0_tee1 trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM0_EVT_OP1_TEE1_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_op1_tee1 trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM0_EVT_OP2_TEE1_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_op2_tee1 trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM0_EVT_OP0_TEE2_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_op0_tee2 trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM0_EVT_OP1_TEE2_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_op1_tee2 trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM0_EVT_OP2_TEE2_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_op2_tee2 trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM1_EVT_TIMER0_STOP_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_timer0_stop trigger + status.\\0: Invalid, No effect\\1: Clear */ + } bit; + } EVT_ST2_CLR; + + union { + __IOM uint32_t reg; /*!< Events trigger status register */ + + struct { + __IOM uint32_t MCPWM1_EVT_TIMER1_STOP_ST : 1;/*!< Represents MCPWM1_evt_timer1_stop trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM1_EVT_TIMER2_STOP_ST : 1;/*!< Represents MCPWM1_evt_timer2_stop trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM1_EVT_TIMER0_TEZ_ST : 1;/*!< Represents MCPWM1_evt_timer0_tez trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM1_EVT_TIMER1_TEZ_ST : 1;/*!< Represents MCPWM1_evt_timer1_tez trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM1_EVT_TIMER2_TEZ_ST : 1;/*!< Represents MCPWM1_evt_timer2_tez trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM1_EVT_TIMER0_TEP_ST : 1;/*!< Represents MCPWM1_evt_timer0_tep trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM1_EVT_TIMER1_TEP_ST : 1;/*!< Represents MCPWM1_evt_timer1_tep trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM1_EVT_TIMER2_TEP_ST : 1;/*!< Represents MCPWM1_evt_timer2_tep trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM1_EVT_OP0_TEA_ST : 1; /*!< Represents MCPWM1_evt_op0_tea trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM1_EVT_OP1_TEA_ST : 1; /*!< Represents MCPWM1_evt_op1_tea trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM1_EVT_OP2_TEA_ST : 1; /*!< Represents MCPWM1_evt_op2_tea trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM1_EVT_OP0_TEB_ST : 1; /*!< Represents MCPWM1_evt_op0_teb trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM1_EVT_OP1_TEB_ST : 1; /*!< Represents MCPWM1_evt_op1_teb trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM1_EVT_OP2_TEB_ST : 1; /*!< Represents MCPWM1_evt_op2_teb trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM1_EVT_F0_ST : 1; /*!< Represents MCPWM1_evt_f0 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM1_EVT_F1_ST : 1; /*!< Represents MCPWM1_evt_f1 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM1_EVT_F2_ST : 1; /*!< Represents MCPWM1_evt_f2 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM1_EVT_F0_CLR_ST : 1; /*!< Represents MCPWM1_evt_f0_clr trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM1_EVT_F1_CLR_ST : 1; /*!< Represents MCPWM1_evt_f1_clr trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM1_EVT_F2_CLR_ST : 1; /*!< Represents MCPWM1_evt_f2_clr trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM1_EVT_TZ0_CBC_ST : 1; /*!< Represents MCPWM1_evt_tz0_cbc trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM1_EVT_TZ1_CBC_ST : 1; /*!< Represents MCPWM1_evt_tz1_cbc trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM1_EVT_TZ2_CBC_ST : 1; /*!< Represents MCPWM1_evt_tz2_cbc trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM1_EVT_TZ0_OST_ST : 1; /*!< Represents MCPWM1_evt_tz0_ost trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM1_EVT_TZ1_OST_ST : 1; /*!< Represents MCPWM1_evt_tz1_ost trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM1_EVT_TZ2_OST_ST : 1; /*!< Represents MCPWM1_evt_tz2_ost trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM1_EVT_CAP0_ST : 1; /*!< Represents MCPWM1_evt_cap0 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM1_EVT_CAP1_ST : 1; /*!< Represents MCPWM1_evt_cap1 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM1_EVT_CAP2_ST : 1; /*!< Represents MCPWM1_evt_cap2 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM1_EVT_OP0_TEE1_ST : 1;/*!< Represents MCPWM1_evt_op0_tee1 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM1_EVT_OP1_TEE1_ST : 1;/*!< Represents MCPWM1_evt_op1_tee1 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM1_EVT_OP2_TEE1_ST : 1;/*!< Represents MCPWM1_evt_op2_tee1 trigger status.\\0: Not triggered\\1: + Triggered */ + } bit; + } EVT_ST3; + + union { + __IOM uint32_t reg; /*!< Events trigger status clear register */ + + struct { + __OM uint32_t MCPWM1_EVT_TIMER1_STOP_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_timer1_stop trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM1_EVT_TIMER2_STOP_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_timer2_stop trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM1_EVT_TIMER0_TEZ_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_timer0_tez trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM1_EVT_TIMER1_TEZ_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_timer1_tez trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM1_EVT_TIMER2_TEZ_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_timer2_tez trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM1_EVT_TIMER0_TEP_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_timer0_tep trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM1_EVT_TIMER1_TEP_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_timer1_tep trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM1_EVT_TIMER2_TEP_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_timer2_tep trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM1_EVT_OP0_TEA_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_op0_tea trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM1_EVT_OP1_TEA_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_op1_tea trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM1_EVT_OP2_TEA_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_op2_tea trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM1_EVT_OP0_TEB_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_op0_teb trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM1_EVT_OP1_TEB_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_op1_teb trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM1_EVT_OP2_TEB_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_op2_teb trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM1_EVT_F0_ST_CLR : 1; /*!< Configures whether or not to clear MCPWM1_evt_f0 trigger status.\\0: + Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM1_EVT_F1_ST_CLR : 1; /*!< Configures whether or not to clear MCPWM1_evt_f1 trigger status.\\0: + Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM1_EVT_F2_ST_CLR : 1; /*!< Configures whether or not to clear MCPWM1_evt_f2 trigger status.\\0: + Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM1_EVT_F0_CLR_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_f0_clr trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM1_EVT_F1_CLR_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_f1_clr trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM1_EVT_F2_CLR_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_f2_clr trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM1_EVT_TZ0_CBC_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_tz0_cbc trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM1_EVT_TZ1_CBC_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_tz1_cbc trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM1_EVT_TZ2_CBC_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_tz2_cbc trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM1_EVT_TZ0_OST_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_tz0_ost trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM1_EVT_TZ1_OST_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_tz1_ost trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM1_EVT_TZ2_OST_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_tz2_ost trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM1_EVT_CAP0_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_cap0 trigger status.\\0: + Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM1_EVT_CAP1_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_cap1 trigger status.\\0: + Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM1_EVT_CAP2_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_cap2 trigger status.\\0: + Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM1_EVT_OP0_TEE1_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_op0_tee1 trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM1_EVT_OP1_TEE1_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_op1_tee1 trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM1_EVT_OP2_TEE1_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_op2_tee1 trigger + status.\\0: Invalid, No effect\\1: Clear */ + } bit; + } EVT_ST3_CLR; + + union { + __IOM uint32_t reg; /*!< Events trigger status register */ + + struct { + __IOM uint32_t MCPWM1_EVT_OP0_TEE2_ST : 1;/*!< Represents MCPWM1_evt_op0_tee2 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM1_EVT_OP1_TEE2_ST : 1;/*!< Represents MCPWM1_evt_op1_tee2 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM1_EVT_OP2_TEE2_ST : 1;/*!< Represents MCPWM1_evt_op2_tee2 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t ADC_EVT_CONV_CMPLT0_ST : 1;/*!< Represents ADC_evt_conv_cmplt0 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t ADC_EVT_EQ_ABOVE_THRESH0_ST : 1;/*!< Represents ADC_evt_eq_above_thresh0 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t ADC_EVT_EQ_ABOVE_THRESH1_ST : 1;/*!< Represents ADC_evt_eq_above_thresh1 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t ADC_EVT_EQ_BELOW_THRESH0_ST : 1;/*!< Represents ADC_evt_eq_below_thresh0 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t ADC_EVT_EQ_BELOW_THRESH1_ST : 1;/*!< Represents ADC_evt_eq_below_thresh1 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t ADC_EVT_RESULT_DONE0_ST : 1;/*!< Represents ADC_evt_result_done0 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t ADC_EVT_STOPPED0_ST : 1; /*!< Represents ADC_evt_stopped0 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t ADC_EVT_STARTED0_ST : 1; /*!< Represents ADC_evt_started0 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t REGDMA_EVT_DONE0_ST : 1; /*!< Represents REGDMA_evt_done0 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t REGDMA_EVT_DONE1_ST : 1; /*!< Represents REGDMA_evt_done1 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t REGDMA_EVT_DONE2_ST : 1; /*!< Represents REGDMA_evt_done2 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t REGDMA_EVT_DONE3_ST : 1; /*!< Represents REGDMA_evt_done3 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t REGDMA_EVT_ERR0_ST : 1; /*!< Represents REGDMA_evt_err0 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t REGDMA_EVT_ERR1_ST : 1; /*!< Represents REGDMA_evt_err1 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t REGDMA_EVT_ERR2_ST : 1; /*!< Represents REGDMA_evt_err2 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t REGDMA_EVT_ERR3_ST : 1; /*!< Represents REGDMA_evt_err3 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t TMPSNSR_EVT_OVER_LIMIT_ST : 1;/*!< Represents TMPSNSR_evt_over_limit trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t I2S0_EVT_RX_DONE_ST : 1; /*!< Represents I2S0_evt_rx_done trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t I2S0_EVT_TX_DONE_ST : 1; /*!< Represents I2S0_evt_tx_done trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t I2S0_EVT_X_WORDS_RECEIVED_ST : 1;/*!< Represents I2S0_evt_x_words_received trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t I2S0_EVT_X_WORDS_SENT_ST : 1;/*!< Represents I2S0_evt_x_words_sent trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t I2S1_EVT_RX_DONE_ST : 1; /*!< Represents I2S1_evt_rx_done trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t I2S1_EVT_TX_DONE_ST : 1; /*!< Represents I2S1_evt_tx_done trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t I2S1_EVT_X_WORDS_RECEIVED_ST : 1;/*!< Represents I2S1_evt_x_words_received trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t I2S1_EVT_X_WORDS_SENT_ST : 1;/*!< Represents I2S1_evt_x_words_sent trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t I2S2_EVT_RX_DONE_ST : 1; /*!< Represents I2S2_evt_rx_done trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t I2S2_EVT_TX_DONE_ST : 1; /*!< Represents I2S2_evt_tx_done trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t I2S2_EVT_X_WORDS_RECEIVED_ST : 1;/*!< Represents I2S2_evt_x_words_received trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t I2S2_EVT_X_WORDS_SENT_ST : 1;/*!< Represents I2S2_evt_x_words_sent trigger status.\\0: Not triggered\\1: + Triggered */ + } bit; + } EVT_ST4; + + union { + __IOM uint32_t reg; /*!< Events trigger status clear register */ + + struct { + __OM uint32_t MCPWM1_EVT_OP0_TEE2_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_op0_tee2 trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM1_EVT_OP1_TEE2_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_op1_tee2 trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM1_EVT_OP2_TEE2_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_op2_tee2 trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t ADC_EVT_CONV_CMPLT0_ST_CLR : 1;/*!< Configures whether or not to clear ADC_evt_conv_cmplt0 trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR : 1;/*!< Configures whether or not to clear ADC_evt_eq_above_thresh0 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR : 1;/*!< Configures whether or not to clear ADC_evt_eq_above_thresh1 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t ADC_EVT_EQ_BELOW_THRESH0_ST_CLR : 1;/*!< Configures whether or not to clear ADC_evt_eq_below_thresh0 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t ADC_EVT_EQ_BELOW_THRESH1_ST_CLR : 1;/*!< Configures whether or not to clear ADC_evt_eq_below_thresh1 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t ADC_EVT_RESULT_DONE0_ST_CLR : 1;/*!< Configures whether or not to clear ADC_evt_result_done0 trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t ADC_EVT_STOPPED0_ST_CLR : 1;/*!< Configures whether or not to clear ADC_evt_stopped0 trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t ADC_EVT_STARTED0_ST_CLR : 1;/*!< Configures whether or not to clear ADC_evt_started0 trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t REGDMA_EVT_DONE0_ST_CLR : 1;/*!< Configures whether or not to clear REGDMA_evt_done0 trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t REGDMA_EVT_DONE1_ST_CLR : 1;/*!< Configures whether or not to clear REGDMA_evt_done1 trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t REGDMA_EVT_DONE2_ST_CLR : 1;/*!< Configures whether or not to clear REGDMA_evt_done2 trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t REGDMA_EVT_DONE3_ST_CLR : 1;/*!< Configures whether or not to clear REGDMA_evt_done3 trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t REGDMA_EVT_ERR0_ST_CLR : 1;/*!< Configures whether or not to clear REGDMA_evt_err0 trigger status.\\0: + Invalid, No effect\\1: Clear */ + __OM uint32_t REGDMA_EVT_ERR1_ST_CLR : 1;/*!< Configures whether or not to clear REGDMA_evt_err1 trigger status.\\0: + Invalid, No effect\\1: Clear */ + __OM uint32_t REGDMA_EVT_ERR2_ST_CLR : 1;/*!< Configures whether or not to clear REGDMA_evt_err2 trigger status.\\0: + Invalid, No effect\\1: Clear */ + __OM uint32_t REGDMA_EVT_ERR3_ST_CLR : 1;/*!< Configures whether or not to clear REGDMA_evt_err3 trigger status.\\0: + Invalid, No effect\\1: Clear */ + __OM uint32_t TMPSNSR_EVT_OVER_LIMIT_ST_CLR : 1;/*!< Configures whether or not to clear TMPSNSR_evt_over_limit trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t I2S0_EVT_RX_DONE_ST_CLR : 1;/*!< Configures whether or not to clear I2S0_evt_rx_done trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t I2S0_EVT_TX_DONE_ST_CLR : 1;/*!< Configures whether or not to clear I2S0_evt_tx_done trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t I2S0_EVT_X_WORDS_RECEIVED_ST_CLR : 1;/*!< Configures whether or not to clear I2S0_evt_x_words_received + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t I2S0_EVT_X_WORDS_SENT_ST_CLR : 1;/*!< Configures whether or not to clear I2S0_evt_x_words_sent trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t I2S1_EVT_RX_DONE_ST_CLR : 1;/*!< Configures whether or not to clear I2S1_evt_rx_done trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t I2S1_EVT_TX_DONE_ST_CLR : 1;/*!< Configures whether or not to clear I2S1_evt_tx_done trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t I2S1_EVT_X_WORDS_RECEIVED_ST_CLR : 1;/*!< Configures whether or not to clear I2S1_evt_x_words_received + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t I2S1_EVT_X_WORDS_SENT_ST_CLR : 1;/*!< Configures whether or not to clear I2S1_evt_x_words_sent trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t I2S2_EVT_RX_DONE_ST_CLR : 1;/*!< Configures whether or not to clear I2S2_evt_rx_done trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t I2S2_EVT_TX_DONE_ST_CLR : 1;/*!< Configures whether or not to clear I2S2_evt_tx_done trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t I2S2_EVT_X_WORDS_RECEIVED_ST_CLR : 1;/*!< Configures whether or not to clear I2S2_evt_x_words_received + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t I2S2_EVT_X_WORDS_SENT_ST_CLR : 1;/*!< Configures whether or not to clear I2S2_evt_x_words_sent trigger + status.\\0: Invalid, No effect\\1: Clear */ + } bit; + } EVT_ST4_CLR; + + union { + __IOM uint32_t reg; /*!< Events trigger status register */ + + struct { + __IOM uint32_t ULP_EVT_ERR_INTR_ST : 1; /*!< Represents ULP_evt_err_intr trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t ULP_EVT_HALT_ST : 1; /*!< Represents ULP_evt_halt trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t ULP_EVT_START_INTR_ST : 1; /*!< Represents ULP_evt_start_intr trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t RTC_EVT_TICK_ST : 1; /*!< Represents RTC_evt_tick trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t RTC_EVT_OVF_ST : 1; /*!< Represents RTC_evt_ovf trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t RTC_EVT_CMP_ST : 1; /*!< Represents RTC_evt_cmp trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t PDMA_AHB_EVT_IN_DONE_CH0_ST : 1;/*!< Represents PDMA_AHB_evt_in_done_ch0 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t PDMA_AHB_EVT_IN_DONE_CH1_ST : 1;/*!< Represents PDMA_AHB_evt_in_done_ch1 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t PDMA_AHB_EVT_IN_DONE_CH2_ST : 1;/*!< Represents PDMA_AHB_evt_in_done_ch2 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST : 1;/*!< Represents PDMA_AHB_evt_in_suc_eof_ch0 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST : 1;/*!< Represents PDMA_AHB_evt_in_suc_eof_ch1 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST : 1;/*!< Represents PDMA_AHB_evt_in_suc_eof_ch2 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST : 1;/*!< Represents PDMA_AHB_evt_in_fifo_empty_ch0 trigger status.\\0: + Not triggered\\1: Triggered */ + __IOM uint32_t PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST : 1;/*!< Represents PDMA_AHB_evt_in_fifo_empty_ch1 trigger status.\\0: + Not triggered\\1: Triggered */ + __IOM uint32_t PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST : 1;/*!< Represents PDMA_AHB_evt_in_fifo_empty_ch2 trigger status.\\0: + Not triggered\\1: Triggered */ + __IOM uint32_t PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST : 1;/*!< Represents PDMA_AHB_evt_in_fifo_full_ch0 trigger status.\\0: + Not triggered\\1: Triggered */ + __IOM uint32_t PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST : 1;/*!< Represents PDMA_AHB_evt_in_fifo_full_ch1 trigger status.\\0: + Not triggered\\1: Triggered */ + __IOM uint32_t PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST : 1;/*!< Represents PDMA_AHB_evt_in_fifo_full_ch2 trigger status.\\0: + Not triggered\\1: Triggered */ + __IOM uint32_t PDMA_AHB_EVT_OUT_DONE_CH0_ST : 1;/*!< Represents PDMA_AHB_evt_out_done_ch0 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t PDMA_AHB_EVT_OUT_DONE_CH1_ST : 1;/*!< Represents PDMA_AHB_evt_out_done_ch1 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t PDMA_AHB_EVT_OUT_DONE_CH2_ST : 1;/*!< Represents PDMA_AHB_evt_out_done_ch2 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t PDMA_AHB_EVT_OUT_EOF_CH0_ST : 1;/*!< Represents PDMA_AHB_evt_out_eof_ch0 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t PDMA_AHB_EVT_OUT_EOF_CH1_ST : 1;/*!< Represents PDMA_AHB_evt_out_eof_ch1 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t PDMA_AHB_EVT_OUT_EOF_CH2_ST : 1;/*!< Represents PDMA_AHB_evt_out_eof_ch2 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST : 1;/*!< Represents PDMA_AHB_evt_out_total_eof_ch0 trigger status.\\0: + Not triggered\\1: Triggered */ + __IOM uint32_t PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST : 1;/*!< Represents PDMA_AHB_evt_out_total_eof_ch1 trigger status.\\0: + Not triggered\\1: Triggered */ + __IOM uint32_t PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST : 1;/*!< Represents PDMA_AHB_evt_out_total_eof_ch2 trigger status.\\0: + Not triggered\\1: Triggered */ + __IOM uint32_t PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST : 1;/*!< Represents PDMA_AHB_evt_out_fifo_empty_ch0 trigger status.\\0: + Not triggered\\1: Triggered */ + __IOM uint32_t PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST : 1;/*!< Represents PDMA_AHB_evt_out_fifo_empty_ch1 trigger status.\\0: + Not triggered\\1: Triggered */ + __IOM uint32_t PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST : 1;/*!< Represents PDMA_AHB_evt_out_fifo_empty_ch2 trigger status.\\0: + Not triggered\\1: Triggered */ + __IOM uint32_t PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST : 1;/*!< Represents PDMA_AHB_evt_out_fifo_full_ch0 trigger status.\\0: + Not triggered\\1: Triggered */ + __IOM uint32_t PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST : 1;/*!< Represents PDMA_AHB_evt_out_fifo_full_ch1 trigger status.\\0: + Not triggered\\1: Triggered */ + } bit; + } EVT_ST5; + + union { + __IOM uint32_t reg; /*!< Events trigger status clear register */ + + struct { + __OM uint32_t ULP_EVT_ERR_INTR_ST_CLR : 1;/*!< Configures whether or not to clear ULP_evt_err_intr trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t ULP_EVT_HALT_ST_CLR : 1; /*!< Configures whether or not to clear ULP_evt_halt trigger status.\\0: + Invalid, No effect\\1: Clear */ + __OM uint32_t ULP_EVT_START_INTR_ST_CLR : 1;/*!< Configures whether or not to clear ULP_evt_start_intr trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t RTC_EVT_TICK_ST_CLR : 1; /*!< Configures whether or not to clear RTC_evt_tick trigger status.\\0: + Invalid, No effect\\1: Clear */ + __OM uint32_t RTC_EVT_OVF_ST_CLR : 1; /*!< Configures whether or not to clear RTC_evt_ovf trigger status.\\0: + Invalid, No effect\\1: Clear */ + __OM uint32_t RTC_EVT_CMP_ST_CLR : 1; /*!< Configures whether or not to clear RTC_evt_cmp trigger status.\\0: + Invalid, No effect\\1: Clear */ + __OM uint32_t PDMA_AHB_EVT_IN_DONE_CH0_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_evt_in_done_ch0 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t PDMA_AHB_EVT_IN_DONE_CH1_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_evt_in_done_ch1 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t PDMA_AHB_EVT_IN_DONE_CH2_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_evt_in_done_ch2 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_evt_in_suc_eof_ch0 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_evt_in_suc_eof_ch1 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_evt_in_suc_eof_ch2 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_evt_in_fifo_empty_ch0 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_evt_in_fifo_empty_ch1 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_evt_in_fifo_empty_ch2 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_evt_in_fifo_full_ch0 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_evt_in_fifo_full_ch1 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_evt_in_fifo_full_ch2 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t PDMA_AHB_EVT_OUT_DONE_CH0_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_evt_out_done_ch0 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t PDMA_AHB_EVT_OUT_DONE_CH1_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_evt_out_done_ch1 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t PDMA_AHB_EVT_OUT_DONE_CH2_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_evt_out_done_ch2 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t PDMA_AHB_EVT_OUT_EOF_CH0_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_evt_out_eof_ch0 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t PDMA_AHB_EVT_OUT_EOF_CH1_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_evt_out_eof_ch1 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t PDMA_AHB_EVT_OUT_EOF_CH2_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_evt_out_eof_ch2 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_evt_out_total_eof_ch0 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_evt_out_total_eof_ch1 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_evt_out_total_eof_ch2 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_evt_out_fifo_empty_ch0 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_evt_out_fifo_empty_ch1 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_evt_out_fifo_empty_ch2 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_evt_out_fifo_full_ch0 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_evt_out_fifo_full_ch1 + trigger status.\\0: Invalid, No effect\\1: Clear */ + } bit; + } EVT_ST5_CLR; + + union { + __IOM uint32_t reg; /*!< Events trigger status register */ + + struct { + __IOM uint32_t PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST : 1;/*!< Represents PDMA_AHB_evt_out_fifo_full_ch2 trigger status.\\0: + Not triggered\\1: Triggered */ + __IOM uint32_t PDMA_AXI_EVT_IN_DONE_CH0_ST : 1;/*!< Represents PDMA_AXI_evt_in_done_ch0 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t PDMA_AXI_EVT_IN_DONE_CH1_ST : 1;/*!< Represents PDMA_AXI_evt_in_done_ch1 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t PDMA_AXI_EVT_IN_DONE_CH2_ST : 1;/*!< Represents PDMA_AXI_evt_in_done_ch2 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST : 1;/*!< Represents PDMA_AXI_evt_in_suc_eof_ch0 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST : 1;/*!< Represents PDMA_AXI_evt_in_suc_eof_ch1 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST : 1;/*!< Represents PDMA_AXI_evt_in_suc_eof_ch2 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST : 1;/*!< Represents PDMA_AXI_evt_in_fifo_empty_ch0 trigger status.\\0: + Not triggered\\1: Triggered */ + __IOM uint32_t PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST : 1;/*!< Represents PDMA_AXI_evt_in_fifo_empty_ch1 trigger status.\\0: + Not triggered\\1: Triggered */ + __IOM uint32_t PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST : 1;/*!< Represents PDMA_AXI_evt_in_fifo_empty_ch2 trigger status.\\0: + Not triggered\\1: Triggered */ + __IOM uint32_t PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST : 1;/*!< Represents PDMA_AXI_evt_in_fifo_full_ch0 trigger status.\\0: + Not triggered\\1: Triggered */ + __IOM uint32_t PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST : 1;/*!< Represents PDMA_AXI_evt_in_fifo_full_ch1 trigger status.\\0: + Not triggered\\1: Triggered */ + __IOM uint32_t PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST : 1;/*!< Represents PDMA_AXI_evt_in_fifo_full_ch2 trigger status.\\0: + Not triggered\\1: Triggered */ + __IOM uint32_t PDMA_AXI_EVT_OUT_DONE_CH0_ST : 1;/*!< Represents PDMA_AXI_evt_out_done_ch0 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t PDMA_AXI_EVT_OUT_DONE_CH1_ST : 1;/*!< Represents PDMA_AXI_evt_out_done_ch1 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t PDMA_AXI_EVT_OUT_DONE_CH2_ST : 1;/*!< Represents PDMA_AXI_evt_out_done_ch2 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t PDMA_AXI_EVT_OUT_EOF_CH0_ST : 1;/*!< Represents PDMA_AXI_evt_out_eof_ch0 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t PDMA_AXI_EVT_OUT_EOF_CH1_ST : 1;/*!< Represents PDMA_AXI_evt_out_eof_ch1 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t PDMA_AXI_EVT_OUT_EOF_CH2_ST : 1;/*!< Represents PDMA_AXI_evt_out_eof_ch2 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST : 1;/*!< Represents PDMA_AXI_evt_out_total_eof_ch0 trigger status.\\0: + Not triggered\\1: Triggered */ + __IOM uint32_t PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST : 1;/*!< Represents PDMA_AXI_evt_out_total_eof_ch1 trigger status.\\0: + Not triggered\\1: Triggered */ + __IOM uint32_t PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST : 1;/*!< Represents PDMA_AXI_evt_out_total_eof_ch2 trigger status.\\0: + Not triggered\\1: Triggered */ + __IOM uint32_t PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST : 1;/*!< Represents PDMA_AXI_evt_out_fifo_empty_ch0 trigger status.\\0: + Not triggered\\1: Triggered */ + __IOM uint32_t PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST : 1;/*!< Represents PDMA_AXI_evt_out_fifo_empty_ch1 trigger status.\\0: + Not triggered\\1: Triggered */ + __IOM uint32_t PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST : 1;/*!< Represents PDMA_AXI_evt_out_fifo_empty_ch2 trigger status.\\0: + Not triggered\\1: Triggered */ + __IOM uint32_t PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST : 1;/*!< Represents PDMA_AXI_evt_out_fifo_full_ch0 trigger status.\\0: + Not triggered\\1: Triggered */ + __IOM uint32_t PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST : 1;/*!< Represents PDMA_AXI_evt_out_fifo_full_ch1 trigger status.\\0: + Not triggered\\1: Triggered */ + __IOM uint32_t PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST : 1;/*!< Represents PDMA_AXI_evt_out_fifo_full_ch2 trigger status.\\0: + Not triggered\\1: Triggered */ + __IOM uint32_t PMU_EVT_SLEEP_WEEKUP_ST : 1;/*!< Represents PMU_evt_sleep_weekup trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t DMA2D_EVT_IN_DONE_CH0_ST : 1;/*!< Represents DMA2D_evt_in_done_ch0 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t DMA2D_EVT_IN_DONE_CH1_ST : 1;/*!< Represents DMA2D_evt_in_done_ch1 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t DMA2D_EVT_IN_SUC_EOF_CH0_ST : 1;/*!< Represents DMA2D_evt_in_suc_eof_ch0 trigger status.\\0: Not + triggered\\1: Triggered */ + } bit; + } EVT_ST6; + + union { + __IOM uint32_t reg; /*!< Events trigger status clear register */ + + struct { + __OM uint32_t PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_evt_out_fifo_full_ch2 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t PDMA_AXI_EVT_IN_DONE_CH0_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_evt_in_done_ch0 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t PDMA_AXI_EVT_IN_DONE_CH1_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_evt_in_done_ch1 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t PDMA_AXI_EVT_IN_DONE_CH2_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_evt_in_done_ch2 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_evt_in_suc_eof_ch0 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_evt_in_suc_eof_ch1 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_evt_in_suc_eof_ch2 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_evt_in_fifo_empty_ch0 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_evt_in_fifo_empty_ch1 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_evt_in_fifo_empty_ch2 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_evt_in_fifo_full_ch0 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_evt_in_fifo_full_ch1 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_evt_in_fifo_full_ch2 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t PDMA_AXI_EVT_OUT_DONE_CH0_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_evt_out_done_ch0 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t PDMA_AXI_EVT_OUT_DONE_CH1_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_evt_out_done_ch1 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t PDMA_AXI_EVT_OUT_DONE_CH2_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_evt_out_done_ch2 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t PDMA_AXI_EVT_OUT_EOF_CH0_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_evt_out_eof_ch0 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t PDMA_AXI_EVT_OUT_EOF_CH1_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_evt_out_eof_ch1 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t PDMA_AXI_EVT_OUT_EOF_CH2_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_evt_out_eof_ch2 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_evt_out_total_eof_ch0 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_evt_out_total_eof_ch1 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_evt_out_total_eof_ch2 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_evt_out_fifo_empty_ch0 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_evt_out_fifo_empty_ch1 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_evt_out_fifo_empty_ch2 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_evt_out_fifo_full_ch0 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_evt_out_fifo_full_ch1 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_evt_out_fifo_full_ch2 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t PMU_EVT_SLEEP_WEEKUP_ST_CLR : 1;/*!< Configures whether or not to clear PMU_evt_sleep_weekup trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t DMA2D_EVT_IN_DONE_CH0_ST_CLR : 1;/*!< Configures whether or not to clear DMA2D_evt_in_done_ch0 trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t DMA2D_EVT_IN_DONE_CH1_ST_CLR : 1;/*!< Configures whether or not to clear DMA2D_evt_in_done_ch1 trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t DMA2D_EVT_IN_SUC_EOF_CH0_ST_CLR : 1;/*!< Configures whether or not to clear DMA2D_evt_in_suc_eof_ch0 + trigger status.\\0: Invalid, No effect\\1: Clear */ + } bit; + } EVT_ST6_CLR; + + union { + __IOM uint32_t reg; /*!< Events trigger status register */ + + struct { + __IOM uint32_t DMA2D_EVT_IN_SUC_EOF_CH1_ST : 1;/*!< Represents DMA2D_evt_in_suc_eof_ch1 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t DMA2D_EVT_OUT_DONE_CH0_ST : 1;/*!< Represents DMA2D_evt_out_done_ch0 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t DMA2D_EVT_OUT_DONE_CH1_ST : 1;/*!< Represents DMA2D_evt_out_done_ch1 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t DMA2D_EVT_OUT_DONE_CH2_ST : 1;/*!< Represents DMA2D_evt_out_done_ch2 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t DMA2D_EVT_OUT_EOF_CH0_ST : 1;/*!< Represents DMA2D_evt_out_eof_ch0 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t DMA2D_EVT_OUT_EOF_CH1_ST : 1;/*!< Represents DMA2D_evt_out_eof_ch1 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t DMA2D_EVT_OUT_EOF_CH2_ST : 1;/*!< Represents DMA2D_evt_out_eof_ch2 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST : 1;/*!< Represents DMA2D_evt_out_total_eof_ch0 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST : 1;/*!< Represents DMA2D_evt_out_total_eof_ch1 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST : 1;/*!< Represents DMA2D_evt_out_total_eof_ch2 trigger status.\\0: Not + triggered\\1: Triggered */ + uint32_t : 22; + } bit; + } EVT_ST7; + + union { + __IOM uint32_t reg; /*!< Events trigger status clear register */ + + struct { + __OM uint32_t DMA2D_EVT_IN_SUC_EOF_CH1_ST_CLR : 1;/*!< Configures whether or not to clear DMA2D_evt_in_suc_eof_ch1 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t DMA2D_EVT_OUT_DONE_CH0_ST_CLR : 1;/*!< Configures whether or not to clear DMA2D_evt_out_done_ch0 trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t DMA2D_EVT_OUT_DONE_CH1_ST_CLR : 1;/*!< Configures whether or not to clear DMA2D_evt_out_done_ch1 trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t DMA2D_EVT_OUT_DONE_CH2_ST_CLR : 1;/*!< Configures whether or not to clear DMA2D_evt_out_done_ch2 trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t DMA2D_EVT_OUT_EOF_CH0_ST_CLR : 1;/*!< Configures whether or not to clear DMA2D_evt_out_eof_ch0 trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t DMA2D_EVT_OUT_EOF_CH1_ST_CLR : 1;/*!< Configures whether or not to clear DMA2D_evt_out_eof_ch1 trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t DMA2D_EVT_OUT_EOF_CH2_ST_CLR : 1;/*!< Configures whether or not to clear DMA2D_evt_out_eof_ch2 trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST_CLR : 1;/*!< Configures whether or not to clear DMA2D_evt_out_total_eof_ch0 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST_CLR : 1;/*!< Configures whether or not to clear DMA2D_evt_out_total_eof_ch1 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST_CLR : 1;/*!< Configures whether or not to clear DMA2D_evt_out_total_eof_ch2 + trigger status.\\0: Invalid, No effect\\1: Clear */ + uint32_t : 22; + } bit; + } EVT_ST7_CLR; + + union { + __IOM uint32_t reg; /*!< Tasks trigger status register */ + + struct { + __IOM uint32_t GPIO_TASK_CH0_SET_ST : 1; /*!< Represents GPIO_task_ch0_set trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t GPIO_TASK_CH1_SET_ST : 1; /*!< Represents GPIO_task_ch1_set trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t GPIO_TASK_CH2_SET_ST : 1; /*!< Represents GPIO_task_ch2_set trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t GPIO_TASK_CH3_SET_ST : 1; /*!< Represents GPIO_task_ch3_set trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t GPIO_TASK_CH4_SET_ST : 1; /*!< Represents GPIO_task_ch4_set trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t GPIO_TASK_CH5_SET_ST : 1; /*!< Represents GPIO_task_ch5_set trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t GPIO_TASK_CH6_SET_ST : 1; /*!< Represents GPIO_task_ch6_set trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t GPIO_TASK_CH7_SET_ST : 1; /*!< Represents GPIO_task_ch7_set trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t GPIO_TASK_CH0_CLEAR_ST : 1;/*!< Represents GPIO_task_ch0_clear trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t GPIO_TASK_CH1_CLEAR_ST : 1;/*!< Represents GPIO_task_ch1_clear trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t GPIO_TASK_CH2_CLEAR_ST : 1;/*!< Represents GPIO_task_ch2_clear trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t GPIO_TASK_CH3_CLEAR_ST : 1;/*!< Represents GPIO_task_ch3_clear trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t GPIO_TASK_CH4_CLEAR_ST : 1;/*!< Represents GPIO_task_ch4_clear trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t GPIO_TASK_CH5_CLEAR_ST : 1;/*!< Represents GPIO_task_ch5_clear trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t GPIO_TASK_CH6_CLEAR_ST : 1;/*!< Represents GPIO_task_ch6_clear trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t GPIO_TASK_CH7_CLEAR_ST : 1;/*!< Represents GPIO_task_ch7_clear trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t GPIO_TASK_CH0_TOGGLE_ST : 1;/*!< Represents GPIO_task_ch0_toggle trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t GPIO_TASK_CH1_TOGGLE_ST : 1;/*!< Represents GPIO_task_ch1_toggle trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t GPIO_TASK_CH2_TOGGLE_ST : 1;/*!< Represents GPIO_task_ch2_toggle trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t GPIO_TASK_CH3_TOGGLE_ST : 1;/*!< Represents GPIO_task_ch3_toggle trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t GPIO_TASK_CH4_TOGGLE_ST : 1;/*!< Represents GPIO_task_ch4_toggle trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t GPIO_TASK_CH5_TOGGLE_ST : 1;/*!< Represents GPIO_task_ch5_toggle trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t GPIO_TASK_CH6_TOGGLE_ST : 1;/*!< Represents GPIO_task_ch6_toggle trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t GPIO_TASK_CH7_TOGGLE_ST : 1;/*!< Represents GPIO_task_ch7_toggle trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t LEDC_TASK_TIMER0_RES_UPDATE_ST : 1;/*!< Represents LEDC_task_timer0_res_update trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t LEDC_TASK_TIMER1_RES_UPDATE_ST : 1;/*!< Represents LEDC_task_timer1_res_update trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t LEDC_TASK_TIMER2_RES_UPDATE_ST : 1;/*!< Represents LEDC_task_timer2_res_update trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t LEDC_TASK_TIMER3_RES_UPDATE_ST : 1;/*!< Represents LEDC_task_timer3_res_update trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST : 1;/*!< Represents LEDC_task_duty_scale_update_ch0 trigger status.\\0: + Not triggered\\1: Triggered */ + __IOM uint32_t LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST : 1;/*!< Represents LEDC_task_duty_scale_update_ch1 trigger status.\\0: + Not triggered\\1: Triggered */ + __IOM uint32_t LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST : 1;/*!< Represents LEDC_task_duty_scale_update_ch2 trigger status.\\0: + Not triggered\\1: Triggered */ + __IOM uint32_t LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST : 1;/*!< Represents LEDC_task_duty_scale_update_ch3 trigger status.\\0: + Not triggered\\1: Triggered */ + } bit; + } TASK_ST0; + + union { + __IOM uint32_t reg; /*!< Tasks trigger status clear register */ + + struct { + __OM uint32_t GPIO_TASK_CH0_SET_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_task_ch0_set trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t GPIO_TASK_CH1_SET_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_task_ch1_set trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t GPIO_TASK_CH2_SET_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_task_ch2_set trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t GPIO_TASK_CH3_SET_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_task_ch3_set trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t GPIO_TASK_CH4_SET_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_task_ch4_set trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t GPIO_TASK_CH5_SET_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_task_ch5_set trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t GPIO_TASK_CH6_SET_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_task_ch6_set trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t GPIO_TASK_CH7_SET_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_task_ch7_set trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t GPIO_TASK_CH0_CLEAR_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_task_ch0_clear trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t GPIO_TASK_CH1_CLEAR_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_task_ch1_clear trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t GPIO_TASK_CH2_CLEAR_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_task_ch2_clear trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t GPIO_TASK_CH3_CLEAR_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_task_ch3_clear trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t GPIO_TASK_CH4_CLEAR_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_task_ch4_clear trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t GPIO_TASK_CH5_CLEAR_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_task_ch5_clear trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t GPIO_TASK_CH6_CLEAR_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_task_ch6_clear trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t GPIO_TASK_CH7_CLEAR_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_task_ch7_clear trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t GPIO_TASK_CH0_TOGGLE_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_task_ch0_toggle trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t GPIO_TASK_CH1_TOGGLE_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_task_ch1_toggle trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t GPIO_TASK_CH2_TOGGLE_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_task_ch2_toggle trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t GPIO_TASK_CH3_TOGGLE_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_task_ch3_toggle trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t GPIO_TASK_CH4_TOGGLE_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_task_ch4_toggle trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t GPIO_TASK_CH5_TOGGLE_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_task_ch5_toggle trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t GPIO_TASK_CH6_TOGGLE_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_task_ch6_toggle trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t GPIO_TASK_CH7_TOGGLE_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_task_ch7_toggle trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_timer0_res_update + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_timer1_res_update + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_timer2_res_update + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_timer3_res_update + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_duty_scale_update_ch0 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_duty_scale_update_ch1 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_duty_scale_update_ch2 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_duty_scale_update_ch3 + trigger status.\\0: Invalid, No effect\\1: Clear */ + } bit; + } TASK_ST0_CLR; + + union { + __IOM uint32_t reg; /*!< Tasks trigger status register */ + + struct { + __IOM uint32_t LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST : 1;/*!< Represents LEDC_task_duty_scale_update_ch4 trigger status.\\0: + Not triggered\\1: Triggered */ + __IOM uint32_t LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST : 1;/*!< Represents LEDC_task_duty_scale_update_ch5 trigger status.\\0: + Not triggered\\1: Triggered */ + __IOM uint32_t LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST : 1;/*!< Represents LEDC_task_duty_scale_update_ch6 trigger status.\\0: + Not triggered\\1: Triggered */ + __IOM uint32_t LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST : 1;/*!< Represents LEDC_task_duty_scale_update_ch7 trigger status.\\0: + Not triggered\\1: Triggered */ + __IOM uint32_t LEDC_TASK_TIMER0_CAP_ST : 1;/*!< Represents LEDC_task_timer0_cap trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t LEDC_TASK_TIMER1_CAP_ST : 1;/*!< Represents LEDC_task_timer1_cap trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t LEDC_TASK_TIMER2_CAP_ST : 1;/*!< Represents LEDC_task_timer2_cap trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t LEDC_TASK_TIMER3_CAP_ST : 1;/*!< Represents LEDC_task_timer3_cap trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t LEDC_TASK_SIG_OUT_DIS_CH0_ST : 1;/*!< Represents LEDC_task_sig_out_dis_ch0 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t LEDC_TASK_SIG_OUT_DIS_CH1_ST : 1;/*!< Represents LEDC_task_sig_out_dis_ch1 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t LEDC_TASK_SIG_OUT_DIS_CH2_ST : 1;/*!< Represents LEDC_task_sig_out_dis_ch2 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t LEDC_TASK_SIG_OUT_DIS_CH3_ST : 1;/*!< Represents LEDC_task_sig_out_dis_ch3 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t LEDC_TASK_SIG_OUT_DIS_CH4_ST : 1;/*!< Represents LEDC_task_sig_out_dis_ch4 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t LEDC_TASK_SIG_OUT_DIS_CH5_ST : 1;/*!< Represents LEDC_task_sig_out_dis_ch5 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t LEDC_TASK_SIG_OUT_DIS_CH6_ST : 1;/*!< Represents LEDC_task_sig_out_dis_ch6 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t LEDC_TASK_SIG_OUT_DIS_CH7_ST : 1;/*!< Represents LEDC_task_sig_out_dis_ch7 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t LEDC_TASK_OVF_CNT_RST_CH0_ST : 1;/*!< Represents LEDC_task_ovf_cnt_rst_ch0 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t LEDC_TASK_OVF_CNT_RST_CH1_ST : 1;/*!< Represents LEDC_task_ovf_cnt_rst_ch1 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t LEDC_TASK_OVF_CNT_RST_CH2_ST : 1;/*!< Represents LEDC_task_ovf_cnt_rst_ch2 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t LEDC_TASK_OVF_CNT_RST_CH3_ST : 1;/*!< Represents LEDC_task_ovf_cnt_rst_ch3 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t LEDC_TASK_OVF_CNT_RST_CH4_ST : 1;/*!< Represents LEDC_task_ovf_cnt_rst_ch4 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t LEDC_TASK_OVF_CNT_RST_CH5_ST : 1;/*!< Represents LEDC_task_ovf_cnt_rst_ch5 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t LEDC_TASK_OVF_CNT_RST_CH6_ST : 1;/*!< Represents LEDC_task_ovf_cnt_rst_ch6 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t LEDC_TASK_OVF_CNT_RST_CH7_ST : 1;/*!< Represents LEDC_task_ovf_cnt_rst_ch7 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t LEDC_TASK_TIMER0_RST_ST : 1;/*!< Represents LEDC_task_timer0_rst trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t LEDC_TASK_TIMER1_RST_ST : 1;/*!< Represents LEDC_task_timer1_rst trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t LEDC_TASK_TIMER2_RST_ST : 1;/*!< Represents LEDC_task_timer2_rst trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t LEDC_TASK_TIMER3_RST_ST : 1;/*!< Represents LEDC_task_timer3_rst trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t LEDC_TASK_TIMER0_RESUME_ST : 1;/*!< Represents LEDC_task_timer0_resume trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t LEDC_TASK_TIMER1_RESUME_ST : 1;/*!< Represents LEDC_task_timer1_resume trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t LEDC_TASK_TIMER2_RESUME_ST : 1;/*!< Represents LEDC_task_timer2_resume trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t LEDC_TASK_TIMER3_RESUME_ST : 1;/*!< Represents LEDC_task_timer3_resume trigger status.\\0: Not triggered\\1: + Triggered */ + } bit; + } TASK_ST1; + + union { + __IOM uint32_t reg; /*!< Tasks trigger status clear register */ + + struct { + __OM uint32_t LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_duty_scale_update_ch4 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_duty_scale_update_ch5 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_duty_scale_update_ch6 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_duty_scale_update_ch7 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_TIMER0_CAP_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_timer0_cap trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_TIMER1_CAP_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_timer1_cap trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_TIMER2_CAP_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_timer2_cap trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_TIMER3_CAP_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_timer3_cap trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_sig_out_dis_ch0 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_sig_out_dis_ch1 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_sig_out_dis_ch2 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_sig_out_dis_ch3 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_sig_out_dis_ch4 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_sig_out_dis_ch5 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_SIG_OUT_DIS_CH6_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_sig_out_dis_ch6 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_SIG_OUT_DIS_CH7_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_sig_out_dis_ch7 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch0 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch1 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch2 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch3 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch4 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch5 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_OVF_CNT_RST_CH6_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch6 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_OVF_CNT_RST_CH7_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch7 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_TIMER0_RST_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_timer0_rst trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_TIMER1_RST_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_timer1_rst trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_TIMER2_RST_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_timer2_rst trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_TIMER3_RST_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_timer3_rst trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_TIMER0_RESUME_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_timer0_resume trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_TIMER1_RESUME_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_timer1_resume trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_TIMER2_RESUME_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_timer2_resume trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_TIMER3_RESUME_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_timer3_resume trigger + status.\\0: Invalid, No effect\\1: Clear */ + } bit; + } TASK_ST1_CLR; + + union { + __IOM uint32_t reg; /*!< Tasks trigger status register */ + + struct { + __IOM uint32_t LEDC_TASK_TIMER0_PAUSE_ST : 1;/*!< Represents LEDC_task_timer0_pause trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t LEDC_TASK_TIMER1_PAUSE_ST : 1;/*!< Represents LEDC_task_timer1_pause trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t LEDC_TASK_TIMER2_PAUSE_ST : 1;/*!< Represents LEDC_task_timer2_pause trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t LEDC_TASK_TIMER3_PAUSE_ST : 1;/*!< Represents LEDC_task_timer3_pause trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t LEDC_TASK_GAMMA_RESTART_CH0_ST : 1;/*!< Represents LEDC_task_gamma_restart_ch0 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t LEDC_TASK_GAMMA_RESTART_CH1_ST : 1;/*!< Represents LEDC_task_gamma_restart_ch1 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t LEDC_TASK_GAMMA_RESTART_CH2_ST : 1;/*!< Represents LEDC_task_gamma_restart_ch2 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t LEDC_TASK_GAMMA_RESTART_CH3_ST : 1;/*!< Represents LEDC_task_gamma_restart_ch3 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t LEDC_TASK_GAMMA_RESTART_CH4_ST : 1;/*!< Represents LEDC_task_gamma_restart_ch4 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t LEDC_TASK_GAMMA_RESTART_CH5_ST : 1;/*!< Represents LEDC_task_gamma_restart_ch5 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t LEDC_TASK_GAMMA_RESTART_CH6_ST : 1;/*!< Represents LEDC_task_gamma_restart_ch6 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t LEDC_TASK_GAMMA_RESTART_CH7_ST : 1;/*!< Represents LEDC_task_gamma_restart_ch7 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t LEDC_TASK_GAMMA_PAUSE_CH0_ST : 1;/*!< Represents LEDC_task_gamma_pause_ch0 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t LEDC_TASK_GAMMA_PAUSE_CH1_ST : 1;/*!< Represents LEDC_task_gamma_pause_ch1 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t LEDC_TASK_GAMMA_PAUSE_CH2_ST : 1;/*!< Represents LEDC_task_gamma_pause_ch2 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t LEDC_TASK_GAMMA_PAUSE_CH3_ST : 1;/*!< Represents LEDC_task_gamma_pause_ch3 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t LEDC_TASK_GAMMA_PAUSE_CH4_ST : 1;/*!< Represents LEDC_task_gamma_pause_ch4 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t LEDC_TASK_GAMMA_PAUSE_CH5_ST : 1;/*!< Represents LEDC_task_gamma_pause_ch5 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t LEDC_TASK_GAMMA_PAUSE_CH6_ST : 1;/*!< Represents LEDC_task_gamma_pause_ch6 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t LEDC_TASK_GAMMA_PAUSE_CH7_ST : 1;/*!< Represents LEDC_task_gamma_pause_ch7 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t LEDC_TASK_GAMMA_RESUME_CH0_ST : 1;/*!< Represents LEDC_task_gamma_resume_ch0 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t LEDC_TASK_GAMMA_RESUME_CH1_ST : 1;/*!< Represents LEDC_task_gamma_resume_ch1 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t LEDC_TASK_GAMMA_RESUME_CH2_ST : 1;/*!< Represents LEDC_task_gamma_resume_ch2 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t LEDC_TASK_GAMMA_RESUME_CH3_ST : 1;/*!< Represents LEDC_task_gamma_resume_ch3 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t LEDC_TASK_GAMMA_RESUME_CH4_ST : 1;/*!< Represents LEDC_task_gamma_resume_ch4 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t LEDC_TASK_GAMMA_RESUME_CH5_ST : 1;/*!< Represents LEDC_task_gamma_resume_ch5 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t LEDC_TASK_GAMMA_RESUME_CH6_ST : 1;/*!< Represents LEDC_task_gamma_resume_ch6 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t LEDC_TASK_GAMMA_RESUME_CH7_ST : 1;/*!< Represents LEDC_task_gamma_resume_ch7 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t TG0_TASK_CNT_START_TIMER0_ST : 1;/*!< Represents TG0_task_cnt_start_timer0 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t TG0_TASK_ALARM_START_TIMER0_ST : 1;/*!< Represents TG0_task_alarm_start_timer0 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t TG0_TASK_CNT_STOP_TIMER0_ST : 1;/*!< Represents TG0_task_cnt_stop_timer0 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t TG0_TASK_CNT_RELOAD_TIMER0_ST : 1;/*!< Represents TG0_task_cnt_reload_timer0 trigger status.\\0: Not + triggered\\1: Triggered */ + } bit; + } TASK_ST2; + + union { + __IOM uint32_t reg; /*!< Tasks trigger status clear register */ + + struct { + __OM uint32_t LEDC_TASK_TIMER0_PAUSE_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_timer0_pause trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_TIMER1_PAUSE_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_timer1_pause trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_TIMER2_PAUSE_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_timer2_pause trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_TIMER3_PAUSE_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_timer3_pause trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_gamma_restart_ch0 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_gamma_restart_ch1 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_gamma_restart_ch2 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_gamma_restart_ch3 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_gamma_restart_ch4 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_gamma_restart_ch5 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_GAMMA_RESTART_CH6_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_gamma_restart_ch6 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_GAMMA_RESTART_CH7_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_gamma_restart_ch7 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_gamma_pause_ch0 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_gamma_pause_ch1 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_gamma_pause_ch2 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_gamma_pause_ch3 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_gamma_pause_ch4 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_gamma_pause_ch5 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_GAMMA_PAUSE_CH6_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_gamma_pause_ch6 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_GAMMA_PAUSE_CH7_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_gamma_pause_ch7 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_gamma_resume_ch0 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_gamma_resume_ch1 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_gamma_resume_ch2 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_gamma_resume_ch3 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_gamma_resume_ch4 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_gamma_resume_ch5 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_GAMMA_RESUME_CH6_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_gamma_resume_ch6 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t LEDC_TASK_GAMMA_RESUME_CH7_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_gamma_resume_ch7 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t TG0_TASK_CNT_START_TIMER0_ST_CLR : 1;/*!< Configures whether or not to clear TG0_task_cnt_start_timer0 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t TG0_TASK_ALARM_START_TIMER0_ST_CLR : 1;/*!< Configures whether or not to clear TG0_task_alarm_start_timer0 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t TG0_TASK_CNT_STOP_TIMER0_ST_CLR : 1;/*!< Configures whether or not to clear TG0_task_cnt_stop_timer0 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR : 1;/*!< Configures whether or not to clear TG0_task_cnt_reload_timer0 + trigger status.\\0: Invalid, No effect\\1: Clear */ + } bit; + } TASK_ST2_CLR; + + union { + __IOM uint32_t reg; /*!< Tasks trigger status register */ + + struct { + __IOM uint32_t TG0_TASK_CNT_CAP_TIMER0_ST : 1;/*!< Represents TG0_task_cnt_cap_timer0 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t TG0_TASK_CNT_START_TIMER1_ST : 1;/*!< Represents TG0_task_cnt_start_timer1 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t TG0_TASK_ALARM_START_TIMER1_ST : 1;/*!< Represents TG0_task_alarm_start_timer1 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t TG0_TASK_CNT_STOP_TIMER1_ST : 1;/*!< Represents TG0_task_cnt_stop_timer1 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t TG0_TASK_CNT_RELOAD_TIMER1_ST : 1;/*!< Represents TG0_task_cnt_reload_timer1 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t TG0_TASK_CNT_CAP_TIMER1_ST : 1;/*!< Represents TG0_task_cnt_cap_timer1 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t TG1_TASK_CNT_START_TIMER0_ST : 1;/*!< Represents TG1_task_cnt_start_timer0 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t TG1_TASK_ALARM_START_TIMER0_ST : 1;/*!< Represents TG1_task_alarm_start_timer0 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t TG1_TASK_CNT_STOP_TIMER0_ST : 1;/*!< Represents TG1_task_cnt_stop_timer0 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t TG1_TASK_CNT_RELOAD_TIMER0_ST : 1;/*!< Represents TG1_task_cnt_reload_timer0 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t TG1_TASK_CNT_CAP_TIMER0_ST : 1;/*!< Represents TG1_task_cnt_cap_timer0 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t TG1_TASK_CNT_START_TIMER1_ST : 1;/*!< Represents TG1_task_cnt_start_timer1 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t TG1_TASK_ALARM_START_TIMER1_ST : 1;/*!< Represents TG1_task_alarm_start_timer1 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t TG1_TASK_CNT_STOP_TIMER1_ST : 1;/*!< Represents TG1_task_cnt_stop_timer1 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t TG1_TASK_CNT_RELOAD_TIMER1_ST : 1;/*!< Represents TG1_task_cnt_reload_timer1 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t TG1_TASK_CNT_CAP_TIMER1_ST : 1;/*!< Represents TG1_task_cnt_cap_timer1 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM0_TASK_CMPR0_A_UP_ST : 1;/*!< Represents MCPWM0_task_cmpr0_a_up trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM0_TASK_CMPR1_A_UP_ST : 1;/*!< Represents MCPWM0_task_cmpr1_a_up trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM0_TASK_CMPR2_A_UP_ST : 1;/*!< Represents MCPWM0_task_cmpr2_a_up trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM0_TASK_CMPR0_B_UP_ST : 1;/*!< Represents MCPWM0_task_cmpr0_b_up trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM0_TASK_CMPR1_B_UP_ST : 1;/*!< Represents MCPWM0_task_cmpr1_b_up trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM0_TASK_CMPR2_B_UP_ST : 1;/*!< Represents MCPWM0_task_cmpr2_b_up trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM0_TASK_GEN_STOP_ST : 1;/*!< Represents MCPWM0_task_gen_stop trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM0_TASK_TIMER0_SYN_ST : 1;/*!< Represents MCPWM0_task_timer0_syn trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM0_TASK_TIMER1_SYN_ST : 1;/*!< Represents MCPWM0_task_timer1_syn trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM0_TASK_TIMER2_SYN_ST : 1;/*!< Represents MCPWM0_task_timer2_syn trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM0_TASK_TIMER0_PERIOD_UP_ST : 1;/*!< Represents MCPWM0_task_timer0_period_up trigger status.\\0: + Not triggered\\1: Triggered */ + __IOM uint32_t MCPWM0_TASK_TIMER1_PERIOD_UP_ST : 1;/*!< Represents MCPWM0_task_timer1_period_up trigger status.\\0: + Not triggered\\1: Triggered */ + __IOM uint32_t MCPWM0_TASK_TIMER2_PERIOD_UP_ST : 1;/*!< Represents MCPWM0_task_timer2_period_up trigger status.\\0: + Not triggered\\1: Triggered */ + __IOM uint32_t MCPWM0_TASK_TZ0_OST_ST : 1;/*!< Represents MCPWM0_task_tz0_ost trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM0_TASK_TZ1_OST_ST : 1;/*!< Represents MCPWM0_task_tz1_ost trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM0_TASK_TZ2_OST_ST : 1;/*!< Represents MCPWM0_task_tz2_ost trigger status.\\0: Not triggered\\1: + Triggered */ + } bit; + } TASK_ST3; + + union { + __IOM uint32_t reg; /*!< Tasks trigger status clear register */ + + struct { + __OM uint32_t TG0_TASK_CNT_CAP_TIMER0_ST_CLR : 1;/*!< Configures whether or not to clear TG0_task_cnt_cap_timer0 trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t TG0_TASK_CNT_START_TIMER1_ST_CLR : 1;/*!< Configures whether or not to clear TG0_task_cnt_start_timer1 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t TG0_TASK_ALARM_START_TIMER1_ST_CLR : 1;/*!< Configures whether or not to clear TG0_task_alarm_start_timer1 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t TG0_TASK_CNT_STOP_TIMER1_ST_CLR : 1;/*!< Configures whether or not to clear TG0_task_cnt_stop_timer1 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR : 1;/*!< Configures whether or not to clear TG0_task_cnt_reload_timer1 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t TG0_TASK_CNT_CAP_TIMER1_ST_CLR : 1;/*!< Configures whether or not to clear TG0_task_cnt_cap_timer1 trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t TG1_TASK_CNT_START_TIMER0_ST_CLR : 1;/*!< Configures whether or not to clear TG1_task_cnt_start_timer0 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t TG1_TASK_ALARM_START_TIMER0_ST_CLR : 1;/*!< Configures whether or not to clear TG1_task_alarm_start_timer0 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t TG1_TASK_CNT_STOP_TIMER0_ST_CLR : 1;/*!< Configures whether or not to clear TG1_task_cnt_stop_timer0 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR : 1;/*!< Configures whether or not to clear TG1_task_cnt_reload_timer0 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t TG1_TASK_CNT_CAP_TIMER0_ST_CLR : 1;/*!< Configures whether or not to clear TG1_task_cnt_cap_timer0 trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t TG1_TASK_CNT_START_TIMER1_ST_CLR : 1;/*!< Configures whether or not to clear TG1_task_cnt_start_timer1 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t TG1_TASK_ALARM_START_TIMER1_ST_CLR : 1;/*!< Configures whether or not to clear TG1_task_alarm_start_timer1 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t TG1_TASK_CNT_STOP_TIMER1_ST_CLR : 1;/*!< Configures whether or not to clear TG1_task_cnt_stop_timer1 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR : 1;/*!< Configures whether or not to clear TG1_task_cnt_reload_timer1 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t TG1_TASK_CNT_CAP_TIMER1_ST_CLR : 1;/*!< Configures whether or not to clear TG1_task_cnt_cap_timer1 trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM0_TASK_CMPR0_A_UP_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_task_cmpr0_a_up trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM0_TASK_CMPR1_A_UP_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_task_cmpr1_a_up trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM0_TASK_CMPR2_A_UP_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_task_cmpr2_a_up trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM0_TASK_CMPR0_B_UP_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_task_cmpr0_b_up trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM0_TASK_CMPR1_B_UP_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_task_cmpr1_b_up trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM0_TASK_CMPR2_B_UP_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_task_cmpr2_b_up trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM0_TASK_GEN_STOP_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_task_gen_stop trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM0_TASK_TIMER0_SYN_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_task_timer0_syn trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM0_TASK_TIMER1_SYN_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_task_timer1_syn trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM0_TASK_TIMER2_SYN_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_task_timer2_syn trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM0_TASK_TIMER0_PERIOD_UP_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_task_timer0_period_up + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM0_TASK_TIMER1_PERIOD_UP_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_task_timer1_period_up + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM0_TASK_TIMER2_PERIOD_UP_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_task_timer2_period_up + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM0_TASK_TZ0_OST_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_task_tz0_ost trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM0_TASK_TZ1_OST_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_task_tz1_ost trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM0_TASK_TZ2_OST_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_task_tz2_ost trigger + status.\\0: Invalid, No effect\\1: Clear */ + } bit; + } TASK_ST3_CLR; + + union { + __IOM uint32_t reg; /*!< Tasks trigger status register */ + + struct { + __IOM uint32_t MCPWM0_TASK_CLR0_OST_ST : 1;/*!< Represents MCPWM0_task_clr0_ost trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM0_TASK_CLR1_OST_ST : 1;/*!< Represents MCPWM0_task_clr1_ost trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM0_TASK_CLR2_OST_ST : 1;/*!< Represents MCPWM0_task_clr2_ost trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM0_TASK_CAP0_ST : 1; /*!< Represents MCPWM0_task_cap0 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM0_TASK_CAP1_ST : 1; /*!< Represents MCPWM0_task_cap1 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM0_TASK_CAP2_ST : 1; /*!< Represents MCPWM0_task_cap2 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM1_TASK_CMPR0_A_UP_ST : 1;/*!< Represents MCPWM1_task_cmpr0_a_up trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM1_TASK_CMPR1_A_UP_ST : 1;/*!< Represents MCPWM1_task_cmpr1_a_up trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM1_TASK_CMPR2_A_UP_ST : 1;/*!< Represents MCPWM1_task_cmpr2_a_up trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM1_TASK_CMPR0_B_UP_ST : 1;/*!< Represents MCPWM1_task_cmpr0_b_up trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM1_TASK_CMPR1_B_UP_ST : 1;/*!< Represents MCPWM1_task_cmpr1_b_up trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM1_TASK_CMPR2_B_UP_ST : 1;/*!< Represents MCPWM1_task_cmpr2_b_up trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM1_TASK_GEN_STOP_ST : 1;/*!< Represents MCPWM1_task_gen_stop trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM1_TASK_TIMER0_SYN_ST : 1;/*!< Represents MCPWM1_task_timer0_syn trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM1_TASK_TIMER1_SYN_ST : 1;/*!< Represents MCPWM1_task_timer1_syn trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM1_TASK_TIMER2_SYN_ST : 1;/*!< Represents MCPWM1_task_timer2_syn trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM1_TASK_TIMER0_PERIOD_UP_ST : 1;/*!< Represents MCPWM1_task_timer0_period_up trigger status.\\0: + Not triggered\\1: Triggered */ + __IOM uint32_t MCPWM1_TASK_TIMER1_PERIOD_UP_ST : 1;/*!< Represents MCPWM1_task_timer1_period_up trigger status.\\0: + Not triggered\\1: Triggered */ + __IOM uint32_t MCPWM1_TASK_TIMER2_PERIOD_UP_ST : 1;/*!< Represents MCPWM1_task_timer2_period_up trigger status.\\0: + Not triggered\\1: Triggered */ + __IOM uint32_t MCPWM1_TASK_TZ0_OST_ST : 1;/*!< Represents MCPWM1_task_tz0_ost trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM1_TASK_TZ1_OST_ST : 1;/*!< Represents MCPWM1_task_tz1_ost trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM1_TASK_TZ2_OST_ST : 1;/*!< Represents MCPWM1_task_tz2_ost trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM1_TASK_CLR0_OST_ST : 1;/*!< Represents MCPWM1_task_clr0_ost trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM1_TASK_CLR1_OST_ST : 1;/*!< Represents MCPWM1_task_clr1_ost trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM1_TASK_CLR2_OST_ST : 1;/*!< Represents MCPWM1_task_clr2_ost trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM1_TASK_CAP0_ST : 1; /*!< Represents MCPWM1_task_cap0 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM1_TASK_CAP1_ST : 1; /*!< Represents MCPWM1_task_cap1 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t MCPWM1_TASK_CAP2_ST : 1; /*!< Represents MCPWM1_task_cap2 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t ADC_TASK_SAMPLE0_ST : 1; /*!< Represents ADC_task_sample0 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t ADC_TASK_SAMPLE1_ST : 1; /*!< Represents ADC_task_sample1 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t ADC_TASK_START0_ST : 1; /*!< Represents ADC_task_start0 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t ADC_TASK_STOP0_ST : 1; /*!< Represents ADC_task_stop0 trigger status.\\0: Not triggered\\1: + Triggered */ + } bit; + } TASK_ST4; + + union { + __IOM uint32_t reg; /*!< Tasks trigger status clear register */ + + struct { + __OM uint32_t MCPWM0_TASK_CLR0_OST_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_task_clr0_ost trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM0_TASK_CLR1_OST_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_task_clr1_ost trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM0_TASK_CLR2_OST_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_task_clr2_ost trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM0_TASK_CAP0_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_task_cap0 trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM0_TASK_CAP1_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_task_cap1 trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM0_TASK_CAP2_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_task_cap2 trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM1_TASK_CMPR0_A_UP_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_task_cmpr0_a_up trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM1_TASK_CMPR1_A_UP_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_task_cmpr1_a_up trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM1_TASK_CMPR2_A_UP_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_task_cmpr2_a_up trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM1_TASK_CMPR0_B_UP_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_task_cmpr0_b_up trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM1_TASK_CMPR1_B_UP_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_task_cmpr1_b_up trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM1_TASK_CMPR2_B_UP_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_task_cmpr2_b_up trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM1_TASK_GEN_STOP_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_task_gen_stop trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM1_TASK_TIMER0_SYN_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_task_timer0_syn trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM1_TASK_TIMER1_SYN_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_task_timer1_syn trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM1_TASK_TIMER2_SYN_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_task_timer2_syn trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM1_TASK_TIMER0_PERIOD_UP_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_task_timer0_period_up + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM1_TASK_TIMER1_PERIOD_UP_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_task_timer1_period_up + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM1_TASK_TIMER2_PERIOD_UP_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_task_timer2_period_up + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM1_TASK_TZ0_OST_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_task_tz0_ost trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM1_TASK_TZ1_OST_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_task_tz1_ost trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM1_TASK_TZ2_OST_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_task_tz2_ost trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM1_TASK_CLR0_OST_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_task_clr0_ost trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM1_TASK_CLR1_OST_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_task_clr1_ost trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM1_TASK_CLR2_OST_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_task_clr2_ost trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM1_TASK_CAP0_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_task_cap0 trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM1_TASK_CAP1_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_task_cap1 trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t MCPWM1_TASK_CAP2_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_task_cap2 trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t ADC_TASK_SAMPLE0_ST_CLR : 1;/*!< Configures whether or not to clear ADC_task_sample0 trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t ADC_TASK_SAMPLE1_ST_CLR : 1;/*!< Configures whether or not to clear ADC_task_sample1 trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t ADC_TASK_START0_ST_CLR : 1;/*!< Configures whether or not to clear ADC_task_start0 trigger status.\\0: + Invalid, No effect\\1: Clear */ + __OM uint32_t ADC_TASK_STOP0_ST_CLR : 1; /*!< Configures whether or not to clear ADC_task_stop0 trigger status.\\0: + Invalid, No effect\\1: Clear */ + } bit; + } TASK_ST4_CLR; + + union { + __IOM uint32_t reg; /*!< Tasks trigger status register */ + + struct { + __IOM uint32_t REGDMA_TASK_START0_ST : 1; /*!< Represents REGDMA_task_start0 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t REGDMA_TASK_START1_ST : 1; /*!< Represents REGDMA_task_start1 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t REGDMA_TASK_START2_ST : 1; /*!< Represents REGDMA_task_start2 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t REGDMA_TASK_START3_ST : 1; /*!< Represents REGDMA_task_start3 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t TMPSNSR_TASK_START_SAMPLE_ST : 1;/*!< Represents TMPSNSR_task_start_sample trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t TMPSNSR_TASK_STOP_SAMPLE_ST : 1;/*!< Represents TMPSNSR_task_stop_sample trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t I2S0_TASK_START_RX_ST : 1; /*!< Represents I2S0_task_start_rx trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t I2S0_TASK_START_TX_ST : 1; /*!< Represents I2S0_task_start_tx trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t I2S0_TASK_STOP_RX_ST : 1; /*!< Represents I2S0_task_stop_rx trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t I2S0_TASK_STOP_TX_ST : 1; /*!< Represents I2S0_task_stop_tx trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t I2S1_TASK_START_RX_ST : 1; /*!< Represents I2S1_task_start_rx trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t I2S1_TASK_START_TX_ST : 1; /*!< Represents I2S1_task_start_tx trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t I2S1_TASK_STOP_RX_ST : 1; /*!< Represents I2S1_task_stop_rx trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t I2S1_TASK_STOP_TX_ST : 1; /*!< Represents I2S1_task_stop_tx trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t I2S2_TASK_START_RX_ST : 1; /*!< Represents I2S2_task_start_rx trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t I2S2_TASK_START_TX_ST : 1; /*!< Represents I2S2_task_start_tx trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t I2S2_TASK_STOP_RX_ST : 1; /*!< Represents I2S2_task_stop_rx trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t I2S2_TASK_STOP_TX_ST : 1; /*!< Represents I2S2_task_stop_tx trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t ULP_TASK_WAKEUP_CPU_ST : 1;/*!< Represents ULP_task_wakeup_cpu trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t ULP_TASK_INT_CPU_ST : 1; /*!< Represents ULP_task_int_cpu trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t RTC_TASK_START_ST : 1; /*!< Represents RTC_task_start trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t RTC_TASK_STOP_ST : 1; /*!< Represents RTC_task_stop trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t RTC_TASK_CLR_ST : 1; /*!< Represents RTC_task_clr trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t RTC_TASK_TRIGGERFLW_ST : 1;/*!< Represents RTC_task_triggerflw trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t PDMA_AHB_TASK_IN_START_CH0_ST : 1;/*!< Represents PDMA_AHB_task_in_start_ch0 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t PDMA_AHB_TASK_IN_START_CH1_ST : 1;/*!< Represents PDMA_AHB_task_in_start_ch1 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t PDMA_AHB_TASK_IN_START_CH2_ST : 1;/*!< Represents PDMA_AHB_task_in_start_ch2 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t PDMA_AHB_TASK_OUT_START_CH0_ST : 1;/*!< Represents PDMA_AHB_task_out_start_ch0 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t PDMA_AHB_TASK_OUT_START_CH1_ST : 1;/*!< Represents PDMA_AHB_task_out_start_ch1 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t PDMA_AHB_TASK_OUT_START_CH2_ST : 1;/*!< Represents PDMA_AHB_task_out_start_ch2 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t PDMA_AXI_TASK_IN_START_CH0_ST : 1;/*!< Represents PDMA_AXI_task_in_start_ch0 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t PDMA_AXI_TASK_IN_START_CH1_ST : 1;/*!< Represents PDMA_AXI_task_in_start_ch1 trigger status.\\0: Not + triggered\\1: Triggered */ + } bit; + } TASK_ST5; + + union { + __IOM uint32_t reg; /*!< Tasks trigger status clear register */ + + struct { + __OM uint32_t REGDMA_TASK_START0_ST_CLR : 1;/*!< Configures whether or not to clear REGDMA_task_start0 trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t REGDMA_TASK_START1_ST_CLR : 1;/*!< Configures whether or not to clear REGDMA_task_start1 trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t REGDMA_TASK_START2_ST_CLR : 1;/*!< Configures whether or not to clear REGDMA_task_start2 trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t REGDMA_TASK_START3_ST_CLR : 1;/*!< Configures whether or not to clear REGDMA_task_start3 trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t TMPSNSR_TASK_START_SAMPLE_ST_CLR : 1;/*!< Configures whether or not to clear TMPSNSR_task_start_sample + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t TMPSNSR_TASK_STOP_SAMPLE_ST_CLR : 1;/*!< Configures whether or not to clear TMPSNSR_task_stop_sample + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t I2S0_TASK_START_RX_ST_CLR : 1;/*!< Configures whether or not to clear I2S0_task_start_rx trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t I2S0_TASK_START_TX_ST_CLR : 1;/*!< Configures whether or not to clear I2S0_task_start_tx trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t I2S0_TASK_STOP_RX_ST_CLR : 1;/*!< Configures whether or not to clear I2S0_task_stop_rx trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t I2S0_TASK_STOP_TX_ST_CLR : 1;/*!< Configures whether or not to clear I2S0_task_stop_tx trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t I2S1_TASK_START_RX_ST_CLR : 1;/*!< Configures whether or not to clear I2S1_task_start_rx trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t I2S1_TASK_START_TX_ST_CLR : 1;/*!< Configures whether or not to clear I2S1_task_start_tx trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t I2S1_TASK_STOP_RX_ST_CLR : 1;/*!< Configures whether or not to clear I2S1_task_stop_rx trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t I2S1_TASK_STOP_TX_ST_CLR : 1;/*!< Configures whether or not to clear I2S1_task_stop_tx trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t I2S2_TASK_START_RX_ST_CLR : 1;/*!< Configures whether or not to clear I2S2_task_start_rx trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t I2S2_TASK_START_TX_ST_CLR : 1;/*!< Configures whether or not to clear I2S2_task_start_tx trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t I2S2_TASK_STOP_RX_ST_CLR : 1;/*!< Configures whether or not to clear I2S2_task_stop_rx trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t I2S2_TASK_STOP_TX_ST_CLR : 1;/*!< Configures whether or not to clear I2S2_task_stop_tx trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t ULP_TASK_WAKEUP_CPU_ST_CLR : 1;/*!< Configures whether or not to clear ULP_task_wakeup_cpu trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t ULP_TASK_INT_CPU_ST_CLR : 1;/*!< Configures whether or not to clear ULP_task_int_cpu trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t RTC_TASK_START_ST_CLR : 1; /*!< Configures whether or not to clear RTC_task_start trigger status.\\0: + Invalid, No effect\\1: Clear */ + __OM uint32_t RTC_TASK_STOP_ST_CLR : 1; /*!< Configures whether or not to clear RTC_task_stop trigger status.\\0: + Invalid, No effect\\1: Clear */ + __OM uint32_t RTC_TASK_CLR_ST_CLR : 1; /*!< Configures whether or not to clear RTC_task_clr trigger status.\\0: + Invalid, No effect\\1: Clear */ + __OM uint32_t RTC_TASK_TRIGGERFLW_ST_CLR : 1;/*!< Configures whether or not to clear RTC_task_triggerflw trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t PDMA_AHB_TASK_IN_START_CH0_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_task_in_start_ch0 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t PDMA_AHB_TASK_IN_START_CH1_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_task_in_start_ch1 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t PDMA_AHB_TASK_IN_START_CH2_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_task_in_start_ch2 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t PDMA_AHB_TASK_OUT_START_CH0_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_task_out_start_ch0 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t PDMA_AHB_TASK_OUT_START_CH1_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_task_out_start_ch1 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t PDMA_AHB_TASK_OUT_START_CH2_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_task_out_start_ch2 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t PDMA_AXI_TASK_IN_START_CH0_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_task_in_start_ch0 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t PDMA_AXI_TASK_IN_START_CH1_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_task_in_start_ch1 + trigger status.\\0: Invalid, No effect\\1: Clear */ + } bit; + } TASK_ST5_CLR; + + union { + __IOM uint32_t reg; /*!< Tasks trigger status register */ + + struct { + __IOM uint32_t PDMA_AXI_TASK_IN_START_CH2_ST : 1;/*!< Represents PDMA_AXI_task_in_start_ch2 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t PDMA_AXI_TASK_OUT_START_CH0_ST : 1;/*!< Represents PDMA_AXI_task_out_start_ch0 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t PDMA_AXI_TASK_OUT_START_CH1_ST : 1;/*!< Represents PDMA_AXI_task_out_start_ch1 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t PDMA_AXI_TASK_OUT_START_CH2_ST : 1;/*!< Represents PDMA_AXI_task_out_start_ch2 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t PMU_TASK_SLEEP_REQ_ST : 1; /*!< Represents PMU_task_sleep_req trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t DMA2D_TASK_IN_START_CH0_ST : 1;/*!< Represents DMA2D_task_in_start_ch0 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t DMA2D_TASK_IN_START_CH1_ST : 1;/*!< Represents DMA2D_task_in_start_ch1 trigger status.\\0: Not triggered\\1: + Triggered */ + __IOM uint32_t DMA2D_TASK_IN_DSCR_READY_CH0_ST : 1;/*!< Represents DMA2D_task_in_dscr_ready_ch0 trigger status.\\0: + Not triggered\\1: Triggered */ + __IOM uint32_t DMA2D_TASK_IN_DSCR_READY_CH1_ST : 1;/*!< Represents DMA2D_task_in_dscr_ready_ch1 trigger status.\\0: + Not triggered\\1: Triggered */ + __IOM uint32_t DMA2D_TASK_OUT_START_CH0_ST : 1;/*!< Represents DMA2D_task_out_start_ch0 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t DMA2D_TASK_OUT_START_CH1_ST : 1;/*!< Represents DMA2D_task_out_start_ch1 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t DMA2D_TASK_OUT_START_CH2_ST : 1;/*!< Represents DMA2D_task_out_start_ch2 trigger status.\\0: Not + triggered\\1: Triggered */ + __IOM uint32_t DMA2D_TASK_OUT_DSCR_READY_CH0_ST : 1;/*!< Represents DMA2D_task_out_dscr_ready_ch0 trigger status.\\0: + Not triggered\\1: Triggered */ + __IOM uint32_t DMA2D_TASK_OUT_DSCR_READY_CH1_ST : 1;/*!< Represents DMA2D_task_out_dscr_ready_ch1 trigger status.\\0: + Not triggered\\1: Triggered */ + __IOM uint32_t DMA2D_TASK_OUT_DSCR_READY_CH2_ST : 1;/*!< Represents DMA2D_task_out_dscr_ready_ch2 trigger status.\\0: + Not triggered\\1: Triggered */ + uint32_t : 17; + } bit; + } TASK_ST6; + + union { + __IOM uint32_t reg; /*!< Tasks trigger status clear register */ + + struct { + __OM uint32_t PDMA_AXI_TASK_IN_START_CH2_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_task_in_start_ch2 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t PDMA_AXI_TASK_OUT_START_CH0_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_task_out_start_ch0 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t PDMA_AXI_TASK_OUT_START_CH1_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_task_out_start_ch1 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t PDMA_AXI_TASK_OUT_START_CH2_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_task_out_start_ch2 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t PMU_TASK_SLEEP_REQ_ST_CLR : 1;/*!< Configures whether or not to clear PMU_task_sleep_req trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t DMA2D_TASK_IN_START_CH0_ST_CLR : 1;/*!< Configures whether or not to clear DMA2D_task_in_start_ch0 trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t DMA2D_TASK_IN_START_CH1_ST_CLR : 1;/*!< Configures whether or not to clear DMA2D_task_in_start_ch1 trigger + status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t DMA2D_TASK_IN_DSCR_READY_CH0_ST_CLR : 1;/*!< Configures whether or not to clear DMA2D_task_in_dscr_ready_ch0 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t DMA2D_TASK_IN_DSCR_READY_CH1_ST_CLR : 1;/*!< Configures whether or not to clear DMA2D_task_in_dscr_ready_ch1 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t DMA2D_TASK_OUT_START_CH0_ST_CLR : 1;/*!< Configures whether or not to clear DMA2D_task_out_start_ch0 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t DMA2D_TASK_OUT_START_CH1_ST_CLR : 1;/*!< Configures whether or not to clear DMA2D_task_out_start_ch1 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t DMA2D_TASK_OUT_START_CH2_ST_CLR : 1;/*!< Configures whether or not to clear DMA2D_task_out_start_ch2 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t DMA2D_TASK_OUT_DSCR_READY_CH0_ST_CLR : 1;/*!< Configures whether or not to clear DMA2D_task_out_dscr_ready_ch0 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t DMA2D_TASK_OUT_DSCR_READY_CH1_ST_CLR : 1;/*!< Configures whether or not to clear DMA2D_task_out_dscr_ready_ch1 + trigger status.\\0: Invalid, No effect\\1: Clear */ + __OM uint32_t DMA2D_TASK_OUT_DSCR_READY_CH2_ST_CLR : 1;/*!< Configures whether or not to clear DMA2D_task_out_dscr_ready_ch2 + trigger status.\\0: Invalid, No effect\\1: Clear */ + uint32_t : 17; + } bit; + } TASK_ST6_CLR; + + union { + __IOM uint32_t reg; /*!< ETM clock enable register */ + + struct { + __IOM uint32_t CLK_EN : 1; /*!< Configures whether or not to open register clock gate.\\0: Open + the clock gate only when application writes registers\\1: + Force open the clock gate for register */ + uint32_t : 31; + } bit; + } CLK_EN; + + union { + __IOM uint32_t reg; /*!< ETM date register */ + + struct { + __IOM uint32_t DATE : 28; /*!< Configures the version. */ + uint32_t : 4; + } bit; + } DATE; +} SOC_ETM_Type; /*!< Size = 552 (0x228) */ + + + +/* =========================================================================================================================== */ +/* ================ SPI0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief SPI (Serial Peripheral Interface) Controller 0 (SPI0) + */ + +typedef struct { /*!< SPI0 Structure */ + + union { + __IOM uint32_t reg; /*!< SPI0 FSM status register */ + + struct { + __IM uint32_t SPI_MEM_MST_ST : 4; /*!< The current status of SPI0 master FSM: spi0_mst_st. 0: idle + state, 1:SPI0_GRANT , 2: program/erase suspend state, 3: + SPI0 read data state, 4: wait cache/EDMA sent data is stored + in SPI0 TX FIFO, 5: SPI0 write data state. */ + __IM uint32_t SPI_MEM_SLV_ST : 4; /*!< The current status of SPI0 slave FSM: mspi_st. 0: idle state, + 1: preparation state, 2: send command state, 3: send address + state, 4: wait state, 5: read data state, 6:write data + state, 7: done state, 8: read data end state. */ + uint32_t : 10; + __IM uint32_t SPI_MEM_USR : 1; /*!< SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is + cleared. An operation will be triggered when the bit is + set. The bit will be cleared once the operation done.1: + enable 0: disable. */ + uint32_t : 13; + } bit; + } SPI_MEM_CMD; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t reg; /*!< SPI0 control register. */ + + struct { + __IOM uint32_t SPI_MEM_WDUMMY_DQS_ALWAYS_OUT : 1;/*!< In the dummy phase of an MSPI write data transfer when accesses + to flash, the level of SPI_DQS is output by the MSPI controller. */ + __IOM uint32_t SPI_MEM_WDUMMY_ALWAYS_OUT : 1;/*!< In the dummy phase of an MSPI write data transfer when accesses + to flash, the level of SPI_IO[7:0] is output by the MSPI + controller. */ + __IOM uint32_t SPI_MEM_FDUMMY_RIN : 1; /*!< In an MSPI read data transfer when accesses to flash, the level + of SPI_IO[7:0] is output by the MSPI controller in the + first half part of dummy phase. It is used to mask invalid + SPI_DQS in the half part of dummy phase. */ + __IOM uint32_t SPI_MEM_FDUMMY_WOUT : 1; /*!< In an MSPI write data transfer when accesses to flash, the level + of SPI_IO[7:0] is output by the MSPI controller in the + second half part of dummy phase. It is used to pre-drive + flash. */ + __IOM uint32_t SPI_MEM_FDOUT_OCT : 1; /*!< Apply 8 signals during write-data phase 1:enable 0: disable */ + __IOM uint32_t SPI_MEM_FDIN_OCT : 1; /*!< Apply 8 signals during read-data phase 1:enable 0: disable */ + __IOM uint32_t SPI_MEM_FADDR_OCT : 1; /*!< Apply 8 signals during address phase 1:enable 0: disable */ + uint32_t : 1; + __IOM uint32_t SPI_MEM_FCMD_QUAD : 1; /*!< Apply 4 signals during command phase 1:enable 0: disable */ + __IOM uint32_t SPI_MEM_FCMD_OCT : 1; /*!< Apply 8 signals during command phase 1:enable 0: disable */ + uint32_t : 3; + __IOM uint32_t SPI_MEM_FASTRD_MODE : 1; /*!< This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, + SPI_MEM_FREAD_QOUT and SPI_MEM_FREAD_DOUT. 1: enable 0: + disable. */ + __IOM uint32_t SPI_MEM_FREAD_DUAL : 1; /*!< In the read operations, read-data phase apply 2 signals. 1: + enable 0: disable. */ + uint32_t : 3; + __IOM uint32_t SPI_MEM_Q_POL : 1; /*!< The bit is used to set MISO line polarity, 1: high 0, low */ + __IOM uint32_t SPI_MEM_D_POL : 1; /*!< The bit is used to set MOSI line polarity, 1: high 0, low */ + __IOM uint32_t SPI_MEM_FREAD_QUAD : 1; /*!< In the read operations read-data phase apply 4 signals. 1: enable + 0: disable. */ + __IOM uint32_t SPI_MEM_WP : 1; /*!< Write protect signal output when SPI is idle. 1: output high, + 0: output low. */ + uint32_t : 1; + __IOM uint32_t SPI_MEM_FREAD_DIO : 1; /*!< In the read operations address phase and read-data phase apply + 2 signals. 1: enable 0: disable. */ + __IOM uint32_t SPI_MEM_FREAD_QIO : 1; /*!< In the read operations address phase and read-data phase apply + 4 signals. 1: enable 0: disable. */ + uint32_t : 5; + __IOM uint32_t SPI_MEM_DQS_IE_ALWAYS_ON : 1;/*!< When accesses to flash, 1: the IE signals of pads connected + to SPI_DQS are always 1. 0: Others. */ + __IOM uint32_t SPI_MEM_DATA_IE_ALWAYS_ON : 1;/*!< When accesses to flash, 1: the IE signals of pads connected + to SPI_IO[7:0] are always 1. 0: Others. */ + } bit; + } SPI_MEM_CTRL; + + union { + __IOM uint32_t reg; /*!< SPI0 control1 register. */ + + struct { + __IOM uint32_t SPI_MEM_CLK_MODE : 2; /*!< SPI clock mode bits. 0: SPI clock is off when CS inactive 1: + SPI clock is delayed one cycle after CS inactive 2: SPI + clock is delayed two cycles after CS inactive 3: SPI clock + is alwasy on. */ + uint32_t : 19; + __IOM uint32_t SPI_AR_SIZE0_1_SUPPORT_EN : 1;/*!< 1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address + is 4*n and reply the real AXI read data back. 0: When ARSIZE + 0~1, MSPI reply SLV_ERR. */ + __IOM uint32_t SPI_AW_SIZE0_1_SUPPORT_EN : 1;/*!< 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply + SLV_ERR. */ + __IOM uint32_t SPI_AXI_RDATA_BACK_FAST : 1;/*!< 1: Reply AXI read data to AXI bus when one AXI read beat data + is available. 0: Reply AXI read data to AXI bus when all + the read data is available. */ + __IOM uint32_t SPI_MEM_RRESP_ECC_ERR_EN : 1;/*!< 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. + 0: RRESP is OKAY when there is a ECC error in AXI read + data. The ECC error information is recorded in SPI_MEM_ECC_ERR_ADDR_REG. */ + __IOM uint32_t SPI_MEM_AR_SPLICE_EN : 1; /*!< Set this bit to enable AXI Read Splice-transfer. */ + __IOM uint32_t SPI_MEM_AW_SPLICE_EN : 1; /*!< Set this bit to enable AXI Write Splice-transfer. */ + __IM uint32_t SPI_MEM_RAM0_EN : 1; /*!< When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only + EXT_RAM0 will be accessed. When SPI_MEM_DUAL_RAM_EN is + 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 will be accessed. + When SPI_MEM_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will + be accessed at the same time. */ + __IM uint32_t SPI_MEM_DUAL_RAM_EN : 1; /*!< Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 + will be accessed at the same time. */ + __IOM uint32_t SPI_MEM_FAST_WRITE_EN : 1; /*!< Set this bit to write data faster, do not wait write data has + been stored in tx_bus_fifo_l2. It will wait 4*T_clk_ctrl + to insure the write data has been stored in tx_bus_fifo_l2. */ + __OM uint32_t SPI_MEM_RXFIFO_RST : 1; /*!< The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI + SYNC FIFO to receive signals from AXI. Set this bit to + reset these FIFO. */ + __OM uint32_t SPI_MEM_TXFIFO_RST : 1; /*!< The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI + SYNC FIFO to send signals to AXI. Set this bit to reset + these FIFO. */ + } bit; + } SPI_MEM_CTRL1; + + union { + __IOM uint32_t reg; /*!< SPI0 control2 register. */ + + struct { + __IOM uint32_t SPI_MEM_CS_SETUP_TIME : 5; /*!< (cycles-1) of prepare phase by SPI Bus clock, this bits are + combined with SPI_MEM_CS_SETUP bit. */ + __IOM uint32_t SPI_MEM_CS_HOLD_TIME : 5; /*!< SPI CS signal is delayed to inactive by SPI bus clock, this + bits are combined with SPI_MEM_CS_HOLD bit. */ + __IOM uint32_t SPI_MEM_ECC_CS_HOLD_TIME : 3;/*!< SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 + CS hold cycle in ECC mode when accessed flash. */ + __IOM uint32_t SPI_MEM_ECC_SKIP_PAGE_CORNER : 1;/*!< 1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not + skip page corner when accesses flash. */ + __IOM uint32_t SPI_MEM_ECC_16TO18_BYTE_EN : 1;/*!< Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with + 2 ECC bytes mode when accesses flash. */ + uint32_t : 9; + __IOM uint32_t SPI_MEM_SPLIT_TRANS_EN : 1;/*!< Set this bit to enable SPI0 split one AXI read flash transfer + into two SPI transfers when one transfer will cross flash + or EXT_RAM page corner, valid no matter whether there is + an ECC region or not. */ + __IOM uint32_t SPI_MEM_CS_HOLD_DELAY : 6; /*!< These bits are used to set the minimum CS high time tSHSL between + SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELA + [5:0] + 1) MSPI core clock cycles. */ + __OM uint32_t SPI_MEM_SYNC_RESET : 1; /*!< The spi0_mst_st and spi0_slv_st will be reset. */ + } bit; + } SPI_MEM_CTRL2; + + union { + __IOM uint32_t reg; /*!< SPI clock division control register. */ + + struct { + __IOM uint32_t SPI_MEM_CLKCNT_L : 8; /*!< In the master mode it must be equal to spi_mem_clkcnt_N. */ + __IOM uint32_t SPI_MEM_CLKCNT_H : 8; /*!< In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). */ + __IOM uint32_t SPI_MEM_CLKCNT_N : 8; /*!< In the master mode it is the divider of spi_mem_clk. So spi_mem_clk + frequency is system/(spi_mem_clkcnt_N+1) */ + uint32_t : 7; + __IOM uint32_t SPI_MEM_CLK_EQU_SYSCLK : 1;/*!< 1: 1-division mode, the frequency of SPI bus clock equals to + that of MSPI module clock. */ + } bit; + } SPI_MEM_CLOCK; + + union { + __IOM uint32_t reg; /*!< SPI0 user register. */ + + struct { + uint32_t : 6; + __IOM uint32_t SPI_MEM_CS_HOLD : 1; /*!< spi cs keep low when spi is in done phase. 1: enable 0: disable. */ + __IOM uint32_t SPI_MEM_CS_SETUP : 1; /*!< spi cs is enable when spi is in prepare phase. 1: enable 0: + disable. */ + uint32_t : 1; + __IOM uint32_t SPI_MEM_CK_OUT_EDGE : 1; /*!< The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI + clock mode 0~3. */ + uint32_t : 16; + __IOM uint32_t SPI_MEM_USR_DUMMY_IDLE : 1;/*!< spi clock is disable in dummy phase when the bit is enable. */ + uint32_t : 2; + __IOM uint32_t SPI_MEM_USR_DUMMY : 1; /*!< This bit enable the dummy phase of an operation. */ + uint32_t : 2; + } bit; + } SPI_MEM_USER; + + union { + __IOM uint32_t reg; /*!< SPI0 user1 register. */ + + struct { + __IOM uint32_t SPI_MEM_USR_DUMMY_CYCLELEN : 6;/*!< The length in spi_mem_clk cycles of dummy phase. The register + value shall be (cycle_num-1). */ + __IM uint32_t SPI_MEM_USR_DBYTELEN : 3; /*!< SPI0 USR_CMD read or write data byte length -1 */ + uint32_t : 17; + __IOM uint32_t SPI_MEM_USR_ADDR_BITLEN : 6;/*!< The length in bits of address phase. The register value shall + be (bit_num-1). */ + } bit; + } SPI_MEM_USER1; + + union { + __IOM uint32_t reg; /*!< SPI0 user2 register. */ + + struct { + __IOM uint32_t SPI_MEM_USR_COMMAND_VALUE : 16;/*!< The value of command. */ + uint32_t : 12; + __IOM uint32_t SPI_MEM_USR_COMMAND_BITLEN : 4;/*!< The length in bits of command phase. The register value shall + be (bit_num-1) */ + } bit; + } SPI_MEM_USER2; + __IM uint32_t RESERVED1[2]; + + union { + __IOM uint32_t reg; /*!< SPI0 read control register. */ + + struct { + uint32_t : 16; + __IOM uint32_t SPI_MEM_WB_MODE : 8; /*!< Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode + bit. */ + uint32_t : 8; + } bit; + } SPI_MEM_RD_STATUS; + __IM uint32_t RESERVED2; + + union { + __IOM uint32_t reg; /*!< SPI0 misc register */ + + struct { + uint32_t : 7; + __IOM uint32_t SPI_MEM_FSUB_PIN : 1; /*!< For SPI0, flash is connected to SUBPINs. */ + __IOM uint32_t SPI_MEM_SSUB_PIN : 1; /*!< For SPI0, sram is connected to SUBPINs. */ + __IOM uint32_t SPI_MEM_CK_IDLE_EDGE : 1; /*!< 1: SPI_CLK line is high when idle 0: spi clk line is low when + idle */ + __IOM uint32_t SPI_MEM_CS_KEEP_ACTIVE : 1;/*!< SPI_CS line keep low when the bit is set. */ + uint32_t : 21; + } bit; + } SPI_MEM_MISC; + __IM uint32_t RESERVED3; + + union { + __IOM uint32_t reg; /*!< SPI0 bit mode control register. */ + + struct { + __IOM uint32_t SPI_MEM_AXI_REQ_EN : 1; /*!< For SPI0, AXI master access enable, 1: enable, 0:disable. */ + __IOM uint32_t SPI_MEM_CACHE_USR_ADDR_4BYTE : 1;/*!< For SPI0, cache read flash with 4 bytes address, 1: enable, + 0:disable. */ + __IOM uint32_t SPI_MEM_CACHE_FLASH_USR_CMD : 1;/*!< For SPI0, cache read flash for user define command, 1: enable, + 0:disable. */ + __IOM uint32_t SPI_MEM_FDIN_DUAL : 1; /*!< For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. + The bit is the same with spi_mem_fread_dio. */ + __IOM uint32_t SPI_MEM_FDOUT_DUAL : 1; /*!< For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. + The bit is the same with spi_mem_fread_dio. */ + __IOM uint32_t SPI_MEM_FADDR_DUAL : 1; /*!< For SPI0 flash, address phase apply 2 signals. 1: enable 0: + disable. The bit is the same with spi_mem_fread_dio. */ + __IOM uint32_t SPI_MEM_FDIN_QUAD : 1; /*!< For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. + The bit is the same with spi_mem_fread_qio. */ + __IOM uint32_t SPI_MEM_FDOUT_QUAD : 1; /*!< For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. + The bit is the same with spi_mem_fread_qio. */ + __IOM uint32_t SPI_MEM_FADDR_QUAD : 1; /*!< For SPI0 flash, address phase apply 4 signals. 1: enable 0: + disable. The bit is the same with spi_mem_fread_qio. */ + uint32_t : 21; + __IOM uint32_t SPI_SAME_AW_AR_ADDR_CHK_EN : 1;/*!< Set this bit to check AXI read/write the same address region. */ + __IOM uint32_t SPI_CLOSE_AXI_INF_EN : 1; /*!< Set this bit to close AXI read/write transfer to MSPI, which + means that only SLV_ERR will be replied to BRESP/RRESP. */ + } bit; + } SPI_MEM_CACHE_FCTRL; + + union { + __IOM uint32_t reg; /*!< SPI0 external RAM control register */ + + struct { + __IOM uint32_t SPI_MEM_CACHE_USR_SADDR_4BYTE : 1;/*!< For SPI0, In the external RAM mode, cache read flash with 4 + bytes command, 1: enable, 0:disable. */ + __IOM uint32_t SPI_MEM_USR_SRAM_DIO : 1; /*!< For SPI0, In the external RAM mode, spi dual I/O mode enable, + 1: enable, 0:disable */ + __IOM uint32_t SPI_MEM_USR_SRAM_QIO : 1; /*!< For SPI0, In the external RAM mode, spi quad I/O mode enable, + 1: enable, 0:disable */ + __IOM uint32_t SPI_MEM_USR_WR_SRAM_DUMMY : 1;/*!< For SPI0, In the external RAM mode, it is the enable bit of + dummy phase for write operations. */ + __IOM uint32_t SPI_MEM_USR_RD_SRAM_DUMMY : 1;/*!< For SPI0, In the external RAM mode, it is the enable bit of + dummy phase for read operations. */ + __IOM uint32_t SPI_MEM_CACHE_SRAM_USR_RCMD : 1;/*!< For SPI0, In the external RAM mode cache read external RAM for + user define command. */ + __IOM uint32_t SPI_MEM_SRAM_RDUMMY_CYCLELEN : 6;/*!< For SPI0, In the external RAM mode, it is the length in bits + of read dummy phase. The register value shall be (bit_num-1). */ + uint32_t : 2; + __IOM uint32_t SPI_MEM_SRAM_ADDR_BITLEN : 6;/*!< For SPI0, In the external RAM mode, it is the length in bits + of address phase. The register value shall be (bit_num-1). */ + __IOM uint32_t SPI_MEM_CACHE_SRAM_USR_WCMD : 1;/*!< For SPI0, In the external RAM mode cache write sram for user + define command */ + __IOM uint32_t SPI_MEM_SRAM_OCT : 1; /*!< reserved */ + __IOM uint32_t SPI_MEM_SRAM_WDUMMY_CYCLELEN : 6;/*!< For SPI0, In the external RAM mode, it is the length in bits + of write dummy phase. The register value shall be (bit_num-1). */ + uint32_t : 4; + } bit; + } SPI_MEM_CACHE_SCTRL; + + union { + __IOM uint32_t reg; /*!< SPI0 external RAM mode control register */ + + struct { + __IOM uint32_t SPI_MEM_SCLK_MODE : 2; /*!< SPI clock mode bits. 0: SPI clock is off when CS inactive 1: + SPI clock is delayed one cycle after CS inactive 2: SPI + clock is delayed two cycles after CS inactive 3: SPI clock + is always on. */ + __IOM uint32_t SPI_MEM_SWB_MODE : 8; /*!< Mode bits in the external RAM fast read mode it is combined + with spi_mem_fastrd_mode bit. */ + __IOM uint32_t SPI_MEM_SDIN_DUAL : 1; /*!< For SPI0 external RAM , din phase apply 2 signals. 1: enable + 0: disable. The bit is the same with spi_mem_usr_sram_dio. */ + __IOM uint32_t SPI_MEM_SDOUT_DUAL : 1; /*!< For SPI0 external RAM , dout phase apply 2 signals. 1: enable + 0: disable. The bit is the same with spi_mem_usr_sram_dio. */ + __IOM uint32_t SPI_MEM_SADDR_DUAL : 1; /*!< For SPI0 external RAM , address phase apply 2 signals. 1: enable + 0: disable. The bit is the same with spi_mem_usr_sram_dio. */ + uint32_t : 1; + __IOM uint32_t SPI_MEM_SDIN_QUAD : 1; /*!< For SPI0 external RAM , din phase apply 4 signals. 1: enable + 0: disable. The bit is the same with spi_mem_usr_sram_qio. */ + __IOM uint32_t SPI_MEM_SDOUT_QUAD : 1; /*!< For SPI0 external RAM , dout phase apply 4 signals. 1: enable + 0: disable. The bit is the same with spi_mem_usr_sram_qio. */ + __IOM uint32_t SPI_MEM_SADDR_QUAD : 1; /*!< For SPI0 external RAM , address phase apply 4 signals. 1: enable + 0: disable. The bit is the same with spi_mem_usr_sram_qio. */ + __IOM uint32_t SPI_MEM_SCMD_QUAD : 1; /*!< For SPI0 external RAM , cmd phase apply 4 signals. 1: enable + 0: disable. The bit is the same with spi_mem_usr_sram_qio. */ + __IOM uint32_t SPI_MEM_SDIN_OCT : 1; /*!< For SPI0 external RAM , din phase apply 8 signals. 1: enable + 0: disable. */ + __IOM uint32_t SPI_MEM_SDOUT_OCT : 1; /*!< For SPI0 external RAM , dout phase apply 8 signals. 1: enable + 0: disable. */ + __IOM uint32_t SPI_MEM_SADDR_OCT : 1; /*!< For SPI0 external RAM , address phase apply 4 signals. 1: enable + 0: disable. */ + __IOM uint32_t SPI_MEM_SCMD_OCT : 1; /*!< For SPI0 external RAM , cmd phase apply 8 signals. 1: enable + 0: disable. */ + __IOM uint32_t SPI_MEM_SDUMMY_RIN : 1; /*!< In the dummy phase of a MSPI read data transfer when accesses + to external RAM, the signal level of SPI bus is output + by the MSPI controller. */ + __IOM uint32_t SPI_MEM_SDUMMY_WOUT : 1; /*!< In the dummy phase of a MSPI write data transfer when accesses + to external RAM, the signal level of SPI bus is output + by the MSPI controller. */ + __IOM uint32_t SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT : 1;/*!< In the dummy phase of an MSPI write data transfer when accesses + to external RAM, the level of SPI_DQS is output by the + MSPI controller. */ + __IOM uint32_t SPI_SMEM_WDUMMY_ALWAYS_OUT : 1;/*!< In the dummy phase of an MSPI write data transfer when accesses + to external RAM, the level of SPI_IO[7:0] is output by + the MSPI controller. */ + __IOM uint32_t SPI_MEM_SDIN_HEX : 1; /*!< For SPI0 external RAM , din phase apply 16 signals. 1: enable + 0: disable. */ + __IOM uint32_t SPI_MEM_SDOUT_HEX : 1; /*!< For SPI0 external RAM , dout phase apply 16 signals. 1: enable + 0: disable. */ + uint32_t : 2; + __IOM uint32_t SPI_SMEM_DQS_IE_ALWAYS_ON : 1;/*!< When accesses to external RAM, 1: the IE signals of pads connected + to SPI_DQS are always 1. 0: Others. */ + __IOM uint32_t SPI_SMEM_DATA_IE_ALWAYS_ON : 1;/*!< When accesses to external RAM, 1: the IE signals of pads connected + to SPI_IO[7:0] are always 1. 0: Others. */ + } bit; + } SPI_MEM_SRAM_CMD; + + union { + __IOM uint32_t reg; /*!< SPI0 external RAM DDR read command control register */ + + struct { + __IOM uint32_t SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE : 16;/*!< For SPI0,When cache mode is enable it is the read command value + of command phase for sram. */ + uint32_t : 12; + __IOM uint32_t SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN : 4;/*!< For SPI0,When cache mode is enable it is the length in bits + of command phase for sram. The register value shall be + (bit_num-1). */ + } bit; + } SPI_MEM_SRAM_DRD_CMD; + + union { + __IOM uint32_t reg; /*!< SPI0 external RAM DDR write command control register */ + + struct { + __IOM uint32_t SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE : 16;/*!< For SPI0,When cache mode is enable it is the write command value + of command phase for sram. */ + uint32_t : 12; + __IOM uint32_t SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN : 4;/*!< For SPI0,When cache mode is enable it is the in bits of command + phase for sram. The register value shall be (bit_num-1). */ + } bit; + } SPI_MEM_SRAM_DWR_CMD; + + union { + __IOM uint32_t reg; /*!< SPI0 external RAM clock control register */ + + struct { + __IOM uint32_t SPI_MEM_SCLKCNT_L : 8; /*!< For SPI0 external RAM interface, it must be equal to spi_mem_clkcnt_N. */ + __IOM uint32_t SPI_MEM_SCLKCNT_H : 8; /*!< For SPI0 external RAM interface, it must be floor((spi_mem_clkcnt_N+1)/2-1). */ + __IOM uint32_t SPI_MEM_SCLKCNT_N : 8; /*!< For SPI0 external RAM interface, it is the divider of spi_mem_clk. + So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1) */ + uint32_t : 7; + __IOM uint32_t SPI_MEM_SCLK_EQU_SYSCLK : 1;/*!< For SPI0 external RAM interface, 1: spi_mem_clk is eqaul to + system 0: spi_mem_clk is divided from system clock. */ + } bit; + } SPI_MEM_SRAM_CLK; + + union { + __IOM uint32_t reg; /*!< SPI0 FSM status register */ + + struct { + uint32_t : 7; + __IOM uint32_t SPI_MEM_LOCK_DELAY_TIME : 5;/*!< The lock delay time of SPI0/1 arbiter by spi0_slv_st, after + PER is sent by SPI1. */ + uint32_t : 20; + } bit; + } SPI_MEM_FSM; + __IM uint32_t RESERVED4[26]; + + union { + __IOM uint32_t reg; /*!< SPI0 interrupt enable register */ + + struct { + uint32_t : 3; + __IOM uint32_t SPI_MEM_SLV_ST_END_INT_ENA : 1;/*!< The enable bit for SPI_MEM_SLV_ST_END_INT interrupt. */ + __IOM uint32_t SPI_MEM_MST_ST_END_INT_ENA : 1;/*!< The enable bit for SPI_MEM_MST_ST_END_INT interrupt. */ + __IOM uint32_t SPI_MEM_ECC_ERR_INT_ENA : 1;/*!< The enable bit for SPI_MEM_ECC_ERR_INT interrupt. */ + __IOM uint32_t SPI_MEM_PMS_REJECT_INT_ENA : 1;/*!< The enable bit for SPI_MEM_PMS_REJECT_INT interrupt. */ + __IOM uint32_t SPI_MEM_AXI_RADDR_ERR_INT_ENA : 1;/*!< The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. */ + __IOM uint32_t SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA : 1;/*!< The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. */ + __IOM uint32_t SPI_MEM_AXI_WADDR_ERR_INT__ENA : 1;/*!< The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. */ + uint32_t : 18; + __IOM uint32_t SPI_MEM_DQS0_AFIFO_OVF_INT_ENA : 1;/*!< The enable bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. */ + __IOM uint32_t SPI_MEM_DQS1_AFIFO_OVF_INT_ENA : 1;/*!< The enable bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. */ + __IOM uint32_t SPI_MEM_BUS_FIFO1_UDF_INT_ENA : 1;/*!< The enable bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. */ + __IOM uint32_t SPI_MEM_BUS_FIFO0_UDF_INT_ENA : 1;/*!< The enable bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. */ + } bit; + } SPI_MEM_INT_ENA; + + union { + __IOM uint32_t reg; /*!< SPI0 interrupt clear register */ + + struct { + uint32_t : 3; + __OM uint32_t SPI_MEM_SLV_ST_END_INT_CLR : 1;/*!< The clear bit for SPI_MEM_SLV_ST_END_INT interrupt. */ + __OM uint32_t SPI_MEM_MST_ST_END_INT_CLR : 1;/*!< The clear bit for SPI_MEM_MST_ST_END_INT interrupt. */ + __OM uint32_t SPI_MEM_ECC_ERR_INT_CLR : 1;/*!< The clear bit for SPI_MEM_ECC_ERR_INT interrupt. */ + __OM uint32_t SPI_MEM_PMS_REJECT_INT_CLR : 1;/*!< The clear bit for SPI_MEM_PMS_REJECT_INT interrupt. */ + __OM uint32_t SPI_MEM_AXI_RADDR_ERR_INT_CLR : 1;/*!< The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. */ + __OM uint32_t SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR : 1;/*!< The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. */ + __OM uint32_t SPI_MEM_AXI_WADDR_ERR_INT_CLR : 1;/*!< The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. */ + uint32_t : 18; + __OM uint32_t SPI_MEM_DQS0_AFIFO_OVF_INT_CLR : 1;/*!< The clear bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. */ + __OM uint32_t SPI_MEM_DQS1_AFIFO_OVF_INT_CLR : 1;/*!< The clear bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. */ + __OM uint32_t SPI_MEM_BUS_FIFO1_UDF_INT_CLR : 1;/*!< The clear bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. */ + __OM uint32_t SPI_MEM_BUS_FIFO0_UDF_INT_CLR : 1;/*!< The clear bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. */ + } bit; + } SPI_MEM_INT_CLR; + + union { + __IOM uint32_t reg; /*!< SPI0 interrupt raw register */ + + struct { + uint32_t : 3; + __IOM uint32_t SPI_MEM_SLV_ST_END_INT_RAW : 1;/*!< The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered + when spi0_slv_st is changed from non idle state to idle + state. It means that SPI_CS raises high. 0: Others */ + __IOM uint32_t SPI_MEM_MST_ST_END_INT_RAW : 1;/*!< The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered + when spi0_mst_st is changed from non idle state to idle + state. 0: Others. */ + __IOM uint32_t SPI_MEM_ECC_ERR_INT_RAW : 1;/*!< The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN + is set and SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit + is triggered when the error times of SPI0/1 ECC read flash + are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When + SPI_FMEM_ECC_ERR_INT_EN is cleared and SPI_SMEM_ECC_ERR_INT_EN + is set, this bit is triggered when the error times of SPI0/1 + ECC read external RAM are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. + When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN + are set, this bit is triggered when the total error times + of SPI0/1 ECC read external RAM and flash are equal or + bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN + and SPI_SMEM_ECC_ERR_INT_EN are cleared, this bit will + not be triggered. */ + __IOM uint32_t SPI_MEM_PMS_REJECT_INT_RAW : 1;/*!< The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered + when SPI1 access is rejected. 0: Others. */ + __IOM uint32_t SPI_MEM_AXI_RADDR_ERR_INT_RAW : 1;/*!< The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered + when AXI read address is invalid by compared to MMU configuration. + 0: Others. */ + __IOM uint32_t SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW : 1;/*!< The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered + when AXI write flash request is received. 0: Others. */ + __IOM uint32_t SPI_MEM_AXI_WADDR_ERR_INT_RAW : 1;/*!< The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered + when AXI write address is invalid by compared to MMU configuration. + 0: Others. */ + uint32_t : 18; + __IOM uint32_t SPI_MEM_DQS0_AFIFO_OVF_INT_RAW : 1;/*!< The raw bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. 1: Triggered + when the AFIFO connected to SPI_DQS1 is overflow. */ + __IOM uint32_t SPI_MEM_DQS1_AFIFO_OVF_INT_RAW : 1;/*!< The raw bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. 1: Triggered + when the AFIFO connected to SPI_DQS is overflow. */ + __IOM uint32_t SPI_MEM_BUS_FIFO1_UDF_INT_RAW : 1;/*!< The raw bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. 1: Triggered + when BUS1 FIFO is underflow. */ + __IOM uint32_t SPI_MEM_BUS_FIFO0_UDF_INT_RAW : 1;/*!< The raw bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. 1: Triggered + when BUS0 FIFO is underflow. */ + } bit; + } SPI_MEM_INT_RAW; + + union { + __IOM uint32_t reg; /*!< SPI0 interrupt status register */ + + struct { + uint32_t : 3; + __IM uint32_t SPI_MEM_SLV_ST_END_INT_ST : 1;/*!< The status bit for SPI_MEM_SLV_ST_END_INT interrupt. */ + __IM uint32_t SPI_MEM_MST_ST_END_INT_ST : 1;/*!< The status bit for SPI_MEM_MST_ST_END_INT interrupt. */ + __IM uint32_t SPI_MEM_ECC_ERR_INT_ST : 1;/*!< The status bit for SPI_MEM_ECC_ERR_INT interrupt. */ + __IM uint32_t SPI_MEM_PMS_REJECT_INT_ST : 1;/*!< The status bit for SPI_MEM_PMS_REJECT_INT interrupt. */ + __IM uint32_t SPI_MEM_AXI_RADDR_ERR_INT_ST : 1;/*!< The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. */ + __IM uint32_t SPI_MEM_AXI_WR_FLASH_ERR_INT_ST : 1;/*!< The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. */ + __IM uint32_t SPI_MEM_AXI_WADDR_ERR_INT_ST : 1;/*!< The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. */ + uint32_t : 18; + __IM uint32_t SPI_MEM_DQS0_AFIFO_OVF_INT_ST : 1;/*!< The status bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. */ + __IM uint32_t SPI_MEM_DQS1_AFIFO_OVF_INT_ST : 1;/*!< The status bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. */ + __IM uint32_t SPI_MEM_BUS_FIFO1_UDF_INT_ST : 1;/*!< The status bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. */ + __IM uint32_t SPI_MEM_BUS_FIFO0_UDF_INT_ST : 1;/*!< The status bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. */ + } bit; + } SPI_MEM_INT_ST; + __IM uint32_t RESERVED5; + + union { + __IOM uint32_t reg; /*!< SPI0 flash DDR mode control register */ + + struct { + __IOM uint32_t SPI_FMEM_DDR_EN : 1; /*!< 1: in DDR mode, 0 in SDR mode */ + __IOM uint32_t SPI_FMEM_VAR_DUMMY : 1; /*!< Set the bit to enable variable dummy cycle in spi DDR mode. */ + __IOM uint32_t SPI_FMEM_DDR_RDAT_SWP : 1; /*!< Set the bit to reorder rx data of the word in spi DDR mode. */ + __IOM uint32_t SPI_FMEM_DDR_WDAT_SWP : 1; /*!< Set the bit to reorder tx data of the word in spi DDR mode. */ + __IOM uint32_t SPI_FMEM_DDR_CMD_DIS : 1; /*!< the bit is used to disable dual edge in command phase when DDR + mode. */ + __IOM uint32_t SPI_FMEM_OUTMINBYTELEN : 7;/*!< It is the minimum output data length in the panda device. */ + __IOM uint32_t SPI_FMEM_TX_DDR_MSK_EN : 1;/*!< Set this bit to mask the first or the last byte in SPI0 ECC + DDR write mode, when accesses to flash. */ + __IOM uint32_t SPI_FMEM_RX_DDR_MSK_EN : 1;/*!< Set this bit to mask the first or the last byte in SPI0 ECC + DDR read mode, when accesses to flash. */ + __IOM uint32_t SPI_FMEM_USR_DDR_DQS_THD : 7;/*!< The delay number of data strobe which from memory based on SPI + clock. */ + __IOM uint32_t SPI_FMEM_DDR_DQS_LOOP : 1; /*!< 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive + data when spi0_slv_st is in SPI_MEM_DIN state. It is used + when there is no SPI_DQS signal or SPI_DQS signal is not + stable. 0: SPI0 starts to store data at the positive and + negative edge of SPI_DQS. */ + uint32_t : 2; + __IOM uint32_t SPI_FMEM_CLK_DIFF_EN : 1; /*!< Set this bit to enable the differential SPI_CLK#. */ + uint32_t : 1; + __IOM uint32_t SPI_FMEM_DQS_CA_IN : 1; /*!< Set this bit to enable the input of SPI_DQS signal in SPI phases + of CMD and ADDR. */ + __IOM uint32_t SPI_FMEM_HYPERBUS_DUMMY_2X : 1;/*!< Set this bit to enable the vary dummy function in SPI HyperBus + mode, when SPI0 accesses flash or SPI1 accesses flash or + sram. */ + __IOM uint32_t SPI_FMEM_CLK_DIFF_INV : 1; /*!< Set this bit to invert SPI_DIFF when accesses to flash. . */ + __IOM uint32_t SPI_FMEM_OCTA_RAM_ADDR : 1;/*!< Set this bit to enable octa_ram address out when accesses to + flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], + 6'd0, spi_usr_addr_value[3:1], 1'b0}. */ + __IOM uint32_t SPI_FMEM_HYPERBUS_CA : 1; /*!< Set this bit to enable HyperRAM address out when accesses to + flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], + 13'd0, spi_usr_addr_value[3:1]}. */ + uint32_t : 1; + } bit; + } SPI_MEM_DDR; + + union { + __IOM uint32_t reg; /*!< SPI0 external RAM DDR mode control register */ + + struct { + __IOM uint32_t EN : 1; /*!< 1: in DDR mode, 0 in SDR mode */ + __IOM uint32_t SPI_SMEM_VAR_DUMMY : 1; /*!< Set the bit to enable variable dummy cycle in spi DDR mode. */ + __IOM uint32_t RDAT_SWP : 1; /*!< Set the bit to reorder rx data of the word in spi DDR mode. */ + __IOM uint32_t WDAT_SWP : 1; /*!< Set the bit to reorder tx data of the word in spi DDR mode. */ + __IOM uint32_t CMD_DIS : 1; /*!< the bit is used to disable dual edge in command phase when DDR + mode. */ + __IOM uint32_t SPI_SMEM_OUTMINBYTELEN : 7;/*!< It is the minimum output data length in the DDR psram. */ + __IOM uint32_t SPI_SMEM_TX_DDR_MSK_EN : 1;/*!< Set this bit to mask the first or the last byte in SPI0 ECC + DDR write mode, when accesses to external RAM. */ + __IOM uint32_t SPI_SMEM_RX_DDR_MSK_EN : 1;/*!< Set this bit to mask the first or the last byte in SPI0 ECC + DDR read mode, when accesses to external RAM. */ + __IOM uint32_t SPI_SMEM_USR_DDR_DQS_THD : 7;/*!< The delay number of data strobe which from memory based on SPI + clock. */ + __IOM uint32_t DQS_LOOP : 1; /*!< 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive + data when spi0_slv_st is in SPI_MEM_DIN state. It is used + when there is no SPI_DQS signal or SPI_DQS signal is not + stable. 0: SPI0 starts to store data at the positive and + negative edge of SPI_DQS. */ + uint32_t : 2; + __IOM uint32_t SPI_SMEM_CLK_DIFF_EN : 1; /*!< Set this bit to enable the differential SPI_CLK#. */ + uint32_t : 1; + __IOM uint32_t SPI_SMEM_DQS_CA_IN : 1; /*!< Set this bit to enable the input of SPI_DQS signal in SPI phases + of CMD and ADDR. */ + __IOM uint32_t SPI_SMEM_HYPERBUS_DUMMY_2X : 1;/*!< Set this bit to enable the vary dummy function in SPI HyperBus + mode, when SPI0 accesses flash or SPI1 accesses flash or + sram. */ + __IOM uint32_t SPI_SMEM_CLK_DIFF_INV : 1; /*!< Set this bit to invert SPI_DIFF when accesses to external RAM. + . */ + __IOM uint32_t SPI_SMEM_OCTA_RAM_ADDR : 1;/*!< Set this bit to enable octa_ram address out when accesses to + external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], + 6'd0, spi_usr_addr_value[3:1], 1'b0}. */ + __IOM uint32_t SPI_SMEM_HYPERBUS_CA : 1; /*!< Set this bit to enable HyperRAM address out when accesses to + external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], + 13'd0, spi_usr_addr_value[3:1]}. */ + uint32_t : 1; + } bit; + } SPI_SMEM_DDR; + __IM uint32_t RESERVED6[9]; + __IOM uint32_t SPI_FMEM_PMS0_ATTR; /*!< MSPI flash PMS section 0 attribute register */ + __IM uint32_t RESERVED7[3]; + + union { + __IOM uint32_t SPI_FMEM_PMS1_ATTR; /*!< MSPI flash PMS section 1 attribute register */ + __IOM uint32_t SPI_FMEM_PMS0_ADDR; /*!< SPI1 flash PMS section 0 start address register */ + }; + __IM uint32_t RESERVED8[3]; + + union { + __IOM uint32_t SPI_FMEM_PMS2_ATTR; /*!< MSPI flash PMS section 2 attribute register */ + __IOM uint32_t SPI_FMEM_PMS1_ADDR; /*!< SPI1 flash PMS section 1 start address register */ + __IOM uint32_t SPI_FMEM_PMS0_SIZE; /*!< SPI1 flash PMS section 0 start address register */ + }; + __IM uint32_t RESERVED9[3]; + + union { + __IOM uint32_t SPI_FMEM_PMS3_ATTR; /*!< MSPI flash PMS section 3 attribute register */ + __IOM uint32_t SPI_FMEM_PMS2_ADDR; /*!< SPI1 flash PMS section 2 start address register */ + __IOM uint32_t SPI_FMEM_PMS1_SIZE; /*!< SPI1 flash PMS section 1 start address register */ + __IOM uint32_t SPI_SMEM_PMS0_ATTR; /*!< SPI1 flash PMS section 0 start address register */ + }; + __IM uint32_t RESERVED10[3]; + + union { + __IOM uint32_t SPI_FMEM_PMS3_ADDR; /*!< SPI1 flash PMS section 3 start address register */ + __IOM uint32_t SPI_FMEM_PMS2_SIZE; /*!< SPI1 flash PMS section 2 start address register */ + __IOM uint32_t SPI_SMEM_PMS1_ATTR; /*!< SPI1 flash PMS section 1 start address register */ + __IOM uint32_t SPI_SMEM_PMS0_ADDR; /*!< SPI1 external RAM PMS section 0 start address register */ + }; + __IM uint32_t RESERVED11[3]; + + union { + __IOM uint32_t SPI_FMEM_PMS3_SIZE; /*!< SPI1 flash PMS section 3 start address register */ + __IOM uint32_t SPI_SMEM_PMS2_ATTR; /*!< SPI1 flash PMS section 2 start address register */ + __IOM uint32_t SPI_SMEM_PMS1_ADDR; /*!< SPI1 external RAM PMS section 1 start address register */ + __IOM uint32_t SPI_SMEM_PMS0_SIZE; /*!< SPI1 external RAM PMS section 0 start address register */ + }; + __IM uint32_t RESERVED12[3]; + + union { + __IOM uint32_t SPI_SMEM_PMS3_ATTR; /*!< SPI1 flash PMS section 3 start address register */ + __IOM uint32_t SPI_SMEM_PMS2_ADDR; /*!< SPI1 external RAM PMS section 2 start address register */ + __IOM uint32_t SPI_SMEM_PMS1_SIZE; /*!< SPI1 external RAM PMS section 1 start address register */ + }; + + union { + __IOM uint32_t reg; /*!< SPI1 access reject register */ + + struct { + __IM uint32_t SPI_MEM_REJECT_ADDR : 27; /*!< This bits show the first SPI1 access error address. It is cleared + by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. */ + __IOM uint32_t SPI_MEM_PM_EN : 1; /*!< Set this bit to enable SPI0/1 transfer permission control function. */ + __IM uint32_t SPI_MEM_PMS_LD : 1; /*!< 1: SPI1 write access error. 0: No write access error. It is + cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. */ + __IM uint32_t SPI_MEM_PMS_ST : 1; /*!< 1: SPI1 read access error. 0: No read access error. It is cleared + by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. */ + __IM uint32_t SPI_MEM_PMS_MULTI_HIT : 1; /*!< 1: SPI1 access is rejected because of address miss. 0: No address + miss error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR + bit is set. */ + __IM uint32_t SPI_MEM_PMS_IVD : 1; /*!< 1: SPI1 access is rejected because of address multi-hit. 0: + No address multi-hit error. It is cleared by when SPI_MEM_PMS_REJECT_INT_ + LR bit is set. */ + } bit; + } SPI_MEM_PMS_REJECT; + + union { + __IOM uint32_t reg; /*!< MSPI ECC control register */ + + struct { + uint32_t : 5; + __IM uint32_t SPI_MEM_ECC_ERR_CNT : 6; /*!< This bits show the error times of MSPI ECC read. It is cleared + by when SPI_MEM_ECC_ERR_INT_CLR bit is set. */ + __IOM uint32_t SPI_FMEM_ECC_ERR_INT_NUM : 6;/*!< Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT + interrupt. */ + __IOM uint32_t SPI_FMEM_ECC_ERR_INT_EN : 1;/*!< Set this bit to calculate the error times of MSPI ECC read when + accesses to flash. */ + __IOM uint32_t SPI_FMEM_PAGE_SIZE : 2; /*!< Set the page size of the flash accessed by MSPI. 0: 256 bytes. + 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes. */ + __IOM uint32_t SPI_FMEM_ECC_ADDR_EN : 1; /*!< Set this bit to enable MSPI ECC address conversion, no matter + MSPI accesses to the ECC region or non-ECC region of flash. + If there is no ECC region in flash, this bit should be + 0. Otherwise, this bit should be 1. */ + __IOM uint32_t SPI_MEM_USR_ECC_ADDR_EN : 1;/*!< Set this bit to enable ECC address convert in SPI0/1 USR_CMD + transfer. */ + uint32_t : 2; + __IOM uint32_t SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN : 1;/*!< 1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR + is updated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS + and SPI_MEM_ECC_ERR_ADDR record the first ECC error information. */ + __IM uint32_t SPI_MEM_ECC_ERR_BITS : 7; /*!< Records the first ECC error bit number in the 16 bytes(From + 0~127, corresponding to byte 0 bit 0 to byte 15 bit 7) */ + } bit; + } SPI_MEM_ECC_CTRL; + + union { + __IOM uint32_t reg; /*!< MSPI ECC error address register */ + + struct { + __IM uint32_t SPI_MEM_ECC_ERR_ADDR : 27; /*!< This bits show the first MSPI ECC error address. It is cleared + by when SPI_MEM_ECC_ERR_INT_CLR bit is set. */ + uint32_t : 5; + } bit; + } SPI_MEM_ECC_ERR_ADDR; + + union { + __IOM uint32_t SPI_SMEM_PMS3_ADDR; /*!< SPI1 external RAM PMS section 3 start address register */ + __IOM uint32_t SPI_SMEM_PMS2_SIZE; /*!< SPI1 external RAM PMS section 2 start address register */ + + union { + __IOM uint32_t reg; /*!< SPI0 AXI request error address. */ + + struct { + __IM uint32_t SPI_MEM_AXI_ERR_ADDR : 27;/*!< This bits show the first AXI write/read invalid error or AXI + write flash error address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_IN + _CLR, SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR + bit is set. */ + uint32_t : 5; + } bit; + } SPI_MEM_AXI_ERR_ADDR; + }; + + union { + __IOM uint32_t reg; /*!< MSPI ECC control register */ + + struct { + uint32_t : 17; + __IOM uint32_t SPI_SMEM_ECC_ERR_INT_EN : 1;/*!< Set this bit to calculate the error times of MSPI ECC read when + accesses to external RAM. */ + __IOM uint32_t SPI_SMEM_PAGE_SIZE : 2; /*!< Set the page size of the external RAM accessed by MSPI. 0: 256 + bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes. */ + __IOM uint32_t SPI_SMEM_ECC_ADDR_EN : 1; /*!< Set this bit to enable MSPI ECC address conversion, no matter + MSPI accesses to the ECC region or non-ECC region of external + RAM. If there is no ECC region in external RAM, this bit + should be 0. Otherwise, this bit should be 1. */ + uint32_t : 11; + } bit; + } SPI_SMEM_ECC_CTRL; + + union { + __IOM uint32_t reg; /*!< SPI0 AXI address control register */ + + struct { + uint32_t : 26; + __IM uint32_t SPI_MEM_ALL_FIFO_EMPTY : 1;/*!< The empty status of all AFIFO and SYNC_FIFO in MSPI module. + 1: All AXI transfers and SPI0 transfers are done. 0: Others. */ + __IM uint32_t SPI_RDATA_AFIFO_REMPTY : 1;/*!< 1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is + pending. */ + __IM uint32_t SPI_RADDR_AFIFO_REMPTY : 1;/*!< 1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer + is pending. */ + __IM uint32_t SPI_WDATA_AFIFO_REMPTY : 1;/*!< 1: WDATA_AFIFO is empty. 0: At least one AXI write transfer + is pending. */ + __IM uint32_t SPI_WBLEN_AFIFO_REMPTY : 1;/*!< 1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer + is pending. */ + __IM uint32_t SPI_ALL_AXI_TRANS_AFIFO_EMPTY : 1;/*!< This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, + AXI_RADDR_CTL_AFIFO and RDATA_AFIFO are empty and spi0_mst_st + is IDLE. */ + } bit; + } SPI_SMEM_AXI_ADDR_CTRL; + + union { + __IOM uint32_t reg; /*!< SPI0 AXI error response enable register */ + + struct { + __IOM uint32_t SPI_MEM_AW_RESP_EN_MMU_VLD : 1;/*!< Set this bit to enable AXI response function for mmu valid err + in axi write trans. */ + __IOM uint32_t SPI_MEM_AW_RESP_EN_MMU_GID : 1;/*!< Set this bit to enable AXI response function for mmu gid err + in axi write trans. */ + __IOM uint32_t SPI_MEM_AW_RESP_EN_AXI_SIZE : 1;/*!< Set this bit to enable AXI response function for axi size err + in axi write trans. */ + __IOM uint32_t SPI_MEM_AW_RESP_EN_AXI_FLASH : 1;/*!< Set this bit to enable AXI response function for axi flash err + in axi write trans. */ + __IOM uint32_t SPI_MEM_AW_RESP_EN_MMU_ECC : 1;/*!< Set this bit to enable AXI response function for mmu ecc err + in axi write trans. */ + __IOM uint32_t SPI_MEM_AW_RESP_EN_MMU_SENS : 1;/*!< Set this bit to enable AXI response function for mmu sens in + err axi write trans. */ + __IOM uint32_t SPI_MEM_AW_RESP_EN_AXI_WSTRB : 1;/*!< Set this bit to enable AXI response function for axi wstrb err + in axi write trans. */ + __IOM uint32_t SPI_MEM_AR_RESP_EN_MMU_VLD : 1;/*!< Set this bit to enable AXI response function for mmu valid err + in axi read trans. */ + __IOM uint32_t SPI_MEM_AR_RESP_EN_MMU_GID : 1;/*!< Set this bit to enable AXI response function for mmu gid err + in axi read trans. */ + __IOM uint32_t SPI_MEM_AR_RESP_EN_MMU_ECC : 1;/*!< Set this bit to enable AXI response function for mmu ecc err + in axi read trans. */ + __IOM uint32_t SPI_MEM_AR_RESP_EN_MMU_SENS : 1;/*!< Set this bit to enable AXI response function for mmu sensitive + err in axi read trans. */ + __IOM uint32_t SPI_MEM_AR_RESP_EN_AXI_SIZE : 1;/*!< Set this bit to enable AXI response function for axi size err + in axi read trans. */ + uint32_t : 20; + } bit; + } SPI_MEM_AXI_ERR_RESP_EN; + + union { + __IOM uint32_t SPI_SMEM_PMS3_SIZE; /*!< SPI1 external RAM PMS section 3 start address register */ + + union { + __IOM uint32_t reg; /*!< SPI0 flash timing calibration register */ + + struct { + __IOM uint32_t SPI_MEM_TIMING_CLK_ENA : 1;/*!< The bit is used to enable timing adjust clock for all reading + operations. */ + __IOM uint32_t SPI_MEM_TIMING_CALI : 1; /*!< The bit is used to enable timing auto-calibration for all reading + operations. */ + __IOM uint32_t SPI_MEM_EXTRA_DUMMY_CYCLELEN : 3;/*!< add extra dummy spi clock cycle length for spi clock calibration. */ + __IOM uint32_t SPI_MEM_DLL_TIMING_CALI : 1;/*!< Set this bit to enable DLL for timing calibration in DDR mode + when accessed to flash. */ + __OM uint32_t UPDATE : 1; /*!< Set this bit to update delay mode, delay num and extra dummy + in MSPI. */ + uint32_t : 25; + } bit; + } SPI_MEM_TIMING_CALI; + }; + + union { + __IOM uint32_t reg; /*!< MSPI flash input timing delay mode control register */ + + struct { + __IOM uint32_t SPI_MEM_DIN0_MODE : 3; /*!< the input signals are delayed by system clock cycles, 0: input + without delayed, 1: input with the posedge of clk_apb,2 + input with the negedge of clk_apb, 3: input with the posedge + of clk_160, 4 input with the negedge of clk_160, 5: input + with the spi_clk high edge, 6: input with the spi_clk low + edge */ + __IOM uint32_t SPI_MEM_DIN1_MODE : 3; /*!< the input signals are delayed by system clock cycles, 0: input + without delayed, 1: input with the posedge of clk_apb,2 + input with the negedge of clk_apb, 3: input with the posedge + of clk_160, 4 input with the negedge of clk_160, 5: input + with the spi_clk high edge, 6: input with the spi_clk low + edge */ + __IOM uint32_t SPI_MEM_DIN2_MODE : 3; /*!< the input signals are delayed by system clock cycles, 0: input + without delayed, 1: input with the posedge of clk_apb,2 + input with the negedge of clk_apb, 3: input with the posedge + of clk_160, 4 input with the negedge of clk_160, 5: input + with the spi_clk high edge, 6: input with the spi_clk low + edge */ + __IOM uint32_t SPI_MEM_DIN3_MODE : 3; /*!< the input signals are delayed by system clock cycles, 0: input + without delayed, 1: input with the posedge of clk_apb,2 + input with the negedge of clk_apb, 3: input with the posedge + of clk_160, 4 input with the negedge of clk_160, 5: input + with the spi_clk high edge, 6: input with the spi_clk low + edge */ + __IOM uint32_t SPI_MEM_DIN4_MODE : 3; /*!< the input signals are delayed by system clock cycles, 0: input + without delayed, 1: input with the posedge of clk_apb,2 + input with the negedge of clk_apb, 3: input with the spi_clk */ + __IOM uint32_t SPI_MEM_DIN5_MODE : 3; /*!< the input signals are delayed by system clock cycles, 0: input + without delayed, 1: input with the posedge of clk_apb,2 + input with the negedge of clk_apb, 3: input with the spi_clk */ + __IOM uint32_t SPI_MEM_DIN6_MODE : 3; /*!< the input signals are delayed by system clock cycles, 0: input + without delayed, 1: input with the posedge of clk_apb,2 + input with the negedge of clk_apb, 3: input with the spi_clk */ + __IOM uint32_t SPI_MEM_DIN7_MODE : 3; /*!< the input signals are delayed by system clock cycles, 0: input + without delayed, 1: input with the posedge of clk_apb,2 + input with the negedge of clk_apb, 3: input with the spi_clk */ + __IOM uint32_t SPI_MEM_DINS_MODE : 3; /*!< the input signals are delayed by system clock cycles, 0: input + without delayed, 1: input with the posedge of clk_apb,2 + input with the negedge of clk_apb, 3: input with the spi_clk */ + uint32_t : 5; + } bit; + } SPI_MEM_DIN_MODE; + + union { + __IOM uint32_t reg; /*!< MSPI flash input timing delay number control register */ + + struct { + __IOM uint32_t SPI_MEM_DIN0_NUM : 2; /*!< the input signals are delayed by system clock cycles, 0: delayed + by 1 cycle, 1: delayed by 2 cycles,... */ + __IOM uint32_t SPI_MEM_DIN1_NUM : 2; /*!< the input signals are delayed by system clock cycles, 0: delayed + by 1 cycle, 1: delayed by 2 cycles,... */ + __IOM uint32_t SPI_MEM_DIN2_NUM : 2; /*!< the input signals are delayed by system clock cycles, 0: delayed + by 1 cycle, 1: delayed by 2 cycles,... */ + __IOM uint32_t SPI_MEM_DIN3_NUM : 2; /*!< the input signals are delayed by system clock cycles, 0: delayed + by 1 cycle, 1: delayed by 2 cycles,... */ + __IOM uint32_t SPI_MEM_DIN4_NUM : 2; /*!< the input signals are delayed by system clock cycles, 0: delayed + by 1 cycle, 1: delayed by 2 cycles,... */ + __IOM uint32_t SPI_MEM_DIN5_NUM : 2; /*!< the input signals are delayed by system clock cycles, 0: delayed + by 1 cycle, 1: delayed by 2 cycles,... */ + __IOM uint32_t SPI_MEM_DIN6_NUM : 2; /*!< the input signals are delayed by system clock cycles, 0: delayed + by 1 cycle, 1: delayed by 2 cycles,... */ + __IOM uint32_t SPI_MEM_DIN7_NUM : 2; /*!< the input signals are delayed by system clock cycles, 0: delayed + by 1 cycle, 1: delayed by 2 cycles,... */ + __IOM uint32_t SPI_MEM_DINS_NUM : 2; /*!< the input signals are delayed by system clock cycles, 0: delayed + by 1 cycle, 1: delayed by 2 cycles,... */ + uint32_t : 14; + } bit; + } SPI_MEM_DIN_NUM; + + union { + __IOM uint32_t reg; /*!< MSPI flash output timing adjustment control register */ + + struct { + __IOM uint32_t SPI_MEM_DOUT0_MODE : 1; /*!< the output signals are delayed by system clock cycles, 0: output + without delayed, 1: output with the posedge of clk_apb,2 + output with the negedge of clk_apb, 3: output with the + posedge of clk_160,4 output with the negedge of clk_160,5: + output with the spi_clk high edge ,6: output with the spi_clk + low edge */ + __IOM uint32_t SPI_MEM_DOUT1_MODE : 1; /*!< the output signals are delayed by system clock cycles, 0: output + without delayed, 1: output with the posedge of clk_apb,2 + output with the negedge of clk_apb, 3: output with the + posedge of clk_160,4 output with the negedge of clk_160,5: + output with the spi_clk high edge ,6: output with the spi_clk + low edge */ + __IOM uint32_t SPI_MEM_DOUT2_MODE : 1; /*!< the output signals are delayed by system clock cycles, 0: output + without delayed, 1: output with the posedge of clk_apb,2 + output with the negedge of clk_apb, 3: output with the + posedge of clk_160,4 output with the negedge of clk_160,5: + output with the spi_clk high edge ,6: output with the spi_clk + low edge */ + __IOM uint32_t SPI_MEM_DOUT3_MODE : 1; /*!< the output signals are delayed by system clock cycles, 0: output + without delayed, 1: output with the posedge of clk_apb,2 + output with the negedge of clk_apb, 3: output with the + posedge of clk_160,4 output with the negedge of clk_160,5: + output with the spi_clk high edge ,6: output with the spi_clk + low edge */ + __IOM uint32_t SPI_MEM_DOUT4_MODE : 1; /*!< the output signals are delayed by system clock cycles, 0: output + without delayed, 1: output with the posedge of clk_apb,2 + output with the negedge of clk_apb, 3: output with the + spi_clk */ + __IOM uint32_t SPI_MEM_DOUT5_MODE : 1; /*!< the output signals are delayed by system clock cycles, 0: output + without delayed, 1: output with the posedge of clk_apb,2 + output with the negedge of clk_apb, 3: output with the + spi_clk */ + __IOM uint32_t SPI_MEM_DOUT6_MODE : 1; /*!< the output signals are delayed by system clock cycles, 0: output + without delayed, 1: output with the posedge of clk_apb,2 + output with the negedge of clk_apb, 3: output with the + spi_clk */ + __IOM uint32_t SPI_MEM_DOUT7_MODE : 1; /*!< the output signals are delayed by system clock cycles, 0: output + without delayed, 1: output with the posedge of clk_apb,2 + output with the negedge of clk_apb, 3: output with the + spi_clk */ + __IOM uint32_t SPI_MEM_DOUTS_MODE : 1; /*!< the output signals are delayed by system clock cycles, 0: output + without delayed, 1: output with the posedge of clk_apb,2 + output with the negedge of clk_apb, 3: output with the + spi_clk */ + uint32_t : 23; + } bit; + } SPI_MEM_DOUT_MODE; + + union { + __IOM uint32_t reg; /*!< MSPI external RAM timing calibration register */ + + struct { + __IOM uint32_t SPI_SMEM_TIMING_CLK_ENA : 1;/*!< For sram, the bit is used to enable timing adjust clock for + all reading operations. */ + __IOM uint32_t SPI_SMEM_TIMING_CALI : 1; /*!< For sram, the bit is used to enable timing auto-calibration + for all reading operations. */ + __IOM uint32_t SPI_SMEM_EXTRA_DUMMY_CYCLELEN : 3;/*!< For sram, add extra dummy spi clock cycle length for spi clock + calibration. */ + __IOM uint32_t SPI_SMEM_DLL_TIMING_CALI : 1;/*!< Set this bit to enable DLL for timing calibration in DDR mode + when accessed to EXT_RAM. */ + uint32_t : 26; + } bit; + } SPI_SMEM_TIMING_CALI; + + union { + __IOM uint32_t reg; /*!< MSPI external RAM input timing delay mode control register */ + + struct { + __IOM uint32_t SPI_SMEM_DIN0_MODE : 3; /*!< the input signals are delayed by system clock cycles, 0: input + without delayed, 1: input with the posedge of clk_apb,2 + input with the negedge of clk_apb, 3: input with the posedge + of clk_160, 4 input with the negedge of clk_160, 5: input + with the spi_clk high edge, 6: input with the spi_clk low + edge */ + __IOM uint32_t SPI_SMEM_DIN1_MODE : 3; /*!< the input signals are delayed by system clock cycles, 0: input + without delayed, 1: input with the posedge of clk_apb,2 + input with the negedge of clk_apb, 3: input with the posedge + of clk_160, 4 input with the negedge of clk_160, 5: input + with the spi_clk high edge, 6: input with the spi_clk low + edge */ + __IOM uint32_t SPI_SMEM_DIN2_MODE : 3; /*!< the input signals are delayed by system clock cycles, 0: input + without delayed, 1: input with the posedge of clk_apb,2 + input with the negedge of clk_apb, 3: input with the posedge + of clk_160, 4 input with the negedge of clk_160, 5: input + with the spi_clk high edge, 6: input with the spi_clk low + edge */ + __IOM uint32_t SPI_SMEM_DIN3_MODE : 3; /*!< the input signals are delayed by system clock cycles, 0: input + without delayed, 1: input with the posedge of clk_apb,2 + input with the negedge of clk_apb, 3: input with the posedge + of clk_160, 4 input with the negedge of clk_160, 5: input + with the spi_clk high edge, 6: input with the spi_clk low + edge */ + __IOM uint32_t SPI_SMEM_DIN4_MODE : 3; /*!< the input signals are delayed by system clock cycles, 0: input + without delayed, 1: input with the posedge of clk_apb,2 + input with the negedge of clk_apb, 3: input with the posedge + of clk_160, 4 input with the negedge of clk_160, 5: input + with the spi_clk high edge, 6: input with the spi_clk low + edge */ + __IOM uint32_t SPI_SMEM_DIN5_MODE : 3; /*!< the input signals are delayed by system clock cycles, 0: input + without delayed, 1: input with the posedge of clk_apb,2 + input with the negedge of clk_apb, 3: input with the posedge + of clk_160, 4 input with the negedge of clk_160, 5: input + with the spi_clk high edge, 6: input with the spi_clk low + edge */ + __IOM uint32_t SPI_SMEM_DIN6_MODE : 3; /*!< the input signals are delayed by system clock cycles, 0: input + without delayed, 1: input with the posedge of clk_apb,2 + input with the negedge of clk_apb, 3: input with the posedge + of clk_160, 4 input with the negedge of clk_160, 5: input + with the spi_clk high edge, 6: input with the spi_clk low + edge */ + __IOM uint32_t SPI_SMEM_DIN7_MODE : 3; /*!< the input signals are delayed by system clock cycles, 0: input + without delayed, 1: input with the posedge of clk_apb,2 + input with the negedge of clk_apb, 3: input with the posedge + of clk_160, 4 input with the negedge of clk_160, 5: input + with the spi_clk high edge, 6: input with the spi_clk low + edge */ + __IOM uint32_t SPI_SMEM_DINS_MODE : 3; /*!< the input signals are delayed by system clock cycles, 0: input + without delayed, 1: input with the posedge of clk_apb,2 + input with the negedge of clk_apb, 3: input with the posedge + of clk_160, 4 input with the negedge of clk_160, 5: input + with the spi_clk high edge, 6: input with the spi_clk low + edge */ + uint32_t : 5; + } bit; + } SPI_SMEM_DIN_MODE; + + union { + __IOM uint32_t reg; /*!< MSPI external RAM input timing delay number control register */ + + struct { + __IOM uint32_t SPI_SMEM_DIN0_NUM : 2; /*!< the input signals are delayed by system clock cycles, 0: delayed + by 1 cycle, 1: delayed by 2 cycles,... */ + __IOM uint32_t SPI_SMEM_DIN1_NUM : 2; /*!< the input signals are delayed by system clock cycles, 0: delayed + by 1 cycle, 1: delayed by 2 cycles,... */ + __IOM uint32_t SPI_SMEM_DIN2_NUM : 2; /*!< the input signals are delayed by system clock cycles, 0: delayed + by 1 cycle, 1: delayed by 2 cycles,... */ + __IOM uint32_t SPI_SMEM_DIN3_NUM : 2; /*!< the input signals are delayed by system clock cycles, 0: delayed + by 1 cycle, 1: delayed by 2 cycles,... */ + __IOM uint32_t SPI_SMEM_DIN4_NUM : 2; /*!< the input signals are delayed by system clock cycles, 0: delayed + by 1 cycle, 1: delayed by 2 cycles,... */ + __IOM uint32_t SPI_SMEM_DIN5_NUM : 2; /*!< the input signals are delayed by system clock cycles, 0: delayed + by 1 cycle, 1: delayed by 2 cycles,... */ + __IOM uint32_t SPI_SMEM_DIN6_NUM : 2; /*!< the input signals are delayed by system clock cycles, 0: delayed + by 1 cycle, 1: delayed by 2 cycles,... */ + __IOM uint32_t SPI_SMEM_DIN7_NUM : 2; /*!< the input signals are delayed by system clock cycles, 0: delayed + by 1 cycle, 1: delayed by 2 cycles,... */ + __IOM uint32_t SPI_SMEM_DINS_NUM : 2; /*!< the input signals are delayed by system clock cycles, 0: delayed + by 1 cycle, 1: delayed by 2 cycles,... */ + uint32_t : 14; + } bit; + } SPI_SMEM_DIN_NUM; + + union { + __IOM uint32_t reg; /*!< MSPI external RAM output timing adjustment control register */ + + struct { + __IOM uint32_t SPI_SMEM_DOUT0_MODE : 1; /*!< the output signals are delayed by system clock cycles, 0: output + without delayed, 1: output with the posedge of clk_apb,2 + output with the negedge of clk_apb, 3: output with the + posedge of clk_160,4 output with the negedge of clk_160,5: + output with the spi_clk high edge ,6: output with the spi_clk + low edge */ + __IOM uint32_t SPI_SMEM_DOUT1_MODE : 1; /*!< the output signals are delayed by system clock cycles, 0: output + without delayed, 1: output with the posedge of clk_apb,2 + output with the negedge of clk_apb, 3: output with the + posedge of clk_160,4 output with the negedge of clk_160,5: + output with the spi_clk high edge ,6: output with the spi_clk + low edge */ + __IOM uint32_t SPI_SMEM_DOUT2_MODE : 1; /*!< the output signals are delayed by system clock cycles, 0: output + without delayed, 1: output with the posedge of clk_apb,2 + output with the negedge of clk_apb, 3: output with the + posedge of clk_160,4 output with the negedge of clk_160,5: + output with the spi_clk high edge ,6: output with the spi_clk + low edge */ + __IOM uint32_t SPI_SMEM_DOUT3_MODE : 1; /*!< the output signals are delayed by system clock cycles, 0: output + without delayed, 1: output with the posedge of clk_apb,2 + output with the negedge of clk_apb, 3: output with the + posedge of clk_160,4 output with the negedge of clk_160,5: + output with the spi_clk high edge ,6: output with the spi_clk + low edge */ + __IOM uint32_t SPI_SMEM_DOUT4_MODE : 1; /*!< the output signals are delayed by system clock cycles, 0: output + without delayed, 1: output with the posedge of clk_apb,2 + output with the negedge of clk_apb, 3: output with the + posedge of clk_160,4 output with the negedge of clk_160,5: + output with the spi_clk high edge ,6: output with the spi_clk + low edge */ + __IOM uint32_t SPI_SMEM_DOUT5_MODE : 1; /*!< the output signals are delayed by system clock cycles, 0: output + without delayed, 1: output with the posedge of clk_apb,2 + output with the negedge of clk_apb, 3: output with the + posedge of clk_160,4 output with the negedge of clk_160,5: + output with the spi_clk high edge ,6: output with the spi_clk + low edge */ + __IOM uint32_t SPI_SMEM_DOUT6_MODE : 1; /*!< the output signals are delayed by system clock cycles, 0: output + without delayed, 1: output with the posedge of clk_apb,2 + output with the negedge of clk_apb, 3: output with the + posedge of clk_160,4 output with the negedge of clk_160,5: + output with the spi_clk high edge ,6: output with the spi_clk + low edge */ + __IOM uint32_t SPI_SMEM_DOUT7_MODE : 1; /*!< the output signals are delayed by system clock cycles, 0: output + without delayed, 1: output with the posedge of clk_apb,2 + output with the negedge of clk_apb, 3: output with the + posedge of clk_160,4 output with the negedge of clk_160,5: + output with the spi_clk high edge ,6: output with the spi_clk + low edge */ + __IOM uint32_t SPI_SMEM_DOUTS_MODE : 1; /*!< the output signals are delayed by system clock cycles, 0: output + without delayed, 1: output with the posedge of clk_apb,2 + output with the negedge of clk_apb, 3: output with the + posedge of clk_160,4 output with the negedge of clk_160,5: + output with the spi_clk high edge ,6: output with the spi_clk + low edge */ + uint32_t : 23; + } bit; + } SPI_SMEM_DOUT_MODE; + + union { + __IOM uint32_t reg; /*!< MSPI external RAM ECC and SPI CS timing control register */ + + struct { + __IOM uint32_t SPI_SMEM_CS_SETUP : 1; /*!< For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. + 1: enable 0: disable. */ + __IOM uint32_t SPI_SMEM_CS_HOLD : 1; /*!< For SPI0 and SPI1, spi cs keep low when spi is in done phase. + 1: enable 0: disable. */ + __IOM uint32_t SPI_SMEM_CS_SETUP_TIME : 5;/*!< For spi0, (cycles-1) of prepare phase by spi clock this bits + are combined with spi_mem_cs_setup bit. */ + __IOM uint32_t SPI_SMEM_CS_HOLD_TIME : 5; /*!< For SPI0 and SPI1, spi cs signal is delayed to inactive by spi + clock this bits are combined with spi_mem_cs_hold bit. */ + __IOM uint32_t SPI_SMEM_ECC_CS_HOLD_TIME : 3;/*!< SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 + and SPI1 CS hold cycles in ECC mode when accessed external + RAM. */ + __IOM uint32_t SPI_SMEM_ECC_SKIP_PAGE_CORNER : 1;/*!< 1: SPI0 skips page corner when accesses external RAM. 0: Not + skip page corner when accesses external RAM. */ + __IOM uint32_t SPI_SMEM_ECC_16TO18_BYTE_EN : 1;/*!< Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with + 2 ECC bytes mode when accesses external RAM. */ + uint32_t : 8; + __IOM uint32_t SPI_SMEM_CS_HOLD_DELAY : 6;/*!< These bits are used to set the minimum CS high time tSHSL between + SPI burst transfer when accesses to external RAM. tSHSL + is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles. */ + __IOM uint32_t SPI_SMEM_SPLIT_TRANS_EN : 1;/*!< Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer + into two SPI transfers when one transfer will cross flash/EXT_RAM + page corner, valid no matter whether there is an ECC region + or not. */ + } bit; + } SPI_SMEM_AC; + + union { + __IOM uint32_t reg; /*!< MSPI 16x external RAM input timing delay mode control register */ + + struct { + __IOM uint32_t SPI_SMEM_DIN08_MODE : 3; /*!< the input signals are delayed by system clock cycles, 0: input + without delayed, 1: input with the posedge of clk_apb,2 + input with the negedge of clk_apb, 3: input with the posedge + of clk_160, 4 input with the negedge of clk_160, 5: input + with the spi_clk high edge, 6: input with the spi_clk low + edge */ + __IOM uint32_t SPI_SMEM_DIN09_MODE : 3; /*!< the input signals are delayed by system clock cycles, 0: input + without delayed, 1: input with the posedge of clk_apb,2 + input with the negedge of clk_apb, 3: input with the posedge + of clk_160, 4 input with the negedge of clk_160, 5: input + with the spi_clk high edge, 6: input with the spi_clk low + edge */ + __IOM uint32_t SPI_SMEM_DIN10_MODE : 3; /*!< the input signals are delayed by system clock cycles, 0: input + without delayed, 1: input with the posedge of clk_apb,2 + input with the negedge of clk_apb, 3: input with the posedge + of clk_160, 4 input with the negedge of clk_160, 5: input + with the spi_clk high edge, 6: input with the spi_clk low + edge */ + __IOM uint32_t SPI_SMEM_DIN11_MODE : 3; /*!< the input signals are delayed by system clock cycles, 0: input + without delayed, 1: input with the posedge of clk_apb,2 + input with the negedge of clk_apb, 3: input with the posedge + of clk_160, 4 input with the negedge of clk_160, 5: input + with the spi_clk high edge, 6: input with the spi_clk low + edge */ + __IOM uint32_t SPI_SMEM_DIN12_MODE : 3; /*!< the input signals are delayed by system clock cycles, 0: input + without delayed, 1: input with the posedge of clk_apb,2 + input with the negedge of clk_apb, 3: input with the posedge + of clk_160, 4 input with the negedge of clk_160, 5: input + with the spi_clk high edge, 6: input with the spi_clk low + edge */ + __IOM uint32_t SPI_SMEM_DIN13_MODE : 3; /*!< the input signals are delayed by system clock cycles, 0: input + without delayed, 1: input with the posedge of clk_apb,2 + input with the negedge of clk_apb, 3: input with the posedge + of clk_160, 4 input with the negedge of clk_160, 5: input + with the spi_clk high edge, 6: input with the spi_clk low + edge */ + __IOM uint32_t SPI_SMEM_DIN14_MODE : 3; /*!< the input signals are delayed by system clock cycles, 0: input + without delayed, 1: input with the posedge of clk_apb,2 + input with the negedge of clk_apb, 3: input with the posedge + of clk_160, 4 input with the negedge of clk_160, 5: input + with the spi_clk high edge, 6: input with the spi_clk low + edge */ + __IOM uint32_t SPI_SMEM_DIN15_MODE : 3; /*!< the input signals are delayed by system clock cycles, 0: input + without delayed, 1: input with the posedge of clk_apb,2 + input with the negedge of clk_apb, 3: input with the posedge + of clk_160, 4 input with the negedge of clk_160, 5: input + with the spi_clk high edge, 6: input with the spi_clk low + edge */ + __IOM uint32_t SPI_SMEM_DINS_HEX_MODE : 3;/*!< the input signals are delayed by system clock cycles, 0: input + without delayed, 1: input with the posedge of clk_apb,2 + input with the negedge of clk_apb, 3: input with the posedge + of clk_160, 4 input with the negedge of clk_160, 5: input + with the spi_clk high edge, 6: input with the spi_clk low + edge */ + uint32_t : 5; + } bit; + } SPI_SMEM_DIN_HEX_MODE; + + union { + __IOM uint32_t reg; /*!< MSPI 16x external RAM input timing delay number control register */ + + struct { + __IOM uint32_t SPI_SMEM_DIN08_NUM : 2; /*!< the input signals are delayed by system clock cycles, 0: delayed + by 1 cycle, 1: delayed by 2 cycles,... */ + __IOM uint32_t SPI_SMEM_DIN09_NUM : 2; /*!< the input signals are delayed by system clock cycles, 0: delayed + by 1 cycle, 1: delayed by 2 cycles,... */ + __IOM uint32_t SPI_SMEM_DIN10_NUM : 2; /*!< the input signals are delayed by system clock cycles, 0: delayed + by 1 cycle, 1: delayed by 2 cycles,... */ + __IOM uint32_t SPI_SMEM_DIN11_NUM : 2; /*!< the input signals are delayed by system clock cycles, 0: delayed + by 1 cycle, 1: delayed by 2 cycles,... */ + __IOM uint32_t SPI_SMEM_DIN12_NUM : 2; /*!< the input signals are delayed by system clock cycles, 0: delayed + by 1 cycle, 1: delayed by 2 cycles,... */ + __IOM uint32_t SPI_SMEM_DIN13_NUM : 2; /*!< the input signals are delayed by system clock cycles, 0: delayed + by 1 cycle, 1: delayed by 2 cycles,... */ + __IOM uint32_t SPI_SMEM_DIN14_NUM : 2; /*!< the input signals are delayed by system clock cycles, 0: delayed + by 1 cycle, 1: delayed by 2 cycles,... */ + __IOM uint32_t SPI_SMEM_DIN15_NUM : 2; /*!< the input signals are delayed by system clock cycles, 0: delayed + by 1 cycle, 1: delayed by 2 cycles,... */ + __IOM uint32_t SPI_SMEM_DINS_HEX_NUM : 2; /*!< the input signals are delayed by system clock cycles, 0: delayed + by 1 cycle, 1: delayed by 2 cycles,... */ + uint32_t : 14; + } bit; + } SPI_SMEM_DIN_HEX_NUM; + + union { + __IOM uint32_t reg; /*!< MSPI 16x external RAM output timing adjustment control register */ + + struct { + __IOM uint32_t SPI_SMEM_DOUT08_MODE : 1; /*!< the output signals are delayed by system clock cycles, 0: output + without delayed, 1: output with the posedge of clk_apb,2 + output with the negedge of clk_apb, 3: output with the + posedge of clk_160,4 output with the negedge of clk_160,5: + output with the spi_clk high edge ,6: output with the spi_clk + low edge */ + __IOM uint32_t SPI_SMEM_DOUT09_MODE : 1; /*!< the output signals are delayed by system clock cycles, 0: output + without delayed, 1: output with the posedge of clk_apb,2 + output with the negedge of clk_apb, 3: output with the + posedge of clk_160,4 output with the negedge of clk_160,5: + output with the spi_clk high edge ,6: output with the spi_clk + low edge */ + __IOM uint32_t SPI_SMEM_DOUT10_MODE : 1; /*!< the output signals are delayed by system clock cycles, 0: output + without delayed, 1: output with the posedge of clk_apb,2 + output with the negedge of clk_apb, 3: output with the + posedge of clk_160,4 output with the negedge of clk_160,5: + output with the spi_clk high edge ,6: output with the spi_clk + low edge */ + __IOM uint32_t SPI_SMEM_DOUT11_MODE : 1; /*!< the output signals are delayed by system clock cycles, 0: output + without delayed, 1: output with the posedge of clk_apb,2 + output with the negedge of clk_apb, 3: output with the + posedge of clk_160,4 output with the negedge of clk_160,5: + output with the spi_clk high edge ,6: output with the spi_clk + low edge */ + __IOM uint32_t SPI_SMEM_DOUT12_MODE : 1; /*!< the output signals are delayed by system clock cycles, 0: output + without delayed, 1: output with the posedge of clk_apb,2 + output with the negedge of clk_apb, 3: output with the + posedge of clk_160,4 output with the negedge of clk_160,5: + output with the spi_clk high edge ,6: output with the spi_clk + low edge */ + __IOM uint32_t SPI_SMEM_DOUT13_MODE : 1; /*!< the output signals are delayed by system clock cycles, 0: output + without delayed, 1: output with the posedge of clk_apb,2 + output with the negedge of clk_apb, 3: output with the + posedge of clk_160,4 output with the negedge of clk_160,5: + output with the spi_clk high edge ,6: output with the spi_clk + low edge */ + __IOM uint32_t SPI_SMEM_DOUT14_MODE : 1; /*!< the output signals are delayed by system clock cycles, 0: output + without delayed, 1: output with the posedge of clk_apb,2 + output with the negedge of clk_apb, 3: output with the + posedge of clk_160,4 output with the negedge of clk_160,5: + output with the spi_clk high edge ,6: output with the spi_clk + low edge */ + __IOM uint32_t SPI_SMEM_DOUT15_MODE : 1; /*!< the output signals are delayed by system clock cycles, 0: output + without delayed, 1: output with the posedge of clk_apb,2 + output with the negedge of clk_apb, 3: output with the + posedge of clk_160,4 output with the negedge of clk_160,5: + output with the spi_clk high edge ,6: output with the spi_clk + low edge */ + __IOM uint32_t SPI_SMEM_DOUTS_HEX_MODE : 1;/*!< the output signals are delayed by system clock cycles, 0: output + without delayed, 1: output with the posedge of clk_apb,2 + output with the negedge of clk_apb, 3: output with the + posedge of clk_160,4 output with the negedge of clk_160,5: + output with the spi_clk high edge ,6: output with the spi_clk + low edge */ + uint32_t : 23; + } bit; + } SPI_SMEM_DOUT_HEX_MODE; + __IM uint32_t RESERVED13[20]; + + union { + __IOM uint32_t reg; /*!< SPI0 clock gate register */ + + struct { + __IOM uint32_t SPI_CLK_EN : 1; /*!< Register clock gate enable signal. 1: Enable. 0: Disable. */ + uint32_t : 31; + } bit; + } SPI_MEM_CLOCK_GATE; + __IM uint32_t RESERVED14[63]; + + union { + __IOM uint32_t reg; /*!< The base address of the memory that stores plaintext in Manual + Encryption */ + + struct { + __IOM uint32_t SPI_XTS_PLAIN : 32; /*!< This field is only used to generate include file in c case. + This field is useless. Please do not use this field. */ + } bit; + } SPI_MEM_XTS_PLAIN_BASE; + __IM uint32_t RESERVED15[15]; + + union { + __IOM uint32_t reg; /*!< Manual Encryption Line-Size register */ + + struct { + __IOM uint32_t SPI_XTS_LINESIZE : 2; /*!< This bits stores the line-size parameter which will be used + in manual encryption calculation. It decides how many bytes + will be encrypted one time. 0: 16-bytes, 1: 32-bytes, 2: + 64-bytes, 3:reserved. */ + uint32_t : 30; + } bit; + } SPI_MEM_XTS_LINESIZE; + + union { + __IOM uint32_t reg; /*!< Manual Encryption destination register */ + + struct { + __IOM uint32_t SPI_XTS_DESTINATION : 1; /*!< This bit stores the destination parameter which will be used + in manual encryption calculation. 0: flash(default), 1: + psram(reserved). Only default value can be used. */ + uint32_t : 31; + } bit; + } SPI_MEM_XTS_DESTINATION; + + union { + __IOM uint32_t reg; /*!< Manual Encryption physical address register */ + + struct { + __IOM uint32_t SPI_XTS_PHYSICAL_ADDRESS : 26;/*!< This bits stores the physical-address parameter which will be + used in manual encryption calculation. This value should + aligned with byte number decided by line-size parameter. */ + uint32_t : 6; + } bit; + } SPI_MEM_XTS_PHYSICAL_ADDRESS; + + union { + __IOM uint32_t reg; /*!< Manual Encryption physical address register */ + + struct { + __OM uint32_t SPI_XTS_TRIGGER : 1; /*!< Set this bit to trigger the process of manual encryption calculation. + This action should only be asserted when manual encryption + status is 0. After this action, manual encryption status + becomes 1. After calculation is done, manual encryption + status becomes 2. */ + uint32_t : 31; + } bit; + } SPI_MEM_XTS_TRIGGER; + + union { + __IOM uint32_t reg; /*!< Manual Encryption physical address register */ + + struct { + __OM uint32_t SPI_XTS_RELEASE : 1; /*!< Set this bit to release encrypted result to mspi. This action + should only be asserted when manual encryption status is + 2. After this action, manual encryption status will become + 3. */ + uint32_t : 31; + } bit; + } SPI_MEM_XTS_RELEASE; + + union { + __IOM uint32_t reg; /*!< Manual Encryption physical address register */ + + struct { + __OM uint32_t SPI_XTS_DESTROY : 1; /*!< Set this bit to destroy encrypted result. This action should + be asserted only when manual encryption status is 3. After + this action, manual encryption status will become 0. */ + uint32_t : 31; + } bit; + } SPI_MEM_XTS_DESTROY; + + union { + __IOM uint32_t reg; /*!< Manual Encryption physical address register */ + + struct { + __IM uint32_t SPI_XTS_STATE : 2; /*!< This bits stores the status of manual encryption. 0: idle, 1: + busy of encryption calculation, 2: encryption calculation + is done but the encrypted result is invisible to mspi, + 3: the encrypted result is visible to mspi. */ + uint32_t : 30; + } bit; + } SPI_MEM_XTS_STATE; + + union { + __IOM uint32_t reg; /*!< Manual Encryption version register */ + + struct { + __IOM uint32_t SPI_XTS_DATE : 30; /*!< This bits stores the last modified-time of manual encryption + feature. */ + uint32_t : 2; + } bit; + } SPI_MEM_XTS_DATE; + __IM uint32_t RESERVED16[7]; + + union { + __IOM uint32_t reg; /*!< MSPI-MMU item content register */ + + struct { + __IOM uint32_t SPI_MMU_ITEM_CONTENT : 32; /*!< MSPI-MMU item content */ + } bit; + } SPI_MEM_MMU_ITEM_CONTENT; + + union { + __IOM uint32_t reg; /*!< MSPI-MMU item index register */ + + struct { + __IOM uint32_t SPI_MMU_ITEM_INDEX : 32; /*!< MSPI-MMU item index */ + } bit; + } SPI_MEM_MMU_ITEM_INDEX; + + union { + __IOM uint32_t reg; /*!< MSPI MMU power control register */ + + struct { + __IOM uint32_t SPI_MMU_MEM_FORCE_ON : 1; /*!< Set this bit to enable mmu-memory clock force on */ + __IOM uint32_t SPI_MMU_MEM_FORCE_PD : 1; /*!< Set this bit to force mmu-memory powerdown */ + __IOM uint32_t SPI_MMU_MEM_FORCE_PU : 1; /*!< Set this bit to force mmu-memory powerup, in this case, the + power should also be controlled by rtc. */ + uint32_t : 13; + __IOM uint32_t SPI_MEM_AUX_CTRL : 14; /*!< MMU PSRAM aux control register */ + __IOM uint32_t SPI_MEM_RDN_ENA : 1; /*!< ECO register enable bit */ + __IM uint32_t SPI_MEM_RDN_RESULT : 1; /*!< MSPI module clock domain and AXI clock domain ECO register result + register */ + } bit; + } SPI_MEM_MMU_POWER_CTRL; + + union { + __IOM uint32_t reg; /*!< SPI memory cryption DPA register */ + + struct { + __IOM uint32_t SPI_CRYPT_SECURITY_LEVEL : 3;/*!< Set the security level of spi mem cryption. 0: Shut off cryption + DPA funtion. 1-7: The bigger the number is, the more secure + the cryption is. (Note that the performance of cryption + will decrease together with this number increasing) */ + __IOM uint32_t SPI_CRYPT_CALC_D_DPA_EN : 1;/*!< Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable + DPA in the calculation that using key 1 or key 2. 0: Enable + DPA only in the calculation that using key 1. */ + __IOM uint32_t SPI_CRYPT_DPA_SELECT_REGISTER : 1;/*!< 1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN + and SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits. */ + uint32_t : 27; + } bit; + } SPI_MEM_DPA_CTRL; + __IM uint32_t RESERVED17[25]; + + union { + __IOM uint32_t reg; /*!< MSPI ECO high register */ + + struct { + __IOM uint32_t SPI_MEM_REGISTERRND_ECO_HIGH : 32;/*!< ECO high register */ + } bit; + } SPI_MEM_REGISTERRND_ECO_HIGH; + + union { + __IOM uint32_t reg; /*!< MSPI ECO low register */ + + struct { + __IOM uint32_t SPI_MEM_REGISTERRND_ECO_LOW : 32;/*!< ECO low register */ + } bit; + } SPI_MEM_REGISTERRND_ECO_LOW; + __IM uint32_t RESERVED18; + + union { + __IOM uint32_t reg; /*!< SPI0 version control register */ + + struct { + __IOM uint32_t SPI_MEM_DATE : 28; /*!< SPI0 register version. */ + uint32_t : 4; + } bit; + } SPI_MEM_DATE; +} SPI0_Type; /*!< Size = 1024 (0x400) */ + + + +/* =========================================================================================================================== */ +/* ================ SPI1 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief SPI (Serial Peripheral Interface) Controller 1 (SPI1) + */ + +typedef struct { /*!< SPI1 Structure */ + + union { + __IOM uint32_t reg; /*!< SPI1 memory command register */ + + struct { + __IM uint32_t SPI_MEM_MST_ST : 4; /*!< The current status of SPI1 master FSM. */ + __IM uint32_t SPI_MEM_SLV_ST : 4; /*!< The current status of SPI1 slave FSM: mspi_st. 0: idle state, + 1: preparation state, 2: send command state, 3: send address + state, 4: wait state, 5: read data state, 6:write data + state, 7: done state, 8: read data end state. */ + uint32_t : 9; + __IOM uint32_t SPI_MEM_FLASH_PE : 1; /*!< In user mode, it is set to indicate that program/erase operation + will be triggered. The bit is combined with spi_mem_usr + bit. The bit will be cleared once the operation done.1: + enable 0: disable. */ + __IOM uint32_t SPI_MEM_USR : 1; /*!< User define command enable. An operation will be triggered when + the bit is set. The bit will be cleared once the operation + done.1: enable 0: disable. */ + __IOM uint32_t SPI_MEM_FLASH_HPM : 1; /*!< Drive Flash into high performance mode. The bit will be cleared + once the operation done.1: enable 0: disable. */ + __IOM uint32_t SPI_MEM_FLASH_RES : 1; /*!< This bit combined with reg_resandres bit releases Flash from + the power-down state or high performance mode and obtains + the devices ID. The bit will be cleared once the operation + done.1: enable 0: disable. */ + __IOM uint32_t SPI_MEM_FLASH_DP : 1; /*!< Drive Flash into power down. An operation will be triggered + when the bit is set. The bit will be cleared once the operation + done.1: enable 0: disable. */ + __IOM uint32_t SPI_MEM_FLASH_CE : 1; /*!< Chip erase enable. Chip erase operation will be triggered when + the bit is set. The bit will be cleared once the operation + done.1: enable 0: disable. */ + __IOM uint32_t SPI_MEM_FLASH_BE : 1; /*!< Block erase enable(32KB) . Block erase operation will be triggered + when the bit is set. The bit will be cleared once the operation + done.1: enable 0: disable. */ + __IOM uint32_t SPI_MEM_FLASH_SE : 1; /*!< Sector erase enable(4KB). Sector erase operation will be triggered + when the bit is set. The bit will be cleared once the operation + done.1: enable 0: disable. */ + __IOM uint32_t SPI_MEM_FLASH_PP : 1; /*!< Page program enable(1 byte ~256 bytes data to be programmed). + Page program operation will be triggered when the bit is + set. The bit will be cleared once the operation done .1: + enable 0: disable. */ + __IOM uint32_t SPI_MEM_FLASH_WRSR : 1; /*!< Write status register enable. Write status operation will be + triggered when the bit is set. The bit will be cleared + once the operation done.1: enable 0: disable. */ + __IOM uint32_t SPI_MEM_FLASH_RDSR : 1; /*!< Read status register-1. Read status operation will be triggered + when the bit is set. The bit will be cleared once the operation + done.1: enable 0: disable. */ + __IOM uint32_t SPI_MEM_FLASH_RDID : 1; /*!< Read JEDEC ID . Read ID command will be sent when the bit is + set. The bit will be cleared once the operation done. 1: + enable 0: disable. */ + __IOM uint32_t SPI_MEM_FLASH_WRDI : 1; /*!< Write flash disable. Write disable command will be sent when + the bit is set. The bit will be cleared once the operation + done. 1: enable 0: disable. */ + __IOM uint32_t SPI_MEM_FLASH_WREN : 1; /*!< Write flash enable. Write enable command will be sent when the + bit is set. The bit will be cleared once the operation + done. 1: enable 0: disable. */ + __IOM uint32_t SPI_MEM_FLASH_READ : 1; /*!< Read flash enable. Read flash operation will be triggered when + the bit is set. The bit will be cleared once the operation + done. 1: enable 0: disable. */ + } bit; + } SPI_MEM_CMD; + + union { + __IOM uint32_t reg; /*!< SPI1 address register */ + + struct { + __IOM uint32_t SPI_MEM_USR_ADDR_VALUE : 32;/*!< In user mode, it is the memory address. other then the bit0-bit23 + is the memory address, the bit24-bit31 are the byte length + of a transfer. */ + } bit; + } SPI_MEM_ADDR; + + union { + __IOM uint32_t reg; /*!< SPI1 control register. */ + + struct { + uint32_t : 2; + __IOM uint32_t SPI_MEM_FDUMMY_RIN : 1; /*!< In the dummy phase of a MSPI read data transfer when accesses + to flash, the signal level of SPI bus is output by the + MSPI controller. */ + __IOM uint32_t SPI_MEM_FDUMMY_WOUT : 1; /*!< In the dummy phase of a MSPI write data transfer when accesses + to flash, the signal level of SPI bus is output by the + MSPI controller. */ + __IOM uint32_t SPI_MEM_FDOUT_OCT : 1; /*!< Apply 8 signals during write-data phase 1:enable 0: disable */ + __IOM uint32_t SPI_MEM_FDIN_OCT : 1; /*!< Apply 8 signals during read-data phase 1:enable 0: disable */ + __IOM uint32_t SPI_MEM_FADDR_OCT : 1; /*!< Apply 8 signals during address phase 1:enable 0: disable */ + uint32_t : 1; + __IOM uint32_t SPI_MEM_FCMD_QUAD : 1; /*!< Apply 4 signals during command phase 1:enable 0: disable */ + __IOM uint32_t SPI_MEM_FCMD_OCT : 1; /*!< Apply 8 signals during command phase 1:enable 0: disable */ + __IOM uint32_t SPI_MEM_FCS_CRC_EN : 1; /*!< For SPI1, initialize crc32 module before writing encrypted data + to flash. Active low. */ + __IOM uint32_t SPI_MEM_TX_CRC_EN : 1; /*!< For SPI1, enable crc32 when writing encrypted data to flash. + 1: enable 0:disable */ + uint32_t : 1; + __IOM uint32_t SPI_MEM_FASTRD_MODE : 1; /*!< This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, + spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: + disable. */ + __IOM uint32_t SPI_MEM_FREAD_DUAL : 1; /*!< In the read operations, read-data phase apply 2 signals. 1: + enable 0: disable. */ + __IOM uint32_t SPI_MEM_RESANDRES : 1; /*!< The Device ID is read out to SPI_MEM_RD_STATUS register, this + bit combine with spi_mem_flash_res bit. 1: enable 0: disable. */ + uint32_t : 2; + __IOM uint32_t SPI_MEM_Q_POL : 1; /*!< The bit is used to set MISO line polarity, 1: high 0, low */ + __IOM uint32_t SPI_MEM_D_POL : 1; /*!< The bit is used to set MOSI line polarity, 1: high 0, low */ + __IOM uint32_t SPI_MEM_FREAD_QUAD : 1; /*!< In the read operations read-data phase apply 4 signals. 1: enable + 0: disable. */ + __IOM uint32_t SPI_MEM_WP : 1; /*!< Write protect signal output when SPI is idle. 1: output high, + 0: output low. */ + __IOM uint32_t SPI_MEM_WRSR_2B : 1; /*!< two bytes data will be written to status register when it is + set. 1: enable 0: disable. */ + __IOM uint32_t SPI_MEM_FREAD_DIO : 1; /*!< In the read operations address phase and read-data phase apply + 2 signals. 1: enable 0: disable. */ + __IOM uint32_t SPI_MEM_FREAD_QIO : 1; /*!< In the read operations address phase and read-data phase apply + 4 signals. 1: enable 0: disable. */ + uint32_t : 7; + } bit; + } SPI_MEM_CTRL; + + union { + __IOM uint32_t reg; /*!< SPI1 control1 register. */ + + struct { + __IOM uint32_t SPI_MEM_CLK_MODE : 2; /*!< SPI clock mode bits. 0: SPI clock is off when CS inactive 1: + SPI clock is delayed one cycle after CS inactive 2: SPI + clock is delayed two cycles after CS inactive 3: SPI clock + is alwasy on. */ + __IOM uint32_t SPI_MEM_CS_HOLD_DLY_RES : 10;/*!< After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] + * 512) SPI_CLK cycles. */ + uint32_t : 20; + } bit; + } SPI_MEM_CTRL1; + + union { + __IOM uint32_t reg; /*!< SPI1 control2 register. */ + + struct { + uint32_t : 31; + __OM uint32_t SPI_MEM_SYNC_RESET : 1; /*!< The FSM will be reset. */ + } bit; + } SPI_MEM_CTRL2; + + union { + __IOM uint32_t reg; /*!< SPI1 clock division control register. */ + + struct { + __IOM uint32_t SPI_MEM_CLKCNT_L : 8; /*!< In the master mode it must be equal to spi_mem_clkcnt_N. */ + __IOM uint32_t SPI_MEM_CLKCNT_H : 8; /*!< In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). */ + __IOM uint32_t SPI_MEM_CLKCNT_N : 8; /*!< In the master mode it is the divider of spi_mem_clk. So spi_mem_clk + frequency is system/(spi_mem_clkcnt_N+1) */ + uint32_t : 7; + __IOM uint32_t SPI_MEM_CLK_EQU_SYSCLK : 1;/*!< reserved */ + } bit; + } SPI_MEM_CLOCK; + + union { + __IOM uint32_t reg; /*!< SPI1 user register. */ + + struct { + uint32_t : 9; + __IOM uint32_t SPI_MEM_CK_OUT_EDGE : 1; /*!< the bit combined with spi_mem_mosi_delay_mode bits to set mosi + signal delay mode. */ + uint32_t : 2; + __IOM uint32_t SPI_MEM_FWRITE_DUAL : 1; /*!< In the write operations read-data phase apply 2 signals */ + __IOM uint32_t SPI_MEM_FWRITE_QUAD : 1; /*!< In the write operations read-data phase apply 4 signals */ + __IOM uint32_t SPI_MEM_FWRITE_DIO : 1; /*!< In the write operations address phase and read-data phase apply + 2 signals. */ + __IOM uint32_t SPI_MEM_FWRITE_QIO : 1; /*!< In the write operations address phase and read-data phase apply + 4 signals. */ + uint32_t : 8; + __IOM uint32_t SPI_MEM_USR_MISO_HIGHPART : 1;/*!< read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. + 1: enable 0: disable. */ + __IOM uint32_t SPI_MEM_USR_MOSI_HIGHPART : 1;/*!< write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15 + 1: enable 0: disable. */ + __IOM uint32_t SPI_MEM_USR_DUMMY_IDLE : 1;/*!< SPI clock is disable in dummy phase when the bit is enable. */ + __IOM uint32_t SPI_MEM_USR_MOSI : 1; /*!< This bit enable the write-data phase of an operation. */ + __IOM uint32_t SPI_MEM_USR_MISO : 1; /*!< This bit enable the read-data phase of an operation. */ + __IOM uint32_t SPI_MEM_USR_DUMMY : 1; /*!< This bit enable the dummy phase of an operation. */ + __IOM uint32_t SPI_MEM_USR_ADDR : 1; /*!< This bit enable the address phase of an operation. */ + __IOM uint32_t SPI_MEM_USR_COMMAND : 1; /*!< This bit enable the command phase of an operation. */ + } bit; + } SPI_MEM_USER; + + union { + __IOM uint32_t reg; /*!< SPI1 user1 register. */ + + struct { + __IOM uint32_t SPI_MEM_USR_DUMMY_CYCLELEN : 6;/*!< The length in spi_mem_clk cycles of dummy phase. The register + value shall be (cycle_num-1). */ + uint32_t : 20; + __IOM uint32_t SPI_MEM_USR_ADDR_BITLEN : 6;/*!< The length in bits of address phase. The register value shall + be (bit_num-1). */ + } bit; + } SPI_MEM_USER1; + + union { + __IOM uint32_t reg; /*!< SPI1 user2 register. */ + + struct { + __IOM uint32_t SPI_MEM_USR_COMMAND_VALUE : 16;/*!< The value of command. */ + uint32_t : 12; + __IOM uint32_t SPI_MEM_USR_COMMAND_BITLEN : 4;/*!< The length in bits of command phase. The register value shall + be (bit_num-1) */ + } bit; + } SPI_MEM_USER2; + + union { + __IOM uint32_t reg; /*!< SPI1 send data bit length control register. */ + + struct { + __IOM uint32_t SPI_MEM_USR_MOSI_DBITLEN : 10;/*!< The length in bits of write-data. The register value shall be + (bit_num-1). */ + uint32_t : 22; + } bit; + } SPI_MEM_MOSI_DLEN; + + union { + __IOM uint32_t reg; /*!< SPI1 receive data bit length control register. */ + + struct { + __IOM uint32_t SPI_MEM_USR_MISO_DBITLEN : 10;/*!< The length in bits of read-data. The register value shall be + (bit_num-1). */ + uint32_t : 22; + } bit; + } SPI_MEM_MISO_DLEN; + + union { + __IOM uint32_t reg; /*!< SPI1 status register. */ + + struct { + __IOM uint32_t SPI_MEM_STATUS : 16; /*!< The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res + bit. */ + __IOM uint32_t SPI_MEM_WB_MODE : 8; /*!< Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode + bit. */ + uint32_t : 8; + } bit; + } SPI_MEM_RD_STATUS; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t reg; /*!< SPI1 misc register */ + + struct { + __IOM uint32_t SPI_MEM_CS0_DIS : 1; /*!< SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active + to select SPI device, such as flash, external RAM and so + on. */ + __IOM uint32_t SPI_MEM_CS1_DIS : 1; /*!< SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active + to select SPI device, such as flash, external RAM and so + on. */ + uint32_t : 7; + __IOM uint32_t SPI_MEM_CK_IDLE_EDGE : 1; /*!< 1: spi clk line is high when idle 0: spi clk line is low when + idle */ + __IOM uint32_t SPI_MEM_CS_KEEP_ACTIVE : 1;/*!< spi cs line keep low when the bit is set. */ + uint32_t : 21; + } bit; + } SPI_MEM_MISC; + + union { + __IOM uint32_t reg; /*!< SPI1 TX CRC data register. */ + + struct { + __IM uint32_t DATA : 32; /*!< For SPI1, the value of crc32. */ + } bit; + } SPI_MEM_TX_CRC; + + union { + __IOM uint32_t reg; /*!< SPI1 bit mode control register. */ + + struct { + uint32_t : 1; + __IOM uint32_t SPI_MEM_CACHE_USR_ADDR_4BYTE : 1;/*!< For SPI1, cache read flash with 4 bytes address, 1: enable, + 0:disable. */ + uint32_t : 1; + __IOM uint32_t SPI_MEM_FDIN_DUAL : 1; /*!< For SPI1, din phase apply 2 signals. 1: enable 0: disable. The + bit is the same with spi_mem_fread_dio. */ + __IOM uint32_t SPI_MEM_FDOUT_DUAL : 1; /*!< For SPI1, dout phase apply 2 signals. 1: enable 0: disable. + The bit is the same with spi_mem_fread_dio. */ + __IOM uint32_t SPI_MEM_FADDR_DUAL : 1; /*!< For SPI1, address phase apply 2 signals. 1: enable 0: disable. + The bit is the same with spi_mem_fread_dio. */ + __IOM uint32_t SPI_MEM_FDIN_QUAD : 1; /*!< For SPI1, din phase apply 4 signals. 1: enable 0: disable. The + bit is the same with spi_mem_fread_qio. */ + __IOM uint32_t SPI_MEM_FDOUT_QUAD : 1; /*!< For SPI1, dout phase apply 4 signals. 1: enable 0: disable. + The bit is the same with spi_mem_fread_qio. */ + __IOM uint32_t SPI_MEM_FADDR_QUAD : 1; /*!< For SPI1, address phase apply 4 signals. 1: enable 0: disable. + The bit is the same with spi_mem_fread_qio. */ + uint32_t : 23; + } bit; + } SPI_MEM_CACHE_FCTRL; + __IM uint32_t RESERVED1[6]; + + union { + __IOM uint32_t reg; /*!< SPI1 memory data buffer0 */ + + struct { + __IOM uint32_t SPI_MEM_BUF0 : 32; /*!< data buffer */ + } bit; + } SPI_MEM_W0; + + union { + __IOM uint32_t reg; /*!< SPI1 memory data buffer1 */ + + struct { + __IOM uint32_t SPI_MEM_BUF1 : 32; /*!< data buffer */ + } bit; + } SPI_MEM_W1; + + union { + __IOM uint32_t reg; /*!< SPI1 memory data buffer2 */ + + struct { + __IOM uint32_t SPI_MEM_BUF2 : 32; /*!< data buffer */ + } bit; + } SPI_MEM_W2; + + union { + __IOM uint32_t reg; /*!< SPI1 memory data buffer3 */ + + struct { + __IOM uint32_t SPI_MEM_BUF3 : 32; /*!< data buffer */ + } bit; + } SPI_MEM_W3; + + union { + __IOM uint32_t reg; /*!< SPI1 memory data buffer4 */ + + struct { + __IOM uint32_t SPI_MEM_BUF4 : 32; /*!< data buffer */ + } bit; + } SPI_MEM_W4; + + union { + __IOM uint32_t reg; /*!< SPI1 memory data buffer5 */ + + struct { + __IOM uint32_t SPI_MEM_BUF5 : 32; /*!< data buffer */ + } bit; + } SPI_MEM_W5; + + union { + __IOM uint32_t reg; /*!< SPI1 memory data buffer6 */ + + struct { + __IOM uint32_t SPI_MEM_BUF6 : 32; /*!< data buffer */ + } bit; + } SPI_MEM_W6; + + union { + __IOM uint32_t reg; /*!< SPI1 memory data buffer7 */ + + struct { + __IOM uint32_t SPI_MEM_BUF7 : 32; /*!< data buffer */ + } bit; + } SPI_MEM_W7; + + union { + __IOM uint32_t reg; /*!< SPI1 memory data buffer8 */ + + struct { + __IOM uint32_t SPI_MEM_BUF8 : 32; /*!< data buffer */ + } bit; + } SPI_MEM_W8; + + union { + __IOM uint32_t reg; /*!< SPI1 memory data buffer9 */ + + struct { + __IOM uint32_t SPI_MEM_BUF9 : 32; /*!< data buffer */ + } bit; + } SPI_MEM_W9; + + union { + __IOM uint32_t reg; /*!< SPI1 memory data buffer10 */ + + struct { + __IOM uint32_t SPI_MEM_BUF10 : 32; /*!< data buffer */ + } bit; + } SPI_MEM_W10; + + union { + __IOM uint32_t reg; /*!< SPI1 memory data buffer11 */ + + struct { + __IOM uint32_t SPI_MEM_BUF11 : 32; /*!< data buffer */ + } bit; + } SPI_MEM_W11; + + union { + __IOM uint32_t reg; /*!< SPI1 memory data buffer12 */ + + struct { + __IOM uint32_t SPI_MEM_BUF12 : 32; /*!< data buffer */ + } bit; + } SPI_MEM_W12; + + union { + __IOM uint32_t reg; /*!< SPI1 memory data buffer13 */ + + struct { + __IOM uint32_t SPI_MEM_BUF13 : 32; /*!< data buffer */ + } bit; + } SPI_MEM_W13; + + union { + __IOM uint32_t reg; /*!< SPI1 memory data buffer14 */ + + struct { + __IOM uint32_t SPI_MEM_BUF14 : 32; /*!< data buffer */ + } bit; + } SPI_MEM_W14; + + union { + __IOM uint32_t reg; /*!< SPI1 memory data buffer15 */ + + struct { + __IOM uint32_t SPI_MEM_BUF15 : 32; /*!< data buffer */ + } bit; + } SPI_MEM_W15; + + union { + __IOM uint32_t reg; /*!< SPI1 wait idle control register */ + + struct { + __IOM uint32_t SPI_MEM_WAITI_EN : 1; /*!< 1: The hardware will wait idle after SE/PP/WRSR automatically, + and hardware auto Suspend/Resume can be enabled. 0: The + functions of hardware wait idle and auto Suspend/Resume + are not supported. */ + __IOM uint32_t SPI_MEM_WAITI_DUMMY : 1; /*!< The dummy phase enable when wait flash idle (RDSR) */ + __IOM uint32_t SPI_MEM_WAITI_ADDR_EN : 1; /*!< 1: Output address 0 in RDSR or read SUS command transfer. 0: + Do not send out address in RDSR or read SUS command transfer. */ + __IOM uint32_t SPI_MEM_WAITI_ADDR_CYCLELEN : 2;/*!< When SPI_MEM_WAITI_ADDR_EN is set, the cycle length of sent + out address is (SPI_MEM_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI + bus clock cycles. It is not active when SPI_MEM_WAITI_ADDR_EN + is cleared. */ + uint32_t : 4; + __IOM uint32_t SPI_MEM_WAITI_CMD_2B : 1; /*!< 1:The wait idle command bit length is 16. 0: The wait idle command + bit length is 8. */ + __IOM uint32_t SPI_MEM_WAITI_DUMMY_CYCLELEN : 6;/*!< The dummy cycle length when wait flash idle(RDSR). */ + __IOM uint32_t SPI_MEM_WAITI_CMD : 16; /*!< The command value to wait flash idle(RDSR). */ + } bit; + } SPI_MEM_FLASH_WAITI_CTRL; + + union { + __IOM uint32_t reg; /*!< SPI1 flash suspend control register */ + + struct { + __IOM uint32_t SPI_MEM_FLASH_PER : 1; /*!< program erase resume bit, program erase suspend operation will + be triggered when the bit is set. The bit will be cleared + once the operation done.1: enable 0: disable. */ + __IOM uint32_t SPI_MEM_FLASH_PES : 1; /*!< program erase suspend bit, program erase suspend operation will + be triggered when the bit is set. The bit will be cleared + once the operation done.1: enable 0: disable. */ + __IOM uint32_t SPI_MEM_FLASH_PER_WAIT_EN : 1;/*!< 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK + cycles after program erase resume command is sent. 0: SPI1 + does not wait after program erase resume command is sent. */ + __IOM uint32_t SPI_MEM_FLASH_PES_WAIT_EN : 1;/*!< 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK + cycles after program erase suspend command is sent. 0: + SPI1 does not wait after program erase suspend command + is sent. */ + __IOM uint32_t SPI_MEM_PES_PER_EN : 1; /*!< Set this bit to enable PES end triggers PER transfer option. + If this bit is 0, application should send PER after PES + is done. */ + __IOM uint32_t SPI_MEM_FLASH_PES_EN : 1; /*!< Set this bit to enable Auto-suspending function. */ + __IOM uint32_t SPI_MEM_PESR_END_MSK : 16; /*!< The mask value when check SUS/SUS1/SUS2 status bit. If the read + status value is status_in[15:0](only status_in[7:0] is + valid when only one byte of data is read out, status_in[15:0] + is valid when two bytes of data are read out), SUS/SUS1/SUS2 + = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0]. */ + __IOM uint32_t SPI_FMEM_RD_SUS_2B : 1; /*!< 1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. + 0: Read one byte when check flash SUS/SUS1/SUS2 status + bit */ + __IOM uint32_t SPI_MEM_PER_END_EN : 1; /*!< 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure + the resume status of flash. 0: Only need to check WIP is + 0. */ + __IOM uint32_t SPI_MEM_PES_END_EN : 1; /*!< 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure + the suspend status of flash. 0: Only need to check WIP + is 0. */ + __IOM uint32_t SPI_MEM_SUS_TIMEOUT_CNT : 7;/*!< When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] + times, it will be treated as check pass. */ + } bit; + } SPI_MEM_FLASH_SUS_CTRL; + + union { + __IOM uint32_t reg; /*!< SPI1 flash suspend command register */ + + struct { + __IOM uint32_t SPI_MEM_FLASH_PES_COMMAND : 16;/*!< Program/Erase suspend command. */ + __IOM uint32_t SPI_MEM_WAIT_PESR_COMMAND : 16;/*!< Flash SUS/SUS1/SUS2 status bit read command. The command should + be sent when SUS/SUS1/SUS2 bit should be checked to insure + the suspend or resume status of flash. */ + } bit; + } SPI_MEM_FLASH_SUS_CMD; + + union { + __IOM uint32_t reg; /*!< SPI1 flash suspend status register */ + + struct { + __IOM uint32_t SPI_MEM_FLASH_SUS : 1; /*!< The status of flash suspend, only used in SPI1. */ + __IOM uint32_t SPI_MEM_WAIT_PESR_CMD_2B : 1;/*!< 1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 + bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to + check SUS/SUS1/SUS2 bit. */ + __IOM uint32_t SPI_MEM_FLASH_HPM_DLY_128 : 1;/*!< 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK + cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RE + [9:0] * 4) SPI_CLK cycles after HPM command is sent. */ + __IOM uint32_t SPI_MEM_FLASH_RES_DLY_128 : 1;/*!< 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK + cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RE + [9:0] * 4) SPI_CLK cycles after RES command is sent. */ + __IOM uint32_t SPI_MEM_FLASH_DP_DLY_128 : 1;/*!< 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK + cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES + 9:0] * 4) SPI_CLK cycles after DP command is sent. */ + __IOM uint32_t SPI_MEM_FLASH_PER_DLY_128 : 1;/*!< Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELA + _RES[9:0] * 128) SPI_CLK cycles after PER command is sent. + 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK + cycles after PER command is sent. */ + __IOM uint32_t SPI_MEM_FLASH_PES_DLY_128 : 1;/*!< Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELA + _RES[9:0] * 128) SPI_CLK cycles after PES command is sent. + 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK + cycles after PES command is sent. */ + __IOM uint32_t SPI_MEM_SPI0_LOCK_EN : 1; /*!< 1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it. */ + uint32_t : 7; + __IOM uint32_t SPI_MEM_FLASH_PESR_CMD_2B : 1;/*!< 1: The bit length of Program/Erase Suspend/Resume command is + 16. 0: The bit length of Program/Erase Suspend/Resume command + is 8. */ + __IOM uint32_t SPI_MEM_FLASH_PER_COMMAND : 16;/*!< Program/Erase resume command. */ + } bit; + } SPI_MEM_SUS_STATUS; + __IM uint32_t RESERVED2[6]; + + union { + __IOM uint32_t reg; /*!< SPI1 interrupt enable register */ + + struct { + __IOM uint32_t SPI_MEM_PER_END_INT_ENA : 1;/*!< The enable bit for SPI_MEM_PER_END_INT interrupt. */ + __IOM uint32_t SPI_MEM_PES_END_INT_ENA : 1;/*!< The enable bit for SPI_MEM_PES_END_INT interrupt. */ + __IOM uint32_t SPI_MEM_WPE_END_INT_ENA : 1;/*!< The enable bit for SPI_MEM_WPE_END_INT interrupt. */ + __IOM uint32_t SPI_MEM_SLV_ST_END_INT_ENA : 1;/*!< The enable bit for SPI_MEM_SLV_ST_END_INT interrupt. */ + __IOM uint32_t SPI_MEM_MST_ST_END_INT_ENA : 1;/*!< The enable bit for SPI_MEM_MST_ST_END_INT interrupt. */ + uint32_t : 5; + __IOM uint32_t SPI_MEM_BROWN_OUT_INT_ENA : 1;/*!< The enable bit for SPI_MEM_BROWN_OUT_INT interrupt. */ + uint32_t : 21; + } bit; + } SPI_MEM_INT_ENA; + + union { + __IOM uint32_t reg; /*!< SPI1 interrupt clear register */ + + struct { + __OM uint32_t SPI_MEM_PER_END_INT_CLR : 1;/*!< The clear bit for SPI_MEM_PER_END_INT interrupt. */ + __OM uint32_t SPI_MEM_PES_END_INT_CLR : 1;/*!< The clear bit for SPI_MEM_PES_END_INT interrupt. */ + __OM uint32_t SPI_MEM_WPE_END_INT_CLR : 1;/*!< The clear bit for SPI_MEM_WPE_END_INT interrupt. */ + __OM uint32_t SPI_MEM_SLV_ST_END_INT_CLR : 1;/*!< The clear bit for SPI_MEM_SLV_ST_END_INT interrupt. */ + __OM uint32_t SPI_MEM_MST_ST_END_INT_CLR : 1;/*!< The clear bit for SPI_MEM_MST_ST_END_INT interrupt. */ + uint32_t : 5; + __OM uint32_t SPI_MEM_BROWN_OUT_INT_CLR : 1;/*!< The status bit for SPI_MEM_BROWN_OUT_INT interrupt. */ + uint32_t : 21; + } bit; + } SPI_MEM_INT_CLR; + + union { + __IOM uint32_t reg; /*!< SPI1 interrupt raw register */ + + struct { + __IOM uint32_t SPI_MEM_PER_END_INT_RAW : 1;/*!< The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered + when Auto Resume command (0x7A) is sent and flash is resumed + successfully. 0: Others. */ + __IOM uint32_t SPI_MEM_PES_END_INT_RAW : 1;/*!< The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when + Auto Suspend command (0x75) is sent and flash is suspended + successfully. 0: Others. */ + __IOM uint32_t SPI_MEM_WPE_END_INT_RAW : 1;/*!< The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered + when WRSR/PP/SE/BE/CE is sent and flash is already idle. + 0: Others. */ + __IOM uint32_t SPI_MEM_SLV_ST_END_INT_RAW : 1;/*!< The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered + when spi1_slv_st is changed from non idle state to idle + state. It means that SPI_CS raises high. 0: Others */ + __IOM uint32_t SPI_MEM_MST_ST_END_INT_RAW : 1;/*!< The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered + when spi1_mst_st is changed from non idle state to idle + state. 0: Others. */ + uint32_t : 5; + __IOM uint32_t SPI_MEM_BROWN_OUT_INT_RAW : 1;/*!< The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered + condition is that chip is loosing power and RTC module + sends out brown out close flash request to SPI1. After + SPI1 sends out suspend command to flash, this interrupt + is triggered and MSPI returns to idle state. 0: Others. */ + uint32_t : 21; + } bit; + } SPI_MEM_INT_RAW; + + union { + __IOM uint32_t reg; /*!< SPI1 interrupt status register */ + + struct { + __IM uint32_t SPI_MEM_PER_END_INT_ST : 1;/*!< The status bit for SPI_MEM_PER_END_INT interrupt. */ + __IM uint32_t SPI_MEM_PES_END_INT_ST : 1;/*!< The status bit for SPI_MEM_PES_END_INT interrupt. */ + __IM uint32_t SPI_MEM_WPE_END_INT_ST : 1;/*!< The status bit for SPI_MEM_WPE_END_INT interrupt. */ + __IM uint32_t SPI_MEM_SLV_ST_END_INT_ST : 1;/*!< The status bit for SPI_MEM_SLV_ST_END_INT interrupt. */ + __IM uint32_t SPI_MEM_MST_ST_END_INT_ST : 1;/*!< The status bit for SPI_MEM_MST_ST_END_INT interrupt. */ + uint32_t : 5; + __IM uint32_t SPI_MEM_BROWN_OUT_INT_ST : 1;/*!< The status bit for SPI_MEM_BROWN_OUT_INT interrupt. */ + uint32_t : 21; + } bit; + } SPI_MEM_INT_ST; + __IM uint32_t RESERVED3; + + union { + __IOM uint32_t reg; /*!< SPI1 DDR control register */ + + struct { + __IOM uint32_t SPI_FMEM_DDR_EN : 1; /*!< 1: in ddr mode, 0 in sdr mode */ + __IOM uint32_t SPI_FMEM_VAR_DUMMY : 1; /*!< Set the bit to enable variable dummy cycle in spi ddr mode. */ + __IOM uint32_t SPI_FMEM_DDR_RDAT_SWP : 1; /*!< Set the bit to reorder rx data of the word in spi ddr mode. */ + __IOM uint32_t SPI_FMEM_DDR_WDAT_SWP : 1; /*!< Set the bit to reorder tx data of the word in spi ddr mode. */ + __IOM uint32_t SPI_FMEM_DDR_CMD_DIS : 1; /*!< the bit is used to disable dual edge in command phase when ddr + mode. */ + __IOM uint32_t SPI_FMEM_OUTMINBYTELEN : 7;/*!< It is the minimum output data length in the panda device. */ + uint32_t : 2; + __IOM uint32_t SPI_FMEM_USR_DDR_DQS_THD : 7;/*!< The delay number of data strobe which from memory based on SPI + clock. */ + __IOM uint32_t SPI_FMEM_DDR_DQS_LOOP : 1; /*!< 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive + data when spi0_slv_st is in SPI_MEM_DIN state. It is used + when there is no SPI_DQS signal or SPI_DQS signal is not + stable. 0: SPI0 starts to store data at the positive and + negative edge of SPI_DQS. */ + uint32_t : 2; + __IOM uint32_t SPI_FMEM_CLK_DIFF_EN : 1; /*!< Set this bit to enable the differential SPI_CLK#. */ + uint32_t : 1; + __IOM uint32_t SPI_FMEM_DQS_CA_IN : 1; /*!< Set this bit to enable the input of SPI_DQS signal in SPI phases + of CMD and ADDR. */ + __IOM uint32_t SPI_FMEM_HYPERBUS_DUMMY_2X : 1;/*!< Set this bit to enable the vary dummy function in SPI HyperBus + mode, when SPI0 accesses flash or SPI1 accesses flash or + sram. */ + __IOM uint32_t SPI_FMEM_CLK_DIFF_INV : 1; /*!< Set this bit to invert SPI_DIFF when accesses to flash. . */ + __IOM uint32_t SPI_FMEM_OCTA_RAM_ADDR : 1;/*!< Set this bit to enable octa_ram address out when accesses to + flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], + 6'd0, spi_usr_addr_value[3:1], 1'b0}. */ + __IOM uint32_t SPI_FMEM_HYPERBUS_CA : 1; /*!< Set this bit to enable HyperRAM address out when accesses to + flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], + 13'd0, spi_usr_addr_value[3:1]}. */ + uint32_t : 1; + } bit; + } SPI_MEM_DDR; + __IM uint32_t RESERVED4[42]; + + union { + __IOM uint32_t reg; /*!< SPI1 timing control register */ + + struct { + uint32_t : 1; + __IOM uint32_t SPI_MEM_TIMING_CALI : 1; /*!< The bit is used to enable timing auto-calibration for all reading + operations. */ + __IOM uint32_t SPI_MEM_EXTRA_DUMMY_CYCLELEN : 3;/*!< add extra dummy spi clock cycle length for spi clock calibration. */ + uint32_t : 27; + } bit; + } SPI_MEM_TIMING_CALI; + __IM uint32_t RESERVED5[31]; + + union { + __IOM uint32_t reg; /*!< SPI1 clk_gate register */ + + struct { + __IOM uint32_t SPI_MEM_CLK_EN : 1; /*!< Register clock gate enable signal. 1: Enable. 0: Disable. */ + uint32_t : 31; + } bit; + } SPI_MEM_CLOCK_GATE; + __IM uint32_t RESERVED6[126]; + + union { + __IOM uint32_t reg; /*!< Version control register */ + + struct { + __IOM uint32_t SPI_MEM_DATE : 28; /*!< Version control register */ + uint32_t : 4; + } bit; + } SPI_MEM_DATE; +} SPI1_Type; /*!< Size = 1024 (0x400) */ + + + +/* =========================================================================================================================== */ +/* ================ SPI2 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief SPI (Serial Peripheral Interface) Controller 2 (SPI2) + */ + +typedef struct { /*!< SPI2 Structure */ + + union { + __IOM uint32_t reg; /*!< Command control register */ + + struct { + __IOM uint32_t SPI_CONF_BITLEN : 18; /*!< Define the APB cycles of SPI_CONF state. Can be configured in + CONF state. */ + uint32_t : 5; + __OM uint32_t SPI_UPDATE : 1; /*!< Set this bit to synchronize SPI registers from APB clock domain + into SPI module clock domain, which is only used in SPI + master mode. */ + __IOM uint32_t SPI_USR : 1; /*!< User define command enable. An operation will be triggered when + the bit is set. The bit will be cleared once the operation + done.1: enable 0: disable. Can not be changed by CONF_buf. */ + uint32_t : 7; + } bit; + } SPI_CMD; + + union { + __IOM uint32_t reg; /*!< Address value register */ + + struct { + __IOM uint32_t SPI_USR_ADDR_VALUE : 32; /*!< Address to slave. Can be configured in CONF state. */ + } bit; + } SPI_ADDR; + + union { + __IOM uint32_t reg; /*!< SPI control register */ + + struct { + uint32_t : 3; + __IOM uint32_t SPI_DUMMY_OUT : 1; /*!< 0: In the dummy phase, the FSPI bus signals are not output. + 1: In the dummy phase, the FSPI bus signals are output. + Can be configured in CONF state. */ + uint32_t : 1; + __IOM uint32_t SPI_FADDR_DUAL : 1; /*!< Apply 2 signals during addr phase 1:enable 0: disable. Can be + configured in CONF state. */ + __IOM uint32_t SPI_FADDR_QUAD : 1; /*!< Apply 4 signals during addr phase 1:enable 0: disable. Can be + configured in CONF state. */ + __IOM uint32_t SPI_FADDR_OCT : 1; /*!< Apply 8 signals during addr phase 1:enable 0: disable. Can be + configured in CONF state. */ + __IOM uint32_t SPI_FCMD_DUAL : 1; /*!< Apply 2 signals during command phase 1:enable 0: disable. Can + be configured in CONF state. */ + __IOM uint32_t SPI_FCMD_QUAD : 1; /*!< Apply 4 signals during command phase 1:enable 0: disable. Can + be configured in CONF state. */ + __IOM uint32_t SPI_FCMD_OCT : 1; /*!< Apply 8 signals during command phase 1:enable 0: disable. Can + be configured in CONF state. */ + uint32_t : 3; + __IOM uint32_t SPI_FREAD_DUAL : 1; /*!< In the read operations, read-data phase apply 2 signals. 1: + enable 0: disable. Can be configured in CONF state. */ + __IOM uint32_t SPI_FREAD_QUAD : 1; /*!< In the read operations read-data phase apply 4 signals. 1: enable + 0: disable. Can be configured in CONF state. */ + __IOM uint32_t SPI_FREAD_OCT : 1; /*!< In the read operations read-data phase apply 8 signals. 1: enable + 0: disable. Can be configured in CONF state. */ + uint32_t : 1; + __IOM uint32_t SPI_Q_POL : 1; /*!< The bit is used to set MISO line polarity, 1: high 0, low. Can + be configured in CONF state. */ + __IOM uint32_t SPI_D_POL : 1; /*!< The bit is used to set MOSI line polarity, 1: high 0, low. Can + be configured in CONF state. */ + __IOM uint32_t SPI_HOLD_POL : 1; /*!< SPI_HOLD output value when SPI is idle. 1: output high, 0: output + low. Can be configured in CONF state. */ + __IOM uint32_t SPI_WP_POL : 1; /*!< Write protect signal output when SPI is idle. 1: output high, + 0: output low. Can be configured in CONF state. */ + uint32_t : 1; + __IOM uint32_t SPI_RD_BIT_ORDER : 2; /*!< In read-data (MISO) phase 1: LSB first 0: MSB first. Can be + configured in CONF state. */ + __IOM uint32_t SPI_WR_BIT_ORDER : 2; /*!< In command address write-data (MOSI) phases 1: LSB firs 0: MSB + first. Can be configured in CONF state. */ + uint32_t : 5; + } bit; + } SPI_CTRL; + + union { + __IOM uint32_t reg; /*!< SPI clock control register */ + + struct { + __IOM uint32_t SPI_CLKCNT_L : 6; /*!< In the master mode it must be equal to spi_clkcnt_N. In the + slave mode it must be 0. Can be configured in CONF state. */ + __IOM uint32_t SPI_CLKCNT_H : 6; /*!< In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In + the slave mode it must be 0. Can be configured in CONF + state. */ + __IOM uint32_t SPI_CLKCNT_N : 6; /*!< In the master mode it is the divider of spi_clk. So spi_clk + frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). + Can be configured in CONF state. */ + __IOM uint32_t SPI_CLKDIV_PRE : 4; /*!< In the master mode it is pre-divider of spi_clk. Can be configured + in CONF state. */ + uint32_t : 9; + __IOM uint32_t SPI_CLK_EQU_SYSCLK : 1; /*!< In the master mode 1: spi_clk is eqaul to system 0: spi_clk + is divided from system clock. Can be configured in CONF + state. */ + } bit; + } SPI_CLOCK; + + union { + __IOM uint32_t reg; /*!< SPI USER control register */ + + struct { + __IOM uint32_t SPI_DOUTDIN : 1; /*!< Set the bit to enable full duplex communication. 1: enable 0: + disable. Can be configured in CONF state. */ + uint32_t : 2; + __IOM uint32_t SPI_QPI_MODE : 1; /*!< Both for master mode and slave mode. 1: spi controller is in + QPI mode. 0: others. Can be configured in CONF state. */ + __IOM uint32_t SPI_OPI_MODE : 1; /*!< Just for master mode. 1: spi controller is in OPI mode (all + in 8-b-m). 0: others. Can be configured in CONF state. */ + __IOM uint32_t SPI_TSCK_I_EDGE : 1; /*!< In the slave mode, this bit can be used to change the polarity + of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i. */ + __IOM uint32_t SPI_CS_HOLD : 1; /*!< spi cs keep low when spi is in done phase. 1: enable 0: disable. + Can be configured in CONF state. */ + __IOM uint32_t SPI_CS_SETUP : 1; /*!< spi cs is enable when spi is in prepare phase. 1: enable 0: + disable. Can be configured in CONF state. */ + __IOM uint32_t SPI_RSCK_I_EDGE : 1; /*!< In the slave mode, this bit can be used to change the polarity + of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i. */ + __IOM uint32_t SPI_CK_OUT_EDGE : 1; /*!< the bit combined with spi_mosi_delay_mode bits to set mosi signal + delay mode. Can be configured in CONF state. */ + uint32_t : 2; + __IOM uint32_t SPI_FWRITE_DUAL : 1; /*!< In the write operations read-data phase apply 2 signals. Can + be configured in CONF state. */ + __IOM uint32_t SPI_FWRITE_QUAD : 1; /*!< In the write operations read-data phase apply 4 signals. Can + be configured in CONF state. */ + __IOM uint32_t SPI_FWRITE_OCT : 1; /*!< In the write operations read-data phase apply 8 signals. Can + be configured in CONF state. */ + __IOM uint32_t SPI_USR_CONF_NXT : 1; /*!< 1: Enable the DMA CONF phase of next seg-trans operation, which + means seg-trans will continue. 0: The seg-trans will end + after the current SPI seg-trans or this is not seg-trans + mode. Can be configured in CONF state. */ + uint32_t : 1; + __IOM uint32_t SPI_SIO : 1; /*!< Set the bit to enable 3-line half duplex communication mosi + and miso signals share the same pin. 1: enable 0: disable. + Can be configured in CONF state. */ + uint32_t : 6; + __IOM uint32_t SPI_USR_MISO_HIGHPART : 1; /*!< read-data phase only access to high-part of the buffer spi_w8~spi_w15. + 1: enable 0: disable. Can be configured in CONF state. */ + __IOM uint32_t SPI_USR_MOSI_HIGHPART : 1; /*!< write-data phase only access to high-part of the buffer spi_w8~spi_w15. + 1: enable 0: disable. Can be configured in CONF state. */ + __IOM uint32_t SPI_USR_DUMMY_IDLE : 1; /*!< spi clock is disable in dummy phase when the bit is enable. + Can be configured in CONF state. */ + __IOM uint32_t SPI_USR_MOSI : 1; /*!< This bit enable the write-data phase of an operation. Can be + configured in CONF state. */ + __IOM uint32_t SPI_USR_MISO : 1; /*!< This bit enable the read-data phase of an operation. Can be + configured in CONF state. */ + __IOM uint32_t SPI_USR_DUMMY : 1; /*!< This bit enable the dummy phase of an operation. Can be configured + in CONF state. */ + __IOM uint32_t SPI_USR_ADDR : 1; /*!< This bit enable the address phase of an operation. Can be configured + in CONF state. */ + __IOM uint32_t SPI_USR_COMMAND : 1; /*!< This bit enable the command phase of an operation. Can be configured + in CONF state. */ + } bit; + } SPI_USER; + + union { + __IOM uint32_t reg; /*!< SPI USER control register 1 */ + + struct { + __IOM uint32_t SPI_USR_DUMMY_CYCLELEN : 8;/*!< The length in spi_clk cycles of dummy phase. The register value + shall be (cycle_num-1). Can be configured in CONF state. */ + uint32_t : 8; + __IOM uint32_t SPI_MST_WFULL_ERR_END_EN : 1;/*!< 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid + in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended + when SPI RX AFIFO wfull error is valid in GP-SPI master + FD/HD-mode. */ + __IOM uint32_t SPI_CS_SETUP_TIME : 5; /*!< (cycles+1) of prepare phase by spi clock this bits are combined + with spi_cs_setup bit. Can be configured in CONF state. */ + __IOM uint32_t SPI_CS_HOLD_TIME : 5; /*!< delay cycles of cs pin by spi clock this bits are combined with + spi_cs_hold bit. Can be configured in CONF state. */ + __IOM uint32_t SPI_USR_ADDR_BITLEN : 5; /*!< The length in bits of address phase. The register value shall + be (bit_num-1). Can be configured in CONF state. */ + } bit; + } SPI_USER1; + + union { + __IOM uint32_t reg; /*!< SPI USER control register 2 */ + + struct { + __IOM uint32_t SPI_USR_COMMAND_VALUE : 16;/*!< The value of command. Can be configured in CONF state. */ + uint32_t : 11; + __IOM uint32_t SPI_MST_REMPTY_ERR_END_EN : 1;/*!< 1: SPI transfer is ended when SPI TX AFIFO read empty error + is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is + not ended when SPI TX AFIFO read empty error is valid in + GP-SPI master FD/HD-mode. */ + __IOM uint32_t SPI_USR_COMMAND_BITLEN : 4;/*!< The length in bits of command phase. The register value shall + be (bit_num-1). Can be configured in CONF state. */ + } bit; + } SPI_USER2; + + union { + __IOM uint32_t reg; /*!< SPI data bit length control register */ + + struct { + __IOM uint32_t SPI_MS_DATA_BITLEN : 18; /*!< The value of these bits is the configured SPI transmission data + bit length in master mode DMA controlled transfer or CPU + controlled transfer. The value is also the configured bit + length in slave mode DMA RX controlled transfer. The register + value shall be (bit_num-1). Can be configured in CONF state. */ + uint32_t : 14; + } bit; + } SPI_MS_DLEN; + + union { + __IOM uint32_t reg; /*!< SPI misc register */ + + struct { + __IOM uint32_t SPI_CS0_DIS : 1; /*!< SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to + CS0 pin. Can be configured in CONF state. */ + __IOM uint32_t SPI_CS1_DIS : 1; /*!< SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to + CS1 pin. Can be configured in CONF state. */ + __IOM uint32_t SPI_CS2_DIS : 1; /*!< SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to + CS2 pin. Can be configured in CONF state. */ + __IOM uint32_t SPI_CS3_DIS : 1; /*!< SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to + CS3 pin. Can be configured in CONF state. */ + __IOM uint32_t SPI_CS4_DIS : 1; /*!< SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to + CS4 pin. Can be configured in CONF state. */ + __IOM uint32_t SPI_CS5_DIS : 1; /*!< SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to + CS5 pin. Can be configured in CONF state. */ + __IOM uint32_t SPI_CK_DIS : 1; /*!< 1: spi clk out disable, 0: spi clk out enable. Can be configured + in CONF state. */ + __IOM uint32_t SPI_MASTER_CS_POL : 6; /*!< In the master mode the bits are the polarity of spi cs line, + the value is equivalent to spi_cs ^ spi_master_cs_pol. + Can be configured in CONF state. */ + uint32_t : 3; + __IOM uint32_t SPI_CLK_DATA_DTR_EN : 1; /*!< 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. + 0: SPI master DTR mode is only applied to spi_dqs. This + bit should be used with bit 17/18/19. */ + __IOM uint32_t SPI_DATA_DTR_EN : 1; /*!< 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR + mode, including master 1/2/4/8-bm. 0: SPI clk and data + of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured + in CONF state. */ + __IOM uint32_t SPI_ADDR_DTR_EN : 1; /*!< 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, + including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR + state are in STR mode. Can be configured in CONF state. */ + __IOM uint32_t SPI_CMD_DTR_EN : 1; /*!< 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including + master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD + state are in STR mode. Can be configured in CONF state. */ + uint32_t : 3; + __IOM uint32_t SPI_SLAVE_CS_POL : 1; /*!< spi slave input cs polarity select. 1: inv 0: not change. Can + be configured in CONF state. */ + __IOM uint32_t SPI_DQS_IDLE_EDGE : 1; /*!< The default value of spi_dqs. Can be configured in CONF state. */ + uint32_t : 4; + __IOM uint32_t SPI_CK_IDLE_EDGE : 1; /*!< 1: spi clk line is high when idle 0: spi clk line is low when + idle. Can be configured in CONF state. */ + __IOM uint32_t SPI_CS_KEEP_ACTIVE : 1; /*!< spi cs line keep low when the bit is set. Can be configured + in CONF state. */ + __IOM uint32_t SPI_QUAD_DIN_PIN_SWAP : 1; /*!< 1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP + with FSPIHD. 0: spi quad input swap disable. Can be configured + in CONF state. */ + } bit; + } SPI_MISC; + + union { + __IOM uint32_t reg; /*!< SPI input delay mode configuration */ + + struct { + __IOM uint32_t SPI_DIN0_MODE : 2; /*!< the input signals are delayed by SPI module clock cycles, 0: + input without delayed, 1: input with the posedge of clk_apb,2 + input with the negedge of clk_apb, 3: input with the spi_clk. + Can be configured in CONF state. */ + __IOM uint32_t SPI_DIN1_MODE : 2; /*!< the input signals are delayed by SPI module clock cycles, 0: + input without delayed, 1: input with the posedge of clk_apb,2 + input with the negedge of clk_apb, 3: input with the spi_clk. + Can be configured in CONF state. */ + __IOM uint32_t SPI_DIN2_MODE : 2; /*!< the input signals are delayed by SPI module clock cycles, 0: + input without delayed, 1: input with the posedge of clk_apb,2 + input with the negedge of clk_apb, 3: input with the spi_clk. + Can be configured in CONF state. */ + __IOM uint32_t SPI_DIN3_MODE : 2; /*!< the input signals are delayed by SPI module clock cycles, 0: + input without delayed, 1: input with the posedge of clk_apb,2 + input with the negedge of clk_apb, 3: input with the spi_clk. + Can be configured in CONF state. */ + __IOM uint32_t SPI_DIN4_MODE : 2; /*!< the input signals are delayed by SPI module clock cycles, 0: + input without delayed, 1: input with the posedge of clk_apb,2 + input with the negedge of clk_apb, 3: input with the spi_clk. + Can be configured in CONF state. */ + __IOM uint32_t SPI_DIN5_MODE : 2; /*!< the input signals are delayed by SPI module clock cycles, 0: + input without delayed, 1: input with the posedge of clk_apb,2 + input with the negedge of clk_apb, 3: input with the spi_clk. + Can be configured in CONF state. */ + __IOM uint32_t SPI_DIN6_MODE : 2; /*!< the input signals are delayed by SPI module clock cycles, 0: + input without delayed, 1: input with the posedge of clk_apb,2 + input with the negedge of clk_apb, 3: input with the spi_clk. + Can be configured in CONF state. */ + __IOM uint32_t SPI_DIN7_MODE : 2; /*!< the input signals are delayed by SPI module clock cycles, 0: + input without delayed, 1: input with the posedge of clk_apb,2 + input with the negedge of clk_apb, 3: input with the spi_clk. + Can be configured in CONF state. */ + __IOM uint32_t SPI_TIMING_HCLK_ACTIVE : 1;/*!< 1:enable hclk in SPI input timing module. 0: disable it. Can + be configured in CONF state. */ + uint32_t : 15; + } bit; + } SPI_DIN_MODE; + + union { + __IOM uint32_t reg; /*!< SPI input delay number configuration */ + + struct { + __IOM uint32_t SPI_DIN0_NUM : 2; /*!< the input signals are delayed by SPI module clock cycles, 0: + delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured + in CONF state. */ + __IOM uint32_t SPI_DIN1_NUM : 2; /*!< the input signals are delayed by SPI module clock cycles, 0: + delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured + in CONF state. */ + __IOM uint32_t SPI_DIN2_NUM : 2; /*!< the input signals are delayed by SPI module clock cycles, 0: + delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured + in CONF state. */ + __IOM uint32_t SPI_DIN3_NUM : 2; /*!< the input signals are delayed by SPI module clock cycles, 0: + delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured + in CONF state. */ + __IOM uint32_t SPI_DIN4_NUM : 2; /*!< the input signals are delayed by SPI module clock cycles, 0: + delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured + in CONF state. */ + __IOM uint32_t SPI_DIN5_NUM : 2; /*!< the input signals are delayed by SPI module clock cycles, 0: + delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured + in CONF state. */ + __IOM uint32_t SPI_DIN6_NUM : 2; /*!< the input signals are delayed by SPI module clock cycles, 0: + delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured + in CONF state. */ + __IOM uint32_t SPI_DIN7_NUM : 2; /*!< the input signals are delayed by SPI module clock cycles, 0: + delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured + in CONF state. */ + uint32_t : 16; + } bit; + } SPI_DIN_NUM; + + union { + __IOM uint32_t reg; /*!< SPI output delay mode configuration */ + + struct { + __IOM uint32_t SPI_DOUT0_MODE : 1; /*!< The output signal 0 is delayed by the SPI module clock, 0: output + without delayed, 1: output delay for a SPI module clock + cycle at its negative edge. Can be configured in CONF state. */ + __IOM uint32_t SPI_DOUT1_MODE : 1; /*!< The output signal 1 is delayed by the SPI module clock, 0: output + without delayed, 1: output delay for a SPI module clock + cycle at its negative edge. Can be configured in CONF state. */ + __IOM uint32_t SPI_DOUT2_MODE : 1; /*!< The output signal 2 is delayed by the SPI module clock, 0: output + without delayed, 1: output delay for a SPI module clock + cycle at its negative edge. Can be configured in CONF state. */ + __IOM uint32_t SPI_DOUT3_MODE : 1; /*!< The output signal 3 is delayed by the SPI module clock, 0: output + without delayed, 1: output delay for a SPI module clock + cycle at its negative edge. Can be configured in CONF state. */ + __IOM uint32_t SPI_DOUT4_MODE : 1; /*!< The output signal 4 is delayed by the SPI module clock, 0: output + without delayed, 1: output delay for a SPI module clock + cycle at its negative edge. Can be configured in CONF state. */ + __IOM uint32_t SPI_DOUT5_MODE : 1; /*!< The output signal 5 is delayed by the SPI module clock, 0: output + without delayed, 1: output delay for a SPI module clock + cycle at its negative edge. Can be configured in CONF state. */ + __IOM uint32_t SPI_DOUT6_MODE : 1; /*!< The output signal 6 is delayed by the SPI module clock, 0: output + without delayed, 1: output delay for a SPI module clock + cycle at its negative edge. Can be configured in CONF state. */ + __IOM uint32_t SPI_DOUT7_MODE : 1; /*!< The output signal 7 is delayed by the SPI module clock, 0: output + without delayed, 1: output delay for a SPI module clock + cycle at its negative edge. Can be configured in CONF state. */ + __IOM uint32_t SPI_D_DQS_MODE : 1; /*!< The output signal SPI_DQS is delayed by the SPI module clock, + 0: output without delayed, 1: output delay for a SPI module + clock cycle at its negative edge. Can be configured in + CONF state. */ + uint32_t : 23; + } bit; + } SPI_DOUT_MODE; + + union { + __IOM uint32_t reg; /*!< SPI DMA control register */ + + struct { + __IM uint32_t SPI_DMA_OUTFIFO_EMPTY : 1; /*!< Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready + for sending data. 0: DMA TX FIFO is ready for sending data. */ + __IM uint32_t SPI_DMA_INFIFO_FULL : 1; /*!< Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready + for receiving data. 0: DMA RX FIFO is ready for receiving + data. */ + uint32_t : 16; + __IOM uint32_t SPI_DMA_SLV_SEG_TRANS_EN : 1;/*!< Enable dma segment transfer in spi dma half slave mode. 1: enable. + 0: disable. */ + __IOM uint32_t SPI_SLV_RX_SEG_TRANS_CLR_EN : 1;/*!< 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: + spi_dma_infifo_full_vld is cleared by spi_trans_done. */ + __IOM uint32_t SPI_SLV_TX_SEG_TRANS_CLR_EN : 1;/*!< 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. + 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done. */ + __IOM uint32_t SPI_RX_EOF_EN : 1; /*!< 1: spi_dma_inlink_eof is set when the number of dma pushed data + bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] + in spi dma transition. 0: spi_dma_inlink_eof is set by + spi_trans_done in non-seg-trans or spi_dma_seg_trans_done + in seg-trans. */ + uint32_t : 5; + __IOM uint32_t SPI_DMA_RX_ENA : 1; /*!< Set this bit to enable SPI DMA controlled receive data mode. */ + __IOM uint32_t SPI_DMA_TX_ENA : 1; /*!< Set this bit to enable SPI DMA controlled send data mode. */ + __OM uint32_t SPI_RX_AFIFO_RST : 1; /*!< Set this bit to reset RX AFIFO, which is used to receive data + in SPI master and slave mode transfer. */ + __OM uint32_t SPI_BUF_AFIFO_RST : 1; /*!< Set this bit to reset BUF TX AFIFO, which is used send data + out in SPI slave CPU controlled mode transfer and master + mode transfer. */ + __OM uint32_t SPI_DMA_AFIFO_RST : 1; /*!< Set this bit to reset DMA TX AFIFO, which is used to send data + out in SPI slave DMA controlled mode transfer. */ + } bit; + } SPI_DMA_CONF; + + union { + __IOM uint32_t reg; /*!< SPI interrupt enable register */ + + struct { + __IOM uint32_t SPI_DMA_INFIFO_FULL_ERR_INT_ENA : 1;/*!< The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. */ + __IOM uint32_t SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA : 1;/*!< The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. */ + __IOM uint32_t SPI_SLV_EX_QPI_INT_ENA : 1;/*!< The enable bit for SPI slave Ex_QPI interrupt. */ + __IOM uint32_t SPI_SLV_EN_QPI_INT_ENA : 1;/*!< The enable bit for SPI slave En_QPI interrupt. */ + __IOM uint32_t SPI_SLV_CMD7_INT_ENA : 1; /*!< The enable bit for SPI slave CMD7 interrupt. */ + __IOM uint32_t SPI_SLV_CMD8_INT_ENA : 1; /*!< The enable bit for SPI slave CMD8 interrupt. */ + __IOM uint32_t SPI_SLV_CMD9_INT_ENA : 1; /*!< The enable bit for SPI slave CMD9 interrupt. */ + __IOM uint32_t SPI_SLV_CMDA_INT_ENA : 1; /*!< The enable bit for SPI slave CMDA interrupt. */ + __IOM uint32_t SPI_SLV_RD_DMA_DONE_INT_ENA : 1;/*!< The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt. */ + __IOM uint32_t SPI_SLV_WR_DMA_DONE_INT_ENA : 1;/*!< The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt. */ + __IOM uint32_t SPI_SLV_RD_BUF_DONE_INT_ENA : 1;/*!< The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt. */ + __IOM uint32_t SPI_SLV_WR_BUF_DONE_INT_ENA : 1;/*!< The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt. */ + __IOM uint32_t SPI_TRANS_DONE_INT_ENA : 1;/*!< The enable bit for SPI_TRANS_DONE_INT interrupt. */ + __IOM uint32_t SPI_DMA_SEG_TRANS_DONE_INT_ENA : 1;/*!< The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. */ + __IOM uint32_t SPI_SEG_MAGIC_ERR_INT_ENA : 1;/*!< The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt. */ + __IOM uint32_t SPI_SLV_BUF_ADDR_ERR_INT_ENA : 1;/*!< The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. */ + __IOM uint32_t SPI_SLV_CMD_ERR_INT_ENA : 1;/*!< The enable bit for SPI_SLV_CMD_ERR_INT interrupt. */ + __IOM uint32_t SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA : 1;/*!< The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. */ + __IOM uint32_t SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA : 1;/*!< The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. */ + __IOM uint32_t SPI_APP2_INT_ENA : 1; /*!< The enable bit for SPI_APP2_INT interrupt. */ + __IOM uint32_t SPI_APP1_INT_ENA : 1; /*!< The enable bit for SPI_APP1_INT interrupt. */ + uint32_t : 11; + } bit; + } SPI_DMA_INT_ENA; + + union { + __IOM uint32_t reg; /*!< SPI interrupt clear register */ + + struct { + __OM uint32_t SPI_DMA_INFIFO_FULL_ERR_INT_CLR : 1;/*!< The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. */ + __OM uint32_t SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR : 1;/*!< The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. */ + __OM uint32_t SPI_SLV_EX_QPI_INT_CLR : 1;/*!< The clear bit for SPI slave Ex_QPI interrupt. */ + __OM uint32_t SPI_SLV_EN_QPI_INT_CLR : 1;/*!< The clear bit for SPI slave En_QPI interrupt. */ + __OM uint32_t SPI_SLV_CMD7_INT_CLR : 1; /*!< The clear bit for SPI slave CMD7 interrupt. */ + __OM uint32_t SPI_SLV_CMD8_INT_CLR : 1; /*!< The clear bit for SPI slave CMD8 interrupt. */ + __OM uint32_t SPI_SLV_CMD9_INT_CLR : 1; /*!< The clear bit for SPI slave CMD9 interrupt. */ + __OM uint32_t SPI_SLV_CMDA_INT_CLR : 1; /*!< The clear bit for SPI slave CMDA interrupt. */ + __OM uint32_t SPI_SLV_RD_DMA_DONE_INT_CLR : 1;/*!< The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt. */ + __OM uint32_t SPI_SLV_WR_DMA_DONE_INT_CLR : 1;/*!< The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt. */ + __OM uint32_t SPI_SLV_RD_BUF_DONE_INT_CLR : 1;/*!< The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt. */ + __OM uint32_t SPI_SLV_WR_BUF_DONE_INT_CLR : 1;/*!< The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt. */ + __OM uint32_t SPI_TRANS_DONE_INT_CLR : 1;/*!< The clear bit for SPI_TRANS_DONE_INT interrupt. */ + __OM uint32_t SPI_DMA_SEG_TRANS_DONE_INT_CLR : 1;/*!< The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. */ + __OM uint32_t SPI_SEG_MAGIC_ERR_INT_CLR : 1;/*!< The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt. */ + __OM uint32_t SPI_SLV_BUF_ADDR_ERR_INT_CLR : 1;/*!< The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. */ + __OM uint32_t SPI_SLV_CMD_ERR_INT_CLR : 1;/*!< The clear bit for SPI_SLV_CMD_ERR_INT interrupt. */ + __OM uint32_t SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR : 1;/*!< The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. */ + __OM uint32_t SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR : 1;/*!< The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. */ + __OM uint32_t SPI_APP2_INT_CLR : 1; /*!< The clear bit for SPI_APP2_INT interrupt. */ + __OM uint32_t SPI_APP1_INT_CLR : 1; /*!< The clear bit for SPI_APP1_INT interrupt. */ + uint32_t : 11; + } bit; + } SPI_DMA_INT_CLR; + + union { + __IOM uint32_t reg; /*!< SPI interrupt raw register */ + + struct { + __IOM uint32_t SPI_DMA_INFIFO_FULL_ERR_INT_RAW : 1;/*!< 1: The current data rate of DMA Rx is smaller than that of SPI, + which will lose the receive data. 0: Others. */ + __IOM uint32_t SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW : 1;/*!< 1: The current data rate of DMA TX is smaller than that of SPI. + SPI will stop in master mode and send out all 0 in slave + mode. 0: Others. */ + __IOM uint32_t SPI_SLV_EX_QPI_INT_RAW : 1;/*!< The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode + Ex_QPI transmission is ended. 0: Others. */ + __IOM uint32_t SPI_SLV_EN_QPI_INT_RAW : 1;/*!< The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode + En_QPI transmission is ended. 0: Others. */ + __IOM uint32_t SPI_SLV_CMD7_INT_RAW : 1; /*!< The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode + CMD7 transmission is ended. 0: Others. */ + __IOM uint32_t SPI_SLV_CMD8_INT_RAW : 1; /*!< The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode + CMD8 transmission is ended. 0: Others. */ + __IOM uint32_t SPI_SLV_CMD9_INT_RAW : 1; /*!< The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode + CMD9 transmission is ended. 0: Others. */ + __IOM uint32_t SPI_SLV_CMDA_INT_RAW : 1; /*!< The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode + CMDA transmission is ended. 0: Others. */ + __IOM uint32_t SPI_SLV_RD_DMA_DONE_INT_RAW : 1;/*!< The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave + mode Rd_DMA transmission is ended. 0: Others. */ + __IOM uint32_t SPI_SLV_WR_DMA_DONE_INT_RAW : 1;/*!< The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave + mode Wr_DMA transmission is ended. 0: Others. */ + __IOM uint32_t SPI_SLV_RD_BUF_DONE_INT_RAW : 1;/*!< The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave + mode Rd_BUF transmission is ended. 0: Others. */ + __IOM uint32_t SPI_SLV_WR_BUF_DONE_INT_RAW : 1;/*!< The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave + mode Wr_BUF transmission is ended. 0: Others. */ + __IOM uint32_t SPI_TRANS_DONE_INT_RAW : 1;/*!< The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master + mode transmission is ended. 0: others. */ + __IOM uint32_t SPI_DMA_SEG_TRANS_DONE_INT_RAW : 1;/*!< The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi + master DMA full-duplex/half-duplex seg-conf-trans ends + or slave half-duplex seg-trans ends. And data has been + pushed to corresponding memory. 0: seg-conf-trans or seg-trans + is not ended or not occurred. */ + __IOM uint32_t SPI_SEG_MAGIC_ERR_INT_RAW : 1;/*!< The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic + value in CONF buffer is error in the DMA seg-conf-trans. + 0: others. */ + __IOM uint32_t SPI_SLV_BUF_ADDR_ERR_INT_RAW : 1;/*!< The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing + data address of the current SPI slave mode CPU controlled + FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: + Others. */ + __IOM uint32_t SPI_SLV_CMD_ERR_INT_RAW : 1;/*!< The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave + command value in the current SPI slave HD mode transmission + is not supported. 0: Others. */ + __IOM uint32_t SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW : 1;/*!< The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: + There is a RX AFIFO write-full error when SPI inputs data + in master mode. 0: Others. */ + __IOM uint32_t SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW : 1;/*!< The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: + There is a TX BUF AFIFO read-empty error when SPI outputs + data in master mode. 0: Others. */ + __IOM uint32_t SPI_APP2_INT_RAW : 1; /*!< The raw bit for SPI_APP2_INT interrupt. The value is only controlled + by software. */ + __IOM uint32_t SPI_APP1_INT_RAW : 1; /*!< The raw bit for SPI_APP1_INT interrupt. The value is only controlled + by software. */ + uint32_t : 11; + } bit; + } SPI_DMA_INT_RAW; + + union { + __IOM uint32_t reg; /*!< SPI interrupt status register */ + + struct { + __IM uint32_t SPI_DMA_INFIFO_FULL_ERR_INT_ST : 1;/*!< The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. */ + __IM uint32_t SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST : 1;/*!< The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. */ + __IM uint32_t SPI_SLV_EX_QPI_INT_ST : 1; /*!< The status bit for SPI slave Ex_QPI interrupt. */ + __IM uint32_t SPI_SLV_EN_QPI_INT_ST : 1; /*!< The status bit for SPI slave En_QPI interrupt. */ + __IM uint32_t SPI_SLV_CMD7_INT_ST : 1; /*!< The status bit for SPI slave CMD7 interrupt. */ + __IM uint32_t SPI_SLV_CMD8_INT_ST : 1; /*!< The status bit for SPI slave CMD8 interrupt. */ + __IM uint32_t SPI_SLV_CMD9_INT_ST : 1; /*!< The status bit for SPI slave CMD9 interrupt. */ + __IM uint32_t SPI_SLV_CMDA_INT_ST : 1; /*!< The status bit for SPI slave CMDA interrupt. */ + __IM uint32_t SPI_SLV_RD_DMA_DONE_INT_ST : 1;/*!< The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt. */ + __IM uint32_t SPI_SLV_WR_DMA_DONE_INT_ST : 1;/*!< The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt. */ + __IM uint32_t SPI_SLV_RD_BUF_DONE_INT_ST : 1;/*!< The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt. */ + __IM uint32_t SPI_SLV_WR_BUF_DONE_INT_ST : 1;/*!< The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt. */ + __IM uint32_t SPI_TRANS_DONE_INT_ST : 1; /*!< The status bit for SPI_TRANS_DONE_INT interrupt. */ + __IM uint32_t SPI_DMA_SEG_TRANS_DONE_INT_ST : 1;/*!< The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. */ + __IM uint32_t SPI_SEG_MAGIC_ERR_INT_ST : 1;/*!< The status bit for SPI_SEG_MAGIC_ERR_INT interrupt. */ + __IM uint32_t SPI_SLV_BUF_ADDR_ERR_INT_ST : 1;/*!< The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. */ + __IM uint32_t SPI_SLV_CMD_ERR_INT_ST : 1;/*!< The status bit for SPI_SLV_CMD_ERR_INT interrupt. */ + __IM uint32_t SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST : 1;/*!< The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. */ + __IM uint32_t SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST : 1;/*!< The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. */ + __IM uint32_t SPI_APP2_INT_ST : 1; /*!< The status bit for SPI_APP2_INT interrupt. */ + __IM uint32_t SPI_APP1_INT_ST : 1; /*!< The status bit for SPI_APP1_INT interrupt. */ + uint32_t : 11; + } bit; + } SPI_DMA_INT_ST; + + union { + __IOM uint32_t reg; /*!< SPI interrupt software set register */ + + struct { + __OM uint32_t SPI_DMA_INFIFO_FULL_ERR_INT_SET : 1;/*!< The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. */ + __OM uint32_t SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET : 1;/*!< The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. */ + __OM uint32_t SPI_SLV_EX_QPI_INT_SET : 1;/*!< The software set bit for SPI slave Ex_QPI interrupt. */ + __OM uint32_t SPI_SLV_EN_QPI_INT_SET : 1;/*!< The software set bit for SPI slave En_QPI interrupt. */ + __OM uint32_t SPI_SLV_CMD7_INT_SET : 1; /*!< The software set bit for SPI slave CMD7 interrupt. */ + __OM uint32_t SPI_SLV_CMD8_INT_SET : 1; /*!< The software set bit for SPI slave CMD8 interrupt. */ + __OM uint32_t SPI_SLV_CMD9_INT_SET : 1; /*!< The software set bit for SPI slave CMD9 interrupt. */ + __OM uint32_t SPI_SLV_CMDA_INT_SET : 1; /*!< The software set bit for SPI slave CMDA interrupt. */ + __OM uint32_t SPI_SLV_RD_DMA_DONE_INT_SET : 1;/*!< The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt. */ + __OM uint32_t SPI_SLV_WR_DMA_DONE_INT_SET : 1;/*!< The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt. */ + __OM uint32_t SPI_SLV_RD_BUF_DONE_INT_SET : 1;/*!< The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt. */ + __OM uint32_t SPI_SLV_WR_BUF_DONE_INT_SET : 1;/*!< The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt. */ + __OM uint32_t SPI_TRANS_DONE_INT_SET : 1;/*!< The software set bit for SPI_TRANS_DONE_INT interrupt. */ + __OM uint32_t SPI_DMA_SEG_TRANS_DONE_INT_SET : 1;/*!< The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. */ + __OM uint32_t SPI_SEG_MAGIC_ERR_INT_SET : 1;/*!< The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt. */ + __OM uint32_t SPI_SLV_BUF_ADDR_ERR_INT_SET : 1;/*!< The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. */ + __OM uint32_t SPI_SLV_CMD_ERR_INT_SET : 1;/*!< The software set bit for SPI_SLV_CMD_ERR_INT interrupt. */ + __OM uint32_t SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET : 1;/*!< The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. */ + __OM uint32_t SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET : 1;/*!< The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. */ + __OM uint32_t SPI_APP2_INT_SET : 1; /*!< The software set bit for SPI_APP2_INT interrupt. */ + __OM uint32_t SPI_APP1_INT_SET : 1; /*!< The software set bit for SPI_APP1_INT interrupt. */ + uint32_t : 11; + } bit; + } SPI_DMA_INT_SET; + __IM uint32_t RESERVED[20]; + + union { + __IOM uint32_t reg; /*!< SPI CPU-controlled buffer0 */ + + struct { + __IOM uint32_t SPI_BUF0 : 32; /*!< data buffer */ + } bit; + } SPI_W0; + + union { + __IOM uint32_t reg; /*!< SPI CPU-controlled buffer1 */ + + struct { + __IOM uint32_t SPI_BUF1 : 32; /*!< data buffer */ + } bit; + } SPI_W1; + + union { + __IOM uint32_t reg; /*!< SPI CPU-controlled buffer2 */ + + struct { + __IOM uint32_t SPI_BUF2 : 32; /*!< data buffer */ + } bit; + } SPI_W2; + + union { + __IOM uint32_t reg; /*!< SPI CPU-controlled buffer3 */ + + struct { + __IOM uint32_t SPI_BUF3 : 32; /*!< data buffer */ + } bit; + } SPI_W3; + + union { + __IOM uint32_t reg; /*!< SPI CPU-controlled buffer4 */ + + struct { + __IOM uint32_t SPI_BUF4 : 32; /*!< data buffer */ + } bit; + } SPI_W4; + + union { + __IOM uint32_t reg; /*!< SPI CPU-controlled buffer5 */ + + struct { + __IOM uint32_t SPI_BUF5 : 32; /*!< data buffer */ + } bit; + } SPI_W5; + + union { + __IOM uint32_t reg; /*!< SPI CPU-controlled buffer6 */ + + struct { + __IOM uint32_t SPI_BUF6 : 32; /*!< data buffer */ + } bit; + } SPI_W6; + + union { + __IOM uint32_t reg; /*!< SPI CPU-controlled buffer7 */ + + struct { + __IOM uint32_t SPI_BUF7 : 32; /*!< data buffer */ + } bit; + } SPI_W7; + + union { + __IOM uint32_t reg; /*!< SPI CPU-controlled buffer8 */ + + struct { + __IOM uint32_t SPI_BUF8 : 32; /*!< data buffer */ + } bit; + } SPI_W8; + + union { + __IOM uint32_t reg; /*!< SPI CPU-controlled buffer9 */ + + struct { + __IOM uint32_t SPI_BUF9 : 32; /*!< data buffer */ + } bit; + } SPI_W9; + + union { + __IOM uint32_t reg; /*!< SPI CPU-controlled buffer10 */ + + struct { + __IOM uint32_t SPI_BUF10 : 32; /*!< data buffer */ + } bit; + } SPI_W10; + + union { + __IOM uint32_t reg; /*!< SPI CPU-controlled buffer11 */ + + struct { + __IOM uint32_t SPI_BUF11 : 32; /*!< data buffer */ + } bit; + } SPI_W11; + + union { + __IOM uint32_t reg; /*!< SPI CPU-controlled buffer12 */ + + struct { + __IOM uint32_t SPI_BUF12 : 32; /*!< data buffer */ + } bit; + } SPI_W12; + + union { + __IOM uint32_t reg; /*!< SPI CPU-controlled buffer13 */ + + struct { + __IOM uint32_t SPI_BUF13 : 32; /*!< data buffer */ + } bit; + } SPI_W13; + + union { + __IOM uint32_t reg; /*!< SPI CPU-controlled buffer14 */ + + struct { + __IOM uint32_t SPI_BUF14 : 32; /*!< data buffer */ + } bit; + } SPI_W14; + + union { + __IOM uint32_t reg; /*!< SPI CPU-controlled buffer15 */ + + struct { + __IOM uint32_t SPI_BUF15 : 32; /*!< data buffer */ + } bit; + } SPI_W15; + __IM uint32_t RESERVED1[2]; + + union { + __IOM uint32_t reg; /*!< SPI slave control register */ + + struct { + __IOM uint32_t SPI_CLK_MODE : 2; /*!< SPI clock mode bits. 0: SPI clock is off when CS inactive 1: + SPI clock is delayed one cycle after CS inactive 2: SPI + clock is delayed two cycles after CS inactive 3: SPI clock + is alwasy on. Can be configured in CONF state. */ + __IOM uint32_t SPI_CLK_MODE_13 : 1; /*!< {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output + data B[0]/B[7]. 0: support spi clk mode 0 and 2, first + edge output data B[1]/B[6]. */ + __IOM uint32_t SPI_RSCK_DATA_OUT : 1; /*!< It saves half a cycle when tsck is the same as rsck. 1: output + data at rsck posedge 0: output data at tsck posedge */ + uint32_t : 4; + __IOM uint32_t SPI_SLV_RDDMA_BITLEN_EN : 1;/*!< 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave + data length in DMA controlled mode(Rd_DMA). 0: others */ + __IOM uint32_t SPI_SLV_WRDMA_BITLEN_EN : 1;/*!< 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave + data length in DMA controlled mode(Wr_DMA). 0: others */ + __IOM uint32_t SPI_SLV_RDBUF_BITLEN_EN : 1;/*!< 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave + data length in CPU controlled mode(Rd_BUF). 0: others */ + __IOM uint32_t SPI_SLV_WRBUF_BITLEN_EN : 1;/*!< 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave + data length in CPU controlled mode(Wr_BUF). 0: others */ + __IM uint32_t SPI_SLV_LAST_BYTE_STRB : 8;/*!< Represents the effective bit of the last received data byte + in SPI slave FD and HD mode. */ + uint32_t : 2; + __IOM uint32_t SPI_DMA_SEG_MAGIC_VALUE : 4;/*!< The magic value of BM table in master DMA seg-trans. */ + __IOM uint32_t MODE : 1; /*!< Set SPI work mode. 1: slave mode 0: master mode. */ + __OM uint32_t SPI_SOFT_RESET : 1; /*!< Software reset enable, reset the spi clock line cs line and + data lines. Can be configured in CONF state. */ + __IOM uint32_t SPI_USR_CONF : 1; /*!< 1: Enable the DMA CONF phase of current seg-trans operation, + which means seg-trans will start. 0: This is not seg-trans + mode. */ + __IOM uint32_t SPI_MST_FD_WAIT_DMA_TX_DATA : 1;/*!< In master full-duplex mode, 1: GP-SPI will wait DMA TX data + is ready before starting SPI transfer. 0: GP-SPI does not + wait DMA TX data before starting SPI transfer. */ + uint32_t : 2; + } bit; + } SPI_SLAVE; + + union { + __IOM uint32_t reg; /*!< SPI slave control register 1 */ + + struct { + __IOM uint32_t SPI_SLV_DATA_BITLEN : 18; /*!< The transferred data bit length in SPI slave FD and HD mode. */ + __IOM uint32_t SPI_SLV_LAST_COMMAND : 8; /*!< In the slave mode it is the value of command. */ + __IOM uint32_t SPI_SLV_LAST_ADDR : 6; /*!< In the slave mode it is the value of address. */ + } bit; + } SPI_SLAVE1; + + union { + __IOM uint32_t reg; /*!< SPI module clock and register clock control */ + + struct { + __IOM uint32_t SPI_CLK_EN : 1; /*!< Set this bit to enable clk gate */ + __IOM uint32_t SPI_MST_CLK_ACTIVE : 1; /*!< Set this bit to power on the SPI module clock. */ + __IOM uint32_t SPI_MST_CLK_SEL : 1; /*!< This bit is used to select SPI module clock source in master + mode. 1: PLL_CLK_80M. 0: XTAL CLK. */ + uint32_t : 29; + } bit; + } SPI_CLK_GATE; + __IM uint32_t RESERVED2; + + union { + __IOM uint32_t reg; /*!< Version control */ + + struct { + __IOM uint32_t SPI_DATE : 28; /*!< SPI register version. */ + uint32_t : 4; + } bit; + } SPI_DATE; +} SPI2_Type; /*!< Size = 244 (0xf4) */ + + + +/* =========================================================================================================================== */ +/* ================ SPI3 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief SPI (Serial Peripheral Interface) Controller 3 (SPI3) + */ + +typedef struct { /*!< SPI3 Structure */ + + union { + __IOM uint32_t reg; /*!< Command control register */ + + struct { + uint32_t : 23; + __OM uint32_t SPI_UPDATE : 1; /*!< Set this bit to synchronize SPI registers from APB clock domain + into SPI module clock domain, which is only used in SPI + master mode. */ + __IOM uint32_t SPI_USR : 1; /*!< User define command enable. An operation will be triggered when + the bit is set. The bit will be cleared once the operation + done.1: enable 0: disable. Can not be changed by CONF_buf. */ + uint32_t : 7; + } bit; + } SPI_CMD; + + union { + __IOM uint32_t reg; /*!< Address value register */ + + struct { + __IOM uint32_t SPI_USR_ADDR_VALUE : 32; /*!< Address to slave. Can be configured in CONF state. */ + } bit; + } SPI_ADDR; + + union { + __IOM uint32_t reg; /*!< SPI control register */ + + struct { + uint32_t : 3; + __IOM uint32_t SPI_DUMMY_OUT : 1; /*!< 0: In the dummy phase, the FSPI bus signals are not output. + 1: In the dummy phase, the FSPI bus signals are output. + Can be configured in CONF state. */ + uint32_t : 1; + __IOM uint32_t SPI_FADDR_DUAL : 1; /*!< Apply 2 signals during addr phase 1:enable 0: disable. Can be + configured in CONF state. */ + __IOM uint32_t SPI_FADDR_QUAD : 1; /*!< Apply 4 signals during addr phase 1:enable 0: disable. Can be + configured in CONF state. */ + uint32_t : 1; + __IOM uint32_t SPI_FCMD_DUAL : 1; /*!< Apply 2 signals during command phase 1:enable 0: disable. Can + be configured in CONF state. */ + __IOM uint32_t SPI_FCMD_QUAD : 1; /*!< Apply 4 signals during command phase 1:enable 0: disable. Can + be configured in CONF state. */ + uint32_t : 4; + __IOM uint32_t SPI_FREAD_DUAL : 1; /*!< In the read operations, read-data phase apply 2 signals. 1: + enable 0: disable. Can be configured in CONF state. */ + __IOM uint32_t SPI_FREAD_QUAD : 1; /*!< In the read operations read-data phase apply 4 signals. 1: enable + 0: disable. Can be configured in CONF state. */ + uint32_t : 2; + __IOM uint32_t SPI_Q_POL : 1; /*!< The bit is used to set MISO line polarity, 1: high 0, low. Can + be configured in CONF state. */ + __IOM uint32_t SPI_D_POL : 1; /*!< The bit is used to set MOSI line polarity, 1: high 0, low. Can + be configured in CONF state. */ + __IOM uint32_t SPI_HOLD_POL : 1; /*!< SPI_HOLD output value when SPI is idle. 1: output high, 0: output + low. Can be configured in CONF state. */ + __IOM uint32_t SPI_WP_POL : 1; /*!< Write protect signal output when SPI is idle. 1: output high, + 0: output low. Can be configured in CONF state. */ + uint32_t : 1; + __IOM uint32_t SPI_RD_BIT_ORDER : 2; /*!< In read-data (MISO) phase 1: LSB first 0: MSB first. Can be + configured in CONF state. */ + __IOM uint32_t SPI_WR_BIT_ORDER : 2; /*!< In command address write-data (MOSI) phases 1: LSB firs 0: MSB + first. Can be configured in CONF state. */ + uint32_t : 5; + } bit; + } SPI_CTRL; + + union { + __IOM uint32_t reg; /*!< SPI clock control register */ + + struct { + __IOM uint32_t SPI_CLKCNT_L : 6; /*!< In the master mode it must be equal to spi_clkcnt_N. In the + slave mode it must be 0. Can be configured in CONF state. */ + __IOM uint32_t SPI_CLKCNT_H : 6; /*!< In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In + the slave mode it must be 0. Can be configured in CONF + state. */ + __IOM uint32_t SPI_CLKCNT_N : 6; /*!< In the master mode it is the divider of spi_clk. So spi_clk + frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). + Can be configured in CONF state. */ + __IOM uint32_t SPI_CLKDIV_PRE : 4; /*!< In the master mode it is pre-divider of spi_clk. Can be configured + in CONF state. */ + uint32_t : 9; + __IOM uint32_t SPI_CLK_EQU_SYSCLK : 1; /*!< In the master mode 1: spi_clk is eqaul to system 0: spi_clk + is divided from system clock. Can be configured in CONF + state. */ + } bit; + } SPI_CLOCK; + + union { + __IOM uint32_t reg; /*!< SPI USER control register */ + + struct { + __IOM uint32_t SPI_DOUTDIN : 1; /*!< Set the bit to enable full duplex communication. 1: enable 0: + disable. Can be configured in CONF state. */ + uint32_t : 2; + __IOM uint32_t SPI_QPI_MODE : 1; /*!< Both for master mode and slave mode. 1: spi controller is in + QPI mode. 0: others. Can be configured in CONF state. */ + uint32_t : 1; + __IOM uint32_t SPI_TSCK_I_EDGE : 1; /*!< In the slave mode, this bit can be used to change the polarity + of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i. */ + __IOM uint32_t SPI_CS_HOLD : 1; /*!< spi cs keep low when spi is in done phase. 1: enable 0: disable. + Can be configured in CONF state. */ + __IOM uint32_t SPI_CS_SETUP : 1; /*!< spi cs is enable when spi is in prepare phase. 1: enable 0: + disable. Can be configured in CONF state. */ + __IOM uint32_t SPI_RSCK_I_EDGE : 1; /*!< In the slave mode, this bit can be used to change the polarity + of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i. */ + __IOM uint32_t SPI_CK_OUT_EDGE : 1; /*!< the bit combined with spi_mosi_delay_mode bits to set mosi signal + delay mode. Can be configured in CONF state. */ + uint32_t : 2; + __IOM uint32_t SPI_FWRITE_DUAL : 1; /*!< In the write operations read-data phase apply 2 signals. Can + be configured in CONF state. */ + __IOM uint32_t SPI_FWRITE_QUAD : 1; /*!< In the write operations read-data phase apply 4 signals. Can + be configured in CONF state. */ + uint32_t : 3; + __IOM uint32_t SPI_SIO : 1; /*!< Set the bit to enable 3-line half duplex communication mosi + and miso signals share the same pin. 1: enable 0: disable. + Can be configured in CONF state. */ + uint32_t : 6; + __IOM uint32_t SPI_USR_MISO_HIGHPART : 1; /*!< read-data phase only access to high-part of the buffer spi_w8~spi_w15. + 1: enable 0: disable. Can be configured in CONF state. */ + __IOM uint32_t SPI_USR_MOSI_HIGHPART : 1; /*!< write-data phase only access to high-part of the buffer spi_w8~spi_w15. + 1: enable 0: disable. Can be configured in CONF state. */ + __IOM uint32_t SPI_USR_DUMMY_IDLE : 1; /*!< spi clock is disable in dummy phase when the bit is enable. + Can be configured in CONF state. */ + __IOM uint32_t SPI_USR_MOSI : 1; /*!< This bit enable the write-data phase of an operation. Can be + configured in CONF state. */ + __IOM uint32_t SPI_USR_MISO : 1; /*!< This bit enable the read-data phase of an operation. Can be + configured in CONF state. */ + __IOM uint32_t SPI_USR_DUMMY : 1; /*!< This bit enable the dummy phase of an operation. Can be configured + in CONF state. */ + __IOM uint32_t SPI_USR_ADDR : 1; /*!< This bit enable the address phase of an operation. Can be configured + in CONF state. */ + __IOM uint32_t SPI_USR_COMMAND : 1; /*!< This bit enable the command phase of an operation. Can be configured + in CONF state. */ + } bit; + } SPI_USER; + + union { + __IOM uint32_t reg; /*!< SPI USER control register 1 */ + + struct { + __IOM uint32_t SPI_USR_DUMMY_CYCLELEN : 8;/*!< The length in spi_clk cycles of dummy phase. The register value + shall be (cycle_num-1). Can be configured in CONF state. */ + uint32_t : 8; + __IOM uint32_t SPI_MST_WFULL_ERR_END_EN : 1;/*!< 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid + in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended + when SPI RX AFIFO wfull error is valid in GP-SPI master + FD/HD-mode. */ + __IOM uint32_t SPI_CS_SETUP_TIME : 5; /*!< (cycles+1) of prepare phase by spi clock this bits are combined + with spi_cs_setup bit. Can be configured in CONF state. */ + __IOM uint32_t SPI_CS_HOLD_TIME : 5; /*!< delay cycles of cs pin by spi clock this bits are combined with + spi_cs_hold bit. Can be configured in CONF state. */ + __IOM uint32_t SPI_USR_ADDR_BITLEN : 5; /*!< The length in bits of address phase. The register value shall + be (bit_num-1). Can be configured in CONF state. */ + } bit; + } SPI_USER1; + + union { + __IOM uint32_t reg; /*!< SPI USER control register 2 */ + + struct { + __IOM uint32_t SPI_USR_COMMAND_VALUE : 16;/*!< The value of command. Can be configured in CONF state. */ + uint32_t : 11; + __IOM uint32_t SPI_MST_REMPTY_ERR_END_EN : 1;/*!< 1: SPI transfer is ended when SPI TX AFIFO read empty error + is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is + not ended when SPI TX AFIFO read empty error is valid in + GP-SPI master FD/HD-mode. */ + __IOM uint32_t SPI_USR_COMMAND_BITLEN : 4;/*!< The length in bits of command phase. The register value shall + be (bit_num-1). Can be configured in CONF state. */ + } bit; + } SPI_USER2; + + union { + __IOM uint32_t reg; /*!< SPI data bit length control register */ + + struct { + __IOM uint32_t SPI_MS_DATA_BITLEN : 18; /*!< The value of these bits is the configured SPI transmission data + bit length in master mode DMA controlled transfer or CPU + controlled transfer. The value is also the configured bit + length in slave mode DMA RX controlled transfer. The register + value shall be (bit_num-1). Can be configured in CONF state. */ + uint32_t : 14; + } bit; + } SPI_MS_DLEN; + + union { + __IOM uint32_t reg; /*!< SPI misc register */ + + struct { + __IOM uint32_t SPI_CS0_DIS : 1; /*!< SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to + CS0 pin. Can be configured in CONF state. */ + __IOM uint32_t SPI_CS1_DIS : 1; /*!< SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to + CS1 pin. Can be configured in CONF state. */ + __IOM uint32_t SPI_CS2_DIS : 1; /*!< SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to + CS2 pin. Can be configured in CONF state. */ + uint32_t : 3; + __IOM uint32_t SPI_CK_DIS : 1; /*!< 1: spi clk out disable, 0: spi clk out enable. Can be configured + in CONF state. */ + __IOM uint32_t SPI_MASTER_CS_POL : 3; /*!< In the master mode the bits are the polarity of spi cs line, + the value is equivalent to spi_cs ^ spi_master_cs_pol. + Can be configured in CONF state. */ + uint32_t : 13; + __IOM uint32_t SPI_SLAVE_CS_POL : 1; /*!< spi slave input cs polarity select. 1: inv 0: not change. Can + be configured in CONF state. */ + uint32_t : 5; + __IOM uint32_t SPI_CK_IDLE_EDGE : 1; /*!< 1: spi clk line is high when idle 0: spi clk line is low when + idle. Can be configured in CONF state. */ + __IOM uint32_t SPI_CS_KEEP_ACTIVE : 1; /*!< spi cs line keep low when the bit is set. Can be configured + in CONF state. */ + __IOM uint32_t SPI_QUAD_DIN_PIN_SWAP : 1; /*!< 1: spi quad input swap enable 0: spi quad input swap disable. + Can be configured in CONF state. */ + } bit; + } SPI_MISC; + + union { + __IOM uint32_t reg; /*!< SPI input delay mode configuration */ + + struct { + __IOM uint32_t SPI_DIN0_MODE : 2; /*!< the input signals are delayed by SPI module clock cycles, 0: + input without delayed, 1: input with the posedge of clk_apb,2 + input with the negedge of clk_apb, 3: input with the spi_clk. + Can be configured in CONF state. */ + __IOM uint32_t SPI_DIN1_MODE : 2; /*!< the input signals are delayed by SPI module clock cycles, 0: + input without delayed, 1: input with the posedge of clk_apb,2 + input with the negedge of clk_apb, 3: input with the spi_clk. + Can be configured in CONF state. */ + __IOM uint32_t SPI_DIN2_MODE : 2; /*!< the input signals are delayed by SPI module clock cycles, 0: + input without delayed, 1: input with the posedge of clk_apb,2 + input with the negedge of clk_apb, 3: input with the spi_clk. + Can be configured in CONF state. */ + __IOM uint32_t SPI_DIN3_MODE : 2; /*!< the input signals are delayed by SPI module clock cycles, 0: + input without delayed, 1: input with the posedge of clk_apb,2 + input with the negedge of clk_apb, 3: input with the spi_clk. + Can be configured in CONF state. */ + uint32_t : 8; + __IOM uint32_t SPI_TIMING_HCLK_ACTIVE : 1;/*!< 1:enable hclk in SPI input timing module. 0: disable it. Can + be configured in CONF state. */ + uint32_t : 15; + } bit; + } SPI_DIN_MODE; + + union { + __IOM uint32_t reg; /*!< SPI input delay number configuration */ + + struct { + __IOM uint32_t SPI_DIN0_NUM : 2; /*!< the input signals are delayed by SPI module clock cycles, 0: + delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured + in CONF state. */ + __IOM uint32_t SPI_DIN1_NUM : 2; /*!< the input signals are delayed by SPI module clock cycles, 0: + delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured + in CONF state. */ + __IOM uint32_t SPI_DIN2_NUM : 2; /*!< the input signals are delayed by SPI module clock cycles, 0: + delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured + in CONF state. */ + __IOM uint32_t SPI_DIN3_NUM : 2; /*!< the input signals are delayed by SPI module clock cycles, 0: + delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured + in CONF state. */ + uint32_t : 24; + } bit; + } SPI_DIN_NUM; + + union { + __IOM uint32_t reg; /*!< SPI output delay mode configuration */ + + struct { + __IOM uint32_t SPI_DOUT0_MODE : 1; /*!< The output signal 0 is delayed by the SPI module clock, 0: output + without delayed, 1: output delay for a SPI module clock + cycle at its negative edge. Can be configured in CONF state. */ + __IOM uint32_t SPI_DOUT1_MODE : 1; /*!< The output signal 1 is delayed by the SPI module clock, 0: output + without delayed, 1: output delay for a SPI module clock + cycle at its negative edge. Can be configured in CONF state. */ + __IOM uint32_t SPI_DOUT2_MODE : 1; /*!< The output signal 2 is delayed by the SPI module clock, 0: output + without delayed, 1: output delay for a SPI module clock + cycle at its negative edge. Can be configured in CONF state. */ + __IOM uint32_t SPI_DOUT3_MODE : 1; /*!< The output signal 3 is delayed by the SPI module clock, 0: output + without delayed, 1: output delay for a SPI module clock + cycle at its negative edge. Can be configured in CONF state. */ + uint32_t : 28; + } bit; + } SPI_DOUT_MODE; + + union { + __IOM uint32_t reg; /*!< SPI DMA control register */ + + struct { + __IM uint32_t SPI_DMA_OUTFIFO_EMPTY : 1; /*!< Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready + for sending data. 0: DMA TX FIFO is ready for sending data. */ + __IM uint32_t SPI_DMA_INFIFO_FULL : 1; /*!< Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready + for receiving data. 0: DMA RX FIFO is ready for receiving + data. */ + uint32_t : 16; + __IOM uint32_t SPI_DMA_SLV_SEG_TRANS_EN : 1;/*!< Enable dma segment transfer in spi dma half slave mode. 1: enable. + 0: disable. */ + __IOM uint32_t SPI_SLV_RX_SEG_TRANS_CLR_EN : 1;/*!< 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: + spi_dma_infifo_full_vld is cleared by spi_trans_done. */ + __IOM uint32_t SPI_SLV_TX_SEG_TRANS_CLR_EN : 1;/*!< 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. + 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done. */ + __IOM uint32_t SPI_RX_EOF_EN : 1; /*!< 1: spi_dma_inlink_eof is set when the number of dma pushed data + bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] + in spi dma transition. 0: spi_dma_inlink_eof is set by + spi_trans_done in non-seg-trans or spi_dma_seg_trans_done + in seg-trans. */ + uint32_t : 5; + __IOM uint32_t SPI_DMA_RX_ENA : 1; /*!< Set this bit to enable SPI DMA controlled receive data mode. */ + __IOM uint32_t SPI_DMA_TX_ENA : 1; /*!< Set this bit to enable SPI DMA controlled send data mode. */ + __OM uint32_t SPI_RX_AFIFO_RST : 1; /*!< Set this bit to reset RX AFIFO, which is used to receive data + in SPI master and slave mode transfer. */ + __OM uint32_t SPI_BUF_AFIFO_RST : 1; /*!< Set this bit to reset BUF TX AFIFO, which is used send data + out in SPI slave CPU controlled mode transfer and master + mode transfer. */ + __OM uint32_t SPI_DMA_AFIFO_RST : 1; /*!< Set this bit to reset DMA TX AFIFO, which is used to send data + out in SPI slave DMA controlled mode transfer. */ + } bit; + } SPI_DMA_CONF; + + union { + __IOM uint32_t reg; /*!< SPI interrupt enable register */ + + struct { + __IOM uint32_t SPI_DMA_INFIFO_FULL_ERR_INT_ENA : 1;/*!< The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. */ + __IOM uint32_t SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA : 1;/*!< The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. */ + __IOM uint32_t SPI_SLV_EX_QPI_INT_ENA : 1;/*!< The enable bit for SPI slave Ex_QPI interrupt. */ + __IOM uint32_t SPI_SLV_EN_QPI_INT_ENA : 1;/*!< The enable bit for SPI slave En_QPI interrupt. */ + __IOM uint32_t SPI_SLV_CMD7_INT_ENA : 1; /*!< The enable bit for SPI slave CMD7 interrupt. */ + __IOM uint32_t SPI_SLV_CMD8_INT_ENA : 1; /*!< The enable bit for SPI slave CMD8 interrupt. */ + __IOM uint32_t SPI_SLV_CMD9_INT_ENA : 1; /*!< The enable bit for SPI slave CMD9 interrupt. */ + __IOM uint32_t SPI_SLV_CMDA_INT_ENA : 1; /*!< The enable bit for SPI slave CMDA interrupt. */ + __IOM uint32_t SPI_SLV_RD_DMA_DONE_INT_ENA : 1;/*!< The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt. */ + __IOM uint32_t SPI_SLV_WR_DMA_DONE_INT_ENA : 1;/*!< The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt. */ + __IOM uint32_t SPI_SLV_RD_BUF_DONE_INT_ENA : 1;/*!< The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt. */ + __IOM uint32_t SPI_SLV_WR_BUF_DONE_INT_ENA : 1;/*!< The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt. */ + __IOM uint32_t SPI_TRANS_DONE_INT_ENA : 1;/*!< The enable bit for SPI_TRANS_DONE_INT interrupt. */ + __IOM uint32_t SPI_DMA_SEG_TRANS_DONE_INT_ENA : 1;/*!< The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. */ + uint32_t : 1; + __IOM uint32_t SPI_SLV_BUF_ADDR_ERR_INT_ENA : 1;/*!< The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. */ + __IOM uint32_t SPI_SLV_CMD_ERR_INT_ENA : 1;/*!< The enable bit for SPI_SLV_CMD_ERR_INT interrupt. */ + __IOM uint32_t SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA : 1;/*!< The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. */ + __IOM uint32_t SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA : 1;/*!< The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. */ + __IOM uint32_t SPI_APP2_INT_ENA : 1; /*!< The enable bit for SPI_APP2_INT interrupt. */ + __IOM uint32_t SPI_APP1_INT_ENA : 1; /*!< The enable bit for SPI_APP1_INT interrupt. */ + uint32_t : 11; + } bit; + } SPI_DMA_INT_ENA; + + union { + __IOM uint32_t reg; /*!< SPI interrupt clear register */ + + struct { + __OM uint32_t SPI_DMA_INFIFO_FULL_ERR_INT_CLR : 1;/*!< The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. */ + __OM uint32_t SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR : 1;/*!< The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. */ + __OM uint32_t SPI_SLV_EX_QPI_INT_CLR : 1;/*!< The clear bit for SPI slave Ex_QPI interrupt. */ + __OM uint32_t SPI_SLV_EN_QPI_INT_CLR : 1;/*!< The clear bit for SPI slave En_QPI interrupt. */ + __OM uint32_t SPI_SLV_CMD7_INT_CLR : 1; /*!< The clear bit for SPI slave CMD7 interrupt. */ + __OM uint32_t SPI_SLV_CMD8_INT_CLR : 1; /*!< The clear bit for SPI slave CMD8 interrupt. */ + __OM uint32_t SPI_SLV_CMD9_INT_CLR : 1; /*!< The clear bit for SPI slave CMD9 interrupt. */ + __OM uint32_t SPI_SLV_CMDA_INT_CLR : 1; /*!< The clear bit for SPI slave CMDA interrupt. */ + __OM uint32_t SPI_SLV_RD_DMA_DONE_INT_CLR : 1;/*!< The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt. */ + __OM uint32_t SPI_SLV_WR_DMA_DONE_INT_CLR : 1;/*!< The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt. */ + __OM uint32_t SPI_SLV_RD_BUF_DONE_INT_CLR : 1;/*!< The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt. */ + __OM uint32_t SPI_SLV_WR_BUF_DONE_INT_CLR : 1;/*!< The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt. */ + __OM uint32_t SPI_TRANS_DONE_INT_CLR : 1;/*!< The clear bit for SPI_TRANS_DONE_INT interrupt. */ + __OM uint32_t SPI_DMA_SEG_TRANS_DONE_INT_CLR : 1;/*!< The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. */ + uint32_t : 1; + __OM uint32_t SPI_SLV_BUF_ADDR_ERR_INT_CLR : 1;/*!< The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. */ + __OM uint32_t SPI_SLV_CMD_ERR_INT_CLR : 1;/*!< The clear bit for SPI_SLV_CMD_ERR_INT interrupt. */ + __OM uint32_t SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR : 1;/*!< The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. */ + __OM uint32_t SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR : 1;/*!< The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. */ + __OM uint32_t SPI_APP2_INT_CLR : 1; /*!< The clear bit for SPI_APP2_INT interrupt. */ + __OM uint32_t SPI_APP1_INT_CLR : 1; /*!< The clear bit for SPI_APP1_INT interrupt. */ + uint32_t : 11; + } bit; + } SPI_DMA_INT_CLR; + + union { + __IOM uint32_t reg; /*!< SPI interrupt raw register */ + + struct { + __IOM uint32_t SPI_DMA_INFIFO_FULL_ERR_INT_RAW : 1;/*!< 1: The current data rate of DMA Rx is smaller than that of SPI, + which will lose the receive data. 0: Others. */ + __IOM uint32_t SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW : 1;/*!< 1: The current data rate of DMA TX is smaller than that of SPI. + SPI will stop in master mode and send out all 0 in slave + mode. 0: Others. */ + __IOM uint32_t SPI_SLV_EX_QPI_INT_RAW : 1;/*!< The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode + Ex_QPI transmission is ended. 0: Others. */ + __IOM uint32_t SPI_SLV_EN_QPI_INT_RAW : 1;/*!< The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode + En_QPI transmission is ended. 0: Others. */ + __IOM uint32_t SPI_SLV_CMD7_INT_RAW : 1; /*!< The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode + CMD7 transmission is ended. 0: Others. */ + __IOM uint32_t SPI_SLV_CMD8_INT_RAW : 1; /*!< The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode + CMD8 transmission is ended. 0: Others. */ + __IOM uint32_t SPI_SLV_CMD9_INT_RAW : 1; /*!< The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode + CMD9 transmission is ended. 0: Others. */ + __IOM uint32_t SPI_SLV_CMDA_INT_RAW : 1; /*!< The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode + CMDA transmission is ended. 0: Others. */ + __IOM uint32_t SPI_SLV_RD_DMA_DONE_INT_RAW : 1;/*!< The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave + mode Rd_DMA transmission is ended. 0: Others. */ + __IOM uint32_t SPI_SLV_WR_DMA_DONE_INT_RAW : 1;/*!< The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave + mode Wr_DMA transmission is ended. 0: Others. */ + __IOM uint32_t SPI_SLV_RD_BUF_DONE_INT_RAW : 1;/*!< The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave + mode Rd_BUF transmission is ended. 0: Others. */ + __IOM uint32_t SPI_SLV_WR_BUF_DONE_INT_RAW : 1;/*!< The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave + mode Wr_BUF transmission is ended. 0: Others. */ + __IOM uint32_t SPI_TRANS_DONE_INT_RAW : 1;/*!< The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master + mode transmission is ended. 0: others. */ + __IOM uint32_t SPI_DMA_SEG_TRANS_DONE_INT_RAW : 1;/*!< The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi + master DMA full-duplex/half-duplex seg-conf-trans ends + or slave half-duplex seg-trans ends. And data has been + pushed to corresponding memory. 0: seg-conf-trans or seg-trans + is not ended or not occurred. */ + uint32_t : 1; + __IOM uint32_t SPI_SLV_BUF_ADDR_ERR_INT_RAW : 1;/*!< The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing + data address of the current SPI slave mode CPU controlled + FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: + Others. */ + __IOM uint32_t SPI_SLV_CMD_ERR_INT_RAW : 1;/*!< The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave + command value in the current SPI slave HD mode transmission + is not supported. 0: Others. */ + __IOM uint32_t SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW : 1;/*!< The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: + There is a RX AFIFO write-full error when SPI inputs data + in master mode. 0: Others. */ + __IOM uint32_t SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW : 1;/*!< The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: + There is a TX BUF AFIFO read-empty error when SPI outputs + data in master mode. 0: Others. */ + __IOM uint32_t SPI_APP2_INT_RAW : 1; /*!< The raw bit for SPI_APP2_INT interrupt. The value is only controlled + by software. */ + __IOM uint32_t SPI_APP1_INT_RAW : 1; /*!< The raw bit for SPI_APP1_INT interrupt. The value is only controlled + by software. */ + uint32_t : 11; + } bit; + } SPI_DMA_INT_RAW; + + union { + __IOM uint32_t reg; /*!< SPI interrupt status register */ + + struct { + __IM uint32_t SPI_DMA_INFIFO_FULL_ERR_INT_ST : 1;/*!< The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. */ + __IM uint32_t SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST : 1;/*!< The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. */ + __IM uint32_t SPI_SLV_EX_QPI_INT_ST : 1; /*!< The status bit for SPI slave Ex_QPI interrupt. */ + __IM uint32_t SPI_SLV_EN_QPI_INT_ST : 1; /*!< The status bit for SPI slave En_QPI interrupt. */ + __IM uint32_t SPI_SLV_CMD7_INT_ST : 1; /*!< The status bit for SPI slave CMD7 interrupt. */ + __IM uint32_t SPI_SLV_CMD8_INT_ST : 1; /*!< The status bit for SPI slave CMD8 interrupt. */ + __IM uint32_t SPI_SLV_CMD9_INT_ST : 1; /*!< The status bit for SPI slave CMD9 interrupt. */ + __IM uint32_t SPI_SLV_CMDA_INT_ST : 1; /*!< The status bit for SPI slave CMDA interrupt. */ + __IM uint32_t SPI_SLV_RD_DMA_DONE_INT_ST : 1;/*!< The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt. */ + __IM uint32_t SPI_SLV_WR_DMA_DONE_INT_ST : 1;/*!< The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt. */ + __IM uint32_t SPI_SLV_RD_BUF_DONE_INT_ST : 1;/*!< The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt. */ + __IM uint32_t SPI_SLV_WR_BUF_DONE_INT_ST : 1;/*!< The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt. */ + __IM uint32_t SPI_TRANS_DONE_INT_ST : 1; /*!< The status bit for SPI_TRANS_DONE_INT interrupt. */ + __IM uint32_t SPI_DMA_SEG_TRANS_DONE_INT_ST : 1;/*!< The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. */ + uint32_t : 1; + __IM uint32_t SPI_SLV_BUF_ADDR_ERR_INT_ST : 1;/*!< The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. */ + __IM uint32_t SPI_SLV_CMD_ERR_INT_ST : 1;/*!< The status bit for SPI_SLV_CMD_ERR_INT interrupt. */ + __IM uint32_t SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST : 1;/*!< The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. */ + __IM uint32_t SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST : 1;/*!< The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. */ + __IM uint32_t SPI_APP2_INT_ST : 1; /*!< The status bit for SPI_APP2_INT interrupt. */ + __IM uint32_t SPI_APP1_INT_ST : 1; /*!< The status bit for SPI_APP1_INT interrupt. */ + uint32_t : 11; + } bit; + } SPI_DMA_INT_ST; + + union { + __IOM uint32_t reg; /*!< SPI interrupt software set register */ + + struct { + __OM uint32_t SPI_DMA_INFIFO_FULL_ERR_INT_SET : 1;/*!< The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. */ + __OM uint32_t SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET : 1;/*!< The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. */ + __OM uint32_t SPI_SLV_EX_QPI_INT_SET : 1;/*!< The software set bit for SPI slave Ex_QPI interrupt. */ + __OM uint32_t SPI_SLV_EN_QPI_INT_SET : 1;/*!< The software set bit for SPI slave En_QPI interrupt. */ + __OM uint32_t SPI_SLV_CMD7_INT_SET : 1; /*!< The software set bit for SPI slave CMD7 interrupt. */ + __OM uint32_t SPI_SLV_CMD8_INT_SET : 1; /*!< The software set bit for SPI slave CMD8 interrupt. */ + __OM uint32_t SPI_SLV_CMD9_INT_SET : 1; /*!< The software set bit for SPI slave CMD9 interrupt. */ + __OM uint32_t SPI_SLV_CMDA_INT_SET : 1; /*!< The software set bit for SPI slave CMDA interrupt. */ + __OM uint32_t SPI_SLV_RD_DMA_DONE_INT_SET : 1;/*!< The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt. */ + __OM uint32_t SPI_SLV_WR_DMA_DONE_INT_SET : 1;/*!< The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt. */ + __OM uint32_t SPI_SLV_RD_BUF_DONE_INT_SET : 1;/*!< The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt. */ + __OM uint32_t SPI_SLV_WR_BUF_DONE_INT_SET : 1;/*!< The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt. */ + __OM uint32_t SPI_TRANS_DONE_INT_SET : 1;/*!< The software set bit for SPI_TRANS_DONE_INT interrupt. */ + __OM uint32_t SPI_DMA_SEG_TRANS_DONE_INT_SET : 1;/*!< The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. */ + uint32_t : 1; + __OM uint32_t SPI_SLV_BUF_ADDR_ERR_INT_SET : 1;/*!< The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. */ + __OM uint32_t SPI_SLV_CMD_ERR_INT_SET : 1;/*!< The software set bit for SPI_SLV_CMD_ERR_INT interrupt. */ + __OM uint32_t SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET : 1;/*!< The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. */ + __OM uint32_t SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET : 1;/*!< The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. */ + __OM uint32_t SPI_APP2_INT_SET : 1; /*!< The software set bit for SPI_APP2_INT interrupt. */ + __OM uint32_t SPI_APP1_INT_SET : 1; /*!< The software set bit for SPI_APP1_INT interrupt. */ + uint32_t : 11; + } bit; + } SPI_DMA_INT_SET; + __IM uint32_t RESERVED[20]; + + union { + __IOM uint32_t reg; /*!< SPI CPU-controlled buffer0 */ + + struct { + __IOM uint32_t SPI_BUF0 : 32; /*!< data buffer */ + } bit; + } SPI_W0; + + union { + __IOM uint32_t reg; /*!< SPI CPU-controlled buffer1 */ + + struct { + __IOM uint32_t SPI_BUF1 : 32; /*!< data buffer */ + } bit; + } SPI_W1; + + union { + __IOM uint32_t reg; /*!< SPI CPU-controlled buffer2 */ + + struct { + __IOM uint32_t SPI_BUF2 : 32; /*!< data buffer */ + } bit; + } SPI_W2; + + union { + __IOM uint32_t reg; /*!< SPI CPU-controlled buffer3 */ + + struct { + __IOM uint32_t SPI_BUF3 : 32; /*!< data buffer */ + } bit; + } SPI_W3; + + union { + __IOM uint32_t reg; /*!< SPI CPU-controlled buffer4 */ + + struct { + __IOM uint32_t SPI_BUF4 : 32; /*!< data buffer */ + } bit; + } SPI_W4; + + union { + __IOM uint32_t reg; /*!< SPI CPU-controlled buffer5 */ + + struct { + __IOM uint32_t SPI_BUF5 : 32; /*!< data buffer */ + } bit; + } SPI_W5; + + union { + __IOM uint32_t reg; /*!< SPI CPU-controlled buffer6 */ + + struct { + __IOM uint32_t SPI_BUF6 : 32; /*!< data buffer */ + } bit; + } SPI_W6; + + union { + __IOM uint32_t reg; /*!< SPI CPU-controlled buffer7 */ + + struct { + __IOM uint32_t SPI_BUF7 : 32; /*!< data buffer */ + } bit; + } SPI_W7; + + union { + __IOM uint32_t reg; /*!< SPI CPU-controlled buffer8 */ + + struct { + __IOM uint32_t SPI_BUF8 : 32; /*!< data buffer */ + } bit; + } SPI_W8; + + union { + __IOM uint32_t reg; /*!< SPI CPU-controlled buffer9 */ + + struct { + __IOM uint32_t SPI_BUF9 : 32; /*!< data buffer */ + } bit; + } SPI_W9; + + union { + __IOM uint32_t reg; /*!< SPI CPU-controlled buffer10 */ + + struct { + __IOM uint32_t SPI_BUF10 : 32; /*!< data buffer */ + } bit; + } SPI_W10; + + union { + __IOM uint32_t reg; /*!< SPI CPU-controlled buffer11 */ + + struct { + __IOM uint32_t SPI_BUF11 : 32; /*!< data buffer */ + } bit; + } SPI_W11; + + union { + __IOM uint32_t reg; /*!< SPI CPU-controlled buffer12 */ + + struct { + __IOM uint32_t SPI_BUF12 : 32; /*!< data buffer */ + } bit; + } SPI_W12; + + union { + __IOM uint32_t reg; /*!< SPI CPU-controlled buffer13 */ + + struct { + __IOM uint32_t SPI_BUF13 : 32; /*!< data buffer */ + } bit; + } SPI_W13; + + union { + __IOM uint32_t reg; /*!< SPI CPU-controlled buffer14 */ + + struct { + __IOM uint32_t SPI_BUF14 : 32; /*!< data buffer */ + } bit; + } SPI_W14; + + union { + __IOM uint32_t reg; /*!< SPI CPU-controlled buffer15 */ + + struct { + __IOM uint32_t SPI_BUF15 : 32; /*!< data buffer */ + } bit; + } SPI_W15; + __IM uint32_t RESERVED1[2]; + + union { + __IOM uint32_t reg; /*!< SPI slave control register */ + + struct { + __IOM uint32_t SPI_CLK_MODE : 2; /*!< SPI clock mode bits. 0: SPI clock is off when CS inactive 1: + SPI clock is delayed one cycle after CS inactive 2: SPI + clock is delayed two cycles after CS inactive 3: SPI clock + is alwasy on. Can be configured in CONF state. */ + __IOM uint32_t SPI_CLK_MODE_13 : 1; /*!< {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output + data B[0]/B[7]. 0: support spi clk mode 0 and 2, first + edge output data B[1]/B[6]. */ + __IOM uint32_t SPI_RSCK_DATA_OUT : 1; /*!< It saves half a cycle when tsck is the same as rsck. 1: output + data at rsck posedge 0: output data at tsck posedge */ + uint32_t : 4; + __IOM uint32_t SPI_SLV_RDDMA_BITLEN_EN : 1;/*!< 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave + data length in DMA controlled mode(Rd_DMA). 0: others */ + __IOM uint32_t SPI_SLV_WRDMA_BITLEN_EN : 1;/*!< 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave + data length in DMA controlled mode(Wr_DMA). 0: others */ + __IOM uint32_t SPI_SLV_RDBUF_BITLEN_EN : 1;/*!< 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave + data length in CPU controlled mode(Rd_BUF). 0: others */ + __IOM uint32_t SPI_SLV_WRBUF_BITLEN_EN : 1;/*!< 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave + data length in CPU controlled mode(Wr_BUF). 0: others */ + __IM uint32_t SPI_SLV_LAST_BYTE_STRB : 8;/*!< Represents the effective bit of the last received data byte + in SPI slave FD and HD mode. */ + uint32_t : 6; + __IOM uint32_t MODE : 1; /*!< Set SPI work mode. 1: slave mode 0: master mode. */ + __OM uint32_t SPI_SOFT_RESET : 1; /*!< Software reset enable, reset the spi clock line cs line and + data lines. Can be configured in CONF state. */ + uint32_t : 1; + __IOM uint32_t SPI_MST_FD_WAIT_DMA_TX_DATA : 1;/*!< In master full-duplex mode, 1: GP-SPI will wait DMA TX data + is ready before starting SPI transfer. 0: GP-SPI does not + wait DMA TX data before starting SPI transfer. */ + uint32_t : 2; + } bit; + } SPI_SLAVE; + + union { + __IOM uint32_t reg; /*!< SPI slave control register 1 */ + + struct { + __IOM uint32_t SPI_SLV_DATA_BITLEN : 18; /*!< The transferred data bit length in SPI slave FD and HD mode. */ + __IOM uint32_t SPI_SLV_LAST_COMMAND : 8; /*!< In the slave mode it is the value of command. */ + __IOM uint32_t SPI_SLV_LAST_ADDR : 6; /*!< In the slave mode it is the value of address. */ + } bit; + } SPI_SLAVE1; + + union { + __IOM uint32_t reg; /*!< SPI module clock and register clock control */ + + struct { + __IOM uint32_t SPI_CLK_EN : 1; /*!< Set this bit to enable clk gate */ + __IOM uint32_t SPI_MST_CLK_ACTIVE : 1; /*!< Set this bit to power on the SPI module clock. */ + __IOM uint32_t SPI_MST_CLK_SEL : 1; /*!< This bit is used to select SPI module clock source in master + mode. 1: PLL_CLK_80M. 0: XTAL CLK. */ + uint32_t : 29; + } bit; + } SPI_CLK_GATE; + __IM uint32_t RESERVED2; + + union { + __IOM uint32_t reg; /*!< Version control */ + + struct { + __IOM uint32_t SPI_DATE : 28; /*!< SPI register version. */ + uint32_t : 4; + } bit; + } SPI_DATE; +} SPI3_Type; /*!< Size = 244 (0xf4) */ + + + +/* =========================================================================================================================== */ +/* ================ SYSTIMER ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief System Timer (SYSTIMER) + */ + +typedef struct { /*!< SYSTIMER Structure */ + + union { + __IOM uint32_t reg; /*!< Configure system timer clock */ + + struct { + __IOM uint32_t SYSTIMER_CLK_FO : 1; /*!< systimer clock force on */ + __IOM uint32_t ETM_EN : 1; /*!< enable systimer's etm task and event */ + uint32_t : 20; + __IOM uint32_t TARGET2_WORK_EN : 1; /*!< target2 work enable */ + __IOM uint32_t TARGET1_WORK_EN : 1; /*!< target1 work enable */ + __IOM uint32_t TARGET0_WORK_EN : 1; /*!< target0 work enable */ + __IOM uint32_t TIMER_UNIT1_CORE1_STALL_EN : 1;/*!< If timer unit1 is stalled when core1 stalled */ + __IOM uint32_t TIMER_UNIT1_CORE0_STALL_EN : 1;/*!< If timer unit1 is stalled when core0 stalled */ + __IOM uint32_t TIMER_UNIT0_CORE1_STALL_EN : 1;/*!< If timer unit0 is stalled when core1 stalled */ + __IOM uint32_t TIMER_UNIT0_CORE0_STALL_EN : 1;/*!< If timer unit0 is stalled when core0 stalled */ + __IOM uint32_t TIMER_UNIT1_WORK_EN : 1; /*!< timer unit1 work enable */ + __IOM uint32_t TIMER_UNIT0_WORK_EN : 1; /*!< timer unit0 work enable */ + __IOM uint32_t CLK_EN : 1; /*!< register file clk gating */ + } bit; + } CONF; + + union { + __IOM uint32_t reg; /*!< system timer unit0 value update register */ + + struct { + uint32_t : 29; + __IM uint32_t TIMER_UNIT0_VALUE_VALID : 1;/*!< timer value is sync and valid */ + __OM uint32_t TIMER_UNIT0_UPDATE : 1; /*!< update timer_unit0 */ + uint32_t : 1; + } bit; + } UNIT0_OP; + + union { + __IOM uint32_t reg; /*!< system timer unit1 value update register */ + + struct { + uint32_t : 29; + __IM uint32_t TIMER_UNIT1_VALUE_VALID : 1;/*!< timer value is sync and valid */ + __OM uint32_t TIMER_UNIT1_UPDATE : 1; /*!< update timer unit1 */ + uint32_t : 1; + } bit; + } UNIT1_OP; + + union { + __IOM uint32_t reg; /*!< system timer unit0 value high load register */ + + struct { + __IOM uint32_t TIMER_UNIT0_LOAD_HI : 20; /*!< timer unit0 load high 20 bits */ + uint32_t : 12; + } bit; + } UNIT0_LOAD_HI; + + union { + __IOM uint32_t reg; /*!< system timer unit0 value low load register */ + + struct { + __IOM uint32_t TIMER_UNIT0_LOAD_LO : 32; /*!< timer unit0 load low 32 bits */ + } bit; + } UNIT0_LOAD_LO; + + union { + __IOM uint32_t reg; /*!< system timer unit1 value high load register */ + + struct { + __IOM uint32_t TIMER_UNIT1_LOAD_HI : 20; /*!< timer unit1 load high 20 bits */ + uint32_t : 12; + } bit; + } UNIT1_LOAD_HI; + + union { + __IOM uint32_t reg; /*!< system timer unit1 value low load register */ + + struct { + __IOM uint32_t TIMER_UNIT1_LOAD_LO : 32; /*!< timer unit1 load low 32 bits */ + } bit; + } UNIT1_LOAD_LO; + + union { + __IOM uint32_t reg; /*!< system timer comp0 value high register */ + + struct { + __IOM uint32_t TIMER_TARGET0_HI : 20; /*!< timer taget0 high 20 bits */ + uint32_t : 12; + } bit; + } TARGET0_HI; + + union { + __IOM uint32_t reg; /*!< system timer comp0 value low register */ + + struct { + __IOM uint32_t TIMER_TARGET0_LO : 32; /*!< timer taget0 low 32 bits */ + } bit; + } TARGET0_LO; + + union { + __IOM uint32_t reg; /*!< system timer comp1 value high register */ + + struct { + __IOM uint32_t TIMER_TARGET1_HI : 20; /*!< timer taget1 high 20 bits */ + uint32_t : 12; + } bit; + } TARGET1_HI; + + union { + __IOM uint32_t reg; /*!< system timer comp1 value low register */ + + struct { + __IOM uint32_t TIMER_TARGET1_LO : 32; /*!< timer taget1 low 32 bits */ + } bit; + } TARGET1_LO; + + union { + __IOM uint32_t reg; /*!< system timer comp2 value high register */ + + struct { + __IOM uint32_t TIMER_TARGET2_HI : 20; /*!< timer taget2 high 20 bits */ + uint32_t : 12; + } bit; + } TARGET2_HI; + + union { + __IOM uint32_t reg; /*!< system timer comp2 value low register */ + + struct { + __IOM uint32_t TIMER_TARGET2_LO : 32; /*!< timer taget2 low 32 bits */ + } bit; + } TARGET2_LO; + + union { + __IOM uint32_t reg; /*!< system timer comp0 target mode register */ + + struct { + __IOM uint32_t TARGET0_PERIOD : 26; /*!< target0 period */ + uint32_t : 4; + __IOM uint32_t TARGET0_PERIOD_MODE : 1; /*!< Set target0 to period mode */ + __IOM uint32_t TARGET0_TIMER_UNIT_SEL : 1;/*!< select which unit to compare */ + } bit; + } TARGET0_CONF; + + union { + __IOM uint32_t reg; /*!< system timer comp1 target mode register */ + + struct { + __IOM uint32_t TARGET1_PERIOD : 26; /*!< target1 period */ + uint32_t : 4; + __IOM uint32_t TARGET1_PERIOD_MODE : 1; /*!< Set target1 to period mode */ + __IOM uint32_t TARGET1_TIMER_UNIT_SEL : 1;/*!< select which unit to compare */ + } bit; + } TARGET1_CONF; + + union { + __IOM uint32_t reg; /*!< system timer comp2 target mode register */ + + struct { + __IOM uint32_t TARGET2_PERIOD : 26; /*!< target2 period */ + uint32_t : 4; + __IOM uint32_t TARGET2_PERIOD_MODE : 1; /*!< Set target2 to period mode */ + __IOM uint32_t TARGET2_TIMER_UNIT_SEL : 1;/*!< select which unit to compare */ + } bit; + } TARGET2_CONF; + + union { + __IOM uint32_t reg; /*!< system timer unit0 value high register */ + + struct { + __IM uint32_t TIMER_UNIT0_VALUE_HI : 20; /*!< timer read value high 20bits */ + uint32_t : 12; + } bit; + } UNIT0_VALUE_HI; + + union { + __IOM uint32_t reg; /*!< system timer unit0 value low register */ + + struct { + __IM uint32_t TIMER_UNIT0_VALUE_LO : 32; /*!< timer read value low 32bits */ + } bit; + } UNIT0_VALUE_LO; + + union { + __IOM uint32_t reg; /*!< system timer unit1 value high register */ + + struct { + __IM uint32_t TIMER_UNIT1_VALUE_HI : 20; /*!< timer read value high 20bits */ + uint32_t : 12; + } bit; + } UNIT1_VALUE_HI; + + union { + __IOM uint32_t reg; /*!< system timer unit1 value low register */ + + struct { + __IM uint32_t TIMER_UNIT1_VALUE_LO : 32; /*!< timer read value low 32bits */ + } bit; + } UNIT1_VALUE_LO; + + union { + __IOM uint32_t reg; /*!< system timer comp0 conf sync register */ + + struct { + __OM uint32_t TIMER_COMP0_LOAD : 1; /*!< timer comp0 sync enable signal */ + uint32_t : 31; + } bit; + } COMP0_LOAD; + + union { + __IOM uint32_t reg; /*!< system timer comp1 conf sync register */ + + struct { + __OM uint32_t TIMER_COMP1_LOAD : 1; /*!< timer comp1 sync enable signal */ + uint32_t : 31; + } bit; + } COMP1_LOAD; + + union { + __IOM uint32_t reg; /*!< system timer comp2 conf sync register */ + + struct { + __OM uint32_t TIMER_COMP2_LOAD : 1; /*!< timer comp2 sync enable signal */ + uint32_t : 31; + } bit; + } COMP2_LOAD; + + union { + __IOM uint32_t reg; /*!< system timer unit0 conf sync register */ + + struct { + __OM uint32_t TIMER_UNIT0_LOAD : 1; /*!< timer unit0 sync enable signal */ + uint32_t : 31; + } bit; + } UNIT0_LOAD; + + union { + __IOM uint32_t reg; /*!< system timer unit1 conf sync register */ + + struct { + __OM uint32_t TIMER_UNIT1_LOAD : 1; /*!< timer unit1 sync enable signal */ + uint32_t : 31; + } bit; + } UNIT1_LOAD; + + union { + __IOM uint32_t reg; /*!< systimer interrupt enable register */ + + struct { + __IOM uint32_t TARGET0_INT_ENA : 1; /*!< interupt0 enable */ + __IOM uint32_t TARGET1_INT_ENA : 1; /*!< interupt1 enable */ + __IOM uint32_t TARGET2_INT_ENA : 1; /*!< interupt2 enable */ + uint32_t : 29; + } bit; + } INT_ENA; + + union { + __IOM uint32_t reg; /*!< systimer interrupt raw register */ + + struct { + __IOM uint32_t TARGET0_INT_RAW : 1; /*!< interupt0 raw */ + __IOM uint32_t TARGET1_INT_RAW : 1; /*!< interupt1 raw */ + __IOM uint32_t TARGET2_INT_RAW : 1; /*!< interupt2 raw */ + uint32_t : 29; + } bit; + } INT_RAW; + + union { + __IOM uint32_t reg; /*!< systimer interrupt clear register */ + + struct { + __OM uint32_t TARGET0_INT_CLR : 1; /*!< interupt0 clear */ + __OM uint32_t TARGET1_INT_CLR : 1; /*!< interupt1 clear */ + __OM uint32_t TARGET2_INT_CLR : 1; /*!< interupt2 clear */ + uint32_t : 29; + } bit; + } INT_CLR; + + union { + __IOM uint32_t reg; /*!< systimer interrupt status register */ + + struct { + __IM uint32_t TARGET0_INT_ST : 1; /*!< interupt0 status */ + __IM uint32_t TARGET1_INT_ST : 1; /*!< interupt1 status */ + __IM uint32_t TARGET2_INT_ST : 1; /*!< interupt2 status */ + uint32_t : 29; + } bit; + } INT_ST; + + union { + __IOM uint32_t reg; /*!< system timer comp0 actual target value low register */ + + struct { + __IM uint32_t TARGET0_LO_RO : 32; /*!< actual target value value low 32bits */ + } bit; + } REAL_TARGET0_LO; + + union { + __IOM uint32_t reg; /*!< system timer comp0 actual target value high register */ + + struct { + __IM uint32_t TARGET0_HI_RO : 20; /*!< actual target value value high 20bits */ + uint32_t : 12; + } bit; + } REAL_TARGET0_HI; + + union { + __IOM uint32_t reg; /*!< system timer comp1 actual target value low register */ + + struct { + __IM uint32_t TARGET1_LO_RO : 32; /*!< actual target value value low 32bits */ + } bit; + } REAL_TARGET1_LO; + + union { + __IOM uint32_t reg; /*!< system timer comp1 actual target value high register */ + + struct { + __IM uint32_t TARGET1_HI_RO : 20; /*!< actual target value value high 20bits */ + uint32_t : 12; + } bit; + } REAL_TARGET1_HI; + + union { + __IOM uint32_t reg; /*!< system timer comp2 actual target value low register */ + + struct { + __IM uint32_t TARGET2_LO_RO : 32; /*!< actual target value value low 32bits */ + } bit; + } REAL_TARGET2_LO; + + union { + __IOM uint32_t reg; /*!< system timer comp2 actual target value high register */ + + struct { + __IM uint32_t TARGET2_HI_RO : 20; /*!< actual target value value high 20bits */ + uint32_t : 12; + } bit; + } REAL_TARGET2_HI; + __IM uint32_t RESERVED[28]; + + union { + __IOM uint32_t reg; /*!< system timer version control register */ + + struct { + __IOM uint32_t DATE : 32; /*!< systimer register version */ + } bit; + } DATE; +} SYSTIMER_Type; /*!< Size = 256 (0x100) */ + + + +/* =========================================================================================================================== */ +/* ================ TIMG0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Timer Group 0 (TIMG0) + */ + +typedef struct { /*!< TIMG0 Structure */ + __IM uint32_t RESERVED[18]; + + union { + __IOM uint32_t reg; /*!< Watchdog timer configuration register */ + + struct { + uint32_t : 12; + __IOM uint32_t WDT_APPCPU_RESET_EN : 1; /*!< WDT reset CPU enable. */ + __IOM uint32_t WDT_PROCPU_RESET_EN : 1; /*!< WDT reset CPU enable. */ + __IOM uint32_t WDT_FLASHBOOT_MOD_EN : 1; /*!< When set, Flash boot protection is enabled. */ + __IOM uint32_t WDT_SYS_RESET_LENGTH : 3; /*!< System reset signal length selection. 0: 100 ns, 1: 200 ns,2: + 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: + 3.2 us. */ + __IOM uint32_t WDT_CPU_RESET_LENGTH : 3; /*!< CPU reset signal length selection. 0: 100 ns, 1: 200 ns,2: 300 + ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 + us. */ + __IOM uint32_t WDT_USE_XTAL : 1; /*!< choose WDT clock:0-apb_clk, 1-xtal_clk. */ + __OM uint32_t WDT_CONF_UPDATE_EN : 1; /*!< update the WDT configuration registers */ + __IOM uint32_t WDT_STG3 : 2; /*!< Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: + reset system. */ + __IOM uint32_t WDT_STG2 : 2; /*!< Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: + reset system. */ + __IOM uint32_t WDT_STG1 : 2; /*!< Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: + reset system. */ + __IOM uint32_t WDT_STG0 : 2; /*!< Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: + reset system. */ + __IOM uint32_t WDT_EN : 1; /*!< When set, MWDT is enabled. */ + } bit; + } WDTCONFIG0; + + union { + __IOM uint32_t reg; /*!< Watchdog timer prescaler register */ + + struct { + __OM uint32_t WDT_DIVCNT_RST : 1; /*!< When set, WDT 's clock divider counter will be reset. */ + uint32_t : 15; + __IOM uint32_t WDT_CLK_PRESCALE : 16; /*!< MWDT clock prescaler value. MWDT clock period = 12.5 ns *TIMG_WDT_CLK_PRESCALE + */ + } bit; + } WDTCONFIG1; + + union { + __IOM uint32_t reg; /*!< Watchdog timer stage 0 timeout value */ + + struct { + __IOM uint32_t WDT_STG0_HOLD : 32; /*!< Stage 0 timeout value, in MWDT clock cycles. */ + } bit; + } WDTCONFIG2; + + union { + __IOM uint32_t reg; /*!< Watchdog timer stage 1 timeout value */ + + struct { + __IOM uint32_t WDT_STG1_HOLD : 32; /*!< Stage 1 timeout value, in MWDT clock cycles. */ + } bit; + } WDTCONFIG3; + + union { + __IOM uint32_t reg; /*!< Watchdog timer stage 2 timeout value */ + + struct { + __IOM uint32_t WDT_STG2_HOLD : 32; /*!< Stage 2 timeout value, in MWDT clock cycles. */ + } bit; + } WDTCONFIG4; + + union { + __IOM uint32_t reg; /*!< Watchdog timer stage 3 timeout value */ + + struct { + __IOM uint32_t WDT_STG3_HOLD : 32; /*!< Stage 3 timeout value, in MWDT clock cycles. */ + } bit; + } WDTCONFIG5; + + union { + __IOM uint32_t reg; /*!< Write to feed the watchdog timer */ + + struct { + __OM uint32_t WDT_FEED : 32; /*!< Write any value to feed the MWDT. (WO) */ + } bit; + } WDTFEED; + + union { + __IOM uint32_t reg; /*!< Watchdog write protect register */ + + struct { + __IOM uint32_t WDT_WKEY : 32; /*!< If the register contains a different value than its reset value, + writeprotection is enabled. */ + } bit; + } WDTWPROTECT; + + union { + __IOM uint32_t reg; /*!< RTC calibration configure register */ + + struct { + uint32_t : 12; + __IOM uint32_t RTC_CALI_START_CYCLING : 1;/*!< 0: one-shot frequency calculation,1: periodic frequency calculation, */ + __IOM uint32_t RTC_CALI_CLK_SEL : 2; /*!< 0:rtc slow clock. 1:clk_8m, 2:xtal_32k. */ + __IM uint32_t RTC_CALI_RDY : 1; /*!< indicate one-shot frequency calculation is done. */ + __IOM uint32_t RTC_CALI_MAX : 15; /*!< Configure the time to calculate RTC slow clock's frequency. */ + __IOM uint32_t RTC_CALI_START : 1; /*!< Set this bit to start one-shot frequency calculation. */ + } bit; + } RTCCALICFG; + + union { + __IOM uint32_t reg; /*!< RTC calibration configure1 register */ + + struct { + __IM uint32_t RTC_CALI_CYCLING_DATA_VLD : 1;/*!< indicate periodic frequency calculation is done. */ + uint32_t : 6; + __IM uint32_t RTC_CALI_VALUE : 25; /*!< When one-shot or periodic frequency calculation is done, read + this value to calculate RTC slow clock's frequency. */ + } bit; + } RTCCALICFG1; + + union { + __IOM uint32_t reg; /*!< Interrupt enable bits */ + + struct { + __IOM uint32_t T0_INT_ENA : 1; /*!< The interrupt enable bit for the TIMG_T0_INT interrupt. */ + __IOM uint32_t T1_INT_ENA : 1; /*!< The interrupt enable bit for the TIMG_T1_INT interrupt. */ + __IOM uint32_t WDT_INT_ENA : 1; /*!< The interrupt enable bit for the TIMG_WDT_INT interrupt. */ + uint32_t : 29; + } bit; + } INT_ENA_TIMERS; + + union { + __IOM uint32_t reg; /*!< Raw interrupt status */ + + struct { + __IM uint32_t T0_INT_RAW : 1; /*!< The raw interrupt status bit for the TIMG_T0_INT interrupt. */ + __IM uint32_t T1_INT_RAW : 1; /*!< The raw interrupt status bit for the TIMG_T1_INT interrupt. */ + __IM uint32_t WDT_INT_RAW : 1; /*!< The raw interrupt status bit for the TIMG_WDT_INT interrupt. */ + uint32_t : 29; + } bit; + } INT_RAW_TIMERS; + + union { + __IOM uint32_t reg; /*!< Masked interrupt status */ + + struct { + __IM uint32_t T0_INT_ST : 1; /*!< The masked interrupt status bit for the TIMG_T0_INT interrupt. */ + __IM uint32_t T1_INT_ST : 1; /*!< The masked interrupt status bit for the TIMG_T1_INT interrupt. */ + __IM uint32_t WDT_INT_ST : 1; /*!< The masked interrupt status bit for the TIMG_WDT_INT interrupt. */ + uint32_t : 29; + } bit; + } INT_ST_TIMERS; + + union { + __IOM uint32_t reg; /*!< Interrupt clear bits */ + + struct { + __OM uint32_t T0_INT_CLR : 1; /*!< Set this bit to clear the TIMG_T0_INT interrupt. */ + __OM uint32_t T1_INT_CLR : 1; /*!< Set this bit to clear the TIMG_T1_INT interrupt. */ + __OM uint32_t WDT_INT_CLR : 1; /*!< Set this bit to clear the TIMG_WDT_INT interrupt. */ + uint32_t : 29; + } bit; + } INT_CLR_TIMERS; + + union { + __IOM uint32_t reg; /*!< Timer group calibration register */ + + struct { + __IM uint32_t RTC_CALI_TIMEOUT : 1; /*!< RTC calibration timeout indicator */ + uint32_t : 2; + __IOM uint32_t RTC_CALI_TIMEOUT_RST_CNT : 4;/*!< Cycles that release calibration timeout reset */ + __IOM uint32_t RTC_CALI_TIMEOUT_THRES : 25;/*!< Threshold value for the RTC calibration timer. If the calibration + timer's value exceeds this threshold, a timeout is triggered. */ + } bit; + } RTCCALICFG2; + __IM uint32_t RESERVED1[29]; + + union { + __IOM uint32_t reg; /*!< Timer version control register */ + + struct { + __IOM uint32_t NTIMGS_DATE : 28; /*!< Timer version control register */ + uint32_t : 4; + } bit; + } NTIMERS_DATE; + + union { + __IOM uint32_t reg; /*!< Timer group clock gate register */ + + struct { + uint32_t : 28; + __IOM uint32_t ETM_EN : 1; /*!< enable timer's etm task and event */ + __IOM uint32_t WDT_CLK_IS_ACTIVE : 1; /*!< enable WDT's clock */ + __IOM uint32_t TIMER_CLK_IS_ACTIVE : 1; /*!< enable Timer 30's clock */ + __IOM uint32_t CLK_EN : 1; /*!< Register clock gate signal. 1: Registers can be read and written + to by software. 0: Registers can not be read or written + to by software. */ + } bit; + } REGCLK; +} TIMG0_Type; /*!< Size = 256 (0x100) */ + + + +/* =========================================================================================================================== */ +/* ================ TRACE0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief TRACE0 Peripheral (TRACE0) + */ + +typedef struct { /*!< TRACE0 Structure */ + + union { + __IOM uint32_t reg; /*!< mem start addr */ + + struct { + __IOM uint32_t MEM_START_ADDR : 32; /*!< The start address of trace memory */ + } bit; + } MEM_START_ADDR; + + union { + __IOM uint32_t reg; /*!< mem end addr */ + + struct { + __IOM uint32_t MEM_END_ADDR : 32; /*!< The end address of trace memory */ + } bit; + } MEM_END_ADDR; + + union { + __IOM uint32_t reg; /*!< mem current addr */ + + struct { + __IM uint32_t MEM_CURRENT_ADDR : 32; /*!< current_mem_addr,indicate that next writing addr */ + } bit; + } MEM_CURRENT_ADDR; + + union { + __IOM uint32_t reg; /*!< mem addr update */ + + struct { + __OM uint32_t MEM_CURRENT_ADDR_UPDATE : 1;/*!< when set, the will \hyperref[fielddesc:TRACEMEMCURRENTADDR]{TRACE_MEM_CURRENT_ + DDR} update to \hyperref[fielddesc:TRACEMEMSTARTADDR]{TRACE_MEM_START_ADD + }. */ + uint32_t : 31; + } bit; + } MEM_ADDR_UPDATE; + + union { + __IOM uint32_t reg; /*!< fifo status register */ + + struct { + __IM uint32_t FIFO_EMPTY : 1; /*!< Represent whether the fifo is empty. \\1: empty \\0: not empty */ + __IM uint32_t WORK_STATUS : 2; /*!< Represent trace work status: \\0: idle state \\1: working state\\ + 2: wait state due to hart halted or havereset \\3: lost + state */ + uint32_t : 29; + } bit; + } FIFO_STATUS; + + union { + __IOM uint32_t reg; /*!< interrupt enable register */ + + struct { + __IOM uint32_t FIFO_OVERFLOW_INTR_ENA : 1;/*!< Set 1 enable fifo_overflow interrupt */ + __IOM uint32_t MEM_FULL_INTR_ENA : 1; /*!< Set 1 enable mem_full interrupt */ + uint32_t : 30; + } bit; + } INTR_ENA; + + union { + __IOM uint32_t reg; /*!< interrupt status register */ + + struct { + __IM uint32_t FIFO_OVERFLOW_INTR_RAW : 1;/*!< fifo_overflow interrupt status */ + __IM uint32_t MEM_FULL_INTR_RAW : 1; /*!< mem_full interrupt status */ + uint32_t : 30; + } bit; + } INTR_RAW; + + union { + __IOM uint32_t reg; /*!< interrupt clear register */ + + struct { + __OM uint32_t FIFO_OVERFLOW_INTR_CLR : 1;/*!< Set 1 clear fifo overflow interrupt */ + __OM uint32_t MEM_FULL_INTR_CLR : 1; /*!< Set 1 clear mem full interrupt */ + uint32_t : 30; + } bit; + } INTR_CLR; + + union { + __IOM uint32_t reg; /*!< trigger register */ + + struct { + __OM uint32_t ON : 1; /*!< Configure whether or not start trace.\\1: start trace \\0: invalid\\ */ + __OM uint32_t OFF : 1; /*!< Configure whether or not stop trace.\\1: stop trace \\0: invalid\\ */ + __IOM uint32_t MEM_LOOP : 1; /*!< Configure memory loop mode. \\1: trace will loop wrtie trace_mem. + \\0: when mem_current_addr at mem_end_addr, it will stop + at the mem_end_addr\\ */ + __IOM uint32_t RESTART_ENA : 1; /*!< Configure whether or not enable auto-restart.\\1: enable\\0: + disable\\ */ + uint32_t : 28; + } bit; + } TRIGGER; + + union { + __IOM uint32_t reg; /*!< trace configuration register */ + + struct { + __IOM uint32_t DM_TRIGGER_ENA : 1; /*!< Configure whether or not enable cpu trigger action.\\1: enable\\0:disable\\ */ + __IOM uint32_t RESET_ENA : 1; /*!< Configure whether or not enable trace cpu haverest, when enabeld, + if cpu have reset, the encoder will output a packet to + report the address of the last instruction, and upon reset + deassertion, the encoder start again.\\1: enabeld\\0: disabled\\ */ + __IOM uint32_t HALT_ENA : 1; /*!< Configure whether or not enable trace cpu is halted, when enabeld, + if the cpu halted, the encoder will output a packet to + report the address of the last instruction, and upon halted + deassertion, the encoder start again.When disabled, encoder + will not report the last address before halted and first + address after halted, cpu halted information will not be + tracked. \\1: enabeld\\0: disabled\\ */ + __IOM uint32_t STALL_ENA : 1; /*!< Configure whether or not enable stall cpu. When enabled, when + the fifo almost full, the cpu will be stalled until the + packets is able to write to fifo.\\1: enabled.\\0: disabled\\ */ + __IOM uint32_t FULL_ADDRESS : 1; /*!< Configure whether or not enable full-address mode.\\1: full + address mode.\\0: delta address mode\\ */ + __IOM uint32_t IMPLICIT_EXCEPT : 1; /*!< Configure whether or not enabel implicit exception mode. When + enabled,, do not sent exception address, only exception + cause in exception packets.\\1: enabled\\0: disabled\\ */ + uint32_t : 26; + } bit; + } CONFIG; + + union { + __IOM uint32_t reg; /*!< filter control register */ + + struct { + __IOM uint32_t FILTER_EN : 1; /*!< Configure whether or not enable filter unit. \\1: enable filter.\\ + 0: always match */ + __IOM uint32_t MATCH_COMP : 1; /*!< when set, the comparator must be high in order for the filter + to match */ + __IOM uint32_t MATCH_PRIVILEGE : 1; /*!< when set, match privilege levels specified by \hyperref[fielddesc:TRACEMATCHCH + ICEPRIVILEGE]{TRACE_MATCH_CHOICE_PRIVILEGE}. */ + __IOM uint32_t MATCH_ECAUSE : 1; /*!< when set, start matching from exception cause codes specified + by \hyperref[fielddesc:TRACEMATCHCHOICEECAUSE]{TRACE_MATCH_CHOICE_ECAUSE} + and stop matching upon return from the 1st matching exception. */ + __IOM uint32_t MATCH_INTERRUPT : 1; /*!< when set, start matching from a trap with the interrupt level + codes specified by \hyperref[fielddesc:TRACEMATCHVALUEINTERRUPT]{TRACE_MA + CH_VALUE_INTERRUPT}, and stop matching upon return from + the 1st matching trap. */ + uint32_t : 27; + } bit; + } FILTER_CONTROL; + + union { + __IOM uint32_t reg; /*!< filter match control register */ + + struct { + __IOM uint32_t MATCH_CHOICE_PRIVILEGE : 1;/*!< Select match which privilege level when \hyperref[fielddesc:TRACEMATCHPRIVILEG + ]{TRACE_MATCH_PRIVILEGE} is set. \\1: machine mode. \\0: + user mode */ + __IOM uint32_t MATCH_VALUE_INTERRUPT : 1; /*!< Select which match which itype when \hyperref[fielddesc:TRACEMATCHINTERRUPT]{T + ACE_MATCH_INTERRUP} is set. \\1: match itype of 2. \\0: + match itype or 1. */ + __IOM uint32_t MATCH_CHOICE_ECAUSE : 6; /*!< specified which ecause matched. */ + uint32_t : 24; + } bit; + } FILTER_MATCH_CONTROL; + + union { + __IOM uint32_t reg; /*!< filter comparator match control register */ + + struct { + __IOM uint32_t P_INPUT : 1; /*!< Determines which input to compare against the primary comparator, + \\0: iaddr, \\1: tval. */ + uint32_t : 1; + __IOM uint32_t P_FUNCTION : 3; /*!< Select the primary comparator function. \\0: equal, \\1: not + equal, \\2: less than, \\3: less than or equal, \\4: greater + than, \\5: greater than or equal, \\other: always match */ + __IOM uint32_t P_NOTIFY : 1; /*!< Generate a trace packet explicitly reporting the address that + cause the primary match */ + uint32_t : 2; + __IOM uint32_t S_INPUT : 1; /*!< Determines which input to compare against the secondary comparator, + \\0: iaddr, \\1: tval. */ + uint32_t : 1; + __IOM uint32_t S_FUNCTION : 3; /*!< Select the secondary comparator function. \\0: equal, \\1: not + equal, \\2: less than, \\3: less than or equal, \\4: greater + than, \\5: greater than or equal, \\other: always match */ + __IOM uint32_t S_NOTIFY : 1; /*!< Generate a trace packet explicitly reporting the address that + cause the secondary match */ + uint32_t : 2; + __IOM uint32_t MATCH_MODE : 2; /*!< 0: only primary matches, \\1: primary and secondary comparator + both matches(P\&\&S),\\ 2:either primary or secondary comparator + matches !(P\&\&S), \\3: set when primary matches and continue + to match until after secondary comparator matches */ + uint32_t : 14; + } bit; + } FILTER_COMPARATOR_CONTROL; + + union { + __IOM uint32_t reg; /*!< primary comparator match value */ + + struct { + __IOM uint32_t P_MATCH : 32; /*!< primary comparator match value */ + } bit; + } FILTER_P_COMPARATOR_MATCH; + + union { + __IOM uint32_t reg; /*!< secondary comparator match value */ + + struct { + __IOM uint32_t S_MATCH : 32; /*!< secondary comparator match value */ + } bit; + } FILTER_S_COMPARATOR_MATCH; + + union { + __IOM uint32_t reg; /*!< resync configuration register */ + + struct { + __IOM uint32_t RESYNC_PROLONGED : 24; /*!< count number, when count to this value, send a sync package */ + __IOM uint32_t RESYNC_MODE : 2; /*!< resyc mode sel: \\0: off, \\2: cycle count \\3: package num + count */ + uint32_t : 6; + } bit; + } RESYNC_PROLONGED; + + union { + __IOM uint32_t reg; /*!< AHB config register */ + + struct { + __IOM uint32_t HBURST : 3; /*!< set hburst */ + __IOM uint32_t MAX_INCR : 3; /*!< set max continuous access for incr mode */ + uint32_t : 26; + } bit; + } AHB_CONFIG; + + union { + __IOM uint32_t reg; /*!< Clock gate control register */ + + struct { + __IOM uint32_t CLK_EN : 1; /*!< The bit is used to enable clock gate when access all registers + in this module. */ + uint32_t : 31; + } bit; + } CLOCK_GATE; + __IM uint32_t RESERVED[237]; + + union { + __IOM uint32_t reg; /*!< Version control register */ + + struct { + __IOM uint32_t DATE : 28; /*!< version control register. Note that this default value stored + is the latest date when the hardware logic was updated. */ + uint32_t : 4; + } bit; + } DATE; +} TRACE0_Type; /*!< Size = 1024 (0x400) */ + + + +/* =========================================================================================================================== */ +/* ================ LP_TSENS ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Low-power Temperature Sensor (LP_TSENS) + */ + +typedef struct { /*!< LP_TSENS Structure */ + + union { + __IOM uint32_t reg; /*!< Tsens configuration. */ + + struct { + __IM uint32_t OUT : 8; /*!< Temperature sensor data out. */ + __IM uint32_t READY : 1; /*!< Indicate temperature sensor out ready. */ + __IOM uint32_t SAMPLE_EN : 1; /*!< Enable sample signal for wakeup module. */ + __IOM uint32_t WAKEUP_MASK : 1; /*!< Wake up signal mask. */ + uint32_t : 1; + __IOM uint32_t INT_EN : 1; /*!< Enable temperature sensor to send out interrupt. */ + __IOM uint32_t IN_INV : 1; /*!< Invert temperature sensor data. */ + __IOM uint32_t CLK_DIV : 8; /*!< Temperature sensor clock divider. */ + __IOM uint32_t POWER_UP : 1; /*!< Temperature sensor power up. */ + __IOM uint32_t POWER_UP_FORCE : 1; /*!< 1: dump out & power up controlled by SW, 0: by FSM. */ + uint32_t : 8; + } bit; + } CTRL; + + union { + __IOM uint32_t reg; /*!< Tsens configuration. */ + + struct { + __IOM uint32_t XPD_WAIT : 12; /*!< N/A */ + __IOM uint32_t XPD_FORCE : 2; /*!< N/A */ + __IOM uint32_t CLK_INV : 1; /*!< N/A */ + uint32_t : 17; + } bit; + } CTRL2; + + union { + __IOM uint32_t reg; /*!< Tsens interrupt raw registers. */ + + struct { + __IOM uint32_t COCPU_TSENS_WAKE_INT_RAW : 1;/*!< Tsens wakeup interrupt raw. */ + uint32_t : 31; + } bit; + } INT_RAW; + + union { + __IOM uint32_t reg; /*!< Tsens interrupt status registers. */ + + struct { + __IM uint32_t COCPU_TSENS_WAKE_INT_ST : 1;/*!< Tsens wakeup interrupt status. */ + uint32_t : 31; + } bit; + } INT_ST; + + union { + __IOM uint32_t reg; /*!< Tsens interrupt enable registers. */ + + struct { + __IOM uint32_t COCPU_TSENS_WAKE_INT_ENA : 1;/*!< Tsens wakeup interrupt enable. */ + uint32_t : 31; + } bit; + } INT_ENA; + + union { + __IOM uint32_t reg; /*!< Tsens interrupt clear registers. */ + + struct { + __OM uint32_t COCPU_TSENS_WAKE_INT_CLR : 1;/*!< Tsens wakeup interrupt clear. */ + uint32_t : 31; + } bit; + } INT_CLR; + + union { + __IOM uint32_t reg; /*!< Tsens regbank configuration registers. */ + + struct { + __IOM uint32_t CLK_EN : 1; /*!< Tsens regbank clock gating enable. */ + uint32_t : 31; + } bit; + } CLK_CONF; + + union { + __IOM uint32_t reg; /*!< Tsens wakeup interrupt enable assert. */ + + struct { + __OM uint32_t COCPU_TSENS_WAKE_INT_ENA_W1TS : 1;/*!< Write 1 to this field to assert interrupt enable. */ + uint32_t : 31; + } bit; + } INT_ENA_W1TS; + + union { + __IOM uint32_t reg; /*!< Tsens wakeup interrupt enable deassert. */ + + struct { + __OM uint32_t COCPU_TSENS_WAKE_INT_ENA_W1TC : 1;/*!< Write 1 to this field to deassert interrupt enable. */ + uint32_t : 31; + } bit; + } INT_ENA_W1TC; + + union { + __IOM uint32_t reg; /*!< Tsens wakeup control registers. */ + + struct { + __IOM uint32_t WAKEUP_TH_LOW : 8; /*!< Lower threshold. */ + uint32_t : 6; + __IOM uint32_t WAKEUP_TH_HIGH : 8; /*!< Upper threshold. */ + uint32_t : 7; + __IM uint32_t WAKEUP_OVER_UPPER_TH : 1; /*!< Indicates that this wakeup event arose from exceeding upper + threshold. */ + __IOM uint32_t WAKEUP_EN : 1; /*!< Tsens wakeup enable. */ + __IOM uint32_t WAKEUP_MODE : 1; /*!< 0:absolute value comparison mode. 1: relative value comparison + mode. */ + } bit; + } WAKEUP_CTRL; + + union { + __IOM uint32_t reg; /*!< Hardware automatic sampling control registers. */ + + struct { + __IOM uint32_t SAMPLE_RATE : 16; /*!< Hardware automatic sampling rate. */ + uint32_t : 16; + } bit; + } SAMPLE_RATE; + + union { + __IOM uint32_t reg; /*!< N/A */ + + struct { + __IOM uint32_t RND_ECO_LOW : 32; /*!< N/A */ + } bit; + } RND_ECO_LOW; + + union { + __IOM uint32_t reg; /*!< N/A */ + + struct { + __IOM uint32_t RND_ECO_HIGH : 32; /*!< N/A */ + } bit; + } RND_ECO_HIGH; + + union { + __IOM uint32_t reg; /*!< N/A */ + + struct { + __IOM uint32_t RND_ECO_EN : 1; /*!< N/A */ + __IM uint32_t RND_ECO_RESULT : 1; /*!< N/A */ + uint32_t : 30; + } bit; + } RND_ECO_CS; +} LP_TSENS_Type; /*!< Size = 56 (0x38) */ + + + +/* =========================================================================================================================== */ +/* ================ TWAI0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Two-Wire Automotive Interface (TWAI0) + */ + +typedef struct { /*!< TWAI0 Structure */ + + union { + __IOM uint32_t reg; /*!< TWAI mode register. */ + + struct { + __IOM uint32_t RESET_MODE : 1; /*!< 1: reset, detection of a set reset mode bit results in aborting + the current transmission/reception of a message and entering + the reset mode. 0: normal, on the '1-to-0' transition of + the reset mode bit, the TWAI controller returns to the + operating mode. */ + __IOM uint32_t LISTEN_ONLY_MODE : 1; /*!< 1: listen only, in this mode the TWAI controller would give + no acknowledge to the TWAI-bus, even if a message is received + successfully. The error counters are stopped at the current + value. 0: normal. */ + __IOM uint32_t SELF_TEST_MODE : 1; /*!< 1: self test, in this mode a full node test is possible without + any other active node on the bus using the self reception + request command. The TWAI controller will perform a successful + transmission, even if there is no acknowledge received. + 0: normal, an acknowledge is required for successful transmission. */ + __IOM uint32_t ACCEPTANCE_FILTER_MODE : 1;/*!< 1:single, the single acceptance filter option is enabled (one + filter with the length of 32 bit is active). 0:dual, the + dual acceptance filter option is enabled (two filters, + each with the length of 16 bit are active). */ + uint32_t : 28; + } bit; + } MODE; + + union { + __IOM uint32_t reg; /*!< TWAI command register. */ + + struct { + __OM uint32_t TX_REQUEST : 1; /*!< 1: present, a message shall be transmitted. 0: absent */ + __OM uint32_t ABORT_TX : 1; /*!< 1: present, if not already in progress, a pending transmission + request is cancelled. 0: absent */ + __OM uint32_t RELEASE_BUFFER : 1; /*!< 1: released, the receive buffer, representing the message memory + space in the RXFIFO is released. 0: no action */ + __OM uint32_t CLEAR_DATA_OVERRUN : 1; /*!< 1: clear, the data overrun status bit is cleared. 0: no action. */ + __OM uint32_t SELF_RX_REQUEST : 1; /*!< 1: present, a message shall be transmitted and received simultaneously. + 0: absent. */ + uint32_t : 27; + } bit; + } CMD; + + union { + __IOM uint32_t reg; /*!< TWAI status register. */ + + struct { + __IM uint32_t RECEIVE_BUFFER : 1; /*!< 1: full, one or more complete messages are available in the + RXFIFO. 0: empty, no message is available */ + __IM uint32_t OVERRUN : 1; /*!< 1: overrun, a message was lost because there was not enough + space for that message in the RXFIFO. 0: absent, no data + overrun has occurred since the last clear data overrun + command was given */ + __IM uint32_t TRANSMIT_BUFFER : 1; /*!< 1: released, the CPU may write a message into the transmit buffer. + 0: locked, the CPU cannot access the transmit buffer, a + message is either waiting for transmission or is in the + process of being transmitted */ + __IM uint32_t TRANSMISSION_COMPLETE : 1; /*!< 1: complete, last requested transmission has been successfully + completed. 0: incomplete, previously requested transmission + is not yet completed */ + __IM uint32_t RECEIVE : 1; /*!< 1: receive, the TWAI controller is receiving a message. 0: idle */ + __IM uint32_t TRANSMIT : 1; /*!< 1: transmit, the TWAI controller is transmitting a message. + 0: idle */ + __IM uint32_t ERR : 1; /*!< 1: error, at least one of the error counters has reached or + exceeded the CPU warning limit defined by the Error Warning + Limit Register (EWLR). 0: ok, both error counters are below + the warning limit */ + __IM uint32_t NODE_BUS_OFF : 1; /*!< 1: bus-off, the TWAI controller is not involved in bus activities. + 0: bus-on, the TWAI controller is involved in bus activities */ + __IM uint32_t MISS : 1; /*!< 1: current message is destroyed because of FIFO overflow. */ + uint32_t : 23; + } bit; + } STATUS; + + union { + __IOM uint32_t reg; /*!< Interrupt signals' register. */ + + struct { + __IM uint32_t RECEIVE_INT_ST : 1; /*!< 1: this bit is set while the receive FIFO is not empty and the + RIE bit is set within the interrupt enable register. 0: + reset */ + __IM uint32_t TRANSMIT_INT_ST : 1; /*!< 1: this bit is set whenever the transmit buffer status changes + from '0-to-1' (released) and the TIE bit is set within + the interrupt enable register. 0: reset */ + __IM uint32_t ERR_WARNING_INT_ST : 1; /*!< 1: this bit is set on every change (set and clear) of either + the error status or bus status bits and the EIE bit is + set within the interrupt enable register. 0: reset */ + __IM uint32_t DATA_OVERRUN_INT_ST : 1; /*!< 1: this bit is set on a '0-to-1' transition of the data overrun + status bit and the DOIE bit is set within the interrupt + enable register. 0: reset */ + __IM uint32_t TS_COUNTER_OVFL_INT_ST : 1;/*!< 1: this bit is set then the timestamp counter reaches the maximum + value and overflow. */ + __IM uint32_t ERR_PASSIVE_INT_ST : 1; /*!< 1: this bit is set whenever the TWAI controller has reached + the error passive status (at least one error counter exceeds + the protocol-defined level of 127) or if the TWAI controller + is in the error passive status and enters the error active + status again and the EPIE bit is set within the interrupt + enable register. 0: reset */ + __IM uint32_t ARBITRATION_LOST_INT_ST : 1;/*!< 1: this bit is set when the TWAI controller lost the arbitration + and becomes a receiver and the ALIE bit is set within the + interrupt enable register. 0: reset */ + __IM uint32_t BUS_ERR_INT_ST : 1; /*!< 1: this bit is set when the TWAI controller detects an error + on the TWAI-bus and the BEIE bit is set within the interrupt + enable register. 0: reset */ + __IM uint32_t IDLE_INT_ST : 1; /*!< 1: this bit is set when the TWAI controller detects state of + TWAI become IDLE and this interrupt enable bit is set within + the interrupt enable register. 0: reset */ + uint32_t : 23; + } bit; + } INTERRUPT; + + union { + __IOM uint32_t reg; /*!< Interrupt enable register. */ + + struct { + __IOM uint32_t EXT_RECEIVE_INT_ENA : 1; /*!< 1: enabled, when the receive buffer status is 'full' the TWAI + controller requests the respective interrupt. 0: disable */ + __IOM uint32_t EXT_TRANSMIT_INT_ENA : 1; /*!< 1: enabled, when a message has been successfully transmitted + or the transmit buffer is accessible again (e.g. after + an abort transmission command), the TWAI controller requests + the respective interrupt. 0: disable */ + __IOM uint32_t EXT_ERR_WARNING_INT_ENA : 1;/*!< 1: enabled, if the error or bus status change (see status register. + Table 14), the TWAI controllerrequests the respective interrupt. + 0: disable */ + __IOM uint32_t EXT_DATA_OVERRUN_INT_ENA : 1;/*!< 1: enabled, if the data overrun status bit is set (see status + register. Table 14), the TWAI controllerrequests the respective + interrupt. 0: disable */ + __IOM uint32_t TS_COUNTER_OVFL_INT_ENA : 1;/*!< enable the timestamp counter overflow interrupt request. */ + __IOM uint32_t ERR_PASSIVE_INT_ENA : 1; /*!< 1: enabled, if the error status of the TWAI controller changes + from error active to error passive or vice versa, the respective + interrupt is requested. 0: disable */ + __IOM uint32_t ARBITRATION_LOST_INT_ENA : 1;/*!< 1: enabled, if the TWAI controller has lost arbitration, the + respective interrupt is requested. 0: disable */ + __IOM uint32_t BUS_ERR_INT_ENA : 1; /*!< 1: enabled, if an bus error has been detected, the TWAI controller + requests the respective interrupt. 0: disable */ + __IM uint32_t IDLE_INT_ENA : 1; /*!< 1: enabled, if state of TWAI become IDLE, the TWAI controller + requests the respective interrupt. 0: disable */ + uint32_t : 23; + } bit; + } INTERRUPT_ENABLE; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t reg; /*!< Bit timing configuration register 0. */ + + struct { + __IOM uint32_t BAUD_PRESC : 14; /*!< The period of the TWAI system clock is programmable and determines + the individual bit timing. Software has R/W permission + in reset mode and RO permission in operation mode. */ + __IOM uint32_t SYNC_JUMP_WIDTH : 2; /*!< The synchronization jump width defines the maximum number of + clock cycles a bit period may be shortened or lengthened. + Software has R/W permission in reset mode and RO in operation + mode. */ + uint32_t : 16; + } bit; + } BUS_TIMING_0; + + union { + __IOM uint32_t reg; /*!< Bit timing configuration register 1. */ + + struct { + __IOM uint32_t TIME_SEGMENT1 : 4; /*!< The number of clock cycles in TSEG1 per bit timing. Software + has R/W permission in reset mode and RO in operation mode. */ + __IOM uint32_t TIME_SEGMENT2 : 3; /*!< The number of clock cycles in TSEG2 per bit timing. Software + has R/W permission in reset mode and RO in operation mode. */ + __IOM uint32_t TIME_SAMPLING : 1; /*!< 1: triple, the bus is sampled three times. 0: single, the bus + is sampled once. Software has R/W permission in reset mode + and RO in operation mode. */ + uint32_t : 24; + } bit; + } BUS_TIMING_1; + __IM uint32_t RESERVED1[3]; + + union { + __IOM uint32_t reg; /*!< TWAI arbiter lost capture register. */ + + struct { + __IM uint32_t ARBITRATION_LOST_CAPTURE : 5;/*!< This register contains information about the bit position of + losing arbitration. */ + uint32_t : 27; + } bit; + } ARB_LOST_CAP; + + union { + __IOM uint32_t reg; /*!< TWAI error info capture register. */ + + struct { + __IM uint32_t ERR_CAPTURE_CODE_SEGMENT : 5;/*!< This register contains information about the location of errors + on the bus. */ + __IM uint32_t ERR_CAPTURE_CODE_DIRECTION : 1;/*!< 1: RX, error occurred during reception. 0: TX, error occurred + during transmission. */ + __IM uint32_t ERR_CAPTURE_CODE_TYPE : 2; /*!< 00: bit error. 01: form error. 10:stuff error. 11:other type + of error. */ + uint32_t : 24; + } bit; + } ERR_CODE_CAP; + + union { + __IOM uint32_t reg; /*!< TWAI error threshold configuration register. */ + + struct { + __IOM uint32_t ERR_WARNING_LIMIT : 8; /*!< The threshold that trigger error warning interrupt when this + interrupt is enabled. Software has R/W permission in reset + mode and RO in operation mode. */ + uint32_t : 24; + } bit; + } ERR_WARNING_LIMIT; + + union { + __IOM uint32_t reg; /*!< Rx error counter register. */ + + struct { + __IOM uint32_t RX_ERR_CNT : 8; /*!< The RX error counter register reflects the current value of + the transmit error counter. Software has R/W permission + in reset mode and RO in operation mode. */ + uint32_t : 24; + } bit; + } RX_ERR_CNT; + + union { + __IOM uint32_t reg; /*!< Tx error counter register. */ + + struct { + __IOM uint32_t TX_ERR_CNT : 8; /*!< The TX error counter register reflects the current value of + the transmit error counter. Software has R/W permission + in reset mode and RO in operation mode. */ + uint32_t : 24; + } bit; + } TX_ERR_CNT; + + union { + __IOM uint32_t reg; /*!< Data register 0. */ + + struct { + __IOM uint32_t DATA_0 : 8; /*!< In reset mode, it is acceptance code register 0 with R/W Permission. + In operation mode, when software initiate write operation, + it is tx data register 0 and when software initiate read + operation, it is rx data register 0. */ + uint32_t : 24; + } bit; + } DATA_0; + + union { + __IOM uint32_t reg; /*!< Data register 1. */ + + struct { + __IOM uint32_t DATA_1 : 8; /*!< In reset mode, it is acceptance code register 1 with R/W Permission. + In operation mode, when software initiate write operation, + it is tx data register 1 and when software initiate read + operation, it is rx data register 1. */ + uint32_t : 24; + } bit; + } DATA_1; + + union { + __IOM uint32_t reg; /*!< Data register 2. */ + + struct { + __IOM uint32_t DATA_2 : 8; /*!< In reset mode, it is acceptance code register 2 with R/W Permission. + In operation mode, when software initiate write operation, + it is tx data register 2 and when software initiate read + operation, it is rx data register 2. */ + uint32_t : 24; + } bit; + } DATA_2; + + union { + __IOM uint32_t reg; /*!< Data register 3. */ + + struct { + __IOM uint32_t DATA_3 : 8; /*!< In reset mode, it is acceptance code register 3 with R/W Permission. + In operation mode, when software initiate write operation, + it is tx data register 3 and when software initiate read + operation, it is rx data register 3. */ + uint32_t : 24; + } bit; + } DATA_3; + + union { + __IOM uint32_t reg; /*!< Data register 4. */ + + struct { + __IOM uint32_t DATA_4 : 8; /*!< In reset mode, it is acceptance mask register 0 with R/W Permission. + In operation mode, when software initiate write operation, + it is tx data register 4 and when software initiate read + operation, it is rx data register 4. */ + uint32_t : 24; + } bit; + } DATA_4; + + union { + __IOM uint32_t reg; /*!< Data register 5. */ + + struct { + __IOM uint32_t DATA_5 : 8; /*!< In reset mode, it is acceptance mask register 1 with R/W Permission. + In operation mode, when software initiate write operation, + it is tx data register 5 and when software initiate read + operation, it is rx data register 5. */ + uint32_t : 24; + } bit; + } DATA_5; + + union { + __IOM uint32_t reg; /*!< Data register 6. */ + + struct { + __IOM uint32_t DATA_6 : 8; /*!< In reset mode, it is acceptance mask register 2 with R/W Permission. + In operation mode, when software initiate write operation, + it is tx data register 6 and when software initiate read + operation, it is rx data register 6. */ + uint32_t : 24; + } bit; + } DATA_6; + + union { + __IOM uint32_t reg; /*!< Data register 7. */ + + struct { + __IOM uint32_t DATA_7 : 8; /*!< In reset mode, it is acceptance mask register 3 with R/W Permission. + In operation mode, when software initiate write operation, + it is tx data register 7 and when software initiate read + operation, it is rx data register 7. */ + uint32_t : 24; + } bit; + } DATA_7; + + union { + __IOM uint32_t reg; /*!< Data register 8. */ + + struct { + __IOM uint32_t DATA_8 : 8; /*!< In reset mode, reserved with RO. In operation mode, when software + initiate write operation, it is tx data register 8 and + when software initiate read operation, it is rx data register + 8. */ + uint32_t : 24; + } bit; + } DATA_8; + + union { + __IOM uint32_t reg; /*!< Data register 9. */ + + struct { + __IOM uint32_t DATA_9 : 8; /*!< In reset mode, reserved with RO. In operation mode, when software + initiate write operation, it is tx data register 9 and + when software initiate read operation, it is rx data register + 9. */ + uint32_t : 24; + } bit; + } DATA_9; + + union { + __IOM uint32_t reg; /*!< Data register 10. */ + + struct { + __IOM uint32_t DATA_10 : 8; /*!< In reset mode, reserved with RO. In operation mode, when software + initiate write operation, it is tx data register 10 and + when software initiate read operation, it is rx data register + 10. */ + uint32_t : 24; + } bit; + } DATA_10; + + union { + __IOM uint32_t reg; /*!< Data register 11. */ + + struct { + __IOM uint32_t DATA_11 : 8; /*!< In reset mode, reserved with RO. In operation mode, when software + initiate write operation, it is tx data register 11 and + when software initiate read operation, it is rx data register + 11. */ + uint32_t : 24; + } bit; + } DATA_11; + + union { + __IOM uint32_t reg; /*!< Data register 12. */ + + struct { + __IOM uint32_t DATA_12 : 8; /*!< In reset mode, reserved with RO. In operation mode, when software + initiate write operation, it is tx data register 12 and + when software initiate read operation, it is rx data register + 12. */ + uint32_t : 24; + } bit; + } DATA_12; + + union { + __IOM uint32_t reg; /*!< Received message counter register. */ + + struct { + __IM uint32_t RX_MESSAGE_COUNTER : 7; /*!< Reflects the number of messages available within the RXFIFO. + The value is incremented with each receive event and decremented + by the release receive buffer command. */ + uint32_t : 25; + } bit; + } RX_MESSAGE_COUNTER; + __IM uint32_t RESERVED2; + + union { + __IOM uint32_t reg; /*!< Clock divider register. */ + + struct { + __IOM uint32_t CD : 8; /*!< These bits are used to define the frequency at the external + CLKOUT pin. */ + __IOM uint32_t CLOCK_OFF : 1; /*!< 1: Disable the external CLKOUT pin. 0: Enable the external CLKOUT + pin. Software has R/W permission in reset mode and RO in + operation mode. */ + uint32_t : 23; + } bit; + } CLOCK_DIVIDER; + + union { + __IOM uint32_t reg; /*!< Software configure standby pin directly. */ + + struct { + __IOM uint32_t SW_STANDBY_EN : 1; /*!< Enable standby pin. */ + __IOM uint32_t SW_STANDBY_CLR : 1; /*!< Clear standby pin. */ + uint32_t : 30; + } bit; + } SW_STANDBY_CFG; + + union { + __IOM uint32_t reg; /*!< Hardware configure standby pin. */ + + struct { + __IOM uint32_t HW_STANDBY_EN : 1; /*!< Enable function that hardware control standby pin. */ + uint32_t : 31; + } bit; + } HW_CFG; + + union { + __IOM uint32_t reg; /*!< Configure standby counter. */ + + struct { + __IOM uint32_t STANDBY_WAIT_CNT : 32; /*!< Configure the number of cycles before standby becomes high when + TWAI_HW_STANDBY_EN is enabled. */ + } bit; + } HW_STANDBY_CNT; + + union { + __IOM uint32_t reg; /*!< Configure idle interrupt counter. */ + + struct { + __IOM uint32_t IDLE_INTR_CNT : 32; /*!< Configure the number of cycles before triggering idle interrupt. */ + } bit; + } IDLE_INTR_CNT; + + union { + __IOM uint32_t reg; /*!< ECO configuration register. */ + + struct { + __IOM uint32_t RDN_ENA : 1; /*!< Enable eco module. */ + __IM uint32_t RDN_RESULT : 1; /*!< Output of eco module. */ + uint32_t : 30; + } bit; + } ECO_CFG; + + union { + __IOM uint32_t reg; /*!< Timestamp data register */ + + struct { + __IM uint32_t TIMESTAMP_DATA : 32; /*!< Data of timestamp of a CAN frame. */ + } bit; + } TIMESTAMP_DATA; + + union { + __IOM uint32_t reg; /*!< Timestamp configuration register */ + + struct { + __IOM uint32_t TS_DIV_NUM : 16; /*!< Configures the clock division number of timestamp counter. */ + uint32_t : 16; + } bit; + } TIMESTAMP_PRESCALER; + + union { + __IOM uint32_t reg; /*!< Timestamp configuration register */ + + struct { + __IOM uint32_t TS_ENABLE : 1; /*!< enable the timestamp collection function. */ + uint32_t : 31; + } bit; + } TIMESTAMP_CFG; +} TWAI0_Type; /*!< Size = 160 (0xa0) */ + + + +/* =========================================================================================================================== */ +/* ================ UART0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief UART (Universal Asynchronous Receiver-Transmitter) Controller 0 (UART0) + */ + +typedef struct { /*!< UART0 Structure */ + + union { + __IOM uint32_t reg; /*!< FIFO data register */ + + struct { + __IM uint32_t RXFIFO_RD_BYTE : 8; /*!< UART 0 accesses FIFO via this register. */ + uint32_t : 24; + } bit; + } FIFO; + + union { + __IOM uint32_t reg; /*!< Raw interrupt status */ + + struct { + __IOM uint32_t RXFIFO_FULL_INT_RAW : 1; /*!< This interrupt raw bit turns to high level when receiver receives + more data than what rxfifo_full_thrhd specifies. */ + __IOM uint32_t TXFIFO_EMPTY_INT_RAW : 1; /*!< This interrupt raw bit turns to high level when the amount of + data in Tx-FIFO is less than what txfifo_empty_thrhd specifies + . */ + __IOM uint32_t PARITY_ERR_INT_RAW : 1; /*!< This interrupt raw bit turns to high level when receiver detects + a parity error in the data. */ + __IOM uint32_t FRM_ERR_INT_RAW : 1; /*!< This interrupt raw bit turns to high level when receiver detects + a data frame error . */ + __IOM uint32_t RXFIFO_OVF_INT_RAW : 1; /*!< This interrupt raw bit turns to high level when receiver receives + more data than the FIFO can store. */ + __IOM uint32_t DSR_CHG_INT_RAW : 1; /*!< This interrupt raw bit turns to high level when receiver detects + the edge change of DSRn signal. */ + __IOM uint32_t CTS_CHG_INT_RAW : 1; /*!< This interrupt raw bit turns to high level when receiver detects + the edge change of CTSn signal. */ + __IOM uint32_t BRK_DET_INT_RAW : 1; /*!< This interrupt raw bit turns to high level when receiver detects + a 0 after the stop bit. */ + __IOM uint32_t RXFIFO_TOUT_INT_RAW : 1; /*!< This interrupt raw bit turns to high level when receiver takes + more time than rx_tout_thrhd to receive a byte. */ + __IOM uint32_t SW_XON_INT_RAW : 1; /*!< This interrupt raw bit turns to high level when receiver recevies + Xon char when uart_sw_flow_con_en is set to 1. */ + __IOM uint32_t SW_XOFF_INT_RAW : 1; /*!< This interrupt raw bit turns to high level when receiver receives + Xoff char when uart_sw_flow_con_en is set to 1. */ + __IOM uint32_t GLITCH_DET_INT_RAW : 1; /*!< This interrupt raw bit turns to high level when receiver detects + a glitch in the middle of a start bit. */ + __IOM uint32_t TX_BRK_DONE_INT_RAW : 1; /*!< This interrupt raw bit turns to high level when transmitter + completes sending NULL characters after all data in Tx-FIFO + are sent. */ + __IOM uint32_t TX_BRK_IDLE_DONE_INT_RAW : 1;/*!< This interrupt raw bit turns to high level when transmitter + has kept the shortest duration after sending the last data. */ + __IOM uint32_t TX_DONE_INT_RAW : 1; /*!< This interrupt raw bit turns to high level when transmitter + has send out all data in FIFO. */ + __IOM uint32_t RS485_PARITY_ERR_INT_RAW : 1;/*!< This interrupt raw bit turns to high level when receiver detects + a parity error from the echo of transmitter in rs485 mode. */ + __IOM uint32_t RS485_FRM_ERR_INT_RAW : 1; /*!< This interrupt raw bit turns to high level when receiver detects + a data frame error from the echo of transmitter in rs485 + mode. */ + __IOM uint32_t RS485_CLASH_INT_RAW : 1; /*!< This interrupt raw bit turns to high level when detects a clash + between transmitter and receiver in rs485 mode. */ + __IOM uint32_t AT_CMD_CHAR_DET_INT_RAW : 1;/*!< This interrupt raw bit turns to high level when receiver detects + the configured at_cmd char. */ + __IOM uint32_t WAKEUP_INT_RAW : 1; /*!< This interrupt raw bit turns to high level when input rxd edge + changes more times than what reg_active_threshold specifies + in light sleeping mode. */ + uint32_t : 12; + } bit; + } INT_RAW; + + union { + __IOM uint32_t reg; /*!< Masked interrupt status */ + + struct { + __IM uint32_t RXFIFO_FULL_INT_ST : 1; /*!< This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena + is set to 1. */ + __IM uint32_t TXFIFO_EMPTY_INT_ST : 1; /*!< This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena + is set to 1. */ + __IM uint32_t PARITY_ERR_INT_ST : 1; /*!< This is the status bit for parity_err_int_raw when parity_err_int_ena + is set to 1. */ + __IM uint32_t FRM_ERR_INT_ST : 1; /*!< This is the status bit for frm_err_int_raw when frm_err_int_ena + is set to 1. */ + __IM uint32_t RXFIFO_OVF_INT_ST : 1; /*!< This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena + is set to 1. */ + __IM uint32_t DSR_CHG_INT_ST : 1; /*!< This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena + is set to 1. */ + __IM uint32_t CTS_CHG_INT_ST : 1; /*!< This is the status bit for cts_chg_int_raw when cts_chg_int_ena + is set to 1. */ + __IM uint32_t BRK_DET_INT_ST : 1; /*!< This is the status bit for brk_det_int_raw when brk_det_int_ena + is set to 1. */ + __IM uint32_t RXFIFO_TOUT_INT_ST : 1; /*!< This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena + is set to 1. */ + __IM uint32_t SW_XON_INT_ST : 1; /*!< This is the status bit for sw_xon_int_raw when sw_xon_int_ena + is set to 1. */ + __IM uint32_t SW_XOFF_INT_ST : 1; /*!< This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena + is set to 1. */ + __IM uint32_t GLITCH_DET_INT_ST : 1; /*!< This is the status bit for glitch_det_int_raw when glitch_det_int_ena + is set to 1. */ + __IM uint32_t TX_BRK_DONE_INT_ST : 1; /*!< This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena + is set to 1. */ + __IM uint32_t TX_BRK_IDLE_DONE_INT_ST : 1;/*!< This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ + na is set to 1. */ + __IM uint32_t TX_DONE_INT_ST : 1; /*!< This is the status bit for tx_done_int_raw when tx_done_int_ena + is set to 1. */ + __IM uint32_t RS485_PARITY_ERR_INT_ST : 1;/*!< This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena + is set to 1. */ + __IM uint32_t RS485_FRM_ERR_INT_ST : 1; /*!< This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena + is set to 1. */ + __IM uint32_t RS485_CLASH_INT_ST : 1; /*!< This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena + is set to 1. */ + __IM uint32_t AT_CMD_CHAR_DET_INT_ST : 1;/*!< This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena + is set to 1. */ + __IM uint32_t WAKEUP_INT_ST : 1; /*!< This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena + is set to 1. */ + uint32_t : 12; + } bit; + } INT_ST; + + union { + __IOM uint32_t reg; /*!< Interrupt enable bits */ + + struct { + __IOM uint32_t RXFIFO_FULL_INT_ENA : 1; /*!< This is the enable bit for rxfifo_full_int_st register. */ + __IOM uint32_t TXFIFO_EMPTY_INT_ENA : 1; /*!< This is the enable bit for txfifo_empty_int_st register. */ + __IOM uint32_t PARITY_ERR_INT_ENA : 1; /*!< This is the enable bit for parity_err_int_st register. */ + __IOM uint32_t FRM_ERR_INT_ENA : 1; /*!< This is the enable bit for frm_err_int_st register. */ + __IOM uint32_t RXFIFO_OVF_INT_ENA : 1; /*!< This is the enable bit for rxfifo_ovf_int_st register. */ + __IOM uint32_t DSR_CHG_INT_ENA : 1; /*!< This is the enable bit for dsr_chg_int_st register. */ + __IOM uint32_t CTS_CHG_INT_ENA : 1; /*!< This is the enable bit for cts_chg_int_st register. */ + __IOM uint32_t BRK_DET_INT_ENA : 1; /*!< This is the enable bit for brk_det_int_st register. */ + __IOM uint32_t RXFIFO_TOUT_INT_ENA : 1; /*!< This is the enable bit for rxfifo_tout_int_st register. */ + __IOM uint32_t SW_XON_INT_ENA : 1; /*!< This is the enable bit for sw_xon_int_st register. */ + __IOM uint32_t SW_XOFF_INT_ENA : 1; /*!< This is the enable bit for sw_xoff_int_st register. */ + __IOM uint32_t GLITCH_DET_INT_ENA : 1; /*!< This is the enable bit for glitch_det_int_st register. */ + __IOM uint32_t TX_BRK_DONE_INT_ENA : 1; /*!< This is the enable bit for tx_brk_done_int_st register. */ + __IOM uint32_t TX_BRK_IDLE_DONE_INT_ENA : 1;/*!< This is the enable bit for tx_brk_idle_done_int_st register. */ + __IOM uint32_t TX_DONE_INT_ENA : 1; /*!< This is the enable bit for tx_done_int_st register. */ + __IOM uint32_t RS485_PARITY_ERR_INT_ENA : 1;/*!< This is the enable bit for rs485_parity_err_int_st register. */ + __IOM uint32_t RS485_FRM_ERR_INT_ENA : 1; /*!< This is the enable bit for rs485_parity_err_int_st register. */ + __IOM uint32_t RS485_CLASH_INT_ENA : 1; /*!< This is the enable bit for rs485_clash_int_st register. */ + __IOM uint32_t AT_CMD_CHAR_DET_INT_ENA : 1;/*!< This is the enable bit for at_cmd_char_det_int_st register. */ + __IOM uint32_t WAKEUP_INT_ENA : 1; /*!< This is the enable bit for uart_wakeup_int_st register. */ + uint32_t : 12; + } bit; + } INT_ENA; + + union { + __IOM uint32_t reg; /*!< Interrupt clear bits */ + + struct { + __OM uint32_t RXFIFO_FULL_INT_CLR : 1; /*!< Set this bit to clear the rxfifo_full_int_raw interrupt. */ + __OM uint32_t TXFIFO_EMPTY_INT_CLR : 1; /*!< Set this bit to clear txfifo_empty_int_raw interrupt. */ + __OM uint32_t PARITY_ERR_INT_CLR : 1; /*!< Set this bit to clear parity_err_int_raw interrupt. */ + __OM uint32_t FRM_ERR_INT_CLR : 1; /*!< Set this bit to clear frm_err_int_raw interrupt. */ + __OM uint32_t RXFIFO_OVF_INT_CLR : 1; /*!< Set this bit to clear rxfifo_ovf_int_raw interrupt. */ + __OM uint32_t DSR_CHG_INT_CLR : 1; /*!< Set this bit to clear the dsr_chg_int_raw interrupt. */ + __OM uint32_t CTS_CHG_INT_CLR : 1; /*!< Set this bit to clear the cts_chg_int_raw interrupt. */ + __OM uint32_t BRK_DET_INT_CLR : 1; /*!< Set this bit to clear the brk_det_int_raw interrupt. */ + __OM uint32_t RXFIFO_TOUT_INT_CLR : 1; /*!< Set this bit to clear the rxfifo_tout_int_raw interrupt. */ + __OM uint32_t SW_XON_INT_CLR : 1; /*!< Set this bit to clear the sw_xon_int_raw interrupt. */ + __OM uint32_t SW_XOFF_INT_CLR : 1; /*!< Set this bit to clear the sw_xoff_int_raw interrupt. */ + __OM uint32_t GLITCH_DET_INT_CLR : 1; /*!< Set this bit to clear the glitch_det_int_raw interrupt. */ + __OM uint32_t TX_BRK_DONE_INT_CLR : 1; /*!< Set this bit to clear the tx_brk_done_int_raw interrupt.. */ + __OM uint32_t TX_BRK_IDLE_DONE_INT_CLR : 1;/*!< Set this bit to clear the tx_brk_idle_done_int_raw interrupt. */ + __OM uint32_t TX_DONE_INT_CLR : 1; /*!< Set this bit to clear the tx_done_int_raw interrupt. */ + __OM uint32_t RS485_PARITY_ERR_INT_CLR : 1;/*!< Set this bit to clear the rs485_parity_err_int_raw interrupt. */ + __OM uint32_t RS485_FRM_ERR_INT_CLR : 1; /*!< Set this bit to clear the rs485_frm_err_int_raw interrupt. */ + __OM uint32_t RS485_CLASH_INT_CLR : 1; /*!< Set this bit to clear the rs485_clash_int_raw interrupt. */ + __OM uint32_t AT_CMD_CHAR_DET_INT_CLR : 1;/*!< Set this bit to clear the at_cmd_char_det_int_raw interrupt. */ + __OM uint32_t WAKEUP_INT_CLR : 1; /*!< Set this bit to clear the uart_wakeup_int_raw interrupt. */ + uint32_t : 12; + } bit; + } INT_CLR; + + union { + __IOM uint32_t reg; /*!< Clock divider configuration */ + + struct { + __IOM uint32_t CLKDIV : 12; /*!< The integral part of the frequency divider factor. */ + uint32_t : 8; + __IOM uint32_t CLKDIV_FRAG : 4; /*!< The decimal part of the frequency divider factor. */ + uint32_t : 8; + } bit; + } CLKDIV_SYNC; + + union { + __IOM uint32_t reg; /*!< Rx Filter configuration */ + + struct { + __IOM uint32_t GLITCH_FILT : 8; /*!< when input pulse width is lower than this value the pulse is + ignored. */ + __IOM uint32_t GLITCH_FILT_EN : 1; /*!< Set this bit to enable Rx signal filter. */ + uint32_t : 23; + } bit; + } RX_FILT; + + union { + __IOM uint32_t reg; /*!< UART status register */ + + struct { + __IM uint32_t RXFIFO_CNT : 8; /*!< Stores the byte number of valid data in Rx-FIFO. */ + uint32_t : 5; + __IM uint32_t DSRN : 1; /*!< The register represent the level value of the internal uart + dsr signal. */ + __IM uint32_t CTSN : 1; /*!< This register represent the level value of the internal uart + cts signal. */ + __IM uint32_t RXD : 1; /*!< This register represent the level value of the internal uart + rxd signal. */ + __IM uint32_t TXFIFO_CNT : 8; /*!< Stores the byte number of data in Tx-FIFO. */ + uint32_t : 5; + __IM uint32_t DTRN : 1; /*!< This bit represents the level of the internal uart dtr signal. */ + __IM uint32_t RTSN : 1; /*!< This bit represents the level of the internal uart rts signal. */ + __IM uint32_t TXD : 1; /*!< This bit represents the level of the internal uart txd signal. */ + } bit; + } STATUS; + + union { + __IOM uint32_t reg; /*!< a */ + + struct { + __IOM uint32_t PARITY : 1; /*!< This register is used to configure the parity check mode. */ + __IOM uint32_t PARITY_EN : 1; /*!< Set this bit to enable uart parity check. */ + __IOM uint32_t BIT_NUM : 2; /*!< This register is used to set the length of data. */ + __IOM uint32_t STOP_BIT_NUM : 2; /*!< This register is used to set the length of stop bit. */ + __IOM uint32_t TXD_BRK : 1; /*!< Set this bit to enbale transmitter to send NULL when the process + of sending data is done. */ + __IOM uint32_t IRDA_DPLX : 1; /*!< Set this bit to enable IrDA loopback mode. */ + __IOM uint32_t IRDA_TX_EN : 1; /*!< This is the start enable bit for IrDA transmitter. */ + __IOM uint32_t IRDA_WCTL : 1; /*!< 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. + 1'h0: Set IrDA transmitter's 11th bit to 0. */ + __IOM uint32_t IRDA_TX_INV : 1; /*!< Set this bit to invert the level of IrDA transmitter. */ + __IOM uint32_t IRDA_RX_INV : 1; /*!< Set this bit to invert the level of IrDA receiver. */ + __IOM uint32_t LOOPBACK : 1; /*!< Set this bit to enable uart loopback test mode. */ + __IOM uint32_t TX_FLOW_EN : 1; /*!< Set this bit to enable flow control function for transmitter. */ + __IOM uint32_t IRDA_EN : 1; /*!< Set this bit to enable IrDA protocol. */ + __IOM uint32_t RXD_INV : 1; /*!< Set this bit to inverse the level value of uart rxd signal. */ + __IOM uint32_t TXD_INV : 1; /*!< Set this bit to inverse the level value of uart txd signal. */ + __IOM uint32_t DIS_RX_DAT_OVF : 1; /*!< Disable UART Rx data overflow detect. */ + __IOM uint32_t ERR_WR_MASK : 1; /*!< 1'h1: Receiver stops storing data into FIFO when data is wrong. + 1'h0: Receiver stores the data even if the received data + is wrong. */ + __IOM uint32_t AUTOBAUD_EN : 1; /*!< This is the enable bit for detecting baudrate. */ + __IOM uint32_t MEM_CLK_EN : 1; /*!< UART memory clock gate enable signal. */ + __IOM uint32_t SW_RTS : 1; /*!< This register is used to configure the software rts signal which + is used in software flow control. */ + __IOM uint32_t RXFIFO_RST : 1; /*!< Set this bit to reset the uart receive-FIFO. */ + __IOM uint32_t TXFIFO_RST : 1; /*!< Set this bit to reset the uart transmit-FIFO. */ + uint32_t : 8; + } bit; + } CONF0_SYNC; + + union { + __IOM uint32_t reg; /*!< Configuration register 1 */ + + struct { + __IOM uint32_t RXFIFO_FULL_THRHD : 8; /*!< It will produce rxfifo_full_int interrupt when receiver receives + more data than this register value. */ + __IOM uint32_t TXFIFO_EMPTY_THRHD : 8; /*!< It will produce txfifo_empty_int interrupt when the data amount + in Tx-FIFO is less than this register value. */ + __IOM uint32_t CTS_INV : 1; /*!< Set this bit to inverse the level value of uart cts signal. */ + __IOM uint32_t DSR_INV : 1; /*!< Set this bit to inverse the level value of uart dsr signal. */ + __IOM uint32_t RTS_INV : 1; /*!< Set this bit to inverse the level value of uart rts signal. */ + __IOM uint32_t DTR_INV : 1; /*!< Set this bit to inverse the level value of uart dtr signal. */ + __IOM uint32_t SW_DTR : 1; /*!< This register is used to configure the software dtr signal which + is used in software flow control. */ + __IOM uint32_t CLK_EN : 1; /*!< 1'h1: Force clock on for register. 1'h0: Support clock only + when application writes registers. */ + uint32_t : 10; + } bit; + } CONF1; + __IM uint32_t RESERVED; + + union { + __IOM uint32_t reg; /*!< Hardware flow-control configuration */ + + struct { + __IOM uint32_t RX_FLOW_THRHD : 8; /*!< This register is used to configure the maximum amount of data + that can be received when hardware flow control works. */ + __IOM uint32_t RX_FLOW_EN : 1; /*!< This is the flow enable bit for UART receiver. */ + uint32_t : 23; + } bit; + } HWFC_CONF_SYNC; + + union { + __IOM uint32_t reg; /*!< UART sleep configure register 0 */ + + struct { + __IOM uint32_t WK_CHAR1 : 8; /*!< This register restores the specified wake up char1 to wake up */ + __IOM uint32_t WK_CHAR2 : 8; /*!< This register restores the specified wake up char2 to wake up */ + __IOM uint32_t WK_CHAR3 : 8; /*!< This register restores the specified wake up char3 to wake up */ + __IOM uint32_t WK_CHAR4 : 8; /*!< This register restores the specified wake up char4 to wake up */ + } bit; + } SLEEP_CONF0; + + union { + __IOM uint32_t reg; /*!< UART sleep configure register 1 */ + + struct { + __IOM uint32_t WK_CHAR0 : 8; /*!< This register restores the specified char0 to wake up */ + uint32_t : 24; + } bit; + } SLEEP_CONF1; + + union { + __IOM uint32_t reg; /*!< UART sleep configure register 2 */ + + struct { + __IOM uint32_t ACTIVE_THRESHOLD : 10; /*!< The uart is activated from light sleeping mode when the input + rxd edge changes more times than this register value. */ + __IOM uint32_t RX_WAKE_UP_THRHD : 8; /*!< In wake up mode 1 this field is used to set the received data + number threshold to wake up chip. */ + __IOM uint32_t WK_CHAR_NUM : 3; /*!< This register is used to select number of wake up char. */ + __IOM uint32_t WK_CHAR_MASK : 5; /*!< This register is used to mask wake up char. */ + __IOM uint32_t WK_MODE_SEL : 2; /*!< This register is used to select wake up mode. 0: RXD toggling + to wake up. 1: received data number larger than */ + uint32_t : 4; + } bit; + } SLEEP_CONF2; + + union { + __IOM uint32_t reg; /*!< Software flow-control character configuration */ + + struct { + __IOM uint32_t XON_CHAR : 8; /*!< This register stores the Xon flow control char. */ + __IOM uint32_t XOFF_CHAR : 8; /*!< This register stores the Xoff flow control char. */ + __IOM uint32_t XON_XOFF_STILL_SEND : 1; /*!< In software flow control mode, UART Tx is disabled once UART + Rx receives XOFF. In this status, UART Tx can not transmit + XOFF even the received data number is larger than UART_XOFF_THRESHOLD. + Set this bit to enable UART Tx can transmit XON/XOFF when + UART Tx is disabled. */ + __IOM uint32_t SW_FLOW_CON_EN : 1; /*!< Set this bit to enable software flow control. It is used with + register sw_xon or sw_xoff. */ + __IOM uint32_t XONOFF_DEL : 1; /*!< Set this bit to remove flow control char from the received data. */ + __IOM uint32_t FORCE_XON : 1; /*!< Set this bit to enable the transmitter to go on sending data. */ + __IOM uint32_t FORCE_XOFF : 1; /*!< Set this bit to stop the transmitter from sending data. */ + __IOM uint32_t SEND_XON : 1; /*!< Set this bit to send Xon char. It is cleared by hardware automatically. */ + __IOM uint32_t SEND_XOFF : 1; /*!< Set this bit to send Xoff char. It is cleared by hardware automatically. */ + uint32_t : 9; + } bit; + } SWFC_CONF0_SYNC; + + union { + __IOM uint32_t reg; /*!< Software flow-control character configuration */ + + struct { + __IOM uint32_t XON_THRESHOLD : 8; /*!< When the data amount in Rx-FIFO is less than this register value + with uart_sw_flow_con_en set to 1 it will send a Xon char. */ + __IOM uint32_t XOFF_THRESHOLD : 8; /*!< When the data amount in Rx-FIFO is more than this register value + with uart_sw_flow_con_en set to 1 it will send a Xoff char. */ + uint32_t : 16; + } bit; + } SWFC_CONF1; + + union { + __IOM uint32_t reg; /*!< Tx Break character configuration */ + + struct { + __IOM uint32_t TX_BRK_NUM : 8; /*!< This register is used to configure the number of 0 to be sent + after the process of sending data is done. It is active + when txd_brk is set to 1. */ + uint32_t : 24; + } bit; + } TXBRK_CONF_SYNC; + + union { + __IOM uint32_t reg; /*!< Frame-end idle configuration */ + + struct { + __IOM uint32_t RX_IDLE_THRHD : 10; /*!< It will produce frame end signal when receiver takes more time + to receive one byte data than this register value. */ + __IOM uint32_t TX_IDLE_NUM : 10; /*!< This register is used to configure the duration time between + transfers. */ + uint32_t : 12; + } bit; + } IDLE_CONF_SYNC; + + union { + __IOM uint32_t reg; /*!< RS485 mode configuration */ + + struct { + __IOM uint32_t RS485_EN : 1; /*!< Set this bit to choose the rs485 mode. */ + __IOM uint32_t DL0_EN : 1; /*!< Set this bit to delay the stop bit by 1 bit. */ + __IOM uint32_t DL1_EN : 1; /*!< Set this bit to delay the stop bit by 1 bit. */ + __IOM uint32_t RS485TX_RX_EN : 1; /*!< Set this bit to enable receiver could receive data when the + transmitter is transmitting data in rs485 mode. */ + __IOM uint32_t RS485RXBY_TX_EN : 1; /*!< 1'h1: enable rs485 transmitter to send data when rs485 receiver + line is busy. */ + __IOM uint32_t RS485_RX_DLY_NUM : 1; /*!< This register is used to delay the receiver's internal data + signal. */ + __IOM uint32_t RS485_TX_DLY_NUM : 4; /*!< This register is used to delay the transmitter's internal data + signal. */ + uint32_t : 22; + } bit; + } RS485_CONF_SYNC; + + union { + __IOM uint32_t reg; /*!< Pre-sequence timing configuration */ + + struct { + __IOM uint32_t PRE_IDLE_NUM : 16; /*!< This register is used to configure the idle duration time before + the first at_cmd is received by receiver. */ + uint32_t : 16; + } bit; + } AT_CMD_PRECNT_SYNC; + + union { + __IOM uint32_t reg; /*!< Post-sequence timing configuration */ + + struct { + __IOM uint32_t POST_IDLE_NUM : 16; /*!< This register is used to configure the duration time between + the last at_cmd and the next data. */ + uint32_t : 16; + } bit; + } AT_CMD_POSTCNT_SYNC; + + union { + __IOM uint32_t reg; /*!< Timeout configuration */ + + struct { + __IOM uint32_t RX_GAP_TOUT : 16; /*!< This register is used to configure the duration time between + the at_cmd chars. */ + uint32_t : 16; + } bit; + } AT_CMD_GAPTOUT_SYNC; + + union { + __IOM uint32_t reg; /*!< AT escape sequence detection configuration */ + + struct { + __IOM uint32_t AT_CMD_CHAR : 8; /*!< This register is used to configure the content of at_cmd char. */ + __IOM uint32_t CHAR_NUM : 8; /*!< This register is used to configure the num of continuous at_cmd + chars received by receiver. */ + uint32_t : 16; + } bit; + } AT_CMD_CHAR_SYNC; + + union { + __IOM uint32_t reg; /*!< UART memory power configuration */ + + struct { + uint32_t : 25; + __IOM uint32_t MEM_FORCE_PD : 1; /*!< Set this bit to force power down UART memory. */ + __IOM uint32_t MEM_FORCE_PU : 1; /*!< Set this bit to force power up UART memory. */ + uint32_t : 5; + } bit; + } MEM_CONF; + + union { + __IOM uint32_t reg; /*!< UART threshold and allocation configuration */ + + struct { + __IOM uint32_t RX_TOUT_EN : 1; /*!< This is the enble bit for uart receiver's timeout function. */ + __IOM uint32_t RX_TOUT_FLOW_DIS : 1; /*!< Set this bit to stop accumulating idle_cnt when hardware flow + control works. */ + __IOM uint32_t RX_TOUT_THRHD : 10; /*!< This register is used to configure the threshold time that receiver + takes to receive one byte. The rxfifo_tout_int interrupt + will be trigger when the receiver takes more time to receive + one byte with rx_tout_en set to 1. */ + uint32_t : 20; + } bit; + } TOUT_CONF_SYNC; + + union { + __IOM uint32_t reg; /*!< Tx-SRAM write and read offset address. */ + + struct { + __IM uint32_t TX_SRAM_WADDR : 8; /*!< This register stores the offset write address in Tx-SRAM. */ + uint32_t : 1; + __IM uint32_t TX_SRAM_RADDR : 8; /*!< This register stores the offset read address in Tx-SRAM. */ + uint32_t : 15; + } bit; + } MEM_TX_STATUS; + + union { + __IOM uint32_t reg; /*!< Rx-SRAM write and read offset address. */ + + struct { + __IM uint32_t RX_SRAM_RADDR : 8; /*!< This register stores the offset read address in RX-SRAM. */ + uint32_t : 1; + __IM uint32_t RX_SRAM_WADDR : 8; /*!< This register stores the offset write address in Rx-SRAM. */ + uint32_t : 15; + } bit; + } MEM_RX_STATUS; + + union { + __IOM uint32_t reg; /*!< UART transmit and receive status. */ + + struct { + __IM uint32_t ST_URX_OUT : 4; /*!< This is the status register of receiver. */ + __IM uint32_t ST_UTX_OUT : 4; /*!< This is the status register of transmitter. */ + uint32_t : 24; + } bit; + } FSM_STATUS; + + union { + __IOM uint32_t reg; /*!< Autobaud high pulse register */ + + struct { + __IM uint32_t POSEDGE_MIN_CNT : 12; /*!< This register stores the minimal input clock count between two + positive edges. It is used in boudrate-detect process. */ + uint32_t : 20; + } bit; + } POSPULSE; + + union { + __IOM uint32_t reg; /*!< Autobaud low pulse register */ + + struct { + __IM uint32_t NEGEDGE_MIN_CNT : 12; /*!< This register stores the minimal input clock count between two + negative edges. It is used in boudrate-detect process. */ + uint32_t : 20; + } bit; + } NEGPULSE; + + union { + __IOM uint32_t reg; /*!< Autobaud minimum low pulse duration register */ + + struct { + __IM uint32_t MIN_CNT : 12; /*!< This register stores the value of the minimum duration time + of the low level pulse. It is used in baud rate-detect + process. */ + uint32_t : 20; + } bit; + } LOWPULSE; + + union { + __IOM uint32_t reg; /*!< Autobaud minimum high pulse duration register */ + + struct { + __IM uint32_t MIN_CNT : 12; /*!< This register stores the value of the maxinum duration time + for the high level pulse. It is used in baud rate-detect + process. */ + uint32_t : 20; + } bit; + } HIGHPULSE; + + union { + __IOM uint32_t reg; /*!< Autobaud edge change count register */ + + struct { + __IM uint32_t RXD_EDGE_CNT : 10; /*!< This register stores the count of rxd edge change. It is used + in baud rate-detect process. */ + uint32_t : 22; + } bit; + } RXD_CNT; + + union { + __IOM uint32_t reg; /*!< UART core clock configuration */ + + struct { + uint32_t : 24; + __IOM uint32_t TX_SCLK_EN : 1; /*!< Set this bit to enable UART Tx clock. */ + __IOM uint32_t RX_SCLK_EN : 1; /*!< Set this bit to enable UART Rx clock. */ + __IOM uint32_t TX_RST_CORE : 1; /*!< Write 1 then write 0 to this bit to reset UART Tx. */ + __IOM uint32_t RX_RST_CORE : 1; /*!< Write 1 then write 0 to this bit to reset UART Rx. */ + uint32_t : 4; + } bit; + } CLK_CONF; + + union { + __IOM uint32_t reg; /*!< UART Version register */ + + struct { + __IOM uint32_t DATE : 32; /*!< This is the version register. */ + } bit; + } DATE; + + union { + __IOM uint32_t reg; /*!< UART AFIFO Status */ + + struct { + __IM uint32_t TX_AFIFO_FULL : 1; /*!< Full signal of APB TX AFIFO. */ + __IM uint32_t TX_AFIFO_EMPTY : 1; /*!< Empty signal of APB TX AFIFO. */ + __IM uint32_t RX_AFIFO_FULL : 1; /*!< Full signal of APB RX AFIFO. */ + __IM uint32_t RX_AFIFO_EMPTY : 1; /*!< Empty signal of APB RX AFIFO. */ + uint32_t : 28; + } bit; + } AFIFO_STATUS; + __IM uint32_t RESERVED1; + + union { + __IOM uint32_t reg; /*!< UART Registers Configuration Update register */ + + struct { + __IOM uint32_t REG_UPDATE : 1; /*!< Software write 1 would synchronize registers into UART Core + clock domain and would be cleared by hardware after synchronization + is done. */ + uint32_t : 31; + } bit; + } REG_UPDATE; + + union { + __IOM uint32_t reg; /*!< UART ID register */ + + struct { + __IOM uint32_t ID : 32; /*!< This register is used to configure the uart_id. */ + } bit; + } ID; +} UART0_Type; /*!< Size = 160 (0xa0) */ + + + +/* =========================================================================================================================== */ +/* ================ UHCI0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Universal Host Controller Interface 0 (UHCI0) + */ + +typedef struct { /*!< UHCI0 Structure */ + + union { + __IOM uint32_t reg; /*!< UHCI Configuration Register0 */ + + struct { + __IOM uint32_t TX_RST : 1; /*!< Write 1 then write 0 to this bit to reset decode state machine. */ + __IOM uint32_t RX_RST : 1; /*!< Write 1 then write 0 to this bit to reset encode state machine. */ + __IOM uint32_t UART_SEL : 3; /*!< Select which uart to connect with GDMA. */ + __IOM uint32_t SEPER_EN : 1; /*!< Set this bit to separate the data frame using a special char. */ + __IOM uint32_t HEAD_EN : 1; /*!< Set this bit to encode the data packet with a formatting header. */ + __IOM uint32_t CRC_REC_EN : 1; /*!< Set this bit to enable UHCI to receive the 16 bit CRC. */ + __IOM uint32_t UART_IDLE_EOF_EN : 1; /*!< If this bit is set to 1 UHCI will end the payload receiving + process when UART has been in idle state. */ + __IOM uint32_t LEN_EOF_EN : 1; /*!< If this bit is set to 1 UHCI decoder receiving payload data + is end when the receiving byte count has reached the specified + value. The value is payload length indicated by UHCI packet + header when UHCI_HEAD_EN is 1 or the value is configuration + value when UHCI_HEAD_EN is 0. If this bit is set to 0 UHCI + decoder receiving payload data is end when 0xc0 is received. */ + __IOM uint32_t ENCODE_CRC_EN : 1; /*!< Set this bit to enable data integrity checking by appending + a 16 bit CCITT-CRC to end of the payload. */ + __IOM uint32_t CLK_EN : 1; /*!< 1'b1: Force clock on for register. 1'b0: Support clock only + when application writes registers. */ + __IOM uint32_t UART_RX_BRK_EOF_EN : 1; /*!< If this bit is set to 1 UHCI will end payload receive process + when NULL frame is received by UART. */ + uint32_t : 19; + } bit; + } CONF0; + + union { + __IOM uint32_t reg; /*!< UHCI Interrupt Raw Register */ + + struct { + __IOM uint32_t RX_START_INT_RAW : 1; /*!< Indicates the raw interrupt of UHCI_RX_START_INT. Interrupt + will be triggered when delimiter is sent successfully. */ + __IOM uint32_t TX_START_INT_RAW : 1; /*!< Indicates the raw interrupt of UHCI_TX_START_INT. Interrupt + will be triggered when DMA detects delimiter. */ + __IOM uint32_t RX_HUNG_INT_RAW : 1; /*!< Indicates the raw interrupt of UHCI_RX_HUNG_INT. Interrupt will + be triggered when the required time of DMA receiving data + exceeds the configuration value. */ + __IOM uint32_t TX_HUNG_INT_RAW : 1; /*!< Indicates the raw interrupt of UHCI_TX_HUNG_INT. Interrupt will + be triggered when the required time of DMA reading RAM + data exceeds the configuration value. */ + __IOM uint32_t SEND_S_REG_Q_INT_RAW : 1; /*!< Indicates the raw interrupt of UHCI_SEND_S_REG_Q_INT. Interrupt + will be triggered when UHCI sends short packet successfully + with single_send mode. */ + __IOM uint32_t SEND_A_REG_Q_INT_RAW : 1; /*!< Indicates the raw interrupt of UHCI_SEND_A_REG_Q_INT. Interrupt + will be triggered when UHCI sends short packet successfully + with always_send mode. */ + __IOM uint32_t OUT_EOF_INT_RAW : 1; /*!< Indicates the raw interrupt of UHCI_OUT_EOF_INT. Interrupt will + be triggered when there are errors in EOF. */ + __IOM uint32_t APP_CTRL0_INT_RAW : 1; /*!< Indicates the raw interrupt of UHCI_APP_CTRL0_INT. Interrupt + will be triggered when UHCI_APP_CTRL0_IN_SET is set to + 1. */ + __IOM uint32_t APP_CTRL1_INT_RAW : 1; /*!< Indicates the raw interrupt of UHCI_APP_CTRL1_INT. Interrupt + will be triggered when UHCI_APP_CTRL1_IN_SET is set to + 1. */ + uint32_t : 23; + } bit; + } INT_RAW; + + union { + __IOM uint32_t reg; /*!< UHCI Interrupt Status Register */ + + struct { + __IM uint32_t RX_START_INT_ST : 1; /*!< Indicates the interrupt status of UHCI_RX_START_INT. */ + __IM uint32_t TX_START_INT_ST : 1; /*!< Indicates the interrupt status of UHCI_TX_START_INT. */ + __IM uint32_t RX_HUNG_INT_ST : 1; /*!< Indicates the interrupt status of UHCI_RX_HUNG_INT. */ + __IM uint32_t TX_HUNG_INT_ST : 1; /*!< Indicates the interrupt status of UHCI_TX_HUNG_INT. */ + __IM uint32_t SEND_S_REG_Q_INT_ST : 1; /*!< Indicates the interrupt status of UHCI_SEND_S_REG_Q_INT. */ + __IM uint32_t SEND_A_REG_Q_INT_ST : 1; /*!< Indicates the interrupt status of UHCI_SEND_A_REG_Q_INT. */ + __IM uint32_t OUTLINK_EOF_ERR_INT_ST : 1;/*!< Indicates the interrupt status of UHCI_OUT_EOF_INT. */ + __IM uint32_t APP_CTRL0_INT_ST : 1; /*!< Indicates the interrupt status of UHCI_APP_CTRL0_INT. */ + __IM uint32_t APP_CTRL1_INT_ST : 1; /*!< Indicates the interrupt status of UHCI_APP_CTRL1_INT. */ + uint32_t : 23; + } bit; + } INT_ST; + + union { + __IOM uint32_t reg; /*!< UHCI Interrupt Enable Register */ + + struct { + __IOM uint32_t RX_START_INT_ENA : 1; /*!< Set this bit to enable the interrupt of UHCI_RX_START_INT. */ + __IOM uint32_t TX_START_INT_ENA : 1; /*!< Set this bit to enable the interrupt of UHCI_TX_START_INT. */ + __IOM uint32_t RX_HUNG_INT_ENA : 1; /*!< Set this bit to enable the interrupt of UHCI_RX_HUNG_INT. */ + __IOM uint32_t TX_HUNG_INT_ENA : 1; /*!< Set this bit to enable the interrupt of UHCI_TX_HUNG_INT. */ + __IOM uint32_t SEND_S_REG_Q_INT_ENA : 1; /*!< Set this bit to enable the interrupt of UHCI_SEND_S_REG_Q_INT. */ + __IOM uint32_t SEND_A_REG_Q_INT_ENA : 1; /*!< Set this bit to enable the interrupt of UHCI_SEND_A_REG_Q_INT. */ + __IOM uint32_t OUTLINK_EOF_ERR_INT_ENA : 1;/*!< Set this bit to enable the interrupt of UHCI_OUT_EOF_INT. */ + __IOM uint32_t APP_CTRL0_INT_ENA : 1; /*!< Set this bit to enable the interrupt of UHCI_APP_CTRL0_INT. */ + __IOM uint32_t APP_CTRL1_INT_ENA : 1; /*!< Set this bit to enable the interrupt of UHCI_APP_CTRL1_INT. */ + uint32_t : 23; + } bit; + } INT_ENA; + + union { + __IOM uint32_t reg; /*!< UHCI Interrupt Clear Register */ + + struct { + __OM uint32_t RX_START_INT_CLR : 1; /*!< Set this bit to clear the raw interrupt of UHCI_RX_START_INT. */ + __OM uint32_t TX_START_INT_CLR : 1; /*!< Set this bit to clear the raw interrupt of UHCI_TX_START_INT. */ + __OM uint32_t RX_HUNG_INT_CLR : 1; /*!< Set this bit to clear the raw interrupt of UHCI_RX_HUNG_INT. */ + __OM uint32_t TX_HUNG_INT_CLR : 1; /*!< Set this bit to clear the raw interrupt of UHCI_TX_HUNG_INT. */ + __OM uint32_t SEND_S_REG_Q_INT_CLR : 1; /*!< Set this bit to clear the raw interrupt of UHCI_SEND_S_REG_Q_INT. */ + __OM uint32_t SEND_A_REG_Q_INT_CLR : 1; /*!< Set this bit to clear the raw interrupt of UHCI_SEND_A_REG_Q_INT. */ + __OM uint32_t OUTLINK_EOF_ERR_INT_CLR : 1;/*!< Set this bit to clear the raw interrupt of UHCI_OUT_EOF_INT. */ + __OM uint32_t APP_CTRL0_INT_CLR : 1; /*!< Set this bit to clear the raw interrupt of UHCI_APP_CTRL0_INT. */ + __OM uint32_t APP_CTRL1_INT_CLR : 1; /*!< Set this bit to clear the raw interrupt of UHCI_APP_CTRL1_INT. */ + uint32_t : 23; + } bit; + } INT_CLR; + + union { + __IOM uint32_t reg; /*!< UHCI Configuration Register1 */ + + struct { + __IOM uint32_t CHECK_SUM_EN : 1; /*!< Set this bit to enable head checksum check when receiving. */ + __IOM uint32_t CHECK_SEQ_EN : 1; /*!< Set this bit to enable sequence number check when receiving. */ + __IOM uint32_t CRC_DISABLE : 1; /*!< Set this bit to support CRC calculation, and data integrity + check bit should 1. */ + __IOM uint32_t SAVE_HEAD : 1; /*!< Set this bit to save data packet head when UHCI receive data. */ + __IOM uint32_t TX_CHECK_SUM_RE : 1; /*!< Set this bit to encode data packet with checksum. */ + __IOM uint32_t TX_ACK_NUM_RE : 1; /*!< Set this bit to encode data packet with ACK when reliable data + packet is ready. */ + uint32_t : 1; + __IOM uint32_t WAIT_SW_START : 1; /*!< Set this bit to enable UHCI encoder transfer to ST_SW_WAIT status. */ + __OM uint32_t SW_START : 1; /*!< Set this bit to transmit data packet if UCHI_ENCODE_STATE is + ST_SW_WAIT. */ + uint32_t : 23; + } bit; + } CONF1; + + union { + __IOM uint32_t reg; /*!< UHCI Receive Status Register */ + + struct { + __IM uint32_t RX_ERR_CAUSE : 3; /*!< Indicates the error types when DMA receives the error frame. + 3'b001: UHCI packet checksum error. 3'b010: UHCI packet + sequence number error. 3'b011: UHCI packet CRC bit error. + 3'b100: find 0xC0, but received packet is uncompleted. + 3'b101: 0xC0 is not found, but received packet is completed. + 3'b110: CRC check error. */ + __IM uint32_t DECODE_STATE : 3; /*!< Indicates UHCI decoder status. */ + uint32_t : 26; + } bit; + } STATE0; + + union { + __IOM uint32_t reg; /*!< UHCI Transmit Status Register */ + + struct { + __IM uint32_t ENCODE_STATE : 3; /*!< Indicates UHCI encoder status. */ + uint32_t : 29; + } bit; + } STATE1; + + union { + __IOM uint32_t reg; /*!< UHCI Escapes Configuration Register0 */ + + struct { + __IOM uint32_t TX_C0_ESC_EN : 1; /*!< Set this bit to enable resolve char 0xC0 when DMA receiving + data. */ + __IOM uint32_t TX_DB_ESC_EN : 1; /*!< Set this bit to enable resolve char 0xDB when DMA receiving + data. */ + __IOM uint32_t TX_11_ESC_EN : 1; /*!< Set this bit to enable resolve flow control char 0x11 when DMA + receiving data. */ + __IOM uint32_t TX_13_ESC_EN : 1; /*!< Set this bit to enable resolve flow control char 0x13 when DMA + receiving data. */ + __IOM uint32_t RX_C0_ESC_EN : 1; /*!< Set this bit to enable replacing 0xC0 with special char when + DMA receiving data. */ + __IOM uint32_t RX_DB_ESC_EN : 1; /*!< Set this bit to enable replacing 0xDB with special char when + DMA receiving data. */ + __IOM uint32_t RX_11_ESC_EN : 1; /*!< Set this bit to enable replacing 0x11 with special char when + DMA receiving data. */ + __IOM uint32_t RX_13_ESC_EN : 1; /*!< Set this bit to enable replacing 0x13 with special char when + DMA receiving data. */ + uint32_t : 24; + } bit; + } ESCAPE_CONF; + + union { + __IOM uint32_t reg; /*!< UHCI Hung Configuration Register0 */ + + struct { + __IOM uint32_t TXFIFO_TIMEOUT : 8; /*!< Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for + timeout when receiving data. */ + __IOM uint32_t TXFIFO_TIMEOUT_SHIFT : 3; /*!< Configures the maximum counter value. */ + __IOM uint32_t TXFIFO_TIMEOUT_ENA : 1; /*!< Set this bit to enable TX FIFO timeout when receiving. */ + __IOM uint32_t RXFIFO_TIMEOUT : 8; /*!< Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for + timeout when reading RAM data. */ + __IOM uint32_t RXFIFO_TIMEOUT_SHIFT : 3; /*!< Configures the maximum counter value. */ + __IOM uint32_t RXFIFO_TIMEOUT_ENA : 1; /*!< Set this bit to enable TX FIFO timeout when DMA sending data. */ + uint32_t : 8; + } bit; + } HUNG_CONF; + + union { + __IOM uint32_t reg; /*!< UHCI Ack Value Configuration Register0 */ + + struct { + __IOM uint32_t ACK_NUM : 3; /*!< Indicates the ACK number during software flow control. */ + __OM uint32_t LOAD : 1; /*!< Set this bit to load the ACK value of UHCI_ACK_NUM. */ + uint32_t : 28; + } bit; + } ACK_NUM; + + union { + __IOM uint32_t reg; /*!< UHCI Head Register */ + + struct { + __IM uint32_t RX_HEAD : 32; /*!< Stores the head of received packet. */ + } bit; + } RX_HEAD; + + union { + __IOM uint32_t reg; /*!< UCHI Quick send Register */ + + struct { + __IOM uint32_t SINGLE_SEND_NUM : 3; /*!< Configures single_send mode. */ + __OM uint32_t SINGLE_SEND_EN : 1; /*!< Set this bit to enable sending short packet with single_send + mode. */ + __IOM uint32_t ALWAYS_SEND_NUM : 3; /*!< Configures always_send mode. */ + __IOM uint32_t ALWAYS_SEND_EN : 1; /*!< Set this bit to enable sending short packet with always_send + mode. */ + uint32_t : 24; + } bit; + } QUICK_SENT; + + union { + __IOM uint32_t reg; /*!< UHCI Q0_WORD0 Quick Send Register */ + + struct { + __IOM uint32_t SEND_Q0_WORD0 : 32; /*!< Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM + or UHCI_SINGLE_SEND_NUM. */ + } bit; + } REG_Q0_WORD0; + + union { + __IOM uint32_t reg; /*!< UHCI Q0_WORD1 Quick Send Register */ + + struct { + __IOM uint32_t SEND_Q0_WORD1 : 32; /*!< Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM + or UHCI_SINGLE_SEND_NUM. */ + } bit; + } REG_Q0_WORD1; + + union { + __IOM uint32_t reg; /*!< UHCI Q1_WORD0 Quick Send Register */ + + struct { + __IOM uint32_t SEND_Q1_WORD0 : 32; /*!< Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM + or UHCI_SINGLE_SEND_NUM. */ + } bit; + } REG_Q1_WORD0; + + union { + __IOM uint32_t reg; /*!< UHCI Q1_WORD1 Quick Send Register */ + + struct { + __IOM uint32_t SEND_Q1_WORD1 : 32; /*!< Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM + or UHCI_SINGLE_SEND_NUM. */ + } bit; + } REG_Q1_WORD1; + + union { + __IOM uint32_t reg; /*!< UHCI Q2_WORD0 Quick Send Register */ + + struct { + __IOM uint32_t SEND_Q2_WORD0 : 32; /*!< Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM + or UHCI_SINGLE_SEND_NUM. */ + } bit; + } REG_Q2_WORD0; + + union { + __IOM uint32_t reg; /*!< UHCI Q2_WORD1 Quick Send Register */ + + struct { + __IOM uint32_t SEND_Q2_WORD1 : 32; /*!< Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM + or UHCI_SINGLE_SEND_NUM. */ + } bit; + } REG_Q2_WORD1; + + union { + __IOM uint32_t reg; /*!< UHCI Q3_WORD0 Quick Send Register */ + + struct { + __IOM uint32_t SEND_Q3_WORD0 : 32; /*!< Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM + or UHCI_SINGLE_SEND_NUM. */ + } bit; + } REG_Q3_WORD0; + + union { + __IOM uint32_t reg; /*!< UHCI Q3_WORD1 Quick Send Register */ + + struct { + __IOM uint32_t SEND_Q3_WORD1 : 32; /*!< Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM + or UHCI_SINGLE_SEND_NUM. */ + } bit; + } REG_Q3_WORD1; + + union { + __IOM uint32_t reg; /*!< UHCI Q4_WORD0 Quick Send Register */ + + struct { + __IOM uint32_t SEND_Q4_WORD0 : 32; /*!< Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM + or UHCI_SINGLE_SEND_NUM. */ + } bit; + } REG_Q4_WORD0; + + union { + __IOM uint32_t reg; /*!< UHCI Q4_WORD1 Quick Send Register */ + + struct { + __IOM uint32_t SEND_Q4_WORD1 : 32; /*!< Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM + or UHCI_SINGLE_SEND_NUM. */ + } bit; + } REG_Q4_WORD1; + + union { + __IOM uint32_t reg; /*!< UHCI Q5_WORD0 Quick Send Register */ + + struct { + __IOM uint32_t SEND_Q5_WORD0 : 32; /*!< Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM + or UHCI_SINGLE_SEND_NUM. */ + } bit; + } REG_Q5_WORD0; + + union { + __IOM uint32_t reg; /*!< UHCI Q5_WORD1 Quick Send Register */ + + struct { + __IOM uint32_t SEND_Q5_WORD1 : 32; /*!< Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM + or UHCI_SINGLE_SEND_NUM. */ + } bit; + } REG_Q5_WORD1; + + union { + __IOM uint32_t reg; /*!< UHCI Q6_WORD0 Quick Send Register */ + + struct { + __IOM uint32_t SEND_Q6_WORD0 : 32; /*!< Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM + or UHCI_SINGLE_SEND_NUM. */ + } bit; + } REG_Q6_WORD0; + + union { + __IOM uint32_t reg; /*!< UHCI Q6_WORD1 Quick Send Register */ + + struct { + __IOM uint32_t SEND_Q6_WORD1 : 32; /*!< Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM + or UHCI_SINGLE_SEND_NUM. */ + } bit; + } REG_Q6_WORD1; + + union { + __IOM uint32_t reg; /*!< UHCI Escapes Sequence Configuration Register0 */ + + struct { + __IOM uint32_t SEPER_CHAR : 8; /*!< Configures the delimiter for encoding, default value is 0xC0. */ + __IOM uint32_t SEPER_ESC_CHAR0 : 8; /*!< Configures the first char of SLIP escape character, default + value is 0xDB. */ + __IOM uint32_t SEPER_ESC_CHAR1 : 8; /*!< Configures the second char of SLIP escape character, default + value is 0xDC. */ + uint32_t : 8; + } bit; + } ESC_CONF0; + + union { + __IOM uint32_t reg; /*!< UHCI Escapes Sequence Configuration Register1 */ + + struct { + __IOM uint32_t ESC_SEQ0 : 8; /*!< Configures the char needing encoding, which is 0xDB as flow + control char by default. */ + __IOM uint32_t ESC_SEQ0_CHAR0 : 8; /*!< Configures the first char of SLIP escape character, default + value is 0xDB. */ + __IOM uint32_t ESC_SEQ0_CHAR1 : 8; /*!< Configures the second char of SLIP escape character, default + value is 0xDD. */ + uint32_t : 8; + } bit; + } ESC_CONF1; + + union { + __IOM uint32_t reg; /*!< UHCI Escapes Sequence Configuration Register2 */ + + struct { + __IOM uint32_t ESC_SEQ1 : 8; /*!< Configures the char needing encoding, which is 0x11 as flow + control char by default. */ + __IOM uint32_t ESC_SEQ1_CHAR0 : 8; /*!< Configures the first char of SLIP escape character, default + value is 0xDB. */ + __IOM uint32_t ESC_SEQ1_CHAR1 : 8; /*!< Configures the second char of SLIP escape character, default + value is 0xDE. */ + uint32_t : 8; + } bit; + } ESC_CONF2; + + union { + __IOM uint32_t reg; /*!< UHCI Escapes Sequence Configuration Register3 */ + + struct { + __IOM uint32_t ESC_SEQ2 : 8; /*!< Configures the char needing encoding, which is 0x13 as flow + control char by default. */ + __IOM uint32_t ESC_SEQ2_CHAR0 : 8; /*!< Configures the first char of SLIP escape character, default + value is 0xDB. */ + __IOM uint32_t ESC_SEQ2_CHAR1 : 8; /*!< Configures the second char of SLIP escape character, default + value is 0xDF. */ + uint32_t : 8; + } bit; + } ESC_CONF3; + + union { + __IOM uint32_t reg; /*!< UCHI Packet Length Configuration Register */ + + struct { + __IOM uint32_t PKT_THRS : 13; /*!< Configures the data packet's maximum length when UHCI_HEAD_EN + is 0. */ + uint32_t : 19; + } bit; + } PKT_THRES; + + union { + __IOM uint32_t reg; /*!< UHCI Version Register */ + + struct { + __IOM uint32_t DATE : 32; /*!< Configures version. */ + } bit; + } DATE; +} UHCI0_Type; /*!< Size = 132 (0x84) */ + + + +/* =========================================================================================================================== */ +/* ================ USB_DEVICE ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Full-speed USB Serial/JTAG Controller (USB_DEVICE) + */ + +typedef struct { /*!< USB_DEVICE Structure */ + + union { + __IOM uint32_t reg; /*!< FIFO access for the CDC-ACM data IN and OUT endpoints. */ + + struct { + __IM uint32_t USB_SERIAL_JTAG_RDWR_BYTE : 8;/*!< Write and read byte data to/from UART Tx/Rx FIFO through this + field. When USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then + user can write data (up to 64 bytes) into UART Tx FIFO. + When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can + check USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR + to know how many data is received, then read data from + UART Rx FIFO. */ + uint32_t : 24; + } bit; + } EP1; + + union { + __IOM uint32_t reg; /*!< Configuration and control registers for the CDC-ACM FIFOs. */ + + struct { + __OM uint32_t USB_SERIAL_JTAG_WR_DONE : 1;/*!< Set this bit to indicate writing byte data to UART Tx FIFO is + done. */ + __IM uint32_t USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE : 1;/*!< 1'b1: Indicate UART Tx FIFO is not full and can write data into + in. After writing USB_DEVICE_WR_DONE, this bit would be + 0 until data in UART Tx FIFO is read by USB Host. */ + __IM uint32_t USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL : 1;/*!< 1'b1: Indicate there is data in UART Rx FIFO. */ + uint32_t : 29; + } bit; + } EP1_CONF; + + union { + __IOM uint32_t reg; /*!< Interrupt raw status register. */ + + struct { + __IOM uint32_t USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when flush cmd is + received for IN endpoint 2 of JTAG. */ + __IOM uint32_t USB_SERIAL_JTAG_SOF_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when SOF frame is + received. */ + __IOM uint32_t USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when Serial Port OUT + Endpoint received one packet. */ + __IOM uint32_t USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when Serial Port IN + Endpoint is empty. */ + __IOM uint32_t USB_SERIAL_JTAG_PID_ERR_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when pid error is + detected. */ + __IOM uint32_t USB_SERIAL_JTAG_CRC5_ERR_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when CRC5 error is + detected. */ + __IOM uint32_t USB_SERIAL_JTAG_CRC16_ERR_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when CRC16 error is + detected. */ + __IOM uint32_t USB_SERIAL_JTAG_STUFF_ERR_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when stuff error is + detected. */ + __IOM uint32_t USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when IN token for + IN endpoint 1 is received. */ + __IOM uint32_t USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when usb bus reset + is detected. */ + __IOM uint32_t USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when OUT endpoint + 1 received packet with zero palyload. */ + __IOM uint32_t USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when OUT endpoint + 2 received packet with zero palyload. */ + __IOM uint32_t USB_SERIAL_JTAG_RTS_CHG_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when level of RTS + from usb serial channel is changed. */ + __IOM uint32_t USB_SERIAL_JTAG_DTR_CHG_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when level of DTR + from usb serial channel is changed. */ + __IOM uint32_t USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when level of GET + LINE CODING request is received. */ + __IOM uint32_t USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when level of SET + LINE CODING request is received. */ + uint32_t : 16; + } bit; + } INT_RAW; + + union { + __IOM uint32_t reg; /*!< Interrupt status register. */ + + struct { + __IM uint32_t USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST : 1;/*!< The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT + interrupt. */ + __IM uint32_t USB_SERIAL_JTAG_SOF_INT_ST : 1;/*!< The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt. */ + __IM uint32_t USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST : 1;/*!< The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT + interrupt. */ + __IM uint32_t USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST : 1;/*!< The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT + interrupt. */ + __IM uint32_t USB_SERIAL_JTAG_PID_ERR_INT_ST : 1;/*!< The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT + interrupt. */ + __IM uint32_t USB_SERIAL_JTAG_CRC5_ERR_INT_ST : 1;/*!< The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT + interrupt. */ + __IM uint32_t USB_SERIAL_JTAG_CRC16_ERR_INT_ST : 1;/*!< The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT + interrupt. */ + __IM uint32_t USB_SERIAL_JTAG_STUFF_ERR_INT_ST : 1;/*!< The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT + interrupt. */ + __IM uint32_t USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST : 1;/*!< The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT + interrupt. */ + __IM uint32_t USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST : 1;/*!< The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT + interrupt. */ + __IM uint32_t USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST : 1;/*!< The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT + interrupt. */ + __IM uint32_t USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST : 1;/*!< The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT + interrupt. */ + __IM uint32_t USB_SERIAL_JTAG_RTS_CHG_INT_ST : 1;/*!< The raw interrupt status bit for the USB_DEVICE_RTS_CHG_INT + interrupt. */ + __IM uint32_t USB_SERIAL_JTAG_DTR_CHG_INT_ST : 1;/*!< The raw interrupt status bit for the USB_DEVICE_DTR_CHG_INT + interrupt. */ + __IM uint32_t USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST : 1;/*!< The raw interrupt status bit for the USB_DEVICE_GET_LINE_CODE_INT + interrupt. */ + __IM uint32_t USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST : 1;/*!< The raw interrupt status bit for the USB_DEVICE_SET_LINE_CODE_INT + interrupt. */ + uint32_t : 16; + } bit; + } INT_ST; + + union { + __IOM uint32_t reg; /*!< Interrupt enable status register. */ + + struct { + __IOM uint32_t USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA : 1;/*!< The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT + interrupt. */ + __IOM uint32_t USB_SERIAL_JTAG_SOF_INT_ENA : 1;/*!< The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt. */ + __IOM uint32_t USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA : 1;/*!< The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT + interrupt. */ + __IOM uint32_t USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA : 1;/*!< The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT + interrupt. */ + __IOM uint32_t USB_SERIAL_JTAG_PID_ERR_INT_ENA : 1;/*!< The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt. */ + __IOM uint32_t USB_SERIAL_JTAG_CRC5_ERR_INT_ENA : 1;/*!< The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt. */ + __IOM uint32_t USB_SERIAL_JTAG_CRC16_ERR_INT_ENA : 1;/*!< The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt. */ + __IOM uint32_t USB_SERIAL_JTAG_STUFF_ERR_INT_ENA : 1;/*!< The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt. */ + __IOM uint32_t USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA : 1;/*!< The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT + interrupt. */ + __IOM uint32_t USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA : 1;/*!< The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT + interrupt. */ + __IOM uint32_t USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA : 1;/*!< The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT + interrupt. */ + __IOM uint32_t USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA : 1;/*!< The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT + interrupt. */ + __IOM uint32_t USB_SERIAL_JTAG_RTS_CHG_INT_ENA : 1;/*!< The interrupt enable bit for the USB_DEVICE_RTS_CHG_INT interrupt. */ + __IOM uint32_t USB_SERIAL_JTAG_DTR_CHG_INT_ENA : 1;/*!< The interrupt enable bit for the USB_DEVICE_DTR_CHG_INT interrupt. */ + __IOM uint32_t USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA : 1;/*!< The interrupt enable bit for the USB_DEVICE_GET_LINE_CODE_INT + interrupt. */ + __IOM uint32_t USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA : 1;/*!< The interrupt enable bit for the USB_DEVICE_SET_LINE_CODE_INT + interrupt. */ + uint32_t : 16; + } bit; + } INT_ENA; + + union { + __IOM uint32_t reg; /*!< Interrupt clear status register. */ + + struct { + __OM uint32_t USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR : 1;/*!< Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. */ + __OM uint32_t USB_SERIAL_JTAG_SOF_INT_CLR : 1;/*!< Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt. */ + __OM uint32_t USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR : 1;/*!< Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT + interrupt. */ + __OM uint32_t USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR : 1;/*!< Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. */ + __OM uint32_t USB_SERIAL_JTAG_PID_ERR_INT_CLR : 1;/*!< Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt. */ + __OM uint32_t USB_SERIAL_JTAG_CRC5_ERR_INT_CLR : 1;/*!< Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt. */ + __OM uint32_t USB_SERIAL_JTAG_CRC16_ERR_INT_CLR : 1;/*!< Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt. */ + __OM uint32_t USB_SERIAL_JTAG_STUFF_ERR_INT_CLR : 1;/*!< Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt. */ + __OM uint32_t USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR : 1;/*!< Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt. */ + __OM uint32_t USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR : 1;/*!< Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt. */ + __OM uint32_t USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR : 1;/*!< Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT + interrupt. */ + __OM uint32_t USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR : 1;/*!< Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT + interrupt. */ + __OM uint32_t USB_SERIAL_JTAG_RTS_CHG_INT_CLR : 1;/*!< Set this bit to clear the USB_DEVICE_RTS_CHG_INT interrupt. */ + __OM uint32_t USB_SERIAL_JTAG_DTR_CHG_INT_CLR : 1;/*!< Set this bit to clear the USB_DEVICE_DTR_CHG_INT interrupt. */ + __OM uint32_t USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR : 1;/*!< Set this bit to clear the USB_DEVICE_GET_LINE_CODE_INT interrupt. */ + __OM uint32_t USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR : 1;/*!< Set this bit to clear the USB_DEVICE_SET_LINE_CODE_INT interrupt. */ + uint32_t : 16; + } bit; + } INT_CLR; + + union { + __IOM uint32_t reg; /*!< PHY hardware configuration. */ + + struct { + __IOM uint32_t USB_SERIAL_JTAG_PHY_SEL : 1;/*!< Select internal/external PHY */ + __IOM uint32_t USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE : 1;/*!< Enable software control USB D+ D- exchange */ + __IOM uint32_t USB_SERIAL_JTAG_EXCHG_PINS : 1;/*!< USB D+ D- exchange */ + __IOM uint32_t USB_SERIAL_JTAG_VREFH : 2; /*!< Control single-end input high threshold,1.76V to 2V, step 80mV */ + __IOM uint32_t USB_SERIAL_JTAG_VREFL : 2; /*!< Control single-end input low threshold,0.8V to 1.04V, step 80mV */ + __IOM uint32_t USB_SERIAL_JTAG_VREF_OVERRIDE : 1;/*!< Enable software control input threshold */ + __IOM uint32_t USB_SERIAL_JTAG_PAD_PULL_OVERRIDE : 1;/*!< Enable software control USB D+ D- pullup pulldown */ + __IOM uint32_t USB_SERIAL_JTAG_DP_PULLUP : 1;/*!< Control USB D+ pull up. */ + __IOM uint32_t USB_SERIAL_JTAG_DP_PULLDOWN : 1;/*!< Control USB D+ pull down. */ + __IOM uint32_t USB_SERIAL_JTAG_DM_PULLUP : 1;/*!< Control USB D- pull up. */ + __IOM uint32_t USB_SERIAL_JTAG_DM_PULLDOWN : 1;/*!< Control USB D- pull down. */ + __IOM uint32_t USB_SERIAL_JTAG_PULLUP_VALUE : 1;/*!< Control pull up value. */ + __IOM uint32_t USB_SERIAL_JTAG_USB_PAD_ENABLE : 1;/*!< Enable USB pad function. */ + __IOM uint32_t USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN : 1;/*!< Set this bit usb_jtag, the connection between usb_jtag and internal + JTAG is disconnected, and MTMS, MTDI, MTCK are output through + GPIO Matrix, MTDO is input through GPIO Matrix. */ + uint32_t : 16; + } bit; + } CONF0; + + union { + __IOM uint32_t reg; /*!< Registers used for debugging the PHY. */ + + struct { + __IOM uint32_t USB_SERIAL_JTAG_TEST_ENABLE : 1;/*!< Enable test of the USB pad */ + __IOM uint32_t USB_SERIAL_JTAG_TEST_USB_OE : 1;/*!< USB pad oen in test */ + __IOM uint32_t USB_SERIAL_JTAG_TEST_TX_DP : 1;/*!< USB D+ tx value in test */ + __IOM uint32_t USB_SERIAL_JTAG_TEST_TX_DM : 1;/*!< USB D- tx value in test */ + __IM uint32_t USB_SERIAL_JTAG_TEST_RX_RCV : 1;/*!< USB RCV value in test */ + __IM uint32_t USB_SERIAL_JTAG_TEST_RX_DP : 1;/*!< USB D+ rx value in test */ + __IM uint32_t USB_SERIAL_JTAG_TEST_RX_DM : 1;/*!< USB D- rx value in test */ + uint32_t : 25; + } bit; + } TEST; + + union { + __IOM uint32_t reg; /*!< JTAG FIFO status and control registers. */ + + struct { + __IM uint32_t USB_SERIAL_JTAG_IN_FIFO_CNT : 2;/*!< JTAT in fifo counter. */ + __IM uint32_t USB_SERIAL_JTAG_IN_FIFO_EMPTY : 1;/*!< 1: JTAG in fifo is empty. */ + __IM uint32_t USB_SERIAL_JTAG_IN_FIFO_FULL : 1;/*!< 1: JTAG in fifo is full. */ + __IM uint32_t USB_SERIAL_JTAG_OUT_FIFO_CNT : 2;/*!< JTAT out fifo counter. */ + __IM uint32_t USB_SERIAL_JTAG_OUT_FIFO_EMPTY : 1;/*!< 1: JTAG out fifo is empty. */ + __IM uint32_t USB_SERIAL_JTAG_OUT_FIFO_FULL : 1;/*!< 1: JTAG out fifo is full. */ + __IOM uint32_t USB_SERIAL_JTAG_IN_FIFO_RESET : 1;/*!< Write 1 to reset JTAG in fifo. */ + __IOM uint32_t USB_SERIAL_JTAG_OUT_FIFO_RESET : 1;/*!< Write 1 to reset JTAG out fifo. */ + uint32_t : 22; + } bit; + } JFIFO_ST; + + union { + __IOM uint32_t reg; /*!< Last received SOF frame index register. */ + + struct { + __IM uint32_t USB_SERIAL_JTAG_SOF_FRAME_INDEX : 11;/*!< Frame index of received SOF frame. */ + uint32_t : 21; + } bit; + } FRAM_NUM; + + union { + __IOM uint32_t reg; /*!< Control IN endpoint status information. */ + + struct { + __IM uint32_t USB_SERIAL_JTAG_IN_EP0_STATE : 2;/*!< State of IN Endpoint 0. */ + __IM uint32_t USB_SERIAL_JTAG_IN_EP0_WR_ADDR : 7;/*!< Write data address of IN endpoint 0. */ + __IM uint32_t USB_SERIAL_JTAG_IN_EP0_RD_ADDR : 7;/*!< Read data address of IN endpoint 0. */ + uint32_t : 16; + } bit; + } IN_EP0_ST; + + union { + __IOM uint32_t reg; /*!< CDC-ACM IN endpoint status information. */ + + struct { + __IM uint32_t USB_SERIAL_JTAG_IN_EP1_STATE : 2;/*!< State of IN Endpoint 1. */ + __IM uint32_t USB_SERIAL_JTAG_IN_EP1_WR_ADDR : 7;/*!< Write data address of IN endpoint 1. */ + __IM uint32_t USB_SERIAL_JTAG_IN_EP1_RD_ADDR : 7;/*!< Read data address of IN endpoint 1. */ + uint32_t : 16; + } bit; + } IN_EP1_ST; + + union { + __IOM uint32_t reg; /*!< CDC-ACM interrupt IN endpoint status information. */ + + struct { + __IM uint32_t USB_SERIAL_JTAG_IN_EP2_STATE : 2;/*!< State of IN Endpoint 2. */ + __IM uint32_t USB_SERIAL_JTAG_IN_EP2_WR_ADDR : 7;/*!< Write data address of IN endpoint 2. */ + __IM uint32_t USB_SERIAL_JTAG_IN_EP2_RD_ADDR : 7;/*!< Read data address of IN endpoint 2. */ + uint32_t : 16; + } bit; + } IN_EP2_ST; + + union { + __IOM uint32_t reg; /*!< JTAG IN endpoint status information. */ + + struct { + __IM uint32_t USB_SERIAL_JTAG_IN_EP3_STATE : 2;/*!< State of IN Endpoint 3. */ + __IM uint32_t USB_SERIAL_JTAG_IN_EP3_WR_ADDR : 7;/*!< Write data address of IN endpoint 3. */ + __IM uint32_t USB_SERIAL_JTAG_IN_EP3_RD_ADDR : 7;/*!< Read data address of IN endpoint 3. */ + uint32_t : 16; + } bit; + } IN_EP3_ST; + + union { + __IOM uint32_t reg; /*!< Control OUT endpoint status information. */ + + struct { + __IM uint32_t USB_SERIAL_JTAG_OUT_EP0_STATE : 2;/*!< State of OUT Endpoint 0. */ + __IM uint32_t USB_SERIAL_JTAG_OUT_EP0_WR_ADDR : 7;/*!< Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT + is detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes + data in OUT EP0. */ + __IM uint32_t USB_SERIAL_JTAG_OUT_EP0_RD_ADDR : 7;/*!< Read data address of OUT endpoint 0. */ + uint32_t : 16; + } bit; + } OUT_EP0_ST; + + union { + __IOM uint32_t reg; /*!< CDC-ACM OUT endpoint status information. */ + + struct { + __IM uint32_t USB_SERIAL_JTAG_OUT_EP1_STATE : 2;/*!< State of OUT Endpoint 1. */ + __IM uint32_t USB_SERIAL_JTAG_OUT_EP1_WR_ADDR : 7;/*!< Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT + is detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes + data in OUT EP1. */ + __IM uint32_t USB_SERIAL_JTAG_OUT_EP1_RD_ADDR : 7;/*!< Read data address of OUT endpoint 1. */ + __IM uint32_t USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT : 7;/*!< Data count in OUT endpoint 1 when one packet is received. */ + uint32_t : 9; + } bit; + } OUT_EP1_ST; + + union { + __IOM uint32_t reg; /*!< JTAG OUT endpoint status information. */ + + struct { + __IM uint32_t USB_SERIAL_JTAG_OUT_EP2_STATE : 2;/*!< State of OUT Endpoint 2. */ + __IM uint32_t USB_SERIAL_JTAG_OUT_EP2_WR_ADDR : 7;/*!< Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT + is detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes + data in OUT EP2. */ + __IM uint32_t USB_SERIAL_JTAG_OUT_EP2_RD_ADDR : 7;/*!< Read data address of OUT endpoint 2. */ + uint32_t : 16; + } bit; + } OUT_EP2_ST; + + union { + __IOM uint32_t reg; /*!< Clock enable control */ + + struct { + __IOM uint32_t USB_SERIAL_JTAG_CLK_EN : 1;/*!< 1'h1: Force clock on for register. 1'h0: Support clock only + when application writes registers. */ + uint32_t : 31; + } bit; + } MISC_CONF; + + union { + __IOM uint32_t reg; /*!< Memory power control */ + + struct { + __IOM uint32_t USB_SERIAL_JTAG_USB_MEM_PD : 1;/*!< 1: power down usb memory. */ + __IOM uint32_t USB_SERIAL_JTAG_USB_MEM_CLK_EN : 1;/*!< 1: Force clock on for usb memory. */ + uint32_t : 30; + } bit; + } MEM_CONF; + + union { + __IOM uint32_t reg; /*!< CDC-ACM chip reset control. */ + + struct { + __IM uint32_t USB_SERIAL_JTAG_RTS : 1; /*!< 1: Chip reset is detected from usb serial channel. Software + write 1 to clear it. */ + __IM uint32_t USB_SERIAL_JTAG_DTR : 1; /*!< 1: Chip reset is detected from usb jtag channel. Software write + 1 to clear it. */ + __IOM uint32_t USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS : 1;/*!< Set this bit to disable chip reset from usb serial channel to + reset chip. */ + uint32_t : 29; + } bit; + } CHIP_RST; + + union { + __IOM uint32_t reg; /*!< W0 of SET_LINE_CODING command. */ + + struct { + __IM uint32_t USB_SERIAL_JTAG_DW_DTE_RATE : 32;/*!< The value of dwDTERate set by host through SET_LINE_CODING command. */ + } bit; + } SET_LINE_CODE_W0; + + union { + __IOM uint32_t reg; /*!< W1 of SET_LINE_CODING command. */ + + struct { + __IM uint32_t USB_SERIAL_JTAG_BCHAR_FORMAT : 8;/*!< The value of bCharFormat set by host through SET_LINE_CODING + command. */ + __IM uint32_t USB_SERIAL_JTAG_BPARITY_TYPE : 8;/*!< The value of bParityTpye set by host through SET_LINE_CODING + command. */ + __IM uint32_t USB_SERIAL_JTAG_BDATA_BITS : 8;/*!< The value of bDataBits set by host through SET_LINE_CODING command. */ + uint32_t : 8; + } bit; + } SET_LINE_CODE_W1; + + union { + __IOM uint32_t reg; /*!< W0 of GET_LINE_CODING command. */ + + struct { + __IOM uint32_t USB_SERIAL_JTAG_GET_DW_DTE_RATE : 32;/*!< The value of dwDTERate set by software which is requested by + GET_LINE_CODING command. */ + } bit; + } GET_LINE_CODE_W0; + + union { + __IOM uint32_t reg; /*!< W1 of GET_LINE_CODING command. */ + + struct { + __IOM uint32_t USB_SERIAL_JTAG_GET_BDATA_BITS : 8;/*!< The value of bCharFormat set by software which is requested + by GET_LINE_CODING command. */ + __IOM uint32_t USB_SERIAL_JTAG_GET_BPARITY_TYPE : 8;/*!< The value of bParityTpye set by software which is requested + by GET_LINE_CODING command. */ + __IOM uint32_t USB_SERIAL_JTAG_GET_BCHAR_FORMAT : 8;/*!< The value of bDataBits set by software which is requested by + GET_LINE_CODING command. */ + uint32_t : 8; + } bit; + } GET_LINE_CODE_W1; + + union { + __IOM uint32_t reg; /*!< Configuration registers' value update */ + + struct { + __OM uint32_t USB_SERIAL_JTAG_CONFIG_UPDATE : 1;/*!< Write 1 to this register would update the value of configure + registers from APB clock domain to 48MHz clock domain. */ + uint32_t : 31; + } bit; + } CONFIG_UPDATE; + + union { + __IOM uint32_t reg; /*!< Serial AFIFO configure register */ + + struct { + __IOM uint32_t USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR : 1;/*!< Write 1 to reset CDC_ACM IN async FIFO write clock domain. */ + __IOM uint32_t USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD : 1;/*!< Write 1 to reset CDC_ACM IN async FIFO read clock domain. */ + __IOM uint32_t USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR : 1;/*!< Write 1 to reset CDC_ACM OUT async FIFO write clock domain. */ + __IOM uint32_t USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD : 1;/*!< Write 1 to reset CDC_ACM OUT async FIFO read clock domain. */ + __IM uint32_t USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY : 1;/*!< CDC_ACM OUTOUT async FIFO empty signal in read clock domain. */ + __IM uint32_t USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL : 1;/*!< CDC_ACM OUT IN async FIFO empty signal in write clock domain. */ + uint32_t : 26; + } bit; + } SER_AFIFO_CONFIG; + + union { + __IOM uint32_t reg; /*!< USB Bus reset status register */ + + struct { + __IM uint32_t USB_SERIAL_JTAG_USB_BUS_RESET_ST : 1;/*!< USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset + status. 1: USB bus reset is released. */ + uint32_t : 31; + } bit; + } BUS_RESET_ST; + + union { + __IOM uint32_t reg; /*!< Reserved. */ + + struct { + __IOM uint32_t USB_SERIAL_JTAG_RND_ECO_LOW_48 : 32;/*!< Reserved. */ + } bit; + } ECO_LOW_48; + + union { + __IOM uint32_t reg; /*!< Reserved. */ + + struct { + __IOM uint32_t USB_SERIAL_JTAG_RND_ECO_HIGH_48 : 32;/*!< Reserved. */ + } bit; + } ECO_HIGH_48; + + union { + __IOM uint32_t reg; /*!< Reserved. */ + + struct { + __IM uint32_t USB_SERIAL_JTAG_RDN_RESULT_48 : 1;/*!< Reserved. */ + __IOM uint32_t USB_SERIAL_JTAG_RDN_ENA_48 : 1;/*!< Reserved. */ + uint32_t : 30; + } bit; + } ECO_CELL_CTRL_48; + + union { + __IOM uint32_t reg; /*!< Reserved. */ + + struct { + __IOM uint32_t USB_SERIAL_JTAG_RND_ECO_LOW_APB : 32;/*!< Reserved. */ + } bit; + } ECO_LOW_APB; + + union { + __IOM uint32_t reg; /*!< Reserved. */ + + struct { + __IOM uint32_t USB_SERIAL_JTAG_RND_ECO_HIGH_APB : 32;/*!< Reserved. */ + } bit; + } ECO_HIGH_APB; + + union { + __IOM uint32_t reg; /*!< Reserved. */ + + struct { + __IM uint32_t USB_SERIAL_JTAG_RDN_RESULT_APB : 1;/*!< Reserved. */ + __IOM uint32_t USB_SERIAL_JTAG_RDN_ENA_APB : 1;/*!< Reserved. */ + uint32_t : 30; + } bit; + } ECO_CELL_CTRL_APB; + + union { + __IOM uint32_t reg; /*!< PPA SRAM Control Register */ + + struct { + __IOM uint32_t USB_SERIAL_JTAG_MEM_AUX_CTRL : 14;/*!< Control signals */ + uint32_t : 18; + } bit; + } SRAM_CTRL; + + union { + __IOM uint32_t reg; /*!< Date register */ + + struct { + __IOM uint32_t USB_SERIAL_JTAG_DATE : 32; /*!< register version. */ + } bit; + } DATE; +} USB_DEVICE_Type; /*!< Size = 140 (0x8c) */ + + + +/* =========================================================================================================================== */ +/* ================ USB_WRAP ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief USB_WRAP Peripheral (USB_WRAP) + */ + +typedef struct { /*!< USB_WRAP Structure */ + + union { + __IOM uint32_t reg; /*!< USB wrapper configuration registers. */ + + struct { + __IOM uint32_t SRP_SESSEND_OVERRIDE : 1; /*!< This bit is used to enable the software over-ride of srp session + end signal. 1'b0: the signal is controlled by the chip + input, 1'b1: the signal is controlled by the software. */ + __IOM uint32_t SRP_SESSEND_VALUE : 1; /*!< Software over-ride value of srp session end signal. */ + __IOM uint32_t PHY_SEL : 1; /*!< Select internal external PHY. 1'b0: Select internal PHY, 1'b1: + Select external PHY. */ + __IOM uint32_t DFIFO_FORCE_PD : 1; /*!< Force the dfifo to go into low power mode. The data in dfifo + will not lost. */ + __IOM uint32_t DBNCE_FLTR_BYPASS : 1; /*!< Bypass Debounce filters for avalid,bvalid,vbusvalid,session + end, id signals */ + __IOM uint32_t EXCHG_PINS_OVERRIDE : 1; /*!< Enable software controlle USB D+ D- exchange */ + __IOM uint32_t EXCHG_PINS : 1; /*!< USB D+ D- exchange. 1'b0: don't change, 1'b1: exchange D+ D-. */ + __IOM uint32_t VREFH : 2; /*!< Control single-end input high threshold,1.76V to 2V, step 80mV. */ + __IOM uint32_t VREFL : 2; /*!< Control single-end input low threshold,0.8V to 1.04V, step 80mV. */ + __IOM uint32_t VREF_OVERRIDE : 1; /*!< Enable software controlle input threshold. */ + __IOM uint32_t PAD_PULL_OVERRIDE : 1; /*!< Enable software controlle USB D+ D- pullup pulldown. */ + __IOM uint32_t DP_PULLUP : 1; /*!< Controlle USB D+ pullup. */ + __IOM uint32_t DP_PULLDOWN : 1; /*!< Controlle USB D+ pulldown. */ + __IOM uint32_t DM_PULLUP : 1; /*!< Controlle USB D+ pullup. */ + __IOM uint32_t DM_PULLDOWN : 1; /*!< Controlle USB D+ pulldown. */ + __IOM uint32_t PULLUP_VALUE : 1; /*!< Controlle pullup value. 1'b0: typical value is 2.4K, 1'b1: typical + value is 1.2K. */ + __IOM uint32_t USB_PAD_ENABLE : 1; /*!< Enable USB pad function. */ + __IOM uint32_t AHB_CLK_FORCE_ON : 1; /*!< Force ahb clock always on. */ + __IOM uint32_t PHY_CLK_FORCE_ON : 1; /*!< Force phy clock always on. */ + __IOM uint32_t PHY_TX_EDGE_SEL : 1; /*!< Select phy tx signal output clock edge. 1'b0: negedge, 1'b1: + posedge. */ + __IOM uint32_t DFIFO_FORCE_PU : 1; /*!< Disable the dfifo to go into low power mode. The data in dfifo + will not lost. */ + uint32_t : 8; + __IOM uint32_t CLK_EN : 1; /*!< Disable auto clock gating of CSR registers. */ + } bit; + } OTG_CONF; + + union { + __IOM uint32_t reg; /*!< USB wrapper test configuration registers. */ + + struct { + __IOM uint32_t TEST_ENABLE : 1; /*!< Enable test of the USB pad. */ + __IOM uint32_t TEST_USB_OE : 1; /*!< USB pad oen in test. */ + __IOM uint32_t TEST_TX_DP : 1; /*!< USB D+ tx value in test. */ + __IOM uint32_t TEST_TX_DM : 1; /*!< USB D- tx value in test. */ + __IM uint32_t TEST_RX_RCV : 1; /*!< USB differential rx value in test. */ + __IM uint32_t TEST_RX_DP : 1; /*!< USB D+ rx value in test. */ + __IM uint32_t TEST_RX_DM : 1; /*!< USB D- rx value in test. */ + uint32_t : 25; + } bit; + } TEST_CONF; + __IM uint32_t RESERVED[253]; + + union { + __IOM uint32_t reg; /*!< Date register. */ + + struct { + __IM uint32_t USB_WRAP_DATE : 32; /*!< Date register. */ + } bit; + } DATE; +} USB_WRAP_Type; /*!< Size = 1024 (0x400) */ + + +/** @} */ /* End of group Device_Peripheral_peripherals */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + +#define ADC_BASE 0x500DE000UL +#define AES_BASE 0x50090000UL +#define AHB_DMA_BASE 0x50085000UL +#define LP_I2C_ANA_MST_BASE 0x50124000UL +#define ASSIST_DEBUG_BASE 0x3FF06000UL +#define AXI_DMA_BASE 0x5008A000UL +#define BITSCRAMBLER_BASE 0x500A3000UL +#define CACHE_BASE 0x3FF10000UL +#define INTERRUPT_CORE0_BASE 0x500D6000UL +#define INTERRUPT_CORE1_BASE 0x500D6800UL +#define MIPI_CSI_BRIDGE_BASE 0x5009F800UL +#define MIPI_CSI_HOST_BASE 0x5009F000UL +#define DMA_BASE 0x50081000UL +#define DS_BASE 0x50094000UL +#define MIPI_DSI_BRIDGE_BASE 0x500A0800UL +#define MIPI_DSI_HOST_BASE 0x500A0000UL +#define ECC_BASE 0x50093000UL +#define ECDSA_BASE 0x50096000UL +#define EFUSE_BASE 0x5012D000UL +#define GPIO_BASE 0x500E0000UL +#define GPIO_SD_BASE 0x500E0F00UL +#define H264_BASE 0x50084000UL +#define H264_DMA_BASE 0x500A7000UL +#define HMAC_BASE 0x50095000UL +#define HP_SYS_BASE 0x500E5000UL +#define HP_SYS_CLKRST_BASE 0x500E6000UL +#define LP_HUK_BASE 0x50114000UL +#define I2C0_BASE 0x500C4000UL +#define I2C1_BASE 0x500C5000UL +#define I2S0_BASE 0x500C6000UL +#define I2S1_BASE 0x500C7000UL +#define I2S2_BASE 0x500C8000UL +#define I3C_MST_BASE 0x500DA000UL +#define I3C_MST_MEM_BASE 0x500DA000UL +#define I3C_SLV_BASE 0x500DB000UL +#define AXI_ICM_BASE 0x500A4000UL +#define IO_MUX_BASE 0x500E1000UL +#define ISP_BASE 0x500A1000UL +#define JPEG_BASE 0x50086000UL +#define LCD_CAM_BASE 0x500DC000UL +#define LEDC_BASE 0x500D3000UL +#define LP_INTR_BASE 0x5012C000UL +#define LP_PERI_BASE 0x50120000UL +#define LP_SYS_BASE 0x50110000UL +#define LP_ANA_PERI_BASE 0x50113000UL +#define LP_AON_CLKRST_BASE 0x50111000UL +#define LP_GPIO_BASE 0x5012A000UL +#define LP_I2C0_BASE 0x50122000UL +#define LP_I2S0_BASE 0x50125000UL +#define LP_IO_MUX_BASE 0x5012B000UL +#define LP_UART_BASE 0x50121000UL +#define MCPWM0_BASE 0x500C0000UL +#define MCPWM1_BASE 0x500C1000UL +#define PARL_IO_BASE 0x500CF000UL +#define PAU_BASE 0x60093000UL +#define PCNT_BASE 0x500C9000UL +#define PMU_BASE 0x50115000UL +#define PPA_BASE 0x50087000UL +#define PVT_BASE 0x5009E000UL +#define RMT_BASE 0x500D4000UL +#define RSA_BASE 0x50092000UL +#define LP_ADC_BASE 0x50127000UL +#define LP_TIMER_BASE 0x50112000UL +#define LP_TOUCH_BASE 0x50128000UL +#define LP_WDT_BASE 0x50116000UL +#define SDHOST_BASE 0x50083000UL +#define SHA_BASE 0x50091000UL +#define SOC_ETM_BASE 0x500D5000UL +#define SPI0_BASE 0x5008C000UL +#define SPI1_BASE 0x5008D000UL +#define SPI2_BASE 0x500D0000UL +#define SPI3_BASE 0x500D1000UL +#define SYSTIMER_BASE 0x500E2000UL +#define TIMG0_BASE 0x500C2000UL +#define TIMG1_BASE 0x500C3000UL +#define TRACE0_BASE 0x3FF04000UL +#define TRACE1_BASE 0x3FF05000UL +#define LP_TSENS_BASE 0x5012F000UL +#define TWAI0_BASE 0x500D7000UL +#define TWAI1_BASE 0x500D8000UL +#define TWAI2_BASE 0x500D9000UL +#define UART0_BASE 0x500CA000UL +#define UART1_BASE 0x500CB000UL +#define UART2_BASE 0x500CC000UL +#define UART3_BASE 0x500CD000UL +#define UART4_BASE 0x500CE000UL +#define UHCI0_BASE 0x500DF000UL +#define USB_DEVICE_BASE 0x500D2000UL +#define USB_WRAP_BASE 0x50080000UL + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + +#define ADC ((ADC_Type*) ADC_BASE) +#define AES ((AES_Type*) AES_BASE) +#define AHB_DMA ((AHB_DMA_Type*) AHB_DMA_BASE) +#define LP_I2C_ANA_MST ((LP_I2C_ANA_MST_Type*) LP_I2C_ANA_MST_BASE) +#define ASSIST_DEBUG ((ASSIST_DEBUG_Type*) ASSIST_DEBUG_BASE) +#define AXI_DMA ((AXI_DMA_Type*) AXI_DMA_BASE) +#define BITSCRAMBLER ((BITSCRAMBLER_Type*) BITSCRAMBLER_BASE) +#define CACHE ((CACHE_Type*) CACHE_BASE) +#define INTERRUPT_CORE0 ((INTERRUPT_CORE0_Type*) INTERRUPT_CORE0_BASE) +#define INTERRUPT_CORE1 ((INTERRUPT_CORE1_Type*) INTERRUPT_CORE1_BASE) +#define MIPI_CSI_BRIDGE ((MIPI_CSI_BRIDGE_Type*) MIPI_CSI_BRIDGE_BASE) +#define MIPI_CSI_HOST ((MIPI_CSI_HOST_Type*) MIPI_CSI_HOST_BASE) +#define DMA ((DMA_Type*) DMA_BASE) +#define DS ((DS_Type*) DS_BASE) +#define MIPI_DSI_BRIDGE ((MIPI_DSI_BRIDGE_Type*) MIPI_DSI_BRIDGE_BASE) +#define MIPI_DSI_HOST ((MIPI_DSI_HOST_Type*) MIPI_DSI_HOST_BASE) +#define ECC ((ECC_Type*) ECC_BASE) +#define ECDSA ((ECDSA_Type*) ECDSA_BASE) +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) +#define GPIO ((GPIO_Type*) GPIO_BASE) +#define GPIO_SD ((GPIO_SD_Type*) GPIO_SD_BASE) +#define H264 ((H264_Type*) H264_BASE) +#define H264_DMA ((H264_DMA_Type*) H264_DMA_BASE) +#define HMAC ((HMAC_Type*) HMAC_BASE) +#define HP_SYS ((HP_SYS_Type*) HP_SYS_BASE) +#define HP_SYS_CLKRST ((HP_SYS_CLKRST_Type*) HP_SYS_CLKRST_BASE) +#define LP_HUK ((LP_HUK_Type*) LP_HUK_BASE) +#define I2C0 ((I2C0_Type*) I2C0_BASE) +#define I2C1 ((I2C0_Type*) I2C1_BASE) +#define I2S0 ((I2S0_Type*) I2S0_BASE) +#define I2S1 ((I2S0_Type*) I2S1_BASE) +#define I2S2 ((I2S0_Type*) I2S2_BASE) +#define I3C_MST ((I3C_MST_Type*) I3C_MST_BASE) +#define I3C_MST_MEM ((I3C_MST_MEM_Type*) I3C_MST_MEM_BASE) +#define I3C_SLV ((I3C_SLV_Type*) I3C_SLV_BASE) +#define AXI_ICM ((AXI_ICM_Type*) AXI_ICM_BASE) +#define IO_MUX ((IO_MUX_Type*) IO_MUX_BASE) +#define ISP ((ISP_Type*) ISP_BASE) +#define JPEG ((JPEG_Type*) JPEG_BASE) +#define LCD_CAM ((LCD_CAM_Type*) LCD_CAM_BASE) +#define LEDC ((LEDC_Type*) LEDC_BASE) +#define LP_INTR ((LP_INTR_Type*) LP_INTR_BASE) +#define LP_PERI ((LP_PERI_Type*) LP_PERI_BASE) +#define LP_SYS ((LP_SYS_Type*) LP_SYS_BASE) +#define LP_ANA_PERI ((LP_ANA_PERI_Type*) LP_ANA_PERI_BASE) +#define LP_AON_CLKRST ((LP_AON_CLKRST_Type*) LP_AON_CLKRST_BASE) +#define LP_GPIO ((LP_GPIO_Type*) LP_GPIO_BASE) +#define LP_I2C0 ((LP_I2C0_Type*) LP_I2C0_BASE) +#define LP_I2S0 ((LP_I2S0_Type*) LP_I2S0_BASE) +#define LP_IO_MUX ((LP_IO_MUX_Type*) LP_IO_MUX_BASE) +#define LP_UART ((LP_UART_Type*) LP_UART_BASE) +#define MCPWM0 ((MCPWM0_Type*) MCPWM0_BASE) +#define MCPWM1 ((MCPWM0_Type*) MCPWM1_BASE) +#define PARL_IO ((PARL_IO_Type*) PARL_IO_BASE) +#define PAU ((PAU_Type*) PAU_BASE) +#define PCNT ((PCNT_Type*) PCNT_BASE) +#define PMU ((PMU_Type*) PMU_BASE) +#define PPA ((PPA_Type*) PPA_BASE) +#define PVT ((PVT_Type*) PVT_BASE) +#define RMT ((RMT_Type*) RMT_BASE) +#define RSA ((RSA_Type*) RSA_BASE) +#define LP_ADC ((LP_ADC_Type*) LP_ADC_BASE) +#define LP_TIMER ((LP_TIMER_Type*) LP_TIMER_BASE) +#define LP_TOUCH ((LP_TOUCH_Type*) LP_TOUCH_BASE) +#define LP_WDT ((LP_WDT_Type*) LP_WDT_BASE) +#define SDHOST ((SDHOST_Type*) SDHOST_BASE) +#define SHA ((SHA_Type*) SHA_BASE) +#define SOC_ETM ((SOC_ETM_Type*) SOC_ETM_BASE) +#define SPI0 ((SPI0_Type*) SPI0_BASE) +#define SPI1 ((SPI1_Type*) SPI1_BASE) +#define SPI2 ((SPI2_Type*) SPI2_BASE) +#define SPI3 ((SPI3_Type*) SPI3_BASE) +#define SYSTIMER ((SYSTIMER_Type*) SYSTIMER_BASE) +#define TIMG0 ((TIMG0_Type*) TIMG0_BASE) +#define TIMG1 ((TIMG0_Type*) TIMG1_BASE) +#define TRACE0 ((TRACE0_Type*) TRACE0_BASE) +#define TRACE1 ((TRACE0_Type*) TRACE1_BASE) +#define LP_TSENS ((LP_TSENS_Type*) LP_TSENS_BASE) +#define TWAI0 ((TWAI0_Type*) TWAI0_BASE) +#define TWAI1 ((TWAI0_Type*) TWAI1_BASE) +#define TWAI2 ((TWAI0_Type*) TWAI2_BASE) +#define UART0 ((UART0_Type*) UART0_BASE) +#define UART1 ((UART0_Type*) UART1_BASE) +#define UART2 ((UART0_Type*) UART2_BASE) +#define UART3 ((UART0_Type*) UART3_BASE) +#define UART4 ((UART0_Type*) UART4_BASE) +#define UHCI0 ((UHCI0_Type*) UHCI0_BASE) +#define USB_DEVICE ((USB_DEVICE_Type*) USB_DEVICE_BASE) +#define USB_WRAP ((USB_WRAP_Type*) USB_WRAP_BASE) + + +#ifdef __cplusplus +} +#endif + +#endif /* ESP32_P4_H */ diff --git a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/esp32p4.svd b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/esp32p4.svd new file mode 100644 index 000000000..e805dcf66 --- /dev/null +++ b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/esp32p4.svd @@ -0,0 +1,133701 @@ + + + ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD. + ESPRESSIF + ESP32-P4 + ESP32 P-Series + 2 + 32-bit RISC-V MCU + Copyright 2024 Espressif Systems (Shanghai) PTE LTD + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + + RV32IMAFC + r0p0 + little + false + true + 0 + false + + 32 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADC + ADC (Analog to Digital Converter) + ADC + 0x500DE000 + + 0x0 + 0x7C + registers + + + + CTRL + Register + 0x0 + 0x20 + 0x403FC120 + + + START_FORCE + need_des + 0 + 1 + read-write + + + START + need_des + 1 + 1 + read-write + + + WORK_MODE + 0: single mode, 1: double mode, 2: alternate mode + 2 + 2 + read-write + + + SAR_SEL + 0: SAR1, 1: SAR2, only work for single SAR mode + 4 + 1 + read-write + + + SAR_CLK_GATED + need_des + 5 + 1 + read-write + + + SAR_CLK_DIV + SAR clock divider + 6 + 8 + read-write + + + SAR1_PATT_LEN + 0 ~ 15 means length 1 ~ 16 + 14 + 4 + read-write + + + SAR2_PATT_LEN + 0 ~ 15 means length 1 ~ 16 + 18 + 4 + read-write + + + SAR1_PATT_P_CLEAR + clear the pointer of pattern table for DIG ADC1 CTRL + 22 + 1 + read-write + + + SAR2_PATT_P_CLEAR + clear the pointer of pattern table for DIG ADC2 CTRL + 23 + 1 + read-write + + + DATA_SAR_SEL + 1: sar_sel will be coded by the MSB of the 16-bit output data, in this case the resolution should not be larger than 11 bits. + 24 + 1 + read-write + + + DATA_TO_I2S + 1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix + 25 + 1 + read-write + + + XPD_SAR1_FORCE + force option to xpd sar1 blocks + 26 + 2 + read-write + + + XPD_SAR2_FORCE + force option to xpd sar2 blocks + 28 + 2 + read-write + + + WAIT_ARB_CYCLE + wait arbit signal stable after sar_done + 30 + 2 + read-write + + + + + CTRL2 + Register + 0x4 + 0x20 + 0x0000A1FE + + + MEAS_NUM_LIMIT + need_des + 0 + 1 + read-write + + + MAX_MEAS_NUM + max conversion number + 1 + 8 + read-write + + + SAR1_INV + 1: data to DIG ADC1 CTRL is inverted, otherwise not + 9 + 1 + read-write + + + SAR2_INV + 1: data to DIG ADC2 CTRL is inverted, otherwise not + 10 + 1 + read-write + + + TIMER_SEL + 1: select saradc timer 0: i2s_ws trigger + 11 + 1 + read-write + + + TIMER_TARGET + to set saradc timer target + 12 + 12 + read-write + + + TIMER_EN + to enable saradc timer trigger + 24 + 1 + read-write + + + + + FILTER_CTRL1 + Register + 0x8 + 0x20 + + + FILTER_FACTOR1 + need_des + 26 + 3 + read-write + + + FILTER_FACTOR0 + need_des + 29 + 3 + read-write + + + + + FSM_WAIT + Register + 0xC + 0x20 + 0x00FF0808 + + + XPD_WAIT + need_des + 0 + 8 + read-write + + + RSTB_WAIT + need_des + 8 + 8 + read-write + + + STANDBY_WAIT + need_des + 16 + 8 + read-write + + + + + SAR1_STATUS + Register + 0x10 + 0x20 + + + SAR1_STATUS + 0 + 32 + read-only + + + + + SAR2_STATUS + Register + 0x14 + 0x20 + + + SAR2_STATUS + 0 + 32 + read-only + + + + + SAR1_PATT_TAB1 + Register + 0x18 + 0x20 + + + SAR1_PATT_TAB1 + item 0 ~ 3 for pattern table 1 (each item one byte) + 0 + 24 + read-write + + + + + SAR1_PATT_TAB2 + Register + 0x1C + 0x20 + + + SAR1_PATT_TAB2 + Item 4 ~ 7 for pattern table 1 (each item one byte) + 0 + 24 + read-write + + + + + SAR1_PATT_TAB3 + Register + 0x20 + 0x20 + + + SAR1_PATT_TAB3 + Item 8 ~ 11 for pattern table 1 (each item one byte) + 0 + 24 + read-write + + + + + SAR1_PATT_TAB4 + Register + 0x24 + 0x20 + + + SAR1_PATT_TAB4 + Item 12 ~ 15 for pattern table 1 (each item one byte) + 0 + 24 + read-write + + + + + SAR2_PATT_TAB1 + Register + 0x28 + 0x20 + + + SAR2_PATT_TAB1 + item 0 ~ 3 for pattern table 2 (each item one byte) + 0 + 24 + read-write + + + + + SAR2_PATT_TAB2 + Register + 0x2C + 0x20 + + + SAR2_PATT_TAB2 + Item 4 ~ 7 for pattern table 2 (each item one byte) + 0 + 24 + read-write + + + + + SAR2_PATT_TAB3 + Register + 0x30 + 0x20 + + + SAR2_PATT_TAB3 + Item 8 ~ 11 for pattern table 2 (each item one byte) + 0 + 24 + read-write + + + + + SAR2_PATT_TAB4 + Register + 0x34 + 0x20 + + + SAR2_PATT_TAB4 + Item 12 ~ 15 for pattern table 2 (each item one byte) + 0 + 24 + read-write + + + + + ARB_CTRL + Register + 0x38 + 0x20 + 0x00000900 + + + ARB_APB_FORCE + adc2 arbiter force to enableapb controller + 2 + 1 + read-write + + + ARB_RTC_FORCE + adc2 arbiter force to enable rtc controller + 3 + 1 + read-write + + + ARB_WIFI_FORCE + adc2 arbiter force to enable wifi controller + 4 + 1 + read-write + + + ARB_GRANT_FORCE + adc2 arbiter force grant + 5 + 1 + read-write + + + ARB_APB_PRIORITY + Set adc2 arbiterapb priority + 6 + 2 + read-write + + + ARB_RTC_PRIORITY + Set adc2 arbiter rtc priority + 8 + 2 + read-write + + + ARB_WIFI_PRIORITY + Set adc2 arbiter wifi priority + 10 + 2 + read-write + + + ARB_FIX_PRIORITY + adc2 arbiter uses fixed priority + 12 + 1 + read-write + + + + + FILTER_CTRL0 + Register + 0x3C + 0x20 + 0x006B4000 + + + FILTER_CHANNEL1 + need_des + 14 + 5 + read-write + + + FILTER_CHANNEL0 + apb_adc1_filter_factor + 19 + 5 + read-write + + + FILTER_RESET + enable apb_adc1_filter + 31 + 1 + read-write + + + + + SAR1_DATA_STATUS + Register + 0x40 + 0x20 + + + APB_SARADC1_DATA + need_des + 0 + 17 + read-only + + + + + THRES0_CTRL + Register + 0x44 + 0x20 + 0x0003FFED + + + THRES0_CHANNEL + need_des + 0 + 5 + read-write + + + THRES0_HIGH + saradc1's thres0 monitor thres + 5 + 13 + read-write + + + THRES0_LOW + saradc1's thres0 monitor thres + 18 + 13 + read-write + + + + + THRES1_CTRL + Register + 0x48 + 0x20 + 0x0003FFED + + + THRES1_CHANNEL + need_des + 0 + 5 + read-write + + + THRES1_HIGH + saradc1's thres0 monitor thres + 5 + 13 + read-write + + + THRES1_LOW + saradc1's thres0 monitor thres + 18 + 13 + read-write + + + + + THRES_CTRL + Register + 0x4C + 0x20 + + + THRES_ALL_EN + need_des + 27 + 1 + read-write + + + THRES3_EN + need_des + 28 + 1 + read-write + + + THRES2_EN + need_des + 29 + 1 + read-write + + + THRES1_EN + need_des + 30 + 1 + read-write + + + THRES0_EN + need_des + 31 + 1 + read-write + + + + + INT_ENA + Register + 0x50 + 0x20 + + + THRES1_LOW_INT_ENA + need_des + 26 + 1 + read-write + + + THRES0_LOW_INT_ENA + need_des + 27 + 1 + read-write + + + THRES1_HIGH_INT_ENA + need_des + 28 + 1 + read-write + + + THRES0_HIGH_INT_ENA + need_des + 29 + 1 + read-write + + + SAR2_DONE_INT_ENA + need_des + 30 + 1 + read-write + + + SAR1_DONE_INT_ENA + need_des + 31 + 1 + read-write + + + + + INT_RAW + Register + 0x54 + 0x20 + + + THRES1_LOW_INT_RAW + need_des + 26 + 1 + read-write + + + THRES0_LOW_INT_RAW + need_des + 27 + 1 + read-write + + + THRES1_HIGH_INT_RAW + need_des + 28 + 1 + read-write + + + THRES0_HIGH_INT_RAW + need_des + 29 + 1 + read-write + + + SAR2_DONE_INT_RAW + need_des + 30 + 1 + read-write + + + SAR1_DONE_INT_RAW + need_des + 31 + 1 + read-write + + + + + INT_ST + Register + 0x58 + 0x20 + + + THRES1_LOW_INT_ST + need_des + 26 + 1 + read-only + + + THRES0_LOW_INT_ST + need_des + 27 + 1 + read-only + + + THRES1_HIGH_INT_ST + need_des + 28 + 1 + read-only + + + THRES0_HIGH_INT_ST + need_des + 29 + 1 + read-only + + + APB_SARADC2_DONE_INT_ST + need_des + 30 + 1 + read-only + + + APB_SARADC1_DONE_INT_ST + need_des + 31 + 1 + read-only + + + + + INT_CLR + Register + 0x5C + 0x20 + + + THRES1_LOW_INT_CLR + need_des + 26 + 1 + write-only + + + THRES0_LOW_INT_CLR + need_des + 27 + 1 + write-only + + + THRES1_HIGH_INT_CLR + need_des + 28 + 1 + write-only + + + THRES0_HIGH_INT_CLR + need_des + 29 + 1 + write-only + + + APB_SARADC2_DONE_INT_CLR + need_des + 30 + 1 + write-only + + + APB_SARADC1_DONE_INT_CLR + need_des + 31 + 1 + write-only + + + + + DMA_CONF + Register + 0x60 + 0x20 + 0x000000FF + + + APB_ADC_EOF_NUM + the dma_in_suc_eof gen when sample cnt = spi_eof_num + 0 + 16 + read-write + + + APB_ADC_RESET_FSM + reset_apb_adc_state + 30 + 1 + read-write + + + APB_ADC_TRANS + enable apb_adc use spi_dma + 31 + 1 + read-write + + + + + SAR2_DATA_STATUS + Register + 0x64 + 0x20 + + + APB_SARADC2_DATA + need_des + 0 + 17 + read-only + + + + + CALI + Register + 0x68 + 0x20 + 0x00008000 + + + CFG + need_des + 0 + 17 + read-write + + + + + RND_ECO_LOW + Register + 0x6C + 0x20 + + + RND_ECO_LOW + rnd eco low + 0 + 32 + read-write + + + + + RND_ECO_HIGH + Register + 0x70 + 0x20 + 0xFFFFFFFF + + + RND_ECO_HIGH + rnd eco high + 0 + 32 + read-write + + + + + RND_ECO_CS + Register + 0x74 + 0x20 + + + RND_ECO_EN + need_des + 0 + 1 + read-write + + + RND_ECO_RESULT + need_des + 1 + 1 + read-only + + + + + CTRL_DATE + Register + 0x3FC + 0x20 + 0x02212260 + + + CTRL_DATE + need_des + 0 + 31 + read-write + + + CLK_EN + need_des + 31 + 1 + read-write + + + + + + + AES + AES (Advanced Encryption Standard) Accelerator + AES + 0x50090000 + + 0x0 + 0xBC + registers + + + AES + 69 + + + + KEY_0 + Key material key_0 configure register + 0x0 + 0x20 + + + KEY_0 + This bits stores key_0 that is a part of key material. + 0 + 32 + read-write + + + + + KEY_1 + Key material key_1 configure register + 0x4 + 0x20 + + + KEY_1 + This bits stores key_1 that is a part of key material. + 0 + 32 + read-write + + + + + KEY_2 + Key material key_2 configure register + 0x8 + 0x20 + + + KEY_2 + This bits stores key_2 that is a part of key material. + 0 + 32 + read-write + + + + + KEY_3 + Key material key_3 configure register + 0xC + 0x20 + + + KEY_3 + This bits stores key_3 that is a part of key material. + 0 + 32 + read-write + + + + + KEY_4 + Key material key_4 configure register + 0x10 + 0x20 + + + KEY_4 + This bits stores key_4 that is a part of key material. + 0 + 32 + read-write + + + + + KEY_5 + Key material key_5 configure register + 0x14 + 0x20 + + + KEY_5 + This bits stores key_5 that is a part of key material. + 0 + 32 + read-write + + + + + KEY_6 + Key material key_6 configure register + 0x18 + 0x20 + + + KEY_6 + This bits stores key_6 that is a part of key material. + 0 + 32 + read-write + + + + + KEY_7 + Key material key_7 configure register + 0x1C + 0x20 + + + KEY_7 + This bits stores key_7 that is a part of key material. + 0 + 32 + read-write + + + + + TEXT_IN_0 + source text material text_in_0 configure register + 0x20 + 0x20 + + + TEXT_IN_0 + This bits stores text_in_0 that is a part of source text material. + 0 + 32 + read-write + + + + + TEXT_IN_1 + source text material text_in_1 configure register + 0x24 + 0x20 + + + TEXT_IN_1 + This bits stores text_in_1 that is a part of source text material. + 0 + 32 + read-write + + + + + TEXT_IN_2 + source text material text_in_2 configure register + 0x28 + 0x20 + + + TEXT_IN_2 + This bits stores text_in_2 that is a part of source text material. + 0 + 32 + read-write + + + + + TEXT_IN_3 + source text material text_in_3 configure register + 0x2C + 0x20 + + + TEXT_IN_3 + This bits stores text_in_3 that is a part of source text material. + 0 + 32 + read-write + + + + + TEXT_OUT_0 + result text material text_out_0 configure register + 0x30 + 0x20 + + + TEXT_OUT_0 + This bits stores text_out_0 that is a part of result text material. + 0 + 32 + read-write + + + + + TEXT_OUT_1 + result text material text_out_1 configure register + 0x34 + 0x20 + + + TEXT_OUT_1 + This bits stores text_out_1 that is a part of result text material. + 0 + 32 + read-write + + + + + TEXT_OUT_2 + result text material text_out_2 configure register + 0x38 + 0x20 + + + TEXT_OUT_2 + This bits stores text_out_2 that is a part of result text material. + 0 + 32 + read-write + + + + + TEXT_OUT_3 + result text material text_out_3 configure register + 0x3C + 0x20 + + + TEXT_OUT_3 + This bits stores text_out_3 that is a part of result text material. + 0 + 32 + read-write + + + + + MODE + AES Mode register + 0x40 + 0x20 + + + MODE + This bits decides which one operation mode will be used. 3'd0: AES-EN-128, 3'd1: AES-EN-192, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: AES-DE-192, 3'd6: AES-DE-256. + 0 + 3 + read-write + + + + + ENDIAN + AES Endian configure register + 0x44 + 0x20 + + + ENDIAN + endian. [1:0] key endian, [3:2] text_in endian or in_stream endian, [5:4] text_out endian or out_stream endian + 0 + 6 + read-write + + + + + TRIGGER + AES trigger register + 0x48 + 0x20 + + + TRIGGER + Set this bit to start AES calculation. + 0 + 1 + write-only + + + + + STATE + AES state register + 0x4C + 0x20 + + + STATE + Those bits shows AES status. For typical AES, 0: idle, 1: busy. For DMA-AES, 0: idle, 1: busy, 2: calculation_done. + 0 + 2 + read-only + + + + + 4 + 0x4 + IV_MEM[%s] + The memory that stores initialization vector + 0x50 + 0x20 + + + 4 + 0x4 + H_MEM[%s] + The memory that stores GCM hash subkey + 0x60 + 0x20 + + + 4 + 0x4 + J0_MEM[%s] + The memory that stores J0 + 0x70 + 0x20 + + + 4 + 0x4 + T0_MEM[%s] + The memory that stores T0 + 0x80 + 0x20 + + + DMA_ENABLE + DMA-AES working mode register + 0x90 + 0x20 + + + DMA_ENABLE + 1'b0: typical AES working mode, 1'b1: DMA-AES working mode. + 0 + 1 + read-write + + + + + BLOCK_MODE + AES cipher block mode register + 0x94 + 0x20 + + + BLOCK_MODE + Those bits decides which block mode will be used. 0x0: ECB, 0x1: CBC, 0x2: OFB, 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: GCM, 0x7: reserved. + 0 + 3 + read-write + + + + + BLOCK_NUM + AES block number register + 0x98 + 0x20 + + + BLOCK_NUM + Those bits stores the number of Plaintext/ciphertext block. + 0 + 32 + read-write + + + + + INC_SEL + Standard incrementing function configure register + 0x9C + 0x20 + + + INC_SEL + This bit decides the standard incrementing function. 0: INC32. 1: INC128. + 0 + 1 + read-write + + + + + AAD_BLOCK_NUM + Additional Authential Data block number register + 0xA0 + 0x20 + + + AAD_BLOCK_NUM + Those bits stores the number of AAD block. + 0 + 32 + read-write + + + + + REMAINDER_BIT_NUM + AES remainder bit number register + 0xA4 + 0x20 + + + REMAINDER_BIT_NUM + Those bits stores the number of remainder bit. + 0 + 7 + read-write + + + + + CONTINUE + AES continue register + 0xA8 + 0x20 + + + CONTINUE + Set this bit to continue GCM operation. + 0 + 1 + write-only + + + + + INT_CLEAR + AES Interrupt clear register + 0xAC + 0x20 + + + INT_CLEAR + Set this bit to clear the AES interrupt. + 0 + 1 + write-only + + + + + INT_ENA + AES Interrupt enable register + 0xB0 + 0x20 + + + INT_ENA + Set this bit to enable interrupt that occurs when DMA-AES calculation is done. + 0 + 1 + read-write + + + + + DATE + AES version control register + 0xB4 + 0x20 + 0x20191210 + + + DATE + This bits stores the version information of AES. + 0 + 30 + read-write + + + + + DMA_EXIT + AES-DMA exit config + 0xB8 + 0x20 + + + DMA_EXIT + Set this register to leave calculation done stage. Recommend to use it after software finishes reading DMA's output buffer. + 0 + 1 + write-only + + + + + + + AHB_DMA + AHB_DMA Peripheral + AHB_DMA + 0x50085000 + + 0x0 + 0x2C4 + registers + + + AHB_PDMA_IN_CH0 + 56 + + + AHB_PDMA_IN_CH1 + 57 + + + AHB_PDMA_IN_CH2 + 58 + + + AHB_PDMA_OUT_CH0 + 59 + + + AHB_PDMA_OUT_CH1 + 60 + + + AHB_PDMA_OUT_CH2 + 61 + + + AXI_PDMA_IN_CH0 + 62 + + + AXI_PDMA_IN_CH1 + 63 + + + AXI_PDMA_IN_CH2 + 64 + + + AXI_PDMA_OUT_CH0 + 65 + + + AXI_PDMA_OUT_CH1 + 66 + + + AXI_PDMA_OUT_CH2 + 67 + + + + 3 + 0x10 + IN_INT_RAW_CH%s + Raw status interrupt of channel 0 + 0x0 + 0x20 + + + IN_DONE_CH_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. + 0 + 1 + read-write + + + IN_SUC_EOF_CH_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0. + 1 + 1 + read-write + + + IN_ERR_EOF_CH_INT_RAW + The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw interrupt is reserved. + 2 + 1 + read-write + + + IN_DSCR_ERR_CH_INT_RAW + The raw interrupt bit turns to high level when detecting inlink descriptor error including owner error and the second and third word error of inlink descriptor for Rx channel 0. + 3 + 1 + read-write + + + IN_DSCR_EMPTY_CH_INT_RAW + The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed but there is no more inlink for Rx channel 0. + 4 + 1 + read-write + + + INFIFO_OVF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow. + 5 + 1 + read-write + + + INFIFO_UDF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow. + 6 + 1 + read-write + + + + + 3 + 0x10 + IN_INT_ST_CH%s + Masked interrupt of channel 0 + 0x4 + 0x20 + + + IN_DONE_CH_INT_ST + The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-only + + + IN_SUC_EOF_CH_INT_ST + The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-only + + + IN_ERR_EOF_CH_INT_ST + The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + read-only + + + IN_DSCR_ERR_CH_INT_ST + The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 + read-only + + + IN_DSCR_EMPTY_CH_INT_ST + The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + 4 + 1 + read-only + + + INFIFO_OVF_CH_INT_ST + The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + 5 + 1 + read-only + + + INFIFO_UDF_CH_INT_ST + The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + 6 + 1 + read-only + + + + + 3 + 0x10 + IN_INT_ENA_CH%s + Interrupt enable bits of channel 0 + 0x8 + 0x20 + + + IN_DONE_CH_INT_ENA + The interrupt enable bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-write + + + IN_SUC_EOF_CH_INT_ENA + The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-write + + + IN_ERR_EOF_CH_INT_ENA + The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + read-write + + + IN_DSCR_ERR_CH_INT_ENA + The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 + read-write + + + IN_DSCR_EMPTY_CH_INT_ENA + The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + 4 + 1 + read-write + + + INFIFO_OVF_CH_INT_ENA + The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + 5 + 1 + read-write + + + INFIFO_UDF_CH_INT_ENA + The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + 6 + 1 + read-write + + + + + 3 + 0x10 + IN_INT_CLR_CH%s + Interrupt clear bits of channel 0 + 0xC + 0x20 + + + IN_DONE_CH_INT_CLR + Set this bit to clear the IN_DONE_CH_INT interrupt. + 0 + 1 + write-only + + + IN_SUC_EOF_CH_INT_CLR + Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + write-only + + + IN_ERR_EOF_CH_INT_CLR + Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + write-only + + + IN_DSCR_ERR_CH_INT_CLR + Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 + write-only + + + IN_DSCR_EMPTY_CH_INT_CLR + Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + 4 + 1 + write-only + + + INFIFO_OVF_CH_INT_CLR + Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + 5 + 1 + write-only + + + INFIFO_UDF_CH_INT_CLR + Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + 6 + 1 + write-only + + + + + 3 + 0x10 + OUT_INT_RAW_CH%s + Raw status interrupt of channel 0 + 0x30 + 0x20 + + + OUT_DONE_CH_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0. + 0 + 1 + read-write + + + OUT_EOF_CH_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. + 1 + 1 + read-write + + + OUT_DSCR_ERR_CH_INT_RAW + The raw interrupt bit turns to high level when detecting outlink descriptor error including owner error and the second and third word error of outlink descriptor for Tx channel 0. + 2 + 1 + read-write + + + OUT_TOTAL_EOF_CH_INT_RAW + The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0. + 3 + 1 + read-write + + + OUTFIFO_OVF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow. + 4 + 1 + read-write + + + OUTFIFO_UDF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow. + 5 + 1 + read-write + + + + + 3 + 0x10 + OUT_INT_ST_CH%s + Masked interrupt of channel 0 + 0x34 + 0x20 + + + OUT_DONE_CH_INT_ST + The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + 0 + 1 + read-only + + + OUT_EOF_CH_INT_ST + The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + 1 + 1 + read-only + + + OUT_DSCR_ERR_CH_INT_ST + The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + read-only + + + OUT_TOTAL_EOF_CH_INT_ST + The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + read-only + + + OUTFIFO_OVF_CH_INT_ST + The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-only + + + OUTFIFO_UDF_CH_INT_ST + The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-only + + + + + 3 + 0x10 + OUT_INT_ENA_CH%s + Interrupt enable bits of channel 0 + 0x38 + 0x20 + + + OUT_DONE_CH_INT_ENA + The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + 0 + 1 + read-write + + + OUT_EOF_CH_INT_ENA + The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + 1 + 1 + read-write + + + OUT_DSCR_ERR_CH_INT_ENA + The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + read-write + + + OUT_TOTAL_EOF_CH_INT_ENA + The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + read-write + + + OUTFIFO_OVF_CH_INT_ENA + The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-write + + + OUTFIFO_UDF_CH_INT_ENA + The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-write + + + + + 3 + 0x10 + OUT_INT_CLR_CH%s + Interrupt clear bits of channel 0 + 0x3C + 0x20 + + + OUT_DONE_CH_INT_CLR + Set this bit to clear the OUT_DONE_CH_INT interrupt. + 0 + 1 + write-only + + + OUT_EOF_CH_INT_CLR + Set this bit to clear the OUT_EOF_CH_INT interrupt. + 1 + 1 + write-only + + + OUT_DSCR_ERR_CH_INT_CLR + Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + write-only + + + OUT_TOTAL_EOF_CH_INT_CLR + Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + write-only + + + OUTFIFO_OVF_CH_INT_CLR + Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + write-only + + + OUTFIFO_UDF_CH_INT_CLR + Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + write-only + + + + + AHB_TEST + reserved + 0x60 + 0x20 + + + AHB_TESTMODE + reserved + 0 + 3 + read-write + + + AHB_TESTADDR + reserved + 4 + 2 + read-write + + + + + MISC_CONF + MISC register + 0x64 + 0x20 + + + AHBM_RST_INTER + Set this bit then clear this bit to reset the internal ahb FSM. + 0 + 1 + read-write + + + ARB_PRI_DIS + Set this bit to disable priority arbitration function. + 2 + 1 + read-write + + + CLK_EN + 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers. + 3 + 1 + read-write + + + + + DATE + Version control register + 0x68 + 0x20 + 0x02303140 + + + DATE + register version. + 0 + 32 + read-write + + + + + 3 + 0xC0 + IN_CONF0_CH%s + Configure 0 register of Rx channel 0 + 0x70 + 0x20 + + + IN_RST_CH + This bit is used to reset AHB_DMA channel 0 Rx FSM and Rx FIFO pointer. + 0 + 1 + read-write + + + IN_LOOP_TEST_CH + reserved + 1 + 1 + read-write + + + INDSCR_BURST_EN_CH + Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM. + 2 + 1 + read-write + + + IN_DATA_BURST_EN_CH + Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM. + 3 + 1 + read-write + + + MEM_TRANS_EN_CH + Set this bit 1 to enable automatic transmitting data from memory to memory via AHB_DMA. + 4 + 1 + read-write + + + IN_ETM_EN_CH + Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm task. + 5 + 1 + read-write + + + + + 3 + 0xC0 + IN_CONF1_CH%s + Configure 1 register of Rx channel 0 + 0x74 + 0x20 + + + IN_CHECK_OWNER_CH + Set this bit to enable checking the owner attribute of the link descriptor. + 12 + 1 + read-write + + + + + 3 + 0xC0 + INFIFO_STATUS_CH%s + Receive FIFO status of Rx channel 0 + 0x78 + 0x20 + 0x07800003 + + + INFIFO_FULL_CH + L1 Rx FIFO full signal for Rx channel 0. + 0 + 1 + read-only + + + INFIFO_EMPTY_CH + L1 Rx FIFO empty signal for Rx channel 0. + 1 + 1 + read-only + + + INFIFO_CNT_CH + The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0. + 2 + 6 + read-only + + + IN_REMAIN_UNDER_1B_CH + reserved + 23 + 1 + read-only + + + IN_REMAIN_UNDER_2B_CH + reserved + 24 + 1 + read-only + + + IN_REMAIN_UNDER_3B_CH + reserved + 25 + 1 + read-only + + + IN_REMAIN_UNDER_4B_CH + reserved + 26 + 1 + read-only + + + IN_BUF_HUNGRY_CH + reserved + 27 + 1 + read-only + + + + + 3 + 0xC0 + IN_POP_CH%s + Pop control register of Rx channel 0 + 0x7C + 0x20 + 0x00000800 + + + INFIFO_RDATA_CH + This register stores the data popping from AHB_DMA FIFO. + 0 + 12 + read-only + + + INFIFO_POP_CH + Set this bit to pop data from AHB_DMA FIFO. + 12 + 1 + write-only + + + + + 3 + 0xC0 + IN_LINK_CH%s + Link descriptor configure and control register of Rx channel 0 + 0x80 + 0x20 + 0x00000011 + + + INLINK_AUTO_RET_CH + Set this bit to return to current inlink descriptor's address when there are some errors in current receiving data. + 0 + 1 + read-write + + + INLINK_STOP_CH + Set this bit to stop dealing with the inlink descriptors. + 1 + 1 + write-only + + + INLINK_START_CH + Set this bit to start dealing with the inlink descriptors. + 2 + 1 + write-only + + + INLINK_RESTART_CH + Set this bit to mount a new inlink descriptor. + 3 + 1 + write-only + + + INLINK_PARK_CH + 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. + 4 + 1 + read-only + + + + + 3 + 0xC0 + IN_STATE_CH%s + Receive status of Rx channel 0 + 0x84 + 0x20 + + + INLINK_DSCR_ADDR_CH + This register stores the current inlink descriptor's address. + 0 + 18 + read-only + + + IN_DSCR_STATE_CH + reserved + 18 + 2 + read-only + + + IN_STATE_CH + reserved + 20 + 3 + read-only + + + + + 3 + 0xC0 + IN_SUC_EOF_DES_ADDR_CH%s + Inlink descriptor address when EOF occurs of Rx channel 0 + 0x88 + 0x20 + + + IN_SUC_EOF_DES_ADDR_CH + This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. + 0 + 32 + read-only + + + + + 3 + 0xC0 + IN_ERR_EOF_DES_ADDR_CH%s + Inlink descriptor address when errors occur of Rx channel 0 + 0x8C + 0x20 + + + IN_ERR_EOF_DES_ADDR_CH + This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0. + 0 + 32 + read-only + + + + + 3 + 0xC0 + IN_DSCR_CH%s + Current inlink descriptor address of Rx channel 0 + 0x90 + 0x20 + + + INLINK_DSCR_CH + The address of the current inlink descriptor x. + 0 + 32 + read-only + + + + + 3 + 0xC0 + IN_DSCR_BF0_CH%s + The last inlink descriptor address of Rx channel 0 + 0x94 + 0x20 + + + INLINK_DSCR_BF0_CH + The address of the last inlink descriptor x-1. + 0 + 32 + read-only + + + + + 3 + 0xC0 + IN_DSCR_BF1_CH%s + The second-to-last inlink descriptor address of Rx channel 0 + 0x98 + 0x20 + + + INLINK_DSCR_BF1_CH + The address of the second-to-last inlink descriptor x-2. + 0 + 32 + read-only + + + + + 3 + 0xC0 + IN_PRI_CH%s + Priority register of Rx channel 0 + 0x9C + 0x20 + + + RX_PRI_CH + The priority of Rx channel 0. The larger of the value the higher of the priority. + 0 + 4 + read-write + + + + + 3 + 0xC0 + IN_PERI_SEL_CH%s + Peripheral selection of Rx channel 0 + 0xA0 + 0x20 + 0x0000003F + + + PERI_IN_SEL_CH + This register is used to select peripheral for Rx channel 0. I3C. 1: Dummy. 2: UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: Dummy. 7: Dummy. 8: ADC_DAC. 9: Dummy. 10: RMT,11~15: Dummy + 0 + 6 + read-write + + + + + OUT_CONF0_CH0 + Configure 0 register of Tx channel 0 + 0xD0 + 0x20 + 0x00000008 + + + OUT_RST_CH0 + This bit is used to reset AHB_DMA channel 0 Tx FSM and Tx FIFO pointer. + 0 + 1 + read-write + + + OUT_LOOP_TEST_CH0 + reserved + 1 + 1 + read-write + + + OUT_AUTO_WRBACK_CH0 + Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted. + 2 + 1 + read-write + + + OUT_EOF_MODE_CH0 + EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in AHB_DMA + 3 + 1 + read-write + + + OUTDSCR_BURST_EN_CH0 + Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. + 4 + 1 + read-write + + + OUT_DATA_BURST_EN_CH0 + Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM. + 5 + 1 + read-write + + + OUT_ETM_EN_CH0 + Set this bit to 1 to enable etm control mode, dma Tx channel 0 is triggered by etm task. + 6 + 1 + read-write + + + + + 3 + 0xC0 + OUT_CONF1_CH%s + Configure 1 register of Tx channel 0 + 0xD4 + 0x20 + + + OUT_CHECK_OWNER_CH + Set this bit to enable checking the owner attribute of the link descriptor. + 12 + 1 + read-write + + + + + 3 + 0xC0 + OUTFIFO_STATUS_CH%s + Transmit FIFO status of Tx channel 0 + 0xD8 + 0x20 + 0x07800002 + + + OUTFIFO_FULL_CH + L1 Tx FIFO full signal for Tx channel 0. + 0 + 1 + read-only + + + OUTFIFO_EMPTY_CH + L1 Tx FIFO empty signal for Tx channel 0. + 1 + 1 + read-only + + + OUTFIFO_CNT_CH + The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0. + 2 + 6 + read-only + + + OUT_REMAIN_UNDER_1B_CH + reserved + 23 + 1 + read-only + + + OUT_REMAIN_UNDER_2B_CH + reserved + 24 + 1 + read-only + + + OUT_REMAIN_UNDER_3B_CH + reserved + 25 + 1 + read-only + + + OUT_REMAIN_UNDER_4B_CH + reserved + 26 + 1 + read-only + + + + + 3 + 0xC0 + OUT_PUSH_CH%s + Push control register of Rx channel 0 + 0xDC + 0x20 + + + OUTFIFO_WDATA_CH + This register stores the data that need to be pushed into AHB_DMA FIFO. + 0 + 9 + read-write + + + OUTFIFO_PUSH_CH + Set this bit to push data into AHB_DMA FIFO. + 9 + 1 + write-only + + + + + 3 + 0xC0 + OUT_LINK_CH%s + Link descriptor configure and control register of Tx channel 0 + 0xE0 + 0x20 + 0x00000008 + + + OUTLINK_STOP_CH + Set this bit to stop dealing with the outlink descriptors. + 0 + 1 + write-only + + + OUTLINK_START_CH + Set this bit to start dealing with the outlink descriptors. + 1 + 1 + write-only + + + OUTLINK_RESTART_CH + Set this bit to restart a new outlink from the last address. + 2 + 1 + write-only + + + OUTLINK_PARK_CH + 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. + 3 + 1 + read-only + + + + + 3 + 0xC0 + OUT_STATE_CH%s + Transmit status of Tx channel 0 + 0xE4 + 0x20 + + + OUTLINK_DSCR_ADDR_CH + This register stores the current outlink descriptor's address. + 0 + 18 + read-only + + + OUT_DSCR_STATE_CH + reserved + 18 + 2 + read-only + + + OUT_STATE_CH + reserved + 20 + 3 + read-only + + + + + 3 + 0xC0 + OUT_EOF_DES_ADDR_CH%s + Outlink descriptor address when EOF occurs of Tx channel 0 + 0xE8 + 0x20 + + + OUT_EOF_DES_ADDR_CH + This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1. + 0 + 32 + read-only + + + + + 3 + 0xC0 + OUT_EOF_BFR_DES_ADDR_CH%s + The last outlink descriptor address when EOF occurs of Tx channel 0 + 0xEC + 0x20 + + + OUT_EOF_BFR_DES_ADDR_CH + This register stores the address of the outlink descriptor before the last outlink descriptor. + 0 + 32 + read-only + + + + + 3 + 0xC0 + OUT_DSCR_CH%s + Current inlink descriptor address of Tx channel 0 + 0xF0 + 0x20 + + + OUTLINK_DSCR_CH + The address of the current outlink descriptor y. + 0 + 32 + read-only + + + + + 3 + 0xC0 + OUT_DSCR_BF0_CH%s + The last inlink descriptor address of Tx channel 0 + 0xF4 + 0x20 + + + OUTLINK_DSCR_BF0_CH + The address of the last outlink descriptor y-1. + 0 + 32 + read-only + + + + + 3 + 0xC0 + OUT_DSCR_BF1_CH%s + The second-to-last inlink descriptor address of Tx channel 0 + 0xF8 + 0x20 + + + OUTLINK_DSCR_BF1_CH + The address of the second-to-last inlink descriptor x-2. + 0 + 32 + read-only + + + + + 3 + 0xC0 + OUT_PRI_CH%s + Priority register of Tx channel 0. + 0xFC + 0x20 + + + TX_PRI_CH + The priority of Tx channel 0. The larger of the value the higher of the priority. + 0 + 4 + read-write + + + + + 3 + 0xC0 + OUT_PERI_SEL_CH%s + Peripheral selection of Tx channel 0 + 0x100 + 0x20 + 0x0000003F + + + PERI_OUT_SEL_CH + This register is used to select peripheral for Tx channel 0. I3C. 1: Dummy. 2: UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: Dummy. 7: Dummy. 8: ADC_DAC. 9: Dummy. 10: RMT,11~15: Dummy + 0 + 6 + read-write + + + + + 2 + 0xC0 + OUT_CONF0_CH%s + Configure 0 register of Tx channel 1 + 0x190 + 0x20 + 0x00000008 + + + OUT_RST_CH + This bit is used to reset AHB_DMA channel 1 Tx FSM and Tx FIFO pointer. + 0 + 1 + read-write + + + OUT_LOOP_TEST_CH + reserved + 1 + 1 + read-write + + + OUT_AUTO_WRBACK_CH + Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted. + 2 + 1 + read-write + + + OUT_EOF_MODE_CH + EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 1 is generated when data need to transmit has been popped from FIFO in AHB_DMA + 3 + 1 + read-write + + + OUTDSCR_BURST_EN_CH + Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link descriptor when accessing internal SRAM. + 4 + 1 + read-write + + + OUT_DATA_BURST_EN_CH + Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting data when accessing internal SRAM. + 5 + 1 + read-write + + + OUT_ETM_EN_CH + Set this bit to 1 to enable etm control mode, dma Tx channel 1 is triggered by etm task. + 6 + 1 + read-write + + + + + 3 + 0x28 + OUT_CRC_INIT_DATA_CH%s + This register is used to config ch0 crc initial data(max 32 bit) + 0x2BC + 0x20 + 0xFFFFFFFF + + + OUT_CRC_INIT_DATA_CH + This register is used to config ch0 of tx crc initial value + 0 + 32 + read-write + + + + + 3 + 0x28 + TX_CRC_WIDTH_CH%s + This register is used to confiig tx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean 24<crc_width<=32 + 0x2C0 + 0x20 + + + TX_CRC_WIDTH_CH + reserved + 0 + 2 + read-write + + + TX_CRC_LAUTCH_FLGA_CH + reserved + 2 + 1 + read-write + + + + + 3 + 0x28 + OUT_CRC_CLEAR_CH%s + This register is used to clear ch0 crc result + 0x2C4 + 0x20 + + + OUT_CRC_CLEAR_CH + This register is used to clear ch0 of tx crc result + 0 + 1 + read-write + + + + + 3 + 0x28 + OUT_CRC_FINAL_RESULT_CH%s + This register is used to store ch0 crc result + 0x2C8 + 0x20 + + + OUT_CRC_FINAL_RESULT_CH + This register is used to store result ch0 of tx + 0 + 32 + read-only + + + + + 3 + 0x28 + TX_CRC_EN_WR_DATA_CH%s + This resister is used to config ch0 crc en for every bit + 0x2CC + 0x20 + + + TX_CRC_EN_WR_DATA_CH + This register is used to enable tx ch0 crc 32bit on/off + 0 + 32 + read-write + + + + + 3 + 0x28 + TX_CRC_EN_ADDR_CH%s + This register is used to config ch0 crc en addr + 0x2D0 + 0x20 + + + TX_CRC_EN_ADDR_CH + reserved + 0 + 32 + read-write + + + + + 3 + 0x28 + TX_CRC_DATA_EN_WR_DATA_CH%s + This register is used to config crc data_8bit en + 0x2D4 + 0x20 + + + TX_CRC_DATA_EN_WR_DATA_CH + reserved + 0 + 8 + read-write + + + + + 3 + 0x28 + TX_CRC_DATA_EN_ADDR_CH%s + This register is used to config addr of crc data_8bit en + 0x2D8 + 0x20 + + + TX_CRC_DATA_EN_ADDR_CH + reserved + 0 + 32 + read-write + + + + + 3 + 0x28 + TX_CH_ARB_WEIGH_CH%s + This register is used to config ch0 arbiter weigh + 0x2DC + 0x20 + + + TX_CH_ARB_WEIGH_CH + reserved + 0 + 4 + read-write + + + + + 3 + 0x28 + TX_ARB_WEIGH_OPT_DIR_CH%s + This register is used to config off or on weigh optimization + 0x2E0 + 0x20 + + + TX_ARB_WEIGH_OPT_DIR_CH + reserved + 0 + 1 + read-write + + + + + 3 + 0x28 + IN_CRC_INIT_DATA_CH%s + This register is used to config ch0 crc initial data(max 32 bit) + 0x334 + 0x20 + 0xFFFFFFFF + + + IN_CRC_INIT_DATA_CH + This register is used to config ch0 of rx crc initial value + 0 + 32 + read-write + + + + + 3 + 0x28 + RX_CRC_WIDTH_CH%s + This register is used to confiig rx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean 24<crc_width<=32 + 0x338 + 0x20 + + + RX_CRC_WIDTH_CH + reserved + 0 + 2 + read-write + + + RX_CRC_LAUTCH_FLGA_CH + reserved + 2 + 1 + read-write + + + + + 3 + 0x28 + IN_CRC_CLEAR_CH%s + This register is used to clear ch0 crc result + 0x33C + 0x20 + + + IN_CRC_CLEAR_CH + This register is used to clear ch0 of rx crc result + 0 + 1 + read-write + + + + + 3 + 0x28 + IN_CRC_FINAL_RESULT_CH%s + This register is used to store ch0 crc result + 0x340 + 0x20 + + + IN_CRC_FINAL_RESULT_CH + This register is used to store result ch0 of rx + 0 + 32 + read-only + + + + + 3 + 0x28 + RX_CRC_EN_WR_DATA_CH%s + This resister is used to config ch0 crc en for every bit + 0x344 + 0x20 + + + RX_CRC_EN_WR_DATA_CH + This register is used to enable rx ch0 crc 32bit on/off + 0 + 32 + read-write + + + + + 3 + 0x28 + RX_CRC_EN_ADDR_CH%s + This register is used to config ch0 crc en addr + 0x348 + 0x20 + + + RX_CRC_EN_ADDR_CH + reserved + 0 + 32 + read-write + + + + + 3 + 0x28 + RX_CRC_DATA_EN_WR_DATA_CH%s + This register is used to config crc data_8bit en + 0x34C + 0x20 + + + RX_CRC_DATA_EN_WR_DATA_CH + reserved + 0 + 8 + read-write + + + + + 3 + 0x28 + RX_CRC_DATA_EN_ADDR_CH%s + This register is used to config addr of crc data_8bit en + 0x350 + 0x20 + + + RX_CRC_DATA_EN_ADDR_CH + reserved + 0 + 32 + read-write + + + + + 3 + 0x28 + RX_CH_ARB_WEIGH_CH%s + This register is used to config ch0 arbiter weigh + 0x354 + 0x20 + + + RX_CH_ARB_WEIGH_CH + reserved + 0 + 4 + read-write + + + + + 3 + 0x28 + RX_ARB_WEIGH_OPT_DIR_CH%s + This register is used to config off or on weigh optimization + 0x358 + 0x20 + + + RX_ARB_WEIGH_OPT_DIR_CH + reserved + 0 + 1 + read-write + + + + + 3 + 0x4 + IN_LINK_ADDR_CH%s + Link descriptor configure of Rx channel 0 + 0x3AC + 0x20 + + + INLINK_ADDR_CH + This register stores the 32 least significant bits of the first inlink descriptor's address. + 0 + 32 + read-write + + + + + 3 + 0x4 + OUT_LINK_ADDR_CH%s + Link descriptor configure of Tx channel 0 + 0x3B8 + 0x20 + + + OUTLINK_ADDR_CH + This register stores the 32 least significant bits of the first outlink descriptor's address. + 0 + 32 + read-write + + + + + INTR_MEM_START_ADDR + The start address of accessible address space. + 0x3C4 + 0x20 + + + ACCESS_INTR_MEM_START_ADDR + The start address of accessible address space. + 0 + 32 + read-write + + + + + INTR_MEM_END_ADDR + The end address of accessible address space. The access address beyond this range would lead to descriptor error. + 0x3C8 + 0x20 + 0xFFFFFFFF + + + ACCESS_INTR_MEM_END_ADDR + The end address of accessible address space. The access address beyond this range would lead to descriptor error. + 0 + 32 + read-write + + + + + ARB_TIMEOUT_TX + This retister is used to config arbiter time slice for tx dir + 0x3CC + 0x20 + + + ARB_TIMEOUT_TX + This register is used to config arbiter time out value + 0 + 16 + read-write + + + + + ARB_TIMEOUT_RX + This retister is used to config arbiter time slice for rx dir + 0x3D0 + 0x20 + + + ARB_TIMEOUT_RX + This register is used to config arbiter time out value + 0 + 16 + read-write + + + + + WEIGHT_EN_TX + This register is used to config arbiter weigh function to on or off for tx dir + 0x3D4 + 0x20 + + + WEIGHT_EN_TX + This register is used to config arbiter weight function off/on + 0 + 1 + read-write + + + + + WEIGHT_EN_RX + This register is used to config arbiter weigh function to on or off for rx dir + 0x3D8 + 0x20 + + + WEIGHT_EN_RX + This register is used to config arbiter weight function off/on + 0 + 1 + read-write + + + + + + + LP_I2C_ANA_MST + LP_I2C_ANA_MST Peripheral + ANA_I2C_MST + 0x50124000 + + 0x0 + 0x3C + registers + + + + I2C0_CTRL + need des + 0x0 + 0x20 + + + I2C0_CTRL + need des + 0 + 25 + read-write + + + I2C0_BUSY + need des + 25 + 1 + read-only + + + + + I2C1_CTRL + need des + 0x4 + 0x20 + + + I2C1_CTRL + need des + 0 + 25 + read-write + + + I2C1_BUSY + need des + 25 + 1 + read-only + + + + + I2C0_CONF + need des + 0x8 + 0x20 + + + I2C0_CONF + need des + 0 + 24 + read-write + + + I2C0_STATUS + need des + 24 + 8 + read-only + + + + + I2C1_CONF + need des + 0xC + 0x20 + + + I2C1_CONF + need des + 0 + 24 + read-write + + + I2C1_STATUS + need des + 24 + 8 + read-only + + + + + I2C_BURST_CONF + need des + 0x10 + 0x20 + + + I2C_MST_BURST_CTRL + need des + 0 + 32 + read-write + + + + + I2C_BURST_STATUS + need des + 0x14 + 0x20 + 0x40000000 + + + I2C_MST_BURST_DONE + need des + 0 + 1 + read-only + + + I2C_MST0_BURST_ERR_FLAG + need des + 1 + 1 + read-only + + + I2C_MST1_BURST_ERR_FLAG + need des + 2 + 1 + read-only + + + I2C_MST_BURST_TIMEOUT_CNT + need des + 20 + 12 + read-write + + + + + ANA_CONF0 + need des + 0x18 + 0x20 + + + ANA_CONF0 + need des + 0 + 24 + read-write + + + ANA_STATUS0 + need des + 24 + 8 + read-only + + + + + ANA_CONF1 + need des + 0x1C + 0x20 + + + ANA_CONF1 + need des + 0 + 24 + read-write + + + ANA_STATUS1 + need des + 24 + 8 + read-only + + + + + ANA_CONF2 + need des + 0x20 + 0x20 + + + ANA_CONF2 + need des + 0 + 24 + read-write + + + ANA_STATUS2 + need des + 24 + 8 + read-only + + + + + I2C0_CTRL1 + need des + 0x24 + 0x20 + 0x00000042 + + + I2C0_SCL_PULSE_DUR + need des + 0 + 6 + read-write + + + I2C0_SDA_SIDE_GUARD + need des + 6 + 5 + read-write + + + + + I2C1_CTRL1 + need des + 0x28 + 0x20 + 0x00000042 + + + I2C1_SCL_PULSE_DUR + need des + 0 + 6 + read-write + + + I2C1_SDA_SIDE_GUARD + need des + 6 + 5 + read-write + + + + + HW_I2C_CTRL + need des + 0x2C + 0x20 + 0x00000042 + + + HW_I2C_SCL_PULSE_DUR + need des + 0 + 6 + read-write + + + HW_I2C_SDA_SIDE_GUARD + need des + 6 + 5 + read-write + + + ARBITER_DIS + need des + 11 + 1 + read-write + + + + + NOUSE + need des + 0x30 + 0x20 + + + I2C_MST_NOUSE + need des + 0 + 32 + read-write + + + + + CLK160M + need des + 0x34 + 0x20 + + + CLK_I2C_MST_SEL_160M + need des + 0 + 1 + read-write + + + + + DATE + need des + 0x38 + 0x20 + 0x02201300 + + + DATE + need des + 0 + 28 + read-write + + + I2C_MST_CLK_EN + need des + 28 + 1 + read-write + + + + + + + ASSIST_DEBUG + Debug Assist + ASSIST_DEBUG + 0x3FF06000 + + 0x0 + 0x100 + registers + + + ASSIST_DEBUG + 127 + + + + CORE_0_INTR_ENA + core0 monitor enable configuration register + 0x0 + 0x20 + + + CORE_0_AREA_DRAM0_0_RD_ENA + Core0 dram0 area0 read monitor enable + 0 + 1 + read-write + + + CORE_0_AREA_DRAM0_0_WR_ENA + Core0 dram0 area0 write monitor enable + 1 + 1 + read-write + + + CORE_0_AREA_DRAM0_1_RD_ENA + Core0 dram0 area1 read monitor enable + 2 + 1 + read-write + + + CORE_0_AREA_DRAM0_1_WR_ENA + Core0 dram0 area1 write monitor enable + 3 + 1 + read-write + + + CORE_0_AREA_PIF_0_RD_ENA + Core0 PIF area0 read monitor enable + 4 + 1 + read-write + + + CORE_0_AREA_PIF_0_WR_ENA + Core0 PIF area0 write monitor enable + 5 + 1 + read-write + + + CORE_0_AREA_PIF_1_RD_ENA + Core0 PIF area1 read monitor enable + 6 + 1 + read-write + + + CORE_0_AREA_PIF_1_WR_ENA + Core0 PIF area1 write monitor enable + 7 + 1 + read-write + + + CORE_0_SP_SPILL_MIN_ENA + Core0 stackpoint underflow monitor enable + 8 + 1 + read-write + + + CORE_0_SP_SPILL_MAX_ENA + Core0 stackpoint overflow monitor enable + 9 + 1 + read-write + + + CORE_0_IRAM0_EXCEPTION_MONITOR_ENA + IBUS busy monitor enable + 10 + 1 + read-write + + + CORE_0_DRAM0_EXCEPTION_MONITOR_ENA + DBUS busy monitor enbale + 11 + 1 + read-write + + + + + CORE_0_INTR_RAW + core0 monitor interrupt status register + 0x4 + 0x20 + + + CORE_0_AREA_DRAM0_0_RD_RAW + Core0 dram0 area0 read monitor interrupt status + 0 + 1 + read-only + + + CORE_0_AREA_DRAM0_0_WR_RAW + Core0 dram0 area0 write monitor interrupt status + 1 + 1 + read-only + + + CORE_0_AREA_DRAM0_1_RD_RAW + Core0 dram0 area1 read monitor interrupt status + 2 + 1 + read-only + + + CORE_0_AREA_DRAM0_1_WR_RAW + Core0 dram0 area1 write monitor interrupt status + 3 + 1 + read-only + + + CORE_0_AREA_PIF_0_RD_RAW + Core0 PIF area0 read monitor interrupt status + 4 + 1 + read-only + + + CORE_0_AREA_PIF_0_WR_RAW + Core0 PIF area0 write monitor interrupt status + 5 + 1 + read-only + + + CORE_0_AREA_PIF_1_RD_RAW + Core0 PIF area1 read monitor interrupt status + 6 + 1 + read-only + + + CORE_0_AREA_PIF_1_WR_RAW + Core0 PIF area1 write monitor interrupt status + 7 + 1 + read-only + + + CORE_0_SP_SPILL_MIN_RAW + Core0 stackpoint underflow monitor interrupt status + 8 + 1 + read-only + + + CORE_0_SP_SPILL_MAX_RAW + Core0 stackpoint overflow monitor interrupt status + 9 + 1 + read-only + + + CORE_0_IRAM0_EXCEPTION_MONITOR_RAW + IBUS busy monitor interrupt status + 10 + 1 + read-only + + + CORE_0_DRAM0_EXCEPTION_MONITOR_RAW + DBUS busy monitor initerrupt status + 11 + 1 + read-only + + + + + CORE_0_INTR_RLS + core0 monitor interrupt enable register + 0x8 + 0x20 + + + CORE_0_AREA_DRAM0_0_RD_RLS + Core0 dram0 area0 read monitor interrupt enable + 0 + 1 + read-write + + + CORE_0_AREA_DRAM0_0_WR_RLS + Core0 dram0 area0 write monitor interrupt enable + 1 + 1 + read-write + + + CORE_0_AREA_DRAM0_1_RD_RLS + Core0 dram0 area1 read monitor interrupt enable + 2 + 1 + read-write + + + CORE_0_AREA_DRAM0_1_WR_RLS + Core0 dram0 area1 write monitor interrupt enable + 3 + 1 + read-write + + + CORE_0_AREA_PIF_0_RD_RLS + Core0 PIF area0 read monitor interrupt enable + 4 + 1 + read-write + + + CORE_0_AREA_PIF_0_WR_RLS + Core0 PIF area0 write monitor interrupt enable + 5 + 1 + read-write + + + CORE_0_AREA_PIF_1_RD_RLS + Core0 PIF area1 read monitor interrupt enable + 6 + 1 + read-write + + + CORE_0_AREA_PIF_1_WR_RLS + Core0 PIF area1 write monitor interrupt enable + 7 + 1 + read-write + + + CORE_0_SP_SPILL_MIN_RLS + Core0 stackpoint underflow monitor interrupt enable + 8 + 1 + read-write + + + CORE_0_SP_SPILL_MAX_RLS + Core0 stackpoint overflow monitor interrupt enable + 9 + 1 + read-write + + + CORE_0_IRAM0_EXCEPTION_MONITOR_RLS + IBUS busy monitor interrupt enable + 10 + 1 + read-write + + + CORE_0_DRAM0_EXCEPTION_MONITOR_RLS + DBUS busy monitor interrupt enbale + 11 + 1 + read-write + + + + + CORE_0_INTR_CLR + core0 monitor interrupt clr register + 0xC + 0x20 + + + CORE_0_AREA_DRAM0_0_RD_CLR + Core0 dram0 area0 read monitor interrupt clr + 0 + 1 + write-only + + + CORE_0_AREA_DRAM0_0_WR_CLR + Core0 dram0 area0 write monitor interrupt clr + 1 + 1 + write-only + + + CORE_0_AREA_DRAM0_1_RD_CLR + Core0 dram0 area1 read monitor interrupt clr + 2 + 1 + write-only + + + CORE_0_AREA_DRAM0_1_WR_CLR + Core0 dram0 area1 write monitor interrupt clr + 3 + 1 + write-only + + + CORE_0_AREA_PIF_0_RD_CLR + Core0 PIF area0 read monitor interrupt clr + 4 + 1 + write-only + + + CORE_0_AREA_PIF_0_WR_CLR + Core0 PIF area0 write monitor interrupt clr + 5 + 1 + write-only + + + CORE_0_AREA_PIF_1_RD_CLR + Core0 PIF area1 read monitor interrupt clr + 6 + 1 + write-only + + + CORE_0_AREA_PIF_1_WR_CLR + Core0 PIF area1 write monitor interrupt clr + 7 + 1 + write-only + + + CORE_0_SP_SPILL_MIN_CLR + Core0 stackpoint underflow monitor interrupt clr + 8 + 1 + write-only + + + CORE_0_SP_SPILL_MAX_CLR + Core0 stackpoint overflow monitor interrupt clr + 9 + 1 + write-only + + + CORE_0_IRAM0_EXCEPTION_MONITOR_CLR + IBUS busy monitor interrupt clr + 10 + 1 + write-only + + + CORE_0_DRAM0_EXCEPTION_MONITOR_CLR + DBUS busy monitor interrupt clr + 11 + 1 + write-only + + + + + CORE_0_AREA_DRAM0_0_MIN + core0 dram0 region0 addr configuration register + 0x10 + 0x20 + 0xFFFFFFFF + + + CORE_0_AREA_DRAM0_0_MIN + Core0 dram0 region0 start addr + 0 + 32 + read-write + + + + + CORE_0_AREA_DRAM0_0_MAX + core0 dram0 region0 addr configuration register + 0x14 + 0x20 + + + CORE_0_AREA_DRAM0_0_MAX + Core0 dram0 region0 end addr + 0 + 32 + read-write + + + + + CORE_0_AREA_DRAM0_1_MIN + core0 dram0 region1 addr configuration register + 0x18 + 0x20 + 0xFFFFFFFF + + + CORE_0_AREA_DRAM0_1_MIN + Core0 dram0 region1 start addr + 0 + 32 + read-write + + + + + CORE_0_AREA_DRAM0_1_MAX + core0 dram0 region1 addr configuration register + 0x1C + 0x20 + + + CORE_0_AREA_DRAM0_1_MAX + Core0 dram0 region1 end addr + 0 + 32 + read-write + + + + + CORE_0_AREA_PIF_0_MIN + core0 PIF region0 addr configuration register + 0x20 + 0x20 + 0xFFFFFFFF + + + CORE_0_AREA_PIF_0_MIN + Core0 PIF region0 start addr + 0 + 32 + read-write + + + + + CORE_0_AREA_PIF_0_MAX + core0 PIF region0 addr configuration register + 0x24 + 0x20 + + + CORE_0_AREA_PIF_0_MAX + Core0 PIF region0 end addr + 0 + 32 + read-write + + + + + CORE_0_AREA_PIF_1_MIN + core0 PIF region1 addr configuration register + 0x28 + 0x20 + 0xFFFFFFFF + + + CORE_0_AREA_PIF_1_MIN + Core0 PIF region1 start addr + 0 + 32 + read-write + + + + + CORE_0_AREA_PIF_1_MAX + core0 PIF region1 addr configuration register + 0x2C + 0x20 + + + CORE_0_AREA_PIF_1_MAX + Core0 PIF region1 end addr + 0 + 32 + read-write + + + + + CORE_0_AREA_PC + core0 area pc status register + 0x30 + 0x20 + + + CORE_0_AREA_PC + the stackpointer when first touch region monitor interrupt + 0 + 32 + read-only + + + + + CORE_0_AREA_SP + core0 area sp status register + 0x34 + 0x20 + + + CORE_0_AREA_SP + the PC when first touch region monitor interrupt + 0 + 32 + read-only + + + + + CORE_0_SP_MIN + stack min value + 0x38 + 0x20 + + + CORE_0_SP_MIN + core0 sp region configuration regsiter + 0 + 32 + read-write + + + + + CORE_0_SP_MAX + stack max value + 0x3C + 0x20 + 0xFFFFFFFF + + + CORE_0_SP_MAX + core0 sp pc status register + 0 + 32 + read-write + + + + + CORE_0_SP_PC + stack monitor pc status register + 0x40 + 0x20 + + + CORE_0_SP_PC + This regsiter stores the PC when trigger stack monitor. + 0 + 32 + read-only + + + + + CORE_0_RCD_EN + record enable configuration register + 0x44 + 0x20 + + + CORE_0_RCD_RECORDEN + Set 1 to enable record PC + 0 + 1 + read-write + + + CORE_0_RCD_PDEBUGEN + Set 1 to enable cpu pdebug function, must set this bit can get cpu PC + 1 + 1 + read-write + + + + + CORE_0_RCD_PDEBUGPC + record status regsiter + 0x48 + 0x20 + + + CORE_0_RCD_PDEBUGPC + recorded PC + 0 + 32 + read-only + + + + + CORE_0_RCD_PDEBUGSP + record status regsiter + 0x4C + 0x20 + + + CORE_0_RCD_PDEBUGSP + recorded sp + 0 + 32 + read-only + + + + + CORE_0_IRAM0_EXCEPTION_MONITOR_0 + exception monitor status register0 + 0x50 + 0x20 + + + CORE_0_IRAM0_RECORDING_ADDR_0 + reg_core_0_iram0_recording_addr_0 + 0 + 24 + read-only + + + CORE_0_IRAM0_RECORDING_WR_0 + reg_core_0_iram0_recording_wr_0 + 24 + 1 + read-only + + + CORE_0_IRAM0_RECORDING_LOADSTORE_0 + reg_core_0_iram0_recording_loadstore_0 + 25 + 1 + read-only + + + + + CORE_0_IRAM0_EXCEPTION_MONITOR_1 + exception monitor status register1 + 0x54 + 0x20 + + + CORE_0_IRAM0_RECORDING_ADDR_1 + reg_core_0_iram0_recording_addr_1 + 0 + 24 + read-only + + + CORE_0_IRAM0_RECORDING_WR_1 + reg_core_0_iram0_recording_wr_1 + 24 + 1 + read-only + + + CORE_0_IRAM0_RECORDING_LOADSTORE_1 + reg_core_0_iram0_recording_loadstore_1 + 25 + 1 + read-only + + + + + CORE_0_DRAM0_EXCEPTION_MONITOR_0 + exception monitor status register2 + 0x58 + 0x20 + + + CORE_0_DRAM0_RECORDING_WR_0 + reg_core_0_dram0_recording_wr_0 + 0 + 1 + read-only + + + CORE_0_DRAM0_RECORDING_BYTEEN_0 + reg_core_0_dram0_recording_byteen_0 + 1 + 16 + read-only + + + + + CORE_0_DRAM0_EXCEPTION_MONITOR_1 + exception monitor status register3 + 0x5C + 0x20 + + + CORE_0_DRAM0_RECORDING_ADDR_0 + reg_core_0_dram0_recording_addr_0 + 0 + 24 + read-only + + + + + CORE_0_DRAM0_EXCEPTION_MONITOR_2 + exception monitor status register4 + 0x60 + 0x20 + + + CORE_0_DRAM0_RECORDING_PC_0 + reg_core_0_dram0_recording_pc_0 + 0 + 32 + read-only + + + + + CORE_0_DRAM0_EXCEPTION_MONITOR_3 + exception monitor status register5 + 0x64 + 0x20 + + + CORE_0_DRAM0_RECORDING_WR_1 + reg_core_0_dram0_recording_wr_1 + 0 + 1 + read-only + + + CORE_0_DRAM0_RECORDING_BYTEEN_1 + reg_core_0_dram0_recording_byteen_1 + 1 + 16 + read-only + + + + + CORE_0_DRAM0_EXCEPTION_MONITOR_4 + exception monitor status register6 + 0x68 + 0x20 + + + CORE_0_DRAM0_RECORDING_ADDR_1 + reg_core_0_dram0_recording_addr_1 + 0 + 24 + read-only + + + + + CORE_0_DRAM0_EXCEPTION_MONITOR_5 + exception monitor status register7 + 0x6C + 0x20 + + + CORE_0_DRAM0_RECORDING_PC_1 + reg_core_0_dram0_recording_pc_1 + 0 + 32 + read-only + + + + + CORE_0_LASTPC_BEFORE_EXCEPTION + cpu status register + 0x70 + 0x20 + + + CORE_0_LASTPC_BEFORE_EXC + cpu's lastpc before exception + 0 + 32 + read-only + + + + + CORE_0_DEBUG_MODE + cpu status register + 0x74 + 0x20 + + + CORE_0_DEBUG_MODE + cpu debug mode status, 1 means cpu enter debug mode. + 0 + 1 + read-only + + + CORE_0_DEBUG_MODULE_ACTIVE + cpu debug_module active status + 1 + 1 + read-only + + + + + CORE_1_INTR_ENA + core1 monitor enable configuration register + 0x80 + 0x20 + + + CORE_1_AREA_DRAM0_0_RD_ENA + Core1 dram0 area0 read monitor enable + 0 + 1 + read-write + + + CORE_1_AREA_DRAM0_0_WR_ENA + Core1 dram0 area0 write monitor enable + 1 + 1 + read-write + + + CORE_1_AREA_DRAM0_1_RD_ENA + Core1 dram0 area1 read monitor enable + 2 + 1 + read-write + + + CORE_1_AREA_DRAM0_1_WR_ENA + Core1 dram0 area1 write monitor enable + 3 + 1 + read-write + + + CORE_1_AREA_PIF_0_RD_ENA + Core1 PIF area0 read monitor enable + 4 + 1 + read-write + + + CORE_1_AREA_PIF_0_WR_ENA + Core1 PIF area0 write monitor enable + 5 + 1 + read-write + + + CORE_1_AREA_PIF_1_RD_ENA + Core1 PIF area1 read monitor enable + 6 + 1 + read-write + + + CORE_1_AREA_PIF_1_WR_ENA + Core1 PIF area1 write monitor enable + 7 + 1 + read-write + + + CORE_1_SP_SPILL_MIN_ENA + Core1 stackpoint underflow monitor enable + 8 + 1 + read-write + + + CORE_1_SP_SPILL_MAX_ENA + Core1 stackpoint overflow monitor enable + 9 + 1 + read-write + + + CORE_1_IRAM0_EXCEPTION_MONITOR_ENA + IBUS busy monitor enable + 10 + 1 + read-write + + + CORE_1_DRAM0_EXCEPTION_MONITOR_ENA + DBUS busy monitor enbale + 11 + 1 + read-write + + + + + CORE_1_INTR_RAW + core1 monitor interrupt status register + 0x84 + 0x20 + + + CORE_1_AREA_DRAM0_0_RD_RAW + Core1 dram0 area0 read monitor interrupt status + 0 + 1 + read-only + + + CORE_1_AREA_DRAM0_0_WR_RAW + Core1 dram0 area0 write monitor interrupt status + 1 + 1 + read-only + + + CORE_1_AREA_DRAM0_1_RD_RAW + Core1 dram0 area1 read monitor interrupt status + 2 + 1 + read-only + + + CORE_1_AREA_DRAM0_1_WR_RAW + Core1 dram0 area1 write monitor interrupt status + 3 + 1 + read-only + + + CORE_1_AREA_PIF_0_RD_RAW + Core1 PIF area0 read monitor interrupt status + 4 + 1 + read-only + + + CORE_1_AREA_PIF_0_WR_RAW + Core1 PIF area0 write monitor interrupt status + 5 + 1 + read-only + + + CORE_1_AREA_PIF_1_RD_RAW + Core1 PIF area1 read monitor interrupt status + 6 + 1 + read-only + + + CORE_1_AREA_PIF_1_WR_RAW + Core1 PIF area1 write monitor interrupt status + 7 + 1 + read-only + + + CORE_1_SP_SPILL_MIN_RAW + Core1 stackpoint underflow monitor interrupt status + 8 + 1 + read-only + + + CORE_1_SP_SPILL_MAX_RAW + Core1 stackpoint overflow monitor interrupt status + 9 + 1 + read-only + + + CORE_1_IRAM0_EXCEPTION_MONITOR_RAW + IBUS busy monitor interrupt status + 10 + 1 + read-only + + + CORE_1_DRAM0_EXCEPTION_MONITOR_RAW + DBUS busy monitor initerrupt status + 11 + 1 + read-only + + + + + CORE_1_INTR_RLS + core1 monitor interrupt enable register + 0x88 + 0x20 + + + CORE_1_AREA_DRAM0_0_RD_RLS + Core1 dram0 area0 read monitor interrupt enable + 0 + 1 + read-write + + + CORE_1_AREA_DRAM0_0_WR_RLS + Core1 dram0 area0 write monitor interrupt enable + 1 + 1 + read-write + + + CORE_1_AREA_DRAM0_1_RD_RLS + Core1 dram0 area1 read monitor interrupt enable + 2 + 1 + read-write + + + CORE_1_AREA_DRAM0_1_WR_RLS + Core1 dram0 area1 write monitor interrupt enable + 3 + 1 + read-write + + + CORE_1_AREA_PIF_0_RD_RLS + Core1 PIF area0 read monitor interrupt enable + 4 + 1 + read-write + + + CORE_1_AREA_PIF_0_WR_RLS + Core1 PIF area0 write monitor interrupt enable + 5 + 1 + read-write + + + CORE_1_AREA_PIF_1_RD_RLS + Core1 PIF area1 read monitor interrupt enable + 6 + 1 + read-write + + + CORE_1_AREA_PIF_1_WR_RLS + Core1 PIF area1 write monitor interrupt enable + 7 + 1 + read-write + + + CORE_1_SP_SPILL_MIN_RLS + Core1 stackpoint underflow monitor interrupt enable + 8 + 1 + read-write + + + CORE_1_SP_SPILL_MAX_RLS + Core1 stackpoint overflow monitor interrupt enable + 9 + 1 + read-write + + + CORE_1_IRAM0_EXCEPTION_MONITOR_RLS + IBUS busy monitor interrupt enable + 10 + 1 + read-write + + + CORE_1_DRAM0_EXCEPTION_MONITOR_RLS + DBUS busy monitor interrupt enbale + 11 + 1 + read-write + + + + + CORE_1_INTR_CLR + core1 monitor interrupt clr register + 0x8C + 0x20 + + + CORE_1_AREA_DRAM0_0_RD_CLR + Core1 dram0 area0 read monitor interrupt clr + 0 + 1 + write-only + + + CORE_1_AREA_DRAM0_0_WR_CLR + Core1 dram0 area0 write monitor interrupt clr + 1 + 1 + write-only + + + CORE_1_AREA_DRAM0_1_RD_CLR + Core1 dram0 area1 read monitor interrupt clr + 2 + 1 + write-only + + + CORE_1_AREA_DRAM0_1_WR_CLR + Core1 dram0 area1 write monitor interrupt clr + 3 + 1 + write-only + + + CORE_1_AREA_PIF_0_RD_CLR + Core1 PIF area0 read monitor interrupt clr + 4 + 1 + write-only + + + CORE_1_AREA_PIF_0_WR_CLR + Core1 PIF area0 write monitor interrupt clr + 5 + 1 + write-only + + + CORE_1_AREA_PIF_1_RD_CLR + Core1 PIF area1 read monitor interrupt clr + 6 + 1 + write-only + + + CORE_1_AREA_PIF_1_WR_CLR + Core1 PIF area1 write monitor interrupt clr + 7 + 1 + write-only + + + CORE_1_SP_SPILL_MIN_CLR + Core1 stackpoint underflow monitor interrupt clr + 8 + 1 + write-only + + + CORE_1_SP_SPILL_MAX_CLR + Core1 stackpoint overflow monitor interrupt clr + 9 + 1 + write-only + + + CORE_1_IRAM0_EXCEPTION_MONITOR_CLR + IBUS busy monitor interrupt clr + 10 + 1 + write-only + + + CORE_1_DRAM0_EXCEPTION_MONITOR_CLR + DBUS busy monitor interrupt clr + 11 + 1 + write-only + + + + + CORE_1_AREA_DRAM0_0_MIN + core1 dram0 region0 addr configuration register + 0x90 + 0x20 + 0xFFFFFFFF + + + CORE_1_AREA_DRAM0_0_MIN + Core1 dram0 region0 start addr + 0 + 32 + read-write + + + + + CORE_1_AREA_DRAM0_0_MAX + core1 dram0 region0 addr configuration register + 0x94 + 0x20 + + + CORE_1_AREA_DRAM0_0_MAX + Core1 dram0 region0 end addr + 0 + 32 + read-write + + + + + CORE_1_AREA_DRAM0_1_MIN + core1 dram0 region1 addr configuration register + 0x98 + 0x20 + 0xFFFFFFFF + + + CORE_1_AREA_DRAM0_1_MIN + Core1 dram0 region1 start addr + 0 + 32 + read-write + + + + + CORE_1_AREA_DRAM0_1_MAX + core1 dram0 region1 addr configuration register + 0x9C + 0x20 + + + CORE_1_AREA_DRAM0_1_MAX + Core1 dram0 region1 end addr + 0 + 32 + read-write + + + + + CORE_1_AREA_PIF_0_MIN + core1 PIF region0 addr configuration register + 0xA0 + 0x20 + 0xFFFFFFFF + + + CORE_1_AREA_PIF_0_MIN + Core1 PIF region0 start addr + 0 + 32 + read-write + + + + + CORE_1_AREA_PIF_0_MAX + core1 PIF region0 addr configuration register + 0xA4 + 0x20 + + + CORE_1_AREA_PIF_0_MAX + Core1 PIF region0 end addr + 0 + 32 + read-write + + + + + CORE_1_AREA_PIF_1_MIN + core1 PIF region1 addr configuration register + 0xA8 + 0x20 + 0xFFFFFFFF + + + CORE_1_AREA_PIF_1_MIN + Core1 PIF region1 start addr + 0 + 32 + read-write + + + + + CORE_1_AREA_PIF_1_MAX + core1 PIF region1 addr configuration register + 0xAC + 0x20 + + + CORE_1_AREA_PIF_1_MAX + Core1 PIF region1 end addr + 0 + 32 + read-write + + + + + CORE_1_AREA_PC + core1 area pc status register + 0xB0 + 0x20 + + + CORE_1_AREA_PC + the stackpointer when first touch region monitor interrupt + 0 + 32 + read-only + + + + + CORE_1_AREA_SP + core1 area sp status register + 0xB4 + 0x20 + + + CORE_1_AREA_SP + the PC when first touch region monitor interrupt + 0 + 32 + read-only + + + + + CORE_1_SP_MIN + stack min value + 0xB8 + 0x20 + + + CORE_1_SP_MIN + core1 sp region configuration regsiter + 0 + 32 + read-write + + + + + CORE_1_SP_MAX + stack max value + 0xBC + 0x20 + 0xFFFFFFFF + + + CORE_1_SP_MAX + core1 sp pc status register + 0 + 32 + read-write + + + + + CORE_1_SP_PC + stack monitor pc status register + 0xC0 + 0x20 + + + CORE_1_SP_PC + This regsiter stores the PC when trigger stack monitor. + 0 + 32 + read-only + + + + + CORE_1_RCD_EN + record enable configuration register + 0xC4 + 0x20 + + + CORE_1_RCD_RECORDEN + Set 1 to enable record PC + 0 + 1 + read-write + + + CORE_1_RCD_PDEBUGEN + Set 1 to enable cpu pdebug function, must set this bit can get cpu PC + 1 + 1 + read-write + + + + + CORE_1_RCD_PDEBUGPC + record status regsiter + 0xC8 + 0x20 + + + CORE_1_RCD_PDEBUGPC + recorded PC + 0 + 32 + read-only + + + + + CORE_1_RCD_PDEBUGSP + record status regsiter + 0xCC + 0x20 + + + CORE_1_RCD_PDEBUGSP + recorded sp + 0 + 32 + read-only + + + + + CORE_1_IRAM0_EXCEPTION_MONITOR_0 + exception monitor status register0 + 0xD0 + 0x20 + + + CORE_1_IRAM0_RECORDING_ADDR_0 + reg_core_1_iram0_recording_addr_0 + 0 + 24 + read-only + + + CORE_1_IRAM0_RECORDING_WR_0 + reg_core_1_iram0_recording_wr_0 + 24 + 1 + read-only + + + CORE_1_IRAM0_RECORDING_LOADSTORE_0 + reg_core_1_iram0_recording_loadstore_0 + 25 + 1 + read-only + + + + + CORE_1_IRAM0_EXCEPTION_MONITOR_1 + exception monitor status register1 + 0xD4 + 0x20 + + + CORE_1_IRAM0_RECORDING_ADDR_1 + reg_core_1_iram0_recording_addr_1 + 0 + 24 + read-only + + + CORE_1_IRAM0_RECORDING_WR_1 + reg_core_1_iram0_recording_wr_1 + 24 + 1 + read-only + + + CORE_1_IRAM0_RECORDING_LOADSTORE_1 + reg_core_1_iram0_recording_loadstore_1 + 25 + 1 + read-only + + + + + CORE_1_DRAM0_EXCEPTION_MONITOR_0 + exception monitor status register2 + 0xD8 + 0x20 + + + CORE_1_DRAM0_RECORDING_WR_0 + reg_core_1_dram0_recording_wr_0 + 0 + 1 + read-only + + + CORE_1_DRAM0_RECORDING_BYTEEN_0 + reg_core_1_dram0_recording_byteen_0 + 1 + 16 + read-only + + + + + CORE_1_DRAM0_EXCEPTION_MONITOR_1 + exception monitor status register3 + 0xDC + 0x20 + + + CORE_1_DRAM0_RECORDING_ADDR_0 + reg_core_1_dram0_recording_addr_0 + 0 + 24 + read-only + + + + + CORE_1_DRAM0_EXCEPTION_MONITOR_2 + exception monitor status register4 + 0xE0 + 0x20 + + + CORE_1_DRAM0_RECORDING_PC_0 + reg_core_1_dram0_recording_pc_0 + 0 + 32 + read-only + + + + + CORE_1_DRAM0_EXCEPTION_MONITOR_3 + exception monitor status register5 + 0xE4 + 0x20 + + + CORE_1_DRAM0_RECORDING_WR_1 + reg_core_1_dram0_recording_wr_1 + 0 + 1 + read-only + + + CORE_1_DRAM0_RECORDING_BYTEEN_1 + reg_core_1_dram0_recording_byteen_1 + 1 + 16 + read-only + + + + + CORE_1_DRAM0_EXCEPTION_MONITOR_4 + exception monitor status register6 + 0xE8 + 0x20 + + + CORE_1_DRAM0_RECORDING_ADDR_1 + reg_core_1_dram0_recording_addr_1 + 0 + 24 + read-only + + + + + CORE_1_DRAM0_EXCEPTION_MONITOR_5 + exception monitor status register7 + 0xEC + 0x20 + + + CORE_1_DRAM0_RECORDING_PC_1 + reg_core_1_dram0_recording_pc_1 + 0 + 32 + read-only + + + + + CORE_1_LASTPC_BEFORE_EXCEPTION + cpu status register + 0xF0 + 0x20 + + + CORE_1_LASTPC_BEFORE_EXC + cpu's lastpc before exception + 0 + 32 + read-only + + + + + CORE_1_DEBUG_MODE + cpu status register + 0xF4 + 0x20 + + + CORE_1_DEBUG_MODE + cpu debug mode status, 1 means cpu enter debug mode. + 0 + 1 + read-only + + + CORE_1_DEBUG_MODULE_ACTIVE + cpu debug_module active status + 1 + 1 + read-only + + + + + CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0 + exception monitor status register6 + 0x100 + 0x20 + + + CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 + reg_core_x_iram0_dram0_limit_cycle_0 + 0 + 20 + read-write + + + + + CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1 + exception monitor status register7 + 0x104 + 0x20 + + + CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 + reg_core_x_iram0_dram0_limit_cycle_1 + 0 + 20 + read-write + + + + + CLOCK_GATE + clock register + 0x108 + 0x20 + 0x00000001 + + + CLK_EN + Set 1 force on the clock gate + 0 + 1 + read-write + + + + + DATE + version register + 0x3FC + 0x20 + 0x02109130 + + + ASSIST_DEBUG_DATE + version register + 0 + 28 + read-write + + + + + + + AXI_DMA + AXI_DMA Peripheral + AXI_DMA + 0x5008A000 + + 0x0 + 0x2D8 + registers + + + + 3 + 0x68 + IN_INT_RAW_CH%s + Raw status interrupt of channel 0 + 0x0 + 0x20 + + + IN_DONE_CH_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. + 0 + 1 + read-write + + + IN_SUC_EOF_CH_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0. + 1 + 1 + read-write + + + IN_ERR_EOF_CH_INT_RAW + The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw interrupt is reserved. + 2 + 1 + read-write + + + IN_DSCR_ERR_CH_INT_RAW + The raw interrupt bit turns to high level when detecting inlink descriptor error including owner error and the second and third word error of inlink descriptor for Rx channel 0. + 3 + 1 + read-write + + + IN_DSCR_EMPTY_CH_INT_RAW + The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed but there is no more inlink for Rx channel 0. + 4 + 1 + read-write + + + INFIFO_L1_OVF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow. + 5 + 1 + read-write + + + INFIFO_L1_UDF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow. + 6 + 1 + read-write + + + INFIFO_L2_OVF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow. + 7 + 1 + read-write + + + INFIFO_L2_UDF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow. + 8 + 1 + read-write + + + INFIFO_L3_OVF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow. + 9 + 1 + read-write + + + INFIFO_L3_UDF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow. + 10 + 1 + read-write + + + + + 3 + 0x68 + IN_INT_ST_CH%s + Masked interrupt of channel 0 + 0x4 + 0x20 + + + IN_DONE_CH_INT_ST + The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-only + + + IN_SUC_EOF_CH_INT_ST + The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-only + + + IN_ERR_EOF_CH_INT_ST + The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + read-only + + + IN_DSCR_ERR_CH_INT_ST + The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 + read-only + + + IN_DSCR_EMPTY_CH_INT_ST + The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + 4 + 1 + read-only + + + INFIFO_OVF_CH_INT_ST + The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + 5 + 1 + read-only + + + INFIFO_UDF_CH_INT_ST + The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + 6 + 1 + read-only + + + INFIFO_L1_OVF_CH_INT_ST + The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. + 7 + 1 + read-only + + + INFIFO_L1_UDF_CH_INT_ST + The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. + 8 + 1 + read-only + + + INFIFO_L3_OVF_CH_INT_ST + The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt. + 9 + 1 + read-only + + + INFIFO_L3_UDF_CH_INT_ST + The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt. + 10 + 1 + read-only + + + + + 3 + 0x68 + IN_INT_ENA_CH%s + Interrupt enable bits of channel 0 + 0x8 + 0x20 + + + IN_DONE_CH_INT_ENA + The interrupt enable bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-write + + + IN_SUC_EOF_CH_INT_ENA + The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-write + + + IN_ERR_EOF_CH_INT_ENA + The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + read-write + + + IN_DSCR_ERR_CH_INT_ENA + The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 + read-write + + + IN_DSCR_EMPTY_CH_INT_ENA + The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + 4 + 1 + read-write + + + INFIFO_L1_OVF_CH_INT_ENA + The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + 5 + 1 + read-write + + + INFIFO_L1_UDF_CH_INT_ENA + The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + 6 + 1 + read-write + + + INFIFO_L2_OVF_CH_INT_ENA + The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. + 7 + 1 + read-write + + + INFIFO_L2_UDF_CH_INT_ENA + The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. + 8 + 1 + read-write + + + INFIFO_L3_OVF_CH_INT_ENA + The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt. + 9 + 1 + read-write + + + INFIFO_L3_UDF_CH_INT_ENA + The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt. + 10 + 1 + read-write + + + + + 3 + 0x68 + IN_INT_CLR_CH%s + Interrupt clear bits of channel 0 + 0xC + 0x20 + + + IN_DONE_CH_INT_CLR + Set this bit to clear the IN_DONE_CH_INT interrupt. + 0 + 1 + write-only + + + IN_SUC_EOF_CH_INT_CLR + Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + write-only + + + IN_ERR_EOF_CH_INT_CLR + Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + write-only + + + IN_DSCR_ERR_CH_INT_CLR + Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 + write-only + + + IN_DSCR_EMPTY_CH_INT_CLR + Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + 4 + 1 + write-only + + + INFIFO_L1_OVF_CH_INT_CLR + Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + 5 + 1 + write-only + + + INFIFO_L1_UDF_CH_INT_CLR + Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + 6 + 1 + write-only + + + INFIFO_L2_OVF_CH_INT_CLR + Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. + 7 + 1 + write-only + + + INFIFO_L2_UDF_CH_INT_CLR + Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. + 8 + 1 + write-only + + + INFIFO_L3_OVF_CH_INT_CLR + Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt. + 9 + 1 + write-only + + + INFIFO_L3_UDF_CH_INT_CLR + Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt. + 10 + 1 + write-only + + + + + 3 + 0x68 + IN_CONF0_CH%s + Configure 0 register of Rx channel 0 + 0x10 + 0x20 + + + IN_RST_CH + This bit is used to reset AXI_DMA channel 0 Rx FSM and Rx FIFO pointer. + 0 + 1 + read-write + + + IN_LOOP_TEST_CH + reserved + 1 + 1 + read-write + + + MEM_TRANS_EN_CH + Set this bit 1 to enable automatic transmitting data from memory to memory via AXI_DMA. + 2 + 1 + read-write + + + IN_ETM_EN_CH + Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm task. + 3 + 1 + read-write + + + IN_BURST_SIZE_SEL_CH + 3'b000-3'b100:burst length 8byte~128byte + 4 + 3 + read-write + + + IN_CMD_DISABLE_CH + 1:mean disable cmd of this ch0 + 7 + 1 + read-write + + + IN_ECC_AEC_EN_CH + 1: mean access ecc or aes domain,0: mean not + 8 + 1 + read-write + + + INDSCR_BURST_EN_CH + Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM. + 9 + 1 + read-write + + + + + 3 + 0x68 + IN_CONF1_CH%s + Configure 1 register of Rx channel 0 + 0x14 + 0x20 + + + IN_CHECK_OWNER_CH + Set this bit to enable checking the owner attribute of the link descriptor. + 12 + 1 + read-write + + + + + 3 + 0x68 + INFIFO_STATUS_CH%s + Receive FIFO status of Rx channel 0 + 0x18 + 0x20 + 0x00008803 + + + INFIFO_L3_FULL_CH + L3 Rx FIFO full signal for Rx channel 0. + 0 + 1 + read-only + + + INFIFO_L3_EMPTY_CH + L3 Rx FIFO empty signal for Rx channel 0. + 1 + 1 + read-only + + + INFIFO_L3_CNT_CH + The register stores the byte number of the data in L3 Rx FIFO for Rx channel 0. + 2 + 6 + read-only + + + INFIFO_L3_UDF_CH + L3 Rx FIFO under flow signal for Rx channel 0. + 8 + 1 + read-only + + + INFIFO_L3_OVF_CH + L3 Rx FIFO over flow signal for Rx channel 0. + 9 + 1 + read-only + + + INFIFO_L1_FULL_CH + L1 Rx FIFO full signal for Rx channel 0. + 10 + 1 + read-only + + + INFIFO_L1_EMPTY_CH + L1 Rx FIFO empty signal for Rx channel 0. + 11 + 1 + read-only + + + INFIFO_L1_UDF_CH + L1 Rx FIFO under flow signal for Rx channel 0. + 12 + 1 + read-only + + + INFIFO_L1_OVF_CH + L1 Rx FIFO over flow signal for Rx channel 0. + 13 + 1 + read-only + + + INFIFO_L2_FULL_CH + L2 Rx RAM full signal for Rx channel 0. + 14 + 1 + read-only + + + INFIFO_L2_EMPTY_CH + L2 Rx RAM empty signal for Rx channel 0. + 15 + 1 + read-only + + + INFIFO_L2_UDF_CH + L2 Rx FIFO under flow signal for Rx channel 0. + 16 + 1 + read-only + + + INFIFO_L2_OVF_CH + L2 Rx FIFO over flow signal for Rx channel 0. + 17 + 1 + read-only + + + IN_REMAIN_UNDER_1B_CH + reserved + 23 + 1 + read-only + + + IN_REMAIN_UNDER_2B_CH + reserved + 24 + 1 + read-only + + + IN_REMAIN_UNDER_3B_CH + reserved + 25 + 1 + read-only + + + IN_REMAIN_UNDER_4B_CH + reserved + 26 + 1 + read-only + + + IN_REMAIN_UNDER_5B_CH + reserved + 27 + 1 + read-only + + + IN_REMAIN_UNDER_6B_CH + reserved + 28 + 1 + read-only + + + IN_REMAIN_UNDER_7B_CH + reserved + 29 + 1 + read-only + + + IN_REMAIN_UNDER_8B_CH + reserved + 30 + 1 + read-only + + + IN_BUF_HUNGRY_CH + reserved + 31 + 1 + read-only + + + + + 3 + 0x68 + IN_POP_CH%s + Pop control register of Rx channel 0 + 0x1C + 0x20 + 0x00000800 + + + INFIFO_RDATA_CH + This register stores the data popping from AXI_DMA FIFO. + 0 + 12 + read-only + + + INFIFO_POP_CH + Set this bit to pop data from AXI_DMA FIFO. + 12 + 1 + write-only + + + + + 3 + 0x68 + IN_LINK1_CH%s + Link descriptor configure and control register of Rx channel 0 + 0x20 + 0x20 + 0x00000011 + + + INLINK_AUTO_RET_CH + Set this bit to return to current inlink descriptor's address when there are some errors in current receiving data. + 0 + 1 + read-write + + + INLINK_STOP_CH + Set this bit to stop dealing with the inlink descriptors. + 1 + 1 + write-only + + + INLINK_START_CH + Set this bit to start dealing with the inlink descriptors. + 2 + 1 + write-only + + + INLINK_RESTART_CH + Set this bit to mount a new inlink descriptor. + 3 + 1 + write-only + + + INLINK_PARK_CH + 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. + 4 + 1 + read-only + + + + + 3 + 0x68 + IN_LINK2_CH%s + Link descriptor configure and control register of Rx channel 0 + 0x24 + 0x20 + + + INLINK_ADDR_CH + This register stores the 20 least significant bits of the first inlink descriptor's address. + 0 + 32 + read-write + + + + + 3 + 0x68 + IN_STATE_CH%s + Receive status of Rx channel 0 + 0x28 + 0x20 + + + INLINK_DSCR_ADDR_CH + This register stores the current inlink descriptor's address. + 0 + 18 + read-only + + + IN_DSCR_STATE_CH + reserved + 18 + 2 + read-only + + + IN_STATE_CH + reserved + 20 + 3 + read-only + + + + + 3 + 0x68 + IN_SUC_EOF_DES_ADDR_CH%s + Inlink descriptor address when EOF occurs of Rx channel 0 + 0x2C + 0x20 + + + IN_SUC_EOF_DES_ADDR_CH + This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. + 0 + 32 + read-only + + + + + 3 + 0x68 + IN_ERR_EOF_DES_ADDR_CH%s + Inlink descriptor address when errors occur of Rx channel 0 + 0x30 + 0x20 + + + IN_ERR_EOF_DES_ADDR_CH + This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0. + 0 + 32 + read-only + + + + + 3 + 0x68 + IN_DSCR_CH%s + Current inlink descriptor address of Rx channel 0 + 0x34 + 0x20 + + + INLINK_DSCR_CH + The address of the current inlink descriptor x. + 0 + 32 + read-only + + + + + 3 + 0x68 + IN_DSCR_BF0_CH%s + The last inlink descriptor address of Rx channel 0 + 0x38 + 0x20 + + + INLINK_DSCR_BF0_CH + The address of the last inlink descriptor x-1. + 0 + 32 + read-only + + + + + 3 + 0x68 + IN_DSCR_BF1_CH%s + The second-to-last inlink descriptor address of Rx channel 0 + 0x3C + 0x20 + + + INLINK_DSCR_BF1_CH + The address of the second-to-last inlink descriptor x-2. + 0 + 32 + read-only + + + + + 3 + 0x68 + IN_PRI_CH%s + Priority register of Rx channel 0 + 0x40 + 0x20 + + + RX_PRI_CH + The priority of Rx channel 0. The larger of the value the higher of the priority. + 0 + 4 + read-write + + + RX_CH_ARB_WEIGH_CH + The weight of Rx channel 0 + 4 + 4 + read-write + + + RX_ARB_WEIGH_OPT_DIR_CH + 0: mean not optimazation weight function ,1: mean optimazation + 8 + 1 + read-write + + + + + 3 + 0x68 + IN_PERI_SEL_CH%s + Peripheral selection of Rx channel 0 + 0x44 + 0x20 + 0x0000003F + + + PERI_IN_SEL_CH + This register is used to select peripheral for Rx channel 0. 0:lcdcam. 1: gpspi_2. 2: gpspi_3. 3: parl_io. 4: aes. 5: sha. 6~15: Dummy + 0 + 6 + read-write + + + + + 3 + 0x68 + IN_CRC_INIT_DATA_CH%s + This register is used to config ch0 crc initial data(max 32 bit) + 0x48 + 0x20 + 0xFFFFFFFF + + + IN_CRC_INIT_DATA_CH + This register is used to config ch0 of rx crc initial value + 0 + 32 + read-write + + + + + 3 + 0x68 + RX_CRC_WIDTH_CH%s + This register is used to confiig rx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean 24<crc_width<=32 + 0x4C + 0x20 + + + RX_CRC_WIDTH_CH + reserved + 0 + 2 + read-write + + + RX_CRC_LAUTCH_FLGA_CH + reserved + 2 + 1 + read-write + + + + + 3 + 0x68 + IN_CRC_CLEAR_CH%s + This register is used to clear ch0 crc result + 0x50 + 0x20 + + + IN_CRC_CLEAR_CH + This register is used to clear ch0 of rx crc result + 0 + 1 + read-write + + + + + 3 + 0x68 + IN_CRC_FINAL_RESULT_CH%s + This register is used to store ch0 crc result + 0x54 + 0x20 + + + IN_CRC_FINAL_RESULT_CH + This register is used to store result ch0 of rx + 0 + 32 + read-only + + + + + 3 + 0x68 + RX_CRC_EN_WR_DATA_CH%s + This resister is used to config ch0 crc en for every bit + 0x58 + 0x20 + + + RX_CRC_EN_WR_DATA_CH + This register is used to enable rx ch0 crc 32bit on/off + 0 + 32 + read-write + + + + + 3 + 0x68 + RX_CRC_EN_ADDR_CH%s + This register is used to config ch0 crc en addr + 0x5C + 0x20 + + + RX_CRC_EN_ADDR_CH + reserved + 0 + 32 + read-write + + + + + 3 + 0x68 + RX_CRC_DATA_EN_WR_DATA_CH%s + This register is used to config crc data_8bit en + 0x60 + 0x20 + + + RX_CRC_DATA_EN_WR_DATA_CH + reserved + 0 + 16 + read-write + + + + + 3 + 0x68 + RX_CRC_DATA_EN_ADDR_CH%s + This register is used to config addr of crc data_8bit en + 0x64 + 0x20 + + + RX_CRC_DATA_EN_ADDR_CH + reserved + 0 + 32 + read-write + + + + + 3 + 0x68 + OUT_INT_RAW_CH%s + Raw status interrupt of channel0 + 0x138 + 0x20 + + + OUT_DONE_CH_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel0. + 0 + 1 + read-write + + + OUT_EOF_CH_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel0. + 1 + 1 + read-write + + + OUT_DSCR_ERR_CH_INT_RAW + The raw interrupt bit turns to high level when detecting outlink descriptor error including owner error and the second and third word error of outlink descriptor for Tx channel0. + 2 + 1 + read-write + + + OUT_TOTAL_EOF_CH_INT_RAW + The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel0. + 3 + 1 + read-write + + + OUTFIFO_L1_OVF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is overflow. + 4 + 1 + read-write + + + OUTFIFO_L1_UDF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is underflow. + 5 + 1 + read-write + + + OUTFIFO_L2_OVF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is overflow. + 6 + 1 + read-write + + + OUTFIFO_L2_UDF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is underflow. + 7 + 1 + read-write + + + OUTFIFO_L3_OVF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is overflow. + 8 + 1 + read-write + + + OUTFIFO_L3_UDF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is underflow. + 9 + 1 + read-write + + + + + 3 + 0x68 + OUT_INT_ST_CH%s + Masked interrupt of channel0 + 0x13C + 0x20 + + + OUT_DONE_CH_INT_ST + The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + 0 + 1 + read-only + + + OUT_EOF_CH_INT_ST + The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + 1 + 1 + read-only + + + OUT_DSCR_ERR_CH_INT_ST + The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + read-only + + + OUT_TOTAL_EOF_CH_INT_ST + The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + read-only + + + OUTFIFO_OVF_CH_INT_ST + The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-only + + + OUTFIFO_UDF_CH_INT_ST + The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-only + + + OUTFIFO_L1_OVF_CH_INT_ST + The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-only + + + OUTFIFO_L1_UDF_CH_INT_ST + The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-only + + + OUTFIFO_L3_OVF_CH_INT_ST + The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt. + 8 + 1 + read-only + + + OUTFIFO_L3_UDF_CH_INT_ST + The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt. + 9 + 1 + read-only + + + + + 3 + 0x68 + OUT_INT_ENA_CH%s + Interrupt enable bits of channel0 + 0x140 + 0x20 + + + OUT_DONE_CH_INT_ENA + The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + 0 + 1 + read-write + + + OUT_EOF_CH_INT_ENA + The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + 1 + 1 + read-write + + + OUT_DSCR_ERR_CH_INT_ENA + The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + read-write + + + OUT_TOTAL_EOF_CH_INT_ENA + The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + read-write + + + OUTFIFO_L1_OVF_CH_INT_ENA + The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-write + + + OUTFIFO_L1_UDF_CH_INT_ENA + The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-write + + + OUTFIFO_L2_OVF_CH_INT_ENA + The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-write + + + OUTFIFO_L2_UDF_CH_INT_ENA + The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-write + + + OUTFIFO_L3_OVF_CH_INT_ENA + The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt. + 8 + 1 + read-write + + + OUTFIFO_L3_UDF_CH_INT_ENA + The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt. + 9 + 1 + read-write + + + + + 3 + 0x68 + OUT_INT_CLR_CH%s + Interrupt clear bits of channel0 + 0x144 + 0x20 + + + OUT_DONE_CH_INT_CLR + Set this bit to clear the OUT_DONE_CH_INT interrupt. + 0 + 1 + write-only + + + OUT_EOF_CH_INT_CLR + Set this bit to clear the OUT_EOF_CH_INT interrupt. + 1 + 1 + write-only + + + OUT_DSCR_ERR_CH_INT_CLR + Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + write-only + + + OUT_TOTAL_EOF_CH_INT_CLR + Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + write-only + + + OUTFIFO_L1_OVF_CH_INT_CLR + Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + write-only + + + OUTFIFO_L1_UDF_CH_INT_CLR + Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + write-only + + + OUTFIFO_L2_OVF_CH_INT_CLR + Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + write-only + + + OUTFIFO_L2_UDF_CH_INT_CLR + Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + write-only + + + OUTFIFO_L3_OVF_CH_INT_CLR + Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt. + 8 + 1 + write-only + + + OUTFIFO_L3_UDF_CH_INT_CLR + Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt. + 9 + 1 + write-only + + + + + OUT_CONF0_CH0 + Configure 0 register of Tx channel0 + 0x148 + 0x20 + 0x00000008 + + + OUT_RST_CH0 + This bit is used to reset AXI_DMA channel0 Tx FSM and Tx FIFO pointer. + 0 + 1 + read-write + + + OUT_LOOP_TEST_CH0 + reserved + 1 + 1 + read-write + + + OUT_AUTO_WRBACK_CH0 + Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted. + 2 + 1 + read-write + + + OUT_EOF_MODE_CH0 + EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel0 is generated when data need to transmit has been popped from FIFO in AXI_DMA + 3 + 1 + read-write + + + OUT_ETM_EN_CH0 + Set this bit to 1 to enable etm control mode, dma Tx channel0 is triggered by etm task. + 4 + 1 + read-write + + + OUT_BURST_SIZE_SEL_CH0 + 3'b000-3'b100:burst length 8byte~128byte + 5 + 3 + read-write + + + OUT_CMD_DISABLE_CH0 + 1:mean disable cmd of this ch0 + 8 + 1 + read-write + + + OUT_ECC_AEC_EN_CH0 + 1: mean access ecc or aes domain,0: mean not + 9 + 1 + read-write + + + OUTDSCR_BURST_EN_CH0 + Set this bit to 1 to enable INCR burst transfer for Tx channel0 reading link descriptor when accessing internal SRAM. + 10 + 1 + read-write + + + + + 3 + 0x68 + OUT_CONF1_CH%s + Configure 1 register of Tx channel0 + 0x14C + 0x20 + + + OUT_CHECK_OWNER_CH + Set this bit to enable checking the owner attribute of the link descriptor. + 12 + 1 + read-write + + + + + 3 + 0x68 + OUTFIFO_STATUS_CH%s + Transmit FIFO status of Tx channel0 + 0x150 + 0x20 + 0x7F808802 + + + OUTFIFO_L3_FULL_CH + L3 Tx FIFO full signal for Tx channel0. + 0 + 1 + read-only + + + OUTFIFO_L3_EMPTY_CH + L3 Tx FIFO empty signal for Tx channel0. + 1 + 1 + read-only + + + OUTFIFO_L3_CNT_CH + The register stores the byte number of the data in L3 Tx FIFO for Tx channel0. + 2 + 6 + read-only + + + OUTFIFO_L3_UDF_CH + L3 Tx FIFO under flow signal for Tx channel0. + 8 + 1 + read-only + + + OUTFIFO_L3_OVF_CH + L3 Tx FIFO over flow signal for Tx channel0. + 9 + 1 + read-only + + + OUTFIFO_L1_FULL_CH + L1 Tx FIFO full signal for Tx channel0. + 10 + 1 + read-only + + + OUTFIFO_L1_EMPTY_CH + L1 Tx FIFO empty signal for Tx channel0. + 11 + 1 + read-only + + + OUTFIFO_L1_UDF_CH + L1 Tx FIFO under flow signal for Tx channel0. + 12 + 1 + read-only + + + OUTFIFO_L1_OVF_CH + L1 Tx FIFO over flow signal for Tx channel0. + 13 + 1 + read-only + + + OUTFIFO_L2_FULL_CH + L2 Tx RAM full signal for Tx channel0. + 14 + 1 + read-only + + + OUTFIFO_L2_EMPTY_CH + L2 Tx RAM empty signal for Tx channel0. + 15 + 1 + read-only + + + OUTFIFO_L2_UDF_CH + L2 Tx FIFO under flow signal for Tx channel0. + 16 + 1 + read-only + + + OUTFIFO_L2_OVF_CH + L2 Tx FIFO over flow signal for Tx channel0. + 17 + 1 + read-only + + + OUT_REMAIN_UNDER_1B_CH + reserved + 23 + 1 + read-only + + + OUT_REMAIN_UNDER_2B_CH + reserved + 24 + 1 + read-only + + + OUT_REMAIN_UNDER_3B_CH + reserved + 25 + 1 + read-only + + + OUT_REMAIN_UNDER_4B_CH + reserved + 26 + 1 + read-only + + + OUT_REMAIN_UNDER_5B_CH + reserved + 27 + 1 + read-only + + + OUT_REMAIN_UNDER_6B_CH + reserved + 28 + 1 + read-only + + + OUT_REMAIN_UNDER_7B_CH + reserved + 29 + 1 + read-only + + + OUT_REMAIN_UNDER_8B_CH + reserved + 30 + 1 + read-only + + + + + 3 + 0x68 + OUT_PUSH_CH%s + Push control register of Tx channel0 + 0x154 + 0x20 + + + OUTFIFO_WDATA_CH + This register stores the data that need to be pushed into AXI_DMA FIFO. + 0 + 9 + read-write + + + OUTFIFO_PUSH_CH + Set this bit to push data into AXI_DMA FIFO. + 9 + 1 + write-only + + + + + 3 + 0x68 + OUT_LINK1_CH%s + Link descriptor configure and control register of Tx channel0 + 0x158 + 0x20 + 0x00000008 + + + OUTLINK_STOP_CH + Set this bit to stop dealing with the outlink descriptors. + 0 + 1 + write-only + + + OUTLINK_START_CH + Set this bit to start dealing with the outlink descriptors. + 1 + 1 + write-only + + + OUTLINK_RESTART_CH + Set this bit to restart a new outlink from the last address. + 2 + 1 + write-only + + + OUTLINK_PARK_CH + 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. + 3 + 1 + read-only + + + + + 3 + 0x68 + OUT_LINK2_CH%s + Link descriptor configure and control register of Tx channel0 + 0x15C + 0x20 + + + OUTLINK_ADDR_CH + This register stores the 32 least significant bits of the first outlink descriptor's address. + 0 + 32 + read-write + + + + + 3 + 0x68 + OUT_STATE_CH%s + Transmit status of Tx channel0 + 0x160 + 0x20 + + + OUTLINK_DSCR_ADDR_CH + This register stores the current outlink descriptor's address. + 0 + 18 + read-only + + + OUT_DSCR_STATE_CH + reserved + 18 + 2 + read-only + + + OUT_STATE_CH + reserved + 20 + 3 + read-only + + + + + 3 + 0x68 + OUT_EOF_DES_ADDR_CH%s + Outlink descriptor address when EOF occurs of Tx channel0 + 0x164 + 0x20 + + + OUT_EOF_DES_ADDR_CH + This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1. + 0 + 32 + read-only + + + + + 3 + 0x68 + OUT_EOF_BFR_DES_ADDR_CH%s + The last outlink descriptor address when EOF occurs of Tx channel0 + 0x168 + 0x20 + + + OUT_EOF_BFR_DES_ADDR_CH + This register stores the address of the outlink descriptor before the last outlink descriptor. + 0 + 32 + read-only + + + + + 3 + 0x68 + OUT_DSCR_CH%s + Current outlink descriptor address of Tx channel0 + 0x16C + 0x20 + + + OUTLINK_DSCR_CH + The address of the current outlink descriptor y. + 0 + 32 + read-only + + + + + 3 + 0x68 + OUT_DSCR_BF0_CH%s + The last outlink descriptor address of Tx channel0 + 0x170 + 0x20 + + + OUTLINK_DSCR_BF0_CH + The address of the last outlink descriptor y-1. + 0 + 32 + read-only + + + + + 3 + 0x68 + OUT_DSCR_BF1_CH%s + The second-to-last outlink descriptor address of Tx channel0 + 0x174 + 0x20 + + + OUTLINK_DSCR_BF1_CH + The address of the second-to-last outlink descriptor x-2. + 0 + 32 + read-only + + + + + 3 + 0x68 + OUT_PRI_CH%s + Priority register of Tx channel0. + 0x178 + 0x20 + + + TX_PRI_CH + The priority of Tx channel0. The larger of the value the higher of the priority. + 0 + 4 + read-write + + + TX_CH_ARB_WEIGH_CH + The weight of Tx channel0 + 4 + 4 + read-write + + + TX_ARB_WEIGH_OPT_DIR_CH + 0: mean not optimazation weight function ,1: mean optimazation + 8 + 1 + read-write + + + + + 3 + 0x68 + OUT_PERI_SEL_CH%s + Peripheral selection of Tx channel0 + 0x17C + 0x20 + 0x0000003F + + + PERI_OUT_SEL_CH + This register is used to select peripheral for Tx channel0. 0:lcdcam. 1: gpspi_2. 2: gpspi_3. 3: parl_io. 4: aes. 5: sha. 6~15: Dummy + 0 + 6 + read-write + + + + + 3 + 0x68 + OUT_CRC_INIT_DATA_CH%s + This register is used to config ch0 crc initial data(max 32 bit) + 0x180 + 0x20 + 0xFFFFFFFF + + + OUT_CRC_INIT_DATA_CH + This register is used to config ch0 of tx crc initial value + 0 + 32 + read-write + + + + + 3 + 0x68 + TX_CRC_WIDTH_CH%s + This register is used to confiig tx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean 24<crc_width<=32 + 0x184 + 0x20 + + + TX_CRC_WIDTH_CH + reserved + 0 + 2 + read-write + + + TX_CRC_LAUTCH_FLGA_CH + reserved + 2 + 1 + read-write + + + + + 3 + 0x68 + OUT_CRC_CLEAR_CH%s + This register is used to clear ch0 crc result + 0x188 + 0x20 + + + OUT_CRC_CLEAR_CH + This register is used to clear ch0 of tx crc result + 0 + 1 + read-write + + + + + 3 + 0x68 + OUT_CRC_FINAL_RESULT_CH%s + This register is used to store ch0 crc result + 0x18C + 0x20 + + + OUT_CRC_FINAL_RESULT_CH + This register is used to store result ch0 of tx + 0 + 32 + read-only + + + + + 3 + 0x68 + TX_CRC_EN_WR_DATA_CH%s + This resister is used to config ch0 crc en for every bit + 0x190 + 0x20 + + + TX_CRC_EN_WR_DATA_CH + This register is used to enable tx ch0 crc 32bit on/off + 0 + 32 + read-write + + + + + 3 + 0x68 + TX_CRC_EN_ADDR_CH%s + This register is used to config ch0 crc en addr + 0x194 + 0x20 + + + TX_CRC_EN_ADDR_CH + reserved + 0 + 32 + read-write + + + + + 3 + 0x68 + TX_CRC_DATA_EN_WR_DATA_CH%s + This register is used to config crc data_8bit en + 0x198 + 0x20 + + + TX_CRC_DATA_EN_WR_DATA_CH + reserved + 0 + 16 + read-write + + + + + 3 + 0x68 + TX_CRC_DATA_EN_ADDR_CH%s + This register is used to config addr of crc data_8bit en + 0x19C + 0x20 + + + TX_CRC_DATA_EN_ADDR_CH + reserved + 0 + 32 + read-write + + + + + OUT_CONF0_CH1 + Configure 0 register of Tx channel1 + 0x1B0 + 0x20 + 0x00000008 + + + OUT_RST_CH1 + This bit is used to reset AXI_DMA channel1 Tx FSM and Tx FIFO pointer. + 0 + 1 + read-write + + + OUT_LOOP_TEST_CH1 + reserved + 1 + 1 + read-write + + + OUT_AUTO_WRBACK_CH1 + Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted. + 2 + 1 + read-write + + + OUT_EOF_MODE_CH1 + EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel1 is generated when data need to transmit has been popped from FIFO in AXI_DMA + 3 + 1 + read-write + + + OUT_ETM_EN_CH1 + Set this bit to 1 to enable etm control mode, dma Tx channel1 is triggered by etm task. + 4 + 1 + read-write + + + OUT_BURST_SIZE_SEL_CH1 + 3'b000-3'b100:burst length 8byte~128byte + 5 + 3 + read-write + + + OUT_CMD_DISABLE_CH1 + 1:mean disable cmd of this ch1 + 8 + 1 + read-write + + + OUT_ECC_AEC_EN_CH1 + 1: mean access ecc or aes domain,0: mean not + 9 + 1 + read-write + + + OUTDSCR_BURST_EN_CH1 + Set this bit to 1 to enable INCR burst transfer for Tx channel1 reading link descriptor when accessing internal SRAM. + 10 + 1 + read-write + + + + + OUT_CONF0_CH2 + Configure 0 register of Tx channel2 + 0x218 + 0x20 + 0x00000008 + + + OUT_RST_CH2 + This bit is used to reset AXI_DMA channel2 Tx FSM and Tx FIFO pointer. + 0 + 1 + read-write + + + OUT_LOOP_TEST_CH2 + reserved + 1 + 1 + read-write + + + OUT_AUTO_WRBACK_CH2 + Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted. + 2 + 1 + read-write + + + OUT_EOF_MODE_CH2 + EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel2 is generated when data need to transmit has been popped from FIFO in AXI_DMA + 3 + 1 + read-write + + + OUT_ETM_EN_CH2 + Set this bit to 1 to enable etm control mode, dma Tx channel2 is triggered by etm task. + 4 + 1 + read-write + + + OUT_BURST_SIZE_SEL_CH2 + 3'b000-3'b100:burst length 8byte~128byte + 5 + 3 + read-write + + + OUT_CMD_DISABLE_CH2 + 1:mean disable cmd of this ch2 + 8 + 1 + read-write + + + OUT_ECC_AEC_EN_CH2 + 1: mean access ecc or aes domain,0: mean not + 9 + 1 + read-write + + + OUTDSCR_BURST_EN_CH2 + Set this bit to 1 to enable INCR burst transfer for Tx channel2 reading link descriptor when accessing internal SRAM. + 10 + 1 + read-write + + + + + ARB_TIMEOUT + This retister is used to config arbiter time slice + 0x270 + 0x20 + + + TX + This register is used to config tx arbiter time out value + 0 + 16 + read-write + + + RX + This register is used to config rx arbiter time out value + 16 + 16 + read-write + + + + + WEIGHT_EN + This register is used to config arbiter weight function to on or off + 0x274 + 0x20 + + + TX + This register is used to config tx arbiter weight function off/on + 0 + 1 + read-write + + + RX + This register is used to config rx arbiter weight function off/on + 1 + 1 + read-write + + + + + IN_MEM_CONF + Mem power configure register of Rx channel + 0x278 + 0x20 + + + IN_MEM_CLK_FORCE_EN + 1: Force to open the clock and bypass the gate-clock when accessing the RAM in AXI_DMA. 0: A gate-clock will be used when accessing the RAM in AXI_DMA. + 0 + 1 + read-write + + + IN_MEM_FORCE_PU + Force power up ram + 1 + 1 + read-write + + + IN_MEM_FORCE_PD + Force power down ram + 2 + 1 + read-write + + + OUT_MEM_CLK_FORCE_EN + 1: Force to open the clock and bypass the gate-clock when accessing the RAM in AXI_DMA. 0: A gate-clock will be used when accessing the RAM in AXI_DMA. + 3 + 1 + read-write + + + OUT_MEM_FORCE_PU + Force power up ram + 4 + 1 + read-write + + + OUT_MEM_FORCE_PD + Force power down ram + 5 + 1 + read-write + + + + + INTR_MEM_START_ADDR + The start address of accessible address space. + 0x27C + 0x20 + 0x30100000 + + + ACCESS_INTR_MEM_START_ADDR + The start address of accessible address space. + 0 + 32 + read-write + + + + + INTR_MEM_END_ADDR + The end address of accessible address space. The access address beyond this range would lead to descriptor error. + 0x280 + 0x20 + 0x8FFFFFFF + + + ACCESS_INTR_MEM_END_ADDR + The end address of accessible address space. The access address beyond this range would lead to descriptor error. + 0 + 32 + read-write + + + + + EXTR_MEM_START_ADDR + The start address of accessible address space. + 0x284 + 0x20 + 0x30100000 + + + ACCESS_EXTR_MEM_START_ADDR + The start address of accessible address space. + 0 + 32 + read-write + + + + + EXTR_MEM_END_ADDR + The end address of accessible address space. The access address beyond this range would lead to descriptor error. + 0x288 + 0x20 + 0x8FFFFFFF + + + ACCESS_EXTR_MEM_END_ADDR + The end address of accessible address space. The access address beyond this range would lead to descriptor error. + 0 + 32 + read-write + + + + + 3 + 0x4 + IN_RESET_AVAIL_CH%s + The rx channel 0 reset valid_flag register. + 0x28C + 0x20 + 0x00000001 + + + IN_RESET_AVAIL_CH + rx chan0 reset valid reg. + 0 + 1 + read-only + + + + + 3 + 0x4 + OUT_RESET_AVAIL_CH%s + The tx channel 0 reset valid_flag register. + 0x298 + 0x20 + 0x00000001 + + + OUT_RESET_AVAIL_CH + tx chan0 reset valid reg. + 0 + 1 + read-only + + + + + MISC_CONF + MISC register + 0x2A8 + 0x20 + + + AXIM_RST_WR_INTER + Set this bit then clear this bit to reset the internal axi_wr FSM. + 0 + 1 + read-write + + + AXIM_RST_RD_INTER + Set this bit then clear this bit to reset the internal axi_rd FSM. + 1 + 1 + read-write + + + ARB_PRI_DIS + Set this bit to disable priority arbitration function. + 3 + 1 + read-write + + + CLK_EN + 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers. + 4 + 1 + read-write + + + + + RDN_RESULT + reserved + 0x2AC + 0x20 + + + RDN_ENA + reserved + 0 + 1 + read-write + + + RDN_RESULT + reserved + 1 + 1 + read-only + + + + + RDN_ECO_HIGH + reserved + 0x2B0 + 0x20 + 0xFFFFFFFF + + + RDN_ECO_HIGH + The start address of accessible address space. + 0 + 32 + read-write + + + + + RDN_ECO_LOW + reserved + 0x2B4 + 0x20 + + + RDN_ECO_LOW + The start address of accessible address space. + 0 + 32 + read-write + + + + + WRESP_CNT + AXI wr responce cnt register. + 0x2B8 + 0x20 + + + WRESP_CNT + axi wr responce cnt reg. + 0 + 4 + read-only + + + + + RRESP_CNT + AXI wr responce cnt register. + 0x2BC + 0x20 + + + RRESP_CNT + axi rd responce cnt reg. + 0 + 4 + read-only + + + + + 3 + 0x4 + INFIFO_STATUS1_CH%s + Receive FIFO status of Rx channel 0 + 0x2C0 + 0x20 + + + L1INFIFO_CNT_CH + The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0. + 0 + 6 + read-only + + + L2INFIFO_CNT_CH + The register stores the byte number of the data in L2 Rx FIFO for Rx channel 0. + 6 + 4 + read-only + + + + + 3 + 0x4 + OUTFIFO_STATUS1_CH%s + Receive FIFO status of Tx channel 0 + 0x2CC + 0x20 + + + L1OUTFIFO_CNT_CH + The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0. + 0 + 6 + read-only + + + L2OUTFIFO_CNT_CH + The register stores the byte number of the data in L2 Tx FIFO for Tx channel 0. + 6 + 4 + read-only + + + + + DATE + Version control register + 0x2D8 + 0x20 + 0x02303140 + + + DATE + register version. + 0 + 32 + read-write + + + + + + + BITSCRAMBLER + BITSCRAMBLER Peripheral + BITSCRAMBLER + 0x500A3000 + + 0x0 + 0x40 + registers + + + + TX_INST_CFG0 + Control and configuration registers + 0x0 + 0x20 + + + TX_INST_IDX + write this bits to specify the one of 8 instruction + 0 + 3 + read-write + + + TX_INST_POS + write this bits to specify the bit position of 257 bit instruction which in units of 32 bits + 3 + 4 + read-write + + + + + TX_INST_CFG1 + Control and configuration registers + 0x4 + 0x20 + 0x00000004 + + + TX_INST + write this bits to update instruction which specified by BITSCRAMBLER_TX_INST_CFG0_REG, Read this bits to get instruction which specified by BITSCRAMBLER_TX_INST_CFG0_REG + 0 + 32 + read-write + + + + + RX_INST_CFG0 + Control and configuration registers + 0x8 + 0x20 + + + RX_INST_IDX + write this bits to specify the one of 8 instruction + 0 + 3 + read-write + + + RX_INST_POS + write this bits to specify the bit position of 257 bit instruction which in units of 32 bits + 3 + 4 + read-write + + + + + RX_INST_CFG1 + Control and configuration registers + 0xC + 0x20 + 0x0000000C + + + RX_INST + write this bits to update instruction which specified by BITSCRAMBLER_RX_INST_CFG0_REG, Read this bits to get instruction which specified by BITSCRAMBLER_RX_INST_CFG0_REG + 0 + 32 + read-write + + + + + TX_LUT_CFG0 + Control and configuration registers + 0x10 + 0x20 + + + TX_LUT_IDX + write this bits to specify the bytes position of LUT RAM based on reg_bitscrambler_tx_lut_mode + 0 + 11 + read-write + + + TX_LUT_MODE + write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4 bytes + 11 + 2 + read-write + + + + + TX_LUT_CFG1 + Control and configuration registers + 0x14 + 0x20 + 0x00000014 + + + TX_LUT + write this bits to update LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG, Read this bits to get LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG + 0 + 32 + read-write + + + + + RX_LUT_CFG0 + Control and configuration registers + 0x18 + 0x20 + + + RX_LUT_IDX + write this bits to specify the bytes position of LUT RAM based on reg_bitscrambler_rx_lut_mode + 0 + 11 + read-write + + + RX_LUT_MODE + write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4 bytes + 11 + 2 + read-write + + + + + RX_LUT_CFG1 + Control and configuration registers + 0x1C + 0x20 + 0x0000001C + + + RX_LUT + write this bits to update LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG, Read this bits to get LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG + 0 + 32 + read-write + + + + + TX_TAILING_BITS + Control and configuration registers + 0x20 + 0x20 + + + TX_TAILING_BITS + write this bits to specify the extra data bit length after getting EOF + 0 + 16 + read-write + + + + + RX_TAILING_BITS + Control and configuration registers + 0x24 + 0x20 + + + RX_TAILING_BITS + write this bits to specify the extra data bit length after getting EOF + 0 + 16 + read-write + + + + + TX_CTRL + Control and configuration registers + 0x28 + 0x20 + 0x00000004 + + + TX_ENA + write this bit to enable the bitscrambler tx + 0 + 1 + read-write + + + TX_PAUSE + write this bit to pause the bitscrambler tx core + 1 + 1 + read-write + + + TX_HALT + write this bit to halt the bitscrambler tx core + 2 + 1 + read-write + + + TX_EOF_MODE + write this bit to ser the bitscrambler tx core EOF signal generating mode which is combined with reg_bitscrambler_tx_tailing_bits, 0: counter by read dma fifo, 0 counter by write peripheral buffer + 3 + 1 + read-write + + + TX_COND_MODE + write this bit to specify the LOOP instruction condition mode of bitscrambler tx core, 0: use the little than operator to get the condition, 1: use not equal operator to get the condition + 4 + 1 + read-write + + + TX_FETCH_MODE + write this bit to set the bitscrambler tx core fetch instruction mode, 0: prefetch by reset, 1: fetch by instrutions + 5 + 1 + read-write + + + TX_HALT_MODE + write this bit to set the bitscrambler tx core halt mode when tx_halt is set, 0: wait write data back done, , 1: ignore write data back + 6 + 1 + read-write + + + TX_RD_DUMMY + write this bit to set the bitscrambler tx core read data mode when EOF received.0: wait read data, 1: ignore read data + 7 + 1 + read-write + + + TX_FIFO_RST + write this bit to reset the bitscrambler tx fifo + 8 + 1 + write-only + + + + + RX_CTRL + Control and configuration registers + 0x2C + 0x20 + 0x00000004 + + + RX_ENA + write this bit to enable the bitscrambler rx + 0 + 1 + read-write + + + RX_PAUSE + write this bit to pause the bitscrambler rx core + 1 + 1 + read-write + + + RX_HALT + write this bit to halt the bitscrambler rx core + 2 + 1 + read-write + + + RX_EOF_MODE + write this bit to ser the bitscrambler rx core EOF signal generating mode which is combined with reg_bitscrambler_rx_tailing_bits, 0: counter by read peripheral buffer, 0 counter by write dma fifo + 3 + 1 + read-write + + + RX_COND_MODE + write this bit to specify the LOOP instruction condition mode of bitscrambler rx core, 0: use the little than operator to get the condition, 1: use not equal operator to get the condition + 4 + 1 + read-write + + + RX_FETCH_MODE + write this bit to set the bitscrambler rx core fetch instruction mode, 0: prefetch by reset, 1: fetch by instrutions + 5 + 1 + read-write + + + RX_HALT_MODE + write this bit to set the bitscrambler rx core halt mode when rx_halt is set, 0: wait write data back done, , 1: ignore write data back + 6 + 1 + read-write + + + RX_RD_DUMMY + write this bit to set the bitscrambler rx core read data mode when EOF received.0: wait read data, 1: ignore read data + 7 + 1 + read-write + + + RX_FIFO_RST + write this bit to reset the bitscrambler rx fifo + 8 + 1 + write-only + + + + + TX_STATE + Status registers + 0x30 + 0x20 + 0x00000001 + + + TX_IN_IDLE + represents the bitscrambler tx core in halt mode + 0 + 1 + read-only + + + TX_IN_RUN + represents the bitscrambler tx core in run mode + 1 + 1 + read-only + + + TX_IN_WAIT + represents the bitscrambler tx core in wait mode to wait write back done + 2 + 1 + read-only + + + TX_IN_PAUSE + represents the bitscrambler tx core in pause mode + 3 + 1 + read-only + + + TX_FIFO_EMPTY + represents the bitscrambler tx fifo in empty state + 4 + 1 + read-only + + + TX_EOF_GET_CNT + represents the bytes numbers of bitscrambler tx core when get EOF + 16 + 14 + read-only + + + TX_EOF_OVERLOAD + represents the some EOFs will be lost for bitscrambler tx core + 30 + 1 + read-only + + + TX_EOF_TRACE_CLR + write this bit to clear reg_bitscrambler_tx_eof_overload and reg_bitscrambler_tx_eof_get_cnt registers + 31 + 1 + write-only + + + + + RX_STATE + Status registers + 0x34 + 0x20 + 0x00000001 + + + RX_IN_IDLE + represents the bitscrambler rx core in halt mode + 0 + 1 + read-only + + + RX_IN_RUN + represents the bitscrambler rx core in run mode + 1 + 1 + read-only + + + RX_IN_WAIT + represents the bitscrambler rx core in wait mode to wait write back done + 2 + 1 + read-only + + + RX_IN_PAUSE + represents the bitscrambler rx core in pause mode + 3 + 1 + read-only + + + RX_FIFO_FULL + represents the bitscrambler rx fifo in full state + 4 + 1 + read-only + + + RX_EOF_GET_CNT + represents the bytes numbers of bitscrambler rx core when get EOF + 16 + 14 + read-only + + + RX_EOF_OVERLOAD + represents the some EOFs will be lost for bitscrambler rx core + 30 + 1 + read-only + + + RX_EOF_TRACE_CLR + write this bit to clear reg_bitscrambler_rx_eof_overload and reg_bitscrambler_rx_eof_get_cnt registers + 31 + 1 + write-only + + + + + SYS + Control and configuration registers + 0xF8 + 0x20 + + + LOOP_MODE + write this bit to set the bitscrambler tx loop back to DMA rx + 0 + 1 + read-write + + + CLK_EN + Reserved + 31 + 1 + read-write + + + + + VERSION + Control and configuration registers + 0xFC + 0x20 + 0x02303240 + + + BITSCRAMBLER_VER + Reserved + 0 + 28 + read-write + + + + + + + CACHE + CACHE Peripheral + CACHE + 0x3FF10000 + + 0x0 + 0x3F0 + registers + + + CACHE + 83 + + + + L1_ICACHE_CTRL + L1 instruction Cache(L1-ICache) control register + 0x0 + 0x20 + + + L1_ICACHE_SHUT_IBUS0 + The bit is used to disable core0 ibus access L1-ICache, 0: enable, 1: disable + 0 + 1 + read-write + + + L1_ICACHE_SHUT_IBUS1 + The bit is used to disable core1 ibus access L1-ICache, 0: enable, 1: disable + 1 + 1 + read-write + + + L1_ICACHE_SHUT_IBUS2 + Reserved + 2 + 1 + read-only + + + L1_ICACHE_SHUT_IBUS3 + Reserved + 3 + 1 + read-only + + + L1_ICACHE_UNDEF_OP + Reserved + 8 + 8 + read-write + + + + + L1_DCACHE_CTRL + L1 data Cache(L1-DCache) control register + 0x4 + 0x20 + + + L1_DCACHE_SHUT_DBUS0 + The bit is used to disable core0 dbus access L1-DCache, 0: enable, 1: disable + 0 + 1 + read-write + + + L1_DCACHE_SHUT_DBUS1 + The bit is used to disable core1 dbus access L1-DCache, 0: enable, 1: disable + 1 + 1 + read-write + + + L1_DCACHE_SHUT_DBUS2 + Reserved + 2 + 1 + read-only + + + L1_DCACHE_SHUT_DBUS3 + Reserved + 3 + 1 + read-only + + + L1_DCACHE_SHUT_DMA + The bit is used to disable DMA access L1-DCache, 0: enable, 1: disable + 4 + 1 + read-write + + + L1_DCACHE_UNDEF_OP + Reserved + 8 + 8 + read-write + + + + + L1_BYPASS_CACHE_CONF + Bypass Cache configure register + 0x8 + 0x20 + + + BYPASS_L1_ICACHE0_EN + The bit is used to enable bypass L1-ICache0. 0: disable bypass, 1: enable bypass. + 0 + 1 + read-write + + + BYPASS_L1_ICACHE1_EN + The bit is used to enable bypass L1-ICache1. 0: disable bypass, 1: enable bypass. + 1 + 1 + read-write + + + BYPASS_L1_ICACHE2_EN + Reserved + 2 + 1 + read-only + + + BYPASS_L1_ICACHE3_EN + Reserved + 3 + 1 + read-only + + + BYPASS_L1_DCACHE_EN + The bit is used to enable bypass L1-DCache. 0: disable bypass, 1: enable bypass. + 4 + 1 + read-write + + + + + L1_CACHE_ATOMIC_CONF + L1 Cache atomic feature configure register + 0xC + 0x20 + 0x00000001 + + + L1_DCACHE_ATOMIC_EN + The bit is used to enable atomic feature on L1-DCache when multiple cores access L1-DCache. 1: disable, 1: enable. + 0 + 1 + read-write + + + + + L1_ICACHE_CACHESIZE_CONF + L1 instruction Cache CacheSize mode configure register + 0x10 + 0x20 + 0x00000040 + + + L1_ICACHE_CACHESIZE_256 + The field is used to configure cachesize of L1-ICache as 256 bytes. This field and all other fields within this register is onehot. + 0 + 1 + read-only + + + L1_ICACHE_CACHESIZE_512 + The field is used to configure cachesize of L1-ICache as 512 bytes. This field and all other fields within this register is onehot. + 1 + 1 + read-only + + + L1_ICACHE_CACHESIZE_1K + The field is used to configure cachesize of L1-ICache as 1k bytes. This field and all other fields within this register is onehot. + 2 + 1 + read-only + + + L1_ICACHE_CACHESIZE_2K + The field is used to configure cachesize of L1-ICache as 2k bytes. This field and all other fields within this register is onehot. + 3 + 1 + read-only + + + L1_ICACHE_CACHESIZE_4K + The field is used to configure cachesize of L1-ICache as 4k bytes. This field and all other fields within this register is onehot. + 4 + 1 + read-only + + + L1_ICACHE_CACHESIZE_8K + The field is used to configure cachesize of L1-ICache as 8k bytes. This field and all other fields within this register is onehot. + 5 + 1 + read-only + + + L1_ICACHE_CACHESIZE_16K + The field is used to configure cachesize of L1-ICache as 16k bytes. This field and all other fields within this register is onehot. + 6 + 1 + read-only + + + L1_ICACHE_CACHESIZE_32K + The field is used to configure cachesize of L1-ICache as 32k bytes. This field and all other fields within this register is onehot. + 7 + 1 + read-only + + + L1_ICACHE_CACHESIZE_64K + The field is used to configure cachesize of L1-ICache as 64k bytes. This field and all other fields within this register is onehot. + 8 + 1 + read-only + + + L1_ICACHE_CACHESIZE_128K + The field is used to configure cachesize of L1-ICache as 128k bytes. This field and all other fields within this register is onehot. + 9 + 1 + read-only + + + L1_ICACHE_CACHESIZE_256K + The field is used to configure cachesize of L1-ICache as 256k bytes. This field and all other fields within this register is onehot. + 10 + 1 + read-only + + + L1_ICACHE_CACHESIZE_512K + The field is used to configure cachesize of L1-ICache as 512k bytes. This field and all other fields within this register is onehot. + 11 + 1 + read-only + + + L1_ICACHE_CACHESIZE_1024K + The field is used to configure cachesize of L1-ICache as 1024k bytes. This field and all other fields within this register is onehot. + 12 + 1 + read-only + + + + + L1_ICACHE_BLOCKSIZE_CONF + L1 instruction Cache BlockSize mode configure register + 0x14 + 0x20 + 0x00000008 + + + L1_ICACHE_BLOCKSIZE_8 + The field is used to configureblocksize of L1-ICache as 8 bytes. This field and all other fields within this register is onehot. + 0 + 1 + read-only + + + L1_ICACHE_BLOCKSIZE_16 + The field is used to configureblocksize of L1-ICache as 16 bytes. This field and all other fields within this register is onehot. + 1 + 1 + read-only + + + L1_ICACHE_BLOCKSIZE_32 + The field is used to configureblocksize of L1-ICache as 32 bytes. This field and all other fields within this register is onehot. + 2 + 1 + read-only + + + L1_ICACHE_BLOCKSIZE_64 + The field is used to configureblocksize of L1-ICache as 64 bytes. This field and all other fields within this register is onehot. + 3 + 1 + read-only + + + L1_ICACHE_BLOCKSIZE_128 + The field is used to configureblocksize of L1-ICache as 128 bytes. This field and all other fields within this register is onehot. + 4 + 1 + read-only + + + L1_ICACHE_BLOCKSIZE_256 + The field is used to configureblocksize of L1-ICache as 256 bytes. This field and all other fields within this register is onehot. + 5 + 1 + read-only + + + + + L1_DCACHE_CACHESIZE_CONF + L1 data Cache CacheSize mode configure register + 0x18 + 0x20 + 0x00000100 + + + L1_DCACHE_CACHESIZE_256 + The field is used to configure cachesize of L1-DCache as 256 bytes. This field and all other fields within this register is onehot. + 0 + 1 + read-only + + + L1_DCACHE_CACHESIZE_512 + The field is used to configure cachesize of L1-DCache as 512 bytes. This field and all other fields within this register is onehot. + 1 + 1 + read-only + + + L1_DCACHE_CACHESIZE_1K + The field is used to configure cachesize of L1-DCache as 1k bytes. This field and all other fields within this register is onehot. + 2 + 1 + read-only + + + L1_DCACHE_CACHESIZE_2K + The field is used to configure cachesize of L1-DCache as 2k bytes. This field and all other fields within this register is onehot. + 3 + 1 + read-only + + + L1_DCACHE_CACHESIZE_4K + The field is used to configure cachesize of L1-DCache as 4k bytes. This field and all other fields within this register is onehot. + 4 + 1 + read-only + + + L1_DCACHE_CACHESIZE_8K + The field is used to configure cachesize of L1-DCache as 8k bytes. This field and all other fields within this register is onehot. + 5 + 1 + read-only + + + L1_DCACHE_CACHESIZE_16K + The field is used to configure cachesize of L1-DCache as 16k bytes. This field and all other fields within this register is onehot. + 6 + 1 + read-only + + + L1_DCACHE_CACHESIZE_32K + The field is used to configure cachesize of L1-DCache as 32k bytes. This field and all other fields within this register is onehot. + 7 + 1 + read-only + + + L1_DCACHE_CACHESIZE_64K + The field is used to configure cachesize of L1-DCache as 64k bytes. This field and all other fields within this register is onehot. + 8 + 1 + read-only + + + L1_DCACHE_CACHESIZE_128K + The field is used to configure cachesize of L1-DCache as 128k bytes. This field and all other fields within this register is onehot. + 9 + 1 + read-only + + + L1_DCACHE_CACHESIZE_256K + The field is used to configure cachesize of L1-DCache as 256k bytes. This field and all other fields within this register is onehot. + 10 + 1 + read-only + + + L1_DCACHE_CACHESIZE_512K + The field is used to configure cachesize of L1-DCache as 512k bytes. This field and all other fields within this register is onehot. + 11 + 1 + read-only + + + L1_DCACHE_CACHESIZE_1024K + The field is used to configure cachesize of L1-DCache as 1024k bytes. This field and all other fields within this register is onehot. + 12 + 1 + read-only + + + + + L1_DCACHE_BLOCKSIZE_CONF + L1 data Cache BlockSize mode configure register + 0x1C + 0x20 + 0x00000008 + + + L1_DCACHE_BLOCKSIZE_8 + The field is used to configureblocksize of L1-DCache as 8 bytes. This field and all other fields within this register is onehot. + 0 + 1 + read-only + + + L1_DCACHE_BLOCKSIZE_16 + The field is used to configureblocksize of L1-DCache as 16 bytes. This field and all other fields within this register is onehot. + 1 + 1 + read-only + + + L1_DCACHE_BLOCKSIZE_32 + The field is used to configureblocksize of L1-DCache as 32 bytes. This field and all other fields within this register is onehot. + 2 + 1 + read-only + + + L1_DCACHE_BLOCKSIZE_64 + The field is used to configureblocksize of L1-DCache as 64 bytes. This field and all other fields within this register is onehot. + 3 + 1 + read-only + + + L1_DCACHE_BLOCKSIZE_128 + The field is used to configureblocksize of L1-DCache as 128 bytes. This field and all other fields within this register is onehot. + 4 + 1 + read-only + + + L1_DCACHE_BLOCKSIZE_256 + The field is used to configureblocksize of L1-DCache as 256 bytes. This field and all other fields within this register is onehot. + 5 + 1 + read-only + + + + + L1_CACHE_WRAP_AROUND_CTRL + Cache wrap around control register + 0x20 + 0x20 + + + L1_ICACHE0_WRAP + Set this bit as 1 to enable L1-ICache0 wrap around mode. + 0 + 1 + read-write + + + L1_ICACHE1_WRAP + Set this bit as 1 to enable L1-ICache1 wrap around mode. + 1 + 1 + read-write + + + L1_ICACHE2_WRAP + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_WRAP + Reserved + 3 + 1 + read-only + + + L1_DCACHE_WRAP + Set this bit as 1 to enable L1-DCache wrap around mode. + 4 + 1 + read-write + + + + + L1_CACHE_TAG_MEM_POWER_CTRL + Cache tag memory power control register + 0x24 + 0x20 + 0x00055555 + + + L1_ICACHE0_TAG_MEM_FORCE_ON + The bit is used to close clock gating of L1-ICache0 tag memory. 1: close gating, 0: open clock gating. + 0 + 1 + read-write + + + L1_ICACHE0_TAG_MEM_FORCE_PD + The bit is used to power L1-ICache0 tag memory down. 0: follow rtc_lslp, 1: power down + 1 + 1 + read-write + + + L1_ICACHE0_TAG_MEM_FORCE_PU + The bit is used to power L1-ICache0 tag memory up. 0: follow rtc_lslp, 1: power up + 2 + 1 + read-write + + + L1_ICACHE1_TAG_MEM_FORCE_ON + The bit is used to close clock gating of L1-ICache1 tag memory. 1: close gating, 0: open clock gating. + 4 + 1 + read-write + + + L1_ICACHE1_TAG_MEM_FORCE_PD + The bit is used to power L1-ICache1 tag memory down. 0: follow rtc_lslp, 1: power down + 5 + 1 + read-write + + + L1_ICACHE1_TAG_MEM_FORCE_PU + The bit is used to power L1-ICache1 tag memory up. 0: follow rtc_lslp, 1: power up + 6 + 1 + read-write + + + L1_ICACHE2_TAG_MEM_FORCE_ON + Reserved + 8 + 1 + read-only + + + L1_ICACHE2_TAG_MEM_FORCE_PD + Reserved + 9 + 1 + read-only + + + L1_ICACHE2_TAG_MEM_FORCE_PU + Reserved + 10 + 1 + read-only + + + L1_ICACHE3_TAG_MEM_FORCE_ON + Reserved + 12 + 1 + read-only + + + L1_ICACHE3_TAG_MEM_FORCE_PD + Reserved + 13 + 1 + read-only + + + L1_ICACHE3_TAG_MEM_FORCE_PU + Reserved + 14 + 1 + read-only + + + L1_DCACHE_TAG_MEM_FORCE_ON + The bit is used to close clock gating of L1-DCache tag memory. 1: close gating, 0: open clock gating. + 16 + 1 + read-write + + + L1_DCACHE_TAG_MEM_FORCE_PD + The bit is used to power L1-DCache tag memory down. 0: follow rtc_lslp, 1: power down + 17 + 1 + read-write + + + L1_DCACHE_TAG_MEM_FORCE_PU + The bit is used to power L1-DCache tag memory up. 0: follow rtc_lslp, 1: power up + 18 + 1 + read-write + + + + + L1_CACHE_DATA_MEM_POWER_CTRL + Cache data memory power control register + 0x28 + 0x20 + 0x00055555 + + + L1_ICACHE0_DATA_MEM_FORCE_ON + The bit is used to close clock gating of L1-ICache0 data memory. 1: close gating, 0: open clock gating. + 0 + 1 + read-write + + + L1_ICACHE0_DATA_MEM_FORCE_PD + The bit is used to power L1-ICache0 data memory down. 0: follow rtc_lslp, 1: power down + 1 + 1 + read-write + + + L1_ICACHE0_DATA_MEM_FORCE_PU + The bit is used to power L1-ICache0 data memory up. 0: follow rtc_lslp, 1: power up + 2 + 1 + read-write + + + L1_ICACHE1_DATA_MEM_FORCE_ON + The bit is used to close clock gating of L1-ICache1 data memory. 1: close gating, 0: open clock gating. + 4 + 1 + read-write + + + L1_ICACHE1_DATA_MEM_FORCE_PD + The bit is used to power L1-ICache1 data memory down. 0: follow rtc_lslp, 1: power down + 5 + 1 + read-write + + + L1_ICACHE1_DATA_MEM_FORCE_PU + The bit is used to power L1-ICache1 data memory up. 0: follow rtc_lslp, 1: power up + 6 + 1 + read-write + + + L1_ICACHE2_DATA_MEM_FORCE_ON + Reserved + 8 + 1 + read-only + + + L1_ICACHE2_DATA_MEM_FORCE_PD + Reserved + 9 + 1 + read-only + + + L1_ICACHE2_DATA_MEM_FORCE_PU + Reserved + 10 + 1 + read-only + + + L1_ICACHE3_DATA_MEM_FORCE_ON + Reserved + 12 + 1 + read-only + + + L1_ICACHE3_DATA_MEM_FORCE_PD + Reserved + 13 + 1 + read-only + + + L1_ICACHE3_DATA_MEM_FORCE_PU + Reserved + 14 + 1 + read-only + + + L1_DCACHE_DATA_MEM_FORCE_ON + The bit is used to close clock gating of L1-DCache data memory. 1: close gating, 0: open clock gating. + 16 + 1 + read-write + + + L1_DCACHE_DATA_MEM_FORCE_PD + The bit is used to power L1-DCache data memory down. 0: follow rtc_lslp, 1: power down + 17 + 1 + read-write + + + L1_DCACHE_DATA_MEM_FORCE_PU + The bit is used to power L1-DCache data memory up. 0: follow rtc_lslp, 1: power up + 18 + 1 + read-write + + + + + L1_CACHE_FREEZE_CTRL + Cache Freeze control register + 0x2C + 0x20 + + + L1_ICACHE0_FREEZE_EN + The bit is used to enable freeze operation on L1-ICache0. It can be cleared by software. + 0 + 1 + read-write + + + L1_ICACHE0_FREEZE_MODE + The bit is used to configure mode of freeze operation L1-ICache0. 0: a miss-access will not stuck. 1: a miss-access will stuck. + 1 + 1 + read-write + + + L1_ICACHE0_FREEZE_DONE + The bit is used to indicate whether freeze operation on L1-ICache0 is finished or not. 0: not finished. 1: finished. + 2 + 1 + read-only + + + L1_ICACHE1_FREEZE_EN + The bit is used to enable freeze operation on L1-ICache1. It can be cleared by software. + 4 + 1 + read-write + + + L1_ICACHE1_FREEZE_MODE + The bit is used to configure mode of freeze operation L1-ICache1. 0: a miss-access will not stuck. 1: a miss-access will stuck. + 5 + 1 + read-write + + + L1_ICACHE1_FREEZE_DONE + The bit is used to indicate whether freeze operation on L1-ICache1 is finished or not. 0: not finished. 1: finished. + 6 + 1 + read-only + + + L1_ICACHE2_FREEZE_EN + Reserved + 8 + 1 + read-only + + + L1_ICACHE2_FREEZE_MODE + Reserved + 9 + 1 + read-only + + + L1_ICACHE2_FREEZE_DONE + Reserved + 10 + 1 + read-only + + + L1_ICACHE3_FREEZE_EN + Reserved + 12 + 1 + read-only + + + L1_ICACHE3_FREEZE_MODE + Reserved + 13 + 1 + read-only + + + L1_ICACHE3_FREEZE_DONE + Reserved + 14 + 1 + read-only + + + L1_DCACHE_FREEZE_EN + The bit is used to enable freeze operation on L1-DCache. It can be cleared by software. + 16 + 1 + read-write + + + L1_DCACHE_FREEZE_MODE + The bit is used to configure mode of freeze operation L1-DCache. 0: a miss-access will not stuck. 1: a miss-access will stuck. + 17 + 1 + read-write + + + L1_DCACHE_FREEZE_DONE + The bit is used to indicate whether freeze operation on L1-DCache is finished or not. 0: not finished. 1: finished. + 18 + 1 + read-only + + + + + L1_CACHE_DATA_MEM_ACS_CONF + Cache data memory access configure register + 0x30 + 0x20 + 0x00033333 + + + L1_ICACHE0_DATA_MEM_RD_EN + The bit is used to enable config-bus read L1-ICache0 data memoryory. 0: disable, 1: enable. + 0 + 1 + read-write + + + L1_ICACHE0_DATA_MEM_WR_EN + The bit is used to enable config-bus write L1-ICache0 data memoryory. 0: disable, 1: enable. + 1 + 1 + read-write + + + L1_ICACHE1_DATA_MEM_RD_EN + The bit is used to enable config-bus read L1-ICache1 data memoryory. 0: disable, 1: enable. + 4 + 1 + read-write + + + L1_ICACHE1_DATA_MEM_WR_EN + The bit is used to enable config-bus write L1-ICache1 data memoryory. 0: disable, 1: enable. + 5 + 1 + read-write + + + L1_ICACHE2_DATA_MEM_RD_EN + Reserved + 8 + 1 + read-only + + + L1_ICACHE2_DATA_MEM_WR_EN + Reserved + 9 + 1 + read-only + + + L1_ICACHE3_DATA_MEM_RD_EN + Reserved + 12 + 1 + read-only + + + L1_ICACHE3_DATA_MEM_WR_EN + Reserved + 13 + 1 + read-only + + + L1_DCACHE_DATA_MEM_RD_EN + The bit is used to enable config-bus read L1-DCache data memoryory. 0: disable, 1: enable. + 16 + 1 + read-write + + + L1_DCACHE_DATA_MEM_WR_EN + The bit is used to enable config-bus write L1-DCache data memoryory. 0: disable, 1: enable. + 17 + 1 + read-write + + + + + L1_CACHE_TAG_MEM_ACS_CONF + Cache tag memory access configure register + 0x34 + 0x20 + 0x00033333 + + + L1_ICACHE0_TAG_MEM_RD_EN + The bit is used to enable config-bus read L1-ICache0 tag memoryory. 0: disable, 1: enable. + 0 + 1 + read-write + + + L1_ICACHE0_TAG_MEM_WR_EN + The bit is used to enable config-bus write L1-ICache0 tag memoryory. 0: disable, 1: enable. + 1 + 1 + read-write + + + L1_ICACHE1_TAG_MEM_RD_EN + The bit is used to enable config-bus read L1-ICache1 tag memoryory. 0: disable, 1: enable. + 4 + 1 + read-write + + + L1_ICACHE1_TAG_MEM_WR_EN + The bit is used to enable config-bus write L1-ICache1 tag memoryory. 0: disable, 1: enable. + 5 + 1 + read-write + + + L1_ICACHE2_TAG_MEM_RD_EN + Reserved + 8 + 1 + read-only + + + L1_ICACHE2_TAG_MEM_WR_EN + Reserved + 9 + 1 + read-only + + + L1_ICACHE3_TAG_MEM_RD_EN + Reserved + 12 + 1 + read-only + + + L1_ICACHE3_TAG_MEM_WR_EN + Reserved + 13 + 1 + read-only + + + L1_DCACHE_TAG_MEM_RD_EN + The bit is used to enable config-bus read L1-DCache tag memoryory. 0: disable, 1: enable. + 16 + 1 + read-write + + + L1_DCACHE_TAG_MEM_WR_EN + The bit is used to enable config-bus write L1-DCache tag memoryory. 0: disable, 1: enable. + 17 + 1 + read-write + + + + + L1_ICACHE0_PRELOCK_CONF + L1 instruction Cache 0 prelock configure register + 0x38 + 0x20 + + + L1_ICACHE0_PRELOCK_SCT0_EN + The bit is used to enable the first section of prelock function on L1-ICache0. + 0 + 1 + read-write + + + L1_ICACHE0_PRELOCK_SCT1_EN + The bit is used to enable the second section of prelock function on L1-ICache0. + 1 + 1 + read-write + + + L1_ICACHE0_PRELOCK_RGID + The bit is used to set the gid of l1 icache0 prelock. + 2 + 4 + read-write + + + + + L1_ICACHE0_PRELOCK_SCT0_ADDR + L1 instruction Cache 0 prelock section0 address configure register + 0x3C + 0x20 + + + L1_ICACHE0_PRELOCK_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_SIZE_REG + 0 + 32 + read-write + + + + + L1_ICACHE0_PRELOCK_SCT1_ADDR + L1 instruction Cache 0 prelock section1 address configure register + 0x40 + 0x20 + + + L1_ICACHE0_PRELOCK_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_SIZE_REG + 0 + 32 + read-write + + + + + L1_ICACHE0_PRELOCK_SCT_SIZE + L1 instruction Cache 0 prelock section size configure register + 0x44 + 0x20 + 0x3FFF3FFF + + + L1_ICACHE0_PRELOCK_SCT0_SIZE + Those bits are used to configure the size of the first section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_ADDR_REG + 0 + 14 + read-write + + + L1_ICACHE0_PRELOCK_SCT1_SIZE + Those bits are used to configure the size of the second section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_ADDR_REG + 16 + 14 + read-write + + + + + L1_ICACHE1_PRELOCK_CONF + L1 instruction Cache 1 prelock configure register + 0x48 + 0x20 + + + L1_ICACHE1_PRELOCK_SCT0_EN + The bit is used to enable the first section of prelock function on L1-ICache1. + 0 + 1 + read-write + + + L1_ICACHE1_PRELOCK_SCT1_EN + The bit is used to enable the second section of prelock function on L1-ICache1. + 1 + 1 + read-write + + + L1_ICACHE1_PRELOCK_RGID + The bit is used to set the gid of l1 icache1 prelock. + 2 + 4 + read-write + + + + + L1_ICACHE1_PRELOCK_SCT0_ADDR + L1 instruction Cache 1 prelock section0 address configure register + 0x4C + 0x20 + + + L1_ICACHE1_PRELOCK_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_SIZE_REG + 0 + 32 + read-write + + + + + L1_ICACHE1_PRELOCK_SCT1_ADDR + L1 instruction Cache 1 prelock section1 address configure register + 0x50 + 0x20 + + + L1_ICACHE1_PRELOCK_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_SIZE_REG + 0 + 32 + read-write + + + + + L1_ICACHE1_PRELOCK_SCT_SIZE + L1 instruction Cache 1 prelock section size configure register + 0x54 + 0x20 + 0x3FFF3FFF + + + L1_ICACHE1_PRELOCK_SCT0_SIZE + Those bits are used to configure the size of the first section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_ADDR_REG + 0 + 14 + read-write + + + L1_ICACHE1_PRELOCK_SCT1_SIZE + Those bits are used to configure the size of the second section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_ADDR_REG + 16 + 14 + read-write + + + + + L1_ICACHE2_PRELOCK_CONF + L1 instruction Cache 2 prelock configure register + 0x58 + 0x20 + + + L1_ICACHE2_PRELOCK_SCT0_EN + The bit is used to enable the first section of prelock function on L1-ICache2. + 0 + 1 + read-only + + + L1_ICACHE2_PRELOCK_SCT1_EN + The bit is used to enable the second section of prelock function on L1-ICache2. + 1 + 1 + read-only + + + L1_ICACHE2_PRELOCK_RGID + The bit is used to set the gid of l1 icache2 prelock. + 2 + 4 + read-only + + + + + L1_ICACHE2_PRELOCK_SCT0_ADDR + L1 instruction Cache 2 prelock section0 address configure register + 0x5C + 0x20 + + + L1_ICACHE2_PRELOCK_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section of prelock on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT0_SIZE_REG + 0 + 32 + read-only + + + + + L1_ICACHE2_PRELOCK_SCT1_ADDR + L1 instruction Cache 2 prelock section1 address configure register + 0x60 + 0x20 + + + L1_ICACHE2_PRELOCK_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section of prelock on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT1_SIZE_REG + 0 + 32 + read-only + + + + + L1_ICACHE2_PRELOCK_SCT_SIZE + L1 instruction Cache 2 prelock section size configure register + 0x64 + 0x20 + 0x3FFF3FFF + + + L1_ICACHE2_PRELOCK_SCT0_SIZE + Those bits are used to configure the size of the first section of prelock on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT0_ADDR_REG + 0 + 14 + read-only + + + L1_ICACHE2_PRELOCK_SCT1_SIZE + Those bits are used to configure the size of the second section of prelock on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT1_ADDR_REG + 16 + 14 + read-only + + + + + L1_ICACHE3_PRELOCK_CONF + L1 instruction Cache 3 prelock configure register + 0x68 + 0x20 + + + L1_ICACHE3_PRELOCK_SCT0_EN + The bit is used to enable the first section of prelock function on L1-ICache3. + 0 + 1 + read-only + + + L1_ICACHE3_PRELOCK_SCT1_EN + The bit is used to enable the second section of prelock function on L1-ICache3. + 1 + 1 + read-only + + + L1_ICACHE3_PRELOCK_RGID + The bit is used to set the gid of l1 icache3 prelock. + 2 + 4 + read-only + + + + + L1_ICACHE3_PRELOCK_SCT0_ADDR + L1 instruction Cache 3 prelock section0 address configure register + 0x6C + 0x20 + + + L1_ICACHE3_PRELOCK_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section of prelock on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT0_SIZE_REG + 0 + 32 + read-only + + + + + L1_ICACHE3_PRELOCK_SCT1_ADDR + L1 instruction Cache 3 prelock section1 address configure register + 0x70 + 0x20 + + + L1_ICACHE3_PRELOCK_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section of prelock on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT1_SIZE_REG + 0 + 32 + read-only + + + + + L1_ICACHE3_PRELOCK_SCT_SIZE + L1 instruction Cache 3 prelock section size configure register + 0x74 + 0x20 + 0x3FFF3FFF + + + L1_ICACHE3_PRELOCK_SCT0_SIZE + Those bits are used to configure the size of the first section of prelock on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT0_ADDR_REG + 0 + 14 + read-only + + + L1_ICACHE3_PRELOCK_SCT1_SIZE + Those bits are used to configure the size of the second section of prelock on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT1_ADDR_REG + 16 + 14 + read-only + + + + + L1_DCACHE_PRELOCK_CONF + L1 data Cache prelock configure register + 0x78 + 0x20 + + + L1_DCACHE_PRELOCK_SCT0_EN + The bit is used to enable the first section of prelock function on L1-DCache. + 0 + 1 + read-write + + + L1_DCACHE_PRELOCK_SCT1_EN + The bit is used to enable the second section of prelock function on L1-DCache. + 1 + 1 + read-write + + + L1_DCACHE_PRELOCK_RGID + The bit is used to set the gid of l1 dcache prelock. + 2 + 4 + read-write + + + + + L1_DCACHE_PRELOCK_SCT0_ADDR + L1 data Cache prelock section0 address configure register + 0x7C + 0x20 + + + L1_DCACHE_PRELOCK_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section of prelock on L1-DCache, which should be used together with L1_DCACHE_PRELOCK_SCT0_SIZE_REG + 0 + 32 + read-write + + + + + L1_DCACHE_PRELOCK_SCT1_ADDR + L1 data Cache prelock section1 address configure register + 0x80 + 0x20 + + + L1_DCACHE_PRELOCK_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section of prelock on L1-DCache, which should be used together with L1_DCACHE_PRELOCK_SCT1_SIZE_REG + 0 + 32 + read-write + + + + + L1_DCACHE_PRELOCK_SCT_SIZE + L1 data Cache prelock section size configure register + 0x84 + 0x20 + 0x3FFF3FFF + + + L1_DCACHE_PRELOCK_SCT0_SIZE + Those bits are used to configure the size of the first section of prelock on L1-DCache, which should be used together with L1_DCACHE_PRELOCK_SCT0_ADDR_REG + 0 + 14 + read-write + + + L1_DCACHE_PRELOCK_SCT1_SIZE + Those bits are used to configure the size of the second section of prelock on L1-DCache, which should be used together with L1_DCACHE_PRELOCK_SCT1_ADDR_REG + 16 + 14 + read-write + + + + + LOCK_CTRL + Lock-class (manual lock) operation control register + 0x88 + 0x20 + 0x00000004 + + + LOCK_ENA + The bit is used to enable lock operation. It will be cleared by hardware after lock operation done. Note that (1) this bit and unlock_ena bit are mutually exclusive, that is, those bits can not be set to 1 at the same time. (2) lock operation can be applied on LL1-ICache, L1-DCache and L2-Cache. + 0 + 1 + read-write + + + UNLOCK_ENA + The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done. Note that (1) this bit and lock_ena bit are mutually exclusive, that is, those bits can not be set to 1 at the same time. (2) unlock operation can be applied on L1-ICache, L1-DCache and L2-Cache. + 1 + 1 + read-write + + + LOCK_DONE + The bit is used to indicate whether unlock/lock operation is finished or not. 0: not finished. 1: finished. + 2 + 1 + read-only + + + LOCK_RGID + The bit is used to set the gid of cache lock/unlock. + 3 + 4 + read-write + + + + + LOCK_MAP + Lock (manual lock) map configure register + 0x8C + 0x20 + + + LOCK_MAP + Those bits are used to indicate which caches in the two-level cache structure will apply this lock/unlock operation. [0]: L1-ICache0, [1]: L1-ICache1, [2]: L1-ICache2, [3]: L1-ICache3, [4]: L1-DCache, [5]: L2-Cache. + 0 + 6 + read-write + + + + + LOCK_ADDR + Lock (manual lock) address configure register + 0x90 + 0x20 + + + LOCK_ADDR + Those bits are used to configure the start virtual address of the lock/unlock operation, which should be used together with CACHE_LOCK_SIZE_REG + 0 + 32 + read-write + + + + + LOCK_SIZE + Lock (manual lock) size configure register + 0x94 + 0x20 + + + LOCK_SIZE + Those bits are used to configure the size of the lock/unlock operation, which should be used together with CACHE_LOCK_ADDR_REG + 0 + 16 + read-write + + + + + SYNC_CTRL + Sync-class operation control register + 0x98 + 0x20 + 0x00000001 + + + INVALIDATE_ENA + The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done. Note that this bit and the other sync-bits (clean_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time. + 0 + 1 + read-write + + + CLEAN_ENA + The bit is used to enable clean operation. It will be cleared by hardware after clean operation done. Note that this bit and the other sync-bits (invalidate_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time. + 1 + 1 + read-write + + + WRITEBACK_ENA + The bit is used to enable writeback operation. It will be cleared by hardware after writeback operation done. Note that this bit and the other sync-bits (invalidate_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time. + 2 + 1 + read-write + + + WRITEBACK_INVALIDATE_ENA + The bit is used to enable writeback-invalidate operation. It will be cleared by hardware after writeback-invalidate operation done. Note that this bit and the other sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time. + 3 + 1 + read-write + + + SYNC_DONE + The bit is used to indicate whether sync operation (invalidate, clean, writeback, writeback_invalidate) is finished or not. 0: not finished. 1: finished. + 4 + 1 + read-only + + + SYNC_RGID + The bit is used to set the gid of cache sync operation (invalidate, clean, writeback, writeback_invalidate) + 5 + 4 + read-write + + + + + SYNC_MAP + Sync map configure register + 0x9C + 0x20 + 0x0000001F + + + SYNC_MAP + Those bits are used to indicate which caches in the two-level cache structure will apply the sync operation. [0]: L1-ICache0, [1]: L1-ICache1, [2]: L1-ICache2, [3]: L1-ICache3, [4]: L1-DCache, [5]: L2-Cache. + 0 + 6 + read-write + + + + + SYNC_ADDR + Sync address configure register + 0xA0 + 0x20 + + + SYNC_ADDR + Those bits are used to configure the start virtual address of the sync operation, which should be used together with CACHE_SYNC_SIZE_REG + 0 + 32 + read-write + + + + + SYNC_SIZE + Sync size configure register + 0xA4 + 0x20 + + + SYNC_SIZE + Those bits are used to configure the size of the sync operation, which should be used together with CACHE_SYNC_ADDR_REG + 0 + 28 + read-write + + + + + L1_ICACHE0_PRELOAD_CTRL + L1 instruction Cache 0 preload-operation control register + 0xA8 + 0x20 + 0x00000002 + + + L1_ICACHE0_PRELOAD_ENA + The bit is used to enable preload operation on L1-ICache0. It will be cleared by hardware automatically after preload operation is done. + 0 + 1 + read-write + + + L1_ICACHE0_PRELOAD_DONE + The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished. + 1 + 1 + read-only + + + L1_ICACHE0_PRELOAD_ORDER + The bit is used to configure the direction of preload operation. 0: ascending, 1: descending. + 2 + 1 + read-write + + + L1_ICACHE0_PRELOAD_RGID + The bit is used to set the gid of l1 icache0 preload. + 3 + 4 + read-write + + + + + L1_ICACHE0_PRELOAD_ADDR + L1 instruction Cache 0 preload address configure register + 0xAC + 0x20 + + + L1_ICACHE0_PRELOAD_ADDR + Those bits are used to configure the start virtual address of preload on L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_SIZE_REG + 0 + 32 + read-write + + + + + L1_ICACHE0_PRELOAD_SIZE + L1 instruction Cache 0 preload size configure register + 0xB0 + 0x20 + + + L1_ICACHE0_PRELOAD_SIZE + Those bits are used to configure the size of the first section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_ADDR_REG + 0 + 14 + read-write + + + + + L1_ICACHE1_PRELOAD_CTRL + L1 instruction Cache 1 preload-operation control register + 0xB4 + 0x20 + 0x00000002 + + + L1_ICACHE1_PRELOAD_ENA + The bit is used to enable preload operation on L1-ICache1. It will be cleared by hardware automatically after preload operation is done. + 0 + 1 + read-write + + + L1_ICACHE1_PRELOAD_DONE + The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished. + 1 + 1 + read-only + + + L1_ICACHE1_PRELOAD_ORDER + The bit is used to configure the direction of preload operation. 0: ascending, 1: descending. + 2 + 1 + read-write + + + L1_ICACHE1_PRELOAD_RGID + The bit is used to set the gid of l1 icache1 preload. + 3 + 4 + read-write + + + + + L1_ICACHE1_PRELOAD_ADDR + L1 instruction Cache 1 preload address configure register + 0xB8 + 0x20 + + + L1_ICACHE1_PRELOAD_ADDR + Those bits are used to configure the start virtual address of preload on L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_SIZE_REG + 0 + 32 + read-write + + + + + L1_ICACHE1_PRELOAD_SIZE + L1 instruction Cache 1 preload size configure register + 0xBC + 0x20 + + + L1_ICACHE1_PRELOAD_SIZE + Those bits are used to configure the size of the first section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_ADDR_REG + 0 + 14 + read-write + + + + + L1_ICACHE2_PRELOAD_CTRL + L1 instruction Cache 2 preload-operation control register + 0xC0 + 0x20 + 0x00000002 + + + L1_ICACHE2_PRELOAD_ENA + The bit is used to enable preload operation on L1-ICache2. It will be cleared by hardware automatically after preload operation is done. + 0 + 1 + read-only + + + L1_ICACHE2_PRELOAD_DONE + The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished. + 1 + 1 + read-only + + + L1_ICACHE2_PRELOAD_ORDER + The bit is used to configure the direction of preload operation. 0: ascending, 1: descending. + 2 + 1 + read-only + + + L1_ICACHE2_PRELOAD_RGID + The bit is used to set the gid of l1 icache2 preload. + 3 + 4 + read-only + + + + + L1_ICACHE2_PRELOAD_ADDR + L1 instruction Cache 2 preload address configure register + 0xC4 + 0x20 + + + L1_ICACHE2_PRELOAD_ADDR + Those bits are used to configure the start virtual address of preload on L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_SIZE_REG + 0 + 32 + read-only + + + + + L1_ICACHE2_PRELOAD_SIZE + L1 instruction Cache 2 preload size configure register + 0xC8 + 0x20 + + + L1_ICACHE2_PRELOAD_SIZE + Those bits are used to configure the size of the first section of prelock on L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_ADDR_REG + 0 + 14 + read-only + + + + + L1_ICACHE3_PRELOAD_CTRL + L1 instruction Cache 3 preload-operation control register + 0xCC + 0x20 + 0x00000002 + + + L1_ICACHE3_PRELOAD_ENA + The bit is used to enable preload operation on L1-ICache3. It will be cleared by hardware automatically after preload operation is done. + 0 + 1 + read-only + + + L1_ICACHE3_PRELOAD_DONE + The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished. + 1 + 1 + read-only + + + L1_ICACHE3_PRELOAD_ORDER + The bit is used to configure the direction of preload operation. 0: ascending, 1: descending. + 2 + 1 + read-only + + + L1_ICACHE3_PRELOAD_RGID + The bit is used to set the gid of l1 icache3 preload. + 3 + 4 + read-only + + + + + L1_ICACHE3_PRELOAD_ADDR + L1 instruction Cache 3 preload address configure register + 0xD0 + 0x20 + + + L1_ICACHE3_PRELOAD_ADDR + Those bits are used to configure the start virtual address of preload on L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_SIZE_REG + 0 + 32 + read-only + + + + + L1_ICACHE3_PRELOAD_SIZE + L1 instruction Cache 3 preload size configure register + 0xD4 + 0x20 + + + L1_ICACHE3_PRELOAD_SIZE + Those bits are used to configure the size of the first section of prelock on L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_ADDR_REG + 0 + 14 + read-only + + + + + L1_DCACHE_PRELOAD_CTRL + L1 data Cache preload-operation control register + 0xD8 + 0x20 + 0x00000002 + + + L1_DCACHE_PRELOAD_ENA + The bit is used to enable preload operation on L1-DCache. It will be cleared by hardware automatically after preload operation is done. + 0 + 1 + read-write + + + L1_DCACHE_PRELOAD_DONE + The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished. + 1 + 1 + read-only + + + L1_DCACHE_PRELOAD_ORDER + The bit is used to configure the direction of preload operation. 0: ascending, 1: descending. + 2 + 1 + read-write + + + L1_DCACHE_PRELOAD_RGID + The bit is used to set the gid of l1 dcache preload. + 3 + 4 + read-write + + + + + L1_DCACHE_PRELOAD_ADDR + L1 data Cache preload address configure register + 0xDC + 0x20 + + + L1_DCACHE_PRELOAD_ADDR + Those bits are used to configure the start virtual address of preload on L1-DCache, which should be used together with L1_DCACHE_PRELOAD_SIZE_REG + 0 + 32 + read-write + + + + + L1_DCACHE_PRELOAD_SIZE + L1 data Cache preload size configure register + 0xE0 + 0x20 + + + L1_DCACHE_PRELOAD_SIZE + Those bits are used to configure the size of the first section of prelock on L1-DCache, which should be used together with L1_DCACHE_PRELOAD_ADDR_REG + 0 + 14 + read-write + + + + + L1_ICACHE0_AUTOLOAD_CTRL + L1 instruction Cache 0 autoload-operation control register + 0xE4 + 0x20 + 0x00000002 + + + L1_ICACHE0_AUTOLOAD_ENA + The bit is used to enable and disable autoload operation on L1-ICache0. 1: enable, 0: disable. + 0 + 1 + read-write + + + L1_ICACHE0_AUTOLOAD_DONE + The bit is used to indicate whether autoload operation on L1-ICache0 is finished or not. 0: not finished. 1: finished. + 1 + 1 + read-only + + + L1_ICACHE0_AUTOLOAD_ORDER + The bit is used to configure the direction of autoload operation on L1-ICache0. 0: ascending. 1: descending. + 2 + 1 + read-write + + + L1_ICACHE0_AUTOLOAD_TRIGGER_MODE + The field is used to configure trigger mode of autoload operation on L1-ICache0. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + 3 + 2 + read-write + + + L1_ICACHE0_AUTOLOAD_SCT0_ENA + The bit is used to enable the first section for autoload operation on L1-ICache0. + 8 + 1 + read-write + + + L1_ICACHE0_AUTOLOAD_SCT1_ENA + The bit is used to enable the second section for autoload operation on L1-ICache0. + 9 + 1 + read-write + + + L1_ICACHE0_AUTOLOAD_RGID + The bit is used to set the gid of l1 icache0 autoload. + 10 + 4 + read-write + + + + + L1_ICACHE0_AUTOLOAD_SCT0_ADDR + L1 instruction Cache 0 autoload section 0 address configure register + 0xE8 + 0x20 + + + L1_ICACHE0_AUTOLOAD_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section for autoload operation on L1-ICache0. Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. + 0 + 32 + read-write + + + + + L1_ICACHE0_AUTOLOAD_SCT0_SIZE + L1 instruction Cache 0 autoload section 0 size configure register + 0xEC + 0x20 + + + L1_ICACHE0_AUTOLOAD_SCT0_SIZE + Those bits are used to configure the size of the first section for autoload operation on L1-ICache0. Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. + 0 + 28 + read-write + + + + + L1_ICACHE0_AUTOLOAD_SCT1_ADDR + L1 instruction Cache 0 autoload section 1 address configure register + 0xF0 + 0x20 + + + L1_ICACHE0_AUTOLOAD_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section for autoload operation on L1-ICache0. Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. + 0 + 32 + read-write + + + + + L1_ICACHE0_AUTOLOAD_SCT1_SIZE + L1 instruction Cache 0 autoload section 1 size configure register + 0xF4 + 0x20 + + + L1_ICACHE0_AUTOLOAD_SCT1_SIZE + Those bits are used to configure the size of the second section for autoload operation on L1-ICache0. Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA. + 0 + 28 + read-write + + + + + L1_ICACHE1_AUTOLOAD_CTRL + L1 instruction Cache 1 autoload-operation control register + 0xF8 + 0x20 + 0x00000002 + + + L1_ICACHE1_AUTOLOAD_ENA + The bit is used to enable and disable autoload operation on L1-ICache1. 1: enable, 0: disable. + 0 + 1 + read-write + + + L1_ICACHE1_AUTOLOAD_DONE + The bit is used to indicate whether autoload operation on L1-ICache1 is finished or not. 0: not finished. 1: finished. + 1 + 1 + read-only + + + L1_ICACHE1_AUTOLOAD_ORDER + The bit is used to configure the direction of autoload operation on L1-ICache1. 0: ascending. 1: descending. + 2 + 1 + read-write + + + L1_ICACHE1_AUTOLOAD_TRIGGER_MODE + The field is used to configure trigger mode of autoload operation on L1-ICache1. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + 3 + 2 + read-write + + + L1_ICACHE1_AUTOLOAD_SCT0_ENA + The bit is used to enable the first section for autoload operation on L1-ICache1. + 8 + 1 + read-write + + + L1_ICACHE1_AUTOLOAD_SCT1_ENA + The bit is used to enable the second section for autoload operation on L1-ICache1. + 9 + 1 + read-write + + + L1_ICACHE1_AUTOLOAD_RGID + The bit is used to set the gid of l1 icache1 autoload. + 10 + 4 + read-write + + + + + L1_ICACHE1_AUTOLOAD_SCT0_ADDR + L1 instruction Cache 1 autoload section 0 address configure register + 0xFC + 0x20 + + + L1_ICACHE1_AUTOLOAD_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section for autoload operation on L1-ICache1. Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. + 0 + 32 + read-write + + + + + L1_ICACHE1_AUTOLOAD_SCT0_SIZE + L1 instruction Cache 1 autoload section 0 size configure register + 0x100 + 0x20 + + + L1_ICACHE1_AUTOLOAD_SCT0_SIZE + Those bits are used to configure the size of the first section for autoload operation on L1-ICache1. Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. + 0 + 28 + read-write + + + + + L1_ICACHE1_AUTOLOAD_SCT1_ADDR + L1 instruction Cache 1 autoload section 1 address configure register + 0x104 + 0x20 + + + L1_ICACHE1_AUTOLOAD_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section for autoload operation on L1-ICache1. Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. + 0 + 32 + read-write + + + + + L1_ICACHE1_AUTOLOAD_SCT1_SIZE + L1 instruction Cache 1 autoload section 1 size configure register + 0x108 + 0x20 + + + L1_ICACHE1_AUTOLOAD_SCT1_SIZE + Those bits are used to configure the size of the second section for autoload operation on L1-ICache1. Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA. + 0 + 28 + read-write + + + + + L1_ICACHE2_AUTOLOAD_CTRL + L1 instruction Cache 2 autoload-operation control register + 0x10C + 0x20 + 0x00000002 + + + L1_ICACHE2_AUTOLOAD_ENA + The bit is used to enable and disable autoload operation on L1-ICache2. 1: enable, 0: disable. + 0 + 1 + read-only + + + L1_ICACHE2_AUTOLOAD_DONE + The bit is used to indicate whether autoload operation on L1-ICache2 is finished or not. 0: not finished. 1: finished. + 1 + 1 + read-only + + + L1_ICACHE2_AUTOLOAD_ORDER + The bit is used to configure the direction of autoload operation on L1-ICache2. 0: ascending. 1: descending. + 2 + 1 + read-only + + + L1_ICACHE2_AUTOLOAD_TRIGGER_MODE + The field is used to configure trigger mode of autoload operation on L1-ICache2. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + 3 + 2 + read-only + + + L1_ICACHE2_AUTOLOAD_SCT0_ENA + The bit is used to enable the first section for autoload operation on L1-ICache2. + 8 + 1 + read-only + + + L1_ICACHE2_AUTOLOAD_SCT1_ENA + The bit is used to enable the second section for autoload operation on L1-ICache2. + 9 + 1 + read-only + + + L1_ICACHE2_AUTOLOAD_RGID + The bit is used to set the gid of l1 icache2 autoload. + 10 + 4 + read-only + + + + + L1_ICACHE2_AUTOLOAD_SCT0_ADDR + L1 instruction Cache 2 autoload section 0 address configure register + 0x110 + 0x20 + + + L1_ICACHE2_AUTOLOAD_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section for autoload operation on L1-ICache2. Note that it should be used together with L1_ICACHE2_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. + 0 + 32 + read-only + + + + + L1_ICACHE2_AUTOLOAD_SCT0_SIZE + L1 instruction Cache 2 autoload section 0 size configure register + 0x114 + 0x20 + + + L1_ICACHE2_AUTOLOAD_SCT0_SIZE + Those bits are used to configure the size of the first section for autoload operation on L1-ICache2. Note that it should be used together with L1_ICACHE2_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. + 0 + 28 + read-only + + + + + L1_ICACHE2_AUTOLOAD_SCT1_ADDR + L1 instruction Cache 2 autoload section 1 address configure register + 0x118 + 0x20 + + + L1_ICACHE2_AUTOLOAD_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section for autoload operation on L1-ICache2. Note that it should be used together with L1_ICACHE2_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. + 0 + 32 + read-only + + + + + L1_ICACHE2_AUTOLOAD_SCT1_SIZE + L1 instruction Cache 2 autoload section 1 size configure register + 0x11C + 0x20 + + + L1_ICACHE2_AUTOLOAD_SCT1_SIZE + Those bits are used to configure the size of the second section for autoload operation on L1-ICache2. Note that it should be used together with L1_ICACHE2_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA. + 0 + 28 + read-only + + + + + L1_ICACHE3_AUTOLOAD_CTRL + L1 instruction Cache 3 autoload-operation control register + 0x120 + 0x20 + 0x00000002 + + + L1_ICACHE3_AUTOLOAD_ENA + The bit is used to enable and disable autoload operation on L1-ICache3. 1: enable, 0: disable. + 0 + 1 + read-only + + + L1_ICACHE3_AUTOLOAD_DONE + The bit is used to indicate whether autoload operation on L1-ICache3 is finished or not. 0: not finished. 1: finished. + 1 + 1 + read-only + + + L1_ICACHE3_AUTOLOAD_ORDER + The bit is used to configure the direction of autoload operation on L1-ICache3. 0: ascending. 1: descending. + 2 + 1 + read-only + + + L1_ICACHE3_AUTOLOAD_TRIGGER_MODE + The field is used to configure trigger mode of autoload operation on L1-ICache3. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + 3 + 2 + read-only + + + L1_ICACHE3_AUTOLOAD_SCT0_ENA + The bit is used to enable the first section for autoload operation on L1-ICache3. + 8 + 1 + read-only + + + L1_ICACHE3_AUTOLOAD_SCT1_ENA + The bit is used to enable the second section for autoload operation on L1-ICache3. + 9 + 1 + read-only + + + L1_ICACHE3_AUTOLOAD_RGID + The bit is used to set the gid of l1 icache3 autoload. + 10 + 4 + read-only + + + + + L1_ICACHE3_AUTOLOAD_SCT0_ADDR + L1 instruction Cache 3 autoload section 0 address configure register + 0x124 + 0x20 + + + L1_ICACHE3_AUTOLOAD_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section for autoload operation on L1-ICache3. Note that it should be used together with L1_ICACHE3_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. + 0 + 32 + read-only + + + + + L1_ICACHE3_AUTOLOAD_SCT0_SIZE + L1 instruction Cache 3 autoload section 0 size configure register + 0x128 + 0x20 + + + L1_ICACHE3_AUTOLOAD_SCT0_SIZE + Those bits are used to configure the size of the first section for autoload operation on L1-ICache3. Note that it should be used together with L1_ICACHE3_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. + 0 + 28 + read-only + + + + + L1_ICACHE3_AUTOLOAD_SCT1_ADDR + L1 instruction Cache 3 autoload section 1 address configure register + 0x12C + 0x20 + + + L1_ICACHE3_AUTOLOAD_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section for autoload operation on L1-ICache3. Note that it should be used together with L1_ICACHE3_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. + 0 + 32 + read-only + + + + + L1_ICACHE3_AUTOLOAD_SCT1_SIZE + L1 instruction Cache 3 autoload section 1 size configure register + 0x130 + 0x20 + + + L1_ICACHE3_AUTOLOAD_SCT1_SIZE + Reserved + 0 + 28 + read-only + + + + + L1_DCACHE_AUTOLOAD_CTRL + L1 data Cache autoload-operation control register + 0x134 + 0x20 + 0x00000002 + + + L1_DCACHE_AUTOLOAD_ENA + The bit is used to enable and disable autoload operation on L1-DCache. 1: enable, 0: disable. + 0 + 1 + read-write + + + L1_DCACHE_AUTOLOAD_DONE + The bit is used to indicate whether autoload operation on L1-DCache is finished or not. 0: not finished. 1: finished. + 1 + 1 + read-only + + + L1_DCACHE_AUTOLOAD_ORDER + The bit is used to configure the direction of autoload operation on L1-DCache. 0: ascending. 1: descending. + 2 + 1 + read-write + + + L1_DCACHE_AUTOLOAD_TRIGGER_MODE + The field is used to configure trigger mode of autoload operation on L1-DCache. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + 3 + 2 + read-write + + + L1_DCACHE_AUTOLOAD_SCT0_ENA + The bit is used to enable the first section for autoload operation on L1-DCache. + 8 + 1 + read-write + + + L1_DCACHE_AUTOLOAD_SCT1_ENA + The bit is used to enable the second section for autoload operation on L1-DCache. + 9 + 1 + read-write + + + L1_DCACHE_AUTOLOAD_SCT2_ENA + The bit is used to enable the third section for autoload operation on L1-DCache. + 10 + 1 + read-write + + + L1_DCACHE_AUTOLOAD_SCT3_ENA + The bit is used to enable the fourth section for autoload operation on L1-DCache. + 11 + 1 + read-write + + + L1_DCACHE_AUTOLOAD_RGID + The bit is used to set the gid of l1 dcache autoload. + 12 + 4 + read-write + + + + + L1_DCACHE_AUTOLOAD_SCT0_ADDR + L1 data Cache autoload section 0 address configure register + 0x138 + 0x20 + + + L1_DCACHE_AUTOLOAD_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT0_SIZE and L1_DCACHE_AUTOLOAD_SCT0_ENA. + 0 + 32 + read-write + + + + + L1_DCACHE_AUTOLOAD_SCT0_SIZE + L1 data Cache autoload section 0 size configure register + 0x13C + 0x20 + + + L1_DCACHE_AUTOLOAD_SCT0_SIZE + Those bits are used to configure the size of the first section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT0_ADDR and L1_DCACHE_AUTOLOAD_SCT0_ENA. + 0 + 28 + read-write + + + + + L1_DCACHE_AUTOLOAD_SCT1_ADDR + L1 data Cache autoload section 1 address configure register + 0x140 + 0x20 + + + L1_DCACHE_AUTOLOAD_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT1_SIZE and L1_DCACHE_AUTOLOAD_SCT1_ENA. + 0 + 32 + read-write + + + + + L1_DCACHE_AUTOLOAD_SCT1_SIZE + L1 data Cache autoload section 1 size configure register + 0x144 + 0x20 + + + L1_DCACHE_AUTOLOAD_SCT1_SIZE + Those bits are used to configure the size of the second section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT1_ADDR and L1_DCACHE_AUTOLOAD_SCT1_ENA. + 0 + 28 + read-write + + + + + L1_DCACHE_AUTOLOAD_SCT2_ADDR + L1 data Cache autoload section 2 address configure register + 0x148 + 0x20 + + + L1_DCACHE_AUTOLOAD_SCT2_ADDR + Those bits are used to configure the start virtual address of the third section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT2_SIZE and L1_DCACHE_AUTOLOAD_SCT2_ENA. + 0 + 32 + read-write + + + + + L1_DCACHE_AUTOLOAD_SCT2_SIZE + L1 data Cache autoload section 2 size configure register + 0x14C + 0x20 + + + L1_DCACHE_AUTOLOAD_SCT2_SIZE + Those bits are used to configure the size of the third section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT2_ADDR and L1_DCACHE_AUTOLOAD_SCT2_ENA. + 0 + 28 + read-write + + + + + L1_DCACHE_AUTOLOAD_SCT3_ADDR + L1 data Cache autoload section 1 address configure register + 0x150 + 0x20 + + + L1_DCACHE_AUTOLOAD_SCT3_ADDR + Those bits are used to configure the start virtual address of the fourth section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT3_SIZE and L1_DCACHE_AUTOLOAD_SCT3_ENA. + 0 + 32 + read-write + + + + + L1_DCACHE_AUTOLOAD_SCT3_SIZE + L1 data Cache autoload section 1 size configure register + 0x154 + 0x20 + + + L1_DCACHE_AUTOLOAD_SCT3_SIZE + Those bits are used to configure the size of the fourth section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT3_ADDR and L1_DCACHE_AUTOLOAD_SCT3_ENA. + 0 + 28 + read-write + + + + + L1_CACHE_ACS_CNT_INT_ENA + Cache Access Counter Interrupt enable register + 0x158 + 0x20 + + + L1_IBUS0_OVF_INT_ENA + The bit is used to enable interrupt of one of counters overflow that occurs in L1-ICache0 due to bus0 accesses L1-ICache0. + 0 + 1 + read-write + + + L1_IBUS1_OVF_INT_ENA + The bit is used to enable interrupt of one of counters overflow that occurs in L1-ICache1 due to bus1 accesses L1-ICache1. + 1 + 1 + read-write + + + L1_IBUS2_OVF_INT_ENA + Reserved + 2 + 1 + read-only + + + L1_IBUS3_OVF_INT_ENA + Reserved + 3 + 1 + read-only + + + L1_DBUS0_OVF_INT_ENA + The bit is used to enable interrupt of one of counters overflow that occurs in L1-DCache due to bus0 accesses L1-DCache. + 4 + 1 + read-write + + + L1_DBUS1_OVF_INT_ENA + The bit is used to enable interrupt of one of counters overflow that occurs in L1-DCache due to bus1 accesses L1-DCache. + 5 + 1 + read-write + + + L1_DBUS2_OVF_INT_ENA + Reserved + 6 + 1 + read-only + + + L1_DBUS3_OVF_INT_ENA + Reserved + 7 + 1 + read-only + + + + + L1_CACHE_ACS_CNT_INT_CLR + Cache Access Counter Interrupt clear register + 0x15C + 0x20 + + + L1_IBUS0_OVF_INT_CLR + The bit is used to clear counters overflow interrupt and counters in L1-ICache0 due to bus0 accesses L1-ICache0. + 0 + 1 + write-only + + + L1_IBUS1_OVF_INT_CLR + The bit is used to clear counters overflow interrupt and counters in L1-ICache1 due to bus1 accesses L1-ICache1. + 1 + 1 + write-only + + + L1_IBUS2_OVF_INT_CLR + Reserved + 2 + 1 + read-only + + + L1_IBUS3_OVF_INT_CLR + Reserved + 3 + 1 + read-only + + + L1_DBUS0_OVF_INT_CLR + The bit is used to clear counters overflow interrupt and counters in L1-DCache due to bus0 accesses L1-DCache. + 4 + 1 + write-only + + + L1_DBUS1_OVF_INT_CLR + The bit is used to clear counters overflow interrupt and counters in L1-DCache due to bus1 accesses L1-DCache. + 5 + 1 + write-only + + + L1_DBUS2_OVF_INT_CLR + Reserved + 6 + 1 + read-only + + + L1_DBUS3_OVF_INT_CLR + Reserved + 7 + 1 + read-only + + + + + L1_CACHE_ACS_CNT_INT_RAW + Cache Access Counter Interrupt raw register + 0x160 + 0x20 + + + L1_IBUS0_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache0 due to bus0 accesses L1-ICache0. + 0 + 1 + read-write + + + L1_IBUS1_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache1 due to bus1 accesses L1-ICache1. + 1 + 1 + read-write + + + L1_IBUS2_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache2 due to bus2 accesses L1-ICache2. + 2 + 1 + read-write + + + L1_IBUS3_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache3 due to bus3 accesses L1-ICache3. + 3 + 1 + read-write + + + L1_DBUS0_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache due to bus0 accesses L1-DCache. + 4 + 1 + read-write + + + L1_DBUS1_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache due to bus1 accesses L1-DCache. + 5 + 1 + read-write + + + L1_DBUS2_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache due to bus2 accesses L1-DCache. + 6 + 1 + read-write + + + L1_DBUS3_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache due to bus3 accesses L1-DCache. + 7 + 1 + read-write + + + + + L1_CACHE_ACS_CNT_INT_ST + Cache Access Counter Interrupt status register + 0x164 + 0x20 + + + L1_IBUS0_OVF_INT_ST + The bit indicates the interrupt status of one of counters overflow that occurs in L1-ICache0 due to bus0 accesses L1-ICache0. + 0 + 1 + read-only + + + L1_IBUS1_OVF_INT_ST + The bit indicates the interrupt status of one of counters overflow that occurs in L1-ICache1 due to bus1 accesses L1-ICache1. + 1 + 1 + read-only + + + L1_IBUS2_OVF_INT_ST + Reserved + 2 + 1 + read-only + + + L1_IBUS3_OVF_INT_ST + Reserved + 3 + 1 + read-only + + + L1_DBUS0_OVF_INT_ST + The bit indicates the interrupt status of one of counters overflow that occurs in L1-DCache due to bus0 accesses L1-DCache. + 4 + 1 + read-only + + + L1_DBUS1_OVF_INT_ST + The bit indicates the interrupt status of one of counters overflow that occurs in L1-DCache due to bus1 accesses L1-DCache. + 5 + 1 + read-only + + + L1_DBUS2_OVF_INT_ST + Reserved + 6 + 1 + read-only + + + L1_DBUS3_OVF_INT_ST + Reserved + 7 + 1 + read-only + + + + + L1_CACHE_ACS_FAIL_CTRL + Cache Access Fail Configuration register + 0x168 + 0x20 + + + L1_ICACHE0_ACS_FAIL_CHECK_MODE + The bit is used to configure l1 icache0 access fail check mode. 0: the access fail is not propagated to the request, 1: the access fail is propagated to the request + 0 + 1 + read-write + + + L1_ICACHE1_ACS_FAIL_CHECK_MODE + The bit is used to configure l1 icache1 access fail check mode. 0: the access fail is not propagated to the request, 1: the access fail is propagated to the request + 1 + 1 + read-write + + + L1_ICACHE2_ACS_FAIL_CHECK_MODE + The bit is used to configure l1 icache2 access fail check mode. 0: the access fail is not propagated to the request, 1: the access fail is propagated to the request + 2 + 1 + read-write + + + L1_ICACHE3_ACS_FAIL_CHECK_MODE + The bit is used to configure l1 icache3 access fail check mode. 0: the access fail is not propagated to the request, 1: the access fail is propagated to the request + 3 + 1 + read-write + + + L1_DCACHE_ACS_FAIL_CHECK_MODE + The bit is used to configure l1 dcache access fail check mode. 0: the access fail is not propagated to the request, 1: the access fail is propagated to the request + 4 + 1 + read-write + + + + + L1_CACHE_ACS_FAIL_INT_ENA + Cache Access Fail Interrupt enable register + 0x16C + 0x20 + + + L1_ICACHE0_FAIL_INT_ENA + The bit is used to enable interrupt of access fail that occurs in L1-ICache0 due to cpu accesses L1-ICache0. + 0 + 1 + read-write + + + L1_ICACHE1_FAIL_INT_ENA + The bit is used to enable interrupt of access fail that occurs in L1-ICache1 due to cpu accesses L1-ICache1. + 1 + 1 + read-write + + + L1_ICACHE2_FAIL_INT_ENA + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_FAIL_INT_ENA + Reserved + 3 + 1 + read-only + + + L1_DCACHE_FAIL_INT_ENA + The bit is used to enable interrupt of access fail that occurs in L1-DCache due to cpu accesses L1-DCache. + 4 + 1 + read-write + + + + + L1_CACHE_ACS_FAIL_INT_CLR + L1-Cache Access Fail Interrupt clear register + 0x170 + 0x20 + + + L1_ICACHE0_FAIL_INT_CLR + The bit is used to clear interrupt of access fail that occurs in L1-ICache0 due to cpu accesses L1-ICache0. + 0 + 1 + write-only + + + L1_ICACHE1_FAIL_INT_CLR + The bit is used to clear interrupt of access fail that occurs in L1-ICache1 due to cpu accesses L1-ICache1. + 1 + 1 + write-only + + + L1_ICACHE2_FAIL_INT_CLR + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_FAIL_INT_CLR + Reserved + 3 + 1 + read-only + + + L1_DCACHE_FAIL_INT_CLR + The bit is used to clear interrupt of access fail that occurs in L1-DCache due to cpu accesses L1-DCache. + 4 + 1 + write-only + + + + + L1_CACHE_ACS_FAIL_INT_RAW + Cache Access Fail Interrupt raw register + 0x174 + 0x20 + + + L1_ICACHE0_FAIL_INT_RAW + The raw bit of the interrupt of access fail that occurs in L1-ICache0. + 0 + 1 + read-write + + + L1_ICACHE1_FAIL_INT_RAW + The raw bit of the interrupt of access fail that occurs in L1-ICache1. + 1 + 1 + read-write + + + L1_ICACHE2_FAIL_INT_RAW + The raw bit of the interrupt of access fail that occurs in L1-ICache2. + 2 + 1 + read-write + + + L1_ICACHE3_FAIL_INT_RAW + The raw bit of the interrupt of access fail that occurs in L1-ICache3. + 3 + 1 + read-write + + + L1_DCACHE_FAIL_INT_RAW + The raw bit of the interrupt of access fail that occurs in L1-DCache. + 4 + 1 + read-write + + + + + L1_CACHE_ACS_FAIL_INT_ST + Cache Access Fail Interrupt status register + 0x178 + 0x20 + + + L1_ICACHE0_FAIL_INT_ST + The bit indicates the interrupt status of access fail that occurs in L1-ICache0 due to cpu accesses L1-ICache. + 0 + 1 + read-only + + + L1_ICACHE1_FAIL_INT_ST + The bit indicates the interrupt status of access fail that occurs in L1-ICache1 due to cpu accesses L1-ICache. + 1 + 1 + read-only + + + L1_ICACHE2_FAIL_INT_ST + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_FAIL_INT_ST + Reserved + 3 + 1 + read-only + + + L1_DCACHE_FAIL_INT_ST + The bit indicates the interrupt status of access fail that occurs in L1-DCache due to cpu accesses L1-DCache. + 4 + 1 + read-only + + + + + L1_CACHE_ACS_CNT_CTRL + Cache Access Counter enable and clear register + 0x17C + 0x20 + + + L1_IBUS0_CNT_ENA + The bit is used to enable ibus0 counter in L1-ICache0. + 0 + 1 + read-write + + + L1_IBUS1_CNT_ENA + The bit is used to enable ibus1 counter in L1-ICache1. + 1 + 1 + read-write + + + L1_IBUS2_CNT_ENA + Reserved + 2 + 1 + read-only + + + L1_IBUS3_CNT_ENA + Reserved + 3 + 1 + read-only + + + L1_DBUS0_CNT_ENA + The bit is used to enable dbus0 counter in L1-DCache. + 4 + 1 + read-write + + + L1_DBUS1_CNT_ENA + The bit is used to enable dbus1 counter in L1-DCache. + 5 + 1 + read-write + + + L1_DBUS2_CNT_ENA + Reserved + 6 + 1 + read-only + + + L1_DBUS3_CNT_ENA + Reserved + 7 + 1 + read-only + + + L1_IBUS0_CNT_CLR + The bit is used to clear ibus0 counter in L1-ICache0. + 16 + 1 + write-only + + + L1_IBUS1_CNT_CLR + The bit is used to clear ibus1 counter in L1-ICache1. + 17 + 1 + write-only + + + L1_IBUS2_CNT_CLR + Reserved + 18 + 1 + read-only + + + L1_IBUS3_CNT_CLR + Reserved + 19 + 1 + read-only + + + L1_DBUS0_CNT_CLR + The bit is used to clear dbus0 counter in L1-DCache. + 20 + 1 + write-only + + + L1_DBUS1_CNT_CLR + The bit is used to clear dbus1 counter in L1-DCache. + 21 + 1 + write-only + + + L1_DBUS2_CNT_CLR + Reserved + 22 + 1 + read-only + + + L1_DBUS3_CNT_CLR + Reserved + 23 + 1 + read-only + + + + + L1_IBUS0_ACS_HIT_CNT + L1-ICache bus0 Hit-Access Counter register + 0x180 + 0x20 + + + L1_IBUS0_HIT_CNT + The register records the number of hits when bus0 accesses L1-ICache0. + 0 + 32 + read-only + + + + + L1_IBUS0_ACS_MISS_CNT + L1-ICache bus0 Miss-Access Counter register + 0x184 + 0x20 + + + L1_IBUS0_MISS_CNT + The register records the number of missing when bus0 accesses L1-ICache0. + 0 + 32 + read-only + + + + + L1_IBUS0_ACS_CONFLICT_CNT + L1-ICache bus0 Conflict-Access Counter register + 0x188 + 0x20 + + + L1_IBUS0_CONFLICT_CNT + The register records the number of access-conflicts when bus0 accesses L1-ICache0. + 0 + 32 + read-only + + + + + L1_IBUS0_ACS_NXTLVL_RD_CNT + L1-ICache bus0 Next-Level-Access Counter register + 0x18C + 0x20 + + + L1_IBUS0_NXTLVL_RD_CNT + The register records the number of times that L1-ICache accesses L2-Cache due to bus0 accessing L1-ICache0. + 0 + 32 + read-only + + + + + L1_IBUS1_ACS_HIT_CNT + L1-ICache bus1 Hit-Access Counter register + 0x190 + 0x20 + + + L1_IBUS1_HIT_CNT + The register records the number of hits when bus1 accesses L1-ICache1. + 0 + 32 + read-only + + + + + L1_IBUS1_ACS_MISS_CNT + L1-ICache bus1 Miss-Access Counter register + 0x194 + 0x20 + + + L1_IBUS1_MISS_CNT + The register records the number of missing when bus1 accesses L1-ICache1. + 0 + 32 + read-only + + + + + L1_IBUS1_ACS_CONFLICT_CNT + L1-ICache bus1 Conflict-Access Counter register + 0x198 + 0x20 + + + L1_IBUS1_CONFLICT_CNT + The register records the number of access-conflicts when bus1 accesses L1-ICache1. + 0 + 32 + read-only + + + + + L1_IBUS1_ACS_NXTLVL_RD_CNT + L1-ICache bus1 Next-Level-Access Counter register + 0x19C + 0x20 + + + L1_IBUS1_NXTLVL_RD_CNT + The register records the number of times that L1-ICache accesses L2-Cache due to bus1 accessing L1-ICache1. + 0 + 32 + read-only + + + + + L1_IBUS2_ACS_HIT_CNT + L1-ICache bus2 Hit-Access Counter register + 0x1A0 + 0x20 + + + L1_IBUS2_HIT_CNT + The register records the number of hits when bus2 accesses L1-ICache2. + 0 + 32 + read-only + + + + + L1_IBUS2_ACS_MISS_CNT + L1-ICache bus2 Miss-Access Counter register + 0x1A4 + 0x20 + + + L1_IBUS2_MISS_CNT + The register records the number of missing when bus2 accesses L1-ICache2. + 0 + 32 + read-only + + + + + L1_IBUS2_ACS_CONFLICT_CNT + L1-ICache bus2 Conflict-Access Counter register + 0x1A8 + 0x20 + + + L1_IBUS2_CONFLICT_CNT + The register records the number of access-conflicts when bus2 accesses L1-ICache2. + 0 + 32 + read-only + + + + + L1_IBUS2_ACS_NXTLVL_RD_CNT + L1-ICache bus2 Next-Level-Access Counter register + 0x1AC + 0x20 + + + L1_IBUS2_NXTLVL_RD_CNT + The register records the number of times that L1-ICache accesses L2-Cache due to bus2 accessing L1-ICache2. + 0 + 32 + read-only + + + + + L1_IBUS3_ACS_HIT_CNT + L1-ICache bus3 Hit-Access Counter register + 0x1B0 + 0x20 + + + L1_IBUS3_HIT_CNT + The register records the number of hits when bus3 accesses L1-ICache3. + 0 + 32 + read-only + + + + + L1_IBUS3_ACS_MISS_CNT + L1-ICache bus3 Miss-Access Counter register + 0x1B4 + 0x20 + + + L1_IBUS3_MISS_CNT + The register records the number of missing when bus3 accesses L1-ICache3. + 0 + 32 + read-only + + + + + L1_IBUS3_ACS_CONFLICT_CNT + L1-ICache bus3 Conflict-Access Counter register + 0x1B8 + 0x20 + + + L1_IBUS3_CONFLICT_CNT + The register records the number of access-conflicts when bus3 accesses L1-ICache3. + 0 + 32 + read-only + + + + + L1_IBUS3_ACS_NXTLVL_RD_CNT + L1-ICache bus3 Next-Level-Access Counter register + 0x1BC + 0x20 + + + L1_IBUS3_NXTLVL_RD_CNT + The register records the number of times that L1-ICache accesses L2-Cache due to bus3 accessing L1-ICache3. + 0 + 32 + read-only + + + + + L1_DBUS0_ACS_HIT_CNT + L1-DCache bus0 Hit-Access Counter register + 0x1C0 + 0x20 + + + L1_DBUS0_HIT_CNT + The register records the number of hits when bus0 accesses L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS0_ACS_MISS_CNT + L1-DCache bus0 Miss-Access Counter register + 0x1C4 + 0x20 + + + L1_DBUS0_MISS_CNT + The register records the number of missing when bus0 accesses L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS0_ACS_CONFLICT_CNT + L1-DCache bus0 Conflict-Access Counter register + 0x1C8 + 0x20 + + + L1_DBUS0_CONFLICT_CNT + The register records the number of access-conflicts when bus0 accesses L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS0_ACS_NXTLVL_RD_CNT + L1-DCache bus0 Next-Level-Access Counter register + 0x1CC + 0x20 + + + L1_DBUS0_NXTLVL_RD_CNT + The register records the number of times that L1-DCache accesses L2-Cache due to bus0 accessing L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS0_ACS_NXTLVL_WR_CNT + L1-DCache bus0 WB-Access Counter register + 0x1D0 + 0x20 + + + L1_DBUS0_NXTLVL_WR_CNT + The register records the number of write back when bus0 accesses L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS1_ACS_HIT_CNT + L1-DCache bus1 Hit-Access Counter register + 0x1D4 + 0x20 + + + L1_DBUS1_HIT_CNT + The register records the number of hits when bus1 accesses L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS1_ACS_MISS_CNT + L1-DCache bus1 Miss-Access Counter register + 0x1D8 + 0x20 + + + L1_DBUS1_MISS_CNT + The register records the number of missing when bus1 accesses L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS1_ACS_CONFLICT_CNT + L1-DCache bus1 Conflict-Access Counter register + 0x1DC + 0x20 + + + L1_DBUS1_CONFLICT_CNT + The register records the number of access-conflicts when bus1 accesses L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS1_ACS_NXTLVL_RD_CNT + L1-DCache bus1 Next-Level-Access Counter register + 0x1E0 + 0x20 + + + L1_DBUS1_NXTLVL_RD_CNT + The register records the number of times that L1-DCache accesses L2-Cache due to bus1 accessing L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS1_ACS_NXTLVL_WR_CNT + L1-DCache bus1 WB-Access Counter register + 0x1E4 + 0x20 + + + L1_DBUS1_NXTLVL_WR_CNT + The register records the number of write back when bus1 accesses L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS2_ACS_HIT_CNT + L1-DCache bus2 Hit-Access Counter register + 0x1E8 + 0x20 + + + L1_DBUS2_HIT_CNT + The register records the number of hits when bus2 accesses L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS2_ACS_MISS_CNT + L1-DCache bus2 Miss-Access Counter register + 0x1EC + 0x20 + + + L1_DBUS2_MISS_CNT + The register records the number of missing when bus2 accesses L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS2_ACS_CONFLICT_CNT + L1-DCache bus2 Conflict-Access Counter register + 0x1F0 + 0x20 + + + L1_DBUS2_CONFLICT_CNT + The register records the number of access-conflicts when bus2 accesses L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS2_ACS_NXTLVL_RD_CNT + L1-DCache bus2 Next-Level-Access Counter register + 0x1F4 + 0x20 + + + L1_DBUS2_NXTLVL_RD_CNT + The register records the number of times that L1-DCache accesses L2-Cache due to bus2 accessing L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS2_ACS_NXTLVL_WR_CNT + L1-DCache bus2 WB-Access Counter register + 0x1F8 + 0x20 + + + L1_DBUS2_NXTLVL_WR_CNT + The register records the number of write back when bus2 accesses L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS3_ACS_HIT_CNT + L1-DCache bus3 Hit-Access Counter register + 0x1FC + 0x20 + + + L1_DBUS3_HIT_CNT + The register records the number of hits when bus3 accesses L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS3_ACS_MISS_CNT + L1-DCache bus3 Miss-Access Counter register + 0x200 + 0x20 + + + L1_DBUS3_MISS_CNT + The register records the number of missing when bus3 accesses L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS3_ACS_CONFLICT_CNT + L1-DCache bus3 Conflict-Access Counter register + 0x204 + 0x20 + + + L1_DBUS3_CONFLICT_CNT + The register records the number of access-conflicts when bus3 accesses L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS3_ACS_NXTLVL_RD_CNT + L1-DCache bus3 Next-Level-Access Counter register + 0x208 + 0x20 + + + L1_DBUS3_NXTLVL_RD_CNT + The register records the number of times that L1-DCache accesses L2-Cache due to bus3 accessing L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS3_ACS_NXTLVL_WR_CNT + L1-DCache bus3 WB-Access Counter register + 0x20C + 0x20 + + + L1_DBUS3_NXTLVL_WR_CNT + The register records the number of write back when bus0 accesses L1-DCache. + 0 + 32 + read-only + + + + + L1_ICACHE0_ACS_FAIL_ID_ATTR + L1-ICache0 Access Fail ID/attribution information register + 0x210 + 0x20 + + + L1_ICACHE0_FAIL_ID + The register records the ID of fail-access when cache0 accesses L1-ICache. + 0 + 16 + read-only + + + L1_ICACHE0_FAIL_ATTR + The register records the attribution of fail-access when cache0 accesses L1-ICache. + 16 + 16 + read-only + + + + + L1_ICACHE0_ACS_FAIL_ADDR + L1-ICache0 Access Fail Address information register + 0x214 + 0x20 + + + L1_ICACHE0_FAIL_ADDR + The register records the address of fail-access when cache0 accesses L1-ICache. + 0 + 32 + read-only + + + + + L1_ICACHE1_ACS_FAIL_ID_ATTR + L1-ICache0 Access Fail ID/attribution information register + 0x218 + 0x20 + + + L1_ICACHE1_FAIL_ID + The register records the ID of fail-access when cache1 accesses L1-ICache. + 0 + 16 + read-only + + + L1_ICACHE1_FAIL_ATTR + The register records the attribution of fail-access when cache1 accesses L1-ICache. + 16 + 16 + read-only + + + + + L1_ICACHE1_ACS_FAIL_ADDR + L1-ICache0 Access Fail Address information register + 0x21C + 0x20 + + + L1_ICACHE1_FAIL_ADDR + The register records the address of fail-access when cache1 accesses L1-ICache. + 0 + 32 + read-only + + + + + L1_ICACHE2_ACS_FAIL_ID_ATTR + L1-ICache0 Access Fail ID/attribution information register + 0x220 + 0x20 + + + L1_ICACHE2_FAIL_ID + The register records the ID of fail-access when cache2 accesses L1-ICache. + 0 + 16 + read-only + + + L1_ICACHE2_FAIL_ATTR + The register records the attribution of fail-access when cache2 accesses L1-ICache. + 16 + 16 + read-only + + + + + L1_ICACHE2_ACS_FAIL_ADDR + L1-ICache0 Access Fail Address information register + 0x224 + 0x20 + + + L1_ICACHE2_FAIL_ADDR + The register records the address of fail-access when cache2 accesses L1-ICache. + 0 + 32 + read-only + + + + + L1_ICACHE3_ACS_FAIL_ID_ATTR + L1-ICache0 Access Fail ID/attribution information register + 0x228 + 0x20 + + + L1_ICACHE3_FAIL_ID + The register records the ID of fail-access when cache3 accesses L1-ICache. + 0 + 16 + read-only + + + L1_ICACHE3_FAIL_ATTR + The register records the attribution of fail-access when cache3 accesses L1-ICache. + 16 + 16 + read-only + + + + + L1_ICACHE3_ACS_FAIL_ADDR + L1-ICache0 Access Fail Address information register + 0x22C + 0x20 + + + L1_ICACHE3_FAIL_ADDR + The register records the address of fail-access when cache3 accesses L1-ICache. + 0 + 32 + read-only + + + + + L1_DCACHE_ACS_FAIL_ID_ATTR + L1-DCache Access Fail ID/attribution information register + 0x230 + 0x20 + + + L1_DCACHE_FAIL_ID + The register records the ID of fail-access when cache accesses L1-DCache. + 0 + 16 + read-only + + + L1_DCACHE_FAIL_ATTR + The register records the attribution of fail-access when cache accesses L1-DCache. + 16 + 16 + read-only + + + + + L1_DCACHE_ACS_FAIL_ADDR + L1-DCache Access Fail Address information register + 0x234 + 0x20 + + + L1_DCACHE_FAIL_ADDR + The register records the address of fail-access when cache accesses L1-DCache. + 0 + 32 + read-only + + + + + SYNC_L1_CACHE_PRELOAD_INT_ENA + L1-Cache Access Fail Interrupt enable register + 0x238 + 0x20 + + + L1_ICACHE0_PLD_DONE_INT_ENA + The bit is used to enable interrupt of L1-ICache0 preload-operation. If preload operation is done, interrupt occurs. + 0 + 1 + read-write + + + L1_ICACHE1_PLD_DONE_INT_ENA + The bit is used to enable interrupt of L1-ICache1 preload-operation. If preload operation is done, interrupt occurs. + 1 + 1 + read-write + + + L1_ICACHE2_PLD_DONE_INT_ENA + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_PLD_DONE_INT_ENA + Reserved + 3 + 1 + read-only + + + L1_DCACHE_PLD_DONE_INT_ENA + The bit is used to enable interrupt of L1-DCache preload-operation. If preload operation is done, interrupt occurs. + 4 + 1 + read-write + + + SYNC_DONE_INT_ENA + The bit is used to enable interrupt of Cache sync-operation done. + 6 + 1 + read-write + + + L1_ICACHE0_PLD_ERR_INT_ENA + The bit is used to enable interrupt of L1-ICache0 preload-operation error. + 7 + 1 + read-write + + + L1_ICACHE1_PLD_ERR_INT_ENA + The bit is used to enable interrupt of L1-ICache1 preload-operation error. + 8 + 1 + read-write + + + L1_ICACHE2_PLD_ERR_INT_ENA + Reserved + 9 + 1 + read-only + + + L1_ICACHE3_PLD_ERR_INT_ENA + Reserved + 10 + 1 + read-only + + + L1_DCACHE_PLD_ERR_INT_ENA + The bit is used to enable interrupt of L1-DCache preload-operation error. + 11 + 1 + read-write + + + SYNC_ERR_INT_ENA + The bit is used to enable interrupt of Cache sync-operation error. + 13 + 1 + read-write + + + + + SYNC_L1_CACHE_PRELOAD_INT_CLR + Sync Preload operation Interrupt clear register + 0x23C + 0x20 + + + L1_ICACHE0_PLD_DONE_INT_CLR + The bit is used to clear interrupt that occurs only when L1-ICache0 preload-operation is done. + 0 + 1 + write-only + + + L1_ICACHE1_PLD_DONE_INT_CLR + The bit is used to clear interrupt that occurs only when L1-ICache1 preload-operation is done. + 1 + 1 + write-only + + + L1_ICACHE2_PLD_DONE_INT_CLR + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_PLD_DONE_INT_CLR + Reserved + 3 + 1 + read-only + + + L1_DCACHE_PLD_DONE_INT_CLR + The bit is used to clear interrupt that occurs only when L1-DCache preload-operation is done. + 4 + 1 + write-only + + + SYNC_DONE_INT_CLR + The bit is used to clear interrupt that occurs only when Cache sync-operation is done. + 6 + 1 + write-only + + + L1_ICACHE0_PLD_ERR_INT_CLR + The bit is used to clear interrupt of L1-ICache0 preload-operation error. + 7 + 1 + write-only + + + L1_ICACHE1_PLD_ERR_INT_CLR + The bit is used to clear interrupt of L1-ICache1 preload-operation error. + 8 + 1 + write-only + + + L1_ICACHE2_PLD_ERR_INT_CLR + Reserved + 9 + 1 + read-only + + + L1_ICACHE3_PLD_ERR_INT_CLR + Reserved + 10 + 1 + read-only + + + L1_DCACHE_PLD_ERR_INT_CLR + The bit is used to clear interrupt of L1-DCache preload-operation error. + 11 + 1 + write-only + + + SYNC_ERR_INT_CLR + The bit is used to clear interrupt of Cache sync-operation error. + 13 + 1 + write-only + + + + + SYNC_L1_CACHE_PRELOAD_INT_RAW + Sync Preload operation Interrupt raw register + 0x240 + 0x20 + + + L1_ICACHE0_PLD_DONE_INT_RAW + The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation is done. + 0 + 1 + read-write + + + L1_ICACHE1_PLD_DONE_INT_RAW + The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation is done. + 1 + 1 + read-write + + + L1_ICACHE2_PLD_DONE_INT_RAW + Reserved + 2 + 1 + read-write + + + L1_ICACHE3_PLD_DONE_INT_RAW + Reserved + 3 + 1 + read-write + + + L1_DCACHE_PLD_DONE_INT_RAW + The raw bit of the interrupt that occurs only when L1-DCache preload-operation is done. + 4 + 1 + read-write + + + SYNC_DONE_INT_RAW + The raw bit of the interrupt that occurs only when Cache sync-operation is done. + 6 + 1 + read-write + + + L1_ICACHE0_PLD_ERR_INT_RAW + The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation error occurs. + 7 + 1 + read-write + + + L1_ICACHE1_PLD_ERR_INT_RAW + The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation error occurs. + 8 + 1 + read-write + + + L1_ICACHE2_PLD_ERR_INT_RAW + Reserved + 9 + 1 + read-write + + + L1_ICACHE3_PLD_ERR_INT_RAW + Reserved + 10 + 1 + read-write + + + L1_DCACHE_PLD_ERR_INT_RAW + The raw bit of the interrupt that occurs only when L1-DCache preload-operation error occurs. + 11 + 1 + read-write + + + SYNC_ERR_INT_RAW + The raw bit of the interrupt that occurs only when Cache sync-operation error occurs. + 13 + 1 + read-write + + + + + SYNC_L1_CACHE_PRELOAD_INT_ST + L1-Cache Access Fail Interrupt status register + 0x244 + 0x20 + + + L1_ICACHE0_PLD_DONE_INT_ST + The bit indicates the status of the interrupt that occurs only when L1-ICache0 preload-operation is done. + 0 + 1 + read-only + + + L1_ICACHE1_PLD_DONE_INT_ST + The bit indicates the status of the interrupt that occurs only when L1-ICache1 preload-operation is done. + 1 + 1 + read-only + + + L1_ICACHE2_PLD_DONE_INT_ST + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_PLD_DONE_INT_ST + Reserved + 3 + 1 + read-only + + + L1_DCACHE_PLD_DONE_INT_ST + The bit indicates the status of the interrupt that occurs only when L1-DCache preload-operation is done. + 4 + 1 + read-only + + + SYNC_DONE_INT_ST + The bit indicates the status of the interrupt that occurs only when Cache sync-operation is done. + 6 + 1 + read-only + + + L1_ICACHE0_PLD_ERR_INT_ST + The bit indicates the status of the interrupt of L1-ICache0 preload-operation error. + 7 + 1 + read-only + + + L1_ICACHE1_PLD_ERR_INT_ST + The bit indicates the status of the interrupt of L1-ICache1 preload-operation error. + 8 + 1 + read-only + + + L1_ICACHE2_PLD_ERR_INT_ST + Reserved + 9 + 1 + read-only + + + L1_ICACHE3_PLD_ERR_INT_ST + Reserved + 10 + 1 + read-only + + + L1_DCACHE_PLD_ERR_INT_ST + The bit indicates the status of the interrupt of L1-DCache preload-operation error. + 11 + 1 + read-only + + + SYNC_ERR_INT_ST + The bit indicates the status of the interrupt of Cache sync-operation error. + 13 + 1 + read-only + + + + + SYNC_L1_CACHE_PRELOAD_EXCEPTION + Cache Sync/Preload Operation exception register + 0x248 + 0x20 + + + L1_ICACHE0_PLD_ERR_CODE + The value 2 is Only available which means preload size is error in L1-ICache0. + 0 + 2 + read-only + + + L1_ICACHE1_PLD_ERR_CODE + The value 2 is Only available which means preload size is error in L1-ICache1. + 2 + 2 + read-only + + + L1_ICACHE2_PLD_ERR_CODE + Reserved + 4 + 2 + read-only + + + L1_ICACHE3_PLD_ERR_CODE + Reserved + 6 + 2 + read-only + + + L1_DCACHE_PLD_ERR_CODE + The value 2 is Only available which means preload size is error in L1-DCache. + 8 + 2 + read-only + + + SYNC_ERR_CODE + The values 0-2 are available which means sync map, command conflict and size are error in Cache System. + 12 + 2 + read-only + + + + + L1_CACHE_SYNC_RST_CTRL + Cache Sync Reset control register + 0x24C + 0x20 + + + L1_ICACHE0_SYNC_RST + set this bit to reset sync-logic inside L1-ICache0. Recommend that this should only be used to initialize sync-logic when some fatal error of sync-logic occurs. + 0 + 1 + read-write + + + L1_ICACHE1_SYNC_RST + set this bit to reset sync-logic inside L1-ICache1. Recommend that this should only be used to initialize sync-logic when some fatal error of sync-logic occurs. + 1 + 1 + read-write + + + L1_ICACHE2_SYNC_RST + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_SYNC_RST + Reserved + 3 + 1 + read-only + + + L1_DCACHE_SYNC_RST + set this bit to reset sync-logic inside L1-DCache. Recommend that this should only be used to initialize sync-logic when some fatal error of sync-logic occurs. + 4 + 1 + read-write + + + + + L1_CACHE_PRELOAD_RST_CTRL + Cache Preload Reset control register + 0x250 + 0x20 + + + L1_ICACHE0_PLD_RST + set this bit to reset preload-logic inside L1-ICache0. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs. + 0 + 1 + read-write + + + L1_ICACHE1_PLD_RST + set this bit to reset preload-logic inside L1-ICache1. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs. + 1 + 1 + read-write + + + L1_ICACHE2_PLD_RST + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_PLD_RST + Reserved + 3 + 1 + read-only + + + L1_DCACHE_PLD_RST + set this bit to reset preload-logic inside L1-DCache. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs. + 4 + 1 + read-write + + + + + L1_CACHE_AUTOLOAD_BUF_CLR_CTRL + Cache Autoload buffer clear control register + 0x254 + 0x20 + + + L1_ICACHE0_ALD_BUF_CLR + set this bit to clear autoload-buffer inside L1-ICache0. If this bit is active, autoload will not work in L1-ICache0. This bit should not be active when autoload works in L1-ICache0. + 0 + 1 + read-write + + + L1_ICACHE1_ALD_BUF_CLR + set this bit to clear autoload-buffer inside L1-ICache1. If this bit is active, autoload will not work in L1-ICache1. This bit should not be active when autoload works in L1-ICache1. + 1 + 1 + read-write + + + L1_ICACHE2_ALD_BUF_CLR + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_ALD_BUF_CLR + Reserved + 3 + 1 + read-only + + + L1_DCACHE_ALD_BUF_CLR + set this bit to clear autoload-buffer inside L1-DCache. If this bit is active, autoload will not work in L1-DCache. This bit should not be active when autoload works in L1-DCache. + 4 + 1 + read-write + + + + + L1_UNALLOCATE_BUFFER_CLEAR + Unallocate request buffer clear registers + 0x258 + 0x20 + + + L1_ICACHE0_UNALLOC_CLR + The bit is used to clear the unallocate request buffer of l1 icache0 where the unallocate request is responsed but not completed. + 0 + 1 + read-write + + + L1_ICACHE1_UNALLOC_CLR + The bit is used to clear the unallocate request buffer of l1 icache1 where the unallocate request is responsed but not completed. + 1 + 1 + read-write + + + L1_ICACHE2_UNALLOC_CLR + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_UNALLOC_CLR + Reserved + 3 + 1 + read-only + + + L1_DCACHE_UNALLOC_CLR + The bit is used to clear the unallocate request buffer of l1 dcache where the unallocate request is responsed but not completed. + 4 + 1 + read-write + + + + + L1_CACHE_OBJECT_CTRL + Cache Tag and Data memory Object control register + 0x25C + 0x20 + + + L1_ICACHE0_TAG_OBJECT + Set this bit to set L1-ICache0 tag memory as object. This bit should be onehot with the others fields inside this register. + 0 + 1 + read-write + + + L1_ICACHE1_TAG_OBJECT + Set this bit to set L1-ICache1 tag memory as object. This bit should be onehot with the others fields inside this register. + 1 + 1 + read-write + + + L1_ICACHE2_TAG_OBJECT + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_TAG_OBJECT + Reserved + 3 + 1 + read-only + + + L1_DCACHE_TAG_OBJECT + Set this bit to set L1-DCache tag memory as object. This bit should be onehot with the others fields inside this register. + 4 + 1 + read-write + + + L1_ICACHE0_MEM_OBJECT + Set this bit to set L1-ICache0 data memory as object. This bit should be onehot with the others fields inside this register. + 6 + 1 + read-write + + + L1_ICACHE1_MEM_OBJECT + Set this bit to set L1-ICache1 data memory as object. This bit should be onehot with the others fields inside this register. + 7 + 1 + read-write + + + L1_ICACHE2_MEM_OBJECT + Reserved + 8 + 1 + read-only + + + L1_ICACHE3_MEM_OBJECT + Reserved + 9 + 1 + read-only + + + L1_DCACHE_MEM_OBJECT + Set this bit to set L1-DCache data memory as object. This bit should be onehot with the others fields inside this register. + 10 + 1 + read-write + + + + + L1_CACHE_WAY_OBJECT + Cache Tag and Data memory way register + 0x260 + 0x20 + + + L1_CACHE_WAY_OBJECT + Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: way1, 2: way2, 3: way3, ?, 7: way7. + 0 + 3 + read-write + + + + + L1_CACHE_VADDR + Cache Vaddr register + 0x264 + 0x20 + 0x40000000 + + + L1_CACHE_VADDR + Those bits stores the virtual address which will decide where inside the specified tag memory object will be accessed. + 0 + 32 + read-write + + + + + L1_CACHE_DEBUG_BUS + Cache Tag/data memory content register + 0x268 + 0x20 + 0x00000268 + + + L1_CACHE_DEBUG_BUS + This is a constant place where we can write data to or read data from the tag/data memory on the specified cache. + 0 + 32 + read-write + + + + + LEVEL_SPLIT0 + USED TO SPLIT L1 CACHE AND L2 CACHE + 0x26C + 0x20 + 0x0000026C + + + LEVEL_SPLIT0 + Reserved + 0 + 32 + read-only + + + + + L2_CACHE_CTRL + L2 Cache(L2-Cache) control register + 0x270 + 0x20 + 0x00000010 + + + L2_CACHE_SHUT_DMA + The bit is used to disable DMA access L2-Cache, 0: enable, 1: disable + 4 + 1 + read-write + + + L2_CACHE_UNDEF_OP + Reserved + 8 + 8 + read-write + + + + + L2_BYPASS_CACHE_CONF + Bypass Cache configure register + 0x274 + 0x20 + + + BYPASS_L2_CACHE_EN + The bit is used to enable bypass L2-Cache. 0: disable bypass, 1: enable bypass. + 5 + 1 + read-write + + + + + L2_CACHE_CACHESIZE_CONF + L2 Cache CacheSize mode configure register + 0x278 + 0x20 + 0x00000400 + + + L2_CACHE_CACHESIZE_256 + The field is used to configure cachesize of L2-Cache as 256 bytes. This field and all other fields within this register is onehot. + 0 + 1 + read-only + + + L2_CACHE_CACHESIZE_512 + The field is used to configure cachesize of L2-Cache as 512 bytes. This field and all other fields within this register is onehot. + 1 + 1 + read-only + + + L2_CACHE_CACHESIZE_1K + The field is used to configure cachesize of L2-Cache as 1k bytes. This field and all other fields within this register is onehot. + 2 + 1 + read-only + + + L2_CACHE_CACHESIZE_2K + The field is used to configure cachesize of L2-Cache as 2k bytes. This field and all other fields within this register is onehot. + 3 + 1 + read-only + + + L2_CACHE_CACHESIZE_4K + The field is used to configure cachesize of L2-Cache as 4k bytes. This field and all other fields within this register is onehot. + 4 + 1 + read-only + + + L2_CACHE_CACHESIZE_8K + The field is used to configure cachesize of L2-Cache as 8k bytes. This field and all other fields within this register is onehot. + 5 + 1 + read-only + + + L2_CACHE_CACHESIZE_16K + The field is used to configure cachesize of L2-Cache as 16k bytes. This field and all other fields within this register is onehot. + 6 + 1 + read-only + + + L2_CACHE_CACHESIZE_32K + The field is used to configure cachesize of L2-Cache as 32k bytes. This field and all other fields within this register is onehot. + 7 + 1 + read-only + + + L2_CACHE_CACHESIZE_64K + The field is used to configure cachesize of L2-Cache as 64k bytes. This field and all other fields within this register is onehot. + 8 + 1 + read-only + + + L2_CACHE_CACHESIZE_128K + The field is used to configure cachesize of L2-Cache as 128k bytes. This field and all other fields within this register is onehot. + 9 + 1 + read-write + + + L2_CACHE_CACHESIZE_256K + The field is used to configure cachesize of L2-Cache as 256k bytes. This field and all other fields within this register is onehot. + 10 + 1 + read-write + + + L2_CACHE_CACHESIZE_512K + The field is used to configure cachesize of L2-Cache as 512k bytes. This field and all other fields within this register is onehot. + 11 + 1 + read-write + + + L2_CACHE_CACHESIZE_1024K + The field is used to configure cachesize of L2-Cache as 1024k bytes. This field and all other fields within this register is onehot. + 12 + 1 + read-only + + + + + L2_CACHE_BLOCKSIZE_CONF + L2 Cache BlockSize mode configure register + 0x27C + 0x20 + 0x00000008 + + + L2_CACHE_BLOCKSIZE_8 + The field is used to configureblocksize of L2-Cache as 8 bytes. This field and all other fields within this register is onehot. + 0 + 1 + read-only + + + L2_CACHE_BLOCKSIZE_16 + The field is used to configureblocksize of L2-Cache as 16 bytes. This field and all other fields within this register is onehot. + 1 + 1 + read-only + + + L2_CACHE_BLOCKSIZE_32 + The field is used to configureblocksize of L2-Cache as 32 bytes. This field and all other fields within this register is onehot. + 2 + 1 + read-only + + + L2_CACHE_BLOCKSIZE_64 + The field is used to configureblocksize of L2-Cache as 64 bytes. This field and all other fields within this register is onehot. + 3 + 1 + read-write + + + L2_CACHE_BLOCKSIZE_128 + The field is used to configureblocksize of L2-Cache as 128 bytes. This field and all other fields within this register is onehot. + 4 + 1 + read-write + + + L2_CACHE_BLOCKSIZE_256 + The field is used to configureblocksize of L2-Cache as 256 bytes. This field and all other fields within this register is onehot. + 5 + 1 + read-only + + + + + L2_CACHE_WRAP_AROUND_CTRL + Cache wrap around control register + 0x280 + 0x20 + + + L2_CACHE_WRAP + Set this bit as 1 to enable L2-Cache wrap around mode. + 5 + 1 + read-write + + + + + L2_CACHE_TAG_MEM_POWER_CTRL + Cache tag memory power control register + 0x284 + 0x20 + 0x00500000 + + + L2_CACHE_TAG_MEM_FORCE_ON + The bit is used to close clock gating of L2-Cache tag memory. 1: close gating, 0: open clock gating. + 20 + 1 + read-write + + + L2_CACHE_TAG_MEM_FORCE_PD + The bit is used to power L2-Cache tag memory down. 0: follow rtc_lslp, 1: power down + 21 + 1 + read-write + + + L2_CACHE_TAG_MEM_FORCE_PU + The bit is used to power L2-Cache tag memory up. 0: follow rtc_lslp, 1: power up + 22 + 1 + read-write + + + + + L2_CACHE_DATA_MEM_POWER_CTRL + Cache data memory power control register + 0x288 + 0x20 + 0x00500000 + + + L2_CACHE_DATA_MEM_FORCE_ON + The bit is used to close clock gating of L2-Cache data memory. 1: close gating, 0: open clock gating. + 20 + 1 + read-write + + + L2_CACHE_DATA_MEM_FORCE_PD + The bit is used to power L2-Cache data memory down. 0: follow rtc_lslp, 1: power down + 21 + 1 + read-write + + + L2_CACHE_DATA_MEM_FORCE_PU + The bit is used to power L2-Cache data memory up. 0: follow rtc_lslp, 1: power up + 22 + 1 + read-write + + + + + L2_CACHE_FREEZE_CTRL + Cache Freeze control register + 0x28C + 0x20 + + + L2_CACHE_FREEZE_EN + The bit is used to enable freeze operation on L2-Cache. It can be cleared by software. + 20 + 1 + read-write + + + L2_CACHE_FREEZE_MODE + The bit is used to configure mode of freeze operation L2-Cache. 0: a miss-access will not stuck. 1: a miss-access will stuck. + 21 + 1 + read-write + + + L2_CACHE_FREEZE_DONE + The bit is used to indicate whether freeze operation on L2-Cache is finished or not. 0: not finished. 1: finished. + 22 + 1 + read-only + + + + + L2_CACHE_DATA_MEM_ACS_CONF + Cache data memory access configure register + 0x290 + 0x20 + 0x00300000 + + + L2_CACHE_DATA_MEM_RD_EN + The bit is used to enable config-bus read L2-Cache data memoryory. 0: disable, 1: enable. + 20 + 1 + read-write + + + L2_CACHE_DATA_MEM_WR_EN + The bit is used to enable config-bus write L2-Cache data memoryory. 0: disable, 1: enable. + 21 + 1 + read-write + + + + + L2_CACHE_TAG_MEM_ACS_CONF + Cache tag memory access configure register + 0x294 + 0x20 + 0x00300000 + + + L2_CACHE_TAG_MEM_RD_EN + The bit is used to enable config-bus read L2-Cache tag memoryory. 0: disable, 1: enable. + 20 + 1 + read-write + + + L2_CACHE_TAG_MEM_WR_EN + The bit is used to enable config-bus write L2-Cache tag memoryory. 0: disable, 1: enable. + 21 + 1 + read-write + + + + + L2_CACHE_PRELOCK_CONF + L2 Cache prelock configure register + 0x298 + 0x20 + + + L2_CACHE_PRELOCK_SCT0_EN + The bit is used to enable the first section of prelock function on L2-Cache. + 0 + 1 + read-write + + + L2_CACHE_PRELOCK_SCT1_EN + The bit is used to enable the second section of prelock function on L2-Cache. + 1 + 1 + read-write + + + L2_CACHE_PRELOCK_RGID + The bit is used to set the gid of l2 cache prelock. + 2 + 4 + read-write + + + + + L2_CACHE_PRELOCK_SCT0_ADDR + L2 Cache prelock section0 address configure register + 0x29C + 0x20 + + + L2_CACHE_PRELOCK_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_SIZE_REG + 0 + 32 + read-write + + + + + L2_CACHE_PRELOCK_SCT1_ADDR + L2 Cache prelock section1 address configure register + 0x2A0 + 0x20 + + + L2_CACHE_PRELOCK_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_SIZE_REG + 0 + 32 + read-write + + + + + L2_CACHE_PRELOCK_SCT_SIZE + L2 Cache prelock section size configure register + 0x2A4 + 0x20 + 0xFFFFFFFF + + + L2_CACHE_PRELOCK_SCT0_SIZE + Those bits are used to configure the size of the first section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_ADDR_REG + 0 + 16 + read-write + + + L2_CACHE_PRELOCK_SCT1_SIZE + Those bits are used to configure the size of the second section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_ADDR_REG + 16 + 16 + read-write + + + + + L2_CACHE_PRELOAD_CTRL + L2 Cache preload-operation control register + 0x2A8 + 0x20 + 0x00000002 + + + L2_CACHE_PRELOAD_ENA + The bit is used to enable preload operation on L2-Cache. It will be cleared by hardware automatically after preload operation is done. + 0 + 1 + read-write + + + L2_CACHE_PRELOAD_DONE + The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished. + 1 + 1 + read-only + + + L2_CACHE_PRELOAD_ORDER + The bit is used to configure the direction of preload operation. 0: ascending, 1: descending. + 2 + 1 + read-write + + + L2_CACHE_PRELOAD_RGID + The bit is used to set the gid of l2 cache preload. + 3 + 4 + read-write + + + + + L2_CACHE_PRELOAD_ADDR + L2 Cache preload address configure register + 0x2AC + 0x20 + + + L2_CACHE_PRELOAD_ADDR + Those bits are used to configure the start virtual address of preload on L2-Cache, which should be used together with L2_CACHE_PRELOAD_SIZE_REG + 0 + 32 + read-write + + + + + L2_CACHE_PRELOAD_SIZE + L2 Cache preload size configure register + 0x2B0 + 0x20 + + + L2_CACHE_PRELOAD_SIZE + Those bits are used to configure the size of the first section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOAD_ADDR_REG + 0 + 16 + read-write + + + + + L2_CACHE_AUTOLOAD_CTRL + L2 Cache autoload-operation control register + 0x2B4 + 0x20 + 0x00000002 + + + L2_CACHE_AUTOLOAD_ENA + The bit is used to enable and disable autoload operation on L2-Cache. 1: enable, 0: disable. + 0 + 1 + read-write + + + L2_CACHE_AUTOLOAD_DONE + The bit is used to indicate whether autoload operation on L2-Cache is finished or not. 0: not finished. 1: finished. + 1 + 1 + read-only + + + L2_CACHE_AUTOLOAD_ORDER + The bit is used to configure the direction of autoload operation on L2-Cache. 0: ascending. 1: descending. + 2 + 1 + read-write + + + L2_CACHE_AUTOLOAD_TRIGGER_MODE + The field is used to configure trigger mode of autoload operation on L2-Cache. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + 3 + 2 + read-write + + + L2_CACHE_AUTOLOAD_SCT0_ENA + The bit is used to enable the first section for autoload operation on L2-Cache. + 8 + 1 + read-write + + + L2_CACHE_AUTOLOAD_SCT1_ENA + The bit is used to enable the second section for autoload operation on L2-Cache. + 9 + 1 + read-write + + + L2_CACHE_AUTOLOAD_SCT2_ENA + The bit is used to enable the third section for autoload operation on L2-Cache. + 10 + 1 + read-write + + + L2_CACHE_AUTOLOAD_SCT3_ENA + The bit is used to enable the fourth section for autoload operation on L2-Cache. + 11 + 1 + read-write + + + L2_CACHE_AUTOLOAD_RGID + The bit is used to set the gid of l2 cache autoload. + 12 + 4 + read-write + + + + + L2_CACHE_AUTOLOAD_SCT0_ADDR + L2 Cache autoload section 0 address configure register + 0x2B8 + 0x20 + + + L2_CACHE_AUTOLOAD_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT0_SIZE and L2_CACHE_AUTOLOAD_SCT0_ENA. + 0 + 32 + read-write + + + + + L2_CACHE_AUTOLOAD_SCT0_SIZE + L2 Cache autoload section 0 size configure register + 0x2BC + 0x20 + + + L2_CACHE_AUTOLOAD_SCT0_SIZE + Those bits are used to configure the size of the first section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT0_ADDR and L2_CACHE_AUTOLOAD_SCT0_ENA. + 0 + 28 + read-write + + + + + L2_CACHE_AUTOLOAD_SCT1_ADDR + L2 Cache autoload section 1 address configure register + 0x2C0 + 0x20 + + + L2_CACHE_AUTOLOAD_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT1_SIZE and L2_CACHE_AUTOLOAD_SCT1_ENA. + 0 + 32 + read-write + + + + + L2_CACHE_AUTOLOAD_SCT1_SIZE + L2 Cache autoload section 1 size configure register + 0x2C4 + 0x20 + + + L2_CACHE_AUTOLOAD_SCT1_SIZE + Those bits are used to configure the size of the second section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT1_ADDR and L2_CACHE_AUTOLOAD_SCT1_ENA. + 0 + 28 + read-write + + + + + L2_CACHE_AUTOLOAD_SCT2_ADDR + L2 Cache autoload section 2 address configure register + 0x2C8 + 0x20 + + + L2_CACHE_AUTOLOAD_SCT2_ADDR + Those bits are used to configure the start virtual address of the third section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT2_SIZE and L2_CACHE_AUTOLOAD_SCT2_ENA. + 0 + 32 + read-write + + + + + L2_CACHE_AUTOLOAD_SCT2_SIZE + L2 Cache autoload section 2 size configure register + 0x2CC + 0x20 + + + L2_CACHE_AUTOLOAD_SCT2_SIZE + Those bits are used to configure the size of the third section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT2_ADDR and L2_CACHE_AUTOLOAD_SCT2_ENA. + 0 + 28 + read-write + + + + + L2_CACHE_AUTOLOAD_SCT3_ADDR + L2 Cache autoload section 3 address configure register + 0x2D0 + 0x20 + + + L2_CACHE_AUTOLOAD_SCT3_ADDR + Those bits are used to configure the start virtual address of the fourth section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT3_SIZE and L2_CACHE_AUTOLOAD_SCT3_ENA. + 0 + 32 + read-write + + + + + L2_CACHE_AUTOLOAD_SCT3_SIZE + L2 Cache autoload section 3 size configure register + 0x2D4 + 0x20 + + + L2_CACHE_AUTOLOAD_SCT3_SIZE + Those bits are used to configure the size of the fourth section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT3_ADDR and L2_CACHE_AUTOLOAD_SCT3_ENA. + 0 + 28 + read-write + + + + + L2_CACHE_ACS_CNT_INT_ENA + Cache Access Counter Interrupt enable register + 0x2D8 + 0x20 + + + L2_IBUS0_OVF_INT_ENA + The bit is used to enable interrupt of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-Cache. + 8 + 1 + read-write + + + L2_IBUS1_OVF_INT_ENA + The bit is used to enable interrupt of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-Cache. + 9 + 1 + read-write + + + L2_IBUS2_OVF_INT_ENA + Reserved + 10 + 1 + read-only + + + L2_IBUS3_OVF_INT_ENA + Reserved + 11 + 1 + read-only + + + L2_DBUS0_OVF_INT_ENA + The bit is used to enable interrupt of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-Cache. + 12 + 1 + read-write + + + L2_DBUS1_OVF_INT_ENA + The bit is used to enable interrupt of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-Cache. + 13 + 1 + read-write + + + L2_DBUS2_OVF_INT_ENA + Reserved + 14 + 1 + read-only + + + L2_DBUS3_OVF_INT_ENA + Reserved + 15 + 1 + read-only + + + + + L2_CACHE_ACS_CNT_INT_CLR + Cache Access Counter Interrupt clear register + 0x2DC + 0x20 + + + L2_IBUS0_OVF_INT_CLR + The bit is used to clear counters overflow interrupt and counters in L2-Cache due to bus0 accesses L2-Cache. + 8 + 1 + write-only + + + L2_IBUS1_OVF_INT_CLR + The bit is used to clear counters overflow interrupt and counters in L2-Cache due to bus1 accesses L2-Cache. + 9 + 1 + write-only + + + L2_IBUS2_OVF_INT_CLR + Reserved + 10 + 1 + read-only + + + L2_IBUS3_OVF_INT_CLR + Reserved + 11 + 1 + read-only + + + L2_DBUS0_OVF_INT_CLR + The bit is used to clear counters overflow interrupt and counters in L2-Cache due to bus0 accesses L2-Cache. + 12 + 1 + write-only + + + L2_DBUS1_OVF_INT_CLR + The bit is used to clear counters overflow interrupt and counters in L2-Cache due to bus1 accesses L2-Cache. + 13 + 1 + write-only + + + L2_DBUS2_OVF_INT_CLR + Reserved + 14 + 1 + read-only + + + L2_DBUS3_OVF_INT_CLR + Reserved + 15 + 1 + read-only + + + + + L2_CACHE_ACS_CNT_INT_RAW + Cache Access Counter Interrupt raw register + 0x2E0 + 0x20 + + + L2_IBUS0_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-ICache0. + 8 + 1 + read-write + + + L2_IBUS1_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-ICache1. + 9 + 1 + read-write + + + L2_IBUS2_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus2 accesses L2-ICache2. + 10 + 1 + read-write + + + L2_IBUS3_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus3 accesses L2-ICache3. + 11 + 1 + read-write + + + L2_DBUS0_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-DCache. + 12 + 1 + read-write + + + L2_DBUS1_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-DCache. + 13 + 1 + read-write + + + L2_DBUS2_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus2 accesses L2-DCache. + 14 + 1 + read-write + + + L2_DBUS3_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus3 accesses L2-DCache. + 15 + 1 + read-write + + + + + L2_CACHE_ACS_CNT_INT_ST + Cache Access Counter Interrupt status register + 0x2E4 + 0x20 + + + L2_IBUS0_OVF_INT_ST + The bit indicates the interrupt status of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-Cache. + 8 + 1 + read-only + + + L2_IBUS1_OVF_INT_ST + The bit indicates the interrupt status of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-Cache. + 9 + 1 + read-only + + + L2_IBUS2_OVF_INT_ST + Reserved + 10 + 1 + read-only + + + L2_IBUS3_OVF_INT_ST + Reserved + 11 + 1 + read-only + + + L2_DBUS0_OVF_INT_ST + The bit indicates the interrupt status of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-Cache. + 12 + 1 + read-only + + + L2_DBUS1_OVF_INT_ST + The bit indicates the interrupt status of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-Cache. + 13 + 1 + read-only + + + L2_DBUS2_OVF_INT_ST + Reserved + 14 + 1 + read-only + + + L2_DBUS3_OVF_INT_ST + Reserved + 15 + 1 + read-only + + + + + L2_CACHE_ACS_FAIL_CTRL + Cache Access Fail Configuration register + 0x2E8 + 0x20 + + + L2_CACHE_ACS_FAIL_CHECK_MODE + The bit is used to configure l2 cache access fail check mode. 0: the access fail is not propagated to the request, 1: the access fail is propagated to the request + 0 + 1 + read-write + + + + + L2_CACHE_ACS_FAIL_INT_ENA + Cache Access Fail Interrupt enable register + 0x2EC + 0x20 + + + L2_CACHE_FAIL_INT_ENA + The bit is used to enable interrupt of access fail that occurs in L2-Cache due to l1 cache accesses L2-Cache. + 5 + 1 + read-write + + + + + L2_CACHE_ACS_FAIL_INT_CLR + L1-Cache Access Fail Interrupt clear register + 0x2F0 + 0x20 + + + L2_CACHE_FAIL_INT_CLR + The bit is used to clear interrupt of access fail that occurs in L2-Cache due to l1 cache accesses L2-Cache. + 5 + 1 + write-only + + + + + L2_CACHE_ACS_FAIL_INT_RAW + Cache Access Fail Interrupt raw register + 0x2F4 + 0x20 + + + L2_CACHE_FAIL_INT_RAW + The raw bit of the interrupt of access fail that occurs in L2-Cache. + 5 + 1 + read-write + + + + + L2_CACHE_ACS_FAIL_INT_ST + Cache Access Fail Interrupt status register + 0x2F8 + 0x20 + + + L2_CACHE_FAIL_INT_ST + The bit indicates the interrupt status of access fail that occurs in L2-Cache due to l1 cache accesses L2-Cache. + 5 + 1 + read-only + + + + + L2_CACHE_ACS_CNT_CTRL + Cache Access Counter enable and clear register + 0x2FC + 0x20 + + + L2_IBUS0_CNT_ENA + The bit is used to enable ibus0 counter in L2-Cache. + 8 + 1 + read-write + + + L2_IBUS1_CNT_ENA + The bit is used to enable ibus1 counter in L2-Cache. + 9 + 1 + read-write + + + L2_IBUS2_CNT_ENA + Reserved + 10 + 1 + read-only + + + L2_IBUS3_CNT_ENA + Reserved + 11 + 1 + read-only + + + L2_DBUS0_CNT_ENA + The bit is used to enable dbus0 counter in L2-Cache. + 12 + 1 + read-write + + + L2_DBUS1_CNT_ENA + The bit is used to enable dbus1 counter in L2-Cache. + 13 + 1 + read-write + + + L2_DBUS2_CNT_ENA + Reserved + 14 + 1 + read-only + + + L2_DBUS3_CNT_ENA + Reserved + 15 + 1 + read-only + + + L2_IBUS0_CNT_CLR + The bit is used to clear ibus0 counter in L2-Cache. + 24 + 1 + write-only + + + L2_IBUS1_CNT_CLR + The bit is used to clear ibus1 counter in L2-Cache. + 25 + 1 + write-only + + + L2_IBUS2_CNT_CLR + Reserved + 26 + 1 + read-only + + + L2_IBUS3_CNT_CLR + Reserved + 27 + 1 + read-only + + + L2_DBUS0_CNT_CLR + The bit is used to clear dbus0 counter in L2-Cache. + 28 + 1 + write-only + + + L2_DBUS1_CNT_CLR + The bit is used to clear dbus1 counter in L2-Cache. + 29 + 1 + write-only + + + L2_DBUS2_CNT_CLR + Reserved + 30 + 1 + read-only + + + L2_DBUS3_CNT_CLR + Reserved + 31 + 1 + read-only + + + + + L2_IBUS0_ACS_HIT_CNT + L2-Cache bus0 Hit-Access Counter register + 0x300 + 0x20 + + + L2_IBUS0_HIT_CNT + The register records the number of hits when L1-ICache0 accesses L2-Cache due to bus0 accessing L1-ICache0. + 0 + 32 + read-only + + + + + L2_IBUS0_ACS_MISS_CNT + L2-Cache bus0 Miss-Access Counter register + 0x304 + 0x20 + + + L2_IBUS0_MISS_CNT + The register records the number of missing when L1-ICache0 accesses L2-Cache due to bus0 accessing L1-ICache0. + 0 + 32 + read-only + + + + + L2_IBUS0_ACS_CONFLICT_CNT + L2-Cache bus0 Conflict-Access Counter register + 0x308 + 0x20 + + + L2_IBUS0_CONFLICT_CNT + The register records the number of access-conflicts when L1-ICache0 accesses L2-Cache due to bus0 accessing L1-ICache0. + 0 + 32 + read-only + + + + + L2_IBUS0_ACS_NXTLVL_RD_CNT + L2-Cache bus0 Next-Level-Access Counter register + 0x30C + 0x20 + + + L2_IBUS0_NXTLVL_RD_CNT + The register records the number of times that L2-Cache accesses external memory due to L1-ICache0 accessing L2-Cache due to bus0 accessing L1-ICache0. + 0 + 32 + read-only + + + + + L2_IBUS1_ACS_HIT_CNT + L2-Cache bus1 Hit-Access Counter register + 0x310 + 0x20 + + + L2_IBUS1_HIT_CNT + The register records the number of hits when L1-ICache1 accesses L2-Cache due to bus1 accessing L1-ICache1. + 0 + 32 + read-only + + + + + L2_IBUS1_ACS_MISS_CNT + L2-Cache bus1 Miss-Access Counter register + 0x314 + 0x20 + + + L2_IBUS1_MISS_CNT + The register records the number of missing when L1-ICache1 accesses L2-Cache due to bus1 accessing L1-ICache1. + 0 + 32 + read-only + + + + + L2_IBUS1_ACS_CONFLICT_CNT + L2-Cache bus1 Conflict-Access Counter register + 0x318 + 0x20 + + + L2_IBUS1_CONFLICT_CNT + The register records the number of access-conflicts when L1-ICache1 accesses L2-Cache due to bus1 accessing L1-ICache1. + 0 + 32 + read-only + + + + + L2_IBUS1_ACS_NXTLVL_RD_CNT + L2-Cache bus1 Next-Level-Access Counter register + 0x31C + 0x20 + + + L2_IBUS1_NXTLVL_RD_CNT + The register records the number of times that L2-Cache accesses external memory due to L1-ICache1 accessing L2-Cache due to bus1 accessing L1-ICache1. + 0 + 32 + read-only + + + + + L2_IBUS2_ACS_HIT_CNT + L2-Cache bus2 Hit-Access Counter register + 0x320 + 0x20 + + + L2_IBUS2_HIT_CNT + The register records the number of hits when L1-ICache2 accesses L2-Cache due to bus2 accessing L1-ICache2. + 0 + 32 + read-only + + + + + L2_IBUS2_ACS_MISS_CNT + L2-Cache bus2 Miss-Access Counter register + 0x324 + 0x20 + + + L2_IBUS2_MISS_CNT + The register records the number of missing when L1-ICache2 accesses L2-Cache due to bus2 accessing L1-ICache2. + 0 + 32 + read-only + + + + + L2_IBUS2_ACS_CONFLICT_CNT + L2-Cache bus2 Conflict-Access Counter register + 0x328 + 0x20 + + + L2_IBUS2_CONFLICT_CNT + The register records the number of access-conflicts when L1-ICache2 accesses L2-Cache due to bus2 accessing L1-ICache2. + 0 + 32 + read-only + + + + + L2_IBUS2_ACS_NXTLVL_RD_CNT + L2-Cache bus2 Next-Level-Access Counter register + 0x32C + 0x20 + + + L2_IBUS2_NXTLVL_RD_CNT + The register records the number of times that L2-Cache accesses external memory due to L1-ICache2 accessing L2-Cache due to bus2 accessing L1-ICache2. + 0 + 32 + read-only + + + + + L2_IBUS3_ACS_HIT_CNT + L2-Cache bus3 Hit-Access Counter register + 0x330 + 0x20 + + + L2_IBUS3_HIT_CNT + The register records the number of hits when L1-ICache3 accesses L2-Cache due to bus3 accessing L1-ICache3. + 0 + 32 + read-only + + + + + L2_IBUS3_ACS_MISS_CNT + L2-Cache bus3 Miss-Access Counter register + 0x334 + 0x20 + + + L2_IBUS3_MISS_CNT + The register records the number of missing when L1-ICache3 accesses L2-Cache due to bus3 accessing L1-ICache3. + 0 + 32 + read-only + + + + + L2_IBUS3_ACS_CONFLICT_CNT + L2-Cache bus3 Conflict-Access Counter register + 0x338 + 0x20 + + + L2_IBUS3_CONFLICT_CNT + The register records the number of access-conflicts when L1-ICache3 accesses L2-Cache due to bus3 accessing L1-ICache3. + 0 + 32 + read-only + + + + + L2_IBUS3_ACS_NXTLVL_RD_CNT + L2-Cache bus3 Next-Level-Access Counter register + 0x33C + 0x20 + + + L2_IBUS3_NXTLVL_RD_CNT + The register records the number of times that L2-Cache accesses external memory due to L1-ICache3 accessing L2-Cache due to bus3 accessing L1-ICache3. + 0 + 32 + read-only + + + + + L2_DBUS0_ACS_HIT_CNT + L2-Cache bus0 Hit-Access Counter register + 0x340 + 0x20 + + + L2_DBUS0_HIT_CNT + The register records the number of hits when L1-DCache accesses L2-Cache due to bus0 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS0_ACS_MISS_CNT + L2-Cache bus0 Miss-Access Counter register + 0x344 + 0x20 + + + L2_DBUS0_MISS_CNT + The register records the number of missing when L1-DCache accesses L2-Cache due to bus0 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS0_ACS_CONFLICT_CNT + L2-Cache bus0 Conflict-Access Counter register + 0x348 + 0x20 + + + L2_DBUS0_CONFLICT_CNT + The register records the number of access-conflicts when L1-DCache accesses L2-Cache due to bus0 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS0_ACS_NXTLVL_RD_CNT + L2-Cache bus0 Next-Level-Access Counter register + 0x34C + 0x20 + + + L2_DBUS0_NXTLVL_RD_CNT + The register records the number of times that L2-Cache accesses external memory due to L1-DCache accessing L2-Cache due to bus0 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS0_ACS_NXTLVL_WR_CNT + L2-Cache bus0 WB-Access Counter register + 0x350 + 0x20 + + + L2_DBUS0_NXTLVL_WR_CNT + The register records the number of write back when L1-DCache accesses L2-Cache due to bus0 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS1_ACS_HIT_CNT + L2-Cache bus1 Hit-Access Counter register + 0x354 + 0x20 + + + L2_DBUS1_HIT_CNT + The register records the number of hits when L1-DCache accesses L2-Cache due to bus1 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS1_ACS_MISS_CNT + L2-Cache bus1 Miss-Access Counter register + 0x358 + 0x20 + + + L2_DBUS1_MISS_CNT + The register records the number of missing when L1-DCache accesses L2-Cache due to bus1 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS1_ACS_CONFLICT_CNT + L2-Cache bus1 Conflict-Access Counter register + 0x35C + 0x20 + + + L2_DBUS1_CONFLICT_CNT + The register records the number of access-conflicts when L1-DCache accesses L2-Cache due to bus1 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS1_ACS_NXTLVL_RD_CNT + L2-Cache bus1 Next-Level-Access Counter register + 0x360 + 0x20 + + + L2_DBUS1_NXTLVL_RD_CNT + The register records the number of times that L2-Cache accesses external memory due to L1-DCache accessing L2-Cache due to bus1 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS1_ACS_NXTLVL_WR_CNT + L2-Cache bus1 WB-Access Counter register + 0x364 + 0x20 + + + L2_DBUS1_NXTLVL_WR_CNT + The register records the number of write back when L1-DCache accesses L2-Cache due to bus1 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS2_ACS_HIT_CNT + L2-Cache bus2 Hit-Access Counter register + 0x368 + 0x20 + + + L2_DBUS2_HIT_CNT + The register records the number of hits when L1-DCache accesses L2-Cache due to bus2 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS2_ACS_MISS_CNT + L2-Cache bus2 Miss-Access Counter register + 0x36C + 0x20 + + + L2_DBUS2_MISS_CNT + The register records the number of missing when L1-DCache accesses L2-Cache due to bus2 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS2_ACS_CONFLICT_CNT + L2-Cache bus2 Conflict-Access Counter register + 0x370 + 0x20 + + + L2_DBUS2_CONFLICT_CNT + The register records the number of access-conflicts when L1-DCache accesses L2-Cache due to bus2 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS2_ACS_NXTLVL_RD_CNT + L2-Cache bus2 Next-Level-Access Counter register + 0x374 + 0x20 + + + L2_DBUS2_NXTLVL_RD_CNT + The register records the number of times that L2-Cache accesses external memory due to L1-DCache accessing L2-Cache due to bus2 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS2_ACS_NXTLVL_WR_CNT + L2-Cache bus2 WB-Access Counter register + 0x378 + 0x20 + + + L2_DBUS2_NXTLVL_WR_CNT + The register records the number of write back when L1-DCache accesses L2-Cache due to bus2 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS3_ACS_HIT_CNT + L2-Cache bus3 Hit-Access Counter register + 0x37C + 0x20 + + + L2_DBUS3_HIT_CNT + The register records the number of hits when L1-DCache accesses L2-Cache due to bus3 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS3_ACS_MISS_CNT + L2-Cache bus3 Miss-Access Counter register + 0x380 + 0x20 + + + L2_DBUS3_MISS_CNT + The register records the number of missing when L1-DCache accesses L2-Cache due to bus3 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS3_ACS_CONFLICT_CNT + L2-Cache bus3 Conflict-Access Counter register + 0x384 + 0x20 + + + L2_DBUS3_CONFLICT_CNT + The register records the number of access-conflicts when L1-DCache accesses L2-Cache due to bus3 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS3_ACS_NXTLVL_RD_CNT + L2-Cache bus3 Next-Level-Access Counter register + 0x388 + 0x20 + + + L2_DBUS3_NXTLVL_RD_CNT + The register records the number of times that L2-Cache accesses external memory due to L1-DCache accessing L2-Cache due to bus3 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS3_ACS_NXTLVL_WR_CNT + L2-Cache bus3 WB-Access Counter register + 0x38C + 0x20 + + + L2_DBUS3_NXTLVL_WR_CNT + The register records the number of write back when L1-DCache accesses L2-Cache due to bus3 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_CACHE_ACS_FAIL_ID_ATTR + L2-Cache Access Fail ID/attribution information register + 0x390 + 0x20 + + + L2_CACHE_FAIL_ID + The register records the ID of fail-access when L1-Cache accesses L2-Cache. + 0 + 16 + read-only + + + L2_CACHE_FAIL_ATTR + The register records the attribution of fail-access when L1-Cache accesses L2-Cache due to cache accessing L1-Cache. + 16 + 16 + read-only + + + + + L2_CACHE_ACS_FAIL_ADDR + L2-Cache Access Fail Address information register + 0x394 + 0x20 + + + L2_CACHE_FAIL_ADDR + The register records the address of fail-access when L1-Cache accesses L2-Cache. + 0 + 32 + read-only + + + + + L2_CACHE_SYNC_PRELOAD_INT_ENA + L1-Cache Access Fail Interrupt enable register + 0x398 + 0x20 + + + L2_CACHE_PLD_DONE_INT_ENA + The bit is used to enable interrupt of L2-Cache preload-operation done. + 5 + 1 + read-write + + + L2_CACHE_PLD_ERR_INT_ENA + The bit is used to enable interrupt of L2-Cache preload-operation error. + 12 + 1 + read-write + + + + + L2_CACHE_SYNC_PRELOAD_INT_CLR + Sync Preload operation Interrupt clear register + 0x39C + 0x20 + + + L2_CACHE_PLD_DONE_INT_CLR + The bit is used to clear interrupt that occurs only when L2-Cache preload-operation is done. + 5 + 1 + write-only + + + L2_CACHE_PLD_ERR_INT_CLR + The bit is used to clear interrupt of L2-Cache preload-operation error. + 12 + 1 + write-only + + + + + L2_CACHE_SYNC_PRELOAD_INT_RAW + Sync Preload operation Interrupt raw register + 0x3A0 + 0x20 + + + L2_CACHE_PLD_DONE_INT_RAW + The raw bit of the interrupt that occurs only when L2-Cache preload-operation is done. + 5 + 1 + read-write + + + L2_CACHE_PLD_ERR_INT_RAW + The raw bit of the interrupt that occurs only when L2-Cache preload-operation error occurs. + 12 + 1 + read-write + + + + + L2_CACHE_SYNC_PRELOAD_INT_ST + L1-Cache Access Fail Interrupt status register + 0x3A4 + 0x20 + + + L2_CACHE_PLD_DONE_INT_ST + The bit indicates the status of the interrupt that occurs only when L2-Cache preload-operation is done. + 5 + 1 + read-only + + + L2_CACHE_PLD_ERR_INT_ST + The bit indicates the status of the interrupt of L2-Cache preload-operation error. + 12 + 1 + read-only + + + + + L2_CACHE_SYNC_PRELOAD_EXCEPTION + Cache Sync/Preload Operation exception register + 0x3A8 + 0x20 + + + L2_CACHE_PLD_ERR_CODE + The value 2 is Only available which means preload size is error in L2-Cache. + 10 + 2 + read-only + + + + + L2_CACHE_SYNC_RST_CTRL + Cache Sync Reset control register + 0x3AC + 0x20 + + + L2_CACHE_SYNC_RST + set this bit to reset sync-logic inside L2-Cache. Recommend that this should only be used to initialize sync-logic when some fatal error of sync-logic occurs. + 5 + 1 + read-write + + + + + L2_CACHE_PRELOAD_RST_CTRL + Cache Preload Reset control register + 0x3B0 + 0x20 + + + L2_CACHE_PLD_RST + set this bit to reset preload-logic inside L2-Cache. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs. + 5 + 1 + read-write + + + + + L2_CACHE_AUTOLOAD_BUF_CLR_CTRL + Cache Autoload buffer clear control register + 0x3B4 + 0x20 + + + L2_CACHE_ALD_BUF_CLR + set this bit to clear autoload-buffer inside L2-Cache. If this bit is active, autoload will not work in L2-Cache. This bit should not be active when autoload works in L2-Cache. + 5 + 1 + read-write + + + + + L2_UNALLOCATE_BUFFER_CLEAR + Unallocate request buffer clear registers + 0x3B8 + 0x20 + + + L2_CACHE_UNALLOC_CLR + The bit is used to clear the unallocate request buffer of l2 icache where the unallocate request is responsed but not completed. + 5 + 1 + read-write + + + + + L2_CACHE_ACCESS_ATTR_CTRL + L2 cache access attribute control register + 0x3BC + 0x20 + 0x0000000F + + + L2_CACHE_ACCESS_FORCE_CC + Set this bit to force the request to l2 cache with cacheable attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of cacheable and non-cacheable. + 0 + 1 + read-write + + + L2_CACHE_ACCESS_FORCE_WB + Set this bit to force the request to l2 cache with write-back attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of write-back and write-through. + 1 + 1 + read-write + + + L2_CACHE_ACCESS_FORCE_WMA + Set this bit to force the request to l2 cache with write-miss-allocate attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of write-miss-allocate and write-miss-no-allocate. + 2 + 1 + read-write + + + L2_CACHE_ACCESS_FORCE_RMA + Set this bit to force the request to l2 cache with read-miss-allocate attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of read-miss-allocate and read-miss-no-allocate. + 3 + 1 + read-write + + + + + L2_CACHE_OBJECT_CTRL + Cache Tag and Data memory Object control register + 0x3C0 + 0x20 + + + L2_CACHE_TAG_OBJECT + Set this bit to set L2-Cache tag memory as object. This bit should be onehot with the others fields inside this register. + 5 + 1 + read-write + + + L2_CACHE_MEM_OBJECT + Set this bit to set L2-Cache data memory as object. This bit should be onehot with the others fields inside this register. + 11 + 1 + read-write + + + + + L2_CACHE_WAY_OBJECT + Cache Tag and Data memory way register + 0x3C4 + 0x20 + + + L2_CACHE_WAY_OBJECT + Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: way1, 2: way2, 3: way3, ?, 7: way7. + 0 + 3 + read-write + + + + + L2_CACHE_VADDR + Cache Vaddr register + 0x3C8 + 0x20 + 0x40000000 + + + L2_CACHE_VADDR + Those bits stores the virtual address which will decide where inside the specified tag memory object will be accessed. + 0 + 32 + read-write + + + + + L2_CACHE_DEBUG_BUS + Cache Tag/data memory content register + 0x3CC + 0x20 + 0x000003CC + + + L2_CACHE_DEBUG_BUS + This is a constant place where we can write data to or read data from the tag/data memory on the specified cache. + 0 + 32 + read-write + + + + + LEVEL_SPLIT1 + USED TO SPLIT L1 CACHE AND L2 CACHE + 0x3D0 + 0x20 + 0x000003D0 + + + LEVEL_SPLIT1 + Reserved + 0 + 32 + read-only + + + + + CLOCK_GATE + Clock gate control register + 0x3D4 + 0x20 + 0x00000001 + + + CLK_EN + The bit is used to enable clock gate when access all registers in this module. + 0 + 1 + read-write + + + + + REDUNDANCY_SIG0 + Cache redundancy signal 0 register + 0x3D8 + 0x20 + + + REDCY_SIG0 + Those bits are prepared for ECO. + 0 + 32 + read-write + + + + + REDUNDANCY_SIG1 + Cache redundancy signal 1 register + 0x3DC + 0x20 + + + REDCY_SIG1 + Those bits are prepared for ECO. + 0 + 32 + read-write + + + + + REDUNDANCY_SIG2 + Cache redundancy signal 2 register + 0x3E0 + 0x20 + + + REDCY_SIG2 + Those bits are prepared for ECO. + 0 + 32 + read-write + + + + + REDUNDANCY_SIG3 + Cache redundancy signal 3 register + 0x3E4 + 0x20 + + + REDCY_SIG3 + Those bits are prepared for ECO. + 0 + 32 + read-write + + + + + REDUNDANCY_SIG4 + Cache redundancy signal 0 register + 0x3E8 + 0x20 + + + REDCY_SIG4 + Those bits are prepared for ECO. + 0 + 4 + read-only + + + + + DATE + Version control register + 0x3FC + 0x20 + 0x02304130 + + + DATE + version control register. Note that this default value stored is the latest date when the hardware logic was updated. + 0 + 28 + read-write + + + + + + + INTERRUPT_CORE0 + Interrupt Controller (Core 0) + CORE0 + 0x500D6000 + + 0x0 + 0x218 + registers + + + + LP_RTC_INT_MAP + NA + 0x0 + 0x20 + + + CORE0_LP_RTC_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_WDT_INT_MAP + NA + 0x4 + 0x20 + + + CORE0_LP_WDT_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_TIMER_REG_0_INT_MAP + NA + 0x8 + 0x20 + + + CORE0_LP_TIMER_REG_0_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_TIMER_REG_1_INT_MAP + NA + 0xC + 0x20 + + + CORE0_LP_TIMER_REG_1_INT_MAP + NA + 0 + 6 + read-write + + + + + MB_HP_INT_MAP + NA + 0x10 + 0x20 + + + CORE0_MB_HP_INT_MAP + NA + 0 + 6 + read-write + + + + + MB_LP_INT_MAP + NA + 0x14 + 0x20 + + + CORE0_MB_LP_INT_MAP + NA + 0 + 6 + read-write + + + + + PMU_REG_0_INT_MAP + NA + 0x18 + 0x20 + + + CORE0_PMU_REG_0_INT_MAP + NA + 0 + 6 + read-write + + + + + PMU_REG_1_INT_MAP + NA + 0x1C + 0x20 + + + CORE0_PMU_REG_1_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_ANAPERI_INT_MAP + NA + 0x20 + 0x20 + + + CORE0_LP_ANAPERI_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_ADC_INT_MAP + NA + 0x24 + 0x20 + + + CORE0_LP_ADC_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_GPIO_INT_MAP + NA + 0x28 + 0x20 + + + CORE0_LP_GPIO_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_I2C_INT_MAP + NA + 0x2C + 0x20 + + + CORE0_LP_I2C_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_I2S_INT_MAP + NA + 0x30 + 0x20 + + + CORE0_LP_I2S_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_SPI_INT_MAP + NA + 0x34 + 0x20 + + + CORE0_LP_SPI_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_TOUCH_INT_MAP + NA + 0x38 + 0x20 + + + CORE0_LP_TOUCH_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_TSENS_INT_MAP + NA + 0x3C + 0x20 + + + CORE0_LP_TSENS_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_UART_INT_MAP + NA + 0x40 + 0x20 + + + CORE0_LP_UART_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_EFUSE_INT_MAP + NA + 0x44 + 0x20 + + + CORE0_LP_EFUSE_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_SW_INT_MAP + NA + 0x48 + 0x20 + + + CORE0_LP_SW_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_SYSREG_INT_MAP + NA + 0x4C + 0x20 + + + CORE0_LP_SYSREG_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_HUK_INT_MAP + NA + 0x50 + 0x20 + + + CORE0_LP_HUK_INT_MAP + NA + 0 + 6 + read-write + + + + + SYS_ICM_INT_MAP + NA + 0x54 + 0x20 + + + CORE0_SYS_ICM_INT_MAP + NA + 0 + 6 + read-write + + + + + USB_DEVICE_INT_MAP + NA + 0x58 + 0x20 + + + CORE0_USB_DEVICE_INT_MAP + NA + 0 + 6 + read-write + + + + + SDIO_HOST_INT_MAP + NA + 0x5C + 0x20 + + + CORE0_SDIO_HOST_INT_MAP + NA + 0 + 6 + read-write + + + + + GDMA_INT_MAP + NA + 0x60 + 0x20 + + + CORE0_GDMA_INT_MAP + NA + 0 + 6 + read-write + + + + + SPI2_INT_MAP + NA + 0x64 + 0x20 + + + CORE0_SPI2_INT_MAP + NA + 0 + 6 + read-write + + + + + SPI3_INT_MAP + NA + 0x68 + 0x20 + + + CORE0_SPI3_INT_MAP + NA + 0 + 6 + read-write + + + + + I2S0_INT_MAP + NA + 0x6C + 0x20 + + + CORE0_I2S0_INT_MAP + NA + 0 + 6 + read-write + + + + + I2S1_INT_MAP + NA + 0x70 + 0x20 + + + CORE0_I2S1_INT_MAP + NA + 0 + 6 + read-write + + + + + I2S2_INT_MAP + NA + 0x74 + 0x20 + + + CORE0_I2S2_INT_MAP + NA + 0 + 6 + read-write + + + + + UHCI0_INT_MAP + NA + 0x78 + 0x20 + + + CORE0_UHCI0_INT_MAP + NA + 0 + 6 + read-write + + + + + UART0_INT_MAP + NA + 0x7C + 0x20 + + + CORE0_UART0_INT_MAP + NA + 0 + 6 + read-write + + + + + UART1_INT_MAP + NA + 0x80 + 0x20 + + + CORE0_UART1_INT_MAP + NA + 0 + 6 + read-write + + + + + UART2_INT_MAP + NA + 0x84 + 0x20 + + + CORE0_UART2_INT_MAP + NA + 0 + 6 + read-write + + + + + UART3_INT_MAP + NA + 0x88 + 0x20 + + + CORE0_UART3_INT_MAP + NA + 0 + 6 + read-write + + + + + UART4_INT_MAP + NA + 0x8C + 0x20 + + + CORE0_UART4_INT_MAP + NA + 0 + 6 + read-write + + + + + LCD_CAM_INT_MAP + NA + 0x90 + 0x20 + + + CORE0_LCD_CAM_INT_MAP + NA + 0 + 6 + read-write + + + + + ADC_INT_MAP + NA + 0x94 + 0x20 + + + CORE0_ADC_INT_MAP + NA + 0 + 6 + read-write + + + + + PWM0_INT_MAP + NA + 0x98 + 0x20 + + + CORE0_PWM0_INT_MAP + NA + 0 + 6 + read-write + + + + + PWM1_INT_MAP + NA + 0x9C + 0x20 + + + CORE0_PWM1_INT_MAP + NA + 0 + 6 + read-write + + + + + CAN0_INT_MAP + NA + 0xA0 + 0x20 + + + CORE0_CAN0_INT_MAP + NA + 0 + 6 + read-write + + + + + CAN1_INT_MAP + NA + 0xA4 + 0x20 + + + CORE0_CAN1_INT_MAP + NA + 0 + 6 + read-write + + + + + CAN2_INT_MAP + NA + 0xA8 + 0x20 + + + CORE0_CAN2_INT_MAP + NA + 0 + 6 + read-write + + + + + RMT_INT_MAP + NA + 0xAC + 0x20 + + + CORE0_RMT_INT_MAP + NA + 0 + 6 + read-write + + + + + I2C0_INT_MAP + NA + 0xB0 + 0x20 + + + CORE0_I2C0_INT_MAP + NA + 0 + 6 + read-write + + + + + I2C1_INT_MAP + NA + 0xB4 + 0x20 + + + CORE0_I2C1_INT_MAP + NA + 0 + 6 + read-write + + + + + TIMERGRP0_T0_INT_MAP + NA + 0xB8 + 0x20 + + + CORE0_TIMERGRP0_T0_INT_MAP + NA + 0 + 6 + read-write + + + + + TIMERGRP0_T1_INT_MAP + NA + 0xBC + 0x20 + + + CORE0_TIMERGRP0_T1_INT_MAP + NA + 0 + 6 + read-write + + + + + TIMERGRP0_WDT_INT_MAP + NA + 0xC0 + 0x20 + + + CORE0_TIMERGRP0_WDT_INT_MAP + NA + 0 + 6 + read-write + + + + + TIMERGRP1_T0_INT_MAP + NA + 0xC4 + 0x20 + + + CORE0_TIMERGRP1_T0_INT_MAP + NA + 0 + 6 + read-write + + + + + TIMERGRP1_T1_INT_MAP + NA + 0xC8 + 0x20 + + + CORE0_TIMERGRP1_T1_INT_MAP + NA + 0 + 6 + read-write + + + + + TIMERGRP1_WDT_INT_MAP + NA + 0xCC + 0x20 + + + CORE0_TIMERGRP1_WDT_INT_MAP + NA + 0 + 6 + read-write + + + + + LEDC_INT_MAP + NA + 0xD0 + 0x20 + + + CORE0_LEDC_INT_MAP + NA + 0 + 6 + read-write + + + + + SYSTIMER_TARGET0_INT_MAP + NA + 0xD4 + 0x20 + + + CORE0_SYSTIMER_TARGET0_INT_MAP + NA + 0 + 6 + read-write + + + + + SYSTIMER_TARGET1_INT_MAP + NA + 0xD8 + 0x20 + + + CORE0_SYSTIMER_TARGET1_INT_MAP + NA + 0 + 6 + read-write + + + + + SYSTIMER_TARGET2_INT_MAP + NA + 0xDC + 0x20 + + + CORE0_SYSTIMER_TARGET2_INT_MAP + NA + 0 + 6 + read-write + + + + + AHB_PDMA_IN_CH0_INT_MAP + NA + 0xE0 + 0x20 + + + CORE0_AHB_PDMA_IN_CH0_INT_MAP + NA + 0 + 6 + read-write + + + + + AHB_PDMA_IN_CH1_INT_MAP + NA + 0xE4 + 0x20 + + + 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AXI_PDMA_OUT_CH1_INT_MAP + NA + 0x108 + 0x20 + + + CORE0_AXI_PDMA_OUT_CH1_INT_MAP + NA + 0 + 6 + read-write + + + + + AXI_PDMA_OUT_CH2_INT_MAP + NA + 0x10C + 0x20 + + + CORE0_AXI_PDMA_OUT_CH2_INT_MAP + NA + 0 + 6 + read-write + + + + + RSA_INT_MAP + NA + 0x110 + 0x20 + + + CORE0_RSA_INT_MAP + NA + 0 + 6 + read-write + + + + + AES_INT_MAP + NA + 0x114 + 0x20 + + + CORE0_AES_INT_MAP + NA + 0 + 6 + read-write + + + + + SHA_INT_MAP + NA + 0x118 + 0x20 + + + CORE0_SHA_INT_MAP + NA + 0 + 6 + read-write + + + + + ECC_INT_MAP + NA + 0x11C + 0x20 + + + CORE0_ECC_INT_MAP + NA + 0 + 6 + read-write + + + + + ECDSA_INT_MAP + NA + 0x120 + 0x20 + + + CORE0_ECDSA_INT_MAP + NA + 0 + 6 + read-write + + + + + KM_INT_MAP + NA + 0x124 + 0x20 + + + CORE0_KM_INT_MAP + NA + 0 + 6 + read-write + + + + + GPIO_INT0_MAP + NA + 0x128 + 0x20 + + + CORE0_GPIO_INT0_MAP + NA + 0 + 6 + read-write + + + + + GPIO_INT1_MAP + NA + 0x12C + 0x20 + + + CORE0_GPIO_INT1_MAP + NA + 0 + 6 + read-write + + + + + GPIO_INT2_MAP + NA + 0x130 + 0x20 + + + CORE0_GPIO_INT2_MAP + NA + 0 + 6 + read-write + + + + + GPIO_INT3_MAP + NA + 0x134 + 0x20 + + + CORE0_GPIO_INT3_MAP + NA + 0 + 6 + read-write + + + + + GPIO_PAD_COMP_INT_MAP + NA + 0x138 + 0x20 + + + CORE0_GPIO_PAD_COMP_INT_MAP + NA + 0 + 6 + read-write + + + + + CPU_INT_FROM_CPU_0_MAP + NA + 0x13C + 0x20 + + + CORE0_CPU_INT_FROM_CPU_0_MAP + NA + 0 + 6 + read-write + + + + + CPU_INT_FROM_CPU_1_MAP + NA + 0x140 + 0x20 + + + CORE0_CPU_INT_FROM_CPU_1_MAP + NA + 0 + 6 + read-write + + + + + CPU_INT_FROM_CPU_2_MAP + NA + 0x144 + 0x20 + + + CORE0_CPU_INT_FROM_CPU_2_MAP + NA + 0 + 6 + read-write + + + + + CPU_INT_FROM_CPU_3_MAP + NA + 0x148 + 0x20 + + + CORE0_CPU_INT_FROM_CPU_3_MAP + NA + 0 + 6 + read-write + + + + + CACHE_INT_MAP + NA + 0x14C + 0x20 + + + CORE0_CACHE_INT_MAP + NA + 0 + 6 + read-write + + + + + FLASH_MSPI_INT_MAP + NA + 0x150 + 0x20 + + + CORE0_FLASH_MSPI_INT_MAP + NA + 0 + 6 + read-write + + + + + CSI_BRIDGE_INT_MAP + NA + 0x154 + 0x20 + + + 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CORE0_JPEG_INT_MAP + NA + 0 + 6 + read-write + + + + + PPA_INT_MAP + NA + 0x180 + 0x20 + + + CORE0_PPA_INT_MAP + NA + 0 + 6 + read-write + + + + + CORE0_TRACE_INT_MAP + NA + 0x184 + 0x20 + + + CORE0_CORE0_TRACE_INT_MAP + NA + 0 + 6 + read-write + + + + + CORE1_TRACE_INT_MAP + NA + 0x188 + 0x20 + + + CORE0_CORE1_TRACE_INT_MAP + NA + 0 + 6 + read-write + + + + + HP_CORE_CTRL_INT_MAP + NA + 0x18C + 0x20 + + + CORE0_HP_CORE_CTRL_INT_MAP + NA + 0 + 6 + read-write + + + + + ISP_INT_MAP + NA + 0x190 + 0x20 + + + CORE0_ISP_INT_MAP + NA + 0 + 6 + read-write + + + + + I3C_MST_INT_MAP + NA + 0x194 + 0x20 + + + CORE0_I3C_MST_INT_MAP + NA + 0 + 6 + read-write + + + + + I3C_SLV_INT_MAP + NA + 0x198 + 0x20 + + + CORE0_I3C_SLV_INT_MAP + NA + 0 + 6 + read-write + + + + + USB_OTG11_INT_MAP + NA + 0x19C + 0x20 + + + CORE0_USB_OTG11_INT_MAP + NA + 0 + 6 + read-write + + + + + DMA2D_IN_CH0_INT_MAP + NA + 0x1A0 + 0x20 + + + CORE0_DMA2D_IN_CH0_INT_MAP + NA + 0 + 6 + read-write + + + + + DMA2D_IN_CH1_INT_MAP + NA + 0x1A4 + 0x20 + + + CORE0_DMA2D_IN_CH1_INT_MAP + NA + 0 + 6 + read-write + + + + + DMA2D_OUT_CH0_INT_MAP + NA + 0x1A8 + 0x20 + + + CORE0_DMA2D_OUT_CH0_INT_MAP + NA + 0 + 6 + read-write + + + + + DMA2D_OUT_CH1_INT_MAP + NA + 0x1AC + 0x20 + + + CORE0_DMA2D_OUT_CH1_INT_MAP + NA + 0 + 6 + read-write + + + + + DMA2D_OUT_CH2_INT_MAP + NA + 0x1B0 + 0x20 + + + CORE0_DMA2D_OUT_CH2_INT_MAP + NA + 0 + 6 + read-write + + + + + PSRAM_MSPI_INT_MAP + NA + 0x1B4 + 0x20 + + + CORE0_PSRAM_MSPI_INT_MAP + NA + 0 + 6 + read-write + + + + + HP_SYSREG_INT_MAP + NA + 0x1B8 + 0x20 + + + CORE0_HP_SYSREG_INT_MAP + NA + 0 + 6 + read-write + + + + + PCNT_INT_MAP + NA + 0x1BC + 0x20 + + + CORE0_PCNT_INT_MAP + NA + 0 + 6 + read-write + + + + + HP_PAU_INT_MAP + NA + 0x1C0 + 0x20 + + + CORE0_HP_PAU_INT_MAP + NA + 0 + 6 + read-write + + + + + HP_PARLIO_RX_INT_MAP + NA + 0x1C4 + 0x20 + + + CORE0_HP_PARLIO_RX_INT_MAP + NA + 0 + 6 + read-write + + + + + HP_PARLIO_TX_INT_MAP + NA + 0x1C8 + 0x20 + + + CORE0_HP_PARLIO_TX_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_OUT_CH0_INT_MAP + NA + 0x1CC + 0x20 + + + CORE0_H264_DMA2D_OUT_CH0_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_OUT_CH1_INT_MAP + NA + 0x1D0 + 0x20 + + + CORE0_H264_DMA2D_OUT_CH1_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_OUT_CH2_INT_MAP + NA + 0x1D4 + 0x20 + + + CORE0_H264_DMA2D_OUT_CH2_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_OUT_CH3_INT_MAP + NA + 0x1D8 + 0x20 + + + CORE0_H264_DMA2D_OUT_CH3_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_OUT_CH4_INT_MAP + NA + 0x1DC + 0x20 + + + CORE0_H264_DMA2D_OUT_CH4_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_IN_CH0_INT_MAP + NA + 0x1E0 + 0x20 + + + CORE0_H264_DMA2D_IN_CH0_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_IN_CH1_INT_MAP + NA + 0x1E4 + 0x20 + + + CORE0_H264_DMA2D_IN_CH1_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_IN_CH2_INT_MAP + NA + 0x1E8 + 0x20 + + + CORE0_H264_DMA2D_IN_CH2_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_IN_CH3_INT_MAP + NA + 0x1EC + 0x20 + + + CORE0_H264_DMA2D_IN_CH3_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_IN_CH4_INT_MAP + NA + 0x1F0 + 0x20 + + + CORE0_H264_DMA2D_IN_CH4_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_IN_CH5_INT_MAP + NA + 0x1F4 + 0x20 + + + CORE0_H264_DMA2D_IN_CH5_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_REG_INT_MAP + NA + 0x1F8 + 0x20 + + + CORE0_H264_REG_INT_MAP + NA + 0 + 6 + read-write + + + + + ASSIST_DEBUG_INT_MAP + NA + 0x1FC + 0x20 + + + CORE0_ASSIST_DEBUG_INT_MAP + NA + 0 + 6 + read-write + + + + + INTR_STATUS_REG_0 + NA + 0x200 + 0x20 + + + CORE0_INTR_STATUS_0 + NA + 0 + 32 + read-only + + + + + INTR_STATUS_REG_1 + NA + 0x204 + 0x20 + + + CORE0_INTR_STATUS_1 + NA + 0 + 32 + read-only + + + + + INTR_STATUS_REG_2 + NA + 0x208 + 0x20 + + + CORE0_INTR_STATUS_2 + NA + 0 + 32 + read-only + + + + + INTR_STATUS_REG_3 + NA + 0x20C + 0x20 + + + CORE0_INTR_STATUS_3 + NA + 0 + 32 + read-only + + + + + CLOCK_GATE + NA + 0x210 + 0x20 + 0x00000001 + + + CORE0_REG_CLK_EN + NA + 0 + 1 + read-write + + + + + INTERRUPT_REG_DATE + NA + 0x3FC + 0x20 + 0x02003020 + + + CORE0_INTERRUPT_REG_DATE + NA + 0 + 28 + read-write + + + + + + + INTERRUPT_CORE1 + Interrupt Controller (Core 1) + CORE1 + 0x500D6800 + + 0x0 + 0x218 + registers + + + + LP_RTC_INT_MAP + NA + 0x0 + 0x20 + + + CORE1_LP_RTC_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_WDT_INT_MAP + NA + 0x4 + 0x20 + + + CORE1_LP_WDT_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_TIMER_REG_0_INT_MAP + NA + 0x8 + 0x20 + + + CORE1_LP_TIMER_REG_0_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_TIMER_REG_1_INT_MAP + NA + 0xC + 0x20 + + + CORE1_LP_TIMER_REG_1_INT_MAP + NA + 0 + 6 + read-write + + + + + MB_HP_INT_MAP + NA + 0x10 + 0x20 + + + CORE1_MB_HP_INT_MAP + NA + 0 + 6 + read-write + + + + + MB_LP_INT_MAP + NA + 0x14 + 0x20 + + + CORE1_MB_LP_INT_MAP + NA + 0 + 6 + read-write + + + + + PMU_REG_0_INT_MAP + NA + 0x18 + 0x20 + + + CORE1_PMU_REG_0_INT_MAP + NA + 0 + 6 + read-write + + + + + PMU_REG_1_INT_MAP + NA + 0x1C + 0x20 + + + CORE1_PMU_REG_1_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_ANAPERI_INT_MAP + NA + 0x20 + 0x20 + + + CORE1_LP_ANAPERI_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_ADC_INT_MAP + NA + 0x24 + 0x20 + + + CORE1_LP_ADC_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_GPIO_INT_MAP + NA + 0x28 + 0x20 + + + CORE1_LP_GPIO_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_I2C_INT_MAP + NA + 0x2C + 0x20 + + + CORE1_LP_I2C_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_I2S_INT_MAP + NA + 0x30 + 0x20 + + + CORE1_LP_I2S_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_SPI_INT_MAP + NA + 0x34 + 0x20 + + + CORE1_LP_SPI_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_TOUCH_INT_MAP + NA + 0x38 + 0x20 + + + CORE1_LP_TOUCH_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_TSENS_INT_MAP + NA + 0x3C + 0x20 + + + CORE1_LP_TSENS_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_UART_INT_MAP + NA + 0x40 + 0x20 + + + CORE1_LP_UART_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_EFUSE_INT_MAP + NA + 0x44 + 0x20 + + + CORE1_LP_EFUSE_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_SW_INT_MAP + NA + 0x48 + 0x20 + + + CORE1_LP_SW_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_SYSREG_INT_MAP + NA + 0x4C + 0x20 + + + CORE1_LP_SYSREG_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_HUK_INT_MAP + NA + 0x50 + 0x20 + + + CORE1_LP_HUK_INT_MAP + NA + 0 + 6 + read-write + + + + + SYS_ICM_INT_MAP + NA + 0x54 + 0x20 + + + CORE1_SYS_ICM_INT_MAP + NA + 0 + 6 + read-write + + + + + USB_DEVICE_INT_MAP + NA + 0x58 + 0x20 + + + CORE1_USB_DEVICE_INT_MAP + NA + 0 + 6 + read-write + + + + + SDIO_HOST_INT_MAP + NA + 0x5C + 0x20 + + + CORE1_SDIO_HOST_INT_MAP + NA + 0 + 6 + read-write + + + + + GDMA_INT_MAP + NA + 0x60 + 0x20 + + + CORE1_GDMA_INT_MAP + NA + 0 + 6 + read-write + + + + + SPI2_INT_MAP + NA + 0x64 + 0x20 + + + CORE1_SPI2_INT_MAP + NA + 0 + 6 + read-write + + + + + SPI3_INT_MAP + NA + 0x68 + 0x20 + + + CORE1_SPI3_INT_MAP + NA + 0 + 6 + read-write + + + + + I2S0_INT_MAP + NA + 0x6C + 0x20 + + + CORE1_I2S0_INT_MAP + NA + 0 + 6 + read-write + + + + + I2S1_INT_MAP + NA + 0x70 + 0x20 + + + CORE1_I2S1_INT_MAP + NA + 0 + 6 + read-write + + + + + I2S2_INT_MAP + NA + 0x74 + 0x20 + + + CORE1_I2S2_INT_MAP + NA + 0 + 6 + read-write + + + + + UHCI0_INT_MAP + NA + 0x78 + 0x20 + + + CORE1_UHCI0_INT_MAP + NA + 0 + 6 + read-write + + + + + UART0_INT_MAP + NA + 0x7C + 0x20 + + + CORE1_UART0_INT_MAP + NA + 0 + 6 + read-write + + + + + UART1_INT_MAP + NA + 0x80 + 0x20 + + + CORE1_UART1_INT_MAP + NA + 0 + 6 + read-write + + + + + UART2_INT_MAP + NA + 0x84 + 0x20 + + + CORE1_UART2_INT_MAP + NA + 0 + 6 + read-write + + + + + UART3_INT_MAP + NA + 0x88 + 0x20 + + + CORE1_UART3_INT_MAP + NA + 0 + 6 + read-write + + + + + UART4_INT_MAP + NA + 0x8C + 0x20 + + + CORE1_UART4_INT_MAP + NA + 0 + 6 + read-write + + + + + LCD_CAM_INT_MAP + NA + 0x90 + 0x20 + + + CORE1_LCD_CAM_INT_MAP + NA + 0 + 6 + read-write + + + + + ADC_INT_MAP + NA + 0x94 + 0x20 + + + CORE1_ADC_INT_MAP + NA + 0 + 6 + read-write + + + + + PWM0_INT_MAP + NA + 0x98 + 0x20 + + + CORE1_PWM0_INT_MAP + NA + 0 + 6 + read-write + + + + + PWM1_INT_MAP + NA + 0x9C + 0x20 + + + CORE1_PWM1_INT_MAP + NA + 0 + 6 + read-write + + + + + CAN0_INT_MAP + NA + 0xA0 + 0x20 + + + CORE1_CAN0_INT_MAP + NA + 0 + 6 + read-write + + + + + CAN1_INT_MAP + NA + 0xA4 + 0x20 + + + CORE1_CAN1_INT_MAP + NA + 0 + 6 + read-write + + + + + CAN2_INT_MAP + NA + 0xA8 + 0x20 + + + CORE1_CAN2_INT_MAP + NA + 0 + 6 + read-write + + + + + RMT_INT_MAP + NA + 0xAC + 0x20 + + + CORE1_RMT_INT_MAP + NA + 0 + 6 + read-write + + + + + I2C0_INT_MAP + NA + 0xB0 + 0x20 + + + CORE1_I2C0_INT_MAP + NA + 0 + 6 + read-write + + + + + I2C1_INT_MAP + NA + 0xB4 + 0x20 + + + CORE1_I2C1_INT_MAP + NA + 0 + 6 + read-write + + + + + TIMERGRP0_T0_INT_MAP + NA + 0xB8 + 0x20 + + + CORE1_TIMERGRP0_T0_INT_MAP + NA + 0 + 6 + read-write + + + + + TIMERGRP0_T1_INT_MAP + NA + 0xBC + 0x20 + + + CORE1_TIMERGRP0_T1_INT_MAP + NA + 0 + 6 + read-write + + + + + TIMERGRP0_WDT_INT_MAP + NA + 0xC0 + 0x20 + + + CORE1_TIMERGRP0_WDT_INT_MAP + NA + 0 + 6 + read-write + + + + + TIMERGRP1_T0_INT_MAP + NA + 0xC4 + 0x20 + + + CORE1_TIMERGRP1_T0_INT_MAP + NA + 0 + 6 + read-write + + + + + TIMERGRP1_T1_INT_MAP + NA + 0xC8 + 0x20 + + + CORE1_TIMERGRP1_T1_INT_MAP + NA + 0 + 6 + read-write + + + + + TIMERGRP1_WDT_INT_MAP + NA + 0xCC + 0x20 + + + CORE1_TIMERGRP1_WDT_INT_MAP + NA + 0 + 6 + read-write + + + + + LEDC_INT_MAP + NA + 0xD0 + 0x20 + + + CORE1_LEDC_INT_MAP + NA + 0 + 6 + read-write + + + + + SYSTIMER_TARGET0_INT_MAP + NA + 0xD4 + 0x20 + + + CORE1_SYSTIMER_TARGET0_INT_MAP + NA + 0 + 6 + read-write + + + + + SYSTIMER_TARGET1_INT_MAP + NA + 0xD8 + 0x20 + + + CORE1_SYSTIMER_TARGET1_INT_MAP + NA + 0 + 6 + read-write + + + + + SYSTIMER_TARGET2_INT_MAP + NA + 0xDC + 0x20 + + + CORE1_SYSTIMER_TARGET2_INT_MAP + NA + 0 + 6 + read-write + + + + + AHB_PDMA_IN_CH0_INT_MAP + NA + 0xE0 + 0x20 + + + CORE1_AHB_PDMA_IN_CH0_INT_MAP + NA + 0 + 6 + read-write + + + + + AHB_PDMA_IN_CH1_INT_MAP + NA + 0xE4 + 0x20 + + + CORE1_AHB_PDMA_IN_CH1_INT_MAP + NA + 0 + 6 + read-write + + + + + AHB_PDMA_IN_CH2_INT_MAP + NA + 0xE8 + 0x20 + + + CORE1_AHB_PDMA_IN_CH2_INT_MAP + NA + 0 + 6 + read-write + + + + + AHB_PDMA_OUT_CH0_INT_MAP + NA + 0xEC + 0x20 + + + CORE1_AHB_PDMA_OUT_CH0_INT_MAP + NA + 0 + 6 + read-write + + + + + AHB_PDMA_OUT_CH1_INT_MAP + NA + 0xF0 + 0x20 + + + CORE1_AHB_PDMA_OUT_CH1_INT_MAP + NA + 0 + 6 + read-write + + + + + AHB_PDMA_OUT_CH2_INT_MAP + NA + 0xF4 + 0x20 + + + CORE1_AHB_PDMA_OUT_CH2_INT_MAP + NA + 0 + 6 + read-write + + + + + AXI_PDMA_IN_CH0_INT_MAP + NA + 0xF8 + 0x20 + + + CORE1_AXI_PDMA_IN_CH0_INT_MAP + NA + 0 + 6 + read-write + + + + + AXI_PDMA_IN_CH1_INT_MAP + NA + 0xFC + 0x20 + + + CORE1_AXI_PDMA_IN_CH1_INT_MAP + NA + 0 + 6 + read-write + + + + + AXI_PDMA_IN_CH2_INT_MAP + NA + 0x100 + 0x20 + + + CORE1_AXI_PDMA_IN_CH2_INT_MAP + NA + 0 + 6 + read-write + + + + + AXI_PDMA_OUT_CH0_INT_MAP + NA + 0x104 + 0x20 + + + CORE1_AXI_PDMA_OUT_CH0_INT_MAP + NA + 0 + 6 + read-write + + + + + AXI_PDMA_OUT_CH1_INT_MAP + NA + 0x108 + 0x20 + + + CORE1_AXI_PDMA_OUT_CH1_INT_MAP + NA + 0 + 6 + read-write + + + + + AXI_PDMA_OUT_CH2_INT_MAP + NA + 0x10C + 0x20 + + + CORE1_AXI_PDMA_OUT_CH2_INT_MAP + NA + 0 + 6 + read-write + + + + + RSA_INT_MAP + NA + 0x110 + 0x20 + + + CORE1_RSA_INT_MAP + NA + 0 + 6 + read-write + + + + + AES_INT_MAP + NA + 0x114 + 0x20 + + + CORE1_AES_INT_MAP + NA + 0 + 6 + read-write + + + + + SHA_INT_MAP + NA + 0x118 + 0x20 + + + CORE1_SHA_INT_MAP + NA + 0 + 6 + read-write + + + + + ECC_INT_MAP + NA + 0x11C + 0x20 + + + CORE1_ECC_INT_MAP + NA + 0 + 6 + read-write + + + + + ECDSA_INT_MAP + NA + 0x120 + 0x20 + + + CORE1_ECDSA_INT_MAP + NA + 0 + 6 + read-write + + + + + KM_INT_MAP + NA + 0x124 + 0x20 + + + CORE1_KM_INT_MAP + NA + 0 + 6 + read-write + + + + + GPIO_INT0_MAP + NA + 0x128 + 0x20 + + + CORE1_GPIO_INT0_MAP + NA + 0 + 6 + read-write + + + + + GPIO_INT1_MAP + NA + 0x12C + 0x20 + + + CORE1_GPIO_INT1_MAP + NA + 0 + 6 + read-write + + + + + GPIO_INT2_MAP + NA + 0x130 + 0x20 + + + CORE1_GPIO_INT2_MAP + NA + 0 + 6 + read-write + + + + + GPIO_INT3_MAP + NA + 0x134 + 0x20 + + + CORE1_GPIO_INT3_MAP + NA + 0 + 6 + read-write + + + + + GPIO_PAD_COMP_INT_MAP + NA + 0x138 + 0x20 + + + CORE1_GPIO_PAD_COMP_INT_MAP + NA + 0 + 6 + read-write + + + + + CPU_INT_FROM_CPU_0_MAP + NA + 0x13C + 0x20 + + + CORE1_CPU_INT_FROM_CPU_0_MAP + NA + 0 + 6 + read-write + + + + + CPU_INT_FROM_CPU_1_MAP + NA + 0x140 + 0x20 + + + CORE1_CPU_INT_FROM_CPU_1_MAP + NA + 0 + 6 + read-write + + + + + CPU_INT_FROM_CPU_2_MAP + NA + 0x144 + 0x20 + + + CORE1_CPU_INT_FROM_CPU_2_MAP + NA + 0 + 6 + read-write + + + + + CPU_INT_FROM_CPU_3_MAP + NA + 0x148 + 0x20 + + + CORE1_CPU_INT_FROM_CPU_3_MAP + NA + 0 + 6 + read-write + + + + + CACHE_INT_MAP + NA + 0x14C + 0x20 + + + CORE1_CACHE_INT_MAP + NA + 0 + 6 + read-write + + + + + FLASH_MSPI_INT_MAP + NA + 0x150 + 0x20 + + + CORE1_FLASH_MSPI_INT_MAP + NA + 0 + 6 + read-write + + + + + CSI_BRIDGE_INT_MAP + NA + 0x154 + 0x20 + + + CORE1_CSI_BRIDGE_INT_MAP + NA + 0 + 6 + read-write + + + + + DSI_BRIDGE_INT_MAP + NA + 0x158 + 0x20 + + + CORE1_DSI_BRIDGE_INT_MAP + NA + 0 + 6 + read-write + + + + + CSI_INT_MAP + NA + 0x15C + 0x20 + + + CORE1_CSI_INT_MAP + NA + 0 + 6 + read-write + + + + + DSI_INT_MAP + NA + 0x160 + 0x20 + + + CORE1_DSI_INT_MAP + NA + 0 + 6 + read-write + + + + + GMII_PHY_INT_MAP + NA + 0x164 + 0x20 + + + CORE1_GMII_PHY_INT_MAP + NA + 0 + 6 + read-write + + + + + LPI_INT_MAP + NA + 0x168 + 0x20 + + + CORE1_LPI_INT_MAP + NA + 0 + 6 + read-write + + + + + PMT_INT_MAP + NA + 0x16C + 0x20 + + + CORE1_PMT_INT_MAP + NA + 0 + 6 + read-write + + + + + SBD_INT_MAP + NA + 0x170 + 0x20 + + + CORE1_SBD_INT_MAP + NA + 0 + 6 + read-write + + + + + USB_OTG_INT_MAP + NA + 0x174 + 0x20 + + + CORE1_USB_OTG_INT_MAP + NA + 0 + 6 + read-write + + + + + USB_OTG_ENDP_MULTI_PROC_INT_MAP + NA + 0x178 + 0x20 + + + CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP + NA + 0 + 6 + read-write + + + + + JPEG_INT_MAP + NA + 0x17C + 0x20 + + + CORE1_JPEG_INT_MAP + NA + 0 + 6 + read-write + + + + + PPA_INT_MAP + NA + 0x180 + 0x20 + + + CORE1_PPA_INT_MAP + NA + 0 + 6 + read-write + + + + + CORE0_TRACE_INT_MAP + NA + 0x184 + 0x20 + + + CORE1_CORE0_TRACE_INT_MAP + NA + 0 + 6 + read-write + + + + + CORE1_TRACE_INT_MAP + NA + 0x188 + 0x20 + + + CORE1_CORE1_TRACE_INT_MAP + NA + 0 + 6 + read-write + + + + + HP_CORE_CTRL_INT_MAP + NA + 0x18C + 0x20 + + + CORE1_HP_CORE_CTRL_INT_MAP + NA + 0 + 6 + read-write + + + + + ISP_INT_MAP + NA + 0x190 + 0x20 + + + CORE1_ISP_INT_MAP + NA + 0 + 6 + read-write + + + + + I3C_MST_INT_MAP + NA + 0x194 + 0x20 + + + CORE1_I3C_MST_INT_MAP + NA + 0 + 6 + read-write + + + + + I3C_SLV_INT_MAP + NA + 0x198 + 0x20 + + + CORE1_I3C_SLV_INT_MAP + NA + 0 + 6 + read-write + + + + + USB_OTG11_INT_MAP + NA + 0x19C + 0x20 + + + CORE1_USB_OTG11_INT_MAP + NA + 0 + 6 + read-write + + + + + DMA2D_IN_CH0_INT_MAP + NA + 0x1A0 + 0x20 + + + CORE1_DMA2D_IN_CH0_INT_MAP + NA + 0 + 6 + read-write + + + + + DMA2D_IN_CH1_INT_MAP + NA + 0x1A4 + 0x20 + + + CORE1_DMA2D_IN_CH1_INT_MAP + NA + 0 + 6 + read-write + + + + + DMA2D_OUT_CH0_INT_MAP + NA + 0x1A8 + 0x20 + + + CORE1_DMA2D_OUT_CH0_INT_MAP + NA + 0 + 6 + read-write + + + + + DMA2D_OUT_CH1_INT_MAP + NA + 0x1AC + 0x20 + + + CORE1_DMA2D_OUT_CH1_INT_MAP + NA + 0 + 6 + read-write + + + + + DMA2D_OUT_CH2_INT_MAP + NA + 0x1B0 + 0x20 + + + CORE1_DMA2D_OUT_CH2_INT_MAP + NA + 0 + 6 + read-write + + + + + PSRAM_MSPI_INT_MAP + NA + 0x1B4 + 0x20 + + + CORE1_PSRAM_MSPI_INT_MAP + NA + 0 + 6 + read-write + + + + + HP_SYSREG_INT_MAP + NA + 0x1B8 + 0x20 + + + CORE1_HP_SYSREG_INT_MAP + NA + 0 + 6 + read-write + + + + + PCNT_INT_MAP + NA + 0x1BC + 0x20 + + + CORE1_PCNT_INT_MAP + NA + 0 + 6 + read-write + + + + + HP_PAU_INT_MAP + NA + 0x1C0 + 0x20 + + + CORE1_HP_PAU_INT_MAP + NA + 0 + 6 + read-write + + + + + HP_PARLIO_RX_INT_MAP + NA + 0x1C4 + 0x20 + + + CORE1_HP_PARLIO_RX_INT_MAP + NA + 0 + 6 + read-write + + + + + HP_PARLIO_TX_INT_MAP + NA + 0x1C8 + 0x20 + + + CORE1_HP_PARLIO_TX_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_OUT_CH0_INT_MAP + NA + 0x1CC + 0x20 + + + CORE1_H264_DMA2D_OUT_CH0_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_OUT_CH1_INT_MAP + NA + 0x1D0 + 0x20 + + + CORE1_H264_DMA2D_OUT_CH1_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_OUT_CH2_INT_MAP + NA + 0x1D4 + 0x20 + + + CORE1_H264_DMA2D_OUT_CH2_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_OUT_CH3_INT_MAP + NA + 0x1D8 + 0x20 + + + CORE1_H264_DMA2D_OUT_CH3_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_OUT_CH4_INT_MAP + NA + 0x1DC + 0x20 + + + CORE1_H264_DMA2D_OUT_CH4_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_IN_CH0_INT_MAP + NA + 0x1E0 + 0x20 + + + CORE1_H264_DMA2D_IN_CH0_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_IN_CH1_INT_MAP + NA + 0x1E4 + 0x20 + + + CORE1_H264_DMA2D_IN_CH1_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_IN_CH2_INT_MAP + NA + 0x1E8 + 0x20 + + + CORE1_H264_DMA2D_IN_CH2_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_IN_CH3_INT_MAP + NA + 0x1EC + 0x20 + + + CORE1_H264_DMA2D_IN_CH3_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_IN_CH4_INT_MAP + NA + 0x1F0 + 0x20 + + + CORE1_H264_DMA2D_IN_CH4_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_IN_CH5_INT_MAP + NA + 0x1F4 + 0x20 + + + CORE1_H264_DMA2D_IN_CH5_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_REG_INT_MAP + NA + 0x1F8 + 0x20 + + + CORE1_H264_REG_INT_MAP + NA + 0 + 6 + read-write + + + + + ASSIST_DEBUG_INT_MAP + NA + 0x1FC + 0x20 + + + CORE1_ASSIST_DEBUG_INT_MAP + NA + 0 + 6 + read-write + + + + + INTR_STATUS_REG_0 + NA + 0x200 + 0x20 + + + CORE1_INTR_STATUS_0 + NA + 0 + 32 + read-only + + + + + INTR_STATUS_REG_1 + NA + 0x204 + 0x20 + + + CORE1_INTR_STATUS_1 + NA + 0 + 32 + read-only + + + + + INTR_STATUS_REG_2 + NA + 0x208 + 0x20 + + + CORE1_INTR_STATUS_2 + NA + 0 + 32 + read-only + + + + + INTR_STATUS_REG_3 + NA + 0x20C + 0x20 + + + CORE1_INTR_STATUS_3 + NA + 0 + 32 + read-only + + + + + CLOCK_GATE + NA + 0x210 + 0x20 + 0x00000001 + + + CORE1_REG_CLK_EN + NA + 0 + 1 + read-write + + + + + INTERRUPT_REG_DATE + NA + 0x3FC + 0x20 + 0x02003020 + + + CORE1_INTERRUPT_REG_DATE + NA + 0 + 28 + read-write + + + + + + + MIPI_CSI_BRIDGE + MIPI Camera Interface Bridge + CSI_BRIG + 0x5009F800 + + 0x0 + 0x48 + registers + + + CSI_BRIDGE + 85 + + + + CLK_EN + csi bridge register mapping unit clock gating. + 0x0 + 0x20 + + + CLK_EN + 0: enable clock gating. 1: disable clock gating, clock always on. + 0 + 1 + read-write + + + + + CSI_EN + csi bridge enable. + 0x4 + 0x20 + + + CSI_BRIG_EN + 0: disable csi bridge. 1: enable csi bridge. + 0 + 1 + read-write + + + + + DMA_REQ_CFG + dma request configuration. + 0x8 + 0x20 + 0x00000080 + + + DMA_BURST_LEN + DMA burst length. + 0 + 12 + read-write + + + DMA_CFG_UPD_BY_BLK + 1: reg_dma_burst_len & reg_dma_burst_len will be updated by dma block finish. 0: updated by frame. + 12 + 1 + read-write + + + DMA_FORCE_RD_STATUS + 1: mask dma request when reading frame info. 0: disable mask. + 16 + 1 + read-write + + + + + BUF_FLOW_CTL + csi bridge buffer control. + 0xC + 0x20 + 0x000007F8 + + + CSI_BUF_AFULL_THRD + buffer almost full threshold. + 0 + 14 + read-write + + + CSI_BUF_DEPTH + buffer data count. + 16 + 14 + read-only + + + + + DATA_TYPE_CFG + pixel data type configuration. + 0x10 + 0x20 + 0x00002F18 + + + DATA_TYPE_MIN + the min value of data type used for pixel filter. + 0 + 6 + read-write + + + DATA_TYPE_MAX + the max value of data type used for pixel filter. + 8 + 6 + read-write + + + + + FRAME_CFG + frame configuration. + 0x14 + 0x20 + 0x011E01E0 + + + VADR_NUM + vadr of frame data. + 0 + 12 + read-write + + + HADR_NUM + hadr of frame data. + 12 + 12 + read-write + + + HAS_HSYNC_E + 0: frame data doesn't contain hsync. 1: frame data contains hsync. + 24 + 1 + read-write + + + VADR_NUM_CHECK + 0: disable vadr check. 1: enable vadr check. + 25 + 1 + read-write + + + + + ENDIAN_MODE + data endianness order configuration. + 0x18 + 0x20 + + + BYTE_ENDIAN_ORDER + endianness order in bytes. 2'h0 is normal mode and 2'h3 is useful to YUV420(Legacy) when isp is bapassed. + 0 + 1 + read-write + + + BIT_ENDIAN_ORDER + N/A + 1 + 1 + read-write + + + + + INT_RAW + csi bridge interrupt raw. + 0x1C + 0x20 + + + VADR_NUM_GT_INT_RAW + reg_vadr_num is greater than real interrupt raw. + 0 + 1 + read-write + + + VADR_NUM_LT_INT_RAW + reg_vadr_num is less than real interrupt raw. + 1 + 1 + read-write + + + DISCARD_INT_RAW + an incomplete frame of data was sent interrupt raw. + 2 + 1 + read-write + + + CSI_BUF_OVERRUN_INT_RAW + buffer overrun interrupt raw. + 3 + 1 + read-write + + + CSI_ASYNC_FIFO_OVF_INT_RAW + buffer overflow interrupt raw. + 4 + 1 + read-write + + + DMA_CFG_HAS_UPDATED_INT_RAW + dma configuration update complete interrupt raw. + 5 + 1 + read-write + + + + + INT_CLR + csi bridge interrupt clr. + 0x20 + 0x20 + + + VADR_NUM_GT_REAL_INT_CLR + reg_vadr_num is greater than real interrupt clr. + 0 + 1 + write-only + + + VADR_NUM_LT_REAL_INT_CLR + reg_vadr_num is less than real interrupt clr. + 1 + 1 + write-only + + + DISCARD_INT_CLR + an incomplete frame of data was sent interrupt clr. + 2 + 1 + write-only + + + CSI_BUF_OVERRUN_INT_CLR + buffer overrun interrupt clr. + 3 + 1 + write-only + + + CSI_ASYNC_FIFO_OVF_INT_CLR + buffer overflow interrupt clr. + 4 + 1 + write-only + + + DMA_CFG_HAS_UPDATED_INT_CLR + dma configuration update complete interrupt clr. + 5 + 1 + write-only + + + + + INT_ST + csi bridge interrupt st. + 0x24 + 0x20 + + + VADR_NUM_GT_INT_ST + reg_vadr_num is greater than real interrupt st. + 0 + 1 + read-only + + + VADR_NUM_LT_INT_ST + reg_vadr_num is less than real interrupt st. + 1 + 1 + read-only + + + DISCARD_INT_ST + an incomplete frame of data was sent interrupt st. + 2 + 1 + read-only + + + CSI_BUF_OVERRUN_INT_ST + buffer overrun interrupt st. + 3 + 1 + read-only + + + CSI_ASYNC_FIFO_OVF_INT_ST + buffer overflow interrupt st. + 4 + 1 + read-only + + + DMA_CFG_HAS_UPDATED_INT_ST + dma configuration update complete interrupt st. + 5 + 1 + read-only + + + + + INT_ENA + csi bridge interrupt enable. + 0x28 + 0x20 + + + VADR_NUM_GT_INT_ENA + reg_vadr_num is greater than real interrupt enable. + 0 + 1 + read-write + + + VADR_NUM_LT_INT_ENA + reg_vadr_num is less than real interrupt enable. + 1 + 1 + read-write + + + DISCARD_INT_ENA + an incomplete frame of data was sent interrupt enable. + 2 + 1 + read-write + + + CSI_BUF_OVERRUN_INT_ENA + buffer overrun interrupt enable. + 3 + 1 + read-write + + + CSI_ASYNC_FIFO_OVF_INT_ENA + buffer overflow interrupt enable. + 4 + 1 + read-write + + + DMA_CFG_HAS_UPDATED_INT_ENA + dma configuration update complete interrupt enable. + 5 + 1 + read-write + + + + + DMA_REQ_INTERVAL + DMA interval configuration. + 0x2C + 0x20 + 0x00000001 + + + DMA_REQ_INTERVAL + 16'b1: 1 cycle. 16'b11: 2 cycle. ... ... 16'hFFFF: 16 cycle. + 0 + 16 + read-write + + + + + DMABLK_SIZE + DMA block size configuration. + 0x30 + 0x20 + 0x00001FFF + + + DMABLK_SIZE + the number of reg_dma_burst_len in a block + 0 + 13 + read-write + + + + + RDN_ECO_CS + N/A + 0x34 + 0x20 + + + RDN_ECO_EN + N/A + 0 + 1 + read-write + + + RDN_ECO_RESULT + N/A + 1 + 1 + read-only + + + + + RDN_ECO_LOW + N/A + 0x38 + 0x20 + + + RDN_ECO_LOW + N/A + 0 + 32 + read-write + + + + + RDN_ECO_HIGH + N/A + 0x3C + 0x20 + 0xFFFFFFFF + + + RDN_ECO_HIGH + N/A + 0 + 32 + read-write + + + + + HOST_CTRL + csi host control by csi bridge. + 0x40 + 0x20 + 0x00000003 + + + CSI_ENABLECLK + enable clock lane module of csi phy. + 0 + 1 + read-write + + + CSI_CFG_CLK_EN + enable cfg_clk of csi host module. + 1 + 1 + read-write + + + LOOPBK_TEST_EN + for phy test by loopback dsi phy to csi phy. + 2 + 1 + read-write + + + + + MEM_CTRL + csi bridge buffer control. + 0x44 + 0x20 + 0x00002640 + + + CSI_BRIDGE_MEM_CLK_FORCE_ON + csi bridge memory clock gating force on. + 0 + 1 + read-write + + + CSI_MEM_AUX_CTRL + N/A + 1 + 14 + read-write + + + + + + + MIPI_CSI_HOST + MIPI Camera Interface Host + CSI_HOST + 0x5009F000 + + 0x0 + 0xA8 + registers + + + CSI + 87 + + + + VERSION + NA + 0x0 + 0x20 + 0x3135302A + + + VERSION + NA + 0 + 32 + read-only + + + + + N_LANES + NA + 0x4 + 0x20 + 0x00000001 + + + N_LANES + NA + 0 + 3 + read-write + + + + + CSI2_RESETN + NA + 0x8 + 0x20 + + + CSI2_RESETN + NA + 0 + 1 + read-write + + + + + INT_ST_MAIN + NA + 0xC + 0x20 + + + ST_STATUS_INT_PHY_FATAL + NA + 0 + 1 + read-only + + + ST_STATUS_INT_PKT_FATAL + NA + 1 + 1 + read-only + + + ST_STATUS_INT_BNDRY_FRAME_FATAL + NA + 2 + 1 + read-only + + + ST_STATUS_INT_SEQ_FRAME_FATAL + NA + 3 + 1 + read-only + + + ST_STATUS_INT_CRC_FRAME_FATAL + NA + 4 + 1 + read-only + + + ST_STATUS_INT_PLD_CRC_FATAL + NA + 5 + 1 + read-only + + + ST_STATUS_INT_DATA_ID + NA + 6 + 1 + read-only + + + ST_STATUS_INT_ECC_CORRECTED + NA + 7 + 1 + read-only + + + ST_STATUS_INT_PHY + NA + 16 + 1 + read-only + + + + + PHY_SHUTDOWNZ + NA + 0x40 + 0x20 + + + PHY_SHUTDOWNZ + NA + 0 + 1 + read-write + + + + + DPHY_RSTZ + NA + 0x44 + 0x20 + + + DPHY_RSTZ + NA + 0 + 1 + read-write + + + + + PHY_RX + NA + 0x48 + 0x20 + 0x00010000 + + + PHY_RXULPSESC_0 + NA + 0 + 1 + read-only + + + PHY_RXULPSESC_1 + NA + 1 + 1 + read-only + + + PHY_RXULPSCLKNOT + NA + 16 + 1 + read-only + + + PHY_RXCLKACTIVEHS + NA + 17 + 1 + read-only + + + + + PHY_STOPSTATE + NA + 0x4C + 0x20 + + + PHY_STOPSTATEDATA_0 + NA + 0 + 1 + read-only + + + PHY_STOPSTATEDATA_1 + NA + 1 + 1 + read-only + + + PHY_STOPSTATECLK + NA + 16 + 1 + read-only + + + + + PHY_TEST_CTRL0 + NA + 0x50 + 0x20 + 0x00000001 + + + PHY_TESTCLR + NA + 0 + 1 + read-write + + + PHY_TESTCLK + NA + 1 + 1 + read-write + + + + + PHY_TEST_CTRL1 + NA + 0x54 + 0x20 + + + PHY_TESTDIN + NA + 0 + 8 + read-write + + + PHY_TESTDOUT + NA + 8 + 8 + read-only + + + PHY_TESTEN + NA + 16 + 1 + read-write + + + + + VC_EXTENSION + NA + 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CH2_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL + NA + 2 + 1 + read-only + + + CH2_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL + NA + 3 + 1 + read-only + + + + + CH2_INTCLEAR0 + NA + 0x298 + 0x20 + + + CH2_CLEAR_BLOCK_TFR_DONE_INTSTAT + NA + 0 + 1 + write-only + + + CH2_CLEAR_DMA_TFR_DONE_INTSTAT + NA + 1 + 1 + write-only + + + CH2_CLEAR_SRC_TRANSCOMP_INTSTAT + NA + 3 + 1 + write-only + + + CH2_CLEAR_DST_TRANSCOMP_INTSTAT + NA + 4 + 1 + write-only + + + CH2_CLEAR_SRC_DEC_ERR_INTSTAT + NA + 5 + 1 + write-only + + + CH2_CLEAR_DST_DEC_ERR_INTSTAT + NA + 6 + 1 + write-only + + + CH2_CLEAR_SRC_SLV_ERR_INTSTAT + NA + 7 + 1 + write-only + + + CH2_CLEAR_DST_SLV_ERR_INTSTAT + NA + 8 + 1 + write-only + + + CH2_CLEAR_LLI_RD_DEC_ERR_INTSTAT + NA + 9 + 1 + write-only + + + CH2_CLEAR_LLI_WR_DEC_ERR_INTSTAT + NA + 10 + 1 + write-only + + + CH2_CLEAR_LLI_RD_SLV_ERR_INTSTAT + NA + 11 + 1 + write-only + + + CH2_CLEAR_LLI_WR_SLV_ERR_INTSTAT + NA + 12 + 1 + write-only + + + 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CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL + NA + 2 + 1 + read-only + + + CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL + NA + 3 + 1 + read-only + + + + + CH4_INTCLEAR0 + NA + 0x498 + 0x20 + + + CH4_CLEAR_BLOCK_TFR_DONE_INTSTAT + NA + 0 + 1 + write-only + + + CH4_CLEAR_DMA_TFR_DONE_INTSTAT + NA + 1 + 1 + write-only + + + CH4_CLEAR_SRC_TRANSCOMP_INTSTAT + NA + 3 + 1 + write-only + + + CH4_CLEAR_DST_TRANSCOMP_INTSTAT + NA + 4 + 1 + write-only + + + CH4_CLEAR_SRC_DEC_ERR_INTSTAT + NA + 5 + 1 + write-only + + + CH4_CLEAR_DST_DEC_ERR_INTSTAT + NA + 6 + 1 + write-only + + + CH4_CLEAR_SRC_SLV_ERR_INTSTAT + NA + 7 + 1 + write-only + + + CH4_CLEAR_DST_SLV_ERR_INTSTAT + NA + 8 + 1 + write-only + + + CH4_CLEAR_LLI_RD_DEC_ERR_INTSTAT + NA + 9 + 1 + write-only + + + CH4_CLEAR_LLI_WR_DEC_ERR_INTSTAT + NA + 10 + 1 + write-only + + + CH4_CLEAR_LLI_RD_SLV_ERR_INTSTAT + NA + 11 + 1 + write-only + + + CH4_CLEAR_LLI_WR_SLV_ERR_INTSTAT + NA + 12 + 1 + write-only + + + CH4_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT + NA + 13 + 1 + write-only + + + CH4_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT + NA + 14 + 1 + write-only + + + CH4_CLEAR_SLVIF_DEC_ERR_INTSTAT + NA + 16 + 1 + write-only + + + CH4_CLEAR_SLVIF_WR2RO_ERR_INTSTAT + NA + 17 + 1 + write-only + + + CH4_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT + NA + 18 + 1 + write-only + + + CH4_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT + NA + 19 + 1 + write-only + + + CH4_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT + NA + 20 + 1 + write-only + + + CH4_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT + NA + 21 + 1 + write-only + + + CH4_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT + NA + 25 + 1 + write-only + + + CH4_CLEAR_CH_LOCK_CLEARED_INTSTAT + NA + 27 + 1 + write-only + + + CH4_CLEAR_CH_SRC_SUSPENDED_INTSTAT + NA + 28 + 1 + write-only + + + CH4_CLEAR_CH_SUSPENDED_INTSTAT + NA + 29 + 1 + write-only + + + CH4_CLEAR_CH_DISABLED_INTSTAT + NA + 30 + 1 + write-only + + + CH4_CLEAR_CH_ABORTED_INTSTAT + NA + 31 + 1 + write-only + + + + + CH4_INTCLEAR1 + NA + 0x49C + 0x20 + + + CH4_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT + NA + 0 + 1 + write-only + + + CH4_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT + NA + 1 + 1 + write-only + + + CH4_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT + NA + 2 + 1 + write-only + + + CH4_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT + NA + 3 + 1 + write-only + + + + + + + DS + Digital Signature + DS + 0x50094000 + + 0x0 + 0xA5C + registers + + + + 128 + 0x4 + Y_MEM[%s] + memory that stores Y + 0x0 + 0x20 + + + 128 + 0x4 + M_MEM[%s] + memory that stores M + 0x200 + 0x20 + + + 128 + 0x4 + RB_MEM[%s] + memory that stores Rb + 0x400 + 0x20 + + + 12 + 0x4 + BOX_MEM[%s] + memory that stores BOX + 0x600 + 0x20 + + + 4 + 0x4 + IV_MEM[%s] + memory that stores IV + 0x630 + 0x20 + + + 128 + 0x4 + X_MEM[%s] + memory that stores X + 0x800 + 0x20 + + + 128 + 0x4 + Z_MEM[%s] + memory that stores Z + 0xA00 + 0x20 + + + SET_START + DS start control register + 0xE00 + 0x20 + + + SET_START + set this bit to start DS operation. + 0 + 1 + write-only + + + + + SET_CONTINUE + DS continue control register + 0xE04 + 0x20 + + + SET_CONTINUE + set this bit to continue DS operation. + 0 + 1 + write-only + + + + + SET_FINISH + DS finish control register + 0xE08 + 0x20 + + + SET_FINISH + Set this bit to finish DS process. + 0 + 1 + write-only + + + + + QUERY_BUSY + DS query busy register + 0xE0C + 0x20 + + + QUERY_BUSY + digital signature state. 1'b0: idle, 1'b1: busy + 0 + 1 + read-only + + + + + QUERY_KEY_WRONG + DS query key-wrong counter register + 0xE10 + 0x20 + + + QUERY_KEY_WRONG + digital signature key wrong counter + 0 + 4 + read-only + + + + + QUERY_CHECK + DS query check result register + 0xE14 + 0x20 + + + MD_ERROR + MD checkout result. 1'b0: MD check pass, 1'b1: MD check fail + 0 + 1 + read-only + + + PADDING_BAD + padding checkout result. 1'b0: a good padding, 1'b1: a bad padding + 1 + 1 + read-only + + + + + DATE + DS version control register + 0xE20 + 0x20 + 0x20200618 + + + DATE + ds version information + 0 + 30 + read-write + + + + + + + MIPI_DSI_BRIDGE + MIPI Camera Interface Bridge + DSI_BRG + 0x500A0800 + + 0x0 + 0x94 + registers + + + DSI_BRIDGE + 86 + + + + CLK_EN + dsi bridge clk control register + 0x0 + 0x20 + + + CLK_EN + this bit configures force_on of dsi_bridge register clock gate + 0 + 1 + read-write + + + + + EN + dsi bridge en register + 0x4 + 0x20 + + + DSI_EN + this bit configures module enable of dsi_bridge. 0: disable, 1: enable + 0 + 1 + read-write + + + + + DMA_REQ_CFG + dsi bridge dma burst len register + 0x8 + 0x20 + 0x00000080 + + + DMA_BURST_LEN + this field configures the num of 64-bit in one dma burst transfer, valid only when dsi_bridge as flow controller + 0 + 12 + read-write + + + + + RAW_NUM_CFG + dsi bridge raw number control register + 0xC + 0x20 + 0x00038400 + + + RAW_NUM_TOTAL + this field configures number of total pix bits/64 + 0 + 22 + read-write + + + UNALIGN_64BIT_EN + this field configures whether the total pix bits is a multiple of 64bits. 0: align to 64-bit, 1: unalign to 64-bit + 22 + 1 + read-write + + + RAW_NUM_TOTAL_SET + this bit configures enable of reload reg_raw_num_total to internal cnt. 0: disable, 1: enable. valid only when dsi_bridge as flow controller + 31 + 1 + write-only + + + + + RAW_BUF_CREDIT_CTL + dsi bridge credit register + 0x10 + 0x20 + 0x03200400 + + + CREDIT_THRD + this field configures the threshold whether dsi_bridge fifo can receive one more 64-bit, valid only when dsi_bridge as flow controller + 0 + 15 + read-write + + + CREDIT_BURST_THRD + this field configures the threshold whether dsi_bridge fifo can receive one more dma burst, valid only when dsi_bridge as flow controller + 16 + 15 + read-write + + + CREDIT_RESET + this bit configures internal credit cnt clear, 0: non, 1: reset. valid only when dsi_bridge as flow controller + 31 + 1 + read-write + + + + + FIFO_FLOW_STATUS + dsi bridge raw buffer depth register + 0x14 + 0x20 + + + RAW_BUF_DEPTH + this field configures the depth of dsi_bridge fifo depth + 0 + 14 + read-only + + + + + PIXEL_TYPE + dsi bridge dpi type control register + 0x18 + 0x20 + + + RAW_TYPE + this field configures the pixel type. 0: rgb888, 1:rgb666, 2:rgb565 + 0 + 4 + read-write + + + DPI_CONFIG + this field configures the pixel arrange type of dpi interface + 4 + 2 + read-write + + + DATA_IN_TYPE + input data type, 0: rgb, 1: yuv + 6 + 1 + read-write + + + + + DMA_BLOCK_INTERVAL + dsi bridge dma block interval control register + 0x1C + 0x20 + 0x30002409 + + + DMA_BLOCK_SLOT + this field configures the max block_slot_cnt + 0 + 10 + read-write + + + DMA_BLOCK_INTERVAL + this field configures the max block_interval_cnt, block_interval_cnt increased by 1 when block_slot_cnt if full + 10 + 18 + read-write + + + RAW_NUM_TOTAL_AUTO_RELOAD + this bit configures enable of auto reload reg_raw_num_total, 0: disable, 1: enable + 28 + 1 + read-write + + + EN + this bit configures enable of interval between dma block transfer, 0: disable, 1: enable + 29 + 1 + read-write + + + + + DMA_REQ_INTERVAL + dsi bridge dma req interval control register + 0x20 + 0x20 + 0x00000001 + + + DMA_REQ_INTERVAL + this field configures the interval between dma req events + 0 + 16 + read-write + + + + + DPI_LCD_CTL + dsi bridge dpi signal control register + 0x24 + 0x20 + + + DPISHUTDN + this bit configures dpishutdn signal in dpi interface + 0 + 1 + read-write + + + DPICOLORM + this bit configures dpicolorm signal in dpi interface + 1 + 1 + read-write + + + DPIUPDATECFG + this bit configures dpiupdatecfg signal in dpi interface + 2 + 1 + read-write + + + + + DPI_RSV_DPI_DATA + dsi bridge dpi reserved data register + 0x28 + 0x20 + 0x00003FFF + + + DPI_RSV_DATA + this field controls the pixel data sent to dsi_host when dsi_bridge fifo underflow + 0 + 30 + read-write + + + + + DPI_V_CFG0 + dsi bridge dpi v config register 0 + 0x30 + 0x20 + 0x01E0020D + + + VTOTAL + this field configures the total length of one frame (by line) for dpi output, must meet: reg_vtotal > reg_vdisp+reg_vsync+reg_vbank + 0 + 12 + read-write + + + VDISP + this field configures the length of valid line (by line) for dpi output + 16 + 12 + read-write + + + + + DPI_V_CFG1 + dsi bridge dpi v config register 1 + 0x34 + 0x20 + 0x00020021 + + + VBANK + this field configures the length between vsync and valid line (by line) for dpi output + 0 + 12 + read-write + + + VSYNC + this field configures the length of vsync (by line) for dpi output + 16 + 12 + read-write + + + + + DPI_H_CFG0 + dsi bridge dpi h config register 0 + 0x38 + 0x20 + 0x02800320 + + + HTOTAL + this field configures the total length of one line (by pixel num) for dpi output, must meet: reg_htotal > reg_hdisp+reg_hsync+reg_hbank + 0 + 12 + read-write + + + HDISP + this field configures the length of valid pixel data (by pixel num) for dpi output + 16 + 12 + read-write + + + + + DPI_H_CFG1 + dsi bridge dpi h config register 1 + 0x3C + 0x20 + 0x00600030 + + + HBANK + this field configures the length between hsync and pixel data valid (by pixel num) for dpi output + 0 + 12 + read-write + + + HSYNC + this field configures the length of hsync (by pixel num) for dpi output + 16 + 12 + read-write + + + + + DPI_MISC_CONFIG + dsi_bridge dpi misc config register + 0x40 + 0x20 + 0x000019D0 + + + DPI_EN + this bit configures enable of dpi output, 0: disable, 1: enable + 0 + 1 + read-write + + + FIFO_UNDERRUN_DISCARD_VCNT + this field configures the underrun interrupt musk, when underrun occurs and line cnt is less then this field + 4 + 12 + read-write + + + + + DPI_CONFIG_UPDATE + dsi_bridge dpi config update register + 0x44 + 0x20 + + + DPI_CONFIG_UPDATE + write 1 to this bit to update dpi config register MIPI_DSI_BRG_DPI_* + 0 + 1 + write-only + + + + + INT_ENA + dsi_bridge interrupt enable register + 0x50 + 0x20 + + + UNDERRUN_INT_ENA + write 1 to enables dpi_underrun_int_st field of MIPI_DSI_BRG_INT_ST_REG controlled by dpi_underrun interrupt signal + 0 + 1 + read-write + + + + + INT_CLR + dsi_bridge interrupt clear register + 0x54 + 0x20 + + + UNDERRUN_INT_CLR + write 1 to this bit to clear dpi_underrun_int_raw field of MIPI_DSI_BRG_INT_RAW_REG + 0 + 1 + write-only + + + + + INT_RAW + dsi_bridge raw interrupt register + 0x58 + 0x20 + + + UNDERRUN_INT_RAW + the raw interrupt status of dpi_underrun + 0 + 1 + read-write + + + + + INT_ST + dsi_bridge masked interrupt register + 0x5C + 0x20 + + + UNDERRUN_INT_ST + the masked interrupt status of dpi_underrun + 0 + 1 + read-only + + + + + HOST_BIST_CTL + dsi_bridge host bist control register + 0x60 + 0x20 + + + BISTOK + bistok + 0 + 1 + read-only + + + BISTON + biston + 1 + 1 + read-write + + + + + HOST_TRIGGER_REV + dsi_bridge host trigger reverse control register + 0x64 + 0x20 + + + TX_TRIGGER_REV_EN + tx_trigger reverse. 0: disable, 1: enable + 0 + 1 + read-write + + + RX_TRIGGER_REV_EN + rx_trigger reverse. 0: disable, 1: enable + 1 + 1 + read-write + + + + + BLK_RAW_NUM_CFG + dsi_bridge block raw number control register + 0x68 + 0x20 + 0x00038400 + + + BLK_RAW_NUM_TOTAL + this field configures number of total block pix bits/64 + 0 + 22 + read-write + + + BLK_RAW_NUM_TOTAL_SET + write 1 to reload reg_blk_raw_num_total to internal cnt + 31 + 1 + write-only + + + + + DMA_FRAME_INTERVAL + dsi_bridge dam frame interval control register + 0x6C + 0x20 + 0x20002409 + + + DMA_FRAME_SLOT + this field configures the max frame_slot_cnt + 0 + 10 + read-write + + + DMA_FRAME_INTERVAL + this field configures the max frame_interval_cnt, frame_interval_cnt increased by 1 when frame_slot_cnt if full + 10 + 18 + read-write + + + DMA_MULTIBLK_EN + this bit configures enable multi-blk transfer, 0: disable, 1: enable + 28 + 1 + read-write + + + EN + this bit configures enable interval between frame transfer, 0: disable, 1: enable + 29 + 1 + read-write + + + + + MEM_AUX_CTRL + dsi_bridge mem aux control register + 0x70 + 0x20 + 0x00001320 + + + DSI_MEM_AUX_CTRL + this field configures dsi_bridge fifo memory aux ctrl + 0 + 14 + read-write + + + + + RDN_ECO_CS + dsi_bridge rdn eco cs register + 0x74 + 0x20 + + + RDN_ECO_EN + rdn_eco_en + 0 + 1 + read-write + + + RDN_ECO_RESULT + rdn_eco_result + 1 + 1 + read-only + + + + + RDN_ECO_LOW + dsi_bridge rdn eco all low register + 0x78 + 0x20 + + + RDN_ECO_LOW + rdn_eco_low + 0 + 32 + read-write + + + + + RDN_ECO_HIGH + dsi_bridge rdn eco all high register + 0x7C + 0x20 + 0xFFFFFFFF + + + RDN_ECO_HIGH + rdn_eco_high + 0 + 32 + read-write + + + + + HOST_CTRL + dsi_bridge host control register + 0x80 + 0x20 + 0x00000001 + + + DSI_CFG_REF_CLK_EN + this bit configures the clk enable refclk and cfg_clk of dsi_host. 0: disable, 1: enable + 0 + 1 + read-write + + + + + MEM_CLK_CTRL + dsi_bridge mem force on control register + 0x84 + 0x20 + + + DSI_BRIDGE_MEM_CLK_FORCE_ON + this bit configures the clock force on of dsi_bridge fifo memory. 0: disable, 1: force on + 0 + 1 + read-write + + + DSI_MEM_CLK_FORCE_ON + this bit configures the clock force on of dpi fifo memory. 0: disable, 1: force on + 1 + 1 + read-write + + + + + DMA_FLOW_CTRL + dsi_bridge dma flow controller register + 0x88 + 0x20 + 0x00000011 + + + DSI_DMA_FLOW_CONTROLLER + this bit configures the flow controller, 0: dmac as flow controller, 1:dsi_bridge as flow controller + 0 + 1 + read-write + + + DMA_FLOW_MULTIBLK_NUM + this field configures the num of blocks when multi-blk is enable and dmac as flow controller + 4 + 4 + read-write + + + + + RAW_BUF_ALMOST_EMPTY_THRD + dsi_bridge buffer empty threshold register + 0x8C + 0x20 + 0x00000200 + + + DSI_RAW_BUF_ALMOST_EMPTY_THRD + this field configures the fifo almost empty threshold, is valid only when dmac as flow controller + 0 + 11 + read-write + + + + + YUV_CFG + dsi_bridge yuv format config register + 0x90 + 0x20 + + + PROTOCAL + this bit configures yuv protoocl, 0: bt.601, 1: bt.709 + 0 + 1 + read-write + + + YUV_PIX_ENDIAN + this bit configures yuv pixel endian, 0: y0u0y1v1y2u2y3v3, 1: y3u3y2v2y1u1y0v0 + 1 + 1 + read-write + + + YUV422_FORMAT + this field configures yuv422 store format, 0: yuyv, 1: yvyu, 2: uyvy, 3: vyuy + 2 + 2 + read-write + + + + + PHY_LP_LOOPBACK_CTRL + dsi phy lp_loopback test ctrl + 0x94 + 0x20 + + + PHY_LP_TXDATAESC_1 + txdataesc_1 ctrl when enable dsi phy lp_loopback_test + 0 + 8 + read-write + + + PHY_LP_TXREQUESTESC_1 + txrequestesc_1 ctrl when enable dsi phy lp_loopback_test + 8 + 1 + read-write + + + PHY_LP_TXVALIDESC_1 + txvalidesc_1 ctrl when enable dsi phy lp_loopback_test + 9 + 1 + read-write + + + PHY_LP_TXLPDTESC_1 + txlpdtesc_1 ctrl when enable dsi phy lp_loopback_test + 10 + 1 + read-write + + + PHY_LP_BASEDIR_1 + basedir_1 ctrl when enable dsi phy lp_loopback_test + 11 + 1 + read-write + + + PHY_LP_TXDATAESC_0 + txdataesc_0 ctrl when enable dsi phy lp_loopback_test + 16 + 8 + read-write + + + PHY_LP_TXREQUESTESC_0 + txrequestesc_0 ctrl when enable dsi phy lp_loopback_test + 24 + 1 + read-write + + + PHY_LP_TXVALIDESC_0 + txvalidesc_0 ctrl when enable dsi phy lp_loopback_test + 25 + 1 + read-write + + + PHY_LP_TXLPDTESC_0 + txlpdtesc_0 ctrl when enable dsi phy lp_loopback_test + 26 + 1 + read-write + + + PHY_LP_BASEDIR_0 + basedir_0 ctrl when enable dsi phy lp_loopback_test + 27 + 1 + read-write + + + PHY_LP_LOOPBACK_CHECK + dsi phy lp_loopback test start check + 28 + 1 + write-only + + + PHY_LP_LOOPBACK_CHECK_DONE + dsi phy lp_loopback test check done + 29 + 1 + read-only + + + PHY_LP_LOOPBACK_EN + dsi phy lp_loopback ctrl en + 30 + 1 + read-write + + + PHY_LP_LOOPBACK_OK + result of dsi phy lp_loopback test + 31 + 1 + read-only + + + + + PHY_HS_LOOPBACK_CTRL + dsi phy hp_loopback test ctrl + 0x98 + 0x20 + 0x00000200 + + + PHY_HS_TXDATAHS_1 + txdatahs_1 ctrl when enable dsi phy hs_loopback_test + 0 + 8 + read-write + + + PHY_HS_TXREQUESTDATAHS_1 + txrequestdatahs_1 ctrl when enable dsi phy hs_loopback_test + 8 + 1 + read-write + + + PHY_HS_BASEDIR_1 + basedir_1 ctrl when enable dsi phy hs_loopback_test + 9 + 1 + read-write + + + PHY_HS_TXDATAHS_0 + txdatahs_0 ctrl when enable dsi phy hs_loopback_test + 16 + 8 + read-write + + + PHY_HS_TXREQUESTDATAHS_0 + txrequestdatahs_0 ctrl when enable dsi phy hs_loopback_test + 24 + 1 + read-write + + + PHY_HS_BASEDIR_0 + basedir_0 ctrl when enable dsi phy hs_loopback_test + 25 + 1 + read-write + + + PHY_HS_TXREQUESTHSCLK + txrequesthsclk when enable dsi phy hs_loopback_test + 27 + 1 + read-write + + + PHY_HS_LOOPBACK_CHECK + dsi phy hs_loopback test start check + 28 + 1 + write-only + + + PHY_HS_LOOPBACK_CHECK_DONE + dsi phy hs_loopback test check done + 29 + 1 + read-only + + + PHY_HS_LOOPBACK_EN + dsi phy hs_loopback ctrl en + 30 + 1 + read-write + + + PHY_HS_LOOPBACK_OK + result of dsi phy hs_loopback test + 31 + 1 + read-only + + + + + PHY_LOOPBACK_CNT + loopback test cnt + 0x9C + 0x20 + 0x00400040 + + + PHY_HS_CHECK_CNT_TH + hs_loopback test check cnt + 0 + 8 + read-write + + + PHY_LP_CHECK_CNT_TH + lp_loopback test check cnt + 16 + 8 + read-write + + + + + + + MIPI_DSI_HOST + MIPI Display Interface Host + DSI_HOST + 0x500A0000 + + 0x0 + 0x128 + registers + + + DSI + 88 + + + + VERSION + NA + 0x0 + 0x20 + 0x3134312A + + + VERSION + NA + 0 + 32 + read-only + + + + + PWR_UP + NA + 0x4 + 0x20 + + + SHUTDOWNZ + NA + 0 + 1 + read-write + + + + + CLKMGR_CFG + NA + 0x8 + 0x20 + + + TX_ESC_CLK_DIVISION + NA + 0 + 8 + read-write + + + TO_CLK_DIVISION + NA + 8 + 8 + read-write + + + + + DPI_VCID + NA + 0xC + 0x20 + + + DPI_VCID + NA + 0 + 2 + read-write + + + + + DPI_COLOR_CODING + NA + 0x10 + 0x20 + + + DPI_COLOR_CODING + NA + 0 + 4 + read-write + + + LOOSELY18_EN + NA + 8 + 1 + read-write + + + + + DPI_CFG_POL + NA + 0x14 + 0x20 + + + DATAEN_ACTIVE_LOW + NA + 0 + 1 + read-write + + + VSYNC_ACTIVE_LOW + NA + 1 + 1 + read-write + + + HSYNC_ACTIVE_LOW + NA + 2 + 1 + read-write + + + SHUTD_ACTIVE_LOW + NA + 3 + 1 + read-write + + + COLORM_ACTIVE_LOW + NA + 4 + 1 + read-write + + + + + DPI_LP_CMD_TIM + NA + 0x18 + 0x20 + + + INVACT_LPCMD_TIME + NA + 0 + 8 + read-write + + + OUTVACT_LPCMD_TIME + NA + 16 + 8 + read-write + + + + + DBI_VCID + NA + 0x1C + 0x20 + + + DBI_VCID + NA + 0 + 2 + read-write + + + + + DBI_CFG + NA + 0x20 + 0x20 + + + IN_DBI_CONF + NA + 0 + 4 + read-write + + + OUT_DBI_CONF + NA + 8 + 4 + read-write + + + LUT_SIZE_CONF + NA + 16 + 2 + read-write + + + + + DBI_PARTITIONING_EN + NA + 0x24 + 0x20 + + + PARTITIONING_EN + NA + 0 + 1 + read-write + + + + + DBI_CMDSIZE + NA + 0x28 + 0x20 + + + WR_CMD_SIZE + NA + 0 + 16 + read-write + + + ALLOWED_CMD_SIZE + NA + 16 + 16 + read-write + + + + + PCKHDL_CFG + NA + 0x2C + 0x20 + + + EOTP_TX_EN + NA + 0 + 1 + read-write + + + EOTP_RX_EN + NA + 1 + 1 + read-write + + + BTA_EN + NA + 2 + 1 + read-write + + + ECC_RX_EN + NA + 3 + 1 + read-write + + + CRC_RX_EN + NA + 4 + 1 + read-write + + + EOTP_TX_LP_EN + NA + 5 + 1 + read-write + + + + + GEN_VCID + NA + 0x30 + 0x20 + + + RX + NA + 0 + 2 + read-write + + + TEAR_AUTO + NA + 8 + 2 + read-write + + + TX_AUTO + NA + 16 + 2 + read-write + + + + + MODE_CFG + NA + 0x34 + 0x20 + 0x00000001 + + + CMD_VIDEO_MODE + NA + 0 + 1 + read-write + + + + + VID_MODE_CFG + NA + 0x38 + 0x20 + + + VID_MODE_TYPE + NA + 0 + 2 + read-write + + + LP_VSA_EN + NA + 8 + 1 + read-write + + + LP_VBP_EN + NA + 9 + 1 + read-write + + + LP_VFP_EN + NA + 10 + 1 + read-write + + + LP_VACT_EN + NA + 11 + 1 + read-write + + + LP_HBP_EN + NA + 12 + 1 + read-write + + + LP_HFP_EN + NA + 13 + 1 + read-write + + + FRAME_BTA_ACK_EN + NA + 14 + 1 + read-write + + + LP_CMD_EN + NA + 15 + 1 + read-write + + + VPG_EN + NA + 16 + 1 + read-write + + + VPG_MODE + NA + 20 + 1 + read-write + + + VPG_ORIENTATION + NA + 24 + 1 + read-write + + + + + VID_PKT_SIZE + NA + 0x3C + 0x20 + + + VID_PKT_SIZE + NA + 0 + 14 + read-write + + + + + VID_NUM_CHUNKS + NA + 0x40 + 0x20 + + + VID_NUM_CHUNKS + NA + 0 + 13 + read-write + + + + + VID_NULL_SIZE + NA + 0x44 + 0x20 + + + VID_NULL_SIZE + NA + 0 + 13 + read-write + + + + + VID_HSA_TIME + NA + 0x48 + 0x20 + + + VID_HSA_TIME + NA + 0 + 12 + read-write + + + + + VID_HBP_TIME + NA + 0x4C + 0x20 + + + VID_HBP_TIME + NA + 0 + 12 + read-write + + + + + VID_HLINE_TIME + NA + 0x50 + 0x20 + + + VID_HLINE_TIME + NA + 0 + 15 + read-write + + + + + VID_VSA_LINES + NA + 0x54 + 0x20 + + + VSA_LINES + NA + 0 + 10 + read-write + + + + + VID_VBP_LINES + NA + 0x58 + 0x20 + + + VBP_LINES + NA + 0 + 10 + read-write + + + + + VID_VFP_LINES + NA + 0x5C + 0x20 + + + VFP_LINES + NA + 0 + 10 + read-write + + + + + VID_VACTIVE_LINES + NA + 0x60 + 0x20 + + + V_ACTIVE_LINES + NA + 0 + 14 + read-write + + + + + EDPI_CMD_SIZE + NA + 0x64 + 0x20 + + + EDPI_ALLOWED_CMD_SIZE + NA + 0 + 16 + read-write + + + + + CMD_MODE_CFG + NA + 0x68 + 0x20 + + + TEAR_FX_EN + NA + 0 + 1 + read-write + + + ACK_RQST_EN + NA + 1 + 1 + read-write + + + GEN_SW_0P_TX + NA + 8 + 1 + read-write + + + GEN_SW_1P_TX + NA + 9 + 1 + read-write + + + GEN_SW_2P_TX + NA + 10 + 1 + read-write + + + GEN_SR_0P_TX + NA + 11 + 1 + read-write + + + GEN_SR_1P_TX + NA + 12 + 1 + read-write + + + GEN_SR_2P_TX + NA + 13 + 1 + read-write + + + GEN_LW_TX + NA + 14 + 1 + read-write + + + DCS_SW_0P_TX + NA + 16 + 1 + read-write + + + DCS_SW_1P_TX + NA + 17 + 1 + read-write + + + DCS_SR_0P_TX + NA + 18 + 1 + read-write + + + DCS_LW_TX + NA + 19 + 1 + read-write + + + MAX_RD_PKT_SIZE + NA + 24 + 1 + read-write + + + + + GEN_HDR + NA + 0x6C + 0x20 + + + GEN_DT + NA + 0 + 6 + read-write + + + GEN_VC + NA + 6 + 2 + read-write + + + GEN_WC_LSBYTE + NA + 8 + 8 + read-write + + + GEN_WC_MSBYTE + NA + 16 + 8 + read-write + + + + + GEN_PLD_DATA + NA + 0x70 + 0x20 + + + GEN_PLD_B1 + NA + 0 + 8 + read-write + + + GEN_PLD_B2 + NA + 8 + 8 + read-write + + + GEN_PLD_B3 + NA + 16 + 8 + read-write + + + GEN_PLD_B4 + NA + 24 + 8 + read-write + + + + + CMD_PKT_STATUS + NA + 0x74 + 0x20 + 0x00050015 + + + GEN_CMD_EMPTY + NA + 0 + 1 + read-only + + + GEN_CMD_FULL + NA + 1 + 1 + read-only + + + GEN_PLD_W_EMPTY + NA + 2 + 1 + read-only + + + GEN_PLD_W_FULL + NA + 3 + 1 + read-only + + + GEN_PLD_R_EMPTY + NA + 4 + 1 + read-only + + + GEN_PLD_R_FULL + NA + 5 + 1 + read-only + + + GEN_RD_CMD_BUSY + NA + 6 + 1 + read-only + + + GEN_BUFF_CMD_EMPTY + NA + 16 + 1 + read-only + + + GEN_BUFF_CMD_FULL + NA + 17 + 1 + read-only + + + GEN_BUFF_PLD_EMPTY + NA + 18 + 1 + read-only + + + GEN_BUFF_PLD_FULL + NA + 19 + 1 + read-only + + + + + TO_CNT_CFG + NA + 0x78 + 0x20 + + + LPRX_TO_CNT + NA + 0 + 16 + read-write + + + HSTX_TO_CNT + NA + 16 + 16 + read-write + + + + + HS_RD_TO_CNT + NA + 0x7C + 0x20 + + + HS_RD_TO_CNT + NA + 0 + 16 + read-write + + + + + LP_RD_TO_CNT + NA + 0x80 + 0x20 + + + LP_RD_TO_CNT + NA + 0 + 16 + read-write + + + + + HS_WR_TO_CNT + NA + 0x84 + 0x20 + + + HS_WR_TO_CNT + NA + 0 + 16 + read-write + + + + + LP_WR_TO_CNT + NA + 0x88 + 0x20 + + + LP_WR_TO_CNT + NA + 0 + 16 + read-write + + + + + BTA_TO_CNT + NA + 0x8C + 0x20 + + + BTA_TO_CNT + NA + 0 + 16 + read-write + + + + + SDF_3D + NA + 0x90 + 0x20 + + + MODE_3D + NA + 0 + 2 + read-write + + + FORMAT_3D + NA + 2 + 2 + read-write + + + SECOND_VSYNC + NA + 4 + 1 + read-write + + + RIGHT_FIRST + NA + 5 + 1 + read-write + + + SEND_3D_CFG + NA + 16 + 1 + read-write + + + + + LPCLK_CTRL + NA + 0x94 + 0x20 + + + PHY_TXREQUESTCLKHS + NA + 0 + 1 + read-write + + + AUTO_CLKLANE_CTRL + NA + 1 + 1 + read-write + + + + + PHY_TMR_LPCLK_CFG + NA + 0x98 + 0x20 + + + PHY_CLKLP2HS_TIME + NA + 0 + 10 + read-write + + + PHY_CLKHS2LP_TIME + NA + 16 + 10 + read-write + + + + + PHY_TMR_CFG + NA + 0x9C + 0x20 + + + PHY_LP2HS_TIME + NA + 0 + 10 + read-write + + + PHY_HS2LP_TIME + NA + 16 + 10 + read-write + + + + + PHY_RSTZ + NA + 0xA0 + 0x20 + + + PHY_SHUTDOWNZ + NA + 0 + 1 + read-write + + + PHY_RSTZ + NA + 1 + 1 + read-write + + + PHY_ENABLECLK + NA + 2 + 1 + read-write + + + PHY_FORCEPLL + NA + 3 + 1 + read-write + + + + + PHY_IF_CFG + NA + 0xA4 + 0x20 + 0x00000001 + + + N_LANES + NA + 0 + 2 + read-write + + + PHY_STOP_WAIT_TIME + NA + 8 + 8 + read-write + + + + + PHY_ULPS_CTRL + NA + 0xA8 + 0x20 + + + PHY_TXREQULPSCLK + NA + 0 + 1 + read-write + + + PHY_TXEXITULPSCLK + NA + 1 + 1 + read-write + + + PHY_TXREQULPSLAN + NA + 2 + 1 + read-write + + + PHY_TXEXITULPSLAN + NA + 3 + 1 + read-write + + + + + PHY_TX_TRIGGERS + NA + 0xAC + 0x20 + + + PHY_TX_TRIGGERS + NA + 0 + 4 + read-write + + + + + PHY_STATUS + NA + 0xB0 + 0x20 + 0x00000140 + + + PHY_LOCK + NA + 0 + 1 + read-only + + + PHY_DIRECTION + NA + 1 + 1 + read-only + + + PHY_STOPSTATECLKLANE + NA + 2 + 1 + read-only + + + PHY_ULPSACTIVENOTCLK + NA + 3 + 1 + read-only + + + PHY_STOPSTATE0LANE + NA + 4 + 1 + read-only + + + PHY_ULPSACTIVENOT0LANE + NA + 5 + 1 + read-only + + + PHY_RXULPSESC0LANE + NA + 6 + 1 + read-only + + + PHY_STOPSTATE1LANE + NA + 7 + 1 + read-only + + + PHY_ULPSACTIVENOT1LANE + NA + 8 + 1 + read-only + + + + + PHY_TST_CTRL0 + NA + 0xB4 + 0x20 + 0x00000001 + + + PHY_TESTCLR + NA + 0 + 1 + read-write + + + PHY_TESTCLK + NA + 1 + 1 + read-write + + + + + PHY_TST_CTRL1 + NA + 0xB8 + 0x20 + + + PHY_TESTDIN + NA + 0 + 8 + read-write + + + PHT_TESTDOUT + NA + 8 + 8 + read-only + + + PHY_TESTEN + NA + 16 + 1 + read-write + + + + + INT_ST0 + NA + 0xBC + 0x20 + + + ACK_WITH_ERR_0 + NA + 0 + 1 + read-only + + + ACK_WITH_ERR_1 + NA + 1 + 1 + read-only + + + ACK_WITH_ERR_2 + NA + 2 + 1 + read-only + + + ACK_WITH_ERR_3 + NA + 3 + 1 + read-only + + + ACK_WITH_ERR_4 + NA + 4 + 1 + read-only + + + ACK_WITH_ERR_5 + NA + 5 + 1 + read-only + + + ACK_WITH_ERR_6 + NA + 6 + 1 + read-only + + + ACK_WITH_ERR_7 + NA + 7 + 1 + read-only + + + ACK_WITH_ERR_8 + NA + 8 + 1 + read-only + + + ACK_WITH_ERR_9 + NA + 9 + 1 + read-only + + + ACK_WITH_ERR_10 + NA + 10 + 1 + read-only + + + ACK_WITH_ERR_11 + NA + 11 + 1 + read-only + + + ACK_WITH_ERR_12 + NA + 12 + 1 + read-only + + + ACK_WITH_ERR_13 + NA + 13 + 1 + read-only + + + ACK_WITH_ERR_14 + NA + 14 + 1 + read-only + + + ACK_WITH_ERR_15 + NA + 15 + 1 + read-only + + + DPHY_ERRORS_0 + NA + 16 + 1 + read-only + + + DPHY_ERRORS_1 + NA + 17 + 1 + read-only + + + DPHY_ERRORS_2 + NA + 18 + 1 + read-only + + + DPHY_ERRORS_3 + NA + 19 + 1 + read-only + + + DPHY_ERRORS_4 + NA + 20 + 1 + read-only + + + + + INT_ST1 + NA + 0xC0 + 0x20 + + + TO_HS_TX + NA + 0 + 1 + read-only + + + TO_LP_RX + NA + 1 + 1 + read-only + + + ECC_SINGLE_ERR + NA + 2 + 1 + read-only + + + ECC_MILTI_ERR + NA + 3 + 1 + read-only + + + CRC_ERR + NA + 4 + 1 + read-only + + + PKT_SIZE_ERR + NA + 5 + 1 + read-only + + + EOPT_ERR + NA + 6 + 1 + read-only + + + DPI_PLD_WR_ERR + NA + 7 + 1 + read-only + + + GEN_CMD_WR_ERR + NA + 8 + 1 + read-only + + + GEN_PLD_WR_ERR + NA + 9 + 1 + read-only + + + GEN_PLD_SEND_ERR + NA + 10 + 1 + read-only + + + GEN_PLD_RD_ERR + NA + 11 + 1 + read-only + + + GEN_PLD_RECEV_ERR + NA + 12 + 1 + read-only + + + DPI_BUFF_PLD_UNDER + NA + 19 + 1 + read-only + + + + + INT_MSK0 + NA + 0xC4 + 0x20 + + + MASK_ACK_WITH_ERR_0 + NA + 0 + 1 + read-write + + + MASK_ACK_WITH_ERR_1 + NA + 1 + 1 + read-write + + + MASK_ACK_WITH_ERR_2 + NA + 2 + 1 + read-write + + + MASK_ACK_WITH_ERR_3 + NA + 3 + 1 + read-write + + + MASK_ACK_WITH_ERR_4 + NA + 4 + 1 + read-write + + + MASK_ACK_WITH_ERR_5 + NA + 5 + 1 + read-write + + + MASK_ACK_WITH_ERR_6 + NA + 6 + 1 + read-write + + + MASK_ACK_WITH_ERR_7 + NA + 7 + 1 + read-write + + + MASK_ACK_WITH_ERR_8 + NA + 8 + 1 + read-write + + + MASK_ACK_WITH_ERR_9 + NA + 9 + 1 + read-write + + + MASK_ACK_WITH_ERR_10 + NA + 10 + 1 + read-write + + + MASK_ACK_WITH_ERR_11 + NA + 11 + 1 + read-write + + + MASK_ACK_WITH_ERR_12 + NA + 12 + 1 + read-write + + + MASK_ACK_WITH_ERR_13 + NA + 13 + 1 + read-write + + + MASK_ACK_WITH_ERR_14 + NA + 14 + 1 + read-write + + + MASK_ACK_WITH_ERR_15 + NA + 15 + 1 + read-write + + + MASK_DPHY_ERRORS_0 + NA + 16 + 1 + read-write + + + MASK_DPHY_ERRORS_1 + NA + 17 + 1 + read-write + + + MASK_DPHY_ERRORS_2 + NA + 18 + 1 + read-write + + + MASK_DPHY_ERRORS_3 + NA + 19 + 1 + read-write + + + MASK_DPHY_ERRORS_4 + NA + 20 + 1 + read-write + + + + + INT_MSK1 + NA + 0xC8 + 0x20 + + + MASK_TO_HS_TX + NA + 0 + 1 + read-write + + + MASK_TO_LP_RX + NA + 1 + 1 + read-write + + + MASK_ECC_SINGLE_ERR + NA + 2 + 1 + read-write + + + MASK_ECC_MILTI_ERR + NA + 3 + 1 + read-write + + + MASK_CRC_ERR + NA + 4 + 1 + read-write + + + MASK_PKT_SIZE_ERR + NA + 5 + 1 + read-write + + + MASK_EOPT_ERR + NA + 6 + 1 + read-write + + + MASK_DPI_PLD_WR_ERR + NA + 7 + 1 + read-write + + + MASK_GEN_CMD_WR_ERR + NA + 8 + 1 + read-write + + + MASK_GEN_PLD_WR_ERR + NA + 9 + 1 + read-write + + + MASK_GEN_PLD_SEND_ERR + NA + 10 + 1 + read-write + + + MASK_GEN_PLD_RD_ERR + NA + 11 + 1 + read-write + + + MASK_GEN_PLD_RECEV_ERR + NA + 12 + 1 + read-write + + + MASK_DPI_BUFF_PLD_UNDER + NA + 19 + 1 + read-write + + + + + PHY_CAL + NA + 0xCC + 0x20 + + + TXSKEWCALHS + NA + 0 + 1 + read-write + + + + + INT_FORCE0 + NA + 0xD8 + 0x20 + + + FORCE_ACK_WITH_ERR_0 + NA + 0 + 1 + read-write + + + FORCE_ACK_WITH_ERR_1 + NA + 1 + 1 + read-write + + + FORCE_ACK_WITH_ERR_2 + NA + 2 + 1 + read-write + + + FORCE_ACK_WITH_ERR_3 + NA + 3 + 1 + read-write + + + FORCE_ACK_WITH_ERR_4 + NA + 4 + 1 + read-write + + + FORCE_ACK_WITH_ERR_5 + NA + 5 + 1 + read-write + + + FORCE_ACK_WITH_ERR_6 + NA + 6 + 1 + read-write + + + FORCE_ACK_WITH_ERR_7 + NA + 7 + 1 + read-write + + + FORCE_ACK_WITH_ERR_8 + NA + 8 + 1 + read-write + + + FORCE_ACK_WITH_ERR_9 + NA + 9 + 1 + read-write + + + FORCE_ACK_WITH_ERR_10 + NA + 10 + 1 + read-write + + + FORCE_ACK_WITH_ERR_11 + NA + 11 + 1 + read-write + + + FORCE_ACK_WITH_ERR_12 + NA + 12 + 1 + read-write + + + FORCE_ACK_WITH_ERR_13 + NA + 13 + 1 + read-write + + + FORCE_ACK_WITH_ERR_14 + NA + 14 + 1 + read-write + + + FORCE_ACK_WITH_ERR_15 + NA + 15 + 1 + read-write + + + FORCE_DPHY_ERRORS_0 + NA + 16 + 1 + read-write + + + FORCE_DPHY_ERRORS_1 + NA + 17 + 1 + read-write + + + FORCE_DPHY_ERRORS_2 + NA + 18 + 1 + read-write + + + FORCE_DPHY_ERRORS_3 + NA + 19 + 1 + read-write + + + FORCE_DPHY_ERRORS_4 + NA + 20 + 1 + read-write + + + + + INT_FORCE1 + NA + 0xDC + 0x20 + + + FORCE_TO_HS_TX + NA + 0 + 1 + read-write + + + FORCE_TO_LP_RX + NA + 1 + 1 + read-write + + + FORCE_ECC_SINGLE_ERR + NA + 2 + 1 + read-write + + + FORCE_ECC_MILTI_ERR + NA + 3 + 1 + read-write + + + FORCE_CRC_ERR + NA + 4 + 1 + read-write + + + FORCE_PKT_SIZE_ERR + NA + 5 + 1 + read-write + + + FORCE_EOPT_ERR + NA + 6 + 1 + read-write + + + FORCE_DPI_PLD_WR_ERR + NA + 7 + 1 + read-write + + + FORCE_GEN_CMD_WR_ERR + NA + 8 + 1 + read-write + + + FORCE_GEN_PLD_WR_ERR + NA + 9 + 1 + read-write + + + FORCE_GEN_PLD_SEND_ERR + NA + 10 + 1 + read-write + + + FORCE_GEN_PLD_RD_ERR + NA + 11 + 1 + read-write + + + FORCE_GEN_PLD_RECEV_ERR + NA + 12 + 1 + read-write + + + FORCE_DPI_BUFF_PLD_UNDER + NA + 19 + 1 + read-write + + + + + DSC_PARAMETER + NA + 0xF0 + 0x20 + + + COMPRESSION_MODE + NA + 0 + 1 + read-write + + + COMPRESS_ALGO + NA + 8 + 2 + read-write + + + PPS_SEL + NA + 16 + 2 + read-write + + + + + PHY_TMR_RD_CFG + NA + 0xF4 + 0x20 + + + MAX_RD_TIME + NA + 0 + 15 + read-write + + + + + VID_SHADOW_CTRL + NA + 0x100 + 0x20 + + + VID_SHADOW_EN + NA + 0 + 1 + read-write + + + VID_SHADOW_REQ + NA + 8 + 1 + read-write + + + VID_SHADOW_PIN_REQ + NA + 16 + 1 + read-write + + + + + DPI_VCID_ACT + NA + 0x10C + 0x20 + + + DPI_VCID_ACT + NA + 0 + 2 + read-only + + + + + DPI_COLOR_CODING_ACT + NA + 0x110 + 0x20 + + + DPI_COLOR_CODING_ACT + NA + 0 + 4 + read-only + + + LOOSELY18_EN_ACT + NA + 8 + 1 + read-only + + + + + DPI_LP_CMD_TIM_ACT + NA + 0x118 + 0x20 + + + INVACT_LPCMD_TIME_ACT + NA + 0 + 8 + read-only + + + OUTVACT_LPCMD_TIME_ACT + NA + 16 + 8 + read-only + + + + + EDPI_TE_HW_CFG + NA + 0x11C + 0x20 + + + HW_TEAR_EFFECT_ON + NA + 0 + 1 + read-write + + + HW_TEAR_EFFECT_GEN + NA + 1 + 1 + read-write + + + HW_SET_SCAN_LINE + NA + 4 + 1 + read-write + + + SCAN_LINE_PARAMETER + NA + 16 + 16 + read-write + + + + + VID_MODE_CFG_ACT + NA + 0x138 + 0x20 + + + VID_MODE_TYPE_ACT + NA + 0 + 2 + read-only + + + LP_VSA_EN_ACT + NA + 2 + 1 + read-only + + + LP_VBP_EN_ACT + NA + 3 + 1 + read-only + + + LP_VFP_EN_ACT + NA + 4 + 1 + read-only + + + LP_VACT_EN_ACT + NA + 5 + 1 + read-only + + + LP_HBP_EN_ACT + NA + 6 + 1 + read-only + + + LP_HFP_EN_ACT + NA + 7 + 1 + read-only + + + FRAME_BTA_ACK_EN_ACT + NA + 8 + 1 + read-only + + + LP_CMD_EN_ACT + NA + 9 + 1 + read-only + + + + + VID_PKT_SIZE_ACT + NA + 0x13C + 0x20 + + + VID_PKT_SIZE_ACT + NA + 0 + 14 + read-only + + + + + VID_NUM_CHUNKS_ACT + NA + 0x140 + 0x20 + + + VID_NUM_CHUNKS_ACT + NA + 0 + 13 + read-only + + + + + VID_NULL_SIZE_ACT + NA + 0x144 + 0x20 + + + VID_NULL_SIZE_ACT + NA + 0 + 13 + read-only + + + + + VID_HSA_TIME_ACT + NA + 0x148 + 0x20 + + + VID_HSA_TIME_ACT + NA + 0 + 12 + read-only + + + + + VID_HBP_TIME_ACT + NA + 0x14C + 0x20 + + + VID_HBP_TIME_ACT + NA + 0 + 12 + read-only + + + + + VID_HLINE_TIME_ACT + NA + 0x150 + 0x20 + + + VID_HLINE_TIME_ACT + NA + 0 + 15 + read-only + + + + + VID_VSA_LINES_ACT + NA + 0x154 + 0x20 + + + VSA_LINES_ACT + NA + 0 + 10 + read-only + + + + + VID_VBP_LINES_ACT + NA + 0x158 + 0x20 + + + VBP_LINES_ACT + NA + 0 + 10 + read-only + + + + + VID_VFP_LINES_ACT + NA + 0x15C + 0x20 + + + VFP_LINES_ACT + NA + 0 + 10 + read-only + + + + + VID_VACTIVE_LINES_ACT + NA + 0x160 + 0x20 + + + V_ACTIVE_LINES_ACT + NA + 0 + 14 + read-only + + + + + VID_PKT_STATUS + NA + 0x168 + 0x20 + 0x00010005 + + + DPI_CMD_W_EMPTY + NA + 0 + 1 + read-only + + + DPI_CMD_W_FULL + NA + 1 + 1 + read-only + + + DPI_PLD_W_EMPTY + NA + 2 + 1 + read-only + + + DPI_PLD_W_FULL + NA + 3 + 1 + read-only + + + DPI_BUFF_PLD_EMPTY + NA + 16 + 1 + read-only + + + DPI_BUFF_PLD_FULL + NA + 17 + 1 + read-only + + + + + SDF_3D_ACT + NA + 0x190 + 0x20 + + + MODE_3D_ACT + NA + 0 + 2 + read-only + + + FORMAT_3D_ACT + NA + 2 + 2 + read-only + + + SECOND_VSYNC_ACT + NA + 4 + 1 + read-only + + + RIGHT_FIRST_ACT + NA + 5 + 1 + read-only + + + SEND_3D_CFG_ACT + NA + 16 + 1 + read-only + + + + + + + ECC + ECC (ECC Hardware Accelerator) + ECC + 0x50093000 + + 0x0 + 0x78 + registers + + + ECC + 71 + + + + MULT_INT_RAW + ECC interrupt raw register, valid in level. + 0xC + 0x20 + + + CALC_DONE_INT_RAW + The raw interrupt status bit for the ecc_calc_done_int interrupt + 0 + 1 + read-only + + + + + MULT_INT_ST + ECC interrupt status register. + 0x10 + 0x20 + + + CALC_DONE_INT_ST + The masked interrupt status bit for the ecc_calc_done_int interrupt + 0 + 1 + read-only + + + + + MULT_INT_ENA + ECC interrupt enable register. + 0x14 + 0x20 + + + CALC_DONE_INT_ENA + The interrupt enable bit for the ecc_calc_done_int interrupt + 0 + 1 + read-write + + + + + MULT_INT_CLR + ECC interrupt clear register. + 0x18 + 0x20 + + + CALC_DONE_INT_CLR + Set this bit to clear the ecc_calc_done_int interrupt + 0 + 1 + write-only + + + + + MULT_CONF + ECC configure register + 0x1C + 0x20 + + + START + Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after the caculatrion is done. + 0 + 1 + read-write + + + RESET + Write 1 to reset ECC Accelerator. + 1 + 1 + write-only + + + KEY_LENGTH + The key length mode bit of ECC Accelerator. 0: P-192. 1: P-256. + 2 + 1 + read-write + + + MOD_BASE + The mod base of mod operation, only valid in work_mode 8-11. 0: n(order of curve). 1: p(mod base of curve) + 3 + 1 + read-write + + + WORK_MODE + The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: Reserved. 2: Point verification mode. 3: Point Verif+mult mode. 4: Jacobian Point Mult Mode. 5: Point Add Mode. 6: Jacobian Point Verification Mode. 7: Point Verif + Jacobian Mult Mode. 8: mod addition. 9. mod substraction. 10: mod multiplication. 11: mod division. + 4 + 4 + read-write + + + SECURITY_MODE + Reserved + 8 + 1 + read-write + + + VERIFICATION_RESULT + The verification result bit of ECC Accelerator, only valid when calculation is done. + 29 + 1 + read-only + + + CLK_EN + Write 1 to force on register clock gate. + 30 + 1 + read-write + + + MEM_CLOCK_GATE_FORCE_ON + ECC memory clock gate force on register + 31 + 1 + read-write + + + + + MULT_DATE + Version control register + 0xFC + 0x20 + 0x02305040 + + + DATE + ECC mult version control register + 0 + 28 + read-write + + + + + 8 + 0x4 + K_MEM[%s] + The memory that stores k. + 0x100 + 0x20 + + + 8 + 0x4 + PX_MEM[%s] + The memory that stores Px. + 0x120 + 0x20 + + + 8 + 0x4 + PY_MEM[%s] + The memory that stores Py. + 0x140 + 0x20 + + + + + ECDSA + ECDSA (Elliptic Curve Digital Signature Algorithm) Accelerator + ECDSA + 0x50096000 + + 0x0 + 0xF8 + registers + + + + CONF + ECDSA configure register + 0x4 + 0x20 + + + WORK_MODE + The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature Generate Mode. 2: Export Public Key Mode. 3: invalid. + 0 + 2 + read-write + + + ECC_CURVE + The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256. + 2 + 1 + read-write + + + SOFTWARE_SET_K + The source of k select bit. 0: k is automatically generated by hardware. 1: k is written by software. + 3 + 1 + read-write + + + SOFTWARE_SET_Z + The source of z select bit. 0: z is generated from SHA result. 1: z is written by software. + 4 + 1 + read-write + + + DETERMINISTIC_K + The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by deterministic derivation algorithm. + 5 + 1 + read-write + + + DETERMINISTIC_LOOP + The (loop number - 1) value in the deterministic derivation algorithm to derive k. + 6 + 16 + read-write + + + + + CLK + ECDSA clock gate register + 0x8 + 0x20 + + + GATE_FORCE_ON + Write 1 to force on register clock gate. + 0 + 1 + read-write + + + + + INT_RAW + ECDSA interrupt raw register, valid in level. + 0xC + 0x20 + + + CALC_DONE_INT_RAW + The raw interrupt status bit for the ecdsa_calc_done_int interrupt + 0 + 1 + read-only + + + SHA_RELEASE_INT_RAW + The raw interrupt status bit for the ecdsa_sha_release_int interrupt + 1 + 1 + read-only + + + + + INT_ST + ECDSA interrupt status register. + 0x10 + 0x20 + + + CALC_DONE_INT_ST + The masked interrupt status bit for the ecdsa_calc_done_int interrupt + 0 + 1 + read-only + + + SHA_RELEASE_INT_ST + The masked interrupt status bit for the ecdsa_sha_release_int interrupt + 1 + 1 + read-only + + + + + INT_ENA + ECDSA interrupt enable register. + 0x14 + 0x20 + + + CALC_DONE_INT_ENA + The interrupt enable bit for the ecdsa_calc_done_int interrupt + 0 + 1 + read-write + + + SHA_RELEASE_INT_ENA + The interrupt enable bit for the ecdsa_sha_release_int interrupt + 1 + 1 + read-write + + + + + INT_CLR + ECDSA interrupt clear register. + 0x18 + 0x20 + + + CALC_DONE_INT_CLR + Set this bit to clear the ecdsa_calc_done_int interrupt + 0 + 1 + write-only + + + SHA_RELEASE_INT_CLR + Set this bit to clear the ecdsa_sha_release_int interrupt + 1 + 1 + write-only + + + + + START + ECDSA start register + 0x1C + 0x20 + + + START + Write 1 to start caculation of ECDSA Accelerator. This bit will be self-cleared after configuration. + 0 + 1 + write-only + + + LOAD_DONE + Write 1 to input load done signal of ECDSA Accelerator. This bit will be self-cleared after configuration. + 1 + 1 + write-only + + + GET_DONE + Write 1 to input get done signal of ECDSA Accelerator. This bit will be self-cleared after configuration. + 2 + 1 + write-only + + + + + STATE + ECDSA status register + 0x20 + 0x20 + + + BUSY + The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY state. + 0 + 2 + read-only + + + + + RESULT + ECDSA result register + 0x24 + 0x20 + + + OPERATION_RESULT + The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is done. + 0 + 1 + read-only + + + K_VALUE_WARNING + The k value warning bit of ECDSA Accelerator, valid when k value is bigger than the curve order, then actually taken k = k mod n. + 1 + 1 + read-only + + + + + DATE + Version control register + 0xFC + 0x20 + 0x02304070 + + + DATE + ECDSA version control register + 0 + 28 + read-write + + + + + SHA_MODE + ECDSA control SHA register + 0x200 + 0x20 + + + SHA_MODE + The work mode bits of SHA Calculator in ECDSA Accelerator. 1: SHA-224. 2: SHA-256. Others: invalid. + 0 + 3 + read-write + + + + + SHA_START + ECDSA control SHA register + 0x210 + 0x20 + + + SHA_START + Write 1 to start the first caculation of SHA Calculator in ECDSA Accelerator. This bit will be self-cleared after configuration. + 0 + 1 + write-only + + + + + SHA_CONTINUE + ECDSA control SHA register + 0x214 + 0x20 + + + SHA_CONTINUE + Write 1 to start the latter caculation of SHA Calculator in ECDSA Accelerator. This bit will be self-cleared after configuration. + 0 + 1 + write-only + + + + + SHA_BUSY + ECDSA status register + 0x218 + 0x20 + + + SHA_BUSY + The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in calculation. 0: SHA is idle. + 0 + 1 + read-only + + + + + 8 + 0x4 + MESSAGE_MEM[%s] + The memory that stores message. + 0x280 + 0x20 + + + 8 + 0x4 + R_MEM[%s] + The memory that stores r. + 0xA00 + 0x20 + + + 8 + 0x4 + S_MEM[%s] + The memory that stores s. + 0xA20 + 0x20 + + + 8 + 0x4 + Z_MEM[%s] + The memory that stores software written z. + 0xA40 + 0x20 + + + 8 + 0x4 + QAX_MEM[%s] + The memory that stores x coordinates of QA or software written k. + 0xA60 + 0x20 + + + 8 + 0x4 + QAY_MEM[%s] + The memory that stores y coordinates of QA. + 0xA80 + 0x20 + + + + + EFUSE + eFuse Controller + EFUSE + 0x5012D000 + + 0x0 + 0x3D8 + registers + + + + PGM_DATA0 + Register 0 that stores data to be programmed. + 0x0 + 0x20 + + + PGM_DATA_0 + Configures the 0th 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA1 + Register 1 that stores data to be programmed. + 0x4 + 0x20 + + + PGM_DATA_1 + Configures the 1st 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA2 + Register 2 that stores data to be programmed. + 0x8 + 0x20 + + + PGM_DATA_2 + Configures the 2nd 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA3 + Register 3 that stores data to be programmed. + 0xC + 0x20 + + + PGM_DATA_3 + Configures the 3rd 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA4 + Register 4 that stores data to be programmed. + 0x10 + 0x20 + + + PGM_DATA_4 + Configures the 4th 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA5 + Register 5 that stores data to be programmed. + 0x14 + 0x20 + + + PGM_DATA_5 + Configures the 5th 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA6 + Register 6 that stores data to be programmed. + 0x18 + 0x20 + + + PGM_DATA_6 + Configures the 6th 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA7 + Register 7 that stores data to be programmed. + 0x1C + 0x20 + + + PGM_DATA_7 + Configures the 7th 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_CHECK_VALUE0 + Register 0 that stores the RS code to be programmed. + 0x20 + 0x20 + + + PGM_RS_DATA_0 + Configures the 0th 32-bit RS code to be programmed. + 0 + 32 + read-write + + + + + PGM_CHECK_VALUE1 + Register 1 that stores the RS code to be programmed. + 0x24 + 0x20 + + + PGM_RS_DATA_1 + Configures the 1st 32-bit RS code to be programmed. + 0 + 32 + read-write + + + + + PGM_CHECK_VALUE2 + Register 2 that stores the RS code to be programmed. + 0x28 + 0x20 + + + PGM_RS_DATA_2 + Configures the 2nd 32-bit RS code to be programmed. + 0 + 32 + read-write + + + + + RD_WR_DIS + BLOCK0 data register 0. + 0x2C + 0x20 + + + WR_DIS + Represents whether programming of individual eFuse memory bit is disabled or enabled. 1: Disabled. 0 Enabled. + 0 + 32 + read-only + + + + + RD_REPEAT_DATA0 + BLOCK0 data register 1. + 0x30 + 0x20 + + + RD_DIS + Represents whether reading of individual eFuse block(block4~block10) is disabled or enabled. 1: disabled. 0: enabled. + 0 + 7 + read-only + + + USB_DEVICE_EXCHG_PINS + Enable usb device exchange pins of D+ and D-. + 7 + 1 + read-only + + + USB_OTG11_EXCHG_PINS + Enable usb otg11 exchange pins of D+ and D-. + 8 + 1 + read-only + + + DIS_USB_JTAG + Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled. + 9 + 1 + read-only + + + POWERGLITCH_EN + Represents whether power glitch function is enabled. 1: enabled. 0: disabled. + 10 + 1 + read-only + + + DIS_USB_SERIAL_JTAG + Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled. + 11 + 1 + read-only + + + DIS_FORCE_DOWNLOAD + Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled. + 12 + 1 + read-only + + + SPI_DOWNLOAD_MSPI_DIS + Set this bit to disable accessing MSPI flash/MSPI ram by SYS AXI matrix during boot_mode_download. + 13 + 1 + read-only + + + DIS_TWAI + Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled. + 14 + 1 + read-only + + + JTAG_SEL_ENABLE + Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled. 0: disabled. + 15 + 1 + read-only + + + SOFT_DIS_JTAG + Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled. + 16 + 3 + read-only + + + DIS_PAD_JTAG + Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled. + 19 + 1 + read-only + + + DIS_DOWNLOAD_MANUAL_ENCRYPT + Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled. + 20 + 1 + read-only + + + USB_DEVICE_DREFH + USB intphy of usb device signle-end input high threshold, 1.76V to 2V. Step by 80mV + 21 + 2 + read-only + + + USB_OTG11_DREFH + USB intphy of usb otg11 signle-end input high threshold, 1.76V to 2V. Step by 80mV + 23 + 2 + read-only + + + USB_PHY_SEL + TBD + 25 + 1 + read-only + + + KM_HUK_GEN_STATE_LOW + Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, even of 1 is valid. + 26 + 6 + read-only + + + + + RD_REPEAT_DATA1 + BLOCK0 data register 2. + 0x34 + 0x20 + + + KM_HUK_GEN_STATE_HIGH + Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, even of 1 is valid. + 0 + 3 + read-only + + + KM_RND_SWITCH_CYCLE + Set bits to control key manager random number switch cycle. 0: control by register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles. + 3 + 2 + read-only + + + KM_DEPLOY_ONLY_ONCE + Set each bit to control whether corresponding key can only be deployed once. 1 is true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds. + 5 + 4 + read-only + + + FORCE_USE_KEY_MANAGER_KEY + Set each bit to control whether corresponding key must come from key manager.. 1 is true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds. + 9 + 4 + read-only + + + FORCE_DISABLE_SW_INIT_KEY + Set this bit to disable software written init key, and force use efuse_init_key. + 13 + 1 + read-only + + + XTS_KEY_LENGTH_256 + Set this bit to configure flash encryption use xts-128 key, else use xts-256 key. + 14 + 1 + read-only + + + WDT_DELAY_SEL + Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected. + 16 + 2 + read-only + + + SPI_BOOT_CRYPT_CNT + Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of 1: enabled. Even number of 1: disabled. + 18 + 3 + read-only + + + SECURE_BOOT_KEY_REVOKE0 + Represents whether revoking first secure boot key is enabled or disabled. 1: enabled. 0: disabled. + 21 + 1 + read-only + + + SECURE_BOOT_KEY_REVOKE1 + Represents whether revoking second secure boot key is enabled or disabled. 1: enabled. 0: disabled. + 22 + 1 + read-only + + + SECURE_BOOT_KEY_REVOKE2 + Represents whether revoking third secure boot key is enabled or disabled. 1: enabled. 0: disabled. + 23 + 1 + read-only + + + KEY_PURPOSE_0 + Represents the purpose of Key0. + 24 + 4 + read-only + + + KEY_PURPOSE_1 + Represents the purpose of Key1. + 28 + 4 + read-only + + + + + RD_REPEAT_DATA2 + BLOCK0 data register 3. + 0x38 + 0x20 + 0x00080000 + + + KEY_PURPOSE_2 + Represents the purpose of Key2. + 0 + 4 + read-only + + + KEY_PURPOSE_3 + Represents the purpose of Key3. + 4 + 4 + read-only + + + KEY_PURPOSE_4 + Represents the purpose of Key4. + 8 + 4 + read-only + + + KEY_PURPOSE_5 + Represents the purpose of Key5. + 12 + 4 + read-only + + + SEC_DPA_LEVEL + Represents the spa secure level by configuring the clock random divide mode. + 16 + 2 + read-only + + + ECDSA_ENABLE_SOFT_K + Represents whether hardware random number k is forced used in ESDCA. 1: force used. 0: not force used. + 18 + 1 + read-only + + + CRYPT_DPA_ENABLE + Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled. + 19 + 1 + read-only + + + SECURE_BOOT_EN + Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled. + 20 + 1 + read-only + + + SECURE_BOOT_AGGRESSIVE_REVOKE + Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled. + 21 + 1 + read-only + + + FLASH_TYPE + The type of interfaced flash. 0: four data lines, 1: eight data lines. + 23 + 1 + read-only + + + FLASH_PAGE_SIZE + Set flash page size. + 24 + 2 + read-only + + + FLASH_ECC_EN + Set this bit to enable ecc for flash boot. + 26 + 1 + read-only + + + DIS_USB_OTG_DOWNLOAD_MODE + Set this bit to disable download via USB-OTG. + 27 + 1 + read-only + + + FLASH_TPUW + Represents the flash waiting time after power-up, in unit of ms. When the value less than 15, the waiting time is the programmed value. Otherwise, the waiting time is 2 times the programmed value. + 28 + 4 + read-only + + + + + RD_REPEAT_DATA3 + BLOCK0 data register 4. + 0x3C + 0x20 + + + DIS_DOWNLOAD_MODE + Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled. + 0 + 1 + read-only + + + DIS_DIRECT_BOOT + Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled. + 1 + 1 + read-only + + + DIS_USB_SERIAL_JTAG_ROM_PRINT + Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled. + 2 + 1 + read-only + + + LOCK_KM_KEY + TBD + 3 + 1 + read-only + + + DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE + Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled. + 4 + 1 + read-only + + + ENABLE_SECURITY_DOWNLOAD + Represents whether security download is enabled or disabled. 1: enabled. 0: disabled. + 5 + 1 + read-only + + + UART_PRINT_CONTROL + Represents the type of UART printing. 00: force enable printing. 01: enable printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset at high level. 11: force disable printing. + 6 + 2 + read-only + + + FORCE_SEND_RESUME + Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced. + 8 + 1 + read-only + + + SECURE_VERSION + Represents the version used by ESP-IDF anti-rollback feature. + 9 + 16 + read-only + + + SECURE_BOOT_DISABLE_FAST_WAKE + Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled. + 25 + 1 + read-only + + + HYS_EN_PAD + Represents whether the hysteresis function of corresponding PAD is enabled. 1: enabled. 0:disabled. + 26 + 1 + read-only + + + DCDC_VSET + Set the dcdc voltage default. + 27 + 5 + read-only + + + + + RD_REPEAT_DATA4 + BLOCK0 data register 5. + 0x40 + 0x20 + + + _0PXA_TIEH_SEL_0 + TBD + 0 + 2 + read-only + + + _0PXA_TIEH_SEL_1 + TBD. + 2 + 2 + read-only + + + _0PXA_TIEH_SEL_2 + TBD. + 4 + 2 + read-only + + + _0PXA_TIEH_SEL_3 + TBD. + 6 + 2 + read-only + + + KM_DISABLE_DEPLOY_MODE + TBD. + 8 + 4 + read-only + + + USB_DEVICE_DREFL + Represents the usb device single-end input low threhold, 0.8 V to 1.04 V with step of 80 mV. + 12 + 2 + read-only + + + USB_OTG11_DREFL + Represents the usb otg11 single-end input low threhold, 0.8 V to 1.04 V with step of 80 mV. + 14 + 2 + read-only + + + HP_PWR_SRC_SEL + HP system power source select. 0:LDO. 1: DCDC. + 18 + 1 + read-only + + + DCDC_VSET_EN + Select dcdc vset use efuse_dcdc_vset. + 19 + 1 + read-only + + + DIS_WDT + Set this bit to disable watch dog. + 20 + 1 + read-only + + + DIS_SWD + Set this bit to disable super-watchdog. + 21 + 1 + read-only + + + + + RD_MAC_SYS_0 + BLOCK1 data register $n. + 0x44 + 0x20 + + + MAC_0 + Stores the low 32 bits of MAC address. + 0 + 32 + read-only + + + + + RD_MAC_SYS_1 + BLOCK1 data register $n. + 0x48 + 0x20 + + + MAC_1 + Stores the high 16 bits of MAC address. + 0 + 16 + read-only + + + MAC_EXT + Stores the extended bits of MAC address. + 16 + 16 + read-only + + + + + RD_MAC_SYS_2 + BLOCK1 data register $n. + 0x4C + 0x20 + + + MAC_RESERVED_1 + Reserved. + 0 + 14 + read-only + + + MAC_RESERVED_0 + Reserved. + 14 + 18 + read-only + + + + + RD_MAC_SYS_3 + BLOCK1 data register $n. + 0x50 + 0x20 + + + MAC_RESERVED_2 + Reserved. + 0 + 18 + read-only + + + SYS_DATA_PART0_0 + Stores the first 14 bits of the zeroth part of system data. + 18 + 14 + read-only + + + + + RD_MAC_SYS_4 + BLOCK1 data register $n. + 0x54 + 0x20 + + + SYS_DATA_PART0_1 + Stores the first 32 bits of the zeroth part of system data. + 0 + 32 + read-only + + + + + RD_MAC_SYS_5 + BLOCK1 data register $n. + 0x58 + 0x20 + + + SYS_DATA_PART0_2 + Stores the second 32 bits of the zeroth part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA0 + Register $n of BLOCK2 (system). + 0x5C + 0x20 + + + SYS_DATA_PART1_0 + Stores the zeroth 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA1 + Register $n of BLOCK2 (system). + 0x60 + 0x20 + + + SYS_DATA_PART1_1 + Stores the first 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA2 + Register $n of BLOCK2 (system). + 0x64 + 0x20 + + + SYS_DATA_PART1_2 + Stores the second 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA3 + Register $n of BLOCK2 (system). + 0x68 + 0x20 + + + SYS_DATA_PART1_3 + Stores the third 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA4 + Register $n of BLOCK2 (system). + 0x6C + 0x20 + + + SYS_DATA_PART1_4 + Stores the fourth 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA5 + Register $n of BLOCK2 (system). + 0x70 + 0x20 + + + SYS_DATA_PART1_5 + Stores the fifth 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA6 + Register $n of BLOCK2 (system). + 0x74 + 0x20 + + + SYS_DATA_PART1_6 + Stores the sixth 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA7 + Register $n of BLOCK2 (system). + 0x78 + 0x20 + + + SYS_DATA_PART1_7 + Stores the seventh 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_USR_DATA0 + Register $n of BLOCK3 (user). + 0x7C + 0x20 + + + USR_DATA0 + Stores the zeroth 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA1 + Register $n of BLOCK3 (user). + 0x80 + 0x20 + + + USR_DATA1 + Stores the first 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA2 + Register $n of BLOCK3 (user). + 0x84 + 0x20 + + + USR_DATA2 + Stores the second 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA3 + Register $n of BLOCK3 (user). + 0x88 + 0x20 + + + USR_DATA3 + Stores the third 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA4 + Register $n of BLOCK3 (user). + 0x8C + 0x20 + + + USR_DATA4 + Stores the fourth 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA5 + Register $n of BLOCK3 (user). + 0x90 + 0x20 + + + USR_DATA5 + Stores the fifth 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA6 + Register $n of BLOCK3 (user). + 0x94 + 0x20 + + + USR_DATA6 + Stores the sixth 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA7 + Register $n of BLOCK3 (user). + 0x98 + 0x20 + + + USR_DATA7 + Stores the seventh 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_KEY0_DATA0 + Register $n of BLOCK4 (KEY0). + 0x9C + 0x20 + + + KEY0_DATA0 + Stores the zeroth 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA1 + Register $n of BLOCK4 (KEY0). + 0xA0 + 0x20 + + + KEY0_DATA1 + Stores the first 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA2 + Register $n of BLOCK4 (KEY0). + 0xA4 + 0x20 + + + KEY0_DATA2 + Stores the second 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA3 + Register $n of BLOCK4 (KEY0). + 0xA8 + 0x20 + + + KEY0_DATA3 + Stores the third 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA4 + Register $n of BLOCK4 (KEY0). + 0xAC + 0x20 + + + KEY0_DATA4 + Stores the fourth 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA5 + Register $n of BLOCK4 (KEY0). + 0xB0 + 0x20 + + + KEY0_DATA5 + Stores the fifth 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA6 + Register $n of BLOCK4 (KEY0). + 0xB4 + 0x20 + + + KEY0_DATA6 + Stores the sixth 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA7 + Register $n of BLOCK4 (KEY0). + 0xB8 + 0x20 + + + KEY0_DATA7 + Stores the seventh 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY1_DATA0 + Register $n of BLOCK5 (KEY1). + 0xBC + 0x20 + + + KEY1_DATA0 + Stores the zeroth 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA1 + Register $n of BLOCK5 (KEY1). + 0xC0 + 0x20 + + + KEY1_DATA1 + Stores the first 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA2 + Register $n of BLOCK5 (KEY1). + 0xC4 + 0x20 + + + KEY1_DATA2 + Stores the second 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA3 + Register $n of BLOCK5 (KEY1). + 0xC8 + 0x20 + + + KEY1_DATA3 + Stores the third 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA4 + Register $n of BLOCK5 (KEY1). + 0xCC + 0x20 + + + KEY1_DATA4 + Stores the fourth 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA5 + Register $n of BLOCK5 (KEY1). + 0xD0 + 0x20 + + + KEY1_DATA5 + Stores the fifth 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA6 + Register $n of BLOCK5 (KEY1). + 0xD4 + 0x20 + + + KEY1_DATA6 + Stores the sixth 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA7 + Register $n of BLOCK5 (KEY1). + 0xD8 + 0x20 + + + KEY1_DATA7 + Stores the seventh 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY2_DATA0 + Register $n of BLOCK6 (KEY2). + 0xDC + 0x20 + + + KEY2_DATA0 + Stores the zeroth 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA1 + Register $n of BLOCK6 (KEY2). + 0xE0 + 0x20 + + + KEY2_DATA1 + Stores the first 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA2 + Register $n of BLOCK6 (KEY2). + 0xE4 + 0x20 + + + KEY2_DATA2 + Stores the second 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA3 + Register $n of BLOCK6 (KEY2). + 0xE8 + 0x20 + + + KEY2_DATA3 + Stores the third 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA4 + Register $n of BLOCK6 (KEY2). + 0xEC + 0x20 + + + KEY2_DATA4 + Stores the fourth 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA5 + Register $n of BLOCK6 (KEY2). + 0xF0 + 0x20 + + + KEY2_DATA5 + Stores the fifth 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA6 + Register $n of BLOCK6 (KEY2). + 0xF4 + 0x20 + + + KEY2_DATA6 + Stores the sixth 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA7 + Register $n of BLOCK6 (KEY2). + 0xF8 + 0x20 + + + KEY2_DATA7 + Stores the seventh 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY3_DATA0 + Register $n of BLOCK7 (KEY3). + 0xFC + 0x20 + + + KEY3_DATA0 + Stores the zeroth 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA1 + Register $n of BLOCK7 (KEY3). + 0x100 + 0x20 + + + KEY3_DATA1 + Stores the first 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA2 + Register $n of BLOCK7 (KEY3). + 0x104 + 0x20 + + + KEY3_DATA2 + Stores the second 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA3 + Register $n of BLOCK7 (KEY3). + 0x108 + 0x20 + + + KEY3_DATA3 + Stores the third 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA4 + Register $n of BLOCK7 (KEY3). + 0x10C + 0x20 + + + KEY3_DATA4 + Stores the fourth 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA5 + Register $n of BLOCK7 (KEY3). + 0x110 + 0x20 + + + KEY3_DATA5 + Stores the fifth 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA6 + Register $n of BLOCK7 (KEY3). + 0x114 + 0x20 + + + KEY3_DATA6 + Stores the sixth 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA7 + Register $n of BLOCK7 (KEY3). + 0x118 + 0x20 + + + KEY3_DATA7 + Stores the seventh 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY4_DATA0 + Register $n of BLOCK8 (KEY4). + 0x11C + 0x20 + + + KEY4_DATA0 + Stores the zeroth 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA1 + Register $n of BLOCK8 (KEY4). + 0x120 + 0x20 + + + KEY4_DATA1 + Stores the first 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA2 + Register $n of BLOCK8 (KEY4). + 0x124 + 0x20 + + + KEY4_DATA2 + Stores the second 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA3 + Register $n of BLOCK8 (KEY4). + 0x128 + 0x20 + + + KEY4_DATA3 + Stores the third 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA4 + Register $n of BLOCK8 (KEY4). + 0x12C + 0x20 + + + KEY4_DATA4 + Stores the fourth 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA5 + Register $n of BLOCK8 (KEY4). + 0x130 + 0x20 + + + KEY4_DATA5 + Stores the fifth 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA6 + Register $n of BLOCK8 (KEY4). + 0x134 + 0x20 + + + KEY4_DATA6 + Stores the sixth 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA7 + Register $n of BLOCK8 (KEY4). + 0x138 + 0x20 + + + KEY4_DATA7 + Stores the seventh 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY5_DATA0 + Register $n of BLOCK9 (KEY5). + 0x13C + 0x20 + + + KEY5_DATA0 + Stores the zeroth 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA1 + Register $n of BLOCK9 (KEY5). + 0x140 + 0x20 + + + KEY5_DATA1 + Stores the first 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA2 + Register $n of BLOCK9 (KEY5). + 0x144 + 0x20 + + + KEY5_DATA2 + Stores the second 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA3 + Register $n of BLOCK9 (KEY5). + 0x148 + 0x20 + + + KEY5_DATA3 + Stores the third 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA4 + Register $n of BLOCK9 (KEY5). + 0x14C + 0x20 + + + KEY5_DATA4 + Stores the fourth 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA5 + Register $n of BLOCK9 (KEY5). + 0x150 + 0x20 + + + KEY5_DATA5 + Stores the fifth 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA6 + Register $n of BLOCK9 (KEY5). + 0x154 + 0x20 + + + KEY5_DATA6 + Stores the sixth 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA7 + Register $n of BLOCK9 (KEY5). + 0x158 + 0x20 + + + KEY5_DATA7 + Stores the seventh 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA0 + Register $n of BLOCK10 (system). + 0x15C + 0x20 + + + SYS_DATA_PART2_0 + Stores the 0th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA1 + Register $n of BLOCK9 (KEY5). + 0x160 + 0x20 + + + SYS_DATA_PART2_1 + Stores the 0th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA2 + Register $n of BLOCK10 (system). + 0x164 + 0x20 + + + SYS_DATA_PART2_2 + Stores the 0th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA3 + Register $n of BLOCK10 (system). + 0x168 + 0x20 + + + SYS_DATA_PART2_3 + Stores the 0th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA4 + Register $n of BLOCK10 (system). + 0x16C + 0x20 + + + SYS_DATA_PART2_4 + Stores the 0th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA5 + Register $n of BLOCK10 (system). + 0x170 + 0x20 + + + SYS_DATA_PART2_5 + Stores the 0th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA6 + Register $n of BLOCK10 (system). + 0x174 + 0x20 + + + SYS_DATA_PART2_6 + Stores the 0th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA7 + Register $n of BLOCK10 (system). + 0x178 + 0x20 + + + SYS_DATA_PART2_7 + Stores the 0th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_REPEAT_ERR0 + Programming error record register 0 of BLOCK0. + 0x17C + 0x20 + + + RD_DIS_ERR + Indicates a programming error of RD_DIS. + 0 + 7 + read-only + + + DIS_USB_DEVICE_EXCHG_PINS_ERR + Indicates a programming error of DIS_USB_DEVICE_EXCHG_PINS. + 7 + 1 + read-only + + + DIS_USB_OTG11_EXCHG_PINS_ERR + Indicates a programming error of DIS_USB_OTG11_EXCHG_PINS. + 8 + 1 + read-only + + + DIS_USB_JTAG_ERR + Indicates a programming error of DIS_USB_JTAG. + 9 + 1 + read-only + + + POWERGLITCH_EN_ERR + Indicates a programming error of POWERGLITCH_EN. + 10 + 1 + read-only + + + DIS_USB_SERIAL_JTAG_ERR + Indicates a programming error of DIS_USB_SERIAL_JTAG. + 11 + 1 + read-only + + + DIS_FORCE_DOWNLOAD_ERR + Indicates a programming error of DIS_FORCE_DOWNLOAD. + 12 + 1 + read-only + + + SPI_DOWNLOAD_MSPI_DIS_ERR + Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS. + 13 + 1 + read-only + + + DIS_TWAI_ERR + Indicates a programming error of DIS_TWAI. + 14 + 1 + read-only + + + JTAG_SEL_ENABLE_ERR + Indicates a programming error of JTAG_SEL_ENABLE. + 15 + 1 + read-only + + + SOFT_DIS_JTAG_ERR + Indicates a programming error of SOFT_DIS_JTAG. + 16 + 3 + read-only + + + DIS_PAD_JTAG_ERR + Indicates a programming error of DIS_PAD_JTAG. + 19 + 1 + read-only + + + DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR + Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT. + 20 + 1 + read-only + + + USB_DEVICE_DREFH_ERR + Indicates a programming error of USB_DEVICE_DREFH. + 21 + 2 + read-only + + + USB_OTG11_DREFH_ERR + Indicates a programming error of USB_OTG11_DREFH. + 23 + 2 + read-only + + + USB_PHY_SEL_ERR + Indicates a programming error of USB_PHY_SEL. + 25 + 1 + read-only + + + HUK_GEN_STATE_LOW_ERR + Indicates a programming error of HUK_GEN_STATE_LOW. + 26 + 6 + read-only + + + + + RD_REPEAT_ERR1 + Programming error record register 1 of BLOCK0. + 0x180 + 0x20 + + + KM_HUK_GEN_STATE_HIGH_ERR + Indicates a programming error of HUK_GEN_STATE_HIGH. + 0 + 3 + read-only + + + KM_RND_SWITCH_CYCLE_ERR + Indicates a programming error of KM_RND_SWITCH_CYCLE. + 3 + 2 + read-only + + + KM_DEPLOY_ONLY_ONCE_ERR + Indicates a programming error of KM_DEPLOY_ONLY_ONCE. + 5 + 4 + read-only + + + FORCE_USE_KEY_MANAGER_KEY_ERR + Indicates a programming error of FORCE_USE_KEY_MANAGER_KEY. + 9 + 4 + read-only + + + FORCE_DISABLE_SW_INIT_KEY_ERR + Indicates a programming error of FORCE_DISABLE_SW_INIT_KEY. + 13 + 1 + read-only + + + XTS_KEY_LENGTH_256_ERR + Indicates a programming error of XTS_KEY_LENGTH_256. + 14 + 1 + read-only + + + WDT_DELAY_SEL_ERR + Indicates a programming error of WDT_DELAY_SEL. + 16 + 2 + read-only + + + SPI_BOOT_CRYPT_CNT_ERR + Indicates a programming error of SPI_BOOT_CRYPT_CNT. + 18 + 3 + read-only + + + SECURE_BOOT_KEY_REVOKE0_ERR + Indicates a programming error of SECURE_BOOT_KEY_REVOKE0. + 21 + 1 + read-only + + + SECURE_BOOT_KEY_REVOKE1_ERR + Indicates a programming error of SECURE_BOOT_KEY_REVOKE1. + 22 + 1 + read-only + + + SECURE_BOOT_KEY_REVOKE2_ERR + Indicates a programming error of SECURE_BOOT_KEY_REVOKE2. + 23 + 1 + read-only + + + KEY_PURPOSE_0_ERR + Indicates a programming error of KEY_PURPOSE_0. + 24 + 4 + read-only + + + KEY_PURPOSE_1_ERR + Indicates a programming error of KEY_PURPOSE_1. + 28 + 4 + read-only + + + + + RD_REPEAT_ERR2 + Programming error record register 2 of BLOCK0. + 0x184 + 0x20 + + + KEY_PURPOSE_2_ERR + Indicates a programming error of KEY_PURPOSE_2. + 0 + 4 + read-only + + + KEY_PURPOSE_3_ERR + Indicates a programming error of KEY_PURPOSE_3. + 4 + 4 + read-only + + + KEY_PURPOSE_4_ERR + Indicates a programming error of KEY_PURPOSE_4. + 8 + 4 + read-only + + + KEY_PURPOSE_5_ERR + Indicates a programming error of KEY_PURPOSE_5. + 12 + 4 + read-only + + + SEC_DPA_LEVEL_ERR + Indicates a programming error of SEC_DPA_LEVEL. + 16 + 2 + read-only + + + ECDSA_ENABLE_SOFT_K_ERR + Indicates a programming error of ECDSA_FORCE_USE_HARDWARE_K. + 18 + 1 + read-only + + + CRYPT_DPA_ENABLE_ERR + Indicates a programming error of CRYPT_DPA_ENABLE. + 19 + 1 + read-only + + + SECURE_BOOT_EN_ERR + Indicates a programming error of SECURE_BOOT_EN. + 20 + 1 + read-only + + + SECURE_BOOT_AGGRESSIVE_REVOKE_ERR + Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE. + 21 + 1 + read-only + + + FLASH_TYPE_ERR + Indicates a programming error of FLASH_TYPE. + 23 + 1 + read-only + + + FLASH_PAGE_SIZE_ERR + Indicates a programming error of FLASH_PAGE_SIZE. + 24 + 2 + read-only + + + FLASH_ECC_EN_ERR + Indicates a programming error of FLASH_ECC_EN. + 26 + 1 + read-only + + + DIS_USB_OTG_DOWNLOAD_MODE_ERR + Indicates a programming error of DIS_USB_OTG_DOWNLOAD_MODE. + 27 + 1 + read-only + + + FLASH_TPUW_ERR + Indicates a programming error of FLASH_TPUW. + 28 + 4 + read-only + + + + + RD_REPEAT_ERR3 + Programming error record register 3 of BLOCK0. + 0x188 + 0x20 + + + DIS_DOWNLOAD_MODE_ERR + Indicates a programming error of DIS_DOWNLOAD_MODE. + 0 + 1 + read-only + + + DIS_DIRECT_BOOT_ERR + Indicates a programming error of DIS_DIRECT_BOOT. + 1 + 1 + read-only + + + DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR + Indicates a programming error of DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR. + 2 + 1 + read-only + + + LOCK_KM_KEY_ERR + TBD + 3 + 1 + read-only + + + DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR + Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE. + 4 + 1 + read-only + + + ENABLE_SECURITY_DOWNLOAD_ERR + Indicates a programming error of ENABLE_SECURITY_DOWNLOAD. + 5 + 1 + read-only + + + UART_PRINT_CONTROL_ERR + Indicates a programming error of UART_PRINT_CONTROL. + 6 + 2 + read-only + + + FORCE_SEND_RESUME_ERR + Indicates a programming error of FORCE_SEND_RESUME. + 8 + 1 + read-only + + + SECURE_VERSION_ERR + Indicates a programming error of SECURE VERSION. + 9 + 16 + read-only + + + SECURE_BOOT_DISABLE_FAST_WAKE_ERR + Indicates a programming error of SECURE_BOOT_DISABLE_FAST_WAKE. + 25 + 1 + read-only + + + HYS_EN_PAD_ERR + Indicates a programming error of HYS_EN_PAD. + 26 + 1 + read-only + + + DCDC_VSET_ERR + Indicates a programming error of DCDC_VSET. + 27 + 5 + read-only + + + + + RD_REPEAT_ERR4 + Programming error record register 4 of BLOCK0. + 0x18C + 0x20 + + + _0PXA_TIEH_SEL_0_ERR + Indicates a programming error of 0PXA_TIEH_SEL_0. + 0 + 2 + read-only + + + _0PXA_TIEH_SEL_1_ERR + Indicates a programming error of 0PXA_TIEH_SEL_1. + 2 + 2 + read-only + + + _0PXA_TIEH_SEL_2_ERR + Indicates a programming error of 0PXA_TIEH_SEL_2. + 4 + 2 + read-only + + + _0PXA_TIEH_SEL_3_ERR + Indicates a programming error of 0PXA_TIEH_SEL_3. + 6 + 2 + read-only + + + KM_DISABLE_DEPLOY_MODE_ERR + TBD. + 8 + 4 + read-only + + + USB_DEVICE_DREFL_ERR + Indicates a programming error of USB_DEVICE_DREFL. + 12 + 2 + read-only + + + USB_OTG11_DREFL_ERR + Indicates a programming error of USB_OTG11_DREFL. + 14 + 2 + read-only + + + HP_PWR_SRC_SEL_ERR + Indicates a programming error of HP_PWR_SRC_SEL. + 18 + 1 + read-only + + + DCDC_VSET_EN_ERR + Indicates a programming error of DCDC_VSET_EN. + 19 + 1 + read-only + + + DIS_WDT_ERR + Indicates a programming error of DIS_WDT. + 20 + 1 + read-only + + + DIS_SWD_ERR + Indicates a programming error of DIS_SWD. + 21 + 1 + read-only + + + + + RD_RS_ERR0 + Programming error record register 0 of BLOCK1-10. + 0x1C0 + 0x20 + + + MAC_SYS_ERR_NUM + The value of this signal means the number of error bytes. + 0 + 3 + read-only + + + MAC_SYS_FAIL + 0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that programming user data failed and the number of error bytes is over 6. + 3 + 1 + read-only + + + SYS_PART1_ERR_NUM + The value of this signal means the number of error bytes. + 4 + 3 + read-only + + + SYS_PART1_FAIL + 0: Means no failure and that the data of system part1 is reliable 1: Means that programming user data failed and the number of error bytes is over 6. + 7 + 1 + read-only + + + USR_DATA_ERR_NUM + The value of this signal means the number of error bytes. + 8 + 3 + read-only + + + USR_DATA_FAIL + 0: Means no failure and that the user data is reliable 1: Means that programming user data failed and the number of error bytes is over 6. + 11 + 1 + read-only + + + KEY0_ERR_NUM + The value of this signal means the number of error bytes. + 12 + 3 + read-only + + + KEY0_FAIL + 0: Means no failure and that the data of key0 is reliable 1: Means that programming key0 failed and the number of error bytes is over 6. + 15 + 1 + read-only + + + KEY1_ERR_NUM + The value of this signal means the number of error bytes. + 16 + 3 + read-only + + + KEY1_FAIL + 0: Means no failure and that the data of key1 is reliable 1: Means that programming key1 failed and the number of error bytes is over 6. + 19 + 1 + read-only + + + KEY2_ERR_NUM + The value of this signal means the number of error bytes. + 20 + 3 + read-only + + + KEY2_FAIL + 0: Means no failure and that the data of key2 is reliable 1: Means that programming key2 failed and the number of error bytes is over 6. + 23 + 1 + read-only + + + KEY3_ERR_NUM + The value of this signal means the number of error bytes. + 24 + 3 + read-only + + + KEY3_FAIL + 0: Means no failure and that the data of key3 is reliable 1: Means that programming key3 failed and the number of error bytes is over 6. + 27 + 1 + read-only + + + KEY4_ERR_NUM + The value of this signal means the number of error bytes. + 28 + 3 + read-only + + + KEY4_FAIL + 0: Means no failure and that the data of key4 is reliable 1: Means that programming key4 failed and the number of error bytes is over 6. + 31 + 1 + read-only + + + + + RD_RS_ERR1 + Programming error record register 1 of BLOCK1-10. + 0x1C4 + 0x20 + + + KEY5_ERR_NUM + The value of this signal means the number of error bytes. + 0 + 3 + read-only + + + KEY5_FAIL + 0: Means no failure and that the data of key5 is reliable 1: Means that programming key5 failed and the number of error bytes is over 6. + 3 + 1 + read-only + + + SYS_PART2_ERR_NUM + The value of this signal means the number of error bytes. + 4 + 3 + read-only + + + SYS_PART2_FAIL + 0: Means no failure and that the data of system part2 is reliable 1: Means that programming user data failed and the number of error bytes is over 6. + 7 + 1 + read-only + + + + + CLK + eFuse clcok configuration register. + 0x1C8 + 0x20 + + + MEM_FORCE_PD + Set this bit to force eFuse SRAM into power-saving mode. + 0 + 1 + read-write + + + MEM_CLK_FORCE_ON + Set this bit and force to activate clock signal of eFuse SRAM. + 1 + 1 + read-write + + + MEM_FORCE_PU + Set this bit to force eFuse SRAM into working mode. + 2 + 1 + read-write + + + EN + Set this bit to force enable eFuse register configuration clock signal. + 16 + 1 + read-write + + + + + CONF + eFuse operation mode configuraiton register + 0x1CC + 0x20 + + + OP_CODE + 0x5A5A: programming operation command 0x5AA5: read operation command. + 0 + 16 + read-write + + + CFG_ECDSA_BLK + Configures which block to use for ECDSA key output. + 16 + 4 + read-write + + + + + STATUS + eFuse status register. + 0x1D0 + 0x20 + + + STATE + Indicates the state of the eFuse state machine. + 0 + 4 + read-only + + + OTP_LOAD_SW + The value of OTP_LOAD_SW. + 4 + 1 + read-only + + + OTP_VDDQ_C_SYNC2 + The value of OTP_VDDQ_C_SYNC2. + 5 + 1 + read-only + + + OTP_STROBE_SW + The value of OTP_STROBE_SW. + 6 + 1 + read-only + + + OTP_CSB_SW + The value of OTP_CSB_SW. + 7 + 1 + read-only + + + OTP_PGENB_SW + The value of OTP_PGENB_SW. + 8 + 1 + read-only + + + OTP_VDDQ_IS_SW + The value of OTP_VDDQ_IS_SW. + 9 + 1 + read-only + + + BLK0_VALID_BIT_CNT + Indicates the number of block valid bit. + 10 + 10 + read-only + + + CUR_ECDSA_BLK + Indicates which block is used for ECDSA key output. + 20 + 4 + read-only + + + + + CMD + eFuse command register. + 0x1D4 + 0x20 + + + READ_CMD + Set this bit to send read command. + 0 + 1 + read-write + + + PGM_CMD + Set this bit to send programming command. + 1 + 1 + read-write + + + BLK_NUM + The serial number of the block to be programmed. Value 0-10 corresponds to block number 0-10, respectively. + 2 + 4 + read-write + + + + + INT_RAW + eFuse raw interrupt register. + 0x1D8 + 0x20 + + + READ_DONE_INT_RAW + The raw bit signal for read_done interrupt. + 0 + 1 + read-only + + + PGM_DONE_INT_RAW + The raw bit signal for pgm_done interrupt. + 1 + 1 + read-only + + + + + INT_ST + eFuse interrupt status register. + 0x1DC + 0x20 + + + READ_DONE_INT_ST + The status signal for read_done interrupt. + 0 + 1 + read-only + + + PGM_DONE_INT_ST + The status signal for pgm_done interrupt. + 1 + 1 + read-only + + + + + INT_ENA + eFuse interrupt enable register. + 0x1E0 + 0x20 + + + READ_DONE_INT_ENA + The enable signal for read_done interrupt. + 0 + 1 + read-write + + + PGM_DONE_INT_ENA + The enable signal for pgm_done interrupt. + 1 + 1 + read-write + + + + + INT_CLR + eFuse interrupt clear register. + 0x1E4 + 0x20 + + + READ_DONE_INT_CLR + The clear signal for read_done interrupt. + 0 + 1 + write-only + + + PGM_DONE_INT_CLR + The clear signal for pgm_done interrupt. + 1 + 1 + write-only + + + + + DAC_CONF + Controls the eFuse programming voltage. + 0x1E8 + 0x20 + 0x0001FE17 + + + DAC_CLK_DIV + Controls the division factor of the rising clock of the programming voltage. + 0 + 8 + read-write + + + DAC_CLK_PAD_SEL + Don't care. + 8 + 1 + read-write + + + DAC_NUM + Controls the rising period of the programming voltage. + 9 + 8 + read-write + + + OE_CLR + Reduces the power supply of the programming voltage. + 17 + 1 + read-write + + + + + RD_TIM_CONF + Configures read timing parameters. + 0x1EC + 0x20 + 0x0F010201 + + + THR_A + Configures the read hold time. + 0 + 8 + read-write + + + TRD + Configures the read time. + 8 + 8 + read-write + + + TSUR_A + Configures the read setup time. + 16 + 8 + read-write + + + READ_INIT_NUM + Configures the waiting time of reading eFuse memory. + 24 + 8 + read-write + + + + + WR_TIM_CONF1 + Configurarion register 1 of eFuse programming timing parameters. + 0x1F0 + 0x20 + 0x01266701 + + + TSUP_A + Configures the programming setup time. + 0 + 8 + read-write + + + PWR_ON_NUM + Configures the power up time for VDDQ. + 8 + 16 + read-write + + + THP_A + Configures the programming hold time. + 24 + 8 + read-write + + + + + WR_TIM_CONF2 + Configurarion register 2 of eFuse programming timing parameters. + 0x1F4 + 0x20 + 0x00A00140 + + + PWR_OFF_NUM + Configures the power outage time for VDDQ. + 0 + 16 + read-write + + + TPGM + Configures the active programming time. + 16 + 16 + read-write + + + + + WR_TIM_CONF0_RS_BYPASS + Configurarion register0 of eFuse programming time parameters and rs bypass operation. + 0x1F8 + 0x20 + 0x00002000 + + + BYPASS_RS_CORRECTION + Set this bit to bypass reed solomon correction step. + 0 + 1 + read-write + + + BYPASS_RS_BLK_NUM + Configures block number of programming twice operation. + 1 + 11 + read-write + + + UPDATE + Set this bit to update multi-bit register signals. + 12 + 1 + write-only + + + TPGM_INACTIVE + Configures the inactive programming time. + 13 + 8 + read-write + + + + + DATE + eFuse version register. + 0x1FC + 0x20 + 0x02305050 + + + DATE + Stores eFuse version. + 0 + 28 + read-write + + + + + APB2OTP_WR_DIS + eFuse apb2otp block0 data register1. + 0x800 + 0x20 + + + APB2OTP_BLOCK0_WR_DIS + Otp block0 write disable data. + 0 + 32 + read-only + + + + + APB2OTP_BLK0_BACKUP1_W1 + eFuse apb2otp block0 data register2. + 0x804 + 0x20 + + + APB2OTP_BLOCK0_BACKUP1_W1 + Otp block0 backup1 word1 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK0_BACKUP1_W2 + eFuse apb2otp block0 data register3. + 0x808 + 0x20 + + + APB2OTP_BLOCK0_BACKUP1_W2 + Otp block0 backup1 word2 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK0_BACKUP1_W3 + eFuse apb2otp block0 data register4. + 0x80C + 0x20 + + + APB2OTP_BLOCK0_BACKUP1_W3 + Otp block0 backup1 word3 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK0_BACKUP1_W4 + eFuse apb2otp block0 data register5. + 0x810 + 0x20 + + + APB2OTP_BLOCK0_BACKUP1_W4 + Otp block0 backup1 word4 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK0_BACKUP1_W5 + eFuse apb2otp block0 data register6. + 0x814 + 0x20 + + + APB2OTP_BLOCK0_BACKUP1_W5 + Otp block0 backup1 word5 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK0_BACKUP2_W1 + eFuse apb2otp block0 data register7. + 0x818 + 0x20 + + + APB2OTP_BLOCK0_BACKUP2_W1 + Otp block0 backup2 word1 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK0_BACKUP2_W2 + eFuse apb2otp block0 data register8. + 0x81C + 0x20 + + + APB2OTP_BLOCK0_BACKUP2_W2 + Otp block0 backup2 word2 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK0_BACKUP2_W3 + eFuse apb2otp block0 data register9. + 0x820 + 0x20 + + + APB2OTP_BLOCK0_BACKUP2_W3 + Otp block0 backup2 word3 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK0_BACKUP2_W4 + eFuse apb2otp block0 data register10. + 0x824 + 0x20 + + + APB2OTP_BLOCK0_BACKUP2_W4 + Otp block0 backup2 word4 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK0_BACKUP2_W5 + eFuse apb2otp block0 data register11. + 0x828 + 0x20 + + + APB2OTP_BLOCK0_BACKUP2_W5 + Otp block0 backup2 word5 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK0_BACKUP3_W1 + eFuse apb2otp block0 data register12. + 0x82C + 0x20 + + + APB2OTP_BLOCK0_BACKUP3_W1 + Otp block0 backup3 word1 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK0_BACKUP3_W2 + eFuse apb2otp block0 data register13. + 0x830 + 0x20 + + + APB2OTP_BLOCK0_BACKUP3_W2 + Otp block0 backup3 word2 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK0_BACKUP3_W3 + eFuse apb2otp block0 data register14. + 0x834 + 0x20 + + + APB2OTP_BLOCK0_BACKUP3_W3 + Otp block0 backup3 word3 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK0_BACKUP3_W4 + eFuse apb2otp block0 data register15. + 0x838 + 0x20 + + + APB2OTP_BLOCK0_BACKUP3_W4 + Otp block0 backup3 word4 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK0_BACKUP3_W5 + eFuse apb2otp block0 data register16. + 0x83C + 0x20 + + + APB2OTP_BLOCK0_BACKUP3_W5 + Otp block0 backup3 word5 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK0_BACKUP4_W1 + eFuse apb2otp block0 data register17. + 0x840 + 0x20 + + + APB2OTP_BLOCK0_BACKUP4_W1 + Otp block0 backup4 word1 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK0_BACKUP4_W2 + eFuse apb2otp block0 data register18. + 0x844 + 0x20 + + + APB2OTP_BLOCK0_BACKUP4_W2 + Otp block0 backup4 word2 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK0_BACKUP4_W3 + eFuse apb2otp block0 data register19. + 0x848 + 0x20 + + + APB2OTP_BLOCK0_BACKUP4_W3 + Otp block0 backup4 word3 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK0_BACKUP4_W4 + eFuse apb2otp block0 data register20. + 0x84C + 0x20 + + + APB2OTP_BLOCK0_BACKUP4_W4 + Otp block0 backup4 word4 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK0_BACKUP4_W5 + eFuse apb2otp block0 data register21. + 0x850 + 0x20 + + + APB2OTP_BLOCK0_BACKUP4_W5 + Otp block0 backup4 word5 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK1_W1 + eFuse apb2otp block1 data register1. + 0x854 + 0x20 + + + APB2OTP_BLOCK1_W1 + Otp block1 word1 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK1_W2 + eFuse apb2otp block1 data register2. + 0x858 + 0x20 + + + APB2OTP_BLOCK1_W2 + Otp block1 word2 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK1_W3 + eFuse apb2otp block1 data register3. + 0x85C + 0x20 + + + APB2OTP_BLOCK1_W3 + Otp block1 word3 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK1_W4 + eFuse apb2otp block1 data register4. + 0x860 + 0x20 + + + APB2OTP_BLOCK1_W4 + Otp block1 word4 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK1_W5 + eFuse apb2otp block1 data register5. + 0x864 + 0x20 + + + APB2OTP_BLOCK1_W5 + Otp block1 word5 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK1_W6 + eFuse apb2otp block1 data register6. + 0x868 + 0x20 + + + APB2OTP_BLOCK1_W6 + Otp block1 word6 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK1_W7 + eFuse apb2otp block1 data register7. + 0x86C + 0x20 + + + APB2OTP_BLOCK1_W7 + Otp block1 word7 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK1_W8 + eFuse apb2otp block1 data register8. + 0x870 + 0x20 + + + APB2OTP_BLOCK1_W8 + Otp block1 word8 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK1_W9 + eFuse apb2otp block1 data register9. + 0x874 + 0x20 + + + APB2OTP_BLOCK1_W9 + Otp block1 word9 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK2_W1 + eFuse apb2otp block2 data register1. + 0x878 + 0x20 + + + APB2OTP_BLOCK2_W1 + Otp block2 word1 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK2_W2 + eFuse apb2otp block2 data register2. + 0x87C + 0x20 + + + APB2OTP_BLOCK2_W2 + Otp block2 word2 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK2_W3 + eFuse apb2otp block2 data register3. + 0x880 + 0x20 + + + APB2OTP_BLOCK2_W3 + Otp block2 word3 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK2_W4 + eFuse apb2otp block2 data register4. + 0x884 + 0x20 + + + APB2OTP_BLOCK2_W4 + Otp block2 word4 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK2_W5 + eFuse apb2otp block2 data register5. + 0x888 + 0x20 + + + APB2OTP_BLOCK2_W5 + Otp block2 word5 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK2_W6 + eFuse apb2otp block2 data register6. + 0x88C + 0x20 + + + APB2OTP_BLOCK2_W6 + Otp block2 word6 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK2_W7 + eFuse apb2otp block2 data register7. + 0x890 + 0x20 + + + APB2OTP_BLOCK2_W7 + Otp block2 word7 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK2_W8 + eFuse apb2otp block2 data register8. + 0x894 + 0x20 + + + APB2OTP_BLOCK2_W8 + Otp block2 word8 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK2_W9 + eFuse apb2otp block2 data register9. + 0x898 + 0x20 + + + APB2OTP_BLOCK2_W9 + Otp block2 word9 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK2_W10 + eFuse apb2otp block2 data register10. + 0x89C + 0x20 + + + APB2OTP_BLOCK2_W10 + Otp block2 word10 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK2_W11 + eFuse apb2otp block2 data register11. + 0x8A0 + 0x20 + + + APB2OTP_BLOCK2_W11 + Otp block2 word11 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK3_W1 + eFuse apb2otp block3 data register1. + 0x8A4 + 0x20 + + + APB2OTP_BLOCK3_W1 + Otp block3 word1 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK3_W2 + eFuse apb2otp block3 data register2. + 0x8A8 + 0x20 + + + APB2OTP_BLOCK3_W2 + Otp block3 word2 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK3_W3 + eFuse apb2otp block3 data register3. + 0x8AC + 0x20 + + + APB2OTP_BLOCK3_W3 + Otp block3 word3 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK3_W4 + eFuse apb2otp block3 data register4. + 0x8B0 + 0x20 + + + APB2OTP_BLOCK3_W4 + Otp block3 word4 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK3_W5 + eFuse apb2otp block3 data register5. + 0x8B4 + 0x20 + + + APB2OTP_BLOCK3_W5 + Otp block3 word5 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK3_W6 + eFuse apb2otp block3 data register6. + 0x8B8 + 0x20 + + + APB2OTP_BLOCK3_W6 + Otp block3 word6 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK3_W7 + eFuse apb2otp block3 data register7. + 0x8BC + 0x20 + + + APB2OTP_BLOCK3_W7 + Otp block3 word7 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK3_W8 + eFuse apb2otp block3 data register8. + 0x8C0 + 0x20 + + + APB2OTP_BLOCK3_W8 + Otp block3 word8 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK3_W9 + eFuse apb2otp block3 data register9. + 0x8C4 + 0x20 + + + APB2OTP_BLOCK3_W9 + Otp block3 word9 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK3_W10 + eFuse apb2otp block3 data register10. + 0x8C8 + 0x20 + + + APB2OTP_BLOCK3_W10 + Otp block3 word10 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK3_W11 + eFuse apb2otp block3 data register11. + 0x8CC + 0x20 + + + APB2OTP_BLOCK3_W11 + Otp block3 word11 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK4_W1 + eFuse apb2otp block4 data register1. + 0x8D0 + 0x20 + + + APB2OTP_BLOCK4_W1 + Otp block4 word1 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK4_W2 + eFuse apb2otp block4 data register2. + 0x8D4 + 0x20 + + + APB2OTP_BLOCK4_W2 + Otp block4 word2 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK4_W3 + eFuse apb2otp block4 data register3. + 0x8D8 + 0x20 + + + APB2OTP_BLOCK4_W3 + Otp block4 word3 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK4_W4 + eFuse apb2otp block4 data register4. + 0x8DC + 0x20 + + + APB2OTP_BLOCK4_W4 + Otp block4 word4 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK4_W5 + eFuse apb2otp block4 data register5. + 0x8E0 + 0x20 + + + APB2OTP_BLOCK4_W5 + Otp block4 word5 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK4_W6 + eFuse apb2otp block4 data register6. + 0x8E4 + 0x20 + + + APB2OTP_BLOCK4_W6 + Otp block4 word6 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK4_W7 + eFuse apb2otp block4 data register7. + 0x8E8 + 0x20 + + + APB2OTP_BLOCK4_W7 + Otp block4 word7 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK4_W8 + eFuse apb2otp block4 data register8. + 0x8EC + 0x20 + + + APB2OTP_BLOCK4_W8 + Otp block4 word8 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK4_W9 + eFuse apb2otp block4 data register9. + 0x8F0 + 0x20 + + + APB2OTP_BLOCK4_W9 + Otp block4 word9 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK4_W10 + eFuse apb2otp block4 data registe10. + 0x8F4 + 0x20 + + + APB2OTP_BLOCK4_W10 + Otp block4 word10 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK4_W11 + eFuse apb2otp block4 data register11. + 0x8F8 + 0x20 + + + APB2OTP_BLOCK4_W11 + Otp block4 word11 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK5_W1 + eFuse apb2otp block5 data register1. + 0x8FC + 0x20 + + + APB2OTP_BLOCK5_W1 + Otp block5 word1 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK5_W2 + eFuse apb2otp block5 data register2. + 0x900 + 0x20 + + + APB2OTP_BLOCK5_W2 + Otp block5 word2 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK5_W3 + eFuse apb2otp block5 data register3. + 0x904 + 0x20 + + + APB2OTP_BLOCK5_W3 + Otp block5 word3 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK5_W4 + eFuse apb2otp block5 data register4. + 0x908 + 0x20 + + + APB2OTP_BLOCK5_W4 + Otp block5 word4 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK5_W5 + eFuse apb2otp block5 data register5. + 0x90C + 0x20 + + + APB2OTP_BLOCK5_W5 + Otp block5 word5 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK5_W6 + eFuse apb2otp block5 data register6. + 0x910 + 0x20 + + + APB2OTP_BLOCK5_W6 + Otp block5 word6 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK5_W7 + eFuse apb2otp block5 data register7. + 0x914 + 0x20 + + + APB2OTP_BLOCK5_W7 + Otp block5 word7 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK5_W8 + eFuse apb2otp block5 data register8. + 0x918 + 0x20 + + + APB2OTP_BLOCK5_W8 + Otp block5 word8 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK5_W9 + eFuse apb2otp block5 data register9. + 0x91C + 0x20 + + + APB2OTP_BLOCK5_W9 + Otp block5 word9 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK5_W10 + eFuse apb2otp block5 data register10. + 0x920 + 0x20 + + + APB2OTP_BLOCK5_W10 + Otp block5 word10 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK5_W11 + eFuse apb2otp block5 data register11. + 0x924 + 0x20 + + + APB2OTP_BLOCK5_W11 + Otp block5 word11 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK6_W1 + eFuse apb2otp block6 data register1. + 0x928 + 0x20 + + + APB2OTP_BLOCK6_W1 + Otp block6 word1 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK6_W2 + eFuse apb2otp block6 data register2. + 0x92C + 0x20 + + + APB2OTP_BLOCK6_W2 + Otp block6 word2 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK6_W3 + eFuse apb2otp block6 data register3. + 0x930 + 0x20 + + + APB2OTP_BLOCK6_W3 + Otp block6 word3 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK6_W4 + eFuse apb2otp block6 data register4. + 0x934 + 0x20 + + + APB2OTP_BLOCK6_W4 + Otp block6 word4 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK6_W5 + eFuse apb2otp block6 data register5. + 0x938 + 0x20 + + + APB2OTP_BLOCK6_W5 + Otp block6 word5 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK6_W6 + eFuse apb2otp block6 data register6. + 0x93C + 0x20 + + + APB2OTP_BLOCK6_W6 + Otp block6 word6 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK6_W7 + eFuse apb2otp block6 data register7. + 0x940 + 0x20 + + + APB2OTP_BLOCK6_W7 + Otp block6 word7 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK6_W8 + eFuse apb2otp block6 data register8. + 0x944 + 0x20 + + + APB2OTP_BLOCK6_W8 + Otp block6 word8 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK6_W9 + eFuse apb2otp block6 data register9. + 0x948 + 0x20 + + + APB2OTP_BLOCK6_W9 + Otp block6 word9 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK6_W10 + eFuse apb2otp block6 data register10. + 0x94C + 0x20 + + + APB2OTP_BLOCK6_W10 + Otp block6 word10 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK6_W11 + eFuse apb2otp block6 data register11. + 0x950 + 0x20 + + + APB2OTP_BLOCK6_W11 + Otp block6 word11 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK7_W1 + eFuse apb2otp block7 data register1. + 0x954 + 0x20 + + + APB2OTP_BLOCK7_W1 + Otp block7 word1 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK7_W2 + eFuse apb2otp block7 data register2. + 0x958 + 0x20 + + + APB2OTP_BLOCK7_W2 + Otp block7 word2 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK7_W3 + eFuse apb2otp block7 data register3. + 0x95C + 0x20 + + + APB2OTP_BLOCK7_W3 + Otp block7 word3 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK7_W4 + eFuse apb2otp block7 data register4. + 0x960 + 0x20 + + + APB2OTP_BLOCK7_W4 + Otp block7 word4 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK7_W5 + eFuse apb2otp block7 data register5. + 0x964 + 0x20 + + + APB2OTP_BLOCK7_W5 + Otp block7 word5 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK7_W6 + eFuse apb2otp block7 data register6. + 0x968 + 0x20 + + + APB2OTP_BLOCK7_W6 + Otp block7 word6 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK7_W7 + eFuse apb2otp block7 data register7. + 0x96C + 0x20 + + + APB2OTP_BLOCK7_W7 + Otp block7 word7 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK7_W8 + eFuse apb2otp block7 data register8. + 0x970 + 0x20 + + + APB2OTP_BLOCK7_W8 + Otp block7 word8 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK7_W9 + eFuse apb2otp block7 data register9. + 0x974 + 0x20 + + + APB2OTP_BLOCK7_W9 + Otp block7 word9 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK7_W10 + eFuse apb2otp block7 data register10. + 0x978 + 0x20 + + + APB2OTP_BLOCK7_W10 + Otp block7 word10 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK7_W11 + eFuse apb2otp block7 data register11. + 0x97C + 0x20 + + + APB2OTP_BLOCK7_W11 + Otp block7 word11 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK8_W1 + eFuse apb2otp block8 data register1. + 0x980 + 0x20 + + + APB2OTP_BLOCK8_W1 + Otp block8 word1 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK8_W2 + eFuse apb2otp block8 data register2. + 0x984 + 0x20 + + + APB2OTP_BLOCK8_W2 + Otp block8 word2 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK8_W3 + eFuse apb2otp block8 data register3. + 0x988 + 0x20 + + + APB2OTP_BLOCK8_W3 + Otp block8 word3 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK8_W4 + eFuse apb2otp block8 data register4. + 0x98C + 0x20 + + + APB2OTP_BLOCK8_W4 + Otp block8 word4 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK8_W5 + eFuse apb2otp block8 data register5. + 0x990 + 0x20 + + + APB2OTP_BLOCK8_W5 + Otp block8 word5 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK8_W6 + eFuse apb2otp block8 data register6. + 0x994 + 0x20 + + + APB2OTP_BLOCK8_W6 + Otp block8 word6 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK8_W7 + eFuse apb2otp block8 data register7. + 0x998 + 0x20 + + + APB2OTP_BLOCK8_W7 + Otp block8 word7 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK8_W8 + eFuse apb2otp block8 data register8. + 0x99C + 0x20 + + + APB2OTP_BLOCK8_W8 + Otp block8 word8 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK8_W9 + eFuse apb2otp block8 data register9. + 0x9A0 + 0x20 + + + APB2OTP_BLOCK8_W9 + Otp block8 word9 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK8_W10 + eFuse apb2otp block8 data register10. + 0x9A4 + 0x20 + + + APB2OTP_BLOCK8_W10 + Otp block8 word10 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK8_W11 + eFuse apb2otp block8 data register11. + 0x9A8 + 0x20 + + + APB2OTP_BLOCK8_W11 + Otp block8 word11 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK9_W1 + eFuse apb2otp block9 data register1. + 0x9AC + 0x20 + + + APB2OTP_BLOCK9_W1 + Otp block9 word1 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK9_W2 + eFuse apb2otp block9 data register2. + 0x9B0 + 0x20 + + + APB2OTP_BLOCK9_W2 + Otp block9 word2 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK9_W3 + eFuse apb2otp block9 data register3. + 0x9B4 + 0x20 + + + APB2OTP_BLOCK9_W3 + Otp block9 word3 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK9_W4 + eFuse apb2otp block9 data register4. + 0x9B8 + 0x20 + + + APB2OTP_BLOCK9_W4 + Otp block9 word4 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK9_W5 + eFuse apb2otp block9 data register5. + 0x9BC + 0x20 + + + APB2OTP_BLOCK9_W5 + Otp block9 word5 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK9_W6 + eFuse apb2otp block9 data register6. + 0x9C0 + 0x20 + + + APB2OTP_BLOCK9_W6 + Otp block9 word6 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK9_W7 + eFuse apb2otp block9 data register7. + 0x9C4 + 0x20 + + + APB2OTP_BLOCK9_W7 + Otp block9 word7 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK9_W8 + eFuse apb2otp block9 data register8. + 0x9C8 + 0x20 + + + APB2OTP_BLOCK9_W8 + Otp block9 word8 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK9_W9 + eFuse apb2otp block9 data register9. + 0x9CC + 0x20 + + + APB2OTP_BLOCK9_W9 + Otp block9 word9 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK9_W10 + eFuse apb2otp block9 data register10. + 0x9D0 + 0x20 + + + APB2OTP_BLOCK9_W10 + Otp block9 word10 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK9_W11 + eFuse apb2otp block9 data register11. + 0x9D4 + 0x20 + + + APB2OTP_BLOCK9_W11 + Otp block9 word11 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK10_W1 + eFuse apb2otp block10 data register1. + 0x9D8 + 0x20 + + + APB2OTP_BLOCK10_W1 + Otp block10 word1 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK10_W2 + eFuse apb2otp block10 data register2. + 0x9DC + 0x20 + + + APB2OTP_BLOCK10_W2 + Otp block10 word2 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK10_W3 + eFuse apb2otp block10 data register3. + 0x9E0 + 0x20 + + + APB2OTP_BLOCK10_W3 + Otp block10 word3 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK10_W4 + eFuse apb2otp block10 data register4. + 0x9E4 + 0x20 + + + APB2OTP_BLOCK10_W4 + Otp block10 word4 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK10_W5 + eFuse apb2otp block10 data register5. + 0x9E8 + 0x20 + + + APB2OTP_BLOCK10_W5 + Otp block10 word5 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK10_W6 + eFuse apb2otp block10 data register6. + 0x9EC + 0x20 + + + APB2OTP_BLOCK10_W6 + Otp block10 word6 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK10_W7 + eFuse apb2otp block10 data register7. + 0x9F0 + 0x20 + + + APB2OTP_BLOCK10_W7 + Otp block10 word7 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK10_W8 + eFuse apb2otp block10 data register8. + 0x9F4 + 0x20 + + + APB2OTP_BLOCK10_W8 + Otp block10 word8 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK10_W9 + eFuse apb2otp block10 data register9. + 0x9F8 + 0x20 + + + APB2OTP_BLOCK10_W9 + Otp block10 word9 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK10_W10 + eFuse apb2otp block10 data register10. + 0x9FC + 0x20 + + + APB2OTP_BLOCK19_W10 + Otp block10 word10 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK10_W11 + eFuse apb2otp block10 data register11. + 0xA00 + 0x20 + + + APB2OTP_BLOCK10_W11 + Otp block10 word11 data. + 0 + 32 + read-only + + + + + APB2OTP_EN + eFuse apb2otp enable configuration register. + 0xA08 + 0x20 + + + APB2OTP_APB2OTP_EN + Apb2otp mode enable signal. + 0 + 1 + read-write + + + + + + + GPIO + General Purpose Input/Output + GPIO + 0x500E0000 + + 0x0 + 0x5F8 + registers + + + GPIO_INT0 + 74 + + + GPIO_INT1 + 75 + + + GPIO_INT2 + 76 + + + GPIO_INT3 + 77 + + + GPIO_PAD_COMP + 78 + + + + BT_SELECT + GPIO bit select register + 0x0 + 0x20 + + + BT_SEL + GPIO bit select register + 0 + 32 + read-write + + + + + OUT + GPIO output register for GPIO0-31 + 0x4 + 0x20 + + + DATA_ORIG + GPIO output register for GPIO0-31 + 0 + 32 + read-write + + + + + OUT_W1TS + GPIO output set register for GPIO0-31 + 0x8 + 0x20 + + + OUT_W1TS + GPIO output set register for GPIO0-31 + 0 + 32 + write-only + + + + + OUT_W1TC + GPIO output clear register for GPIO0-31 + 0xC + 0x20 + + + OUT_W1TC + GPIO output clear register for GPIO0-31 + 0 + 32 + write-only + + + + + OUT1 + GPIO output register for GPIO32-56 + 0x10 + 0x20 + + + DATA_ORIG + GPIO output register for GPIO32-56 + 0 + 25 + read-write + + + + + OUT1_W1TS + GPIO output set register for GPIO32-56 + 0x14 + 0x20 + + + OUT1_W1TS + GPIO output set register for GPIO32-56 + 0 + 25 + write-only + + + + + OUT1_W1TC + GPIO output clear register for GPIO32-56 + 0x18 + 0x20 + + + OUT1_W1TC + GPIO output clear register for GPIO32-56 + 0 + 25 + write-only + + + + + ENABLE + GPIO output enable register for GPIO0-31 + 0x20 + 0x20 + + + DATA + GPIO output enable register for GPIO0-31 + 0 + 32 + read-write + + + + + ENABLE_W1TS + GPIO output enable set register for GPIO0-31 + 0x24 + 0x20 + + + ENABLE_W1TS + GPIO output enable set register for GPIO0-31 + 0 + 32 + write-only + + + + + ENABLE_W1TC + GPIO output enable clear register for GPIO0-31 + 0x28 + 0x20 + + + ENABLE_W1TC + GPIO output enable clear register for GPIO0-31 + 0 + 32 + write-only + + + + + ENABLE1 + GPIO output enable register for GPIO32-56 + 0x2C + 0x20 + + + DATA + GPIO output enable register for GPIO32-56 + 0 + 25 + read-write + + + + + ENABLE1_W1TS + GPIO output enable set register for GPIO32-56 + 0x30 + 0x20 + + + ENABLE1_W1TS + GPIO output enable set register for GPIO32-56 + 0 + 25 + write-only + + + + + ENABLE1_W1TC + GPIO output enable clear register for GPIO32-56 + 0x34 + 0x20 + + + ENABLE1_W1TC + GPIO output enable clear register for GPIO32-56 + 0 + 25 + write-only + + + + + STRAP + pad strapping register + 0x38 + 0x20 + + + STRAPPING + pad strapping register + 0 + 16 + read-only + + + + + IN + GPIO input register for GPIO0-31 + 0x3C + 0x20 + + + DATA_NEXT + GPIO input register for GPIO0-31 + 0 + 32 + read-only + + + + + IN1 + GPIO input register for GPIO32-56 + 0x40 + 0x20 + + + DATA_NEXT + GPIO input register for GPIO32-56 + 0 + 25 + read-only + + + + + STATUS + GPIO interrupt status register for GPIO0-31 + 0x44 + 0x20 + + + INTERRUPT + GPIO interrupt status register for GPIO0-31 + 0 + 32 + read-write + + + + + STATUS_W1TS + GPIO interrupt status set register for GPIO0-31 + 0x48 + 0x20 + + + STATUS_W1TS + GPIO interrupt status set register for GPIO0-31 + 0 + 32 + write-only + + + + + STATUS_W1TC + GPIO interrupt status clear register for GPIO0-31 + 0x4C + 0x20 + + + STATUS_W1TC + GPIO interrupt status clear register for GPIO0-31 + 0 + 32 + write-only + + + + + STATUS1 + GPIO interrupt status register for GPIO32-56 + 0x50 + 0x20 + + + INTERRUPT + GPIO interrupt status register for GPIO32-56 + 0 + 25 + read-write + + + + + STATUS1_W1TS + GPIO interrupt status set register for GPIO32-56 + 0x54 + 0x20 + + + STATUS1_W1TS + GPIO interrupt status set register for GPIO32-56 + 0 + 25 + write-only + + + + + STATUS1_W1TC + GPIO interrupt status clear register for GPIO32-56 + 0x58 + 0x20 + + + STATUS1_W1TC + GPIO interrupt status clear register for GPIO32-56 + 0 + 25 + write-only + + + + + INTR_0 + GPIO interrupt 0 status register for GPIO0-31 + 0x5C + 0x20 + + + INT_0 + GPIO interrupt 0 status register for GPIO0-31 + 0 + 32 + read-only + + + + + INTR1_0 + GPIO interrupt 0 status register for GPIO32-56 + 0x60 + 0x20 + + + INT1_0 + GPIO interrupt 0 status register for GPIO32-56 + 0 + 25 + read-only + + + + + INTR_1 + GPIO interrupt 1 status register for GPIO0-31 + 0x64 + 0x20 + + + INT_1 + GPIO interrupt 1 status register for GPIO0-31 + 0 + 32 + read-only + + + + + INTR1_1 + GPIO interrupt 1 status register for GPIO32-56 + 0x68 + 0x20 + + + INT1_1 + GPIO interrupt 1 status register for GPIO32-56 + 0 + 25 + read-only + + + + + STATUS_NEXT + GPIO interrupt source register for GPIO0-31 + 0x6C + 0x20 + + + STATUS_INTERRUPT_NEXT + GPIO interrupt source register for GPIO0-31 + 0 + 32 + read-only + + + + + STATUS_NEXT1 + GPIO interrupt source register for GPIO32-56 + 0x70 + 0x20 + + + STATUS_INTERRUPT_NEXT1 + GPIO interrupt source register for GPIO32-56 + 0 + 25 + read-only + + + + + 57 + 0x4 + PIN%s + GPIO pin configuration register + 0x74 + 0x20 + + + SYNC2_BYPASS + set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge. + 0 + 2 + read-write + + + PAD_DRIVER + set this bit to select pad driver. 1:open-drain. 0:normal. + 2 + 1 + read-write + + + SYNC1_BYPASS + set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge. + 3 + 2 + read-write + + + INT_TYPE + set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid at high level + 7 + 3 + read-write + + + WAKEUP_ENABLE + set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + 10 + 1 + read-write + + + CONFIG + reserved + 11 + 2 + read-write + + + INT_ENA + set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) interrupt. + 13 + 5 + read-write + + + + + 57 + 0x4 + FUNC%s_OUT_SEL_CFG + GPIO output function select register + 0x558 + 0x20 + 0x00000100 + + + OUT_SEL + The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. + 0 + 9 + read-write + + + INV_SEL + set this bit to invert output signal.1:invert.0:not invert. + 9 + 1 + read-write + + + OEN_SEL + set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output enable signal.0:use peripheral output enable signal. + 10 + 1 + read-write + + + OEN_INV_SEL + set this bit to invert output enable signal.1:invert.0:not invert. + 11 + 1 + read-write + + + + + INTR_2 + GPIO interrupt 2 status register for GPIO0-31 + 0x63C + 0x20 + + + INT_2 + GPIO interrupt 2 status register for GPIO0-31 + 0 + 32 + read-only + + + + + INTR1_2 + GPIO interrupt 2 status register for GPIO32-56 + 0x640 + 0x20 + + + INT1_2 + GPIO interrupt 2 status register for GPIO32-56 + 0 + 25 + read-only + + + + + INTR_3 + GPIO interrupt 3 status register for GPIO0-31 + 0x644 + 0x20 + + + INT_3 + GPIO interrupt 3 status register for GPIO0-31 + 0 + 32 + read-only + + + + + INTR1_3 + GPIO interrupt 3 status register for GPIO32-56 + 0x648 + 0x20 + + + INT1_3 + GPIO interrupt 3 status register for GPIO32-56 + 0 + 25 + read-only + + + + + CLOCK_GATE + GPIO clock gate register + 0x64C + 0x20 + 0x00000001 + + + CLK_EN + set this bit to enable GPIO clock gate + 0 + 1 + read-write + + + + + INT_RAW + analog comparator interrupt raw + 0x700 + 0x20 + + + COMP0_NEG_INT_RAW + analog comparator pos edge interrupt raw + 0 + 1 + read-write + + + COMP0_POS_INT_RAW + analog comparator neg edge interrupt raw + 1 + 1 + read-write + + + COMP0_ALL_INT_RAW + analog comparator neg or pos edge interrupt raw + 2 + 1 + read-write + + + COMP1_NEG_INT_RAW + analog comparator pos edge interrupt raw + 3 + 1 + read-write + + + COMP1_POS_INT_RAW + analog comparator neg edge interrupt raw + 4 + 1 + read-write + + + COMP1_ALL_INT_RAW + analog comparator neg or pos edge interrupt raw + 5 + 1 + read-write + + + BISTOK_INT_RAW + pad bistok interrupt raw + 6 + 1 + read-write + + + BISTFAIL_INT_RAW + pad bistfail interrupt raw + 7 + 1 + read-write + + + + + INT_ST + analog comparator interrupt status + 0x704 + 0x20 + + + COMP0_NEG_INT_ST + analog comparator pos edge interrupt status + 0 + 1 + read-only + + + COMP0_POS_INT_ST + analog comparator neg edge interrupt status + 1 + 1 + read-only + + + COMP0_ALL_INT_ST + analog comparator neg or pos edge interrupt status + 2 + 1 + read-only + + + COMP1_NEG_INT_ST + analog comparator pos edge interrupt status + 3 + 1 + read-only + + + COMP1_POS_INT_ST + analog comparator neg edge interrupt status + 4 + 1 + read-only + + + COMP1_ALL_INT_ST + analog comparator neg or pos edge interrupt status + 5 + 1 + read-only + + + BISTOK_INT_ST + pad bistok interrupt status + 6 + 1 + read-only + + + BISTFAIL_INT_ST + pad bistfail interrupt status + 7 + 1 + read-only + + + + + INT_ENA + analog comparator interrupt enable + 0x708 + 0x20 + 0x000000FF + + + COMP0_NEG_INT_ENA + analog comparator pos edge interrupt enable + 0 + 1 + read-write + + + COMP0_POS_INT_ENA + analog comparator neg edge interrupt enable + 1 + 1 + read-write + + + COMP0_ALL_INT_ENA + analog comparator neg or pos edge interrupt enable + 2 + 1 + read-write + + + COMP1_NEG_INT_ENA + analog comparator pos edge interrupt enable + 3 + 1 + read-write + + + COMP1_POS_INT_ENA + analog comparator neg edge interrupt enable + 4 + 1 + read-write + + + COMP1_ALL_INT_ENA + analog comparator neg or pos edge interrupt enable + 5 + 1 + read-write + + + BISTOK_INT_ENA + pad bistok interrupt enable + 6 + 1 + read-write + + + BISTFAIL_INT_ENA + pad bistfail interrupt enable + 7 + 1 + read-write + + + + + INT_CLR + analog comparator interrupt clear + 0x70C + 0x20 + + + COMP0_NEG_INT_CLR + analog comparator pos edge interrupt clear + 0 + 1 + write-only + + + COMP0_POS_INT_CLR + analog comparator neg edge interrupt clear + 1 + 1 + write-only + + + COMP0_ALL_INT_CLR + analog comparator neg or pos edge interrupt clear + 2 + 1 + write-only + + + COMP1_NEG_INT_CLR + analog comparator pos edge interrupt clear + 3 + 1 + write-only + + + COMP1_POS_INT_CLR + analog comparator neg edge interrupt clear + 4 + 1 + write-only + + + COMP1_ALL_INT_CLR + analog comparator neg or pos edge interrupt clear + 5 + 1 + write-only + + + BISTOK_INT_CLR + pad bistok interrupt enable + 6 + 1 + write-only + + + BISTFAIL_INT_CLR + pad bistfail interrupt enable + 7 + 1 + write-only + + + + + ZERO_DET0_FILTER_CNT + GPIO analog comparator zero detect filter count + 0x710 + 0x20 + 0xFFFFFFFF + + + ZERO_DET0_FILTER_CNT + GPIO analog comparator zero detect filter count + 0 + 32 + read-write + + + + + ZERO_DET1_FILTER_CNT + GPIO analog comparator zero detect filter count + 0x714 + 0x20 + 0xFFFFFFFF + + + ZERO_DET1_FILTER_CNT + GPIO analog comparator zero detect filter count + 0 + 32 + read-write + + + + + SEND_SEQ + High speed sdio pad bist send sequence + 0x718 + 0x20 + 0x12345678 + + + SEND_SEQ + High speed sdio pad bist send sequence + 0 + 32 + read-write + + + + + RECIVE_SEQ + High speed sdio pad bist recive sequence + 0x71C + 0x20 + + + RECIVE_SEQ + High speed sdio pad bist recive sequence + 0 + 32 + read-only + + + + + BISTIN_SEL + High speed sdio pad bist in pad sel + 0x720 + 0x20 + 0x0000000F + + + BISTIN_SEL + High speed sdio pad bist in pad sel 0:pad39, 1: pad40... + 0 + 4 + read-write + + + + + BIST_CTRL + High speed sdio pad bist control + 0x724 + 0x20 + 0x00000001 + + + BIST_PAD_OE + High speed sdio pad bist out pad oe + 0 + 1 + read-write + + + BIST_START + High speed sdio pad bist start + 1 + 1 + write-only + + + + + DATE + GPIO version register + 0x7FC + 0x20 + 0x00230403 + + + DATE + version register + 0 + 28 + read-write + + + + + 254 + 0x4 + 1-254 + FUNC%s_IN_SEL_CFG + GPIO input function configuration register + 0x15C + 0x20 + read-write + + + IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + + + IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + + + SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + + + + + + + GPIO_SD + Sigma-Delta Modulation + GPIOSD + 0x500E0F00 + + 0x0 + 0xA4 + registers + + + + 8 + 0x4 + SIGMADELTA%s + Duty Cycle Configure Register of SDM%s + 0x0 + 0x20 + 0x0000FF00 + + + SD_IN + This field is used to configure the duty cycle of sigma delta modulation output. + 0 + 8 + read-write + + + SD_PRESCALE + This field is used to set a divider value to divide APB clock. + 8 + 8 + read-write + + + + + CLOCK_GATE + Clock Gating Configure Register + 0x20 + 0x20 + + + CLK_EN + Clock enable bit of configuration registers for sigma delta modulation. + 0 + 1 + read-write + + + + + SIGMADELTA_MISC + MISC Register + 0x24 + 0x20 + + + FUNCTION_CLK_EN + Clock enable bit of sigma delta modulation. + 30 + 1 + read-write + + + SPI_SWAP + Reserved. + 31 + 1 + read-write + + + + + 8 + 0x4 + GLITCH_FILTER_CH%s + Glitch Filter Configure Register of Channel%s + 0x30 + 0x20 + + + FILTER_CH0_EN + Glitch Filter channel enable bit. + 0 + 1 + read-write + + + FILTER_CH0_INPUT_IO_NUM + Glitch Filter input io number. + 1 + 6 + read-write + + + FILTER_CH0_WINDOW_THRES + Glitch Filter window threshold. + 7 + 6 + read-write + + + FILTER_CH0_WINDOW_WIDTH + Glitch Filter window width. + 13 + 6 + read-write + + + + + 8 + 0x4 + ETM_EVENT_CH%s_CFG + Etm Config register of Channel%s + 0x60 + 0x20 + + + ETM_CH0_EVENT_SEL + Etm event channel select gpio. + 0 + 6 + read-write + + + ETM_CH0_EVENT_EN + Etm event send enable bit. + 7 + 1 + read-write + + + + + ETM_TASK_P0_CFG + Etm Configure Register to decide which GPIO been chosen + 0xA0 + 0x20 + + + ETM_TASK_GPIO0_EN + Enable bit of GPIO response etm task. + 0 + 1 + read-write + + + ETM_TASK_GPIO0_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO1_EN + Enable bit of GPIO response etm task. + 8 + 1 + read-write + + + ETM_TASK_GPIO1_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write + + + ETM_TASK_GPIO2_EN + Enable bit of GPIO response etm task. + 16 + 1 + read-write + + + ETM_TASK_GPIO2_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO3_EN + Enable bit of GPIO response etm task. + 24 + 1 + read-write + + + ETM_TASK_GPIO3_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + + + + + ETM_TASK_P1_CFG + Etm Configure Register to decide which GPIO been chosen + 0xA4 + 0x20 + + + ETM_TASK_GPIO4_EN + Enable bit of GPIO response etm task. + 0 + 1 + read-write + + + ETM_TASK_GPIO4_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO5_EN + Enable bit of GPIO response etm task. + 8 + 1 + read-write + + + ETM_TASK_GPIO5_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write + + + ETM_TASK_GPIO6_EN + Enable bit of GPIO response etm task. + 16 + 1 + read-write + + + ETM_TASK_GPIO6_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO7_EN + Enable bit of GPIO response etm task. + 24 + 1 + read-write + + + ETM_TASK_GPIO7_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + + + + + ETM_TASK_P2_CFG + Etm Configure Register to decide which GPIO been chosen + 0xA8 + 0x20 + + + ETM_TASK_GPIO8_EN + Enable bit of GPIO response etm task. + 0 + 1 + read-write + + + ETM_TASK_GPIO8_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO9_EN + Enable bit of GPIO response etm task. + 8 + 1 + read-write + + + ETM_TASK_GPIO9_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write + + + ETM_TASK_GPIO10_EN + Enable bit of GPIO response etm task. + 16 + 1 + read-write + + + ETM_TASK_GPIO10_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO11_EN + Enable bit of GPIO response etm task. + 24 + 1 + read-write + + + ETM_TASK_GPIO11_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + + + + + ETM_TASK_P3_CFG + Etm Configure Register to decide which GPIO been chosen + 0xAC + 0x20 + + + ETM_TASK_GPIO12_EN + Enable bit of GPIO response etm task. + 0 + 1 + read-write + + + ETM_TASK_GPIO12_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO13_EN + Enable bit of GPIO response etm task. + 8 + 1 + read-write + + + ETM_TASK_GPIO13_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write + + + ETM_TASK_GPIO14_EN + Enable bit of GPIO response etm task. + 16 + 1 + read-write + + + ETM_TASK_GPIO14_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO15_EN + Enable bit of GPIO response etm task. + 24 + 1 + read-write + + + ETM_TASK_GPIO15_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + + + + + ETM_TASK_P4_CFG + Etm Configure Register to decide which GPIO been chosen + 0xB0 + 0x20 + + + ETM_TASK_GPIO16_EN + Enable bit of GPIO response etm task. + 0 + 1 + read-write + + + ETM_TASK_GPIO16_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO17_EN + Enable bit of GPIO response etm task. + 8 + 1 + read-write + + + ETM_TASK_GPIO17_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write + + + ETM_TASK_GPIO18_EN + Enable bit of GPIO response etm task. + 16 + 1 + read-write + + + ETM_TASK_GPIO18_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO19_EN + Enable bit of GPIO response etm task. + 24 + 1 + read-write + + + ETM_TASK_GPIO19_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + + + + + ETM_TASK_P5_CFG + Etm Configure Register to decide which GPIO been chosen + 0xB4 + 0x20 + + + ETM_TASK_GPIO20_EN + Enable bit of GPIO response etm task. + 0 + 1 + read-write + + + ETM_TASK_GPIO20_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO21_EN + Enable bit of GPIO response etm task. + 8 + 1 + read-write + + + ETM_TASK_GPIO21_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write + + + ETM_TASK_GPIO22_EN + Enable bit of GPIO response etm task. + 16 + 1 + read-write + + + ETM_TASK_GPIO22_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO23_EN + Enable bit of GPIO response etm task. + 24 + 1 + read-write + + + ETM_TASK_GPIO23_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + + + + + ETM_TASK_P6_CFG + Etm Configure Register to decide which GPIO been chosen + 0xB8 + 0x20 + + + ETM_TASK_GPIO24_EN + Enable bit of GPIO response etm task. + 0 + 1 + read-write + + + ETM_TASK_GPIO24_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO25_EN + Enable bit of GPIO response etm task. + 8 + 1 + read-write + + + ETM_TASK_GPIO25_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write + + + ETM_TASK_GPIO26_EN + Enable bit of GPIO response etm task. + 16 + 1 + read-write + + + ETM_TASK_GPIO26_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO27_EN + Enable bit of GPIO response etm task. + 24 + 1 + read-write + + + ETM_TASK_GPIO27_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + + + + + ETM_TASK_P7_CFG + Etm Configure Register to decide which GPIO been chosen + 0xBC + 0x20 + + + ETM_TASK_GPIO28_EN + Enable bit of GPIO response etm task. + 0 + 1 + read-write + + + ETM_TASK_GPIO28_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO29_EN + Enable bit of GPIO response etm task. + 8 + 1 + read-write + + + ETM_TASK_GPIO29_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write + + + ETM_TASK_GPIO30_EN + Enable bit of GPIO response etm task. + 16 + 1 + read-write + + + ETM_TASK_GPIO30_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO31_EN + Enable bit of GPIO response etm task. + 24 + 1 + read-write + + + ETM_TASK_GPIO31_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + + + + + ETM_TASK_P8_CFG + Etm Configure Register to decide which GPIO been chosen + 0xC0 + 0x20 + + + ETM_TASK_GPIO32_EN + Enable bit of GPIO response etm task. + 0 + 1 + read-write + + + ETM_TASK_GPIO32_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO33_EN + Enable bit of GPIO response etm task. + 8 + 1 + read-write + + + ETM_TASK_GPIO33_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write + + + ETM_TASK_GPIO34_EN + Enable bit of GPIO response etm task. + 16 + 1 + read-write + + + ETM_TASK_GPIO34_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO35_EN + Enable bit of GPIO response etm task. + 24 + 1 + read-write + + + ETM_TASK_GPIO35_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + + + + + ETM_TASK_P9_CFG + Etm Configure Register to decide which GPIO been chosen + 0xC4 + 0x20 + + + ETM_TASK_GPIO36_EN + Enable bit of GPIO response etm task. + 0 + 1 + read-write + + + ETM_TASK_GPIO36_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO37_EN + Enable bit of GPIO response etm task. + 8 + 1 + read-write + + + ETM_TASK_GPIO37_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write + + + ETM_TASK_GPIO38_EN + Enable bit of GPIO response etm task. + 16 + 1 + read-write + + + ETM_TASK_GPIO38_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO39_EN + Enable bit of GPIO response etm task. + 24 + 1 + read-write + + + ETM_TASK_GPIO39_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + + + + + ETM_TASK_P10_CFG + Etm Configure Register to decide which GPIO been chosen + 0xC8 + 0x20 + + + ETM_TASK_GPIO40_EN + Enable bit of GPIO response etm task. + 0 + 1 + read-write + + + ETM_TASK_GPIO40_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO41_EN + Enable bit of GPIO response etm task. + 8 + 1 + read-write + + + ETM_TASK_GPIO41_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write + + + ETM_TASK_GPIO42_EN + Enable bit of GPIO response etm task. + 16 + 1 + read-write + + + ETM_TASK_GPIO42_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO43_EN + Enable bit of GPIO response etm task. + 24 + 1 + read-write + + + ETM_TASK_GPIO43_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + + + + + ETM_TASK_P11_CFG + Etm Configure Register to decide which GPIO been chosen + 0xCC + 0x20 + + + ETM_TASK_GPIO44_EN + Enable bit of GPIO response etm task. + 0 + 1 + read-write + + + ETM_TASK_GPIO44_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO45_EN + Enable bit of GPIO response etm task. + 8 + 1 + read-write + + + ETM_TASK_GPIO45_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write + + + ETM_TASK_GPIO46_EN + Enable bit of GPIO response etm task. + 16 + 1 + read-write + + + ETM_TASK_GPIO46_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO47_EN + Enable bit of GPIO response etm task. + 24 + 1 + read-write + + + ETM_TASK_GPIO47_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + + + + + ETM_TASK_P12_CFG + Etm Configure Register to decide which GPIO been chosen + 0xD0 + 0x20 + + + ETM_TASK_GPIO48_EN + Enable bit of GPIO response etm task. + 0 + 1 + read-write + + + ETM_TASK_GPIO48_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO49_EN + Enable bit of GPIO response etm task. + 8 + 1 + read-write + + + ETM_TASK_GPIO49_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write + + + ETM_TASK_GPIO50_EN + Enable bit of GPIO response etm task. + 16 + 1 + read-write + + + ETM_TASK_GPIO50_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO51_EN + Enable bit of GPIO response etm task. + 24 + 1 + read-write + + + ETM_TASK_GPIO51_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + + + + + ETM_TASK_P13_CFG + Etm Configure Register to decide which GPIO been chosen + 0xD4 + 0x20 + + + ETM_TASK_GPIO52_EN + Enable bit of GPIO response etm task. + 0 + 1 + read-write + + + ETM_TASK_GPIO52_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO53_EN + Enable bit of GPIO response etm task. + 8 + 1 + read-write + + + ETM_TASK_GPIO53_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write + + + ETM_TASK_GPIO54_EN + Enable bit of GPIO response etm task. + 16 + 1 + read-write + + + ETM_TASK_GPIO54_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + + + VERSION + Version Control Register + 0xFC + 0x20 + 0x02203050 + + + GPIO_SD_DATE + Version control register. + 0 + 28 + read-write + + + + + + + H264 + H264 Encoder (Core) + H264 + 0x50084000 + + 0x0 + 0xF4 + registers + + + H264_REG + 126 + + + + SYS_CTRL + H264 system level control register. + 0x0 + 0x20 + + + FRAME_START + Configures whether or not to start encoding one frame.\\0: Invalid. No effect\\1: Start encoding one frame + 0 + 1 + write-only + + + DMA_MOVE_START + Configures whether or not to start moving reference data from external mem.\\0: Invalid. No effect\\1: H264 start moving two MB lines of reference frame from external mem to internal mem + 1 + 1 + write-only + + + FRAME_MODE + Configures H264 running mode. When field H264_DUAL_STREAM_MODE is set to 1, this field must be set to 1 too.\\0: GOP mode. Before every GOP first frame start, need reconfig reference frame DMA\\1: Frame mode. Before every frame start, need reconfig reference frame DMA + 2 + 1 + read-write + + + SYS_RST_PULSE + Configures whether or not to reset H264 ip.\\0: Invalid. No effect\\1: Reset H264 ip + 3 + 1 + write-only + + + + + GOP_CONF + GOP related configuration register. + 0x4 + 0x20 + + + DUAL_STREAM_MODE + Configures whether or not to enable dual stream mode. When this field is set to 1, H264_FRAME_MODE field must be set to 1 too.\\0: Normal mode\\1: Dual stream mode + 0 + 1 + read-write + + + GOP_NUM + Configures the frame number of one GOP.\\0: The frame number of one GOP is infinite\\Others: Actual frame number of one GOP + 1 + 8 + read-write + + + + + A_SYS_MB_RES + Video A horizontal and vertical MB resolution register. + 0x8 + 0x20 + + + A_SYS_TOTAL_MB_Y + Configures video A vertical MB resolution. + 0 + 7 + read-write + + + A_SYS_TOTAL_MB_X + Configures video A horizontal MB resolution. + 7 + 7 + read-write + + + + + A_SYS_CONF + Video A system level configuration register. + 0xC + 0x20 + 0x00000203 + + + A_DB_TMP_READY_TRIGGER_MB_NUM + Configures when to trigger video A H264_DB_TMP_READY_INT. When the (MB number of written db temp+1) is greater than this filed in first MB line, trigger H264_DB_TMP_READY_INT. Min is 3. + 0 + 7 + read-write + + + A_REC_READY_TRIGGER_MB_LINES + Configures when to trigger video A H264_REC_READY_INT. When the MB line number of generated reconstruct pixel is greater than this filed, trigger H264_REC_READY_INT. Min is 4. + 7 + 7 + read-write + + + A_INTRA_COST_CMP_OFFSET + Configures video A intra cost offset when I MB compared with P MB. + 14 + 16 + read-write + + + + + A_DECI_SCORE + Video A luma and chroma MB decimate score Register. + 0x10 + 0x20 + + + A_C_DECI_SCORE + Configures video A chroma MB decimate score. When chroma score is smaller than it, chroma decimate will be enable. + 0 + 10 + read-write + + + A_L_DECI_SCORE + Configures video A luma MB decimate score. When luma score is smaller than it, luma decimate will be enable. + 10 + 10 + read-write + + + + + A_DECI_SCORE_OFFSET + Video A luma and chroma MB decimate score offset Register. + 0x14 + 0x20 + + + A_I16X16_DECI_SCORE_OFFSET + Configures video A i16x16 MB decimate score offset. This offset will be added to i16x16 MB score. + 0 + 6 + read-write + + + A_I_CHROMA_DECI_SCORE_OFFSET + Configures video A I chroma MB decimate score offset. This offset will be added to I chroma MB score. + 6 + 6 + read-write + + + A_P16X16_DECI_SCORE_OFFSET + Configures video A p16x16 MB decimate score offset. This offset will be added to p16x16 MB score. + 12 + 6 + read-write + + + A_P_CHROMA_DECI_SCORE_OFFSET + Configures video A p chroma MB decimate score offset. This offset will be added to p chroma MB score. + 18 + 6 + read-write + + + + + A_RC_CONF0 + Video A rate control configuration register0. + 0x18 + 0x20 + + + A_QP + Configures video A frame level initial luma QP value. + 0 + 6 + read-write + + + A_RATE_CTRL_U + Configures video A parameter U value. U = int((float) u << 8). + 6 + 16 + read-write + + + A_MB_RATE_CTRL_EN + Configures video A whether or not to open macro block rate ctrl.\\1:Open the macro block rate ctrl\\1:Close the macro block rate ctrl. + 22 + 1 + read-write + + + + + A_RC_CONF1 + Video A rate control configuration register1. + 0x1C + 0x20 + + + A_CHROMA_DC_QP_DELTA + Configures video A chroma DC QP offset based on Chroma QP. Chroma DC QP = Chroma QP(after map) + reg_chroma_dc_qp_delta. + 0 + 3 + read-write + + + A_CHROMA_QP_DELTA + Configures video A chroma QP offset based on luma QP. Chroma QP(before map) = Luma QP + reg_chroma_qp_delta. + 3 + 4 + read-write + + + A_QP_MIN + Configures video A allowed luma QP min value. + 7 + 6 + read-write + + + A_QP_MAX + Configures video A allowed luma QP max value. + 13 + 6 + read-write + + + A_MAD_FRAME_PRED + Configures vdieo A frame level predicted MB MAD value. + 19 + 12 + read-write + + + + + A_DB_BYPASS + Video A Deblocking bypass register + 0x20 + 0x20 + + + A_BYPASS_DB_FILTER + Configures whether or not to bypass video A deblcoking filter. \\0: Open the deblock filter\\1: Close the deblock filter + 0 + 1 + read-write + + + + + A_ROI_REGION0 + Video A H264 ROI region0 range configure register. + 0x24 + 0x20 + + + X + Configures the horizontal start macroblocks of region 0 in Video A. + 0 + 7 + read-write + + + Y + Configures the vertical start macroblocks of region 0 in Video A. + 7 + 7 + read-write + + + X_LEN + Configures the number of macroblocks in horizontal direction of the region 0 in Video A. + 14 + 7 + read-write + + + Y_LEN + Configures the number of macroblocks in vertical direction of the region 0 in Video A. + 21 + 7 + read-write + + + EN + Configures whether or not to open Video A ROI of region 0 .\\0:Close ROI\\1:Open ROI. + 28 + 1 + read-write + + + + + A_ROI_REGION1 + Video A H264 ROI region1 range configure register. + 0x28 + 0x20 + + + X + Configures the horizontal start macroblocks of region 1 in Video A. + 0 + 7 + read-write + + + Y + Configures the vertical start macroblocks of region 1 in Video A. + 7 + 7 + read-write + + + X_LEN + Configures the number of macroblocks in horizontal direction of the region 1 in Video A. + 14 + 7 + read-write + + + Y_LEN + Configures the number of macroblocks in vertical direction of the region 1 in Video A. + 21 + 7 + read-write + + + EN + Configures whether or not to open Video A ROI of region 1 .\\0:Close ROI\\1:Open ROI. + 28 + 1 + read-write + + + + + A_ROI_REGION2 + Video A H264 ROI region2 range configure register. + 0x2C + 0x20 + + + X + Configures the horizontal start macroblocks of region 2 in Video A. + 0 + 7 + read-write + + + Y + Configures the vertical start macroblocks of region 2 in Video A. + 7 + 7 + read-write + + + X_LEN + Configures the number of macroblocks in horizontal direction of the region 2 in Video A. + 14 + 7 + read-write + + + Y_LEN + Configures the number of macroblocks in vertical direction of the region 2 in Video A. + 21 + 7 + read-write + + + EN + Configures whether or not to open Video A ROI of region 2 .\\0:Close ROI\\1:Open ROI. + 28 + 1 + read-write + + + + + A_ROI_REGION3 + Video A H264 ROI region3 range configure register. + 0x30 + 0x20 + + + X + Configures the horizontal start macroblocks of region 3 in Video A. + 0 + 7 + read-write + + + Y + Configures the vertical start macroblocks of region 3 in Video A. + 7 + 7 + read-write + + + X_LEN + Configures the number of macroblocks in horizontal direction of the region 3 in video A. + 14 + 7 + read-write + + + Y_LEN + Configures the number of macroblocks in vertical direction of the region 3 in video A. + 21 + 7 + read-write + + + EN + Configures whether or not to open Video A ROI of region 3 .\\0:Close ROI\\1:Open ROI. + 28 + 1 + read-write + + + + + A_ROI_REGION4 + Video A H264 ROI region4 range configure register. + 0x34 + 0x20 + + + X + Configures the horizontal start macroblocks of region 4 in Video A. + 0 + 7 + read-write + + + Y + Configures the vertical start macroblocks of region 4 in Video A. + 7 + 7 + read-write + + + X_LEN + Configures the number of macroblocks in horizontal direction of the region 4 in video A. + 14 + 7 + read-write + + + Y_LEN + Configures the number of macroblocks in vertical direction of the region 4 in video A. + 21 + 7 + read-write + + + EN + Configures whether or not to open Video A ROI of region 4 .\\0:Close ROI\\1:Open ROI. + 28 + 1 + read-write + + + + + A_ROI_REGION5 + Video A H264 ROI region5 range configure register. + 0x38 + 0x20 + + + X + Configures the horizontial start macroblocks of region 5 video A. + 0 + 7 + read-write + + + Y + Configures the vertical start macroblocks of region 5 video A. + 7 + 7 + read-write + + + X_LEN + Configures the number of macroblocks in horizontal direction of the region 5 video A. + 14 + 7 + read-write + + + Y_LEN + Configures the number of macroblocks in vertical direction of the region 5 in video A. + 21 + 7 + read-write + + + EN + Configures whether or not to open Video A ROI of region 5 .\\0:Close ROI\\1:Open ROI. + 28 + 1 + read-write + + + + + A_ROI_REGION6 + Video A H264 ROI region6 range configure register. + 0x3C + 0x20 + + + X + Configures the horizontial start macroblocks of region 6 video A. + 0 + 7 + read-write + + + Y + Configures the vertical start macroblocks of region 6 in video A. + 7 + 7 + read-write + + + X_LEN + Configures the number of macroblocks in horizontal direction of the region 6 in video A. + 14 + 7 + read-write + + + Y_LEN + Configures the number of macroblocks in vertical direction of the region 6 in video A. + 21 + 7 + read-write + + + EN + Configures whether or not to open Video A ROI of region 6 .\\0:Close ROI\\1:Open ROI. + 28 + 1 + read-write + + + + + A_ROI_REGION7 + Video A H264 ROI region7 range configure register. + 0x40 + 0x20 + + + X + Configures the horizontal start macroblocks of region 7 in video A. + 0 + 7 + read-write + + + Y + Configures the vertical start macroblocks of region 7 in video A. + 7 + 7 + read-write + + + X_LEN + Configures the number of macroblocks in horizontal direction of the region 7 in video A. + 14 + 7 + read-write + + + Y_LEN + Configures the number of macroblocks in vertical direction of the region 7 in video A. + 21 + 7 + read-write + + + EN + Configures whether or not to open Video A ROI of region 7 .\\0:Close ROI\\1:Open ROI. + 28 + 1 + read-write + + + + + A_ROI_REGION0_3_QP + Video A H264 ROI region0, region1,region2,region3 QP register. + 0x44 + 0x20 + + + A_ROI_REGION0_QP + Configure H264 ROI region0 qp in video A,fixed qp or delta qp. + 0 + 7 + read-write + + + A_ROI_REGION1_QP + Configure H264 ROI region1 qp in video A,fixed qp or delta qp. + 7 + 7 + read-write + + + A_ROI_REGION2_QP + Configure H264 ROI region2 qp in video A,fixed qp or delta qp. + 14 + 7 + read-write + + + A_ROI_REGION3_QP + Configure H264 ROI region3 qp in video A,fixed qp or delta qp. + 21 + 7 + read-write + + + + + A_ROI_REGION4_7_QP + Video A H264 ROI region4, region5,region6,region7 QP register. + 0x48 + 0x20 + + + A_ROI_REGION4_QP + Configure H264 ROI region4 qp in video A,fixed qp or delta qp. + 0 + 7 + read-write + + + A_ROI_REGION5_QP + Configure H264 ROI region5 qp in video A,fixed qp or delta qp. + 7 + 7 + read-write + + + A_ROI_REGION6_QP + Configure H264 ROI region6 qp in video A,fixed qp or delta qp. + 14 + 7 + read-write + + + A_ROI_REGION7_QP + Configure H264 ROI region7 qp in video A,fixed qp or delta qp. + 21 + 7 + read-write + + + + + A_NO_ROI_REGION_QP_OFFSET + Video A H264 no roi region QP register. + 0x4C + 0x20 + + + A_NO_ROI_REGION_QP + Configure H264 no region qp in video A, delta qp. + 0 + 7 + read-write + + + + + A_ROI_CONFIG + Video A H264 ROI configure register. + 0x50 + 0x20 + + + A_ROI_EN + Configure whether or not to enable ROI in video A.\\0:not enable ROI\\1:enable ROI. + 0 + 1 + read-write + + + A_ROI_MODE + Configure the mode of ROI in video A.\\0:fixed qp\\1:delta qp. + 1 + 1 + read-write + + + + + B_SYS_MB_RES + Video B horizontal and vertical MB resolution register. + 0x54 + 0x20 + + + B_SYS_TOTAL_MB_Y + Configures video B vertical MB resolution. + 0 + 7 + read-write + + + B_SYS_TOTAL_MB_X + Configures video B horizontal MB resolution. + 7 + 7 + read-write + + + + + B_SYS_CONF + Video B system level configuration register. + 0x58 + 0x20 + 0x00000203 + + + B_DB_TMP_READY_TRIGGER_MB_NUM + Configures when to trigger video B H264_DB_TMP_READY_INT. When the (MB number of written db temp+1) is greater than this filed in first MB line, trigger H264_DB_TMP_READY_INT. Min is 3. + 0 + 7 + read-write + + + B_REC_READY_TRIGGER_MB_LINES + Configures when to trigger video B H264_REC_READY_INT. When the MB line number of generated reconstruct pixel is greater than this filed, trigger H264_REC_READY_INT. Min is 4. + 7 + 7 + read-write + + + B_INTRA_COST_CMP_OFFSET + Configures video B intra cost offset when I MB compared with P MB. + 14 + 16 + read-write + + + + + B_DECI_SCORE + Video B luma and chroma MB decimate score Register. + 0x5C + 0x20 + + + B_C_DECI_SCORE + Configures video B chroma MB decimate score. When chroma score is smaller than it, chroma decimate will be enable. + 0 + 10 + read-write + + + B_L_DECI_SCORE + Configures video B luma MB decimate score. When luma score is smaller than it, luma decimate will be enable. + 10 + 10 + read-write + + + + + B_DECI_SCORE_OFFSET + Video B luma and chroma MB decimate score offset Register. + 0x60 + 0x20 + + + B_I16X16_DECI_SCORE_OFFSET + Configures video B i16x16 MB decimate score offset. This offset will be added to i16x16 MB score. + 0 + 6 + read-write + + + B_I_CHROMA_DECI_SCORE_OFFSET + Configures video B I chroma MB decimate score offset. This offset will be added to I chroma MB score. + 6 + 6 + read-write + + + B_P16X16_DECI_SCORE_OFFSET + Configures video B p16x16 MB decimate score offset. This offset will be added to p16x16 MB score. + 12 + 6 + read-write + + + B_P_CHROMA_DECI_SCORE_OFFSET + Configures video B p chroma MB decimate score offset. This offset will be added to p chroma MB score. + 18 + 6 + read-write + + + + + B_RC_CONF0 + Video B rate control configuration register0. + 0x64 + 0x20 + + + B_QP + Configures video B frame level initial luma QP value. + 0 + 6 + read-write + + + B_RATE_CTRL_U + Configures video B parameter U value. U = int((float) u << 8). + 6 + 16 + read-write + + + B_MB_RATE_CTRL_EN + Configures video A whether or not to open macro block rate ctrl.\\1:Open the macro block rate ctrl\\1:Close the macro block rate ctrl. + 22 + 1 + read-write + + + + + B_RC_CONF1 + Video B rate control configuration register1. + 0x68 + 0x20 + + + B_CHROMA_DC_QP_DELTA + Configures video B chroma DC QP offset based on Chroma QP. Chroma DC QP = Chroma QP(after map) + reg_chroma_dc_qp_delta. + 0 + 3 + read-write + + + B_CHROMA_QP_DELTA + Configures video B chroma QP offset based on luma QP. Chroma QP(before map) = Luma QP + reg_chroma_qp_delta. + 3 + 4 + read-write + + + B_QP_MIN + Configures video B allowed luma QP min value. + 7 + 6 + read-write + + + B_QP_MAX + Configures video B allowed luma QP max value. + 13 + 6 + read-write + + + B_MAD_FRAME_PRED + Configures vdieo B frame level predicted MB MAD value. + 19 + 12 + read-write + + + + + B_DB_BYPASS + Video B Deblocking bypass register + 0x6C + 0x20 + + + B_BYPASS_DB_FILTER + Configures whether or not to bypass video B deblcoking filter. \\0: Open the deblock filter\\1: Close the deblock filter + 0 + 1 + read-write + + + + + B_ROI_REGION0 + Video B H264 ROI region0 range configure register. + 0x70 + 0x20 + + + X + Configures the horizontal start macroblocks of region 0 in Video B. + 0 + 7 + read-write + + + Y + Configures the vertical start macroblocks of region 0 in Video B. + 7 + 7 + read-write + + + X_LEN + Configures the number of macroblocks in horizontal direction of the region 0 in Video B. + 14 + 7 + read-write + + + Y_LEN + Configures the number of macroblocks in vertical direction of the region 0 in Video B. + 21 + 7 + read-write + + + EN + Configures whether or not to open Video B ROI of region 0 .\\0:Close ROI\\1:Open ROI. + 28 + 1 + read-write + + + + + B_ROI_REGION1 + Video B H264 ROI region1 range configure register. + 0x74 + 0x20 + + + X + Configures the horizontal start macroblocks of region 1 in Video B. + 0 + 7 + read-write + + + Y + Configures the vertical start macroblocks of region 1 in Video B. + 7 + 7 + read-write + + + X_LEN + Configures the number of macroblocks in horizontal direction of the region 1 in Video B. + 14 + 7 + read-write + + + Y_LEN + Configures the number of macroblocks in vertical direction of the region 1 in Video B. + 21 + 7 + read-write + + + EN + Configures whether or not to open Video B ROI of region 1 .\\0:Close ROI\\1:Open ROI. + 28 + 1 + read-write + + + + + B_ROI_REGION2 + Video B H264 ROI region2 range configure register. + 0x78 + 0x20 + + + X + Configures the horizontal start macroblocks of region 2 in Video B. + 0 + 7 + read-write + + + Y + Configures the vertical start macroblocks of region 2 in Video B. + 7 + 7 + read-write + + + X_LEN + Configures the number of macroblocks in horizontal direction of the region 2 in Video B. + 14 + 7 + read-write + + + Y_LEN + Configures the number of macroblocks in vertical direction of the region 2 in Video B. + 21 + 7 + read-write + + + EN + Configures whether or not to open Video B ROI of region 2 .\\0:Close ROI\\1:Open ROI. + 28 + 1 + read-write + + + + + B_ROI_REGION3 + Video B H264 ROI region3 range configure register. + 0x7C + 0x20 + + + X + Configures the horizontal start macroblocks of region 3 in Video B. + 0 + 7 + read-write + + + Y + Configures the vertical start macroblocks of region 3 in Video B. + 7 + 7 + read-write + + + X_LEN + Configures the number of macroblocks in horizontal direction of the region 3 in video B. + 14 + 7 + read-write + + + Y_LEN + Configures the number of macroblocks in vertical direction of the region 3 in video B. + 21 + 7 + read-write + + + EN + Configures whether or not to open Video B ROI of region 3 .\\0:Close ROI\\1:Open ROI. + 28 + 1 + read-write + + + + + B_ROI_REGION4 + Video B H264 ROI region4 range configure register. + 0x80 + 0x20 + + + X + Configures the horizontal start macroblocks of region 4 in Video B. + 0 + 7 + read-write + + + Y + Configures the vertical start macroblocks of region 4 in Video B. + 7 + 7 + read-write + + + X_LEN + Configures the number of macroblocks in horizontal direction of the region 4 in video B. + 14 + 7 + read-write + + + Y_LEN + Configures the number of macroblocks in vertical direction of the region 4 in video B. + 21 + 7 + read-write + + + EN + Configures whether or not to open Video B ROI of region 4 .\\0:Close ROI\\1:Open ROI. + 28 + 1 + read-write + + + + + B_ROI_REGION5 + Video B H264 ROI region5 range configure register. + 0x84 + 0x20 + + + X + Configures the horizontial start macroblocks of region 5 video B. + 0 + 7 + read-write + + + Y + Configures the vertical start macroblocks of region 5 video B. + 7 + 7 + read-write + + + X_LEN + Configures the number of macroblocks in horizontal direction of the region 5 video B. + 14 + 7 + read-write + + + Y_LEN + Configures the number of macroblocks in vertical direction of the region 5 in video B. + 21 + 7 + read-write + + + EN + Configures whether or not to open Video B ROI of region 5 .\\0:Close ROI\\1:Open ROI. + 28 + 1 + read-write + + + + + B_ROI_REGION6 + Video B H264 ROI region6 range configure register. + 0x88 + 0x20 + + + X + Configures the horizontial start macroblocks of region 6 video B. + 0 + 7 + read-write + + + Y + Configures the vertical start macroblocks of region 6 in video B. + 7 + 7 + read-write + + + X_LEN + Configures the number of macroblocks in horizontal direction of the region 6 in video B. + 14 + 7 + read-write + + + Y_LEN + Configures the number of macroblocks in vertical direction of the region 6 in video B. + 21 + 7 + read-write + + + EN + Configures whether or not to open Video B ROI of region 6 .\\0:Close ROI\\1:Open ROI. + 28 + 1 + read-write + + + + + B_ROI_REGION7 + Video B H264 ROI region7 range configure register. + 0x8C + 0x20 + + + X + Configures the horizontal start macroblocks of region 7 in video B. + 0 + 7 + read-write + + + Y + Configures the vertical start macroblocks of region 7 in video B. + 7 + 7 + read-write + + + X_LEN + Configures the number of macroblocks in horizontal direction of the region 7 in video B. + 14 + 7 + read-write + + + Y_LEN + Configures the number of macroblocks in vertical direction of the region 7 in video B. + 21 + 7 + read-write + + + EN + Configures whether or not to open Video B ROI of region 7 .\\0:Close ROI\\1:Open ROI. + 28 + 1 + read-write + + + + + B_ROI_REGION0_3_QP + Video B H264 ROI region0, region1,region2,region3 QP register. + 0x90 + 0x20 + + + B_ROI_REGION0_QP + Configure H264 ROI region0 qp in video B,fixed qp or delta qp. + 0 + 7 + read-write + + + B_ROI_REGION1_QP + Configure H264 ROI region1 qp in video B,fixed qp or delta qp. + 7 + 7 + read-write + + + B_ROI_REGION2_QP + Configure H264 ROI region2 qp in video B,fixed qp or delta qp. + 14 + 7 + read-write + + + B_ROI_REGION3_QP + Configure H264 ROI region3 qp in video B,fixed qp or delta qp. + 21 + 7 + read-write + + + + + B_ROI_REGION4_7_QP + Video B H264 ROI region4, region5,region6,region7 QP register. + 0x94 + 0x20 + + + B_ROI_REGION4_QP + Configure H264 ROI region4 qp in video B,fixed qp or delta qp. + 0 + 7 + read-write + + + B_ROI_REGION5_QP + Configure H264 ROI region5 qp in video B,fixed qp or delta qp. + 7 + 7 + read-write + + + B_ROI_REGION6_QP + Configure H264 ROI region6 qp in video B,fixed qp or delta qp. + 14 + 7 + read-write + + + B_ROI_REGION7_QP + Configure H264 ROI region7 qp in video B,fixed qp or delta qp. + 21 + 7 + read-write + + + + + B_NO_ROI_REGION_QP_OFFSET + Video B H264 no roi region QP register. + 0x98 + 0x20 + + + B_NO_ROI_REGION_QP + Configure H264 no region qp in video B, delta qp. + 0 + 7 + read-write + + + + + B_ROI_CONFIG + Video B H264 ROI configure register. + 0x9C + 0x20 + + + B_ROI_EN + Configure whether or not to enable ROI in video B.\\0:not enable ROI\\1:enable ROI. + 0 + 1 + read-write + + + B_ROI_MODE + Configure the mode of ROI in video B.\\0:fixed qp\\1:delta qp. + 1 + 1 + read-write + + + + + RC_STATUS0 + Rate control status register0. + 0xA0 + 0x20 + + + FRAME_MAD_SUM + Represents all MB actual MAD sum value of one frame. + 0 + 21 + read-only + + + + + RC_STATUS1 + Rate control status register1. + 0xA4 + 0x20 + + + FRAME_ENC_BITS + Represents all MB actual encoding bits sum value of one frame. + 0 + 27 + read-only + + + + + RC_STATUS2 + Rate control status register2. + 0xA8 + 0x20 + + + FRAME_QP_SUM + Represents all MB actual luma QP sum value of one frame. + 0 + 19 + read-only + + + + + SLICE_HEADER_REMAIN + Frame Slice Header remain bit register. + 0xAC + 0x20 + + + SLICE_REMAIN_BITLENGTH + Configures Slice Header remain bit number + 0 + 3 + read-write + + + SLICE_REMAIN_BIT + Configures Slice Header remain bit + 3 + 8 + read-write + + + + + SLICE_HEADER_BYTE_LENGTH + Frame Slice Header byte length register. + 0xB0 + 0x20 + + + SLICE_BYTE_LENGTH + Configures Slice Header byte number + 0 + 4 + read-write + + + + + BS_THRESHOLD + Bitstream buffer overflow threshold register + 0xB4 + 0x20 + 0x00000030 + + + BS_BUFFER_THRESHOLD + Configures bitstream buffer overflow threshold. This value should be bigger than the encode bytes of one 4x4 submb. + 0 + 7 + read-write + + + + + SLICE_HEADER_BYTE0 + Frame Slice Header byte low 32 bit register. + 0xB8 + 0x20 + + + SLICE_BYTE_LSB + Configures Slice Header low 32 bit + 0 + 32 + read-write + + + + + SLICE_HEADER_BYTE1 + Frame Slice Header byte high 32 bit register. + 0xBC + 0x20 + + + SLICE_BYTE_MSB + Configures Slice Header high 32 bit + 0 + 32 + read-write + + + + + INT_RAW + Interrupt raw status register + 0xC0 + 0x20 + + + DB_TMP_READY_INT_RAW + Raw status bit: The raw interrupt status of H264_DB_TMP_READY_INT. Triggered when H264 written enough db tmp pixel. + 0 + 1 + read-write + + + REC_READY_INT_RAW + Raw status bit: The raw interrupt status of H264_REC_READY_INT. Triggered when H264 encoding enough reconstruct pixel. + 1 + 1 + read-write + + + FRAME_DONE_INT_RAW + Raw status bit: The raw interrupt status of H264_FRAME_DONE_INT. Triggered when H264 encoding one frame done. + 2 + 1 + read-write + + + DMA_MOVE_2MB_LINE_DONE_INT_RAW + Raw status bit: The raw interrupt status of H264_DMA_MOVE_2MB_LINE_DONE_INT. Triggered when H264 move two MB lines of reference frame from external mem to internal mem done. + 3 + 1 + read-write + + + + + INT_ST + Interrupt masked status register + 0xC4 + 0x20 + + + DB_TMP_READY_INT_ST + The masked interrupt status of H264_DB_TMP_READY_INT. Valid only when the H264_DB_TMP_READY_INT_ENA is set to 1. + 0 + 1 + read-only + + + REC_READY_INT_ST + The masked interrupt status of H264_REC_READY_INT. Valid only when the H264_REC_READY_INT_ENA is set to 1. + 1 + 1 + read-only + + + FRAME_DONE_INT_ST + The masked interrupt status of H264_FRAME_DONE_INT. Valid only when the H264_FRAME_DONE_INT_ENA is set to 1. + 2 + 1 + read-only + + + DMA_MOVE_2MB_LINE_DONE_INT_ST + Masked status bit: The masked interrupt status of H264_DMA_MOVE_2MB_LINE_DONE_INT. Valid only when the H264_DMA_MOVE_2MB_LINE_DONE_INT_ENA is set to 1. + 3 + 1 + read-only + + + + + INT_ENA + Interrupt enable register + 0xC8 + 0x20 + + + DB_TMP_READY_INT_ENA + Write 1 to enable H264_DB_TMP_READY_INT. + 0 + 1 + read-write + + + REC_READY_INT_ENA + Write 1 to enable H264_REC_READY_INT. + 1 + 1 + read-write + + + FRAME_DONE_INT_ENA + Write 1 to enable H264_FRAME_DONE_INT. + 2 + 1 + read-write + + + DMA_MOVE_2MB_LINE_DONE_INT_ENA + Enable bit: Write 1 to enable H264_DMA_MOVE_2MB_LINE_DONE_INT. + 3 + 1 + read-write + + + + + INT_CLR + Interrupt clear register + 0xCC + 0x20 + + + DB_TMP_READY_INT_CLR + Write 1 to clear H264_DB_TMP_READY_INT. + 0 + 1 + write-only + + + REC_READY_INT_CLR + Write 1 to clear H264_REC_READY_INT. + 1 + 1 + write-only + + + FRAME_DONE_INT_CLR + Write 1 to clear H264_FRAME_DONE_INT. + 2 + 1 + write-only + + + DMA_MOVE_2MB_LINE_DONE_INT_CLR + Clear bit: Write 1 to clear H264_DMA_MOVE_2MB_LINE_DONE_INT. + 3 + 1 + write-only + + + + + CONF + General configuration register. + 0xD0 + 0x20 + + + CLK_EN + Configures whether or not to open register clock gate.\\0: Open the clock gate only when application writes registers\\1: Force open the clock gate for register + 0 + 1 + read-write + + + REC_RAM_CLK_EN2 + Configures whether or not to open the clock gate for rec ram2.\\0: Open the clock gate only when application writes or reads rec ram2\\1: Force open the clock gate for rec ram2 + 1 + 1 + read-write + + + REC_RAM_CLK_EN1 + Configures whether or not to open the clock gate for rec ram1.\\0: Open the clock gate only when application writes or reads rec ram1\\1: Force open the clock gate for rec ram1 + 2 + 1 + read-write + + + QUANT_RAM_CLK_EN2 + Configures whether or not to open the clock gate for quant ram2.\\0: Open the clock gate only when application writes or reads quant ram2\\1: Force open the clock gate for quant ram2 + 3 + 1 + read-write + + + QUANT_RAM_CLK_EN1 + Configures whether or not to open the clock gate for quant ram1.\\0: Open the clock gate only when application writes or reads quant ram1\\1: Force open the clock gate for quant ram1 + 4 + 1 + read-write + + + PRE_RAM_CLK_EN + Configures whether or not to open the clock gate for pre ram.\\0: Open the clock gate only when application writes or reads pre ram\\1: Force open the clock gate for pre ram + 5 + 1 + read-write + + + MVD_RAM_CLK_EN + Configures whether or not to open the clock gate for mvd ram.\\0: Open the clock gate only when application writes or reads mvd ram\\1: Force open the clock gate for mvd ram + 6 + 1 + read-write + + + MC_RAM_CLK_EN + Configures whether or not to open the clock gate for mc ram.\\0: Open the clock gate only when application writes or reads mc ram\\1: Force open the clock gate for mc ram + 7 + 1 + read-write + + + REF_RAM_CLK_EN + Configures whether or not to open the clock gate for ref ram.\\0: Open the clock gate only when application writes or reads ref ram\\1: Force open the clock gate for ref ram + 8 + 1 + read-write + + + I4X4_REF_RAM_CLK_EN + Configures whether or not to open the clock gate for i4x4_mode ram.\\0: Open the clock gate only when application writes or reads i4x4_mode ram\\1: Force open the clock gate for i4x4_mode ram + 9 + 1 + read-write + + + IME_RAM_CLK_EN + Configures whether or not to open the clock gate for ime ram.\\0: Open the clock gate only when application writes or reads ime ram\\1: Force open the clock gate for ime ram + 10 + 1 + read-write + + + FME_RAM_CLK_EN + Configures whether or not to open the clock gate for fme ram.\\0: Open the clock gate only when application writes or readsfme ram\\1: Force open the clock gate for fme ram + 11 + 1 + read-write + + + FETCH_RAM_CLK_EN + Configures whether or not to open the clock gate for fetch ram.\\0: Open the clock gate only when application writes or reads fetch ram\\1: Force open the clock gate for fetch ram + 12 + 1 + read-write + + + DB_RAM_CLK_EN + Configures whether or not to open the clock gate for db ram.\\0: Open the clock gate only when application writes or reads db ram\\1: Force open the clock gate for db ram + 13 + 1 + read-write + + + CUR_MB_RAM_CLK_EN + Configures whether or not to open the clock gate for cur_mb ram.\\0: Open the clock gate only when application writes or reads cur_mb ram\\1: Force open the clock gate for cur_mb ram + 14 + 1 + read-write + + + CAVLC_RAM_CLK_EN + Configures whether or not to open the clock gate for cavlc ram.\\0: Open the clock gate only when application writes or reads cavlc ram\\1: Force open the clock gate for cavlc ram + 15 + 1 + read-write + + + IME_CLK_EN + Configures whether or not to open the clock gate for ime.\\0: Open the clock gate only when ime work\\1: Force open the clock gate for ime + 16 + 1 + read-write + + + FME_CLK_EN + Configures whether or not to open the clock gate for fme.\\0: Open the clock gate only when fme work\\1: Force open the clock gate for fme + 17 + 1 + read-write + + + MC_CLK_EN + Configures whether or not to open the clock gate for mc.\\0: Open the clock gate only when mc work\\1: Force open the clock gate for mc + 18 + 1 + read-write + + + INTERPOLATOR_CLK_EN + Configures whether or not to open the clock gate for interpolator.\\0: Open the clock gate only when interpolator work\\1: Force open the clock gate for interpolator + 19 + 1 + read-write + + + DB_CLK_EN + Configures whether or not to open the clock gate for deblocking filter.\\0: Open the clock gate only when deblocking filter work\\1: Force open the clock gate for deblocking filter + 20 + 1 + read-write + + + CLAVLC_CLK_EN + Configures whether or not to open the clock gate for cavlc.\\0: Open the clock gate only when cavlc work\\1: Force open the clock gate for cavlc + 21 + 1 + read-write + + + INTRA_CLK_EN + Configures whether or not to open the clock gate for intra.\\0: Open the clock gate only when intra work\\1: Force open the clock gate for intra + 22 + 1 + read-write + + + DECI_CLK_EN + Configures whether or not to open the clock gate for decimate.\\0: Open the clock gate only when decimate work\\1: Force open the clock gate for decimate + 23 + 1 + read-write + + + BS_CLK_EN + Configures whether or not to open the clock gate for bs buffer.\\0: Open the clock gate only when bs buffer work\\1: Force open the clock gate for bs buffer + 24 + 1 + read-write + + + MV_MERGE_CLK_EN + Configures whether or not to open the clock gate for mv merge.\\0: Open the clock gate only when mv merge work\\1: Force open the clock gate for mv merge + 25 + 1 + read-write + + + + + MV_MERGE_CONFIG + Mv merge configuration register. + 0xD4 + 0x20 + + + MV_MERGE_TYPE + Configure mv merge type.\\0: merge p16x16 mv\\1: merge min mv\\2: merge max mv\\3: not valid. + 0 + 2 + read-write + + + INT_MV_OUT_EN + Configure mv merge output integer part not zero mv or all part not zero mv.\\0: output all part not zero mv\\1: output integer part not zero mv. + 2 + 1 + read-write + + + A_MV_MERGE_EN + Configure whether or not to enable video A mv merge.\\0: disable\\1: enable. + 3 + 1 + read-write + + + B_MV_MERGE_EN + Configure whether or not to enable video B mv merge.\\0: disable\\1: enable. + 4 + 1 + read-write + + + MB_VALID_NUM + Represents the valid mb number of mv merge output. + 5 + 13 + read-only + + + + + DEBUG_DMA_SEL + Debug H264 DMA select register + 0xD8 + 0x20 + + + DBG_DMA_SEL + Every bit represents a dma in h264 + 0 + 8 + read-write + + + + + SYS_STATUS + System status register. + 0xDC + 0x20 + + + FRAME_NUM + Represents current frame number. + 0 + 9 + read-only + + + DUAL_STREAM_SEL + Represents which register group is used for cur frame.\\0: Register group A is used\\1: Register group B is used. + 9 + 1 + read-only + + + INTRA_FLAG + Represents the type of current encoding frame.\\0: P frame\\1: I frame. + 10 + 1 + read-only + + + + + FRAME_CODE_LENGTH + Frame code byte length register. + 0xE0 + 0x20 + + + FRAME_CODE_LENGTH + Represents current frame code byte length. + 0 + 24 + read-only + + + + + DEBUG_INFO0 + Debug information register0. + 0xE4 + 0x20 + + + TOP_CTRL_INTER_DEBUG_STATE + Represents top_ctrl_inter module FSM info. + 0 + 4 + read-only + + + TOP_CTRL_INTRA_DEBUG_STATE + Represents top_ctrl_intra module FSM info. + 4 + 3 + read-only + + + P_I_CMP_DEBUG_STATE + Represents p_i_cmp module FSM info. + 7 + 3 + read-only + + + MVD_DEBUG_STATE + Represents mvd module FSM info. + 10 + 3 + read-only + + + MC_CHROMA_IP_DEBUG_STATE + Represents mc_chroma_ip module FSM info. + 13 + 1 + read-only + + + INTRA_16X16_CHROMA_CTRL_DEBUG_STATE + Represents intra_16x16_chroma_ctrl module FSM info. + 14 + 4 + read-only + + + INTRA_4X4_CTRL_DEBUG_STATE + Represents intra_4x4_ctrl module FSM info. + 18 + 4 + read-only + + + INTRA_TOP_CTRL_DEBUG_STATE + Represents intra_top_ctrl module FSM info. + 22 + 3 + read-only + + + IME_CTRL_DEBUG_STATE + Represents ime_ctrl module FSM info. + 25 + 3 + read-only + + + + + DEBUG_INFO1 + Debug information register1. + 0xE8 + 0x20 + + + FME_CTRL_DEBUG_STATE + Represents fme_ctrl module FSM info. + 0 + 3 + read-only + + + DECI_CALC_DEBUG_STATE + Represents deci_calc module's FSM info. DEV use only. + 3 + 2 + read-only + + + DB_DEBUG_STATE + Represents db module FSM info. + 5 + 3 + read-only + + + CAVLC_ENC_DEBUG_STATE + Represents cavlc module enc FSM info. + 8 + 4 + read-only + + + CAVLC_SCAN_DEBUG_STATE + Represents cavlc module scan FSM info. + 12 + 4 + read-only + + + CAVLC_CTRL_DEBUG_STATE + Represents cavlc module ctrl FSM info. + 16 + 2 + read-only + + + BS_BUFFER_DEBUG_STATE + Represents bs buffer overflow info. + 18 + 1 + read-only + + + + + DEBUG_INFO2 + Debug information register2. + 0xEC + 0x20 + + + P_RC_DONE_DEBUG_FLAG + Represents p rate ctrl done status.\\0: not done\\1: done. + 0 + 1 + read-only + + + P_P_I_CMP_DONE_DEBUG_FLAG + Represents p p_i_cmp done status.\\0: not done\\1: done. + 1 + 1 + read-only + + + P_MV_MERGE_DONE_DEBUG_FLAG + Represents p mv merge done status.\\0: not done\\1: done. + 2 + 1 + read-only + + + P_MOVE_ORI_DONE_DEBUG_FLAG + Represents p move origin done status.\\0: not done\\1: done. + 3 + 1 + read-only + + + P_MC_DONE_DEBUG_FLAG + Represents p mc done status.\\0: not done\\1: done. + 4 + 1 + read-only + + + P_IME_DONE_DEBUG_FLAG + Represents p ime done status.\\0: not done\\1: done. + 5 + 1 + read-only + + + P_GET_ORI_DONE_DEBUG_FLAG + Represents p get origin done status.\\0: not done\\1: done. + 6 + 1 + read-only + + + P_FME_DONE_DEBUG_FLAG + Represents p fme done status.\\0: not done\\1: done. + 7 + 1 + read-only + + + P_FETCH_DONE_DEBUG_FLAG + Represents p fetch done status.\\0: not done\\1: done. + 8 + 1 + read-only + + + P_DB_DONE_DEBUG_FLAG + Represents p deblocking done status.\\0: not done\\1: done. + 9 + 1 + read-only + + + P_BS_BUF_DONE_DEBUG_FLAG + Represents p bitstream buffer done status.\\0: not done\\1: done. + 10 + 1 + read-only + + + REF_MOVE_2MB_LINE_DONE_DEBUG_FLAG + Represents dma move 2 ref mb line done status.\\0: not done\\1: done. + 11 + 1 + read-only + + + I_P_I_CMP_DONE_DEBUG_FLAG + Represents I p_i_cmp done status.\\0: not done\\1: done. + 12 + 1 + read-only + + + I_MOVE_ORI_DONE_DEBUG_FLAG + Represents I move origin done status.\\0: not done\\1: done. + 13 + 1 + read-only + + + I_GET_ORI_DONE_DEBUG_FLAG + Represents I get origin done status.\\0: not done\\1: done. + 14 + 1 + read-only + + + I_EC_DONE_DEBUG_FLAG + Represents I encoder done status.\\0: not done\\1: done. + 15 + 1 + read-only + + + I_DB_DONE_DEBUG_FLAG + Represents I deblocking done status.\\0: not done\\1: done. + 16 + 1 + read-only + + + I_BS_BUF_DONE_DEBUG_FLAG + Represents I bitstream buffer done status.\\0: not done\\1: done. + 17 + 1 + read-only + + + + + DATE + Version control register + 0xF0 + 0x20 + 0x02304240 + + + LEDC_DATE + Configures the version. + 0 + 28 + read-write + + + + + + + H264_DMA + H264 Encoder (DMA) + H264_DMA + 0x500A7000 + + 0x0 + 0x3DC + registers + + + H264_DMA2D_OUT_CH0 + 115 + + + H264_DMA2D_OUT_CH1 + 116 + + + H264_DMA2D_OUT_CH2 + 117 + + + H264_DMA2D_OUT_CH3 + 118 + + + H264_DMA2D_OUT_CH4 + 119 + + + H264_DMA2D_IN_CH0 + 120 + + + H264_DMA2D_IN_CH1 + 121 + + + H264_DMA2D_IN_CH2 + 122 + + + H264_DMA2D_IN_CH3 + 123 + + + H264_DMA2D_IN_CH4 + 124 + + + H264_DMA2D_IN_CH5 + 125 + + + + OUT_CONF0_CH0 + TX CH0 config0 register + 0x0 + 0x20 + 0x00000002 + + + OUT_AUTO_WRBACK_CH0 + Set this bit to enable automatic outlink-writeback when all the data pointed by outlink descriptor has been received. + 0 + 1 + read-write + + + OUT_EOF_MODE_CH0 + EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is generated when data need to read has been popped from FIFO in DMA + 1 + 1 + read-write + + + OUTDSCR_BURST_EN_CH0 + Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. + 2 + 1 + read-write + + + OUT_ECC_AES_EN_CH0 + When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned. + 3 + 1 + read-write + + + OUT_CHECK_OWNER_CH0 + Set this bit to enable checking the owner attribute of the link descriptor. + 4 + 1 + read-write + + + OUT_MEM_BURST_LENGTH_CH0 + Block size of Tx channel 0. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes + 6 + 3 + read-write + + + OUT_PAGE_BOUND_EN_CH0 + Set this bit to 1 to make sure AXI read data don't cross the address boundary which define by mem_burst_length + 12 + 1 + read-write + + + OUT_REORDER_EN_CH0 + Enable TX channel 0 macro block reorder when set to 1, only channel0 have this selection + 16 + 1 + read-write + + + OUT_RST_CH0 + Write 1 then write 0 to this bit to reset TX channel + 24 + 1 + read-write + + + OUT_CMD_DISABLE_CH0 + Write 1 before reset and write 0 after reset + 25 + 1 + read-write + + + OUT_ARB_WEIGHT_OPT_DIS_CH0 + Set this bit to 1 to disable arbiter optimum weight function. + 26 + 1 + read-write + + + + + OUT_INT_RAW_CH0 + TX CH0 interrupt raw register + 0x4 + 0x20 + + + OUT_DONE_CH0_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0. + 0 + 1 + read-write + + + OUT_EOF_CH0_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. + 1 + 1 + read-write + + + OUT_DSCR_ERR_CH0_INT_RAW + The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0. + 2 + 1 + read-write + + + OUT_TOTAL_EOF_CH0_INT_RAW + The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0. + 3 + 1 + read-write + + + OUTFIFO_OVF_L1_CH0_INT_RAW + The raw interrupt bit turns to high level when fifo is overflow. + 4 + 1 + read-write + + + OUTFIFO_UDF_L1_CH0_INT_RAW + The raw interrupt bit turns to high level when fifo is underflow. + 5 + 1 + read-write + + + OUTFIFO_OVF_L2_CH0_INT_RAW + The raw interrupt bit turns to high level when fifo is overflow. + 6 + 1 + read-write + + + OUTFIFO_UDF_L2_CH0_INT_RAW + The raw interrupt bit turns to high level when fifo is underflow. + 7 + 1 + read-write + + + OUT_DSCR_TASK_OVF_CH0_INT_RAW + The raw interrupt bit turns to high level when dscr ready task fifo is overflow. + 8 + 1 + read-write + + + + + OUT_INT_ENA_CH0 + TX CH0 interrupt ena register + 0x8 + 0x20 + + + OUT_DONE_CH0_INT_ENA + The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + 0 + 1 + read-write + + + OUT_EOF_CH0_INT_ENA + The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + 1 + 1 + read-write + + + OUT_DSCR_ERR_CH0_INT_ENA + The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + read-write + + + OUT_TOTAL_EOF_CH0_INT_ENA + The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + read-write + + + OUTFIFO_OVF_L1_CH0_INT_ENA + The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-write + + + OUTFIFO_UDF_L1_CH0_INT_ENA + The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-write + + + OUTFIFO_OVF_L2_CH0_INT_ENA + The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-write + + + OUTFIFO_UDF_L2_CH0_INT_ENA + The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-write + + + OUT_DSCR_TASK_OVF_CH0_INT_ENA + The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. + 8 + 1 + read-write + + + + + OUT_INT_ST_CH0 + TX CH0 interrupt st register + 0xC + 0x20 + + + OUT_DONE_CH0_INT_ST + The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + 0 + 1 + read-only + + + OUT_EOF_CH0_INT_ST + The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + 1 + 1 + read-only + + + OUT_DSCR_ERR_CH0_INT_ST + The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + read-only + + + OUT_TOTAL_EOF_CH0_INT_ST + The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + read-only + + + OUTFIFO_OVF_L1_CH0_INT_ST + The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-only + + + OUTFIFO_UDF_L1_CH0_INT_ST + The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-only + + + OUTFIFO_OVF_L2_CH0_INT_ST + The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-only + + + OUTFIFO_UDF_L2_CH0_INT_ST + The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-only + + + OUT_DSCR_TASK_OVF_CH0_INT_ST + The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. + 8 + 1 + read-only + + + + + OUT_INT_CLR_CH0 + TX CH0 interrupt clr register + 0x10 + 0x20 + + + OUT_DONE_CH0_INT_CLR + Set this bit to clear the OUT_DONE_CH_INT interrupt. + 0 + 1 + write-only + + + OUT_EOF_CH0_INT_CLR + Set this bit to clear the OUT_EOF_CH_INT interrupt. + 1 + 1 + write-only + + + OUT_DSCR_ERR_CH0_INT_CLR + Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + write-only + + + OUT_TOTAL_EOF_CH0_INT_CLR + Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + write-only + + + OUTFIFO_OVF_L1_CH0_INT_CLR + Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + write-only + + + OUTFIFO_UDF_L1_CH0_INT_CLR + Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + write-only + + + OUTFIFO_OVF_L2_CH0_INT_CLR + Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + write-only + + + OUTFIFO_UDF_L2_CH0_INT_CLR + Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + write-only + + + OUT_DSCR_TASK_OVF_CH0_INT_CLR + Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. + 8 + 1 + write-only + + + + + OUTFIFO_STATUS_CH0 + TX CH0 outfifo status register + 0x14 + 0x20 + 0x00020082 + + + OUTFIFO_FULL_L2_CH0 + Tx FIFO full signal for Tx channel 0. + 0 + 1 + read-only + + + OUTFIFO_EMPTY_L2_CH0 + Tx FIFO empty signal for Tx channel 0. + 1 + 1 + read-only + + + OUTFIFO_CNT_L2_CH0 + The register stores the byte number of the data in Tx FIFO for Tx channel 0. + 2 + 4 + read-only + + + OUTFIFO_FULL_L1_CH0 + Tx FIFO full signal for Tx channel 0. + 6 + 1 + read-only + + + OUTFIFO_EMPTY_L1_CH0 + Tx FIFO empty signal for Tx channel 0. + 7 + 1 + read-only + + + OUTFIFO_CNT_L1_CH0 + The register stores the byte number of the data in Tx FIFO for Tx channel 0. + 8 + 5 + read-only + + + OUTFIFO_FULL_L3_CH0 + Tx FIFO full signal for Tx channel 0. + 16 + 1 + read-only + + + OUTFIFO_EMPTY_L3_CH0 + Tx FIFO empty signal for Tx channel 0. + 17 + 1 + read-only + + + OUTFIFO_CNT_L3_CH0 + The register stores the 8byte number of the data in Tx FIFO for Tx channel 0. + 18 + 2 + read-only + + + + + OUT_PUSH_CH0 + TX CH0 outfifo push register + 0x18 + 0x20 + + + OUTFIFO_WDATA_CH0 + This register stores the data that need to be pushed into DMA Tx FIFO. + 0 + 10 + read-write + + + OUTFIFO_PUSH_CH0 + Set this bit to push data into DMA Tx FIFO. + 10 + 1 + read-write + + + + + OUT_LINK_CONF_CH0 + TX CH0 out_link dscr ctrl register + 0x1C + 0x20 + 0x00800000 + + + OUTLINK_STOP_CH0 + Set this bit to stop dealing with the outlink descriptors. + 20 + 1 + read-write + + + OUTLINK_START_CH0 + Set this bit to start dealing with the outlink descriptors. + 21 + 1 + read-write + + + OUTLINK_RESTART_CH0 + Set this bit to restart a new outlink from the last address. + 22 + 1 + read-write + + + OUTLINK_PARK_CH0 + 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. + 23 + 1 + read-only + + + + + OUT_LINK_ADDR_CH0 + TX CH0 out_link dscr addr register + 0x20 + 0x20 + + + OUTLINK_ADDR_CH0 + This register stores the first outlink descriptor's address. + 0 + 32 + read-write + + + + + OUT_STATE_CH0 + TX CH0 state register + 0x24 + 0x20 + 0x01000000 + + + OUTLINK_DSCR_ADDR_CH0 + This register stores the current outlink descriptor's address. + 0 + 18 + read-only + + + OUT_DSCR_STATE_CH0 + This register stores the current descriptor state machine state. + 18 + 2 + read-only + + + OUT_STATE_CH0 + This register stores the current control module state machine state. + 20 + 4 + read-only + + + OUT_RESET_AVAIL_CH0 + This register indicate that if the channel reset is safety. + 24 + 1 + read-only + + + + + OUT_EOF_DES_ADDR_CH0 + TX CH0 eof des addr register + 0x28 + 0x20 + + + OUT_EOF_DES_ADDR_CH0 + This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1. + 0 + 32 + read-only + + + + + OUT_DSCR_CH0 + TX CH0 next dscr addr register + 0x2C + 0x20 + + + OUTLINK_DSCR_CH0 + The address of the next outlink descriptor address y. + 0 + 32 + read-only + + + + + OUT_DSCR_BF0_CH0 + TX CH0 last dscr addr register + 0x30 + 0x20 + + + OUTLINK_DSCR_BF0_CH0 + The address of the last outlink descriptor's next address y-1. + 0 + 32 + read-only + + + + + OUT_DSCR_BF1_CH0 + TX CH0 second-to-last dscr addr register + 0x34 + 0x20 + + + OUTLINK_DSCR_BF1_CH0 + The address of the second-to-last outlink descriptor's next address y-2. + 0 + 32 + read-only + + + + + OUT_ARB_CH0 + TX CH0 arb register + 0x3C + 0x20 + 0x00000011 + + + OUT_ARB_TOKEN_NUM_CH0 + Set the max number of token count of arbiter + 0 + 4 + read-write + + + EXTER_OUT_ARB_PRIORITY_CH0 + Set the priority of channel + 4 + 2 + read-write + + + + + OUT_RO_STATUS_CH0 + TX CH0 reorder status register + 0x40 + 0x20 + 0x00000800 + + + OUTFIFO_RO_CNT_CH0 + The register stores the 8byte number of the data in reorder Tx FIFO for channel 0. + 0 + 2 + read-only + + + OUT_RO_WR_STATE_CH0 + The register stores the state of read ram of reorder + 6 + 2 + read-only + + + OUT_RO_RD_STATE_CH0 + The register stores the state of write ram of reorder + 8 + 2 + read-only + + + OUT_PIXEL_BYTE_CH0 + the number of bytes contained in a pixel at TX channel 0: 1byte 1: 1.5bytes 2 : 2bytes 3: 2.5bytes 4: 3bytes 5: 4bytes + 10 + 4 + read-only + + + OUT_BURST_BLOCK_NUM_CH0 + the number of macro blocks contained in a burst of data at TX channel + 14 + 4 + read-only + + + + + OUT_RO_PD_CONF_CH0 + TX CH0 reorder power config register + 0x44 + 0x20 + 0x00000020 + + + OUT_RO_RAM_FORCE_PD_CH0 + dma reorder ram power down + 4 + 1 + read-write + + + OUT_RO_RAM_FORCE_PU_CH0 + dma reorder ram power up + 5 + 1 + read-write + + + OUT_RO_RAM_CLK_FO_CH0 + 1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. 0: A gate-clock will be used when accessing the RAM in DMA. + 6 + 1 + read-write + + + + + OUT_MODE_ENABLE_CH0 + tx CH0 mode enable register + 0x50 + 0x20 + + + OUT_TEST_MODE_ENABLE_CH0 + tx CH0 test mode enable.0 : H264_DMA work in normal mode.1 : H264_DMA work in test mode + 0 + 1 + read-write + + + + + OUT_MODE_YUV_CH0 + tx CH0 test mode yuv value register + 0x54 + 0x20 + + + OUT_TEST_Y_VALUE_CH0 + tx CH0 test mode y value + 0 + 8 + read-write + + + OUT_TEST_U_VALUE_CH0 + tx CH0 test mode u value + 8 + 8 + read-write + + + OUT_TEST_V_VALUE_CH0 + tx CH0 test mode v value + 16 + 8 + read-write + + + + + OUT_ETM_CONF_CH0 + TX CH0 ETM config register + 0x68 + 0x20 + 0x00000004 + + + OUT_ETM_EN_CH0 + Set this bit to 1 to enable ETM task function + 0 + 1 + read-write + + + OUT_ETM_LOOP_EN_CH0 + when this bit is 1, dscr can be processed after receiving a task + 1 + 1 + read-write + + + OUT_DSCR_TASK_MAK_CH0 + ETM dscr_ready maximum cache numbers + 2 + 2 + read-write + + + + + OUT_BUF_LEN_CH0 + tx CH0 buf len register + 0x70 + 0x20 + + + OUT_CMDFIFO_BUF_LEN_HB_CH0 + only for debug + 0 + 13 + read-only + + + + + OUT_FIFO_BCNT_CH0 + tx CH0 fifo byte cnt register + 0x74 + 0x20 + + + OUT_CMDFIFO_OUTFIFO_BCNT_CH0 + only for debug + 0 + 10 + read-only + + + + + OUT_PUSH_BYTECNT_CH0 + tx CH0 push byte cnt register + 0x78 + 0x20 + 0x000000FF + + + OUT_CMDFIFO_PUSH_BYTECNT_CH0 + only for debug + 0 + 8 + read-only + + + + + OUT_XADDR_CH0 + tx CH0 xaddr register + 0x7C + 0x20 + + + OUT_CMDFIFO_XADDR_CH0 + only for debug + 0 + 32 + read-only + + + + + OUT_CONF0_CH1 + TX CH1 config0 register + 0x100 + 0x20 + 0x00000002 + + + OUT_AUTO_WRBACK_CH1 + Set this bit to enable automatic outlink-writeback when all the data pointed by outlink descriptor has been received. + 0 + 1 + read-write + + + OUT_EOF_MODE_CH1 + EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is generated when data need to read has been popped from FIFO in DMA + 1 + 1 + read-write + + + OUTDSCR_BURST_EN_CH1 + Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. + 2 + 1 + read-write + + + OUT_ECC_AES_EN_CH1 + When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned. + 3 + 1 + read-write + + + OUT_CHECK_OWNER_CH1 + Set this bit to enable checking the owner attribute of the link descriptor. + 4 + 1 + read-write + + + OUT_MEM_BURST_LENGTH_CH1 + Block size of Tx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 64 bytes + 6 + 3 + read-write + + + OUT_PAGE_BOUND_EN_CH1 + Set this bit to 1 to make sure AXI read data don't cross the address boundary which define by mem_burst_length + 12 + 1 + read-write + + + OUT_RST_CH1 + Write 1 then write 0 to this bit to reset TX channel + 24 + 1 + read-write + + + OUT_CMD_DISABLE_CH1 + Write 1 before reset and write 0 after reset + 25 + 1 + read-write + + + OUT_ARB_WEIGHT_OPT_DIS_CH1 + Set this bit to 1 to disable arbiter optimum weight function. + 26 + 1 + read-write + + + + + OUT_INT_RAW_CH1 + TX CH1 interrupt raw register + 0x104 + 0x20 + + + OUT_DONE_CH1_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0. + 0 + 1 + read-write + + + OUT_EOF_CH1_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. + 1 + 1 + read-write + + + OUT_DSCR_ERR_CH1_INT_RAW + The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0. + 2 + 1 + read-write + + + OUT_TOTAL_EOF_CH1_INT_RAW + The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0. + 3 + 1 + read-write + + + OUTFIFO_OVF_L1_CH1_INT_RAW + The raw interrupt bit turns to high level when fifo is overflow. + 4 + 1 + read-write + + + OUTFIFO_UDF_L1_CH1_INT_RAW + The raw interrupt bit turns to high level when fifo is underflow. + 5 + 1 + read-write + + + OUTFIFO_OVF_L2_CH1_INT_RAW + The raw interrupt bit turns to high level when fifo is overflow. + 6 + 1 + read-write + + + OUTFIFO_UDF_L2_CH1_INT_RAW + The raw interrupt bit turns to high level when fifo is underflow. + 7 + 1 + read-write + + + OUT_DSCR_TASK_OVF_CH1_INT_RAW + The raw interrupt bit turns to high level when dscr ready task fifo is overflow. + 8 + 1 + read-write + + + + + OUT_INT_ENA_CH1 + TX CH1 interrupt ena register + 0x108 + 0x20 + + + OUT_DONE_CH1_INT_ENA + The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + 0 + 1 + read-write + + + OUT_EOF_CH1_INT_ENA + The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + 1 + 1 + read-write + + + OUT_DSCR_ERR_CH1_INT_ENA + The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + read-write + + + OUT_TOTAL_EOF_CH1_INT_ENA + The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + read-write + + + OUTFIFO_OVF_L1_CH1_INT_ENA + The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-write + + + OUTFIFO_UDF_L1_CH1_INT_ENA + The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-write + + + OUTFIFO_OVF_L2_CH1_INT_ENA + The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-write + + + OUTFIFO_UDF_L2_CH1_INT_ENA + The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-write + + + OUT_DSCR_TASK_OVF_CH1_INT_ENA + The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. + 8 + 1 + read-write + + + + + OUT_INT_ST_CH1 + TX CH1 interrupt st register + 0x10C + 0x20 + + + OUT_DONE_CH1_INT_ST + The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + 0 + 1 + read-only + + + OUT_EOF_CH1_INT_ST + The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + 1 + 1 + read-only + + + OUT_DSCR_ERR_CH1_INT_ST + The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + read-only + + + OUT_TOTAL_EOF_CH1_INT_ST + The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + read-only + + + OUTFIFO_OVF_L1_CH1_INT_ST + The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-only + + + OUTFIFO_UDF_L1_CH1_INT_ST + The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-only + + + OUTFIFO_OVF_L2_CH1_INT_ST + The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-only + + + OUTFIFO_UDF_L2_CH1_INT_ST + The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-only + + + OUT_DSCR_TASK_OVF_CH1_INT_ST + The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. + 8 + 1 + read-only + + + + + OUT_INT_CLR_CH1 + TX CH1 interrupt clr register + 0x110 + 0x20 + + + OUT_DONE_CH1_INT_CLR + Set this bit to clear the OUT_DONE_CH_INT interrupt. + 0 + 1 + write-only + + + OUT_EOF_CH1_INT_CLR + Set this bit to clear the OUT_EOF_CH_INT interrupt. + 1 + 1 + write-only + + + OUT_DSCR_ERR_CH1_INT_CLR + Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + write-only + + + OUT_TOTAL_EOF_CH1_INT_CLR + Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + write-only + + + OUTFIFO_OVF_L1_CH1_INT_CLR + Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + write-only + + + OUTFIFO_UDF_L1_CH1_INT_CLR + Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + write-only + + + OUTFIFO_OVF_L2_CH1_INT_CLR + Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + write-only + + + OUTFIFO_UDF_L2_CH1_INT_CLR + Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + write-only + + + OUT_DSCR_TASK_OVF_CH1_INT_CLR + Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. + 8 + 1 + write-only + + + + + OUTFIFO_STATUS_CH1 + TX CH1 outfifo status register + 0x114 + 0x20 + 0x00020082 + + + OUTFIFO_FULL_L2_CH1 + Tx FIFO full signal for Tx channel 1. + 0 + 1 + read-only + + + OUTFIFO_EMPTY_L2_CH1 + Tx FIFO empty signal for Tx channel 1. + 1 + 1 + read-only + + + OUTFIFO_CNT_L2_CH1 + The register stores the byte number of the data in Tx FIFO for Tx channel 1. + 2 + 4 + read-only + + + OUTFIFO_FULL_L1_CH1 + Tx FIFO full signal for Tx channel 1. + 6 + 1 + read-only + + + OUTFIFO_EMPTY_L1_CH1 + Tx FIFO empty signal for Tx channel 1. + 7 + 1 + read-only + + + OUTFIFO_CNT_L1_CH1 + The register stores the byte number of the data in Tx FIFO for Tx channel 1. + 8 + 5 + read-only + + + OUTFIFO_FULL_L3_CH1 + Tx FIFO full signal for Tx channel 1. + 16 + 1 + read-only + + + OUTFIFO_EMPTY_L3_CH1 + Tx FIFO empty signal for Tx channel 1. + 17 + 1 + read-only + + + OUTFIFO_CNT_L3_CH1 + The register stores the byte number of the data in Tx FIFO for Tx channel 1. + 18 + 2 + read-only + + + + + OUT_PUSH_CH1 + TX CH1 outfifo push register + 0x118 + 0x20 + + + OUTFIFO_WDATA_CH1 + This register stores the data that need to be pushed into DMA Tx FIFO. + 0 + 10 + read-write + + + OUTFIFO_PUSH_CH1 + Set this bit to push data into DMA Tx FIFO. + 10 + 1 + read-write + + + + + OUT_LINK_CONF_CH1 + TX CH1 out_link dscr ctrl register + 0x11C + 0x20 + 0x00800000 + + + OUTLINK_STOP_CH1 + Set this bit to stop dealing with the outlink descriptors. + 20 + 1 + read-write + + + OUTLINK_START_CH1 + Set this bit to start dealing with the outlink descriptors. + 21 + 1 + read-write + + + OUTLINK_RESTART_CH1 + Set this bit to restart a new outlink from the last address. + 22 + 1 + read-write + + + OUTLINK_PARK_CH1 + 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. + 23 + 1 + read-only + + + + + OUT_LINK_ADDR_CH1 + TX CH1 out_link dscr addr register + 0x120 + 0x20 + + + OUTLINK_ADDR_CH1 + This register stores the first outlink descriptor's address. + 0 + 32 + read-write + + + + + OUT_STATE_CH1 + TX CH1 state register + 0x124 + 0x20 + 0x01000000 + + + OUTLINK_DSCR_ADDR_CH1 + This register stores the current outlink descriptor's address. + 0 + 18 + read-only + + + OUT_DSCR_STATE_CH1 + This register stores the current descriptor state machine state. + 18 + 2 + read-only + + + OUT_STATE_CH1 + This register stores the current control module state machine state. + 20 + 4 + read-only + + + OUT_RESET_AVAIL_CH1 + This register indicate that if the channel reset is safety. + 24 + 1 + read-only + + + + + OUT_EOF_DES_ADDR_CH1 + TX CH1 eof des addr register + 0x128 + 0x20 + + + OUT_EOF_DES_ADDR_CH1 + This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1. + 0 + 32 + read-only + + + + + OUT_DSCR_CH1 + TX CH1 next dscr addr register + 0x12C + 0x20 + + + OUTLINK_DSCR_CH1 + The address of the next outlink descriptor address y. + 0 + 32 + read-only + + + + + OUT_DSCR_BF0_CH1 + TX CH1 last dscr addr register + 0x130 + 0x20 + + + OUTLINK_DSCR_BF0_CH1 + The address of the last outlink descriptor's next address y-1. + 0 + 32 + read-only + + + + + OUT_DSCR_BF1_CH1 + TX CH1 second-to-last dscr addr register + 0x134 + 0x20 + + + OUTLINK_DSCR_BF1_CH1 + The address of the second-to-last outlink descriptor's next address y-2. + 0 + 32 + read-only + + + + + OUT_ARB_CH1 + TX CH1 arb register + 0x13C + 0x20 + 0x00000041 + + + OUT_ARB_TOKEN_NUM_CH1 + Set the max number of token count of arbiter + 0 + 4 + read-write + + + INTER_OUT_ARB_PRIORITY_CH1 + Set the priority of channel + 6 + 1 + read-write + + + + + OUT_ETM_CONF_CH1 + TX CH1 ETM config register + 0x168 + 0x20 + 0x00000004 + + + OUT_ETM_EN_CH1 + Set this bit to 1 to enable ETM task function + 0 + 1 + read-write + + + OUT_ETM_LOOP_EN_CH1 + when this bit is 1, dscr can be processed after receiving a task + 1 + 1 + read-write + + + OUT_DSCR_TASK_MAK_CH1 + ETM dscr_ready maximum cache numbers + 2 + 2 + read-write + + + + + OUT_BUF_LEN_CH1 + tx CH1 buf len register + 0x170 + 0x20 + + + OUT_CMDFIFO_BUF_LEN_HB_CH1 + only for debug + 0 + 13 + read-only + + + + + OUT_FIFO_BCNT_CH1 + tx CH1 fifo byte cnt register + 0x174 + 0x20 + + + OUT_CMDFIFO_OUTFIFO_BCNT_CH1 + only for debug + 0 + 10 + read-only + + + + + OUT_PUSH_BYTECNT_CH1 + tx CH1 push byte cnt register + 0x178 + 0x20 + 0x000000FF + + + OUT_CMDFIFO_PUSH_BYTECNT_CH1 + only for debug + 0 + 8 + read-only + + + + + OUT_XADDR_CH1 + tx CH1 xaddr register + 0x17C + 0x20 + + + OUT_CMDFIFO_XADDR_CH1 + only for debug + 0 + 32 + read-only + + + + + OUT_CONF0_CH2 + TX CH2 config0 register + 0x200 + 0x20 + 0x00000002 + + + OUT_AUTO_WRBACK_CH2 + Set this bit to enable automatic outlink-writeback when all the data pointed by outlink descriptor has been received. + 0 + 1 + read-write + + + OUT_EOF_MODE_CH2 + EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is generated when data need to read has been popped from FIFO in DMA + 1 + 1 + read-write + + + OUTDSCR_BURST_EN_CH2 + Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. + 2 + 1 + read-write + + + OUT_ECC_AES_EN_CH2 + When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned. + 3 + 1 + read-write + + + OUT_CHECK_OWNER_CH2 + Set this bit to enable checking the owner attribute of the link descriptor. + 4 + 1 + read-write + + + OUT_MEM_BURST_LENGTH_CH2 + Block size of Tx channel 2. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes + 6 + 3 + read-write + + + OUT_PAGE_BOUND_EN_CH2 + Set this bit to 1 to make sure AXI read data don't cross the address boundary which define by mem_burst_length + 12 + 1 + read-write + + + OUT_RST_CH2 + Write 1 then write 0 to this bit to reset TX channel + 24 + 1 + read-write + + + OUT_CMD_DISABLE_CH2 + Write 1 before reset and write 0 after reset + 25 + 1 + read-write + + + OUT_ARB_WEIGHT_OPT_DIS_CH2 + Set this bit to 1 to disable arbiter optimum weight function. + 26 + 1 + read-write + + + + + OUT_INT_RAW_CH2 + TX CH2 interrupt raw register + 0x204 + 0x20 + + + OUT_DONE_CH2_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0. + 0 + 1 + read-write + + + OUT_EOF_CH2_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. + 1 + 1 + read-write + + + OUT_DSCR_ERR_CH2_INT_RAW + The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0. + 2 + 1 + read-write + + + OUT_TOTAL_EOF_CH2_INT_RAW + The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0. + 3 + 1 + read-write + + + OUTFIFO_OVF_L1_CH2_INT_RAW + The raw interrupt bit turns to high level when fifo is overflow. + 4 + 1 + read-write + + + OUTFIFO_UDF_L1_CH2_INT_RAW + The raw interrupt bit turns to high level when fifo is underflow. + 5 + 1 + read-write + + + OUTFIFO_OVF_L2_CH2_INT_RAW + The raw interrupt bit turns to high level when fifo is overflow. + 6 + 1 + read-write + + + OUTFIFO_UDF_L2_CH2_INT_RAW + The raw interrupt bit turns to high level when fifo is underflow. + 7 + 1 + read-write + + + OUT_DSCR_TASK_OVF_CH2_INT_RAW + The raw interrupt bit turns to high level when dscr ready task fifo is overflow. + 8 + 1 + read-write + + + + + OUT_INT_ENA_CH2 + TX CH2 interrupt ena register + 0x208 + 0x20 + + + OUT_DONE_CH2_INT_ENA + The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + 0 + 1 + read-write + + + OUT_EOF_CH2_INT_ENA + The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + 1 + 1 + read-write + + + OUT_DSCR_ERR_CH2_INT_ENA + The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + read-write + + + OUT_TOTAL_EOF_CH2_INT_ENA + The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + read-write + + + OUTFIFO_OVF_L1_CH2_INT_ENA + The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-write + + + OUTFIFO_UDF_L1_CH2_INT_ENA + The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-write + + + OUTFIFO_OVF_L2_CH2_INT_ENA + The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-write + + + OUTFIFO_UDF_L2_CH2_INT_ENA + The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-write + + + OUT_DSCR_TASK_OVF_CH2_INT_ENA + The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. + 8 + 1 + read-write + + + + + OUT_INT_ST_CH2 + TX CH2 interrupt st register + 0x20C + 0x20 + + + OUT_DONE_CH2_INT_ST + The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + 0 + 1 + read-only + + + OUT_EOF_CH2_INT_ST + The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + 1 + 1 + read-only + + + OUT_DSCR_ERR_CH2_INT_ST + The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + read-only + + + OUT_TOTAL_EOF_CH2_INT_ST + The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + read-only + + + OUTFIFO_OVF_L1_CH2_INT_ST + The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-only + + + OUTFIFO_UDF_L1_CH2_INT_ST + The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-only + + + OUTFIFO_OVF_L2_CH2_INT_ST + The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-only + + + OUTFIFO_UDF_L2_CH2_INT_ST + The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-only + + + OUT_DSCR_TASK_OVF_CH2_INT_ST + The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. + 8 + 1 + read-only + + + + + OUT_INT_CLR_CH2 + TX CH2 interrupt clr register + 0x210 + 0x20 + + + OUT_DONE_CH2_INT_CLR + Set this bit to clear the OUT_DONE_CH_INT interrupt. + 0 + 1 + write-only + + + OUT_EOF_CH2_INT_CLR + Set this bit to clear the OUT_EOF_CH_INT interrupt. + 1 + 1 + write-only + + + OUT_DSCR_ERR_CH2_INT_CLR + Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + write-only + + + OUT_TOTAL_EOF_CH2_INT_CLR + Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + write-only + + + OUTFIFO_OVF_L1_CH2_INT_CLR + Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + write-only + + + OUTFIFO_UDF_L1_CH2_INT_CLR + Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + write-only + + + OUTFIFO_OVF_L2_CH2_INT_CLR + Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + write-only + + + OUTFIFO_UDF_L2_CH2_INT_CLR + Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + write-only + + + OUT_DSCR_TASK_OVF_CH2_INT_CLR + Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. + 8 + 1 + write-only + + + + + OUTFIFO_STATUS_CH2 + TX CH2 outfifo status register + 0x214 + 0x20 + 0x00020082 + + + OUTFIFO_FULL_L2_CH2 + Tx FIFO full signal for Tx channel 2. + 0 + 1 + read-only + + + OUTFIFO_EMPTY_L2_CH2 + Tx FIFO empty signal for Tx channel 2. + 1 + 1 + read-only + + + OUTFIFO_CNT_L2_CH2 + The register stores the byte number of the data in Tx FIFO for Tx channel 2. + 2 + 4 + read-only + + + OUTFIFO_FULL_L1_CH2 + Tx FIFO full signal for Tx channel 2. + 6 + 1 + read-only + + + OUTFIFO_EMPTY_L1_CH2 + Tx FIFO empty signal for Tx channel 2. + 7 + 1 + read-only + + + OUTFIFO_CNT_L1_CH2 + The register stores the byte number of the data in Tx FIFO for Tx channel 2. + 8 + 5 + read-only + + + OUTFIFO_FULL_L3_CH2 + Tx FIFO full signal for Tx channel 2. + 16 + 1 + read-only + + + OUTFIFO_EMPTY_L3_CH2 + Tx FIFO empty signal for Tx channel 2. + 17 + 1 + read-only + + + OUTFIFO_CNT_L3_CH2 + The register stores the byte number of the data in Tx FIFO for Tx channel 2. + 18 + 2 + read-only + + + + + OUT_PUSH_CH2 + TX CH2 outfifo push register + 0x218 + 0x20 + + + OUTFIFO_WDATA_CH2 + This register stores the data that need to be pushed into DMA Tx FIFO. + 0 + 10 + read-write + + + OUTFIFO_PUSH_CH2 + Set this bit to push data into DMA Tx FIFO. + 10 + 1 + read-write + + + + + OUT_LINK_CONF_CH2 + TX CH2 out_link dscr ctrl register + 0x21C + 0x20 + 0x00800000 + + + OUTLINK_STOP_CH2 + Set this bit to stop dealing with the outlink descriptors. + 20 + 1 + read-write + + + OUTLINK_START_CH2 + Set this bit to start dealing with the outlink descriptors. + 21 + 1 + read-write + + + OUTLINK_RESTART_CH2 + Set this bit to restart a new outlink from the last address. + 22 + 1 + read-write + + + OUTLINK_PARK_CH2 + 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. + 23 + 1 + read-only + + + + + OUT_LINK_ADDR_CH2 + TX CH2 out_link dscr addr register + 0x220 + 0x20 + + + OUTLINK_ADDR_CH2 + This register stores the first outlink descriptor's address. + 0 + 32 + read-write + + + + + OUT_STATE_CH2 + TX CH2 state register + 0x224 + 0x20 + 0x01000000 + + + OUTLINK_DSCR_ADDR_CH2 + This register stores the current outlink descriptor's address. + 0 + 18 + read-only + + + OUT_DSCR_STATE_CH2 + This register stores the current descriptor state machine state. + 18 + 2 + read-only + + + OUT_STATE_CH2 + This register stores the current control module state machine state. + 20 + 4 + read-only + + + OUT_RESET_AVAIL_CH2 + This register indicate that if the channel reset is safety. + 24 + 1 + read-only + + + + + OUT_EOF_DES_ADDR_CH2 + TX CH2 eof des addr register + 0x228 + 0x20 + + + OUT_EOF_DES_ADDR_CH2 + This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. + 0 + 32 + read-only + + + + + OUT_DSCR_CH2 + TX CH2 next dscr addr register + 0x22C + 0x20 + + + OUTLINK_DSCR_CH2 + The address of the next outlink descriptor address y. + 0 + 32 + read-only + + + + + OUT_DSCR_BF0_CH2 + TX CH2 last dscr addr register + 0x230 + 0x20 + + + OUTLINK_DSCR_BF0_CH2 + The address of the last outlink descriptor's next address y-1. + 0 + 32 + read-only + + + + + OUT_DSCR_BF1_CH2 + TX CH2 second-to-last dscr addr register + 0x234 + 0x20 + + + OUTLINK_DSCR_BF1_CH2 + The address of the second-to-last outlink descriptor's next address y-2. + 0 + 32 + read-only + + + + + OUT_ARB_CH2 + TX CH2 arb register + 0x23C + 0x20 + 0x00000041 + + + OUT_ARB_TOKEN_NUM_CH2 + Set the max number of token count of arbiter + 0 + 4 + read-write + + + INTER_OUT_ARB_PRIORITY_CH2 + Set the priority of channel + 6 + 1 + read-write + + + + + OUT_ETM_CONF_CH2 + TX CH2 ETM config register + 0x268 + 0x20 + 0x00000004 + + + OUT_ETM_EN_CH2 + Set this bit to 1 to enable ETM task function + 0 + 1 + read-write + + + OUT_ETM_LOOP_EN_CH2 + when this bit is 1, dscr can be processed after receiving a task + 1 + 1 + read-write + + + OUT_DSCR_TASK_MAK_CH2 + ETM dscr_ready maximum cache numbers + 2 + 2 + read-write + + + + + OUT_BUF_LEN_CH2 + tx CH2 buf len register + 0x270 + 0x20 + + + OUT_CMDFIFO_BUF_LEN_HB_CH2 + only for debug + 0 + 13 + read-only + + + + + OUT_FIFO_BCNT_CH2 + tx CH2 fifo byte cnt register + 0x274 + 0x20 + + + OUT_CMDFIFO_OUTFIFO_BCNT_CH2 + only for debug + 0 + 10 + read-only + + + + + OUT_PUSH_BYTECNT_CH2 + tx CH2 push byte cnt register + 0x278 + 0x20 + 0x000000FF + + + OUT_CMDFIFO_PUSH_BYTECNT_CH2 + only for debug + 0 + 8 + read-only + + + + + OUT_XADDR_CH2 + tx CH2 xaddr register + 0x27C + 0x20 + + + OUT_CMDFIFO_XADDR_CH2 + only for debug + 0 + 32 + read-only + + + + + OUT_CONF0_CH3 + TX CH3 config0 register + 0x300 + 0x20 + 0x00000002 + + + OUT_AUTO_WRBACK_CH3 + Set this bit to enable automatic outlink-writeback when all the data pointed by outlink descriptor has been received. + 0 + 1 + read-write + + + OUT_EOF_MODE_CH3 + EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is generated when data need to read has been popped from FIFO in DMA + 1 + 1 + read-write + + + OUTDSCR_BURST_EN_CH3 + Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. + 2 + 1 + read-write + + + OUT_ECC_AES_EN_CH3 + When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned. + 3 + 1 + read-write + + + OUT_CHECK_OWNER_CH3 + Set this bit to enable checking the owner attribute of the link descriptor. + 4 + 1 + read-write + + + OUT_MEM_BURST_LENGTH_CH3 + Block size of Tx channel 3. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes + 6 + 3 + read-write + + + OUT_PAGE_BOUND_EN_CH3 + Set this bit to 1 to make sure AXI read data don't cross the address boundary which define by mem_burst_length + 12 + 1 + read-write + + + OUT_ARB_WEIGHT_OPT_DIS_CH3 + Set this bit to 1 to disable arbiter optimum weight function. + 26 + 1 + read-write + + + + + OUT_INT_RAW_CH3 + TX CH3 interrupt raw register + 0x304 + 0x20 + + + OUT_DONE_CH3_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0. + 0 + 1 + read-write + + + OUT_EOF_CH3_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. + 1 + 1 + read-write + + + OUT_DSCR_ERR_CH3_INT_RAW + The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0. + 2 + 1 + read-write + + + OUT_TOTAL_EOF_CH3_INT_RAW + The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0. + 3 + 1 + read-write + + + OUTFIFO_OVF_L1_CH3_INT_RAW + The raw interrupt bit turns to high level when fifo is overflow. + 4 + 1 + read-write + + + OUTFIFO_UDF_L1_CH3_INT_RAW + The raw interrupt bit turns to high level when fifo is underflow. + 5 + 1 + read-write + + + OUTFIFO_OVF_L2_CH3_INT_RAW + The raw interrupt bit turns to high level when fifo is overflow. + 6 + 1 + read-write + + + OUTFIFO_UDF_L2_CH3_INT_RAW + The raw interrupt bit turns to high level when fifo is underflow. + 7 + 1 + read-write + + + OUT_DSCR_TASK_OVF_CH3_INT_RAW + The raw interrupt bit turns to high level when dscr ready task fifo is overflow. + 8 + 1 + read-write + + + + + OUT_INT_ENA_CH3 + TX CH3 interrupt ena register + 0x308 + 0x20 + + + OUT_DONE_CH3_INT_ENA + The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + 0 + 1 + read-write + + + OUT_EOF_CH3_INT_ENA + The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + 1 + 1 + read-write + + + OUT_DSCR_ERR_CH3_INT_ENA + The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + read-write + + + OUT_TOTAL_EOF_CH3_INT_ENA + The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + read-write + + + OUTFIFO_OVF_L1_CH3_INT_ENA + The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-write + + + OUTFIFO_UDF_L1_CH3_INT_ENA + The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-write + + + OUTFIFO_OVF_L2_CH3_INT_ENA + The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-write + + + OUTFIFO_UDF_L2_CH3_INT_ENA + The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-write + + + OUT_DSCR_TASK_OVF_CH3_INT_ENA + The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. + 8 + 1 + read-write + + + + + OUT_INT_ST_CH3 + TX CH3 interrupt st register + 0x30C + 0x20 + + + OUT_DONE_CH3_INT_ST + The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + 0 + 1 + read-only + + + OUT_EOF_CH3_INT_ST + The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + 1 + 1 + read-only + + + OUT_DSCR_ERR_CH3_INT_ST + The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + read-only + + + OUT_TOTAL_EOF_CH3_INT_ST + The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + read-only + + + OUTFIFO_OVF_L1_CH3_INT_ST + The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-only + + + OUTFIFO_UDF_L1_CH3_INT_ST + The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-only + + + OUTFIFO_OVF_L2_CH3_INT_ST + The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-only + + + OUTFIFO_UDF_L2_CH3_INT_ST + The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-only + + + OUT_DSCR_TASK_OVF_CH3_INT_ST + The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. + 8 + 1 + read-only + + + + + OUT_INT_CLR_CH3 + TX CH3 interrupt clr register + 0x310 + 0x20 + + + OUT_DONE_CH3_INT_CLR + Set this bit to clear the OUT_DONE_CH_INT interrupt. + 0 + 1 + write-only + + + OUT_EOF_CH3_INT_CLR + Set this bit to clear the OUT_EOF_CH_INT interrupt. + 1 + 1 + write-only + + + OUT_DSCR_ERR_CH3_INT_CLR + Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + write-only + + + OUT_TOTAL_EOF_CH3_INT_CLR + Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + write-only + + + OUTFIFO_OVF_L1_CH3_INT_CLR + Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + write-only + + + OUTFIFO_UDF_L1_CH3_INT_CLR + Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + write-only + + + OUTFIFO_OVF_L2_CH3_INT_CLR + Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + write-only + + + OUTFIFO_UDF_L2_CH3_INT_CLR + Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + write-only + + + OUT_DSCR_TASK_OVF_CH3_INT_CLR + Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. + 8 + 1 + write-only + + + + + OUTFIFO_STATUS_CH3 + TX CH3 outfifo status register + 0x314 + 0x20 + 0x00020082 + + + OUTFIFO_FULL_L2_CH3 + Tx FIFO full signal for Tx channel 2. + 0 + 1 + read-only + + + OUTFIFO_EMPTY_L2_CH3 + Tx FIFO empty signal for Tx channel 2. + 1 + 1 + read-only + + + OUTFIFO_CNT_L2_CH3 + The register stores the byte number of the data in Tx FIFO for Tx channel 2. + 2 + 4 + read-only + + + OUTFIFO_FULL_L1_CH3 + Tx FIFO full signal for Tx channel 2. + 6 + 1 + read-only + + + OUTFIFO_EMPTY_L1_CH3 + Tx FIFO empty signal for Tx channel 2. + 7 + 1 + read-only + + + OUTFIFO_CNT_L1_CH3 + The register stores the byte number of the data in Tx FIFO for Tx channel 2. + 8 + 5 + read-only + + + OUTFIFO_FULL_L3_CH3 + Tx FIFO full signal for Tx channel 2. + 16 + 1 + read-only + + + OUTFIFO_EMPTY_L3_CH3 + Tx FIFO empty signal for Tx channel 2. + 17 + 1 + read-only + + + OUTFIFO_CNT_L3_CH3 + The register stores the byte number of the data in Tx FIFO for Tx channel 2. + 18 + 2 + read-only + + + + + OUT_PUSH_CH3 + TX CH3 outfifo push register + 0x318 + 0x20 + + + OUTFIFO_WDATA_CH3 + This register stores the data that need to be pushed into DMA Tx FIFO. + 0 + 10 + read-write + + + OUTFIFO_PUSH_CH3 + Set this bit to push data into DMA Tx FIFO. + 10 + 1 + read-write + + + + + OUT_LINK_CONF_CH3 + TX CH3 out_link dscr ctrl register + 0x31C + 0x20 + 0x00800000 + + + OUTLINK_STOP_CH3 + Set this bit to stop dealing with the outlink descriptors. + 20 + 1 + read-write + + + OUTLINK_START_CH3 + Set this bit to start dealing with the outlink descriptors. + 21 + 1 + read-write + + + OUTLINK_RESTART_CH3 + Set this bit to restart a new outlink from the last address. + 22 + 1 + read-write + + + OUTLINK_PARK_CH3 + 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. + 23 + 1 + read-only + + + + + OUT_LINK_ADDR_CH3 + TX CH3 out_link dscr addr register + 0x320 + 0x20 + + + OUTLINK_ADDR_CH3 + This register stores the first outlink descriptor's address. + 0 + 32 + read-write + + + + + OUT_STATE_CH3 + TX CH3 state register + 0x324 + 0x20 + + + OUTLINK_DSCR_ADDR_CH3 + This register stores the current outlink descriptor's address. + 0 + 18 + read-only + + + OUT_DSCR_STATE_CH3 + This register stores the current descriptor state machine state. + 18 + 2 + read-only + + + OUT_STATE_CH3 + This register stores the current control module state machine state. + 20 + 4 + read-only + + + + + OUT_EOF_DES_ADDR_CH3 + TX CH3 eof des addr register + 0x328 + 0x20 + + + OUT_EOF_DES_ADDR_CH3 + This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. + 0 + 32 + read-only + + + + + OUT_DSCR_CH3 + TX CH3 next dscr addr register + 0x32C + 0x20 + + + OUTLINK_DSCR_CH3 + The address of the next outlink descriptor address y. + 0 + 32 + read-only + + + + + OUT_DSCR_BF0_CH3 + TX CH3 last dscr addr register + 0x330 + 0x20 + + + OUTLINK_DSCR_BF0_CH3 + The address of the last outlink descriptor's next address y-1. + 0 + 32 + read-only + + + + + OUT_DSCR_BF1_CH3 + TX CH3 second-to-last dscr addr register + 0x334 + 0x20 + + + OUTLINK_DSCR_BF1_CH3 + The address of the second-to-last outlink descriptor's next address y-2. + 0 + 32 + read-only + + + + + OUT_ARB_CH3 + TX CH3 arb register + 0x33C + 0x20 + 0x00000011 + + + OUT_ARB_TOKEN_NUM_CH3 + Set the max number of token count of arbiter + 0 + 4 + read-write + + + EXTER_OUT_ARB_PRIORITY_CH3 + Set the priority of channel + 4 + 2 + read-write + + + + + OUT_ETM_CONF_CH3 + TX CH3 ETM config register + 0x368 + 0x20 + 0x00000004 + + + OUT_ETM_EN_CH3 + Set this bit to 1 to enable ETM task function + 0 + 1 + read-write + + + OUT_ETM_LOOP_EN_CH3 + when this bit is 1, dscr can be processed after receiving a task + 1 + 1 + read-write + + + OUT_DSCR_TASK_MAK_CH3 + ETM dscr_ready maximum cache numbers + 2 + 2 + read-write + + + + + OUT_BUF_LEN_CH3 + tx CH3 buf len register + 0x370 + 0x20 + + + OUT_CMDFIFO_BUF_LEN_HB_CH3 + only for debug + 0 + 13 + read-only + + + + + OUT_FIFO_BCNT_CH3 + tx CH3 fifo byte cnt register + 0x374 + 0x20 + + + OUT_CMDFIFO_OUTFIFO_BCNT_CH3 + only for debug + 0 + 10 + read-only + + + + + OUT_PUSH_BYTECNT_CH3 + tx CH3 push byte cnt register + 0x378 + 0x20 + 0x0000003F + + + OUT_CMDFIFO_PUSH_BYTECNT_CH3 + only for debug + 0 + 8 + read-only + + + + + OUT_XADDR_CH3 + tx CH3 xaddr register + 0x37C + 0x20 + + + OUT_CMDFIFO_XADDR_CH3 + only for debug + 0 + 32 + read-only + + + + + OUT_BLOCK_BUF_LEN_CH3 + tx CH3 block buf len register + 0x380 + 0x20 + + + OUT_BLOCK_BUF_LEN_CH3 + only for debug + 0 + 28 + read-only + + + + + OUT_CONF0_CH4 + TX CH4 config0 register + 0x400 + 0x20 + 0x00000002 + + + OUT_AUTO_WRBACK_CH4 + Set this bit to enable automatic outlink-writeback when all the data pointed by outlink descriptor has been received. + 0 + 1 + read-write + + + OUT_EOF_MODE_CH4 + EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is generated when data need to read has been popped from FIFO in DMA + 1 + 1 + read-write + + + OUTDSCR_BURST_EN_CH4 + Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. + 2 + 1 + read-write + + + OUT_ECC_AES_EN_CH4 + When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned. + 3 + 1 + read-write + + + OUT_CHECK_OWNER_CH4 + Set this bit to enable checking the owner attribute of the link descriptor. + 4 + 1 + read-write + + + OUT_MEM_BURST_LENGTH_CH4 + Block size of Tx channel 4. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes + 6 + 3 + read-write + + + OUT_PAGE_BOUND_EN_CH4 + Set this bit to 1 to make sure AXI read data don't cross the address boundary which define by mem_burst_length + 12 + 1 + read-write + + + OUT_ARB_WEIGHT_OPT_DIS_CH4 + Set this bit to 1 to disable arbiter optimum weight function. + 26 + 1 + read-write + + + + + OUT_INT_RAW_CH4 + TX CH4 interrupt raw register + 0x404 + 0x20 + + + OUT_DONE_CH4_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0. + 0 + 1 + read-write + + + OUT_EOF_CH4_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. + 1 + 1 + read-write + + + OUT_DSCR_ERR_CH4_INT_RAW + The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0. + 2 + 1 + read-write + + + OUT_TOTAL_EOF_CH4_INT_RAW + The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0. + 3 + 1 + read-write + + + OUTFIFO_OVF_L1_CH4_INT_RAW + The raw interrupt bit turns to high level when fifo is overflow. + 4 + 1 + read-write + + + OUTFIFO_UDF_L1_CH4_INT_RAW + The raw interrupt bit turns to high level when fifo is underflow. + 5 + 1 + read-write + + + OUTFIFO_OVF_L2_CH4_INT_RAW + The raw interrupt bit turns to high level when fifo is overflow. + 6 + 1 + read-write + + + OUTFIFO_UDF_L2_CH4_INT_RAW + The raw interrupt bit turns to high level when fifo is underflow. + 7 + 1 + read-write + + + OUT_DSCR_TASK_OVF_CH4_INT_RAW + The raw interrupt bit turns to high level when dscr ready task fifo is overflow. + 8 + 1 + read-write + + + + + OUT_INT_ENA_CH4 + TX CH4 interrupt ena register + 0x408 + 0x20 + + + OUT_DONE_CH4_INT_ENA + The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + 0 + 1 + read-write + + + OUT_EOF_CH4_INT_ENA + The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + 1 + 1 + read-write + + + OUT_DSCR_ERR_CH4_INT_ENA + The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + read-write + + + OUT_TOTAL_EOF_CH4_INT_ENA + The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + read-write + + + OUTFIFO_OVF_L1_CH4_INT_ENA + The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-write + + + OUTFIFO_UDF_L1_CH4_INT_ENA + The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-write + + + OUTFIFO_OVF_L2_CH4_INT_ENA + The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-write + + + OUTFIFO_UDF_L2_CH4_INT_ENA + The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-write + + + OUT_DSCR_TASK_OVF_CH4_INT_ENA + The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. + 8 + 1 + read-write + + + + + OUT_INT_ST_CH4 + TX CH4 interrupt st register + 0x40C + 0x20 + + + OUT_DONE_CH4_INT_ST + The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + 0 + 1 + read-only + + + OUT_EOF_CH4_INT_ST + The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + 1 + 1 + read-only + + + OUT_DSCR_ERR_CH4_INT_ST + The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + read-only + + + OUT_TOTAL_EOF_CH4_INT_ST + The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + read-only + + + OUTFIFO_OVF_L1_CH4_INT_ST + The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-only + + + OUTFIFO_UDF_L1_CH4_INT_ST + The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-only + + + OUTFIFO_OVF_L2_CH4_INT_ST + The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-only + + + OUTFIFO_UDF_L2_CH4_INT_ST + The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-only + + + OUT_DSCR_TASK_OVF_CH4_INT_ST + The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. + 8 + 1 + read-only + + + + + OUT_INT_CLR_CH4 + TX CH4 interrupt clr register + 0x410 + 0x20 + + + OUT_DONE_CH4_INT_CLR + Set this bit to clear the OUT_DONE_CH_INT interrupt. + 0 + 1 + write-only + + + OUT_EOF_CH4_INT_CLR + Set this bit to clear the OUT_EOF_CH_INT interrupt. + 1 + 1 + write-only + + + OUT_DSCR_ERR_CH4_INT_CLR + Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + write-only + + + OUT_TOTAL_EOF_CH4_INT_CLR + Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + write-only + + + OUTFIFO_OVF_L1_CH4_INT_CLR + Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + write-only + + + OUTFIFO_UDF_L1_CH4_INT_CLR + Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + write-only + + + OUTFIFO_OVF_L2_CH4_INT_CLR + Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + write-only + + + OUTFIFO_UDF_L2_CH4_INT_CLR + Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + write-only + + + OUT_DSCR_TASK_OVF_CH4_INT_CLR + Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. + 8 + 1 + write-only + + + + + OUTFIFO_STATUS_CH4 + TX CH4 outfifo status register + 0x414 + 0x20 + 0x00020082 + + + OUTFIFO_FULL_L2_CH4 + Tx FIFO full signal for Tx channel 2. + 0 + 1 + read-only + + + OUTFIFO_EMPTY_L2_CH4 + Tx FIFO empty signal for Tx channel 2. + 1 + 1 + read-only + + + OUTFIFO_CNT_L2_CH4 + The register stores the byte number of the data in Tx FIFO for Tx channel 2. + 2 + 4 + read-only + + + OUTFIFO_FULL_L1_CH4 + Tx FIFO full signal for Tx channel 2. + 6 + 1 + read-only + + + OUTFIFO_EMPTY_L1_CH4 + Tx FIFO empty signal for Tx channel 2. + 7 + 1 + read-only + + + OUTFIFO_CNT_L1_CH4 + The register stores the byte number of the data in Tx FIFO for Tx channel 2. + 8 + 5 + read-only + + + OUTFIFO_FULL_L3_CH4 + Tx FIFO full signal for Tx channel 2. + 16 + 1 + read-only + + + OUTFIFO_EMPTY_L3_CH4 + Tx FIFO empty signal for Tx channel 2. + 17 + 1 + read-only + + + OUTFIFO_CNT_L3_CH4 + The register stores the byte number of the data in Tx FIFO for Tx channel 2. + 18 + 2 + read-only + + + + + OUT_PUSH_CH4 + TX CH4 outfifo push register + 0x418 + 0x20 + + + OUTFIFO_WDATA_CH4 + This register stores the data that need to be pushed into DMA Tx FIFO. + 0 + 10 + read-write + + + OUTFIFO_PUSH_CH4 + Set this bit to push data into DMA Tx FIFO. + 10 + 1 + read-write + + + + + OUT_LINK_CONF_CH4 + TX CH4 out_link dscr ctrl register + 0x41C + 0x20 + 0x00800000 + + + OUTLINK_STOP_CH4 + Set this bit to stop dealing with the outlink descriptors. + 20 + 1 + read-write + + + OUTLINK_START_CH4 + Set this bit to start dealing with the outlink descriptors. + 21 + 1 + read-write + + + OUTLINK_RESTART_CH4 + Set this bit to restart a new outlink from the last address. + 22 + 1 + read-write + + + OUTLINK_PARK_CH4 + 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. + 23 + 1 + read-only + + + + + OUT_LINK_ADDR_CH4 + TX CH4 out_link dscr addr register + 0x420 + 0x20 + + + OUTLINK_ADDR_CH4 + This register stores the first outlink descriptor's address. + 0 + 32 + read-write + + + + + OUT_STATE_CH4 + TX CH4 state register + 0x424 + 0x20 + + + OUTLINK_DSCR_ADDR_CH4 + This register stores the current outlink descriptor's address. + 0 + 18 + read-only + + + OUT_DSCR_STATE_CH4 + This register stores the current descriptor state machine state. + 18 + 2 + read-only + + + OUT_STATE_CH4 + This register stores the current control module state machine state. + 20 + 4 + read-only + + + + + OUT_EOF_DES_ADDR_CH4 + TX CH4 eof des addr register + 0x428 + 0x20 + + + OUT_EOF_DES_ADDR_CH4 + This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. + 0 + 32 + read-only + + + + + OUT_DSCR_CH4 + TX CH4 next dscr addr register + 0x42C + 0x20 + + + OUTLINK_DSCR_CH4 + The address of the next outlink descriptor address y. + 0 + 32 + read-only + + + + + OUT_DSCR_BF0_CH4 + TX CH4 last dscr addr register + 0x430 + 0x20 + + + OUTLINK_DSCR_BF0_CH4 + The address of the last outlink descriptor's next address y-1. + 0 + 32 + read-only + + + + + OUT_DSCR_BF1_CH4 + TX CH4 second-to-last dscr addr register + 0x434 + 0x20 + + + OUTLINK_DSCR_BF1_CH4 + The address of the second-to-last outlink descriptor's next address y-2. + 0 + 32 + read-only + + + + + OUT_ARB_CH4 + TX CH4 arb register + 0x43C + 0x20 + 0x00000011 + + + OUT_ARB_TOKEN_NUM_CH4 + Set the max number of token count of arbiter + 0 + 4 + read-write + + + EXTER_OUT_ARB_PRIORITY_CH4 + Set the priority of channel + 4 + 2 + read-write + + + + + OUT_ETM_CONF_CH4 + TX CH4 ETM config register + 0x468 + 0x20 + 0x00000004 + + + OUT_ETM_EN_CH4 + Set this bit to 1 to enable ETM task function + 0 + 1 + read-write + + + OUT_ETM_LOOP_EN_CH4 + when this bit is 1, dscr can be processed after receiving a task + 1 + 1 + read-write + + + OUT_DSCR_TASK_MAK_CH4 + ETM dscr_ready maximum cache numbers + 2 + 2 + read-write + + + + + OUT_BUF_LEN_CH4 + tx CH4 buf len register + 0x470 + 0x20 + + + OUT_CMDFIFO_BUF_LEN_HB_CH4 + only for debug + 0 + 13 + read-only + + + + + OUT_FIFO_BCNT_CH4 + tx CH4 fifo byte cnt register + 0x474 + 0x20 + + + OUT_CMDFIFO_OUTFIFO_BCNT_CH4 + only for debug + 0 + 10 + read-only + + + + + OUT_PUSH_BYTECNT_CH4 + tx CH4 push byte cnt register + 0x478 + 0x20 + 0x0000003F + + + OUT_CMDFIFO_PUSH_BYTECNT_CH4 + only for debug + 0 + 8 + read-only + + + + + OUT_XADDR_CH4 + tx CH4 xaddr register + 0x47C + 0x20 + + + OUT_CMDFIFO_XADDR_CH4 + only for debug + 0 + 32 + read-only + + + + + OUT_BLOCK_BUF_LEN_CH4 + tx CH4 block buf len register + 0x480 + 0x20 + + + OUT_BLOCK_BUF_LEN_CH4 + only for debug + 0 + 28 + read-only + + + + + IN_CONF0_CH0 + RX CH0 config0 register + 0x500 + 0x20 + + + INDSCR_BURST_EN_CH0 + Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor when accessing SRAM. + 2 + 1 + read-write + + + IN_ECC_AES_EN_CH0 + When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned. + 3 + 1 + read-write + + + IN_CHECK_OWNER_CH0 + Set this bit to enable checking the owner attribute of the link descriptor. + 4 + 1 + read-write + + + IN_MEM_BURST_LENGTH_CH0 + Block size of Rx channel 0. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes + 6 + 3 + read-write + + + IN_PAGE_BOUND_EN_CH0 + Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length + 12 + 1 + read-write + + + IN_RST_CH0 + Write 1 then write 0 to this bit to reset Rx channel + 24 + 1 + read-write + + + IN_CMD_DISABLE_CH0 + Write 1 before reset and write 0 after reset + 25 + 1 + read-write + + + IN_ARB_WEIGHT_OPT_DIS_CH0 + Set this bit to 1 to disable arbiter optimum weight function. + 26 + 1 + read-write + + + + + IN_INT_RAW_CH0 + RX CH0 interrupt raw register + 0x504 + 0x20 + + + IN_DONE_CH0_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 0. + 0 + 1 + read-write + + + IN_SUC_EOF_CH0_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0. + 1 + 1 + read-write + + + IN_ERR_EOF_CH0_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and data error is detected + 2 + 1 + read-write + + + IN_DSCR_ERR_CH0_INT_RAW + The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0. + 3 + 1 + read-write + + + INFIFO_OVF_L1_CH0_INT_RAW + The raw interrupt bit turns to high level when fifo of Rx channel is overflow. + 4 + 1 + read-write + + + INFIFO_UDF_L1_CH0_INT_RAW + The raw interrupt bit turns to high level when fifo of Rx channel is underflow. + 5 + 1 + read-write + + + INFIFO_OVF_L2_CH0_INT_RAW + The raw interrupt bit turns to high level when fifo of Rx channel is overflow. + 6 + 1 + read-write + + + INFIFO_UDF_L2_CH0_INT_RAW + The raw interrupt bit turns to high level when fifo of Rx channel is underflow. + 7 + 1 + read-write + + + IN_DSCR_EMPTY_CH0_INT_RAW + The raw interrupt bit turns to high level when the last descriptor is done but fifo also remain data. + 8 + 1 + read-write + + + IN_DSCR_TASK_OVF_CH0_INT_RAW + The raw interrupt bit turns to high level when dscr ready task fifo is overflow. + 9 + 1 + read-write + + + + + IN_INT_ENA_CH0 + RX CH0 interrupt ena register + 0x508 + 0x20 + + + IN_DONE_CH0_INT_ENA + The interrupt enable bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-write + + + IN_SUC_EOF_CH0_INT_ENA + The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-write + + + IN_ERR_EOF_CH0_INT_ENA + The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + read-write + + + IN_DSCR_ERR_CH0_INT_ENA + The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 + read-write + + + INFIFO_OVF_L1_CH0_INT_ENA + The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-write + + + INFIFO_UDF_L1_CH0_INT_ENA + The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-write + + + INFIFO_OVF_L2_CH0_INT_ENA + The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-write + + + INFIFO_UDF_L2_CH0_INT_ENA + The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-write + + + IN_DSCR_EMPTY_CH0_INT_ENA + The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + 8 + 1 + read-write + + + IN_DSCR_TASK_OVF_CH0_INT_ENA + The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. + 9 + 1 + read-write + + + + + IN_INT_ST_CH0 + RX CH0 interrupt st register + 0x50C + 0x20 + + + IN_DONE_CH0_INT_ST + The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-only + + + IN_SUC_EOF_CH0_INT_ST + The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-only + + + IN_ERR_EOF_CH0_INT_ST + The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + read-only + + + IN_DSCR_ERR_CH0_INT_ST + The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 + read-only + + + INFIFO_OVF_L1_CH0_INT_ST + The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-only + + + INFIFO_UDF_L1_CH0_INT_ST + The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-only + + + INFIFO_OVF_L2_CH0_INT_ST + The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-only + + + INFIFO_UDF_L2_CH0_INT_ST + The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-only + + + IN_DSCR_EMPTY_CH0_INT_ST + The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + 8 + 1 + read-only + + + IN_DSCR_TASK_OVF_CH0_INT_ST + The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. + 9 + 1 + read-only + + + + + IN_INT_CLR_CH0 + RX CH0 interrupt clr register + 0x510 + 0x20 + + + IN_DONE_CH0_INT_CLR + Set this bit to clear the IN_DONE_CH_INT interrupt. + 0 + 1 + write-only + + + IN_SUC_EOF_CH0_INT_CLR + Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + write-only + + + IN_ERR_EOF_CH0_INT_CLR + Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + write-only + + + IN_DSCR_ERR_CH0_INT_CLR + Set this bit to clear the INDSCR_ERR_CH_INT interrupt. + 3 + 1 + write-only + + + INFIFO_OVF_L1_CH0_INT_CLR + Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + write-only + + + INFIFO_UDF_L1_CH0_INT_CLR + Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + write-only + + + INFIFO_OVF_L2_CH0_INT_CLR + Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + write-only + + + INFIFO_UDF_L2_CH0_INT_CLR + Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + write-only + + + IN_DSCR_EMPTY_CH0_INT_CLR + Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + 8 + 1 + write-only + + + IN_DSCR_TASK_OVF_CH0_INT_CLR + Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. + 9 + 1 + write-only + + + + + INFIFO_STATUS_CH0 + RX CH0 INFIFO status register + 0x514 + 0x20 + 0x00020082 + + + INFIFO_FULL_L2_CH0 + Rx FIFO full signal for Rx channel. + 0 + 1 + read-only + + + INFIFO_EMPTY_L2_CH0 + Rx FIFO empty signal for Rx channel. + 1 + 1 + read-only + + + INFIFO_CNT_L2_CH0 + The register stores the byte number of the data in Rx FIFO for Rx channel. + 2 + 4 + read-only + + + INFIFO_FULL_L1_CH0 + Tx FIFO full signal for Tx channel 0. + 6 + 1 + read-only + + + INFIFO_EMPTY_L1_CH0 + Tx FIFO empty signal for Tx channel 0. + 7 + 1 + read-only + + + INFIFO_CNT_L1_CH0 + The register stores the byte number of the data in Tx FIFO for Tx channel 0. + 8 + 5 + read-only + + + INFIFO_FULL_L3_CH0 + Tx FIFO full signal for Tx channel 0. + 16 + 1 + read-only + + + INFIFO_EMPTY_L3_CH0 + Tx FIFO empty signal for Tx channel 0. + 17 + 1 + read-only + + + INFIFO_CNT_L3_CH0 + The register stores the 8byte number of the data in Tx FIFO for Tx channel 0. + 18 + 2 + read-only + + + + + IN_POP_CH0 + RX CH0 INFIFO pop register + 0x518 + 0x20 + 0x00000400 + + + INFIFO_RDATA_CH0 + This register stores the data popping from DMA Rx FIFO. + 0 + 11 + read-only + + + INFIFO_POP_CH0 + Set this bit to pop data from DMA Rx FIFO. + 11 + 1 + read-write + + + + + IN_LINK_CONF_CH0 + RX CH0 in_link dscr ctrl register + 0x51C + 0x20 + 0x01100000 + + + INLINK_AUTO_RET_CH0 + Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data. + 20 + 1 + read-write + + + INLINK_STOP_CH0 + Set this bit to stop dealing with the inlink descriptors. + 21 + 1 + read-write + + + INLINK_START_CH0 + Set this bit to start dealing with the inlink descriptors. + 22 + 1 + read-write + + + INLINK_RESTART_CH0 + Set this bit to mount a new inlink descriptor. + 23 + 1 + read-write + + + INLINK_PARK_CH0 + 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. + 24 + 1 + read-only + + + + + IN_LINK_ADDR_CH0 + RX CH0 in_link dscr addr register + 0x520 + 0x20 + + + INLINK_ADDR_CH0 + This register stores the first inlink descriptor's address. + 0 + 32 + read-write + + + + + IN_STATE_CH0 + RX CH0 state register + 0x524 + 0x20 + 0x00800000 + + + INLINK_DSCR_ADDR_CH0 + This register stores the current inlink descriptor's address. + 0 + 18 + read-only + + + IN_DSCR_STATE_CH0 + This register stores the current descriptor state machine state. + 18 + 2 + read-only + + + IN_STATE_CH0 + This register stores the current control module state machine state. + 20 + 3 + read-only + + + IN_RESET_AVAIL_CH0 + This register indicate that if the channel reset is safety. + 23 + 1 + read-only + + + + + IN_SUC_EOF_DES_ADDR_CH0 + RX CH0 eof des addr register + 0x528 + 0x20 + + + IN_SUC_EOF_DES_ADDR_CH0 + This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. + 0 + 32 + read-only + + + + + IN_ERR_EOF_DES_ADDR_CH0 + RX CH0 err eof des addr register + 0x52C + 0x20 + + + IN_ERR_EOF_DES_ADDR_CH0 + This register stores the address of the inlink descriptor when there are some errors in current receiving data. + 0 + 32 + read-only + + + + + IN_DSCR_CH0 + RX CH0 next dscr addr register + 0x530 + 0x20 + + + INLINK_DSCR_CH0 + The address of the next inlink descriptor address x. + 0 + 32 + read-only + + + + + IN_DSCR_BF0_CH0 + RX CH0 last dscr addr register + 0x534 + 0x20 + + + INLINK_DSCR_BF0_CH0 + The address of the last inlink descriptor's next address x-1. + 0 + 32 + read-only + + + + + IN_DSCR_BF1_CH0 + RX CH0 second-to-last dscr addr register + 0x538 + 0x20 + + + INLINK_DSCR_BF1_CH0 + The address of the second-to-last inlink descriptor's next address x-2. + 0 + 32 + read-only + + + + + IN_ARB_CH0 + RX CH0 arb register + 0x540 + 0x20 + 0x00000051 + + + IN_ARB_TOKEN_NUM_CH0 + Set the max number of token count of arbiter + 0 + 4 + read-write + + + EXTER_IN_ARB_PRIORITY_CH0 + Set the priority of channel + 4 + 2 + read-write + + + INTER_IN_ARB_PRIORITY_CH0 + Set the priority of channel + 6 + 3 + read-write + + + + + IN_RO_PD_CONF_CH0 + RX CH0 reorder power config register + 0x548 + 0x20 + + + IN_RO_RAM_CLK_FO_CH0 + 1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. 0: A gate-clock will be used when accessing the RAM in DMA. + 6 + 1 + read-write + + + + + IN_ETM_CONF_CH0 + RX CH0 ETM config register + 0x56C + 0x20 + 0x00000004 + + + IN_ETM_EN_CH0 + Set this bit to 1 to enable ETM task function + 0 + 1 + read-write + + + IN_ETM_LOOP_EN_CH0 + when this bit is 1, dscr can be processed after receiving a task + 1 + 1 + read-write + + + IN_DSCR_TASK_MAK_CH0 + ETM dscr_ready maximum cache numbers + 2 + 2 + read-write + + + + + IN_FIFO_CNT_CH0 + rx CH0 fifo cnt register + 0x580 + 0x20 + + + IN_CMDFIFO_INFIFO_CNT_CH0 + only for debug + 0 + 10 + read-only + + + + + IN_POP_DATA_CNT_CH0 + rx CH0 pop data cnt register + 0x584 + 0x20 + 0x00000007 + + + IN_CMDFIFO_POP_DATA_CNT_CH0 + only for debug + 0 + 8 + read-only + + + + + IN_XADDR_CH0 + rx CH0 xaddr register + 0x588 + 0x20 + + + IN_CMDFIFO_XADDR_CH0 + only for debug + 0 + 32 + read-only + + + + + IN_BUF_HB_RCV_CH0 + rx CH0 buf len hb rcv register + 0x58C + 0x20 + + + IN_CMDFIFO_BUF_HB_RCV_CH0 + only for debug + 0 + 29 + read-only + + + + + IN_CONF0_CH1 + RX CH1 config0 register + 0x600 + 0x20 + + + INDSCR_BURST_EN_CH1 + Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor when accessing SRAM. + 2 + 1 + read-write + + + IN_ECC_AES_EN_CH1 + When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned. + 3 + 1 + read-write + + + IN_CHECK_OWNER_CH1 + Set this bit to enable checking the owner attribute of the link descriptor. + 4 + 1 + read-write + + + IN_MEM_BURST_LENGTH_CH1 + Block size of Rx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes + 6 + 3 + read-write + + + IN_PAGE_BOUND_EN_CH1 + Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length + 12 + 1 + read-write + + + IN_RST_CH1 + Write 1 then write 0 to this bit to reset Rx channel + 24 + 1 + read-write + + + IN_CMD_DISABLE_CH1 + Write 1 before reset and write 0 after reset + 25 + 1 + read-write + + + IN_ARB_WEIGHT_OPT_DIS_CH1 + Set this bit to 1 to disable arbiter optimum weight function. + 26 + 1 + read-write + + + + + IN_INT_RAW_CH1 + RX CH1 interrupt raw register + 0x604 + 0x20 + + + IN_DONE_CH1_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 1. + 0 + 1 + read-write + + + IN_SUC_EOF_CH1_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1. + 1 + 1 + read-write + + + IN_ERR_EOF_CH1_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and data error is detected + 2 + 1 + read-write + + + IN_DSCR_ERR_CH1_INT_RAW + The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 1. + 3 + 1 + read-write + + + INFIFO_OVF_L1_CH1_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is overflow. + 4 + 1 + read-write + + + INFIFO_UDF_L1_CH1_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is underflow. + 5 + 1 + read-write + + + INFIFO_OVF_L2_CH1_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is overflow. + 6 + 1 + read-write + + + INFIFO_UDF_L2_CH1_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is underflow. + 7 + 1 + read-write + + + IN_DSCR_EMPTY_CH1_INT_RAW + The raw interrupt bit turns to high level when the last descriptor is done but fifo also remain data. + 8 + 1 + read-write + + + IN_DSCR_TASK_OVF_CH1_INT_RAW + The raw interrupt bit turns to high level when dscr ready task fifo is overflow. + 9 + 1 + read-write + + + + + IN_INT_ENA_CH1 + RX CH1 interrupt ena register + 0x608 + 0x20 + + + IN_DONE_CH1_INT_ENA + The interrupt enable bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-write + + + IN_SUC_EOF_CH1_INT_ENA + The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-write + + + IN_ERR_EOF_CH1_INT_ENA + The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + read-write + + + IN_DSCR_ERR_CH1_INT_ENA + The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 + read-write + + + INFIFO_OVF_L1_CH1_INT_ENA + The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-write + + + INFIFO_UDF_L1_CH1_INT_ENA + The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-write + + + INFIFO_OVF_L2_CH1_INT_ENA + The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-write + + + INFIFO_UDF_L2_CH1_INT_ENA + The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-write + + + IN_DSCR_EMPTY_CH1_INT_ENA + The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + 8 + 1 + read-write + + + IN_DSCR_TASK_OVF_CH1_INT_ENA + The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. + 9 + 1 + read-write + + + + + IN_INT_ST_CH1 + RX CH1 interrupt st register + 0x60C + 0x20 + + + IN_DONE_CH1_INT_ST + The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-only + + + IN_SUC_EOF_CH1_INT_ST + The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-only + + + IN_ERR_EOF_CH1_INT_ST + The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + read-only + + + IN_DSCR_ERR_CH1_INT_ST + The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 + read-only + + + INFIFO_OVF_L1_CH1_INT_ST + The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-only + + + INFIFO_UDF_L1_CH1_INT_ST + The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-only + + + INFIFO_OVF_L2_CH1_INT_ST + The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-only + + + INFIFO_UDF_L2_CH1_INT_ST + The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-only + + + IN_DSCR_EMPTY_CH1_INT_ST + The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + 8 + 1 + read-only + + + IN_DSCR_TASK_OVF_CH1_INT_ST + The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. + 9 + 1 + read-only + + + + + IN_INT_CLR_CH1 + RX CH1 interrupt clr register + 0x610 + 0x20 + + + IN_DONE_CH1_INT_CLR + Set this bit to clear the IN_DONE_CH_INT interrupt. + 0 + 1 + write-only + + + IN_SUC_EOF_CH1_INT_CLR + Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + write-only + + + IN_ERR_EOF_CH1_INT_CLR + Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + write-only + + + IN_DSCR_ERR_CH1_INT_CLR + Set this bit to clear the INDSCR_ERR_CH_INT interrupt. + 3 + 1 + write-only + + + INFIFO_OVF_L1_CH1_INT_CLR + Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + write-only + + + INFIFO_UDF_L1_CH1_INT_CLR + Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + write-only + + + INFIFO_OVF_L2_CH1_INT_CLR + Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + write-only + + + INFIFO_UDF_L2_CH1_INT_CLR + Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + write-only + + + IN_DSCR_EMPTY_CH1_INT_CLR + Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + 8 + 1 + write-only + + + IN_DSCR_TASK_OVF_CH1_INT_CLR + Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. + 9 + 1 + write-only + + + + + INFIFO_STATUS_CH1 + RX CH1 INFIFO status register + 0x614 + 0x20 + 0x00020082 + + + INFIFO_FULL_L2_CH1 + Rx FIFO full signal for Rx channel. + 0 + 1 + read-only + + + INFIFO_EMPTY_L2_CH1 + Rx FIFO empty signal for Rx channel. + 1 + 1 + read-only + + + INFIFO_CNT_L2_CH1 + The register stores the byte number of the data in Rx FIFO for Rx channel. + 2 + 4 + read-only + + + INFIFO_FULL_L1_CH1 + Tx FIFO full signal for Tx channel 1. + 6 + 1 + read-only + + + INFIFO_EMPTY_L1_CH1 + Tx FIFO empty signal for Tx channel 1. + 7 + 1 + read-only + + + INFIFO_CNT_L1_CH1 + The register stores the byte number of the data in Tx FIFO for Tx channel 1. + 8 + 5 + read-only + + + INFIFO_FULL_L3_CH1 + Tx FIFO full signal for Tx channel 1. + 16 + 1 + read-only + + + INFIFO_EMPTY_L3_CH1 + Tx FIFO empty signal for Tx channel 1. + 17 + 1 + read-only + + + INFIFO_CNT_L3_CH1 + The register stores the byte number of the data in Tx FIFO for Tx channel 1. + 18 + 2 + read-only + + + + + IN_POP_CH1 + RX CH1 INFIFO pop register + 0x618 + 0x20 + 0x00000400 + + + INFIFO_RDATA_CH1 + This register stores the data popping from DMA Rx FIFO. + 0 + 11 + read-only + + + INFIFO_POP_CH1 + Set this bit to pop data from DMA Rx FIFO. + 11 + 1 + read-write + + + + + IN_LINK_CONF_CH1 + RX CH1 in_link dscr ctrl register + 0x61C + 0x20 + 0x01100000 + + + INLINK_AUTO_RET_CH1 + Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data. + 20 + 1 + read-write + + + INLINK_STOP_CH1 + Set this bit to stop dealing with the inlink descriptors. + 21 + 1 + read-write + + + INLINK_START_CH1 + Set this bit to start dealing with the inlink descriptors. + 22 + 1 + read-write + + + INLINK_RESTART_CH1 + Set this bit to mount a new inlink descriptor. + 23 + 1 + read-write + + + INLINK_PARK_CH1 + 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. + 24 + 1 + read-only + + + + + IN_LINK_ADDR_CH1 + RX CH1 in_link dscr addr register + 0x620 + 0x20 + + + INLINK_ADDR_CH1 + This register stores the first inlink descriptor's address. + 0 + 32 + read-write + + + + + IN_STATE_CH1 + RX CH1 state register + 0x624 + 0x20 + 0x00800000 + + + INLINK_DSCR_ADDR_CH1 + This register stores the current inlink descriptor's address. + 0 + 18 + read-only + + + IN_DSCR_STATE_CH1 + This register stores the current descriptor state machine state. + 18 + 2 + read-only + + + IN_STATE_CH1 + This register stores the current control module state machine state. + 20 + 3 + read-only + + + IN_RESET_AVAIL_CH1 + This register indicate that if the channel reset is safety. + 23 + 1 + read-only + + + + + IN_SUC_EOF_DES_ADDR_CH1 + RX CH1 eof des addr register + 0x628 + 0x20 + + + IN_SUC_EOF_DES_ADDR_CH1 + This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. + 0 + 32 + read-only + + + + + IN_ERR_EOF_DES_ADDR_CH1 + RX CH1 err eof des addr register + 0x62C + 0x20 + + + IN_ERR_EOF_DES_ADDR_CH1 + This register stores the address of the inlink descriptor when there are some errors in current receiving data. + 0 + 32 + read-only + + + + + IN_DSCR_CH1 + RX CH1 next dscr addr register + 0x630 + 0x20 + + + INLINK_DSCR_CH1 + The address of the next inlink descriptor address x. + 0 + 32 + read-only + + + + + IN_DSCR_BF0_CH1 + RX CH1 last dscr addr register + 0x634 + 0x20 + + + INLINK_DSCR_BF0_CH1 + The address of the last inlink descriptor's next address x-1. + 0 + 32 + read-only + + + + + IN_DSCR_BF1_CH1 + RX CH1 second-to-last dscr addr register + 0x638 + 0x20 + + + INLINK_DSCR_BF1_CH1 + The address of the second-to-last inlink descriptor's next address x-2. + 0 + 32 + read-only + + + + + IN_ARB_CH1 + RX CH1 arb register + 0x640 + 0x20 + 0x00000051 + + + IN_ARB_TOKEN_NUM_CH1 + Set the max number of token count of arbiter + 0 + 4 + read-write + + + EXTER_IN_ARB_PRIORITY_CH1 + Set the priority of channel + 4 + 2 + read-write + + + INTER_IN_ARB_PRIORITY_CH1 + Set the priority of channel + 6 + 3 + read-write + + + + + IN_ETM_CONF_CH1 + RX CH1 ETM config register + 0x648 + 0x20 + 0x00000004 + + + IN_ETM_EN_CH1 + Set this bit to 1 to enable ETM task function + 0 + 1 + read-write + + + IN_ETM_LOOP_EN_CH1 + when this bit is 1, dscr can be processed after receiving a task + 1 + 1 + read-write + + + IN_DSCR_TASK_MAK_CH1 + ETM dscr_ready maximum cache numbers + 2 + 2 + read-write + + + + + IN_FIFO_CNT_CH1 + rx CH1 fifo cnt register + 0x680 + 0x20 + + + IN_CMDFIFO_INFIFO_CNT_CH1 + only for debug + 0 + 10 + read-only + + + + + IN_POP_DATA_CNT_CH1 + rx CH1 pop data cnt register + 0x684 + 0x20 + 0x00000007 + + + IN_CMDFIFO_POP_DATA_CNT_CH1 + only for debug + 0 + 8 + read-only + + + + + IN_XADDR_CH1 + rx CH1 xaddr register + 0x688 + 0x20 + + + IN_CMDFIFO_XADDR_CH1 + only for debug + 0 + 32 + read-only + + + + + IN_BUF_HB_RCV_CH1 + rx CH1 buf len hb rcv register + 0x68C + 0x20 + + + IN_CMDFIFO_BUF_HB_RCV_CH1 + only for debug + 0 + 29 + read-only + + + + + IN_CONF0_CH2 + RX CH2 config0 register + 0x700 + 0x20 + + + INDSCR_BURST_EN_CH2 + Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor when accessing SRAM. + 2 + 1 + read-write + + + IN_ECC_AES_EN_CH2 + When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned. + 3 + 1 + read-write + + + IN_CHECK_OWNER_CH2 + Set this bit to enable checking the owner attribute of the link descriptor. + 4 + 1 + read-write + + + IN_MEM_BURST_LENGTH_CH2 + Block size of Rx channel 2. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes + 6 + 3 + read-write + + + IN_PAGE_BOUND_EN_CH2 + Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length + 12 + 1 + read-write + + + IN_RST_CH2 + Write 1 then write 0 to this bit to reset Rx channel + 24 + 1 + read-write + + + IN_CMD_DISABLE_CH2 + Write 1 before reset and write 0 after reset + 25 + 1 + read-write + + + IN_ARB_WEIGHT_OPT_DIS_CH2 + Set this bit to 1 to disable arbiter optimum weight function. + 26 + 1 + read-write + + + + + IN_INT_RAW_CH2 + RX CH2 interrupt raw register + 0x704 + 0x20 + + + IN_DONE_CH2_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 1. + 0 + 1 + read-write + + + IN_SUC_EOF_CH2_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1. + 1 + 1 + read-write + + + IN_ERR_EOF_CH2_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and data error is detected + 2 + 1 + read-write + + + IN_DSCR_ERR_CH2_INT_RAW + The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 1. + 3 + 1 + read-write + + + INFIFO_OVF_L1_CH2_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is overflow. + 4 + 1 + read-write + + + INFIFO_UDF_L1_CH2_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is underflow. + 5 + 1 + read-write + + + INFIFO_OVF_L2_CH2_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is overflow. + 6 + 1 + read-write + + + INFIFO_UDF_L2_CH2_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is underflow. + 7 + 1 + read-write + + + IN_DSCR_EMPTY_CH2_INT_RAW + The raw interrupt bit turns to high level when the last descriptor is done but fifo also remain data. + 8 + 1 + read-write + + + IN_DSCR_TASK_OVF_CH2_INT_RAW + The raw interrupt bit turns to high level when dscr ready task fifo is overflow. + 9 + 1 + read-write + + + + + IN_INT_ENA_CH2 + RX CH2 interrupt ena register + 0x708 + 0x20 + + + IN_DONE_CH2_INT_ENA + The interrupt enable bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-write + + + IN_SUC_EOF_CH2_INT_ENA + The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-write + + + IN_ERR_EOF_CH2_INT_ENA + The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + read-write + + + IN_DSCR_ERR_CH2_INT_ENA + The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 + read-write + + + INFIFO_OVF_L1_CH2_INT_ENA + The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-write + + + INFIFO_UDF_L1_CH2_INT_ENA + The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-write + + + INFIFO_OVF_L2_CH2_INT_ENA + The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-write + + + INFIFO_UDF_L2_CH2_INT_ENA + The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-write + + + IN_DSCR_EMPTY_CH2_INT_ENA + The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + 8 + 1 + read-write + + + IN_DSCR_TASK_OVF_CH2_INT_ENA + The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. + 9 + 1 + read-write + + + + + IN_INT_ST_CH2 + RX CH2 interrupt st register + 0x70C + 0x20 + + + IN_DONE_CH2_INT_ST + The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-only + + + IN_SUC_EOF_CH2_INT_ST + The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-only + + + IN_ERR_EOF_CH2_INT_ST + The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + read-only + + + IN_DSCR_ERR_CH2_INT_ST + The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 + read-only + + + INFIFO_OVF_L1_CH2_INT_ST + The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-only + + + INFIFO_UDF_L1_CH2_INT_ST + The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-only + + + INFIFO_OVF_L2_CH2_INT_ST + The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-only + + + INFIFO_UDF_L2_CH2_INT_ST + The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-only + + + IN_DSCR_EMPTY_CH2_INT_ST + The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + 8 + 1 + read-only + + + IN_DSCR_TASK_OVF_CH2_INT_ST + The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. + 9 + 1 + read-only + + + + + IN_INT_CLR_CH2 + RX CH2 interrupt clr register + 0x710 + 0x20 + + + IN_DONE_CH2_INT_CLR + Set this bit to clear the IN_DONE_CH_INT interrupt. + 0 + 1 + write-only + + + IN_SUC_EOF_CH2_INT_CLR + Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + write-only + + + IN_ERR_EOF_CH2_INT_CLR + Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + write-only + + + IN_DSCR_ERR_CH2_INT_CLR + Set this bit to clear the INDSCR_ERR_CH_INT interrupt. + 3 + 1 + write-only + + + INFIFO_OVF_L1_CH2_INT_CLR + Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + write-only + + + INFIFO_UDF_L1_CH2_INT_CLR + Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + write-only + + + INFIFO_OVF_L2_CH2_INT_CLR + Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + write-only + + + INFIFO_UDF_L2_CH2_INT_CLR + Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + write-only + + + IN_DSCR_EMPTY_CH2_INT_CLR + Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + 8 + 1 + write-only + + + IN_DSCR_TASK_OVF_CH2_INT_CLR + Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. + 9 + 1 + write-only + + + + + INFIFO_STATUS_CH2 + RX CH2 INFIFO status register + 0x714 + 0x20 + 0x00020082 + + + INFIFO_FULL_L2_CH2 + Rx FIFO full signal for Rx channel. + 0 + 1 + read-only + + + INFIFO_EMPTY_L2_CH2 + Rx FIFO empty signal for Rx channel. + 1 + 1 + read-only + + + INFIFO_CNT_L2_CH2 + The register stores the byte number of the data in Rx FIFO for Rx channel. + 2 + 4 + read-only + + + INFIFO_FULL_L1_CH2 + Tx FIFO full signal for Tx channel 1. + 6 + 1 + read-only + + + INFIFO_EMPTY_L1_CH2 + Tx FIFO empty signal for Tx channel 1. + 7 + 1 + read-only + + + INFIFO_CNT_L1_CH2 + The register stores the byte number of the data in Tx FIFO for Tx channel 1. + 8 + 5 + read-only + + + INFIFO_FULL_L3_CH2 + Tx FIFO full signal for Tx channel 1. + 16 + 1 + read-only + + + INFIFO_EMPTY_L3_CH2 + Tx FIFO empty signal for Tx channel 1. + 17 + 1 + read-only + + + INFIFO_CNT_L3_CH2 + The register stores the byte number of the data in Tx FIFO for Tx channel 1. + 18 + 2 + read-only + + + + + IN_POP_CH2 + RX CH2 INFIFO pop register + 0x718 + 0x20 + 0x00000400 + + + INFIFO_RDATA_CH2 + This register stores the data popping from DMA Rx FIFO. + 0 + 11 + read-only + + + INFIFO_POP_CH2 + Set this bit to pop data from DMA Rx FIFO. + 11 + 1 + read-write + + + + + IN_LINK_CONF_CH2 + RX CH2 in_link dscr ctrl register + 0x71C + 0x20 + 0x01100000 + + + INLINK_AUTO_RET_CH2 + Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data. + 20 + 1 + read-write + + + INLINK_STOP_CH2 + Set this bit to stop dealing with the inlink descriptors. + 21 + 1 + read-write + + + INLINK_START_CH2 + Set this bit to start dealing with the inlink descriptors. + 22 + 1 + read-write + + + INLINK_RESTART_CH2 + Set this bit to mount a new inlink descriptor. + 23 + 1 + read-write + + + INLINK_PARK_CH2 + 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. + 24 + 1 + read-only + + + + + IN_LINK_ADDR_CH2 + RX CH2 in_link dscr addr register + 0x720 + 0x20 + + + INLINK_ADDR_CH2 + This register stores the first inlink descriptor's address. + 0 + 32 + read-write + + + + + IN_STATE_CH2 + RX CH2 state register + 0x724 + 0x20 + 0x00800000 + + + INLINK_DSCR_ADDR_CH2 + This register stores the current inlink descriptor's address. + 0 + 18 + read-only + + + IN_DSCR_STATE_CH2 + This register stores the current descriptor state machine state. + 18 + 2 + read-only + + + IN_STATE_CH2 + This register stores the current control module state machine state. + 20 + 3 + read-only + + + IN_RESET_AVAIL_CH2 + This register indicate that if the channel reset is safety. + 23 + 1 + read-only + + + + + IN_SUC_EOF_DES_ADDR_CH2 + RX CH2 eof des addr register + 0x728 + 0x20 + + + IN_SUC_EOF_DES_ADDR_CH2 + This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. + 0 + 32 + read-only + + + + + IN_ERR_EOF_DES_ADDR_CH2 + RX CH2 err eof des addr register + 0x72C + 0x20 + + + IN_ERR_EOF_DES_ADDR_CH2 + This register stores the address of the inlink descriptor when there are some errors in current receiving data. + 0 + 32 + read-only + + + + + IN_DSCR_CH2 + RX CH2 next dscr addr register + 0x730 + 0x20 + + + INLINK_DSCR_CH2 + The address of the next inlink descriptor address x. + 0 + 32 + read-only + + + + + IN_DSCR_BF0_CH2 + RX CH2 last dscr addr register + 0x734 + 0x20 + + + INLINK_DSCR_BF0_CH2 + The address of the last inlink descriptor's next address x-1. + 0 + 32 + read-only + + + + + IN_DSCR_BF1_CH2 + RX CH2 second-to-last dscr addr register + 0x738 + 0x20 + + + INLINK_DSCR_BF1_CH2 + The address of the second-to-last inlink descriptor's next address x-2. + 0 + 32 + read-only + + + + + IN_ARB_CH2 + RX CH2 arb register + 0x740 + 0x20 + 0x00000041 + + + IN_ARB_TOKEN_NUM_CH2 + Set the max number of token count of arbiter + 0 + 4 + read-write + + + INTER_IN_ARB_PRIORITY_CH2 + Set the priority of channel + 6 + 3 + read-write + + + + + IN_ETM_CONF_CH2 + RX CH2 ETM config register + 0x748 + 0x20 + 0x00000004 + + + IN_ETM_EN_CH2 + Set this bit to 1 to enable ETM task function + 0 + 1 + read-write + + + IN_ETM_LOOP_EN_CH2 + when this bit is 1, dscr can be processed after receiving a task + 1 + 1 + read-write + + + IN_DSCR_TASK_MAK_CH2 + ETM dscr_ready maximum cache numbers + 2 + 2 + read-write + + + + + IN_FIFO_CNT_CH2 + rx CH2 fifo cnt register + 0x780 + 0x20 + + + IN_CMDFIFO_INFIFO_CNT_CH2 + only for debug + 0 + 10 + read-only + + + + + IN_POP_DATA_CNT_CH2 + rx CH2 pop data cnt register + 0x784 + 0x20 + 0x00000007 + + + IN_CMDFIFO_POP_DATA_CNT_CH2 + only for debug + 0 + 8 + read-only + + + + + IN_XADDR_CH2 + rx CH2 xaddr register + 0x788 + 0x20 + + + IN_CMDFIFO_XADDR_CH2 + only for debug + 0 + 32 + read-only + + + + + IN_BUF_HB_RCV_CH2 + rx CH2 buf len hb rcv register + 0x78C + 0x20 + + + IN_CMDFIFO_BUF_HB_RCV_CH2 + only for debug + 0 + 29 + read-only + + + + + IN_CONF0_CH3 + RX CH3 config0 register + 0x800 + 0x20 + + + INDSCR_BURST_EN_CH3 + Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor when accessing SRAM. + 2 + 1 + read-write + + + IN_ECC_AES_EN_CH3 + When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned. + 3 + 1 + read-write + + + IN_CHECK_OWNER_CH3 + Set this bit to enable checking the owner attribute of the link descriptor. + 4 + 1 + read-write + + + IN_MEM_BURST_LENGTH_CH3 + Block size of Rx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes + 6 + 3 + read-write + + + IN_PAGE_BOUND_EN_CH3 + Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length + 12 + 1 + read-write + + + IN_RST_CH3 + Write 1 then write 0 to this bit to reset Rx channel + 24 + 1 + read-write + + + IN_CMD_DISABLE_CH3 + Write 1 before reset and write 0 after reset + 25 + 1 + read-write + + + IN_ARB_WEIGHT_OPT_DIS_CH3 + Set this bit to 1 to disable arbiter optimum weight function. + 26 + 1 + read-write + + + + + IN_INT_RAW_CH3 + RX CH3 interrupt raw register + 0x804 + 0x20 + + + IN_DONE_CH3_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 1. + 0 + 1 + read-write + + + IN_SUC_EOF_CH3_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1. + 1 + 1 + read-write + + + IN_ERR_EOF_CH3_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and data error is detected + 2 + 1 + read-write + + + IN_DSCR_ERR_CH3_INT_RAW + The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 1. + 3 + 1 + read-write + + + INFIFO_OVF_L1_CH3_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is overflow. + 4 + 1 + read-write + + + INFIFO_UDF_L1_CH3_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is underflow. + 5 + 1 + read-write + + + INFIFO_OVF_L2_CH3_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is overflow. + 6 + 1 + read-write + + + INFIFO_UDF_L2_CH3_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is underflow. + 7 + 1 + read-write + + + IN_DSCR_EMPTY_CH3_INT_RAW + The raw interrupt bit turns to high level when the last descriptor is done but fifo also remain data. + 8 + 1 + read-write + + + IN_DSCR_TASK_OVF_CH3_INT_RAW + The raw interrupt bit turns to high level when dscr ready task fifo is overflow. + 9 + 1 + read-write + + + + + IN_INT_ENA_CH3 + RX CH3 interrupt ena register + 0x808 + 0x20 + + + IN_DONE_CH3_INT_ENA + The interrupt enable bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-write + + + IN_SUC_EOF_CH3_INT_ENA + The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-write + + + IN_ERR_EOF_CH3_INT_ENA + The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + read-write + + + IN_DSCR_ERR_CH3_INT_ENA + The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 + read-write + + + INFIFO_OVF_L1_CH3_INT_ENA + The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-write + + + INFIFO_UDF_L1_CH3_INT_ENA + The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-write + + + INFIFO_OVF_L2_CH3_INT_ENA + The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-write + + + INFIFO_UDF_L2_CH3_INT_ENA + The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-write + + + IN_DSCR_EMPTY_CH3_INT_ENA + The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + 8 + 1 + read-write + + + IN_DSCR_TASK_OVF_CH3_INT_ENA + The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. + 9 + 1 + read-write + + + + + IN_INT_ST_CH3 + RX CH3 interrupt st register + 0x80C + 0x20 + + + IN_DONE_CH3_INT_ST + The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-only + + + IN_SUC_EOF_CH3_INT_ST + The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-only + + + IN_ERR_EOF_CH3_INT_ST + The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + read-only + + + IN_DSCR_ERR_CH3_INT_ST + The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 + read-only + + + INFIFO_OVF_L1_CH3_INT_ST + The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-only + + + INFIFO_UDF_L1_CH3_INT_ST + The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-only + + + INFIFO_OVF_L2_CH3_INT_ST + The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-only + + + INFIFO_UDF_L2_CH3_INT_ST + The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-only + + + IN_DSCR_EMPTY_CH3_INT_ST + The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + 8 + 1 + read-only + + + IN_DSCR_TASK_OVF_CH3_INT_ST + The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. + 9 + 1 + read-only + + + + + IN_INT_CLR_CH3 + RX CH3 interrupt clr register + 0x810 + 0x20 + + + IN_DONE_CH3_INT_CLR + Set this bit to clear the IN_DONE_CH_INT interrupt. + 0 + 1 + write-only + + + IN_SUC_EOF_CH3_INT_CLR + Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + write-only + + + IN_ERR_EOF_CH3_INT_CLR + Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + write-only + + + IN_DSCR_ERR_CH3_INT_CLR + Set this bit to clear the INDSCR_ERR_CH_INT interrupt. + 3 + 1 + write-only + + + INFIFO_OVF_L1_CH3_INT_CLR + Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + write-only + + + INFIFO_UDF_L1_CH3_INT_CLR + Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + write-only + + + INFIFO_OVF_L2_CH3_INT_CLR + Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + write-only + + + INFIFO_UDF_L2_CH3_INT_CLR + Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + write-only + + + IN_DSCR_EMPTY_CH3_INT_CLR + Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + 8 + 1 + write-only + + + IN_DSCR_TASK_OVF_CH3_INT_CLR + Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. + 9 + 1 + write-only + + + + + INFIFO_STATUS_CH3 + RX CH3 INFIFO status register + 0x814 + 0x20 + 0x00020082 + + + INFIFO_FULL_L2_CH3 + Rx FIFO full signal for Rx channel. + 0 + 1 + read-only + + + INFIFO_EMPTY_L2_CH3 + Rx FIFO empty signal for Rx channel. + 1 + 1 + read-only + + + INFIFO_CNT_L2_CH3 + The register stores the byte number of the data in Rx FIFO for Rx channel. + 2 + 4 + read-only + + + INFIFO_FULL_L1_CH3 + Tx FIFO full signal for Tx channel 1. + 6 + 1 + read-only + + + INFIFO_EMPTY_L1_CH3 + Tx FIFO empty signal for Tx channel 1. + 7 + 1 + read-only + + + INFIFO_CNT_L1_CH3 + The register stores the byte number of the data in Tx FIFO for Tx channel 1. + 8 + 5 + read-only + + + INFIFO_FULL_L3_CH3 + Tx FIFO full signal for Tx channel 1. + 16 + 1 + read-only + + + INFIFO_EMPTY_L3_CH3 + Tx FIFO empty signal for Tx channel 1. + 17 + 1 + read-only + + + INFIFO_CNT_L3_CH3 + The register stores the byte number of the data in Tx FIFO for Tx channel 1. + 18 + 2 + read-only + + + + + IN_POP_CH3 + RX CH3 INFIFO pop register + 0x818 + 0x20 + 0x00000400 + + + INFIFO_RDATA_CH3 + This register stores the data popping from DMA Rx FIFO. + 0 + 11 + read-only + + + INFIFO_POP_CH3 + Set this bit to pop data from DMA Rx FIFO. + 11 + 1 + read-write + + + + + IN_LINK_CONF_CH3 + RX CH3 in_link dscr ctrl register + 0x81C + 0x20 + 0x01100000 + + + INLINK_AUTO_RET_CH3 + Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data. + 20 + 1 + read-write + + + INLINK_STOP_CH3 + Set this bit to stop dealing with the inlink descriptors. + 21 + 1 + read-write + + + INLINK_START_CH3 + Set this bit to start dealing with the inlink descriptors. + 22 + 1 + read-write + + + INLINK_RESTART_CH3 + Set this bit to mount a new inlink descriptor. + 23 + 1 + read-write + + + INLINK_PARK_CH3 + 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. + 24 + 1 + read-only + + + + + IN_LINK_ADDR_CH3 + RX CH3 in_link dscr addr register + 0x820 + 0x20 + + + INLINK_ADDR_CH3 + This register stores the first inlink descriptor's address. + 0 + 32 + read-write + + + + + IN_STATE_CH3 + RX CH3 state register + 0x824 + 0x20 + 0x00800000 + + + INLINK_DSCR_ADDR_CH3 + This register stores the current inlink descriptor's address. + 0 + 18 + read-only + + + IN_DSCR_STATE_CH3 + This register stores the current descriptor state machine state. + 18 + 2 + read-only + + + IN_STATE_CH3 + This register stores the current control module state machine state. + 20 + 3 + read-only + + + IN_RESET_AVAIL_CH3 + This register indicate that if the channel reset is safety. + 23 + 1 + read-only + + + + + IN_SUC_EOF_DES_ADDR_CH3 + RX CH3 eof des addr register + 0x828 + 0x20 + + + IN_SUC_EOF_DES_ADDR_CH3 + This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. + 0 + 32 + read-only + + + + + IN_ERR_EOF_DES_ADDR_CH3 + RX CH3 err eof des addr register + 0x82C + 0x20 + + + IN_ERR_EOF_DES_ADDR_CH3 + This register stores the address of the inlink descriptor when there are some errors in current receiving data. + 0 + 32 + read-only + + + + + IN_DSCR_CH3 + RX CH3 next dscr addr register + 0x830 + 0x20 + + + INLINK_DSCR_CH3 + The address of the next inlink descriptor address x. + 0 + 32 + read-only + + + + + IN_DSCR_BF0_CH3 + RX CH3 last dscr addr register + 0x834 + 0x20 + + + INLINK_DSCR_BF0_CH3 + The address of the last inlink descriptor's next address x-1. + 0 + 32 + read-only + + + + + IN_DSCR_BF1_CH3 + RX CH3 second-to-last dscr addr register + 0x838 + 0x20 + + + INLINK_DSCR_BF1_CH3 + The address of the second-to-last inlink descriptor's next address x-2. + 0 + 32 + read-only + + + + + IN_ARB_CH3 + RX CH3 arb register + 0x840 + 0x20 + 0x00000041 + + + IN_ARB_TOKEN_NUM_CH3 + Set the max number of token count of arbiter + 0 + 4 + read-write + + + INTER_IN_ARB_PRIORITY_CH3 + Set the priority of channel + 6 + 3 + read-write + + + + + IN_ETM_CONF_CH3 + RX CH3 ETM config register + 0x848 + 0x20 + 0x00000004 + + + IN_ETM_EN_CH3 + Set this bit to 1 to enable ETM task function + 0 + 1 + read-write + + + IN_ETM_LOOP_EN_CH3 + when this bit is 1, dscr can be processed after receiving a task + 1 + 1 + read-write + + + IN_DSCR_TASK_MAK_CH3 + ETM dscr_ready maximum cache numbers + 2 + 2 + read-write + + + + + IN_FIFO_CNT_CH3 + rx CH3 fifo cnt register + 0x880 + 0x20 + + + IN_CMDFIFO_INFIFO_CNT_CH3 + only for debug + 0 + 10 + read-only + + + + + IN_POP_DATA_CNT_CH3 + rx CH3 pop data cnt register + 0x884 + 0x20 + 0x00000007 + + + IN_CMDFIFO_POP_DATA_CNT_CH3 + only for debug + 0 + 8 + read-only + + + + + IN_XADDR_CH3 + rx CH3 xaddr register + 0x888 + 0x20 + + + IN_CMDFIFO_XADDR_CH3 + only for debug + 0 + 32 + read-only + + + + + IN_BUF_HB_RCV_CH3 + rx CH3 buf len hb rcv register + 0x88C + 0x20 + + + IN_CMDFIFO_BUF_HB_RCV_CH3 + only for debug + 0 + 29 + read-only + + + + + IN_CONF0_CH4 + RX CH4 config0 register + 0x900 + 0x20 + + + INDSCR_BURST_EN_CH4 + Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor when accessing SRAM. + 2 + 1 + read-write + + + IN_ECC_AES_EN_CH4 + When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned. + 3 + 1 + read-write + + + IN_CHECK_OWNER_CH4 + Set this bit to enable checking the owner attribute of the link descriptor. + 4 + 1 + read-write + + + IN_MEM_BURST_LENGTH_CH4 + Block size of Rx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes + 6 + 3 + read-write + + + IN_PAGE_BOUND_EN_CH4 + Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length + 12 + 1 + read-write + + + IN_RST_CH4 + Write 1 then write 0 to this bit to reset Rx channel + 24 + 1 + read-write + + + IN_CMD_DISABLE_CH4 + Write 1 before reset and write 0 after reset + 25 + 1 + read-write + + + IN_ARB_WEIGHT_OPT_DIS_CH4 + Set this bit to 1 to disable arbiter optimum weight function. + 26 + 1 + read-write + + + + + IN_INT_RAW_CH4 + RX CH4 interrupt raw register + 0x904 + 0x20 + + + IN_DONE_CH4_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 1. + 0 + 1 + read-write + + + IN_SUC_EOF_CH4_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1. + 1 + 1 + read-write + + + IN_ERR_EOF_CH4_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and data error is detected + 2 + 1 + read-write + + + IN_DSCR_ERR_CH4_INT_RAW + The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 1. + 3 + 1 + read-write + + + INFIFO_OVF_L1_CH4_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is overflow. + 4 + 1 + read-write + + + INFIFO_UDF_L1_CH4_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is underflow. + 5 + 1 + read-write + + + INFIFO_OVF_L2_CH4_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is overflow. + 6 + 1 + read-write + + + INFIFO_UDF_L2_CH4_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is underflow. + 7 + 1 + read-write + + + IN_DSCR_EMPTY_CH4_INT_RAW + The raw interrupt bit turns to high level when the last descriptor is done but fifo also remain data. + 8 + 1 + read-write + + + IN_DSCR_TASK_OVF_CH4_INT_RAW + The raw interrupt bit turns to high level when dscr ready task fifo is overflow. + 9 + 1 + read-write + + + + + IN_INT_ENA_CH4 + RX CH4 interrupt ena register + 0x908 + 0x20 + + + IN_DONE_CH4_INT_ENA + The interrupt enable bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-write + + + IN_SUC_EOF_CH4_INT_ENA + The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-write + + + IN_ERR_EOF_CH4_INT_ENA + The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + read-write + + + IN_DSCR_ERR_CH4_INT_ENA + The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 + read-write + + + INFIFO_OVF_L1_CH4_INT_ENA + The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-write + + + INFIFO_UDF_L1_CH4_INT_ENA + The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-write + + + INFIFO_OVF_L2_CH4_INT_ENA + The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-write + + + INFIFO_UDF_L2_CH4_INT_ENA + The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-write + + + IN_DSCR_EMPTY_CH4_INT_ENA + The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + 8 + 1 + read-write + + + IN_DSCR_TASK_OVF_CH4_INT_ENA + The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. + 9 + 1 + read-write + + + + + IN_INT_ST_CH4 + RX CH4 interrupt st register + 0x90C + 0x20 + + + IN_DONE_CH4_INT_ST + The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-only + + + IN_SUC_EOF_CH4_INT_ST + The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-only + + + IN_ERR_EOF_CH4_INT_ST + The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + read-only + + + IN_DSCR_ERR_CH4_INT_ST + The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 + read-only + + + INFIFO_OVF_L1_CH4_INT_ST + The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-only + + + INFIFO_UDF_L1_CH4_INT_ST + The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-only + + + INFIFO_OVF_L2_CH4_INT_ST + The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-only + + + INFIFO_UDF_L2_CH4_INT_ST + The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-only + + + IN_DSCR_EMPTY_CH4_INT_ST + The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + 8 + 1 + read-only + + + IN_DSCR_TASK_OVF_CH4_INT_ST + The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. + 9 + 1 + read-only + + + + + IN_INT_CLR_CH4 + RX CH4 interrupt clr register + 0x910 + 0x20 + + + IN_DONE_CH4_INT_CLR + Set this bit to clear the IN_DONE_CH_INT interrupt. + 0 + 1 + write-only + + + IN_SUC_EOF_CH4_INT_CLR + Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + write-only + + + IN_ERR_EOF_CH4_INT_CLR + Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + write-only + + + IN_DSCR_ERR_CH4_INT_CLR + Set this bit to clear the INDSCR_ERR_CH_INT interrupt. + 3 + 1 + write-only + + + INFIFO_OVF_L1_CH4_INT_CLR + Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + write-only + + + INFIFO_UDF_L1_CH4_INT_CLR + Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + write-only + + + INFIFO_OVF_L2_CH4_INT_CLR + Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + write-only + + + INFIFO_UDF_L2_CH4_INT_CLR + Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + write-only + + + IN_DSCR_EMPTY_CH4_INT_CLR + Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + 8 + 1 + write-only + + + IN_DSCR_TASK_OVF_CH4_INT_CLR + Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. + 9 + 1 + write-only + + + + + INFIFO_STATUS_CH4 + RX CH4 INFIFO status register + 0x914 + 0x20 + 0x00020082 + + + INFIFO_FULL_L2_CH4 + Rx FIFO full signal for Rx channel. + 0 + 1 + read-only + + + INFIFO_EMPTY_L2_CH4 + Rx FIFO empty signal for Rx channel. + 1 + 1 + read-only + + + INFIFO_CNT_L2_CH4 + The register stores the byte number of the data in Rx FIFO for Rx channel. + 2 + 4 + read-only + + + INFIFO_FULL_L1_CH4 + Tx FIFO full signal for Tx channel 1. + 6 + 1 + read-only + + + INFIFO_EMPTY_L1_CH4 + Tx FIFO empty signal for Tx channel 1. + 7 + 1 + read-only + + + INFIFO_CNT_L1_CH4 + The register stores the byte number of the data in Tx FIFO for Tx channel 1. + 8 + 5 + read-only + + + INFIFO_FULL_L3_CH4 + Tx FIFO full signal for Tx channel 1. + 16 + 1 + read-only + + + INFIFO_EMPTY_L3_CH4 + Tx FIFO empty signal for Tx channel 1. + 17 + 1 + read-only + + + INFIFO_CNT_L3_CH4 + The register stores the byte number of the data in Tx FIFO for Tx channel 1. + 18 + 2 + read-only + + + + + IN_POP_CH4 + RX CH4 INFIFO pop register + 0x918 + 0x20 + 0x00000400 + + + INFIFO_RDATA_CH4 + This register stores the data popping from DMA Rx FIFO. + 0 + 11 + read-only + + + INFIFO_POP_CH4 + Set this bit to pop data from DMA Rx FIFO. + 11 + 1 + read-write + + + + + IN_LINK_CONF_CH4 + RX CH4 in_link dscr ctrl register + 0x91C + 0x20 + 0x01100000 + + + INLINK_AUTO_RET_CH4 + Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data. + 20 + 1 + read-write + + + INLINK_STOP_CH4 + Set this bit to stop dealing with the inlink descriptors. + 21 + 1 + read-write + + + INLINK_START_CH4 + Set this bit to start dealing with the inlink descriptors. + 22 + 1 + read-write + + + INLINK_RESTART_CH4 + Set this bit to mount a new inlink descriptor. + 23 + 1 + read-write + + + INLINK_PARK_CH4 + 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. + 24 + 1 + read-only + + + + + IN_LINK_ADDR_CH4 + RX CH4 in_link dscr addr register + 0x920 + 0x20 + + + INLINK_ADDR_CH4 + This register stores the first inlink descriptor's address. + 0 + 32 + read-write + + + + + IN_STATE_CH4 + RX CH4 state register + 0x924 + 0x20 + 0x00800000 + + + INLINK_DSCR_ADDR_CH4 + This register stores the current inlink descriptor's address. + 0 + 18 + read-only + + + IN_DSCR_STATE_CH4 + This register stores the current descriptor state machine state. + 18 + 2 + read-only + + + IN_STATE_CH4 + This register stores the current control module state machine state. + 20 + 3 + read-only + + + IN_RESET_AVAIL_CH4 + This register indicate that if the channel reset is safety. + 23 + 1 + read-only + + + + + IN_SUC_EOF_DES_ADDR_CH4 + RX CH4 eof des addr register + 0x928 + 0x20 + + + IN_SUC_EOF_DES_ADDR_CH4 + This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. + 0 + 32 + read-only + + + + + IN_ERR_EOF_DES_ADDR_CH4 + RX CH4 err eof des addr register + 0x92C + 0x20 + + + IN_ERR_EOF_DES_ADDR_CH4 + This register stores the address of the inlink descriptor when there are some errors in current receiving data. + 0 + 32 + read-only + + + + + IN_DSCR_CH4 + RX CH4 next dscr addr register + 0x930 + 0x20 + + + INLINK_DSCR_CH4 + The address of the next inlink descriptor address x. + 0 + 32 + read-only + + + + + IN_DSCR_BF0_CH4 + RX CH4 last dscr addr register + 0x934 + 0x20 + + + INLINK_DSCR_BF0_CH4 + The address of the last inlink descriptor's next address x-1. + 0 + 32 + read-only + + + + + IN_DSCR_BF1_CH4 + RX CH4 second-to-last dscr addr register + 0x938 + 0x20 + + + INLINK_DSCR_BF1_CH4 + The address of the second-to-last inlink descriptor's next address x-2. + 0 + 32 + read-only + + + + + IN_ARB_CH4 + RX CH4 arb register + 0x940 + 0x20 + 0x00000051 + + + IN_ARB_TOKEN_NUM_CH4 + Set the max number of token count of arbiter + 0 + 4 + read-write + + + EXTER_IN_ARB_PRIORITY_CH4 + Set the priority of channel + 4 + 2 + read-write + + + INTER_IN_ARB_PRIORITY_CH4 + Set the priority of channel + 6 + 3 + read-write + + + + + IN_ETM_CONF_CH4 + RX CH4 ETM config register + 0x948 + 0x20 + 0x00000004 + + + IN_ETM_EN_CH4 + Set this bit to 1 to enable ETM task function + 0 + 1 + read-write + + + IN_ETM_LOOP_EN_CH4 + when this bit is 1, dscr can be processed after receiving a task + 1 + 1 + read-write + + + IN_DSCR_TASK_MAK_CH4 + ETM dscr_ready maximum cache numbers + 2 + 2 + read-write + + + + + IN_FIFO_CNT_CH4 + rx CH4 fifo cnt register + 0x980 + 0x20 + + + IN_CMDFIFO_INFIFO_CNT_CH4 + only for debug + 0 + 10 + read-only + + + + + IN_POP_DATA_CNT_CH4 + rx CH4 pop data cnt register + 0x984 + 0x20 + 0x00000007 + + + IN_CMDFIFO_POP_DATA_CNT_CH4 + only for debug + 0 + 8 + read-only + + + + + IN_XADDR_CH4 + rx CH4 xaddr register + 0x988 + 0x20 + + + IN_CMDFIFO_XADDR_CH4 + only for debug + 0 + 32 + read-only + + + + + IN_BUF_HB_RCV_CH4 + rx CH4 buf len hb rcv register + 0x98C + 0x20 + + + IN_CMDFIFO_BUF_HB_RCV_CH4 + only for debug + 0 + 29 + read-only + + + + + IN_CONF0_CH5 + RX CH5 config0 register + 0xA00 + 0x20 + + + IN_ECC_AES_EN_CH5 + When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned. + 3 + 1 + read-write + + + IN_MEM_BURST_LENGTH_CH5 + Block size of Rx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes + 6 + 3 + read-write + + + IN_PAGE_BOUND_EN_CH5 + Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length + 12 + 1 + read-write + + + IN_RST_CH5 + Write 1 then write 0 to this bit to reset Rx channel + 24 + 1 + read-write + + + IN_CMD_DISABLE_CH5 + Write 1 before reset and write 0 after reset + 25 + 1 + read-write + + + + + IN_CONF1_CH5 + RX CH5 config1 register + 0xA04 + 0x20 + + + BLOCK_START_ADDR_CH5 + RX Channel 5 destination start address + 0 + 32 + read-write + + + + + IN_CONF2_CH5 + RX CH5 config2 register + 0xA08 + 0x20 + 0x3C007800 + + + BLOCK_ROW_LENGTH_12LINE_CH5 + The number of bytes contained in a row block 12line in RX channel 5 + 0 + 16 + read-write + + + BLOCK_ROW_LENGTH_4LINE_CH5 + The number of bytes contained in a row block 4line in RX channel 5 + 16 + 16 + read-write + + + + + IN_CONF3_CH5 + RX CH5 config3 register + 0xA0C + 0x20 + 0x00200100 + + + BLOCK_LENGTH_12LINE_CH5 + The number of bytes contained in a block 12line + 0 + 14 + read-write + + + BLOCK_LENGTH_4LINE_CH5 + The number of bytes contained in a block 4line + 14 + 14 + read-write + + + + + IN_INT_RAW_CH5 + RX CH5 interrupt raw register + 0xA10 + 0x20 + + + IN_DONE_CH5_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 1. + 0 + 1 + read-write + + + IN_SUC_EOF_CH5_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1. + 1 + 1 + read-write + + + INFIFO_OVF_L1_CH5_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is overflow. + 2 + 1 + read-write + + + INFIFO_UDF_L1_CH5_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is underflow. + 3 + 1 + read-write + + + FETCH_MB_COL_CNT_OVF_CH5_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is underflow. + 4 + 1 + read-write + + + + + IN_INT_ENA_CH5 + RX CH5 interrupt ena register + 0xA14 + 0x20 + + + IN_DONE_CH5_INT_ENA + The interrupt enable bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-write + + + IN_SUC_EOF_CH5_INT_ENA + The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-write + + + INFIFO_OVF_L1_CH5_INT_ENA + The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + 2 + 1 + read-write + + + INFIFO_UDF_L1_CH5_INT_ENA + The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + 3 + 1 + read-write + + + FETCH_MB_COL_CNT_OVF_CH5_INT_ENA + The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + 4 + 1 + read-write + + + + + IN_INT_ST_CH5 + RX CH5 interrupt st register + 0xA18 + 0x20 + + + IN_DONE_CH5_INT_ST + The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-only + + + IN_SUC_EOF_CH5_INT_ST + The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-only + + + INFIFO_OVF_L1_CH5_INT_ST + The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + 2 + 1 + read-only + + + INFIFO_UDF_L1_CH5_INT_ST + The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + 3 + 1 + read-only + + + FETCH_MB_COL_CNT_OVF_CH5_INT_ST + The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + 4 + 1 + read-only + + + + + IN_INT_CLR_CH5 + RX CH5 interrupt clr register + 0xA1C + 0x20 + + + IN_DONE_CH5_INT_CLR + Set this bit to clear the IN_DONE_CH_INT interrupt. + 0 + 1 + write-only + + + IN_SUC_EOF_CH5_INT_CLR + Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + write-only + + + INFIFO_OVF_L1_CH5_INT_CLR + Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + 2 + 1 + write-only + + + INFIFO_UDF_L1_CH5_INT_CLR + Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + 3 + 1 + write-only + + + FETCH_MB_COL_CNT_OVF_CH5_INT_CLR + Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + 4 + 1 + write-only + + + + + INFIFO_STATUS_CH5 + RX CH5 INFIFO status register + 0xA20 + 0x20 + 0x00000002 + + + INFIFO_FULL_L1_CH5 + Tx FIFO full signal for Tx channel 1. + 0 + 1 + read-only + + + INFIFO_EMPTY_L1_CH5 + Tx FIFO empty signal for Tx channel 1. + 1 + 1 + read-only + + + INFIFO_CNT_L1_CH5 + The register stores the byte number of the data in Tx FIFO for Tx channel 1. + 2 + 5 + read-only + + + + + IN_POP_CH5 + RX CH5 INFIFO pop register + 0xA24 + 0x20 + 0x00000400 + + + INFIFO_RDATA_CH5 + This register stores the data popping from DMA Rx FIFO. + 0 + 11 + read-only + + + INFIFO_POP_CH5 + Set this bit to pop data from DMA Rx FIFO. + 11 + 1 + read-write + + + + + IN_STATE_CH5 + RX CH5 state register + 0xA28 + 0x20 + 0x00000008 + + + IN_STATE_CH5 + This register stores the current control module state machine state. + 0 + 3 + read-only + + + IN_RESET_AVAIL_CH5 + This register indicate that if the channel reset is safety. + 3 + 1 + read-only + + + + + IN_ARB_CH5 + RX CH5 arb register + 0xA40 + 0x20 + 0x00000041 + + + IN_ARB_TOKEN_NUM_CH5 + Set the max number of token count of arbiter + 0 + 4 + read-write + + + INTER_IN_ARB_PRIORITY_CH5 + Set the priority of channel + 6 + 3 + read-write + + + + + IN_FIFO_CNT_CH5 + rx CH5 fifo cnt register + 0xA80 + 0x20 + + + IN_CMDFIFO_INFIFO_CNT_CH5 + only for debug + 0 + 10 + read-only + + + + + IN_POP_DATA_CNT_CH5 + rx CH5 pop data cnt register + 0xA84 + 0x20 + 0x000000FF + + + IN_CMDFIFO_POP_DATA_CNT_CH5 + only for debug + 0 + 8 + read-only + + + + + IN_XADDR_CH5 + rx CH5 xaddr register + 0xA88 + 0x20 + + + IN_CMDFIFO_XADDR_CH5 + only for debug + 0 + 32 + read-only + + + + + IN_BUF_HB_RCV_CH5 + rx CH5 buf len hb rcv register + 0xA8C + 0x20 + + + IN_CMDFIFO_BUF_HB_RCV_CH5 + only for debug + 0 + 29 + read-only + + + + + INTER_AXI_ERR + inter memory axi err register + 0xB00 + 0x20 + + + INTER_RID_ERR_CNT + AXI read id err cnt + 0 + 4 + read-only + + + INTER_RRESP_ERR_CNT + AXI read resp err cnt + 4 + 4 + read-only + + + INTER_WRESP_ERR_CNT + AXI write resp err cnt + 8 + 4 + read-only + + + INTER_RD_FIFO_CNT + AXI read cmd fifo remain cmd count + 12 + 3 + read-only + + + INTER_RD_BAK_FIFO_CNT + AXI read backup cmd fifo remain cmd count + 15 + 4 + read-only + + + INTER_WR_FIFO_CNT + AXI write cmd fifo remain cmd count + 19 + 3 + read-only + + + INTER_WR_BAK_FIFO_CNT + AXI write backup cmd fifo remain cmd count + 22 + 4 + read-only + + + + + EXTER_AXI_ERR + exter memory axi err register + 0xB04 + 0x20 + + + EXTER_RID_ERR_CNT + AXI read id err cnt + 0 + 4 + read-only + + + EXTER_RRESP_ERR_CNT + AXI read resp err cnt + 4 + 4 + read-only + + + EXTER_WRESP_ERR_CNT + AXI write resp err cnt + 8 + 4 + read-only + + + EXTER_RD_FIFO_CNT + AXI read cmd fifo remain cmd count + 12 + 3 + read-only + + + EXTER_RD_BAK_FIFO_CNT + AXI read backup cmd fifo remain cmd count + 15 + 4 + read-only + + + EXTER_WR_FIFO_CNT + AXI write cmd fifo remain cmd count + 19 + 3 + read-only + + + EXTER_WR_BAK_FIFO_CNT + AXI write backup cmd fifo remain cmd count + 22 + 4 + read-only + + + + + RST_CONF + axi reset config register + 0xB08 + 0x20 + + + INTER_AXIM_RD_RST + Write 1 then write 0 to this bit to reset axi master read data FIFO. + 0 + 1 + read-write + + + INTER_AXIM_WR_RST + Write 1 then write 0 to this bit to reset axi master write data FIFO. + 1 + 1 + read-write + + + EXTER_AXIM_RD_RST + Write 1 then write 0 to this bit to reset axi master read data FIFO. + 2 + 1 + read-write + + + EXTER_AXIM_WR_RST + Write 1 then write 0 to this bit to reset axi master write data FIFO. + 3 + 1 + read-write + + + CLK_EN + 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers. + 4 + 1 + read-write + + + + + INTER_MEM_START_ADDR0 + Start address of inter memory range0 register + 0xB0C + 0x20 + 0x30100000 + + + ACCESS_INTER_MEM_START_ADDR0 + The start address of accessible address space. + 0 + 32 + read-write + + + + + INTER_MEM_END_ADDR0 + end address of inter memory range0 register + 0xB10 + 0x20 + 0x8FFFFFFF + + + ACCESS_INTER_MEM_END_ADDR0 + The end address of accessible address space. The access address beyond this range would lead to descriptor error. + 0 + 32 + read-write + + + + + INTER_MEM_START_ADDR1 + Start address of inter memory range1 register + 0xB14 + 0x20 + 0x30100000 + + + ACCESS_INTER_MEM_START_ADDR1 + The start address of accessible address space. + 0 + 32 + read-write + + + + + INTER_MEM_END_ADDR1 + end address of inter memory range1 register + 0xB18 + 0x20 + 0x8FFFFFFF + + + ACCESS_INTER_MEM_END_ADDR1 + The end address of accessible address space. The access address beyond this range would lead to descriptor error. + 0 + 32 + read-write + + + + + EXTER_MEM_START_ADDR0 + Start address of exter memory range0 register + 0xB20 + 0x20 + 0x30100000 + + + ACCESS_EXTER_MEM_START_ADDR0 + The start address of accessible address space. + 0 + 32 + read-write + + + + + EXTER_MEM_END_ADDR0 + end address of exter memory range0 register + 0xB24 + 0x20 + 0x8FFFFFFF + + + ACCESS_EXTER_MEM_END_ADDR0 + The end address of accessible address space. The access address beyond this range would lead to descriptor error. + 0 + 32 + read-write + + + + + EXTER_MEM_START_ADDR1 + Start address of exter memory range1 register + 0xB28 + 0x20 + 0x30100000 + + + ACCESS_EXTER_MEM_START_ADDR1 + The start address of accessible address space. + 0 + 32 + read-write + + + + + EXTER_MEM_END_ADDR1 + end address of exter memory range1 register + 0xB2C + 0x20 + 0x8FFFFFFF + + + ACCESS_EXTER_MEM_END_ADDR1 + The end address of accessible address space. The access address beyond this range would lead to descriptor error. + 0 + 32 + read-write + + + + + OUT_ARB_CONFIG + reserved + 0xB30 + 0x20 + + + OUT_ARB_TIMEOUT_NUM + Set the max number of timeout count of arbiter + 0 + 16 + read-write + + + OUT_WEIGHT_EN + reserved + 16 + 1 + read-write + + + + + IN_ARB_CONFIG + reserved + 0xB34 + 0x20 + + + IN_ARB_TIMEOUT_NUM + Set the max number of timeout count of arbiter + 0 + 16 + read-write + + + IN_WEIGHT_EN + reserved + 16 + 1 + read-write + + + + + DATE + reserved + 0xB3C + 0x20 + 0x20230403 + + + DATE + register version. + 0 + 32 + read-write + + + + + COUNTER_RST + counter reset register + 0xB50 + 0x20 + + + RX_CH0_EXTER_COUNTER_RST + Write 1 then write 0 to this bit to reset rx ch0 counter. + 0 + 1 + read-write + + + RX_CH1_EXTER_COUNTER_RST + Write 1 then write 0 to this bit to reset rx ch1 counter. + 1 + 1 + read-write + + + RX_CH2_INTER_COUNTER_RST + Write 1 then write 0 to this bit to reset rx ch2 counter. + 2 + 1 + read-write + + + RX_CH5_INTER_COUNTER_RST + Write 1 then write 0 to this bit to reset rx ch5 counter. + 3 + 1 + read-write + + + + + RX_CH0_COUNTER + rx ch0 counter register + 0xB54 + 0x20 + + + RX_CH0_CNT + rx ch0 counter register + 0 + 23 + read-only + + + + + RX_CH1_COUNTER + rx ch1 counter register + 0xB58 + 0x20 + + + RX_CH1_CNT + rx ch1 counter register + 0 + 21 + read-only + + + + + RX_CH2_COUNTER + rx ch2 counter register + 0xB5C + 0x20 + + + RX_CH2_CNT + rx ch2 counter register + 0 + 11 + read-only + + + + + RX_CH5_COUNTER + rx ch5 counter register + 0xB60 + 0x20 + + + RX_CH5_CNT + rx ch5 counter register + 0 + 17 + read-only + + + + + + + HMAC + HMAC (Hash-based Message Authentication Code) Accelerator + HMAC + 0x50095000 + + 0x0 + 0xA4 + registers + + + + SET_START + Process control register 0. + 0x40 + 0x20 + + + SET_START + Start hmac operation. + 0 + 1 + write-only + + + + + SET_PARA_PURPOSE + Configure purpose. + 0x44 + 0x20 + + + PURPOSE_SET + Set hmac parameter purpose. + 0 + 4 + write-only + + + + + SET_PARA_KEY + Configure key. + 0x48 + 0x20 + + + KEY_SET + Set hmac parameter key. + 0 + 3 + write-only + + + + + SET_PARA_FINISH + Finish initial configuration. + 0x4C + 0x20 + + + SET_PARA_END + Finish hmac configuration. + 0 + 1 + write-only + + + + + SET_MESSAGE_ONE + Process control register 1. + 0x50 + 0x20 + + + SET_TEXT_ONE + Call SHA to calculate one message block. + 0 + 1 + write-only + + + + + SET_MESSAGE_ING + Process control register 2. + 0x54 + 0x20 + + + SET_TEXT_ING + Continue typical hmac. + 0 + 1 + write-only + + + + + SET_MESSAGE_END + Process control register 3. + 0x58 + 0x20 + + + SET_TEXT_END + Start hardware padding. + 0 + 1 + write-only + + + + + SET_RESULT_FINISH + Process control register 4. + 0x5C + 0x20 + + + SET_RESULT_END + After read result from upstream, then let hmac back to idle. + 0 + 1 + write-only + + + + + SET_INVALIDATE_JTAG + Invalidate register 0. + 0x60 + 0x20 + + + SET_INVALIDATE_JTAG + Clear result from hmac downstream JTAG. + 0 + 1 + write-only + + + + + SET_INVALIDATE_DS + Invalidate register 1. + 0x64 + 0x20 + + + SET_INVALIDATE_DS + Clear result from hmac downstream DS. + 0 + 1 + write-only + + + + + QUERY_ERROR + Error register. + 0x68 + 0x20 + + + QUERY_CHECK + Hmac configuration state. 0: key are agree with purpose. 1: error + 0 + 1 + read-only + + + + + QUERY_BUSY + Busy register. + 0x6C + 0x20 + + + BUSY_STATE + Hmac state. 1'b0: idle. 1'b1: busy + 0 + 1 + read-only + + + + + 16 + 0x4 + WR_MESSAGE_MEM[%s] + Message block memory. + 0x80 + 0x20 + + + 8 + 0x4 + RD_RESULT_MEM[%s] + Result from upstream. + 0xC0 + 0x20 + + + SET_MESSAGE_PAD + Process control register 5. + 0xF0 + 0x20 + + + SET_TEXT_PAD + Start software padding. + 0 + 1 + write-only + + + + + ONE_BLOCK + Process control register 6. + 0xF4 + 0x20 + + + SET_ONE_BLOCK + Don't have to do padding. + 0 + 1 + write-only + + + + + SOFT_JTAG_CTRL + Jtag register 0. + 0xF8 + 0x20 + + + SOFT_JTAG_CTRL + Turn on JTAG verification. + 0 + 1 + write-only + + + + + WR_JTAG + Jtag register 1. + 0xFC + 0x20 + + + WR_JTAG + 32-bit of key to be compared. + 0 + 32 + write-only + + + + + DATE + Date register. + 0x1FC + 0x20 + 0x20200618 + + + DATE + Hmac date information/ hmac version information. + 0 + 30 + read-write + + + + + + + HP_SYS + High-Power System + HP_SYS + 0x500E5000 + + 0x0 + 0x16C + registers + + + HP_SYS + 110 + + + + VER_DATE + NA + 0x0 + 0x20 + 0x20230519 + + + REG_VER_DATE + NA + 0 + 32 + read-write + + + + + CLK_EN + NA + 0x4 + 0x20 + + + REG_CLK_EN + NA + 0 + 1 + read-write + + + + + CPU_INTR_FROM_CPU_0 + NA + 0x10 + 0x20 + + + CPU_INTR_FROM_CPU_0 + set 1 will triger a interrupt + 0 + 1 + read-write + + + + + CPU_INTR_FROM_CPU_1 + NA + 0x14 + 0x20 + + + CPU_INTR_FROM_CPU_1 + set 1 will triger a interrupt + 0 + 1 + read-write + + + + + CPU_INTR_FROM_CPU_2 + NA + 0x18 + 0x20 + + + CPU_INTR_FROM_CPU_2 + set 1 will triger a interrupt + 0 + 1 + read-write + + + + + CPU_INTR_FROM_CPU_3 + NA + 0x1C + 0x20 + + + CPU_INTR_FROM_CPU_3 + set 1 will triger a interrupt + 0 + 1 + read-write + + + + + CACHE_CLK_CONFIG + NA + 0x20 + 0x20 + 0x00000033 + + + REG_L2_CACHE_CLK_ON + l2 cahce clk enable + 0 + 1 + read-write + + + REG_L1_D_CACHE_CLK_ON + l1 dcahce clk enable + 1 + 1 + read-write + + + REG_L1_I1_CACHE_CLK_ON + l1 icahce1 clk enable + 4 + 1 + read-write + + + REG_L1_I0_CACHE_CLK_ON + l1 icahce0 clk enable + 5 + 1 + read-write + + + + + CACHE_RESET_CONFIG + NA + 0x24 + 0x20 + + + REG_L1_D_CACHE_RESET + set 1 to reset l1 dcahce + 1 + 1 + read-write + + + REG_L1_I1_CACHE_RESET + set 1 to reset l1 icahce1 + 4 + 1 + read-write + + + REG_L1_I0_CACHE_RESET + set 1 to reset l1 icahce0 + 5 + 1 + read-write + + + + + DMA_ADDR_CTRL + NA + 0x2C + 0x20 + + + REG_SYS_DMA_ADDR_SEL + 0 means dma access extmem use 8xxx_xxxx else use 4xxx_xxxx + 0 + 1 + read-write + + + + + TCM_RAM_WRR_CONFIG + NA + 0x34 + 0x20 + 0x826ED93F + + + REG_TCM_RAM_IBUS0_WT + weight value of ibus0 + 0 + 3 + read-write + + + REG_TCM_RAM_IBUS1_WT + weight value of ibus1 + 3 + 3 + read-write + + + REG_TCM_RAM_IBUS2_WT + weight value of ibus2 + 6 + 3 + read-write + + + REG_TCM_RAM_IBUS3_WT + weight value of ibus3 + 9 + 3 + read-write + + + REG_TCM_RAM_DBUS0_WT + weight value of dbus0 + 12 + 3 + read-write + + + REG_TCM_RAM_DBUS1_WT + weight value of dbus1 + 15 + 3 + read-write + + + REG_TCM_RAM_DBUS2_WT + weight value of dbus2 + 18 + 3 + read-write + + + REG_TCM_RAM_DBUS3_WT + weight value of dbus3 + 21 + 3 + read-write + + + REG_TCM_RAM_DMA_WT + weight value of dma + 24 + 3 + read-write + + + REG_TCM_RAM_WRR_HIGH + enable weighted round robin arbitration + 31 + 1 + read-write + + + + + TCM_SW_PARITY_BWE_MASK + NA + 0x38 + 0x20 + + + REG_TCM_SW_PARITY_BWE_MASK_CTRL + Set 1 to mask tcm bwe parity code bit + 0 + 1 + read-write + + + + + TCM_RAM_PWR_CTRL0 + NA + 0x3C + 0x20 + + + REG_HP_TCM_CLK_FORCE_ON + hp_tcm clk gatig force on + 0 + 1 + read-write + + + + + L2_ROM_PWR_CTRL0 + NA + 0x40 + 0x20 + + + REG_L2_ROM_CLK_FORCE_ON + l2_rom clk gating force on + 0 + 1 + read-write + + + + + PROBEA_CTRL + NA + 0x50 + 0x20 + + + REG_PROBE_A_MOD_SEL + Tihs field is used to selec probe_group from probe_group0 to probe_group15 for module's probe_out[31:0] in a mode + 0 + 16 + read-write + + + REG_PROBE_A_TOP_SEL + Tihs field is used to selec module's probe_out[31:0] as probe out in a mode + 16 + 8 + read-write + + + REG_PROBE_L_SEL + Tihs field is used to selec probe_out[31:16] + 24 + 2 + read-write + + + REG_PROBE_H_SEL + Tihs field is used to selec probe_out[31:16] + 26 + 2 + read-write + + + REG_PROBE_GLOBAL_EN + Set this bit to enable global debug probe in hp system. + 28 + 1 + read-write + + + + + PROBEB_CTRL + NA + 0x54 + 0x20 + + + REG_PROBE_B_MOD_SEL + Tihs field is used to selec probe_group from probe_group0 to probe_group15 for module's probe_out[31:0] in b mode. + 0 + 16 + read-write + + + REG_PROBE_B_TOP_SEL + Tihs field is used to select module's probe_out[31:0] as probe_out in b mode + 16 + 8 + read-write + + + REG_PROBE_B_EN + Set this bit to enable b mode for debug probe. 1: b mode, 0: a mode. + 24 + 1 + read-write + + + + + PROBE_OUT + NA + 0x5C + 0x20 + + + REG_PROBE_TOP_OUT + NA + 0 + 32 + read-only + + + + + L2_MEM_RAM_PWR_CTRL0 + NA + 0x60 + 0x20 + + + REG_L2_MEM_CLK_FORCE_ON + l2ram clk_gating force on + 0 + 1 + read-write + + + + + CPU_CORESTALLED_ST + NA + 0x64 + 0x20 + + + REG_CORE0_CORESTALLED_ST + hp core0 corestalled status + 0 + 1 + read-only + + + REG_CORE1_CORESTALLED_ST + hp core1 corestalled status + 1 + 1 + read-only + + + + + CRYPTO_CTRL + NA + 0x70 + 0x20 + + + REG_ENABLE_SPI_MANUAL_ENCRYPT + NA + 0 + 1 + read-write + + + REG_ENABLE_DOWNLOAD_DB_ENCRYPT + NA + 1 + 1 + read-write + + + REG_ENABLE_DOWNLOAD_G0CB_DECRYPT + NA + 2 + 1 + read-write + + + REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT + NA + 3 + 1 + read-write + + + + + GPIO_O_HOLD_CTRL0 + NA + 0x74 + 0x20 + + + REG_GPIO_0_HOLD_LOW + hold control for gpio47~16 + 0 + 32 + read-write + + + + + GPIO_O_HOLD_CTRL1 + NA + 0x78 + 0x20 + + + REG_GPIO_0_HOLD_HIGH + hold control for gpio56~48 + 0 + 9 + read-write + + + + + RDN_ECO_CS + NA + 0x7C + 0x20 + + + REG_HP_SYS_RDN_ECO_EN + NA + 0 + 1 + read-write + + + REG_HP_SYS_RDN_ECO_RESULT + NA + 1 + 1 + read-only + + + + + CACHE_APB_POSTW_EN + NA + 0x80 + 0x20 + + + REG_CACHE_APB_POSTW_EN + cache apb register interface post write enable, 1 will speed up write, but will take some time to update value to register + 0 + 1 + read-write + + + + + L2_MEM_SUBSIZE + NA + 0x84 + 0x20 + + + REG_L2_MEM_SUB_BLKSIZE + l2mem sub block size 00=>32 01=>64 10=>128 11=>256 + 0 + 2 + read-write + + + + + L2_MEM_INT_RAW + NA + 0x9C + 0x20 + + + REG_L2_MEM_ECC_ERR_INT_RAW + intr triggered when two bit error detected and corrected from ecc + 0 + 1 + read-write + + + REG_L2_MEM_EXCEED_ADDR_INT_RAW + intr triggered when access addr exceeds 0xff9ffff at bypass mode or exceeds 0xff80000 at l2cache 128kb mode or exceeds 0xff60000 at l2cache 256kb mode + 1 + 1 + read-write + + + REG_L2_MEM_ERR_RESP_INT_RAW + intr triggered when err response occurs + 2 + 1 + read-write + + + + + L2_MEM_INT_ST + NA + 0xA0 + 0x20 + + + REG_L2_MEM_ECC_ERR_INT_ST + NA + 0 + 1 + read-only + + + REG_L2_MEM_EXCEED_ADDR_INT_ST + NA + 1 + 1 + read-only + + + REG_L2_MEM_ERR_RESP_INT_ST + NA + 2 + 1 + read-only + + + + + L2_MEM_INT_ENA + NA + 0xA4 + 0x20 + + + REG_L2_MEM_ECC_ERR_INT_ENA + NA + 0 + 1 + read-write + + + REG_L2_MEM_EXCEED_ADDR_INT_ENA + NA + 1 + 1 + read-write + + + REG_L2_MEM_ERR_RESP_INT_ENA + NA + 2 + 1 + read-write + + + + + L2_MEM_INT_CLR + NA + 0xA8 + 0x20 + + + REG_L2_MEM_ECC_ERR_INT_CLR + NA + 0 + 1 + write-only + + + REG_L2_MEM_EXCEED_ADDR_INT_CLR + NA + 1 + 1 + write-only + + + REG_L2_MEM_ERR_RESP_INT_CLR + NA + 2 + 1 + write-only + + + + + L2_MEM_L2_RAM_ECC + NA + 0xAC + 0x20 + + + REG_L2_RAM_UNIT0_ECC_EN + NA + 0 + 1 + read-write + + + REG_L2_RAM_UNIT1_ECC_EN + NA + 1 + 1 + read-write + + + REG_L2_RAM_UNIT2_ECC_EN + NA + 2 + 1 + read-write + + + REG_L2_RAM_UNIT3_ECC_EN + NA + 3 + 1 + read-write + + + REG_L2_RAM_UNIT4_ECC_EN + NA + 4 + 1 + read-write + + + REG_L2_RAM_UNIT5_ECC_EN + NA + 5 + 1 + read-write + + + + + L2_MEM_INT_RECORD0 + NA + 0xB0 + 0x20 + + + REG_L2_MEM_EXCEED_ADDR_INT_ADDR + NA + 0 + 21 + read-only + + + REG_L2_MEM_EXCEED_ADDR_INT_WE + NA + 21 + 1 + read-only + + + REG_L2_MEM_EXCEED_ADDR_INT_MASTER + NA + 22 + 3 + read-only + + + + + L2_MEM_INT_RECORD1 + NA + 0xB4 + 0x20 + + + REG_L2_MEM_ECC_ERR_INT_ADDR + NA + 0 + 15 + read-only + + + REG_L2_MEM_ECC_ONE_BIT_ERR + NA + 15 + 1 + read-only + + + REG_L2_MEM_ECC_TWO_BIT_ERR + NA + 16 + 1 + read-only + + + REG_L2_MEM_ECC_ERR_BIT + NA + 17 + 9 + read-only + + + REG_L2_CACHE_ERR_BANK + NA + 26 + 1 + read-only + + + + + L2_MEM_L2_CACHE_ECC + NA + 0xC4 + 0x20 + + + REG_L2_CACHE_ECC_EN + NA + 0 + 1 + read-write + + + + + L1CACHE_BUS0_ID + NA + 0xC8 + 0x20 + + + REG_L1_CACHE_BUS0_ID + NA + 0 + 4 + read-write + + + + + L1CACHE_BUS1_ID + NA + 0xCC + 0x20 + + + REG_L1_CACHE_BUS1_ID + NA + 0 + 4 + read-write + + + + + L2_MEM_RDN_ECO_CS + NA + 0xD8 + 0x20 + + + REG_L2_MEM_RDN_ECO_EN + NA + 0 + 1 + read-write + + + REG_L2_MEM_RDN_ECO_RESULT + NA + 1 + 1 + read-only + + + + + L2_MEM_RDN_ECO_LOW + NA + 0xDC + 0x20 + + + REG_L2_MEM_RDN_ECO_LOW + NA + 0 + 32 + read-write + + + + + L2_MEM_RDN_ECO_HIGH + NA + 0xE0 + 0x20 + 0xFFFFFFFF + + + REG_L2_MEM_RDN_ECO_HIGH + NA + 0 + 32 + read-write + + + + + TCM_RDN_ECO_CS + NA + 0xE4 + 0x20 + + + REG_HP_TCM_RDN_ECO_EN + NA + 0 + 1 + read-write + + + REG_HP_TCM_RDN_ECO_RESULT + NA + 1 + 1 + read-only + + + + + TCM_RDN_ECO_LOW + NA + 0xE8 + 0x20 + + + REG_HP_TCM_RDN_ECO_LOW + NA + 0 + 32 + read-write + + + + + TCM_RDN_ECO_HIGH + NA + 0xEC + 0x20 + 0xFFFFFFFF + + + REG_HP_TCM_RDN_ECO_HIGH + NA + 0 + 32 + read-write + + + + + GPIO_DED_HOLD_CTRL + NA + 0xF0 + 0x20 + + + REG_GPIO_DED_HOLD + hold control for gpio63~56 + 0 + 26 + read-write + + + + + L2_MEM_SW_ECC_BWE_MASK + NA + 0xF4 + 0x20 + + + REG_L2_MEM_SW_ECC_BWE_MASK_CTRL + Set 1 to mask bwe hamming code bit + 0 + 1 + read-write + + + + + USB20OTG_MEM_CTRL + NA + 0xF8 + 0x20 + + + REG_USB20_MEM_CLK_FORCE_ON + NA + 0 + 1 + read-write + + + + + TCM_INT_RAW + need_des + 0xFC + 0x20 + + + TCM_PARITY_ERR_INT_RAW + need_des + 31 + 1 + read-write + + + + + TCM_INT_ST + need_des + 0x100 + 0x20 + + + TCM_PARITY_ERR_INT_ST + need_des + 31 + 1 + read-only + + + + + TCM_INT_ENA + need_des + 0x104 + 0x20 + + + TCM_PARITY_ERR_INT_ENA + need_des + 31 + 1 + read-write + + + + + TCM_INT_CLR + need_des + 0x108 + 0x20 + + + TCM_PARITY_ERR_INT_CLR + need_des + 31 + 1 + write-only + + + + + TCM_PARITY_INT_RECORD + need_des + 0x10C + 0x20 + + + TCM_PARITY_ERR_INT_ADDR + hp tcm_parity_err_addr + 0 + 13 + read-only + + + + + L1_CACHE_PWR_CTRL + NA + 0x110 + 0x20 + + + REG_L1_CACHE_MEM_FO + need_des + 0 + 6 + read-write + + + + + L2_CACHE_PWR_CTRL + NA + 0x114 + 0x20 + + + REG_L2_CACHE_MEM_FO + need_des + 0 + 2 + read-write + + + + + CPU_WAITI_CONF + CPU_WAITI configuration register + 0x118 + 0x20 + 0x00000001 + + + CPU_WAIT_MODE_FORCE_ON + Set 1 to force cpu_waiti_clk enable. + 0 + 1 + read-write + + + CPU_WAITI_DELAY_NUM + This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk will close + 1 + 4 + read-write + + + + + CORE_DEBUG_RUNSTALL_CONF + Core Debug runstall configure register + 0x11C + 0x20 + + + CORE_DEBUG_RUNSTALL_ENABLE + Set this field to 1 to enable debug runstall feature between HP-core and LP-core. + 0 + 1 + read-write + + + + + CORE_AHB_TIMEOUT + need_des + 0x120 + 0x20 + 0x0001FFFF + + + EN + set this field to 1 to enable hp core0&1 ahb timeout handle + 0 + 1 + read-write + + + THRES + This field used to set hp core0&1 ahb bus timeout threshold + 1 + 16 + read-write + + + + + CORE_IBUS_TIMEOUT + need_des + 0x124 + 0x20 + 0x0001FFFF + + + EN + set this field to 1 to enable hp core0&1 ibus timeout handle + 0 + 1 + read-write + + + THRES + This field used to set hp core0&1 ibus timeout threshold + 1 + 16 + read-write + + + + + CORE_DBUS_TIMEOUT + need_des + 0x128 + 0x20 + 0x0001FFFF + + + EN + set this field to 1 to enable hp core0&1 dbus timeout handle + 0 + 1 + read-write + + + THRES + This field used to set hp core0&1 dbus timeout threshold + 1 + 16 + read-write + + + + + ICM_CPU_H2X_CFG + need_des + 0x138 + 0x20 + 0x00000003 + + + CPU_ICM_H2X_POST_WR_EN + need_des + 0 + 1 + read-write + + + CPU_ICM_H2X_CUT_THROUGH_EN + need_des + 1 + 1 + read-write + + + CPU_ICM_H2X_BRIDGE_BUSY + need_des + 2 + 1 + read-only + + + + + PERI1_APB_POSTW_EN + NA + 0x13C + 0x20 + + + PERI1_APB_POSTW_EN + hp_peri1 apb register interface post write enable, 1 will speed up write, but will take some time to update value to register + 0 + 1 + read-write + + + + + BITSCRAMBLER_PERI_SEL + Bitscrambler Peri Sel + 0x140 + 0x20 + 0x000000FF + + + BITSCRAMBLER_PERI_RX_SEL + Set this field to sel peri with DMA RX interface to connec with bitscrambler: 4'h0 : lcd_cam, 4'h1: gpspi2, 4'h2: gpspi3, 4'h3: parl_io, 4'h4: aes, 4'h5: sha, 4'h6: adc, 4'h7: i2s0, 4'h8: i2s1, 4'h9: i2s2, 4'ha: i3c_mst, 4'hb: uhci0, 4'hc: RMT, else : none + 0 + 4 + read-write + + + BITSCRAMBLER_PERI_TX_SEL + Set this field to sel peri with DMA TX interface to connec with bitscrambler: 4'h0 : lcd_cam, 4'h1: gpspi2, 4'h2: gpspi3, 4'h3: parl_io, 4'h4: aes, 4'h5: sha, 4'h6: adc, 4'h7: i2s0, 4'h8: i2s1, 4'h9: i2s2, 4'ha: i3c_mst, 4'hb: uhci0, 4'hc: RMT, else : none + 4 + 4 + read-write + + + + + APB_SYNC_POSTW_EN + N/A + 0x144 + 0x20 + + + GMAC_APB_POSTW_EN + N/A + 0 + 1 + read-write + + + DSI_HOST_APB_POSTW_EN + N/A + 1 + 1 + read-write + + + CSI_HOST_APB_SYNC_POSTW_EN + N/A + 2 + 1 + read-write + + + CSI_HOST_APB_ASYNC_POSTW_EN + N/A + 3 + 1 + read-write + + + + + GDMA_CTRL + N/A + 0x148 + 0x20 + + + DEBUG_CH_NUM + N/A + 0 + 2 + read-write + + + + + GMAC_CTRL0 + N/A + 0x14C + 0x20 + + + PTP_PPS + N/A + 0 + 1 + read-only + + + SBD_FLOWCTRL + N/A + 1 + 1 + read-write + + + PHY_INTF_SEL + N/A + 2 + 3 + read-write + + + GMAC_MEM_CLK_FORCE_ON + N/A + 5 + 1 + read-write + + + GMAC_RST_CLK_TX_N + N/A + 6 + 1 + read-only + + + GMAC_RST_CLK_RX_N + N/A + 7 + 1 + read-only + + + + + GMAC_CTRL1 + N/A + 0x150 + 0x20 + + + PTP_TIMESTAMP_L + N/A + 0 + 32 + read-only + + + + + GMAC_CTRL2 + N/A + 0x154 + 0x20 + + + PTP_TIMESTAMP_H + N/A + 0 + 32 + read-only + + + + + VPU_CTRL + N/A + 0x158 + 0x20 + + + PPA_LSLP_MEM_PD + N/A + 0 + 1 + read-write + + + JPEG_SDSLP_MEM_PD + N/A + 1 + 1 + read-write + + + JPEG_LSLP_MEM_PD + N/A + 2 + 1 + read-write + + + JPEG_DSLP_MEM_PD + N/A + 3 + 1 + read-write + + + DMA2D_LSLP_MEM_PD + N/A + 4 + 1 + read-write + + + + + USBOTG20_CTRL + N/A + 0x15C + 0x20 + 0x00822640 + + + OTG_PHY_TEST_DONE + N/A + 0 + 1 + read-only + + + USB_MEM_AUX_CTRL + N/A + 1 + 14 + read-write + + + PHY_SUSPENDM + N/A + 15 + 1 + read-write + + + PHY_SUSPEND_FORCE_EN + N/A + 16 + 1 + read-write + + + PHY_RSTN + N/A + 17 + 1 + read-write + + + PHY_RESET_FORCE_EN + N/A + 18 + 1 + read-write + + + PHY_PLL_FORCE_EN + N/A + 19 + 1 + read-write + + + PHY_PLL_EN + N/A + 20 + 1 + read-write + + + OTG_SUSPENDM + N/A + 21 + 1 + read-write + + + OTG_PHY_TXBITSTUFF_EN + N/A + 22 + 1 + read-write + + + OTG_PHY_REFCLK_MODE + N/A + 23 + 1 + read-write + + + OTG_PHY_BISTEN + N/A + 24 + 1 + read-write + + + + + TCM_ERR_RESP_CTRL + need_des + 0x160 + 0x20 + + + TCM_ERR_RESP_EN + Set 1 to turn on tcm error response + 0 + 1 + read-write + + + + + L2_MEM_REFRESH + NA + 0x164 + 0x20 + 0x00000040 + + + REG_L2_MEM_UNIT0_REFERSH_EN + NA + 0 + 1 + read-write + + + REG_L2_MEM_UNIT1_REFERSH_EN + NA + 1 + 1 + read-write + + + REG_L2_MEM_UNIT2_REFERSH_EN + NA + 2 + 1 + read-write + + + REG_L2_MEM_UNIT3_REFERSH_EN + NA + 3 + 1 + read-write + + + REG_L2_MEM_UNIT4_REFERSH_EN + NA + 4 + 1 + read-write + + + REG_L2_MEM_UNIT5_REFERSH_EN + NA + 5 + 1 + read-write + + + REG_L2_MEM_REFERSH_CNT_RESET + Set 1 to reset l2mem_refresh_cnt + 6 + 1 + read-write + + + REG_L2_MEM_UNIT0_REFRESH_DONE + NA + 7 + 1 + read-only + + + REG_L2_MEM_UNIT1_REFRESH_DONE + NA + 8 + 1 + read-only + + + REG_L2_MEM_UNIT2_REFRESH_DONE + NA + 9 + 1 + read-only + + + REG_L2_MEM_UNIT3_REFRESH_DONE + NA + 10 + 1 + read-only + + + REG_L2_MEM_UNIT4_REFRESH_DONE + NA + 11 + 1 + read-only + + + REG_L2_MEM_UNIT5_REFRESH_DONE + NA + 12 + 1 + read-only + + + + + TCM_INIT + NA + 0x168 + 0x20 + 0x00000002 + + + REG_TCM_INIT_EN + NA + 0 + 1 + read-write + + + REG_TCM_INIT_CNT_RESET + Set 1 to reset tcm init cnt + 1 + 1 + read-write + + + REG_TCM_INIT_DONE + NA + 2 + 1 + read-only + + + + + TCM_PARITY_CHECK_CTRL + need_des + 0x16C + 0x20 + + + TCM_PARITY_CHECK_EN + Set 1 to turn on tcm parity check + 0 + 1 + read-write + + + + + DESIGN_FOR_VERIFICATION0 + need_des + 0x170 + 0x20 + + + DFV0 + register for DV + 0 + 32 + read-write + + + + + DESIGN_FOR_VERIFICATION1 + need_des + 0x174 + 0x20 + + + DFV1 + register for DV + 0 + 32 + read-write + + + + + PSRAM_FLASH_ADDR_INTERCHANGE + need_des + 0x180 + 0x20 + + + CPU + Set 1 to enable addr interchange between psram and flash in axi matrix when hp cpu access through cache + 0 + 1 + read-write + + + DMA + Set 1 to enable addr interchange between psram and flash in axi matrix when dma device access, lp core access and hp core access through ahb + 1 + 1 + read-write + + + + + AHB2AXI_BRESP_ERR_INT_RAW + NA + 0x188 + 0x20 + + + CPU_ICM_H2X_BRESP_ERR_INT_RAW + the raw interrupt status of bresp error, triggered when if bresp err occurs in post write mode in ahb2axi. + 0 + 1 + read-write + + + + + AHB2AXI_BRESP_ERR_INT_ST + need_des + 0x18C + 0x20 + + + CPU_ICM_H2X_BRESP_ERR_INT_ST + the masked interrupt status of cpu_icm_h2x_bresp_err + 31 + 1 + read-only + + + + + AHB2AXI_BRESP_ERR_INT_ENA + need_des + 0x190 + 0x20 + + + CPU_ICM_H2X_BRESP_ERR_INT_ENA + Write 1 to enable cpu_icm_h2x_bresp_err int + 31 + 1 + read-write + + + + + AHB2AXI_BRESP_ERR_INT_CLR + need_des + 0x194 + 0x20 + + + CPU_ICM_H2X_BRESP_ERR_INT_CLR + Write 1 to clear cpu_icm_h2x_bresp_err int + 31 + 1 + write-only + + + + + L2_MEM_ERR_RESP_CTRL + need_des + 0x198 + 0x20 + + + L2_MEM_ERR_RESP_EN + Set 1 to turn on l2mem error response + 0 + 1 + read-write + + + + + L2_MEM_AHB_BUFFER_CTRL + need_des + 0x19C + 0x20 + + + L2_MEM_AHB_WRBUFFER_EN + Set 1 to turn on l2mem ahb wr buffer + 0 + 1 + read-write + + + L2_MEM_AHB_RDBUFFER_EN + Set 1 to turn on l2mem ahb rd buffer + 1 + 1 + read-write + + + + + CORE_DMACTIVE_LPCORE + need_des + 0x1A0 + 0x20 + + + CORE_DMACTIVE_LPCORE + hp core dmactive_lpcore value + 0 + 1 + read-only + + + + + CORE_ERR_RESP_DIS + need_des + 0x1A4 + 0x20 + + + CORE_ERR_RESP_DIS + Set bit0 to disable ibus err resp. Set bit1 to disable dbus err resp. Set bit 2 to disable ahb err resp. + 0 + 3 + read-write + + + + + CORE_TIMEOUT_INT_RAW + Hp core bus timeout interrupt raw register + 0x1A8 + 0x20 + + + CORE0_AHB_TIMEOUT_INT_RAW + the raw interrupt status of hp core0 ahb timeout + 0 + 1 + read-write + + + CORE1_AHB_TIMEOUT_INT_RAW + the raw interrupt status of hp core1 ahb timeout + 1 + 1 + read-write + + + CORE0_IBUS_TIMEOUT_INT_RAW + the raw interrupt status of hp core0 ibus timeout + 2 + 1 + read-write + + + CORE1_IBUS_TIMEOUT_INT_RAW + the raw interrupt status of hp core1 ibus timeout + 3 + 1 + read-write + + + CORE0_DBUS_TIMEOUT_INT_RAW + the raw interrupt status of hp core0 dbus timeout + 4 + 1 + read-write + + + CORE1_DBUS_TIMEOUT_INT_RAW + the raw interrupt status of hp core1 dbus timeout + 5 + 1 + read-write + + + + + CORE_TIMEOUT_INT_ST + masked interrupt register + 0x1AC + 0x20 + + + CORE0_AHB_TIMEOUT_INT_ST + the masked interrupt status of hp core0 ahb timeout + 0 + 1 + read-only + + + CORE1_AHB_TIMEOUT_INT_ST + the masked interrupt status of hp core1 ahb timeout + 1 + 1 + read-only + + + CORE0_IBUS_TIMEOUT_INT_ST + the masked interrupt status of hp core0 ibus timeout + 2 + 1 + read-only + + + CORE1_IBUS_TIMEOUT_INT_ST + the masked interrupt status of hp core1 ibus timeout + 3 + 1 + read-only + + + CORE0_DBUS_TIMEOUT_INT_ST + the masked interrupt status of hp core0 dbus timeout + 4 + 1 + read-only + + + CORE1_DBUS_TIMEOUT_INT_ST + the masked interrupt status of hp core1 dbus timeout + 5 + 1 + read-only + + + + + CORE_TIMEOUT_INT_ENA + masked interrupt register + 0x1B0 + 0x20 + + + CORE0_AHB_TIMEOUT_INT_ENA + Write 1 to enable hp_core0_ahb_timeout int + 0 + 1 + read-write + + + CORE1_AHB_TIMEOUT_INT_ENA + Write 1 to enable hp_core1_ahb_timeout int + 1 + 1 + read-write + + + CORE0_IBUS_TIMEOUT_INT_ENA + Write 1 to enable hp_core0_ibus_timeout int + 2 + 1 + read-write + + + CORE1_IBUS_TIMEOUT_INT_ENA + Write 1 to enable hp_core1_ibus_timeout int + 3 + 1 + read-write + + + CORE0_DBUS_TIMEOUT_INT_ENA + Write 1 to enable hp_core0_dbus_timeout int + 4 + 1 + read-write + + + CORE1_DBUS_TIMEOUT_INT_ENA + Write 1 to enable hp_core1_dbus_timeout int + 5 + 1 + read-write + + + + + CORE_TIMEOUT_INT_CLR + interrupt clear register + 0x1B4 + 0x20 + + + CORE0_AHB_TIMEOUT_INT_CLR + Write 1 to clear hp_core0_ahb_timeout int + 0 + 1 + write-only + + + CORE1_AHB_TIMEOUT_INT_CLR + Write 1 to clear hp_core1_ahb_timeout int + 1 + 1 + write-only + + + CORE0_IBUS_TIMEOUT_INT_CLR + Write 1 to clear hp_core0_ibus_timeout int + 2 + 1 + write-only + + + CORE1_IBUS_TIMEOUT_INT_CLR + Write 1 to clear hp_core1_ibus_timeout int + 3 + 1 + write-only + + + CORE0_DBUS_TIMEOUT_INT_CLR + Write 1 to clear hp_core0_dbus_timeout int + 4 + 1 + write-only + + + CORE1_DBUS_TIMEOUT_INT_CLR + Write 1 to clear hp_core1_dbus_timeout int + 5 + 1 + write-only + + + + + GPIO_O_HYS_CTRL0 + NA + 0x1C0 + 0x20 + + + REG_GPIO_0_HYS_LOW + hys control for gpio47~16 + 0 + 32 + read-write + + + + + GPIO_O_HYS_CTRL1 + NA + 0x1C4 + 0x20 + + + REG_GPIO_0_HYS_HIGH + hys control for gpio56~48 + 0 + 9 + read-write + + + + + RSA_PD_CTRL + rsa pd ctrl register + 0x1D0 + 0x20 + 0x00000002 + + + RSA_MEM_FORCE_PD + Set this bit to power down rsa internal memory. + 0 + 1 + read-write + + + RSA_MEM_FORCE_PU + Set this bit to force power up rsa internal memory + 1 + 1 + read-write + + + RSA_MEM_PD + Set this bit to force power down rsa internal memory. + 2 + 1 + read-write + + + + + ECC_PD_CTRL + ecc pd ctrl register + 0x1D4 + 0x20 + 0x00000002 + + + ECC_MEM_FORCE_PD + Set this bit to power down ecc internal memory. + 0 + 1 + read-write + + + ECC_MEM_FORCE_PU + Set this bit to force power up ecc internal memory + 1 + 1 + read-write + + + ECC_MEM_PD + Set this bit to force power down ecc internal memory. + 2 + 1 + read-write + + + + + RNG_CFG + rng cfg register + 0x1D8 + 0x20 + + + RNG_SAMPLE_ENABLE + enable rng sample chain + 0 + 1 + read-write + + + RNG_CHAIN_CLK_DIV_NUM + chain clk div num to pad for debug + 16 + 8 + read-write + + + RNG_SAMPLE_CNT + debug rng sample cnt + 24 + 8 + read-only + + + + + UART_PD_CTRL + ecc pd ctrl register + 0x1DC + 0x20 + 0x00000002 + + + UART_MEM_FORCE_PD + Set this bit to power down hp uart internal memory. + 0 + 1 + read-write + + + UART_MEM_FORCE_PU + Set this bit to force power up hp uart internal memory + 1 + 1 + read-write + + + + + PERI_MEM_CLK_FORCE_ON + hp peri mem clk force on regpster + 0x1E0 + 0x20 + + + RMT_MEM_CLK_FORCE_ON + Set this bit to force on mem clk in rmt + 0 + 1 + read-write + + + BITSCRAMBLER_TX_MEM_CLK_FORCE_ON + Set this bit to force on tx mem clk in bitscrambler + 1 + 1 + read-write + + + BITSCRAMBLER_RX_MEM_CLK_FORCE_ON + Set this bit to force on rx mem clk in bitscrambler + 2 + 1 + read-write + + + GDMA_MEM_CLK_FORCE_ON + Set this bit to force on mem clk in gdma + 3 + 1 + read-write + + + + + + + HP_SYS_CLKRST + HP_SYS_CLKRST Peripheral + HP_SYS_CLKRST + 0x500E6000 + + 0x0 + 0xF0 + registers + + + + CLK_EN0 + Reserved + 0x0 + 0x20 + 0x00000001 + + + REG_CLK_EN + Reserved + 0 + 1 + read-write + + + + + ROOT_CLK_CTRL0 + Reserved + 0x4 + 0x20 + + + REG_CPUICM_DELAY_NUM + Reserved + 0 + 4 + read-write + + + REG_SOC_CLK_DIV_UPDATE + Reserved + 4 + 1 + write-only + + + REG_CPU_CLK_DIV_NUM + Reserved + 5 + 8 + read-write + + + REG_CPU_CLK_DIV_NUMERATOR + Reserved + 13 + 8 + read-write + + + REG_CPU_CLK_DIV_DENOMINATOR + Reserved + 21 + 8 + read-write + + + + + ROOT_CLK_CTRL1 + Reserved + 0x8 + 0x20 + 0x00000001 + + + REG_MEM_CLK_DIV_NUM + Reserved + 0 + 8 + read-write + + + REG_MEM_CLK_DIV_NUMERATOR + Reserved + 8 + 8 + read-write + + + REG_MEM_CLK_DIV_DENOMINATOR + Reserved + 16 + 8 + read-write + + + REG_SYS_CLK_DIV_NUM + Reserved + 24 + 8 + read-write + + + + + ROOT_CLK_CTRL2 + Reserved + 0xC + 0x20 + 0x00010000 + + + REG_SYS_CLK_DIV_NUMERATOR + Reserved + 0 + 8 + read-write + + + REG_SYS_CLK_DIV_DENOMINATOR + Reserved + 8 + 8 + read-write + + + REG_APB_CLK_DIV_NUM + Reserved + 16 + 8 + read-write + + + REG_APB_CLK_DIV_NUMERATOR + Reserved + 24 + 8 + read-write + + + + + ROOT_CLK_CTRL3 + Reserved + 0x10 + 0x20 + + + REG_APB_CLK_DIV_DENOMINATOR + Reserved + 0 + 8 + read-write + + + + + SOC_CLK_CTRL0 + Reserved + 0x14 + 0x20 + 0xE6DF97AF + + + REG_CORE0_CLIC_CLK_EN + Reserved + 0 + 1 + read-write + + + REG_CORE1_CLIC_CLK_EN + Reserved + 1 + 1 + read-write + + + REG_MISC_CPU_CLK_EN + Reserved + 2 + 1 + read-write + + + REG_CORE0_CPU_CLK_EN + Reserved + 3 + 1 + read-write + + + REG_CORE1_CPU_CLK_EN + Reserved + 4 + 1 + read-write + + + REG_TCM_CPU_CLK_EN + Reserved + 5 + 1 + read-write + + + REG_BUSMON_CPU_CLK_EN + Reserved + 6 + 1 + read-write + + + REG_L1CACHE_CPU_CLK_EN + Reserved + 7 + 1 + read-write + + + REG_L1CACHE_D_CPU_CLK_EN + Reserved + 8 + 1 + read-write + + + REG_L1CACHE_I0_CPU_CLK_EN + Reserved + 9 + 1 + read-write + + + REG_L1CACHE_I1_CPU_CLK_EN + Reserved + 10 + 1 + read-write + + + REG_TRACE_CPU_CLK_EN + Reserved + 11 + 1 + read-write + + + REG_ICM_CPU_CLK_EN + Reserved + 12 + 1 + read-write + + + REG_GDMA_CPU_CLK_EN + Reserved + 13 + 1 + read-write + + + REG_VPU_CPU_CLK_EN + Reserved + 14 + 1 + read-write + + + REG_L1CACHE_MEM_CLK_EN + Reserved + 15 + 1 + read-write + + + REG_L1CACHE_D_MEM_CLK_EN + Reserved + 16 + 1 + read-write + + + REG_L1CACHE_I0_MEM_CLK_EN + Reserved + 17 + 1 + read-write + + + REG_L1CACHE_I1_MEM_CLK_EN + Reserved + 18 + 1 + read-write + + + REG_L2CACHE_MEM_CLK_EN + Reserved + 19 + 1 + read-write + + + REG_L2MEM_MEM_CLK_EN + Reserved + 20 + 1 + read-write + + + REG_L2MEMMON_MEM_CLK_EN + Reserved + 21 + 1 + read-write + + + REG_ICM_MEM_CLK_EN + Reserved + 22 + 1 + read-write + + + REG_MISC_SYS_CLK_EN + Reserved + 23 + 1 + read-write + + + REG_TRACE_SYS_CLK_EN + Reserved + 24 + 1 + read-write + + + REG_L2CACHE_SYS_CLK_EN + Reserved + 25 + 1 + read-write + + + REG_L2MEM_SYS_CLK_EN + Reserved + 26 + 1 + read-write + + + REG_L2MEMMON_SYS_CLK_EN + Reserved + 27 + 1 + read-write + + + REG_TCMMON_SYS_CLK_EN + Reserved + 28 + 1 + read-write + + + REG_ICM_SYS_CLK_EN + Reserved + 29 + 1 + read-write + + + REG_FLASH_SYS_CLK_EN + Reserved + 30 + 1 + read-write + + + REG_PSRAM_SYS_CLK_EN + Reserved + 31 + 1 + read-write + + + + + SOC_CLK_CTRL1 + Reserved + 0x18 + 0x20 + 0x7C7F801F + + + REG_GPSPI2_SYS_CLK_EN + Reserved + 0 + 1 + read-write + + + REG_GPSPI3_SYS_CLK_EN + Reserved + 1 + 1 + read-write + + + REG_REGDMA_SYS_CLK_EN + Reserved + 2 + 1 + read-write + + + REG_AHB_PDMA_SYS_CLK_EN + Reserved + 3 + 1 + read-write + + + REG_AXI_PDMA_SYS_CLK_EN + Reserved + 4 + 1 + read-write + + + REG_GDMA_SYS_CLK_EN + Reserved + 5 + 1 + read-write + + + REG_DMA2D_SYS_CLK_EN + Reserved + 6 + 1 + read-write + + + REG_VPU_SYS_CLK_EN + Reserved + 7 + 1 + read-write + + + REG_JPEG_SYS_CLK_EN + Reserved + 8 + 1 + read-write + + + REG_PPA_SYS_CLK_EN + Reserved + 9 + 1 + read-write + + + REG_CSI_BRG_SYS_CLK_EN + Reserved + 10 + 1 + read-write + + + REG_CSI_HOST_SYS_CLK_EN + Reserved + 11 + 1 + read-write + + + REG_DSI_SYS_CLK_EN + Reserved + 12 + 1 + read-write + + + REG_EMAC_SYS_CLK_EN + Reserved + 13 + 1 + read-write + + + REG_SDMMC_SYS_CLK_EN + Reserved + 14 + 1 + read-write + + + REG_USB_OTG11_SYS_CLK_EN + Reserved + 15 + 1 + read-write + + + REG_USB_OTG20_SYS_CLK_EN + Reserved + 16 + 1 + read-write + + + REG_UHCI_SYS_CLK_EN + Reserved + 17 + 1 + read-write + + + REG_UART0_SYS_CLK_EN + Reserved + 18 + 1 + read-write + + + REG_UART1_SYS_CLK_EN + Reserved + 19 + 1 + read-write + + + REG_UART2_SYS_CLK_EN + Reserved + 20 + 1 + read-write + + + REG_UART3_SYS_CLK_EN + Reserved + 21 + 1 + read-write + + + REG_UART4_SYS_CLK_EN + Reserved + 22 + 1 + read-write + + + REG_PARLIO_SYS_CLK_EN + Reserved + 23 + 1 + read-write + + + REG_ETM_SYS_CLK_EN + Reserved + 24 + 1 + read-write + + + REG_PVT_SYS_CLK_EN + Reserved + 25 + 1 + read-write + + + REG_CRYPTO_SYS_CLK_EN + Reserved + 26 + 1 + read-write + + + REG_KEY_MANAGER_SYS_CLK_EN + Reserved + 27 + 1 + read-write + + + REG_BITSRAMBLER_SYS_CLK_EN + Reserved + 28 + 1 + read-write + + + REG_BITSRAMBLER_RX_SYS_CLK_EN + Reserved + 29 + 1 + read-write + + + REG_BITSRAMBLER_TX_SYS_CLK_EN + Reserved + 30 + 1 + read-write + + + REG_H264_SYS_CLK_EN + Reserved + 31 + 1 + read-write + + + + + SOC_CLK_CTRL2 + Reserved + 0x1C + 0x20 + 0x20F80FDE + + + REG_RMT_SYS_CLK_EN + Reserved + 0 + 1 + read-write + + + REG_HP_CLKRST_APB_CLK_EN + Reserved + 1 + 1 + read-write + + + REG_SYSREG_APB_CLK_EN + Reserved + 2 + 1 + read-write + + + REG_ICM_APB_CLK_EN + Reserved + 3 + 1 + read-write + + + REG_INTRMTX_APB_CLK_EN + Reserved + 4 + 1 + read-write + + + REG_ADC_APB_CLK_EN + Reserved + 5 + 1 + read-write + + + REG_UHCI_APB_CLK_EN + Reserved + 6 + 1 + read-write + + + REG_UART0_APB_CLK_EN + Reserved + 7 + 1 + read-write + + + REG_UART1_APB_CLK_EN + Reserved + 8 + 1 + read-write + + + REG_UART2_APB_CLK_EN + Reserved + 9 + 1 + read-write + + + REG_UART3_APB_CLK_EN + Reserved + 10 + 1 + read-write + + + REG_UART4_APB_CLK_EN + Reserved + 11 + 1 + read-write + + + REG_I2C0_APB_CLK_EN + Reserved + 12 + 1 + read-write + + + REG_I2C1_APB_CLK_EN + Reserved + 13 + 1 + read-write + + + REG_I2S0_APB_CLK_EN + Reserved + 14 + 1 + read-write + + + REG_I2S1_APB_CLK_EN + Reserved + 15 + 1 + read-write + + + REG_I2S2_APB_CLK_EN + Reserved + 16 + 1 + read-write + + + REG_I3C_MST_APB_CLK_EN + Reserved + 17 + 1 + read-write + + + REG_I3C_SLV_APB_CLK_EN + Reserved + 18 + 1 + read-write + + + REG_GPSPI2_APB_CLK_EN + Reserved + 19 + 1 + read-write + + + REG_GPSPI3_APB_CLK_EN + Reserved + 20 + 1 + read-write + + + REG_TIMERGRP0_APB_CLK_EN + Reserved + 21 + 1 + read-write + + + REG_TIMERGRP1_APB_CLK_EN + Reserved + 22 + 1 + read-write + + + REG_SYSTIMER_APB_CLK_EN + Reserved + 23 + 1 + read-write + + + REG_TWAI0_APB_CLK_EN + Reserved + 24 + 1 + read-write + + + REG_TWAI1_APB_CLK_EN + Reserved + 25 + 1 + read-write + + + REG_TWAI2_APB_CLK_EN + Reserved + 26 + 1 + read-write + + + REG_MCPWM0_APB_CLK_EN + Reserved + 27 + 1 + read-write + + + REG_MCPWM1_APB_CLK_EN + Reserved + 28 + 1 + read-write + + + REG_USB_DEVICE_APB_CLK_EN + Reserved + 29 + 1 + read-write + + + REG_PCNT_APB_CLK_EN + Reserved + 30 + 1 + read-write + + + REG_PARLIO_APB_CLK_EN + Reserved + 31 + 1 + read-write + + + + + SOC_CLK_CTRL3 + Reserved + 0x20 + 0x20 + 0x00000008 + + + REG_LEDC_APB_CLK_EN + Reserved + 0 + 1 + read-write + + + REG_LCDCAM_APB_CLK_EN + Reserved + 1 + 1 + read-write + + + REG_ETM_APB_CLK_EN + Reserved + 2 + 1 + read-write + + + REG_IOMUX_APB_CLK_EN + Reserved + 3 + 1 + read-write + + + + + REF_CLK_CTRL0 + Reserved + 0x24 + 0x20 + 0x02011309 + + + REG_REF_50M_CLK_DIV_NUM + Reserved + 0 + 8 + read-write + + + REG_REF_25M_CLK_DIV_NUM + Reserved + 8 + 8 + read-write + + + REG_REF_240M_CLK_DIV_NUM + Reserved + 16 + 8 + read-write + + + REG_REF_160M_CLK_DIV_NUM + Reserved + 24 + 8 + read-write + + + + + REF_CLK_CTRL1 + Reserved + 0x28 + 0x20 + 0x58170503 + + + REG_REF_120M_CLK_DIV_NUM + Reserved + 0 + 8 + read-write + + + REG_REF_80M_CLK_DIV_NUM + Reserved + 8 + 8 + read-write + + + REG_REF_20M_CLK_DIV_NUM + Reserved + 16 + 8 + read-write + + + REG_TM_400M_CLK_EN + Reserved + 24 + 1 + read-write + + + REG_TM_200M_CLK_EN + Reserved + 25 + 1 + read-write + + + REG_TM_100M_CLK_EN + Reserved + 26 + 1 + read-write + + + REG_REF_50M_CLK_EN + Reserved + 27 + 1 + read-write + + + REG_REF_25M_CLK_EN + Reserved + 28 + 1 + read-write + + + REG_TM_480M_CLK_EN + Reserved + 29 + 1 + read-write + + + REG_REF_240M_CLK_EN + Reserved + 30 + 1 + read-write + + + REG_TM_240M_CLK_EN + Reserved + 31 + 1 + read-write + + + + + REF_CLK_CTRL2 + Reserved + 0x2C + 0x20 + 0x00000115 + + + REG_REF_160M_CLK_EN + Reserved + 0 + 1 + read-write + + + REG_TM_160M_CLK_EN + Reserved + 1 + 1 + read-write + + + REG_REF_120M_CLK_EN + Reserved + 2 + 1 + read-write + + + REG_TM_120M_CLK_EN + Reserved + 3 + 1 + read-write + + + REG_REF_80M_CLK_EN + Reserved + 4 + 1 + read-write + + + REG_TM_80M_CLK_EN + Reserved + 5 + 1 + read-write + + + REG_TM_60M_CLK_EN + Reserved + 6 + 1 + read-write + + + REG_TM_48M_CLK_EN + Reserved + 7 + 1 + read-write + + + REG_REF_20M_CLK_EN + Reserved + 8 + 1 + read-write + + + REG_TM_20M_CLK_EN + Reserved + 9 + 1 + read-write + + + + + PERI_CLK_CTRL00 + Reserved + 0x30 + 0x20 + 0x0000C03C + + + REG_FLASH_CLK_SRC_SEL + Reserved + 0 + 2 + read-write + + + REG_FLASH_PLL_CLK_EN + Reserved + 2 + 1 + read-write + + + REG_FLASH_CORE_CLK_EN + Reserved + 3 + 1 + read-write + + + REG_FLASH_CORE_CLK_DIV_NUM + Reserved + 4 + 8 + read-write + + + REG_PSRAM_CLK_SRC_SEL + Reserved + 12 + 2 + read-write + + + REG_PSRAM_PLL_CLK_EN + Reserved + 14 + 1 + read-write + + + REG_PSRAM_CORE_CLK_EN + Reserved + 15 + 1 + read-write + + + REG_PSRAM_CORE_CLK_DIV_NUM + Reserved + 16 + 8 + read-write + + + REG_PAD_EMAC_REF_CLK_EN + Reserved + 24 + 1 + read-write + + + REG_EMAC_RMII_CLK_SRC_SEL + Reserved + 25 + 2 + read-write + + + REG_EMAC_RMII_CLK_EN + Reserved + 27 + 1 + read-write + + + REG_EMAC_RX_CLK_SRC_SEL + Reserved + 28 + 1 + read-write + + + REG_EMAC_RX_CLK_EN + Reserved + 29 + 1 + read-write + + + + + PERI_CLK_CTRL01 + Reserved + 0x34 + 0x20 + 0x00000401 + + + REG_EMAC_RX_CLK_DIV_NUM + Reserved + 0 + 8 + read-write + + + REG_EMAC_TX_CLK_SRC_SEL + Reserved + 8 + 1 + read-write + + + REG_EMAC_TX_CLK_EN + Reserved + 9 + 1 + read-write + + + REG_EMAC_TX_CLK_DIV_NUM + Reserved + 10 + 8 + read-write + + + REG_EMAC_PTP_REF_CLK_SRC_SEL + Reserved + 18 + 1 + read-write + + + REG_EMAC_PTP_REF_CLK_EN + Reserved + 19 + 1 + read-write + + + REG_EMAC_UNUSED0_CLK_EN + Reserved + 20 + 1 + read-write + + + REG_EMAC_UNUSED1_CLK_EN + Reserved + 21 + 1 + read-write + + + REG_SDIO_HS_MODE + Reserved + 22 + 1 + read-write + + + REG_SDIO_LS_CLK_SRC_SEL + Reserved + 23 + 1 + read-write + + + REG_SDIO_LS_CLK_EN + Reserved + 24 + 1 + read-write + + + + + PERI_CLK_CTRL02 + Reserved + 0x38 + 0x20 + + + REG_SDIO_LS_CLK_DIV_NUM + Reserved + 0 + 8 + read-write + + + REG_SDIO_LS_CLK_EDGE_CFG_UPDATE + Reserved + 8 + 1 + write-only + + + REG_SDIO_LS_CLK_EDGE_L + Reserved + 9 + 4 + read-write + + + REG_SDIO_LS_CLK_EDGE_H + Reserved + 13 + 4 + read-write + + + REG_SDIO_LS_CLK_EDGE_N + Reserved + 17 + 4 + read-write + + + REG_SDIO_LS_SLF_CLK_EDGE_SEL + Reserved + 21 + 2 + read-write + + + REG_SDIO_LS_DRV_CLK_EDGE_SEL + Reserved + 23 + 2 + read-write + + + REG_SDIO_LS_SAM_CLK_EDGE_SEL + Reserved + 25 + 2 + read-write + + + REG_SDIO_LS_SLF_CLK_EN + Reserved + 27 + 1 + read-write + + + REG_SDIO_LS_DRV_CLK_EN + Reserved + 28 + 1 + read-write + + + REG_SDIO_LS_SAM_CLK_EN + Reserved + 29 + 1 + read-write + + + REG_MIPI_DSI_DPHY_CLK_SRC_SEL + Reserved + 30 + 2 + read-write + + + + + PERI_CLK_CTRL03 + Reserved + 0x3C + 0x20 + + + REG_MIPI_DSI_DPHY_CFG_CLK_EN + Reserved + 0 + 1 + read-write + + + REG_MIPI_DSI_DPHY_PLL_REFCLK_EN + Reserved + 1 + 1 + read-write + + + REG_MIPI_CSI_DPHY_CLK_SRC_SEL + Reserved + 2 + 2 + read-write + + + REG_MIPI_CSI_DPHY_CFG_CLK_EN + Reserved + 4 + 1 + read-write + + + REG_MIPI_DSI_DPICLK_SRC_SEL + Reserved + 5 + 2 + read-write + + + REG_MIPI_DSI_DPICLK_EN + Reserved + 7 + 1 + read-write + + + REG_MIPI_DSI_DPICLK_DIV_NUM + Reserved + 8 + 8 + read-write + + + + + PERI_CLK_CTRL10 + Reserved + 0x40 + 0x20 + + + REG_I2C0_CLK_SRC_SEL + Reserved + 0 + 1 + read-write + + + REG_I2C0_CLK_EN + Reserved + 1 + 1 + read-write + + + REG_I2C0_CLK_DIV_NUM + Reserved + 2 + 8 + read-write + + + REG_I2C0_CLK_DIV_NUMERATOR + Reserved + 10 + 8 + read-write + + + REG_I2C0_CLK_DIV_DENOMINATOR + Reserved + 18 + 8 + read-write + + + REG_I2C1_CLK_SRC_SEL + Reserved + 26 + 1 + read-write + + + REG_I2C1_CLK_EN + Reserved + 27 + 1 + read-write + + + + + PERI_CLK_CTRL11 + Reserved + 0x44 + 0x20 + + + REG_I2C1_CLK_DIV_NUM + Reserved + 0 + 8 + read-write + + + REG_I2C1_CLK_DIV_NUMERATOR + Reserved + 8 + 8 + read-write + + + REG_I2C1_CLK_DIV_DENOMINATOR + Reserved + 16 + 8 + read-write + + + REG_I2S0_RX_CLK_EN + Reserved + 24 + 1 + read-write + + + REG_I2S0_RX_CLK_SRC_SEL + Reserved + 25 + 2 + read-write + + + + + PERI_CLK_CTRL12 + Reserved + 0x48 + 0x20 + + + REG_I2S0_RX_DIV_N + Reserved + 0 + 8 + read-write + + + REG_I2S0_RX_DIV_X + Reserved + 8 + 9 + read-write + + + REG_I2S0_RX_DIV_Y + Reserved + 17 + 9 + read-write + + + + + PERI_CLK_CTRL13 + Reserved + 0x4C + 0x20 + + + REG_I2S0_RX_DIV_Z + Reserved + 0 + 9 + read-write + + + REG_I2S0_RX_DIV_YN1 + Reserved + 9 + 1 + read-write + + + REG_I2S0_TX_CLK_EN + Reserved + 10 + 1 + read-write + + + REG_I2S0_TX_CLK_SRC_SEL + Reserved + 11 + 2 + read-write + + + REG_I2S0_TX_DIV_N + Reserved + 13 + 8 + read-write + + + REG_I2S0_TX_DIV_X + Reserved + 21 + 9 + read-write + + + + + PERI_CLK_CTRL14 + Reserved + 0x50 + 0x20 + + + REG_I2S0_TX_DIV_Y + Reserved + 0 + 9 + read-write + + + REG_I2S0_TX_DIV_Z + Reserved + 9 + 9 + read-write + + + REG_I2S0_TX_DIV_YN1 + Reserved + 18 + 1 + read-write + + + REG_I2S0_MST_CLK_SEL + Reserved + 19 + 1 + read-write + + + REG_I2S1_RX_CLK_EN + Reserved + 20 + 1 + read-write + + + REG_I2S1_RX_CLK_SRC_SEL + Reserved + 21 + 2 + read-write + + + REG_I2S1_RX_DIV_N + Reserved + 23 + 8 + read-write + + + + + PERI_CLK_CTRL15 + Reserved + 0x54 + 0x20 + + + REG_I2S1_RX_DIV_X + Reserved + 0 + 9 + read-write + + + REG_I2S1_RX_DIV_Y + Reserved + 9 + 9 + read-write + + + REG_I2S1_RX_DIV_Z + Reserved + 18 + 9 + read-write + + + REG_I2S1_RX_DIV_YN1 + Reserved + 27 + 1 + read-write + + + REG_I2S1_TX_CLK_EN + Reserved + 28 + 1 + read-write + + + REG_I2S1_TX_CLK_SRC_SEL + Reserved + 29 + 2 + read-write + + + + + PERI_CLK_CTRL16 + Reserved + 0x58 + 0x20 + + + REG_I2S1_TX_DIV_N + Reserved + 0 + 8 + read-write + + + REG_I2S1_TX_DIV_X + Reserved + 8 + 9 + read-write + + + REG_I2S1_TX_DIV_Y + Reserved + 17 + 9 + read-write + + + + + PERI_CLK_CTRL17 + Reserved + 0x5C + 0x20 + + + REG_I2S1_TX_DIV_Z + Reserved + 0 + 9 + read-write + + + REG_I2S1_TX_DIV_YN1 + Reserved + 9 + 1 + read-write + + + REG_I2S1_MST_CLK_SEL + Reserved + 10 + 1 + read-write + + + REG_I2S2_RX_CLK_EN + Reserved + 11 + 1 + read-write + + + REG_I2S2_RX_CLK_SRC_SEL + Reserved + 12 + 2 + read-write + + + REG_I2S2_RX_DIV_N + Reserved + 14 + 8 + read-write + + + REG_I2S2_RX_DIV_X + Reserved + 22 + 9 + read-write + + + + + PERI_CLK_CTRL18 + Reserved + 0x60 + 0x20 + + + REG_I2S2_RX_DIV_Y + Reserved + 0 + 9 + read-write + + + REG_I2S2_RX_DIV_Z + Reserved + 9 + 9 + read-write + + + REG_I2S2_RX_DIV_YN1 + Reserved + 18 + 1 + read-write + + + REG_I2S2_TX_CLK_EN + Reserved + 19 + 1 + read-write + + + REG_I2S2_TX_CLK_SRC_SEL + Reserved + 20 + 2 + read-write + + + REG_I2S2_TX_DIV_N + Reserved + 22 + 8 + read-write + + + + + PERI_CLK_CTRL19 + Reserved + 0x64 + 0x20 + + + REG_I2S2_TX_DIV_X + Reserved + 0 + 9 + read-write + + + REG_I2S2_TX_DIV_Y + Reserved + 9 + 9 + read-write + + + REG_I2S2_TX_DIV_Z + Reserved + 18 + 9 + read-write + + + REG_I2S2_TX_DIV_YN1 + Reserved + 27 + 1 + read-write + + + REG_I2S2_MST_CLK_SEL + Reserved + 28 + 1 + read-write + + + REG_LCD_CLK_SRC_SEL + Reserved + 29 + 2 + read-write + + + REG_LCD_CLK_EN + Reserved + 31 + 1 + read-write + + + + + PERI_CLK_CTRL110 + Reserved + 0x68 + 0x20 + 0x04000000 + + + REG_LCD_CLK_DIV_NUM + Reserved + 0 + 8 + read-write + + + REG_LCD_CLK_DIV_NUMERATOR + Reserved + 8 + 8 + read-write + + + REG_LCD_CLK_DIV_DENOMINATOR + Reserved + 16 + 8 + read-write + + + REG_UART0_CLK_SRC_SEL + Reserved + 24 + 2 + read-write + + + REG_UART0_CLK_EN + Reserved + 26 + 1 + read-write + + + + + PERI_CLK_CTRL111 + Reserved + 0x6C + 0x20 + 0x04000000 + + + REG_UART0_SCLK_DIV_NUM + Reserved + 0 + 8 + read-write + + + REG_UART0_SCLK_DIV_NUMERATOR + Reserved + 8 + 8 + read-write + + + REG_UART0_SCLK_DIV_DENOMINATOR + Reserved + 16 + 8 + read-write + + + REG_UART1_CLK_SRC_SEL + Reserved + 24 + 2 + read-write + + + REG_UART1_CLK_EN + Reserved + 26 + 1 + read-write + + + + + PERI_CLK_CTRL112 + Reserved + 0x70 + 0x20 + 0x04000000 + + + REG_UART1_SCLK_DIV_NUM + Reserved + 0 + 8 + read-write + + + REG_UART1_SCLK_DIV_NUMERATOR + Reserved + 8 + 8 + read-write + + + REG_UART1_SCLK_DIV_DENOMINATOR + Reserved + 16 + 8 + read-write + + + REG_UART2_CLK_SRC_SEL + Reserved + 24 + 2 + read-write + + + REG_UART2_CLK_EN + Reserved + 26 + 1 + read-write + + + + + PERI_CLK_CTRL113 + Reserved + 0x74 + 0x20 + 0x04000000 + + + REG_UART2_SCLK_DIV_NUM + Reserved + 0 + 8 + read-write + + + REG_UART2_SCLK_DIV_NUMERATOR + Reserved + 8 + 8 + read-write + + + REG_UART2_SCLK_DIV_DENOMINATOR + Reserved + 16 + 8 + read-write + + + REG_UART3_CLK_SRC_SEL + Reserved + 24 + 2 + read-write + + + REG_UART3_CLK_EN + Reserved + 26 + 1 + read-write + + + + + PERI_CLK_CTRL114 + Reserved + 0x78 + 0x20 + 0x04000000 + + + REG_UART3_SCLK_DIV_NUM + Reserved + 0 + 8 + read-write + + + REG_UART3_SCLK_DIV_NUMERATOR + Reserved + 8 + 8 + read-write + + + REG_UART3_SCLK_DIV_DENOMINATOR + Reserved + 16 + 8 + read-write + + + REG_UART4_CLK_SRC_SEL + Reserved + 24 + 2 + read-write + + + REG_UART4_CLK_EN + Reserved + 26 + 1 + read-write + + + + + PERI_CLK_CTRL115 + Reserved + 0x7C + 0x20 + + + REG_UART4_SCLK_DIV_NUM + Reserved + 0 + 8 + read-write + + + REG_UART4_SCLK_DIV_NUMERATOR + Reserved + 8 + 8 + read-write + + + REG_UART4_SCLK_DIV_DENOMINATOR + Reserved + 16 + 8 + read-write + + + REG_TWAI0_CLK_SRC_SEL + Reserved + 24 + 1 + read-write + + + REG_TWAI0_CLK_EN + Reserved + 25 + 1 + read-write + + + REG_TWAI1_CLK_SRC_SEL + Reserved + 26 + 1 + read-write + + + REG_TWAI1_CLK_EN + Reserved + 27 + 1 + read-write + + + REG_TWAI2_CLK_SRC_SEL + Reserved + 28 + 1 + read-write + + + REG_TWAI2_CLK_EN + Reserved + 29 + 1 + read-write + + + + + PERI_CLK_CTRL116 + Reserved + 0x80 + 0x20 + 0x01100008 + + + REG_GPSPI2_CLK_SRC_SEL + Reserved + 0 + 3 + read-write + + + REG_GPSPI2_HS_CLK_EN + Reserved + 3 + 1 + read-write + + + REG_GPSPI2_HS_CLK_DIV_NUM + Reserved + 4 + 8 + read-write + + + REG_GPSPI2_MST_CLK_DIV_NUM + Reserved + 12 + 8 + read-write + + + REG_GPSPI2_MST_CLK_EN + Reserved + 20 + 1 + read-write + + + REG_GPSPI3_CLK_SRC_SEL + Reserved + 21 + 3 + read-write + + + REG_GPSPI3_HS_CLK_EN + Reserved + 24 + 1 + read-write + + + + + PERI_CLK_CTRL117 + Reserved + 0x84 + 0x20 + 0x00010000 + + + REG_GPSPI3_HS_CLK_DIV_NUM + Reserved + 0 + 8 + read-write + + + REG_GPSPI3_MST_CLK_DIV_NUM + Reserved + 8 + 8 + read-write + + + REG_GPSPI3_MST_CLK_EN + Reserved + 16 + 1 + read-write + + + REG_PARLIO_RX_CLK_SRC_SEL + Reserved + 17 + 2 + read-write + + + REG_PARLIO_RX_CLK_EN + Reserved + 19 + 1 + read-write + + + REG_PARLIO_RX_CLK_DIV_NUM + Reserved + 20 + 8 + read-write + + + + + PERI_CLK_CTRL118 + Reserved + 0x88 + 0x20 + + + REG_PARLIO_RX_CLK_DIV_NUMERATOR + Reserved + 0 + 8 + read-write + + + REG_PARLIO_RX_CLK_DIV_DENOMINATOR + Reserved + 8 + 8 + read-write + + + REG_PARLIO_TX_CLK_SRC_SEL + Reserved + 16 + 2 + read-write + + + REG_PARLIO_TX_CLK_EN + Reserved + 18 + 1 + read-write + + + REG_PARLIO_TX_CLK_DIV_NUM + Reserved + 19 + 8 + read-write + + + + + PERI_CLK_CTRL119 + Reserved + 0x8C + 0x20 + + + REG_PARLIO_TX_CLK_DIV_NUMERATOR + Reserved + 0 + 8 + read-write + + + REG_PARLIO_TX_CLK_DIV_DENOMINATOR + Reserved + 8 + 8 + read-write + + + REG_I3C_MST_CLK_SRC_SEL + Reserved + 16 + 2 + read-write + + + REG_I3C_MST_CLK_EN + Reserved + 18 + 1 + read-write + + + REG_I3C_MST_CLK_DIV_NUM + Reserved + 19 + 8 + read-write + + + REG_CAM_CLK_SRC_SEL + Reserved + 27 + 2 + read-write + + + REG_CAM_CLK_EN + Reserved + 29 + 1 + read-write + + + + + PERI_CLK_CTRL120 + Reserved + 0x90 + 0x20 + + + REG_CAM_CLK_DIV_NUM + Reserved + 0 + 8 + read-write + + + REG_CAM_CLK_DIV_NUMERATOR + Reserved + 8 + 8 + read-write + + + REG_CAM_CLK_DIV_DENOMINATOR + Reserved + 16 + 8 + read-write + + + + + PERI_CLK_CTRL20 + Reserved + 0x94 + 0x20 + 0xC9000000 + + + REG_MCPWM0_CLK_SRC_SEL + Reserved + 0 + 2 + read-write + + + REG_MCPWM0_CLK_EN + Reserved + 2 + 1 + read-write + + + REG_MCPWM0_CLK_DIV_NUM + Reserved + 3 + 8 + read-write + + + REG_MCPWM1_CLK_SRC_SEL + Reserved + 11 + 2 + read-write + + + REG_MCPWM1_CLK_EN + Reserved + 13 + 1 + read-write + + + REG_MCPWM1_CLK_DIV_NUM + Reserved + 14 + 8 + read-write + + + REG_TIMERGRP0_T0_SRC_SEL + Reserved + 22 + 2 + read-write + + + REG_TIMERGRP0_T0_CLK_EN + Reserved + 24 + 1 + read-write + + + REG_TIMERGRP0_T1_SRC_SEL + Reserved + 25 + 2 + read-write + + + REG_TIMERGRP0_T1_CLK_EN + Reserved + 27 + 1 + read-write + + + REG_TIMERGRP0_WDT_SRC_SEL + Reserved + 28 + 2 + read-write + + + REG_TIMERGRP0_WDT_CLK_EN + Reserved + 30 + 1 + read-write + + + REG_TIMERGRP0_TGRT_CLK_EN + Reserved + 31 + 1 + read-write + + + + + PERI_CLK_CTRL21 + Reserved + 0x98 + 0x20 + 0x52400000 + + + REG_TIMERGRP0_TGRT_CLK_SRC_SEL + Reserved + 0 + 4 + read-write + + + REG_TIMERGRP0_TGRT_CLK_DIV_NUM + Reserved + 4 + 16 + read-write + + + REG_TIMERGRP1_T0_SRC_SEL + Reserved + 20 + 2 + read-write + + + REG_TIMERGRP1_T0_CLK_EN + Reserved + 22 + 1 + read-write + + + REG_TIMERGRP1_T1_SRC_SEL + Reserved + 23 + 2 + read-write + + + REG_TIMERGRP1_T1_CLK_EN + Reserved + 25 + 1 + read-write + + + REG_TIMERGRP1_WDT_SRC_SEL + Reserved + 26 + 2 + read-write + + + REG_TIMERGRP1_WDT_CLK_EN + Reserved + 28 + 1 + read-write + + + REG_SYSTIMER_CLK_SRC_SEL + Reserved + 29 + 1 + read-write + + + REG_SYSTIMER_CLK_EN + Reserved + 30 + 1 + read-write + + + + + PERI_CLK_CTRL22 + Reserved + 0x9C + 0x20 + + + REG_LEDC_CLK_SRC_SEL + Reserved + 0 + 2 + read-write + + + REG_LEDC_CLK_EN + Reserved + 2 + 1 + read-write + + + REG_RMT_CLK_SRC_SEL + Reserved + 3 + 2 + read-write + + + REG_RMT_CLK_EN + Reserved + 5 + 1 + read-write + + + REG_RMT_CLK_DIV_NUM + Reserved + 6 + 8 + read-write + + + REG_RMT_CLK_DIV_NUMERATOR + Reserved + 14 + 8 + read-write + + + REG_RMT_CLK_DIV_DENOMINATOR + Reserved + 22 + 8 + read-write + + + REG_ADC_CLK_SRC_SEL + Reserved + 30 + 2 + read-write + + + + + PERI_CLK_CTRL23 + Reserved + 0xA0 + 0x20 + 0x00000008 + + + REG_ADC_CLK_EN + Reserved + 0 + 1 + read-write + + + REG_ADC_CLK_DIV_NUM + Reserved + 1 + 8 + read-write + + + REG_ADC_CLK_DIV_NUMERATOR + Reserved + 9 + 8 + read-write + + + REG_ADC_CLK_DIV_DENOMINATOR + Reserved + 17 + 8 + read-write + + + + + PERI_CLK_CTRL24 + Reserved + 0xA4 + 0x20 + 0x00000404 + + + REG_ADC_SAR1_CLK_DIV_NUM + Reserved + 0 + 8 + read-write + + + REG_ADC_SAR2_CLK_DIV_NUM + Reserved + 8 + 8 + read-write + + + REG_PVT_CLK_DIV_NUM + Reserved + 16 + 8 + read-write + + + REG_PVT_CLK_EN + Reserved + 24 + 1 + read-write + + + + + PERI_CLK_CTRL25 + Reserved + 0xA8 + 0x20 + 0x007FC000 + + + REG_PVT_PERI_GROUP_CLK_DIV_NUM + Reserved + 0 + 8 + read-write + + + REG_PVT_PERI_GROUP1_CLK_EN + Reserved + 8 + 1 + read-write + + + REG_PVT_PERI_GROUP2_CLK_EN + Reserved + 9 + 1 + read-write + + + REG_PVT_PERI_GROUP3_CLK_EN + Reserved + 10 + 1 + read-write + + + REG_PVT_PERI_GROUP4_CLK_EN + Reserved + 11 + 1 + read-write + + + REG_CRYPTO_CLK_SRC_SEL + Reserved + 12 + 2 + read-write + + + REG_CRYPTO_AES_CLK_EN + Reserved + 14 + 1 + read-write + + + REG_CRYPTO_DS_CLK_EN + Reserved + 15 + 1 + read-write + + + REG_CRYPTO_ECC_CLK_EN + Reserved + 16 + 1 + read-write + + + REG_CRYPTO_HMAC_CLK_EN + Reserved + 17 + 1 + read-write + + + REG_CRYPTO_RSA_CLK_EN + Reserved + 18 + 1 + read-write + + + REG_CRYPTO_SEC_CLK_EN + Reserved + 19 + 1 + read-write + + + REG_CRYPTO_SHA_CLK_EN + Reserved + 20 + 1 + read-write + + + REG_CRYPTO_ECDSA_CLK_EN + Reserved + 21 + 1 + read-write + + + REG_CRYPTO_KM_CLK_EN + Reserved + 22 + 1 + read-write + + + REG_ISP_CLK_SRC_SEL + Reserved + 23 + 2 + read-write + + + REG_ISP_CLK_EN + Reserved + 25 + 1 + read-write + + + + + PERI_CLK_CTRL26 + Reserved + 0xAC + 0x20 + 0x00000200 + + + REG_ISP_CLK_DIV_NUM + Reserved + 0 + 8 + read-write + + + REG_IOMUX_CLK_SRC_SEL + Reserved + 8 + 1 + read-write + + + REG_IOMUX_CLK_EN + Reserved + 9 + 1 + read-write + + + REG_IOMUX_CLK_DIV_NUM + Reserved + 10 + 8 + read-write + + + REG_H264_CLK_SRC_SEL + Reserved + 18 + 1 + read-write + + + REG_H264_CLK_EN + Reserved + 19 + 1 + read-write + + + REG_H264_CLK_DIV_NUM + Reserved + 20 + 8 + read-write + + + REG_PADBIST_RX_CLK_SRC_SEL + Reserved + 28 + 1 + read-write + + + REG_PADBIST_RX_CLK_EN + Reserved + 29 + 1 + read-write + + + + + PERI_CLK_CTRL27 + Reserved + 0xB0 + 0x20 + + + REG_PADBIST_RX_CLK_DIV_NUM + Reserved + 0 + 8 + read-write + + + REG_PADBIST_TX_CLK_SRC_SEL + Reserved + 8 + 1 + read-write + + + REG_PADBIST_TX_CLK_EN + Reserved + 9 + 1 + read-write + + + REG_PADBIST_TX_CLK_DIV_NUM + Reserved + 10 + 8 + read-write + + + + + CLK_FORCE_ON_CTRL0 + Reserved + 0xB4 + 0x20 + 0x0003FFFF + + + REG_CPUICM_GATED_CLK_FORCE_ON + Reserved + 0 + 1 + read-write + + + REG_TCM_CPU_CLK_FORCE_ON + Reserved + 1 + 1 + read-write + + + REG_BUSMON_CPU_CLK_FORCE_ON + Reserved + 2 + 1 + read-write + + + REG_L1CACHE_CPU_CLK_FORCE_ON + Reserved + 3 + 1 + read-write + + + REG_L1CACHE_D_CPU_CLK_FORCE_ON + Reserved + 4 + 1 + read-write + + + REG_L1CACHE_I0_CPU_CLK_FORCE_ON + Reserved + 5 + 1 + read-write + + + REG_L1CACHE_I1_CPU_CLK_FORCE_ON + Reserved + 6 + 1 + read-write + + + REG_TRACE_CPU_CLK_FORCE_ON + Reserved + 7 + 1 + read-write + + + REG_TRACE_SYS_CLK_FORCE_ON + Reserved + 8 + 1 + read-write + + + REG_L1CACHE_MEM_CLK_FORCE_ON + Reserved + 9 + 1 + read-write + + + REG_L1CACHE_D_MEM_CLK_FORCE_ON + Reserved + 10 + 1 + read-write + + + REG_L1CACHE_I0_MEM_CLK_FORCE_ON + Reserved + 11 + 1 + read-write + + + REG_L1CACHE_I1_MEM_CLK_FORCE_ON + Reserved + 12 + 1 + read-write + + + REG_L2CACHE_MEM_CLK_FORCE_ON + Reserved + 13 + 1 + read-write + + + REG_L2MEM_MEM_CLK_FORCE_ON + Reserved + 14 + 1 + read-write + + + REG_SAR1_CLK_FORCE_ON + Reserved + 15 + 1 + read-write + + + REG_SAR2_CLK_FORCE_ON + Reserved + 16 + 1 + read-write + + + REG_GMAC_TX_CLK_FORCE_ON + Reserved + 17 + 1 + read-write + + + + + DPA_CTRL0 + Reserved + 0xB8 + 0x20 + + + REG_SEC_DPA_LEVEL + Reserved + 0 + 2 + read-write + + + REG_SEC_DPA_CFG_SEL + Reserved + 2 + 1 + read-write + + + + + ANA_PLL_CTRL0 + Reserved + 0xBC + 0x20 + + + REG_PLLA_CAL_END + Reserved + 0 + 1 + read-only + + + REG_PLLA_CAL_STOP + Reserved + 1 + 1 + read-write + + + REG_CPU_PLL_CAL_END + Reserved + 2 + 1 + read-only + + + REG_CPU_PLL_CAL_STOP + Reserved + 3 + 1 + read-write + + + REG_SDIO_PLL_CAL_END + Reserved + 4 + 1 + read-only + + + REG_SDIO_PLL_CAL_STOP + Reserved + 5 + 1 + read-write + + + REG_SYS_PLL_CAL_END + Reserved + 6 + 1 + read-only + + + REG_SYS_PLL_CAL_STOP + Reserved + 7 + 1 + read-write + + + REG_MSPI_CAL_END + Reserved + 8 + 1 + read-only + + + REG_MSPI_CAL_STOP + Reserved + 9 + 1 + read-write + + + + + HP_RST_EN0 + Reserved + 0xC0 + 0x20 + 0x00000100 + + + REG_RST_EN_CORECTRL + Reserved + 0 + 1 + read-write + + + REG_RST_EN_PVT_TOP + Reserved + 1 + 1 + read-write + + + REG_RST_EN_PVT_PERI_GROUP1 + Reserved + 2 + 1 + read-write + + + REG_RST_EN_PVT_PERI_GROUP2 + Reserved + 3 + 1 + read-write + + + REG_RST_EN_PVT_PERI_GROUP3 + Reserved + 4 + 1 + read-write + + + REG_RST_EN_PVT_PERI_GROUP4 + Reserved + 5 + 1 + read-write + + + REG_RST_EN_REGDMA + Reserved + 6 + 1 + read-write + + + REG_RST_EN_CORE0_GLOBAL + Reserved + 7 + 1 + read-write + + + REG_RST_EN_CORE1_GLOBAL + Reserved + 8 + 1 + read-write + + + REG_RST_EN_CORETRACE0 + Reserved + 9 + 1 + read-write + + + REG_RST_EN_CORETRACE1 + Reserved + 10 + 1 + read-write + + + REG_RST_EN_HP_TCM + Reserved + 11 + 1 + read-write + + + REG_RST_EN_HP_CACHE + Reserved + 12 + 1 + read-write + + + REG_RST_EN_L1_I0_CACHE + Reserved + 13 + 1 + read-write + + + REG_RST_EN_L1_I1_CACHE + Reserved + 14 + 1 + read-write + + + REG_RST_EN_L1_D_CACHE + Reserved + 15 + 1 + read-write + + + REG_RST_EN_L2_CACHE + Reserved + 16 + 1 + read-write + + + REG_RST_EN_L2_MEM + Reserved + 17 + 1 + read-write + + + REG_RST_EN_L2MEMMON + Reserved + 18 + 1 + read-write + + + REG_RST_EN_TCMMON + Reserved + 19 + 1 + read-write + + + REG_RST_EN_PVT_APB + Reserved + 20 + 1 + read-write + + + REG_RST_EN_GDMA + Reserved + 21 + 1 + read-write + + + REG_RST_EN_MSPI_AXI + Reserved + 22 + 1 + read-write + + + REG_RST_EN_DUAL_MSPI_AXI + Reserved + 23 + 1 + read-write + + + REG_RST_EN_MSPI_APB + Reserved + 24 + 1 + read-write + + + REG_RST_EN_DUAL_MSPI_APB + Reserved + 25 + 1 + read-write + + + REG_RST_EN_DSI_BRG + Reserved + 26 + 1 + read-write + + + REG_RST_EN_CSI_HOST + Reserved + 27 + 1 + read-write + + + REG_RST_EN_CSI_BRG + Reserved + 28 + 1 + read-write + + + REG_RST_EN_ISP + Reserved + 29 + 1 + read-write + + + REG_RST_EN_JPEG + Reserved + 30 + 1 + read-write + + + REG_RST_EN_DMA2D + Reserved + 31 + 1 + read-write + + + + + HP_RST_EN1 + Reserved + 0xC4 + 0x20 + + + REG_RST_EN_PPA + Reserved + 0 + 1 + read-write + + + REG_RST_EN_AHB_PDMA + Reserved + 1 + 1 + read-write + + + REG_RST_EN_AXI_PDMA + Reserved + 2 + 1 + read-write + + + REG_RST_EN_IOMUX + Reserved + 3 + 1 + read-write + + + REG_RST_EN_PADBIST + Reserved + 4 + 1 + read-write + + + REG_RST_EN_STIMER + Reserved + 5 + 1 + read-write + + + REG_RST_EN_TIMERGRP0 + Reserved + 6 + 1 + read-write + + + REG_RST_EN_TIMERGRP1 + Reserved + 7 + 1 + read-write + + + REG_RST_EN_UART0_CORE + Reserved + 8 + 1 + read-write + + + REG_RST_EN_UART1_CORE + Reserved + 9 + 1 + read-write + + + REG_RST_EN_UART2_CORE + Reserved + 10 + 1 + read-write + + + REG_RST_EN_UART3_CORE + Reserved + 11 + 1 + read-write + + + REG_RST_EN_UART4_CORE + Reserved + 12 + 1 + read-write + + + REG_RST_EN_UART0_APB + Reserved + 13 + 1 + read-write + + + REG_RST_EN_UART1_APB + Reserved + 14 + 1 + read-write + + + REG_RST_EN_UART2_APB + Reserved + 15 + 1 + read-write + + + REG_RST_EN_UART3_APB + Reserved + 16 + 1 + read-write + + + REG_RST_EN_UART4_APB + Reserved + 17 + 1 + read-write + + + REG_RST_EN_UHCI + Reserved + 18 + 1 + read-write + + + REG_RST_EN_I3CMST + Reserved + 19 + 1 + read-write + + + REG_RST_EN_I3CSLV + Reserved + 20 + 1 + read-write + + + REG_RST_EN_I2C1 + Reserved + 21 + 1 + read-write + + + REG_RST_EN_I2C0 + Reserved + 22 + 1 + read-write + + + REG_RST_EN_RMT + Reserved + 23 + 1 + read-write + + + REG_RST_EN_PWM0 + Reserved + 24 + 1 + read-write + + + REG_RST_EN_PWM1 + Reserved + 25 + 1 + read-write + + + REG_RST_EN_CAN0 + Reserved + 26 + 1 + read-write + + + REG_RST_EN_CAN1 + Reserved + 27 + 1 + read-write + + + REG_RST_EN_CAN2 + Reserved + 28 + 1 + read-write + + + REG_RST_EN_LEDC + Reserved + 29 + 1 + read-write + + + REG_RST_EN_PCNT + Reserved + 30 + 1 + read-write + + + REG_RST_EN_ETM + Reserved + 31 + 1 + read-write + + + + + HP_RST_EN2 + Reserved + 0xC8 + 0x20 + + + REG_RST_EN_INTRMTX + Reserved + 0 + 1 + read-write + + + REG_RST_EN_PARLIO + Reserved + 1 + 1 + read-write + + + REG_RST_EN_PARLIO_RX + Reserved + 2 + 1 + read-write + + + REG_RST_EN_PARLIO_TX + Reserved + 3 + 1 + read-write + + + REG_RST_EN_I2S0_APB + Reserved + 4 + 1 + read-write + + + REG_RST_EN_I2S1_APB + Reserved + 5 + 1 + read-write + + + REG_RST_EN_I2S2_APB + Reserved + 6 + 1 + read-write + + + REG_RST_EN_SPI2 + Reserved + 7 + 1 + read-write + + + REG_RST_EN_SPI3 + Reserved + 8 + 1 + read-write + + + REG_RST_EN_LCDCAM + Reserved + 9 + 1 + read-write + + + REG_RST_EN_ADC + Reserved + 10 + 1 + read-write + + + REG_RST_EN_BITSRAMBLER + Reserved + 11 + 1 + read-write + + + REG_RST_EN_BITSRAMBLER_RX + Reserved + 12 + 1 + read-write + + + REG_RST_EN_BITSRAMBLER_TX + Reserved + 13 + 1 + read-write + + + REG_RST_EN_CRYPTO + Reserved + 14 + 1 + read-write + + + REG_RST_EN_SEC + Reserved + 15 + 1 + read-write + + + REG_RST_EN_AES + Reserved + 16 + 1 + read-write + + + REG_RST_EN_DS + Reserved + 17 + 1 + read-write + + + REG_RST_EN_SHA + Reserved + 18 + 1 + read-write + + + REG_RST_EN_HMAC + Reserved + 19 + 1 + read-write + + + REG_RST_EN_ECDSA + Reserved + 20 + 1 + read-write + + + REG_RST_EN_RSA + Reserved + 21 + 1 + read-write + + + REG_RST_EN_ECC + Reserved + 22 + 1 + read-write + + + REG_RST_EN_KM + Reserved + 23 + 1 + read-write + + + REG_RST_EN_H264 + Reserved + 24 + 1 + read-write + + + + + HP_FORCE_NORST0 + Reserved + 0xCC + 0x20 + + + REG_FORCE_NORST_CORE0 + Reserved + 0 + 1 + read-write + + + REG_FORCE_NORST_CORE1 + Reserved + 1 + 1 + read-write + + + REG_FORCE_NORST_CORETRACE0 + Reserved + 2 + 1 + read-write + + + REG_FORCE_NORST_CORETRACE1 + Reserved + 3 + 1 + read-write + + + REG_FORCE_NORST_L2MEMMON + Reserved + 4 + 1 + read-write + + + REG_FORCE_NORST_TCMMON + Reserved + 5 + 1 + read-write + + + REG_FORCE_NORST_GDMA + Reserved + 6 + 1 + read-write + + + REG_FORCE_NORST_MSPI_AXI + Reserved + 7 + 1 + read-write + + + REG_FORCE_NORST_DUAL_MSPI_AXI + Reserved + 8 + 1 + read-write + + + REG_FORCE_NORST_MSPI_APB + Reserved + 9 + 1 + read-write + + + REG_FORCE_NORST_DUAL_MSPI_APB + Reserved + 10 + 1 + read-write + + + REG_FORCE_NORST_DSI_BRG + Reserved + 11 + 1 + read-write + + + REG_FORCE_NORST_CSI_HOST + Reserved + 12 + 1 + read-write + + + REG_FORCE_NORST_CSI_BRG + Reserved + 13 + 1 + read-write + + + REG_FORCE_NORST_ISP + Reserved + 14 + 1 + read-write + + + REG_FORCE_NORST_JPEG + Reserved + 15 + 1 + read-write + + + REG_FORCE_NORST_DMA2D + Reserved + 16 + 1 + read-write + + + REG_FORCE_NORST_PPA + Reserved + 17 + 1 + read-write + + + REG_FORCE_NORST_AHB_PDMA + Reserved + 18 + 1 + read-write + + + REG_FORCE_NORST_AXI_PDMA + Reserved + 19 + 1 + read-write + + + REG_FORCE_NORST_IOMUX + Reserved + 20 + 1 + read-write + + + REG_FORCE_NORST_PADBIST + Reserved + 21 + 1 + read-write + + + REG_FORCE_NORST_STIMER + Reserved + 22 + 1 + read-write + + + REG_FORCE_NORST_TIMERGRP0 + Reserved + 23 + 1 + read-write + + + REG_FORCE_NORST_TIMERGRP1 + Reserved + 24 + 1 + read-write + + + REG_FORCE_NORST_UART0 + Reserved + 25 + 1 + read-write + + + REG_FORCE_NORST_UART1 + Reserved + 26 + 1 + read-write + + + REG_FORCE_NORST_UART2 + Reserved + 27 + 1 + read-write + + + REG_FORCE_NORST_UART3 + Reserved + 28 + 1 + read-write + + + REG_FORCE_NORST_UART4 + Reserved + 29 + 1 + read-write + + + REG_FORCE_NORST_UHCI + Reserved + 30 + 1 + read-write + + + REG_FORCE_NORST_I3CMST + Reserved + 31 + 1 + read-write + + + + + HP_FORCE_NORST1 + Reserved + 0xD0 + 0x20 + + + REG_FORCE_NORST_I3CSLV + Reserved + 0 + 1 + read-write + + + REG_FORCE_NORST_I2C1 + Reserved + 1 + 1 + read-write + + + REG_FORCE_NORST_I2C0 + Reserved + 2 + 1 + read-write + + + REG_FORCE_NORST_RMT + Reserved + 3 + 1 + read-write + + + REG_FORCE_NORST_PWM0 + Reserved + 4 + 1 + read-write + + + REG_FORCE_NORST_PWM1 + Reserved + 5 + 1 + read-write + + + REG_FORCE_NORST_CAN0 + Reserved + 6 + 1 + read-write + + + REG_FORCE_NORST_CAN1 + Reserved + 7 + 1 + read-write + + + REG_FORCE_NORST_CAN2 + Reserved + 8 + 1 + read-write + + + REG_FORCE_NORST_LEDC + Reserved + 9 + 1 + read-write + + + REG_FORCE_NORST_PCNT + Reserved + 10 + 1 + read-write + + + REG_FORCE_NORST_ETM + Reserved + 11 + 1 + read-write + + + REG_FORCE_NORST_INTRMTX + Reserved + 12 + 1 + read-write + + + REG_FORCE_NORST_PARLIO + Reserved + 13 + 1 + read-write + + + REG_FORCE_NORST_PARLIO_RX + Reserved + 14 + 1 + read-write + + + REG_FORCE_NORST_PARLIO_TX + Reserved + 15 + 1 + read-write + + + REG_FORCE_NORST_I2S0 + Reserved + 16 + 1 + read-write + + + REG_FORCE_NORST_I2S1 + Reserved + 17 + 1 + read-write + + + REG_FORCE_NORST_I2S2 + Reserved + 18 + 1 + read-write + + + REG_FORCE_NORST_SPI2 + Reserved + 19 + 1 + read-write + + + REG_FORCE_NORST_SPI3 + Reserved + 20 + 1 + read-write + + + REG_FORCE_NORST_LCDCAM + Reserved + 21 + 1 + read-write + + + REG_FORCE_NORST_ADC + Reserved + 22 + 1 + read-write + + + REG_FORCE_NORST_BITSRAMBLER + Reserved + 23 + 1 + read-write + + + REG_FORCE_NORST_BITSRAMBLER_RX + Reserved + 24 + 1 + read-write + + + REG_FORCE_NORST_BITSRAMBLER_TX + Reserved + 25 + 1 + read-write + + + REG_FORCE_NORST_H264 + Reserved + 26 + 1 + read-write + + + + + HPWDT_CORE0_RST_CTRL0 + Reserved + 0xD4 + 0x20 + 0x00001011 + + + REG_HPCORE0_STALL_EN + Reserved + 0 + 1 + read-write + + + REG_HPCORE0_STALL_WAIT_NUM + Reserved + 1 + 8 + read-write + + + REG_WDT_HPCORE0_RST_LEN + Reserved + 9 + 8 + read-write + + + + + HPWDT_CORE1_RST_CTRL0 + Reserved + 0xD8 + 0x20 + 0x00001011 + + + REG_HPCORE1_STALL_EN + Reserved + 0 + 1 + read-write + + + REG_HPCORE1_STALL_WAIT_NUM + Reserved + 1 + 8 + read-write + + + REG_WDT_HPCORE1_RST_LEN + Reserved + 9 + 8 + read-write + + + + + CPU_SRC_FREQ0 + CPU Source Frequency + 0xDC + 0x20 + + + REG_CPU_SRC_FREQ + cpu source clock frequency, step by 0.25MHz + 0 + 32 + read-only + + + + + CPU_CLK_STATUS0 + CPU Clock Status + 0xE0 + 0x20 + + + REG_ASIC_OR_FPGA + 0: ASIC mode, 1: FPGA mode + 0 + 1 + read-only + + + REG_CPU_DIV_EFFECT + 0: Divider bypass, 1: Divider takes effect + 1 + 1 + read-only + + + REG_CPU_SRC_IS_CPLL + 0: CPU source isn't cpll_400m, 1: CPU Source is cll_400m + 2 + 1 + read-only + + + REG_CPU_DIV_NUM_CUR + cpu current div number + 3 + 8 + read-only + + + REG_CPU_DIV_NUMERATOR_CUR + cpu current div numerator + 11 + 8 + read-only + + + REG_CPU_DIV_DENOMINATOR_CUR + cpu current div denominator + 19 + 8 + read-only + + + + + DBG_CLK_CTRL0 + Reserved + 0xE4 + 0x20 + 0x03FFFFFF + + + REG_DBG_CH0_SEL + Reserved + 0 + 8 + read-write + + + REG_DBG_CH1_SEL + Reserved + 8 + 8 + read-write + + + REG_DBG_CH2_SEL + Reserved + 16 + 8 + read-write + + + REG_DBG_CH0_DIV_NUM + Reserved + 24 + 8 + read-write + + + + + DBG_CLK_CTRL1 + Reserved + 0xE8 + 0x20 + 0x00000303 + + + REG_DBG_CH1_DIV_NUM + Reserved + 0 + 8 + read-write + + + REG_DBG_CH2_DIV_NUM + Reserved + 8 + 8 + read-write + + + REG_DBG_CH0_EN + Reserved + 16 + 1 + read-write + + + REG_DBG_CH1_EN + Reserved + 17 + 1 + read-write + + + REG_DBG_CH2_EN + Reserved + 18 + 1 + read-write + + + + + HPCORE_WDT_RESET_SOURCE0 + Reserved + 0xEC + 0x20 + 0x00000002 + + + REG_HPCORE0_WDT_RESET_SOURCE_SEL + 1'b0: use wdt0 to reset hpcore0, 1'b1: use wdt1 to reset hpcore0 + 0 + 1 + read-write + + + REG_HPCORE1_WDT_RESET_SOURCE_SEL + 1'b0: use wdt0 to reset hpcore1, 1'b1: use wdt1 to reset hpcore1 + 1 + 1 + read-write + + + + + + + LP_HUK + LP_HUK Peripheral + HUK + 0x50114000 + + 0x0 + 0x1A8 + registers + + + LP_HUK + 20 + + + + CLK + HUK Generator clock gate control register + 0x4 + 0x20 + 0x00000001 + + + EN + Write 1 to force on register clock gate. + 0 + 1 + read-write + + + MEM_CG_FORCE_ON + Write 1 to force on memory clock gate. + 1 + 1 + read-write + + + + + INT_RAW + HUK Generator interrupt raw register, valid in level. + 0x8 + 0x20 + + + PREP_DONE_INT_RAW + The raw interrupt status bit for the huk_prep_done_int interrupt + 0 + 1 + read-only + + + PROC_DONE_INT_RAW + The raw interrupt status bit for the huk_proc_done_int interrupt + 1 + 1 + read-only + + + POST_DONE_INT_RAW + The raw interrupt status bit for the huk_post_done_int interrupt + 2 + 1 + read-only + + + + + INT_ST + HUK Generator interrupt status register. + 0xC + 0x20 + + + PREP_DONE_INT_ST + The masked interrupt status bit for the huk_prep_done_int interrupt + 0 + 1 + read-only + + + PROC_DONE_INT_ST + The masked interrupt status bit for the huk_proc_done_int interrupt + 1 + 1 + read-only + + + POST_DONE_INT_ST + The masked interrupt status bit for the huk_post_done_int interrupt + 2 + 1 + read-only + + + + + INT_ENA + HUK Generator interrupt enable register. + 0x10 + 0x20 + + + PREP_DONE_INT_ENA + The interrupt enable bit for the huk_prep_done_int interrupt + 0 + 1 + read-write + + + PROC_DONE_INT_ENA + The interrupt enable bit for the huk_proc_done_int interrupt + 1 + 1 + read-write + + + POST_DONE_INT_ENA + The interrupt enable bit for the huk_post_done_int interrupt + 2 + 1 + read-write + + + + + INT_CLR + HUK Generator interrupt clear register. + 0x14 + 0x20 + + + PREP_DONE_INT_CLR + Set this bit to clear the huk_prep_done_int interrupt + 0 + 1 + write-only + + + PROC_DONE_INT_CLR + Set this bit to clear the huk_proc_done_int interrupt + 1 + 1 + write-only + + + POST_DONE_INT_CLR + Set this bit to clear the huk_post_done_int interrupt + 2 + 1 + write-only + + + + + CONF + HUK Generator configuration register + 0x20 + 0x20 + + + MODE + Set this field to choose the huk process. 1: process huk generate mode. 0: process huk recovery mode. + 0 + 1 + read-write + + + + + START + HUK Generator control register + 0x24 + 0x20 + + + START + Write 1 to continue HUK Generator operation at LOAD/GAIN state. + 0 + 1 + write-only + + + CONTINUE + Write 1 to start HUK Generator at IDLE state. + 1 + 1 + write-only + + + + + STATE + HUK Generator state register + 0x28 + 0x20 + + + STATE + The state of HUK Generator. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY. + 0 + 2 + read-only + + + + + STATUS + HUK Generator HUK status register + 0x34 + 0x20 + + + STATUS + The HUK generation status. 0: HUK is not generated. 1: HUK is generated and valid. 2: HUK is generated but invalid. 3: reserved. + 0 + 2 + read-only + + + RISK_LEVEL + The risk level of HUK. 0-6: the higher the risk level is, the more error bits there are in the PUF SRAM. 7: Error Level, HUK is invalid. + 2 + 3 + read-only + + + + + DATE + Version control register + 0xFC + 0x20 + 0x02305040 + + + DATE + HUK Generator version control register. + 0 + 28 + read-write + + + + + 96 + 0x4 + INFO_MEM[%s] + The memory that stores HUK info. + 0x100 + 0x20 + + + + + I2C0 + I2C (Inter-Integrated Circuit) Controller 0 + I2C + 0x500C4000 + + 0x0 + 0x90 + registers + + + I2C0 + 44 + + + + SCL_LOW_PERIOD + Configures the low level width of the SCL Clock. + 0x0 + 0x20 + + + SCL_LOW_PERIOD + Configures the low level width of the SCL Clock. +Measurement unit: i2c_sclk. + 0 + 9 + read-write + + + + + CTR + Transmission setting + 0x4 + 0x20 + 0x00000208 + + + SDA_FORCE_OUT + Configures the SDA output mode +1: Direct output, + +0: Open drain output. + 0 + 1 + read-write + + + SCL_FORCE_OUT + Configures the SCL output mode +1: Direct output, + +0: Open drain output. + 1 + 1 + read-write + + + SAMPLE_SCL_LEVEL + Configures the sample mode for SDA. +1: Sample SDA data on the SCL low level. + +0: Sample SDA data on the SCL high level. + 2 + 1 + read-write + + + RX_FULL_ACK_LEVEL + Configures the ACK value that needs to be sent by master when the rx_fifo_cnt has reached the threshold. + 3 + 1 + read-write + + + MS_MODE + Configures the module as an I2C Master or Slave. +0: Slave + +1: Master + 4 + 1 + read-write + + + TRANS_START + Configures to start sending the data in txfifo for slave. +0: No effect + +1: Start + 5 + 1 + write-only + + + TX_LSB_FIRST + Configures to control the sending order for data needing to be sent. +1: send data from the least significant bit, + +0: send data from the most significant bit. + 6 + 1 + read-write + + + RX_LSB_FIRST + Configures to control the storage order for received data. +1: receive data from the least significant bit + +0: receive data from the most significant bit. + 7 + 1 + read-write + + + CLK_EN + Configures whether to gate clock signal for registers. + +0: Force clock on for registers + +1: Support clock only when registers are read or written to by software. + 8 + 1 + read-write + + + ARBITRATION_EN + Configures to enable I2C bus arbitration detection. +0: No effect + +1: Enable + 9 + 1 + read-write + + + FSM_RST + Configures to reset the SCL_FSM. +0: No effect + +1: Reset + 10 + 1 + write-only + + + CONF_UPGATE + Configures this bit for synchronization +0: No effect + +1: Synchronize + 11 + 1 + write-only + + + SLV_TX_AUTO_START_EN + Configures to enable slave to send data automatically +0: Disable + +1: Enable + 12 + 1 + read-write + + + ADDR_10BIT_RW_CHECK_EN + Configures to check if the r/w bit of 10bit addressing consists with I2C protocol. +0: Not check + +1: Check + 13 + 1 + read-write + + + ADDR_BROADCASTING_EN + Configures to support the 7bit general call function. +0: Not support + +1: Support + 14 + 1 + read-write + + + + + SR + Describe I2C work status. + 0x8 + 0x20 + 0x0000C000 + + + RESP_REC + Represents the received ACK value in master mode or slave mode. +0: ACK, + +1: NACK. + 0 + 1 + read-only + + + SLAVE_RW + Represents the transfer direction in slave mode,. +1: Master reads from slave, + +0: Master writes to slave. + 1 + 1 + read-only + + + ARB_LOST + Represents whether the I2C controller loses control of SCL line. +0: No arbitration lost + +1: Arbitration lost + 3 + 1 + read-only + + + BUS_BUSY + Represents the I2C bus state. +1: The I2C bus is busy transferring data, + +0: The I2C bus is in idle state. + 4 + 1 + read-only + + + SLAVE_ADDRESSED + Represents whether the address sent by the master is equal to the address of the slave. +Valid only when the module is configured as an I2C Slave. +0: Not equal + +1: Equal + 5 + 1 + read-only + + + RXFIFO_CNT + Represents the number of data bytes to be sent. + 8 + 6 + read-only + + + STRETCH_CAUSE + Represents the cause of SCL clocking stretching in slave mode. +0: Stretching SCL low when the master starts to read data. + +1: Stretching SCL low when I2C TX FIFO is empty in slave mode. + +2: Stretching SCL low when I2C RX FIFO is full in slave mode. + 14 + 2 + read-only + + + TXFIFO_CNT + Represents the number of data bytes received in RAM. + 18 + 6 + read-only + + + SCL_MAIN_STATE_LAST + Represents the states of the I2C module state machine. +0: Idle, + +1: Address shift, + +2: ACK address, + +3: Rx data, + +4: Tx data, + +5: Send ACK, + +6: Wait ACK + 24 + 3 + read-only + + + SCL_STATE_LAST + Represents the states of the state machine used to produce SCL. +0: Idle, + +1: Start, + +2: Negative edge, + +3: Low, + +4: Positive edge, + +5: High, + +6: Stop + 28 + 3 + read-only + + + + + TO + Setting time out control for receiving data. + 0xC + 0x20 + 0x00000010 + + + TIME_OUT_VALUE + Configures the timeout threshold period for SCL stucking at high or low level. The actual period is 2^(reg_time_out_value). +Measurement unit: i2c_sclk. + 0 + 5 + read-write + + + TIME_OUT_EN + Configures to enable time out control. +0: No effect + +1: Enable + 5 + 1 + read-write + + + + + SLAVE_ADDR + Local slave address setting + 0x10 + 0x20 + + + SLAVE_ADDR + Configure the slave address of I2C Slave. + 0 + 15 + read-write + + + ADDR_10BIT_EN + Configures to enable the slave 10-bit addressing mode in master mode. +0: No effect + +1: Enable + 31 + 1 + read-write + + + + + FIFO_ST + FIFO status register. + 0x14 + 0x20 + + + RXFIFO_RADDR + Represents the offset address of the APB reading from RXFIFO + 0 + 5 + read-only + + + RXFIFO_WADDR + Represents the offset address of i2c module receiving data and writing to RXFIFO. + 5 + 5 + read-only + + + TXFIFO_RADDR + Represents the offset address of i2c module reading from TXFIFO. + 10 + 5 + read-only + + + TXFIFO_WADDR + Represents the offset address of APB bus writing to TXFIFO. + 15 + 5 + read-only + + + SLAVE_RW_POINT + Represents the offset address in the I2C Slave RAM addressed by I2C Master when in I2C slave mode. + 22 + 8 + read-only + + + + + FIFO_CONF + FIFO configuration register. + 0x18 + 0x20 + 0x0000408B + + + RXFIFO_WM_THRHD + Configures the water mark threshold of RXFIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd[4:0], reg_rxfifo_wm_int_raw bit will be valid. + 0 + 5 + read-write + + + TXFIFO_WM_THRHD + Configures the water mark threshold of TXFIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than reg_txfifo_wm_thrhd[4:0], reg_txfifo_wm_int_raw bit will be valid. + 5 + 5 + read-write + + + NONFIFO_EN + Configures to enable APB nonfifo access. + 10 + 1 + read-write + + + FIFO_ADDR_CFG_EN + Configures to enable double addressing mode. When this mode is enabled, the byte received after the I2C address byte represents the offset address in the I2C Slave RAM. +0: Disable + +1: Enable + 11 + 1 + read-write + + + RX_FIFO_RST + Configures to reset RXFIFO. +0: No effect + +1: Reset + 12 + 1 + read-write + + + TX_FIFO_RST + Configures to reset TXFIFO. +0: No effect + +1: Reset + 13 + 1 + read-write + + + FIFO_PRT_EN + Configures to enable FIFO pointer in non-fifo access mode. This bit controls the valid bits and the TX/RX FIFO overflow, underflow, full and empty interrupts. +0: No effect + +1: Enable + 14 + 1 + read-write + + + + + DATA + Rx FIFO read data. + 0x1C + 0x20 + + + FIFO_RDATA + Represents the value of RXFIFO read data. + 0 + 8 + read-only + + + + + INT_RAW + Raw interrupt status + 0x20 + 0x20 + 0x00000002 + + + RXFIFO_WM_INT_RAW + The raw interrupt status of I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + read-only + + + TXFIFO_WM_INT_RAW + The raw interrupt status of I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + read-only + + + RXFIFO_OVF_INT_RAW + The raw interrupt status of I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + read-only + + + END_DETECT_INT_RAW + The raw interrupt status of the I2C_END_DETECT_INT interrupt. + 3 + 1 + read-only + + + BYTE_TRANS_DONE_INT_RAW + The raw interrupt status of the I2C_END_DETECT_INT interrupt. + 4 + 1 + read-only + + + ARBITRATION_LOST_INT_RAW + The raw interrupt status of the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + read-only + + + MST_TXFIFO_UDF_INT_RAW + The raw interrupt status of I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + read-only + + + TRANS_COMPLETE_INT_RAW + The raw interrupt status of the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + read-only + + + TIME_OUT_INT_RAW + The raw interrupt status of the I2C_TIME_OUT_INT interrupt. + 8 + 1 + read-only + + + TRANS_START_INT_RAW + The raw interrupt status of the I2C_TRANS_START_INT interrupt. + 9 + 1 + read-only + + + NACK_INT_RAW + The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + read-only + + + TXFIFO_OVF_INT_RAW + The raw interrupt status of I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + read-only + + + RXFIFO_UDF_INT_RAW + The raw interrupt status of I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + read-only + + + SCL_ST_TO_INT_RAW + The raw interrupt status of I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + read-only + + + SCL_MAIN_ST_TO_INT_RAW + The raw interrupt status of I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + read-only + + + DET_START_INT_RAW + The raw interrupt status of I2C_DET_START_INT interrupt. + 15 + 1 + read-only + + + SLAVE_STRETCH_INT_RAW + The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt. + 16 + 1 + read-only + + + GENERAL_CALL_INT_RAW + The raw interrupt status of I2C_GENARAL_CALL_INT interrupt. + 17 + 1 + read-only + + + SLAVE_ADDR_UNMATCH_INT_RAW + The raw interrupt status of I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt. + 18 + 1 + read-only + + + + + INT_CLR + Interrupt clear bits + 0x24 + 0x20 + + + RXFIFO_WM_INT_CLR + Write 1 to clear I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + write-only + + + TXFIFO_WM_INT_CLR + Write 1 to clear I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + write-only + + + RXFIFO_OVF_INT_CLR + Write 1 to clear I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + write-only + + + END_DETECT_INT_CLR + Write 1 to clear the I2C_END_DETECT_INT interrupt. + 3 + 1 + write-only + + + BYTE_TRANS_DONE_INT_CLR + Write 1 to clear the I2C_END_DETECT_INT interrupt. + 4 + 1 + write-only + + + ARBITRATION_LOST_INT_CLR + Write 1 to clear the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + write-only + + + MST_TXFIFO_UDF_INT_CLR + Write 1 to clear I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + write-only + + + TRANS_COMPLETE_INT_CLR + Write 1 to clear the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + write-only + + + TIME_OUT_INT_CLR + Write 1 to clear the I2C_TIME_OUT_INT interrupt. + 8 + 1 + write-only + + + TRANS_START_INT_CLR + Write 1 to clear the I2C_TRANS_START_INT interrupt. + 9 + 1 + write-only + + + NACK_INT_CLR + Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + write-only + + + TXFIFO_OVF_INT_CLR + Write 1 to clear I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + write-only + + + RXFIFO_UDF_INT_CLR + Write 1 to clear I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + write-only + + + SCL_ST_TO_INT_CLR + Write 1 to clear I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + write-only + + + SCL_MAIN_ST_TO_INT_CLR + Write 1 to clear I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + write-only + + + DET_START_INT_CLR + Write 1 to clear I2C_DET_START_INT interrupt. + 15 + 1 + write-only + + + SLAVE_STRETCH_INT_CLR + Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt. + 16 + 1 + write-only + + + GENERAL_CALL_INT_CLR + Write 1 to clear I2C_GENARAL_CALL_INT interrupt. + 17 + 1 + write-only + + + SLAVE_ADDR_UNMATCH_INT_CLR + Write 1 to clear I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt. + 18 + 1 + write-only + + + + + INT_ENA + Interrupt enable bits + 0x28 + 0x20 + + + RXFIFO_WM_INT_ENA + Write 1 to enable I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + read-write + + + TXFIFO_WM_INT_ENA + Write 1 to enable I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + read-write + + + RXFIFO_OVF_INT_ENA + Write 1 to enable I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + read-write + + + END_DETECT_INT_ENA + Write 1 to enable the I2C_END_DETECT_INT interrupt. + 3 + 1 + read-write + + + BYTE_TRANS_DONE_INT_ENA + Write 1 to enable the I2C_END_DETECT_INT interrupt. + 4 + 1 + read-write + + + ARBITRATION_LOST_INT_ENA + Write 1 to enable the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + read-write + + + MST_TXFIFO_UDF_INT_ENA + Write 1 to enable I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + read-write + + + TRANS_COMPLETE_INT_ENA + Write 1 to enable the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + read-write + + + TIME_OUT_INT_ENA + Write 1 to enable the I2C_TIME_OUT_INT interrupt. + 8 + 1 + read-write + + + TRANS_START_INT_ENA + Write 1 to enable the I2C_TRANS_START_INT interrupt. + 9 + 1 + read-write + + + NACK_INT_ENA + Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + read-write + + + TXFIFO_OVF_INT_ENA + Write 1 to enable I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + read-write + + + RXFIFO_UDF_INT_ENA + Write 1 to enable I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + read-write + + + SCL_ST_TO_INT_ENA + Write 1 to enable I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + read-write + + + SCL_MAIN_ST_TO_INT_ENA + Write 1 to enable I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + read-write + + + DET_START_INT_ENA + Write 1 to enable I2C_DET_START_INT interrupt. + 15 + 1 + read-write + + + SLAVE_STRETCH_INT_ENA + Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt. + 16 + 1 + read-write + + + GENERAL_CALL_INT_ENA + Write 1 to enable I2C_GENARAL_CALL_INT interrupt. + 17 + 1 + read-write + + + SLAVE_ADDR_UNMATCH_INT_ENA + Write 1 to enable I2C_SLAVE_ADDR_UNMATCH_INT interrupt. + 18 + 1 + read-write + + + + + INT_STATUS + Status of captured I2C communication events + 0x2C + 0x20 + + + RXFIFO_WM_INT_ST + The masked interrupt status status of I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + read-only + + + TXFIFO_WM_INT_ST + The masked interrupt status status of I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + read-only + + + RXFIFO_OVF_INT_ST + The masked interrupt status status of I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + read-only + + + END_DETECT_INT_ST + The masked interrupt status status of the I2C_END_DETECT_INT interrupt. + 3 + 1 + read-only + + + BYTE_TRANS_DONE_INT_ST + The masked interrupt status status of the I2C_END_DETECT_INT interrupt. + 4 + 1 + read-only + + + ARBITRATION_LOST_INT_ST + The masked interrupt status status of the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + read-only + + + MST_TXFIFO_UDF_INT_ST + The masked interrupt status status of I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + read-only + + + TRANS_COMPLETE_INT_ST + The masked interrupt status status of the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + read-only + + + TIME_OUT_INT_ST + The masked interrupt status status of the I2C_TIME_OUT_INT interrupt. + 8 + 1 + read-only + + + TRANS_START_INT_ST + The masked interrupt status status of the I2C_TRANS_START_INT interrupt. + 9 + 1 + read-only + + + NACK_INT_ST + The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + read-only + + + TXFIFO_OVF_INT_ST + The masked interrupt status status of I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + read-only + + + RXFIFO_UDF_INT_ST + The masked interrupt status status of I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + read-only + + + SCL_ST_TO_INT_ST + The masked interrupt status status of I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + read-only + + + SCL_MAIN_ST_TO_INT_ST + The masked interrupt status status of I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + read-only + + + DET_START_INT_ST + The masked interrupt status status of I2C_DET_START_INT interrupt. + 15 + 1 + read-only + + + SLAVE_STRETCH_INT_ST + The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt. + 16 + 1 + read-only + + + GENERAL_CALL_INT_ST + The masked interrupt status status of I2C_GENARAL_CALL_INT interrupt. + 17 + 1 + read-only + + + SLAVE_ADDR_UNMATCH_INT_ST + The masked interrupt status status of I2C_SLAVE_ADDR_UNMATCH_INT interrupt. + 18 + 1 + read-only + + + + + SDA_HOLD + Configures the hold time after a negative SCL edge. + 0x30 + 0x20 + + + TIME + Configures the time to hold the data after the falling edge of SCL. +Measurement unit: i2c_sclk + 0 + 9 + read-write + + + + + SDA_SAMPLE + Configures the sample time after a positive SCL edge. + 0x34 + 0x20 + + + TIME + Configures the sample time after a positive SCL edge. +Measurement unit: i2c_sclk + 0 + 9 + read-write + + + + + SCL_HIGH_PERIOD + Configures the high level width of SCL + 0x38 + 0x20 + + + SCL_HIGH_PERIOD + Configures for how long SCL remains high in master mode. +Measurement unit: i2c_sclk + 0 + 9 + read-write + + + SCL_WAIT_HIGH_PERIOD + Configures the SCL_FSM's waiting period for SCL high level in master mode. +Measurement unit: i2c_sclk + 9 + 7 + read-write + + + + + SCL_START_HOLD + Configures the delay between the SDA and SCL negative edge for a start condition + 0x40 + 0x20 + 0x00000008 + + + TIME + Configures the time between the falling edge of SDA and the falling edge of SCL for a START condition. +Measurement unit: i2c_sclk. + 0 + 9 + read-write + + + + + SCL_RSTART_SETUP + Configures the delay between the positive edge of SCL and the negative edge of SDA + 0x44 + 0x20 + 0x00000008 + + + TIME + Configures the time between the positive edge of SCL and the negative edge of SDA for a RESTART condition. +Measurement unit: i2c_sclk + 0 + 9 + read-write + + + + + SCL_STOP_HOLD + Configures the delay after the SCL clock edge for a stop condition + 0x48 + 0x20 + 0x00000008 + + + TIME + Configures the delay after the STOP condition. +Measurement unit: i2c_sclk + 0 + 9 + read-write + + + + + SCL_STOP_SETUP + Configures the delay between the SDA and SCL rising edge for a stop condition. +Measurement unit: i2c_sclk + 0x4C + 0x20 + 0x00000008 + + + TIME + Configures the time between the rising edge of SCL and the rising edge of SDA. +Measurement unit: i2c_sclk + 0 + 9 + read-write + + + + + FILTER_CFG + SCL and SDA filter configuration register + 0x50 + 0x20 + 0x00000300 + + + SCL_FILTER_THRES + Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL input has smaller width than this register value, the I2C controller will ignore that pulse. +Measurement unit: i2c_sclk + 0 + 4 + read-write + + + SDA_FILTER_THRES + Configures the threshold pulse width to be filtered on SDA. When a pulse on the SDA input has smaller width than this register value, the I2C controller will ignore that pulse. +Measurement unit: i2c_sclk + 4 + 4 + read-write + + + SCL_FILTER_EN + Configures to enable the filter function for SCL. + 8 + 1 + read-write + + + SDA_FILTER_EN + Configures to enable the filter function for SDA. + 9 + 1 + read-write + + + + + CLK_CONF + I2C CLK configuration register + 0x54 + 0x20 + 0x00200000 + + + SCLK_DIV_NUM + the integral part of the fractional divisor for i2c module + 0 + 8 + read-write + + + SCLK_DIV_A + the numerator of the fractional part of the fractional divisor for i2c module + 8 + 6 + read-write + + + SCLK_DIV_B + the denominator of the fractional part of the fractional divisor for i2c module + 14 + 6 + read-write + + + SCLK_SEL + The clock selection for i2c module:0-XTAL,1-CLK_8MHz. + 20 + 1 + read-write + + + SCLK_ACTIVE + The clock switch for i2c module + 21 + 1 + read-write + + + + + COMD0 + I2C command register 0 + 0x58 + 0x20 + + + COMMAND0 + Configures command 0. It consists of three parts: +op_code is the command, +0: RSTART, +1: WRITE, +2: READ, +3: STOP, +4: END. + +Byte_num represents the number of bytes that need to be sent or received. +ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more information. + 0 + 14 + read-write + + + COMMAND0_DONE + Represents whether command 0 is done in I2C Master mode. +0: Not done + +1: Done + 31 + 1 + read-write + + + + + COMD1 + I2C command register 1 + 0x5C + 0x20 + + + COMMAND1 + Configures command 1. See details in I2C_CMD0_REG[13:0]. + 0 + 14 + read-write + + + COMMAND1_DONE + Represents whether command 1 is done in I2C Master mode. +0: Not done + +1: Done + 31 + 1 + read-write + + + + + COMD2 + I2C command register 2 + 0x60 + 0x20 + + + COMMAND2 + Configures command 2. See details in I2C_CMD0_REG[13:0]. + 0 + 14 + read-write + + + COMMAND2_DONE + Represents whether command 2 is done in I2C Master mode. +0: Not done + +1: Done + 31 + 1 + read-write + + + + + COMD3 + I2C command register 3 + 0x64 + 0x20 + + + COMMAND3 + Configures command 3. See details in I2C_CMD0_REG[13:0]. + 0 + 14 + read-write + + + COMMAND3_DONE + Represents whether command 3 is done in I2C Master mode. +0: Not done + +1: Done + 31 + 1 + read-write + + + + + COMD4 + I2C command register 4 + 0x68 + 0x20 + + + COMMAND4 + Configures command 4. See details in I2C_CMD0_REG[13:0]. + 0 + 14 + read-write + + + COMMAND4_DONE + Represents whether command 4 is done in I2C Master mode. +0: Not done + +1: Done + 31 + 1 + read-write + + + + + COMD5 + I2C command register 5 + 0x6C + 0x20 + + + COMMAND5 + Configures command 5. See details in I2C_CMD0_REG[13:0]. + 0 + 14 + read-write + + + COMMAND5_DONE + Represents whether command 5 is done in I2C Master mode. +0: Not done + +1: Done + 31 + 1 + read-write + + + + + COMD6 + I2C command register 6 + 0x70 + 0x20 + + + COMMAND6 + Configures command 6. See details in I2C_CMD0_REG[13:0]. + 0 + 14 + read-write + + + COMMAND6_DONE + Represents whether command 6 is done in I2C Master mode. +0: Not done + +1: Done + 31 + 1 + read-write + + + + + COMD7 + I2C command register 7 + 0x74 + 0x20 + + + COMMAND7 + Configures command 7. See details in I2C_CMD0_REG[13:0]. + 0 + 14 + read-write + + + COMMAND7_DONE + Represents whether command 7 is done in I2C Master mode. +0: Not done + +1: Done + 31 + 1 + read-write + + + + + SCL_ST_TIME_OUT + SCL status time out register + 0x78 + 0x20 + 0x00000010 + + + SCL_ST_TO_I2C + Configures the threshold value of SCL_FSM state unchanged period. It should be no more than 23. +Measurement unit: i2c_sclk + 0 + 5 + read-write + + + + + SCL_MAIN_ST_TIME_OUT + SCL main status time out register + 0x7C + 0x20 + 0x00000010 + + + SCL_MAIN_ST_TO_I2C + Configures the threshold value of SCL_MAIN_FSM state unchanged period.nIt should be no more than 23. +Measurement unit: i2c_sclk + 0 + 5 + read-write + + + + + SCL_SP_CONF + Power configuration register + 0x80 + 0x20 + + + SCL_RST_SLV_EN + Configures to send out SCL pulses when I2C master is IDLE. The number of pulses equals to reg_scl_rst_slv_num[4:0]. + 0 + 1 + read-write + + + SCL_RST_SLV_NUM + Configure the pulses of SCL generated in I2C master mode. +Valid when reg_scl_rst_slv_en is 1. +Measurement unit: i2c_sclk + 1 + 5 + read-write + + + SCL_PD_EN + Configures to power down the I2C output SCL line. +0: Not power down. + +1: Power down. +Valid only when reg_scl_force_out is 1. + 6 + 1 + read-write + + + SDA_PD_EN + Configures to power down the I2C output SDA line. +0: Not power down. + +1: Power down. +Valid only when reg_sda_force_out is 1. + 7 + 1 + read-write + + + + + SCL_STRETCH_CONF + Set SCL stretch of I2C slave + 0x84 + 0x20 + + + STRETCH_PROTECT_NUM + Configures the time period to release the SCL line from stretching to avoid timing violation. Usually it should be larger than the SDA setup time. +Measurement unit: i2c_sclk + 0 + 10 + read-write + + + SLAVE_SCL_STRETCH_EN + Configures to enable slave SCL stretch function. +0: Disable + +1: Enable +The SCL output line will be stretched low when reg_slave_scl_stretch_en is 1 and stretch event happens. The stretch cause can be seen in reg_stretch_cause. + 10 + 1 + read-write + + + SLAVE_SCL_STRETCH_CLR + Configures to clear the I2C slave SCL stretch function. +0: No effect + +1: Clear + 11 + 1 + write-only + + + SLAVE_BYTE_ACK_CTL_EN + Configures to enable the function for slave to control ACK level. +0: Disable + +1: Enable + 12 + 1 + read-write + + + SLAVE_BYTE_ACK_LVL + Set the ACK level when slave controlling ACK level function enables. +0: Low level + +1: High level + 13 + 1 + read-write + + + + + DATE + Version register + 0xF8 + 0x20 + 0x02201172 + + + DATE + Version control register. + 0 + 32 + read-write + + + + + TXFIFO_START_ADDR + I2C TXFIFO base address register + 0x100 + 0x20 + + + TXFIFO_START_ADDR + Represents the I2C txfifo first address. + 0 + 32 + read-only + + + + + RXFIFO_START_ADDR + I2C RXFIFO base address register + 0x180 + 0x20 + + + RXFIFO_START_ADDR + Represents the I2C rxfifo first address. + 0 + 32 + read-only + + + + + + + I2C1 + I2C (Inter-Integrated Circuit) Controller 1 + 0x500C5000 + + I2C1 + 45 + + + + I2S0 + I2S (Inter-IC Sound) Controller 0 + I2S + 0x500C6000 + + 0x0 + 0x60 + registers + + + I2S0 + 27 + + + + INT_RAW + I2S interrupt raw register, valid in level. + 0xC + 0x20 + + + RX_DONE_INT_RAW + The raw interrupt status bit for the i2s_rx_done_int interrupt + 0 + 1 + read-only + + + TX_DONE_INT_RAW + The raw interrupt status bit for the i2s_tx_done_int interrupt + 1 + 1 + read-only + + + RX_HUNG_INT_RAW + The raw interrupt status bit for the i2s_rx_hung_int interrupt + 2 + 1 + read-only + + + TX_HUNG_INT_RAW + The raw interrupt status bit for the i2s_tx_hung_int interrupt + 3 + 1 + read-only + + + + + INT_ST + I2S interrupt status register. + 0x10 + 0x20 + + + RX_DONE_INT_ST + The masked interrupt status bit for the i2s_rx_done_int interrupt + 0 + 1 + read-only + + + TX_DONE_INT_ST + The masked interrupt status bit for the i2s_tx_done_int interrupt + 1 + 1 + read-only + + + RX_HUNG_INT_ST + The masked interrupt status bit for the i2s_rx_hung_int interrupt + 2 + 1 + read-only + + + TX_HUNG_INT_ST + The masked interrupt status bit for the i2s_tx_hung_int interrupt + 3 + 1 + read-only + + + + + INT_ENA + I2S interrupt enable register. + 0x14 + 0x20 + + + RX_DONE_INT_ENA + The interrupt enable bit for the i2s_rx_done_int interrupt + 0 + 1 + read-write + + + TX_DONE_INT_ENA + The interrupt enable bit for the i2s_tx_done_int interrupt + 1 + 1 + read-write + + + RX_HUNG_INT_ENA + The interrupt enable bit for the i2s_rx_hung_int interrupt + 2 + 1 + read-write + + + TX_HUNG_INT_ENA + The interrupt enable bit for the i2s_tx_hung_int interrupt + 3 + 1 + read-write + + + + + INT_CLR + I2S interrupt clear register. + 0x18 + 0x20 + + + RX_DONE_INT_CLR + Set this bit to clear the i2s_rx_done_int interrupt + 0 + 1 + write-only + + + TX_DONE_INT_CLR + Set this bit to clear the i2s_tx_done_int interrupt + 1 + 1 + write-only + + + RX_HUNG_INT_CLR + Set this bit to clear the i2s_rx_hung_int interrupt + 2 + 1 + write-only + + + TX_HUNG_INT_CLR + Set this bit to clear the i2s_tx_hung_int interrupt + 3 + 1 + write-only + + + + + RX_CONF + I2S RX configure register + 0x20 + 0x20 + 0x00C0B600 + + + RX_RESET + Set this bit to reset receiver + 0 + 1 + write-only + + + RX_FIFO_RESET + Set this bit to reset Rx AFIFO + 1 + 1 + write-only + + + RX_START + Set this bit to start receiving data + 2 + 1 + read-write + + + RX_SLAVE_MOD + Set this bit to enable slave receiver mode + 3 + 1 + read-write + + + RX_STOP_MODE + 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full. + 4 + 2 + read-write + + + RX_MONO + Set this bit to enable receiver in mono mode + 6 + 1 + read-write + + + RX_BIG_ENDIAN + I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value. + 7 + 1 + read-write + + + RX_UPDATE + Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done. + 8 + 1 + read-write + + + RX_MONO_FST_VLD + 1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode. + 9 + 1 + read-write + + + RX_PCM_CONF + I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & + 10 + 2 + read-write + + + RX_PCM_BYPASS + Set this bit to bypass Compress/Decompress module for received data. + 12 + 1 + read-write + + + RX_MSB_SHIFT + Set this bit to enable receiver in Phillips standard mode + 13 + 1 + read-write + + + RX_LEFT_ALIGN + 1: I2S RX left alignment mode. 0: I2S RX right alignment mode. + 15 + 1 + read-write + + + RX_24_FILL_EN + 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits. + 16 + 1 + read-write + + + RX_WS_IDLE_POL + 0: WS should be 0 when receiving left channel data, and WS is 1in right channel. 1: WS should be 1 when receiving left channel data, and WS is 0in right channel. + 17 + 1 + read-write + + + RX_BIT_ORDER + I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first. + 18 + 1 + read-write + + + RX_TDM_EN + 1: Enable I2S TDM Rx mode . 0: Disable. + 19 + 1 + read-write + + + RX_PDM_EN + 1: Enable I2S PDM Rx mode . 0: Disable. + 20 + 1 + read-write + + + RX_BCK_DIV_NUM + Bit clock configuration bits in receiver mode. + 21 + 6 + read-write + + + + + TX_CONF + I2S TX configure register + 0x24 + 0x20 + 0x00C0F210 + + + TX_RESET + Set this bit to reset transmitter + 0 + 1 + write-only + + + TX_FIFO_RESET + Set this bit to reset Tx AFIFO + 1 + 1 + write-only + + + TX_START + Set this bit to start transmitting data + 2 + 1 + read-write + + + TX_SLAVE_MOD + Set this bit to enable slave transmitter mode + 3 + 1 + read-write + + + TX_STOP_EN + Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy + 4 + 1 + read-write + + + TX_CHAN_EQUAL + 1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode. + 5 + 1 + read-write + + + TX_MONO + Set this bit to enable transmitter in mono mode + 6 + 1 + read-write + + + TX_BIG_ENDIAN + I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr value. + 7 + 1 + read-write + + + TX_UPDATE + Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done. + 8 + 1 + read-write + + + TX_MONO_FST_VLD + 1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode. + 9 + 1 + read-write + + + TX_PCM_CONF + I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & + 10 + 2 + read-write + + + TX_PCM_BYPASS + Set this bit to bypass Compress/Decompress module for transmitted data. + 12 + 1 + read-write + + + TX_MSB_SHIFT + Set this bit to enable transmitter in Phillips standard mode + 13 + 1 + read-write + + + TX_BCK_NO_DLY + 1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode. + 14 + 1 + read-write + + + TX_LEFT_ALIGN + 1: I2S TX left alignment mode. 0: I2S TX right alignment mode. + 15 + 1 + read-write + + + TX_24_FILL_EN + 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode + 16 + 1 + read-write + + + TX_WS_IDLE_POL + 0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: WS should be 1 when sending left channel data, and WS is 0in right channel. + 17 + 1 + read-write + + + TX_BIT_ORDER + I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first. + 18 + 1 + read-write + + + TX_TDM_EN + 1: Enable I2S TDM Tx mode . 0: Disable. + 19 + 1 + read-write + + + TX_PDM_EN + 1: Enable I2S PDM Tx mode . 0: Disable. + 20 + 1 + read-write + + + TX_BCK_DIV_NUM + Bit clock configuration bits in transmitter mode. + 21 + 6 + read-write + + + TX_CHAN_MOD + I2S transmitter channel mode configuration bits. + 27 + 3 + read-write + + + SIG_LOOPBACK + Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals. + 30 + 1 + read-write + + + + + RX_CONF1 + I2S RX configure register 1 + 0x28 + 0x20 + 0x787BC000 + + + RX_TDM_WS_WIDTH + The width of rx_ws_out at idle level in TDM mode is (I2S_RX_TDM_WS_WIDTH[8:0] +1) * T_bck + 0 + 9 + read-write + + + RX_BITS_MOD + Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode. + 14 + 5 + read-write + + + RX_HALF_SAMPLE_BITS + I2S Rx half sample bits -1. + 19 + 8 + read-write + + + RX_TDM_CHAN_BITS + The Rx bit number for each channel minus 1in TDM mode. + 27 + 5 + read-write + + + + + TX_CONF1 + I2S TX configure register 1 + 0x2C + 0x20 + 0x787BC000 + + + TX_TDM_WS_WIDTH + The width of tx_ws_out at idle level in TDM mode is (I2S_TX_TDM_WS_WIDTH[8:0] +1) * T_bck + 0 + 9 + read-write + + + TX_BITS_MOD + Set the bits to configure the valid data bit length of I2S transmitter channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode. + 14 + 5 + read-write + + + TX_HALF_SAMPLE_BITS + I2S Tx half sample bits -1. + 19 + 8 + read-write + + + TX_TDM_CHAN_BITS + The Tx bit number for each channel minus 1in TDM mode. + 27 + 5 + read-write + + + + + TX_PCM2PDM_CONF + I2S TX PCM2PDM configuration register + 0x40 + 0x20 + 0x004AA004 + + + TX_PDM_HP_BYPASS + I2S TX PDM bypass hp filter or not. The option has been removed. + 0 + 1 + read-write + + + TX_PDM_SINC_OSR2 + I2S TX PDM OSR2 value + 1 + 4 + read-write + + + TX_PDM_PRESCALE + I2S TX PDM prescale for sigmadelta + 5 + 8 + read-write + + + TX_PDM_HP_IN_SHIFT + I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + 13 + 2 + read-write + + + TX_PDM_LP_IN_SHIFT + I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + 15 + 2 + read-write + + + TX_PDM_SINC_IN_SHIFT + I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + 17 + 2 + read-write + + + TX_PDM_SIGMADELTA_IN_SHIFT + I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + 19 + 2 + read-write + + + TX_PDM_SIGMADELTA_DITHER2 + I2S TX PDM sigmadelta dither2 value + 21 + 1 + read-write + + + TX_PDM_SIGMADELTA_DITHER + I2S TX PDM sigmadelta dither value + 22 + 1 + read-write + + + TX_PDM_DAC_2OUT_EN + I2S TX PDM dac mode enable + 23 + 1 + read-write + + + TX_PDM_DAC_MODE_EN + I2S TX PDM dac 2channel enable + 24 + 1 + read-write + + + PCM2PDM_CONV_EN + I2S TX PDM Converter enable + 25 + 1 + read-write + + + + + TX_PCM2PDM_CONF1 + I2S TX PCM2PDM configuration register + 0x44 + 0x20 + 0x03F783C0 + + + TX_PDM_FP + I2S TX PDM Fp + 0 + 10 + read-write + + + TX_PDM_FS + I2S TX PDM Fs + 10 + 10 + read-write + + + TX_IIR_HP_MULT12_5 + The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MULT12_5[2:0]) + 20 + 3 + read-write + + + TX_IIR_HP_MULT12_0 + The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MULT12_0[2:0]) + 23 + 3 + read-write + + + + + RX_PDM2PCM_CONF + I2S RX configure register + 0x48 + 0x20 + 0xF8200000 + + + RX_PDM2PCM_EN + 1: Enable PDM2PCM RX mode. 0: DIsable. + 19 + 1 + read-write + + + RX_PDM_SINC_DSR_16_EN + Configure the down sampling rate of PDM RX filter group1 module. 1: The down sampling rate is 128. 0: down sampling rate is 64. + 20 + 1 + read-write + + + RX_PDM2PCM_AMPLIFY_NUM + Configure PDM RX amplify number. + 21 + 4 + read-write + + + RX_PDM_HP_BYPASS + I2S PDM RX bypass hp filter or not. + 25 + 1 + read-write + + + RX_IIR_HP_MULT12_5 + The fourth parameter of PDM RX IIR_HP filter stage 2 is (504 + LP_I2S_RX_IIR_HP_MULT12_5[2:0]) + 26 + 3 + read-write + + + RX_IIR_HP_MULT12_0 + The fourth parameter of PDM RX IIR_HP filter stage 1 is (504 + LP_I2S_RX_IIR_HP_MULT12_0[2:0]) + 29 + 3 + read-write + + + + + RX_TDM_CTRL + I2S TX TDM mode control register + 0x50 + 0x20 + 0x0000FFFF + + + RX_TDM_PDM_CHAN0_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0: Disable, just input 0 in this channel. + 0 + 1 + read-write + + + RX_TDM_PDM_CHAN1_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0: Disable, just input 0 in this channel. + 1 + 1 + read-write + + + RX_TDM_PDM_CHAN2_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 2. 0: Disable, just input 0 in this channel. + 2 + 1 + read-write + + + RX_TDM_PDM_CHAN3_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 3. 0: Disable, just input 0 in this channel. + 3 + 1 + read-write + + + RX_TDM_PDM_CHAN4_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 4. 0: Disable, just input 0 in this channel. + 4 + 1 + read-write + + + RX_TDM_PDM_CHAN5_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 5. 0: Disable, just input 0 in this channel. + 5 + 1 + read-write + + + RX_TDM_PDM_CHAN6_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 6. 0: Disable, just input 0 in this channel. + 6 + 1 + read-write + + + RX_TDM_PDM_CHAN7_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 7. 0: Disable, just input 0 in this channel. + 7 + 1 + read-write + + + RX_TDM_CHAN8_EN + 1: Enable the valid data input of I2S RX TDM channel 8. 0: Disable, just input 0 in this channel. + 8 + 1 + read-write + + + RX_TDM_CHAN9_EN + 1: Enable the valid data input of I2S RX TDM channel 9. 0: Disable, just input 0 in this channel. + 9 + 1 + read-write + + + RX_TDM_CHAN10_EN + 1: Enable the valid data input of I2S RX TDM channel 10. 0: Disable, just input 0 in this channel. + 10 + 1 + read-write + + + RX_TDM_CHAN11_EN + 1: Enable the valid data input of I2S RX TDM channel 11. 0: Disable, just input 0 in this channel. + 11 + 1 + read-write + + + RX_TDM_CHAN12_EN + 1: Enable the valid data input of I2S RX TDM channel 12. 0: Disable, just input 0 in this channel. + 12 + 1 + read-write + + + RX_TDM_CHAN13_EN + 1: Enable the valid data input of I2S RX TDM channel 13. 0: Disable, just input 0 in this channel. + 13 + 1 + read-write + + + RX_TDM_CHAN14_EN + 1: Enable the valid data input of I2S RX TDM channel 14. 0: Disable, just input 0 in this channel. + 14 + 1 + read-write + + + RX_TDM_CHAN15_EN + 1: Enable the valid data input of I2S RX TDM channel 15. 0: Disable, just input 0 in this channel. + 15 + 1 + read-write + + + RX_TDM_TOT_CHAN_NUM + The total channel number of I2S TX TDM mode. + 16 + 4 + read-write + + + + + TX_TDM_CTRL + I2S TX TDM mode control register + 0x54 + 0x20 + 0x0000FFFF + + + TX_TDM_CHAN0_EN + 1: Enable the valid data output of I2S TX TDM channel 0. 0: Disable, just output 0 in this channel. + 0 + 1 + read-write + + + TX_TDM_CHAN1_EN + 1: Enable the valid data output of I2S TX TDM channel 1. 0: Disable, just output 0 in this channel. + 1 + 1 + read-write + + + TX_TDM_CHAN2_EN + 1: Enable the valid data output of I2S TX TDM channel 2. 0: Disable, just output 0 in this channel. + 2 + 1 + read-write + + + TX_TDM_CHAN3_EN + 1: Enable the valid data output of I2S TX TDM channel 3. 0: Disable, just output 0 in this channel. + 3 + 1 + read-write + + + TX_TDM_CHAN4_EN + 1: Enable the valid data output of I2S TX TDM channel 4. 0: Disable, just output 0 in this channel. + 4 + 1 + read-write + + + TX_TDM_CHAN5_EN + 1: Enable the valid data output of I2S TX TDM channel 5. 0: Disable, just output 0 in this channel. + 5 + 1 + read-write + + + TX_TDM_CHAN6_EN + 1: Enable the valid data output of I2S TX TDM channel 6. 0: Disable, just output 0 in this channel. + 6 + 1 + read-write + + + TX_TDM_CHAN7_EN + 1: Enable the valid data output of I2S TX TDM channel 7. 0: Disable, just output 0 in this channel. + 7 + 1 + read-write + + + TX_TDM_CHAN8_EN + 1: Enable the valid data output of I2S TX TDM channel 8. 0: Disable, just output 0 in this channel. + 8 + 1 + read-write + + + TX_TDM_CHAN9_EN + 1: Enable the valid data output of I2S TX TDM channel 9. 0: Disable, just output 0 in this channel. + 9 + 1 + read-write + + + TX_TDM_CHAN10_EN + 1: Enable the valid data output of I2S TX TDM channel 10. 0: Disable, just output 0 in this channel. + 10 + 1 + read-write + + + TX_TDM_CHAN11_EN + 1: Enable the valid data output of I2S TX TDM channel 11. 0: Disable, just output 0 in this channel. + 11 + 1 + read-write + + + TX_TDM_CHAN12_EN + 1: Enable the valid data output of I2S TX TDM channel 12. 0: Disable, just output 0 in this channel. + 12 + 1 + read-write + + + TX_TDM_CHAN13_EN + 1: Enable the valid data output of I2S TX TDM channel 13. 0: Disable, just output 0 in this channel. + 13 + 1 + read-write + + + TX_TDM_CHAN14_EN + 1: Enable the valid data output of I2S TX TDM channel 14. 0: Disable, just output 0 in this channel. + 14 + 1 + read-write + + + TX_TDM_CHAN15_EN + 1: Enable the valid data output of I2S TX TDM channel 15. 0: Disable, just output 0 in this channel. + 15 + 1 + read-write + + + TX_TDM_TOT_CHAN_NUM + The total channel number of I2S TX TDM mode. + 16 + 4 + read-write + + + TX_TDM_SKIP_MSK_EN + When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels, and only the data of the enabled channels is sent, then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels. + 20 + 1 + read-write + + + + + RX_TIMING + I2S RX timing control register + 0x58 + 0x20 + + + RX_SD_IN_DM + The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 0 + 2 + read-write + + + RX_SD1_IN_DM + The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 4 + 2 + read-write + + + RX_SD2_IN_DM + The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 8 + 2 + read-write + + + RX_SD3_IN_DM + The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 12 + 2 + read-write + + + RX_WS_OUT_DM + The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 16 + 2 + read-write + + + RX_BCK_OUT_DM + The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 20 + 2 + read-write + + + RX_WS_IN_DM + The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 24 + 2 + read-write + + + RX_BCK_IN_DM + The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 28 + 2 + read-write + + + + + TX_TIMING + I2S TX timing control register + 0x5C + 0x20 + + + TX_SD_OUT_DM + The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 0 + 2 + read-write + + + TX_SD1_OUT_DM + The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 4 + 2 + read-write + + + TX_WS_OUT_DM + The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 16 + 2 + read-write + + + TX_BCK_OUT_DM + The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 20 + 2 + read-write + + + TX_WS_IN_DM + The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 24 + 2 + read-write + + + TX_BCK_IN_DM + The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 28 + 2 + read-write + + + + + LC_HUNG_CONF + I2S HUNG configure register. + 0x60 + 0x20 + 0x00000810 + + + LC_FIFO_TIMEOUT + the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value + 0 + 8 + read-write + + + LC_FIFO_TIMEOUT_SHIFT + The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift + 8 + 3 + read-write + + + LC_FIFO_TIMEOUT_ENA + The enable bit for FIFO timeout + 11 + 1 + read-write + + + + + RXEOF_NUM + I2S RX data number control register. + 0x64 + 0x20 + 0x00000040 + + + RX_EOF_NUM + The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel. + 0 + 12 + read-write + + + + + CONF_SIGLE_DATA + I2S signal data register + 0x68 + 0x20 + + + SINGLE_DATA + The configured constant channel data to be sent out. + 0 + 32 + read-write + + + + + STATE + I2S TX status register + 0x6C + 0x20 + 0x00000001 + + + TX_IDLE + 1: i2s_tx is idle state. 0: i2s_tx is working. + 0 + 1 + read-only + + + + + ETM_CONF + I2S ETM configure register + 0x70 + 0x20 + 0x00010040 + + + ETM_TX_SEND_WORD_NUM + I2S ETM send x words event. When sending word number of reg_etm_tx_send_word_num[9:0], i2s will trigger an etm event. + 0 + 10 + read-write + + + ETM_RX_RECEIVE_WORD_NUM + I2S ETM receive x words event. When receiving word number of reg_etm_rx_receive_word_num[9:0], i2s will trigger an etm event. + 10 + 10 + read-write + + + + + FIFO_CNT + I2S sync counter register + 0x74 + 0x20 + + + TX_FIFO_CNT + tx fifo counter value. + 0 + 31 + read-only + + + TX_FIFO_CNT_RST + Set this bit to reset tx fifo counter. + 31 + 1 + write-only + + + + + BCK_CNT + I2S sync counter register + 0x78 + 0x20 + + + TX_BCK_CNT + tx bck counter value. + 0 + 31 + read-only + + + TX_BCK_CNT_RST + Set this bit to reset tx bck counter. + 31 + 1 + write-only + + + + + CLK_GATE + Clock gate register + 0x7C + 0x20 + + + CLK_EN + set this bit to enable clock gate + 0 + 1 + read-write + + + + + DATE + Version control register + 0x80 + 0x20 + 0x02303240 + + + DATE + I2S version control register + 0 + 28 + read-write + + + + + + + I2S1 + I2S (Inter-IC Sound) Controller 1 + 0x500C7000 + + I2S1 + 28 + + + + I2S2 + I2S (Inter-IC Sound) Controller 2 + 0x500C8000 + + I2S2 + 29 + + + + I3C_MST + I3C Controller (Master) + I3C_MST + 0x500DA000 + + 0x0 + 0x90 + registers + + + I3C + 101 + + + + DEVICE_CTRL + DEVICE_CTRL register controls the transfer properties and disposition of controllers capabilities. + 0x0 + 0x20 + 0x00001020 + + + REG_BA_INCLUDE + This bit is used to include I3C broadcast address(0x7E) for private transfer.(If I3C broadcast address is not include for the private transfer, In-Band Interrupts driven from Slaves may not win address arbitration. Hence IBIs will get delayed) + 1 + 1 + read-write + + + REG_TRANS_START + Transfer Start + 2 + 1 + read-write + + + REG_CLK_EN + NA + 3 + 1 + read-write + + + REG_IBI_RSTART_TRANS_EN + NA + 4 + 1 + read-write + + + REG_AUTO_DIS_IBI_EN + NA + 5 + 1 + read-write + + + REG_DMA_RX_EN + NA + 6 + 1 + read-write + + + REG_DMA_TX_EN + NA + 7 + 1 + read-write + + + REG_MULTI_SLV_SINGLE_CCC_EN + 0: rx high bit first, 1: rx low bit first + 8 + 1 + read-write + + + REG_RX_BIT_ORDER + 0: rx low byte fist, 1: rx high byte first + 9 + 1 + read-write + + + REG_RX_BYTE_ORDER + NA + 10 + 1 + read-write + + + REG_SCL_PULLUP_FORCE_EN + This bit is used to force scl_pullup_en + 11 + 1 + read-write + + + REG_SCL_OE_FORCE_EN + This bit is used to force scl_oe + 12 + 1 + read-write + + + REG_SDA_PP_RD_PULLUP_EN + NA + 13 + 1 + read-write + + + REG_SDA_RD_TBIT_HLVL_PULLUP_EN + NA + 14 + 1 + read-write + + + REG_SDA_PP_WR_PULLUP_EN + NA + 15 + 1 + read-write + + + REG_DATA_BYTE_CNT_UNLATCH + 1: read current real-time updated value 0: read latch data byte cnt value + 16 + 1 + read-write + + + REG_MEM_CLK_FORCE_ON + 1: dev characteristic and address table memory clk date force on . 0 : clock gating by rd/wr. + 17 + 1 + read-write + + + + + BUFFER_THLD_CTRL + In-Band Interrupt Status Threshold Value . Every In Band Interrupt received by I3C controller generates an IBI status. This field controls the number of IBI status entries in the IBI buffer that trigger the IBI_STATUS_THLD_STAT interrupt. + 0x1C + 0x20 + 0x00041041 + + + REG_CMD_BUF_EMPTY_THLD + Command Buffer Empty Threshold Value is used to control the number of empty locations(or greater) in the Command Buffer that trigger CMD_BUFFER_READY_STAT interrupt. + 0 + 4 + read-write + + + REG_RESP_BUF_THLD + Response Buffer Threshold Value is used to control the number of entries in the Response Buffer that trigger the RESP_READY_STAT_INTR. + 6 + 3 + read-write + + + REG_IBI_DATA_BUF_THLD + In-Band Interrupt Data Threshold Value . Every In Band Interrupt received by I3C controller generates an IBI status. This field controls the number of IBI data entries in the IBI buffer that trigger the IBI_DATA_THLD_STAT interrupt. + 12 + 3 + read-write + + + REG_IBI_STATUS_BUF_THLD + NA + 18 + 3 + read-write + + + + + DATA_BUFFER_THLD_CTRL + NA + 0x20 + 0x20 + 0x00000009 + + + REG_TX_DATA_BUF_THLD + Transmit Buffer Threshold Value. This field controls the number of empty locations in the Transmit FIFO that trigger the TX_THLD_STAT interrupt. Supports values: 000:2 001:4 010:8 011:16 100:31, else:31 + 0 + 3 + read-write + + + REG_RX_DATA_BUF_THLD + Receive Buffer Threshold Value. This field controls the number of empty locations in the Receive FIFO that trigger the RX_THLD_STAT interrupt. Supports: 000:2 001:4 010:8 011:16 100:31, else:31 + 3 + 3 + read-write + + + + + IBI_NOTIFY_CTRL + NA + 0x24 + 0x20 + + + REG_NOTIFY_SIR_REJECTED + Notify Rejected Slave Interrupt Request Control. This bit is used to suppress reporting to the application about Slave Interrupt Request. 0:Suppress passing the IBI Status to the IBI FIFO(hence not notifying the application) when a SIR request is NACKed and auto-disabled base on the IBI_SIR_REQ_REJECT register. 1: Writes IBI Status to the IBI FIFO(hence notifying the application) when SIR request is NACKed and auto-disabled based on the IBI_SIR_REQ_REJECT registerl. + 2 + 1 + read-write + + + + + IBI_SIR_REQ_PAYLOAD + NA + 0x28 + 0x20 + + + REG_SIR_REQ_PAYLOAD + NA + 0 + 32 + read-write + + + + + IBI_SIR_REQ_REJECT + NA + 0x2C + 0x20 + + + REG_SIR_REQ_REJECT + The application of controller can decide whether to send ACK or NACK for Slave request received from any I3C device. A device specific response control bit is provided to select the response option, Master will ACK/NACK the Master Request based on programming of control bit, corresponding to the interrupting device. 0:ACK the SIR Request 1:NACK and send direct auto disable CCC + 0 + 32 + read-write + + + + + INT_CLR + NA + 0x30 + 0x20 + + + TX_DATA_BUF_THLD_INT_CLR + NA + 0 + 1 + write-only + + + RX_DATA_BUF_THLD_INT_CLR + NA + 1 + 1 + write-only + + + IBI_STATUS_THLD_INT_CLR + NA + 2 + 1 + write-only + + + CMD_BUF_EMPTY_THLD_INT_CLR + NA + 3 + 1 + write-only + + + RESP_READY_INT_CLR + NA + 4 + 1 + write-only + + + NXT_CMD_REQ_ERR_INT_CLR + NA + 5 + 1 + write-only + + + TRANSFER_ERR_INT_CLR + NA + 6 + 1 + write-only + + + TRANSFER_COMPLETE_INT_CLR + NA + 7 + 1 + write-only + + + COMMAND_DONE_INT_CLR + NA + 8 + 1 + write-only + + + DETECT_START_INT_CLR + NA + 9 + 1 + write-only + + + RESP_BUF_OVF_INT_CLR + NA + 10 + 1 + write-only + + + IBI_DATA_BUF_OVF_INT_CLR + NA + 11 + 1 + write-only + + + IBI_STATUS_BUF_OVF_INT_CLR + NA + 12 + 1 + write-only + + + IBI_HANDLE_DONE_INT_CLR + NA + 13 + 1 + write-only + + + IBI_DETECT_INT_CLR + NA + 14 + 1 + write-only + + + CMD_CCC_MISMATCH_INT_CLR + NA + 15 + 1 + write-only + + + + + INT_RAW + NA + 0x34 + 0x20 + 0x00000008 + + + TX_DATA_BUF_THLD_INT_RAW + NA + 0 + 1 + read-write + + + RX_DATA_BUF_THLD_INT_RAW + NA + 1 + 1 + read-write + + + IBI_STATUS_THLD_INT_RAW + NA + 2 + 1 + read-write + + + CMD_BUF_EMPTY_THLD_INT_RAW + NA + 3 + 1 + read-write + + + RESP_READY_INT_RAW + NA + 4 + 1 + read-write + + + NXT_CMD_REQ_ERR_INT_RAW + NA + 5 + 1 + read-write + + + TRANSFER_ERR_INT_RAW + NA + 6 + 1 + read-write + + + TRANSFER_COMPLETE_INT_RAW + NA + 7 + 1 + read-write + + + COMMAND_DONE_INT_RAW + NA + 8 + 1 + read-write + + + DETECT_START_INT_RAW + NA + 9 + 1 + read-write + + + RESP_BUF_OVF_INT_RAW + NA + 10 + 1 + read-write + + + IBI_DATA_BUF_OVF_INT_RAW + NA + 11 + 1 + read-write + + + IBI_STATUS_BUF_OVF_INT_RAW + NA + 12 + 1 + read-write + + + IBI_HANDLE_DONE_INT_RAW + NA + 13 + 1 + read-write + + + IBI_DETECT_INT_RAW + NA + 14 + 1 + read-write + + + CMD_CCC_MISMATCH_INT_RAW + NA + 15 + 1 + read-write + + + + + INT_ST + NA + 0x38 + 0x20 + + + TX_DATA_BUF_THLD_INT_ST + This interrupt is generated when number of empty locations in transmit buffer is greater than or equal to threshold value specified by TX_EMPTY_BUS_THLD field in DATA_BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of empty locations in transmit buffer is less than threshold value. + 0 + 1 + read-only + + + RX_DATA_BUF_THLD_INT_ST + This interrupt is generated when number of entries in receive buffer is greater than or equal to threshold value specified by RX_BUF_THLD field in DATA_BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of entries in receive buffer is less than threshold value. + 1 + 1 + read-only + + + IBI_STATUS_THLD_INT_ST + Only used in master mode. This interrupt is generated when number of entries in IBI buffer is greater than or equal to threshold value specified by IBI_BUF_THLD field in BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of entries in IBI buffer is less than threshold value. + 2 + 1 + read-only + + + CMD_BUF_EMPTY_THLD_INT_ST + This interrupt is generated when number of empty locations in command buffer is greater than or equal to threshold value specified by CMD_EMPTY_BUF_THLD field in BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of empty locations in command buffer is less than threshold value. + 3 + 1 + read-only + + + RESP_READY_INT_ST + This interrupt is generated when number of entries in response buffer is greater than or equal to threshold value specified by RESP_BUF_THLD field in BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of entries in response buffer is less than threshold value. + 4 + 1 + read-only + + + NXT_CMD_REQ_ERR_INT_ST + This interrupt is generated if toc is 0(master will restart next command), but command buf is empty. + 5 + 1 + read-only + + + TRANSFER_ERR_INT_ST + This interrupt is generated if any error occurs during transfer. The error type will be specified in the response packet associated with the command (in ERR_STATUS field of RESPONSE_BUFFER_PORT register). This bit can be cleared by writing 1'h1. + 6 + 1 + read-only + + + TRANSFER_COMPLETE_INT_ST + NA + 7 + 1 + read-only + + + COMMAND_DONE_INT_ST + NA + 8 + 1 + read-only + + + DETECT_START_INT_ST + NA + 9 + 1 + read-only + + + RESP_BUF_OVF_INT_ST + NA + 10 + 1 + read-only + + + IBI_DATA_BUF_OVF_INT_ST + NA + 11 + 1 + read-only + + + IBI_STATUS_BUF_OVF_INT_ST + NA + 12 + 1 + read-only + + + IBI_HANDLE_DONE_INT_ST + NA + 13 + 1 + read-only + + + IBI_DETECT_INT_ST + NA + 14 + 1 + read-only + + + CMD_CCC_MISMATCH_INT_ST + NA + 15 + 1 + read-only + + + + + INT_ST_ENA + The Interrupt status will be updated in INTR_STATUS register if corresponding Status Enable bit set. + 0x3C + 0x20 + + + TX_DATA_BUF_THLD_INT_ENA + Transmit Buffer threshold status enable. + 0 + 1 + read-write + + + RX_DATA_BUF_THLD_INT_ENA + Receive Buffer threshold status enable. + 1 + 1 + read-write + + + IBI_STATUS_THLD_INT_ENA + Only used in master mode. IBI Buffer threshold status enable. + 2 + 1 + read-write + + + CMD_BUF_EMPTY_THLD_INT_ENA + Command buffer ready status enable. + 3 + 1 + read-write + + + RESP_READY_INT_ENA + Response buffer ready status enable. + 4 + 1 + read-write + + + NXT_CMD_REQ_ERR_INT_ENA + next command request error status enable + 5 + 1 + read-write + + + TRANSFER_ERR_INT_ENA + Transfer error status enable + 6 + 1 + read-write + + + TRANSFER_COMPLETE_INT_ENA + NA + 7 + 1 + read-write + + + COMMAND_DONE_INT_ENA + NA + 8 + 1 + read-write + + + DETECT_START_INT_ENA + NA + 9 + 1 + read-write + + + RESP_BUF_OVF_INT_ENA + NA + 10 + 1 + read-write + + + IBI_DATA_BUF_OVF_INT_ENA + NA + 11 + 1 + read-write + + + IBI_STATUS_BUF_OVF_INT_ENA + NA + 12 + 1 + read-write + + + IBI_HANDLE_DONE_INT_ENA + NA + 13 + 1 + read-write + + + IBI_DETECT_INT_ENA + NA + 14 + 1 + read-write + + + CMD_CCC_MISMATCH_INT_ENA + NA + 15 + 1 + read-write + + + + + RESET_CTRL + NA + 0x44 + 0x20 + + + REG_CORE_SOFT_RST + NA + 0 + 1 + write-only + + + REG_CMD_BUF_RST + NA + 1 + 1 + read-write + + + REG_RESP_BUF_RST + NA + 2 + 1 + read-write + + + REG_TX_DATA_BUF_BUF_RST + NA + 3 + 1 + read-write + + + REG_RX_DATA_BUF_RST + NA + 4 + 1 + read-write + + + REG_IBI_DATA_BUF_RST + NA + 5 + 1 + read-write + + + REG_IBI_STATUS_BUF_RST + NA + 6 + 1 + read-write + + + + + BUFFER_STATUS_LEVEL + BUFFER_STATUS_LEVEL reflects the status level of Buffers in the controller. + 0x48 + 0x20 + 0x00000010 + + + CMD_BUF_EMPTY_CNT + Command Buffer Empty Locations contains the number of empty locations in the command buffer. + 0 + 5 + read-only + + + RESP_BUF_CNT + Response Buffer Level Value contains the number of valid data entries in the response buffer. + 8 + 4 + read-only + + + IBI_DATA_BUF_CNT + IBI Buffer Level Value contains the number of valid entries in the IBI Buffer. This is field is used in master mode. + 16 + 4 + read-only + + + IBI_STATUS_BUF_CNT + IBI Buffer Status Count contains the number of IBI status entries in the IBI Buffer. This field is used in master mode. + 24 + 4 + read-only + + + + + DATA_BUFFER_STATUS_LEVEL + DATA_BUFFER_STATUS_LEVEL reflects the status level of the Buffers in the controller. + 0x4C + 0x20 + 0x00000020 + + + TX_DATA_BUF_EMPTY_CNT + Transmit Buffer Empty Level Value contains the number of empty locations in the transmit Buffer. + 0 + 6 + read-only + + + RX_DATA_BUF_CNT + Receive Buffer Level value contains the number of valid data entries in the receive buffer. + 16 + 6 + read-only + + + + + PRESENT_STATE0 + NA + 0x50 + 0x20 + 0x00000003 + + + SDA_LVL + This bit is used to check the SCL line level to recover from error and for debugging. This bit reflects the value of synchronized scl_in_a. + 0 + 1 + read-only + + + SCL_LVL + This bit is used to check the SDA line level to recover from error and for debugging. This bit reflects the value of synchronized sda_in_a. + 1 + 1 + read-only + + + BUS_BUSY + NA + 2 + 1 + read-only + + + BUS_FREE + NA + 3 + 1 + read-only + + + CMD_TID + NA + 9 + 4 + read-only + + + SCL_GEN_FSM_STATE + NA + 13 + 3 + read-only + + + IBI_EV_HANDLE_FSM_STATE + NA + 16 + 3 + read-only + + + I2C_MODE_FSM_STATE + NA + 19 + 3 + read-only + + + SDR_MODE_FSM_STATE + NA + 22 + 4 + read-only + + + DAA_MODE_FSM_STATE + Reflects whether the Master Controller is in IDLE or not. This bit will be set when all the buffer(Command, Response, IBI, Transmit, Receive) are empty along with the Master State machine is in idle state. 0X0: not in idle 0x1: in idle + 26 + 3 + read-only + + + MAIN_FSM_STATE + NA + 29 + 3 + read-only + + + + + PRESENT_STATE1 + NA + 0x54 + 0x20 + + + DATA_BYTE_CNT + Present transfer data byte cnt: tx data byte cnt if write rx data byte cnt if read ibi data byte cnt if IBI handle. + 0 + 16 + read-only + + + + + DEVICE_TABLE + Pointer for Device Address Table + 0x58 + 0x20 + + + REG_DCT_DAA_INIT_INDEX + Reserved + 0 + 4 + read-write + + + REG_DAT_DAA_INIT_INDEX + NA + 4 + 4 + read-write + + + PRESENT_DCT_INDEX + NA + 8 + 4 + read-only + + + PRESENT_DAT_INDEX + NA + 12 + 4 + read-only + + + + + TIME_OUT_VALUE + NA + 0x5C + 0x20 + 0x00410410 + + + REG_RESP_BUF_TO_VALUE + NA + 0 + 5 + read-write + + + REG_RESP_BUF_TO_EN + NA + 5 + 1 + read-write + + + REG_IBI_DATA_BUF_TO_VALUE + NA + 6 + 5 + read-write + + + REG_IBI_DATA_BUF_TO_EN + NA + 11 + 1 + read-write + + + REG_IBI_STATUS_BUF_TO_VALUE + NA + 12 + 5 + read-write + + + REG_IBI_STATUS_BUF_TO_EN + NA + 17 + 1 + read-write + + + REG_RX_DATA_BUF_TO_VALUE + NA + 18 + 5 + read-write + + + REG_RX_DATA_BUF_TO_EN + NA + 23 + 1 + read-write + + + + + SCL_I3C_MST_OD_TIME + NA + 0x60 + 0x20 + 0x00050019 + + + REG_I3C_MST_OD_LOW_PERIOD + SCL Open-Drain low count for I3C transfers targeted to I3C devices. + 0 + 16 + read-write + + + REG_I3C_MST_OD_HIGH_PERIOD + SCL Open-Drain High count for I3C transfers targeted to I3C devices. + 16 + 16 + read-write + + + + + SCL_I3C_MST_PP_TIME + NA + 0x64 + 0x20 + 0x00050005 + + + REG_I3C_MST_PP_LOW_PERIOD + NA + 0 + 8 + read-write + + + REG_I3C_MST_PP_HIGH_PERIOD + NA + 16 + 8 + read-write + + + + + SCL_I2C_FM_TIME + NA + 0x68 + 0x20 + 0x004B00A3 + + + REG_I2C_FM_LOW_PERIOD + NA + 0 + 16 + read-write + + + REG_I2C_FM_HIGH_PERIOD + The SCL open-drain low count timing for I2C Fast Mode transfers. + 16 + 16 + read-write + + + + + SCL_I2C_FMP_TIME + NA + 0x6C + 0x20 + 0x0021003F + + + REG_I2C_FMP_LOW_PERIOD + NA + 0 + 16 + read-write + + + REG_I2C_FMP_HIGH_PERIOD + NA + 16 + 8 + read-write + + + + + SCL_EXT_LOW_TIME + NA + 0x70 + 0x20 + + + REG_I3C_MST_EXT_LOW_PERIOD1 + NA + 0 + 8 + read-write + + + REG_I3C_MST_EXT_LOW_PERIOD2 + NA + 8 + 8 + read-write + + + REG_I3C_MST_EXT_LOW_PERIOD3 + NA + 16 + 8 + read-write + + + REG_I3C_MST_EXT_LOW_PERIOD4 + NA + 24 + 8 + read-write + + + + + SDA_SAMPLE_TIME + NA + 0x74 + 0x20 + + + REG_SDA_OD_SAMPLE_TIME + It is used to adjust sda sample point when scl high under open drain speed + 0 + 9 + read-write + + + REG_SDA_PP_SAMPLE_TIME + It is used to adjust sda sample point when scl high under push pull speed + 9 + 5 + read-write + + + + + SDA_HOLD_TIME + NA + 0x78 + 0x20 + 0x00000001 + + + REG_SDA_OD_TX_HOLD_TIME + It is used to adjust sda drive point after scl neg under open drain speed + 0 + 9 + read-write + + + REG_SDA_PP_TX_HOLD_TIME + It is used to adjust sda dirve point after scl neg under push pull speed + 9 + 5 + read-write + + + + + SCL_START_HOLD + NA + 0x7C + 0x20 + 0x00000008 + + + REG_SCL_START_HOLD_TIME + I2C_SCL_START_HOLD_TIME + 0 + 9 + read-write + + + REG_START_DET_HOLD_TIME + NA + 9 + 2 + read-write + + + + + SCL_RSTART_SETUP + NA + 0x80 + 0x20 + 0x00000008 + + + REG_SCL_RSTART_SETUP_TIME + I2C_SCL_RSTART_SETUP_TIME + 0 + 9 + read-write + + + + + SCL_STOP_HOLD + NA + 0x84 + 0x20 + 0x00000008 + + + REG_SCL_STOP_HOLD_TIME + I2C_SCL_STOP_HOLD_TIME + 0 + 9 + read-write + + + + + SCL_STOP_SETUP + NA + 0x88 + 0x20 + 0x00000008 + + + REG_SCL_STOP_SETUP_TIME + I2C_SCL_STOP_SETUP_TIME + 0 + 9 + read-write + + + + + BUS_FREE_TIME + NA + 0x90 + 0x20 + 0x00000005 + + + REG_BUS_FREE_TIME + I3C Bus Free Count Value. This field is used only in Master mode. In pure Bus System, this field represents tCAS. In Mixed Bus System, this field is expected to be programmed to tLOW of I2C Timing. + 0 + 16 + read-write + + + + + SCL_TERMN_T_EXT_LOW_TIME + NA + 0x94 + 0x20 + 0x00000002 + + + REG_I3C_MST_TERMN_T_EXT_LOW_TIME + NA + 0 + 8 + read-write + + + + + VER_ID + NA + 0xA0 + 0x20 + 0x20230504 + + + REG_I3C_MST_VER_ID + This field indicates the controller current release number that is read by an application. + 0 + 32 + read-write + + + + + VER_TYPE + NA + 0xA4 + 0x20 + + + REG_I3C_MST_VER_TYPE + This field indicates the controller current release type that is read by an application. + 0 + 32 + read-write + + + + + FPGA_DEBUG_PROBE + NA + 0xAC + 0x20 + 0x00000001 + + + REG_I3C_MST_FPGA_DEBUG_PROBE + For Debug Probe Test on FPGA + 0 + 32 + read-write + + + + + RND_ECO_CS + NA + 0xB0 + 0x20 + + + REG_RND_ECO_EN + NA + 0 + 1 + read-write + + + RND_ECO_RESULT + NA + 1 + 1 + read-only + + + + + RND_ECO_LOW + NA + 0xB4 + 0x20 + + + REG_RND_ECO_LOW + NA + 0 + 32 + read-write + + + + + RND_ECO_HIGH + NA + 0xB8 + 0x20 + 0x0000FFFF + + + REG_RND_ECO_HIGH + NA + 0 + 32 + read-write + + + + + + + I3C_MST_MEM + I3C_MST_MEM Peripheral + I3C_MST_MEM + 0x500DA000 + + 0x0 + 0x108 + registers + + + + COMMAND_BUF_PORT + NA + 0x8 + 0x20 + + + REG_COMMAND + Contains a Command Descriptor structure that depends on the requested transfer type. Command Descriptor structure is used to schedule the transfers to devices on I3C bus. + 0 + 32 + read-write + + + + + RESPONSE_BUF_PORT + NA + 0xC + 0x20 + + + RESPONSE + The Response Buffer can be read through this register. The response status for each Command is written into the Response Buffer by the controller if ROC (Response On Completion) bit is set or if transfer error has occurred. The response buffer can be read through this register. + 0 + 32 + read-only + + + + + RX_DATA_PORT + NA + 0x10 + 0x20 + + + RX_DATA_PORT + Receive Data Port. Receive data is mapped to the Rx-data buffer and receive data is always packed in 4-byte aligned data words. If the length of data transfer is not aligned to 4-bytes boundary, then there will be extra(unused) bytes(the additional data bytes have to be ignored) at the end of the transferred data. The valid data must be identified using the DATA_LENGTH filed in the Response Descriptor. + 0 + 32 + read-only + + + + + TX_DATA_PORT + NA + 0x14 + 0x20 + + + REG_TX_DATA_PORT + Transmit Data Port. Transmit data is mapped to the Tx-data buffer and transmit data is always packed in 4-byte aligned data words. If the length of data transfer is not aligned to 4-bytes boundary, then there will be extra(unused) bytes(the additional data bytes have to be ignored) at the end of the transferred data. The valid data must be identified using the DATA_LENGTH filed in the Response Descriptor. + 0 + 32 + read-write + + + + + IBI_STATUS_BUF + In-Band Interrupt Buffer Status/Data Register. When receiving an IBI, IBI_PORT is used to both: Read the IBI Status Read the IBI Data(which is raw/opaque data) + 0x18 + 0x20 + + + DATA_LENGTH + This field represents the length of data received along with IBI, in bytes. + 0 + 8 + read-only + + + IBI_ID + IBI Identifier. The byte received after START which includes the address the R/W bit: Device address and R/W bit in case of Slave Interrupt or Master Request. + 8 + 8 + read-only + + + IBI_STS + IBI received data/status. IBI Data register is mapped to the IBI Buffer. The IBI Data is always packed in4-byte aligned and put to the IBI Buffer. This register When read from, reads the data from the IBI buffer. IBI Status register when read from, returns the data from the IBI Buffer and indicates how the controller responded to incoming IBI(SIR, MR and HJ). + 28 + 1 + read-only + + + + + IBI_DATA_BUF + NA + 0x40 + 0x20 + + + IBI_DATA + NA + 0 + 32 + read-only + + + + + DEV_ADDR_TABLE1_LOC + NA + 0xC0 + 0x20 + + + REG_DAT_DEV1_STATIC_ADDR + NA + 0 + 7 + read-write + + + REG_DAT_DEV1_DYNAMIC_ADDR + Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. + 16 + 8 + read-write + + + REG_DAT_DEV1_NACK_RETRY_CNT + This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. + 29 + 2 + read-write + + + REG_DAT_DEV1_I2C + Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. + 31 + 1 + read-write + + + + + DEV_ADDR_TABLE2_LOC + NA + 0xC4 + 0x20 + + + REG_DAT_DEV2_STATIC_ADDR + NA + 0 + 7 + read-write + + + REG_DAT_DEV2_DYNAMIC_ADDR + Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. + 16 + 8 + read-write + + + REG_DAT_DEV2_NACK_RETRY_CNT + This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. + 29 + 2 + read-write + + + REG_DAT_DEV2_I2C + Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. + 31 + 1 + read-write + + + + + DEV_ADDR_TABLE3_LOC + NA + 0xC8 + 0x20 + + + REG_DAT_DEV3_STATIC_ADDR + NA + 0 + 7 + read-write + + + REG_DAT_DEV3_DYNAMIC_ADDR + Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. + 16 + 8 + read-write + + + REG_DAT_DEV3_NACK_RETRY_CNT + This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. + 29 + 2 + read-write + + + REG_DAT_DEV3_I2C + Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. + 31 + 1 + read-write + + + + + DEV_ADDR_TABLE4_LOC + NA + 0xCC + 0x20 + + + REG_DAT_DEV4_STATIC_ADDR + NA + 0 + 7 + read-write + + + REG_DAT_DEV4_DYNAMIC_ADDR + Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. + 16 + 8 + read-write + + + REG_DAT_DEV4_NACK_RETRY_CNT + This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. + 29 + 2 + read-write + + + REG_DAT_DEV4_I2C + Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. + 31 + 1 + read-write + + + + + DEV_ADDR_TABLE5_LOC + NA + 0xD0 + 0x20 + + + REG_DAT_DEV5_STATIC_ADDR + NA + 0 + 7 + read-write + + + REG_DAT_DEV5_DYNAMIC_ADDR + Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. + 16 + 8 + read-write + + + REG_DAT_DEV5_NACK_RETRY_CNT + This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. + 29 + 2 + read-write + + + REG_DAT_DEV5_I2C + Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. + 31 + 1 + read-write + + + + + DEV_ADDR_TABLE6_LOC + NA + 0xD4 + 0x20 + + + REG_DAT_DEV6_STATIC_ADDR + NA + 0 + 7 + read-write + + + REG_DAT_DEV6_DYNAMIC_ADDR + Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. + 16 + 8 + read-write + + + REG_DAT_DEV6_NACK_RETRY_CNT + This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. + 29 + 2 + read-write + + + REG_DAT_DEV6_I2C + Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. + 31 + 1 + read-write + + + + + DEV_ADDR_TABLE7_LOC + NA + 0xD8 + 0x20 + + + REG_DAT_DEV7_STATIC_ADDR + NA + 0 + 7 + read-write + + + REG_DAT_DEV7_DYNAMIC_ADDR + Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. + 16 + 8 + read-write + + + REG_DAT_DEV7_NACK_RETRY_CNT + This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. + 29 + 2 + read-write + + + REG_DAT_DEV7_I2C + Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. + 31 + 1 + read-write + + + + + DEV_ADDR_TABLE8_LOC + NA + 0xDC + 0x20 + + + REG_DAT_DEV8_STATIC_ADDR + NA + 0 + 7 + read-write + + + REG_DAT_DEV8_DYNAMIC_ADDR + Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. + 16 + 8 + read-write + + + REG_DAT_DEV8_NACK_RETRY_CNT + This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. + 29 + 2 + read-write + + + REG_DAT_DEV8_I2C + Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. + 31 + 1 + read-write + + + + + DEV_ADDR_TABLE9_LOC + NA + 0xE0 + 0x20 + + + REG_DAT_DEV9_STATIC_ADDR + NA + 0 + 7 + read-write + + + REG_DAT_DEV9_DYNAMIC_ADDR + Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. + 16 + 8 + read-write + + + REG_DAT_DEV9_NACK_RETRY_CNT + This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. + 29 + 2 + read-write + + + REG_DAT_DEV9_I2C + Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. + 31 + 1 + read-write + + + + + DEV_ADDR_TABLE10_LOC + NA + 0xE4 + 0x20 + + + REG_DAT_DEV10_STATIC_ADDR + NA + 0 + 7 + read-write + + + REG_DAT_DEV10_DYNAMIC_ADDR + Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. + 16 + 8 + read-write + + + REG_DAT_DEV10_NACK_RETRY_CNT + This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. + 29 + 2 + read-write + + + REG_DAT_DEV10_I2C + Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. + 31 + 1 + read-write + + + + + DEV_ADDR_TABLE11_LOC + NA + 0xE8 + 0x20 + + + REG_DAT_DEV11_STATIC_ADDR + NA + 0 + 7 + read-write + + + REG_DAT_DEV11_DYNAMIC_ADDR + Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. + 16 + 8 + read-write + + + REG_DAT_DEV11_NACK_RETRY_CNT + This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. + 29 + 2 + read-write + + + REG_DAT_DEV11_I2C + Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. + 31 + 1 + read-write + + + + + DEV_ADDR_TABLE12_LOC + NA + 0xEC + 0x20 + + + REG_DAT_DEV12_STATIC_ADDR + NA + 0 + 7 + read-write + + + REG_DAT_DEV12_DYNAMIC_ADDR + Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. + 16 + 8 + read-write + + + REG_DAT_DEV12_NACK_RETRY_CNT + This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. + 29 + 2 + read-write + + + REG_DAT_DEV12_I2C + Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. + 31 + 1 + read-write + + + + + DEV_CHAR_TABLE1_LOC1 + NA + 0x100 + 0x20 + + + DCT_DEV1_LOC1 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE1_LOC2 + NA + 0x104 + 0x20 + + + DCT_DEV1_LOC2 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE1_LOC3 + NA + 0x108 + 0x20 + + + DCT_DEV1_LOC3 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE1_LOC4 + NA + 0x10C + 0x20 + + + DCT_DEV1_LOC4 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE2_LOC1 + NA + 0x110 + 0x20 + + + DCT_DEV2_LOC1 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE2_LOC2 + NA + 0x114 + 0x20 + + + DCT_DEV2_LOC2 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE2_LOC3 + NA + 0x118 + 0x20 + + + DCT_DEV2_LOC3 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE2_LOC4 + NA + 0x11C + 0x20 + + + DCT_DEV2_LOC4 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE3_LOC1 + NA + 0x120 + 0x20 + + + DCT_DEV3_LOC1 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE3_LOC2 + NA + 0x124 + 0x20 + + + DCT_DEV3_LOC2 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE3_LOC3 + NA + 0x128 + 0x20 + + + DCT_DEV3_LOC3 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE3_LOC4 + NA + 0x12C + 0x20 + + + DCT_DEV3_LOC4 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE4_LOC1 + NA + 0x130 + 0x20 + + + DCT_DEV4_LOC1 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE4_LOC2 + NA + 0x134 + 0x20 + + + DCT_DEV4_LOC2 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE4_LOC3 + NA + 0x138 + 0x20 + + + DCT_DEV4_LOC3 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE4_LOC4 + NA + 0x13C + 0x20 + + + DCT_DEV4_LOC4 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE5_LOC1 + NA + 0x140 + 0x20 + + + DCT_DEV5_LOC1 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE5_LOC2 + NA + 0x144 + 0x20 + + + DCT_DEV5_LOC2 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE5_LOC3 + NA + 0x148 + 0x20 + + + DCT_DEV5_LOC3 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE5_LOC4 + NA + 0x14C + 0x20 + + + DCT_DEV5_LOC4 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE6_LOC1 + NA + 0x150 + 0x20 + + + DCT_DEV6_LOC1 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE6_LOC2 + NA + 0x154 + 0x20 + + + DCT_DEV6_LOC2 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE6_LOC3 + NA + 0x158 + 0x20 + + + DCT_DEV6_LOC3 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE6_LOC4 + NA + 0x15C + 0x20 + + + DCT_DEV6_LOC4 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE7_LOC1 + NA + 0x160 + 0x20 + + + DCT_DEV7_LOC1 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE7_LOC2 + NA + 0x164 + 0x20 + + + DCT_DEV7_LOC2 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE7_LOC3 + NA + 0x168 + 0x20 + + + DCT_DEV7_LOC3 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE7_LOC4 + NA + 0x16C + 0x20 + + + DCT_DEV7_LOC4 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE8_LOC1 + NA + 0x170 + 0x20 + + + DCT_DEV8_LOC1 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE8_LOC2 + NA + 0x174 + 0x20 + + + DCT_DEV8_LOC2 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE8_LOC3 + NA + 0x178 + 0x20 + + + DCT_DEV8_LOC3 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE8_LOC4 + NA + 0x17C + 0x20 + + + DCT_DEV8_LOC4 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE9_LOC1 + NA + 0x180 + 0x20 + + + DCT_DEV9_LOC1 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE9_LOC2 + NA + 0x184 + 0x20 + + + DCT_DEV9_LOC2 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE9_LOC3 + NA + 0x188 + 0x20 + + + DCT_DEV9_LOC3 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE9_LOC4 + NA + 0x18C + 0x20 + + + DCT_DEV9_LOC4 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE10_LOC1 + NA + 0x190 + 0x20 + + + DCT_DEV10_LOC1 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE10_LOC2 + NA + 0x194 + 0x20 + + + DCT_DEV10_LOC2 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE10_LOC3 + NA + 0x198 + 0x20 + + + DCT_DEV10_LOC3 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE10_LOC4 + NA + 0x19C + 0x20 + + + DCT_DEV10_LOC4 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE11_LOC1 + NA + 0x1A0 + 0x20 + + + DCT_DEV11_LOC1 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE11_LOC2 + NA + 0x1A4 + 0x20 + + + DCT_DEV11_LOC2 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE11_LOC3 + NA + 0x1A8 + 0x20 + + + DCT_DEV11_LOC3 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE11_LOC4 + NA + 0x1AC + 0x20 + + + DCT_DEV11_LOC4 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE12_LOC1 + NA + 0x1B0 + 0x20 + + + DCT_DEV12_LOC1 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE12_LOC2 + NA + 0x1B4 + 0x20 + + + DCT_DEV12_LOC2 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE12_LOC3 + NA + 0x1B8 + 0x20 + + + DCT_DEV12_LOC3 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE12_LOC4 + NA + 0x1BC + 0x20 + + + DCT_DEV12_LOC4 + NA + 0 + 32 + read-only + + + + + + + I3C_SLV + I3C Controller (Slave) + I3C_SLV + 0x500DB000 + + 0x0 + 0x40 + registers + + + I3C_SLV + 102 + + + + CONFIG + NA + 0x4 + 0x20 + 0x002F0001 + + + SLVENA + 1: allow the slave to operate on i2c or i3c bus. 0: the slave will ignore the bus. This should be not set until registers such as PARTNO, IDEXT and the like are set 1st -if used- since they impact data to the master + 0 + 1 + read-write + + + NACK + 1:the slave will NACK all requests to it except CCC broadcast. This should be used with caution as the Master may determine the slave is missing if overused. + 1 + 1 + read-write + + + MATCHSS + 1: the START and STOP sticky STATUS bits will only be set if MATCHED is set..This allows START and STOP to be used to detect end of a message to /from this slave. + 2 + 1 + read-write + + + S0IGNORE + If 1, the Slave will not detect S0 or S1 errors and so not lock up waiting on an Exit Pattern. This should only be used when the bus will not use HDR. + 3 + 1 + read-write + + + DDROK + NA + 4 + 1 + read-write + + + IDRAND + NA + 8 + 1 + read-write + + + OFFLINE + NA + 9 + 1 + read-write + + + BAMATCH + Bus Available condition match value for current ???Slow clock???. This provides the count of the slow clock to count out 1us (or more) to allow an IBI to drive SDA Low when the Master is not doing so. The max width , and so max value, is controlled by the block. Only if enabled for events such IBI or MR or HJ, and if enabled to provide this as a register. With is limited to CLK_SLOW_BITS + 16 + 8 + read-write + + + SADDR + If allowed by the block:sets i2c 7 bits static address,else should be 0. If enabled to use one and to be provided by SW. Block may provide in HW as well. + 25 + 7 + read-write + + + + + STATUS + NA + 0x8 + 0x20 + + + STNOTSTOP + Is 1 if bus is busy(activity) and 0 when in a STOP condition. Other bits may also set when busy. Note that this can also be true from an S0 or S1 error, which waits for an Exit Pattern. + 0 + 1 + read-only + + + STMSG + Is 1 if this bus Slave is listening to the bus traffic or repsonding, If STNOSTOP=1, then this will be 0 when a non-matching address seen until next respeated START it STOP. + 1 + 1 + read-only + + + STCCCH + Is 1 if a CCC message is being handled automatically. + 2 + 1 + read-only + + + STREQRD + 1 if the req in process is an sdr read from this slave or an IBI is being pushed out, + 3 + 1 + read-only + + + STREQWR + NA + 4 + 1 + read-only + + + STDAA + NA + 5 + 1 + read-only + + + STHDR + NA + 6 + 1 + read-only + + + START + NA + 8 + 1 + read-write + + + MATCHED + NA + 9 + 1 + read-write + + + STOP + NA + 10 + 1 + read-write + + + RXPEND + Receiving a message from master,which is not being handled by block(not a CCC internally processed). For all but External FIFO, this uses DATACTRL RXTRIG, which defaults to not-empty. If DMA is enabled for RX, DMA will be signaled as well. Will self-clear if data is read(FIFO and non-FIFO) + 11 + 1 + read-only + + + TXNOTFULL + Is 1 when the To-bus buffer/FIFO can accept more data to go out. Defau:1. For all but External FIFO, this uses DATACTRL TXTRIG,which defaults to not-full. If DMA is enabled for TX, it will also be signaled to provide more. + 12 + 1 + read-only + + + DACHG + The Slv Dynamic Address has been assigned, reassigned, or reset(lost) and is now in that state of being valid or none. Actual DA can be seen in the DYNADDR register. Note that this will also be used when MAP Auto feature is configured. This will be changing one or more MAP items. See DYNADDR and/or MAPCTRLn. DYNAADDR for the main DA(0) will indicate if last change was due to Auto MAP. + 13 + 1 + read-write + + + CCC + A common -command-code(CCC), not handled by block, has been received. This acts differently between: *Broadcasted ones, which will then also correspond with RXPEND and the 1st byte will be the CCC(command) . *Direct ones, which may never be directed to this device. If it is, then the TXSEND or RXPEND will be triggered with this end the RXPEND will contain the command. + 14 + 1 + read-write + + + ERRWARN + NA + 15 + 1 + read-only + + + HDRMATCH + NA + 16 + 1 + read-write + + + + + CTRL + NA + 0xC + 0x20 + + + SLV_EVENT + If set to non-0, will request an event. Once requested, STATUS.EVENT and EVDET will show the status as it progresses. Once completed, the field will automatically return to 0. Once non-0, only 0 can be written(to cancel) until done. 0: Normal mode. If set to 0 after was a non-0 value, will cancel if not already in flight. 1: start an IBI. This will try to push through an IBI on the bus. If data associate with the IBI, it will be drawn from the IBIDATA field. Note that if Time control is enabled, this will include anytime control related bytes further, the IBIDATA byte will have bit7 set to 1. + 0 + 2 + read-write + + + EXTDATA + reserved + 3 + 1 + read-write + + + MAPIDX + Index of Dynamic Address that IBI is for. This is 0 for the main or base Dynamic Address, or can be any valid index. + 4 + 4 + read-write + + + IBIDATA + Data byte to go with an IBI, if enabled for it. If enabled (was in BCR), then it is required. + 8 + 8 + read-write + + + PENDINT + Should be set to the pending interrupt that GETSTATUS CCC will return. This should be maintained by the application if used and configured, as the Master will read this. If not configured, the GETSTATUS field will return 1 if an IBI is pending, and 0 otherwise. + 16 + 4 + read-write + + + ACTSTATE + NA + 20 + 2 + read-write + + + VENDINFO + NA + 24 + 8 + read-write + + + + + INTSET + INSET allows setting enables for interrupts(connecting the corresponding STATUS source to causing an IRQ to the processor) + 0x10 + 0x20 + + + STOP_ENA + Interrupt on STOP state on the bus. See Start as the preferred interrupt when needed. This interrupt may not trigger for quick STOP/START combination, as it relates to the state of being stopped. + 10 + 1 + read-write + + + RXPEND_ENA + Interrupt when receiving a message from Master, which is not being handled by the block (excludes CCCs being handled automatically). If FIFO, then RX fullness trigger. If DMA, then message end. + 11 + 1 + read-write + + + TXSEND_ENA + NA + 12 + 1 + read-write + + + + + INTCLR + NA + 0x14 + 0x20 + + + STOP_CLR + Interrupt on STOP state on the bus. See Start as the preferred interrupt when needed. This interrupt may not trigger for quick STOP/START combination, as it relates to the state of being stopped. + 10 + 1 + write-only + + + RXPEND_CLR + Interrupt when receiving a message from Master, which is not being handled by the block (excludes CCCs being handled automatically). If FIFO, then RX fullness trigger. If DMA, then message end. + 11 + 1 + write-only + + + TXSEND_CLR + NA + 12 + 1 + write-only + + + + + INTMASKED + NA + 0x18 + 0x20 + + + STOP_MASK + Interrupt on STOP state on the bus. See Start as the preferred interrupt when needed. This interrupt may not trigger for quick STOP/START combination, as it relates to the state of being stopped. + 10 + 1 + read-only + + + RXPEND_MASK + Interrupt when receiving a message from Master, which is not being handled by the block (excludes CCCs being handled automatically). If FIFO, then RX fullness trigger. If DMA, then message end. + 11 + 1 + read-only + + + TXSEND_MASK + NA + 12 + 1 + read-only + + + + + DATACTRL + NA + 0x2C + 0x20 + 0x000000B0 + + + FLUSHTB + Flushes the from-bus buffer/FIFO. Not normally used + 0 + 1 + write-only + + + FLUSHFB + Flushes the to-bus buffer/FIFO. Used when Master terminates a to-bus (read) message prematurely + 1 + 1 + write-only + + + UNLOCK + If this bit is not written 1, the register bits from 7 to 4 are not changed on write. + 3 + 1 + write-only + + + TXTRIG + Trigger level for tx emptiness when FIFOed, Affects interrupt and DMA(if enabled). The defaults is 3 + 4 + 2 + read-write + + + RXTRIG + Trigger level for rx fulless when FIFOed, Affects interrupt and DMA(if enabled). The defaults is 3 + 6 + 2 + read-write + + + TXCOUNT + NA + 16 + 5 + read-only + + + RXCOUNT + NA + 24 + 5 + read-only + + + TXFULL + NA + 30 + 1 + read-only + + + RXEMPTY + NA + 31 + 1 + read-only + + + + + WDATAB + NA + 0x30 + 0x20 + + + WDATAB + NA + 0 + 8 + write-only + + + WDATA_END + NA + 8 + 1 + write-only + + + + + WDATABE + NA + 0x34 + 0x20 + + + WDATABE + NA + 0 + 8 + write-only + + + + + RDARAB + Read Byte Data (from-bus) register + 0x40 + 0x20 + + + DATA0 + This register allows reading a byte from the bus unless external FIFO is used. A byte should not be read unless there is data waiting, as indicated by the RXPEND bit being set in the STATUS register + 0 + 8 + read-only + + + + + RDATAH + Read Half-word Data (from-bus) register + 0x48 + 0x20 + + + DATA_LSB + NA + 0 + 8 + read-only + + + DATA_MSB + This register allows reading a Half-word (byte pair) from the bus unless external FIFO is used. A Half-word should not be read unless there is at least 2 bytes of data waiting, as indicated by the RX FIFO level trigger or RXCOUNT available space in the DATACTRL register + 8 + 8 + read-only + + + + + CAPABILITIES2 + NA + 0x5C + 0x20 + 0x00000100 + + + CAPABLITIES2 + NA + 0 + 32 + read-only + + + + + CAPABILITIES + NA + 0x60 + 0x20 + 0x7C13FC1C + + + CAPABLITIES + NA + 0 + 32 + read-only + + + + + IDPARTNO + NA + 0x6C + 0x20 + + + PARTNO + NA + 0 + 32 + read-write + + + + + IDEXT + NA + 0x70 + 0x20 + + + IDEXT + NA + 0 + 32 + read-write + + + + + VENDORID + NA + 0x74 + 0x20 + 0x00005550 + + + VID + NA + 0 + 15 + read-write + + + + + + + AXI_ICM + AXI_ICM Peripheral + ICM_AXI + 0x500A4000 + + 0x0 + 0x10 + registers + + + + VERID_FILEDS + NA + 0x0 + 0x20 + 0x3430342A + + + ICM_REG_VERID + NA + 0 + 32 + read-only + + + + + HW_CFG + NA + 0x4 + 0x20 + 0x0070D151 + + + ICM_REG_AXI_HWCFG_QOS_SUPPORT + NA + 0 + 1 + read-only + + + ICM_REG_AXI_HWCFG_APB3_SUPPORT + NA + 1 + 1 + read-only + + + ICM_REG_AXI_HWCFG_AXI4_SUPPORT + NA + 2 + 1 + read-only + + + ICM_REG_AXI_HWCFG_LOCK_EN + NA + 3 + 1 + read-only + + + ICM_REG_AXI_HWCFG_TRUST_ZONE_EN + NA + 4 + 1 + read-only + + + ICM_REG_AXI_HWCFG_DECODER_TYPE + NA + 5 + 1 + read-only + + + ICM_REG_AXI_HWCFG_REMAP_EN + NA + 6 + 1 + read-only + + + ICM_REG_AXI_HWCFG_BI_DIR_CMD_EN + NA + 7 + 1 + read-only + + + ICM_REG_AXI_HWCFG_LOW_POWER_INF_EN + NA + 8 + 1 + read-only + + + ICM_REG_AXI_HWCFG_AXI_NUM_MASTERS + NA + 12 + 5 + read-only + + + ICM_REG_AXI_HWCFG_AXI_NUM_SLAVES + NA + 20 + 5 + read-only + + + + + CMD + NA + 0x8 + 0x20 + + + ICM_REG_AXI_CMD + NA + 0 + 3 + read-write + + + ICM_REG_RD_WR_CHAN + NA + 7 + 1 + read-write + + + ICM_REG_AXI_MASTER_PORT + NA + 8 + 4 + read-write + + + ICM_REG_AXI_ERR_BIT + NA + 28 + 1 + read-only + + + ICM_REG_AXI_SOFT_RESET_BIT + NA + 29 + 1 + read-write + + + ICM_REG_AXI_RD_WR_CMD + NA + 30 + 1 + read-write + + + ICM_REG_AXI_CMD_EN + NA + 31 + 1 + read-write + + + + + DATA + NA + 0xC + 0x20 + + + ICM_REG_DATA + NA + 0 + 32 + read-write + + + + + + + IO_MUX + Input/Output Multiplexer + IO_MUX + 0x500E1000 + + 0x0 + 0xE8 + registers + + + + DATE + iomux version + 0x104 + 0x20 + 0x00201222 + + + DATE + csv date + 0 + 28 + read-write + + + + + 54 + 0x4 + 0-53 + GPIO%s + IO_MUX Control Register + 0x4 + 0x20 + read-write + + + MCU_OE + Configures whether or not to enable the output of GPIOn in sleep mode. 0: Disable 1: Enable + 0 + 1 + + + SLP_SEL + Configures whether or not to enter sleep mode for GPIOn. 0: Not enter 1: Enter + 1 + 1 + + + MCU_WPD + Configure whether or not to enable pull-down resistor of GPIOn during sleep mode. 0: Disable 1: Enable + 2 + 1 + + + MCU_WPU + Configures whether or not to enable pull-up resistor of GPIOn during sleep mode. 0: Disable 1: Enable + 3 + 1 + + + MCU_IE + Configures whether or not to enable the input of GPIOn during sleep mode. 0: Disable 1: Enable + 4 + 1 + + + MCU_DRV + Configures the drive strength of GPIOn during sleep mode. 0: ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA + 5 + 2 + + + FUN_WPD + Configures whether or not to enable pull-down resistor of GPIOn. 0: Disable 1: Enable + 7 + 1 + + + FUN_WPU + Configures whether or not enable pull-up resistor of GPIOn. 0: Disable 1: Enable + 8 + 1 + + + FUN_IE + Configures whether or not to enable input of GPIOn. 0: Disable 1: Enable + 9 + 1 + + + FUN_DRV + Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA + 10 + 2 + + + MCU_SEL + Configures to select IO MUX function for this pin. 0: Select Function 0 1: Select Function 1 ...... + 12 + 3 + + + FILTER_EN + Configures whether or not to enable filter for pin input signals. 0: Disable 1: Enable + 15 + 1 + + + + + + + ISP + ISP Peripheral + ISP + 0x500A1000 + + 0x0 + 0x244 + registers + + + ISP + 100 + + + + VER_DATE + version control register + 0x0 + 0x20 + 0x20210608 + + + VER_DATA + csv version + 0 + 32 + read-write + + + + + CLK_EN + isp clk control register + 0x4 + 0x20 + + + CLK_EN + this bit configures the clk force on of isp reg. 0: disable, 1: enable + 0 + 1 + read-write + + + CLK_BLC_FORCE_ON + this bit configures the clk force on of blc. 0: disable, 1: enable + 1 + 1 + read-write + + + CLK_DPC_FORCE_ON + this bit configures the clk force on of dpc. 0: disable, 1: enable + 2 + 1 + read-write + + + CLK_BF_FORCE_ON + this bit configures the clk force on of bf. 0: disable, 1: enable + 3 + 1 + read-write + + + CLK_LSC_FORCE_ON + this bit configures the clk force on of lsc. 0: disable, 1: enable + 4 + 1 + read-write + + + CLK_DEMOSAIC_FORCE_ON + this bit configures the clk force on of demosaic. 0: disable, 1: enable + 5 + 1 + read-write + + + CLK_MEDIAN_FORCE_ON + this bit configures the clk force on of median. 0: disable, 1: enable + 6 + 1 + read-write + + + CLK_CCM_FORCE_ON + this bit configures the clk force on of ccm. 0: disable, 1: enable + 7 + 1 + read-write + + + CLK_GAMMA_FORCE_ON + this bit configures the clk force on of gamma. 0: disable, 1: enable + 8 + 1 + read-write + + + CLK_RGB2YUV_FORCE_ON + this bit configures the clk force on of rgb2yuv. 0: disable, 1: enable + 9 + 1 + read-write + + + CLK_SHARP_FORCE_ON + this bit configures the clk force on of sharp. 0: disable, 1: enable + 10 + 1 + read-write + + + CLK_COLOR_FORCE_ON + this bit configures the clk force on of color. 0: disable, 1: enable + 11 + 1 + read-write + + + CLK_YUV2RGB_FORCE_ON + this bit configures the clk force on of yuv2rgb. 0: disable, 1: enable + 12 + 1 + read-write + + + CLK_AE_FORCE_ON + this bit configures the clk force on of ae. 0: disable, 1: enable + 13 + 1 + read-write + + + CLK_AF_FORCE_ON + this bit configures the clk force on of af. 0: disable, 1: enable + 14 + 1 + read-write + + + CLK_AWB_FORCE_ON + this bit configures the clk force on of awb. 0: disable, 1: enable + 15 + 1 + read-write + + + CLK_HIST_FORCE_ON + this bit configures the clk force on of hist. 0: disable, 1: enable + 16 + 1 + read-write + + + CLK_MIPI_IDI_FORCE_ON + this bit configures the clk force on of mipi idi input. 0: disable, 1: enable + 17 + 1 + read-write + + + ISP_MEM_CLK_FORCE_ON + this bit configures the clk force on of all isp memory. 0: disable, 1: enable + 18 + 1 + read-write + + + + + CNTL + isp module enable control register + 0x8 + 0x20 + 0x40002442 + + + MIPI_DATA_EN + this bit configures mipi input data enable. 0: disable, 1: enable + 0 + 1 + read-write + + + ISP_EN + this bit configures isp global enable. 0: disable, 1: enable + 1 + 1 + read-write + + + BLC_EN + this bit configures blc enable. 0: disable, 1: enable + 2 + 1 + read-write + + + DPC_EN + this bit configures dpc enable. 0: disable, 1: enable + 3 + 1 + read-write + + + BF_EN + this bit configures bf enable. 0: disable, 1: enable + 4 + 1 + read-write + + + LSC_EN + this bit configures lsc enable. 0: disable, 1: enable + 5 + 1 + read-write + + + DEMOSAIC_EN + this bit configures demosaic enable. 0: disable, 1: enable + 6 + 1 + read-write + + + MEDIAN_EN + this bit configures median enable. 0: disable, 1: enable + 7 + 1 + read-write + + + CCM_EN + this bit configures ccm enable. 0: disable, 1: enable + 8 + 1 + read-write + + + GAMMA_EN + this bit configures gamma enable. 0: disable, 1: enable + 9 + 1 + read-write + + + RGB2YUV_EN + this bit configures rgb2yuv enable. 0: disable, 1: enable + 10 + 1 + read-write + + + SHARP_EN + this bit configures sharp enable. 0: disable, 1: enable + 11 + 1 + read-write + + + COLOR_EN + this bit configures color enable. 0: disable, 1: enable + 12 + 1 + read-write + + + YUV2RGB_EN + this bit configures yuv2rgb enable. 0: disable, 1: enable + 13 + 1 + read-write + + + AE_EN + this bit configures ae enable. 0: disable, 1: enable + 14 + 1 + read-write + + + AF_EN + this bit configures af enable. 0: disable, 1: enable + 15 + 1 + read-write + + + AWB_EN + this bit configures awb enable. 0: disable, 1: enable + 16 + 1 + read-write + + + HIST_EN + this bit configures hist enable. 0: disable, 1: enable + 17 + 1 + read-write + + + BYTE_ENDIAN_ORDER + select input idi data byte_endian_order when isp is bypass, 0: csi_data[31:0], 1: {[7:0], [15:8], [23:16], [31:24]} + 24 + 1 + read-write + + + ISP_DATA_TYPE + this field configures input data type, 0:RAW8 1:RAW10 2:RAW12 + 25 + 2 + read-write + + + ISP_IN_SRC + this field configures input data source, 0:CSI HOST 1:CAM 2:DMA + 27 + 2 + read-write + + + ISP_OUT_TYPE + this field configures pixel output type, 0: RAW8 1: YUV422 2: RGB888 3: YUV420 4: RGB565 + 29 + 3 + read-write + + + + + HSYNC_CNT + header hsync interval control register + 0xC + 0x20 + 0x00000007 + + + HSYNC_CNT + this field configures the number of clock before hsync and after vsync and line_end when decodes pix data from idi to isp + 0 + 8 + read-write + + + + + FRAME_CFG + frame control parameter register + 0x10 + 0x20 + 0x601E01E0 + + + VADR_NUM + this field configures input image size in y-direction, image row number - 1 + 0 + 12 + read-write + + + HADR_NUM + this field configures input image size in x-direction, image line number - 1 + 12 + 12 + read-write + + + BAYER_MODE + this field configures the bayer mode of input pixel. 00 : BG/GR 01 : GB/RG 10 : GR/BG 11 : RG/GB + 27 + 2 + read-write + + + HSYNC_START_EXIST + this bit configures the line end packet exist or not. 0: not exist, 1: exist + 29 + 1 + read-write + + + HSYNC_END_EXIST + this bit configures the line start packet exist or not. 0: not exist, 1: exist + 30 + 1 + read-write + + + + + CCM_COEF0 + ccm coef register 0 + 0x14 + 0x20 + 0x02500740 + + + CCM_RR + this field configures the color correction matrix coefficient + 0 + 13 + read-write + + + CCM_RG + this field configures the color correction matrix coefficient + 13 + 13 + read-write + + + + + CCM_COEF1 + ccm coef register 1 + 0x18 + 0x20 + 0x022810C0 + + + CCM_RB + this field configures the color correction matrix coefficient + 0 + 13 + read-write + + + CCM_GR + this field configures the color correction matrix coefficient + 13 + 13 + read-write + + + + + CCM_COEF3 + ccm coef register 3 + 0x1C + 0x20 + 0x02200680 + + + CCM_GG + this field configures the color correction matrix coefficient + 0 + 13 + read-write + + + CCM_GB + this field configures the color correction matrix coefficient + 13 + 13 + read-write + + + + + CCM_COEF4 + ccm coef register 4 + 0x20 + 0x20 + 0x02581040 + + + CCM_BR + this field configures the color correction matrix coefficient + 0 + 13 + read-write + + + CCM_BG + this field configures the color correction matrix coefficient + 13 + 13 + read-write + + + + + CCM_COEF5 + ccm coef register 5 + 0x24 + 0x20 + 0x00000740 + + + CCM_BB + this field configures the color correction matrix coefficient + 0 + 13 + read-write + + + + + BF_MATRIX_CTRL + bf pix2matrix ctrl + 0x28 + 0x20 + + + BF_TAIL_PIXEN_PULSE_TL + matrix tail pixen low level threshold, should not to large to prevent expanding to next frame, only reg_bf_tail_pixen_pulse_th!=0 and reg_bf_tail_pixen_pulse_tl!=0 and reg_bf_tail_pixen_pulse_th < reg_bf_tail_pixen_pulse_tl will enable tail pulse function + 0 + 8 + read-write + + + BF_TAIL_PIXEN_PULSE_TH + matrix tail pixen high level threshold, must < hnum-1, only reg_bf_tail_pixen_pulse_th!=0 and reg_bf_tail_pixen_pulse_tl!=0 and reg_bf_tail_pixen_pulse_th < reg_bf_tail_pixen_pulse_tl will enable tail pulse function + 8 + 8 + read-write + + + BF_PADDING_DATA + this field configures bf matrix padding data + 16 + 8 + read-write + + + BF_PADDING_MODE + this bit configures the padding mode of bf matrix. 0: use pixel in image to do padding 1: use reg_padding_data to do padding + 24 + 1 + read-write + + + + + BF_SIGMA + bf denoising level control register + 0x2C + 0x20 + 0x00000002 + + + SIGMA + this field configures the bayer denoising level, valid data from 2 to 20 + 0 + 6 + read-write + + + + + BF_GAU0 + bf gau template register 0 + 0x30 + 0x20 + 0xFFFFFFFF + + + GAU_TEMPLATE21 + this field configures index 21 of gausian template + 0 + 4 + read-write + + + GAU_TEMPLATE20 + this field configures index 20 of gausian template + 4 + 4 + read-write + + + GAU_TEMPLATE12 + this field configures index 12 of gausian template + 8 + 4 + read-write + + + GAU_TEMPLATE11 + this field configures index 11 of gausian template + 12 + 4 + read-write + + + GAU_TEMPLATE10 + this field configures index 10 of gausian template + 16 + 4 + read-write + + + GAU_TEMPLATE02 + this field configures index 02 of gausian template + 20 + 4 + read-write + + + GAU_TEMPLATE01 + this field configures index 01 of gausian template + 24 + 4 + read-write + + + GAU_TEMPLATE00 + this field configures index 00 of gausian template + 28 + 4 + read-write + + + + + BF_GAU1 + bf gau template register 1 + 0x34 + 0x20 + 0x0000000F + + + GAU_TEMPLATE22 + this field configures index 22 of gausian template + 0 + 4 + read-write + + + + + DPC_CTRL + DPC mode control register + 0x38 + 0x20 + 0x00000004 + + + DPC_CHECK_EN + this bit configures the check mode enable. 0: disable, 1: enable + 0 + 1 + read-write + + + STA_EN + this bit configures the sta dpc enable. 0: disable, 1: enable + 1 + 1 + read-write + + + DYN_EN + this bit configures the dyn dpc enable. 0: disable, 1: enable + 2 + 1 + read-write + + + DPC_BLACK_EN + this bit configures input image type select when in check mode, 0: white img, 1: black img + 3 + 1 + read-write + + + DPC_METHOD_SEL + this bit configures dyn dpc method select. 0: simple method, 1: hard method + 4 + 1 + read-write + + + DPC_CHECK_OD_EN + this bit configures output pixel data when in check mode or not. 0: no data output, 1: data output + 5 + 1 + read-write + + + + + DPC_CONF + DPC parameter config register + 0x3C + 0x20 + 0x04103030 + + + DPC_THRESHOLD_L + this bit configures the threshold to detect black img in check mode, or the low threshold(use 8 bit 0~255) in dyn method 0, or the low threshold factor (use 5 bit 10000-> 16/16, 00001->1/16, 0/16~16/16) in dyn method 1 + 0 + 8 + read-write + + + DPC_THRESHOLD_H + this bit configures the threshold to detect white img in check mode, or the high threshold(use 8 bit 0~255) in dyn method 0, or the high threshold factor (use 5 bit 10000-> 16/16, 00001->1/16, 0/16~16/16) in dyn method 1 + 8 + 8 + read-write + + + DPC_FACTOR_DARK + this field configures the dynamic correction method 1 dark factor + 16 + 6 + read-write + + + DPC_FACTOR_BRIG + this field configures the dynamic correction method 1 bright factor + 22 + 6 + read-write + + + + + DPC_MATRIX_CTRL + dpc pix2matrix ctrl + 0x40 + 0x20 + + + DPC_TAIL_PIXEN_PULSE_TL + matrix tail pixen low level threshold, should not to large to prevent expanding to next frame, only reg_dpc_tail_pixen_pulse_th!=0 and reg_dpc_tail_pixen_pulse_tl!=0 and reg_dpc_tail_pixen_pulse_th < reg_dpc_tail_pixen_pulse_tl will enable tail pulse function + 0 + 8 + read-write + + + DPC_TAIL_PIXEN_PULSE_TH + matrix tail pixen high level threshold, must < hnum-1, only reg_dpc_tail_pixen_pulse_th!=0 and reg_dpc_tail_pixen_pulse_tl!=0 and reg_dpc_tail_pixen_pulse_th < reg_dpc_tail_pixen_pulse_tl will enable tail pulse function + 8 + 8 + read-write + + + DPC_PADDING_DATA + this field configures dpc matrix padding data + 16 + 8 + read-write + + + DPC_PADDING_MODE + this bit configures the padding mode of dpc matrix. 0: use pixel in image to do padding 1: use reg_padding_data to do padding + 24 + 1 + read-write + + + + + DPC_DEADPIX_CNT + DPC dead-pix number register + 0x44 + 0x20 + + + DPC_DEADPIX_CNT + this field represents the dead pixel count + 0 + 10 + read-only + + + + + LUT_CMD + LUT command register + 0x48 + 0x20 + + + LUT_ADDR + this field configures the lut access addr, when select lsc lut, [11:10]:00 sel gb_b lut, 01 sel r_gr lut + 0 + 12 + write-only + + + LUT_NUM + this field configures the lut selection. 0000:LSC LUT 0001:DPC LUT + 12 + 4 + write-only + + + LUT_CMD + this bit configures the access event of lut. 0:rd 1: wr + 16 + 1 + write-only + + + + + LUT_WDATA + LUT write data register + 0x4C + 0x20 + + + LUT_WDATA + this field configures the write data of lut. please initial ISP_LUT_WDATA before write ISP_LUT_CMD register + 0 + 32 + read-write + + + + + LUT_RDATA + LUT read data register + 0x50 + 0x20 + + + LUT_RDATA + this field represents the read data of lut. read ISP_LUT_RDATA after write ISP_LUT_CMD register + 0 + 32 + read-only + + + + + LSC_TABLESIZE + LSC point in x-direction + 0x54 + 0x20 + 0x0000001F + + + LSC_XTABLESIZE + this field configures lsc table size in x-direction + 0 + 5 + read-write + + + + + DEMOSAIC_MATRIX_CTRL + demosaic pix2matrix ctrl + 0x58 + 0x20 + + + DEMOSAIC_TAIL_PIXEN_PULSE_TL + matrix tail pixen low level threshold, should not to large to prevent expanding to next frame, only reg_demosaic_tail_pixen_pulse_th!=0 and reg_demosaic_tail_pixen_pulse_tl!=0 and reg_demosaic_tail_pixen_pulse_th < reg_demosaic_tail_pixen_pulse_tl will enable tail pulse function + 0 + 8 + read-write + + + DEMOSAIC_TAIL_PIXEN_PULSE_TH + matrix tail pixen high level threshold, must < hnum-1, only reg_demosaic_tail_pixen_pulse_th!=0 and reg_demosaic_tail_pixen_pulse_tl!=0 and reg_demosaic_tail_pixen_pulse_th < reg_demosaic_tail_pixen_pulse_tl will enable tail pulse function + 8 + 8 + read-write + + + DEMOSAIC_PADDING_DATA + this field configures demosaic matrix padding data + 16 + 8 + read-write + + + DEMOSAIC_PADDING_MODE + this bit configures the padding mode of demosaic matrix. 0: use pixel in image to do padding 1: use reg_padding_data to do padding + 24 + 1 + read-write + + + + + DEMOSAIC_GRAD_RATIO + demosaic gradient select ratio + 0x5C + 0x20 + 0x00000010 + + + DEMOSAIC_GRAD_RATIO + this field configures demosaic gradient select ratio + 0 + 6 + read-write + + + + + MEDIAN_MATRIX_CTRL + median pix2matrix ctrl + 0x60 + 0x20 + + + MEDIAN_PADDING_DATA + this field configures median matrix padding data + 0 + 8 + read-write + + + MEDIAN_PADDING_MODE + this bit configures the padding mode of median matrix. 0: use pixel in image to do padding 1: use reg_padding_data to do padding + 8 + 1 + read-write + + + + + INT_RAW + raw interrupt register + 0x64 + 0x20 + + + ISP_DATA_TYPE_ERR_INT_RAW + the raw interrupt status of input data type error. isp only support RGB bayer data type, other type will report type_err_int + 0 + 1 + read-only + + + ISP_ASYNC_FIFO_OVF_INT_RAW + the raw interrupt status of isp input fifo overflow + 1 + 1 + read-only + + + ISP_BUF_FULL_INT_RAW + the raw interrupt status of isp input buffer full + 2 + 1 + read-only + + + ISP_HVNUM_SETTING_ERR_INT_RAW + the raw interrupt status of hnum and vnum setting format error + 3 + 1 + read-only + + + ISP_DATA_TYPE_SETTING_ERR_INT_RAW + the raw interrupt status of setting invalid reg_data_type + 4 + 1 + read-only + + + ISP_MIPI_HNUM_UNMATCH_INT_RAW + the raw interrupt status of hnum setting unmatch with mipi input + 5 + 1 + read-only + + + DPC_CHECK_DONE_INT_RAW + the raw interrupt status of dpc check done + 6 + 1 + read-only + + + GAMMA_XCOORD_ERR_INT_RAW + the raw interrupt status of gamma setting error. it report the sum of the lengths represented by reg_gamma_x00~x0F isn't equal to 256 + 7 + 1 + read-only + + + AE_MONITOR_INT_RAW + the raw interrupt status of ae monitor + 8 + 1 + read-only + + + AE_FRAME_DONE_INT_RAW + the raw interrupt status of ae. + 9 + 1 + read-only + + + AF_FDONE_INT_RAW + the raw interrupt status of af statistic. when auto_update enable, each frame done will send one int pulse when manual_update, each time when write 1 to reg_manual_update will send a int pulse when next frame done + 10 + 1 + read-only + + + AF_ENV_INT_RAW + the raw interrupt status of af monitor. send a int pulse when env_det function enabled and environment changes detected + 11 + 1 + read-only + + + AWB_FDONE_INT_RAW + the raw interrupt status of awb. send a int pulse when statistic of one awb frame done + 12 + 1 + read-only + + + HIST_FDONE_INT_RAW + the raw interrupt status of histogram. send a int pulse when statistic of one frame histogram done + 13 + 1 + read-only + + + FRAME_INT_RAW + the raw interrupt status of isp frame end + 14 + 1 + read-only + + + BLC_FRAME_INT_RAW + the raw interrupt status of blc frame done + 15 + 1 + read-only + + + LSC_FRAME_INT_RAW + the raw interrupt status of lsc frame done + 16 + 1 + read-only + + + DPC_FRAME_INT_RAW + the raw interrupt status of dpc frame done + 17 + 1 + read-only + + + BF_FRAME_INT_RAW + the raw interrupt status of bf frame done + 18 + 1 + read-only + + + DEMOSAIC_FRAME_INT_RAW + the raw interrupt status of demosaic frame done + 19 + 1 + read-only + + + MEDIAN_FRAME_INT_RAW + the raw interrupt status of median frame done + 20 + 1 + read-only + + + CCM_FRAME_INT_RAW + the raw interrupt status of ccm frame done + 21 + 1 + read-only + + + GAMMA_FRAME_INT_RAW + the raw interrupt status of gamma frame done + 22 + 1 + read-only + + + RGB2YUV_FRAME_INT_RAW + the raw interrupt status of rgb2yuv frame done + 23 + 1 + read-only + + + SHARP_FRAME_INT_RAW + the raw interrupt status of sharp frame done + 24 + 1 + read-only + + + COLOR_FRAME_INT_RAW + the raw interrupt status of color frame done + 25 + 1 + read-only + + + YUV2RGB_FRAME_INT_RAW + the raw interrupt status of yuv2rgb frame done + 26 + 1 + read-only + + + TAIL_IDI_FRAME_INT_RAW + the raw interrupt status of isp_tail idi frame_end + 27 + 1 + read-only + + + HEADER_IDI_FRAME_INT_RAW + the raw interrupt status of real input frame end of isp_input + 28 + 1 + read-only + + + + + INT_ST + masked interrupt register + 0x68 + 0x20 + + + ISP_DATA_TYPE_ERR_INT_ST + the masked interrupt status of input data type error + 0 + 1 + read-only + + + ISP_ASYNC_FIFO_OVF_INT_ST + the masked interrupt status of isp input fifo overflow + 1 + 1 + read-only + + + ISP_BUF_FULL_INT_ST + the masked interrupt status of isp input buffer full + 2 + 1 + read-only + + + ISP_HVNUM_SETTING_ERR_INT_ST + the masked interrupt status of hnum and vnum setting format error + 3 + 1 + read-only + + + ISP_DATA_TYPE_SETTING_ERR_INT_ST + the masked interrupt status of setting invalid reg_data_type + 4 + 1 + read-only + + + ISP_MIPI_HNUM_UNMATCH_INT_ST + the masked interrupt status of hnum setting unmatch with mipi input + 5 + 1 + read-only + + + DPC_CHECK_DONE_INT_ST + the masked interrupt status of dpc check done + 6 + 1 + read-only + + + GAMMA_XCOORD_ERR_INT_ST + the masked interrupt status of gamma setting error + 7 + 1 + read-only + + + AE_MONITOR_INT_ST + the masked interrupt status of ae monitor + 8 + 1 + read-only + + + AE_FRAME_DONE_INT_ST + the masked interrupt status of ae + 9 + 1 + read-only + + + AF_FDONE_INT_ST + the masked interrupt status of af statistic + 10 + 1 + read-only + + + AF_ENV_INT_ST + the masked interrupt status of af monitor + 11 + 1 + read-only + + + AWB_FDONE_INT_ST + the masked interrupt status of awb + 12 + 1 + read-only + + + HIST_FDONE_INT_ST + the masked interrupt status of histogram + 13 + 1 + read-only + + + FRAME_INT_ST + the masked interrupt status of isp frame end + 14 + 1 + read-only + + + BLC_FRAME_INT_ST + the masked interrupt status of blc frame done + 15 + 1 + read-only + + + LSC_FRAME_INT_ST + the masked interrupt status of lsc frame done + 16 + 1 + read-only + + + DPC_FRAME_INT_ST + the masked interrupt status of dpc frame done + 17 + 1 + read-only + + + BF_FRAME_INT_ST + the masked interrupt status of bf frame done + 18 + 1 + read-only + + + DEMOSAIC_FRAME_INT_ST + the masked interrupt status of demosaic frame done + 19 + 1 + read-only + + + MEDIAN_FRAME_INT_ST + the masked interrupt status of median frame done + 20 + 1 + read-only + + + CCM_FRAME_INT_ST + the masked interrupt status of ccm frame done + 21 + 1 + read-only + + + GAMMA_FRAME_INT_ST + the masked interrupt status of gamma frame done + 22 + 1 + read-only + + + RGB2YUV_FRAME_INT_ST + the masked interrupt status of rgb2yuv frame done + 23 + 1 + read-only + + + SHARP_FRAME_INT_ST + the masked interrupt status of sharp frame done + 24 + 1 + read-only + + + COLOR_FRAME_INT_ST + the masked interrupt status of color frame done + 25 + 1 + read-only + + + YUV2RGB_FRAME_INT_ST + the masked interrupt status of yuv2rgb frame done + 26 + 1 + read-only + + + TAIL_IDI_FRAME_INT_ST + the masked interrupt status of isp_tail idi frame_end + 27 + 1 + read-only + + + HEADER_IDI_FRAME_INT_ST + the masked interrupt status of real input frame end of isp_input + 28 + 1 + read-only + + + + + INT_ENA + interrupt enable register + 0x6C + 0x20 + 0x000000C3 + + + ISP_DATA_TYPE_ERR_INT_ENA + write 1 to enable input data type error + 0 + 1 + read-write + + + ISP_ASYNC_FIFO_OVF_INT_ENA + write 1 to enable isp input fifo overflow + 1 + 1 + read-write + + + ISP_BUF_FULL_INT_ENA + write 1 to enable isp input buffer full + 2 + 1 + read-write + + + ISP_HVNUM_SETTING_ERR_INT_ENA + write 1 to enable hnum and vnum setting format error + 3 + 1 + read-write + + + ISP_DATA_TYPE_SETTING_ERR_INT_ENA + write 1 to enable setting invalid reg_data_type + 4 + 1 + read-write + + + ISP_MIPI_HNUM_UNMATCH_INT_ENA + write 1 to enable hnum setting unmatch with mipi input + 5 + 1 + read-write + + + DPC_CHECK_DONE_INT_ENA + write 1 to enable dpc check done + 6 + 1 + read-write + + + GAMMA_XCOORD_ERR_INT_ENA + write 1 to enable gamma setting error + 7 + 1 + read-write + + + AE_MONITOR_INT_ENA + write 1 to enable ae monitor + 8 + 1 + read-write + + + AE_FRAME_DONE_INT_ENA + write 1 to enable ae + 9 + 1 + read-write + + + AF_FDONE_INT_ENA + write 1 to enable af statistic + 10 + 1 + read-write + + + AF_ENV_INT_ENA + write 1 to enable af monitor + 11 + 1 + read-write + + + AWB_FDONE_INT_ENA + write 1 to enable awb + 12 + 1 + read-write + + + HIST_FDONE_INT_ENA + write 1 to enable histogram + 13 + 1 + read-write + + + FRAME_INT_ENA + write 1 to enable isp frame end + 14 + 1 + read-write + + + BLC_FRAME_INT_ENA + write 1 to enable blc frame done + 15 + 1 + read-write + + + LSC_FRAME_INT_ENA + write 1 to enable lsc frame done + 16 + 1 + read-write + + + DPC_FRAME_INT_ENA + write 1 to enable dpc frame done + 17 + 1 + read-write + + + BF_FRAME_INT_ENA + write 1 to enable bf frame done + 18 + 1 + read-write + + + DEMOSAIC_FRAME_INT_ENA + write 1 to enable demosaic frame done + 19 + 1 + read-write + + + MEDIAN_FRAME_INT_ENA + write 1 to enable median frame done + 20 + 1 + read-write + + + CCM_FRAME_INT_ENA + write 1 to enable ccm frame done + 21 + 1 + read-write + + + GAMMA_FRAME_INT_ENA + write 1 to enable gamma frame done + 22 + 1 + read-write + + + RGB2YUV_FRAME_INT_ENA + write 1 to enable rgb2yuv frame done + 23 + 1 + read-write + + + SHARP_FRAME_INT_ENA + write 1 to enable sharp frame done + 24 + 1 + read-write + + + COLOR_FRAME_INT_ENA + write 1 to enable color frame done + 25 + 1 + read-write + + + YUV2RGB_FRAME_INT_ENA + write 1 to enable yuv2rgb frame done + 26 + 1 + read-write + + + TAIL_IDI_FRAME_INT_ENA + write 1 to enable isp_tail idi frame_end + 27 + 1 + read-write + + + HEADER_IDI_FRAME_INT_ENA + write 1 to enable real input frame end of isp_input + 28 + 1 + read-write + + + + + INT_CLR + interrupt clear register + 0x70 + 0x20 + + + ISP_DATA_TYPE_ERR_INT_CLR + write 1 to clear input data type error + 0 + 1 + write-only + + + ISP_ASYNC_FIFO_OVF_INT_CLR + write 1 to clear isp input fifo overflow + 1 + 1 + write-only + + + ISP_BUF_FULL_INT_CLR + write 1 to clear isp input buffer full + 2 + 1 + write-only + + + ISP_HVNUM_SETTING_ERR_INT_CLR + write 1 to clear hnum and vnum setting format error + 3 + 1 + write-only + + + ISP_DATA_TYPE_SETTING_ERR_INT_CLR + write 1 to clear setting invalid reg_data_type + 4 + 1 + write-only + + + ISP_MIPI_HNUM_UNMATCH_INT_CLR + write 1 to clear hnum setting unmatch with mipi input + 5 + 1 + write-only + + + DPC_CHECK_DONE_INT_CLR + write 1 to clear dpc check done + 6 + 1 + write-only + + + GAMMA_XCOORD_ERR_INT_CLR + write 1 to clear gamma setting error + 7 + 1 + write-only + + + AE_MONITOR_INT_CLR + write 1 to clear ae monitor + 8 + 1 + write-only + + + AE_FRAME_DONE_INT_CLR + write 1 to clear ae + 9 + 1 + write-only + + + AF_FDONE_INT_CLR + write 1 to clear af statistic + 10 + 1 + write-only + + + AF_ENV_INT_CLR + write 1 to clear af monitor + 11 + 1 + write-only + + + AWB_FDONE_INT_CLR + write 1 to clear awb + 12 + 1 + write-only + + + HIST_FDONE_INT_CLR + write 1 to clear histogram + 13 + 1 + write-only + + + FRAME_INT_CLR + write 1 to clear isp frame end + 14 + 1 + write-only + + + BLC_FRAME_INT_CLR + write 1 to clear blc frame done + 15 + 1 + write-only + + + LSC_FRAME_INT_CLR + write 1 to clear lsc frame done + 16 + 1 + write-only + + + DPC_FRAME_INT_CLR + write 1 to clear dpc frame done + 17 + 1 + write-only + + + BF_FRAME_INT_CLR + write 1 to clear bf frame done + 18 + 1 + write-only + + + DEMOSAIC_FRAME_INT_CLR + write 1 to clear demosaic frame done + 19 + 1 + write-only + + + MEDIAN_FRAME_INT_CLR + write 1 to clear median frame done + 20 + 1 + write-only + + + CCM_FRAME_INT_CLR + write 1 to clear ccm frame done + 21 + 1 + write-only + + + GAMMA_FRAME_INT_CLR + write 1 to clear gamma frame done + 22 + 1 + write-only + + + RGB2YUV_FRAME_INT_CLR + write 1 to clear rgb2yuv frame done + 23 + 1 + write-only + + + SHARP_FRAME_INT_CLR + write 1 to clear sharp frame done + 24 + 1 + write-only + + + COLOR_FRAME_INT_CLR + write 1 to clear color frame done + 25 + 1 + write-only + + + YUV2RGB_FRAME_INT_CLR + write 1 to clear yuv2rgb frame done + 26 + 1 + write-only + + + TAIL_IDI_FRAME_INT_CLR + write 1 to clear isp_tail idi frame_end + 27 + 1 + write-only + + + HEADER_IDI_FRAME_INT_CLR + write 1 to clear real input frame end of isp_input + 28 + 1 + write-only + + + + + GAMMA_CTRL + gamma control register + 0x74 + 0x20 + 0x0000000E + + + GAMMA_UPDATE + Indicates that gamma register configuration is complete + 0 + 1 + read-write + + + GAMMA_B_LAST_CORRECT + this bit configures enable of last b segment correcction. 0: disable, 1: enable + 1 + 1 + read-write + + + GAMMA_G_LAST_CORRECT + this bit configures enable of last g segment correcction. 0: disable, 1: enable + 2 + 1 + read-write + + + GAMMA_R_LAST_CORRECT + this bit configures enable of last r segment correcction. 0: disable, 1: enable + 3 + 1 + read-write + + + + + GAMMA_RY1 + point of Y-axis of r channel gamma curve register 1 + 0x78 + 0x20 + 0x10203040 + + + GAMMA_R_Y03 + this field configures the point 3 of Y-axis of r channel gamma curve + 0 + 8 + read-write + + + GAMMA_R_Y02 + this field configures the point 2 of Y-axis of r channel gamma curve + 8 + 8 + read-write + + + GAMMA_R_Y01 + this field configures the point 1 of Y-axis of r channel gamma curve + 16 + 8 + read-write + + + GAMMA_R_Y00 + this field configures the point 0 of Y-axis of r channel gamma curve + 24 + 8 + read-write + + + + + GAMMA_RY2 + point of Y-axis of r channel gamma curve register 2 + 0x7C + 0x20 + 0x50607080 + + + GAMMA_R_Y07 + this field configures the point 7 of Y-axis of r channel gamma curve + 0 + 8 + read-write + + + GAMMA_R_Y06 + this field configures the point 6 of Y-axis of r channel gamma curve + 8 + 8 + read-write + + + GAMMA_R_Y05 + this field configures the point 5 of Y-axis of r channel gamma curve + 16 + 8 + read-write + + + GAMMA_R_Y04 + this field configures the point 4 of Y-axis of r channel gamma curve + 24 + 8 + read-write + + + + + GAMMA_RY3 + point of Y-axis of r channel gamma curve register 3 + 0x80 + 0x20 + 0x90A0B0C0 + + + GAMMA_R_Y0B + this field configures the point 11 of Y-axis of r channel gamma curve + 0 + 8 + read-write + + + GAMMA_R_Y0A + this field configures the point 10 of Y-axis of r channel gamma curve + 8 + 8 + read-write + + + GAMMA_R_Y09 + this field configures the point 9 of Y-axis of r channel gamma curve + 16 + 8 + read-write + + + GAMMA_R_Y08 + this field configures the point 8 of Y-axis of r channel gamma curve + 24 + 8 + read-write + + + + + GAMMA_RY4 + point of Y-axis of r channel gamma curve register 4 + 0x84 + 0x20 + 0xD0E0F0FF + + + GAMMA_R_Y0F + this field configures the point 15 of Y-axis of r channel gamma curve + 0 + 8 + read-write + + + GAMMA_R_Y0E + this field configures the point 14 of Y-axis of r channel gamma curve + 8 + 8 + read-write + + + GAMMA_R_Y0D + this field configures the point 13 of Y-axis of r channel gamma curve + 16 + 8 + read-write + + + GAMMA_R_Y0C + this field configures the point 12 of Y-axis of r channel gamma curve + 24 + 8 + read-write + + + + + GAMMA_GY1 + point of Y-axis of g channel gamma curve register 1 + 0x88 + 0x20 + 0x10203040 + + + GAMMA_G_Y03 + this field configures the point 3 of Y-axis of g channel gamma curve + 0 + 8 + read-write + + + GAMMA_G_Y02 + this field configures the point 2 of Y-axis of g channel gamma curve + 8 + 8 + read-write + + + GAMMA_G_Y01 + this field configures the point 1 of Y-axis of g channel gamma curve + 16 + 8 + read-write + + + GAMMA_G_Y00 + this field configures the point 0 of Y-axis of g channel gamma curve + 24 + 8 + read-write + + + + + GAMMA_GY2 + point of Y-axis of g channel gamma curve register 2 + 0x8C + 0x20 + 0x50607080 + + + GAMMA_G_Y07 + this field configures the point 7 of Y-axis of g channel gamma curve + 0 + 8 + read-write + + + GAMMA_G_Y06 + this field configures the point 6 of Y-axis of g channel gamma curve + 8 + 8 + read-write + + + GAMMA_G_Y05 + this field configures the point 5 of Y-axis of g channel gamma curve + 16 + 8 + read-write + + + GAMMA_G_Y04 + this field configures the point 4 of Y-axis of g channel gamma curve + 24 + 8 + read-write + + + + + GAMMA_GY3 + point of Y-axis of g channel gamma curve register 3 + 0x90 + 0x20 + 0x90A0B0C0 + + + GAMMA_G_Y0B + this field configures the point 11 of Y-axis of g channel gamma curve + 0 + 8 + read-write + + + GAMMA_G_Y0A + this field configures the point 10 of Y-axis of g channel gamma curve + 8 + 8 + read-write + + + GAMMA_G_Y09 + this field configures the point 9 of Y-axis of g channel gamma curve + 16 + 8 + read-write + + + GAMMA_G_Y08 + this field configures the point 8 of Y-axis of g channel gamma curve + 24 + 8 + read-write + + + + + GAMMA_GY4 + point of Y-axis of g channel gamma curve register 4 + 0x94 + 0x20 + 0xD0E0F0FF + + + GAMMA_G_Y0F + this field configures the point 15 of Y-axis of g channel gamma curve + 0 + 8 + read-write + + + GAMMA_G_Y0E + this field configures the point 14 of Y-axis of g channel gamma curve + 8 + 8 + read-write + + + GAMMA_G_Y0D + this field configures the point 13 of Y-axis of g channel gamma curve + 16 + 8 + read-write + + + GAMMA_G_Y0C + this field configures the point 12 of Y-axis of g channel gamma curve + 24 + 8 + read-write + + + + + GAMMA_BY1 + point of Y-axis of b channel gamma curve register 1 + 0x98 + 0x20 + 0x10203040 + + + GAMMA_B_Y03 + this field configures the point 3 of Y-axis of b channel gamma curve + 0 + 8 + read-write + + + GAMMA_B_Y02 + this field configures the point 2 of Y-axis of b channel gamma curve + 8 + 8 + read-write + + + GAMMA_B_Y01 + this field configures the point 1 of Y-axis of b channel gamma curve + 16 + 8 + read-write + + + GAMMA_B_Y00 + this field configures the point 0 of Y-axis of b channel gamma curve + 24 + 8 + read-write + + + + + GAMMA_BY2 + point of Y-axis of b channel gamma curve register 2 + 0x9C + 0x20 + 0x50607080 + + + GAMMA_B_Y07 + this field configures the point 7 of Y-axis of b channel gamma curve + 0 + 8 + read-write + + + GAMMA_B_Y06 + this field configures the point 6 of Y-axis of b channel gamma curve + 8 + 8 + read-write + + + GAMMA_B_Y05 + this field configures the point 5 of Y-axis of b channel gamma curve + 16 + 8 + read-write + + + GAMMA_B_Y04 + this field configures the point 4 of Y-axis of b channel gamma curve + 24 + 8 + read-write + + + + + GAMMA_BY3 + point of Y-axis of b channel gamma curve register 3 + 0xA0 + 0x20 + 0x90A0B0C0 + + + GAMMA_B_Y0B + this field configures the point 11 of Y-axis of b channel gamma curve + 0 + 8 + read-write + + + GAMMA_B_Y0A + this field configures the point 10 of Y-axis of b channel gamma curve + 8 + 8 + read-write + + + GAMMA_B_Y09 + this field configures the point 9 of Y-axis of b channel gamma curve + 16 + 8 + read-write + + + GAMMA_B_Y08 + this field configures the point 8 of Y-axis of b channel gamma curve + 24 + 8 + read-write + + + + + GAMMA_BY4 + point of Y-axis of b channel gamma curve register 4 + 0xA4 + 0x20 + 0xD0E0F0FF + + + GAMMA_B_Y0F + this field configures the point 15 of Y-axis of b channel gamma curve + 0 + 8 + read-write + + + GAMMA_B_Y0E + this field configures the point 14 of Y-axis of b channel gamma curve + 8 + 8 + read-write + + + GAMMA_B_Y0D + this field configures the point 13 of Y-axis of b channel gamma curve + 16 + 8 + read-write + + + GAMMA_B_Y0C + this field configures the point 12 of Y-axis of b channel gamma curve + 24 + 8 + read-write + + + + + GAMMA_RX1 + point of X-axis of r channel gamma curve register 1 + 0xA8 + 0x20 + 0x00924924 + + + GAMMA_R_X07 + this field configures the point 7 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point + 0 + 3 + read-write + + + GAMMA_R_X06 + this field configures the point 6 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point + 3 + 3 + read-write + + + GAMMA_R_X05 + this field configures the point 5 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point + 6 + 3 + read-write + + + GAMMA_R_X04 + this field configures the point 4 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point + 9 + 3 + read-write + + + GAMMA_R_X03 + this field configures the point 3 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point + 12 + 3 + read-write + + + GAMMA_R_X02 + this field configures the point 2 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point + 15 + 3 + read-write + + + GAMMA_R_X01 + this field configures the point 1 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point + 18 + 3 + read-write + + + GAMMA_R_X00 + this field configures the point 0 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point + 21 + 3 + read-write + + + + + GAMMA_RX2 + point of X-axis of r channel gamma curve register 2 + 0xAC + 0x20 + 0x00924924 + + + GAMMA_R_X0F + this field configures the point 15 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point + 0 + 3 + read-write + + + GAMMA_R_X0E + this field configures the point 14 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point + 3 + 3 + read-write + + + GAMMA_R_X0D + this field configures the point 13 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point + 6 + 3 + read-write + + + GAMMA_R_X0C + this field configures the point 12 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point + 9 + 3 + read-write + + + GAMMA_R_X0B + this field configures the point 11 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point + 12 + 3 + read-write + + + GAMMA_R_X0A + this field configures the point 10 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point + 15 + 3 + read-write + + + GAMMA_R_X09 + this field configures the point 9 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point + 18 + 3 + read-write + + + GAMMA_R_X08 + this field configures the point 8 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point + 21 + 3 + read-write + + + + + GAMMA_GX1 + point of X-axis of g channel gamma curve register 1 + 0xB0 + 0x20 + 0x00924924 + + + GAMMA_G_X07 + this field configures the point 7 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point + 0 + 3 + read-write + + + GAMMA_G_X06 + this field configures the point 6 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point + 3 + 3 + read-write + + + GAMMA_G_X05 + this field configures the point 5 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point + 6 + 3 + read-write + + + GAMMA_G_X04 + this field configures the point 4 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point + 9 + 3 + read-write + + + GAMMA_G_X03 + this field configures the point 3 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point + 12 + 3 + read-write + + + GAMMA_G_X02 + this field configures the point 2 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point + 15 + 3 + read-write + + + GAMMA_G_X01 + this field configures the point 1 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point + 18 + 3 + read-write + + + GAMMA_G_X00 + this field configures the point 0 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point + 21 + 3 + read-write + + + + + GAMMA_GX2 + point of X-axis of g channel gamma curve register 2 + 0xB4 + 0x20 + 0x00924924 + + + GAMMA_G_X0F + this field configures the point 15 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point + 0 + 3 + read-write + + + GAMMA_G_X0E + this field configures the point 14 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point + 3 + 3 + read-write + + + GAMMA_G_X0D + this field configures the point 13 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point + 6 + 3 + read-write + + + GAMMA_G_X0C + this field configures the point 12 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point + 9 + 3 + read-write + + + GAMMA_G_X0B + this field configures the point 11 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point + 12 + 3 + read-write + + + GAMMA_G_X0A + this field configures the point 10 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point + 15 + 3 + read-write + + + GAMMA_G_X09 + this field configures the point 9 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point + 18 + 3 + read-write + + + GAMMA_G_X08 + this field configures the point 8 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point + 21 + 3 + read-write + + + + + GAMMA_BX1 + point of X-axis of b channel gamma curve register 1 + 0xB8 + 0x20 + 0x00924924 + + + GAMMA_B_X07 + this field configures the point 7 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point + 0 + 3 + read-write + + + GAMMA_B_X06 + this field configures the point 6 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point + 3 + 3 + read-write + + + GAMMA_B_X05 + this field configures the point 5 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point + 6 + 3 + read-write + + + GAMMA_B_X04 + this field configures the point 4 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point + 9 + 3 + read-write + + + GAMMA_B_X03 + this field configures the point 3 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point + 12 + 3 + read-write + + + GAMMA_B_X02 + this field configures the point 2 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point + 15 + 3 + read-write + + + GAMMA_B_X01 + this field configures the point 1 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point + 18 + 3 + read-write + + + GAMMA_B_X00 + this field configures the point 0 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point + 21 + 3 + read-write + + + + + GAMMA_BX2 + point of X-axis of b channel gamma curve register 2 + 0xBC + 0x20 + 0x00924924 + + + GAMMA_B_X0F + this field configures the point 15 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point + 0 + 3 + read-write + + + GAMMA_B_X0E + this field configures the point 14 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point + 3 + 3 + read-write + + + GAMMA_B_X0D + this field configures the point 13 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point + 6 + 3 + read-write + + + GAMMA_B_X0C + this field configures the point 12 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point + 9 + 3 + read-write + + + GAMMA_B_X0B + this field configures the point 11 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point + 12 + 3 + read-write + + + GAMMA_B_X0A + this field configures the point 10 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point + 15 + 3 + read-write + + + GAMMA_B_X09 + this field configures the point 9 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point + 18 + 3 + read-write + + + GAMMA_B_X08 + this field configures the point 8 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point + 21 + 3 + read-write + + + + + AE_CTRL + ae control register + 0xC0 + 0x20 + + + AE_UPDATE + write 1 to this bit triggers one statistic event + 0 + 1 + write-only + + + AE_SELECT + this field configures ae input data source, 0: data from median, 1: data from gama + 1 + 1 + read-write + + + + + AE_MONITOR + ae monitor control register + 0xC4 + 0x20 + + + TL + this field configures the lower lum threshold of ae monitor + 0 + 8 + read-write + + + TH + this field configures the higher lum threshold of ae monitor + 8 + 8 + read-write + + + PERIOD + this field cnfigures ae monitor frame period + 16 + 6 + read-write + + + + + AE_BX + ae window register in x-direction + 0xC8 + 0x20 + 0x00000180 + + + AE_X_BSIZE + this field configures every block x size + 0 + 11 + read-write + + + AE_X_START + this field configures first block start x address + 11 + 11 + read-write + + + + + AE_BY + ae window register in y-direction + 0xCC + 0x20 + 0x000000D8 + + + AE_Y_BSIZE + this field configures every block y size + 0 + 11 + read-write + + + AE_Y_START + this field configures first block start y address + 11 + 11 + read-write + + + + + AE_WINPIXNUM + ae sub-window pix num register + 0xD0 + 0x20 + 0x00014400 + + + AE_SUBWIN_PIXNUM + this field configures the pixel number of each sub win + 0 + 17 + read-write + + + + + AE_WIN_RECIPROCAL + reciprocal of ae sub-window pixel number + 0xD4 + 0x20 + + + AE_SUBWIN_RECIP + this field configures the reciprocal of each subwin_pixnum, 20bit fraction + 0 + 20 + read-write + + + + + AE_BLOCK_MEAN_0 + ae statistic result register 0 + 0xD8 + 0x20 + + + AE_B03_MEAN + this field configures block03 Y mean data + 0 + 8 + read-only + + + AE_B02_MEAN + this field configures block02 Y mean data + 8 + 8 + read-only + + + AE_B01_MEAN + this field configures block01 Y mean data + 16 + 8 + read-only + + + AE_B00_MEAN + this field configures block00 Y mean data + 24 + 8 + read-only + + + + + AE_BLOCK_MEAN_1 + ae statistic result register 1 + 0xDC + 0x20 + + + AE_B12_MEAN + this field configures block12 Y mean data + 0 + 8 + read-only + + + AE_B11_MEAN + this field configures block11 Y mean data + 8 + 8 + read-only + + + AE_B10_MEAN + this field configures block10 Y mean data + 16 + 8 + read-only + + + AE_B04_MEAN + this field configures block04 Y mean data + 24 + 8 + read-only + + + + + AE_BLOCK_MEAN_2 + ae statistic result register 2 + 0xE0 + 0x20 + + + AE_B21_MEAN + this field configures block21 Y mean data + 0 + 8 + read-only + + + AE_B20_MEAN + this field configures block20 Y mean data + 8 + 8 + read-only + + + AE_B14_MEAN + this field configures block14 Y mean data + 16 + 8 + read-only + + + AE_B13_MEAN + this field configures block13 Y mean data + 24 + 8 + read-only + + + + + AE_BLOCK_MEAN_3 + ae statistic result register 3 + 0xE4 + 0x20 + + + AE_B30_MEAN + this field configures block30 Y mean data + 0 + 8 + read-only + + + AE_B24_MEAN + this field configures block24 Y mean data + 8 + 8 + read-only + + + AE_B23_MEAN + this field configures block23 Y mean data + 16 + 8 + read-only + + + AE_B22_MEAN + this field configures block22 Y mean data + 24 + 8 + read-only + + + + + AE_BLOCK_MEAN_4 + ae statistic result register 4 + 0xE8 + 0x20 + + + AE_B34_MEAN + this field configures block34 Y mean data + 0 + 8 + read-only + + + AE_B33_MEAN + this field configures block33 Y mean data + 8 + 8 + read-only + + + AE_B32_MEAN + this field configures block32 Y mean data + 16 + 8 + read-only + + + AE_B31_MEAN + this field configures block31 Y mean data + 24 + 8 + read-only + + + + + AE_BLOCK_MEAN_5 + ae statistic result register 5 + 0xEC + 0x20 + + + AE_B43_MEAN + this field configures block43 Y mean data + 0 + 8 + read-only + + + AE_B42_MEAN + this field configures block42 Y mean data + 8 + 8 + read-only + + + AE_B41_MEAN + this field configures block41 Y mean data + 16 + 8 + read-only + + + AE_B40_MEAN + this field configures block40 Y mean data + 24 + 8 + read-only + + + + + AE_BLOCK_MEAN_6 + ae statistic result register 6 + 0xF0 + 0x20 + + + AE_B44_MEAN + this field configures block44 Y mean data + 24 + 8 + read-only + + + + + SHARP_CTRL0 + sharp control register 0 + 0xF4 + 0x20 + + + SHARP_THRESHOLD_LOW + this field configures sharpen threshold for detail + 0 + 8 + read-write + + + SHARP_THRESHOLD_HIGH + this field configures sharpen threshold for edge + 8 + 8 + read-write + + + SHARP_AMOUNT_LOW + this field configures sharpen amount for detail + 16 + 8 + read-write + + + SHARP_AMOUNT_HIGH + this field configures sharpen amount for edge + 24 + 8 + read-write + + + + + SHARP_FILTER0 + sharp usm config register 0 + 0xF8 + 0x20 + 0x00000441 + + + SHARP_FILTER_COE00 + this field configures unsharp masking(usm) filter coefficient + 0 + 5 + read-write + + + SHARP_FILTER_COE01 + this field configures usm filter coefficient + 5 + 5 + read-write + + + SHARP_FILTER_COE02 + this field configures usm filter coefficient + 10 + 5 + read-write + + + + + SHARP_FILTER1 + sharp usm config register 1 + 0xFC + 0x20 + 0x00000882 + + + SHARP_FILTER_COE10 + this field configures usm filter coefficient + 0 + 5 + read-write + + + SHARP_FILTER_COE11 + this field configures usm filter coefficient + 5 + 5 + read-write + + + SHARP_FILTER_COE12 + this field configures usm filter coefficient + 10 + 5 + read-write + + + + + SHARP_FILTER2 + sharp usm config register 2 + 0x100 + 0x20 + 0x00000441 + + + SHARP_FILTER_COE20 + this field configures usm filter coefficient + 0 + 5 + read-write + + + SHARP_FILTER_COE21 + this field configures usm filter coefficient + 5 + 5 + read-write + + + SHARP_FILTER_COE22 + this field configures usm filter coefficient + 10 + 5 + read-write + + + + + SHARP_MATRIX_CTRL + sharp pix2matrix ctrl + 0x104 + 0x20 + + + SHARP_TAIL_PIXEN_PULSE_TL + matrix tail pixen low level threshold, should not to large to prevent expanding to next frame, only reg_demosaic_tail_pixen_pulse_th!=0 and reg_demosaic_tail_pixen_pulse_tl!=0 and reg_demosaic_tail_pixen_pulse_th < reg_demosaic_tail_pixen_pulse_tl will enable tail pulse function + 0 + 8 + read-write + + + SHARP_TAIL_PIXEN_PULSE_TH + matrix tail pixen high level threshold, must < hnum-1, only reg_sharp_tail_pixen_pulse_th!=0 and reg_sharp_tail_pixen_pulse_tl!=0 and reg_sharp_tail_pixen_pulse_th < reg_sharp_tail_pixen_pulse_tl will enable tail pulse function + 8 + 8 + read-write + + + SHARP_PADDING_DATA + this field configures sharp padding data + 16 + 8 + read-write + + + SHARP_PADDING_MODE + this field configures sharp padding mode + 24 + 1 + read-write + + + + + SHARP_CTRL1 + sharp control register 1 + 0x108 + 0x20 + + + SHARP_GRADIENT_MAX + this field configures sharp max gradient, refresh at the end of each frame end + 0 + 8 + read-only + + + + + DMA_CNTL + isp dma source trans control register + 0x10C + 0x20 + 0x001080A8 + + + DMA_EN + write 1 to triger dma to get 1 frame + 0 + 1 + write-only + + + DMA_UPDATE + write 1 to update reg_dma_burst_len & reg_dma_data_type + 1 + 1 + read-write + + + DMA_DATA_TYPE + this field configures the idi data type for image data + 2 + 6 + read-write + + + DMA_BURST_LEN + this field configures dma burst len when data source is dma. set according to dma_msize, it is the number of 64bits in a dma transfer + 8 + 12 + read-write + + + DMA_INTERVAL + this field configures dma req interval, 12'b1: 1 cycle, 12'b11 2 cycle ... + 20 + 12 + read-write + + + + + DMA_RAW_DATA + isp dma source total raw number set register + 0x110 + 0x20 + + + DMA_RAW_NUM_TOTAL + this field configures the the number of 64bits in a frame + 0 + 22 + read-write + + + DMA_RAW_NUM_TOTAL_SET + write 1 to update reg_dma_raw_num_total + 31 + 1 + write-only + + + + + CAM_CNTL + isp cam source control register + 0x114 + 0x20 + 0x00000004 + + + CAM_EN + write 1 to start recive camera data, write 0 to disable + 0 + 1 + read-write + + + CAM_UPDATE + write 1 to update ISP_CAM_CONF + 1 + 1 + read-write + + + CAM_RESET + this bit configures cam clk domain reset, 1: reset cam input logic, 0: release reset + 2 + 1 + read-write + + + CAM_CLK_INV + this bit configures the invertion of cam clk from pad. 0: not invert cam clk, 1: invert cam clk + 3 + 1 + read-write + + + + + CAM_CONF + isp cam source config register + 0x118 + 0x20 + 0x000000A8 + + + CAM_DATA_ORDER + this field configures data order of cam port, 0: cam_data_in, 1:{cam_data_in[7:0], cam_data_in[15:8]} + 0 + 1 + read-write + + + CAM_2BYTE_MODE + this field configures enable of cam 2 byte mode(input 2 bytes each clock). 0: disable, 1: enable + 1 + 1 + read-write + + + CAM_DATA_TYPE + this field configures idi data type for image data, 0x2a: RAW8, 0x2b: RAW10, 0x2c: RAW12 + 2 + 6 + read-write + + + CAM_DE_INV + this bit configures cam data enable invert. 0: not invert, 1: invert + 8 + 1 + read-write + + + CAM_HSYNC_INV + this bit configures cam hsync invert. 0: not invert, 1: invert + 9 + 1 + read-write + + + CAM_VSYNC_INV + this bit configures cam vsync invert. 0: not invert, 1: invert + 10 + 1 + read-write + + + CAM_VSYNC_FILTER_THRES + this bit configures the number of clock of vsync filter length + 11 + 3 + read-write + + + CAM_VSYNC_FILTER_EN + this bit configures vsync filter en + 14 + 1 + read-write + + + + + AF_CTRL0 + af control register 0 + 0x11C + 0x20 + + + AF_AUTO_UPDATE + this bit configures auto_update enable. when set to 1, will update sum and lum each frame + 0 + 1 + read-write + + + AF_MANUAL_UPDATE + write 1 to this bit will update the sum and lum once + 4 + 1 + write-only + + + AF_ENV_THRESHOLD + this field configures env threshold. when both sum and lum changes larger than this value, consider environment changes and need to trigger a new autofocus. 4Bit fractional + 8 + 4 + read-write + + + AF_ENV_PERIOD + this field configures environment changes detection period (frame). When set to 0, disable this function + 16 + 8 + read-write + + + + + AF_CTRL1 + af control register 1 + 0x120 + 0x20 + + + AF_THPIXNUM + this field configures pixnum used when calculating the autofocus threshold. Set to 0 to disable threshold calculation + 0 + 22 + read-write + + + + + AF_GEN_TH_CTRL + af gen threshold control register + 0x124 + 0x20 + 0x04400080 + + + AF_GEN_THRESHOLD_MIN + this field configures min threshold when use auto_threshold + 0 + 16 + read-write + + + AF_GEN_THRESHOLD_MAX + this field configures max threshold when use auto_threshold + 16 + 16 + read-write + + + + + AF_ENV_USER_TH_SUM + af monitor user sum threshold register + 0x128 + 0x20 + + + AF_ENV_USER_THRESHOLD_SUM + this field configures user setup env detect sum threshold + 0 + 32 + read-write + + + + + AF_ENV_USER_TH_LUM + af monitor user lum threshold register + 0x12C + 0x20 + + + AF_ENV_USER_THRESHOLD_LUM + this field configures user setup env detect lum threshold + 0 + 30 + read-write + + + + + AF_THRESHOLD + af threshold register + 0x130 + 0x20 + 0x00000100 + + + AF_THRESHOLD + this field configures user threshold. When set to non-zero, autofocus will use this threshold + 0 + 16 + read-write + + + AF_GEN_THRESHOLD + this field represents the last calculated threshold + 16 + 16 + read-only + + + + + AF_HSCALE_A + h-scale of af window a register + 0x134 + 0x20 + 0x00010080 + + + AF_RPOINT_A + this field configures left coordinate of focus window a, must >= 2 + 0 + 12 + read-write + + + AF_LPOINT_A + this field configures top coordinate of focus window a, must >= 2 + 16 + 12 + read-write + + + + + AF_VSCALE_A + v-scale of af window a register + 0x138 + 0x20 + 0x00010080 + + + AF_BPOINT_A + this field configures right coordinate of focus window a, must <= hnum-2 + 0 + 12 + read-write + + + AF_TPOINT_A + this field configures bottom coordinate of focus window a, must <= hnum-2 + 16 + 12 + read-write + + + + + AF_HSCALE_B + h-scale of af window b register + 0x13C + 0x20 + 0x00010080 + + + AF_RPOINT_B + this field configures left coordinate of focus window b, must >= 2 + 0 + 12 + read-write + + + AF_LPOINT_B + this field configures top coordinate of focus window b, must >= 2 + 16 + 12 + read-write + + + + + AF_VSCALE_B + v-scale of af window b register + 0x140 + 0x20 + 0x00010080 + + + AF_BPOINT_B + this field configures right coordinate of focus window b, must <= hnum-2 + 0 + 12 + read-write + + + AF_TPOINT_B + this field configures bottom coordinate of focus window b, must <= hnum-2 + 16 + 12 + read-write + + + + + AF_HSCALE_C + v-scale of af window c register + 0x144 + 0x20 + 0x00010080 + + + AF_RPOINT_C + this field configures left coordinate of focus window c, must >= 2 + 0 + 12 + read-write + + + AF_LPOINT_C + this field configures top coordinate of focus window c, must >= 2 + 16 + 12 + read-write + + + + + AF_VSCALE_C + v-scale of af window c register + 0x148 + 0x20 + 0x00010080 + + + AF_BPOINT_C + this field configures right coordinate of focus window c, must <= hnum-2 + 0 + 12 + read-write + + + AF_TPOINT_C + this field configures bottom coordinate of focus window c, must <= hnum-2 + 16 + 12 + read-write + + + + + AF_SUM_A + result of sum of af window a + 0x14C + 0x20 + + + AF_SUMA + this field represents the result of accumulation of pix grad of focus window a + 0 + 30 + read-only + + + + + AF_SUM_B + result of sum of af window b + 0x150 + 0x20 + + + AF_SUMB + this field represents the result of accumulation of pix grad of focus window b + 0 + 30 + read-only + + + + + AF_SUM_C + result of sum of af window c + 0x154 + 0x20 + + + AF_SUMC + this field represents the result of accumulation of pix grad of focus window c + 0 + 30 + read-only + + + + + AF_LUM_A + result of lum of af window a + 0x158 + 0x20 + + + AF_LUMA + this field represents the result of accumulation of pix light of focus window a + 0 + 28 + read-only + + + + + AF_LUM_B + result of lum of af window b + 0x15C + 0x20 + + + AF_LUMB + this field represents the result of accumulation of pix light of focus window b + 0 + 28 + read-only + + + + + AF_LUM_C + result of lum of af window c + 0x160 + 0x20 + + + AF_LUMC + this field represents the result of accumulation of pix light of focus window c + 0 + 28 + read-only + + + + + AWB_MODE + awb mode control register + 0x164 + 0x20 + 0x00000003 + + + AWB_MODE + this field configures awb algo sel. 00: none sellected. 01: sel algo0. 10: sel algo1. 11: sel both algo0 and algo1 + 0 + 2 + read-write + + + AWB_SAMPLE + this bit configures awb sample location, 0:before ccm, 1:after ccm + 4 + 1 + read-write + + + + + AWB_HSCALE + h-scale of awb window + 0x168 + 0x20 + 0x0000077F + + + AWB_RPOINT + this field configures awb window right coordinate + 0 + 12 + read-write + + + AWB_LPOINT + this field configures awb window left coordinate + 16 + 12 + read-write + + + + + AWB_VSCALE + v-scale of awb window + 0x16C + 0x20 + 0x00000437 + + + AWB_BPOINT + this field configures awb window bottom coordinate + 0 + 12 + read-write + + + AWB_TPOINT + this field configures awb window top coordinate + 16 + 12 + read-write + + + + + AWB_TH_LUM + awb lum threshold register + 0x170 + 0x20 + 0x02FD0000 + + + AWB_MIN_LUM + this field configures lower threshold of r+g+b + 0 + 10 + read-write + + + AWB_MAX_LUM + this field configures upper threshold of r+g+b + 16 + 10 + read-write + + + + + AWB_TH_RG + awb r/g threshold register + 0x174 + 0x20 + 0x03FF0000 + + + AWB_MIN_RG + this field configures lower threshold of r/g, 2bit integer and 8bit fraction + 0 + 10 + read-write + + + AWB_MAX_RG + this field configures upper threshold of r/g, 2bit integer and 8bit fraction + 16 + 10 + read-write + + + + + AWB_TH_BG + awb b/g threshold register + 0x178 + 0x20 + 0x03FF0000 + + + AWB_MIN_BG + this field configures lower threshold of b/g, 2bit integer and 8bit fraction + 0 + 10 + read-write + + + AWB_MAX_BG + this field configures upper threshold of b/g, 2bit integer and 8bit fraction + 16 + 10 + read-write + + + + + AWB0_WHITE_CNT + result of awb white point number + 0x17C + 0x20 + + + AWB0_WHITE_CNT + this field configures number of white point detected of algo0 + 0 + 24 + read-only + + + + + AWB0_ACC_R + result of accumulate of r channel of all white points + 0x180 + 0x20 + + + AWB0_ACC_R + this field represents accumulate of channel r of all white point of algo0 + 0 + 32 + read-only + + + + + AWB0_ACC_G + result of accumulate of g channel of all white points + 0x184 + 0x20 + + + AWB0_ACC_G + this field represents accumulate of channel g of all white point of algo0 + 0 + 32 + read-only + + + + + AWB0_ACC_B + result of accumulate of b channel of all white points + 0x188 + 0x20 + + + AWB0_ACC_B + this field represents accumulate of channel b of all white point of algo0 + 0 + 32 + read-only + + + + + COLOR_CTRL + color control register + 0x18C + 0x20 + 0x00800080 + + + COLOR_SATURATION + this field configures the color saturation value + 0 + 8 + read-write + + + COLOR_HUE + this field configures the color hue angle + 8 + 8 + read-write + + + COLOR_CONTRAST + this field configures the color contrast value + 16 + 8 + read-write + + + COLOR_BRIGHTNESS + this field configures the color brightness value, signed 2's complement + 24 + 8 + read-write + + + + + BLC_VALUE + blc black level register + 0x190 + 0x20 + + + BLC_R3_VALUE + this field configures the black level of bottom right channel of bayer img + 0 + 8 + read-write + + + BLC_R2_VALUE + this field configures the black level of bottom left channel of bayer img + 8 + 8 + read-write + + + BLC_R1_VALUE + this field configures the black level of top right channel of bayer img + 16 + 8 + read-write + + + BLC_R0_VALUE + this field configures the black level of top left channel of bayer img + 24 + 8 + read-write + + + + + BLC_CTRL0 + blc stretch control register + 0x194 + 0x20 + + + BLC_R3_STRETCH + this bit configures the stretch feature of bottom right channel. 0: stretch disable, 1: stretch enable + 0 + 1 + read-write + + + BLC_R2_STRETCH + this bit configures the stretch feature of bottom left channel. 0: stretch disable, 1: stretch enable + 1 + 1 + read-write + + + BLC_R1_STRETCH + this bit configures the stretch feature of top right channel. 0: stretch disable, 1: stretch enable + 2 + 1 + read-write + + + BLC_R0_STRETCH + this bit configures the stretch feature of top left channel. 0: stretch disable, 1: stretch enable + 3 + 1 + read-write + + + + + BLC_CTRL1 + blc window control register + 0x198 + 0x20 + + + BLC_WINDOW_TOP + this field configures blc average calculation window top + 0 + 11 + read-write + + + BLC_WINDOW_LEFT + this field configures blc average calculation window left + 11 + 11 + read-write + + + BLC_WINDOW_VNUM + this field configures blc average calculation window vnum + 22 + 4 + read-write + + + BLC_WINDOW_HNUM + this field configures blc average calculation window hnum + 26 + 4 + read-write + + + BLC_FILTER_EN + this bit configures enable blc average input filter. 0: disable, 1: enable + 30 + 1 + read-write + + + + + BLC_CTRL2 + blc black threshold control register + 0x19C + 0x20 + + + BLC_R3_TH + this field configures black threshold when get blc average of bottom right channel + 0 + 8 + read-write + + + BLC_R2_TH + this field configures black threshold when get blc average of bottom left channel + 8 + 8 + read-write + + + BLC_R1_TH + this field configures black threshold when get blc average of top right channel + 16 + 8 + read-write + + + BLC_R0_TH + this field configures black threshold when get blc average of top left channel + 24 + 8 + read-write + + + + + BLC_MEAN + results of the average of black window + 0x1A0 + 0x20 + + + BLC_R3_MEAN + this field represents the average black value of bottom right channel + 0 + 8 + read-only + + + BLC_R2_MEAN + this field represents the average black value of bottom left channel + 8 + 8 + read-only + + + BLC_R1_MEAN + this field represents the average black value of top right channel + 16 + 8 + read-only + + + BLC_R0_MEAN + this field represents the average black value of top left channel + 24 + 8 + read-only + + + + + HIST_MODE + histogram mode control register + 0x1A4 + 0x20 + 0x00000004 + + + HIST_MODE + this field configures statistic mode. 0: RAW_B, 1: RAW_GB, 2: RAW_GR 3: RAW_R, 4: RGB, 5:YUV_Y, 6:YUV_U, 7:YUV_V + 0 + 3 + read-write + + + + + HIST_COEFF + histogram rgb to gray coefficients register + 0x1A8 + 0x20 + 0x00555555 + + + B + this field configures coefficient of B when set hist_mode to RGB, sum of coeff_r and coeff_g and coeff_b should be 256 + 0 + 8 + read-write + + + G + this field configures coefficient of G when set hist_mode to RGB, sum of coeff_r and coeff_g and coeff_b should be 256 + 8 + 8 + read-write + + + R + this field configures coefficient of R when set hist_mode to RGB, sum of coeff_r and coeff_g and coeff_b should be 256 + 16 + 8 + read-write + + + + + HIST_OFFS + histogram window offsets register + 0x1AC + 0x20 + + + HIST_Y_OFFS + this field configures y coordinate of first window + 0 + 12 + read-write + + + HIST_X_OFFS + this field configures x coordinate of first window + 16 + 12 + read-write + + + + + HIST_SIZE + histogram sub-window size register + 0x1B0 + 0x20 + 0x00120020 + + + HIST_Y_SIZE + this field configures y direction size of subwindow + 0 + 9 + read-write + + + HIST_X_SIZE + this field configures x direction size of subwindow + 16 + 9 + read-write + + + + + HIST_SEG0 + histogram bin control register 0 + 0x1B4 + 0x20 + 0x10203040 + + + HIST_SEG_3_4 + this field configures threshold of histogram bin 3 and bin 4 + 0 + 8 + read-write + + + HIST_SEG_2_3 + this field configures threshold of histogram bin 2 and bin 3 + 8 + 8 + read-write + + + HIST_SEG_1_2 + this field configures threshold of histogram bin 1 and bin 2 + 16 + 8 + read-write + + + HIST_SEG_0_1 + this field configures threshold of histogram bin 0 and bin 1 + 24 + 8 + read-write + + + + + HIST_SEG1 + histogram bin control register 1 + 0x1B8 + 0x20 + 0x50607080 + + + HIST_SEG_7_8 + this field configures threshold of histogram bin 7 and bin 8 + 0 + 8 + read-write + + + HIST_SEG_6_7 + this field configures threshold of histogram bin 6 and bin 7 + 8 + 8 + read-write + + + HIST_SEG_5_6 + this field configures threshold of histogram bin 5 and bin 6 + 16 + 8 + read-write + + + HIST_SEG_4_5 + this field configures threshold of histogram bin 4 and bin 5 + 24 + 8 + read-write + + + + + HIST_SEG2 + histogram bin control register 2 + 0x1BC + 0x20 + 0x90A0B0C0 + + + HIST_SEG_11_12 + this field configures threshold of histogram bin 11 and bin 12 + 0 + 8 + read-write + + + HIST_SEG_10_11 + this field configures threshold of histogram bin 10 and bin 11 + 8 + 8 + read-write + + + HIST_SEG_9_10 + this field configures threshold of histogram bin 9 and bin 10 + 16 + 8 + read-write + + + HIST_SEG_8_9 + this field configures threshold of histogram bin 8 and bin 9 + 24 + 8 + read-write + + + + + HIST_SEG3 + histogram bin control register 3 + 0x1C0 + 0x20 + 0x00D0E0F0 + + + HIST_SEG_14_15 + this field configures threshold of histogram bin 14 and bin 15 + 0 + 8 + read-write + + + HIST_SEG_13_14 + this field configures threshold of histogram bin 13 and bin 14 + 8 + 8 + read-write + + + HIST_SEG_12_13 + this field configures threshold of histogram bin 12 and bin 13 + 16 + 8 + read-write + + + + + HIST_WEIGHT0 + histogram sub-window weight register 0 + 0x1C4 + 0x20 + 0x01010101 + + + HIST_WEIGHT_03 + this field configures weight of subwindow 03 + 0 + 8 + read-write + + + HIST_WEIGHT_02 + this field configures weight of subwindow 02 + 8 + 8 + read-write + + + HIST_WEIGHT_01 + this field configures weight of subwindow 01 + 16 + 8 + read-write + + + HIST_WEIGHT_00 + this field configures weight of subwindow 00 and sum of all weight should be 256 + 24 + 8 + read-write + + + + + HIST_WEIGHT1 + histogram sub-window weight register 1 + 0x1C8 + 0x20 + 0x01010101 + + + HIST_WEIGHT_12 + this field configures weight of subwindow 12 + 0 + 8 + read-write + + + HIST_WEIGHT_11 + this field configures weight of subwindow 11 + 8 + 8 + read-write + + + HIST_WEIGHT_10 + this field configures weight of subwindow 10 + 16 + 8 + read-write + + + HIST_WEIGHT_04 + this field configures weight of subwindow 04 + 24 + 8 + read-write + + + + + HIST_WEIGHT2 + histogram sub-window weight register 2 + 0x1CC + 0x20 + 0x01010101 + + + HIST_WEIGHT_21 + this field configures weight of subwindow 21 + 0 + 8 + read-write + + + HIST_WEIGHT_20 + this field configures weight of subwindow 20 + 8 + 8 + read-write + + + HIST_WEIGHT_14 + this field configures weight of subwindow 04 + 16 + 8 + read-write + + + HIST_WEIGHT_13 + this field configures weight of subwindow 13 + 24 + 8 + read-write + + + + + HIST_WEIGHT3 + histogram sub-window weight register 3 + 0x1D0 + 0x20 + 0xE8010101 + + + HIST_WEIGHT_30 + this field configures weight of subwindow 30 + 0 + 8 + read-write + + + HIST_WEIGHT_24 + this field configures weight of subwindow 24 + 8 + 8 + read-write + + + HIST_WEIGHT_23 + this field configures weight of subwindow 23 + 16 + 8 + read-write + + + HIST_WEIGHT_22 + this field configures weight of subwindow 22 + 24 + 8 + read-write + + + + + HIST_WEIGHT4 + histogram sub-window weight register 4 + 0x1D4 + 0x20 + 0x01010101 + + + HIST_WEIGHT_34 + this field configures weight of subwindow 34 + 0 + 8 + read-write + + + HIST_WEIGHT_33 + this field configures weight of subwindow 33 + 8 + 8 + read-write + + + HIST_WEIGHT_32 + this field configures weight of subwindow 32 + 16 + 8 + read-write + + + HIST_WEIGHT_31 + this field configures weight of subwindow 31 + 24 + 8 + read-write + + + + + HIST_WEIGHT5 + histogram sub-window weight register 5 + 0x1D8 + 0x20 + 0x01010101 + + + HIST_WEIGHT_43 + this field configures weight of subwindow 43 + 0 + 8 + read-write + + + HIST_WEIGHT_42 + this field configures weight of subwindow 42 + 8 + 8 + read-write + + + HIST_WEIGHT_41 + this field configures weight of subwindow 41 + 16 + 8 + read-write + + + HIST_WEIGHT_40 + this field configures weight of subwindow 40 + 24 + 8 + read-write + + + + + HIST_WEIGHT6 + histogram sub-window weight register 6 + 0x1DC + 0x20 + 0x00000001 + + + HIST_WEIGHT_44 + this field configures weight of subwindow 44 + 0 + 8 + read-write + + + + + HIST_BIN0 + result of histogram bin 0 + 0x1E0 + 0x20 + + + HIST_BIN_0 + this field represents result of histogram bin 0 + 0 + 17 + read-only + + + + + HIST_BIN1 + result of histogram bin 1 + 0x1E4 + 0x20 + + + HIST_BIN_1 + this field represents result of histogram bin 1 + 0 + 17 + read-only + + + + + HIST_BIN2 + result of histogram bin 2 + 0x1E8 + 0x20 + + + HIST_BIN_2 + this field represents result of histogram bin 2 + 0 + 17 + read-only + + + + + HIST_BIN3 + result of histogram bin 3 + 0x1EC + 0x20 + + + HIST_BIN_3 + this field represents result of histogram bin 3 + 0 + 17 + read-only + + + + + HIST_BIN4 + result of histogram bin 4 + 0x1F0 + 0x20 + + + HIST_BIN_4 + this field represents result of histogram bin 4 + 0 + 17 + read-only + + + + + HIST_BIN5 + result of histogram bin 5 + 0x1F4 + 0x20 + + + HIST_BIN_5 + this field represents result of histogram bin 5 + 0 + 17 + read-only + + + + + HIST_BIN6 + result of histogram bin 6 + 0x1F8 + 0x20 + + + HIST_BIN_6 + this field represents result of histogram bin 6 + 0 + 17 + read-only + + + + + HIST_BIN7 + result of histogram bin 7 + 0x1FC + 0x20 + + + HIST_BIN_7 + this field represents result of histogram bin 7 + 0 + 17 + read-only + + + + + HIST_BIN8 + result of histogram bin 8 + 0x200 + 0x20 + + + HIST_BIN_8 + this field represents result of histogram bin 8 + 0 + 17 + read-only + + + + + HIST_BIN9 + result of histogram bin 9 + 0x204 + 0x20 + + + HIST_BIN_9 + this field represents result of histogram bin 9 + 0 + 17 + read-only + + + + + HIST_BIN10 + result of histogram bin 10 + 0x208 + 0x20 + + + HIST_BIN_10 + this field represents result of histogram bin 10 + 0 + 17 + read-only + + + + + HIST_BIN11 + result of histogram bin 11 + 0x20C + 0x20 + + + HIST_BIN_11 + this field represents result of histogram bin 11 + 0 + 17 + read-only + + + + + HIST_BIN12 + result of histogram bin 12 + 0x210 + 0x20 + + + HIST_BIN_12 + this field represents result of histogram bin 12 + 0 + 17 + read-only + + + + + HIST_BIN13 + result of histogram bin 13 + 0x214 + 0x20 + + + HIST_BIN_13 + this field represents result of histogram bin 13 + 0 + 17 + read-only + + + + + HIST_BIN14 + result of histogram bin 14 + 0x218 + 0x20 + + + HIST_BIN_14 + this field represents result of histogram bin 14 + 0 + 17 + read-only + + + + + HIST_BIN15 + result of histogram bin 15 + 0x21C + 0x20 + + + HIST_BIN_15 + this field represents result of histogram bin 15 + 0 + 17 + read-only + + + + + MEM_AUX_CTRL_0 + mem aux control register 0 + 0x220 + 0x20 + 0x13201320 + + + HEADER_MEM_AUX_CTRL + this field configures the mem_aux of isp input buffer memory + 0 + 14 + read-write + + + DPC_LUT_MEM_AUX_CTRL + this field represents this field configures the mem_aux of dpc lut memory + 16 + 14 + read-write + + + + + MEM_AUX_CTRL_1 + mem aux control register 1 + 0x224 + 0x20 + 0x13201320 + + + LSC_LUT_R_GR_MEM_AUX_CTRL + this field configures the mem_aux of lsc r gr lut memory + 0 + 14 + read-write + + + LSC_LUT_GB_B_MEM_AUX_CTRL + this field configures the mem_aux of lsc gb b lut memory + 16 + 14 + read-write + + + + + MEM_AUX_CTRL_2 + mem aux control register 2 + 0x228 + 0x20 + 0x13201320 + + + BF_MATRIX_MEM_AUX_CTRL + this field configures the mem_aux of bf line buffer memory + 0 + 14 + read-write + + + DPC_MATRIX_MEM_AUX_CTRL + this field configures the mem_aux of dpc line buffer memory + 16 + 14 + read-write + + + + + MEM_AUX_CTRL_3 + mem aux control register 3 + 0x22C + 0x20 + 0x13201320 + + + SHARP_MATRIX_Y_MEM_AUX_CTRL + this field configures the mem_aux of sharp y line buffer memory + 0 + 14 + read-write + + + DEMOSAIC_MATRIX_MEM_AUX_CTRL + this field configures the mem_aux of demosaic line buffer memory + 16 + 14 + read-write + + + + + MEM_AUX_CTRL_4 + mem aux control register 4 + 0x230 + 0x20 + 0x00001320 + + + SHARP_MATRIX_UV_MEM_AUX_CTRL + this field configures the mem_aux of sharp uv line buffer memory + 0 + 14 + read-write + + + + + YUV_FORMAT + yuv format control register + 0x234 + 0x20 + + + YUV_MODE + this bit configures the yuv mode. 0: ITU-R BT.601, 1: ITU-R BT.709 + 0 + 1 + read-write + + + YUV_RANGE + this bit configures the yuv range. 0: full range, 1: limit range + 1 + 1 + read-write + + + + + RDN_ECO_CS + rdn eco cs register + 0x238 + 0x20 + + + RDN_ECO_EN + rdn_eco_en + 0 + 1 + read-write + + + RDN_ECO_RESULT + rdn_eco_result + 1 + 1 + read-only + + + + + RDN_ECO_LOW + rdn eco all low register + 0x23C + 0x20 + + + RDN_ECO_LOW + rdn_eco_low + 0 + 32 + read-write + + + + + RDN_ECO_HIGH + rdn eco all high register + 0x240 + 0x20 + 0xFFFFFFFF + + + RDN_ECO_HIGH + rdn_eco_high + 0 + 32 + read-write + + + + + + + JPEG + JPEG Codec + JPEG + 0x50086000 + + 0x0 + 0xB0 + registers + + + JPEG + 95 + + + + CONFIG + Control and configuration registers + 0x0 + 0x20 + 0x00408958 + + + FSM_RST + fsm reset + 0 + 1 + write-only + + + JPEG_START + start to compress a new pic(in dma reg mode) + 1 + 1 + write-only + + + QNR_PRESITION + 0:8bit qnr,1:12bit qnr(TBD) + 2 + 1 + read-write + + + FF_CHECK_EN + enable whether to add "00" after "ff" + 3 + 1 + read-write + + + SAMPLE_SEL + 0:yuv444,1:yuv422, 2:yuv420 + 4 + 2 + read-write + + + DMA_LINKLIST_MODE + 1:use linklist to configure dma + 6 + 1 + read-only + + + DEBUG_DIRECT_OUT_EN + 0:normal mode,1:debug mode for direct output from input + 7 + 1 + read-write + + + GRAY_SEL + 0:use non-fifo way to access qnr ram,1:use fifo way to access qnr ram + 8 + 1 + read-write + + + LQNR_TBL_SEL + choose luminance quntization table id(TBD) + 9 + 2 + read-write + + + CQNR_TBL_SEL + choose chrominance quntization table id (TBD) + 11 + 2 + read-write + + + COLOR_SPACE + configure picture's color space:0-rb888,1-yuv422,2-rgb565, 3-gray + 13 + 2 + read-write + + + DHT_FIFO_EN + 0:use non-fifo way to write dht len_total/codemin/value table,1:use fifo way to write dht len_total/codemin/value table. Reading dht len_total/codemin/value table only has nonfifo way + 15 + 1 + read-write + + + MEM_CLK_FORCE_ON + force memory's clock enabled + 16 + 1 + read-write + + + JFIF_VER + decode pause period to trigger decode_timeout int, the timeout periods =2 power (reg_decode_timeout_thres) -1 + 17 + 6 + read-write + + + DECODE_TIMEOUT_TASK_SEL + 0: software use reset to abort decode process ,1: decoder abort decode process by itself + 23 + 1 + read-write + + + SOFT_RST + when set to 1, soft reset JPEG module except jpeg_reg module + 24 + 1 + read-write + + + FIFO_RST + fifo reset + 25 + 1 + read-write + + + PIXEL_REV + reverse the source color pixel + 26 + 1 + read-write + + + TAILER_EN + set this bit to add EOI of "0xffd9" at the end of bitstream + 27 + 1 + read-write + + + PAUSE_EN + set this bit to pause jpeg encoding + 28 + 1 + read-write + + + MEM_FORCE_PD + 0: no operation,1:force jpeg memory to power down + 29 + 1 + read-write + + + MEM_FORCE_PU + 0: no operation,1:force jpeg memory to power up + 30 + 1 + read-write + + + MODE + 0:encoder mode, 1: decoder mode + 31 + 1 + read-write + + + + + DQT_INFO + Control and configuration registers + 0x4 + 0x20 + 0x03020100 + + + T0_DQT_INFO + Configure dqt table0's quantization coefficient precision in bit[7:4], configure dqt table0's table id in bit[3:0] + 0 + 8 + read-write + + + T1_DQT_INFO + Configure dqt table1's quantization coefficient precision in bit[7:4], configure dqt table1's table id in bit[3:0] + 8 + 8 + read-write + + + T2_DQT_INFO + Configure dqt table2's quantization coefficient precision in bit[7:4], configure dqt table2's table id in bit[3:0] + 16 + 8 + read-write + + + T3_DQT_INFO + Configure dqt table3's quantization coefficient precision in bit[7:4], configure dqt table3's table id in bit[3:0] + 24 + 8 + read-write + + + + + PIC_SIZE + Control and configuration registers + 0x8 + 0x20 + 0x028001E0 + + + VA + configure picture's height. when encode, the max configurable bits is 14, when decode, the max configurable bits is 16 + 0 + 16 + read-write + + + HA + configure picture's width. when encode, the max configurable bits is 14, when decode, the max configurable bits is 16 + 16 + 16 + read-write + + + + + T0QNR + Control and configuration registers + 0x10 + 0x20 + + + T0_QNR_VAL + write this reg to configure 64 quantization coefficient in t0 table + 0 + 32 + read-only + + + + + T1QNR + Control and configuration registers + 0x14 + 0x20 + + + CHROMINANCE_QNR_VAL + write this reg to configure 64 quantization coefficient in t1 table + 0 + 32 + read-only + + + + + T2QNR + Control and configuration registers + 0x18 + 0x20 + + + T2_QNR_VAL + write this reg to configure 64 quantization coefficient in t2 table + 0 + 32 + read-only + + + + + T3QNR + Control and configuration registers + 0x1C + 0x20 + + + T3_QNR_VAL + write this reg to configure 64 quantization coefficient in t3 table + 0 + 32 + read-only + + + + + DECODE_CONF + Control and configuration registers + 0x20 + 0x20 + 0x5F030000 + + + RESTART_INTERVAL + configure restart interval in DRI marker when decode + 0 + 16 + read-write + + + COMPONENT_NUM + configure number of components in frame when decode + 16 + 8 + read-write + + + SW_DHT_EN + software decode dht table enable + 24 + 1 + read-only + + + SOS_CHECK_BYTE_NUM + Configure the byte number to check next sos marker in the multi-scan picture after one scan is decoded down. The real check number is reg_sos_check_byte_num+1 + 25 + 2 + read-write + + + RST_CHECK_BYTE_NUM + Configure the byte number to check next rst marker after one rst interval is decoded down. The real check number is reg_rst_check_byte_num+1 + 27 + 2 + read-write + + + MULTI_SCAN_ERR_CHECK + reserved for decoder + 29 + 1 + read-write + + + DEZIGZAG_READY_CTL + reserved for decoder + 30 + 1 + read-write + + + + + C0 + Control and configuration registers + 0x24 + 0x20 + 0x00001100 + + + DQT_TBL_SEL + choose c0 quntization table id (TBD) + 0 + 8 + read-write + + + Y_FACTOR + vertical sampling factor of c0 + 8 + 4 + read-write + + + X_FACTOR + horizontal sampling factor of c0 + 12 + 4 + read-write + + + ID + the identifier of c0 + 16 + 8 + read-write + + + + + C1 + Control and configuration registers + 0x28 + 0x20 + 0x00001100 + + + DQT_TBL_SEL + choose c1 quntization table id (TBD) + 0 + 8 + read-write + + + Y_FACTOR + vertical sampling factor of c1 + 8 + 4 + read-write + + + X_FACTOR + horizontal sampling factor of c1 + 12 + 4 + read-write + + + ID + the identifier of c1 + 16 + 8 + read-write + + + + + C2 + Control and configuration registers + 0x2C + 0x20 + 0x00001100 + + + DQT_TBL_SEL + choose c2 quntization table id (TBD) + 0 + 8 + read-write + + + Y_FACTOR + vertical sampling factor of c2 + 8 + 4 + read-write + + + X_FACTOR + horizontal sampling factor of c2 + 12 + 4 + read-write + + + ID + the identifier of c2 + 16 + 8 + read-write + + + + + C3 + Control and configuration registers + 0x30 + 0x20 + 0x00001100 + + + DQT_TBL_SEL + choose c3 quntization table id (TBD) + 0 + 8 + read-write + + + Y_FACTOR + vertical sampling factor of c3 + 8 + 4 + read-write + + + X_FACTOR + horizontal sampling factor of c3 + 12 + 4 + read-write + + + ID + the identifier of c3 + 16 + 8 + read-write + + + + + DHT_INFO + Control and configuration registers + 0x34 + 0x20 + 0x00001010 + + + DC0_DHT_ID + configure dht dc table 0 id + 0 + 4 + read-write + + + DC1_DHT_ID + configure dht dc table 1 id + 4 + 4 + read-write + + + AC0_DHT_ID + configure dht ac table 0 id + 8 + 4 + read-write + + + AC1_DHT_ID + configure dht ac table 1 id + 12 + 4 + read-write + + + + + INT_RAW + Interrupt raw registers + 0x38 + 0x20 + + + DONE_INT_RAW + This raw interrupt bit turns to high level when JPEG finishes encoding a picture.. + 0 + 1 + read-write + + + RLE_PARALLEL_ERR_INT_RAW + The raw interrupt bit to sign that rle parallel error when decoding. + 1 + 1 + read-write + + + CID_ERR_INT_RAW + The raw interrupt bit to sign that scan id check with component fails when decoding. + 2 + 1 + read-write + + + C_DHT_DC_ID_ERR_INT_RAW + The raw interrupt bit to sign that scan component's dc dht id check with dc dht table's id fails when decoding. + 3 + 1 + read-write + + + C_DHT_AC_ID_ERR_INT_RAW + The raw interrupt bit to sign that scan component's ac dht id check with ac dht table's id fails when decoding. + 4 + 1 + read-write + + + C_DQT_ID_ERR_INT_RAW + The raw interrupt bit to sign that scan component's dqt id check with dqt table's id fails when decoding. + 5 + 1 + read-write + + + RST_UXP_ERR_INT_RAW + The raw interrupt bit to sign that RST header marker is detected but restart interval is 0 when decoding. + 6 + 1 + read-write + + + RST_CHECK_NONE_ERR_INT_RAW + The raw interrupt bit to sign that RST header marker is not detected but restart interval is not 0 when decoding. + 7 + 1 + read-write + + + RST_CHECK_POS_ERR_INT_RAW + The raw interrupt bit to sign that RST header marker position mismatches with restart interval when decoding. + 8 + 1 + read-write + + + OUT_EOF_INT_RAW + The raw interrupt bit turns to high level when the last pixel of one square has been transmitted for Tx channel. + 9 + 1 + read-write + + + SR_COLOR_MODE_ERR_INT_RAW + The raw interrupt bit to sign that the selected source color mode is not supported. + 10 + 1 + read-write + + + DCT_DONE_INT_RAW + The raw interrupt bit to sign that one dct calculation is finished. + 11 + 1 + read-write + + + BS_LAST_BLOCK_EOF_INT_RAW + The raw interrupt bit to sign that the coding process for last block is finished. + 12 + 1 + read-write + + + SCAN_CHECK_NONE_ERR_INT_RAW + The raw interrupt bit to sign that SOS header marker is not detected but there are still components left to be decoded. + 13 + 1 + read-write + + + SCAN_CHECK_POS_ERR_INT_RAW + The raw interrupt bit to sign that SOS header marker position wrong when decoding. + 14 + 1 + read-write + + + UXP_DET_INT_RAW + The raw interrupt bit to sign that unsupported header marker is detected when decoding. + 15 + 1 + read-write + + + EN_FRAME_EOF_ERR_INT_RAW + The raw interrupt bit to sign that received pixel blocks are smaller than expected when encoding. + 16 + 1 + read-write + + + EN_FRAME_EOF_LACK_INT_RAW + The raw interrupt bit to sign that the frame eof sign bit from dma input is missing when encoding. But the number of pixel blocks is enough. + 17 + 1 + read-write + + + DE_FRAME_EOF_ERR_INT_RAW + The raw interrupt bit to sign that decoded blocks are smaller than expected when decoding. + 18 + 1 + read-write + + + DE_FRAME_EOF_LACK_INT_RAW + The raw interrupt bit to sign that the either frame eof from dma input or eoi marker is missing when encoding. But the number of decoded blocks is enough. + 19 + 1 + read-write + + + SOS_UNMATCH_ERR_INT_RAW + The raw interrupt bit to sign that the component number of a scan is 0 or does not match the sos marker's length when decoding. + 20 + 1 + read-write + + + MARKER_ERR_FST_SCAN_INT_RAW + The raw interrupt bit to sign that the first scan has header marker error when decoding. + 21 + 1 + read-write + + + MARKER_ERR_OTHER_SCAN_INT_RAW + The raw interrupt bit to sign that the following scans but not the first scan have header marker error when decoding. + 22 + 1 + read-write + + + UNDET_INT_RAW + The raw interrupt bit to sign that JPEG format is not detected at the eof data of a packet when decoding. + 23 + 1 + read-write + + + DECODE_TIMEOUT_INT_RAW + The raw interrupt bit to sign that decode pause time is longer than the setting decode timeout time when decoding. + 24 + 1 + read-write + + + + + INT_ENA + Interrupt enable registers + 0x3C + 0x20 + + + DONE_INT_ENA + This enable interrupt bit turns to high level when JPEG finishes encoding a picture.. + 0 + 1 + read-write + + + RLE_PARALLEL_ERR_INT_ENA + The enable interrupt bit to sign that rle parallel error when decoding. + 1 + 1 + read-write + + + CID_ERR_INT_ENA + The enable interrupt bit to sign that scan id check with component fails when decoding. + 2 + 1 + read-write + + + C_DHT_DC_ID_ERR_INT_ENA + The enable interrupt bit to sign that scan component's dc dht id check with dc dht table's id fails when decoding. + 3 + 1 + read-write + + + C_DHT_AC_ID_ERR_INT_ENA + The enable interrupt bit to sign that scan component's ac dht id check with ac dht table's id fails when decoding. + 4 + 1 + read-write + + + C_DQT_ID_ERR_INT_ENA + The enable interrupt bit to sign that scan component's dqt id check with dqt table's id fails when decoding. + 5 + 1 + read-write + + + RST_UXP_ERR_INT_ENA + The enable interrupt bit to sign that RST header marker is detected but restart interval is 0 when decoding. + 6 + 1 + read-write + + + RST_CHECK_NONE_ERR_INT_ENA + The enable interrupt bit to sign that RST header marker is not detected but restart interval is not 0 when decoding. + 7 + 1 + read-write + + + RST_CHECK_POS_ERR_INT_ENA + The enable interrupt bit to sign that RST header marker position mismatches with restart interval when decoding. + 8 + 1 + read-write + + + OUT_EOF_INT_ENA + The enable interrupt bit turns to high level when the last pixel of one square has been transmitted for Tx channel. + 9 + 1 + read-write + + + SR_COLOR_MODE_ERR_INT_ENA + The enable interrupt bit to sign that the selected source color mode is not supported. + 10 + 1 + read-write + + + DCT_DONE_INT_ENA + The enable interrupt bit to sign that one dct calculation is finished. + 11 + 1 + read-write + + + BS_LAST_BLOCK_EOF_INT_ENA + The enable interrupt bit to sign that the coding process for last block is finished. + 12 + 1 + read-write + + + SCAN_CHECK_NONE_ERR_INT_ENA + The enable interrupt bit to sign that SOS header marker is not detected but there are still components left to be decoded. + 13 + 1 + read-write + + + SCAN_CHECK_POS_ERR_INT_ENA + The enable interrupt bit to sign that SOS header marker position wrong when decoding. + 14 + 1 + read-write + + + UXP_DET_INT_ENA + The enable interrupt bit to sign that unsupported header marker is detected when decoding. + 15 + 1 + read-write + + + EN_FRAME_EOF_ERR_INT_ENA + The enable interrupt bit to sign that received pixel blocks are smaller than expected when encoding. + 16 + 1 + read-write + + + EN_FRAME_EOF_LACK_INT_ENA + The enable interrupt bit to sign that the frame eof sign bit from dma input is missing when encoding. But the number of pixel blocks is enough. + 17 + 1 + read-write + + + DE_FRAME_EOF_ERR_INT_ENA + The enable interrupt bit to sign that decoded blocks are smaller than expected when decoding. + 18 + 1 + read-write + + + DE_FRAME_EOF_LACK_INT_ENA + The enable interrupt bit to sign that the either frame eof from dma input or eoi marker is missing when encoding. But the number of decoded blocks is enough. + 19 + 1 + read-write + + + SOS_UNMATCH_ERR_INT_ENA + The enable interrupt bit to sign that the component number of a scan is 0 or does not match the sos marker's length when decoding. + 20 + 1 + read-write + + + MARKER_ERR_FST_SCAN_INT_ENA + The enable interrupt bit to sign that the first scan has header marker error when decoding. + 21 + 1 + read-write + + + MARKER_ERR_OTHER_SCAN_INT_ENA + The enable interrupt bit to sign that the following scans but not the first scan have header marker error when decoding. + 22 + 1 + read-write + + + UNDET_INT_ENA + The enable interrupt bit to sign that JPEG format is not detected at the eof data of a packet when decoding. + 23 + 1 + read-write + + + DECODE_TIMEOUT_INT_ENA + The enable interrupt bit to sign that decode pause time is longer than the setting decode timeout time when decoding. + 24 + 1 + read-write + + + + + INT_ST + Interrupt status registers + 0x40 + 0x20 + + + DONE_INT_ST + This status interrupt bit turns to high level when JPEG finishes encoding a picture.. + 0 + 1 + read-only + + + RLE_PARALLEL_ERR_INT_ST + The status interrupt bit to sign that rle parallel error when decoding. + 1 + 1 + read-only + + + CID_ERR_INT_ST + The status interrupt bit to sign that scan id check with component fails when decoding. + 2 + 1 + read-only + + + C_DHT_DC_ID_ERR_INT_ST + The status interrupt bit to sign that scan component's dc dht id check with dc dht table's id fails when decoding. + 3 + 1 + read-only + + + C_DHT_AC_ID_ERR_INT_ST + The status interrupt bit to sign that scan component's ac dht id check with ac dht table's id fails when decoding. + 4 + 1 + read-only + + + C_DQT_ID_ERR_INT_ST + The status interrupt bit to sign that scan component's dqt id check with dqt table's id fails when decoding. + 5 + 1 + read-only + + + RST_UXP_ERR_INT_ST + The status interrupt bit to sign that RST header marker is detected but restart interval is 0 when decoding. + 6 + 1 + read-only + + + RST_CHECK_NONE_ERR_INT_ST + The status interrupt bit to sign that RST header marker is not detected but restart interval is not 0 when decoding. + 7 + 1 + read-only + + + RST_CHECK_POS_ERR_INT_ST + The status interrupt bit to sign that RST header marker position mismatches with restart interval when decoding. + 8 + 1 + read-only + + + OUT_EOF_INT_ST + The status interrupt bit turns to high level when the last pixel of one square has been transmitted for Tx channel. + 9 + 1 + read-only + + + SR_COLOR_MODE_ERR_INT_ST + The status interrupt bit to sign that the selected source color mode is not supported. + 10 + 1 + read-only + + + DCT_DONE_INT_ST + The status interrupt bit to sign that one dct calculation is finished. + 11 + 1 + read-only + + + BS_LAST_BLOCK_EOF_INT_ST + The status interrupt bit to sign that the coding process for last block is finished. + 12 + 1 + read-only + + + SCAN_CHECK_NONE_ERR_INT_ST + The status interrupt bit to sign that SOS header marker is not detected but there are still components left to be decoded. + 13 + 1 + read-only + + + SCAN_CHECK_POS_ERR_INT_ST + The status interrupt bit to sign that SOS header marker position wrong when decoding. + 14 + 1 + read-only + + + UXP_DET_INT_ST + The status interrupt bit to sign that unsupported header marker is detected when decoding. + 15 + 1 + read-only + + + EN_FRAME_EOF_ERR_INT_ST + The status interrupt bit to sign that received pixel blocks are smaller than expected when encoding. + 16 + 1 + read-only + + + EN_FRAME_EOF_LACK_INT_ST + The status interrupt bit to sign that the frame eof sign bit from dma input is missing when encoding. But the number of pixel blocks is enough. + 17 + 1 + read-only + + + DE_FRAME_EOF_ERR_INT_ST + The status interrupt bit to sign that decoded blocks are smaller than expected when decoding. + 18 + 1 + read-only + + + DE_FRAME_EOF_LACK_INT_ST + The status interrupt bit to sign that the either frame eof from dma input or eoi marker is missing when encoding. But the number of decoded blocks is enough. + 19 + 1 + read-only + + + SOS_UNMATCH_ERR_INT_ST + The status interrupt bit to sign that the component number of a scan is 0 or does not match the sos marker's length when decoding. + 20 + 1 + read-only + + + MARKER_ERR_FST_SCAN_INT_ST + The status interrupt bit to sign that the first scan has header marker error when decoding. + 21 + 1 + read-only + + + MARKER_ERR_OTHER_SCAN_INT_ST + The status interrupt bit to sign that the following scans but not the first scan have header marker error when decoding. + 22 + 1 + read-only + + + UNDET_INT_ST + The status interrupt bit to sign that JPEG format is not detected at the eof data of a packet when decoding. + 23 + 1 + read-only + + + DECODE_TIMEOUT_INT_ST + The status interrupt bit to sign that decode pause time is longer than the setting decode timeout time when decoding. + 24 + 1 + read-only + + + + + INT_CLR + Interrupt clear registers + 0x44 + 0x20 + + + DONE_INT_CLR + This clear interrupt bit turns to high level when JPEG finishes encoding a picture.. + 0 + 1 + write-only + + + RLE_PARALLEL_ERR_INT_CLR + The clear interrupt bit to sign that rle parallel error when decoding. + 1 + 1 + write-only + + + CID_ERR_INT_CLR + The clear interrupt bit to sign that scan id check with component fails when decoding. + 2 + 1 + write-only + + + C_DHT_DC_ID_ERR_INT_CLR + The clear interrupt bit to sign that scan component's dc dht id check with dc dht table's id fails when decoding. + 3 + 1 + write-only + + + C_DHT_AC_ID_ERR_INT_CLR + The clear interrupt bit to sign that scan component's ac dht id check with ac dht table's id fails when decoding. + 4 + 1 + write-only + + + C_DQT_ID_ERR_INT_CLR + The clear interrupt bit to sign that scan component's dqt id check with dqt table's id fails when decoding. + 5 + 1 + write-only + + + RST_UXP_ERR_INT_CLR + The clear interrupt bit to sign that RST header marker is detected but restart interval is 0 when decoding. + 6 + 1 + write-only + + + RST_CHECK_NONE_ERR_INT_CLR + The clear interrupt bit to sign that RST header marker is not detected but restart interval is not 0 when decoding. + 7 + 1 + write-only + + + RST_CHECK_POS_ERR_INT_CLR + The clear interrupt bit to sign that RST header marker position mismatches with restart interval when decoding. + 8 + 1 + write-only + + + OUT_EOF_INT_CLR + The clear interrupt bit turns to high level when the last pixel of one square has been transmitted for Tx channel. + 9 + 1 + write-only + + + SR_COLOR_MODE_ERR_INT_CLR + The clear interrupt bit to sign that the selected source color mode is not supported. + 10 + 1 + write-only + + + DCT_DONE_INT_CLR + The clear interrupt bit to sign that one dct calculation is finished. + 11 + 1 + write-only + + + BS_LAST_BLOCK_EOF_INT_CLR + The clear interrupt bit to sign that the coding process for last block is finished. + 12 + 1 + write-only + + + SCAN_CHECK_NONE_ERR_INT_CLR + The clear interrupt bit to sign that SOS header marker is not detected but there are still components left to be decoded. + 13 + 1 + write-only + + + SCAN_CHECK_POS_ERR_INT_CLR + The clear interrupt bit to sign that SOS header marker position wrong when decoding. + 14 + 1 + write-only + + + UXP_DET_INT_CLR + The clear interrupt bit to sign that unsupported header marker is detected when decoding. + 15 + 1 + write-only + + + EN_FRAME_EOF_ERR_INT_CLR + The clear interrupt bit to sign that received pixel blocks are smaller than expected when encoding. + 16 + 1 + write-only + + + EN_FRAME_EOF_LACK_INT_CLR + The clear interrupt bit to sign that the frame eof sign bit from dma input is missing when encoding. But the number of pixel blocks is enough. + 17 + 1 + write-only + + + DE_FRAME_EOF_ERR_INT_CLR + The clear interrupt bit to sign that decoded blocks are smaller than expected when decoding. + 18 + 1 + write-only + + + DE_FRAME_EOF_LACK_INT_CLR + The clear interrupt bit to sign that the either frame eof from dma input or eoi marker is missing when encoding. But the number of decoded blocks is enough. + 19 + 1 + write-only + + + SOS_UNMATCH_ERR_INT_CLR + The clear interrupt bit to sign that the component number of a scan is 0 or does not match the sos marker's length when decoding. + 20 + 1 + write-only + + + MARKER_ERR_FST_SCAN_INT_CLR + The clear interrupt bit to sign that the first scan has header marker error when decoding. + 21 + 1 + write-only + + + MARKER_ERR_OTHER_SCAN_INT_CLR + The clear interrupt bit to sign that the following scans but not the first scan have header marker error when decoding. + 22 + 1 + write-only + + + UNDET_INT_CLR + The clear interrupt bit to sign that JPEG format is not detected at the eof data of a packet when decoding. + 23 + 1 + write-only + + + DECODE_TIMEOUT_INT_CLR + The clear interrupt bit to sign that decode pause time is longer than the setting decode timeout time when decoding. + 24 + 1 + write-only + + + + + STATUS0 + Trace and Debug registers + 0x48 + 0x20 + + + BITSTREAM_EOF_VLD_CNT + the valid bit count for last bitstream + 11 + 6 + read-only + + + DCTOUT_ZZSCAN_ADDR + the zig-zag read addr from dctout_ram + 17 + 6 + read-only + + + QNRVAL_ZZSCAN_ADDR + the zig-zag read addr from qnrval_ram + 23 + 6 + read-only + + + REG_STATE_YUV + the state of jpeg fsm + 29 + 3 + read-only + + + + + STATUS2 + Trace and Debug registers + 0x4C + 0x20 + 0x08000000 + + + SOURCE_PIXEL + source pixels fetched from dma + 0 + 24 + read-only + + + LAST_BLOCK + indicate the encoding process for the last mcu of the picture + 24 + 1 + read-only + + + LAST_MCU + indicate the encoding process for the last block of the picture + 25 + 1 + read-only + + + LAST_DC + indicate the encoding process is at the header of the last block of the picture + 26 + 1 + read-only + + + PACKFIFO_READY + the jpeg pack_fifo ready signal, high active + 27 + 1 + read-only + + + + + STATUS3 + Trace and Debug registers + 0x50 + 0x20 + + + YO + component y transferred from rgb input + 0 + 9 + read-only + + + Y_READY + component y valid signal, high active + 9 + 1 + read-only + + + CBO + component cb transferred from rgb input + 10 + 9 + read-only + + + CB_READY + component cb valid signal, high active + 19 + 1 + read-only + + + CRO + component cr transferred from rgb input + 20 + 9 + read-only + + + CR_READY + component cr valid signal, high active + 29 + 1 + read-only + + + + + STATUS4 + Trace and Debug registers + 0x54 + 0x20 + + + HFM_BITSTREAM + the hufman bitstream during encoding process + 0 + 32 + read-only + + + + + DHT_TOTLEN_DC0 + Trace and Debug registers + 0x58 + 0x20 + + + DHT_TOTLEN_DC0 + write the numbers of 1~n codeword length sum from 1~16 of dc0 table + 0 + 32 + read-only + + + + + DHT_VAl_DC0 + Trace and Debug registers + 0x5C + 0x20 + + + DHT_VAL_DC0 + write codeword corresponding huffman values of dc0 table + 0 + 32 + read-only + + + + + DHT_TOTLEN_AC0 + Trace and Debug registers + 0x60 + 0x20 + + + DHT_TOTLEN_AC0 + write the numbers of 1~n codeword length sum from 1~16 of ac0 table + 0 + 32 + read-only + + + + + DHT_VAl_AC0 + Trace and Debug registers + 0x64 + 0x20 + + + DHT_VAL_AC0 + write codeword corresponding huffman values of ac0 table + 0 + 32 + read-only + + + + + DHT_TOTLEN_DC1 + Trace and Debug registers + 0x68 + 0x20 + + + DHT_TOTLEN_DC1 + write the numbers of 1~n codeword length sum from 1~16 of dc1 table + 0 + 32 + read-only + + + + + DHT_VAl_DC1 + Trace and Debug registers + 0x6C + 0x20 + + + DHT_VAL_DC1 + write codeword corresponding huffman values of dc1 table + 0 + 32 + read-only + + + + + DHT_TOTLEN_AC1 + Trace and Debug registers + 0x70 + 0x20 + + + DHT_TOTLEN_AC1 + write the numbers of 1~n codeword length sum from 1~16 of ac1 table + 0 + 32 + read-only + + + + + DHT_VAl_AC1 + Trace and Debug registers + 0x74 + 0x20 + + + DHT_VAL_AC1 + write codeword corresponding huffman values of ac1 table + 0 + 32 + read-only + + + + + DHT_CODEMIN_DC0 + Trace and Debug registers + 0x78 + 0x20 + + + DHT_CODEMIN_DC0 + write the minimum codeword of code length from 1~16 of dc0 table. The codeword is left shifted to the MSB position of a 16bit word + 0 + 32 + read-only + + + + + DHT_CODEMIN_AC0 + Trace and Debug registers + 0x7C + 0x20 + + + DHT_CODEMIN_AC0 + write the minimum codeword of code length from 1~16 of ac0 table. The codeword is left shifted to the MSB position of a 16bit word + 0 + 32 + read-only + + + + + DHT_CODEMIN_DC1 + Trace and Debug registers + 0x80 + 0x20 + + + DHT_CODEMIN_DC1 + write the minimum codeword of code length from 1~16 of dc1 table. The codeword is left shifted to the MSB position of a 16bit word + 0 + 32 + read-only + + + + + DHT_CODEMIN_AC1 + Trace and Debug registers + 0x84 + 0x20 + + + DHT_CODEMIN_AC1 + write the minimum codeword of code length from 1~16 of ac1 table. The codeword is left shifted to the MSB position of a 16bit word + 0 + 32 + read-only + + + + + DECODER_STATUS0 + Trace and Debug registers + 0x88 + 0x20 + + + DECODE_BYTE_CNT + Reserved + 0 + 26 + read-only + + + HEADER_DEC_ST + Reserved + 26 + 4 + read-only + + + DECODE_SAMPLE_SEL + Reserved + 30 + 2 + read-only + + + + + DECODER_STATUS1 + Trace and Debug registers + 0x8C + 0x20 + + + ENCODE_DATA + Reserved + 0 + 16 + read-only + + + COUNT_Q + Reserved + 16 + 7 + read-only + + + MCU_FSM_READY + Reserved + 23 + 1 + read-only + + + DECODE_DATA + Reserved + 24 + 8 + read-only + + + + + DECODER_STATUS2 + Trace and Debug registers + 0x90 + 0x20 + + + COMP_BLOCK_NUM + Reserved + 0 + 26 + read-only + + + SCAN_NUM + Reserved + 26 + 3 + read-only + + + RST_CHECK_WAIT + Reserved + 29 + 1 + read-only + + + SCAN_CHECK_WAIT + Reserved + 30 + 1 + read-only + + + MCU_IN_PROC + Reserved + 31 + 1 + read-only + + + + + DECODER_STATUS3 + Trace and Debug registers + 0x94 + 0x20 + + + LOOKUP_DATA + Reserved + 0 + 32 + read-only + + + + + DECODER_STATUS4 + Trace and Debug registers + 0x98 + 0x20 + + + BLOCK_EOF_CNT + Reserved + 0 + 26 + read-only + + + DEZIGZAG_READY + Reserved + 26 + 1 + read-only + + + DE_FRAME_EOF_CHECK + Reserved + 27 + 1 + read-only + + + DE_DMA2D_IN_PUSH + Reserved + 28 + 1 + read-only + + + + + DECODER_STATUS5 + Trace and Debug registers + 0x9C + 0x20 + + + IDCT_HFM_DATA + Reserved + 0 + 16 + read-only + + + NS0 + Reserved + 16 + 3 + read-only + + + NS1 + Reserved + 19 + 3 + read-only + + + NS2 + Reserved + 22 + 3 + read-only + + + NS3 + Reserved + 25 + 3 + read-only + + + DATA_LAST_O + Reserved + 28 + 1 + read-only + + + RDN_RESULT + redundant registers for jpeg + 29 + 1 + read-only + + + RDN_ENA + redundant control registers for jpeg + 30 + 1 + read-write + + + + + STATUS5 + Trace and Debug registers + 0xA0 + 0x20 + + + PIC_BLOCK_NUM + Reserved + 0 + 24 + read-only + + + + + ECO_LOW + Trace and Debug registers + 0xA4 + 0x20 + + + RDN_ECO_LOW + redundant registers for jpeg + 0 + 32 + read-write + + + + + ECO_HIGH + Trace and Debug registers + 0xA8 + 0x20 + 0xFFFFFFFF + + + RDN_ECO_HIGH + redundant registers for jpeg + 0 + 32 + read-write + + + + + SYS + Trace and Debug registers + 0xF8 + 0x20 + + + CLK_EN + Reserved + 31 + 1 + read-write + + + + + VERSION + Trace and Debug registers + 0xFC + 0x20 + 0x02111190 + + + JPEG_VER + Reserved + 0 + 28 + read-write + + + + + + + LCD_CAM + Camera/LCD Controller + LCDCAM + 0x500DC000 + + 0x0 + 0x4C + registers + + + + LCD_CLOCK + LCD clock config register. + 0x0 + 0x20 + 0x00000843 + + + LCD_CLKCNT_N + f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0. + 0 + 6 + read-write + + + LCD_CLK_EQU_SYSCLK + 1: f_LCD_PCLK = f_LCD_CLK. 0: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1). + 6 + 1 + read-write + + + LCD_CK_IDLE_EDGE + 1: LCD_PCLK line is high when idle 0: LCD_PCLK line is low when idle. + 7 + 1 + read-write + + + LCD_CK_OUT_EDGE + 1: LCD_PCLK line is high in the first half data cycle. 0: LCD_PCLK line is low in the second half data cycle. + 8 + 1 + read-write + + + LCD_CLKM_DIV_NUM + Integral LCD clock divider value + 9 + 8 + read-write + + + LCD_CLKM_DIV_B + Fractional clock divider numerator value + 17 + 6 + read-write + + + LCD_CLKM_DIV_A + Fractional clock divider denominator value + 23 + 6 + read-write + + + LCD_CLK_SEL + Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock. + 29 + 2 + read-write + + + CLK_EN + Set this bit to enable clk gate + 31 + 1 + read-write + + + + + CAM_CTRL + CAM config register. + 0x4 + 0x20 + 0x00000800 + + + CAM_STOP_EN + Camera stop enable signal, 1: camera stops when DMA Rx FIFO is full. 0: Not stop. + 0 + 1 + read-write + + + CAM_VSYNC_FILTER_THRES + Filter threshold value for CAM_VSYNC signal. + 1 + 3 + read-write + + + CAM_UPDATE + 1: Update Camera registers, will be cleared by hardware. 0 : Not care. + 4 + 1 + read-write + + + CAM_BYTE_ORDER + 1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in one byte mode, and bits[15:0] to bits[0:15] in two byte mode. 0: Not change. + 5 + 1 + read-write + + + CAM_BIT_ORDER + 1: invert data byte order, only valid in 2 byte mode. 0: Not change. + 6 + 1 + read-write + + + CAM_LINE_INT_EN + 1: Enable to generate CAM_HS_INT. 0: Disable. + 7 + 1 + read-write + + + CAM_VS_EOF_EN + 1: CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by reg_cam_rec_data_cyclelen. + 8 + 1 + read-write + + + CAM_CLKM_DIV_NUM + Integral Camera clock divider value + 9 + 8 + read-write + + + CAM_CLKM_DIV_B + Fractional clock divider numerator value + 17 + 6 + read-write + + + CAM_CLKM_DIV_A + Fractional clock divider denominator value + 23 + 6 + read-write + + + CAM_CLK_SEL + Select Camera module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock. + 29 + 2 + read-write + + + + + CAM_CTRL1 + CAM config register. + 0x8 + 0x20 + + + CAM_REC_DATA_BYTELEN + Camera receive data byte length minus 1 to set DMA in_suc_eof_int. + 0 + 16 + read-write + + + CAM_LINE_INT_NUM + The line number minus 1 to generate cam_hs_int. + 16 + 6 + read-write + + + CAM_CLK_INV + 1: Invert the input signal CAM_PCLK. 0: Not invert. + 22 + 1 + read-write + + + CAM_VSYNC_FILTER_EN + 1: Enable CAM_VSYNC filter function. 0: bypass. + 23 + 1 + read-write + + + CAM_2BYTE_EN + 1: The bit number of input data is 9~16. 0: The bit number of input data is 0~8. + 24 + 1 + read-write + + + CAM_DE_INV + CAM_DE invert enable signal, valid in high level. + 25 + 1 + read-write + + + CAM_HSYNC_INV + CAM_HSYNC invert enable signal, valid in high level. + 26 + 1 + read-write + + + CAM_VSYNC_INV + CAM_VSYNC invert enable signal, valid in high level. + 27 + 1 + read-write + + + CAM_VH_DE_MODE_EN + 1: Input control signals are CAM_DE CAM_HSYNC and CAM_VSYNC. 0: Input control signals are CAM_DE and CAM_VSYNC. + 28 + 1 + read-write + + + CAM_START + Camera module start signal. + 29 + 1 + read-write + + + CAM_RESET + Camera module reset signal. + 30 + 1 + write-only + + + CAM_AFIFO_RESET + Camera AFIFO reset signal. + 31 + 1 + write-only + + + + + CAM_RGB_YUV + CAM YUV/RGB converter configuration register. + 0xC + 0x20 + 0x00C00000 + + + CAM_CONV_8BITS_DATA_INV + 1:invert every two 8bits input data. 2. disabled. + 21 + 1 + read-write + + + CAM_CONV_YUV2YUV_MODE + 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable yuv2yuv mode, trans_mode must be set to 1. + 22 + 2 + read-write + + + CAM_CONV_YUV_MODE + 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv mode of Data_in + 24 + 2 + read-write + + + CAM_CONV_PROTOCOL_MODE + 0:BT601. 1:BT709. + 26 + 1 + read-write + + + CAM_CONV_DATA_OUT_MODE + LIMIT or FULL mode of Data out. 0: limit. 1: full + 27 + 1 + read-write + + + CAM_CONV_DATA_IN_MODE + LIMIT or FULL mode of Data in. 0: limit. 1: full + 28 + 1 + read-write + + + CAM_CONV_MODE_8BITS_ON + 0: 16bits mode. 1: 8bits mode. + 29 + 1 + read-write + + + CAM_CONV_TRANS_MODE + 0: YUV to RGB. 1: RGB to YUV. + 30 + 1 + read-write + + + CAM_CONV_ENABLE + 0: Bypass converter. 1: Enable converter. + 31 + 1 + read-write + + + + + LCD_RGB_YUV + LCD YUV/RGB converter configuration register. + 0x10 + 0x20 + 0x00C00000 + + + LCD_CONV_8BITS_DATA_INV + 1:invert every two 8bits input data. 2. disabled. + 20 + 1 + read-write + + + LCD_CONV_TXTORX + 0: txtorx mode off. 1: txtorx mode on. + 21 + 1 + read-write + + + LCD_CONV_YUV2YUV_MODE + 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable yuv2yuv mode, trans_mode must be set to 1. + 22 + 2 + read-write + + + LCD_CONV_YUV_MODE + 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv mode of Data_in + 24 + 2 + read-write + + + LCD_CONV_PROTOCOL_MODE + 0:BT601. 1:BT709. + 26 + 1 + read-write + + + LCD_CONV_DATA_OUT_MODE + LIMIT or FULL mode of Data out. 0: limit. 1: full + 27 + 1 + read-write + + + LCD_CONV_DATA_IN_MODE + LIMIT or FULL mode of Data in. 0: limit. 1: full + 28 + 1 + read-write + + + LCD_CONV_MODE_8BITS_ON + 0: 16bits mode. 1: 8bits mode. + 29 + 1 + read-write + + + LCD_CONV_TRANS_MODE + 0: YUV to RGB. 1: RGB to YUV. + 30 + 1 + read-write + + + LCD_CONV_ENABLE + 0: Bypass converter. 1: Enable converter. + 31 + 1 + read-write + + + + + LCD_USER + LCD config register. + 0x14 + 0x20 + 0x00000001 + + + LCD_DOUT_CYCLELEN + The output data cycles minus 1 of LCD module. + 0 + 13 + read-write + + + LCD_ALWAYS_OUT_EN + LCD always output when LCD is in LCD_DOUT state, unless reg_lcd_start is cleared or reg_lcd_reset is set. + 13 + 1 + read-write + + + LCD_DOUT_BYTE_SWIZZLE_MODE + 0: ABAB->BABA. 1: ABC->ACB. 2: ABC->BAC. 3: ABC->BCA. 4:ABC->CAB. 5:ABC->CBA + 14 + 3 + read-write + + + LCD_DOUT_BYTE_SWIZZLE_ENABLE + 1: enable byte swizzle 0: disable + 17 + 1 + read-write + + + LCD_DOUT_BIT_ORDER + 1: change bit order in every byte. 0: Not change. + 18 + 1 + read-write + + + LCD_BYTE_MODE + 2: 24bit mode. 1: 16bit mode. 0: 8bit mode + 19 + 2 + read-write + + + LCD_UPDATE + 1: Update LCD registers, will be cleared by hardware. 0 : Not care. + 21 + 1 + read-write + + + LCD_BIT_ORDER + 1: Change data bit order, change LCD_DATA_out[7:0] to LCD_DATA_out[0:7] in one byte mode, and bits[15:0] to bits[0:15] in two byte mode. 0: Not change. + 22 + 1 + read-write + + + LCD_BYTE_ORDER + 1: invert data byte order, only valid in 2 byte mode. 0: Not change. + 23 + 1 + read-write + + + LCD_DOUT + 1: Be able to send data out in LCD sequence when LCD starts. 0: Disable. + 24 + 1 + read-write + + + LCD_DUMMY + 1: Enable DUMMY phase in LCD sequence when LCD starts. 0: Disable. + 25 + 1 + read-write + + + LCD_CMD + 1: Be able to send command in LCD sequence when LCD starts. 0: Disable. + 26 + 1 + read-write + + + LCD_START + LCD start sending data enable signal, valid in high level. + 27 + 1 + read-write + + + LCD_RESET + The value of command. + 28 + 1 + write-only + + + LCD_DUMMY_CYCLELEN + The dummy cycle length minus 1. + 29 + 2 + read-write + + + LCD_CMD_2_CYCLE_EN + The cycle length of command phase. 1: 2 cycles. 0: 1 cycle. + 31 + 1 + read-write + + + + + LCD_MISC + LCD config register. + 0x18 + 0x20 + 0x000000C0 + + + LCD_WIRE_MODE + The wire width of LCD output. 0: 8bit. 1: 16bit 2: 24bit + 4 + 2 + read-write + + + LCD_VFK_CYCLELEN + The setup cycle length minus 1 in LCD non-RGB mode. + 6 + 6 + read-write + + + LCD_VBK_CYCLELEN + The vertical back blank region cycle length minus 1 in LCD RGB mode, or the hold time cycle length in LCD non-RGB mode. + 12 + 13 + read-write + + + LCD_NEXT_FRAME_EN + 1: Send the next frame data when the current frame is sent out. 0: LCD stops when the current frame is sent out. + 25 + 1 + read-write + + + LCD_BK_EN + 1: Enable blank region when LCD sends data out. 0: No blank region. + 26 + 1 + read-write + + + LCD_AFIFO_RESET + LCD AFIFO reset signal. + 27 + 1 + write-only + + + LCD_CD_DATA_SET + 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DOUT state. 0: LCD_CD = reg_cd_idle_edge. + 28 + 1 + read-write + + + LCD_CD_DUMMY_SET + 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DUMMY state. 0: LCD_CD = reg_cd_idle_edge. + 29 + 1 + read-write + + + LCD_CD_CMD_SET + 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_CMD state. 0: LCD_CD = reg_cd_idle_edge. + 30 + 1 + read-write + + + LCD_CD_IDLE_EDGE + The default value of LCD_CD. + 31 + 1 + read-write + + + + + LCD_CTRL + LCD config register. + 0x1C + 0x20 + + + LCD_HB_FRONT + It is the horizontal blank front porch of a frame. + 0 + 11 + read-write + + + LCD_VA_HEIGHT + It is the vertical active height of a frame. + 11 + 10 + read-write + + + LCD_VT_HEIGHT + It is the vertical total height of a frame. + 21 + 10 + read-write + + + LCD_RGB_MODE_EN + 1: Enable LCD RGB mode. 0: Disable LCD RGB mode. + 31 + 1 + read-write + + + + + LCD_CTRL1 + LCD config register. + 0x20 + 0x20 + + + LCD_VB_FRONT + It is the vertical blank front porch of a frame. + 0 + 8 + read-write + + + LCD_HA_WIDTH + It is the horizontal active width of a frame. + 8 + 12 + read-write + + + LCD_HT_WIDTH + It is the horizontal total width of a frame. + 20 + 12 + read-write + + + + + LCD_CTRL2 + LCD config register. + 0x24 + 0x20 + 0x00010001 + + + LCD_VSYNC_WIDTH + It is the position of LCD_VSYNC active pulse in a line. + 0 + 7 + read-write + + + LCD_VSYNC_IDLE_POL + It is the idle value of LCD_VSYNC. + 7 + 1 + read-write + + + LCD_DE_IDLE_POL + It is the idle value of LCD_DE. + 8 + 1 + read-write + + + LCD_HS_BLANK_EN + 1: The pulse of LCD_HSYNC is out in vertical blanking lines RGB mode. 0: LCD_HSYNC pulse is valid only in active region lines in RGB mode. + 9 + 1 + read-write + + + LCD_HSYNC_WIDTH + It is the position of LCD_HSYNC active pulse in a line. + 16 + 7 + read-write + + + LCD_HSYNC_IDLE_POL + It is the idle value of LCD_HSYNC. + 23 + 1 + read-write + + + LCD_HSYNC_POSITION + It is the position of LCD_HSYNC active pulse in a line. + 24 + 8 + read-write + + + + + LCD_FIRST_CMD_VAL + LCD config register. + 0x28 + 0x20 + + + LCD_FIRST_CMD_VALUE + The LCD write command value of first cmd cycle. + 0 + 32 + read-write + + + + + LCD_LATTER_CMD_VAL + LCD config register. + 0x2C + 0x20 + + + LCD_LATTER_CMD_VALUE + The LCD write command value of latter cmd cycle. + 0 + 32 + read-write + + + + + LCD_DLY_MODE_CFG1 + LCD config register. + 0x30 + 0x20 + + + DOUT16_MODE + The output data bit 0 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 0 + 2 + read-write + + + DOUT17_MODE + The output data bit 2 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 2 + 2 + read-write + + + DOUT18_MODE + The output data bit 4 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 4 + 2 + read-write + + + DOUT19_MODE + The output data bit 6 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 6 + 2 + read-write + + + DOUT20_MODE + The output data bit 8 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 8 + 2 + read-write + + + DOUT21_MODE + The output data bit 10 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 10 + 2 + read-write + + + DOUT22_MODE + The output data bit 12 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 12 + 2 + read-write + + + DOUT23_MODE + The output data bit 14 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 14 + 2 + read-write + + + LCD_CD_MODE + The output LCD_CD is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 16 + 2 + read-write + + + LCD_DE_MODE + The output LCD_DE is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 18 + 2 + read-write + + + LCD_HSYNC_MODE + The output LCD_HSYNC is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 20 + 2 + read-write + + + LCD_VSYNC_MODE + The output LCD_VSYNC is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 22 + 2 + read-write + + + + + LCD_DLY_MODE_CFG2 + LCD config register. + 0x38 + 0x20 + + + DOUT0_MODE + The output data bit 0 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 0 + 2 + read-write + + + DOUT1_MODE + The output data bit 2 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 2 + 2 + read-write + + + DOUT2_MODE + The output data bit 4 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 4 + 2 + read-write + + + DOUT3_MODE + The output data bit 6 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 6 + 2 + read-write + + + DOUT4_MODE + The output data bit 8 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 8 + 2 + read-write + + + DOUT5_MODE + The output data bit 10 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 10 + 2 + read-write + + + DOUT6_MODE + The output data bit 12 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 12 + 2 + read-write + + + DOUT7_MODE + The output data bit 14 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 14 + 2 + read-write + + + DOUT8_MODE + The output data bit 16 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 16 + 2 + read-write + + + DOUT9_MODE + The output data bit 18 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 18 + 2 + read-write + + + DOUT10_MODE + The output data bit 20 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 20 + 2 + read-write + + + DOUT11_MODE + The output data bit 22 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 22 + 2 + read-write + + + DOUT12_MODE + The output data bit 24 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 24 + 2 + read-write + + + DOUT13_MODE + The output data bit 26 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 26 + 2 + read-write + + + DOUT14_MODE + The output data bit 28 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 28 + 2 + read-write + + + DOUT15_MODE + The output data bit 30 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 30 + 2 + read-write + + + + + LC_DMA_INT_ENA + LCDCAM interrupt enable register. + 0x64 + 0x20 + + + LCD_VSYNC_INT_ENA + The enable bit for LCD frame end interrupt. + 0 + 1 + read-write + + + LCD_TRANS_DONE_INT_ENA + The enable bit for lcd transfer end interrupt. + 1 + 1 + read-write + + + CAM_VSYNC_INT_ENA + The enable bit for Camera frame end interrupt. + 2 + 1 + read-write + + + CAM_HS_INT_ENA + The enable bit for Camera line interrupt. + 3 + 1 + read-write + + + + + LC_DMA_INT_RAW + LCDCAM interrupt raw register, valid in level. + 0x68 + 0x20 + + + LCD_VSYNC_INT_RAW + The raw bit for LCD frame end interrupt. + 0 + 1 + read-only + + + LCD_TRANS_DONE_INT_RAW + The raw bit for lcd transfer end interrupt. + 1 + 1 + read-only + + + CAM_VSYNC_INT_RAW + The raw bit for Camera frame end interrupt. + 2 + 1 + read-only + + + CAM_HS_INT_RAW + The raw bit for Camera line interrupt. + 3 + 1 + read-only + + + + + LC_DMA_INT_ST + LCDCAM interrupt status register. + 0x6C + 0x20 + + + LCD_VSYNC_INT_ST + The status bit for LCD frame end interrupt. + 0 + 1 + read-only + + + LCD_TRANS_DONE_INT_ST + The status bit for lcd transfer end interrupt. + 1 + 1 + read-only + + + CAM_VSYNC_INT_ST + The status bit for Camera frame end interrupt. + 2 + 1 + read-only + + + CAM_HS_INT_ST + The status bit for Camera transfer end interrupt. + 3 + 1 + read-only + + + + + LC_DMA_INT_CLR + LCDCAM interrupt clear register. + 0x70 + 0x20 + + + LCD_VSYNC_INT_CLR + The clear bit for LCD frame end interrupt. + 0 + 1 + write-only + + + LCD_TRANS_DONE_INT_CLR + The clear bit for lcd transfer end interrupt. + 1 + 1 + write-only + + + CAM_VSYNC_INT_CLR + The clear bit for Camera frame end interrupt. + 2 + 1 + write-only + + + CAM_HS_INT_CLR + The clear bit for Camera line interrupt. + 3 + 1 + write-only + + + + + LC_REG_DATE + Version register + 0xFC + 0x20 + 0x02303090 + + + LC_DATE + LCD_CAM version control register + 0 + 28 + read-write + + + + + + + LEDC + LED Control PWM (Pulse Width Modulation) + LEDC + 0x500D3000 + + 0x0 + 0x124 + registers + + + LEDC + 52 + + + + 8 + 0x14 + CH%s_CONF0 + Configuration register 0 for channel %s + 0x0 + 0x20 + + + TIMER_SEL_CH + Configures which timer is channel %s selected.\\0: Select timer0\\1: Select timer1\\2: Select timer2\\3: Select timer3 + 0 + 2 + read-write + + + SIG_OUT_EN_CH + Configures whether or not to enable signal output on channel %s.\\0: Signal output disable\\1: Signal output enable + 2 + 1 + read-write + + + IDLE_LV_CH + Configures the output value when channel %s is inactive. Valid only when LEDC_SIG_OUT_EN_CH%s is 0.\\0: Output level is low\\1: Output level is high + 3 + 1 + read-write + + + PARA_UP_CH + Configures whether or not to update LEDC_HPOINT_CH%s, LEDC_DUTY_START_CH%s, LEDC_SIG_OUT_EN_CH%s, LEDC_TIMER_SEL_CH%s, LEDC_DUTY_NUM_CH%s, LEDC_DUTY_CYCLE_CH%s, LEDC_DUTY_SCALE_CH%s, LEDC_DUTY_INC_CH%s, and LEDC_OVF_CNT_EN_CH%s fields for channel %s, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update + 4 + 1 + write-only + + + OVF_NUM_CH + Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH%s_INT interrupt will be triggered when channel %s overflows for (LEDC_OVF_NUM_CH%s + 1) times. + 5 + 10 + read-write + + + OVF_CNT_EN_CH + Configures whether or not to enable the ovf_cnt of channel %s.\\0: Disable\\1: Enable + 15 + 1 + read-write + + + OVF_CNT_RESET_CH + Configures whether or not to reset the ovf_cnt of channel %s.\\0: Invalid. No effect\\1: Reset the ovf_cnt + 16 + 1 + write-only + + + + + 8 + 0x14 + CH%s_HPOINT + High point register for channel %s + 0x4 + 0x20 + + + HPOINT_CH + Configures high point of signal output on channel %s. The output value changes to high when the selected timers has reached the value specified by this register. + 0 + 20 + read-write + + + + + 8 + 0x14 + CH%s_DUTY + Initial duty cycle register for channel %s + 0x8 + 0x20 + + + DUTY_CH + Configures the duty of signal output on channel %s. + 0 + 25 + read-write + + + + + 8 + 0x14 + CH%s_CONF1 + Configuration register 1 for channel %s + 0xC + 0x20 + + + DUTY_START_CH + Configures whether the duty cycle fading configurations take effect.\\0: Not take effect\\1: Take effect + 31 + 1 + read-write + + + + + 8 + 0x14 + CH%s_DUTY_R + Current duty cycle register for channel %s + 0x10 + 0x20 + + + DUTY_CH_R + Represents the current duty of output signal on channel %s. + 0 + 25 + read-only + + + + + 4 + 0x8 + TIMER%s_CONF + Timer %s configuration register + 0xA0 + 0x20 + 0x01000000 + + + TIMER_DUTY_RES + Configures the range of the counter in timer %s. + 0 + 5 + read-write + + + CLK_DIV_TIMER + Configures the divisor for the divider in timer %s.The least significant eight bits represent the fractional part. + 5 + 18 + read-write + + + TIMER_PAUSE + Configures whether or not to pause the counter in timer %s.\\0: Normal\\1: Pause + 23 + 1 + read-write + + + TIMER_RST + Configures whether or not to reset timer %s. The counter will show 0 after reset.\\0: Not reset\\1: Reset + 24 + 1 + read-write + + + TICK_SEL_TIMER + Configures which clock is timer %s selected. Unused. + 25 + 1 + read-write + + + TIMER_PARA_UP + Configures whether or not to update LEDC_CLK_DIV_TIMER%s and LEDC_TIMER%s_DUTY_RES.\\0: Invalid. No effect\\1: Update + 26 + 1 + write-only + + + + + 4 + 0x8 + TIMER%s_VALUE + Timer %s current counter value register + 0xA4 + 0x20 + + + TIMER_CNT + Represents the current counter value of timer %s. + 0 + 20 + read-only + + + + + INT_RAW + Interrupt raw status register + 0xC0 + 0x20 + + + TIMER0_OVF_INT_RAW + Raw status bit: The raw interrupt status of LEDC_TIMER0_OVF_INT. Triggered when the timer0 has reached its maximum counter value. + 0 + 1 + read-write + + + TIMER1_OVF_INT_RAW + Raw status bit: The raw interrupt status of LEDC_TIMER1_OVF_INT. Triggered when the timer1 has reached its maximum counter value. + 1 + 1 + read-write + + + TIMER2_OVF_INT_RAW + Raw status bit: The raw interrupt status of LEDC_TIMER2_OVF_INT. Triggered when the timer2 has reached its maximum counter value. + 2 + 1 + read-write + + + TIMER3_OVF_INT_RAW + Raw status bit: The raw interrupt status of LEDC_TIMER3_OVF_INT. Triggered when the timer3 has reached its maximum counter value. + 3 + 1 + read-write + + + DUTY_CHNG_END_CH0_INT_RAW + Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. Triggered when the fading of duty has finished. + 4 + 1 + read-write + + + DUTY_CHNG_END_CH1_INT_RAW + Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. Triggered when the fading of duty has finished. + 5 + 1 + read-write + + + DUTY_CHNG_END_CH2_INT_RAW + Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. Triggered when the fading of duty has finished. + 6 + 1 + read-write + + + DUTY_CHNG_END_CH3_INT_RAW + Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. Triggered when the fading of duty has finished. + 7 + 1 + read-write + + + DUTY_CHNG_END_CH4_INT_RAW + Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. Triggered when the fading of duty has finished. + 8 + 1 + read-write + + + DUTY_CHNG_END_CH5_INT_RAW + Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. Triggered when the fading of duty has finished. + 9 + 1 + read-write + + + DUTY_CHNG_END_CH6_INT_RAW + Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH6_INT. Triggered when the fading of duty has finished. + 10 + 1 + read-write + + + DUTY_CHNG_END_CH7_INT_RAW + Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH7_INT. Triggered when the fading of duty has finished. + 11 + 1 + read-write + + + OVF_CNT_CH0_INT_RAW + Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH0_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH0. + 12 + 1 + read-write + + + OVF_CNT_CH1_INT_RAW + Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH1_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH1. + 13 + 1 + read-write + + + OVF_CNT_CH2_INT_RAW + Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH2_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH2. + 14 + 1 + read-write + + + OVF_CNT_CH3_INT_RAW + Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH3_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH3. + 15 + 1 + read-write + + + OVF_CNT_CH4_INT_RAW + Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH4_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH4. + 16 + 1 + read-write + + + OVF_CNT_CH5_INT_RAW + Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH5_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH5. + 17 + 1 + read-write + + + OVF_CNT_CH6_INT_RAW + Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH6_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH6. + 18 + 1 + read-write + + + OVF_CNT_CH7_INT_RAW + Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH7_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH7. + 19 + 1 + read-write + + + + + INT_ST + Interrupt masked status register + 0xC4 + 0x20 + + + TIMER0_OVF_INT_ST + Masked status bit: The masked interrupt status of LEDC_TIMER0_OVF_INT. Valid only when LEDC_TIMER0_OVF_INT_ENA is set to 1. + 0 + 1 + read-only + + + TIMER1_OVF_INT_ST + Masked status bit: The masked interrupt status of LEDC_TIMER1_OVF_INT. Valid only when LEDC_TIMER1_OVF_INT_ENA is set to 1. + 1 + 1 + read-only + + + TIMER2_OVF_INT_ST + Masked status bit: The masked interrupt status of LEDC_TIMER2_OVF_INT. Valid only when LEDC_TIMER2_OVF_INT_ENA is set to 1. + 2 + 1 + read-only + + + TIMER3_OVF_INT_ST + Masked status bit: The masked interrupt status of LEDC_TIMER3_OVF_INT. Valid only when LEDC_TIMER3_OVF_INT_ENA is set to 1. + 3 + 1 + read-only + + + DUTY_CHNG_END_CH0_INT_ST + Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. Valid only when LEDC_DUTY_CHNG_END_CH0_INT_ENA is set to 1. + 4 + 1 + read-only + + + DUTY_CHNG_END_CH1_INT_ST + Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. Valid only when LEDC_DUTY_CHNG_END_CH1_INT_ENA is set to 1. + 5 + 1 + read-only + + + DUTY_CHNG_END_CH2_INT_ST + Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. Valid only when LEDC_DUTY_CHNG_END_CH2_INT_ENA is set to 1. + 6 + 1 + read-only + + + DUTY_CHNG_END_CH3_INT_ST + Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. Valid only when LEDC_DUTY_CHNG_END_CH3_INT_ENA is set to 1. + 7 + 1 + read-only + + + DUTY_CHNG_END_CH4_INT_ST + Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. Valid only when LEDC_DUTY_CHNG_END_CH4_INT_ENA is set to 1. + 8 + 1 + read-only + + + DUTY_CHNG_END_CH5_INT_ST + Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. Valid only when LEDC_DUTY_CHNG_END_CH5_INT_ENA is set to 1. + 9 + 1 + read-only + + + DUTY_CHNG_END_CH6_INT_ST + Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH6_INT. Valid only when LEDC_DUTY_CHNG_END_CH6_INT_ENA is set to 1. + 10 + 1 + read-only + + + DUTY_CHNG_END_CH7_INT_ST + Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH7_INT. Valid only when LEDC_DUTY_CHNG_END_CH7_INT_ENA is set to 1. + 11 + 1 + read-only + + + OVF_CNT_CH0_INT_ST + Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH0_INT. Valid only when LEDC_OVF_CNT_CH0_INT_ENA is set to 1. + 12 + 1 + read-only + + + OVF_CNT_CH1_INT_ST + Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH1_INT. Valid only when LEDC_OVF_CNT_CH1_INT_ENA is set to 1. + 13 + 1 + read-only + + + OVF_CNT_CH2_INT_ST + Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH2_INT. Valid only when LEDC_OVF_CNT_CH2_INT_ENA is set to 1. + 14 + 1 + read-only + + + OVF_CNT_CH3_INT_ST + Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH3_INT. Valid only when LEDC_OVF_CNT_CH3_INT_ENA is set to 1. + 15 + 1 + read-only + + + OVF_CNT_CH4_INT_ST + Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH4_INT. Valid only when LEDC_OVF_CNT_CH4_INT_ENA is set to 1. + 16 + 1 + read-only + + + OVF_CNT_CH5_INT_ST + Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH5_INT. Valid only when LEDC_OVF_CNT_CH5_INT_ENA is set to 1. + 17 + 1 + read-only + + + OVF_CNT_CH6_INT_ST + Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH6_INT. Valid only when LEDC_OVF_CNT_CH6_INT_ENA is set to 1. + 18 + 1 + read-only + + + OVF_CNT_CH7_INT_ST + Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH7_INT. Valid only when LEDC_OVF_CNT_CH7_INT_ENA is set to 1. + 19 + 1 + read-only + + + + + INT_ENA + Interrupt enable register + 0xC8 + 0x20 + + + TIMER0_OVF_INT_ENA + Enable bit: Write 1 to enable LEDC_TIMER0_OVF_INT. + 0 + 1 + read-write + + + TIMER1_OVF_INT_ENA + Enable bit: Write 1 to enable LEDC_TIMER1_OVF_INT. + 1 + 1 + read-write + + + TIMER2_OVF_INT_ENA + Enable bit: Write 1 to enable LEDC_TIMER2_OVF_INT. + 2 + 1 + read-write + + + TIMER3_OVF_INT_ENA + Enable bit: Write 1 to enable LEDC_TIMER3_OVF_INT. + 3 + 1 + read-write + + + DUTY_CHNG_END_CH0_INT_ENA + Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH0_INT. + 4 + 1 + read-write + + + DUTY_CHNG_END_CH1_INT_ENA + Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH1_INT. + 5 + 1 + read-write + + + DUTY_CHNG_END_CH2_INT_ENA + Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH2_INT. + 6 + 1 + read-write + + + DUTY_CHNG_END_CH3_INT_ENA + Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH3_INT. + 7 + 1 + read-write + + + DUTY_CHNG_END_CH4_INT_ENA + Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH4_INT. + 8 + 1 + read-write + + + DUTY_CHNG_END_CH5_INT_ENA + Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH5_INT. + 9 + 1 + read-write + + + DUTY_CHNG_END_CH6_INT_ENA + Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH6_INT. + 10 + 1 + read-write + + + DUTY_CHNG_END_CH7_INT_ENA + Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH7_INT. + 11 + 1 + read-write + + + OVF_CNT_CH0_INT_ENA + Enable bit: Write 1 to enable LEDC_OVF_CNT_CH0_INT. + 12 + 1 + read-write + + + OVF_CNT_CH1_INT_ENA + Enable bit: Write 1 to enable LEDC_OVF_CNT_CH1_INT. + 13 + 1 + read-write + + + OVF_CNT_CH2_INT_ENA + Enable bit: Write 1 to enable LEDC_OVF_CNT_CH2_INT. + 14 + 1 + read-write + + + OVF_CNT_CH3_INT_ENA + Enable bit: Write 1 to enable LEDC_OVF_CNT_CH3_INT. + 15 + 1 + read-write + + + OVF_CNT_CH4_INT_ENA + Enable bit: Write 1 to enable LEDC_OVF_CNT_CH4_INT. + 16 + 1 + read-write + + + OVF_CNT_CH5_INT_ENA + Enable bit: Write 1 to enable LEDC_OVF_CNT_CH5_INT. + 17 + 1 + read-write + + + OVF_CNT_CH6_INT_ENA + Enable bit: Write 1 to enable LEDC_OVF_CNT_CH6_INT. + 18 + 1 + read-write + + + OVF_CNT_CH7_INT_ENA + Enable bit: Write 1 to enable LEDC_OVF_CNT_CH7_INT. + 19 + 1 + read-write + + + + + INT_CLR + Interrupt clear register + 0xCC + 0x20 + + + TIMER0_OVF_INT_CLR + Clear bit: Write 1 to clear LEDC_TIMER0_OVF_INT. + 0 + 1 + write-only + + + TIMER1_OVF_INT_CLR + Clear bit: Write 1 to clear LEDC_TIMER1_OVF_INT. + 1 + 1 + write-only + + + TIMER2_OVF_INT_CLR + Clear bit: Write 1 to clear LEDC_TIMER2_OVF_INT. + 2 + 1 + write-only + + + TIMER3_OVF_INT_CLR + Clear bit: Write 1 to clear LEDC_TIMER3_OVF_INT. + 3 + 1 + write-only + + + DUTY_CHNG_END_CH0_INT_CLR + Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH0_INT. + 4 + 1 + write-only + + + DUTY_CHNG_END_CH1_INT_CLR + Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH1_INT. + 5 + 1 + write-only + + + DUTY_CHNG_END_CH2_INT_CLR + Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH2_INT. + 6 + 1 + write-only + + + DUTY_CHNG_END_CH3_INT_CLR + Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH3_INT. + 7 + 1 + write-only + + + DUTY_CHNG_END_CH4_INT_CLR + Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH4_INT. + 8 + 1 + write-only + + + DUTY_CHNG_END_CH5_INT_CLR + Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH5_INT. + 9 + 1 + write-only + + + DUTY_CHNG_END_CH6_INT_CLR + Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH6_INT. + 10 + 1 + write-only + + + DUTY_CHNG_END_CH7_INT_CLR + Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH7_INT. + 11 + 1 + write-only + + + OVF_CNT_CH0_INT_CLR + Clear bit: Write 1 to clear LEDC_OVF_CNT_CH0_INT. + 12 + 1 + write-only + + + OVF_CNT_CH1_INT_CLR + Clear bit: Write 1 to clear LEDC_OVF_CNT_CH1_INT. + 13 + 1 + write-only + + + OVF_CNT_CH2_INT_CLR + Clear bit: Write 1 to clear LEDC_OVF_CNT_CH2_INT. + 14 + 1 + write-only + + + OVF_CNT_CH3_INT_CLR + Clear bit: Write 1 to clear LEDC_OVF_CNT_CH3_INT. + 15 + 1 + write-only + + + OVF_CNT_CH4_INT_CLR + Clear bit: Write 1 to clear LEDC_OVF_CNT_CH4_INT. + 16 + 1 + write-only + + + OVF_CNT_CH5_INT_CLR + Clear bit: Write 1 to clear LEDC_OVF_CNT_CH5_INT. + 17 + 1 + write-only + + + OVF_CNT_CH6_INT_CLR + Clear bit: Write 1 to clear LEDC_OVF_CNT_CH6_INT. + 18 + 1 + write-only + + + OVF_CNT_CH7_INT_CLR + Clear bit: Write 1 to clear LEDC_OVF_CNT_CH7_INT. + 19 + 1 + write-only + + + + + 8 + 0x4 + CH%s_GAMMA_CONF + Ledc ch%s gamma config register. + 0x100 + 0x20 + + + CH_GAMMA_ENTRY_NUM + Configures the number of duty cycle fading rages for LEDC ch%s. + 0 + 5 + read-write + + + CH_GAMMA_PAUSE + Configures whether or not to pause duty cycle fading of LEDC ch%s.\\0: Invalid. No effect\\1: Pause + 5 + 1 + write-only + + + CH_GAMMA_RESUME + Configures whether or nor to resume duty cycle fading of LEDC ch%s.\\0: Invalid. No effect\\1: Resume + 6 + 1 + write-only + + + + + EVT_TASK_EN0 + Ledc event task enable bit register0. + 0x120 + 0x20 + + + EVT_DUTY_CHNG_END_CH0_EN + Configures whether or not to enable the ledc_ch0_duty_chng_end event.\\0: Disable\\1: Enable + 0 + 1 + read-write + + + EVT_DUTY_CHNG_END_CH1_EN + Configures whether or not to enable the ledc_ch1_duty_chng_end event.\\0: Disable\\1: Enable + 1 + 1 + read-write + + + EVT_DUTY_CHNG_END_CH2_EN + Configures whether or not to enable the ledc_ch2_duty_chng_end event.\\0: Disable\\1: Enable + 2 + 1 + read-write + + + EVT_DUTY_CHNG_END_CH3_EN + Configures whether or not to enable the ledc_ch3_duty_chng_end event.\\0: Disable\\1: Enable + 3 + 1 + read-write + + + EVT_DUTY_CHNG_END_CH4_EN + Configures whether or not to enable the ledc_ch4_duty_chng_end event.\\0: Disable\\1: Enable + 4 + 1 + read-write + + + EVT_DUTY_CHNG_END_CH5_EN + Configures whether or not to enable the ledc_ch5_duty_chng_end event.\\0: Disable\\1: Enable + 5 + 1 + read-write + + + EVT_DUTY_CHNG_END_CH6_EN + Configures whether or not to enable the ledc_ch6_duty_chng_end event.\\0: Disable\\1: Enable + 6 + 1 + read-write + + + EVT_DUTY_CHNG_END_CH7_EN + Configures whether or not to enable the ledc_ch7_duty_chng_end event.\\0: Disable\\1: Enable + 7 + 1 + read-write + + + EVT_OVF_CNT_PLS_CH0_EN + Configures whether or not to enable the ledc_ch0_ovf_cnt_pls event.\\0: Disable\\1: Enable + 8 + 1 + read-write + + + EVT_OVF_CNT_PLS_CH1_EN + Configures whether or not to enable the ledc_ch1_ovf_cnt_pls event.\\0: Disable\\1: Enable + 9 + 1 + read-write + + + EVT_OVF_CNT_PLS_CH2_EN + Configures whether or not to enable the ledc_ch2_ovf_cnt_pls event.\\0: Disable\\1: Enable + 10 + 1 + read-write + + + EVT_OVF_CNT_PLS_CH3_EN + Configures whether or not to enable the ledc_ch3_ovf_cnt_pls event.\\0: Disable\\1: Enable + 11 + 1 + read-write + + + EVT_OVF_CNT_PLS_CH4_EN + Configures whether or not to enable the ledc_ch4_ovf_cnt_pls event.\\0: Disable\\1: Enable + 12 + 1 + read-write + + + EVT_OVF_CNT_PLS_CH5_EN + Configures whether or not to enable the ledc_ch5_ovf_cnt_pls event.\\0: Disable\\1: Enable + 13 + 1 + read-write + + + EVT_OVF_CNT_PLS_CH6_EN + Configures whether or not to enable the ledc_ch6_ovf_cnt_pls event.\\0: Disable\\1: Enable + 14 + 1 + read-write + + + EVT_OVF_CNT_PLS_CH7_EN + Configures whether or not to enable the ledc_ch7_ovf_cnt_pls event.\\0: Disable\\1: Enable + 15 + 1 + read-write + + + EVT_TIME_OVF_TIMER0_EN + Configures whether or not to enable the ledc_timer0_ovf event.\\0: Disable\\1: Enable + 16 + 1 + read-write + + + EVT_TIME_OVF_TIMER1_EN + Configures whether or not to enable the ledc_timer1_ovf event.\\0: Disable\\1: Enable + 17 + 1 + read-write + + + EVT_TIME_OVF_TIMER2_EN + Configures whether or not to enable the ledc_timer2_ovf event.\\0: Disable\\1: Enable + 18 + 1 + read-write + + + EVT_TIME_OVF_TIMER3_EN + Configures whether or not to enable the ledc_timer3_ovf event.\\0: Disable\\1: Enable + 19 + 1 + read-write + + + EVT_TIME0_CMP_EN + Configures whether or not to enable the ledc_timer0_cmp event.\\0: Disable\\1: Enable + 20 + 1 + read-write + + + EVT_TIME1_CMP_EN + Configures whether or not to enable the ledc_timer1_cmp event.\\0: Disable\\1: Enable + 21 + 1 + read-write + + + EVT_TIME2_CMP_EN + Configures whether or not to enable the ledc_timer2_cmp event.\\0: Disable\\1: Enable + 22 + 1 + read-write + + + EVT_TIME3_CMP_EN + Configures whether or not to enable the ledc_timer3_cmp event.\\0: Disable\\1: Enable + 23 + 1 + read-write + + + TASK_DUTY_SCALE_UPDATE_CH0_EN + Configures whether or not to enable the ledc_ch0_duty_scale_update task.\\0: Disable\\1: Enable + 24 + 1 + read-write + + + TASK_DUTY_SCALE_UPDATE_CH1_EN + Configures whether or not to enable the ledc_ch1_duty_scale_update task.\\0: Disable\\1: Enable + 25 + 1 + read-write + + + TASK_DUTY_SCALE_UPDATE_CH2_EN + Configures whether or not to enable the ledc_ch2_duty_scale_update task.\\0: Disable\\1: Enable + 26 + 1 + read-write + + + TASK_DUTY_SCALE_UPDATE_CH3_EN + Configures whether or not to enable the ledc_ch3_duty_scale_update task.\\0: Disable\\1: Enable + 27 + 1 + read-write + + + TASK_DUTY_SCALE_UPDATE_CH4_EN + Configures whether or not to enable the ledc_ch4_duty_scale_update task.\\0: Disable\\1: Enable + 28 + 1 + read-write + + + TASK_DUTY_SCALE_UPDATE_CH5_EN + Configures whether or not to enable the ledc_ch5_duty_scale_update task.\\0: Disable\\1: Enable + 29 + 1 + read-write + + + TASK_DUTY_SCALE_UPDATE_CH6_EN + Configures whether or not to enable the ledc_ch6_duty_scale_update task.\\0: Disable\\1: Enable + 30 + 1 + read-write + + + TASK_DUTY_SCALE_UPDATE_CH7_EN + Configures whether or not to enable the ledc_ch7_duty_scale_update task.\\0: Disable\\1: Enable + 31 + 1 + read-write + + + + + EVT_TASK_EN1 + Ledc event task enable bit register1. + 0x124 + 0x20 + + + TASK_TIMER0_RES_UPDATE_EN + Configures whether or not to enable ledc_timer0_res_update task.\\0: Disable\\1: Enable + 0 + 1 + read-write + + + TASK_TIMER1_RES_UPDATE_EN + Configures whether or not to enable ledc_timer1_res_update task.\\0: Disable\\1: Enable + 1 + 1 + read-write + + + TASK_TIMER2_RES_UPDATE_EN + Configures whether or not to enable ledc_timer2_res_update task.\\0: Disable\\1: Enable + 2 + 1 + read-write + + + TASK_TIMER3_RES_UPDATE_EN + Configures whether or not to enable ledc_timer3_res_update task.\\0: Disable\\1: Enable + 3 + 1 + read-write + + + TASK_TIMER0_CAP_EN + Configures whether or not to enable ledc_timer0_cap task.\\0: Disable\\1: Enable + 4 + 1 + read-write + + + TASK_TIMER1_CAP_EN + Configures whether or not to enable ledc_timer1_cap task.\\0: Disable\\1: Enable + 5 + 1 + read-write + + + TASK_TIMER2_CAP_EN + Configures whether or not to enable ledc_timer2_cap task.\\0: Disable\\1: Enable + 6 + 1 + read-write + + + TASK_TIMER3_CAP_EN + Configures whether or not to enable ledc_timer3_cap task.\\0: Disable\\1: Enable + 7 + 1 + read-write + + + TASK_SIG_OUT_DIS_CH0_EN + Configures whether or not to enable ledc_ch0_sig_out_dis task.\\0: Disable\\1: Enable + 8 + 1 + read-write + + + TASK_SIG_OUT_DIS_CH1_EN + Configures whether or not to enable ledc_ch1_sig_out_dis task.\\0: Disable\\1: Enable + 9 + 1 + read-write + + + TASK_SIG_OUT_DIS_CH2_EN + Configures whether or not to enable ledc_ch2_sig_out_dis task.\\0: Disable\\1: Enable + 10 + 1 + read-write + + + TASK_SIG_OUT_DIS_CH3_EN + Configures whether or not to enable ledc_ch3_sig_out_dis task.\\0: Disable\\1: Enable + 11 + 1 + read-write + + + TASK_SIG_OUT_DIS_CH4_EN + Configures whether or not to enable ledc_ch4_sig_out_dis task.\\0: Disable\\1: Enable + 12 + 1 + read-write + + + TASK_SIG_OUT_DIS_CH5_EN + Configures whether or not to enable ledc_ch5_sig_out_dis task.\\0: Disable\\1: Enable + 13 + 1 + read-write + + + TASK_SIG_OUT_DIS_CH6_EN + Configures whether or not to enable ledc_ch6_sig_out_dis task.\\0: Disable\\1: Enable + 14 + 1 + read-write + + + TASK_SIG_OUT_DIS_CH7_EN + Configures whether or not to enable ledc_ch7_sig_out_dis task.\\0: Disable\\1: Enable + 15 + 1 + read-write + + + TASK_OVF_CNT_RST_CH0_EN + Configures whether or not to enable ledc_ch0_ovf_cnt_rst task.\\0: Disable\\1: Enable + 16 + 1 + read-write + + + TASK_OVF_CNT_RST_CH1_EN + Configures whether or not to enable ledc_ch1_ovf_cnt_rst task.\\0: Disable\\1: Enable + 17 + 1 + read-write + + + TASK_OVF_CNT_RST_CH2_EN + Configures whether or not to enable ledc_ch2_ovf_cnt_rst task.\\0: Disable\\1: Enable + 18 + 1 + read-write + + + TASK_OVF_CNT_RST_CH3_EN + Configures whether or not to enable ledc_ch3_ovf_cnt_rst task.\\0: Disable\\1: Enable + 19 + 1 + read-write + + + TASK_OVF_CNT_RST_CH4_EN + Configures whether or not to enable ledc_ch4_ovf_cnt_rst task.\\0: Disable\\1: Enable + 20 + 1 + read-write + + + TASK_OVF_CNT_RST_CH5_EN + Configures whether or not to enable ledc_ch5_ovf_cnt_rst task.\\0: Disable\\1: Enable + 21 + 1 + read-write + + + TASK_OVF_CNT_RST_CH6_EN + Configures whether or not to enable ledc_ch6_ovf_cnt_rst task.\\0: Disable\\1: Enable + 22 + 1 + read-write + + + TASK_OVF_CNT_RST_CH7_EN + Configures whether or not to enable ledc_ch7_ovf_cnt_rst task.\\0: Disable\\1: Enable + 23 + 1 + read-write + + + TASK_TIMER0_RST_EN + Configures whether or not to enable ledc_timer0_rst task.\\0: Disable\\1: Enable + 24 + 1 + read-write + + + TASK_TIMER1_RST_EN + Configures whether or not to enable ledc_timer1_rst task.\\0: Disable\\1: Enable + 25 + 1 + read-write + + + TASK_TIMER2_RST_EN + Configures whether or not to enable ledc_timer2_rst task.\\0: Disable\\1: Enable + 26 + 1 + read-write + + + TASK_TIMER3_RST_EN + Configures whether or not to enable ledc_timer3_rst task.\\0: Disable\\1: Enable + 27 + 1 + read-write + + + TASK_TIMER0_PAUSE_RESUME_EN + Configures whether or not to enable ledc_timer0_pause_resume task.\\0: Disable\\1: Enable + 28 + 1 + read-write + + + TASK_TIMER1_PAUSE_RESUME_EN + Configures whether or not to enable ledc_timer1_pause_resume task.\\0: Disable\\1: Enable + 29 + 1 + read-write + + + TASK_TIMER2_PAUSE_RESUME_EN + Configures whether or not to enable ledc_timer2_pause_resume task.\\0: Disable\\1: Enable + 30 + 1 + read-write + + + TASK_TIMER3_PAUSE_RESUME_EN + Configures whether or not to enable ledc_timer3_pause_resume task.\\0: Disable\\1: Enable + 31 + 1 + read-write + + + + + EVT_TASK_EN2 + Ledc event task enable bit register2. + 0x128 + 0x20 + + + TASK_GAMMA_RESTART_CH0_EN + Configures whether or not to enable ledc_ch0_gamma_restart task.\\0: Disable\\1: Enable + 0 + 1 + read-write + + + TASK_GAMMA_RESTART_CH1_EN + Configures whether or not to enable ledc_ch1_gamma_restart task.\\0: Disable\\1: Enable + 1 + 1 + read-write + + + TASK_GAMMA_RESTART_CH2_EN + Configures whether or not to enable ledc_ch2_gamma_restart task.\\0: Disable\\1: Enable + 2 + 1 + read-write + + + TASK_GAMMA_RESTART_CH3_EN + Configures whether or not to enable ledc_ch3_gamma_restart task.\\0: Disable\\1: Enable + 3 + 1 + read-write + + + TASK_GAMMA_RESTART_CH4_EN + Configures whether or not to enable ledc_ch4_gamma_restart task.\\0: Disable\\1: Enable + 4 + 1 + read-write + + + TASK_GAMMA_RESTART_CH5_EN + Configures whether or not to enable ledc_ch5_gamma_restart task.\\0: Disable\\1: Enable + 5 + 1 + read-write + + + TASK_GAMMA_RESTART_CH6_EN + Configures whether or not to enable ledc_ch6_gamma_restart task.\\0: Disable\\1: Enable + 6 + 1 + read-write + + + TASK_GAMMA_RESTART_CH7_EN + Configures whether or not to enable ledc_ch7_gamma_restart task.\\0: Disable\\1: Enable + 7 + 1 + read-write + + + TASK_GAMMA_PAUSE_CH0_EN + Configures whether or not to enable ledc_ch0_gamma_pause task.\\0: Disable\\1: Enable + 8 + 1 + read-write + + + TASK_GAMMA_PAUSE_CH1_EN + Configures whether or not to enable ledc_ch1_gamma_pause task.\\0: Disable\\1: Enable + 9 + 1 + read-write + + + TASK_GAMMA_PAUSE_CH2_EN + Configures whether or not to enable ledc_ch2_gamma_pause task.\\0: Disable\\1: Enable + 10 + 1 + read-write + + + TASK_GAMMA_PAUSE_CH3_EN + Configures whether or not to enable ledc_ch3_gamma_pause task.\\0: Disable\\1: Enable + 11 + 1 + read-write + + + TASK_GAMMA_PAUSE_CH4_EN + Configures whether or not to enable ledc_ch4_gamma_pause task.\\0: Disable\\1: Enable + 12 + 1 + read-write + + + TASK_GAMMA_PAUSE_CH5_EN + Configures whether or not to enable ledc_ch5_gamma_pause task.\\0: Disable\\1: Enable + 13 + 1 + read-write + + + TASK_GAMMA_PAUSE_CH6_EN + Configures whether or not to enable ledc_ch6_gamma_pause task.\\0: Disable\\1: Enable + 14 + 1 + read-write + + + TASK_GAMMA_PAUSE_CH7_EN + Configures whether or not to enable ledc_ch7_gamma_pause task.\\0: Disable\\1: Enable + 15 + 1 + read-write + + + TASK_GAMMA_RESUME_CH0_EN + Configures whether or not to enable ledc_ch0_gamma_resume task.\\0: Disable\\1: Enable + 16 + 1 + read-write + + + TASK_GAMMA_RESUME_CH1_EN + Configures whether or not to enable ledc_ch1_gamma_resume task.\\0: Disable\\1: Enable + 17 + 1 + read-write + + + TASK_GAMMA_RESUME_CH2_EN + Configures whether or not to enable ledc_ch2_gamma_resume task.\\0: Disable\\1: Enable + 18 + 1 + read-write + + + TASK_GAMMA_RESUME_CH3_EN + Configures whether or not to enable ledc_ch3_gamma_resume task.\\0: Disable\\1: Enable + 19 + 1 + read-write + + + TASK_GAMMA_RESUME_CH4_EN + Configures whether or not to enable ledc_ch4_gamma_resume task.\\0: Disable\\1: Enable + 20 + 1 + read-write + + + TASK_GAMMA_RESUME_CH5_EN + Configures whether or not to enable ledc_ch5_gamma_resume task.\\0: Disable\\1: Enable + 21 + 1 + read-write + + + TASK_GAMMA_RESUME_CH6_EN + Configures whether or not to enable ledc_ch6_gamma_resume task.\\0: Disable\\1: Enable + 22 + 1 + read-write + + + TASK_GAMMA_RESUME_CH7_EN + Configures whether or not to enable ledc_ch7_gamma_resume task.\\0: Disable\\1: Enable + 23 + 1 + read-write + + + + + 4 + 0x4 + TIMER%s_CMP + Ledc timer%s compare value register. + 0x140 + 0x20 + + + TIMER_CMP + Configures the comparison value for LEDC timer%s. + 0 + 20 + read-write + + + + + 4 + 0x4 + TIMER%s_CNT_CAP + Ledc timer%s captured count value register. + 0x150 + 0x20 + + + TIMER_CNT_CAP + Represents the captured LEDC timer%s count value. + 0 + 20 + read-only + + + + + CONF + LEDC global configuration register + 0x170 + 0x20 + + + APB_CLK_SEL + Configures the clock source for the four timers.\\0: APB_CLK\\1: RC_FAST_CLK\\2: XTAL_CLK\\3: Invalid. No clock + 0 + 2 + read-write + + + GAMMA_RAM_CLK_EN_CH0 + Configures whether or not to open LEDC ch0 gamma ram clock gate.\\0: Open the clock gate only when application writes or reads LEDC ch0 gamma ram\\1: Force open the clock gate for LEDC ch0 gamma ram + 2 + 1 + read-write + + + GAMMA_RAM_CLK_EN_CH1 + Configures whether or not to open LEDC ch1 gamma ram clock gate.\\0: Open the clock gate only when application writes or reads LEDC ch1 gamma ram\\1: Force open the clock gate for LEDC ch1 gamma ram + 3 + 1 + read-write + + + GAMMA_RAM_CLK_EN_CH2 + Configures whether or not to open LEDC ch2 gamma ram clock gate.\\0: Open the clock gate only when application writes or reads LEDC ch2 gamma ram\\1: Force open the clock gate for LEDC ch2 gamma ram + 4 + 1 + read-write + + + GAMMA_RAM_CLK_EN_CH3 + Configures whether or not to open LEDC ch3 gamma ram clock gate.\\0: Open the clock gate only when application writes or reads LEDC ch3 gamma ram\\1: Force open the clock gate for LEDC ch3 gamma ram + 5 + 1 + read-write + + + GAMMA_RAM_CLK_EN_CH4 + Configures whether or not to open LEDC ch4 gamma ram clock gate.\\0: Open the clock gate only when application writes or reads LEDC ch4 gamma ram\\1: Force open the clock gate for LEDC ch4 gamma ram + 6 + 1 + read-write + + + GAMMA_RAM_CLK_EN_CH5 + Configures whether or not to open LEDC ch5 gamma ram clock gate.\\0: Open the clock gate only when application writes or reads LEDC ch5 gamma ram\\1: Force open the clock gate for LEDC ch5 gamma ram + 7 + 1 + read-write + + + GAMMA_RAM_CLK_EN_CH6 + Configures whether or not to open LEDC ch6 gamma ram clock gate.\\0: Open the clock gate only when application writes or reads LEDC ch6 gamma ram\\1: Force open the clock gate for LEDC ch6 gamma ram + 8 + 1 + read-write + + + GAMMA_RAM_CLK_EN_CH7 + Configures whether or not to open LEDC ch7 gamma ram clock gate.\\0: Open the clock gate only when application writes or reads LEDC ch7 gamma ram\\1: Force open the clock gate for LEDC ch7 gamma ram + 9 + 1 + read-write + + + CLK_EN + Configures whether or not to open register clock gate.\\0: Open the clock gate only when application writes registers\\1: Force open the clock gate for register + 31 + 1 + read-write + + + + + DATE + Version control register + 0x174 + 0x20 + 0x02303070 + + + LEDC_DATE + Configures the version. + 0 + 28 + read-write + + + + + + + LP_INTR + Low-power Interrupt Controller + LPINTR + 0x5012C000 + + 0x0 + 0x18 + registers + + + + SW_INT_RAW + need_des + 0x0 + 0x20 + + + LP_SW_INT_RAW + need_des + 31 + 1 + read-write + + + + + SW_INT_ST + need_des + 0x4 + 0x20 + + + LP_SW_INT_ST + need_des + 31 + 1 + read-only + + + + + SW_INT_ENA + need_des + 0x8 + 0x20 + + + LP_SW_INT_ENA + need_des + 31 + 1 + read-write + + + + + SW_INT_CLR + need_des + 0xC + 0x20 + + + LP_SW_INT_CLR + need_des + 31 + 1 + write-only + + + + + STATUS + need_des + 0x10 + 0x20 + + + LP_HUK_INTR_ST + need_des + 10 + 1 + read-only + + + SYSREG_INTR_ST + need_des + 11 + 1 + read-only + + + LP_SW_INTR_ST + need_des + 12 + 1 + read-only + + + LP_EFUSE_INTR_ST + need_des + 13 + 1 + read-only + + + LP_UART_INTR_ST + need_des + 14 + 1 + read-only + + + LP_TSENS_INTR_ST + need_des + 15 + 1 + read-only + + + LP_TOUCH_INTR_ST + need_des + 16 + 1 + read-only + + + LP_SPI_INTR_ST + need_des + 17 + 1 + read-only + + + LP_I2S_INTR_ST + need_des + 18 + 1 + read-only + + + LP_I2C_INTR_ST + need_des + 19 + 1 + read-only + + + LP_GPIO_INTR_ST + need_des + 20 + 1 + read-only + + + LP_ADC_INTR_ST + need_des + 21 + 1 + read-only + + + ANAPERI_INTR_ST + need_des + 22 + 1 + read-only + + + PMU_REG_1_INTR_ST + need_des + 23 + 1 + read-only + + + PMU_REG_0_INTR_ST + need_des + 24 + 1 + read-only + + + MB_LP_INTR_ST + need_des + 25 + 1 + read-only + + + MB_HP_INTR_ST + need_des + 26 + 1 + read-only + + + LP_TIMER_REG_1_INTR_ST + need_des + 27 + 1 + read-only + + + LP_TIMER_REG_0_INTR_ST + need_des + 28 + 1 + read-only + + + LP_WDT_INTR_ST + need_des + 29 + 1 + read-only + + + LP_RTC_INTR_ST + need_des + 30 + 1 + read-only + + + HP_INTR_ST + need_des + 31 + 1 + read-only + + + + + DATE + need_des + 0x3FC + 0x20 + + + CLK_EN + need_des + 31 + 1 + read-write + + + + + + + LP_PERI + LP_PERI Peripheral + LPPERI + 0x50120000 + + 0x0 + 0x2C + registers + + + + CLK_EN + need_des + 0x0 + 0x20 + 0x7FFF0000 + + + CK_EN_RNG + need_des + 16 + 1 + read-write + + + CK_EN_LP_TSENS + need_des + 17 + 1 + read-write + + + CK_EN_LP_PMS + need_des + 18 + 1 + read-write + + + CK_EN_LP_EFUSE + need_des + 19 + 1 + read-write + + + CK_EN_LP_IOMUX + need_des + 20 + 1 + read-write + + + CK_EN_LP_TOUCH + need_des + 21 + 1 + read-write + + + CK_EN_LP_SPI + need_des + 22 + 1 + read-write + + + CK_EN_LP_ADC + need_des + 23 + 1 + read-write + + + CK_EN_LP_I2S_TX + need_des + 24 + 1 + read-write + + + CK_EN_LP_I2S_RX + need_des + 25 + 1 + read-write + + + CK_EN_LP_I2S + need_des + 26 + 1 + read-write + + + CK_EN_LP_I2CMST + need_des + 27 + 1 + read-write + + + CK_EN_LP_I2C + need_des + 28 + 1 + read-write + + + CK_EN_LP_UART + need_des + 29 + 1 + read-write + + + CK_EN_LP_INTR + need_des + 30 + 1 + read-write + + + CK_EN_LP_CORE + write 1 to force on lp_core clk + 31 + 1 + read-write + + + + + CORE_CLK_SEL + need_des + 0x4 + 0x20 + + + LP_I2S_TX_CLK_SEL + need_des + 24 + 2 + read-write + + + LP_I2S_RX_CLK_SEL + need_des + 26 + 2 + read-write + + + LP_I2C_CLK_SEL + need_des + 28 + 2 + read-write + + + LP_UART_CLK_SEL + need_des + 30 + 2 + read-write + + + + + RESET_EN + need_des + 0x8 + 0x20 + + + RST_EN_LP_TSENS + need_des + 18 + 1 + read-write + + + RST_EN_LP_PMS + need_des + 19 + 1 + read-write + + + RST_EN_LP_EFUSE + need_des + 20 + 1 + read-write + + + RST_EN_LP_IOMUX + need_des + 21 + 1 + read-write + + + RST_EN_LP_TOUCH + need_des + 22 + 1 + read-write + + + RST_EN_LP_SPI + need_des + 23 + 1 + read-write + + + RST_EN_LP_ADC + need_des + 24 + 1 + read-write + + + RST_EN_LP_I2S + need_des + 25 + 1 + read-write + + + RST_EN_LP_I2CMST + need_des + 26 + 1 + read-write + + + RST_EN_LP_I2C + need_des + 27 + 1 + read-write + + + RST_EN_LP_UART + need_des + 28 + 1 + read-write + + + RST_EN_LP_INTR + need_des + 29 + 1 + read-write + + + RST_EN_LP_ROM + need_des + 30 + 1 + read-write + + + RST_EN_LP_CORE + need_des + 31 + 1 + write-only + + + + + CPU + need_des + 0xC + 0x20 + 0x80000000 + + + LPCORE_DBGM_UNAVAILABLE + need_des + 31 + 1 + read-write + + + + + MEM_CTRL + need_des + 0x28 + 0x20 + 0x80000000 + + + LP_UART_WAKEUP_FLAG_CLR + need_des + 0 + 1 + write-only + + + LP_UART_WAKEUP_FLAG + need_des + 1 + 1 + read-write + + + LP_UART_WAKEUP_EN + need_des + 29 + 1 + read-write + + + LP_UART_MEM_FORCE_PD + need_des + 30 + 1 + read-write + + + LP_UART_MEM_FORCE_PU + need_des + 31 + 1 + read-write + + + + + ADC_CTRL + need_des + 0x2C + 0x20 + 0x04040400 + + + SAR2_CLK_FORCE_ON + need_des + 6 + 1 + read-write + + + SAR1_CLK_FORCE_ON + need_des + 7 + 1 + read-write + + + LPADC_FUNC_DIV_NUM + need_des + 8 + 8 + read-write + + + LPADC_SAR2_DIV_NUM + need_des + 16 + 8 + read-write + + + LPADC_SAR1_DIV_NUM + need_des + 24 + 8 + read-write + + + + + LP_I2S_RXCLK_DIV_NUM + need_des + 0x30 + 0x20 + 0x02000000 + + + LP_I2S_RX_CLKM_DIV_NUM + need_des + 24 + 8 + read-write + + + + + LP_I2S_RXCLK_DIV_XYZ + need_des + 0x34 + 0x20 + 0x00004000 + + + LP_I2S_RX_CLKM_DIV_YN1 + need_des + 4 + 1 + read-write + + + LP_I2S_RX_CLKM_DIV_Z + need_des + 5 + 9 + read-write + + + LP_I2S_RX_CLKM_DIV_Y + need_des + 14 + 9 + read-write + + + LP_I2S_RX_CLKM_DIV_X + need_des + 23 + 9 + read-write + + + + + LP_I2S_TXCLK_DIV_NUM + need_des + 0x38 + 0x20 + 0x02000000 + + + LP_I2S_TX_CLKM_DIV_NUM + need_des + 24 + 8 + read-write + + + + + LP_I2S_TXCLK_DIV_XYZ + need_des + 0x3C + 0x20 + 0x00004000 + + + LP_I2S_TX_CLKM_DIV_YN1 + need_des + 4 + 1 + read-write + + + LP_I2S_TX_CLKM_DIV_Z + need_des + 5 + 9 + read-write + + + LP_I2S_TX_CLKM_DIV_Y + need_des + 14 + 9 + read-write + + + LP_I2S_TX_CLKM_DIV_X + need_des + 23 + 9 + read-write + + + + + DATE + need_des + 0x3FC + 0x20 + + + CLK_EN + need_des + 31 + 1 + read-write + + + + + + + LP_SYS + LP_SYS Peripheral + LPSYSREG + 0x50110000 + + 0x0 + 0x110 + registers + + + LP_SYS + 19 + + + + LP_SYS_VER_DATE + need_des + 0x0 + 0x20 + 0x20230509 + + + VER_DATE + need_des + 0 + 32 + read-write + + + + + CLK_SEL_CTRL + need_des + 0x4 + 0x20 + + + ENA_SW_SEL_SYS_CLK + reserved + 16 + 1 + read-write + + + SW_SYS_CLK_SRC_SEL + reserved + 17 + 1 + read-write + + + + + SYS_CTRL + need_des + 0x8 + 0x20 + 0x1FFFC7F8 + + + LP_CORE_DISABLE + lp cpu disable + 0 + 1 + read-write + + + SYS_SW_RST + digital system software reset bit + 1 + 1 + write-only + + + FORCE_DOWNLOAD_BOOT + need_des + 2 + 1 + read-write + + + DIG_FIB + need_des + 3 + 8 + read-write + + + IO_MUX_RESET_DISABLE + reset disable bit for LP IOMUX + 11 + 1 + read-write + + + ANA_FIB + need_des + 14 + 7 + read-only + + + LP_FIB_SEL + need_des + 21 + 8 + read-write + + + LP_CORE_ETM_WAKEUP_FLAG_CLR + need_des + 29 + 1 + write-only + + + LP_CORE_ETM_WAKEUP_FLAG + need_des + 30 + 1 + read-write + + + SYSTIMER_STALL_SEL + 0: use systimer_stall signal from hp_core0, 1: use systimer_stall signal from hp_core1 + 31 + 1 + read-write + + + + + LP_CLK_CTRL + need_des + 0xC + 0x20 + 0x00004001 + + + CLK_EN + need_des + 0 + 1 + read-write + + + LP_FOSC_HP_CKEN + reserved + 14 + 1 + read-write + + + + + LP_RST_CTRL + need_des + 0x10 + 0x20 + 0x00000003 + + + ANA_RST_BYPASS + analog source reset bypass : wdt,brown out,super wdt,glitch + 0 + 1 + read-write + + + SYS_RST_BYPASS + system source reset bypass : software reset,hp wdt,lp wdt,efuse + 1 + 1 + read-write + + + EFUSE_FORCE_NORST + efuse force no reset control + 2 + 1 + read-write + + + + + LP_CORE_BOOT_ADDR + need_des + 0x18 + 0x20 + 0x50100000 + + + LP_CPU_BOOT_ADDR + need_des + 0 + 32 + read-write + + + + + EXT_WAKEUP1 + need_des + 0x1C + 0x20 + + + SEL + Bitmap to select RTC pads for ext wakeup1 + 0 + 16 + read-write + + + STATUS_CLR + clear ext wakeup1 status + 16 + 1 + write-only + + + + + EXT_WAKEUP1_STATUS + need_des + 0x20 + 0x20 + + + EXT_WAKEUP1_STATUS + ext wakeup1 status + 0 + 16 + read-only + + + + + LP_TCM_PWR_CTRL + need_des + 0x24 + 0x20 + + + LP_TCM_ROM_CLK_FORCE_ON + need_des + 5 + 1 + read-write + + + LP_TCM_RAM_CLK_FORCE_ON + need_des + 7 + 1 + read-write + + + + + BOOT_ADDR_HP_LP + need_des + 0x28 + 0x20 + + + BOOT_ADDR_HP_LP + need_des + 0 + 32 + read-write + + + + + LP_STORE0 + need_des + 0x2C + 0x20 + + + LP_SCRATCH0 + need_des + 0 + 32 + read-write + + + + + LP_STORE1 + need_des + 0x30 + 0x20 + + + LP_SCRATCH1 + need_des + 0 + 32 + read-write + + + + + LP_STORE2 + need_des + 0x34 + 0x20 + + + LP_SCRATCH2 + need_des + 0 + 32 + read-write + + + + + LP_STORE3 + need_des + 0x38 + 0x20 + + + LP_SCRATCH3 + need_des + 0 + 32 + read-write + + + + + LP_STORE4 + need_des + 0x3C + 0x20 + + + LP_SCRATCH4 + need_des + 0 + 32 + read-write + + + + + LP_STORE5 + need_des + 0x40 + 0x20 + + + LP_SCRATCH5 + need_des + 0 + 32 + read-write + + + + + LP_STORE6 + need_des + 0x44 + 0x20 + + + LP_SCRATCH6 + need_des + 0 + 32 + read-write + + + + + LP_STORE7 + need_des + 0x48 + 0x20 + + + LP_SCRATCH7 + need_des + 0 + 32 + read-write + + + + + LP_STORE8 + need_des + 0x4C + 0x20 + + + LP_SCRATCH8 + need_des + 0 + 32 + read-write + + + + + LP_STORE9 + need_des + 0x50 + 0x20 + + + LP_SCRATCH9 + need_des + 0 + 32 + read-write + + + + + LP_STORE10 + need_des + 0x54 + 0x20 + + + LP_SCRATCH10 + need_des + 0 + 32 + read-write + + + + + LP_STORE11 + need_des + 0x58 + 0x20 + + + LP_SCRATCH11 + need_des + 0 + 32 + read-write + + + + + LP_STORE12 + need_des + 0x5C + 0x20 + + + LP_SCRATCH12 + need_des + 0 + 32 + read-write + + + + + LP_STORE13 + need_des + 0x60 + 0x20 + + + LP_SCRATCH13 + need_des + 0 + 32 + read-write + + + + + LP_STORE14 + need_des + 0x64 + 0x20 + + + LP_SCRATCH14 + need_des + 0 + 32 + read-write + + + + + LP_STORE15 + need_des + 0x68 + 0x20 + + + LP_SCRATCH15 + need_des + 0 + 32 + read-write + + + + + LP_PROBEA_CTRL + need_des + 0x6C + 0x20 + + + PROBE_A_MOD_SEL + need_des + 0 + 16 + read-write + + + PROBE_A_TOP_SEL + need_des + 16 + 8 + read-write + + + PROBE_L_SEL + need_des + 24 + 2 + read-write + + + PROBE_H_SEL + need_des + 26 + 2 + read-write + + + PROBE_GLOBAL_EN + need_des + 28 + 1 + read-write + + + + + LP_PROBEB_CTRL + need_des + 0x70 + 0x20 + + + PROBE_B_MOD_SEL + need_des + 0 + 16 + read-write + + + PROBE_B_TOP_SEL + need_des + 16 + 8 + read-write + + + PROBE_B_EN + need_des + 24 + 1 + read-write + + + + + LP_PROBE_OUT + need_des + 0x74 + 0x20 + + + PROBE_TOP_OUT + need_des + 0 + 32 + read-only + + + + + F2S_APB_BRG_CNTL + need_des + 0x9C + 0x20 + + + F2S_APB_POSTW_EN + reserved + 0 + 1 + read-write + + + + + USB_CTRL + need_des + 0x100 + 0x20 + + + SW_HW_USB_PHY_SEL + need_des + 0 + 1 + read-write + + + SW_USB_PHY_SEL + need_des + 1 + 1 + read-write + + + USBOTG20_WAKEUP_CLR + clear usb wakeup to PMU. + 2 + 1 + write-only + + + USBOTG20_IN_SUSPEND + indicate usb otg2.0 is in suspend state. + 3 + 1 + read-write + + + + + ANA_XPD_PAD_GROUP + need_des + 0x10C + 0x20 + 0x000000FF + + + ANA_REG_XPD_PAD_GROUP + Set 1 to power up pad group + 0 + 8 + read-write + + + + + LP_TCM_RAM_RDN_ECO_CS + need_des + 0x110 + 0x20 + + + LP_TCM_RAM_RDN_ECO_EN + need_des + 0 + 1 + read-write + + + LP_TCM_RAM_RDN_ECO_RESULT + need_des + 1 + 1 + read-only + + + + + LP_TCM_RAM_RDN_ECO_LOW + need_des + 0x114 + 0x20 + + + LP_TCM_RAM_RDN_ECO_LOW + need_des + 0 + 32 + read-write + + + + + LP_TCM_RAM_RDN_ECO_HIGH + need_des + 0x118 + 0x20 + 0xFFFFFFFF + + + LP_TCM_RAM_RDN_ECO_HIGH + need_des + 0 + 32 + read-write + + + + + LP_TCM_ROM_RDN_ECO_CS + need_des + 0x11C + 0x20 + + + LP_TCM_ROM_RDN_ECO_EN + need_des + 0 + 1 + read-write + + + LP_TCM_ROM_RDN_ECO_RESULT + need_des + 1 + 1 + read-only + + + + + LP_TCM_ROM_RDN_ECO_LOW + need_des + 0x120 + 0x20 + + + LP_TCM_ROM_RDN_ECO_LOW + need_des + 0 + 32 + read-write + + + + + LP_TCM_ROM_RDN_ECO_HIGH + need_des + 0x124 + 0x20 + 0xFFFFFFFF + + + LP_TCM_ROM_RDN_ECO_HIGH + need_des + 0 + 32 + read-write + + + + + HP_ROOT_CLK_CTRL + need_des + 0x130 + 0x20 + 0x00000003 + + + CPU_CLK_EN + clock gate enable for hp cpu root 400M clk + 0 + 1 + read-write + + + SYS_CLK_EN + clock gate enable for hp sys root 480M clk + 1 + 1 + read-write + + + + + LP_PMU_RDN_ECO_LOW + need_des + 0x138 + 0x20 + + + PMU_RDN_ECO_LOW + need_des + 0 + 32 + read-write + + + + + LP_PMU_RDN_ECO_HIGH + need_des + 0x13C + 0x20 + 0xFFFFFFFF + + + PMU_RDN_ECO_HIGH + need_des + 0 + 32 + read-write + + + + + PAD_COMP0 + need_des + 0x148 + 0x20 + + + DREF_COMP0 + pad comp dref + 0 + 3 + read-write + + + MODE_COMP0 + pad comp mode + 3 + 1 + read-write + + + XPD_COMP0 + pad comp xpd + 4 + 1 + read-write + + + + + PAD_COMP1 + need_des + 0x14C + 0x20 + + + DREF_COMP1 + pad comp dref + 0 + 3 + read-write + + + MODE_COMP1 + pad comp mode + 3 + 1 + read-write + + + XPD_COMP1 + pad comp xpd + 4 + 1 + read-write + + + + + BACKUP_DMA_CFG0 + need_des + 0x154 + 0x20 + 0x1906414A + + + BURST_LIMIT_AON + need_des + 0 + 5 + read-write + + + READ_INTERVAL_AON + need_des + 5 + 7 + read-write + + + LINK_BACKUP_TOUT_THRES_AON + need_des + 12 + 10 + read-write + + + LINK_TOUT_THRES_AON + need_des + 22 + 10 + read-write + + + + + BACKUP_DMA_CFG1 + need_des + 0x158 + 0x20 + + + AON_BYPASS + need_des + 31 + 1 + read-write + + + + + BACKUP_DMA_CFG2 + need_des + 0x15C + 0x20 + + + LINK_ADDR_AON + need_des + 0 + 32 + read-write + + + + + BOOT_ADDR_HP_CORE1 + need_des + 0x164 + 0x20 + + + BOOT_ADDR_HP_CORE1 + need_des + 0 + 32 + read-write + + + + + LP_ADDRHOLE_ADDR + need_des + 0x168 + 0x20 + + + LP_ADDRHOLE_ADDR + need_des + 0 + 32 + read-only + + + + + LP_ADDRHOLE_INFO + need_des + 0x16C + 0x20 + + + LP_ADDRHOLE_ID + master id: 5'h0: hp core0, 5'h1:hp core1, 5'h2:lp core, 5'h3:usb otg11, 5'h4: regdma, 5'h5: gmac, 5'h5 sdmmc, 5'h7: usbotg20, 5'h8: trace0, 5'h9: trace1, 5'ha tcm monitor, 5'hb: l2mem monitor. 5'h10~5'h1f: ahb pdma. + 0 + 5 + read-only + + + LP_ADDRHOLE_WR + 1:write trans, 0: read trans. + 5 + 1 + read-only + + + LP_ADDRHOLE_SECURE + 1: illegal address access, 0: access without permission + 6 + 1 + read-only + + + + + INT_RAW + raw interrupt register + 0x170 + 0x20 + + + LP_ADDRHOLE_INT_RAW + the raw interrupt status of lp addrhole(for lp peri and lp ram tee apm, and lp matrix default slave) + 0 + 1 + read-only + + + IDBUS_ADDRHOLE_INT_RAW + the raw interrupt status of idbus addrhole(only for lp cpu ibus and dbus) + 1 + 1 + read-only + + + LP_CORE_AHB_TIMEOUT_INT_RAW + the raw interrupt status of lp core ahb bus timeout + 2 + 1 + read-only + + + LP_CORE_IBUS_TIMEOUT_INT_RAW + the raw interrupt status of lp core ibus timeout + 3 + 1 + read-only + + + LP_CORE_DBUS_TIMEOUT_INT_RAW + the raw interrupt status of lp core dbus timeout + 4 + 1 + read-only + + + ETM_TASK_ULP_INT_RAW + the raw interrupt status of etm task ulp + 5 + 1 + read-only + + + SLOW_CLK_TICK_INT_RAW + the raw interrupt status of slow_clk_tick + 6 + 1 + read-only + + + + + INT_ST + masked interrupt register + 0x174 + 0x20 + + + LP_ADDRHOLE_INT_ST + the masked interrupt status of lp addrhole (for lp peri and lp ram tee apm, and lp matrix default slave) + 0 + 1 + read-only + + + IDBUS_ADDRHOLE_INT_ST + the masked interrupt status of idbus addrhole(only for lp cpu ibus and dbus) + 1 + 1 + read-only + + + LP_CORE_AHB_TIMEOUT_INT_ST + the masked interrupt status of lp core ahb bus timeout + 2 + 1 + read-only + + + LP_CORE_IBUS_TIMEOUT_INT_ST + the masked interrupt status of lp core ibus timeout + 3 + 1 + read-only + + + LP_CORE_DBUS_TIMEOUT_INT_ST + the masked interrupt status of lp core dbus timeout + 4 + 1 + read-only + + + ETM_TASK_ULP_INT_ST + the masked interrupt status of etm task ulp + 5 + 1 + read-only + + + SLOW_CLK_TICK_INT_ST + the masked interrupt status of slow_clk_tick + 6 + 1 + read-only + + + + + INT_ENA + masked interrupt register + 0x178 + 0x20 + + + LP_ADDRHOLE_INT_ENA + Write 1 to enable lp addrhole int + 0 + 1 + read-write + + + IDBUS_ADDRHOLE_INT_ENA + Write 1 to enable idbus addrhole int + 1 + 1 + read-write + + + LP_CORE_AHB_TIMEOUT_INT_ENA + Write 1 to enable lp_core_ahb_timeout int + 2 + 1 + read-write + + + LP_CORE_IBUS_TIMEOUT_INT_ENA + Write 1 to enable lp_core_ibus_timeout int + 3 + 1 + read-write + + + LP_CORE_DBUS_TIMEOUT_INT_ENA + Write 1 to enable lp_core_dbus_timeout int + 4 + 1 + read-write + + + ETM_TASK_ULP_INT_ENA + Write 1 to enable etm task ulp int + 5 + 1 + read-write + + + SLOW_CLK_TICK_INT_ENA + Write 1 to enable slow_clk_tick int + 6 + 1 + read-write + + + + + INT_CLR + interrupt clear register + 0x17C + 0x20 + + + LP_ADDRHOLE_INT_CLR + write 1 to clear lp addrhole int + 0 + 1 + write-only + + + IDBUS_ADDRHOLE_INT_CLR + write 1 to clear idbus addrhole int + 1 + 1 + write-only + + + LP_CORE_AHB_TIMEOUT_INT_CLR + Write 1 to clear lp_core_ahb_timeout int + 2 + 1 + write-only + + + LP_CORE_IBUS_TIMEOUT_INT_CLR + Write 1 to clear lp_core_ibus_timeout int + 3 + 1 + write-only + + + LP_CORE_DBUS_TIMEOUT_INT_CLR + Write 1 to clear lp_core_dbus_timeout int + 4 + 1 + write-only + + + ETM_TASK_ULP_INT_CLR + Write 1 to clear etm tasl ulp int + 5 + 1 + write-only + + + SLOW_CLK_TICK_INT_CLR + Write 1 to clear slow_clk_tick int + 6 + 1 + write-only + + + + + HP_MEM_AUX_CTRL + need_des + 0x180 + 0x20 + 0x00002070 + + + HP_MEM_AUX_CTRL + need_des + 0 + 32 + read-write + + + + + LP_MEM_AUX_CTRL + need_des + 0x184 + 0x20 + 0x00002070 + + + LP_MEM_AUX_CTRL + need_des + 0 + 32 + read-write + + + + + HP_ROM_AUX_CTRL + need_des + 0x188 + 0x20 + 0x00000070 + + + HP_ROM_AUX_CTRL + need_des + 0 + 32 + read-write + + + + + LP_ROM_AUX_CTRL + need_des + 0x18C + 0x20 + 0x00000070 + + + LP_ROM_AUX_CTRL + need_des + 0 + 32 + read-write + + + + + LP_CPU_DBG_PC + need_des + 0x190 + 0x20 + + + LP_CPU_DBG_PC + need_des + 0 + 32 + read-only + + + + + LP_CPU_EXC_PC + need_des + 0x194 + 0x20 + + + LP_CPU_EXC_PC + need_des + 0 + 32 + read-only + + + + + IDBUS_ADDRHOLE_ADDR + need_des + 0x198 + 0x20 + + + IDBUS_ADDRHOLE_ADDR + need_des + 0 + 32 + read-only + + + + + IDBUS_ADDRHOLE_INFO + need_des + 0x19C + 0x20 + + + IDBUS_ADDRHOLE_ID + need_des + 0 + 5 + read-only + + + IDBUS_ADDRHOLE_WR + need_des + 5 + 1 + read-only + + + IDBUS_ADDRHOLE_SECURE + need_des + 6 + 1 + read-only + + + + + HP_POR_RST_BYPASS_CTRL + need_des + 0x1A0 + 0x20 + 0xFF00FF00 + + + HP_PO_CNNT_RSTN_BYPASS_CTRL + [15] 1'b1: po_cnnt_rstn bypass sys_sw_rstn +[14] 1'b1: po_cnnt_rstn bypass hp_wdt_sys_rstn +[13] 1'b1: po_cnnt_rstn bypass hp_cpu_intrusion_rstn +[12] 1'b1: po_cnnt_rstn bypass hp_sdio_sys_rstn +[11] 1'b1: po_cnnt_rstn bypass usb_jtag_chip_rst +[10] 1'b1: po_cnnt_rstn bypass usb_uart_chip_rst +[9] 1'b1: po_cnnt_rstn bypass lp_wdt_hp_sys_rstn +[8] 1'b1: po_cnnt_rstn bypass efuse_err_rstn + 8 + 8 + read-write + + + HP_PO_RSTN_BYPASS_CTRL + [31] 1'b1: po_rstn bypass sys_sw_rstn +[30] 1'b1: po_rstn bypass hp_wdt_sys_rstn +[29] 1'b1: po_rstn bypass hp_cpu_intrusion_rstn +[28] 1'b1: po_rstn bypass hp_sdio_sys_rstn +[27] 1'b1: po_rstn bypass usb_jtag_chip_rst +[26] 1'b1: po_rstn bypass usb_uart_chip_rst +[25] 1'b1: po_rstn bypass lp_wdt_hp_sys_rstn +[24] 1'b1: po_rstn bypass efuse_err_rstn + 24 + 8 + read-write + + + + + RNG_DATA + rng data register + 0x1A4 + 0x20 + + + RND_DATA + result of rng output + 0 + 32 + read-only + + + + + LP_CORE_AHB_TIMEOUT + need_des + 0x1B0 + 0x20 + 0x007FFFFF + + + EN + set this field to 1 to enable lp core ahb timeout handle + 0 + 1 + read-write + + + THRES + This field used to set lp core ahb bus timeout threshold + 1 + 16 + read-write + + + LP2HP_AHB_TIMEOUT_EN + set this field to 1 to enable lp2hp ahb timeout handle + 17 + 1 + read-write + + + LP2HP_AHB_TIMEOUT_THRES + This field used to set lp2hp ahb bus timeout threshold + 18 + 5 + read-write + + + + + LP_CORE_IBUS_TIMEOUT + need_des + 0x1B4 + 0x20 + 0x0001FFFF + + + EN + set this field to 1 to enable lp core ibus timeout handle + 0 + 1 + read-write + + + THRES + This field used to set lp core ibus timeout threshold + 1 + 16 + read-write + + + + + LP_CORE_DBUS_TIMEOUT + need_des + 0x1B8 + 0x20 + 0x0001FFFF + + + EN + set this field to 1 to enable lp core dbus timeout handle + 0 + 1 + read-write + + + THRES + This field used to set lp core dbus timeout threshold + 1 + 16 + read-write + + + + + LP_CORE_ERR_RESP_DIS + need_des + 0x1BC + 0x20 + + + LP_CORE_ERR_RESP_DIS + Set bit0 to disable ibus err resp;Set bit1 to disable dbus err resp; Set bit 2 to disable ahb err resp. + 0 + 3 + read-write + + + + + RNG_CFG + rng cfg register + 0x1C0 + 0x20 + 0x00000003 + + + RNG_TIMER_EN + enable rng timer + 0 + 1 + read-write + + + RNG_TIMER_PSCALE + configure ng timer pscale + 1 + 8 + read-write + + + RNG_SAR_ENABLE + enable rng_saradc + 9 + 1 + read-write + + + RNG_SAR_DATA + debug rng sar sample cnt + 16 + 13 + read-only + + + + + + + LP_ANA_PERI + LP_ANA_PERI Peripheral + LP_ANA_PERI + 0x50113000 + + 0x0 + 0x140 + registers + + + LP_ANA + 8 + + + + LP_ANA_BOD_MODE0_CNTL + need_des + 0x0 + 0x20 + 0x0FFC0100 + + + LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA + need_des + 6 + 1 + read-write + + + LP_ANA_BOD_MODE0_PD_RF_ENA + need_des + 7 + 1 + read-write + + + LP_ANA_BOD_MODE0_INTR_WAIT + need_des + 8 + 10 + read-write + + + LP_ANA_BOD_MODE0_RESET_WAIT + need_des + 18 + 10 + read-write + + + LP_ANA_BOD_MODE0_CNT_CLR + need_des + 28 + 1 + read-write + + + LP_ANA_BOD_MODE0_INTR_ENA + need_des + 29 + 1 + read-write + + + LP_ANA_BOD_MODE0_RESET_SEL + need_des + 30 + 1 + read-write + + + LP_ANA_BOD_MODE0_RESET_ENA + need_des + 31 + 1 + read-write + + + + + LP_ANA_BOD_MODE1_CNTL + need_des + 0x4 + 0x20 + + + LP_ANA_BOD_MODE1_RESET_ENA + need_des + 31 + 1 + read-write + + + + + LP_ANA_VDD_SOURCE_CNTL + need_des + 0x8 + 0x20 + 0x040000FF + + + LP_ANA_DETMODE_SEL + need_des + 0 + 8 + read-write + + + LP_ANA_VGOOD_EVENT_RECORD + need_des + 8 + 8 + read-only + + + LP_ANA_VBAT_EVENT_RECORD_CLR + need_des + 16 + 8 + write-only + + + LP_ANA_BOD_SOURCE_ENA + need_des + 24 + 8 + read-write + + + + + LP_ANA_VDDBAT_BOD_CNTL + need_des + 0xC + 0x20 + 0xFFC00000 + + + LP_ANA_VDDBAT_UNDERVOLTAGE_FLAG + need_des + 0 + 1 + read-only + + + LP_ANA_VDDBAT_CHARGER + need_des + 10 + 1 + read-write + + + LP_ANA_VDDBAT_CNT_CLR + need_des + 11 + 1 + read-write + + + LP_ANA_VDDBAT_UPVOLTAGE_TARGET + need_des + 12 + 10 + read-write + + + LP_ANA_VDDBAT_UNDERVOLTAGE_TARGET + need_des + 22 + 10 + read-write + + + + + LP_ANA_VDDBAT_CHARGE_CNTL + need_des + 0x10 + 0x20 + 0xFFC00000 + + + LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG + need_des + 0 + 1 + read-only + + + LP_ANA_VDDBAT_CHARGE_CHARGER + need_des + 10 + 1 + read-write + + + LP_ANA_VDDBAT_CHARGE_CNT_CLR + need_des + 11 + 1 + read-write + + + LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_TARGET + need_des + 12 + 10 + read-write + + + LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET + need_des + 22 + 10 + read-write + + + + + LP_ANA_CK_GLITCH_CNTL + need_des + 0x14 + 0x20 + + + LP_ANA_CK_GLITCH_RESET_ENA + need_des + 31 + 1 + read-write + + + + + LP_ANA_PG_GLITCH_CNTL + need_des + 0x18 + 0x20 + + + LP_ANA_POWER_GLITCH_RESET_ENA + need_des + 31 + 1 + read-write + + + + + LP_ANA_FIB_ENABLE + need_des + 0x1C + 0x20 + 0xFFFFFFFF + + + LP_ANA_ANA_FIB_ENA + need_des + 0 + 32 + read-write + + + + + LP_ANA_INT_RAW + need_des + 0x20 + 0x20 + + + LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW + need_des + 27 + 1 + read-write + + + LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW + need_des + 28 + 1 + read-write + + + LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW + need_des + 29 + 1 + read-write + + + LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW + need_des + 30 + 1 + read-write + + + LP_ANA_BOD_MODE0_INT_RAW + need_des + 31 + 1 + read-write + + + + + LP_ANA_INT_ST + need_des + 0x24 + 0x20 + + + LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ST + need_des + 27 + 1 + read-only + + + LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST + need_des + 28 + 1 + read-only + + + LP_ANA_VDDBAT_UPVOLTAGE_INT_ST + need_des + 29 + 1 + read-only + + + LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ST + need_des + 30 + 1 + read-only + + + LP_ANA_BOD_MODE0_INT_ST + need_des + 31 + 1 + read-only + + + + + LP_ANA_INT_ENA + need_des + 0x28 + 0x20 + + + LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA + need_des + 27 + 1 + read-write + + + LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA + need_des + 28 + 1 + read-write + + + LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA + need_des + 29 + 1 + read-write + + + LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA + need_des + 30 + 1 + read-write + + + LP_ANA_BOD_MODE0_INT_ENA + need_des + 31 + 1 + read-write + + + + + LP_ANA_INT_CLR + need_des + 0x2C + 0x20 + + + LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR + need_des + 27 + 1 + write-only + + + LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR + need_des + 28 + 1 + write-only + + + LP_ANA_VDDBAT_UPVOLTAGE_INT_CLR + need_des + 29 + 1 + write-only + + + LP_ANA_VDDBAT_UNDERVOLTAGE_INT_CLR + need_des + 30 + 1 + write-only + + + LP_ANA_BOD_MODE0_INT_CLR + need_des + 31 + 1 + write-only + + + + + LP_ANA_LP_INT_RAW + need_des + 0x30 + 0x20 + + + LP_ANA_BOD_MODE0_LP_INT_RAW + need_des + 31 + 1 + read-write + + + + + LP_ANA_LP_INT_ST + need_des + 0x34 + 0x20 + + + LP_ANA_BOD_MODE0_LP_INT_ST + need_des + 31 + 1 + read-only + + + + + LP_ANA_LP_INT_ENA + need_des + 0x38 + 0x20 + + + LP_ANA_BOD_MODE0_LP_INT_ENA + need_des + 31 + 1 + read-write + + + + + LP_ANA_LP_INT_CLR + need_des + 0x3C + 0x20 + + + LP_ANA_BOD_MODE0_LP_INT_CLR + need_des + 31 + 1 + write-only + + + + + LP_ANA_TOUCH_APPROACH_WORK_MEAS_NUM + need_des + 0xFC + 0x20 + 0x06419064 + + + LP_ANA_TOUCH_APPROACH_MEAS_NUM2 + need_des + 0 + 10 + read-write + + + LP_ANA_TOUCH_APPROACH_MEAS_NUM1 + need_des + 10 + 10 + read-write + + + LP_ANA_TOUCH_APPROACH_MEAS_NUM0 + need_des + 20 + 10 + read-write + + + + + LP_ANA_TOUCH_SCAN_CTRL1 + need_des + 0x100 + 0x20 + 0x00080000 + + + LP_ANA_TOUCH_SHIELD_PAD_EN + need_des + 0 + 1 + read-write + + + LP_ANA_TOUCH_INACTIVE_CONNECTION + need_des + 1 + 1 + read-write + + + LP_ANA_TOUCH_SCAN_PAD_MAP + need_des + 2 + 15 + read-write + + + LP_ANA_TOUCH_XPD_WAIT + need_des + 17 + 15 + read-write + + + + + LP_ANA_TOUCH_SCAN_CTRL2 + need_des + 0x104 + 0x20 + 0x37BFFFC0 + + + LP_ANA_TOUCH_TIMEOUT_NUM + need_des + 6 + 16 + read-write + + + LP_ANA_TOUCH_TIMEOUT_EN + need_des + 22 + 1 + read-write + + + LP_ANA_TOUCH_OUT_RING + need_des + 23 + 4 + read-write + + + LP_ANA_FREQ_SCAN_EN + need_des + 27 + 1 + read-write + + + LP_ANA_FREQ_SCAN_CNT_LIMIT + need_des + 28 + 2 + read-write + + + + + LP_ANA_TOUCH_WORK + need_des + 0x108 + 0x20 + + + LP_ANA_DIV_NUM2 + need_des + 16 + 3 + read-write + + + LP_ANA_DIV_NUM1 + need_des + 19 + 3 + read-write + + + LP_ANA_DIV_NUM0 + need_des + 22 + 3 + read-write + + + LP_ANA_TOUCH_OUT_SEL + need_des + 25 + 1 + read-write + + + LP_ANA_TOUCH_OUT_RESET + need_des + 26 + 1 + write-only + + + LP_ANA_TOUCH_OUT_GATE + need_des + 27 + 1 + read-write + + + + + LP_ANA_TOUCH_WORK_MEAS_NUM + need_des + 0x10C + 0x20 + 0x06419064 + + + LP_ANA_TOUCH_MEAS_NUM2 + need_des + 0 + 10 + read-write + + + LP_ANA_TOUCH_MEAS_NUM1 + need_des + 10 + 10 + read-write + + + LP_ANA_TOUCH_MEAS_NUM0 + need_des + 20 + 10 + read-write + + + + + LP_ANA_TOUCH_FILTER1 + need_des + 0x110 + 0x20 + 0x6A0A0200 + + + LP_ANA_TOUCH_NEG_NOISE_DISUPDATE_BASELINE_EN + Reserved + 0 + 1 + read-write + + + LP_ANA_TOUCH_HYSTERESIS + need_des + 1 + 2 + read-write + + + LP_ANA_TOUCH_NEG_NOISE_THRES + need_des + 3 + 2 + read-write + + + LP_ANA_TOUCH_NOISE_THRES + need_des + 5 + 2 + read-write + + + LP_ANA_TOUCH_SMOOTH_LVL + need_des + 7 + 2 + read-write + + + LP_ANA_TOUCH_JITTER_STEP + need_des + 9 + 4 + read-write + + + LP_ANA_TOUCH_FILTER_MODE + need_des + 13 + 3 + read-write + + + LP_ANA_TOUCH_FILTER_EN + need_des + 16 + 1 + read-write + + + LP_ANA_TOUCH_NEG_NOISE_LIMIT + need_des + 17 + 4 + read-write + + + LP_ANA_TOUCH_APPROACH_LIMIT + need_des + 21 + 8 + read-write + + + LP_ANA_TOUCH_DEBOUNCE_LIMIT + need_des + 29 + 3 + read-write + + + + + LP_ANA_TOUCH_FILTER2 + need_des + 0x114 + 0x20 + 0x1FFF8000 + + + LP_ANA_TOUCH_OUTEN + need_des + 15 + 15 + read-write + + + LP_ANA_TOUCH_BYPASS_NOISE_THRES + need_des + 30 + 1 + read-write + + + LP_ANA_TOUCH_BYPASS_NEG_NOISE_THRES + need_des + 31 + 1 + read-write + + + + + LP_ANA_TOUCH_FILTER3 + need_des + 0x118 + 0x20 + + + LP_ANA_TOUCH_BASELINE_SW + need_des + 0 + 16 + read-write + + + LP_ANA_TOUCH_UPDATE_BASELINE_SW + need_des + 16 + 1 + write-only + + + + + LP_ANA_TOUCH_SLP0 + need_des + 0x11C + 0x20 + 0x001E0000 + + + LP_ANA_TOUCH_SLP_TH0 + need_des + 0 + 16 + read-write + + + LP_ANA_TOUCH_SLP_CHANNEL_CLR + need_des + 16 + 1 + write-only + + + LP_ANA_TOUCH_SLP_PAD + need_des + 17 + 4 + read-write + + + + + LP_ANA_TOUCH_SLP1 + need_des + 0x120 + 0x20 + + + LP_ANA_TOUCH_SLP_TH2 + need_des + 0 + 16 + read-write + + + LP_ANA_TOUCH_SLP_TH1 + need_des + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_CLR + need_des + 0x124 + 0x20 + + + LP_ANA_TOUCH_CHANNEL_CLR + need_des + 0 + 15 + write-only + + + LP_ANA_TOUCH_STATUS_CLR + need_des + 15 + 1 + write-only + + + + + LP_ANA_TOUCH_APPROACH + need_des + 0x128 + 0x20 + 0x00000FFF + + + PAD0 + need_des + 0 + 4 + read-write + + + PAD1 + need_des + 4 + 4 + read-write + + + PAD2 + need_des + 8 + 4 + read-write + + + LP_ANA_TOUCH_SLP_APPROACH_EN + need_des + 12 + 1 + read-write + + + + + LP_ANA_TOUCH_FREQ0_SCAN_PARA + need_des + 0x12C + 0x20 + + + LP_ANA_TOUCH_FREQ0_DCAP_LPF + need_des + 0 + 7 + read-write + + + LP_ANA_TOUCH_FREQ0_DRES_LPF + need_des + 7 + 2 + read-write + + + LP_ANA_TOUCH_FREQ0_DRV_LS + need_des + 9 + 4 + read-write + + + LP_ANA_TOUCH_FREQ0_DRV_HS + need_des + 13 + 5 + read-write + + + LP_ANA_TOUCH_FREQ0_DBIAS + need_des + 18 + 5 + read-write + + + + + LP_ANA_TOUCH_FREQ1_SCAN_PARA + need_des + 0x130 + 0x20 + + + LP_ANA_TOUCH_FREQ1_DCAP_LPF + need_des + 0 + 7 + read-write + + + LP_ANA_TOUCH_FREQ1_DRES_LPF + need_des + 7 + 2 + read-write + + + LP_ANA_TOUCH_FREQ1_DRV_LS + need_des + 9 + 4 + read-write + + + LP_ANA_TOUCH_FREQ1_DRV_HS + need_des + 13 + 5 + read-write + + + LP_ANA_TOUCH_FREQ1_DBIAS + need_des + 18 + 5 + read-write + + + + + LP_ANA_TOUCH_FREQ2_SCAN_PARA + need_des + 0x134 + 0x20 + + + LP_ANA_TOUCH_FREQ2_DCAP_LPF + need_des + 0 + 7 + read-write + + + LP_ANA_TOUCH_FREQ2_DRES_LPF + need_des + 7 + 2 + read-write + + + LP_ANA_TOUCH_FREQ2_DRV_LS + need_des + 9 + 4 + read-write + + + LP_ANA_TOUCH_FREQ2_DRV_HS + need_des + 13 + 5 + read-write + + + LP_ANA_TOUCH_FREQ2_DBIAS + need_des + 18 + 5 + read-write + + + + + LP_ANA_TOUCH_ANA_PARA + need_des + 0x138 + 0x20 + + + LP_ANA_TOUCH_TOUCH_BUF_DRV + need_des + 0 + 3 + read-write + + + LP_ANA_TOUCH_TOUCH_EN_CAL + need_des + 3 + 1 + read-write + + + LP_ANA_TOUCH_TOUCH_DCAP_CAL + need_des + 4 + 7 + read-write + + + + + LP_ANA_TOUCH_MUX0 + need_des + 0x13C + 0x20 + 0x20000000 + + + LP_ANA_TOUCH_DATA_SEL + need_des + 8 + 2 + read-write + + + LP_ANA_TOUCH_FREQ_SEL + need_des + 10 + 2 + read-write + + + LP_ANA_TOUCH_BUFSEL + need_des + 12 + 15 + read-write + + + LP_ANA_TOUCH_DONE_EN + need_des + 27 + 1 + read-write + + + LP_ANA_TOUCH_DONE_FORCE + need_des + 28 + 1 + read-write + + + LP_ANA_TOUCH_FSM_EN + need_des + 29 + 1 + read-write + + + LP_ANA_TOUCH_START_EN + need_des + 30 + 1 + read-write + + + LP_ANA_TOUCH_START_FORCE + need_des + 31 + 1 + read-write + + + + + LP_ANA_TOUCH_MUX1 + need_des + 0x140 + 0x20 + + + LP_ANA_TOUCH_START + need_des + 0 + 15 + read-write + + + LP_ANA_TOUCH_XPD + need_des + 15 + 15 + read-write + + + + + LP_ANA_TOUCH_PAD0_TH0 + need_des + 0x144 + 0x20 + + + LP_ANA_TOUCH_PAD0_TH0 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD0_TH1 + need_des + 0x148 + 0x20 + + + LP_ANA_TOUCH_PAD0_TH1 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD0_TH2 + need_des + 0x14C + 0x20 + + + LP_ANA_TOUCH_PAD0_TH2 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD1_TH0 + need_des + 0x150 + 0x20 + + + LP_ANA_TOUCH_PAD1_TH0 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD1_TH1 + need_des + 0x154 + 0x20 + + + LP_ANA_TOUCH_PAD1_TH1 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD1_TH2 + need_des + 0x158 + 0x20 + + + LP_ANA_TOUCH_PAD1_TH2 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD2_TH0 + need_des + 0x15C + 0x20 + + + LP_ANA_TOUCH_PAD2_TH0 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD2_TH1 + need_des + 0x160 + 0x20 + + + LP_ANA_TOUCH_PAD2_TH1 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD2_TH2 + need_des + 0x164 + 0x20 + + + LP_ANA_TOUCH_PAD2_TH2 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD3_TH0 + need_des + 0x168 + 0x20 + + + LP_ANA_TOUCH_PAD3_TH0 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD3_TH1 + need_des + 0x16C + 0x20 + + + LP_ANA_TOUCH_PAD3_TH1 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD3_TH2 + need_des + 0x170 + 0x20 + + + LP_ANA_TOUCH_PAD3_TH2 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD4_TH0 + need_des + 0x174 + 0x20 + + + LP_ANA_TOUCH_PAD4_TH0 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD4_TH1 + need_des + 0x178 + 0x20 + + + LP_ANA_TOUCH_PAD4_TH1 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD4_TH2 + need_des + 0x17C + 0x20 + + + LP_ANA_TOUCH_PAD4_TH2 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD5_TH0 + need_des + 0x180 + 0x20 + + + LP_ANA_TOUCH_PAD5_TH0 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD5_TH1 + need_des + 0x184 + 0x20 + + + LP_ANA_TOUCH_PAD5_TH1 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD5_TH2 + need_des + 0x188 + 0x20 + + + LP_ANA_TOUCH_PAD5_TH2 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD6_TH0 + need_des + 0x18C + 0x20 + + + LP_ANA_TOUCH_PAD6_TH0 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD6_TH1 + need_des + 0x190 + 0x20 + + + LP_ANA_TOUCH_PAD6_TH1 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD6_TH2 + need_des + 0x194 + 0x20 + + + LP_ANA_TOUCH_PAD6_TH2 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD7_TH0 + need_des + 0x198 + 0x20 + + + LP_ANA_TOUCH_PAD7_TH0 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD7_TH1 + need_des + 0x19C + 0x20 + + + LP_ANA_TOUCH_PAD7_TH1 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD7_TH2 + need_des + 0x1A0 + 0x20 + + + LP_ANA_TOUCH_PAD7_TH2 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD8_TH0 + need_des + 0x1A4 + 0x20 + + + LP_ANA_TOUCH_PAD8_TH0 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD8_TH1 + need_des + 0x1A8 + 0x20 + + + LP_ANA_TOUCH_PAD8_TH1 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD8_TH2 + need_des + 0x1AC + 0x20 + + + LP_ANA_TOUCH_PAD8_TH2 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD9_TH0 + need_des + 0x1B0 + 0x20 + + + LP_ANA_TOUCH_PAD9_TH0 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD9_TH1 + need_des + 0x1B4 + 0x20 + + + LP_ANA_TOUCH_PAD9_TH1 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD9_TH2 + need_des + 0x1B8 + 0x20 + + + LP_ANA_TOUCH_PAD9_TH2 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD10_TH0 + need_des + 0x1BC + 0x20 + + + LP_ANA_TOUCH_PAD10_TH0 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD10_TH1 + need_des + 0x1C0 + 0x20 + + + LP_ANA_TOUCH_PAD10_TH1 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD10_TH2 + need_des + 0x1C4 + 0x20 + + + LP_ANA_TOUCH_PAD10_TH2 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD11_TH0 + need_des + 0x1C8 + 0x20 + + + LP_ANA_TOUCH_PAD11_TH0 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD11_TH1 + need_des + 0x1CC + 0x20 + + + LP_ANA_TOUCH_PAD11_TH1 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD11_TH2 + need_des + 0x1D0 + 0x20 + + + LP_ANA_TOUCH_PAD11_TH2 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD12_TH0 + need_des + 0x1D4 + 0x20 + + + LP_ANA_TOUCH_PAD12_TH0 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD12_TH1 + need_des + 0x1D8 + 0x20 + + + LP_ANA_TOUCH_PAD12_TH1 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD12_TH2 + need_des + 0x1DC + 0x20 + + + LP_ANA_TOUCH_PAD12_TH2 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD13_TH0 + need_des + 0x1E0 + 0x20 + + + LP_ANA_TOUCH_PAD13_TH0 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD13_TH1 + need_des + 0x1E4 + 0x20 + + + LP_ANA_TOUCH_PAD13_TH1 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD13_TH2 + need_des + 0x1E8 + 0x20 + + + LP_ANA_TOUCH_PAD13_TH2 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD14_TH0 + need_des + 0x1EC + 0x20 + + + LP_ANA_TOUCH_PAD14_TH0 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD14_TH1 + need_des + 0x1F0 + 0x20 + + + LP_ANA_TOUCH_PAD14_TH1 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD14_TH2 + need_des + 0x1F4 + 0x20 + + + LP_ANA_TOUCH_PAD14_TH2 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_DATE + need_des + 0x3FC + 0x20 + 0x00230420 + + + LP_ANA_LP_ANA_DATE + need_des + 0 + 31 + read-write + + + LP_ANA_CLK_EN + need_des + 31 + 1 + read-write + + + + + + + LP_AON_CLKRST + LP_AON_CLKRST Peripheral + LP_AON_CLKRST + 0x50111000 + + 0x0 + 0x54 + registers + + + + LP_AONCLKRST_LP_CLK_CONF + need_des + 0x0 + 0x20 + 0x00000004 + + + LP_AONCLKRST_SLOW_CLK_SEL + need_des + 0 + 2 + read-write + + + LP_AONCLKRST_FAST_CLK_SEL + need_des + 2 + 2 + read-write + + + LP_AONCLKRST_LP_PERI_DIV_NUM + need_des + 4 + 6 + read-write + + + LP_AONCLKRST_ANA_SEL_REF_PLL8M + need_des + 10 + 1 + read-write + + + + + LP_AONCLKRST_LP_CLK_PO_EN + need_des + 0x4 + 0x20 + + + LP_AONCLKRST_CLK_CORE_EFUSE_OEN + need_des + 0 + 1 + read-write + + + LP_AONCLKRST_CLK_LP_BUS_OEN + need_des + 1 + 1 + read-write + + + LP_AONCLKRST_CLK_AON_SLOW_OEN + need_des + 2 + 1 + read-write + + + LP_AONCLKRST_CLK_AON_FAST_OEN + need_des + 3 + 1 + read-write + + + LP_AONCLKRST_CLK_SLOW_OEN + need_des + 4 + 1 + read-write + + + LP_AONCLKRST_CLK_FAST_OEN + need_des + 5 + 1 + read-write + + + LP_AONCLKRST_CLK_FOSC_OEN + need_des + 6 + 1 + read-write + + + LP_AONCLKRST_CLK_RC32K_OEN + need_des + 7 + 1 + read-write + + + LP_AONCLKRST_CLK_SXTAL_OEN + need_des + 8 + 1 + read-write + + + LP_AONCLKRST_CLK_SOSC_OEN + 1'b1: probe sosc clk on +1'b0: probe sosc clk off + 9 + 1 + read-write + + + + + LP_AONCLKRST_LP_CLK_EN + need_des + 0x8 + 0x20 + 0x08000000 + + + LP_AONCLKRST_LP_RTC_XTAL_FORCE_ON + need_des + 26 + 1 + read-write + + + LP_AONCLKRST_CK_EN_LP_RAM + need_des + 27 + 1 + read-write + + + LP_AONCLKRST_ETM_EVENT_TICK_EN + need_des + 28 + 1 + read-write + + + LP_AONCLKRST_PLL8M_CLK_FORCE_ON + need_des + 29 + 1 + read-write + + + LP_AONCLKRST_XTAL_CLK_FORCE_ON + need_des + 30 + 1 + read-write + + + LP_AONCLKRST_FOSC_CLK_FORCE_ON + need_des + 31 + 1 + read-write + + + + + LP_AONCLKRST_LP_RST_EN + need_des + 0xC + 0x20 + + + LP_AONCLKRST_RST_EN_LP_HUK + need_des + 24 + 1 + read-write + + + LP_AONCLKRST_RST_EN_LP_ANAPERI + need_des + 25 + 1 + read-write + + + LP_AONCLKRST_RST_EN_LP_WDT + need_des + 26 + 1 + read-write + + + LP_AONCLKRST_RST_EN_LP_TIMER + need_des + 27 + 1 + read-write + + + LP_AONCLKRST_RST_EN_LP_RTC + need_des + 28 + 1 + read-write + + + LP_AONCLKRST_RST_EN_LP_MAILBOX + need_des + 29 + 1 + read-write + + + LP_AONCLKRST_RST_EN_LP_AONEFUSEREG + need_des + 30 + 1 + read-write + + + LP_AONCLKRST_RST_EN_LP_RAM + need_des + 31 + 1 + read-write + + + + + LP_AONCLKRST_RESET_CAUSE + need_des + 0x10 + 0x20 + 0x02000000 + + + LP_AONCLKRST_LPCORE_RESET_CAUSE + 6'h1: POR reset +6'h9: PMU LP PERI power down reset +6'ha: PMU LP CPU reset +6'hf: brown out reset +6'h10: LP watchdog chip reset +6'h12: super watch dog reset +6'h13: glitch reset +6'h14: software reset + 0 + 6 + read-only + + + LP_AONCLKRST_LPCORE_RESET_FLAG + need_des + 6 + 1 + read-only + + + LP_AONCLKRST_HPCORE0_RESET_CAUSE + 6'h1: POR reset +6'h3: digital system software reset +6'h5: PMU HP system power down reset +6'h7: HP system reset from HP watchdog +6'h9: HP system reset from LP watchdog +6'hb: HP core reset from HP watchdog +6'hc: HP core software reset +6'hd: HP core reset from LP watchdog +6'hf: brown out reset +6'h10: LP watchdog chip reset +6'h12: super watch dog reset +6'h13: glitch reset +6'h14: efuse crc error reset +6'h16: HP usb jtag chip reset +6'h17: HP usb uart chip reset +6'h18: HP jtag reset +6'h1a: HP core lockup + 7 + 6 + read-only + + + LP_AONCLKRST_HPCORE0_RESET_FLAG + need_des + 13 + 1 + read-only + + + LP_AONCLKRST_HPCORE1_RESET_CAUSE + 6'h1: POR reset +6'h3: digital system software reset +6'h5: PMU HP system power down reset +6'h7: HP system reset from HP watchdog +6'h9: HP system reset from LP watchdog +6'hb: HP core reset from HP watchdog +6'hc: HP core software reset +6'hd: HP core reset from LP watchdog +6'hf: brown out reset +6'h10: LP watchdog chip reset +6'h12: super watch dog reset +6'h13: glitch reset +6'h14: efuse crc error reset +6'h16: HP usb jtag chip reset +6'h17: HP usb uart chip reset +6'h18: HP jtag reset +6'h1a: HP core lockup + 14 + 6 + read-only + + + LP_AONCLKRST_HPCORE1_RESET_FLAG + need_des + 20 + 1 + read-only + + + LP_AONCLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK + 1'b0: enable lpcore pmu_lp_cpu_reset reset_cause, 1'b1: disable lpcore pmu_lp_cpu_reset reset_cause + 25 + 1 + read-write + + + LP_AONCLKRST_LPCORE_RESET_CAUSE_CLR + need_des + 26 + 1 + write-only + + + LP_AONCLKRST_LPCORE_RESET_FLAG_CLR + need_des + 27 + 1 + write-only + + + LP_AONCLKRST_HPCORE0_RESET_CAUSE_CLR + need_des + 28 + 1 + write-only + + + LP_AONCLKRST_HPCORE0_RESET_FLAG_CLR + need_des + 29 + 1 + write-only + + + LP_AONCLKRST_HPCORE1_RESET_CAUSE_CLR + need_des + 30 + 1 + write-only + + + LP_AONCLKRST_HPCORE1_RESET_FLAG_CLR + need_des + 31 + 1 + write-only + + + + + LP_AONCLKRST_HPCPU_RESET_CTRL0 + need_des + 0x14 + 0x20 + 0x80028002 + + + LP_AONCLKRST_HPCORE0_LOCKUP_RESET_EN + write 1 to enable hpcore0 lockup reset feature, write 0 to disable hpcore0 lockup reset feature + 0 + 1 + read-write + + + LP_AONCLKRST_LP_WDT_HPCORE0_RESET_LENGTH + need_des + 1 + 3 + read-write + + + LP_AONCLKRST_LP_WDT_HPCORE0_RESET_EN + write 1 to enable lp_wdt reset hpcore0 feature, write 0 to disable lp_wdt reset hpcore0 feature + 4 + 1 + read-write + + + LP_AONCLKRST_HPCORE0_STALL_WAIT + need_des + 5 + 7 + read-write + + + LP_AONCLKRST_HPCORE0_STALL_EN + need_des + 12 + 1 + read-write + + + LP_AONCLKRST_HPCORE0_SW_RESET + need_des + 13 + 1 + write-only + + + LP_AONCLKRST_HPCORE0_OCD_HALT_ON_RESET + need_des + 14 + 1 + read-write + + + LP_AONCLKRST_HPCORE0_STAT_VECTOR_SEL + 1'b1: boot from HP TCM ROM: 0x4FC00000 +1'b0: boot from LP TCM RAM: 0x50108000 + 15 + 1 + read-write + + + LP_AONCLKRST_HPCORE1_LOCKUP_RESET_EN + write 1 to enable hpcore1 lockup reset feature, write 0 to disable hpcore1 lockup reset feature + 16 + 1 + read-write + + + LP_AONCLKRST_LP_WDT_HPCORE1_RESET_LENGTH + need_des + 17 + 3 + read-write + + + LP_AONCLKRST_LP_WDT_HPCORE1_RESET_EN + write 1 to enable lp_wdt reset hpcore1 feature, write 0 to disable lp_wdt reset hpcore1 feature + 20 + 1 + read-write + + + LP_AONCLKRST_HPCORE1_STALL_WAIT + need_des + 21 + 7 + read-write + + + LP_AONCLKRST_HPCORE1_STALL_EN + need_des + 28 + 1 + read-write + + + LP_AONCLKRST_HPCORE1_SW_RESET + need_des + 29 + 1 + write-only + + + LP_AONCLKRST_HPCORE1_OCD_HALT_ON_RESET + need_des + 30 + 1 + read-write + + + LP_AONCLKRST_HPCORE1_STAT_VECTOR_SEL + 1'b1: boot from HP TCM ROM: 0x4FC00000 +1'b0: boot from LP TCM RAM: 0x50108000 + 31 + 1 + read-write + + + + + LP_AONCLKRST_HPCPU_RESET_CTRL1 + need_des + 0x18 + 0x20 + + + LP_AONCLKRST_HPCORE0_SW_STALL_CODE + HP core0 software stall when set to 8'h86 + 16 + 8 + read-write + + + LP_AONCLKRST_HPCORE1_SW_STALL_CODE + HP core1 software stall when set to 8'h86 + 24 + 8 + read-write + + + + + LP_AONCLKRST_FOSC_CNTL + need_des + 0x1C + 0x20 + 0x64000000 + + + LP_AONCLKRST_FOSC_DFREQ + need_des + 22 + 10 + read-write + + + + + LP_AONCLKRST_RC32K_CNTL + need_des + 0x20 + 0x20 + 0x0000028A + + + LP_AONCLKRST_RC32K_DFREQ + need_des + 0 + 32 + read-write + + + + + LP_AONCLKRST_SOSC_CNTL + need_des + 0x24 + 0x20 + 0x2B000000 + + + LP_AONCLKRST_SOSC_DFREQ + need_des + 22 + 10 + read-write + + + + + LP_AONCLKRST_CLK_TO_HP + need_des + 0x28 + 0x20 + 0xF0000000 + + + LP_AONCLKRST_ICG_HP_XTAL32K + reserved + 28 + 1 + read-write + + + LP_AONCLKRST_ICG_HP_SOSC + reserved + 29 + 1 + read-write + + + LP_AONCLKRST_ICG_HP_OSC32K + reserved + 30 + 1 + read-write + + + LP_AONCLKRST_ICG_HP_FOSC + reserved + 31 + 1 + read-write + + + + + LP_AONCLKRST_LPMEM_FORCE + need_des + 0x2C + 0x20 + + + LP_AONCLKRST_LPMEM_CLK_FORCE_ON + reserved + 31 + 1 + read-write + + + + + LP_AONCLKRST_XTAL32K + need_des + 0x30 + 0x20 + 0x66C00000 + + + LP_AONCLKRST_DRES_XTAL32K + need_des + 22 + 3 + read-write + + + LP_AONCLKRST_DGM_XTAL32K + need_des + 25 + 3 + read-write + + + LP_AONCLKRST_DBUF_XTAL32K + need_des + 28 + 1 + read-write + + + LP_AONCLKRST_DAC_XTAL32K + need_des + 29 + 3 + read-write + + + + + LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS + need_des + 0x34 + 0x20 + 0xFFFFFFFF + + + LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS + reserved + 0 + 32 + read-write + + + + + LP_AONCLKRST_HPSYS_0_RESET_BYPASS + need_des + 0x38 + 0x20 + 0xFFFFFFFF + + + LP_AONCLKRST_HPSYS_0_RESET_BYPASS + reserved + 0 + 32 + read-write + + + + + LP_AONCLKRST_HPSYS_APM_RESET_BYPASS + need_des + 0x3C + 0x20 + 0xFFFFFFFF + + + LP_AONCLKRST_HPSYS_APM_RESET_BYPASS + reserved + 0 + 32 + read-write + + + + + LP_AONCLKRST_HP_CLK_CTRL + HP Clock Control Register. + 0x40 + 0x20 + 0x1FFFFFFC + + + LP_AONCLKRST_HP_ROOT_CLK_SRC_SEL + HP SoC Root Clock Source Select. 2'd0: xtal_40m, 2'd1: cpll_400m, 2'd2: fosc_20m. + 0 + 2 + read-write + + + LP_AONCLKRST_HP_ROOT_CLK_EN + HP SoC Root Clock Enable. + 2 + 1 + read-write + + + LP_AONCLKRST_HP_PAD_PARLIO_TX_CLK_EN + PARLIO TX Clock From Pad Enable. + 3 + 1 + read-write + + + LP_AONCLKRST_HP_PAD_PARLIO_RX_CLK_EN + PARLIO RX Clock From Pad Enable. + 4 + 1 + read-write + + + LP_AONCLKRST_HP_PAD_UART4_SLP_CLK_EN + UART4 SLP Clock From Pad Enable. + 5 + 1 + read-write + + + LP_AONCLKRST_HP_PAD_UART3_SLP_CLK_EN + UART3 SLP Clock From Pad Enable. + 6 + 1 + read-write + + + LP_AONCLKRST_HP_PAD_UART2_SLP_CLK_EN + UART2 SLP Clock From Pad Enable. + 7 + 1 + read-write + + + LP_AONCLKRST_HP_PAD_UART1_SLP_CLK_EN + UART1 SLP Clock From Pad Enable. + 8 + 1 + read-write + + + LP_AONCLKRST_HP_PAD_UART0_SLP_CLK_EN + UART0 SLP Clock From Pad Enable. + 9 + 1 + read-write + + + LP_AONCLKRST_HP_PAD_I2S2_MCLK_EN + I2S2 MCLK Clock From Pad Enable. + 10 + 1 + read-write + + + LP_AONCLKRST_HP_PAD_I2S1_MCLK_EN + I2S1 MCLK Clock From Pad Enable. + 11 + 1 + read-write + + + LP_AONCLKRST_HP_PAD_I2S0_MCLK_EN + I2S0 MCLK Clock From Pad Enable. + 12 + 1 + read-write + + + LP_AONCLKRST_HP_PAD_EMAC_TX_CLK_EN + EMAC RX Clock From Pad Enable. + 13 + 1 + read-write + + + LP_AONCLKRST_HP_PAD_EMAC_RX_CLK_EN + EMAC TX Clock From Pad Enable. + 14 + 1 + read-write + + + LP_AONCLKRST_HP_PAD_EMAC_TXRX_CLK_EN + EMAC TXRX Clock From Pad Enable. + 15 + 1 + read-write + + + LP_AONCLKRST_HP_XTAL_32K_CLK_EN + XTAL 32K Clock Enable. + 16 + 1 + read-write + + + LP_AONCLKRST_HP_RC_32K_CLK_EN + RC 32K Clock Enable. + 17 + 1 + read-write + + + LP_AONCLKRST_HP_SOSC_150K_CLK_EN + SOSC 150K Clock Enable. + 18 + 1 + read-write + + + LP_AONCLKRST_HP_PLL_8M_CLK_EN + PLL 8M Clock Enable. + 19 + 1 + read-write + + + LP_AONCLKRST_HP_AUDIO_PLL_CLK_EN + AUDIO PLL Clock Enable. + 20 + 1 + read-write + + + LP_AONCLKRST_HP_SDIO_PLL2_CLK_EN + SDIO PLL2 Clock Enable. + 21 + 1 + read-write + + + LP_AONCLKRST_HP_SDIO_PLL1_CLK_EN + SDIO PLL1 Clock Enable. + 22 + 1 + read-write + + + LP_AONCLKRST_HP_SDIO_PLL0_CLK_EN + SDIO PLL0 Clock Enable. + 23 + 1 + read-write + + + LP_AONCLKRST_HP_FOSC_20M_CLK_EN + FOSC 20M Clock Enable. + 24 + 1 + read-write + + + LP_AONCLKRST_HP_XTAL_40M_CLK_EN + XTAL 40M Clock Enalbe. + 25 + 1 + read-write + + + LP_AONCLKRST_HP_CPLL_400M_CLK_EN + CPLL 400M Clock Enable. + 26 + 1 + read-write + + + LP_AONCLKRST_HP_SPLL_480M_CLK_EN + SPLL 480M Clock Enable. + 27 + 1 + read-write + + + LP_AONCLKRST_HP_MPLL_500M_CLK_EN + MPLL 500M Clock Enable. + 28 + 1 + read-write + + + + + LP_AONCLKRST_HP_USB_CLKRST_CTRL0 + HP USB Clock Reset Control Register. + 0x44 + 0x20 + 0x09C4C27A + + + LP_AONCLKRST_USB_OTG20_SLEEP_MODE + unused. + 0 + 1 + read-write + + + LP_AONCLKRST_USB_OTG20_BK_SYS_CLK_EN + unused. + 1 + 1 + read-write + + + LP_AONCLKRST_USB_OTG11_SLEEP_MODE + unused. + 2 + 1 + read-write + + + LP_AONCLKRST_USB_OTG11_BK_SYS_CLK_EN + unused. + 3 + 1 + read-write + + + LP_AONCLKRST_USB_OTG11_48M_CLK_EN + usb otg11 fs phy clock enable. + 4 + 1 + read-write + + + LP_AONCLKRST_USB_DEVICE_48M_CLK_EN + usb device fs phy clock enable. + 5 + 1 + read-write + + + LP_AONCLKRST_USB_48M_DIV_NUM + usb 480m to 25m divide number. + 6 + 8 + read-write + + + LP_AONCLKRST_USB_25M_DIV_NUM + usb 500m to 25m divide number. + 14 + 8 + read-write + + + LP_AONCLKRST_USB_12M_DIV_NUM + usb 480m to 12m divide number. + 22 + 8 + read-write + + + + + LP_AONCLKRST_HP_USB_CLKRST_CTRL1 + HP USB Clock Reset Control Register. + 0x48 + 0x20 + 0xC0000000 + + + LP_AONCLKRST_RST_EN_USB_OTG20_ADP + usb otg20 adp reset en + 0 + 1 + read-write + + + LP_AONCLKRST_RST_EN_USB_OTG20_PHY + usb otg20 phy reset en + 1 + 1 + read-write + + + LP_AONCLKRST_RST_EN_USB_OTG20 + usb otg20 reset en + 2 + 1 + read-write + + + LP_AONCLKRST_RST_EN_USB_OTG11 + usb org11 reset en + 3 + 1 + read-write + + + LP_AONCLKRST_RST_EN_USB_DEVICE + usb device reset en + 4 + 1 + read-write + + + LP_AONCLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL + usb otg20 hs phy src sel. 2'd0: 12m, 2'd1: 25m, 2'd2: pad_hsphy_refclk. + 28 + 2 + read-write + + + LP_AONCLKRST_USB_OTG20_PHYREF_CLK_EN + usb otg20 hs phy refclk enable. + 30 + 1 + read-write + + + LP_AONCLKRST_USB_OTG20_ULPI_CLK_EN + usb otg20 ulpi clock enable. + 31 + 1 + read-write + + + + + LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL + need_des + 0x4C + 0x20 + + + LP_AONCLKRST_RST_EN_SDMMC + hp sdmmc reset en + 28 + 1 + read-write + + + LP_AONCLKRST_FORCE_NORST_SDMMC + hp sdmmc force norst + 29 + 1 + read-write + + + LP_AONCLKRST_RST_EN_EMAC + hp emac reset en + 30 + 1 + read-write + + + LP_AONCLKRST_FORCE_NORST_EMAC + hp emac force norst + 31 + 1 + read-write + + + + + LP_AONCLKRST_DATE + need_des + 0x3FC + 0x20 + + + LP_AONCLKRST_CLK_EN + need_des + 31 + 1 + read-write + + + + + + + LP_GPIO + Low-power General Purpose Input/Output + LP_GPIO + 0x5012A000 + + 0x0 + 0xEC + registers + + + LP_GPIO + 10 + + + + CLK_EN + Reserved + 0x0 + 0x20 + 0x00000001 + + + REG_CLK_EN + Reserved + 0 + 1 + read-write + + + + + VER_DATE + Reserved + 0x4 + 0x20 + 0x00230323 + + + REG_VER_DATE + Reserved + 0 + 28 + read-write + + + + + OUT + Reserved + 0x8 + 0x20 + + + REG_GPIO_OUT_DATA + Reserved + 0 + 16 + read-write + + + + + OUT_W1TS + Reserved + 0xC + 0x20 + + + REG_GPIO_OUT_DATA_W1TS + Reserved + 0 + 16 + write-only + + + + + OUT_W1TC + Reserved + 0x10 + 0x20 + + + REG_GPIO_OUT_DATA_W1TC + Reserved + 0 + 16 + write-only + + + + + ENABLE + Reserved + 0x14 + 0x20 + + + REG_GPIO_ENABLE_DATA + Reserved + 0 + 16 + read-write + + + + + ENABLE_W1TS + Reserved + 0x18 + 0x20 + + + REG_GPIO_ENABLE_DATA_W1TS + Reserved + 0 + 16 + write-only + + + + + ENABLE_W1TC + Reserved + 0x1C + 0x20 + + + REG_GPIO_ENABLE_DATA_W1TC + Reserved + 0 + 16 + write-only + + + + + STATUS + Reserved + 0x20 + 0x20 + + + REG_GPIO_STATUS_DATA + Reserved + 0 + 16 + read-write + + + + + STATUS_W1TS + Reserved + 0x24 + 0x20 + + + REG_GPIO_STATUS_DATA_W1TS + Reserved + 0 + 16 + write-only + + + + + STATUS_W1TC + Reserved + 0x28 + 0x20 + + + REG_GPIO_STATUS_DATA_W1TC + Reserved + 0 + 16 + write-only + + + + + STATUS_NEXT + Reserved + 0x2C + 0x20 + + + REG_GPIO_STATUS_INTERRUPT_NEXT + Reserved + 0 + 16 + read-only + + + + + IN + Reserved + 0x30 + 0x20 + + + REG_GPIO_IN_DATA_NEXT + Reserved + 0 + 16 + read-only + + + + + PIN0 + Reserved + 0x34 + 0x20 + + + REG_GPIO_PIN0_WAKEUP_ENABLE + Reserved + 0 + 1 + read-write + + + REG_GPIO_PIN0_INT_TYPE + Reserved + 1 + 3 + read-write + + + REG_GPIO_PIN0_PAD_DRIVER + Reserved + 4 + 1 + read-write + + + REG_GPIO_PIN0_EDGE_WAKEUP_CLR + need des + 5 + 1 + write-only + + + + + PIN1 + Reserved + 0x38 + 0x20 + + + REG_GPIO_PIN1_WAKEUP_ENABLE + Reserved + 0 + 1 + read-write + + + REG_GPIO_PIN1_INT_TYPE + Reserved + 1 + 3 + read-write + + + REG_GPIO_PIN1_PAD_DRIVER + Reserved + 4 + 1 + read-write + + + REG_GPI1_PIN0_EDGE_WAKEUP_CLR + need des + 5 + 1 + write-only + + + + + PIN2 + Reserved + 0x3C + 0x20 + + + REG_GPIO_PIN2_WAKEUP_ENABLE + Reserved + 0 + 1 + read-write + + + REG_GPIO_PIN2_INT_TYPE + Reserved + 1 + 3 + read-write + + + REG_GPIO_PIN2_PAD_DRIVER + Reserved + 4 + 1 + read-write + + + REG_GPI2_PIN0_EDGE_WAKEUP_CLR + need des + 5 + 1 + write-only + + + + + PIN3 + Reserved + 0x40 + 0x20 + + + REG_GPIO_PIN3_WAKEUP_ENABLE + Reserved + 0 + 1 + read-write + + + REG_GPIO_PIN3_INT_TYPE + Reserved + 1 + 3 + read-write + + + REG_GPIO_PIN3_PAD_DRIVER + Reserved + 4 + 1 + read-write + + + REG_GPI3_PIN0_EDGE_WAKEUP_CLR + need des + 5 + 1 + write-only + + + + + PIN4 + Reserved + 0x44 + 0x20 + + + REG_GPIO_PIN4_WAKEUP_ENABLE + Reserved + 0 + 1 + read-write + + + REG_GPIO_PIN4_INT_TYPE + Reserved + 1 + 3 + read-write + + + REG_GPIO_PIN4_PAD_DRIVER + Reserved + 4 + 1 + read-write + + + REG_GPI4_PIN0_EDGE_WAKEUP_CLR + need des + 5 + 1 + write-only + + + + + PIN5 + Reserved + 0x48 + 0x20 + + + REG_GPIO_PIN5_WAKEUP_ENABLE + Reserved + 0 + 1 + read-write + + + REG_GPIO_PIN5_INT_TYPE + Reserved + 1 + 3 + read-write + + + REG_GPIO_PIN5_PAD_DRIVER + Reserved + 4 + 1 + read-write + + + REG_GPI5_PIN0_EDGE_WAKEUP_CLR + need des + 5 + 1 + write-only + + + + + PIN6 + Reserved + 0x4C + 0x20 + + + REG_GPIO_PIN6_WAKEUP_ENABLE + Reserved + 0 + 1 + read-write + + + REG_GPIO_PIN6_INT_TYPE + Reserved + 1 + 3 + read-write + + + REG_GPIO_PIN6_PAD_DRIVER + Reserved + 4 + 1 + read-write + + + REG_GPI6_PIN0_EDGE_WAKEUP_CLR + need des + 5 + 1 + write-only + + + + + PIN7 + Reserved + 0x50 + 0x20 + + + REG_GPIO_PIN7_WAKEUP_ENABLE + Reserved + 0 + 1 + read-write + + + REG_GPIO_PIN7_INT_TYPE + Reserved + 1 + 3 + read-write + + + REG_GPIO_PIN7_PAD_DRIVER + Reserved + 4 + 1 + read-write + + + REG_GPI7_PIN0_EDGE_WAKEUP_CLR + need des + 5 + 1 + write-only + + + + + PIN8 + Reserved + 0x54 + 0x20 + + + REG_GPIO_PIN8_WAKEUP_ENABLE + Reserved + 0 + 1 + read-write + + + REG_GPIO_PIN8_INT_TYPE + Reserved + 1 + 3 + read-write + + + REG_GPIO_PIN8_PAD_DRIVER + Reserved + 4 + 1 + read-write + + + REG_GPI8_PIN0_EDGE_WAKEUP_CLR + need des + 5 + 1 + write-only + + + + + PIN9 + Reserved + 0x58 + 0x20 + + + REG_GPIO_PIN9_WAKEUP_ENABLE + Reserved + 0 + 1 + read-write + + + REG_GPIO_PIN9_INT_TYPE + Reserved + 1 + 3 + read-write + + + REG_GPIO_PIN9_PAD_DRIVER + Reserved + 4 + 1 + read-write + + + REG_GPI9_PIN0_EDGE_WAKEUP_CLR + need des + 5 + 1 + write-only + + + + + PIN10 + Reserved + 0x5C + 0x20 + + + REG_GPIO_PIN10_WAKEUP_ENABLE + Reserved + 0 + 1 + read-write + + + REG_GPIO_PIN10_INT_TYPE + Reserved + 1 + 3 + read-write + + + REG_GPIO_PIN10_PAD_DRIVER + Reserved + 4 + 1 + read-write + + + REG_GPI10_PIN0_EDGE_WAKEUP_CLR + need des + 5 + 1 + write-only + + + + + PIN11 + Reserved + 0x60 + 0x20 + + + REG_GPIO_PIN11_WAKEUP_ENABLE + Reserved + 0 + 1 + read-write + + + REG_GPIO_PIN11_INT_TYPE + Reserved + 1 + 3 + read-write + + + REG_GPIO_PIN11_PAD_DRIVER + Reserved + 4 + 1 + read-write + + + REG_GPI11_PIN0_EDGE_WAKEUP_CLR + need des + 5 + 1 + write-only + + + + + PIN12 + Reserved + 0x64 + 0x20 + + + REG_GPIO_PIN12_WAKEUP_ENABLE + Reserved + 0 + 1 + read-write + + + REG_GPIO_PIN12_INT_TYPE + Reserved + 1 + 3 + read-write + + + REG_GPIO_PIN12_PAD_DRIVER + Reserved + 4 + 1 + read-write + + + REG_GPI12_PIN0_EDGE_WAKEUP_CLR + need des + 5 + 1 + write-only + + + + + PIN13 + Reserved + 0x68 + 0x20 + + + REG_GPIO_PIN13_WAKEUP_ENABLE + Reserved + 0 + 1 + read-write + + + REG_GPIO_PIN13_INT_TYPE + Reserved + 1 + 3 + read-write + + + REG_GPIO_PIN13_PAD_DRIVER + Reserved + 4 + 1 + read-write + + + REG_GPI13_PIN0_EDGE_WAKEUP_CLR + need des + 5 + 1 + write-only + + + + + PIN14 + Reserved + 0x6C + 0x20 + + + REG_GPIO_PIN14_WAKEUP_ENABLE + Reserved + 0 + 1 + read-write + + + REG_GPIO_PIN14_INT_TYPE + Reserved + 1 + 3 + read-write + + + REG_GPIO_PIN14_PAD_DRIVER + Reserved + 4 + 1 + read-write + + + REG_GPI14_PIN0_EDGE_WAKEUP_CLR + need des + 5 + 1 + write-only + + + + + PIN15 + Reserved + 0x70 + 0x20 + + + REG_GPIO_PIN15_WAKEUP_ENABLE + Reserved + 0 + 1 + read-write + + + REG_GPIO_PIN15_INT_TYPE + Reserved + 1 + 3 + read-write + + + REG_GPIO_PIN15_PAD_DRIVER + Reserved + 4 + 1 + read-write + + + REG_GPI15_PIN0_EDGE_WAKEUP_CLR + need des + 5 + 1 + write-only + + + + + FUNC0_IN_SEL_CFG + Reserved + 0x74 + 0x20 + 0x000000C0 + + + REG_GPIO_FUNC0_IN_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_SIG0_IN_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC0_IN_SEL + reg_gpio_func0_in_sel[5:4]==2'b11->constant 1,reg_gpio_func0_in_sel[5:4]==2'b10->constant 0 + 2 + 6 + read-write + + + + + FUNC1_IN_SEL_CFG + Reserved + 0x78 + 0x20 + 0x000000C0 + + + REG_GPIO_FUNC1_IN_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_SIG1_IN_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC1_IN_SEL + Reserved + 2 + 6 + read-write + + + + + FUNC2_IN_SEL_CFG + Reserved + 0x7C + 0x20 + 0x00000080 + + + REG_GPIO_FUNC2_IN_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_SIG2_IN_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC2_IN_SEL + Reserved + 2 + 6 + read-write + + + + + FUNC3_IN_SEL_CFG + Reserved + 0x80 + 0x20 + 0x000000C0 + + + REG_GPIO_FUNC3_IN_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_SIG3_IN_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC3_IN_SEL + Reserved + 2 + 6 + read-write + + + + + FUNC4_IN_SEL_CFG + Reserved + 0x84 + 0x20 + 0x000000C0 + + + REG_GPIO_FUNC4_IN_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_SIG4_IN_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC4_IN_SEL + Reserved + 2 + 6 + read-write + + + + + FUNC5_IN_SEL_CFG + Reserved + 0x88 + 0x20 + 0x00000080 + + + REG_GPIO_FUNC5_IN_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_SIG5_IN_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC5_IN_SEL + Reserved + 2 + 6 + read-write + + + + + FUNC6_IN_SEL_CFG + Reserved + 0x8C + 0x20 + 0x00000080 + + + REG_GPIO_FUNC6_IN_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_SIG6_IN_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC6_IN_SEL + Reserved + 2 + 6 + read-write + + + + + FUNC7_IN_SEL_CFG + Reserved + 0x90 + 0x20 + 0x00000080 + + + REG_GPIO_FUNC7_IN_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_SIG7_IN_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC7_IN_SEL + Reserved + 2 + 6 + read-write + + + + + FUNC8_IN_SEL_CFG + Reserved + 0x94 + 0x20 + 0x00000080 + + + REG_GPIO_FUNC8_IN_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_SIG8_IN_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC8_IN_SEL + Reserved + 2 + 6 + read-write + + + + + FUNC9_IN_SEL_CFG + Reserved + 0x98 + 0x20 + 0x00000080 + + + REG_GPIO_FUNC9_IN_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_SIG9_IN_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC9_IN_SEL + Reserved + 2 + 6 + read-write + + + + + FUNC10_IN_SEL_CFG + Reserved + 0x9C + 0x20 + 0x00000080 + + + REG_GPIO_FUNC10_IN_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_SIG10_IN_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC10_IN_SEL + Reserved + 2 + 6 + read-write + + + + + FUNC11_IN_SEL_CFG + Reserved + 0xA0 + 0x20 + 0x00000080 + + + REG_GPIO_FUNC11_IN_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_SIG11_IN_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC11_IN_SEL + Reserved + 2 + 6 + read-write + + + + + FUNC12_IN_SEL_CFG + Reserved + 0xA4 + 0x20 + 0x00000080 + + + REG_GPIO_FUNC12_IN_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_SIG12_IN_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC12_IN_SEL + Reserved + 2 + 6 + read-write + + + + + FUNC13_IN_SEL_CFG + Reserved + 0xA8 + 0x20 + 0x00000080 + + + REG_GPIO_FUNC13_IN_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_SIG13_IN_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC13_IN_SEL + Reserved + 2 + 6 + read-write + + + + + FUNC0_OUT_SEL_CFG + Reserved + 0xF4 + 0x20 + 0x00000100 + + + REG_GPIO_FUNC0_OE_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_FUNC0_OE_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC0_OUT_INV_SEL + Reserved + 2 + 1 + read-write + + + REG_GPIO_FUNC0_OUT_SEL + reg_gpio_func0_out_sel[5:1]==16 -> output gpio register value to pad + 3 + 6 + read-write + + + + + FUNC1_OUT_SEL_CFG + Reserved + 0xF8 + 0x20 + 0x00000100 + + + REG_GPIO_FUNC1_OE_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_FUNC1_OE_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC1_OUT_INV_SEL + Reserved + 2 + 1 + read-write + + + REG_GPIO_FUNC1_OUT_SEL + Reserved + 3 + 6 + read-write + + + + + FUNC2_OUT_SEL_CFG + Reserved + 0xFC + 0x20 + 0x00000100 + + + REG_GPIO_FUNC2_OE_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_FUNC2_OE_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC2_OUT_INV_SEL + Reserved + 2 + 1 + read-write + + + REG_GPIO_FUNC2_OUT_SEL + Reserved + 3 + 6 + read-write + + + + + FUNC3_OUT_SEL_CFG + Reserved + 0x100 + 0x20 + 0x00000100 + + + REG_GPIO_FUNC3_OE_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_FUNC3_OE_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC3_OUT_INV_SEL + Reserved + 2 + 1 + read-write + + + REG_GPIO_FUNC3_OUT_SEL + Reserved + 3 + 6 + read-write + + + + + FUNC4_OUT_SEL_CFG + Reserved + 0x104 + 0x20 + 0x00000100 + + + REG_GPIO_FUNC4_OE_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_FUNC4_OE_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC4_OUT_INV_SEL + Reserved + 2 + 1 + read-write + + + REG_GPIO_FUNC4_OUT_SEL + Reserved + 3 + 6 + read-write + + + + + FUNC5_OUT_SEL_CFG + Reserved + 0x108 + 0x20 + 0x00000100 + + + REG_GPIO_FUNC5_OE_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_FUNC5_OE_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC5_OUT_INV_SEL + Reserved + 2 + 1 + read-write + + + REG_GPIO_FUNC5_OUT_SEL + Reserved + 3 + 6 + read-write + + + + + FUNC6_OUT_SEL_CFG + Reserved + 0x10C + 0x20 + 0x00000100 + + + REG_GPIO_FUNC6_OE_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_FUNC6_OE_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC6_OUT_INV_SEL + Reserved + 2 + 1 + read-write + + + REG_GPIO_FUNC6_OUT_SEL + Reserved + 3 + 6 + read-write + + + + + FUNC7_OUT_SEL_CFG + Reserved + 0x110 + 0x20 + 0x00000100 + + + REG_GPIO_FUNC7_OE_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_FUNC7_OE_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC7_OUT_INV_SEL + Reserved + 2 + 1 + read-write + + + REG_GPIO_FUNC7_OUT_SEL + Reserved + 3 + 6 + read-write + + + + + FUNC8_OUT_SEL_CFG + Reserved + 0x114 + 0x20 + 0x00000100 + + + REG_GPIO_FUNC8_OE_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_FUNC8_OE_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC8_OUT_INV_SEL + Reserved + 2 + 1 + read-write + + + REG_GPIO_FUNC8_OUT_SEL + Reserved + 3 + 6 + read-write + + + + + FUNC9_OUT_SEL_CFG + Reserved + 0x118 + 0x20 + 0x00000100 + + + REG_GPIO_FUNC9_OE_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_FUNC9_OE_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC9_OUT_INV_SEL + Reserved + 2 + 1 + read-write + + + REG_GPIO_FUNC9_OUT_SEL + Reserved + 3 + 6 + read-write + + + + + FUNC10_OUT_SEL_CFG + Reserved + 0x11C + 0x20 + 0x00000100 + + + REG_GPIO_FUNC10_OE_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_FUNC10_OE_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC10_OUT_INV_SEL + Reserved + 2 + 1 + read-write + + + REG_GPIO_FUNC10_OUT_SEL + Reserved + 3 + 6 + read-write + + + + + FUNC11_OUT_SEL_CFG + Reserved + 0x120 + 0x20 + 0x00000100 + + + REG_GPIO_FUNC11_OE_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_FUNC11_OE_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC11_OUT_INV_SEL + Reserved + 2 + 1 + read-write + + + REG_GPIO_FUNC11_OUT_SEL + Reserved + 3 + 6 + read-write + + + + + FUNC12_OUT_SEL_CFG + Reserved + 0x124 + 0x20 + 0x00000100 + + + REG_GPIO_FUNC12_OE_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_FUNC12_OE_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC12_OUT_INV_SEL + Reserved + 2 + 1 + read-write + + + REG_GPIO_FUNC12_OUT_SEL + Reserved + 3 + 6 + read-write + + + + + FUNC13_OUT_SEL_CFG + Reserved + 0x128 + 0x20 + 0x00000100 + + + REG_GPIO_FUNC13_OE_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_FUNC13_OE_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC13_OUT_INV_SEL + Reserved + 2 + 1 + read-write + + + REG_GPIO_FUNC13_OUT_SEL + Reserved + 3 + 6 + read-write + + + + + FUNC14_OUT_SEL_CFG + Reserved + 0x12C + 0x20 + 0x00000100 + + + REG_GPIO_FUNC14_OE_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_FUNC14_OE_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC14_OUT_INV_SEL + Reserved + 2 + 1 + read-write + + + REG_GPIO_FUNC14_OUT_SEL + Reserved + 3 + 6 + read-write + + + + + FUNC15_OUT_SEL_CFG + Reserved + 0x130 + 0x20 + 0x00000100 + + + REG_GPIO_FUNC15_OE_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_FUNC15_OE_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC15_OUT_INV_SEL + Reserved + 2 + 1 + read-write + + + REG_GPIO_FUNC15_OUT_SEL + Reserved + 3 + 6 + read-write + + + + + + + LP_I2C0 + Low-power I2C (Inter-Integrated Circuit) Controller 0 + LP_I2C + 0x50122000 + + 0x0 + 0x88 + registers + + + LP_I2C0 + 11 + + + + SCL_LOW_PERIOD + Configures the low level width of the SCL +Clock + 0x0 + 0x20 + + + SCL_LOW_PERIOD + Configures the low level width of the SCL Clock. +Measurement unit: i2c_sclk. + 0 + 9 + read-write + + + + + CTR + Transmission setting + 0x4 + 0x20 + 0x00000208 + + + SDA_FORCE_OUT + Configures the SDA output mode +1: Direct output, + +0: Open drain output. + 0 + 1 + read-write + + + SCL_FORCE_OUT + Configures the SCL output mode +1: Direct output, + +0: Open drain output. + 1 + 1 + read-write + + + SAMPLE_SCL_LEVEL + Configures the sample mode for SDA. +1: Sample SDA data on the SCL low level. + +0: Sample SDA data on the SCL high level. + 2 + 1 + read-write + + + RX_FULL_ACK_LEVEL + Configures the ACK value that needs to be sent by master when the rx_fifo_cnt has reached the threshold. + 3 + 1 + read-write + + + TRANS_START + Configures to start sending the data in txfifo for slave. +0: No effect + +1: Start + 5 + 1 + write-only + + + TX_LSB_FIRST + Configures to control the sending order for data needing to be sent. +1: send data from the least significant bit, + +0: send data from the most significant bit. + 6 + 1 + read-write + + + RX_LSB_FIRST + Configures to control the storage order for received data. +1: receive data from the least significant bit + +0: receive data from the most significant bit. + 7 + 1 + read-write + + + CLK_EN + Configures whether to gate clock signal for registers. + +0: Force clock on for registers + +1: Support clock only when registers are read or written to by software. + 8 + 1 + read-write + + + ARBITRATION_EN + Configures to enable I2C bus arbitration detection. +0: No effect + +1: Enable + 9 + 1 + read-write + + + FSM_RST + Configures to reset the SCL_FSM. +0: No effect + +1: Reset + 10 + 1 + write-only + + + CONF_UPGATE + Configures this bit for synchronization +0: No effect + +1: Synchronize + 11 + 1 + write-only + + + + + SR + Describe I2C work status. + 0x8 + 0x20 + + + RESP_REC + Represents the received ACK value in master mode or slave mode. +0: ACK, + +1: NACK. + 0 + 1 + read-only + + + ARB_LOST + Represents whether the I2C controller loses control of SCL line. +0: No arbitration lost + +1: Arbitration lost + 3 + 1 + read-only + + + BUS_BUSY + Represents the I2C bus state. +1: The I2C bus is busy transferring data, + +0: The I2C bus is in idle state. + 4 + 1 + read-only + + + RXFIFO_CNT + Represents the number of data bytes to be sent. + 8 + 5 + read-only + + + TXFIFO_CNT + Represents the number of data bytes received in RAM. + 18 + 5 + read-only + + + SCL_MAIN_STATE_LAST + Represents the states of the I2C module state machine. +0: Idle, + +1: Address shift, + +2: ACK address, + +3: Rx data, + +4: Tx data, + +5: Send ACK, + +6: Wait ACK + 24 + 3 + read-only + + + SCL_STATE_LAST + Represents the states of the state machine used to produce SCL. +0: Idle, + +1: Start, + +2: Negative edge, + +3: Low, + +4: Positive edge, + +5: High, + +6: Stop + 28 + 3 + read-only + + + + + TO + Setting time out control for receiving data. + 0xC + 0x20 + 0x00000010 + + + TIME_OUT_VALUE + Configures the timeout threshold period for SCL stucking at high or low level. The actual period is 2^(reg_time_out_value). +Measurement unit: i2c_sclk. + 0 + 5 + read-write + + + TIME_OUT_EN + Configures to enable time out control. +0: No effect + +1: Enable + 5 + 1 + read-write + + + + + FIFO_ST + FIFO status register. + 0x14 + 0x20 + + + RXFIFO_RADDR + Represents the offset address of the APB reading from RXFIFO + 0 + 4 + read-only + + + RXFIFO_WADDR + Represents the offset address of i2c module receiving data and writing to RXFIFO. + 5 + 4 + read-only + + + TXFIFO_RADDR + Represents the offset address of i2c module reading from TXFIFO. + 10 + 4 + read-only + + + TXFIFO_WADDR + Represents the offset address of APB bus writing to TXFIFO. + 15 + 4 + read-only + + + + + FIFO_CONF + FIFO configuration register. + 0x18 + 0x20 + 0x00004046 + + + RXFIFO_WM_THRHD + Configures the water mark threshold of RXFIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd[3:0], reg_rxfifo_wm_int_raw bit will be valid. + 0 + 4 + read-write + + + TXFIFO_WM_THRHD + Configures the water mark threshold of TXFIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than reg_txfifo_wm_thrhd[3:0], reg_txfifo_wm_int_raw bit will be valid. + 5 + 4 + read-write + + + NONFIFO_EN + Configures to enable APB nonfifo access. + 10 + 1 + read-write + + + RX_FIFO_RST + Configures to reset RXFIFO. +0: No effect + +1: Reset + 12 + 1 + read-write + + + TX_FIFO_RST + Configures to reset TXFIFO. +0: No effect + +1: Reset + 13 + 1 + read-write + + + FIFO_PRT_EN + Configures to enable FIFO pointer in non-fifo access mode. This bit controls the valid bits and the TX/RX FIFO overflow, underflow, full and empty interrupts. +0: No effect + +1: Enable + 14 + 1 + read-write + + + + + DATA + Rx FIFO read data. + 0x1C + 0x20 + + + FIFO_RDATA + Represents the value of RXFIFO read data. + 0 + 8 + read-only + + + + + INT_RAW + Raw interrupt status + 0x20 + 0x20 + 0x00000002 + + + RXFIFO_WM_INT_RAW + The raw interrupt status of I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + read-only + + + TXFIFO_WM_INT_RAW + The raw interrupt status of I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + read-only + + + RXFIFO_OVF_INT_RAW + The raw interrupt status of I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + read-only + + + END_DETECT_INT_RAW + The raw interrupt status of the I2C_END_DETECT_INT interrupt. + 3 + 1 + read-only + + + BYTE_TRANS_DONE_INT_RAW + The raw interrupt status of the I2C_END_DETECT_INT interrupt. + 4 + 1 + read-only + + + ARBITRATION_LOST_INT_RAW + The raw interrupt status of the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + read-only + + + MST_TXFIFO_UDF_INT_RAW + The raw interrupt status of I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + read-only + + + TRANS_COMPLETE_INT_RAW + The raw interrupt status of the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + read-only + + + TIME_OUT_INT_RAW + The raw interrupt status of the I2C_TIME_OUT_INT interrupt. + 8 + 1 + read-only + + + TRANS_START_INT_RAW + The raw interrupt status of the I2C_TRANS_START_INT interrupt. + 9 + 1 + read-only + + + NACK_INT_RAW + The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + read-only + + + TXFIFO_OVF_INT_RAW + The raw interrupt status of I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + read-only + + + RXFIFO_UDF_INT_RAW + The raw interrupt status of I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + read-only + + + SCL_ST_TO_INT_RAW + The raw interrupt status of I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + read-only + + + SCL_MAIN_ST_TO_INT_RAW + The raw interrupt status of I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + read-only + + + DET_START_INT_RAW + The raw interrupt status of I2C_DET_START_INT interrupt. + 15 + 1 + read-only + + + + + INT_CLR + Interrupt clear bits + 0x24 + 0x20 + + + RXFIFO_WM_INT_CLR + Write 1 to clear I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + write-only + + + TXFIFO_WM_INT_CLR + Write 1 to clear I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + write-only + + + RXFIFO_OVF_INT_CLR + Write 1 to clear I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + write-only + + + END_DETECT_INT_CLR + Write 1 to clear the I2C_END_DETECT_INT interrupt. + 3 + 1 + write-only + + + BYTE_TRANS_DONE_INT_CLR + Write 1 to clear the I2C_END_DETECT_INT interrupt. + 4 + 1 + write-only + + + ARBITRATION_LOST_INT_CLR + Write 1 to clear the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + write-only + + + MST_TXFIFO_UDF_INT_CLR + Write 1 to clear I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + write-only + + + TRANS_COMPLETE_INT_CLR + Write 1 to clear the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + write-only + + + TIME_OUT_INT_CLR + Write 1 to clear the I2C_TIME_OUT_INT interrupt. + 8 + 1 + write-only + + + TRANS_START_INT_CLR + Write 1 to clear the I2C_TRANS_START_INT interrupt. + 9 + 1 + write-only + + + NACK_INT_CLR + Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + write-only + + + TXFIFO_OVF_INT_CLR + Write 1 to clear I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + write-only + + + RXFIFO_UDF_INT_CLR + Write 1 to clear I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + write-only + + + SCL_ST_TO_INT_CLR + Write 1 to clear I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + write-only + + + SCL_MAIN_ST_TO_INT_CLR + Write 1 to clear I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + write-only + + + DET_START_INT_CLR + Write 1 to clear I2C_DET_START_INT interrupt. + 15 + 1 + write-only + + + + + INT_ENA + Interrupt enable bits + 0x28 + 0x20 + + + RXFIFO_WM_INT_ENA + Write 1 to anable I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + read-write + + + TXFIFO_WM_INT_ENA + Write 1 to anable I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + read-write + + + RXFIFO_OVF_INT_ENA + Write 1 to anable I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + read-write + + + END_DETECT_INT_ENA + Write 1 to anable the I2C_END_DETECT_INT interrupt. + 3 + 1 + read-write + + + BYTE_TRANS_DONE_INT_ENA + Write 1 to anable the I2C_END_DETECT_INT interrupt. + 4 + 1 + read-write + + + ARBITRATION_LOST_INT_ENA + Write 1 to anable the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + read-write + + + MST_TXFIFO_UDF_INT_ENA + Write 1 to anable I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + read-write + + + TRANS_COMPLETE_INT_ENA + Write 1 to anable the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + read-write + + + TIME_OUT_INT_ENA + Write 1 to anable the I2C_TIME_OUT_INT interrupt. + 8 + 1 + read-write + + + TRANS_START_INT_ENA + Write 1 to anable the I2C_TRANS_START_INT interrupt. + 9 + 1 + read-write + + + NACK_INT_ENA + Write 1 to anable I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + read-write + + + TXFIFO_OVF_INT_ENA + Write 1 to anable I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + read-write + + + RXFIFO_UDF_INT_ENA + Write 1 to anable I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + read-write + + + SCL_ST_TO_INT_ENA + Write 1 to anable I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + read-write + + + SCL_MAIN_ST_TO_INT_ENA + Write 1 to anable I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + read-write + + + DET_START_INT_ENA + Write 1 to anable I2C_DET_START_INT interrupt. + 15 + 1 + read-write + + + + + INT_STATUS + Status of captured I2C communication events + 0x2C + 0x20 + + + RXFIFO_WM_INT_ST + The masked interrupt status status of I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + read-only + + + TXFIFO_WM_INT_ST + The masked interrupt status status of I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + read-only + + + RXFIFO_OVF_INT_ST + The masked interrupt status status of I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + read-only + + + END_DETECT_INT_ST + The masked interrupt status status of the I2C_END_DETECT_INT interrupt. + 3 + 1 + read-only + + + BYTE_TRANS_DONE_INT_ST + The masked interrupt status status of the I2C_END_DETECT_INT interrupt. + 4 + 1 + read-only + + + ARBITRATION_LOST_INT_ST + The masked interrupt status status of the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + read-only + + + MST_TXFIFO_UDF_INT_ST + The masked interrupt status status of I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + read-only + + + TRANS_COMPLETE_INT_ST + The masked interrupt status status of the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + read-only + + + TIME_OUT_INT_ST + The masked interrupt status status of the I2C_TIME_OUT_INT interrupt. + 8 + 1 + read-only + + + TRANS_START_INT_ST + The masked interrupt status status of the I2C_TRANS_START_INT interrupt. + 9 + 1 + read-only + + + NACK_INT_ST + The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + read-only + + + TXFIFO_OVF_INT_ST + The masked interrupt status status of I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + read-only + + + RXFIFO_UDF_INT_ST + The masked interrupt status status of I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + read-only + + + SCL_ST_TO_INT_ST + The masked interrupt status status of I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + read-only + + + SCL_MAIN_ST_TO_INT_ST + The masked interrupt status status of I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + read-only + + + DET_START_INT_ST + The masked interrupt status status of I2C_DET_START_INT interrupt. + 15 + 1 + read-only + + + + + SDA_HOLD + Configures the hold time after a negative SCL edge. + 0x30 + 0x20 + + + TIME + Configures the time to hold the data after the falling edge of SCL. +Measurement unit: i2c_sclk + 0 + 9 + read-write + + + + + SDA_SAMPLE + Configures the sample time after a positive SCL edge. + 0x34 + 0x20 + + + TIME + Configures the sample time after a positive SCL edge. +Measurement unit: i2c_sclk + 0 + 9 + read-write + + + + + SCL_HIGH_PERIOD + Configures the high level width of SCL + 0x38 + 0x20 + + + SCL_HIGH_PERIOD + Configures for how long SCL remains high in master mode. +Measurement unit: i2c_sclk + 0 + 9 + read-write + + + SCL_WAIT_HIGH_PERIOD + Configures the SCL_FSM's waiting period for SCL high level in master mode. +Measurement unit: i2c_sclk + 9 + 7 + read-write + + + + + SCL_START_HOLD + Configures the delay between the SDA and SCL negative edge for a start condition + 0x40 + 0x20 + 0x00000008 + + + TIME + Configures the time between the falling edge of SDA and the falling edge of SCL for a START condition. +Measurement unit: i2c_sclk. + 0 + 9 + read-write + + + + + SCL_RSTART_SETUP + Configures the delay between the positive +edge of SCL and the negative edge of SDA + 0x44 + 0x20 + 0x00000008 + + + TIME + Configures the time between the positive edge of SCL and the negative edge of SDA for a RESTART condition. +Measurement unit: i2c_sclk + 0 + 9 + read-write + + + + + SCL_STOP_HOLD + Configures the delay after the SCL clock +edge for a stop condition + 0x48 + 0x20 + 0x00000008 + + + TIME + Configures the delay after the STOP condition. +Measurement unit: i2c_sclk + 0 + 9 + read-write + + + + + SCL_STOP_SETUP + Configures the delay between the SDA and +SCL positive edge for a stop condition + 0x4C + 0x20 + 0x00000008 + + + TIME + Configures the time between the rising edge of SCL and the rising edge of SDA. +Measurement unit: i2c_sclk + 0 + 9 + read-write + + + + + FILTER_CFG + SCL and SDA filter configuration register + 0x50 + 0x20 + 0x00000300 + + + SCL_FILTER_THRES + Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL input has smaller width than this register value, the I2C controller will ignore that pulse. +Measurement unit: i2c_sclk + 0 + 4 + read-write + + + SDA_FILTER_THRES + Configures the threshold pulse width to be filtered on SDA. When a pulse on the SDA input has smaller width than this register value, the I2C controller will ignore that pulse. +Measurement unit: i2c_sclk + 4 + 4 + read-write + + + SCL_FILTER_EN + Configures to enable the filter function for SCL. + 8 + 1 + read-write + + + SDA_FILTER_EN + Configures to enable the filter function for SDA. + 9 + 1 + read-write + + + + + CLK_CONF + I2C CLK configuration register + 0x54 + 0x20 + 0x00200000 + + + SCLK_DIV_NUM + the integral part of the fractional divisor for i2c module + 0 + 8 + read-write + + + SCLK_DIV_A + the numerator of the fractional part of the fractional divisor for i2c module + 8 + 6 + read-write + + + SCLK_DIV_B + the denominator of the fractional part of the fractional divisor for i2c module + 14 + 6 + read-write + + + SCLK_SEL + The clock selection for i2c module:0-XTAL,1-CLK_8MHz. + 20 + 1 + read-write + + + SCLK_ACTIVE + The clock switch for i2c module + 21 + 1 + read-write + + + + + COMD0 + I2C command register 0 + 0x58 + 0x20 + + + COMMAND0 + Configures command 0. It consists of three parts: +op_code is the command, +0: RSTART, +1: WRITE, +2: READ, +3: STOP, +4: END. + +Byte_num represents the number of bytes that need to be sent or received. +ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more information. + 0 + 14 + read-write + + + COMMAND0_DONE + Represents whether command 0 is done in I2C Master mode. +0: Not done + +1: Done + 31 + 1 + read-write + + + + + COMD1 + I2C command register 1 + 0x5C + 0x20 + + + COMMAND1 + Configures command 1. See details in I2C_CMD0_REG[13:0]. + 0 + 14 + read-write + + + COMMAND1_DONE + Represents whether command 1 is done in I2C Master mode. +0: Not done + +1: Done + 31 + 1 + read-write + + + + + COMD2 + I2C command register 2 + 0x60 + 0x20 + + + COMMAND2 + Configures command 2. See details in I2C_CMD0_REG[13:0]. + 0 + 14 + read-write + + + COMMAND2_DONE + Represents whether command 2 is done in I2C Master mode. +0: Not done + +1: Done + 31 + 1 + read-write + + + + + COMD3 + I2C command register 3 + 0x64 + 0x20 + + + COMMAND3 + Configures command 3. See details in I2C_CMD0_REG[13:0]. + 0 + 14 + read-write + + + COMMAND3_DONE + Represents whether command 3 is done in I2C Master mode. +0: Not done + +1: Done + 31 + 1 + read-write + + + + + COMD4 + I2C command register 4 + 0x68 + 0x20 + + + COMMAND4 + Configures command 4. See details in I2C_CMD0_REG[13:0]. + 0 + 14 + read-write + + + COMMAND4_DONE + Represents whether command 4 is done in I2C Master mode. +0: Not done + +1: Done + 31 + 1 + read-write + + + + + COMD5 + I2C command register 5 + 0x6C + 0x20 + + + COMMAND5 + Configures command 5. See details in I2C_CMD0_REG[13:0]. + 0 + 14 + read-write + + + COMMAND5_DONE + Represents whether command 5 is done in I2C Master mode. +0: Not done + +1: Done + 31 + 1 + read-write + + + + + COMD6 + I2C command register 6 + 0x70 + 0x20 + + + COMMAND6 + Configures command 6. See details in I2C_CMD0_REG[13:0]. + 0 + 14 + read-write + + + COMMAND6_DONE + Represents whether command 6 is done in I2C Master mode. +0: Not done + +1: Done + 31 + 1 + read-write + + + + + COMD7 + I2C command register 7 + 0x74 + 0x20 + + + COMMAND7 + Configures command 7. See details in I2C_CMD0_REG[13:0]. + 0 + 14 + read-write + + + COMMAND7_DONE + Represents whether command 7 is done in I2C Master mode. +0: Not done + +1: Done + 31 + 1 + read-write + + + + + SCL_ST_TIME_OUT + SCL status time out register + 0x78 + 0x20 + 0x00000010 + + + SCL_ST_TO_I2C + Configures the threshold value of SCL_FSM state unchanged period. It should be no more than 23. +Measurement unit: i2c_sclk + 0 + 5 + read-write + + + + + SCL_MAIN_ST_TIME_OUT + SCL main status time out register + 0x7C + 0x20 + 0x00000010 + + + SCL_MAIN_ST_TO_I2C + Configures the threshold value of SCL_MAIN_FSM state unchanged period.nIt should be no more than 23. +Measurement unit: i2c_sclk + 0 + 5 + read-write + + + + + SCL_SP_CONF + Power configuration register + 0x80 + 0x20 + + + SCL_RST_SLV_EN + When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to reg_scl_rst_slv_num[4:0]. + 0 + 1 + read-write + + + SCL_RST_SLV_NUM + Configures to send out SCL pulses when I2C master is IDLE. The number of pulses equals to reg_scl_rst_slv_num[4:0]. + 1 + 5 + read-write + + + SCL_PD_EN + Configure the pulses of SCL generated in I2C master mode. +Valid when reg_scl_rst_slv_en is 1. +Measurement unit: i2c_sclk + 6 + 1 + read-write + + + SDA_PD_EN + Configures to power down the I2C output SCL line. +0: Not power down. + +1: Power down. +Valid only when reg_scl_force_out is 1. + 7 + 1 + read-write + + + + + DATE + Version register + 0xF8 + 0x20 + 0x02201143 + + + DATE + Version control register. + 0 + 32 + read-write + + + + + TXFIFO_START_ADDR + I2C TXFIFO base address register + 0x100 + 0x20 + + + TXFIFO_START_ADDR + Represents the I2C txfifo first address. + 0 + 32 + read-only + + + + + RXFIFO_START_ADDR + I2C RXFIFO base address register + 0x180 + 0x20 + + + RXFIFO_START_ADDR + Represents the I2C rxfifo first address. + 0 + 32 + read-only + + + + + + + LP_I2S0 + Low-power I2S (Inter-IC Sound) Controller 0 + LP_I2S + 0x50125000 + + 0x0 + 0x98 + registers + + + LP_I2S0 + 12 + + + + VAD_CONF + I2S VAD Configure register + 0x0 + 0x20 + + + VAD_EN + VAD enable register + 0 + 1 + read-write + + + VAD_RESET + VAD reset register + 1 + 1 + write-only + + + VAD_FORCE_START + VAD force start register. + 2 + 1 + write-only + + + + + VAD_RESULT + I2S VAD Result register + 0x4 + 0x20 + + + VAD_FLAG + Reg vad flag observe signal + 0 + 1 + read-only + + + ENERGY_ENOUGH + Reg energy enough observe signal + 1 + 1 + read-only + + + + + RX_MEM_CONF + I2S VAD Observe register + 0x8 + 0x20 + 0x00007E00 + + + RX_MEM_FIFO_CNT + The number of data in the rx mem + 0 + 9 + read-only + + + RX_MEM_THRESHOLD + I2S rx mem will trigger an interrupt when the data in the mem is over(not including equal) reg_rx_mem_threshold + 9 + 8 + read-write + + + + + INT_RAW + I2S interrupt raw register, valid in level. + 0xC + 0x20 + + + RX_DONE_INT_RAW + The raw interrupt status bit for the i2s_rx_done_int interrupt + 0 + 1 + read-only + + + RX_HUNG_INT_RAW + The raw interrupt status bit for the i2s_rx_hung_int interrupt + 1 + 1 + read-only + + + RX_FIFOMEM_UDF_INT_RAW + The raw interrupt status bit for the i2s_rx_fifomem_udf_int interrupt + 2 + 1 + read-only + + + VAD_DONE_INT_RAW + The raw interrupt status bit for the vad_done_int interrupt + 3 + 1 + read-only + + + VAD_RESET_DONE_INT_RAW + The raw interrupt status bit for the vad_reset_done_int interrupt + 4 + 1 + read-only + + + RX_MEM_THRESHOLD_INT_RAW + The raw interrupt status bit for the rx_mem_threshold_int interrupt + 5 + 1 + read-only + + + + + INT_ST + I2S interrupt status register. + 0x10 + 0x20 + + + RX_DONE_INT_ST + The masked interrupt status bit for the i2s_rx_done_int interrupt + 0 + 1 + read-only + + + RX_HUNG_INT_ST + The masked interrupt status bit for the i2s_rx_hung_int interrupt + 1 + 1 + read-only + + + RX_FIFOMEM_UDF_INT_ST + The masked interrupt status bit for the i2s_rx_fifomem_udf_int interrupt + 2 + 1 + read-only + + + LP_VAD_DONE_INT_ST + The masked interrupt status bit for the vad_done_int interrupt + 3 + 1 + read-only + + + LP_VAD_RESET_DONE_INT_ST + The masked interrupt status bit for the vad_reset_done_int interrupt + 4 + 1 + read-only + + + RX_MEM_THRESHOLD_INT_ST + The masked interrupt status bit for the rx_mem_threshold_int interrupt + 5 + 1 + read-only + + + + + INT_ENA + I2S interrupt enable register. + 0x14 + 0x20 + + + RX_DONE_INT_ENA + The interrupt enable bit for the i2s_rx_done_int interrupt + 0 + 1 + read-write + + + RX_HUNG_INT_ENA + The interrupt enable bit for the i2s_rx_hung_int interrupt + 1 + 1 + read-write + + + RX_FIFOMEM_UDF_INT_ENA + The interrupt enable bit for the i2s_rx_fifomem_udf_int interrupt + 2 + 1 + read-write + + + LP_VAD_DONE_INT_ENA + The interrupt enable bit for the vad_done_int interrupt + 3 + 1 + read-write + + + LP_VAD_RESET_DONE_INT_ENA + The interrupt enable bit for the vad_reset_done_int interrupt + 4 + 1 + read-write + + + RX_MEM_THRESHOLD_INT_ENA + The interrupt enable bit for the rx_mem_threshold_int interrupt + 5 + 1 + read-write + + + + + INT_CLR + I2S interrupt clear register. + 0x18 + 0x20 + + + RX_DONE_INT_CLR + Set this bit to clear the i2s_rx_done_int interrupt + 0 + 1 + write-only + + + RX_HUNG_INT_CLR + Set this bit to clear the i2s_rx_hung_int interrupt + 1 + 1 + write-only + + + RX_FIFOMEM_UDF_INT_CLR + Set this bit to clear the i2s_rx_fifomem_udf_int interrupt + 2 + 1 + write-only + + + LP_VAD_DONE_INT_CLR + Set this bit to clear the vad_done_int interrupt + 3 + 1 + write-only + + + LP_VAD_RESET_DONE_INT_CLR + Set this bit to clear the vad_reset_done_int interrupt + 4 + 1 + write-only + + + RX_MEM_THRESHOLD_INT_CLR + Set this bit to clear the rx_mem_threshold_int interrupt + 5 + 1 + write-only + + + + + RX_CONF + I2S RX configure register + 0x20 + 0x20 + 0x00009600 + + + RX_RESET + Set this bit to reset receiver + 0 + 1 + write-only + + + RX_FIFO_RESET + Set this bit to reset Rx AFIFO + 1 + 1 + write-only + + + RX_START + Set this bit to start receiving data + 2 + 1 + read-write + + + RX_SLAVE_MOD + Set this bit to enable slave receiver mode + 3 + 1 + read-write + + + RX_FIFOMEM_RESET + Set this bit to reset Rx Syncfifomem + 4 + 1 + write-only + + + RX_MONO + Set this bit to enable receiver in mono mode + 5 + 1 + read-write + + + RX_BIG_ENDIAN + I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value. + 7 + 1 + read-write + + + RX_UPDATE + Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done. + 8 + 1 + read-write + + + RX_MONO_FST_VLD + 1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode. + 9 + 1 + read-write + + + RX_PCM_CONF + I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & + 10 + 2 + read-write + + + RX_PCM_BYPASS + Set this bit to bypass Compress/Decompress module for received data. + 12 + 1 + read-write + + + RX_STOP_MODE + 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full. + 13 + 2 + read-write + + + RX_LEFT_ALIGN + 1: I2S RX left alignment mode. 0: I2S RX right alignment mode. + 15 + 1 + read-write + + + RX_24_FILL_EN + 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits. + 16 + 1 + read-write + + + RX_WS_IDLE_POL + 0: WS should be 0 when receiving left channel data, and WS is 1in right channel. 1: WS should be 1 when receiving left channel data, and WS is 0in right channel. + 17 + 1 + read-write + + + RX_BIT_ORDER + I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first. + 18 + 1 + read-write + + + RX_TDM_EN + 1: Enable I2S TDM Rx mode . 0: Disable. + 19 + 1 + read-write + + + RX_PDM_EN + 1: Enable I2S PDM Rx mode . 0: Disable. + 20 + 1 + read-write + + + + + RX_CONF1 + I2S RX configure register 1 + 0x28 + 0x20 + 0x2F3DE300 + + + RX_TDM_WS_WIDTH + The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH[6:0] +1) * T_bck + 0 + 7 + read-write + + + RX_BCK_DIV_NUM + Bit clock configuration bits in receiver mode. + 7 + 6 + read-write + + + RX_BITS_MOD + Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode. + 13 + 5 + read-write + + + RX_HALF_SAMPLE_BITS + I2S Rx half sample bits -1. + 18 + 6 + read-write + + + RX_TDM_CHAN_BITS + The Rx bit number for each channel minus 1in TDM mode. + 24 + 5 + read-write + + + RX_MSB_SHIFT + Set this bit to enable receiver in Phillips standard mode + 29 + 1 + read-write + + + + + RX_TDM_CTRL + I2S TX TDM mode control register + 0x50 + 0x20 + 0x00000003 + + + RX_TDM_PDM_CHAN0_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0: Disable, just input 0 in this channel. + 0 + 1 + read-write + + + RX_TDM_PDM_CHAN1_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0: Disable, just input 0 in this channel. + 1 + 1 + read-write + + + RX_TDM_TOT_CHAN_NUM + The total channel number of I2S TX TDM mode. + 16 + 4 + read-write + + + + + RX_TIMING + I2S RX timing control register + 0x58 + 0x20 + + + RX_SD_IN_DM + The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 0 + 2 + read-write + + + RX_WS_OUT_DM + The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 16 + 2 + read-write + + + RX_BCK_OUT_DM + The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 20 + 2 + read-write + + + RX_WS_IN_DM + The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 24 + 2 + read-write + + + RX_BCK_IN_DM + The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 28 + 2 + read-write + + + + + LC_HUNG_CONF + I2S HUNG configure register. + 0x60 + 0x20 + 0x00000810 + + + LC_FIFO_TIMEOUT + the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value + 0 + 8 + read-write + + + LC_FIFO_TIMEOUT_SHIFT + The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift + 8 + 3 + read-write + + + LC_FIFO_TIMEOUT_ENA + The enable bit for FIFO timeout + 11 + 1 + read-write + + + + + RXEOF_NUM + I2S RX data number control register. + 0x64 + 0x20 + 0x00000040 + + + RX_EOF_NUM + The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel. + 0 + 12 + read-write + + + + + CONF_SIGLE_DATA + I2S signal data register + 0x68 + 0x20 + + + SINGLE_DATA + The configured constant channel data to be sent out. + 0 + 32 + read-write + + + + + RX_PDM_CONF + I2S RX configure register + 0x70 + 0x20 + 0xF8200000 + + + RX_PDM2PCM_EN + 1: Enable PDM2PCM RX mode. 0: DIsable. + 19 + 1 + read-write + + + RX_PDM_SINC_DSR_16_EN + Configure the down sampling rate of PDM RX filter group1 module. 1: The down sampling rate is 128. 0: down sampling rate is 64. + 20 + 1 + read-write + + + RX_PDM2PCM_AMPLIFY_NUM + Configure PDM RX amplify number. + 21 + 4 + read-write + + + RX_PDM_HP_BYPASS + I2S PDM RX bypass hp filter or not. + 25 + 1 + read-write + + + RX_IIR_HP_MULT12_5 + The fourth parameter of PDM RX IIR_HP filter stage 2 is (504 + LP_I2S_RX_IIR_HP_MULT12_5[2:0]) + 26 + 3 + read-write + + + RX_IIR_HP_MULT12_0 + The fourth parameter of PDM RX IIR_HP filter stage 1 is (504 + LP_I2S_RX_IIR_HP_MULT12_0[2:0]) + 29 + 3 + read-write + + + + + ECO_LOW + I2S ECO register + 0x74 + 0x20 + + + RDN_ECO_LOW + logic low eco registers + 0 + 32 + read-write + + + + + ECO_HIGH + I2S ECO register + 0x78 + 0x20 + 0xFFFFFFFF + + + RDN_ECO_HIGH + logic high eco registers + 0 + 32 + read-write + + + + + ECO_CONF + I2S ECO register + 0x7C + 0x20 + + + RDN_ENA + enable rdn counter bit + 0 + 1 + read-write + + + RDN_RESULT + rdn result + 1 + 1 + read-only + + + + + VAD_PARAM0 + I2S VAD Parameter register + 0x80 + 0x20 + 0x00C81388 + + + PARAM_MIN_ENERGY + VAD parameter + 0 + 16 + read-write + + + PARAM_INIT_FRAME_NUM + VAD parameter + 16 + 9 + read-write + + + + + VAD_PARAM1 + I2S VAD Parameter register + 0x84 + 0x20 + 0x281E1E43 + + + PARAM_MIN_SPEECH_COUNT + VAD parameter + 0 + 4 + read-write + + + PARAM_MAX_SPEECH_COUNT + VAD parameter + 4 + 7 + read-write + + + PARAM_HANGOVER_SPEECH + VAD parameter + 11 + 5 + read-write + + + PARAM_HANGOVER_SILENT + VAD parameter + 16 + 8 + read-write + + + PARAM_MAX_OFFSET + VAD parameter + 24 + 7 + read-write + + + PARAM_SKIP_BAND_ENERGY + Set 1 to skip band energy check. + 31 + 1 + read-write + + + + + VAD_PARAM2 + I2S VAD Parameter register + 0x88 + 0x20 + 0x7EB86666 + + + PARAM_NOISE_AMP_DOWN + VAD parameter + 0 + 16 + read-write + + + PARAM_NOISE_AMP_UP + VAD parameter + 16 + 16 + read-write + + + + + VAD_PARAM3 + I2S VAD Parameter register + 0x8C + 0x20 + 0x7D717FDF + + + PARAM_NOISE_SPE_UP0 + VAD parameter + 0 + 16 + read-write + + + PARAM_NOISE_SPE_UP1 + VAD parameter + 16 + 16 + read-write + + + + + VAD_PARAM4 + I2S VAD Parameter register + 0x90 + 0x20 + 0x799A6666 + + + PARAM_NOISE_SPE_DOWN + VAD parameter + 0 + 16 + read-write + + + PARAM_NOISE_MEAN_DOWN + VAD parameter + 16 + 16 + read-write + + + + + VAD_PARAM5 + I2S VAD Parameter register + 0x94 + 0x20 + 0x7C287D71 + + + PARAM_NOISE_MEAN_UP0 + VAD parameter + 0 + 16 + read-write + + + PARAM_NOISE_MEAN_UP1 + VAD parameter + 16 + 16 + read-write + + + + + VAD_PARAM6 + I2S VAD Parameter register + 0x98 + 0x20 + 0xB4007D00 + + + PARAM_NOISE_STD_FS_THSL + Feature_sum threshold to determine noise_std max value when vad_tag=1, equal to ((noise_std_max)>>11)^2*5 + 0 + 16 + read-write + + + PARAM_NOISE_STD_FS_THSH + Feature_sum threshold to determine noise_std max value when vad_tag=0, equal to ((noise_std_max)>>11)^2*5 + 16 + 16 + read-write + + + + + VAD_PARAM7 + I2S VAD Parameter register + 0x9C + 0x20 + 0x01487EB8 + + + PARAM_THRES_UPD_BASE + VAD parameter + 0 + 16 + read-write + + + PARAM_THRES_UPD_VARY + VAD parameter + 16 + 16 + read-write + + + + + VAD_PARAM8 + I2S VAD Parameter register + 0xA0 + 0x20 + 0x20005040 + + + PARAM_THRES_UPD_BDL + Noise_std boundary low when updating threshold. + 0 + 8 + read-write + + + PARAM_THRES_UPD_BDH + Noise_std boundary high when updating threshold. + 8 + 8 + read-write + + + PARAM_FEATURE_BURST + VAD parameter + 16 + 16 + read-write + + + + + VAD_OB0 + I2S VAD Observe register + 0xB0 + 0x20 + + + SPEECH_COUNT_OB + Reg silent count observe + 0 + 8 + read-only + + + SILENT_COUNT_OB + Reg speech count observe + 8 + 8 + read-only + + + MAX_SIGNAL0_OB + Reg max signal0 observe + 16 + 16 + read-only + + + + + VAD_OB1 + I2S VAD Observe register + 0xB4 + 0x20 + + + MAX_SIGNAL1_OB + Reg max signal1 observe + 0 + 16 + read-only + + + MAX_SIGNAL2_OB + Reg max signal2 observe + 16 + 16 + read-only + + + + + VAD_OB2 + I2S VAD Observe register + 0xB8 + 0x20 + + + NOISE_AMP_OB + Reg noise_amp observe signal + 0 + 32 + read-only + + + + + VAD_OB3 + I2S VAD Observe register + 0xBC + 0x20 + + + NOISE_MEAN_OB + Reg noise_mean observe signal + 0 + 32 + read-only + + + + + VAD_OB4 + I2S VAD Observe register + 0xC0 + 0x20 + + + NOISE_STD_OB + Reg noise_std observe signal + 0 + 32 + read-only + + + + + VAD_OB5 + I2S VAD Observe register + 0xC4 + 0x20 + + + OFFSET_OB + Reg offset observe signal + 0 + 32 + read-only + + + + + VAD_OB6 + I2S VAD Observe register + 0xC8 + 0x20 + + + THRESHOLD_OB + Reg threshold observe signal + 0 + 32 + read-only + + + + + VAD_OB7 + I2S VAD Observe register + 0xCC + 0x20 + + + ENERGY_LOW_OB + Reg energy bit 31~0 observe signal + 0 + 32 + read-only + + + + + VAD_OB8 + I2S VAD Observe register + 0xD0 + 0x20 + + + ENERGY_HIGH_OB + Reg energy bit 63~32 observe signal + 0 + 32 + read-only + + + + + CLK_GATE + Clock gate register + 0xF8 + 0x20 + 0x0000000A + + + CLK_EN + set this bit to enable clock gate + 0 + 1 + read-write + + + VAD_CG_FORCE_ON + VAD clock gate force on register + 1 + 1 + read-write + + + RX_MEM_CG_FORCE_ON + I2S rx mem clock gate force on register + 2 + 1 + read-write + + + RX_REG_CG_FORCE_ON + I2S rx reg clock gate force on register + 3 + 1 + read-write + + + + + DATE + Version control register + 0xFC + 0x20 + 0x02305040 + + + DATE + I2S version control register + 0 + 28 + read-write + + + + + + + LP_IO_MUX + Low-power Input/Output Multiplexer + LP_IOMUX + 0x5012B000 + + 0x0 + 0x54 + registers + + + + CLK_EN + Reserved + 0x0 + 0x20 + 0x00000001 + + + REG_CLK_EN + Reserved + 0 + 1 + read-write + + + + + VER_DATE + Reserved + 0x4 + 0x20 + 0x00230313 + + + REG_VER_DATE + Reserved + 0 + 28 + read-write + + + + + PAD0 + Reserved + 0x8 + 0x20 + 0x00000002 + + + REG_PAD0_DRV + Reserved + 0 + 2 + read-write + + + REG_PAD0_RDE + Reserved + 2 + 1 + read-write + + + REG_PAD0_RUE + Reserved + 3 + 1 + read-write + + + REG_PAD0_MUX_SEL + 1:use LP GPIO,0: use digital GPIO + 4 + 1 + read-write + + + REG_PAD0_FUN_SEL + function sel + 5 + 2 + read-write + + + REG_PAD0_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 7 + 1 + read-write + + + REG_PAD0_SLP_IE + input enable in sleep mode + 8 + 1 + read-write + + + REG_PAD0_SLP_OE + output enable in sleep mode + 9 + 1 + read-write + + + REG_PAD0_FUN_IE + input enable in work mode + 10 + 1 + read-write + + + REG_PAD0_FILTER_EN + need des + 11 + 1 + read-write + + + + + PAD1 + Reserved + 0xC + 0x20 + 0x00000002 + + + REG_PAD1_DRV + Reserved + 0 + 2 + read-write + + + REG_PAD1_RDE + Reserved + 2 + 1 + read-write + + + REG_PAD1_RUE + Reserved + 3 + 1 + read-write + + + REG_PAD1_MUX_SEL + 1:use LP GPIO,0: use digital GPIO + 4 + 1 + read-write + + + REG_PAD1_FUN_SEL + function sel + 5 + 2 + read-write + + + REG_PAD1_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 7 + 1 + read-write + + + REG_PAD1_SLP_IE + input enable in sleep mode + 8 + 1 + read-write + + + REG_PAD1_SLP_OE + output enable in sleep mode + 9 + 1 + read-write + + + REG_PAD1_FUN_IE + input enable in work mode + 10 + 1 + read-write + + + REG_PAD1_FILTER_EN + need des + 11 + 1 + read-write + + + + + PAD2 + Reserved + 0x10 + 0x20 + 0x00000002 + + + REG_PAD2_DRV + Reserved + 0 + 2 + read-write + + + REG_PAD2_RDE + Reserved + 2 + 1 + read-write + + + REG_PAD2_RUE + Reserved + 3 + 1 + read-write + + + REG_PAD2_MUX_SEL + 1:use LP GPIO,0: use digital GPIO + 4 + 1 + read-write + + + REG_PAD2_FUN_SEL + function sel + 5 + 2 + read-write + + + REG_PAD2_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 7 + 1 + read-write + + + REG_PAD2_SLP_IE + input enable in sleep mode + 8 + 1 + read-write + + + REG_PAD2_SLP_OE + output enable in sleep mode + 9 + 1 + read-write + + + REG_PAD2_FUN_IE + input enable in work mode + 10 + 1 + read-write + + + REG_PAD2_FILTER_EN + need des + 11 + 1 + read-write + + + + + PAD3 + Reserved + 0x14 + 0x20 + 0x00000002 + + + REG_PAD3_DRV + Reserved + 0 + 2 + read-write + + + REG_PAD3_RDE + Reserved + 2 + 1 + read-write + + + REG_PAD3_RUE + Reserved + 3 + 1 + read-write + + + REG_PAD3_MUX_SEL + 1:use LP GPIO,0: use digital GPIO + 4 + 1 + read-write + + + REG_PAD3_FUN_SEL + function sel + 5 + 2 + read-write + + + REG_PAD3_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 7 + 1 + read-write + + + REG_PAD3_SLP_IE + input enable in sleep mode + 8 + 1 + read-write + + + REG_PAD3_SLP_OE + output enable in sleep mode + 9 + 1 + read-write + + + REG_PAD3_FUN_IE + input enable in work mode + 10 + 1 + read-write + + + REG_PAD3_FILTER_EN + need des + 11 + 1 + read-write + + + + + PAD4 + Reserved + 0x18 + 0x20 + 0x00000002 + + + REG_PAD4_DRV + Reserved + 0 + 2 + read-write + + + REG_PAD4_RDE + Reserved + 2 + 1 + read-write + + + REG_PAD4_RUE + Reserved + 3 + 1 + read-write + + + REG_PAD4_MUX_SEL + 1:use LP GPIO,0: use digital GPIO + 4 + 1 + read-write + + + REG_PAD4_FUN_SEL + function sel + 5 + 2 + read-write + + + REG_PAD4_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 7 + 1 + read-write + + + REG_PAD4_SLP_IE + input enable in sleep mode + 8 + 1 + read-write + + + REG_PAD4_SLP_OE + output enable in sleep mode + 9 + 1 + read-write + + + REG_PAD4_FUN_IE + input enable in work mode + 10 + 1 + read-write + + + REG_PAD4_FILTER_EN + need des + 11 + 1 + read-write + + + + + PAD5 + Reserved + 0x1C + 0x20 + 0x00000002 + + + REG_PAD5_DRV + Reserved + 0 + 2 + read-write + + + REG_PAD5_RDE + Reserved + 2 + 1 + read-write + + + REG_PAD5_RUE + Reserved + 3 + 1 + read-write + + + REG_PAD5_MUX_SEL + 1:use LP GPIO,0: use digital GPIO + 4 + 1 + read-write + + + REG_PAD5_FUN_SEL + function sel + 5 + 2 + read-write + + + REG_PAD5_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 7 + 1 + read-write + + + REG_PAD5_SLP_IE + input enable in sleep mode + 8 + 1 + read-write + + + REG_PAD5_SLP_OE + output enable in sleep mode + 9 + 1 + read-write + + + REG_PAD5_FUN_IE + input enable in work mode + 10 + 1 + read-write + + + REG_PAD5_FILTER_EN + need des + 11 + 1 + read-write + + + + + PAD6 + Reserved + 0x20 + 0x20 + 0x00000002 + + + REG_PAD6_DRV + Reserved + 0 + 2 + read-write + + + REG_PAD6_RDE + Reserved + 2 + 1 + read-write + + + REG_PAD6_RUE + Reserved + 3 + 1 + read-write + + + REG_PAD6_MUX_SEL + 1:use LP GPIO,0: use digital GPIO + 4 + 1 + read-write + + + REG_PAD6_FUN_SEL + function sel + 5 + 2 + read-write + + + REG_PAD6_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 7 + 1 + read-write + + + REG_PAD6_SLP_IE + input enable in sleep mode + 8 + 1 + read-write + + + REG_PAD6_SLP_OE + output enable in sleep mode + 9 + 1 + read-write + + + REG_PAD6_FUN_IE + input enable in work mode + 10 + 1 + read-write + + + REG_PAD6_FILTER_EN + need des + 11 + 1 + read-write + + + + + PAD7 + Reserved + 0x24 + 0x20 + 0x00000002 + + + REG_PAD7_DRV + Reserved + 0 + 2 + read-write + + + REG_PAD7_RDE + Reserved + 2 + 1 + read-write + + + REG_PAD7_RUE + Reserved + 3 + 1 + read-write + + + REG_PAD7_MUX_SEL + 1:use LP GPIO,0: use digital GPIO + 4 + 1 + read-write + + + REG_PAD7_FUN_SEL + function sel + 5 + 2 + read-write + + + REG_PAD7_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 7 + 1 + read-write + + + REG_PAD7_SLP_IE + input enable in sleep mode + 8 + 1 + read-write + + + REG_PAD7_SLP_OE + output enable in sleep mode + 9 + 1 + read-write + + + REG_PAD7_FUN_IE + input enable in work mode + 10 + 1 + read-write + + + REG_PAD7_FILTER_EN + need des + 11 + 1 + read-write + + + + + PAD8 + Reserved + 0x28 + 0x20 + 0x00000002 + + + REG_PAD8_DRV + Reserved + 0 + 2 + read-write + + + REG_PAD8_RDE + Reserved + 2 + 1 + read-write + + + REG_PAD8_RUE + Reserved + 3 + 1 + read-write + + + REG_PAD8_MUX_SEL + 1:use LP GPIO,0: use digital GPIO + 4 + 1 + read-write + + + REG_PAD8_FUN_SEL + function sel + 5 + 2 + read-write + + + REG_PAD8_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 7 + 1 + read-write + + + REG_PAD8_SLP_IE + input enable in sleep mode + 8 + 1 + read-write + + + REG_PAD8_SLP_OE + output enable in sleep mode + 9 + 1 + read-write + + + REG_PAD8_FUN_IE + input enable in work mode + 10 + 1 + read-write + + + REG_PAD8_FILTER_EN + need des + 11 + 1 + read-write + + + + + PAD9 + Reserved + 0x2C + 0x20 + 0x00000002 + + + REG_PAD9_DRV + Reserved + 0 + 2 + read-write + + + REG_PAD9_RDE + Reserved + 2 + 1 + read-write + + + REG_PAD9_RUE + Reserved + 3 + 1 + read-write + + + REG_PAD9_MUX_SEL + 1:use LP GPIO,0: use digital GPIO + 4 + 1 + read-write + + + REG_PAD9_FUN_SEL + function sel + 5 + 2 + read-write + + + REG_PAD9_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 7 + 1 + read-write + + + REG_PAD9_SLP_IE + input enable in sleep mode + 8 + 1 + read-write + + + REG_PAD9_SLP_OE + output enable in sleep mode + 9 + 1 + read-write + + + REG_PAD9_FUN_IE + input enable in work mode + 10 + 1 + read-write + + + REG_PAD9_FILTER_EN + need des + 11 + 1 + read-write + + + + + PAD10 + Reserved + 0x30 + 0x20 + 0x00000002 + + + REG_PAD10_DRV + Reserved + 0 + 2 + read-write + + + REG_PAD10_RDE + Reserved + 2 + 1 + read-write + + + REG_PAD10_RUE + Reserved + 3 + 1 + read-write + + + REG_PAD10_MUX_SEL + 1:use LP GPIO,0: use digital GPIO + 4 + 1 + read-write + + + REG_PAD10_FUN_SEL + function sel + 5 + 2 + read-write + + + REG_PAD10_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 7 + 1 + read-write + + + REG_PAD10_SLP_IE + input enable in sleep mode + 8 + 1 + read-write + + + REG_PAD10_SLP_OE + output enable in sleep mode + 9 + 1 + read-write + + + REG_PAD10_FUN_IE + input enable in work mode + 10 + 1 + read-write + + + REG_PAD10_FILTER_EN + need des + 11 + 1 + read-write + + + + + PAD11 + Reserved + 0x34 + 0x20 + 0x00000002 + + + REG_PAD11_DRV + Reserved + 0 + 2 + read-write + + + REG_PAD11_RDE + Reserved + 2 + 1 + read-write + + + REG_PAD11_RUE + Reserved + 3 + 1 + read-write + + + REG_PAD11_MUX_SEL + 1:use LP GPIO,0: use digital GPIO + 4 + 1 + read-write + + + REG_PAD11_FUN_SEL + function sel + 5 + 2 + read-write + + + REG_PAD11_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 7 + 1 + read-write + + + REG_PAD11_SLP_IE + input enable in sleep mode + 8 + 1 + read-write + + + REG_PAD11_SLP_OE + output enable in sleep mode + 9 + 1 + read-write + + + REG_PAD11_FUN_IE + input enable in work mode + 10 + 1 + read-write + + + REG_PAD11_FILTER_EN + need des + 11 + 1 + read-write + + + + + PAD120 + Reserved + 0x38 + 0x20 + 0x00000002 + + + REG_PAD12_DRV + Reserved + 0 + 2 + read-write + + + REG_PAD12_RDE + Reserved + 2 + 1 + read-write + + + REG_PAD12_RUE + Reserved + 3 + 1 + read-write + + + REG_PAD12_MUX_SEL + 1:use LP GPIO,0: use digital GPIO + 4 + 1 + read-write + + + REG_PAD12_FUN_SEL + function sel + 5 + 2 + read-write + + + REG_PAD12_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 7 + 1 + read-write + + + REG_PAD12_SLP_IE + input enable in sleep mode + 8 + 1 + read-write + + + REG_PAD12_SLP_OE + output enable in sleep mode + 9 + 1 + read-write + + + REG_PAD12_FUN_IE + input enable in work mode + 10 + 1 + read-write + + + REG_PAD12_FILTER_EN + need des + 11 + 1 + read-write + + + + + PAD13 + Reserved + 0x3C + 0x20 + 0x00000002 + + + REG_PAD13_DRV + Reserved + 0 + 2 + read-write + + + REG_PAD13_RDE + Reserved + 2 + 1 + read-write + + + REG_PAD13_RUE + Reserved + 3 + 1 + read-write + + + REG_PAD13_MUX_SEL + 1:use LP GPIO,0: use digital GPIO + 4 + 1 + read-write + + + REG_PAD13_FUN_SEL + function sel + 5 + 2 + read-write + + + REG_PAD13_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 7 + 1 + read-write + + + REG_PAD13_SLP_IE + input enable in sleep mode + 8 + 1 + read-write + + + REG_PAD13_SLP_OE + output enable in sleep mode + 9 + 1 + read-write + + + REG_PAD13_FUN_IE + input enable in work mode + 10 + 1 + read-write + + + REG_PAD13_FILTER_EN + need des + 11 + 1 + read-write + + + + + PAD14 + Reserved + 0x40 + 0x20 + 0x00000002 + + + REG_PAD14_DRV + Reserved + 0 + 2 + read-write + + + REG_PAD14_RDE + Reserved + 2 + 1 + read-write + + + REG_PAD14_RUE + Reserved + 3 + 1 + read-write + + + REG_PAD14_MUX_SEL + 1:use LP GPIO,0: use digital GPIO + 4 + 1 + read-write + + + REG_PAD14_FUN_SEL + function sel + 5 + 2 + read-write + + + REG_PAD14_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 7 + 1 + read-write + + + REG_PAD14_SLP_IE + input enable in sleep mode + 8 + 1 + read-write + + + REG_PAD14_SLP_OE + output enable in sleep mode + 9 + 1 + read-write + + + REG_PAD14_FUN_IE + input enable in work mode + 10 + 1 + read-write + + + REG_PAD14_FILTER_EN + need des + 11 + 1 + read-write + + + + + PAD15 + Reserved + 0x44 + 0x20 + 0x00000002 + + + REG_PAD15_DRV + Reserved + 0 + 2 + read-write + + + REG_PAD15_RDE + Reserved + 2 + 1 + read-write + + + REG_PAD15_RUE + Reserved + 3 + 1 + read-write + + + REG_PAD15_MUX_SEL + 1:use LP GPIO,0: use digital GPIO + 4 + 1 + read-write + + + REG_PAD15_FUN_SEL + function sel + 5 + 2 + read-write + + + REG_PAD15_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 7 + 1 + read-write + + + REG_PAD15_SLP_IE + input enable in sleep mode + 8 + 1 + read-write + + + REG_PAD15_SLP_OE + output enable in sleep mode + 9 + 1 + read-write + + + REG_PAD15_FUN_IE + input enable in work mode + 10 + 1 + read-write + + + REG_PAD15_FILTER_EN + need des + 11 + 1 + read-write + + + + + EXT_WAKEUP0_SEL + Reserved + 0x48 + 0x20 + + + REG_XTL_EXT_CTR_SEL + select LP GPIO 0 ~ 15 to control XTAL + 0 + 5 + read-write + + + REG_EXT_WAKEUP0_SEL + Reserved + 5 + 5 + read-write + + + + + LP_PAD_HOLD + Reserved + 0x4C + 0x20 + + + REG_LP_GPIO_HOLD + Reserved + 0 + 16 + read-write + + + + + LP_PAD_HYS + Reserved + 0x50 + 0x20 + + + REG_LP_GPIO_HYS + Reserved + 0 + 16 + read-write + + + + + + + LP_UART + Low-power UART (Universal Asynchronous Receiver-Transmitter) Controller + LP_UART + 0x50121000 + + 0x0 + 0x84 + registers + + + LP_UART + 16 + + + + FIFO + FIFO data register + 0x0 + 0x20 + + + RXFIFO_RD_BYTE + UART 0 accesses FIFO via this register. + 0 + 8 + read-only + + + + + INT_RAW + Raw interrupt status + 0x4 + 0x20 + 0x00000002 + + + RXFIFO_FULL_INT_RAW + This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies. + 0 + 1 + read-write + + + TXFIFO_EMPTY_INT_RAW + This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies . + 1 + 1 + read-write + + + PARITY_ERR_INT_RAW + This interrupt raw bit turns to high level when receiver detects a parity error in the data. + 2 + 1 + read-write + + + FRM_ERR_INT_RAW + This interrupt raw bit turns to high level when receiver detects a data frame error . + 3 + 1 + read-write + + + RXFIFO_OVF_INT_RAW + This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store. + 4 + 1 + read-write + + + DSR_CHG_INT_RAW + This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal. + 5 + 1 + read-write + + + CTS_CHG_INT_RAW + This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal. + 6 + 1 + read-write + + + BRK_DET_INT_RAW + This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit. + 7 + 1 + read-write + + + RXFIFO_TOUT_INT_RAW + This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte. + 8 + 1 + read-write + + + SW_XON_INT_RAW + This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1. + 9 + 1 + read-write + + + SW_XOFF_INT_RAW + This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1. + 10 + 1 + read-write + + + GLITCH_DET_INT_RAW + This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit. + 11 + 1 + read-write + + + TX_BRK_DONE_INT_RAW + This interrupt raw bit turns to high level when transmitter completes sending NULL characters after all data in Tx-FIFO are sent. + 12 + 1 + read-write + + + TX_BRK_IDLE_DONE_INT_RAW + This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data. + 13 + 1 + read-write + + + TX_DONE_INT_RAW + This interrupt raw bit turns to high level when transmitter has send out all data in FIFO. + 14 + 1 + read-write + + + AT_CMD_CHAR_DET_INT_RAW + This interrupt raw bit turns to high level when receiver detects the configured at_cmd char. + 18 + 1 + read-write + + + WAKEUP_INT_RAW + This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode. + 19 + 1 + read-write + + + + + INT_ST + Masked interrupt status + 0x8 + 0x20 + + + RXFIFO_FULL_INT_ST + This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. + 0 + 1 + read-only + + + TXFIFO_EMPTY_INT_ST + This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1. + 1 + 1 + read-only + + + PARITY_ERR_INT_ST + This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. + 2 + 1 + read-only + + + FRM_ERR_INT_ST + This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1. + 3 + 1 + read-only + + + RXFIFO_OVF_INT_ST + This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. + 4 + 1 + read-only + + + DSR_CHG_INT_ST + This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. + 5 + 1 + read-only + + + CTS_CHG_INT_ST + This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. + 6 + 1 + read-only + + + BRK_DET_INT_ST + This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. + 7 + 1 + read-only + + + RXFIFO_TOUT_INT_ST + This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. + 8 + 1 + read-only + + + SW_XON_INT_ST + This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. + 9 + 1 + read-only + + + SW_XOFF_INT_ST + This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. + 10 + 1 + read-only + + + GLITCH_DET_INT_ST + This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. + 11 + 1 + read-only + + + TX_BRK_DONE_INT_ST + This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. + 12 + 1 + read-only + + + TX_BRK_IDLE_DONE_INT_ST + This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1. + 13 + 1 + read-only + + + TX_DONE_INT_ST + This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. + 14 + 1 + read-only + + + AT_CMD_CHAR_DET_INT_ST + This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1. + 18 + 1 + read-only + + + WAKEUP_INT_ST + This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1. + 19 + 1 + read-only + + + + + INT_ENA + Interrupt enable bits + 0xC + 0x20 + + + RXFIFO_FULL_INT_ENA + This is the enable bit for rxfifo_full_int_st register. + 0 + 1 + read-write + + + TXFIFO_EMPTY_INT_ENA + This is the enable bit for txfifo_empty_int_st register. + 1 + 1 + read-write + + + PARITY_ERR_INT_ENA + This is the enable bit for parity_err_int_st register. + 2 + 1 + read-write + + + FRM_ERR_INT_ENA + This is the enable bit for frm_err_int_st register. + 3 + 1 + read-write + + + RXFIFO_OVF_INT_ENA + This is the enable bit for rxfifo_ovf_int_st register. + 4 + 1 + read-write + + + DSR_CHG_INT_ENA + This is the enable bit for dsr_chg_int_st register. + 5 + 1 + read-write + + + CTS_CHG_INT_ENA + This is the enable bit for cts_chg_int_st register. + 6 + 1 + read-write + + + BRK_DET_INT_ENA + This is the enable bit for brk_det_int_st register. + 7 + 1 + read-write + + + RXFIFO_TOUT_INT_ENA + This is the enable bit for rxfifo_tout_int_st register. + 8 + 1 + read-write + + + SW_XON_INT_ENA + This is the enable bit for sw_xon_int_st register. + 9 + 1 + read-write + + + SW_XOFF_INT_ENA + This is the enable bit for sw_xoff_int_st register. + 10 + 1 + read-write + + + GLITCH_DET_INT_ENA + This is the enable bit for glitch_det_int_st register. + 11 + 1 + read-write + + + TX_BRK_DONE_INT_ENA + This is the enable bit for tx_brk_done_int_st register. + 12 + 1 + read-write + + + TX_BRK_IDLE_DONE_INT_ENA + This is the enable bit for tx_brk_idle_done_int_st register. + 13 + 1 + read-write + + + TX_DONE_INT_ENA + This is the enable bit for tx_done_int_st register. + 14 + 1 + read-write + + + AT_CMD_CHAR_DET_INT_ENA + This is the enable bit for at_cmd_char_det_int_st register. + 18 + 1 + read-write + + + WAKEUP_INT_ENA + This is the enable bit for uart_wakeup_int_st register. + 19 + 1 + read-write + + + + + INT_CLR + Interrupt clear bits + 0x10 + 0x20 + + + RXFIFO_FULL_INT_CLR + Set this bit to clear the rxfifo_full_int_raw interrupt. + 0 + 1 + write-only + + + TXFIFO_EMPTY_INT_CLR + Set this bit to clear txfifo_empty_int_raw interrupt. + 1 + 1 + write-only + + + PARITY_ERR_INT_CLR + Set this bit to clear parity_err_int_raw interrupt. + 2 + 1 + write-only + + + FRM_ERR_INT_CLR + Set this bit to clear frm_err_int_raw interrupt. + 3 + 1 + write-only + + + RXFIFO_OVF_INT_CLR + Set this bit to clear rxfifo_ovf_int_raw interrupt. + 4 + 1 + write-only + + + DSR_CHG_INT_CLR + Set this bit to clear the dsr_chg_int_raw interrupt. + 5 + 1 + write-only + + + CTS_CHG_INT_CLR + Set this bit to clear the cts_chg_int_raw interrupt. + 6 + 1 + write-only + + + BRK_DET_INT_CLR + Set this bit to clear the brk_det_int_raw interrupt. + 7 + 1 + write-only + + + RXFIFO_TOUT_INT_CLR + Set this bit to clear the rxfifo_tout_int_raw interrupt. + 8 + 1 + write-only + + + SW_XON_INT_CLR + Set this bit to clear the sw_xon_int_raw interrupt. + 9 + 1 + write-only + + + SW_XOFF_INT_CLR + Set this bit to clear the sw_xoff_int_raw interrupt. + 10 + 1 + write-only + + + GLITCH_DET_INT_CLR + Set this bit to clear the glitch_det_int_raw interrupt. + 11 + 1 + write-only + + + TX_BRK_DONE_INT_CLR + Set this bit to clear the tx_brk_done_int_raw interrupt.. + 12 + 1 + write-only + + + TX_BRK_IDLE_DONE_INT_CLR + Set this bit to clear the tx_brk_idle_done_int_raw interrupt. + 13 + 1 + write-only + + + TX_DONE_INT_CLR + Set this bit to clear the tx_done_int_raw interrupt. + 14 + 1 + write-only + + + AT_CMD_CHAR_DET_INT_CLR + Set this bit to clear the at_cmd_char_det_int_raw interrupt. + 18 + 1 + write-only + + + WAKEUP_INT_CLR + Set this bit to clear the uart_wakeup_int_raw interrupt. + 19 + 1 + write-only + + + + + CLKDIV_SYNC + Clock divider configuration + 0x14 + 0x20 + 0x000002B6 + + + CLKDIV + The integral part of the frequency divider factor. + 0 + 12 + read-write + + + CLKDIV_FRAG + The decimal part of the frequency divider factor. + 20 + 4 + read-write + + + + + RX_FILT + Rx Filter configuration + 0x18 + 0x20 + 0x00000008 + + + GLITCH_FILT + when input pulse width is lower than this value the pulse is ignored. + 0 + 8 + read-write + + + GLITCH_FILT_EN + Set this bit to enable Rx signal filter. + 8 + 1 + read-write + + + + + STATUS + UART status register + 0x1C + 0x20 + 0xE000C000 + + + RXFIFO_CNT + Stores the byte number of valid data in Rx-FIFO. + 3 + 5 + read-only + + + DSRN + The register represent the level value of the internal uart dsr signal. + 13 + 1 + read-only + + + CTSN + This register represent the level value of the internal uart cts signal. + 14 + 1 + read-only + + + RXD + This register represent the level value of the internal uart rxd signal. + 15 + 1 + read-only + + + TXFIFO_CNT + Stores the byte number of data in Tx-FIFO. + 19 + 5 + read-only + + + DTRN + This bit represents the level of the internal uart dtr signal. + 29 + 1 + read-only + + + RTSN + This bit represents the level of the internal uart rts signal. + 30 + 1 + read-only + + + TXD + This bit represents the level of the internal uart txd signal. + 31 + 1 + read-only + + + + + CONF0_SYNC + Configuration register 0 + 0x20 + 0x20 + 0x0000001C + + + PARITY + This register is used to configure the parity check mode. + 0 + 1 + read-write + + + PARITY_EN + Set this bit to enable uart parity check. + 1 + 1 + read-write + + + BIT_NUM + This register is used to set the length of data. + 2 + 2 + read-write + + + STOP_BIT_NUM + This register is used to set the length of stop bit. + 4 + 2 + read-write + + + TXD_BRK + Set this bit to enbale transmitter to send NULL when the process of sending data is done. + 6 + 1 + read-write + + + LOOPBACK + Set this bit to enable uart loopback test mode. + 12 + 1 + read-write + + + TX_FLOW_EN + Set this bit to enable flow control function for transmitter. + 13 + 1 + read-write + + + RXD_INV + Set this bit to inverse the level value of uart rxd signal. + 15 + 1 + read-write + + + TXD_INV + Set this bit to inverse the level value of uart txd signal. + 16 + 1 + read-write + + + DIS_RX_DAT_OVF + Disable UART Rx data overflow detect. + 17 + 1 + read-write + + + ERR_WR_MASK + 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong. + 18 + 1 + read-write + + + MEM_CLK_EN + UART memory clock gate enable signal. + 20 + 1 + read-write + + + SW_RTS + This register is used to configure the software rts signal which is used in software flow control. + 21 + 1 + read-write + + + RXFIFO_RST + Set this bit to reset the uart receive-FIFO. + 22 + 1 + read-write + + + TXFIFO_RST + Set this bit to reset the uart transmit-FIFO. + 23 + 1 + read-write + + + + + CONF1 + Configuration register 1 + 0x24 + 0x20 + 0x00006060 + + + RXFIFO_FULL_THRHD + It will produce rxfifo_full_int interrupt when receiver receives more data than this register value. + 3 + 5 + read-write + + + TXFIFO_EMPTY_THRHD + It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value. + 11 + 5 + read-write + + + CTS_INV + Set this bit to inverse the level value of uart cts signal. + 16 + 1 + read-write + + + DSR_INV + Set this bit to inverse the level value of uart dsr signal. + 17 + 1 + read-write + + + RTS_INV + Set this bit to inverse the level value of uart rts signal. + 18 + 1 + read-write + + + DTR_INV + Set this bit to inverse the level value of uart dtr signal. + 19 + 1 + read-write + + + SW_DTR + This register is used to configure the software dtr signal which is used in software flow control. + 20 + 1 + read-write + + + CLK_EN + 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers. + 21 + 1 + read-write + + + + + HWFC_CONF_SYNC + Hardware flow-control configuration + 0x2C + 0x20 + + + RX_FLOW_THRHD + This register is used to configure the maximum amount of data that can be received when hardware flow control works. + 3 + 5 + read-write + + + RX_FLOW_EN + This is the flow enable bit for UART receiver. + 8 + 1 + read-write + + + + + SLEEP_CONF0 + UART sleep configure register 0 + 0x30 + 0x20 + + + WK_CHAR1 + This register restores the specified wake up char1 to wake up + 0 + 8 + read-write + + + WK_CHAR2 + This register restores the specified wake up char2 to wake up + 8 + 8 + read-write + + + WK_CHAR3 + This register restores the specified wake up char3 to wake up + 16 + 8 + read-write + + + WK_CHAR4 + This register restores the specified wake up char4 to wake up + 24 + 8 + read-write + + + + + SLEEP_CONF1 + UART sleep configure register 1 + 0x34 + 0x20 + + + WK_CHAR0 + This register restores the specified char0 to wake up + 0 + 8 + read-write + + + + + SLEEP_CONF2 + UART sleep configure register 2 + 0x38 + 0x20 + 0x001420F0 + + + ACTIVE_THRESHOLD + The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value. + 0 + 10 + read-write + + + RX_WAKE_UP_THRHD + In wake up mode 1 this field is used to set the received data number threshold to wake up chip. + 13 + 5 + read-write + + + WK_CHAR_NUM + This register is used to select number of wake up char. + 18 + 3 + read-write + + + WK_CHAR_MASK + This register is used to mask wake up char. + 21 + 5 + read-write + + + WK_MODE_SEL + This register is used to select wake up mode. 0: RXD toggling to wake up. 1: received data number larger than + 26 + 2 + read-write + + + + + SWFC_CONF0_SYNC + Software flow-control character configuration + 0x3C + 0x20 + 0x00001311 + + + XON_CHAR + This register stores the Xon flow control char. + 0 + 8 + read-write + + + XOFF_CHAR + This register stores the Xoff flow control char. + 8 + 8 + read-write + + + XON_XOFF_STILL_SEND + In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In this status, UART Tx can not transmit XOFF even the received data number is larger than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when UART Tx is disabled. + 16 + 1 + read-write + + + SW_FLOW_CON_EN + Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff. + 17 + 1 + read-write + + + XONOFF_DEL + Set this bit to remove flow control char from the received data. + 18 + 1 + read-write + + + FORCE_XON + Set this bit to enable the transmitter to go on sending data. + 19 + 1 + read-write + + + FORCE_XOFF + Set this bit to stop the transmitter from sending data. + 20 + 1 + read-write + + + SEND_XON + Set this bit to send Xon char. It is cleared by hardware automatically. + 21 + 1 + read-write + + + SEND_XOFF + Set this bit to send Xoff char. It is cleared by hardware automatically. + 22 + 1 + read-write + + + + + SWFC_CONF1 + Software flow-control character configuration + 0x40 + 0x20 + 0x00006000 + + + XON_THRESHOLD + When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1 it will send a Xon char. + 3 + 5 + read-write + + + XOFF_THRESHOLD + When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1 it will send a Xoff char. + 11 + 5 + read-write + + + + + TXBRK_CONF_SYNC + Tx Break character configuration + 0x44 + 0x20 + 0x0000000A + + + TX_BRK_NUM + This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1. + 0 + 8 + read-write + + + + + IDLE_CONF_SYNC + Frame-end idle configuration + 0x48 + 0x20 + 0x00040100 + + + RX_IDLE_THRHD + It will produce frame end signal when receiver takes more time to receive one byte data than this register value. + 0 + 10 + read-write + + + TX_IDLE_NUM + This register is used to configure the duration time between transfers. + 10 + 10 + read-write + + + + + RS485_CONF_SYNC + RS485 mode configuration + 0x4C + 0x20 + + + DL0_EN + Set this bit to delay the stop bit by 1 bit. + 1 + 1 + read-write + + + DL1_EN + Set this bit to delay the stop bit by 1 bit. + 2 + 1 + read-write + + + + + AT_CMD_PRECNT_SYNC + Pre-sequence timing configuration + 0x50 + 0x20 + 0x00000901 + + + PRE_IDLE_NUM + This register is used to configure the idle duration time before the first at_cmd is received by receiver. + 0 + 16 + read-write + + + + + AT_CMD_POSTCNT_SYNC + Post-sequence timing configuration + 0x54 + 0x20 + 0x00000901 + + + POST_IDLE_NUM + This register is used to configure the duration time between the last at_cmd and the next data. + 0 + 16 + read-write + + + + + AT_CMD_GAPTOUT_SYNC + Timeout configuration + 0x58 + 0x20 + 0x0000000B + + + RX_GAP_TOUT + This register is used to configure the duration time between the at_cmd chars. + 0 + 16 + read-write + + + + + AT_CMD_CHAR_SYNC + AT escape sequence detection configuration + 0x5C + 0x20 + 0x0000032B + + + AT_CMD_CHAR + This register is used to configure the content of at_cmd char. + 0 + 8 + read-write + + + CHAR_NUM + This register is used to configure the num of continuous at_cmd chars received by receiver. + 8 + 8 + read-write + + + + + MEM_CONF + UART memory power configuration + 0x60 + 0x20 + + + MEM_FORCE_PD + Set this bit to force power down UART memory. + 25 + 1 + read-write + + + MEM_FORCE_PU + Set this bit to force power up UART memory. + 26 + 1 + read-write + + + + + TOUT_CONF_SYNC + UART threshold and allocation configuration + 0x64 + 0x20 + 0x00000028 + + + RX_TOUT_EN + This is the enble bit for uart receiver's timeout function. + 0 + 1 + read-write + + + RX_TOUT_FLOW_DIS + Set this bit to stop accumulating idle_cnt when hardware flow control works. + 1 + 1 + read-write + + + RX_TOUT_THRHD + This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1. + 2 + 10 + read-write + + + + + MEM_TX_STATUS + Tx-SRAM write and read offset address. + 0x68 + 0x20 + + + TX_SRAM_WADDR + This register stores the offset write address in Tx-SRAM. + 3 + 5 + read-only + + + TX_SRAM_RADDR + This register stores the offset read address in Tx-SRAM. + 12 + 5 + read-only + + + + + MEM_RX_STATUS + Rx-SRAM write and read offset address. + 0x6C + 0x20 + 0x00010080 + + + RX_SRAM_RADDR + This register stores the offset read address in RX-SRAM. + 3 + 5 + read-only + + + RX_SRAM_WADDR + This register stores the offset write address in Rx-SRAM. + 12 + 5 + read-only + + + + + FSM_STATUS + UART transmit and receive status. + 0x70 + 0x20 + + + ST_URX_OUT + This is the status register of receiver. + 0 + 4 + read-only + + + ST_UTX_OUT + This is the status register of transmitter. + 4 + 4 + read-only + + + + + CLK_CONF + UART core clock configuration + 0x88 + 0x20 + 0x03000000 + + + TX_SCLK_EN + Set this bit to enable UART Tx clock. + 24 + 1 + read-write + + + RX_SCLK_EN + Set this bit to enable UART Rx clock. + 25 + 1 + read-write + + + TX_RST_CORE + Write 1 then write 0 to this bit to reset UART Tx. + 26 + 1 + read-write + + + RX_RST_CORE + Write 1 then write 0 to this bit to reset UART Rx. + 27 + 1 + read-write + + + + + DATE + UART Version register + 0x8C + 0x20 + 0x02305050 + + + DATE + This is the version register. + 0 + 32 + read-write + + + + + AFIFO_STATUS + UART AFIFO Status + 0x90 + 0x20 + 0x0000000A + + + TX_AFIFO_FULL + Full signal of APB TX AFIFO. + 0 + 1 + read-only + + + TX_AFIFO_EMPTY + Empty signal of APB TX AFIFO. + 1 + 1 + read-only + + + RX_AFIFO_FULL + Full signal of APB RX AFIFO. + 2 + 1 + read-only + + + RX_AFIFO_EMPTY + Empty signal of APB RX AFIFO. + 3 + 1 + read-only + + + + + REG_UPDATE + UART Registers Configuration Update register + 0x98 + 0x20 + + + REG_UPDATE + Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done. + 0 + 1 + read-write + + + + + ID + UART ID register + 0x9C + 0x20 + 0x00000500 + + + ID + This register is used to configure the uart_id. + 0 + 32 + read-write + + + + + + + MCPWM0 + Motor Control Pulse-Width Modulation 0 + MCPWM + 0x500C0000 + + 0x0 + 0x14C + registers + + + PWM0 + 38 + + + + CLK_CFG + PWM clock prescaler register. + 0x0 + 0x20 + + + CLK_PRESCALE + Configures the prescaler value of clock, so that the period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1). + 0 + 8 + read-write + + + + + 3 + 0x10 + TIMER%s_CFG0 + PWM timer%s period and update method configuration register. + 0x4 + 0x20 + 0x0000FF00 + + + TIMER_PRESCALE + Configures the prescaler value of timer%s, so that the period of PT0_clk = Period of PWM_clk * (PWM_TIMER%s_PRESCALE + 1) + 0 + 8 + read-write + + + TIMER_PERIOD + Configures the period shadow of PWM timer%s + 8 + 16 + read-write + + + TIMER_PERIOD_UPMETHOD + Configures the update method for active register of PWM timer%s period.\\0: Immediate\\1: TEZ\\2: Sync\\3: TEZ or sync\\TEZ here and below means timer equal zero event + 24 + 2 + read-write + + + + + 3 + 0x10 + TIMER%s_CFG1 + PWM timer%s working mode and start/stop control register. + 0x8 + 0x20 + + + TIMER_START + Configures whether or not to start/stop PWM timer%s.\\0: If PWM timer%s starts, then stops at TEZ\\1: If timer%s starts, then stops at TEP\\2: PWM timer%s starts and runs on\\3: Timer%s starts and stops at the next TEZ\\4: Timer0 starts and stops at the next TEP.\\TEP here and below means the event that happens when the timer equals to period + 0 + 3 + read-write + + + TIMER_MOD + Configures the working mode of PWM timer%s.\\0: Freeze\\1: Increase mode\\2: Decrease mode\\3: Up-down mode + 3 + 2 + read-write + + + + + 3 + 0x10 + TIMER%s_SYNC + PWM timer%s sync function configuration register. + 0xC + 0x20 + + + TIMER_SYNCI_EN + Configures whether or not to enable timer%s reloading with phase on sync input event is enabled.\\0: Disable\\1: Enable + 0 + 1 + read-write + + + SW + Configures the generation of software sync. Toggling this bit will trigger a software sync. + 1 + 1 + read-write + + + TIMER_SYNCO_SEL + Configures the selection of PWM timer%s sync_out.\\0: Sync_in\\1: TEZ\\2: TEP\\3: Invalid, sync_out selects noting + 2 + 2 + read-write + + + TIMER_PHASE + Configures the phase for timer%s reload on sync event. + 4 + 16 + read-write + + + TIMER_PHASE_DIRECTION + Configures the PWM timer%s's direction when timer%s mode is up-down mode.\\0: Increase\\1: Decrease + 20 + 1 + read-write + + + + + 3 + 0x10 + TIMER%s_STATUS + PWM timer%s status register. + 0x10 + 0x20 + + + TIMER_VALUE + Represents current PWM timer%s counter value. + 0 + 16 + read-only + + + TIMER_DIRECTION + Represents current PWM timer%s counter direction.\\0: Increment\\1: Decrement + 16 + 1 + read-only + + + + + TIMER_SYNCI_CFG + Synchronization input selection register for PWM timers. + 0x34 + 0x20 + + + TIMER0_SYNCISEL + Configures the selection of sync input for PWM timer0.\\1: PWM timer0 sync_out\\2: PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1 from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected + 0 + 3 + read-write + + + TIMER1_SYNCISEL + Configures the selection of sync input for PWM timer1.\\1: PWM timer0 sync_out\\2: PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1 from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected + 3 + 3 + read-write + + + TIMER2_SYNCISEL + Configures the selection of sync input for PWM timer2.\\1: PWM timer0 sync_out\\2: PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1 from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected + 6 + 3 + read-write + + + EXTERNAL_SYNCI0_INVERT + Configures whether or not to invert SYNC0 from GPIO matrix.\\0: Not invert\\1: Invert + 9 + 1 + read-write + + + EXTERNAL_SYNCI1_INVERT + Configures whether or not to invert SYNC1 from GPIO matrix.\\0: Not invert\\1: Invert + 10 + 1 + read-write + + + EXTERNAL_SYNCI2_INVERT + Configures whether or not to invert SYNC2 from GPIO matrix.\\0: Not invert\\1: Invert + 11 + 1 + read-write + + + + + OPERATOR_TIMERSEL + PWM operator's timer select register + 0x38 + 0x20 + + + OPERATOR0_TIMERSEL + Configures which PWM timer will be the timing reference for PWM operator0.\\0: Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2 + 0 + 2 + read-write + + + OPERATOR1_TIMERSEL + Configures which PWM timer will be the timing reference for PWM operator1.\\0: Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2 + 2 + 2 + read-write + + + OPERATOR2_TIMERSEL + Configures which PWM timer will be the timing reference for PWM operator2.\\0: Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2 + 4 + 2 + read-write + + + + + 3 + 0x38 + GEN%s_STMP_CFG + Generator%s time stamp registers A and B transfer status and update method register + 0x3C + 0x20 + + + CMPR_A_UPMETHOD + Configures the update method for PWM generator %s time stamp A's active register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: Sync\\Bit3 is set to 1: Disable the update + 0 + 4 + read-write + + + CMPR_B_UPMETHOD + Configures the update method for PWM generator %s time stamp B's active register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: Sync\\Bit3 is set to 1: Disable the update + 4 + 4 + read-write + + + CMPR_A_SHDW_FULL + Represents whether or not generator%s time stamp A's shadow reg is transferred.\\0: A's active reg has been updated with shadow register latest value.\\1: A's shadow reg is filled and waiting to be transferred to A's active reg + 8 + 1 + read-write + + + CMPR_B_SHDW_FULL + Represents whether or not generator%s time stamp B's shadow reg is transferred.\\0: B's active reg has been updated with shadow register latest value.\\1: B's shadow reg is filled and waiting to be transferred to B's active reg + 9 + 1 + read-write + + + + + 3 + 0x38 + GEN%s_TSTMP_A + Generator%s time stamp A's shadow register + 0x40 + 0x20 + + + CMPR_A + Configures the value of PWM generator %s time stamp A's shadow register. + 0 + 16 + read-write + + + + + 3 + 0x38 + GEN%s_TSTMP_B + Generator%s time stamp B's shadow register + 0x44 + 0x20 + + + CMPR_B + Configures the value of PWM generator %s time stamp B's shadow register. + 0 + 16 + read-write + + + + + 3 + 0x38 + GEN%s_CFG0 + Generator%s fault event T0 and T1 configuration register + 0x48 + 0x20 + + + GEN_CFG_UPMETHOD + Configures update method for PWM generator %s's active register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: Sync\\Bit3 is set to 1: Disable the update + 0 + 4 + read-write + + + GEN_T0_SEL + Configures source selection for PWM generator %s event_t0, take effect immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4: Invalid, Select nothing + 4 + 3 + read-write + + + GEN_T1_SEL + Configures source selection for PWM generator %s event_t1, take effect immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4: Invalid, Select nothing + 7 + 3 + read-write + + + + + 3 + 0x38 + GEN%s_FORCE + Generator%s output signal force mode register. + 0x4C + 0x20 + 0x00000020 + + + GEN_CNTUFORCE_UPMETHOD + Configures update method for continuous software force of PWM generator%s.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: TEA\\Bit3 is set to 1: TEB\\Bit4 is set to 1: Sync\\Bit5 is set to 1: Disable update. TEA/B here and below means an event generated when the timer's value equals to that of register A/B. + 0 + 6 + read-write + + + GEN_A_CNTUFORCE_MODE + Configures continuous software force mode for PWM%s A.\\0: Disabled\\1: Low\\2: High\\3: Disabled + 6 + 2 + read-write + + + GEN_B_CNTUFORCE_MODE + Configures continuous software force mode for PWM%s B.\\0: Disabled\\1: Low\\2: High\\3: Disabled + 8 + 2 + read-write + + + GEN_A_NCIFORCE + Configures the generation of non-continuous immediate software-force event for PWM%s A, a toggle will trigger a force event. + 10 + 1 + read-write + + + GEN_A_NCIFORCE_MODE + Configures non-continuous immediate software force mode for PWM%s A.\\0: Disabled\\1: Low\\2: High\\3: Disabled + 11 + 2 + read-write + + + GEN_B_NCIFORCE + Configures the generation of non-continuous immediate software-force event for PWM%s B, a toggle will trigger a force event. + 13 + 1 + read-write + + + GEN_B_NCIFORCE_MODE + Configures non-continuous immediate software force mode for PWM%s B.\\0: Disabled\\1: Low\\2: High\\3: Disabled + 14 + 2 + read-write + + + + + 3 + 0x38 + GEN%s_A + PWM%s output signal A actions configuration register + 0x50 + 0x20 + + + UTEZ + Configures action on PWM%s A triggered by event TEZ when timer increasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 0 + 2 + read-write + + + UTEP + Configures action on PWM%s A triggered by event TEP when timer increasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 2 + 2 + read-write + + + UTEA + Configures action on PWM%s A triggered by event TEA when timer increasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 4 + 2 + read-write + + + UTEB + Configures action on PWM%s A triggered by event TEB when timer increasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 6 + 2 + read-write + + + UT0 + Configures action on PWM%s A triggered by event_t0 when timer increasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 8 + 2 + read-write + + + UT1 + Configures action on PWM%s A triggered by event_t1 when timer increasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 10 + 2 + read-write + + + DTEZ + Configures action on PWM%s A triggered by event TEZ when timer decreasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 12 + 2 + read-write + + + DTEP + Configures action on PWM%s A triggered by event TEP when timer decreasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 14 + 2 + read-write + + + DTEA + Configures action on PWM%s A triggered by event TEA when timer decreasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 16 + 2 + read-write + + + DTEB + Configures action on PWM%s A triggered by event TEB when timer decreasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 18 + 2 + read-write + + + DT0 + Configures action on PWM%s A triggered by event_t0 when timer decreasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 20 + 2 + read-write + + + DT1 + Configures action on PWM%s A triggered by event_t1 when timer decreasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 22 + 2 + read-write + + + + + 3 + 0x38 + GEN%s_B + PWM%s output signal B actions configuration register + 0x54 + 0x20 + + + UTEZ + Configures action on PWM%s B triggered by event TEZ when timer increasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 0 + 2 + read-write + + + UTEP + Configures action on PWM%s B triggered by event TEP when timer increasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 2 + 2 + read-write + + + UTEA + Configures action on PWM%s B triggered by event TEA when timer increasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 4 + 2 + read-write + + + UTEB + Configures action on PWM%s B triggered by event TEB when timer increasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 6 + 2 + read-write + + + UT0 + Configures action on PWM%s B triggered by event_t0 when timer increasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 8 + 2 + read-write + + + UT1 + Configures action on PWM%s B triggered by event_t1 when timer increasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 10 + 2 + read-write + + + DTEZ + Configures action on PWM%s B triggered by event TEZ when timer decreasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 12 + 2 + read-write + + + DTEP + Configures action on PWM%s B triggered by event TEP when timer decreasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 14 + 2 + read-write + + + DTEA + Configures action on PWM%s B triggered by event TEA when timer decreasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 16 + 2 + read-write + + + DTEB + Configures action on PWM%s B triggered by event TEB when timer decreasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 18 + 2 + read-write + + + DT0 + Configures action on PWM%s B triggered by event_t0 when timer decreasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 20 + 2 + read-write + + + DT1 + Configures action on PWM%s B triggered by event_t1 when timer decreasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 22 + 2 + read-write + + + + + 3 + 0x38 + DT%s_CFG + Dead time configuration register + 0x58 + 0x20 + 0x00018000 + + + DB_FED_UPMETHOD + Configures update method for FED (Falling edge delay) active register.\\0: Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: Sync\\Bit3 is set to 1: Disable the update + 0 + 4 + read-write + + + DB_RED_UPMETHOD + Configures update method for RED (rising edge delay) active register.\\0: Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: Sync\\Bit3 is set to 1: Disable the update + 4 + 4 + read-write + + + DB_DEB_MODE + Configures S8 in table, dual-edge B mode.\\0: fed/red take effect on different path separately\\1: fed/red take effect on B path, A out is in bypass or dulpB mode + 8 + 1 + read-write + + + DB_A_OUTSWAP + Configures S6 in table. + 9 + 1 + read-write + + + DB_B_OUTSWAP + Configures S7 in table. + 10 + 1 + read-write + + + DB_RED_INSEL + Configures S4 in table. + 11 + 1 + read-write + + + DB_FED_INSEL + Configures S5 in table. + 12 + 1 + read-write + + + DB_RED_OUTINVERT + Configures S2 in table. + 13 + 1 + read-write + + + DB_FED_OUTINVERT + Configures S3 in table. + 14 + 1 + read-write + + + DB_A_OUTBYPASS + Configures S1 in table. + 15 + 1 + read-write + + + DB_B_OUTBYPASS + Configures S0 in table. + 16 + 1 + read-write + + + DB_CLK_SEL + Configures dead time generator %s clock selection.\\0: PWM_clk\\1: PT_clk + 17 + 1 + read-write + + + + + 3 + 0x38 + DT%s_FED_CFG + Falling edge delay (FED) shadow register + 0x5C + 0x20 + + + DB_FED + Configures shadow register for FED. + 0 + 16 + read-write + + + + + 3 + 0x38 + DT%s_RED_CFG + Rising edge delay (RED) shadow register + 0x60 + 0x20 + + + DB_RED + Configures shadow register for RED. + 0 + 16 + read-write + + + + + 3 + 0x38 + CARRIER%s_CFG + Carrier%s configuration register + 0x64 + 0x20 + + + CHOPPER_EN + Configures whether or not to enable carrier%s.\\0: Bypassed\\1: Enabled + 0 + 1 + read-write + + + CHOPPER_PRESCALE + Configures the prescale value of PWM carrier%s clock (PC_clk), so that period of PC_clk = period of PWM_clk * (PWM_CARRIER%s_PRESCALE + 1) + 1 + 4 + read-write + + + CHOPPER_DUTY + Configures carrier duty. Duty = PWM_CARRIER%s_DUTY / 8 + 5 + 3 + read-write + + + CHOPPER_OSHTWTH + Configures width of the first pulse. Measurement unit: Periods of the carrier. + 8 + 4 + read-write + + + CHOPPER_OUT_INVERT + Configures whether or not to invert the output of PWM%s A and PWM%s B for this submodule.\\0: Normal\\1: Invert + 12 + 1 + read-write + + + CHOPPER_IN_INVERT + Configures whether or not to invert the input of PWM%s A and PWM%s B for this submodule.\\0: Normal\\1: Invert + 13 + 1 + read-write + + + + + 3 + 0x38 + FH%s_CFG0 + PWM%s A and PWM%s B trip events actions configuration register + 0x68 + 0x20 + + + TZ_SW_CBC + Configures whether or not to enable software force cycle-by-cycle mode action.\\0: Disable\\1: Enable + 0 + 1 + read-write + + + TZ_F2_CBC + Configures whether or not event_f2 will trigger cycle-by-cycle mode action.\\0: Disable\\1: Enable + 1 + 1 + read-write + + + TZ_F1_CBC + Configures whether or not event_f1 will trigger cycle-by-cycle mode action.\\0: Disable\\1: Enable + 2 + 1 + read-write + + + TZ_F0_CBC + Configures whether or not event_f0 will trigger cycle-by-cycle mode action.\\0: Disable\\1: Enable + 3 + 1 + read-write + + + TZ_SW_OST + Configures whether or not to enable software force one-shot mode action.\\0: Disable\\1: Enable + 4 + 1 + read-write + + + TZ_F2_OST + Configures whether or not event_f2 will trigger one-shot mode action.\\0: Disable\\1: Enable + 5 + 1 + read-write + + + TZ_F1_OST + Configures whether or not event_f1 will trigger one-shot mode action.\\0: Disable\\1: Enable + 6 + 1 + read-write + + + TZ_F0_OST + Configures whether or not event_f0 will trigger one-shot mode action.\\0: Disable\\1: Enable + 7 + 1 + read-write + + + TZ_A_CBC_D + Configures cycle-by-cycle mode action on PWM%s A when fault event occurs and timer is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + 8 + 2 + read-write + + + TZ_A_CBC_U + Configures cycle-by-cycle mode action on PWM%s A when fault event occurs and timer is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + 10 + 2 + read-write + + + TZ_A_OST_D + Configures one-shot mode action on PWM%s A when fault event occurs and timer is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + 12 + 2 + read-write + + + TZ_A_OST_U + Configures one-shot mode action on PWM%s A when fault event occurs and timer is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + 14 + 2 + read-write + + + TZ_B_CBC_D + Configures cycle-by-cycle mode action on PWM%s B when fault event occurs and timer is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + 16 + 2 + read-write + + + TZ_B_CBC_U + Configures cycle-by-cycle mode action on PWM%s B when fault event occurs and timer is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + 18 + 2 + read-write + + + TZ_B_OST_D + Configures one-shot mode action on PWM%s B when fault event occurs and timer is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + 20 + 2 + read-write + + + TZ_B_OST_U + Configures one-shot mode action on PWM%s B when fault event occurs and timer is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + 22 + 2 + read-write + + + + + 3 + 0x38 + FH%s_CFG1 + Software triggers for fault handler actions configuration register + 0x6C + 0x20 + + + TZ_CLR_OST + Configures the generation of software one-shot mode action clear. A toggle (software negate its value) triggers a clear for on going one-shot mode action. + 0 + 1 + read-write + + + TZ_CBCPULSE + Configures the refresh moment selection of cycle-by-cycle mode action.\\0: Select nothing, will not refresh\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP + 1 + 2 + read-write + + + TZ_FORCE_CBC + Configures the generation of software cycle-by-cycle mode action. A toggle (software negate its value) triggers a cycle-by-cycle mode action. + 3 + 1 + read-write + + + TZ_FORCE_OST + Configures the generation of software one-shot mode action. A toggle (software negate its value) triggers a one-shot mode action. + 4 + 1 + read-write + + + + + 3 + 0x38 + FH%s_STATUS + Fault events status register + 0x70 + 0x20 + + + TZ_CBC_ON + Represents whether or not an cycle-by-cycle mode action is on going.\\0:No action\\1: On going + 0 + 1 + read-only + + + TZ_OST_ON + Represents whether or not an one-shot mode action is on going.\\0:No action\\1: On going + 1 + 1 + read-only + + + + + FAULT_DETECT + Fault detection configuration and status register + 0xE4 + 0x20 + + + F0_EN + Configures whether or not to enable event_f0 generation.\\0: Disable\\1: Enable + 0 + 1 + read-write + + + F1_EN + Configures whether or not to enable event_f1 generation.\\0: Disable\\1: Enable + 1 + 1 + read-write + + + F2_EN + Configures whether or not to enable event_f2 generation.\\0: Disable\\1: Enable + 2 + 1 + read-write + + + F0_POLE + Configures event_f0 trigger polarity on FAULT0 source from GPIO matrix.\\0: Level low\\1: Level high + 3 + 1 + read-write + + + F1_POLE + Configures event_f1 trigger polarity on FAULT1 source from GPIO matrix.\\0: Level low\\1: Level high + 4 + 1 + read-write + + + F2_POLE + Configures event_f2 trigger polarity on FAULT2 source from GPIO matrix.\\0: Level low\\1: Level high + 5 + 1 + read-write + + + EVENT_F0 + Represents whether or not an event_f0 is on going.\\0: No action\\1: On going + 6 + 1 + read-only + + + EVENT_F1 + Represents whether or not an event_f1 is on going.\\0: No action\\1: On going + 7 + 1 + read-only + + + EVENT_F2 + Represents whether or not an event_f2 is on going.\\0: No action\\1: On going + 8 + 1 + read-only + + + + + CAP_TIMER_CFG + Capture timer configuration register + 0xE8 + 0x20 + + + CAP_TIMER_EN + Configures whether or not to enable capture timer increment.\\0: Disable\\1: Enable + 0 + 1 + read-write + + + CAP_SYNCI_EN + Configures whether or not to enable capture timer sync.\\0: Disable\\1: Enable + 1 + 1 + read-write + + + CAP_SYNCI_SEL + Configures the selection of capture module sync input.\\0: None\\1: Timer0 sync_out\\2: Timer1 sync_out\\3: Timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1 from GPIO matrix\\6: SYNC2 from GPIO matrix\\7: None + 2 + 3 + read-write + + + CAP_SYNC_SW + Configures the generation of a capture timer sync when reg_cap_synci_en is 1.\\0: Invalid, No effect\\1: Trigger a capture timer sync, capture timer is loaded with value in phase register + 5 + 1 + write-only + + + + + CAP_TIMER_PHASE + Capture timer sync phase register + 0xEC + 0x20 + + + CAP_PHASE + Configures phase value for capture timer sync operation. + 0 + 32 + read-write + + + + + 3 + 0x4 + CAP_CH%s_CFG + Capture channel %s configuration register + 0xF0 + 0x20 + + + CAP_EN + Configures whether or not to enable capture on channel %s.\\0: Disable\\1: Enable + 0 + 1 + read-write + + + CAP_MODE + Configures which edge of capture on channel %s after prescaling is used.\\0: None\\Bit0 is set to 1: Rnable capture on the negative edge\\Bit1 is set to 1: Enable capture on the positive edge + 1 + 2 + read-write + + + CAP_PRESCALE + Configures prescale value on possitive edge of CAP%s. Prescale value = PWM_CAP%s_PRESCALE + 1 + 3 + 8 + read-write + + + CAP_IN_INVERT + Configures whether or not to invert CAP%s from GPIO matrix before prescale.\\0: Normal\\1: Invert + 11 + 1 + read-write + + + CAP_SW + Configures the generation of software capture.\\0: Invalid, No effect\\1: Trigger a software forced capture on channel %s + 12 + 1 + write-only + + + + + 3 + 0x4 + CAP_CH%s + CAP%s capture value register + 0xFC + 0x20 + + + CAP_VALUE + Represents value of last capture on CAP%s + 0 + 32 + read-only + + + + + CAP_STATUS + Last capture trigger edge information register + 0x108 + 0x20 + + + CAP0_EDGE + Represents edge of last capture trigger on channel0.\\0: Posedge\\1: Negedge + 0 + 1 + read-only + + + CAP1_EDGE + Represents edge of last capture trigger on channel1.\\0: Posedge\\1: Negedge + 1 + 1 + read-only + + + CAP2_EDGE + Represents edge of last capture trigger on channel2.\\0: Posedge\\1: Negedge + 2 + 1 + read-only + + + + + UPDATE_CFG + Generator Update configuration register + 0x10C + 0x20 + 0x00000005 + + + GLOBAL_UP_EN + Configures whether or not to enable global update for all active registers in MCPWM module.\\0: Disable\\1: Enable + 0 + 1 + read-write + + + GLOBAL_FORCE_UP + Configures the generation of global forced update for all active registers in MCPWM module. A toggle (software invert its value) will trigger a global forced update. Valid only when MCPWM_GLOBAL_UP_EN and MCPWM_OP0/1/2_UP_EN are both set to 1. + 1 + 1 + read-write + + + OP0_UP_EN + Configures whether or not to enable update of active registers in PWM operator0. Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable + 2 + 1 + read-write + + + OP0_FORCE_UP + Configures the generation of forced update for active registers in PWM operator0. A toggle (software invert its value) will trigger a forced update. Valid only when MCPWM_GLOBAL_UP_EN and MCPWM_OP0_UP_EN are both set to 1. + 3 + 1 + read-write + + + OP1_UP_EN + Configures whether or not to enable update of active registers in PWM operator1. Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable + 4 + 1 + read-write + + + OP1_FORCE_UP + Configures the generation of forced update for active registers in PWM operator1. A toggle (software invert its value) will trigger a forced update. Valid only when MCPWM_GLOBAL_UP_EN and MCPWM_OP1_UP_EN are both set to 1. + 5 + 1 + read-write + + + OP2_UP_EN + Configures whether or not to enable update of active registers in PWM operator2. Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable + 6 + 1 + read-write + + + OP2_FORCE_UP + Configures the generation of forced update for active registers in PWM operator2. A toggle (software invert its value) will trigger a forced update. Valid only when MCPWM_GLOBAL_UP_EN and MCPWM_OP2_UP_EN are both set to 1. + 7 + 1 + read-write + + + + + INT_ENA + Interrupt enable register + 0x110 + 0x20 + + + TIMER0_STOP_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered when the timer 0 stops. + 0 + 1 + read-write + + + TIMER1_STOP_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered when the timer 1 stops. + 1 + 1 + read-write + + + TIMER2_STOP_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered when the timer 2 stops. + 2 + 1 + read-write + + + TIMER0_TEZ_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEZ event. + 3 + 1 + read-write + + + TIMER1_TEZ_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEZ event. + 4 + 1 + read-write + + + TIMER2_TEZ_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEZ event. + 5 + 1 + read-write + + + TIMER0_TEP_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEP event. + 6 + 1 + read-write + + + TIMER1_TEP_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEP event. + 7 + 1 + read-write + + + TIMER2_TEP_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEP event. + 8 + 1 + read-write + + + FAULT0_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered when event_f0 starts. + 9 + 1 + read-write + + + FAULT1_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered when event_f1 starts. + 10 + 1 + read-write + + + FAULT2_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered when event_f2 starts. + 11 + 1 + read-write + + + FAULT0_CLR_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered when event_f0 clears. + 12 + 1 + read-write + + + FAULT1_CLR_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered when event_f1 clears. + 13 + 1 + read-write + + + FAULT2_CLR_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered when event_f2 clears. + 14 + 1 + read-write + + + CMPR0_TEA_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEA event. + 15 + 1 + read-write + + + CMPR1_TEA_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEA event. + 16 + 1 + read-write + + + CMPR2_TEA_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEA event. + 17 + 1 + read-write + + + CMPR0_TEB_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEB event. + 18 + 1 + read-write + + + CMPR1_TEB_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEB event. + 19 + 1 + read-write + + + CMPR2_TEB_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEB event. + 20 + 1 + read-write + + + TZ0_CBC_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode action on PWM0. + 21 + 1 + read-write + + + TZ1_CBC_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode action on PWM1. + 22 + 1 + read-write + + + TZ2_CBC_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode action on PWM2. + 23 + 1 + read-write + + + TZ0_OST_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on PWM0. + 24 + 1 + read-write + + + TZ1_OST_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on PWM1. + 25 + 1 + read-write + + + TZ2_OST_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on PWM2. + 26 + 1 + read-write + + + CAP0_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered by capture on CAP0. + 27 + 1 + read-write + + + CAP1_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered by capture on CAP1. + 28 + 1 + read-write + + + CAP2_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered by capture on CAP2. + 29 + 1 + read-write + + + + + INT_RAW + Interrupt raw status register + 0x114 + 0x20 + + + TIMER0_STOP_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered when the timer 0 stops. + 0 + 1 + read-write + + + TIMER1_STOP_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered when the timer 1 stops. + 1 + 1 + read-write + + + TIMER2_STOP_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered when the timer 2 stops. + 2 + 1 + read-write + + + TIMER0_TEZ_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 0 TEZ event. + 3 + 1 + read-write + + + TIMER1_TEZ_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 1 TEZ event. + 4 + 1 + read-write + + + TIMER2_TEZ_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 2 TEZ event. + 5 + 1 + read-write + + + TIMER0_TEP_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 0 TEP event. + 6 + 1 + read-write + + + TIMER1_TEP_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 1 TEP event. + 7 + 1 + read-write + + + TIMER2_TEP_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 2 TEP event. + 8 + 1 + read-write + + + FAULT0_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered when event_f0 starts. + 9 + 1 + read-write + + + FAULT1_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered when event_f1 starts. + 10 + 1 + read-write + + + FAULT2_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered when event_f2 starts. + 11 + 1 + read-write + + + FAULT0_CLR_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered when event_f0 clears. + 12 + 1 + read-write + + + FAULT1_CLR_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered when event_f1 clears. + 13 + 1 + read-write + + + FAULT2_CLR_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered when event_f2 clears. + 14 + 1 + read-write + + + CMPR0_TEA_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 0 TEA event + 15 + 1 + read-write + + + CMPR1_TEA_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 1 TEA event + 16 + 1 + read-write + + + CMPR2_TEA_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 2 TEA event + 17 + 1 + read-write + + + CMPR0_TEB_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 0 TEB event + 18 + 1 + read-write + + + CMPR1_TEB_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 1 TEB event + 19 + 1 + read-write + + + CMPR2_TEB_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 2 TEB event + 20 + 1 + read-write + + + TZ0_CBC_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM0. + 21 + 1 + read-write + + + TZ1_CBC_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM1. + 22 + 1 + read-write + + + TZ2_CBC_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM2. + 23 + 1 + read-write + + + TZ0_OST_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot mode action on PWM0. + 24 + 1 + read-write + + + TZ1_OST_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot mode action on PWM1. + 25 + 1 + read-write + + + TZ2_OST_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot mode action on PWM2. + 26 + 1 + read-write + + + CAP0_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered by capture on CAP0. + 27 + 1 + read-write + + + CAP1_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered by capture on CAP1. + 28 + 1 + read-write + + + CAP2_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered by capture on CAP2. + 29 + 1 + read-write + + + + + INT_ST + Interrupt masked status register + 0x118 + 0x20 + + + TIMER0_STOP_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered when the timer 0 stops. + 0 + 1 + read-only + + + TIMER1_STOP_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered when the timer 1 stops. + 1 + 1 + read-only + + + TIMER2_STOP_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered when the timer 2 stops. + 2 + 1 + read-only + + + TIMER0_TEZ_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 0 TEZ event. + 3 + 1 + read-only + + + TIMER1_TEZ_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 1 TEZ event. + 4 + 1 + read-only + + + TIMER2_TEZ_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 2 TEZ event. + 5 + 1 + read-only + + + TIMER0_TEP_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 0 TEP event. + 6 + 1 + read-only + + + TIMER1_TEP_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 1 TEP event. + 7 + 1 + read-only + + + TIMER2_TEP_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 2 TEP event. + 8 + 1 + read-only + + + FAULT0_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered when event_f0 starts. + 9 + 1 + read-only + + + FAULT1_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered when event_f1 starts. + 10 + 1 + read-only + + + FAULT2_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered when event_f2 starts. + 11 + 1 + read-only + + + FAULT0_CLR_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered when event_f0 clears. + 12 + 1 + read-only + + + FAULT1_CLR_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered when event_f1 clears. + 13 + 1 + read-only + + + FAULT2_CLR_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered when event_f2 clears. + 14 + 1 + read-only + + + CMPR0_TEA_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 0 TEA event + 15 + 1 + read-only + + + CMPR1_TEA_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 1 TEA event + 16 + 1 + read-only + + + CMPR2_TEA_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 2 TEA event + 17 + 1 + read-only + + + CMPR0_TEB_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 0 TEB event + 18 + 1 + read-only + + + CMPR1_TEB_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 1 TEB event + 19 + 1 + read-only + + + CMPR2_TEB_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 2 TEB event + 20 + 1 + read-only + + + TZ0_CBC_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM0. + 21 + 1 + read-only + + + TZ1_CBC_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM1. + 22 + 1 + read-only + + + TZ2_CBC_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM2. + 23 + 1 + read-only + + + TZ0_OST_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered by a one-shot mode action on PWM0. + 24 + 1 + read-only + + + TZ1_OST_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered by a one-shot mode action on PWM1. + 25 + 1 + read-only + + + TZ2_OST_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered by a one-shot mode action on PWM2. + 26 + 1 + read-only + + + CAP0_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered by capture on CAP0. + 27 + 1 + read-only + + + CAP1_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered by capture on CAP1. + 28 + 1 + read-only + + + CAP2_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered by capture on CAP2. + 29 + 1 + read-only + + + + + INT_CLR + Interrupt clear register + 0x11C + 0x20 + + + TIMER0_STOP_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered when the timer 0 stops. + 0 + 1 + write-only + + + TIMER1_STOP_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered when the timer 1 stops. + 1 + 1 + write-only + + + TIMER2_STOP_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered when the timer 2 stops. + 2 + 1 + write-only + + + TIMER0_TEZ_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEZ event. + 3 + 1 + write-only + + + TIMER1_TEZ_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEZ event. + 4 + 1 + write-only + + + TIMER2_TEZ_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEZ event. + 5 + 1 + write-only + + + TIMER0_TEP_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEP event. + 6 + 1 + write-only + + + TIMER1_TEP_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEP event. + 7 + 1 + write-only + + + TIMER2_TEP_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEP event. + 8 + 1 + write-only + + + FAULT0_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered when event_f0 starts. + 9 + 1 + write-only + + + FAULT1_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered when event_f1 starts. + 10 + 1 + write-only + + + FAULT2_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered when event_f2 starts. + 11 + 1 + write-only + + + FAULT0_CLR_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered when event_f0 clears. + 12 + 1 + write-only + + + FAULT1_CLR_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered when event_f1 clears. + 13 + 1 + write-only + + + FAULT2_CLR_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered when event_f2 clears. + 14 + 1 + write-only + + + CMPR0_TEA_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEA event + 15 + 1 + write-only + + + CMPR1_TEA_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEA event + 16 + 1 + write-only + + + CMPR2_TEA_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEA event + 17 + 1 + write-only + + + CMPR0_TEB_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEB event + 18 + 1 + write-only + + + CMPR1_TEB_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEB event + 19 + 1 + write-only + + + CMPR2_TEB_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEB event + 20 + 1 + write-only + + + TZ0_CBC_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action on PWM0. + 21 + 1 + write-only + + + TZ1_CBC_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action on PWM1. + 22 + 1 + write-only + + + TZ2_CBC_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action on PWM2. + 23 + 1 + write-only + + + TZ0_OST_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on PWM0. + 24 + 1 + write-only + + + TZ1_OST_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on PWM1. + 25 + 1 + write-only + + + TZ2_OST_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on PWM2. + 26 + 1 + write-only + + + CAP0_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered by capture on CAP0. + 27 + 1 + write-only + + + CAP1_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered by capture on CAP1. + 28 + 1 + write-only + + + CAP2_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered by capture on CAP2. + 29 + 1 + write-only + + + + + EVT_EN + Event enable register + 0x120 + 0x20 + + + EVT_TIMER0_STOP_EN + Configures whether or not to enable timer0 stop event generate.\\0: Disable\\1: Enable + 0 + 1 + read-write + + + EVT_TIMER1_STOP_EN + Configures whether or not to enable timer1 stop event generate.\\0: Disable\\1: Enable + 1 + 1 + read-write + + + EVT_TIMER2_STOP_EN + Configures whether or not to enable timer2 stop event generate.\\0: Disable\\1: Enable + 2 + 1 + read-write + + + EVT_TIMER0_TEZ_EN + Configures whether or not to enable timer0 equal zero event generate.\\0: Disable\\1: Enable + 3 + 1 + read-write + + + EVT_TIMER1_TEZ_EN + Configures whether or not to enable timer1 equal zero event generate.\\0: Disable\\1: Enable + 4 + 1 + read-write + + + EVT_TIMER2_TEZ_EN + Configures whether or not to enable timer2 equal zero event generate.\\0: Disable\\1: Enable + 5 + 1 + read-write + + + EVT_TIMER0_TEP_EN + Configures whether or not to enable timer0 equal period event generate.\\0: Disable\\1: Enable + 6 + 1 + read-write + + + EVT_TIMER1_TEP_EN + Configures whether or not to enable timer1 equal period event generate.\\0: Disable\\1: Enable + 7 + 1 + read-write + + + EVT_TIMER2_TEP_EN + Configures whether or not to enable timer2 equal period event generate.\\0: Disable\\1: Enable + 8 + 1 + read-write + + + EVT_OP0_TEA_EN + Configures whether or not to enable PWM generator0 timer equal a event generate.\\0: Disable\\1: Enable + 9 + 1 + read-write + + + EVT_OP1_TEA_EN + Configures whether or not to enable PWM generator1 timer equal a event generate.\\0: Disable\\1: Enable + 10 + 1 + read-write + + + EVT_OP2_TEA_EN + Configures whether or not to enable PWM generator2 timer equal a event generate.\\0: Disable\\1: Enable + 11 + 1 + read-write + + + EVT_OP0_TEB_EN + Configures whether or not to enable PWM generator0 timer equal b event generate.\\0: Disable\\1: Enable + 12 + 1 + read-write + + + EVT_OP1_TEB_EN + Configures whether or not to enable PWM generator1 timer equal b event generate.\\0: Disable\\1: Enable + 13 + 1 + read-write + + + EVT_OP2_TEB_EN + Configures whether or not to enable PWM generator2 timer equal b event generate.\\0: Disable\\1: Enable + 14 + 1 + read-write + + + EVT_F0_EN + Configures whether or not to enable fault0 event generate.\\0: Disable\\1: Enable + 15 + 1 + read-write + + + EVT_F1_EN + Configures whether or not to enable fault1 event generate.\\0: Disable\\1: Enable + 16 + 1 + read-write + + + EVT_F2_EN + Configures whether or not to enable fault2 event generate.\\0: Disable\\1: Enable + 17 + 1 + read-write + + + EVT_F0_CLR_EN + Configures whether or not to enable fault0 clear event generate.\\0: Disable\\1: Enable + 18 + 1 + read-write + + + EVT_F1_CLR_EN + Configures whether or not to enable fault1 clear event generate.\\0: Disable\\1: Enable + 19 + 1 + read-write + + + EVT_F2_CLR_EN + Configures whether or not to enable fault2 clear event generate.\\0: Disable\\1: Enable + 20 + 1 + read-write + + + EVT_TZ0_CBC_EN + Configures whether or not to enable cycle-by-cycle trip0 event generate.\\0: Disable\\1: Enable + 21 + 1 + read-write + + + EVT_TZ1_CBC_EN + Configures whether or not to enable cycle-by-cycle trip1 event generate.\\0: Disable\\1: Enable + 22 + 1 + read-write + + + EVT_TZ2_CBC_EN + Configures whether or not to enable cycle-by-cycle trip2 event generate.\\0: Disable\\1: Enable + 23 + 1 + read-write + + + EVT_TZ0_OST_EN + Configures whether or not to enable one-shot trip0 event generate.\\0: Disable\\1: Enable + 24 + 1 + read-write + + + EVT_TZ1_OST_EN + Configures whether or not to enable one-shot trip1 event generate.\\0: Disable\\1: Enable + 25 + 1 + read-write + + + EVT_TZ2_OST_EN + Configures whether or not to enable one-shot trip2 event generate.\\0: Disable\\1: Enable + 26 + 1 + read-write + + + EVT_CAP0_EN + Configures whether or not to enable capture0 event generate.\\0: Disable\\1: Enable + 27 + 1 + read-write + + + EVT_CAP1_EN + Configures whether or not to enable capture1 event generate.\\0: Disable\\1: Enable + 28 + 1 + read-write + + + EVT_CAP2_EN + Configures whether or not to enable capture2 event generate.\\0: Disable\\1: Enable + 29 + 1 + read-write + + + + + TASK_EN + Task enable register + 0x124 + 0x20 + + + TASK_CMPR0_A_UP_EN + Configures whether or not to enable PWM generator0 timer stamp A's shadow register update task receive.\\0: Disable\\1: Enable + 0 + 1 + read-write + + + TASK_CMPR1_A_UP_EN + Configures whether or not to enable PWM generator1 timer stamp A's shadow register update task receive.\\0: Disable\\1: Enable + 1 + 1 + read-write + + + TASK_CMPR2_A_UP_EN + Configures whether or not to enable PWM generator2 timer stamp A's shadow register update task receive.\\0: Disable\\1: Enable + 2 + 1 + read-write + + + TASK_CMPR0_B_UP_EN + Configures whether or not to enable PWM generator0 timer stamp B's shadow register update task receive.\\0: Disable\\1: Enable + 3 + 1 + read-write + + + TASK_CMPR1_B_UP_EN + Configures whether or not to enable PWM generator1 timer stamp B's shadow register update task receive.\\0: Disable\\1: Enable + 4 + 1 + read-write + + + TASK_CMPR2_B_UP_EN + Configures whether or not to enable PWM generator2 timer stamp B's shadow register update task receive.\\0: Disable\\1: Enable + 5 + 1 + read-write + + + TASK_GEN_STOP_EN + Configures whether or not to enable all PWM generate stop task receive.\\0: Disable\\1: Enable + 6 + 1 + read-write + + + TASK_TIMER0_SYNC_EN + Configures whether or not to enable timer0 sync task receive.\\0: Disable\\1: Enable + 7 + 1 + read-write + + + TASK_TIMER1_SYNC_EN + Configures whether or not to enable timer1 sync task receive.\\0: Disable\\1: Enable + 8 + 1 + read-write + + + TASK_TIMER2_SYNC_EN + Configures whether or not to enable timer2 sync task receive.\\0: Disable\\1: Enable + 9 + 1 + read-write + + + TASK_TIMER0_PERIOD_UP_EN + Configures whether or not to enable timer0 period update task receive.\\0: Disable\\1: Enable + 10 + 1 + read-write + + + TASK_TIMER1_PERIOD_UP_EN + Configures whether or not to enable timer1 period update task receive.\\0: Disable\\1: Enable + 11 + 1 + read-write + + + TASK_TIMER2_PERIOD_UP_EN + Configures whether or not to enable timer2 period update task receive.\\0: Disable\\1: Enable + 12 + 1 + read-write + + + TASK_TZ0_OST_EN + Configures whether or not to enable one shot trip0 task receive.\\0: Disable\\1: Enable + 13 + 1 + read-write + + + TASK_TZ1_OST_EN + Configures whether or not to enable one shot trip1 task receive.\\0: Disable\\1: Enable + 14 + 1 + read-write + + + TASK_TZ2_OST_EN + Configures whether or not to enable one shot trip2 task receive.\\0: Disable\\1: Enable + 15 + 1 + read-write + + + TASK_CLR0_OST_EN + Configures whether or not to enable one shot trip0 clear task receive.\\0: Disable\\1: Enable + 16 + 1 + read-write + + + TASK_CLR1_OST_EN + Configures whether or not to enable one shot trip1 clear task receive.\\0: Disable\\1: Enable + 17 + 1 + read-write + + + TASK_CLR2_OST_EN + Configures whether or not to enable one shot trip2 clear task receive.\\0: Disable\\1: Enable + 18 + 1 + read-write + + + TASK_CAP0_EN + Configures whether or not to enable capture0 task receive.\\0: Disable\\1: Enable + 19 + 1 + read-write + + + TASK_CAP1_EN + Configures whether or not to enable capture1 task receive.\\0: Disable\\1: Enable + 20 + 1 + read-write + + + TASK_CAP2_EN + Configures whether or not to enable capture2 task receive.\\0: Disable\\1: Enable + 21 + 1 + read-write + + + + + EVT_EN2 + Event enable register2 + 0x128 + 0x20 + + + EVT_OP0_TEE1_EN + Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E1_REG event generate.\\0: Disable\\1: Enable + 0 + 1 + read-write + + + EVT_OP1_TEE1_EN + Configures whether or not to enable PWM generator1 timer equal OP1_TSTMP_E1_REG event generate.\\0: Disable\\1: Enable + 1 + 1 + read-write + + + EVT_OP2_TEE1_EN + Configures whether or not to enable PWM generator2 timer equal OP2_TSTMP_E1_REG event generate.\\0: Disable\\1: Enable + 2 + 1 + read-write + + + EVT_OP0_TEE2_EN + Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E2_REG event generate.\\0: Disable\\1: Enable + 3 + 1 + read-write + + + EVT_OP1_TEE2_EN + Configures whether or not to enable PWM generator1 timer equal OP1_TSTMP_E2_REG event generate.\\0: Disable\\1: Enable + 4 + 1 + read-write + + + EVT_OP2_TEE2_EN + Configures whether or not to enable PWM generator2 timer equal OP2_TSTMP_E2_REG event generate.\\0: Disable\\1: Enable + 5 + 1 + read-write + + + + + 3 + 0x8 + OP%s_TSTMP_E1 + Generator%s timer stamp E1 value register + 0x12C + 0x20 + + + OP_TSTMP_E1 + Configures generator%s timer stamp E1 value register + 0 + 16 + read-write + + + + + 3 + 0x8 + OP%s_TSTMP_E2 + Generator%s timer stamp E2 value register + 0x130 + 0x20 + + + OP_TSTMP_E2 + Configures generator%s timer stamp E2 value register + 0 + 16 + read-write + + + + + CLK + Global configuration register + 0x144 + 0x20 + + + EN + Configures whether or not to open register clock gate.\\0: Open the clock gate only when application writes registers\\1: Force open the clock gate for register + 0 + 1 + read-write + + + + + VERSION + Version register. + 0x148 + 0x20 + 0x02212290 + + + DATE + Configures the version. + 0 + 28 + read-write + + + + + + + MCPWM1 + Motor Control Pulse-Width Modulation 1 + 0x500C1000 + + PWM1 + 39 + + + + PARL_IO + Parallel IO Controller + PARL_IO + 0x500CF000 + + 0x0 + 0x54 + registers + + + PARLIO_RX + 113 + + + PARLIO_TX + 114 + + + + RX_MODE_CFG + Parallel RX Sampling mode configuration register. + 0x0 + 0x20 + 0x00E00000 + + + RX_EXT_EN_SEL + Configures rx external enable signal selection from IO PAD. + 21 + 4 + read-write + + + RX_SW_EN + Set this bit to enable data sampling by software. + 25 + 1 + read-write + + + RX_EXT_EN_INV + Set this bit to invert the external enable signal. + 26 + 1 + read-write + + + RX_PULSE_SUBMODE_SEL + Configures the rxd pulse sampling submode. +4'd0: positive pulse start(data bit included) && positive pulse end(data bit included) +4'd1: positive pulse start(data bit included) && positive pulse end (data bit excluded) +4'd2: positive pulse start(data bit excluded) && positive pulse end (data bit included) +4'd3: positive pulse start(data bit excluded) && positive pulse end (data bit excluded) +4'd4: positive pulse start(data bit included) && length end +4'd5: positive pulse start(data bit excluded) && length end + 27 + 3 + read-write + + + RX_SMP_MODE_SEL + Configures the rxd sampling mode. +2'b00: external level enable mode +2'b01: external pulse enable mode +2'b10: internal software enable mode + 30 + 2 + read-write + + + + + RX_DATA_CFG + Parallel RX data configuration register. + 0x4 + 0x20 + 0x60000000 + + + RX_BITLEN + Configures expected byte number of received data. + 9 + 19 + read-write + + + RX_DATA_ORDER_INV + Set this bit to invert bit order of one byte sent from RX_FIFO to DMA. + 28 + 1 + read-write + + + RX_BUS_WID_SEL + Configures the rxd bus width. +3'd0: bus width is 1. +3'd1: bus width is 2. +3'd2: bus width is 4. +3'd3: bus width is 8. + 29 + 3 + read-write + + + + + RX_GENRL_CFG + Parallel RX general configuration register. + 0x8 + 0x20 + 0x21FFE000 + + + RX_GATING_EN + Set this bit to enable the clock gating of output rx clock. + 12 + 1 + read-write + + + RX_TIMEOUT_THRES + Configures threshold of timeout counter. + 13 + 16 + read-write + + + RX_TIMEOUT_EN + Set this bit to enable timeout function to generate error eof. + 29 + 1 + read-write + + + RX_EOF_GEN_SEL + Configures the DMA eof generated mechanism. 1'b0: eof generated by data bit length. 1'b1: eof generated by external enable signal. + 30 + 1 + read-write + + + + + RX_START_CFG + Parallel RX Start configuration register. + 0xC + 0x20 + + + RX_START + Set this bit to start rx data sampling. + 31 + 1 + read-write + + + + + TX_DATA_CFG + Parallel TX data configuration register. + 0x10 + 0x20 + 0x60000000 + + + TX_BITLEN + Configures expected byte number of sent data. + 9 + 19 + read-write + + + TX_DATA_ORDER_INV + Set this bit to invert bit order of one byte sent from TX_FIFO to IO data. + 28 + 1 + read-write + + + TX_BUS_WID_SEL + Configures the txd bus width. +3'd0: bus width is 1. +3'd1: bus width is 2. +3'd2: bus width is 4. +3'd3: bus width is 8. + 29 + 3 + read-write + + + + + TX_START_CFG + Parallel TX Start configuration register. + 0x14 + 0x20 + + + TX_START + Set this bit to start tx data transmit. + 31 + 1 + read-write + + + + + TX_GENRL_CFG + Parallel TX general configuration register. + 0x18 + 0x20 + + + TX_EOF_GEN_SEL + Configures the tx eof generated mechanism. 1'b0: eof generated by data bit length. 1'b1: eof generated by DMA eof. + 13 + 1 + read-write + + + TX_IDLE_VALUE + Configures bus value of transmitter in IDLE state. + 14 + 16 + read-write + + + TX_GATING_EN + Set this bit to enable the clock gating of output tx clock. + 30 + 1 + read-write + + + TX_VALID_OUTPUT_EN + Set this bit to enable the output of tx data valid signal. + 31 + 1 + read-write + + + + + FIFO_CFG + Parallel IO FIFO configuration register. + 0x1C + 0x20 + + + TX_FIFO_SRST + Set this bit to reset async fifo in tx module. + 30 + 1 + read-write + + + RX_FIFO_SRST + Set this bit to reset async fifo in rx module. + 31 + 1 + read-write + + + + + REG_UPDATE + Parallel IO FIFO configuration register. + 0x20 + 0x20 + + + RX_REG_UPDATE + Set this bit to update rx register configuration. + 31 + 1 + write-only + + + + + ST + Parallel IO module status register0. + 0x24 + 0x20 + + + TX_READY + Represents the status that tx is ready to transmit. + 31 + 1 + read-only + + + + + INT_ENA + Parallel IO interrupt enable singal configuration register. + 0x28 + 0x20 + + + TX_FIFO_REMPTY_INT_ENA + Set this bit to enable TX_FIFO_REMPTY_INT. + 0 + 1 + read-write + + + RX_FIFO_WOVF_INT_ENA + Set this bit to enable RX_FIFO_WOVF_INT. + 1 + 1 + read-write + + + TX_EOF_INT_ENA + Set this bit to enable TX_EOF_INT. + 2 + 1 + read-write + + + + + INT_RAW + Parallel IO interrupt raw singal status register. + 0x2C + 0x20 + + + TX_FIFO_REMPTY_INT_RAW + The raw interrupt status of TX_FIFO_REMPTY_INT. + 0 + 1 + read-write + + + RX_FIFO_WOVF_INT_RAW + The raw interrupt status of RX_FIFO_WOVF_INT. + 1 + 1 + read-write + + + TX_EOF_INT_RAW + The raw interrupt status of TX_EOF_INT. + 2 + 1 + read-write + + + + + INT_ST + Parallel IO interrupt singal status register. + 0x30 + 0x20 + + + TX_FIFO_REMPTY_INT_ST + The masked interrupt status of TX_FIFO_REMPTY_INT. + 0 + 1 + read-only + + + RX_FIFO_WOVF_INT_ST + The masked interrupt status of RX_FIFO_WOVF_INT. + 1 + 1 + read-only + + + TX_EOF_INT_ST + The masked interrupt status of TX_EOF_INT. + 2 + 1 + read-only + + + + + INT_CLR + Parallel IO interrupt clear singal configuration register. + 0x34 + 0x20 + + + TX_FIFO_REMPTY_INT_CLR + Set this bit to clear TX_FIFO_REMPTY_INT. + 0 + 1 + write-only + + + RX_FIFO_WOVF_INT_CLR + Set this bit to clear RX_FIFO_WOVF_INT. + 1 + 1 + write-only + + + TX_EOF_INT_CLR + Set this bit to clear TX_EOF_INT. + 2 + 1 + write-only + + + + + RX_ST0 + Parallel IO RX status register0 + 0x38 + 0x20 + + + RX_CNT + Indicates the cycle number of reading Rx FIFO. + 8 + 5 + read-only + + + RX_FIFO_WR_BIT_CNT + Indicates the current written bit number into Rx FIFO. + 13 + 19 + read-only + + + + + RX_ST1 + Parallel IO RX status register1 + 0x3C + 0x20 + + + RX_FIFO_RD_BIT_CNT + Indicates the current read bit number from Rx FIFO. + 13 + 19 + read-only + + + + + TX_ST0 + Parallel IO TX status register0 + 0x40 + 0x20 + + + TX_CNT + Indicates the cycle number of reading Tx FIFO. + 6 + 7 + read-only + + + TX_FIFO_RD_BIT_CNT + Indicates the current read bit number from Tx FIFO. + 13 + 19 + read-only + + + + + RX_CLK_CFG + Parallel IO RX clk configuration register + 0x44 + 0x20 + + + RX_CLK_I_INV + Set this bit to invert the input Rx core clock. + 30 + 1 + read-write + + + RX_CLK_O_INV + Set this bit to invert the output Rx core clock. + 31 + 1 + read-write + + + + + TX_CLK_CFG + Parallel IO TX clk configuration register + 0x48 + 0x20 + + + TX_CLK_I_INV + Set this bit to invert the input Tx core clock. + 30 + 1 + read-write + + + TX_CLK_O_INV + Set this bit to invert the output Tx core clock. + 31 + 1 + read-write + + + + + CLK + Parallel IO clk configuration register + 0x120 + 0x20 + + + EN + Force clock on for this register file + 31 + 1 + read-write + + + + + VERSION + Version register. + 0x3FC + 0x20 + 0x02212260 + + + DATE + Version of this register file + 0 + 28 + read-write + + + + + + + PAU + PAU Peripheral + PAU + 0x60093000 + + 0x0 + 0x44 + registers + + + PAU + 112 + + + + REGDMA_CONF + Peri backup control register + 0x0 + 0x20 + + + FLOW_ERR + backup error type + 0 + 3 + read-only + + + START + backup start signal + 3 + 1 + write-only + + + TO_MEM + backup direction(reg to mem / mem to reg) + 4 + 1 + read-write + + + LINK_SEL + Link select + 5 + 2 + read-write + + + START_MAC + mac sw backup start signal + 7 + 1 + write-only + + + TO_MEM_MAC + mac sw backup direction(reg to mem / mem to reg) + 8 + 1 + read-write + + + SEL_MAC + mac hw/sw select + 9 + 1 + read-write + + + + + REGDMA_CLK_CONF + Clock control register + 0x4 + 0x20 + + + CLK_EN + clock enable + 0 + 1 + read-write + + + + + REGDMA_ETM_CTRL + ETM start ctrl reg + 0x8 + 0x20 + + + ETM_START_0 + etm_start_0 reg + 0 + 1 + write-only + + + ETM_START_1 + etm_start_1 reg + 1 + 1 + write-only + + + ETM_START_2 + etm_start_2 reg + 2 + 1 + write-only + + + ETM_START_3 + etm_start_3 reg + 3 + 1 + write-only + + + + + REGDMA_LINK_0_ADDR + link_0_addr + 0xC + 0x20 + + + LINK_ADDR_0 + link_0_addr reg + 0 + 32 + read-write + + + + + REGDMA_LINK_1_ADDR + Link_1_addr + 0x10 + 0x20 + + + LINK_ADDR_1 + Link_1_addr reg + 0 + 32 + read-write + + + + + REGDMA_LINK_2_ADDR + Link_2_addr + 0x14 + 0x20 + + + LINK_ADDR_2 + Link_2_addr reg + 0 + 32 + read-write + + + + + REGDMA_LINK_3_ADDR + Link_3_addr + 0x18 + 0x20 + + + LINK_ADDR_3 + Link_3_addr reg + 0 + 32 + read-write + + + + + REGDMA_LINK_MAC_ADDR + Link_mac_addr + 0x1C + 0x20 + + + LINK_ADDR_MAC + Link_mac_addr reg + 0 + 32 + read-write + + + + + REGDMA_CURRENT_LINK_ADDR + current link addr + 0x20 + 0x20 + + + CURRENT_LINK_ADDR + current link addr reg + 0 + 32 + read-only + + + + + REGDMA_BACKUP_ADDR + Backup addr + 0x24 + 0x20 + + + BACKUP_ADDR + backup addr reg + 0 + 32 + read-only + + + + + REGDMA_MEM_ADDR + mem addr + 0x28 + 0x20 + + + MEM_ADDR + mem addr reg + 0 + 32 + read-only + + + + + REGDMA_BKP_CONF + backup config + 0x2C + 0x20 + 0x7D101920 + + + READ_INTERVAL + Link read_interval + 0 + 7 + read-write + + + LINK_TOUT_THRES + link wait timeout threshold + 7 + 10 + read-write + + + BURST_LIMIT + burst limit + 17 + 5 + read-write + + + BACKUP_TOUT_THRES + Backup timeout threshold + 22 + 10 + read-write + + + + + INT_ENA + Read only register for error and done + 0x30 + 0x20 + + + DONE_INT_ENA + backup done flag + 0 + 1 + read-write + + + ERROR_INT_ENA + error flag + 1 + 1 + read-write + + + + + INT_RAW + Read only register for error and done + 0x34 + 0x20 + + + DONE_INT_RAW + backup done flag + 0 + 1 + read-write + + + ERROR_INT_RAW + error flag + 1 + 1 + read-write + + + + + INT_CLR + Read only register for error and done + 0x38 + 0x20 + + + DONE_INT_CLR + backup done flag + 0 + 1 + write-only + + + ERROR_INT_CLR + error flag + 1 + 1 + write-only + + + + + INT_ST + Read only register for error and done + 0x3C + 0x20 + + + DONE_INT_ST + backup done flag + 0 + 1 + read-only + + + ERROR_INT_ST + error flag + 1 + 1 + read-only + + + + + DATE + Date register. + 0x3FC + 0x20 + 0x02203070 + + + DATE + REGDMA date information/ REGDMA version information. + 0 + 28 + read-write + + + + + + + PCNT + Pulse Count Controller + PCNT + 0x500C9000 + + 0x0 + 0x78 + registers + + + PCNT + 111 + + + + 4 + 0xC + U%s_CONF0 + Configuration register 0 for unit %s + 0x0 + 0x20 + 0x00003C10 + + + FILTER_THRES_U + This sets the maximum threshold, in APB_CLK cycles, for the filter. + +Any pulses with width less than this will be ignored when the filter is enabled. + 0 + 10 + read-write + + + FILTER_EN_U + This is the enable bit for unit %s's input filter. + 10 + 1 + read-write + + + THR_ZERO_EN_U + This is the enable bit for unit %s's zero comparator. + 11 + 1 + read-write + + + THR_H_LIM_EN_U + This is the enable bit for unit %s's thr_h_lim comparator. Configures it to enable the high limit interrupt. + 12 + 1 + read-write + + + THR_L_LIM_EN_U + This is the enable bit for unit %s's thr_l_lim comparator. Configures it to enable the low limit interrupt. + 13 + 1 + read-write + + + THR_THRES0_EN_U + This is the enable bit for unit %s's thres0 comparator. + 14 + 1 + read-write + + + THR_THRES1_EN_U + This is the enable bit for unit %s's thres1 comparator. + 15 + 1 + read-write + + + CH0_NEG_MODE_U + This register sets the behavior when the signal input of channel 0 detects a negative edge. + +1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + 16 + 2 + read-write + + + CH0_POS_MODE_U + This register sets the behavior when the signal input of channel 0 detects a positive edge. + +1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + 18 + 2 + read-write + + + CH0_HCTRL_MODE_U + This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high. + +0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification + 20 + 2 + read-write + + + CH0_LCTRL_MODE_U + This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low. + +0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification + 22 + 2 + read-write + + + CH1_NEG_MODE_U + This register sets the behavior when the signal input of channel 1 detects a negative edge. + +1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + 24 + 2 + read-write + + + CH1_POS_MODE_U + This register sets the behavior when the signal input of channel 1 detects a positive edge. + +1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + 26 + 2 + read-write + + + CH1_HCTRL_MODE_U + This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high. + +0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification + 28 + 2 + read-write + + + CH1_LCTRL_MODE_U + This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low. + +0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification + 30 + 2 + read-write + + + + + 4 + 0xC + U%s_CONF1 + Configuration register 1 for unit %s + 0x4 + 0x20 + + + CNT_THRES0_U + This register is used to configure the thres0 value for unit %s. + 0 + 16 + read-write + + + CNT_THRES1_U + This register is used to configure the thres1 value for unit %s. + 16 + 16 + read-write + + + + + 4 + 0xC + U%s_CONF2 + Configuration register 2 for unit %s + 0x8 + 0x20 + + + CNT_H_LIM_U + This register is used to configure the thr_h_lim value for unit %s. When pcnt reaches this value, the counter will be cleared to 0. + 0 + 16 + read-write + + + CNT_L_LIM_U + This register is used to configure the thr_l_lim value for unit %s. When pcnt reaches this value, the counter will be cleared to 0. + 16 + 16 + read-write + + + + + 4 + 0x4 + U%s_CNT + Counter value for unit %s + 0x30 + 0x20 + + + PULSE_CNT_U + This register stores the current pulse count value for unit %s. + 0 + 16 + read-only + + + + + INT_RAW + Interrupt raw status register + 0x40 + 0x20 + + + CNT_THR_EVENT_U0_INT_RAW + The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + 0 + 1 + read-write + + + CNT_THR_EVENT_U1_INT_RAW + The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + 1 + 1 + read-write + + + CNT_THR_EVENT_U2_INT_RAW + The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + 2 + 1 + read-write + + + CNT_THR_EVENT_U3_INT_RAW + The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + 3 + 1 + read-write + + + + + INT_ST + Interrupt status register + 0x44 + 0x20 + + + CNT_THR_EVENT_U0_INT_ST + The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + 0 + 1 + read-only + + + CNT_THR_EVENT_U1_INT_ST + The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + 1 + 1 + read-only + + + CNT_THR_EVENT_U2_INT_ST + The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + 2 + 1 + read-only + + + CNT_THR_EVENT_U3_INT_ST + The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + 3 + 1 + read-only + + + + + INT_ENA + Interrupt enable register + 0x48 + 0x20 + + + CNT_THR_EVENT_U0_INT_ENA + The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + 0 + 1 + read-write + + + CNT_THR_EVENT_U1_INT_ENA + The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + 1 + 1 + read-write + + + CNT_THR_EVENT_U2_INT_ENA + The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + 2 + 1 + read-write + + + CNT_THR_EVENT_U3_INT_ENA + The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + 3 + 1 + read-write + + + + + INT_CLR + Interrupt clear register + 0x4C + 0x20 + + + CNT_THR_EVENT_U0_INT_CLR + Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt. + 0 + 1 + write-only + + + CNT_THR_EVENT_U1_INT_CLR + Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt. + 1 + 1 + write-only + + + CNT_THR_EVENT_U2_INT_CLR + Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt. + 2 + 1 + write-only + + + CNT_THR_EVENT_U3_INT_CLR + Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt. + 3 + 1 + write-only + + + + + 4 + 0x4 + U%s_STATUS + PNCT UNIT%s status register + 0x50 + 0x20 + + + CNT_THR_ZERO_MODE_U + The pulse counter status of PCNT_U%s corresponding to 0. 0: pulse counter decreases from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter is negative. 3: pulse counter is positive. + 0 + 2 + read-only + + + CNT_THR_THRES1_LAT_U + The latched value of thres1 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0: others + 2 + 1 + read-only + + + CNT_THR_THRES0_LAT_U + The latched value of thres0 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0: others + 3 + 1 + read-only + + + CNT_THR_L_LIM_LAT_U + The latched value of low limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_l_lim and low limit event is valid. 0: others + 4 + 1 + read-only + + + CNT_THR_H_LIM_LAT_U + The latched value of high limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_h_lim and high limit event is valid. 0: others + 5 + 1 + read-only + + + CNT_THR_ZERO_LAT_U + The latched value of zero threshold event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to 0 and zero threshold event is valid. 0: others + 6 + 1 + read-only + + + + + CTRL + Control register for all counters + 0x60 + 0x20 + 0x00000001 + + + PULSE_CNT_RST_U0 + Set this bit to clear unit 0's counter. + 0 + 1 + read-write + + + CNT_PAUSE_U0 + Set this bit to freeze unit 0's counter. + 1 + 1 + read-write + + + PULSE_CNT_RST_U1 + Set this bit to clear unit 1's counter. + 2 + 1 + read-write + + + CNT_PAUSE_U1 + Set this bit to freeze unit 1's counter. + 3 + 1 + read-write + + + PULSE_CNT_RST_U2 + Set this bit to clear unit 2's counter. + 4 + 1 + read-write + + + CNT_PAUSE_U2 + Set this bit to freeze unit 2's counter. + 5 + 1 + read-write + + + PULSE_CNT_RST_U3 + Set this bit to clear unit 3's counter. + 6 + 1 + read-write + + + CNT_PAUSE_U3 + Set this bit to freeze unit 3's counter. + 7 + 1 + read-write + + + DALTA_CHANGE_EN_U0 + Configures this bit to enable unit 0's step comparator. + 8 + 1 + read-write + + + DALTA_CHANGE_EN_U1 + Configures this bit to enable unit 1's step comparator. + 9 + 1 + read-write + + + DALTA_CHANGE_EN_U2 + Configures this bit to enable unit 2's step comparator. + 10 + 1 + read-write + + + DALTA_CHANGE_EN_U3 + Configures this bit to enable unit 3's step comparator. + 11 + 1 + read-write + + + CLK_EN + The registers clock gate enable signal of PCNT module. 1: the registers can be read and written by application. 0: the registers can not be read or written by application + 16 + 1 + read-write + + + + + U3_CHANGE_CONF + Configuration register for unit $n's step value. + 0x64 + 0x20 + + + CNT_STEP_U3 + Configures the step value for unit 3. + 0 + 16 + read-write + + + CNT_STEP_LIM_U3 + Configures the step limit value for unit 3. + 16 + 16 + read-write + + + + + U2_CHANGE_CONF + Configuration register for unit $n's step value. + 0x68 + 0x20 + + + CNT_STEP_U2 + Configures the step value for unit 2. + 0 + 16 + read-write + + + CNT_STEP_LIM_U2 + Configures the step limit value for unit 2. + 16 + 16 + read-write + + + + + U1_CHANGE_CONF + Configuration register for unit $n's step value. + 0x6C + 0x20 + + + CNT_STEP_U1 + Configures the step value for unit 1. + 0 + 16 + read-write + + + CNT_STEP_LIM_U1 + Configures the step limit value for unit 1. + 16 + 16 + read-write + + + + + U0_CHANGE_CONF + Configuration register for unit $n's step value. + 0x70 + 0x20 + + + CNT_STEP_U0 + Configures the step value for unit 0. + 0 + 16 + read-write + + + CNT_STEP_LIM_U0 + Configures the step limit value for unit 0. + 16 + 16 + read-write + + + + + DATE + PCNT version control register + 0xFC + 0x20 + 0x22091900 + + + DATE + This is the PCNT version control register. + 0 + 32 + read-write + + + + + + + PMU + PMU Peripheral + PMU + 0x50115000 + + 0x0 + 0x21C + registers + + + PMU0 + 6 + + + PMU1 + 7 + + + + HP_ACTIVE_DIG_POWER + need_des + 0x0 + 0x20 + + + HP_ACTIVE_DCDC_SWITCH_PD_EN + need_des + 21 + 1 + read-write + + + HP_ACTIVE_HP_MEM_DSLP + need_des + 22 + 1 + read-write + + + HP_ACTIVE_PD_HP_MEM_PD_EN + need_des + 23 + 1 + read-write + + + HP_ACTIVE_PD_CNNT_PD_EN + need_des + 30 + 1 + read-write + + + HP_ACTIVE_PD_TOP_PD_EN + need_des + 31 + 1 + read-write + + + + + HP_ACTIVE_ICG_HP_FUNC + need_des + 0x4 + 0x20 + 0xFFFFFFFF + + + HP_ACTIVE_DIG_ICG_FUNC_EN + need_des + 0 + 32 + read-write + + + + + HP_ACTIVE_ICG_HP_APB + need_des + 0x8 + 0x20 + 0xFFFFFFFF + + + HP_ACTIVE_DIG_ICG_APB_EN + need_des + 0 + 32 + read-write + + + + + HP_ACTIVE_ICG_MODEM + need_des + 0xC + 0x20 + + + HP_ACTIVE_DIG_ICG_MODEM_CODE + need_des + 30 + 2 + read-write + + + + + HP_ACTIVE_HP_SYS_CNTL + need_des + 0x10 + 0x20 + + + HP_ACTIVE_HP_POWER_DET_BYPASS + need_des + 23 + 1 + read-write + + + HP_ACTIVE_UART_WAKEUP_EN + need_des + 24 + 1 + read-write + + + HP_ACTIVE_LP_PAD_HOLD_ALL + need_des + 25 + 1 + read-write + + + HP_ACTIVE_HP_PAD_HOLD_ALL + need_des + 26 + 1 + read-write + + + HP_ACTIVE_DIG_PAD_SLP_SEL + need_des + 27 + 1 + read-write + + + HP_ACTIVE_DIG_PAUSE_WDT + need_des + 28 + 1 + read-write + + + HP_ACTIVE_DIG_CPU_STALL + need_des + 29 + 1 + read-write + + + + + HP_ACTIVE_HP_CK_POWER + need_des + 0x14 + 0x20 + + + HP_ACTIVE_I2C_ISO_EN + need_des + 21 + 1 + read-write + + + HP_ACTIVE_I2C_RETENTION + need_des + 22 + 1 + read-write + + + HP_ACTIVE_XPD_PLL_I2C + need_des + 23 + 4 + read-write + + + HP_ACTIVE_XPD_PLL + need_des + 27 + 4 + read-write + + + + + HP_ACTIVE_BIAS + need_des + 0x18 + 0x20 + 0x00500000 + + + HP_ACTIVE_DCM_VSET + need_des + 18 + 5 + read-write + + + HP_ACTIVE_DCM_MODE + need_des + 23 + 2 + read-write + + + HP_ACTIVE_XPD_BIAS + need_des + 25 + 1 + read-write + + + HP_ACTIVE_DBG_ATTEN + need_des + 26 + 4 + read-write + + + HP_ACTIVE_PD_CUR + need_des + 30 + 1 + read-write + + + SLEEP + need_des + 31 + 1 + read-write + + + + + HP_ACTIVE_BACKUP + need_des + 0x1C + 0x20 + + + HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE + need_des + 4 + 2 + read-write + + + HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE + need_des + 6 + 2 + read-write + + + HP_ACTIVE_RETENTION_MODE + need_des + 10 + 1 + read-write + + + HP_SLEEP2ACTIVE_RETENTION_EN + need_des + 11 + 1 + read-write + + + HP_MODEM2ACTIVE_RETENTION_EN + need_des + 12 + 1 + read-write + + + HP_SLEEP2ACTIVE_BACKUP_CLK_SEL + need_des + 14 + 2 + read-write + + + HP_MODEM2ACTIVE_BACKUP_CLK_SEL + need_des + 16 + 2 + read-write + + + HP_SLEEP2ACTIVE_BACKUP_MODE + need_des + 20 + 3 + read-write + + + HP_MODEM2ACTIVE_BACKUP_MODE + need_des + 23 + 3 + read-write + + + HP_SLEEP2ACTIVE_BACKUP_EN + need_des + 29 + 1 + read-write + + + HP_MODEM2ACTIVE_BACKUP_EN + need_des + 30 + 1 + read-write + + + + + HP_ACTIVE_BACKUP_CLK + need_des + 0x20 + 0x20 + + + HP_ACTIVE_BACKUP_ICG_FUNC_EN + need_des + 0 + 32 + read-write + + + + + HP_ACTIVE_SYSCLK + need_des + 0x24 + 0x20 + + + HP_ACTIVE_DIG_SYS_CLK_NO_DIV + need_des + 26 + 1 + read-write + + + HP_ACTIVE_ICG_SYS_CLOCK_EN + need_des + 27 + 1 + read-write + + + HP_ACTIVE_SYS_CLK_SLP_SEL + need_des + 28 + 1 + read-write + + + HP_ACTIVE_ICG_SLP_SEL + need_des + 29 + 1 + read-write + + + HP_ACTIVE_DIG_SYS_CLK_SEL + need_des + 30 + 2 + read-write + + + + + HP_ACTIVE_HP_REGULATOR0 + need_des + 0x28 + 0x20 + 0xC6677180 + + + LP_DBIAS_VOL + need_des + 4 + 5 + read-only + + + HP_DBIAS_VOL + need_des + 9 + 5 + read-only + + + DIG_REGULATOR0_DBIAS_SEL + need_des + 14 + 1 + read-write + + + DIG_DBIAS_INIT + need_des + 15 + 1 + write-only + + + HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD + need_des + 16 + 1 + read-write + + + HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD + need_des + 17 + 1 + read-write + + + HP_ACTIVE_HP_REGULATOR_XPD + need_des + 18 + 1 + read-write + + + HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS + need_des + 19 + 4 + read-write + + + HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS + need_des + 23 + 4 + read-write + + + HP_ACTIVE_HP_REGULATOR_DBIAS + need_des + 27 + 5 + read-write + + + + + HP_ACTIVE_HP_REGULATOR1 + need_des + 0x2C + 0x20 + + + HP_ACTIVE_HP_REGULATOR_DRV_B + need_des + 26 + 6 + read-write + + + + + HP_ACTIVE_XTAL + need_des + 0x30 + 0x20 + 0x80000000 + + + HP_ACTIVE_XPD_XTAL + need_des + 31 + 1 + read-write + + + + + HP_MODEM_DIG_POWER + need_des + 0x34 + 0x20 + + + HP_MODEM_DCDC_SWITCH_PD_EN + need_des + 21 + 1 + read-write + + + HP_MODEM_HP_MEM_DSLP + need_des + 22 + 1 + write-only + + + HP_MODEM_PD_HP_MEM_PD_EN + need_des + 23 + 4 + write-only + + + HP_MODEM_PD_HP_WIFI_PD_EN + need_des + 27 + 1 + write-only + + + HP_MODEM_PD_HP_CPU_PD_EN + need_des + 29 + 1 + write-only + + + HP_MODEM_PD_CNNT_PD_EN + need_des + 30 + 1 + write-only + + + HP_MODEM_PD_TOP_PD_EN + need_des + 31 + 1 + write-only + + + + + HP_MODEM_ICG_HP_FUNC + need_des + 0x38 + 0x20 + 0xFFFFFFFF + + + HP_MODEM_DIG_ICG_FUNC_EN + need_des + 0 + 32 + write-only + + + + + HP_MODEM_ICG_HP_APB + need_des + 0x3C + 0x20 + 0xFFFFFFFF + + + HP_MODEM_DIG_ICG_APB_EN + need_des + 0 + 32 + write-only + + + + + HP_MODEM_ICG_MODEM + need_des + 0x40 + 0x20 + + + HP_MODEM_DIG_ICG_MODEM_CODE + need_des + 30 + 2 + write-only + + + + + HP_MODEM_HP_SYS_CNTL + need_des + 0x44 + 0x20 + + + HP_MODEM_HP_POWER_DET_BYPASS + need_des + 23 + 1 + write-only + + + HP_MODEM_UART_WAKEUP_EN + need_des + 24 + 1 + write-only + + + HP_MODEM_LP_PAD_HOLD_ALL + need_des + 25 + 1 + write-only + + + HP_MODEM_HP_PAD_HOLD_ALL + need_des + 26 + 1 + write-only + + + HP_MODEM_DIG_PAD_SLP_SEL + need_des + 27 + 1 + write-only + + + HP_MODEM_DIG_PAUSE_WDT + need_des + 28 + 1 + write-only + + + HP_MODEM_DIG_CPU_STALL + need_des + 29 + 1 + write-only + + + + + HP_MODEM_HP_CK_POWER + need_des + 0x48 + 0x20 + + + HP_MODEM_I2C_ISO_EN + need_des + 21 + 1 + write-only + + + HP_MODEM_I2C_RETENTION + need_des + 22 + 1 + write-only + + + HP_MODEM_XPD_PLL_I2C + need_des + 23 + 4 + write-only + + + HP_MODEM_XPD_PLL + need_des + 27 + 4 + write-only + + + + + HP_MODEM_BIAS + need_des + 0x4C + 0x20 + 0x00500000 + + + HP_MODEM_DCM_VSET + need_des + 18 + 5 + write-only + + + HP_MODEM_DCM_MODE + need_des + 23 + 2 + write-only + + + HP_MODEM_XPD_BIAS + need_des + 25 + 1 + write-only + + + HP_MODEM_DBG_ATTEN + need_des + 26 + 4 + write-only + + + HP_MODEM_PD_CUR + need_des + 30 + 1 + write-only + + + SLEEP + need_des + 31 + 1 + write-only + + + + + HP_MODEM_BACKUP + need_des + 0x50 + 0x20 + + + HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE + need_des + 4 + 2 + write-only + + + HP_MODEM_RETENTION_MODE + need_des + 10 + 1 + write-only + + + HP_SLEEP2MODEM_RETENTION_EN + need_des + 11 + 1 + write-only + + + HP_SLEEP2MODEM_BACKUP_CLK_SEL + need_des + 14 + 2 + write-only + + + HP_SLEEP2MODEM_BACKUP_MODE + need_des + 20 + 3 + write-only + + + HP_SLEEP2MODEM_BACKUP_EN + need_des + 29 + 1 + write-only + + + + + HP_MODEM_BACKUP_CLK + need_des + 0x54 + 0x20 + + + HP_MODEM_BACKUP_ICG_FUNC_EN + need_des + 0 + 32 + write-only + + + + + HP_MODEM_SYSCLK + need_des + 0x58 + 0x20 + + + HP_MODEM_DIG_SYS_CLK_NO_DIV + need_des + 26 + 1 + write-only + + + HP_MODEM_ICG_SYS_CLOCK_EN + need_des + 27 + 1 + write-only + + + HP_MODEM_SYS_CLK_SLP_SEL + need_des + 28 + 1 + write-only + + + HP_MODEM_ICG_SLP_SEL + need_des + 29 + 1 + write-only + + + HP_MODEM_DIG_SYS_CLK_SEL + need_des + 30 + 2 + write-only + + + + + HP_MODEM_HP_REGULATOR0 + need_des + 0x5C + 0x20 + 0xC6670000 + + + HP_MODEM_HP_REGULATOR_SLP_MEM_XPD + need_des + 16 + 1 + write-only + + + HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD + need_des + 17 + 1 + write-only + + + HP_MODEM_HP_REGULATOR_XPD + need_des + 18 + 1 + write-only + + + HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS + need_des + 19 + 4 + write-only + + + HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS + need_des + 23 + 4 + write-only + + + HP_MODEM_HP_REGULATOR_DBIAS + need_des + 27 + 5 + write-only + + + + + HP_MODEM_HP_REGULATOR1 + need_des + 0x60 + 0x20 + + + HP_MODEM_HP_REGULATOR_DRV_B + need_des + 8 + 24 + write-only + + + + + HP_MODEM_XTAL + need_des + 0x64 + 0x20 + 0x80000000 + + + HP_MODEM_XPD_XTAL + need_des + 31 + 1 + write-only + + + + + HP_SLEEP_DIG_POWER + need_des + 0x68 + 0x20 + + + HP_SLEEP_DCDC_SWITCH_PD_EN + need_des + 21 + 1 + read-write + + + HP_SLEEP_HP_MEM_DSLP + need_des + 22 + 1 + read-write + + + HP_SLEEP_PD_HP_MEM_PD_EN + need_des + 23 + 1 + read-write + + + HP_SLEEP_PD_CNNT_PD_EN + need_des + 30 + 1 + read-write + + + HP_SLEEP_PD_TOP_PD_EN + need_des + 31 + 1 + read-write + + + + + HP_SLEEP_ICG_HP_FUNC + need_des + 0x6C + 0x20 + 0xFFFFFFFF + + + HP_SLEEP_DIG_ICG_FUNC_EN + need_des + 0 + 32 + read-write + + + + + HP_SLEEP_ICG_HP_APB + need_des + 0x70 + 0x20 + 0xFFFFFFFF + + + HP_SLEEP_DIG_ICG_APB_EN + need_des + 0 + 32 + read-write + + + + + HP_SLEEP_ICG_MODEM + need_des + 0x74 + 0x20 + + + HP_SLEEP_DIG_ICG_MODEM_CODE + need_des + 30 + 2 + read-write + + + + + HP_SLEEP_HP_SYS_CNTL + need_des + 0x78 + 0x20 + + + HP_SLEEP_HP_POWER_DET_BYPASS + need_des + 23 + 1 + read-write + + + HP_SLEEP_UART_WAKEUP_EN + need_des + 24 + 1 + read-write + + + HP_SLEEP_LP_PAD_HOLD_ALL + need_des + 25 + 1 + read-write + + + HP_SLEEP_HP_PAD_HOLD_ALL + need_des + 26 + 1 + read-write + + + HP_SLEEP_DIG_PAD_SLP_SEL + need_des + 27 + 1 + read-write + + + HP_SLEEP_DIG_PAUSE_WDT + need_des + 28 + 1 + read-write + + + HP_SLEEP_DIG_CPU_STALL + need_des + 29 + 1 + read-write + + + + + HP_SLEEP_HP_CK_POWER + need_des + 0x7C + 0x20 + + + HP_SLEEP_I2C_ISO_EN + need_des + 21 + 1 + read-write + + + HP_SLEEP_I2C_RETENTION + need_des + 22 + 1 + read-write + + + HP_SLEEP_XPD_PLL_I2C + need_des + 23 + 4 + read-write + + + HP_SLEEP_XPD_PLL + need_des + 27 + 4 + read-write + + + + + HP_SLEEP_BIAS + need_des + 0x80 + 0x20 + 0x00500000 + + + HP_SLEEP_DCM_VSET + need_des + 18 + 5 + read-write + + + HP_SLEEP_DCM_MODE + need_des + 23 + 2 + read-write + + + HP_SLEEP_XPD_BIAS + need_des + 25 + 1 + read-write + + + HP_SLEEP_DBG_ATTEN + need_des + 26 + 4 + read-write + + + HP_SLEEP_PD_CUR + need_des + 30 + 1 + read-write + + + SLEEP + need_des + 31 + 1 + read-write + + + + + HP_SLEEP_BACKUP + need_des + 0x84 + 0x20 + + + HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE + need_des + 6 + 2 + read-write + + + HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE + need_des + 8 + 2 + read-write + + + HP_SLEEP_RETENTION_MODE + need_des + 10 + 1 + read-write + + + HP_MODEM2SLEEP_RETENTION_EN + need_des + 12 + 1 + read-write + + + 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read-only + + + PMU_ANA_XPD_PLL_STATE + need_des + 27 + 4 + read-only + + + PMU_ANA_XPD_XTAL_STATE + need_des + 31 + 1 + read-only + + + + + CLK_STATE1 + need_des + 0x1B0 + 0x20 + 0xFFFFFFFF + + + PMU_ICG_FUNC_EN_STATE + need_des + 0 + 32 + read-only + + + + + CLK_STATE2 + need_des + 0x1B4 + 0x20 + 0xFFFFFFFF + + + PMU_ICG_APB_EN_STATE + need_des + 0 + 32 + read-only + + + + + EXT_LDO_P0_0P1A + need_des + 0x1B8 + 0x20 + 0x40200100 + + + _0P1A_FORCE_TIEH_SEL_0 + need_des + 7 + 1 + read-write + + + _0P1A_XPD_0 + need_des + 8 + 1 + read-write + + + _0P1A_TIEH_SEL_0 + need_des + 9 + 3 + read-write + + + _0P1A_TIEH_POS_EN_0 + need_des + 12 + 1 + read-write + + + _0P1A_TIEH_NEG_EN_0 + need_des + 13 + 1 + read-write + + + _0P1A_TIEH_0 + need_des + 14 + 1 + read-write + + + _0P1A_TARGET1_0 + need_des + 15 + 8 + read-write + + + _0P1A_TARGET0_0 + need_des + 23 + 8 + read-write + + + _0P1A_LDO_CNT_PRESCALER_SEL_0 + need_des + 31 + 1 + read-write + + + + + EXT_LDO_P0_0P1A_ANA + need_des + 0x1BC + 0x20 + 0xB1000000 + + + ANA_0P1A_MUL_0 + need_des + 23 + 3 + read-write + + + ANA_0P1A_EN_VDET_0 + need_des + 26 + 1 + read-write + + + ANA_0P1A_EN_CUR_LIM_0 + need_des + 27 + 1 + read-write + + + ANA_0P1A_DREF_0 + need_des + 28 + 4 + read-write + + + + + EXT_LDO_P0_0P2A + need_des + 0x1C0 + 0x20 + 0x40200000 + + + _0P2A_FORCE_TIEH_SEL_0 + need_des + 7 + 1 + read-write + + + _0P2A_XPD_0 + need_des + 8 + 1 + read-write + + + _0P2A_TIEH_SEL_0 + need_des + 9 + 3 + read-write + + + _0P2A_TIEH_POS_EN_0 + need_des + 12 + 1 + read-write + + + _0P2A_TIEH_NEG_EN_0 + need_des + 13 + 1 + read-write + + + _0P2A_TIEH_0 + need_des + 14 + 1 + read-write + + + _0P2A_TARGET1_0 + need_des + 15 + 8 + read-write + + + _0P2A_TARGET0_0 + need_des + 23 + 8 + read-write + + + _0P2A_LDO_CNT_PRESCALER_SEL_0 + need_des + 31 + 1 + read-write + + + + + EXT_LDO_P0_0P2A_ANA + need_des + 0x1C4 + 0x20 + 0xA0000000 + + + ANA_0P2A_MUL_0 + need_des + 23 + 3 + read-write + + + ANA_0P2A_EN_VDET_0 + need_des + 26 + 1 + read-write + + + ANA_0P2A_EN_CUR_LIM_0 + need_des + 27 + 1 + read-write + + + ANA_0P2A_DREF_0 + need_des + 28 + 4 + read-write + + + + + EXT_LDO_P0_0P3A + need_des + 0x1C8 + 0x20 + 0x40200000 + + + _0P3A_FORCE_TIEH_SEL_0 + need_des + 7 + 1 + read-write + + + _0P3A_XPD_0 + need_des + 8 + 1 + read-write + + + _0P3A_TIEH_SEL_0 + need_des + 9 + 3 + read-write + + + _0P3A_TIEH_POS_EN_0 + need_des + 12 + 1 + read-write + + + _0P3A_TIEH_NEG_EN_0 + need_des + 13 + 1 + read-write + + + _0P3A_TIEH_0 + need_des + 14 + 1 + read-write + + + _0P3A_TARGET1_0 + need_des + 15 + 8 + read-write + + + _0P3A_TARGET0_0 + need_des + 23 + 8 + read-write + + + _0P3A_LDO_CNT_PRESCALER_SEL_0 + need_des + 31 + 1 + read-write + + + + + EXT_LDO_P0_0P3A_ANA + need_des + 0x1CC + 0x20 + 0xA0000000 + + + ANA_0P3A_MUL_0 + need_des + 23 + 3 + read-write + + + ANA_0P3A_EN_VDET_0 + need_des + 26 + 1 + read-write + + + ANA_0P3A_EN_CUR_LIM_0 + need_des + 27 + 1 + read-write + + + ANA_0P3A_DREF_0 + need_des + 28 + 4 + read-write + + + + + EXT_LDO_P1_0P1A + need_des + 0x1D0 + 0x20 + 0x40200000 + + + _0P1A_FORCE_TIEH_SEL_1 + need_des + 7 + 1 + read-write + + + _0P1A_XPD_1 + need_des + 8 + 1 + read-write + + + _0P1A_TIEH_SEL_1 + need_des + 9 + 3 + read-write + + + _0P1A_TIEH_POS_EN_1 + need_des + 12 + 1 + read-write + + + _0P1A_TIEH_NEG_EN_1 + need_des + 13 + 1 + read-write + + + _0P1A_TIEH_1 + need_des + 14 + 1 + read-write + + + _0P1A_TARGET1_1 + need_des + 15 + 8 + read-write + + + _0P1A_TARGET0_1 + need_des + 23 + 8 + read-write + + + _0P1A_LDO_CNT_PRESCALER_SEL_1 + need_des + 31 + 1 + read-write + + + + + EXT_LDO_P1_0P1A_ANA + need_des + 0x1D4 + 0x20 + 0xA0000000 + + + ANA_0P1A_MUL_1 + need_des + 23 + 3 + read-write + + + ANA_0P1A_EN_VDET_1 + need_des + 26 + 1 + read-write + + + ANA_0P1A_EN_CUR_LIM_1 + need_des + 27 + 1 + read-write + + + ANA_0P1A_DREF_1 + need_des + 28 + 4 + read-write + + + + + EXT_LDO_P1_0P2A + need_des + 0x1D8 + 0x20 + 0x40200000 + + + _0P2A_FORCE_TIEH_SEL_1 + need_des + 7 + 1 + read-write + + + _0P2A_XPD_1 + need_des + 8 + 1 + read-write + + + _0P2A_TIEH_SEL_1 + need_des + 9 + 3 + read-write + + + _0P2A_TIEH_POS_EN_1 + need_des + 12 + 1 + read-write + + + _0P2A_TIEH_NEG_EN_1 + need_des + 13 + 1 + read-write + + + _0P2A_TIEH_1 + need_des + 14 + 1 + read-write + + + _0P2A_TARGET1_1 + need_des + 15 + 8 + read-write + + + _0P2A_TARGET0_1 + need_des + 23 + 8 + read-write + + + _0P2A_LDO_CNT_PRESCALER_SEL_1 + need_des + 31 + 1 + read-write + + + + + EXT_LDO_P1_0P2A_ANA + need_des + 0x1DC + 0x20 + 0xA0000000 + + + ANA_0P2A_MUL_1 + need_des + 23 + 3 + read-write + + + ANA_0P2A_EN_VDET_1 + need_des + 26 + 1 + read-write + + + ANA_0P2A_EN_CUR_LIM_1 + need_des + 27 + 1 + read-write + + + ANA_0P2A_DREF_1 + need_des + 28 + 4 + read-write + + + + + EXT_LDO_P1_0P3A + need_des + 0x1E0 + 0x20 + 0x40200000 + + + _0P3A_FORCE_TIEH_SEL_1 + need_des + 7 + 1 + read-write + + + _0P3A_XPD_1 + need_des + 8 + 1 + read-write + + + _0P3A_TIEH_SEL_1 + need_des + 9 + 3 + read-write + + + _0P3A_TIEH_POS_EN_1 + need_des + 12 + 1 + read-write + + + _0P3A_TIEH_NEG_EN_1 + need_des + 13 + 1 + read-write + + + _0P3A_TIEH_1 + need_des + 14 + 1 + read-write + + + _0P3A_TARGET1_1 + need_des + 15 + 8 + read-write + + + _0P3A_TARGET0_1 + need_des + 23 + 8 + read-write + + + _0P3A_LDO_CNT_PRESCALER_SEL_1 + need_des + 31 + 1 + read-write + + + + + EXT_LDO_P1_0P3A_ANA + need_des + 0x1E4 + 0x20 + 0xA0000000 + + + ANA_0P3A_MUL_1 + need_des + 23 + 3 + read-write + + + ANA_0P3A_EN_VDET_1 + need_des + 26 + 1 + read-write + + + ANA_0P3A_EN_CUR_LIM_1 + need_des + 27 + 1 + read-write + + + ANA_0P3A_DREF_1 + need_des + 28 + 4 + read-write + + + + + EXT_WAKEUP_LV + need_des + 0x1E8 + 0x20 + + + EXT_WAKEUP_LV + need_des + 0 + 32 + read-write + + + + + EXT_WAKEUP_SEL + need_des + 0x1EC + 0x20 + + + EXT_WAKEUP_SEL + need_des + 0 + 32 + read-write + + + + + EXT_WAKEUP_ST + need_des + 0x1F0 + 0x20 + + + EXT_WAKEUP_STATUS + need_des + 0 + 32 + read-only + + + + + EXT_WAKEUP_CNTL + need_des + 0x1F4 + 0x20 + + + EXT_WAKEUP_STATUS_CLR + need_des + 30 + 1 + read-write + + + EXT_WAKEUP_FILTER + need_des + 31 + 1 + read-write + + + + + SDIO_WAKEUP_CNTL + need_des + 0x1F8 + 0x20 + 0x000003FF + + + SDIO_ACT_DNUM + need_des + 0 + 10 + read-write + + + + + XTAL_SLP + need_des + 0x1FC + 0x20 + 0x000F0000 + + + CNT_TARGET + need_des + 16 + 16 + read-write + + + + + CPU_SW_STALL + need_des + 0x200 + 0x20 + + + HPCORE1_SW_STALL_CODE + need_des + 16 + 8 + read-write + + + HPCORE0_SW_STALL_CODE + need_des + 24 + 8 + read-write + + + + + DCM_CTRL + need_des + 0x204 + 0x20 + 0x00010000 + + + DCDC_ON_REQ + SW trigger dcdc on + 0 + 1 + write-only + + + DCDC_OFF_REQ + SW trigger dcdc off + 1 + 1 + write-only + + + DCDC_LIGHTSLP_REQ + SW trigger dcdc enter lightsleep + 2 + 1 + write-only + + + DCDC_DEEPSLP_REQ + SW trigger dcdc enter deepsleep + 3 + 1 + write-only + + + DCDC_DONE_FORCE + need_des + 7 + 1 + read-write + + + DCDC_ON_FORCE_PU + need_des + 8 + 1 + read-write + + + DCDC_ON_FORCE_PD + need_des + 9 + 1 + read-write + + + DCDC_FB_RES_FORCE_PU + need_des + 10 + 1 + read-write + + + DCDC_FB_RES_FORCE_PD + need_des + 11 + 1 + read-write + + + DCDC_LS_FORCE_PU + need_des + 12 + 1 + read-write + + + DCDC_LS_FORCE_PD + need_des + 13 + 1 + read-write + + + DCDC_DS_FORCE_PU + need_des + 14 + 1 + read-write + + + DCDC_DS_FORCE_PD + need_des + 15 + 1 + read-write + + + DCM_CUR_ST + need_des + 16 + 8 + read-only + + + DCDC_EN_AMUX_TEST + Enable analog mux to pull PAD TEST_DCDC voltage signal + 29 + 1 + read-write + + + + + DCM_WAIT_DELAY + need_des + 0x208 + 0x20 + 0x004B0205 + + + DCDC_PRE_DELAY + DCDC pre-on/post off delay + 0 + 8 + read-write + + + DCDC_RES_OFF_DELAY + DCDC fb res off delay + 8 + 8 + read-write + + + DCDC_STABLE_DELAY + DCDC stable delay + 16 + 10 + read-write + + + + + VDDBAT_CFG + need_des + 0x20C + 0x20 + + + ANA_VDDBAT_MODE + need_des + 0 + 2 + read-only + + + VDDBAT_SW_UPDATE + need_des + 31 + 1 + write-only + + + + + TOUCH_PWR_CNTL + need_des + 0x210 + 0x20 + 0x00190140 + + + TOUCH_WAIT_CYCLES + need_des + 5 + 9 + read-write + + + TOUCH_SLEEP_CYCLES + need_des + 14 + 16 + read-write + + + TOUCH_FORCE_DONE + need_des + 30 + 1 + read-write + + + TOUCH_SLEEP_TIMER_EN + need_des + 31 + 1 + read-write + + + + + RDN_ECO + need_des + 0x214 + 0x20 + + + PMU_RDN_ECO_RESULT + need_des + 0 + 1 + read-only + + + PMU_RDN_ECO_EN + need_des + 31 + 1 + read-write + + + + + DATE + need_des + 0x3FC + 0x20 + 0x02303140 + + + PMU_DATE + need_des + 0 + 31 + read-write + + + CLK_EN + need_des + 31 + 1 + read-write + + + + + + + PPA + PPA Peripheral + PPA + 0x50087000 + + 0x0 + 0x88 + registers + + + PPA + 96 + + + + BLEND0_CLUT_DATA + CLUT sram data read/write register in background plane of blender + 0x0 + 0x20 + + + RDWR_WORD_BLEND0_CLUT + Write and read data to/from CLUT RAM in background plane of blender engine through this field in fifo mode. + 0 + 32 + read-write + + + + + BLEND1_CLUT_DATA + CLUT sram data read/write register in foreground plane of blender + 0x4 + 0x20 + + + RDWR_WORD_BLEND1_CLUT + Write and read data to/from CLUT RAM in foreground plane of blender engine through this field in fifo mode. + 0 + 32 + read-write + + + + + CLUT_CONF + CLUT configure register + 0xC + 0x20 + + + APB_FIFO_MASK + 1'b0: fifo mode to wr/rd clut0/clut1 RAM through register PPA_SR_CLUT_DATA_REG/PPA_BLEND0_CLUT_DATA_REG/PPA_BLEND1_CLUT_DATA_REG. 1'b1: memory mode to wr/rd sr/blend0/blend1 clut RAM. The bit 11 and 10 of the waddr should be 01 to access sr clut and should be 10 to access blend0 clut and should be 11 to access blend 1 clut in memory mode. + 0 + 1 + read-write + + + BLEND0_CLUT_MEM_RST + Write 1 then write 0 to this bit to reset BLEND0 CLUT. + 1 + 1 + read-write + + + BLEND1_CLUT_MEM_RST + Write 1 then write 0 to this bit to reset BLEND1 CLUT. + 2 + 1 + read-write + + + BLEND0_CLUT_MEM_RDADDR_RST + Write 1 then write 0 to reset the read address of BLEND0 CLUT in fifo mode. + 3 + 1 + read-write + + + BLEND1_CLUT_MEM_RDADDR_RST + Write 1 then write 0 to reset the read address of BLEND1 CLUT in fifo mode. + 4 + 1 + read-write + + + BLEND0_CLUT_MEM_FORCE_PD + 1: force power down BLEND CLUT memory. + 5 + 1 + read-write + + + BLEND0_CLUT_MEM_FORCE_PU + 1: force power up BLEND CLUT memory. + 6 + 1 + read-write + + + BLEND0_CLUT_MEM_CLK_ENA + 1: Force clock on for BLEND CLUT memory. + 7 + 1 + read-write + + + + + INT_RAW + Raw status interrupt + 0x10 + 0x20 + + + SR_EOF_INT_RAW + The raw interrupt bit turns to high level when scaling and rotating engine calculate one frame image. + 0 + 1 + read-write + + + BLEND_EOF_INT_RAW + The raw interrupt bit turns to high level when blending engine calculate one frame image. + 1 + 1 + read-write + + + SR_PARAM_CFG_ERR_INT_RAW + The raw interrupt bit turns to high level when the configured scaling and rotating coefficient is wrong. User can check the reasons through register PPA_SR_PARAM_ERR_ST_REG. + 2 + 1 + read-write + + + + + INT_ST + Masked interrupt + 0x14 + 0x20 + + + SR_EOF_INT_ST + The raw interrupt status bit for the PPA_SR_EOF_INT interrupt. + 0 + 1 + read-only + + + BLEND_EOF_INT_ST + The raw interrupt status bit for the PPA_BLEND_EOF_INT interrupt. + 1 + 1 + read-only + + + SR_PARAM_CFG_ERR_INT_ST + The raw interrupt status bit for the PPA_SR_RX_YSCAL_ERR_INT interrupt. + 2 + 1 + read-only + + + + + INT_ENA + Interrupt enable bits + 0x18 + 0x20 + + + SR_EOF_INT_ENA + The interrupt enable bit for the PPA_SR_EOF_INT interrupt. + 0 + 1 + read-write + + + BLEND_EOF_INT_ENA + The interrupt enable bit for the PPA_BLEND_EOF_INT interrupt. + 1 + 1 + read-write + + + SR_PARAM_CFG_ERR_INT_ENA + The interrupt enable bit for the PPA_SR_RX_YSCAL_ERR_INT interrupt. + 2 + 1 + read-write + + + + + INT_CLR + Interrupt clear bits + 0x1C + 0x20 + + + SR_EOF_INT_CLR + Set this bit to clear the PPA_SR_EOF_INT interrupt. + 0 + 1 + write-only + + + BLEND_EOF_INT_CLR + Set this bit to clear the PPA_BLEND_EOF_INT interrupt. + 1 + 1 + write-only + + + SR_PARAM_CFG_ERR_INT_CLR + Set this bit to clear the PPA_SR_RX_YSCAL_ERR_INT interrupt. + 2 + 1 + write-only + + + + + SR_COLOR_MODE + Scaling and rotating engine color mode register + 0x20 + 0x20 + + + SR_RX_CM + The source image color mode for Scaling and Rotating engine Rx. 0: ARGB8888. 1: RGB888. 2: RGB565. 8: YUV420. others: Reserved. + 0 + 4 + read-write + + + SR_TX_CM + The destination image color mode for Scaling and Rotating engine Tx. 0: ARGB8888. 1: RGB888. 2: RGB565. 8: YUV420. others: Reserved. + 4 + 4 + read-write + + + YUV_RX_RANGE + YUV input range when reg_sr_rx_cm is 4'd8. 0: limit range. 1: full range + 8 + 1 + read-write + + + YUV_TX_RANGE + YUV output range when reg_sr_tx_cm is 4'd8. 0: limit range. 1: full range + 9 + 1 + read-write + + + YUV2RGB_PROTOCAL + YUV to RGB protocal when reg_sr_rx_cm is 4'd8. 0: BT601. 1: BT709 + 10 + 1 + read-write + + + RGB2YUV_PROTOCAL + RGB to YUV protocal when reg_sr_tx_cm is 4'd8. 0: BT601. 1: BT709 + 11 + 1 + read-write + + + + + BLEND_COLOR_MODE + blending engine color mode register + 0x24 + 0x20 + + + BLEND0_RX_CM + The source image color mode for background plane. 0: ARGB8888. 1: RGB888. 2: RGB565. 3: Reserved. 4: L8. 5: L4. + 0 + 4 + read-write + + + BLEND1_RX_CM + The source image color mode for foreground plane. 0: ARGB8888. 1: RGB888. 2: RGB565. 3: Reserved. 4: L8. 5: L4. 6: A8. 7: A4. + 4 + 4 + read-write + + + BLEND_TX_CM + The destination image color mode for output of blender. 0: ARGB8888. 1: RGB888. 2: RGB565. 3: Reserved.. + 8 + 4 + read-write + + + + + SR_BYTE_ORDER + Scaling and rotating engine byte order register + 0x28 + 0x20 + + + SR_RX_BYTE_SWAP_EN + Set this bit to 1 the data into Rx channel 0 would be swapped in byte. The Byte0 and Byte1 would be swapped while byte 2 and byte 3 would be swappped. + 0 + 1 + read-write + + + SR_RX_RGB_SWAP_EN + Set this bit to 1 the data into Rx channel 0 would be swapped in rgb. It means rgb would be swap to bgr. + 1 + 1 + read-write + + + SR_MACRO_BK_RO_BYPASS + Set this bit to 1 to bypass the macro block order function. This function is used to improve efficient accessing external memory. + 2 + 1 + read-write + + + + + BLEND_BYTE_ORDER + Blending engine byte order register + 0x2C + 0x20 + + + BLEND0_RX_BYTE_SWAP_EN + Set this bit to 1 the data into Rx channel 0 would be swapped in byte. The Byte0 and Byte1 would be swapped while byte 2 and byte 3 would be swappped. + 0 + 1 + read-write + + + BLEND1_RX_BYTE_SWAP_EN + Set this bit to 1 the data into Rx channel 0 would be swapped in byte. The Byte0 and Byte1 would be swapped while byte 2 and byte 3 would be swappped. + 1 + 1 + read-write + + + BLEND0_RX_RGB_SWAP_EN + Set this bit to 1 the data into Rx channel 0 would be swapped in rgb. It means rgb would be swap to bgr. + 2 + 1 + read-write + + + BLEND1_RX_RGB_SWAP_EN + Set this bit to 1 the data into Rx channel 0 would be swapped in rgb. It means rgb would be swap to bgr. + 3 + 1 + read-write + + + + + BLEND_TRANS_MODE + Blending engine mode configure register + 0x34 + 0x20 + + + BLEND_EN + Set this bit to enable alpha blending. + 0 + 1 + read-write + + + BLEND_BYPASS + Set this bit to bypass blender. Then background date would be output. + 1 + 1 + read-write + + + BLEND_FIX_PIXEL_FILL_EN + This bit is used to enable fix pixel filling. When this mode is enable only Tx channel is work and the output pixel is configured by PPA_OUT_FIX_PIXEL. + 2 + 1 + read-write + + + UPDATE + Set this bit to update the transfer mode. Only the bit is set the transfer mode is valid. + 3 + 1 + write-only + + + BLEND_RST + write 1 then write 0 to reset blending engine. + 4 + 1 + read-write + + + + + SR_FIX_ALPHA + Scaling and rotating engine alpha override register + 0x38 + 0x20 + 0x00000080 + + + SR_RX_FIX_ALPHA + The value would replace the alpha value in received pixel for Scaling and Rotating engine when PPA_SR_RX_ALPHA_CONF_EN is enabled. + 0 + 8 + read-write + + + SR_RX_ALPHA_MOD + Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_SR_FIX_ALPHA. 2: Original alpha multiply with PPA_SR_FIX_ALPHA/256. + 8 + 2 + read-write + + + SR_RX_ALPHA_INV + Set this bit to invert the original alpha value. When RX color mode is RGB565/RGB88. The original alpha value is 255. + 10 + 1 + read-write + + + + + BLEND_TX_SIZE + Fix pixel filling mode image size register + 0x3C + 0x20 + + + BLEND_HB + The horizontal width of image block that would be filled in fix pixel filling mode. The unit is pixel + 0 + 14 + read-write + + + BLEND_VB + The vertical width of image block that would be filled in fix pixel filling mode. The unit is pixel + 14 + 14 + read-write + + + + + BLEND_FIX_ALPHA + Blending engine alpha override register + 0x40 + 0x20 + 0x00008080 + + + BLEND0_RX_FIX_ALPHA + The value would replace the alpha value in received pixel for background plane of blender when PPA_BLEND0_RX_ALPHA_CONF_EN is enabled. + 0 + 8 + read-write + + + BLEND1_RX_FIX_ALPHA + The value would replace the alpha value in received pixel for foreground plane of blender when PPA_BLEND1_RX_ALPHA_CONF_EN is enabled. + 8 + 8 + read-write + + + BLEND0_RX_ALPHA_MOD + Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_SR_FIX_ALPHA. 2: Original alpha multiply with PPA_SR_FIX_ALPHA/256. + 16 + 2 + read-write + + + BLEND1_RX_ALPHA_MOD + Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_SR_FIX_ALPHA. 2: Original alpha multiply with PPA_SR_FIX_ALPHA/256. + 18 + 2 + read-write + + + BLEND0_RX_ALPHA_INV + Set this bit to invert the original alpha value. When RX color mode is RGB565/RGB88. The original alpha value is 255. + 20 + 1 + read-write + + + BLEND1_RX_ALPHA_INV + Set this bit to invert the original alpha value. When RX color mode is RGB565/RGB88. The original alpha value is 255. + 21 + 1 + read-write + + + + + BLEND_RGB + RGB color register + 0x48 + 0x20 + 0x00808080 + + + BLEND1_RX_B + blue color for A4/A8 mode. + 0 + 8 + read-write + + + BLEND1_RX_G + green color for A4/A8 mode. + 8 + 8 + read-write + + + BLEND1_RX_R + red color for A4/A8 mode. + 16 + 8 + read-write + + + + + BLEND_FIX_PIXEL + Blending engine fix pixel register + 0x4C + 0x20 + + + BLEND_TX_FIX_PIXEL + The configure fix pixel in fix pixel filling mode for blender engine. + 0 + 32 + read-write + + + + + CK_FG_LOW + foreground color key lower threshold + 0x50 + 0x20 + 0x00FFFFFF + + + COLORKEY_FG_B_LOW + color key lower threshold of foreground b channel + 0 + 8 + read-write + + + COLORKEY_FG_G_LOW + color key lower threshold of foreground g channel + 8 + 8 + read-write + + + COLORKEY_FG_R_LOW + color key lower threshold of foreground r channel + 16 + 8 + read-write + + + + + CK_FG_HIGH + foreground color key higher threshold + 0x54 + 0x20 + + + COLORKEY_FG_B_HIGH + color key higher threshold of foreground b channel + 0 + 8 + read-write + + + COLORKEY_FG_G_HIGH + color key higher threshold of foreground g channel + 8 + 8 + read-write + + + COLORKEY_FG_R_HIGH + color key higher threshold of foreground r channel + 16 + 8 + read-write + + + + + CK_BG_LOW + background color key lower threshold + 0x58 + 0x20 + 0x00FFFFFF + + + COLORKEY_BG_B_LOW + color key lower threshold of background b channel + 0 + 8 + read-write + + + COLORKEY_BG_G_LOW + color key lower threshold of background g channel + 8 + 8 + read-write + + + COLORKEY_BG_R_LOW + color key lower threshold of background r channel + 16 + 8 + read-write + + + + + CK_BG_HIGH + background color key higher threshold + 0x5C + 0x20 + + + COLORKEY_BG_B_HIGH + color key higher threshold of background b channel + 0 + 8 + read-write + + + COLORKEY_BG_G_HIGH + color key higher threshold of background g channel + 8 + 8 + read-write + + + COLORKEY_BG_R_HIGH + color key higher threshold of background r channel + 16 + 8 + read-write + + + + + CK_DEFAULT + default value when foreground and background both in color key range + 0x60 + 0x20 + + + COLORKEY_DEFAULT_B + default B channle value of color key + 0 + 8 + read-write + + + COLORKEY_DEFAULT_G + default G channle value of color key + 8 + 8 + read-write + + + COLORKEY_DEFAULT_R + default R channle value of color key + 16 + 8 + read-write + + + COLORKEY_FG_BG_REVERSE + when pixel in bg ck range but not in fg ck range, 0: the result is bg, 1: the result is fg + 24 + 1 + read-write + + + + + SR_SCAL_ROTATE + Scaling and rotating coefficient register + 0x64 + 0x20 + 0x00001001 + + + SR_SCAL_X_INT + The integrated part of scaling coefficient in X direction. + 0 + 8 + read-write + + + SR_SCAL_X_FRAG + The fragment part of scaling coefficient in X direction. + 8 + 4 + read-write + + + SR_SCAL_Y_INT + The integrated part of scaling coefficient in Y direction. + 12 + 8 + read-write + + + SR_SCAL_Y_FRAG + The fragment part of scaling coefficient in Y direction. + 20 + 4 + read-write + + + SR_ROTATE_ANGLE + The rotate angle. 0: 0 degree. 1: 90 degree. 2: 180 degree. 3: 270 degree. + 24 + 2 + read-write + + + SCAL_ROTATE_RST + Write 1 then write 0 to this bit to reset scaling and rotating engine. + 26 + 1 + read-write + + + SCAL_ROTATE_START + Write 1 to enable scaling and rotating engine after parameter is configured. + 27 + 1 + write-only + + + SR_MIRROR_X + Image mirror in X direction. 0: disable, 1: enable + 28 + 1 + read-write + + + SR_MIRROR_Y + Image mirror in Y direction. 0: disable, 1: enable + 29 + 1 + read-write + + + + + SR_MEM_PD + SR memory power done register + 0x68 + 0x20 + + + SR_MEM_CLK_ENA + Set this bit to force clock enable of scaling and rotating engine's data memory. + 0 + 1 + read-write + + + SR_MEM_FORCE_PD + Set this bit to force power down scaling and rotating engine's data memory. + 1 + 1 + read-write + + + SR_MEM_FORCE_PU + Set this bit to force power up scaling and rotating engine's data memory. + 2 + 1 + read-write + + + + + REG_CONF + Register clock enable register + 0x6C + 0x20 + + + CLK_EN + PPA register clock gate enable signal. + 0 + 1 + read-write + + + + + CLUT_CNT + BLEND CLUT write counter register + 0x70 + 0x20 + + + BLEND0_CLUT_CNT + The write data counter of BLEND0 CLUT in fifo mode. + 0 + 9 + read-only + + + BLEND1_CLUT_CNT + The write data counter of BLEND1 CLUT in fifo mode. + 9 + 9 + read-only + + + + + BLEND_ST + Blending engine status register + 0x74 + 0x20 + + + BLEND_SIZE_DIFF_ST + 1: indicate the size of two image is different. + 0 + 1 + read-only + + + + + SR_PARAM_ERR_ST + Scaling and rotating coefficient error register + 0x78 + 0x20 + + + TX_DSCR_VB_ERR_ST + The error is that the scaled VB plus the offset of Y coordinate in 2DDMA receive descriptor is larger than VA in 2DDMA receive descriptor. + 0 + 1 + read-only + + + TX_DSCR_HB_ERR_ST + The error is that the scaled HB plus the offset of X coordinate in 2DDMA receive descriptor is larger than HA in 2DDMA receive descriptor. + 1 + 1 + read-only + + + Y_RX_SCAL_EQUAL_0_ERR_ST + The error is that the PPA_SR_SCAL_Y_INT and PPA_SR_CAL_Y_FRAG both are 0. + 2 + 1 + read-only + + + RX_DSCR_VB_ERR_ST + The error is that VB in 2DDMA receive descriptor plus the offset of Y coordinate in 2DDMA transmit descriptor is larger than VA in 2DDMA transmit descriptor + 3 + 1 + read-only + + + YDST_LEN_TOO_SAMLL_ERR_ST + The error is that the scaled image width is 0. For example. when source width is 14. scaled value is 1/16. and no rotate operation. then scaled width would be 0 as the result would be floored. + 4 + 1 + read-only + + + YDST_LEN_TOO_LARGE_ERR_ST + The error is that the scaled width is larger than (2^13 - 1). + 5 + 1 + read-only + + + X_RX_SCAL_EQUAL_0_ERR_ST + The error is that the scaled image height is 0. + 6 + 1 + read-only + + + RX_DSCR_HB_ERR_ST + The error is that the HB in 2DDMA transmit descriptor plus the offset of X coordinate in 2DDMA transmit descriptor is larger than HA in 2DDMA transmit descriptor. + 7 + 1 + read-only + + + XDST_LEN_TOO_SAMLL_ERR_ST + The error is that the scaled image height is 0. For example. when source height is 14. scaled value is 1/16. and no rotate operation. then scaled height would be 0 as the result would be floored. + 8 + 1 + read-only + + + XDST_LEN_TOO_LARGE_ERR_ST + The error is that the scaled image height is larger than (2^13 - 1). + 9 + 1 + read-only + + + X_YUV420_RX_SCALE_ERR_ST + The error is that the ha/hb/x param in dma2d descriptor is an odd num when enable yuv420 rx + 10 + 1 + read-only + + + Y_YUV420_RX_SCALE_ERR_ST + The error is that the va/vb/y param in dma2d descriptor is an odd num when enable yuv420 rx + 11 + 1 + read-only + + + X_YUV420_TX_SCALE_ERR_ST + The error is that the ha/hb/x param in dma2d descriptor is an odd num when enable yuv420 tx + 12 + 1 + read-only + + + Y_YUV420_TX_SCALE_ERR_ST + The error is that the va/vb/y param in dma2d descriptor is an odd num when enable yuv420 tx + 13 + 1 + read-only + + + + + SR_STATUS + SR FSM register + 0x7C + 0x20 + + + SR_RX_DSCR_SAMPLE_STATE + Reserved. + 0 + 2 + read-only + + + SR_RX_SCAN_STATE + Reserved. + 2 + 2 + read-only + + + SR_TX_DSCR_SAMPLE_STATE + Reserved. + 4 + 2 + read-only + + + SR_TX_SCAN_STATE + Reserved. + 6 + 3 + read-only + + + + + ECO_LOW + Reserved. + 0x80 + 0x20 + + + RND_ECO_LOW + Reserved. + 0 + 32 + read-write + + + + + ECO_HIGH + Reserved. + 0x84 + 0x20 + 0xFFFFFFFF + + + RND_ECO_HIGH + Reserved. + 0 + 32 + read-write + + + + + ECO_CELL_CTRL + Reserved. + 0x88 + 0x20 + + + RDN_RESULT + Reserved. + 0 + 1 + read-only + + + RDN_ENA + Reserved. + 1 + 1 + read-write + + + + + SRAM_CTRL + PPA SRAM Control Register + 0x8C + 0x20 + 0x00001320 + + + MEM_AUX_CTRL + Control signals + 0 + 14 + read-write + + + + + DATE + PPA Version register + 0x100 + 0x20 + 0x02304041 + + + DATE + register version. + 0 + 32 + read-write + + + + + + + PVT + PVT Peripheral + PVT + 0x5009E000 + + 0x0 + 0x1F0 + registers + + + + PMUP_BITMAP_HIGH0 + select valid pvt channel + 0x0 + 0x20 + + + PUMP_BITMAP_HIGH0 + select valid high channel0 + 0 + 32 + read-write + + + + + PMUP_BITMAP_HIGH1 + select valid pvt channel + 0x4 + 0x20 + + + PUMP_BITMAP_HIGH1 + select valid high channel1 + 0 + 32 + read-write + + + + + PMUP_BITMAP_HIGH2 + select valid pvt channel + 0x8 + 0x20 + + + PUMP_BITMAP_HIGH2 + select valid high channel2 + 0 + 32 + read-write + + + + + PMUP_BITMAP_HIGH3 + select valid pvt channel + 0xC + 0x20 + + + PUMP_BITMAP_HIGH3 + select valid high channel3 + 0 + 32 + read-write + + + + + PMUP_BITMAP_HIGH4 + select valid pvt channel + 0x10 + 0x20 + + + PUMP_BITMAP_HIGH4 + select valid high channel4 + 0 + 32 + read-write + + + + + PMUP_BITMAP_LOW0 + select valid pvt channel + 0x14 + 0x20 + + + PUMP_BITMAP_LOW0 + select valid low channel0 + 0 + 32 + read-write + + + + + PMUP_BITMAP_LOW1 + select valid pvt channel + 0x18 + 0x20 + + + PUMP_BITMAP_LOW1 + select valid low channel1 + 0 + 32 + read-write + + + + + PMUP_BITMAP_LOW2 + select valid pvt channel + 0x1C + 0x20 + + + PUMP_BITMAP_LOW2 + select valid low channel2 + 0 + 32 + read-write + + + + + PMUP_BITMAP_LOW3 + select valid pvt channel + 0x20 + 0x20 + + + PUMP_BITMAP_LOW3 + select valid low channel3 + 0 + 32 + read-write + + + + + PMUP_BITMAP_LOW4 + select valid pvt channel + 0x24 + 0x20 + + + PUMP_BITMAP_LOW4 + select valid low channel4 + 0 + 32 + read-write + + + + + PMUP_DRV_CFG + configure pump drv + 0x28 + 0x20 + + + PUMP_EN + configure pvt charge xpd + 9 + 1 + read-write + + + CLK_EN + force register clken + 10 + 1 + read-write + + + PUMP_DRV4 + configure cmd4 drv + 11 + 4 + read-write + + + PUMP_DRV3 + configure cmd3 drv + 15 + 4 + read-write + + + PUMP_DRV2 + configure cmd2 drv + 19 + 4 + read-write + + + PUMP_DRV1 + configure cmd1 drv + 23 + 4 + read-write + + + PUMP_DRV0 + configure cmd0 drv + 27 + 4 + read-write + + + + + PMUP_CHANNEL_CFG + configure the code of valid pump channel code + 0x2C + 0x20 + + + PUMP_CHANNEL_CODE4 + configure cmd4 code + 7 + 5 + read-write + + + PUMP_CHANNEL_CODE3 + configure cmd3 code + 12 + 5 + read-write + + + PUMP_CHANNEL_CODE2 + configure cmd2 code + 17 + 5 + read-write + + + PUMP_CHANNEL_CODE1 + configure cmd1 code + 22 + 5 + read-write + + + PUMP_CHANNEL_CODE0 + configure cmd0 code + 27 + 5 + read-write + + + + + CLK_CFG + configure pvt clk + 0x30 + 0x20 + + + PUMP_CLK_DIV_NUM + needs field desc + 0 + 8 + read-write + + + MONITOR_CLK_PVT_EN + needs field desc + 8 + 1 + read-write + + + CLK_SEL + select pvt clk + 31 + 1 + read-write + + + + + DBIAS_CHANNEL_SEL0 + needs desc + 0x34 + 0x20 + 0x81020400 + + + DBIAS_CHANNEL3_SEL + needs field desc + 4 + 7 + read-write + + + DBIAS_CHANNEL2_SEL + needs field desc + 11 + 7 + read-write + + + DBIAS_CHANNEL1_SEL + needs field desc + 18 + 7 + read-write + + + DBIAS_CHANNEL0_SEL + needs field desc + 25 + 7 + read-write + + + + + DBIAS_CHANNEL_SEL1 + needs desc + 0x38 + 0x20 + 0x80000000 + + + DBIAS_CHANNEL4_SEL + needs field desc + 25 + 7 + read-write + + + + + DBIAS_CHANNEL0_SEL + needs desc + 0x3C + 0x20 + + + DBIAS_CHANNEL0_CFG + needs field desc + 0 + 17 + read-write + + + + + DBIAS_CHANNEL1_SEL + needs desc + 0x40 + 0x20 + + + DBIAS_CHANNEL1_CFG + needs field desc + 0 + 17 + read-write + + + + + DBIAS_CHANNEL2_SEL + needs desc + 0x44 + 0x20 + + + DBIAS_CHANNEL2_CFG + needs field desc + 0 + 17 + read-write + + + + + DBIAS_CHANNEL3_SEL + needs desc + 0x48 + 0x20 + + + DBIAS_CHANNEL3_CFG + needs field desc + 0 + 17 + read-write + + + + + DBIAS_CHANNEL4_SEL + needs desc + 0x4C + 0x20 + + + DBIAS_CHANNEL4_CFG + needs field desc + 0 + 17 + read-write + + + + + DBIAS_CMD0 + needs desc + 0x50 + 0x20 + + + DBIAS_CMD0 + needs field desc + 0 + 17 + read-write + + + + + DBIAS_CMD1 + needs desc + 0x54 + 0x20 + + + DBIAS_CMD1 + needs field desc + 0 + 17 + read-write + + + + + DBIAS_CMD2 + needs desc + 0x58 + 0x20 + + + DBIAS_CMD2 + needs field desc + 0 + 17 + read-write + + + + + DBIAS_CMD3 + needs desc + 0x5C + 0x20 + + + DBIAS_CMD3 + needs field desc + 0 + 17 + read-write + + + + + DBIAS_CMD4 + needs desc + 0x60 + 0x20 + + + DBIAS_CMD4 + needs field desc + 0 + 17 + read-write + + + + + DBIAS_TIMER + needs desc + 0x64 + 0x20 + 0x7FFF8000 + + + TIMER_TARGET + needs field desc + 15 + 16 + read-write + + + TIMER_EN + needs field desc + 31 + 1 + read-write + + + + + COMB_PD_SITE0_UNIT0_VT0_CONF1 + needs desc + 0x68 + 0x20 + 0x00000050 + + + MONITOR_EN_VT0_PD_SITE0_UNIT0 + needs field desc + 0 + 1 + read-write + + + TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT0 + needs field desc + 1 + 1 + write-only + + + DELAY_LIMIT_VT0_PD_SITE0_UNIT0 + needs field desc + 2 + 8 + read-write + + + DELAY_NUM_O_VT0_PD_SITE0_UNIT0 + needs field desc + 23 + 8 + read-only + + + TIMING_ERR_VT0_PD_SITE0_UNIT0 + needs field desc + 31 + 1 + read-only + + + + + COMB_PD_SITE0_UNIT1_VT0_CONF1 + needs desc + 0x6C + 0x20 + 0x00000050 + + + MONITOR_EN_VT0_PD_SITE0_UNIT1 + needs field desc + 0 + 1 + read-write + + + TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT1 + needs field desc + 1 + 1 + write-only + + + DELAY_LIMIT_VT0_PD_SITE0_UNIT1 + needs field desc + 2 + 8 + read-write + + + DELAY_NUM_O_VT0_PD_SITE0_UNIT1 + needs field desc + 23 + 8 + read-only + + + TIMING_ERR_VT0_PD_SITE0_UNIT1 + needs field desc + 31 + 1 + read-only + + + + + COMB_PD_SITE0_UNIT2_VT0_CONF1 + needs desc + 0x70 + 0x20 + 0x00000050 + + + MONITOR_EN_VT0_PD_SITE0_UNIT2 + needs field desc + 0 + 1 + read-write + + + TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT2 + needs field desc + 1 + 1 + write-only + + + DELAY_LIMIT_VT0_PD_SITE0_UNIT2 + needs field desc + 2 + 8 + read-write + + + DELAY_NUM_O_VT0_PD_SITE0_UNIT2 + needs field desc + 23 + 8 + read-only + + + TIMING_ERR_VT0_PD_SITE0_UNIT2 + needs field desc + 31 + 1 + read-only + + + + + COMB_PD_SITE0_UNIT3_VT0_CONF1 + needs desc + 0x74 + 0x20 + 0x00000050 + + + MONITOR_EN_VT0_PD_SITE0_UNIT3 + needs field desc + 0 + 1 + read-write + + + TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT3 + needs field desc + 1 + 1 + write-only + + + DELAY_LIMIT_VT0_PD_SITE0_UNIT3 + needs field desc + 2 + 8 + read-write + + + DELAY_NUM_O_VT0_PD_SITE0_UNIT3 + needs field desc + 23 + 8 + read-only + + + TIMING_ERR_VT0_PD_SITE0_UNIT3 + needs field desc + 31 + 1 + read-only + + + + + COMB_PD_SITE0_UNIT0_VT1_CONF1 + needs desc + 0x78 + 0x20 + 0x00000050 + + + MONITOR_EN_VT1_PD_SITE0_UNIT0 + needs field desc + 0 + 1 + read-write + + + TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT0 + needs field desc + 1 + 1 + write-only + + + DELAY_LIMIT_VT1_PD_SITE0_UNIT0 + needs field desc + 2 + 8 + read-write + + + DELAY_NUM_O_VT1_PD_SITE0_UNIT0 + needs field desc + 23 + 8 + read-only + + + TIMING_ERR_VT1_PD_SITE0_UNIT0 + needs field desc + 31 + 1 + read-only + + + + + COMB_PD_SITE0_UNIT1_VT1_CONF1 + needs desc + 0x7C + 0x20 + 0x00000050 + + + MONITOR_EN_VT1_PD_SITE0_UNIT1 + needs field desc + 0 + 1 + read-write + + + TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT1 + needs field desc + 1 + 1 + write-only + + + DELAY_LIMIT_VT1_PD_SITE0_UNIT1 + needs field desc + 2 + 8 + read-write + + + DELAY_NUM_O_VT1_PD_SITE0_UNIT1 + needs field desc + 23 + 8 + read-only + + + TIMING_ERR_VT1_PD_SITE0_UNIT1 + needs field desc + 31 + 1 + read-only + + + + + COMB_PD_SITE0_UNIT2_VT1_CONF1 + needs desc + 0x80 + 0x20 + 0x00000050 + + + MONITOR_EN_VT1_PD_SITE0_UNIT2 + needs field desc + 0 + 1 + read-write + + + TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT2 + needs field desc + 1 + 1 + write-only + + + DELAY_LIMIT_VT1_PD_SITE0_UNIT2 + needs field desc + 2 + 8 + read-write + + + DELAY_NUM_O_VT1_PD_SITE0_UNIT2 + needs field desc + 23 + 8 + read-only + + + TIMING_ERR_VT1_PD_SITE0_UNIT2 + needs field desc + 31 + 1 + read-only + + + + + COMB_PD_SITE0_UNIT3_VT1_CONF1 + needs desc + 0x84 + 0x20 + 0x00000050 + + + MONITOR_EN_VT1_PD_SITE0_UNIT3 + needs field desc + 0 + 1 + read-write + + + TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT3 + needs field desc + 1 + 1 + write-only + + + DELAY_LIMIT_VT1_PD_SITE0_UNIT3 + needs field desc + 2 + 8 + read-write + + + DELAY_NUM_O_VT1_PD_SITE0_UNIT3 + needs field desc + 23 + 8 + read-only + + + TIMING_ERR_VT1_PD_SITE0_UNIT3 + needs field desc + 31 + 1 + read-only + + + + + COMB_PD_SITE0_UNIT0_VT2_CONF1 + needs desc + 0x88 + 0x20 + 0x00000050 + + + MONITOR_EN_VT2_PD_SITE0_UNIT0 + needs field desc + 0 + 1 + read-write + + + TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT0 + needs field desc + 1 + 1 + write-only + + + DELAY_LIMIT_VT2_PD_SITE0_UNIT0 + needs field desc + 2 + 8 + read-write + + + DELAY_NUM_O_VT2_PD_SITE0_UNIT0 + needs field desc + 23 + 8 + read-only + + + TIMING_ERR_VT2_PD_SITE0_UNIT0 + needs field desc + 31 + 1 + read-only + + + + + COMB_PD_SITE0_UNIT1_VT2_CONF1 + needs desc + 0x8C + 0x20 + 0x00000050 + + + MONITOR_EN_VT2_PD_SITE0_UNIT1 + needs field desc + 0 + 1 + read-write + + + TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT1 + needs field desc + 1 + 1 + write-only + + + DELAY_LIMIT_VT2_PD_SITE0_UNIT1 + needs field desc + 2 + 8 + read-write + + + DELAY_NUM_O_VT2_PD_SITE0_UNIT1 + needs field desc + 23 + 8 + read-only + + + TIMING_ERR_VT2_PD_SITE0_UNIT1 + needs field desc + 31 + 1 + read-only + + + + + COMB_PD_SITE0_UNIT2_VT2_CONF1 + needs desc + 0x90 + 0x20 + 0x00000050 + + + MONITOR_EN_VT2_PD_SITE0_UNIT2 + needs field desc + 0 + 1 + read-write + + + TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT2 + needs field desc + 1 + 1 + write-only + + + DELAY_LIMIT_VT2_PD_SITE0_UNIT2 + needs field desc + 2 + 8 + read-write + + + DELAY_NUM_O_VT2_PD_SITE0_UNIT2 + needs field desc + 23 + 8 + read-only + + + TIMING_ERR_VT2_PD_SITE0_UNIT2 + needs field desc + 31 + 1 + read-only + + + + + COMB_PD_SITE0_UNIT3_VT2_CONF1 + needs desc + 0x94 + 0x20 + 0x00000050 + + + MONITOR_EN_VT2_PD_SITE0_UNIT3 + needs field desc + 0 + 1 + read-write + + + TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT3 + needs field desc + 1 + 1 + write-only + + + DELAY_LIMIT_VT2_PD_SITE0_UNIT3 + needs field desc + 2 + 8 + read-write + + + DELAY_NUM_O_VT2_PD_SITE0_UNIT3 + needs field desc + 23 + 8 + read-only + + + TIMING_ERR_VT2_PD_SITE0_UNIT3 + needs field desc + 31 + 1 + read-only + + + + + COMB_PD_SITE1_UNIT0_VT0_CONF1 + needs desc + 0x98 + 0x20 + 0x00000050 + + + MONITOR_EN_VT0_PD_SITE1_UNIT0 + needs field desc + 0 + 1 + read-write + + + TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT0 + needs field desc + 1 + 1 + write-only + + + DELAY_LIMIT_VT0_PD_SITE1_UNIT0 + needs field desc + 2 + 8 + read-write + + + DELAY_NUM_O_VT0_PD_SITE1_UNIT0 + needs field desc + 23 + 8 + read-only + + + TIMING_ERR_VT0_PD_SITE1_UNIT0 + needs field desc + 31 + 1 + read-only + + + + + COMB_PD_SITE1_UNIT1_VT0_CONF1 + needs desc + 0x9C + 0x20 + 0x00000050 + + + MONITOR_EN_VT0_PD_SITE1_UNIT1 + needs field desc + 0 + 1 + read-write + + + TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT1 + needs field desc + 1 + 1 + write-only + + + DELAY_LIMIT_VT0_PD_SITE1_UNIT1 + needs field desc + 2 + 8 + read-write + + + DELAY_NUM_O_VT0_PD_SITE1_UNIT1 + needs field desc + 23 + 8 + read-only + + + TIMING_ERR_VT0_PD_SITE1_UNIT1 + needs field desc + 31 + 1 + read-only + + + + + COMB_PD_SITE1_UNIT2_VT0_CONF1 + needs desc + 0xA0 + 0x20 + 0x00000050 + + + MONITOR_EN_VT0_PD_SITE1_UNIT2 + needs field desc + 0 + 1 + read-write + + + TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT2 + needs field desc + 1 + 1 + write-only + + + DELAY_LIMIT_VT0_PD_SITE1_UNIT2 + needs field desc + 2 + 8 + read-write + + + DELAY_NUM_O_VT0_PD_SITE1_UNIT2 + needs field desc + 23 + 8 + read-only + + + TIMING_ERR_VT0_PD_SITE1_UNIT2 + needs field desc + 31 + 1 + read-only + + + + + COMB_PD_SITE1_UNIT3_VT0_CONF1 + needs desc + 0xA4 + 0x20 + 0x00000050 + + + MONITOR_EN_VT0_PD_SITE1_UNIT3 + needs field desc + 0 + 1 + read-write + + + TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT3 + needs field desc + 1 + 1 + write-only + + + DELAY_LIMIT_VT0_PD_SITE1_UNIT3 + needs field desc + 2 + 8 + read-write + + + DELAY_NUM_O_VT0_PD_SITE1_UNIT3 + needs field desc + 23 + 8 + read-only + + + TIMING_ERR_VT0_PD_SITE1_UNIT3 + needs field desc + 31 + 1 + read-only + + + + + COMB_PD_SITE1_UNIT0_VT1_CONF1 + needs desc + 0xA8 + 0x20 + 0x00000050 + + + MONITOR_EN_VT1_PD_SITE1_UNIT0 + needs field desc + 0 + 1 + read-write + + + TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT0 + needs field desc + 1 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+ + RMT + Remote Control + RMT + 0x500D4000 + + 0x0 + 0xD0 + registers + + + RMT + 43 + + + + 4 + 0x4 + TX_CH%sDATA + The read and write data register for CHANNEL%s by apb fifo access. + 0x0 + 0x20 + + + CHDATA + Read and write data for channel %s via APB FIFO. + 0 + 32 + read-only + + + + + 4 + 0x4 + RX_CH%sDATA + The read and write data register for CHANNEL$n by apb fifo access. + 0x10 + 0x20 + + + CHDATA + Read and write data for channel 0 via APB FIFO. + 0 + 32 + read-only + + + + + 4 + 0x4 + TX_CH%sCONF0 + Channel %s configure register 0 + 0x20 + 0x20 + 0x00710200 + + + TX_START_CH0 + Set this bit to start sending data on CHANNEL%s. + 0 + 1 + write-only + + + MEM_RD_RST_CH0 + Set this bit to reset read ram address for CHANNEL%s by accessing transmitter. + 1 + 1 + write-only + + + APB_MEM_RST_CH0 + Set this bit to reset W/R ram address for CHANNEL%s by accessing apb fifo. + 2 + 1 + write-only + + + TX_CONTI_MODE_CH0 + Set this bit to restart transmission from the first data to the last data in CHANNEL%s. + 3 + 1 + read-write + + + MEM_TX_WRAP_EN_CH0 + This is the channel %s enable bit for wraparound mode: it will resume sending at the start when the data to be sent is more than its memory size. + 4 + 1 + read-write + + + IDLE_OUT_LV_CH0 + This bit configures the level of output signal in CHANNEL%s when the latter is in IDLE state. + 5 + 1 + read-write + + + IDLE_OUT_EN_CH0 + This is the output enable-control bit for CHANNEL%s in IDLE state. + 6 + 1 + read-write + + + TX_STOP_CH0 + Set this bit to stop the transmitter of CHANNEL%s sending data out. + 7 + 1 + read-write + + + DIV_CNT_CH0 + This register is used to configure the divider for clock of CHANNEL%s. + 8 + 8 + read-write + + + MEM_SIZE_CH0 + This register is used to configure the maximum size of memory allocated to CHANNEL%s. + 16 + 4 + read-write + + + CARRIER_EFF_EN_CH0 + 1: Add carrier modulation on the output signal only at the send data state for CHANNEL%s. 0: Add carrier modulation on the output signal at all state for CHANNEL%s. Only valid when RMT_CARRIER_EN_CH%s is 1. + 20 + 1 + read-write + + + CARRIER_EN_CH0 + This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out. + 21 + 1 + read-write + + + CARRIER_OUT_LV_CH0 + This bit is used to configure the position of carrier wave for CHANNEL%s.1'h0: add carrier wave on low level.1'h1: add carrier wave on high level. + 22 + 1 + read-write + + + AFIFO_RST_CH0 + Reserved + 23 + 1 + write-only + + + CONF_UPDATE_CH0 + synchronization bit for CHANNEL%s + 24 + 1 + write-only + + + + + 4 + 0x8 + RX_CH%sCONF0 + Channel %s configure register 0 + 0x30 + 0x20 + 0x317FFF02 + + + DIV_CNT_CH4 + This register is used to configure the divider for clock of CHANNEL%s. + 0 + 8 + read-write + + + IDLE_THRES_CH4 + When no edge is detected on the input signal and continuous clock cycles is longer than this register value, received process is finished. + 8 + 15 + read-write + + + MEM_SIZE_CH4 + This register is used to configure the maximum size of memory allocated to CHANNEL%s. + 24 + 4 + read-write + + + CARRIER_EN_CH4 + This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out. + 28 + 1 + read-write + + + CARRIER_OUT_LV_CH4 + This bit is used to configure the position of carrier wave for CHANNEL%s.1'h0: add carrier wave on low level.1'h1: add carrier wave on high level. + 29 + 1 + read-write + + + + + 4 + 0x8 + RX_CH%sCONF1 + Channel %s configure register 1 + 0x34 + 0x20 + 0x000001E8 + + + RX_EN_CH4 + Set this bit to enable receiver to receive data on CHANNEL%s. + 0 + 1 + read-write + + + MEM_WR_RST_CH4 + Set this bit to reset write ram address for CHANNEL%s by accessing receiver. + 1 + 1 + write-only + + + APB_MEM_RST_CH4 + Set this bit to reset W/R ram address for CHANNEL%s by accessing apb fifo. + 2 + 1 + write-only + + + MEM_OWNER_CH4 + This register marks the ownership of CHANNEL%s's ram block.1'h1: Receiver is using the ram. 1'h0: APB bus is using the ram. + 3 + 1 + read-write + + + RX_FILTER_EN_CH4 + This is the receive filter's enable bit for CHANNEL%s. + 4 + 1 + read-write + + + RX_FILTER_THRES_CH4 + Ignores the input pulse when its width is smaller than this register value in APB clock periods (in receive mode). + 5 + 8 + read-write + + + MEM_RX_WRAP_EN_CH4 + This is the channel %s enable bit for wraparound mode: it will resume receiving at the start when the data to be received is more than its memory size. + 13 + 1 + read-write + + + AFIFO_RST_CH4 + Reserved + 14 + 1 + write-only + + + CONF_UPDATE_CH4 + synchronization bit for CHANNEL%s + 15 + 1 + write-only + + + + + 4 + 0x4 + TX_CH%sSTATUS + Channel %s status register + 0x50 + 0x20 + + + MEM_RADDR_EX_CH0 + This register records the memory address offset when transmitter of CHANNEL%s is using the RAM. + 0 + 10 + read-only + + + APB_MEM_WADDR_CH0 + This register records the memory address offset when writes RAM over APB bus. + 11 + 10 + read-only + + + STATE_CH0 + This register records the FSM status of CHANNEL%s. + 22 + 3 + read-only + + + MEM_EMPTY_CH0 + This status bit will be set when the data to be set is more than memory size and the wraparound mode is disabled. + 25 + 1 + read-only + + + APB_MEM_WR_ERR_CH0 + This status bit will be set if the offset address out of memory size when writes via APB bus. + 26 + 1 + read-only + + + + + 4 + 0x4 + RX_CH%sSTATUS + Channel %s status register + 0x60 + 0x20 + 0x000600C0 + + + MEM_WADDR_EX_CH4 + This register records the memory address offset when receiver of CHANNEL%s is using the RAM. + 0 + 10 + read-only + + + APB_MEM_RADDR_CH4 + This register records the memory address offset when reads RAM over APB bus. + 11 + 10 + read-only + + + STATE_CH4 + This register records the FSM status of CHANNEL%s. + 22 + 3 + read-only + + + MEM_OWNER_ERR_CH4 + This status bit will be set when the ownership of memory block is wrong. + 25 + 1 + read-only + + + MEM_FULL_CH4 + This status bit will be set if the receiver receives more data than the memory size. + 26 + 1 + read-only + + + APB_MEM_RD_ERR_CH4 + This status bit will be set if the offset address out of memory size when reads via APB bus. + 27 + 1 + read-only + + + + + INT_RAW + Raw interrupt status + 0x70 + 0x20 + + + CH0_TX_END_INT_RAW + The interrupt raw bit for CHANNEL0. Triggered when transmission done. + 0 + 1 + read-write + + + CH1_TX_END_INT_RAW + The interrupt raw bit for CHANNEL1. Triggered when transmission done. + 1 + 1 + read-write + + + CH2_TX_END_INT_RAW + The interrupt raw bit for CHANNEL2. Triggered when transmission done. + 2 + 1 + read-write + + + CH3_TX_END_INT_RAW + The interrupt raw bit for CHANNEL3. Triggered when transmission done. + 3 + 1 + read-write + + + TX_CH0_ERR_INT_RAW + The interrupt raw bit for CHANNEL0. Triggered when error occurs. + 4 + 1 + read-write + + + TX_CH1_ERR_INT_RAW + The interrupt raw bit for CHANNEL1. Triggered when error occurs. + 5 + 1 + read-write + + + TX_CH2_ERR_INT_RAW + The interrupt raw bit for CHANNEL2. Triggered when error occurs. + 6 + 1 + read-write + + + TX_CH3_ERR_INT_RAW + The interrupt raw bit for CHANNEL3. Triggered when error occurs. + 7 + 1 + read-write + + + CH0_TX_THR_EVENT_INT_RAW + The interrupt raw bit for CHANNEL0. Triggered when transmitter sent more data than configured value. + 8 + 1 + read-write + + + CH1_TX_THR_EVENT_INT_RAW + The interrupt raw bit for CHANNEL1. Triggered when transmitter sent more data than configured value. + 9 + 1 + read-write + + + CH2_TX_THR_EVENT_INT_RAW + The interrupt raw bit for CHANNEL2. Triggered when transmitter sent more data than configured value. + 10 + 1 + read-write + + + CH3_TX_THR_EVENT_INT_RAW + The interrupt raw bit for CHANNEL3. Triggered when transmitter sent more data than configured value. + 11 + 1 + read-write + + + CH0_TX_LOOP_INT_RAW + The interrupt raw bit for CHANNEL0. Triggered when the loop count reaches the configured threshold value. + 12 + 1 + read-write + + + CH1_TX_LOOP_INT_RAW + The interrupt raw bit for CHANNEL1. Triggered when the loop count reaches the configured threshold value. + 13 + 1 + read-write + + + CH2_TX_LOOP_INT_RAW + The interrupt raw bit for CHANNEL2. Triggered when the loop count reaches the configured threshold value. + 14 + 1 + read-write + + + CH3_TX_LOOP_INT_RAW + The interrupt raw bit for CHANNEL3. Triggered when the loop count reaches the configured threshold value. + 15 + 1 + read-write + + + CH4_RX_END_INT_RAW + The interrupt raw bit for CHANNEL4. Triggered when reception done. + 16 + 1 + read-write + + + CH5_RX_END_INT_RAW + The interrupt raw bit for CHANNEL5. Triggered when reception done. + 17 + 1 + read-write + + + CH6_RX_END_INT_RAW + The interrupt raw bit for CHANNEL6. Triggered when reception done. + 18 + 1 + read-write + + + CH7_RX_END_INT_RAW + The interrupt raw bit for CHANNEL7. Triggered when reception done. + 19 + 1 + read-write + + + RX_CH4_ERR_INT_RAW + The interrupt raw bit for CHANNEL4. Triggered when error occurs. + 20 + 1 + read-write + + + RX_CH5_ERR_INT_RAW + The interrupt raw bit for CHANNEL5. Triggered when error occurs. + 21 + 1 + read-write + + + RX_CH6_ERR_INT_RAW + The interrupt raw bit for CHANNEL6. Triggered when error occurs. + 22 + 1 + read-write + + + RX_CH7_ERR_INT_RAW + The interrupt raw bit for CHANNEL7. Triggered when error occurs. + 23 + 1 + read-write + + + CH4_RX_THR_EVENT_INT_RAW + The interrupt raw bit for CHANNEL4. Triggered when receiver receive more data than configured value. + 24 + 1 + read-write + + + CH5_RX_THR_EVENT_INT_RAW + The interrupt raw bit for CHANNEL5. Triggered when receiver receive more data than configured value. + 25 + 1 + read-write + + + CH6_RX_THR_EVENT_INT_RAW + The interrupt raw bit for CHANNEL6. Triggered when receiver receive more data than configured value. + 26 + 1 + read-write + + + CH7_RX_THR_EVENT_INT_RAW + The interrupt raw bit for CHANNEL7. Triggered when receiver receive more data than configured value. + 27 + 1 + read-write + + + TX_CH3_DMA_ACCESS_FAIL_INT_RAW + The interrupt raw bit for CHANNEL3. Triggered when dma accessing CHANNEL3 fails. + 28 + 1 + read-write + + + RX_CH7_DMA_ACCESS_FAIL_INT_RAW + The interrupt raw bit for CHANNEL7. Triggered when dma accessing CHANNEL7 fails. + 29 + 1 + read-write + + + + + INT_ST + Masked interrupt status + 0x74 + 0x20 + + + CH0_TX_END_INT_ST + The masked interrupt status bit for CH0_TX_END_INT. + 0 + 1 + read-only + + + CH1_TX_END_INT_ST + The masked interrupt status bit for CH1_TX_END_INT. + 1 + 1 + read-only + + + CH2_TX_END_INT_ST + The masked interrupt status bit for CH2_TX_END_INT. + 2 + 1 + read-only + + + CH3_TX_END_INT_ST + The masked interrupt status bit for CH3_TX_END_INT. + 3 + 1 + read-only + + + TX_CH0_ERR_INT_ST + The masked interrupt status bit for CH0_ERR_INT. + 4 + 1 + read-only + + + TX_CH1_ERR_INT_ST + The masked interrupt status bit for CH1_ERR_INT. + 5 + 1 + read-only + + + TX_CH2_ERR_INT_ST + The masked interrupt status bit for CH2_ERR_INT. + 6 + 1 + read-only + + + TX_CH3_ERR_INT_ST + The masked interrupt status bit for CH3_ERR_INT. + 7 + 1 + read-only + + + CH0_TX_THR_EVENT_INT_ST + The masked interrupt status bit for CH0_TX_THR_EVENT_INT. + 8 + 1 + read-only + + + CH1_TX_THR_EVENT_INT_ST + The masked interrupt status bit for CH1_TX_THR_EVENT_INT. + 9 + 1 + read-only + + + CH2_TX_THR_EVENT_INT_ST + The masked interrupt status bit for CH2_TX_THR_EVENT_INT. + 10 + 1 + read-only + + + CH3_TX_THR_EVENT_INT_ST + The masked interrupt status bit for CH3_TX_THR_EVENT_INT. + 11 + 1 + read-only + + + CH0_TX_LOOP_INT_ST + The masked interrupt status bit for CH0_TX_LOOP_INT. + 12 + 1 + read-only + + + CH1_TX_LOOP_INT_ST + The masked interrupt status bit for CH1_TX_LOOP_INT. + 13 + 1 + read-only + + + CH2_TX_LOOP_INT_ST + The masked interrupt status bit for CH2_TX_LOOP_INT. + 14 + 1 + read-only + + + CH3_TX_LOOP_INT_ST + The masked interrupt status bit for CH3_TX_LOOP_INT. + 15 + 1 + read-only + + + CH4_RX_END_INT_ST + The masked interrupt status bit for CH4_RX_END_INT. + 16 + 1 + read-only + + + CH5_RX_END_INT_ST + The masked interrupt status bit for CH5_RX_END_INT. + 17 + 1 + read-only + + + CH6_RX_END_INT_ST + The masked interrupt status bit for CH6_RX_END_INT. + 18 + 1 + read-only + + + CH7_RX_END_INT_ST + The masked interrupt status bit for CH7_RX_END_INT. + 19 + 1 + read-only + + + RX_CH4_ERR_INT_ST + The masked interrupt status bit for CH4_ERR_INT. + 20 + 1 + read-only + + + RX_CH5_ERR_INT_ST + The masked interrupt status bit for CH5_ERR_INT. + 21 + 1 + read-only + + + RX_CH6_ERR_INT_ST + The masked interrupt status bit for CH6_ERR_INT. + 22 + 1 + read-only + + + RX_CH7_ERR_INT_ST + The masked interrupt status bit for CH7_ERR_INT. + 23 + 1 + read-only + + + CH4_RX_THR_EVENT_INT_ST + The masked interrupt status bit for CH4_RX_THR_EVENT_INT. + 24 + 1 + read-only + + + CH5_RX_THR_EVENT_INT_ST + The masked interrupt status bit for CH5_RX_THR_EVENT_INT. + 25 + 1 + read-only + + + CH6_RX_THR_EVENT_INT_ST + The masked interrupt status bit for CH6_RX_THR_EVENT_INT. + 26 + 1 + read-only + + + CH7_RX_THR_EVENT_INT_ST + The masked interrupt status bit for CH7_RX_THR_EVENT_INT. + 27 + 1 + read-only + + + TX_CH3_DMA_ACCESS_FAIL_INT_ST + The masked interrupt status bit for CH3_DMA_ACCESS_FAIL_INT. + 28 + 1 + read-only + + + RX_CH7_DMA_ACCESS_FAIL_INT_ST + The masked interrupt status bit for CH7_DMA_ACCESS_FAIL_INT. + 29 + 1 + read-only + + + + + INT_ENA + Interrupt enable bits + 0x78 + 0x20 + + + CH0_TX_END_INT_ENA + The interrupt enable bit for CH0_TX_END_INT. + 0 + 1 + read-write + + + CH1_TX_END_INT_ENA + The interrupt enable bit for CH1_TX_END_INT. + 1 + 1 + read-write + + + CH2_TX_END_INT_ENA + The interrupt enable bit for CH2_TX_END_INT. + 2 + 1 + read-write + + + CH3_TX_END_INT_ENA + The interrupt enable bit for CH3_TX_END_INT. + 3 + 1 + read-write + + + TX_CH0_ERR_INT_ENA + The interrupt enable bit for CH0_ERR_INT. + 4 + 1 + read-write + + + TX_CH1_ERR_INT_ENA + The interrupt enable bit for CH1_ERR_INT. + 5 + 1 + read-write + + + TX_CH2_ERR_INT_ENA + The interrupt enable bit for CH2_ERR_INT. + 6 + 1 + read-write + + + TX_CH3_ERR_INT_ENA + The interrupt enable bit for CH3_ERR_INT. + 7 + 1 + read-write + + + CH0_TX_THR_EVENT_INT_ENA + The interrupt enable bit for CH0_TX_THR_EVENT_INT. + 8 + 1 + read-write + + + CH1_TX_THR_EVENT_INT_ENA + The interrupt enable bit for CH1_TX_THR_EVENT_INT. + 9 + 1 + read-write + + + CH2_TX_THR_EVENT_INT_ENA + The interrupt enable bit for CH2_TX_THR_EVENT_INT. + 10 + 1 + read-write + + + CH3_TX_THR_EVENT_INT_ENA + The interrupt enable bit for CH3_TX_THR_EVENT_INT. + 11 + 1 + read-write + + + CH0_TX_LOOP_INT_ENA + The interrupt enable bit for CH0_TX_LOOP_INT. + 12 + 1 + read-write + + + CH1_TX_LOOP_INT_ENA + The interrupt enable bit for CH1_TX_LOOP_INT. + 13 + 1 + read-write + + + CH2_TX_LOOP_INT_ENA + The interrupt enable bit for CH2_TX_LOOP_INT. + 14 + 1 + read-write + + + CH3_TX_LOOP_INT_ENA + The interrupt enable bit for CH3_TX_LOOP_INT. + 15 + 1 + read-write + + + CH4_RX_END_INT_ENA + The interrupt enable bit for CH4_RX_END_INT. + 16 + 1 + read-write + + + CH5_RX_END_INT_ENA + The interrupt enable bit for CH5_RX_END_INT. + 17 + 1 + read-write + + + CH6_RX_END_INT_ENA + The interrupt enable bit for CH6_RX_END_INT. + 18 + 1 + read-write + + + CH7_RX_END_INT_ENA + The interrupt enable bit for CH7_RX_END_INT. + 19 + 1 + read-write + + + CH4_ERR_INT_ENA + The interrupt enable bit for CH4_ERR_INT. + 20 + 1 + read-write + + + CH5_ERR_INT_ENA + The interrupt enable bit for CH5_ERR_INT. + 21 + 1 + read-write + + + CH6_ERR_INT_ENA + The interrupt enable bit for CH6_ERR_INT. + 22 + 1 + read-write + + + CH7_ERR_INT_ENA + The interrupt enable bit for CH7_ERR_INT. + 23 + 1 + read-write + + + CH4_RX_THR_EVENT_INT_ENA + The interrupt enable bit for CH4_RX_THR_EVENT_INT. + 24 + 1 + read-write + + + CH5_RX_THR_EVENT_INT_ENA + The interrupt enable bit for CH5_RX_THR_EVENT_INT. + 25 + 1 + read-write + + + CH6_RX_THR_EVENT_INT_ENA + The interrupt enable bit for CH6_RX_THR_EVENT_INT. + 26 + 1 + read-write + + + CH7_RX_THR_EVENT_INT_ENA + The interrupt enable bit for CH7_RX_THR_EVENT_INT. + 27 + 1 + read-write + + + TX_CH3_DMA_ACCESS_FAIL_INT_ENA + The interrupt enable bit for CH3_DMA_ACCESS_FAIL_INT. + 28 + 1 + read-write + + + RX_CH7_DMA_ACCESS_FAIL_INT_ENA + The interrupt enable bit for CH7_DMA_ACCESS_FAIL_INT. + 29 + 1 + read-write + + + + + INT_CLR + Interrupt clear bits + 0x7C + 0x20 + + + CH0_TX_END_INT_CLR + Set this bit to clear theCH0_TX_END_INT interrupt. + 0 + 1 + write-only + + + CH1_TX_END_INT_CLR + Set this bit to clear theCH1_TX_END_INT interrupt. + 1 + 1 + write-only + + + CH2_TX_END_INT_CLR + Set this bit to clear theCH2_TX_END_INT interrupt. + 2 + 1 + write-only + + + CH3_TX_END_INT_CLR + Set this bit to clear theCH3_TX_END_INT interrupt. + 3 + 1 + write-only + + + TX_CH0_ERR_INT_CLR + Set this bit to clear theCH0_ERR_INT interrupt. + 4 + 1 + write-only + + + TX_CH1_ERR_INT_CLR + Set this bit to clear theCH1_ERR_INT interrupt. + 5 + 1 + write-only + + + TX_CH2_ERR_INT_CLR + Set this bit to clear theCH2_ERR_INT interrupt. + 6 + 1 + write-only + + + TX_CH3_ERR_INT_CLR + Set this bit to clear theCH3_ERR_INT interrupt. + 7 + 1 + write-only + + + CH0_TX_THR_EVENT_INT_CLR + Set this bit to clear theCH0_TX_THR_EVENT_INT interrupt. + 8 + 1 + write-only + + + CH1_TX_THR_EVENT_INT_CLR + Set this bit to clear theCH1_TX_THR_EVENT_INT interrupt. + 9 + 1 + write-only + + + CH2_TX_THR_EVENT_INT_CLR + Set this bit to clear theCH2_TX_THR_EVENT_INT interrupt. + 10 + 1 + write-only + + + CH3_TX_THR_EVENT_INT_CLR + Set this bit to clear theCH3_TX_THR_EVENT_INT interrupt. + 11 + 1 + write-only + + + CH0_TX_LOOP_INT_CLR + Set this bit to clear theCH0_TX_LOOP_INT interrupt. + 12 + 1 + write-only + + + CH1_TX_LOOP_INT_CLR + Set this bit to clear theCH1_TX_LOOP_INT interrupt. + 13 + 1 + write-only + + + CH2_TX_LOOP_INT_CLR + Set this bit to clear theCH2_TX_LOOP_INT interrupt. + 14 + 1 + write-only + + + CH3_TX_LOOP_INT_CLR + Set this bit to clear theCH3_TX_LOOP_INT interrupt. + 15 + 1 + write-only + + + CH4_RX_END_INT_CLR + Set this bit to clear theCH4_RX_END_INT interrupt. + 16 + 1 + write-only + + + CH5_RX_END_INT_CLR + Set this bit to clear theCH5_RX_END_INT interrupt. + 17 + 1 + write-only + + + CH6_RX_END_INT_CLR + Set this bit to clear theCH6_RX_END_INT interrupt. + 18 + 1 + write-only + + + CH7_RX_END_INT_CLR + Set this bit to clear theCH7_RX_END_INT interrupt. + 19 + 1 + write-only + + + RX_CH4_ERR_INT_CLR + Set this bit to clear theCH4_ERR_INT interrupt. + 20 + 1 + write-only + + + RX_CH5_ERR_INT_CLR + Set this bit to clear theCH5_ERR_INT interrupt. + 21 + 1 + write-only + + + RX_CH6_ERR_INT_CLR + Set this bit to clear theCH6_ERR_INT interrupt. + 22 + 1 + write-only + + + RX_CH7_ERR_INT_CLR + Set this bit to clear theCH7_ERR_INT interrupt. + 23 + 1 + write-only + + + CH4_RX_THR_EVENT_INT_CLR + Set this bit to clear theCH4_RX_THR_EVENT_INT interrupt. + 24 + 1 + write-only + + + CH5_RX_THR_EVENT_INT_CLR + Set this bit to clear theCH5_RX_THR_EVENT_INT interrupt. + 25 + 1 + write-only + + + CH6_RX_THR_EVENT_INT_CLR + Set this bit to clear theCH6_RX_THR_EVENT_INT interrupt. + 26 + 1 + write-only + + + CH7_RX_THR_EVENT_INT_CLR + Set this bit to clear theCH7_RX_THR_EVENT_INT interrupt. + 27 + 1 + write-only + + + TX_CH3_DMA_ACCESS_FAIL_INT_CLR + Set this bit to clear the CH3_DMA_ACCESS_FAIL_INT interrupt. + 28 + 1 + write-only + + + RX_CH7_DMA_ACCESS_FAIL_INT_CLR + Set this bit to clear the CH7_DMA_ACCESS_FAIL_INT interrupt. + 29 + 1 + write-only + + + + + 4 + 0x4 + CH%sCARRIER_DUTY + Channel %s duty cycle configuration register + 0x80 + 0x20 + 0x00400040 + + + CARRIER_LOW_CH + This register is used to configure carrier wave 's low level clock period for CHANNEL%s. + 0 + 16 + read-write + + + CARRIER_HIGH_CH + This register is used to configure carrier wave 's high level clock period for CHANNEL%s. + 16 + 16 + read-write + + + + + 4 + 0x4 + CH%s_RX_CARRIER_RM + Channel %s carrier remove register + 0x90 + 0x20 + + + CARRIER_LOW_THRES_CH + The low level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_LOW_THRES_CH%s + 1) for channel %s. + 0 + 16 + read-write + + + CARRIER_HIGH_THRES_CH + The high level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_HIGH_THRES_CH%s + 1) for channel %s. + 16 + 16 + read-write + + + + + 4 + 0x4 + CH%s_TX_LIM + Channel %s Tx event configuration register + 0xA0 + 0x20 + 0x00000080 + + + TX_LIM_CH + This register is used to configure the maximum entries that CHANNEL%s can send out. + 0 + 9 + read-write + + + TX_LOOP_NUM_CH + This register is used to configure the maximum loop count when tx_conti_mode is valid. + 9 + 10 + read-write + + + TX_LOOP_CNT_EN_CH + This register is the enabled bit for loop count. + 19 + 1 + read-write + + + LOOP_COUNT_RESET_CH + This register is used to reset the loop count when tx_conti_mode is valid. + 20 + 1 + write-only + + + LOOP_STOP_EN_CH + This bit is used to enable the loop send stop function after the loop counter counts to loop number for CHANNEL%s. + 21 + 1 + read-write + + + + + 4 + 0x4 + CH%s_RX_LIM + Channel %s Rx event configuration register + 0xB0 + 0x20 + 0x00000080 + + + RX_LIM_CH4 + This register is used to configure the maximum entries that CHANNEL%s can receive. + 0 + 9 + read-write + + + + + SYS_CONF + RMT apb configuration register + 0xC0 + 0x20 + 0x05000010 + + + APB_FIFO_MASK + 1'h1: access memory directly. 1'h0: access memory by FIFO. + 0 + 1 + read-write + + + MEM_CLK_FORCE_ON + Set this bit to enable the clock for RMT memory. + 1 + 1 + read-write + + + MEM_FORCE_PD + Set this bit to power down RMT memory. + 2 + 1 + read-write + + + MEM_FORCE_PU + 1: Disable RMT memory light sleep power down function. 0: Power down RMT memory when RMT is in light sleep mode. + 3 + 1 + read-write + + + SCLK_DIV_NUM + the integral part of the fractional divisor + 4 + 8 + read-write + + + SCLK_DIV_A + the numerator of the fractional part of the fractional divisor + 12 + 6 + read-write + + + SCLK_DIV_B + the denominator of the fractional part of the fractional divisor + 18 + 6 + read-write + + + SCLK_SEL + choose the clock source of rmt_sclk. 1:CLK_80Mhz.2:CLK_8MHz.3:XTAL + 24 + 2 + read-write + + + SCLK_ACTIVE + rmt_sclk switch + 26 + 1 + read-write + + + CLK_EN + RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0: Power down the drive clock of registers + 31 + 1 + read-write + + + + + TX_SIM + RMT TX synchronous register + 0xC4 + 0x20 + + + CH0 + Set this bit to enable CHANNEL0 to start sending data synchronously with other enabled channels. + 0 + 1 + read-write + + + CH1 + Set this bit to enable CHANNEL1 to start sending data synchronously with other enabled channels. + 1 + 1 + read-write + + + CH2 + Set this bit to enable CHANNEL2 to start sending data synchronously with other enabled channels. + 2 + 1 + read-write + + + CH3 + Set this bit to enable CHANNEL3 to start sending data synchronously with other enabled channels. + 3 + 1 + read-write + + + EN + This register is used to enable multiple of channels to start sending data synchronously. + 4 + 1 + read-write + + + + + REF_CNT_RST + RMT clock divider reset register + 0xC8 + 0x20 + + + TX_REF_CNT_RST_CH0 + This register is used to reset the clock divider of CHANNEL0. + 0 + 1 + write-only + + + TX_REF_CNT_RST_CH1 + This register is used to reset the clock divider of CHANNEL1. + 1 + 1 + write-only + + + TX_REF_CNT_RST_CH2 + This register is used to reset the clock divider of CHANNEL2. + 2 + 1 + write-only + + + TX_REF_CNT_RST_CH3 + This register is used to reset the clock divider of CHANNEL3. + 3 + 1 + write-only + + + RX_REF_CNT_RST_CH4 + This register is used to reset the clock divider of CHANNEL4. + 4 + 1 + write-only + + + RX_REF_CNT_RST_CH5 + This register is used to reset the clock divider of CHANNEL5. + 5 + 1 + write-only + + + RX_REF_CNT_RST_CH6 + This register is used to reset the clock divider of CHANNEL6. + 6 + 1 + write-only + + + RX_REF_CNT_RST_CH7 + This register is used to reset the clock divider of CHANNEL7. + 7 + 1 + write-only + + + + + DATE + RMT version register + 0xCC + 0x20 + 0x02201111 + + + DATE + This is the version register. + 0 + 28 + read-write + + + + + + + RSA + RSA (Rivest Shamir Adleman) Accelerator + RSA + 0x50092000 + + 0x0 + 0x74 + registers + + + RSA + 68 + + + + 4 + 0x4 + M_MEM[%s] + Represents M + 0x0 + 0x20 + + + 4 + 0x4 + Z_MEM[%s] + Represents Z + 0x200 + 0x20 + + + 4 + 0x4 + Y_MEM[%s] + Represents Y + 0x400 + 0x20 + + + 4 + 0x4 + X_MEM[%s] + Represents X + 0x600 + 0x20 + + + M_PRIME + Represents M’ + 0x800 + 0x20 + + + M_PRIME + Represents M’ + 0 + 32 + read-write + + + + + MODE + Configures RSA length + 0x804 + 0x20 + + + MODE + Configures the RSA length. + 0 + 7 + read-write + + + + + QUERY_CLEAN + RSA clean register + 0x808 + 0x20 + + + QUERY_CLEAN + Represents whether or not the RSA memory completes initialization. + +0: Not complete + +1: Completed + 0 + 1 + read-only + + + + + SET_START_MODEXP + Starts modular exponentiation + 0x80C + 0x20 + + + SET_START_MODEXP + Configure whether or not to start the modular exponentiation. + +0: No effect + +1: Start + 0 + 1 + write-only + + + + + SET_START_MODMULT + Starts modular multiplication + 0x810 + 0x20 + + + SET_START_MODMULT + Configure whether or not to start the modular multiplication. + +0: No effect + +1: Start + 0 + 1 + write-only + + + + + SET_START_MULT + Starts multiplication + 0x814 + 0x20 + + + SET_START_MULT + Configure whether or not to start the multiplication. + +0: No effect + +1: Start + 0 + 1 + write-only + + + + + QUERY_IDLE + Represents the RSA status + 0x818 + 0x20 + + + QUERY_IDLE + Represents the RSA status. + +0: Busy + +1: Idle + 0 + 1 + read-only + + + + + INT_CLR + Clears RSA interrupt + 0x81C + 0x20 + + + CLEAR_INTERRUPT + Write 1 to clear the RSA interrupt. + 0 + 1 + write-only + + + + + CONSTANT_TIME + Configures the constant_time option + 0x820 + 0x20 + 0x00000001 + + + CONSTANT_TIME + Configures the constant_time option. + +0: Acceleration + +1: No acceleration (default) + 0 + 1 + read-write + + + + + SEARCH_ENABLE + Configures the search option + 0x824 + 0x20 + + + SEARCH_ENABLE + Configure the search option. + +0: No acceleration (default) + +1: Acceleration + +This option should be used together with RSA_SEARCH_POS. + 0 + 1 + read-write + + + + + SEARCH_POS + Configures the search position + 0x828 + 0x20 + + + SEARCH_POS + Configures the starting address to start search. This field should be used together with RSA_SEARCH_ENABLE. The field is only valid when RSA_SEARCH_ENABLE is high. + 0 + 12 + read-write + + + + + INT_ENA + Enables the RSA interrupt + 0x82C + 0x20 + + + INT_ENA + Write 1 to enable the RSA interrupt. + 0 + 1 + read-write + + + + + DATE + Version control register + 0x830 + 0x20 + 0x20200618 + + + DATE + Version control register. + 0 + 30 + read-write + + + + + + + LP_ADC + Low-power Analog to Digital Converter + RTCADC + 0x50127000 + + 0x0 + 0x80 + registers + + + LP_ADC + 9 + + + + READER1_CTRL + Control the read operation of ADC1. + 0x0 + 0x20 + 0x20040002 + + + SAR1_CLK_DIV + Clock divider. + 0 + 8 + read-write + + + SAR1_CLK_GATED + N/A + 18 + 1 + read-write + + + SAR1_SAMPLE_NUM + N/A + 19 + 8 + read-write + + + SAR1_DATA_INV + Invert SAR ADC1 data. + 28 + 1 + read-write + + + SAR1_INT_EN + Enable saradc1 to send out interrupt. + 29 + 1 + read-write + + + SAR1_EN_PAD_FORCE_ENABLE + Force enable adc en_pad to analog circuit 2'b11: force enable . + 30 + 2 + read-write + + + + + READER1_STATUS + N/A + 0x4 + 0x20 + 0x20000000 + + + SAR1_READER_STATUS + N/A + 0 + 32 + read-only + + + + + MEAS1_CTRL1 + N/A + 0x8 + 0x20 + + + FORCE_XPD_AMP + N/A + 24 + 2 + read-write + + + AMP_RST_FB_FORCE + N/A + 26 + 2 + read-write + + + AMP_SHORT_REF_FORCE + N/A + 28 + 2 + read-write + + + AMP_SHORT_REF_GND_FORCE + N/A + 30 + 2 + read-write + + + + + MEAS1_CTRL2 + ADC1 configuration registers. + 0xC + 0x20 + + + MEAS1_DATA_SAR + SAR ADC1 data. + 0 + 16 + read-only + + + MEAS1_DONE_SAR + SAR ADC1 conversion done indication. + 16 + 1 + read-only + + + MEAS1_START_SAR + SAR ADC1 controller (in RTC) starts conversion. + 17 + 1 + read-write + + + MEAS1_START_FORCE + 1: SAR ADC1 controller (in RTC) is started by SW. + 18 + 1 + read-write + + + SAR1_EN_PAD + SAR ADC1 pad enable bitmap. + 19 + 12 + read-write + + + SAR1_EN_PAD_FORCE + 1: SAR ADC1 pad enable bitmap is controlled by SW. + 31 + 1 + read-write + + + + + MEAS1_MUX + SAR ADC1 MUX register. + 0x10 + 0x20 + + + SAR1_DIG_FORCE + 1: SAR ADC1 controlled by DIG ADC1 CTRL. + 31 + 1 + read-write + + + + + ATTEN1 + ADC1 attenuation registers. + 0x14 + 0x20 + 0xFFFFFFFF + + + SAR1_ATTEN + 2-bit attenuation for each pad. + 0 + 32 + read-write + + + + + AMP_CTRL1 + N/A + 0x18 + 0x20 + 0x000A000A + + + SAR_AMP_WAIT1 + N/A + 0 + 16 + read-write + + + SAR_AMP_WAIT2 + N/A + 16 + 16 + read-write + + + + + AMP_CTRL2 + N/A + 0x1C + 0x20 + 0x000A0000 + + + SAR1_DAC_XPD_FSM_IDLE + N/A + 0 + 1 + read-write + + + XPD_SAR_AMP_FSM_IDLE + N/A + 1 + 1 + read-write + + + AMP_RST_FB_FSM_IDLE + N/A + 2 + 1 + read-write + + + AMP_SHORT_REF_FSM_IDLE + N/A + 3 + 1 + read-write + + + AMP_SHORT_REF_GND_FSM_IDLE + N/A + 4 + 1 + read-write + + + XPD_SAR_FSM_IDLE + N/A + 5 + 1 + read-write + + + SAR_RSTB_FSM_IDLE + N/A + 6 + 1 + read-write + + + SAR_AMP_WAIT3 + N/A + 16 + 16 + read-write + + + + + AMP_CTRL3 + N/A + 0x20 + 0x20 + 0x007338F3 + + + SAR1_DAC_XPD_FSM + N/A + 0 + 4 + read-write + + + XPD_SAR_AMP_FSM + N/A + 4 + 4 + read-write + + + AMP_RST_FB_FSM + N/A + 8 + 4 + read-write + + + AMP_SHORT_REF_FSM + N/A + 12 + 4 + read-write + + + AMP_SHORT_REF_GND_FSM + N/A + 16 + 4 + read-write + + + XPD_SAR_FSM + N/A + 20 + 4 + read-write + + + SAR_RSTB_FSM + N/A + 24 + 4 + read-write + + + + + READER2_CTRL + Control the read operation of ADC2. + 0x24 + 0x20 + 0x40050002 + + + SAR2_CLK_DIV + Clock divider. + 0 + 8 + read-write + + + SAR2_WAIT_ARB_CYCLE + Wait arbit stable after sar_done. + 16 + 2 + read-write + + + SAR2_CLK_GATED + N/A + 18 + 1 + read-write + + + SAR2_SAMPLE_NUM + N/A + 19 + 8 + read-write + + + SAR2_EN_PAD_FORCE_ENABLE + Force enable adc en_pad to analog circuit 2'b11: force enable . + 27 + 2 + read-write + + + SAR2_DATA_INV + Invert SAR ADC2 data. + 29 + 1 + read-write + + + SAR2_INT_EN + Enable saradc2 to send out interrupt. + 30 + 1 + read-write + + + + + READER2_STATUS + N/A + 0x28 + 0x20 + + + SAR2_READER_STATUS + N/A + 0 + 32 + read-only + + + + + MEAS2_CTRL1 + ADC2 configuration registers. + 0x2C + 0x20 + 0x07020200 + + + SAR2_CNTL_STATE + saradc2_cntl_fsm. + 0 + 3 + read-only + + + SAR2_PWDET_CAL_EN + RTC control pwdet enable. + 3 + 1 + read-write + + + SAR2_PKDET_CAL_EN + RTC control pkdet enable. + 4 + 1 + read-write + + + SAR2_EN_TEST + SAR2_EN_TEST. + 5 + 1 + read-write + + + SAR2_RSTB_FORCE + N/A + 6 + 2 + read-write + + + SAR2_STANDBY_WAIT + N/A + 8 + 8 + read-write + + + SAR2_RSTB_WAIT + N/A + 16 + 8 + read-write + + + SAR2_XPD_WAIT + N/A + 24 + 8 + read-write + + + + + MEAS2_CTRL2 + ADC2 configuration registers. + 0x30 + 0x20 + + + MEAS2_DATA_SAR + SAR ADC2 data. + 0 + 16 + read-only + + + MEAS2_DONE_SAR + SAR ADC2 conversion done indication. + 16 + 1 + read-only + + + MEAS2_START_SAR + SAR ADC2 controller (in RTC) starts conversion. + 17 + 1 + read-write + + + MEAS2_START_FORCE + 1: SAR ADC2 controller (in RTC) is started by SW. + 18 + 1 + read-write + + + SAR2_EN_PAD + SAR ADC2 pad enable bitmap. + 19 + 12 + read-write + + + SAR2_EN_PAD_FORCE + 1: SAR ADC2 pad enable bitmap is controlled by SW. + 31 + 1 + read-write + + + + + MEAS2_MUX + SAR ADC2 MUX register. + 0x34 + 0x20 + + + SAR2_PWDET_CCT + SAR2_PWDET_CCT. + 28 + 3 + read-write + + + SAR2_RTC_FORCE + In sleep, force to use rtc to control ADC. + 31 + 1 + read-write + + + + + ATTEN2 + ADC1 attenuation registers. + 0x38 + 0x20 + 0xFFFFFFFF + + + SAR2_ATTEN + 2-bit attenuation for each pad. + 0 + 32 + read-write + + + + + FORCE_WPD_SAR + In sleep, force to use rtc to control ADC + 0x3C + 0x20 + + + FORCE_XPD_SAR1 + 2'b11:software control, force on. 2'b10:software control, force off. 2'b0x:hardware control. + 0 + 2 + read-write + + + FORCE_XPD_SAR2 + 2'b11:software control, force on. 2'b10:software control, force off. 2'b0x:hardware control. + 2 + 2 + read-write + + + + + MEAS_STATUS + N/A + 0x40 + 0x20 + + + SARADC_MEAS_STATUS + N/A + 0 + 8 + read-only + + + + + REG_CLKEN + N/A + 0x44 + 0x20 + + + CLK_EN + N/A + 0 + 1 + read-write + + + + + COCPU_INT_RAW + Interrupt raw registers. + 0x48 + 0x20 + + + COCPU_SARADC1_INT_RAW + ADC1 Conversion is done, int raw. + 0 + 1 + read-write + + + COCPU_SARADC2_INT_RAW + ADC2 Conversion is done, int raw. + 1 + 1 + read-write + + + COCPU_SARADC1_ERROR_INT_RAW + An errro occurs from ADC1, int raw. + 2 + 1 + read-write + + + COCPU_SARADC2_ERROR_INT_RAW + An errro occurs from ADC2, int raw. + 3 + 1 + read-write + + + COCPU_SARADC1_WAKE_INT_RAW + A wakeup event is triggered from ADC1, int raw. + 4 + 1 + read-write + + + COCPU_SARADC2_WAKE_INT_RAW + A wakeup event is triggered from ADC2, int raw. + 5 + 1 + read-write + + + + + INT_ENA + Interrupt enable registers. + 0x4C + 0x20 + + + COCPU_SARADC1_INT_ENA + ADC1 Conversion is done, int enable. + 0 + 1 + read-write + + + COCPU_SARADC2_INT_ENA + ADC2 Conversion is done, int enable. + 1 + 1 + read-write + + + COCPU_SARADC1_ERROR_INT_ENA + An errro occurs from ADC1, int enable. + 2 + 1 + read-write + + + COCPU_SARADC2_ERROR_INT_ENA + An errro occurs from ADC2, int enable. + 3 + 1 + read-write + + + COCPU_SARADC1_WAKE_INT_ENA + A wakeup event is triggered from ADC1, int enable. + 4 + 1 + read-write + + + COCPU_SARADC2_WAKE_INT_ENA + A wakeup event is triggered from ADC2, int enable. + 5 + 1 + read-write + + + + + INT_ST + Interrupt status registers. + 0x50 + 0x20 + + + COCPU_SARADC1_INT_ST + ADC1 Conversion is done, int status. + 0 + 1 + read-only + + + COCPU_SARADC2_INT_ST + ADC2 Conversion is done, int status. + 1 + 1 + read-only + + + COCPU_SARADC1_ERROR_INT_ST + An errro occurs from ADC1, int status. + 2 + 1 + read-only + + + COCPU_SARADC2_ERROR_INT_ST + An errro occurs from ADC2, int status. + 3 + 1 + read-only + + + COCPU_SARADC1_WAKE_INT_ST + A wakeup event is triggered from ADC1, int status. + 4 + 1 + read-only + + + COCPU_SARADC2_WAKE_INT_ST + A wakeup event is triggered from ADC2, int status. + 5 + 1 + read-only + + + + + INT_CLR + Interrupt clear registers. + 0x54 + 0x20 + + + COCPU_SARADC1_INT_CLR + ADC1 Conversion is done, int clear. + 0 + 1 + write-only + + + COCPU_SARADC2_INT_CLR + ADC2 Conversion is done, int clear. + 1 + 1 + write-only + + + COCPU_SARADC1_ERROR_INT_CLR + An errro occurs from ADC1, int clear. + 2 + 1 + write-only + + + COCPU_SARADC2_ERROR_INT_CLR + An errro occurs from ADC2, int clear. + 3 + 1 + write-only + + + COCPU_SARADC1_WAKE_INT_CLR + A wakeup event is triggered from ADC1, int clear. + 4 + 1 + write-only + + + COCPU_SARADC2_WAKE_INT_CLR + A wakeup event is triggered from ADC2, int clear. + 5 + 1 + write-only + + + + + INT_ENA_W1TS + Interrupt enable assert registers. + 0x58 + 0x20 + + + COCPU_SARADC1_INT_ENA_W1TS + ADC1 Conversion is done, write 1 to assert int enable. + 0 + 1 + write-only + + + COCPU_SARADC2_INT_ENA_W1TS + ADC2 Conversion is done, write 1 to assert int enable. + 1 + 1 + write-only + + + COCPU_SARADC1_ERROR_INT_ENA_W1TS + An errro occurs from ADC1, write 1 to assert int enable. + 2 + 1 + write-only + + + COCPU_SARADC2_ERROR_INT_ENA_W1TS + An errro occurs from ADC2, write 1 to assert int enable. + 3 + 1 + write-only + + + COCPU_SARADC1_WAKE_INT_ENA_W1TS + A wakeup event is triggered from ADC1, write 1 to assert int enable. + 4 + 1 + write-only + + + COCPU_SARADC2_WAKE_INT_ENA_W1TS + A wakeup event is triggered from ADC2, write 1 to assert int enable. + 5 + 1 + write-only + + + + + INT_ENA_W1TC + Interrupt enable deassert registers. + 0x5C + 0x20 + + + COCPU_SARADC1_INT_ENA_W1TC + ADC1 Conversion is done, write 1 to deassert int enable. + 0 + 1 + write-only + + + COCPU_SARADC2_INT_ENA_W1TC + ADC2 Conversion is done, write 1 to deassert int enable. + 1 + 1 + write-only + + + COCPU_SARADC1_ERROR_INT_ENA_W1TC + An errro occurs from ADC1, write 1 to deassert int enable. + 2 + 1 + write-only + + + COCPU_SARADC2_ERROR_INT_ENA_W1TC + An errro occurs from ADC2, write 1 to deassert int enable. + 3 + 1 + write-only + + + COCPU_SARADC1_WAKE_INT_ENA_W1TC + A wakeup event is triggered from ADC1, write 1 to deassert int enable. + 4 + 1 + write-only + + + COCPU_SARADC2_WAKE_INT_ENA_W1TC + A wakeup event is triggered from ADC2, write 1 to deassert int enable. + 5 + 1 + write-only + + + + + WAKEUP1 + ADC1 wakeup configuration registers. + 0x60 + 0x20 + 0x03FFC000 + + + SAR1_WAKEUP_TH_LOW + Lower threshold. + 0 + 12 + read-write + + + SAR1_WAKEUP_TH_HIGH + Upper threshold. + 14 + 12 + read-write + + + SAR1_WAKEUP_OVER_UPPER_TH + Indicates that this wakeup event arose from exceeding upper threshold. + 29 + 1 + read-only + + + SAR1_WAKEUP_EN + Wakeup function enable. + 30 + 1 + read-write + + + SAR1_WAKEUP_MODE + 0:absolute value comparison mode. 1: relative value comparison mode. + 31 + 1 + read-write + + + + + WAKEUP2 + ADC2 wakeup configuration registers. + 0x64 + 0x20 + 0x03FFC000 + + + SAR2_WAKEUP_TH_LOW + Lower threshold. + 0 + 12 + read-write + + + SAR2_WAKEUP_TH_HIGH + Upper threshold. + 14 + 12 + read-write + + + SAR2_WAKEUP_OVER_UPPER_TH + Indicates that this wakeup event arose from exceeding upper threshold. + 29 + 1 + read-only + + + SAR2_WAKEUP_EN + Wakeup function enable. + 30 + 1 + read-write + + + SAR2_WAKEUP_MODE + 0:absolute value comparison mode. 1: relative value comparison mode. + 31 + 1 + read-write + + + + + WAKEUP_SEL + Wakeup source select register. + 0x68 + 0x20 + + + SAR_WAKEUP_SEL + 0: ADC1. 1: ADC2. + 0 + 1 + read-write + + + + + SAR1_HW_WAKEUP + Hardware automatic sampling registers for wakeup function. + 0x6C + 0x20 + 0x000000C8 + + + ADC1_HW_READ_EN_I + Enable hardware automatic sampling. + 0 + 1 + read-write + + + ADC1_HW_READ_RATE_I + Hardware automatic sampling rate. + 1 + 16 + read-write + + + + + SAR2_HW_WAKEUP + Hardware automatic sampling registers for wakeup function. + 0x70 + 0x20 + 0x000000C8 + + + ADC2_HW_READ_EN_I + Enable hardware automatic sampling. + 0 + 1 + read-write + + + ADC2_HW_READ_RATE_I + Hardware automatic sampling rate. + 1 + 16 + read-write + + + + + RND_ECO_LOW + N/A + 0x74 + 0x20 + + + RND_ECO_LOW + N/A + 0 + 32 + read-write + + + + + RND_ECO_HIGH + N/A + 0x78 + 0x20 + 0xFFFFFFFF + + + RND_ECO_HIGH + N/A + 0 + 32 + read-write + + + + + RND_ECO_CS + N/A + 0x7C + 0x20 + + + RND_ECO_EN + N/A + 0 + 1 + read-write + + + RND_ECO_RESULT + N/A + 1 + 1 + read-only + + + + + + + LP_TIMER + Low-power Timer + RTC_TIMER + 0x50112000 + + 0x0 + 0x4C + registers + + + LP_TIMER0 + 2 + + + LP_TIMER1 + 3 + + + + TAR0_LOW + need_des + 0x0 + 0x20 + + + MAIN_TIMER_TAR_LOW0 + need_des + 0 + 32 + read-write + + + + + TAR0_HIGH + need_des + 0x4 + 0x20 + + + MAIN_TIMER_TAR_HIGH0 + need_des + 0 + 16 + read-write + + + MAIN_TIMER_TAR_EN0 + need_des + 31 + 1 + write-only + + + + + TAR1_LOW + need_des + 0x8 + 0x20 + + + MAIN_TIMER_TAR_LOW1 + need_des + 0 + 32 + read-write + + + + + TAR1_HIGH + need_des + 0xC + 0x20 + + + MAIN_TIMER_TAR_HIGH1 + need_des + 0 + 16 + read-write + + + MAIN_TIMER_TAR_EN1 + need_des + 31 + 1 + write-only + + + + + UPDATE + need_des + 0x10 + 0x20 + + + MAIN_TIMER_UPDATE + need_des + 28 + 1 + write-only + + + MAIN_TIMER_XTAL_OFF + need_des + 29 + 1 + read-write + + + MAIN_TIMER_SYS_STALL + need_des + 30 + 1 + read-write + + + MAIN_TIMER_SYS_RST + need_des + 31 + 1 + read-write + + + + + MAIN_BUF0_LOW + need_des + 0x14 + 0x20 + + + MAIN_TIMER_BUF0_LOW + need_des + 0 + 32 + read-only + + + + + MAIN_BUF0_HIGH + need_des + 0x18 + 0x20 + + + MAIN_TIMER_BUF0_HIGH + need_des + 0 + 16 + read-only + + + + + MAIN_BUF1_LOW + need_des + 0x1C + 0x20 + + + MAIN_TIMER_BUF1_LOW + need_des + 0 + 32 + read-only + + + + + MAIN_BUF1_HIGH + need_des + 0x20 + 0x20 + + + MAIN_TIMER_BUF1_HIGH + need_des + 0 + 16 + read-only + + + + + MAIN_OVERFLOW + need_des + 0x24 + 0x20 + + + MAIN_TIMER_ALARM_LOAD + need_des + 31 + 1 + write-only + + + + + INT_RAW + need_des + 0x28 + 0x20 + + + OVERFLOW_RAW + need_des + 30 + 1 + read-write + + + SOC_WAKEUP_INT_RAW + need_des + 31 + 1 + read-write + + + + + INT_ST + need_des + 0x2C + 0x20 + + + OVERFLOW_ST + need_des + 30 + 1 + read-only + + + SOC_WAKEUP_INT_ST + need_des + 31 + 1 + read-only + + + + + INT_ENA + need_des + 0x30 + 0x20 + + + OVERFLOW_ENA + need_des + 30 + 1 + read-write + + + SOC_WAKEUP_INT_ENA + need_des + 31 + 1 + read-write + + + + + INT_CLR + need_des + 0x34 + 0x20 + + + OVERFLOW_CLR + need_des + 30 + 1 + write-only + + + SOC_WAKEUP_INT_CLR + need_des + 31 + 1 + write-only + + + + + LP_INT_RAW + need_des + 0x38 + 0x20 + + + MAIN_TIMER_OVERFLOW_LP_INT_RAW + need_des + 30 + 1 + read-write + + + MAIN_TIMER_LP_INT_RAW + need_des + 31 + 1 + read-write + + + + + LP_INT_ST + need_des + 0x3C + 0x20 + + + MAIN_TIMER_OVERFLOW_LP_INT_ST + need_des + 30 + 1 + read-only + + + MAIN_TIMER_LP_INT_ST + need_des + 31 + 1 + read-only + + + + + LP_INT_ENA + need_des + 0x40 + 0x20 + + + MAIN_TIMER_OVERFLOW_LP_INT_ENA + need_des + 30 + 1 + read-write + + + MAIN_TIMER_LP_INT_ENA + need_des + 31 + 1 + read-write + + + + + LP_INT_CLR + need_des + 0x44 + 0x20 + + + MAIN_TIMER_OVERFLOW_LP_INT_CLR + need_des + 30 + 1 + write-only + + + MAIN_TIMER_LP_INT_CLR + need_des + 31 + 1 + write-only + + + + + DATE + need_des + 0x3FC + 0x20 + 0x02111150 + + + DATE + need_des + 0 + 31 + read-write + + + CLK_EN + need_des + 31 + 1 + read-write + + + + + + + LP_TOUCH + LP_TOUCH Peripheral + RTC_TOUCH + 0x50128000 + + 0x0 + 0x64 + registers + + + LP_TOUCH + 14 + + + + INT_RAW + need_des + 0x0 + 0x20 + + + SCAN_DONE_INT_RAW + need_des + 0 + 1 + read-write + + + DONE_INT_RAW + need_des + 1 + 1 + read-write + + + ACTIVE_INT_RAW + need_des + 2 + 1 + read-write + + + INACTIVE_INT_RAW + need_des + 3 + 1 + read-write + + + TIMEOUT_INT_RAW + need_des + 4 + 1 + read-write + + + APPROACH_LOOP_DONE_INT_RAW + need_des + 5 + 1 + read-write + + + + + INT_ST + need_des + 0x4 + 0x20 + + + SCAN_DONE_INT_ST + need_des + 0 + 1 + read-only + + + DONE_INT_ST + need_des + 1 + 1 + read-only + + + ACTIVE_INT_ST + need_des + 2 + 1 + read-only + + + INACTIVE_INT_ST + need_des + 3 + 1 + read-only + + + TIMEOUT_INT_ST + need_des + 4 + 1 + read-only + + + APPROACH_LOOP_DONE_INT_ST + need_des + 5 + 1 + read-only + + + + + INT_ENA + need_des + 0x8 + 0x20 + + + SCAN_DONE_INT_ENA + need_des + 0 + 1 + read-write + + + DONE_INT_ENA + need_des + 1 + 1 + read-write + + + ACTIVE_INT_ENA + need_des + 2 + 1 + read-write + + + INACTIVE_INT_ENA + need_des + 3 + 1 + read-write + + + TIMEOUT_INT_ENA + need_des + 4 + 1 + read-write + + + APPROACH_LOOP_DONE_INT_ENA + need_des + 5 + 1 + read-write + + + + + INT_CLR + need_des + 0xC + 0x20 + + + SCAN_DONE_INT_CLR + need_des + 0 + 1 + write-only + + + DONE_INT_CLR + need_des + 1 + 1 + write-only + + + ACTIVE_INT_CLR + need_des + 2 + 1 + write-only + + + INACTIVE_INT_CLR + need_des + 3 + 1 + write-only + + + TIMEOUT_INT_CLR + need_des + 4 + 1 + write-only + + + APPROACH_LOOP_DONE_INT_CLR + need_des + 5 + 1 + write-only + + + + + CHN_STATUS + need_des + 0x10 + 0x20 + + + PAD_ACTIVE + need_des + 0 + 15 + read-only + + + MEAS_DONE + need_des + 15 + 1 + read-only + + + SCAN_CURR + need_des + 16 + 4 + read-only + + + + + STATUS_0 + need_des + 0x14 + 0x20 + + + PAD0_DATA + need_des + 0 + 16 + read-only + + + PAD0_DEBOUNCE_CNT + need_des + 16 + 3 + read-only + + + PAD0_NEG_NOISE_CNT + need_des + 19 + 4 + read-only + + + + + STATUS_1 + need_des + 0x18 + 0x20 + + + PAD1_DATA + need_des + 0 + 16 + read-only + + + PAD1_DEBOUNCE_CNT + need_des + 16 + 3 + read-only + + + PAD1_NEG_NOISE_CNT + need_des + 19 + 4 + read-only + + + + + STATUS_2 + need_des + 0x1C + 0x20 + + + PAD2_DATA + need_des + 0 + 16 + read-only + + + PAD2_DEBOUNCE_CNT + need_des + 16 + 3 + read-only + + + PAD2_NEG_NOISE_CNT + need_des + 19 + 4 + read-only + + + + + STATUS_3 + need_des + 0x20 + 0x20 + + + PAD3_DATA + need_des + 0 + 16 + read-only + + + PAD3_DEBOUNCE_CNT + need_des + 16 + 3 + read-only + + + PAD3_NEG_NOISE_CNT + need_des + 19 + 4 + read-only + + + + + STATUS_4 + need_des + 0x24 + 0x20 + + + PAD4_DATA + need_des + 0 + 16 + read-only + + + PAD4_DEBOUNCE_CNT + need_des + 16 + 3 + read-only + + + PAD4_NEG_NOISE_CNT + need_des + 19 + 4 + read-only + + + + + STATUS_5 + need_des + 0x28 + 0x20 + + + PAD5_DATA + need_des + 0 + 16 + read-only + + + PAD5_DEBOUNCE_CNT + need_des + 16 + 3 + read-only + + + PAD5_NEG_NOISE_CNT + need_des + 19 + 4 + read-only + + + + + STATUS_6 + need_des + 0x2C + 0x20 + + + PAD6_DATA + need_des + 0 + 16 + read-only + + + PAD6_DEBOUNCE_CNT + need_des + 16 + 3 + read-only + + + PAD6_NEG_NOISE_CNT + need_des + 19 + 4 + read-only + + + + + STATUS_7 + need_des + 0x30 + 0x20 + + + PAD7_DATA + need_des + 0 + 16 + read-only + + + PAD7_DEBOUNCE_CNT + need_des + 16 + 3 + read-only + + + PAD7_NEG_NOISE_CNT + need_des + 19 + 4 + read-only + + + + + STATUS_8 + need_des + 0x34 + 0x20 + + + PAD8_DATA + need_des + 0 + 16 + read-only + + + PAD8_DEBOUNCE_CNT + need_des + 16 + 3 + read-only + + + PAD8_NEG_NOISE_CNT + need_des + 19 + 4 + read-only + + + + + STATUS_9 + need_des + 0x38 + 0x20 + + + PAD9_DATA + need_des + 0 + 16 + read-only + + + PAD9_DEBOUNCE_CNT + need_des + 16 + 3 + read-only + + + PAD9_NEG_NOISE_CNT + need_des + 19 + 4 + read-only + + + + + STATUS_10 + need_des + 0x3C + 0x20 + + + PAD10_DATA + need_des + 0 + 16 + read-only + + + PAD10_DEBOUNCE_CNT + need_des + 16 + 3 + read-only + + + PAD10_NEG_NOISE_CNT + need_des + 19 + 4 + read-only + + + + + STATUS_11 + need_des + 0x40 + 0x20 + + + PAD11_DATA + need_des + 0 + 16 + read-only + + + PAD11_DEBOUNCE_CNT + need_des + 16 + 3 + read-only + + + PAD11_NEG_NOISE_CNT + need_des + 19 + 4 + read-only + + + + + STATUS_12 + need_des + 0x44 + 0x20 + + + PAD12_DATA + need_des + 0 + 16 + read-only + + + PAD12_DEBOUNCE_CNT + need_des + 16 + 3 + read-only + + + PAD12_NEG_NOISE_CNT + need_des + 19 + 4 + read-only + + + + + STATUS_13 + need_des + 0x48 + 0x20 + + + PAD13_DATA + need_des + 0 + 16 + read-only + + + PAD13_DEBOUNCE_CNT + need_des + 16 + 3 + read-only + + + PAD13_NEG_NOISE_CNT + need_des + 19 + 4 + read-only + + + + + STATUS_14 + need_des + 0x4C + 0x20 + + + PAD14_DATA + need_des + 0 + 16 + read-only + + + PAD14_DEBOUNCE_CNT + need_des + 16 + 3 + read-only + + + PAD14_NEG_NOISE_CNT + need_des + 19 + 4 + read-only + + + + + STATUS_15 + need_des + 0x50 + 0x20 + + + SLP_DATA + need_des + 0 + 16 + read-only + + + SLP_DEBOUNCE_CNT + need_des + 16 + 3 + read-only + + + SLP_NEG_NOISE_CNT + need_des + 19 + 4 + read-only + + + + + STATUS_16 + need_des + 0x54 + 0x20 + + + APPROACH_PAD2_CNT + need_des + 0 + 8 + read-only + + + APPROACH_PAD1_CNT + need_des + 8 + 8 + read-only + + + APPROACH_PAD0_CNT + need_des + 16 + 8 + read-only + + + SLP_APPROACH_CNT + need_des + 24 + 8 + read-only + + + + + STATUS_17 + need_des + 0x58 + 0x20 + + + DCAP_LPF + Reserved + 0 + 7 + read-only + + + DRES_LPF + need_des + 7 + 2 + read-only + + + DRV_LS + need_des + 9 + 4 + read-only + + + DRV_HS + need_des + 13 + 5 + read-only + + + DBIAS + need_des + 18 + 5 + read-only + + + RTC_FREQ_SCAN_CNT + need_des + 23 + 2 + read-only + + + + + CHN_TMP_STATUS + need_des + 0x5C + 0x20 + + + PAD_INACTIVE_STATUS + need_des + 0 + 15 + read-only + + + PAD_ACTIVE_STATUS + need_des + 15 + 15 + read-only + + + + + DATE + need_des + 0x100 + 0x20 + 0x00230314 + + + RTC_DATE + need_des + 0 + 28 + read-write + + + RTC_CLK_EN + need_des + 31 + 1 + read-write + + + + + + + LP_WDT + Low-power Watchdog Timer + RTC_WDT + 0x50116000 + + 0x0 + 0x38 + registers + + + LP_WDT + 1 + + + + CONFIG0 + need_des + 0x0 + 0x20 + 0x00013214 + + + WDT_CHIP_RESET_WIDTH + need_des + 0 + 8 + read-write + + + WDT_CHIP_RESET_EN + need_des + 8 + 1 + read-write + + + WDT_PAUSE_IN_SLP + need_des + 9 + 1 + read-write + + + WDT_APPCPU_RESET_EN + need_des + 10 + 1 + read-write + + + WDT_PROCPU_RESET_EN + need_des + 11 + 1 + read-write + + + WDT_FLASHBOOT_MOD_EN + need_des + 12 + 1 + read-write + + + WDT_SYS_RESET_LENGTH + need_des + 13 + 3 + read-write + + + WDT_CPU_RESET_LENGTH + need_des + 16 + 3 + read-write + + + WDT_STG3 + need_des + 19 + 3 + read-write + + + WDT_STG2 + need_des + 22 + 3 + read-write + + + WDT_STG1 + need_des + 25 + 3 + read-write + + + WDT_STG0 + need_des + 28 + 3 + read-write + + + WDT_EN + need_des + 31 + 1 + read-write + + + + + CONFIG1 + need_des + 0x4 + 0x20 + 0x00030D40 + + + WDT_STG0_HOLD + need_des + 0 + 32 + read-write + + + + + CONFIG2 + need_des + 0x8 + 0x20 + 0x00013880 + + + WDT_STG1_HOLD + need_des + 0 + 32 + read-write + + + + + CONFIG3 + need_des + 0xC + 0x20 + 0x00000FFF + + + WDT_STG2_HOLD + need_des + 0 + 32 + read-write + + + + + CONFIG4 + need_des + 0x10 + 0x20 + 0x00000FFF + + + WDT_STG3_HOLD + need_des + 0 + 32 + read-write + + + + + FEED + need_des + 0x14 + 0x20 + + + FEED + need_des + 31 + 1 + write-only + + + + + WPROTECT + need_des + 0x18 + 0x20 + + + WDT_WKEY + need_des + 0 + 32 + read-write + + + + + SWD_CONFIG + need_des + 0x1C + 0x20 + 0x12C00000 + + + SWD_RESET_FLAG + need_des + 0 + 1 + read-only + + + SWD_AUTO_FEED_EN + need_des + 18 + 1 + read-write + + + SWD_RST_FLAG_CLR + need_des + 19 + 1 + write-only + + + SWD_SIGNAL_WIDTH + need_des + 20 + 10 + read-write + + + SWD_DISABLE + need_des + 30 + 1 + read-write + + + SWD_FEED + need_des + 31 + 1 + write-only + + + + + SWD_WPROTECT + need_des + 0x20 + 0x20 + + + SWD_WKEY + need_des + 0 + 32 + read-write + + + + + INT_RAW + need_des + 0x24 + 0x20 + + + SUPER_WDT_INT_RAW + need_des + 30 + 1 + read-write + + + LP_WDT_INT_RAW + need_des + 31 + 1 + read-write + + + + + INT_ST + need_des + 0x28 + 0x20 + + + SUPER_WDT_INT_ST + need_des + 30 + 1 + read-only + + + LP_WDT_INT_ST + need_des + 31 + 1 + read-only + + + + + INT_ENA + need_des + 0x2C + 0x20 + + + SUPER_WDT_INT_ENA + need_des + 30 + 1 + read-write + + + LP_WDT_INT_ENA + need_des + 31 + 1 + read-write + + + + + INT_CLR + need_des + 0x30 + 0x20 + + + SUPER_WDT_INT_CLR + need_des + 30 + 1 + write-only + + + LP_WDT_INT_CLR + need_des + 31 + 1 + write-only + + + + + DATE + need_des + 0x3FC + 0x20 + 0x02112080 + + + LP_WDT_DATE + need_des + 0 + 31 + read-write + + + CLK_EN + need_des + 31 + 1 + read-write + + + + + + + SDHOST + SD/MMC Host Controller + SDHOST + 0x50083000 + + 0x0 + 0xB0 + registers + + + + CTRL + Control register + 0x0 + 0x20 + + + CONTROLLER_RESET + To reset controller, firmware should set this bit. This bit is auto-cleared after two AHB and two sdhost_cclk_in clock cycles. + 0 + 1 + read-write + + + FIFO_RESET + To reset FIFO, firmware should set bit to 1. This bit is auto-cleared after completion of reset operation. +Note: FIFO pointers will be out of reset after 2 cycles of system clocks in addition to synchronization delay (2 cycles of card clock), after the fifo_reset is cleared. + 1 + 1 + read-write + + + DMA_RESET + To reset DMA interface, firmware should set bit to 1. This bit is auto-cleared after two AHB clocks. + 2 + 1 + read-write + + + INT_ENABLE + Global interrupt enable/disable bit. 0: Disable; 1: Enable. + 4 + 1 + read-write + + + READ_WAIT + For sending read-wait to SDIO cards. + 6 + 1 + read-write + + + SEND_IRQ_RESPONSE + Bit automatically clears once response is sent. To wait for MMC card interrupts, host issues CMD40 and waits for interrupt response from MMC card(s). In the meantime, if host wants SD/MMC to exit waiting for interrupt state, it can set this bit, at which time SD/MMC command state-machine sends CMD40 response on bus and returns to idle state. + 7 + 1 + read-write + + + ABORT_READ_DATA + After a suspend-command is issued during a read-operation, software polls the card to find when the suspend-event occurred. Once the suspend-event has occurred, software sets the bit which will reset the data state machine that is waiting for the next block of data. This bit is automatically cleared once the data state machine is reset to idle. + 8 + 1 + read-write + + + SEND_CCSD + When set, SD/MMC sends CCSD to the CE-ATA device. Software sets this bit only if the current command is expecting CCS (that is, RW_BLK), and if interrupts are enabled for the CE-ATA device. Once the CCSD pattern is sent to the device, SD/MMC automatically clears the SDHOST_SEND_CCSD bit. It also sets the Command Done (CD) bit in the SDHOST_RINTSTS_REG register, and generates an interrupt for the host, in case the Command Done interrupt is not masked. +NOTE: Once the SDHOST_SEND_CCSD bit is set, it takes two card clock cycles to drive the CCSD on the CMD line. Due to this, within the boundary conditions the CCSD may be sent to the CE-ATA device, even if the device has signalled CCS. + 9 + 1 + read-write + + + SEND_AUTO_STOP_CCSD + Always Set SDHOST_SEND_AUTO_STOP_CCSD and SDHOST_SEND_CCSD bits together; SDHOST_SEND_AUTO_STOP_CCSD should not be set independently of send_ccsd. When set, SD/MMC automatically sends an internally-generated STOP command (CMD12) to the CE-ATA device. After sending this internally-generated STOP command, the Auto Command Done (ACD) bit in SDHOST_RINTSTS_REG is set and an interrupt is generated for the host, in case the ACD interrupt is not masked. After sending the Command Completion Signal Disable (CCSD), SD/MMC automatically clears the SDHOST_SEND_AUTO_STOP_CCSD bit. + 10 + 1 + read-write + + + CEATA_DEVICE_INTERRUPT_STATUS + Software should appropriately write to this bit after the power-on reset or any other reset to the CE-ATA device. After reset, the CE-ATA device's interrupt is usually disabled (nIEN = 1). If the host enables the CE-ATA device's interrupt, then software should set this bit. + 11 + 1 + read-write + + + + + CLKDIV + Clock divider configuration register + 0x8 + 0x20 + + + CLK_DIVIDER0 + Clock divider0 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on. + 0 + 8 + read-write + + + CLK_DIVIDER1 + Clock divider1 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on. + 8 + 8 + read-write + + + CLK_DIVIDER2 + Clock divider2 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on. + 16 + 8 + read-write + + + CLK_DIVIDER3 + Clock divider3 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on. + 24 + 8 + read-write + + + + + CLKSRC + Clock source selection register + 0xC + 0x20 + + + CLKSRC + Clock divider source for two SD cards is supported. Each card has two bits assigned to it. For example, bit[1:0] are assigned for card 0, bit[3:2] are assigned for card 1. Card 0 maps and internally routes clock divider[0:3] outputs to cclk_out[1:0] pins, depending on bit value. +00 : Clock divider 0; +01 : Clock divider 1; +10 : Clock divider 2; +11 : Clock divider 3. + 0 + 4 + read-write + + + + + CLKENA + Clock enable register + 0x10 + 0x20 + + + CCLK_ENABLE + Clock-enable control for two SD card clocks and one MMC card clock is supported. One bit per card. +0: Clock disabled; +1: Clock enabled. + 0 + 2 + read-write + + + LP_ENABLE + Disable clock when the card is in IDLE state. One bit per card. +0: clock disabled; +1: clock enabled. + 16 + 2 + read-write + + + + + TMOUT + Data and response timeout configuration register + 0x14 + 0x20 + 0xFFFFFF40 + + + RESPONSE_TIMEOUT + Response timeout value. Value is specified in terms of number of card output clocks, i.e., sdhost_cclk_out. + 0 + 8 + read-write + + + DATA_TIMEOUT + Value for card data read timeout. This value is also used for data starvation by host timeout. The timeout counter is started only after the card clock is stopped. This value is specified in number of card output clocks, i.e. sdhost_cclk_out of the selected card. +NOTE: The software timer should be used if the timeout value is in the order of 100 ms. In this case, read data timeout interrupt needs to be disabled. + 8 + 24 + read-write + + + + + CTYPE + Card bus width configuration register + 0x18 + 0x20 + + + CARD_WIDTH4 + One bit per card indicates if card is 1-bit or 4-bit mode. +0: 1-bit mode; +1: 4-bit mode. +Bit[1:0] correspond to card[1:0] respectively. + 0 + 2 + read-write + + + CARD_WIDTH8 + One bit per card indicates if card is in 8-bit mode. +0: Non 8-bit mode; +1: 8-bit mode. +Bit[17:16] correspond to card[1:0] respectively. + 16 + 2 + read-write + + + + + BLKSIZ + Card data block size configuration register + 0x1C + 0x20 + 0x00000200 + + + BLOCK_SIZE + Block size. + 0 + 16 + read-write + + + + + BYTCNT + Data transfer length configuration register + 0x20 + 0x20 + 0x00000200 + + + BYTE_COUNT + Number of bytes to be transferred, should be an integral multiple of Block Size for block transfers. For data transfers of undefined byte lengths, byte count should be set to 0. When byte count is set to 0, it is the responsibility of host to explicitly send stop/abort command to terminate data transfer. + 0 + 32 + read-write + + + + + INTMASK + SDIO interrupt mask register + 0x24 + 0x20 + + + INT_MASK + These bits used to mask unwanted interrupts. A value of 0 masks interrupt, and a value of 1 enables the interrupt. +Bit 15 (EBE): End-bit error/no CRC error; +Bit 14 (ACD): Auto command done; +Bit 13 (SBE/BCI): Rx Start Bit Error; +Bit 12 (HLE): Hardware locked write error; +Bit 11 (FRUN): FIFO underrun/overrun error; +Bit 10 (HTO): Data starvation-by-host timeout; +Bit 9 (DRTO): Data read timeout; +Bit 8 (RTO): Response timeout; +Bit 7 (DCRC): Data CRC error; +Bit 6 (RCRC): Response CRC error; +Bit 5 (RXDR): Receive FIFO data request; +Bit 4 (TXDR): Transmit FIFO data request; +Bit 3 (DTO): Data transfer over; +Bit 2 (CD): Command done; +Bit 1 (RE): Response error; +Bit 0 (CD): Card detect. + 0 + 16 + read-write + + + SDIO_INT_MASK + SDIO interrupt mask, one bit for each card. Bit[17:16] correspond to card[15:0] respectively. When masked, SDIO interrupt detection for that card is disabled. 0 masks an interrupt, and 1 enables an interrupt. + 16 + 2 + read-write + + + + + CMDARG + Command argument data register + 0x28 + 0x20 + + + CMDARG + Value indicates command argument to be passed to the card. + 0 + 32 + read-write + + + + + CMD + Command and boot configuration register + 0x2C + 0x20 + 0x20000000 + + + INDEX + Command index. + 0 + 6 + read-write + + + RESPONSE_EXPECT + 0: No response expected from card; 1: Response expected from card. + 6 + 1 + read-write + + + RESPONSE_LENGTH + 0: Short response expected from card; 1: Long response expected from card. + 7 + 1 + read-write + + + CHECK_RESPONSE_CRC + 0: Do not check; 1: Check response CRC. +Some of command responses do not return valid CRC bits. Software should disable CRC checks for those commands in order to disable CRC checking by controller. + 8 + 1 + read-write + + + DATA_EXPECTED + 0: No data transfer expected; 1: Data transfer expected. + 9 + 1 + read-write + + + READ_WRITE + 0: Read from card; 1: Write to card. +Don't care if no data is expected from card. + 10 + 1 + read-write + + + TRANSFER_MODE + 0: Block data transfer command; 1: Stream data transfer command. +Don't care if no data expected. + 11 + 1 + read-write + + + SEND_AUTO_STOP + 0: No stop command is sent at the end of data transfer; 1: Send stop command at the end of data transfer. + 12 + 1 + read-write + + + WAIT_PRVDATA_COMPLETE + 0: Send command at once, even if previous data transfer has not completed; 1: Wait for previous data transfer to complete before sending Command. +The SDHOST_WAIT_PRVDATA_COMPLETE] = 0 option is typically used to query status of card during data transfer or to stop current data transfer. SDHOST_CARD_NUMBERr should be same as in previous command. + 13 + 1 + read-write + + + STOP_ABORT_CMD + 0: Neither stop nor abort command can stop current data transfer. If abort is sent to function-number currently selected or not in data-transfer mode, then bit should be set to 0; 1: Stop or abort command intended to stop current data transfer in progress. +When open-ended or predefined data transfer is in progress, and host issues stop or abort command to stop data transfer, bit should be set so that command/data state-machines of CIU can return correctly to idle state. + 14 + 1 + read-write + + + SEND_INITIALIZATION + 0: Do not send initialization sequence (80 clocks of 1) before sending this command; 1: Send initialization sequence before sending this command. +After powered on, 80 clocks must be sent to card for initialization before sending any commands to card. Bit should be set while sending first command to card so that controller will initialize clocks before sending command to card. + 15 + 1 + read-write + + + CARD_NUMBER + Card number in use. Represents physical slot number of card being accessed. In SD-only mode, up to two cards are supported. + 16 + 5 + read-write + + + UPDATE_CLOCK_REGISTERS_ONLY + 0: Normal command sequence; 1: Do not send commands, just update clock register value into card clock domain. +Following register values are transferred into card clock domain: CLKDIV, CLRSRC, and CLKENA. +Changes card clocks (change frequency, truncate off or on, and set low-frequency mode). This is provided in order to change clock frequency or stop clock without having to send command to cards. During normal command sequence, when sdhost_update_clock_registers_only = 0, following control registers are transferred from BIU to CIU: CMD, CMDARG, TMOUT, CTYPE, BLKSIZ, and BYTCNT. CIU uses new register values for new command sequence to card(s). When bit is set, there are no Command Done interrupts because no command is sent to SD_MMC_CEATA cards. + 21 + 1 + read-write + + + READ_CEATA_DEVICE + Read access flag. +0: Host is not performing read access (RW_REG or RW_BLK)towards CE-ATA device; +1: Host is performing read access (RW_REG or RW_BLK) towards CE-ATA device. +Software should set this bit to indicate that CE-ATA device is being accessed for read transfer. This bit is used to disable read data timeout indication while performing CE-ATA read transfers. Maximum value of I/O transmission delay can be no less than 10 seconds. SD/MMC should not indicate read data timeout while waiting for data from CE-ATA device. + 22 + 1 + read-write + + + CCS_EXPECTED + Expected Command Completion Signal (CCS) configuration. +0: Interrupts are not enabled in CE-ATA device (nIEN = 1 in ATA control register), or command does not expect CCS from device; +1: Interrupts are enabled in CE-ATA device (nIEN = 0), and RW_BLK command expects command completion signal from CE-ATA device. +If the command expects Command Completion Signal (CCS) from the CE-ATA device, the software should set this control bit. SD/MMC sets Data Transfer Over (DTO) bit in RINTSTS register and generates interrupt to host if Data Transfer Over interrupt is not masked. + 23 + 1 + read-write + + + USE_HOLE + Use Hold Register. +0: CMD and DATA sent to card bypassing HOLD Register; +1: CMD and DATA sent to card through the HOLD Register. + 29 + 1 + read-write + + + START_CMD + Start command. Once command is served by the CIU, this bit is automatically cleared. When this bit is set, host should not attempt to write to any command registers. If a write is attempted, hardware lock error is set in raw interrupt register. Once command is sent and a response is received from SD_MMC_CEATA cards, Command Done bit is set in the raw interrupt Register. + 31 + 1 + read-write + + + + + RESP0 + Response data register + 0x30 + 0x20 + + + RESPONSE0 + Bit[31:0] of response. + 0 + 32 + read-only + + + + + RESP1 + Long response data register + 0x34 + 0x20 + + + RESPONSE1 + Bit[63:32] of long response. + 0 + 32 + read-only + + + + + RESP2 + Long response data register + 0x38 + 0x20 + + + RESPONSE2 + Bit[95:64] of long response. + 0 + 32 + read-only + + + + + RESP3 + Long response data register + 0x3C + 0x20 + + + RESPONSE3 + Bit[127:96] of long response. + 0 + 32 + read-only + + + + + MINTSTS + Masked interrupt status register + 0x40 + 0x20 + + + INT_STATUS_MSK + Interrupt enabled only if corresponding bit in interrupt mask register is set. +Bit 15 (EBE): End-bit error/no CRC error; +Bit 14 (ACD): Auto command done; +Bit 13 (SBE/BCI): RX Start Bit Error; +Bit 12 (HLE): Hardware locked write error; +Bit 11 (FRUN): FIFO underrun/overrun error; +Bit 10 (HTO): Data starvation by host timeout (HTO); +Bit 9 (DTRO): Data read timeout; +Bit 8 (RTO): Response timeout; +Bit 7 (DCRC): Data CRC error; +Bit 6 (RCRC): Response CRC error; +Bit 5 (RXDR): Receive FIFO data request; +Bit 4 (TXDR): Transmit FIFO data request; +Bit 3 (DTO): Data transfer over; +Bit 2 (CD): Command done; +Bit 1 (RE): Response error; +Bit 0 (CD): Card detect. + 0 + 16 + read-only + + + SDIO_INTERRUPT_MSK + Interrupt from SDIO card, one bit for each card. Bit[17:16] correspond to card1 and card0, respectively. SDIO interrupt for card is enabled only if corresponding sdhost_sdio_int_mask bit is set in Interrupt mask register (Setting mask bit enables interrupt). + 16 + 2 + read-only + + + + + RINTSTS + Raw interrupt status register + 0x44 + 0x20 + + + INT_STATUS_RAW + Setting a bit clears the corresponding interrupt and writing 0 has no effect. Bits are logged regardless of interrupt mask status. +Bit 15 (EBE): End-bit error/no CRC error; +Bit 14 (ACD): Auto command done; +Bit 13 (SBE/BCI): RX Start Bit Error; +Bit 12 (HLE): Hardware locked write error; +Bit 11 (FRUN): FIFO underrun/overrun error; +Bit 10 (HTO): Data starvation by host timeout (HTO); +Bit 9 (DTRO): Data read timeout; +Bit 8 (RTO): Response timeout; +Bit 7 (DCRC): Data CRC error; +Bit 6 (RCRC): Response CRC error; +Bit 5 (RXDR): Receive FIFO data request; +Bit 4 (TXDR): Transmit FIFO data request; +Bit 3 (DTO): Data transfer over; +Bit 2 (CD): Command done; +Bit 1 (RE): Response error; +Bit 0 (CD): Card detect. + 0 + 16 + read-write + + + SDIO_INTERRUPT_RAW + Interrupt from SDIO card, one bit for each card. Bit[17:16] correspond to card1 and card0, respectively. Setting a bit clears the corresponding interrupt bit and writing 0 has no effect. +0: No SDIO interrupt from card; +1: SDIO interrupt from card. + 16 + 2 + read-write + + + + + STATUS + SD/MMC status register + 0x48 + 0x20 + 0x00000716 + + + FIFO_RX_WATERMARK + FIFO reached Receive watermark level, not qualified with data transfer. + 0 + 1 + read-only + + + FIFO_TX_WATERMARK + FIFO reached Transmit watermark level, not qualified with data transfer. + 1 + 1 + read-only + + + FIFO_EMPTY + FIFO is empty status. + 2 + 1 + read-only + + + FIFO_FULL + FIFO is full status. + 3 + 1 + read-only + + + COMMAND_FSM_STATES + Command FSM states. +0: Idle; +1: Send init sequence; +2: Send cmd start bit; +3: Send cmd tx bit; +4: Send cmd index + arg; +5: Send cmd crc7; +6: Send cmd end bit; +7: Receive resp start bit; +8: Receive resp IRQ response; +9: Receive resp tx bit; +10: Receive resp cmd idx; +11: Receive resp data; +12: Receive resp crc7; +13: Receive resp end bit; +14: Cmd path wait NCC; +15: Wait, cmd-to-response turnaround. + 4 + 4 + read-only + + + DATA_3_STATUS + Raw selected sdhost_card_data[3], checks whether card is present. +0: card not present; +1: card present. + 8 + 1 + read-only + + + DATA_BUSY + Inverted version of raw selected sdhost_card_data[0]. +0: Card data not busy; +1: Card data busy. + 9 + 1 + read-only + + + DATA_STATE_MC_BUSY + Data transmit or receive state-machine is busy. + 10 + 1 + read-only + + + RESPONSE_INDEX + Index of previous response, including any auto-stop sent by core. + 11 + 6 + read-only + + + FIFO_COUNT + FIFO count, number of filled locations in FIFO. + 17 + 13 + read-only + + + + + FIFOTH + FIFO configuration register + 0x4C + 0x20 + + + TX_WMARK + FIFO threshold watermark level when transmitting data to card. When FIFO data count is less than or equal to this number, DMA/FIFO request is raised. If Interrupt is enabled, then interrupt occurs. During end of packet, request or interrupt is generated, regardless of threshold programming.In non-DMA mode, when transmit FIFO threshold (TXDR) interrupt is enabled, then interrupt is generated instead of DMA request. During end of packet, on last interrupt, host is responsible for filling FIFO with only required remaining bytes (not before FIFO is full or after CIU completes data transfers, because FIFO may not be empty). In DMA mode, at end of packet, if last transfer is less than burst size, DMA controller does single cycles until required bytes are transferred. + 0 + 12 + read-write + + + RX_WMARK + FIFO threshold watermark level when receiving data to card.When FIFO data count reaches greater than this number , DMA/FIFO request is raised. During end of packet, request is generated regardless of threshold programming in order to complete any remaining data.In non-DMA mode, when receiver FIFO threshold (RXDR) interrupt is enabled, then interrupt is generated instead of DMA request.During end of packet, interrupt is not generated if threshold programming is larger than any remaining data. It is responsibility of host to read remaining bytes on seeing Data Transfer Done interrupt.In DMA mode, at end of packet, even if remaining bytes are less than threshold, DMA request does single transfers to flush out any remaining bytes before Data Transfer Done interrupt is set. + 16 + 11 + read-write + + + DMA_MULTIPLE_TRANSACTION_SIZE + Burst size of multiple transaction, should be programmed same as DMA controller multiple-transaction-size SDHOST_SRC/DEST_MSIZE. +000: 1-byte transfer; +001: 4-byte transfer; +010: 8-byte transfer; +011: 16-byte transfer; +100: 32-byte transfer; +101: 64-byte transfer; +110: 128-byte transfer; +111: 256-byte transfer. + 28 + 3 + read-write + + + + + CDETECT + Card detect register + 0x50 + 0x20 + + + CARD_DETECT_N + Value on sdhost_card_detect_n input ports (1 bit per card), read-only bits. 0 represents presence of card. Only NUM_CARDS number of bits are implemented. + 0 + 2 + read-only + + + + + WRTPRT + Card write protection (WP) status register + 0x54 + 0x20 + + + WRITE_PROTECT + Value on sdhost_card_write_prt input ports (1 bit per card). 1 represents write protection. Only NUM_CARDS number of bits are implemented. + 0 + 2 + read-only + + + + + TCBCNT + Transferred byte count register + 0x5C + 0x20 + + + TCBCNT + Number of bytes transferred by CIU unit to card. + 0 + 32 + read-only + + + + + TBBCNT + Transferred byte count register + 0x60 + 0x20 + + + TBBCNT + Number of bytes transferred between Host/DMA memory and BIU FIFO. + 0 + 32 + read-only + + + + + DEBNCE + Debounce filter time configuration register + 0x64 + 0x20 + + + DEBOUNCE_COUNT + Number of host clocks (clk) used by debounce filter logic. The typical debounce time is 5 \verb+~+ 25 ms to prevent the card instability when the card is inserted or removed. + 0 + 24 + read-write + + + + + USRID + User ID (scratchpad) register + 0x68 + 0x20 + + + USRID + User identification register, value set by user. Can also be used as a scratchpad register by user. + 0 + 32 + read-write + + + + + VERID + Version ID (scratchpad) register + 0x6C + 0x20 + 0x5432270A + + + VERSIONID + Hardware version register. Can also be read by fireware. + 0 + 32 + read-only + + + + + HCON + Hardware feature register + 0x70 + 0x20 + 0x03444CC3 + + + CARD_TYPE + Hardware support SDIO and MMC. + 0 + 1 + read-only + + + CARD_NUM + Support card number is 2. + 1 + 5 + read-only + + + BUS_TYPE + Register config is APB bus. + 6 + 1 + read-only + + + DATA_WIDTH + Regisger data widht is 32. + 7 + 3 + read-only + + + ADDR_WIDTH + Register address width is 32. + 10 + 6 + read-only + + + DMA_WIDTH + DMA data witdth is 32. + 18 + 3 + read-only + + + RAM_INDISE + Inside RAM in SDMMC module. + 21 + 1 + read-only + + + HOLD + Have a hold regiser in data path . + 22 + 1 + read-only + + + NUM_CLK_DIV + Have 4 clk divider in design . + 24 + 2 + read-only + + + + + UHS + UHS-1 register + 0x74 + 0x20 + + + DDR + DDR mode selecton,1 bit for each card. +0-Non-DDR mdoe. +1-DDR mdoe. + 16 + 2 + read-write + + + + + RST_N + Card reset register + 0x78 + 0x20 + 0x00000001 + + + CARD_RESET + Hardware reset. +1: Active mode; +0: Reset. +These bits cause the cards to enter pre-idle state, which requires them to be re-initialized. SDHOST_RST_CARD_RESET[0] should be set to 1'b0 to reset card0, SDHOST_RST_CARD_RESET[1] should be set to 1'b0 to reset card1. + 0 + 2 + read-write + + + + + BMOD + Burst mode transfer configuration register + 0x80 + 0x20 + + + SWR + Software Reset. When set, the DMA Controller resets all its internal registers. It is automatically cleared after one clock cycle. + 0 + 1 + read-write + + + FB + Fixed Burst. Controls whether the AHB Master interface performs fixed burst transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16 during start of normal burst transfers. When reset, the AHB will use SINGLE and INCR burst transfer operations. + 1 + 1 + read-write + + + DE + IDMAC Enable. When set, the IDMAC is enabled. + 7 + 1 + read-write + + + PBL + Programmable Burst Length. These bits indicate the maximum number of beats to be performed in one IDMAC???Internal DMA Control???transaction. The IDMAC will always attempt to burst as specified in PBL each time it starts a burst transfer on the host bus. The permissible values are 1, 4, 8, 16, 32, 64, 128 and 256. This value is the mirror of MSIZE of FIFOTH register. In order to change this value, write the required value to FIFOTH register. This is an encode value as follows: +000: 1-byte transfer; +001: 4-byte transfer; +010: 8-byte transfer; +011: 16-byte transfer; +100: 32-byte transfer; +101: 64-byte transfer; +110: 128-byte transfer; +111: 256-byte transfer. +PBL is a read-only value and is applicable only for data access, it does not apply to descriptor access. + 8 + 3 + read-write + + + + + PLDMND + Poll demand configuration register + 0x84 + 0x20 + + + PD + Poll Demand. If the OWNER bit of a descriptor is not set, the FSM goes to the Suspend state. The host needs to write any value into this register for the IDMAC FSM to resume normal descriptor fetch operation. This is a write only . + 0 + 32 + write-only + + + + + DBADDR + Descriptor base address register + 0x88 + 0x20 + + + DBADDR + Start of Descriptor List. Contains the base address of the First Descriptor. The LSB bits [1:0] are ignored and taken as all-zero by the IDMAC internally. Hence these LSB bits may be treated as read-only. + 0 + 32 + read-write + + + + + IDSTS + IDMAC status register + 0x8C + 0x20 + + + TI + Transmit Interrupt. Indicates that data transmission is finished for a descriptor. Writing 1 clears this bit. + 0 + 1 + read-write + + + RI + Receive Interrupt. Indicates the completion of data reception for a descriptor. Writing 1 clears this bit. + 1 + 1 + read-write + + + FBE + Fatal Bus Error Interrupt. Indicates that a Bus Error occurred (IDSTS[12:10]) . When this bit is set, the DMA disables all its bus accesses. Writing 1 clears this bit. + 2 + 1 + read-write + + + DU + Descriptor Unavailable Interrupt. This bit is set when the descriptor is unavailable due to OWNER bit = 0 (DES0[31] = 0). Writing 1 clears this bit. + 4 + 1 + read-write + + + CES + Card Error Summary. Indicates the status of the transaction to/from the card, also present in RINTSTS. Indicates the logical OR of the following bits: +EBE : End Bit Error; +RTO : Response Timeout/Boot Ack Timeout; +RCRC : Response CRC; +SBE : Start Bit Error; +DRTO : Data Read Timeout/BDS timeout; +DCRC : Data CRC for Receive; +RE : Response Error. +Writing 1 clears this bit. The abort condition of the IDMAC depends on the setting of this CES bit. If the CES bit is enabled, then the IDMAC aborts on a response error. + 5 + 1 + read-write + + + NIS + Normal Interrupt Summary. Logical OR of the following: IDSTS[0] : Transmit Interrupt, IDSTS[1] : Receive Interrupt. Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes NIS to be set is cleared. Writing 1 clears this bit. + 8 + 1 + read-write + + + AIS + Abnormal Interrupt Summary. Logical OR of the following: IDSTS[2] : Fatal Bus Interrupt, IDSTS[4] : DU bit Interrupt. Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes AIS to be set is cleared. Writing 1 clears this bit. + 9 + 1 + read-write + + + FBE_CODE + Fatal Bus Error Code. Indicates the type of error that caused a Bus Error. Valid only when the Fatal Bus Error bit IDSTS[2] is set. This field does not generate an interrupt. +001: Host Abort received during transmission; +010: Host Abort received during reception; +Others: Reserved. + 10 + 3 + read-write + + + FSM + DMAC FSM present state. +0: DMA_IDLE (idle state); +1: DMA_SUSPEND (suspend state); +2: DESC_RD (descriptor reading state); +3: DESC_CHK (descriptor checking state); +4: DMA_RD_REQ_WAIT (read-data request waiting state); +5: DMA_WR_REQ_WAIT (write-data request waiting state); +6: DMA_RD (data-read state); +7: DMA_WR (data-write state); +8: DESC_CLOSE (descriptor close state). + 13 + 4 + read-write + + + + + IDINTEN + IDMAC interrupt enable register + 0x90 + 0x20 + + + TI + Transmit Interrupt Enable. When set with Normal Interrupt Summary Enable, Transmit Interrupt is enabled. When reset, Transmit Interrupt is disabled. + 0 + 1 + read-write + + + RI + Receive Interrupt Enable. When set with Normal Interrupt Summary Enable, Receive Interrupt is enabled. When reset, Receive Interrupt is disabled. + 1 + 1 + read-write + + + FBE + Fatal Bus Error Enable. When set with Abnormal Interrupt Summary Enable, the Fatal Bus Error Interrupt is enabled. When reset, Fatal Bus Error Enable Interrupt is disabled. + 2 + 1 + read-write + + + DU + Descriptor Unavailable Interrupt. When set along with Abnormal Interrupt Summary Enable, the DU interrupt is enabled. + 4 + 1 + read-write + + + CES + Card Error summary Interrupt Enable. When set, it enables the Card Interrupt summary. + 5 + 1 + read-write + + + NI + Normal Interrupt Summary Enable. When set, a normal interrupt is enabled. When reset, a normal interrupt is disabled. This bit enables the following bits: +IDINTEN[0]: Transmit Interrupt; +IDINTEN[1]: Receive Interrupt. + 8 + 1 + read-write + + + AI + Abnormal Interrupt Summary Enable. When set, an abnormal interrupt is enabled. This bit enables the following bits: +IDINTEN[2]: Fatal Bus Error Interrupt; +IDINTEN[4]: DU Interrupt. + 9 + 1 + read-write + + + + + DSCADDR + Host descriptor address pointer + 0x94 + 0x20 + + + DSCADDR + Host Descriptor Address Pointer, updated by IDMAC during operation and cleared on reset. This register points to the start address of the current descriptor read by the IDMAC. + 0 + 32 + read-only + + + + + BUFADDR + Host buffer address pointer register + 0x98 + 0x20 + + + BUFADDR + Host Buffer Address Pointer, updated by IDMAC during operation and cleared on reset. This register points to the current Data Buffer Address being accessed by the IDMAC. + 0 + 32 + read-only + + + + + CARDTHRCTL + Card Threshold Control register + 0x100 + 0x20 + + + CARDRDTHREN + Card read threshold enable. +1'b0-Card read threshold disabled. +1'b1-Card read threshold enabled. + 0 + 1 + read-write + + + CARDCLRINTEN + Busy clear interrupt generation: +1'b0-Busy clear interrypt disabled. +1'b1-Busy clear interrypt enabled. + 1 + 1 + read-write + + + CARDWRTHREN + Applicable when HS400 mode is enabled. +1'b0-Card write Threshold disabled. +1'b1-Card write Threshold enabled. + 2 + 1 + read-write + + + CARDTHRESHOLD + The inside FIFO size is 512,This register is applicable when SDHOST_CARDERTHREN_REG is set to 1 or SDHOST_CARDRDTHREN_REG set to 1. + 16 + 16 + read-write + + + + + EMMCDDR + eMMC DDR register + 0x10C + 0x20 + + + HALFSTARTBIT + Control for start bit detection mechanism duration of start bit.Each bit refers to one slot.Set this bit to 1 for eMMC4.5 and above,set to 0 for SD applications.For eMMC4.5,start bit can be: +1'b0-Full cycle. +1'b1-less than one full cycle. + 0 + 2 + read-write + + + HS400_MODE + Set 1 to enable HS400 mode. + 31 + 1 + read-write + + + + + ENSHIFT + Enable Phase Shift register + 0x110 + 0x20 + + + ENABLE_SHIFT + Control for the amount of phase shift provided on the default enables in the design.Two bits assigned for each card. +2'b00-Default phase shift. +2'b01-Enables shifted to next immediate positive edge. +2'b10-Enables shifted to next immediate negative edge. +2'b11-Reserved. + 0 + 4 + read-write + + + + + BUFFIFO + CPU write and read transmit data by FIFO + 0x200 + 0x20 + + + BUFFIFO + CPU write and read transmit data by FIFO. This register points to the current Data FIFO . + 0 + 32 + read-write + + + + + CLK_EDGE_SEL + SDIO control register. + 0x800 + 0x20 + 0x00820200 + + + CCLKIN_EDGE_DRV_SEL + It's used to select the clock phase of the output signal from phase 0, phase 90, phase 180, phase 270. + 0 + 3 + read-write + + + CCLKIN_EDGE_SAM_SEL + It's used to select the clock phase of the input signal from phase 0, phase 90, phase 180, phase 270. + 3 + 3 + read-write + + + CCLKIN_EDGE_SLF_SEL + It's used to select the clock phase of the internal signal from phase 0, phase 90, phase 180, phase 270. + 6 + 3 + read-write + + + CCLLKIN_EDGE_H + The high level of the divider clock. The value should be smaller than CCLKIN_EDGE_L. + 9 + 4 + read-write + + + CCLLKIN_EDGE_L + The low level of the divider clock. The value should be larger than CCLKIN_EDGE_H. + 13 + 4 + read-write + + + CCLLKIN_EDGE_N + The clock division of cclk_in. + 17 + 4 + read-write + + + ESDIO_MODE + Enable esdio mode. + 21 + 1 + read-write + + + ESD_MODE + Enable esd mode. + 22 + 1 + read-write + + + CCLK_EN + Sdio clock enable. + 23 + 1 + read-write + + + ULTRA_HIGH_SPEED_MODE + Enable ultra high speed mode, use dll to generate clk. + 24 + 1 + read-write + + + + + RAW_INTS + SDIO raw ints register. + 0x804 + 0x20 + + + RAW_INTS + It indicates raw ints. + 0 + 32 + read-only + + + + + DLL_CLK_CONF + SDIO DLL clock control register. + 0x808 + 0x20 + + + DLL_CCLK_IN_SLF_EN + Clock enable of cclk_in_slf when ULTRA_HIGH_SPEED_MODE==1. + 0 + 1 + read-write + + + DLL_CCLK_IN_DRV_EN + Clock enable of cclk_in_drv when ULTRA_HIGH_SPEED_MODE==1. + 1 + 1 + read-write + + + DLL_CCLK_IN_SAM_EN + Clock enable of cclk_in_sam when ULTRA_HIGH_SPEED_MODE==1. + 2 + 1 + read-write + + + DLL_CCLK_IN_SLF_PHASE + It's used to control the phase of cclk_in_slf when ULTRA_HIGH_SPEED_MODE==1. + 3 + 6 + read-write + + + DLL_CCLK_IN_DRV_PHASE + It's used to control the phase of cclk_in_drv when ULTRA_HIGH_SPEED_MODE==1. + 9 + 6 + read-write + + + DLL_CCLK_IN_SAM_PHASE + It's used to control the phase of cclk_in_sam when ULTRA_HIGH_SPEED_MODE==1. + 15 + 6 + read-write + + + + + DLL_CONF + SDIO DLL configuration register. + 0x80C + 0x20 + + + DLL_CAL_STOP + Set 1 to stop calibration. + 0 + 1 + read-write + + + DLL_CAL_END + 1 means calibration finished. + 1 + 1 + read-only + + + + + + + SHA + SHA (Secure Hash Algorithm) Accelerator + SHA + 0x50091000 + + 0x0 + 0xB0 + registers + + + SHA + 70 + + + + MODE + Initial configuration register. + 0x0 + 0x20 + + + MODE + Sha mode. + 0 + 3 + read-write + + + + + T_STRING + SHA 512/t configuration register 0. + 0x4 + 0x20 + + + T_STRING + Sha t_string (used if and only if mode == SHA_512/t). + 0 + 32 + read-write + + + + + T_LENGTH + SHA 512/t configuration register 1. + 0x8 + 0x20 + + + T_LENGTH + Sha t_length (used if and only if mode == SHA_512/t). + 0 + 6 + read-write + + + + + DMA_BLOCK_NUM + DMA configuration register 0. + 0xC + 0x20 + + + DMA_BLOCK_NUM + Dma-sha block number. + 0 + 6 + read-write + + + + + START + Typical SHA configuration register 0. + 0x10 + 0x20 + + + START + Reserved. + 1 + 31 + read-only + + + + + CONTINUE + Typical SHA configuration register 1. + 0x14 + 0x20 + + + CONTINUE + Reserved. + 1 + 31 + read-only + + + + + BUSY + Busy register. + 0x18 + 0x20 + + + STATE + Sha busy state. 1'b0: idle. 1'b1: busy. + 0 + 1 + read-only + + + + + DMA_START + DMA configuration register 1. + 0x1C + 0x20 + + + DMA_START + Start dma-sha. + 0 + 1 + write-only + + + + + DMA_CONTINUE + DMA configuration register 2. + 0x20 + 0x20 + + + DMA_CONTINUE + Continue dma-sha. + 0 + 1 + write-only + + + + + CLEAR_IRQ + Interrupt clear register. + 0x24 + 0x20 + + + CLEAR_INTERRUPT + Clear sha interrupt. + 0 + 1 + write-only + + + + + IRQ_ENA + Interrupt enable register. + 0x28 + 0x20 + + + INTERRUPT_ENA + Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable. + 0 + 1 + read-write + + + + + DATE + Date register. + 0x2C + 0x20 + 0x20201229 + + + DATE + Sha date information/ sha version information. + 0 + 30 + read-write + + + + + 16 + 0x4 + H_MEM[%s] + Sha H memory which contains intermediate hash or finial hash. + 0x40 + 0x20 + + + 16 + 0x4 + M_MEM[%s] + Sha M memory which contains message. + 0x80 + 0x20 + + + + + SOC_ETM + Event Task Matrix + SOC_ETM + 0x500D5000 + + 0x0 + 0x228 + registers + + + + CH_ENA_AD0 + Channel enable status register + 0x0 + 0x20 + + + CH_ENA0 + Represents ch0 enable status.\\0: Disable\\1: Enable + 0 + 1 + read-write + + + CH_ENA1 + Represents ch1 enable status.\\0: Disable\\1: Enable + 1 + 1 + read-write + + + CH_ENA2 + Represents ch2 enable status.\\0: Disable\\1: Enable + 2 + 1 + read-write + + + CH_ENA3 + Represents ch3 enable status.\\0: Disable\\1: Enable + 3 + 1 + read-write + + + CH_ENA4 + Represents ch4 enable status.\\0: Disable\\1: Enable + 4 + 1 + read-write + + + CH_ENA5 + Represents ch5 enable status.\\0: Disable\\1: Enable + 5 + 1 + read-write + + + CH_ENA6 + Represents ch6 enable status.\\0: Disable\\1: Enable + 6 + 1 + read-write + + + CH_ENA7 + Represents ch7 enable status.\\0: Disable\\1: Enable + 7 + 1 + read-write + + + CH_ENA8 + Represents ch8 enable status.\\0: Disable\\1: Enable + 8 + 1 + read-write + + + CH_ENA9 + Represents ch9 enable status.\\0: Disable\\1: Enable + 9 + 1 + read-write + + + CH_ENA10 + Represents ch10 enable status.\\0: Disable\\1: Enable + 10 + 1 + read-write + + + CH_ENA11 + Represents ch11 enable status.\\0: Disable\\1: Enable + 11 + 1 + read-write + + + CH_ENA12 + Represents ch12 enable status.\\0: Disable\\1: Enable + 12 + 1 + read-write + + + CH_ENA13 + Represents ch13 enable status.\\0: Disable\\1: Enable + 13 + 1 + read-write + + + CH_ENA14 + Represents ch14 enable status.\\0: Disable\\1: Enable + 14 + 1 + read-write + + + CH_ENA15 + Represents ch15 enable status.\\0: Disable\\1: Enable + 15 + 1 + read-write + + + CH_ENA16 + Represents ch16 enable status.\\0: Disable\\1: Enable + 16 + 1 + read-write + + + CH_ENA17 + Represents ch17 enable status.\\0: Disable\\1: Enable + 17 + 1 + read-write + + + CH_ENA18 + Represents ch18 enable status.\\0: Disable\\1: Enable + 18 + 1 + read-write + + + CH_ENA19 + Represents ch19 enable status.\\0: Disable\\1: Enable + 19 + 1 + read-write + + + CH_ENA20 + Represents ch20 enable status.\\0: Disable\\1: Enable + 20 + 1 + read-write + + + CH_ENA21 + Represents ch21 enable status.\\0: Disable\\1: Enable + 21 + 1 + read-write + + + CH_ENA22 + Represents ch22 enable status.\\0: Disable\\1: Enable + 22 + 1 + read-write + + + CH_ENA23 + Represents ch23 enable status.\\0: Disable\\1: Enable + 23 + 1 + read-write + + + CH_ENA24 + Represents ch24 enable status.\\0: Disable\\1: Enable + 24 + 1 + read-write + + + CH_ENA25 + Represents ch25 enable status.\\0: Disable\\1: Enable + 25 + 1 + read-write + + + CH_ENA26 + Represents ch26 enable status.\\0: Disable\\1: Enable + 26 + 1 + read-write + + + CH_ENA27 + Represents ch27 enable status.\\0: Disable\\1: Enable + 27 + 1 + read-write + + + CH_ENA28 + Represents ch28 enable status.\\0: Disable\\1: Enable + 28 + 1 + read-write + + + CH_ENA29 + Represents ch29 enable status.\\0: Disable\\1: Enable + 29 + 1 + read-write + + + CH_ENA30 + Represents ch30 enable status.\\0: Disable\\1: Enable + 30 + 1 + read-write + + + CH_ENA31 + Represents ch31 enable status.\\0: Disable\\1: Enable + 31 + 1 + read-write + + + + + CH_ENA_AD0_SET + Channel enable set register + 0x4 + 0x20 + + + CH_SET0 + Configures whether or not to enable ch0.\\0: Invalid, No effect\\1: Enable + 0 + 1 + write-only + + + CH_SET1 + Configures whether or not to enable ch1.\\0: Invalid, No effect\\1: Enable + 1 + 1 + write-only + + + CH_SET2 + Configures whether or not to enable ch2.\\0: Invalid, No effect\\1: Enable + 2 + 1 + write-only + + + CH_SET3 + Configures whether or not to enable ch3.\\0: Invalid, No effect\\1: Enable + 3 + 1 + write-only + + + CH_SET4 + Configures whether or not to enable ch4.\\0: Invalid, No effect\\1: Enable + 4 + 1 + write-only + + + CH_SET5 + Configures whether or not to enable ch5.\\0: Invalid, No effect\\1: Enable + 5 + 1 + write-only + + + CH_SET6 + Configures whether or not to enable ch6.\\0: Invalid, No effect\\1: Enable + 6 + 1 + write-only + + + CH_SET7 + Configures whether or not to enable ch7.\\0: Invalid, No effect\\1: Enable + 7 + 1 + write-only + + + CH_SET8 + Configures whether or not to enable ch8.\\0: Invalid, No effect\\1: Enable + 8 + 1 + write-only + + + CH_SET9 + Configures whether or not to enable ch9.\\0: Invalid, No effect\\1: Enable + 9 + 1 + write-only + + + CH_SET10 + Configures whether or not to enable ch10.\\0: Invalid, No effect\\1: Enable + 10 + 1 + write-only + + + CH_SET11 + Configures whether or not to enable ch11.\\0: Invalid, No effect\\1: Enable + 11 + 1 + write-only + + + CH_SET12 + Configures whether or not to enable ch12.\\0: Invalid, No effect\\1: Enable + 12 + 1 + write-only + + + CH_SET13 + Configures whether or not to enable ch13.\\0: Invalid, No effect\\1: Enable + 13 + 1 + write-only + + + CH_SET14 + Configures whether or not to enable ch14.\\0: Invalid, No effect\\1: Enable + 14 + 1 + write-only + + + CH_SET15 + Configures whether or not to enable ch15.\\0: Invalid, No effect\\1: Enable + 15 + 1 + write-only + + + CH_SET16 + Configures whether or not to enable ch16.\\0: Invalid, No effect\\1: Enable + 16 + 1 + write-only + + + CH_SET17 + Configures whether or not to enable ch17.\\0: Invalid, No effect\\1: Enable + 17 + 1 + write-only + + + CH_SET18 + Configures whether or not to enable ch18.\\0: Invalid, No effect\\1: Enable + 18 + 1 + write-only + + + CH_SET19 + Configures whether or not to enable ch19.\\0: Invalid, No effect\\1: Enable + 19 + 1 + write-only + + + CH_SET20 + Configures whether or not to enable ch20.\\0: Invalid, No effect\\1: Enable + 20 + 1 + write-only + + + CH_SET21 + Configures whether or not to enable ch21.\\0: Invalid, No effect\\1: Enable + 21 + 1 + write-only + + + CH_SET22 + Configures whether or not to enable ch22.\\0: Invalid, No effect\\1: Enable + 22 + 1 + write-only + + + CH_SET23 + Configures whether or not to enable ch23.\\0: Invalid, No effect\\1: Enable + 23 + 1 + write-only + + + CH_SET24 + Configures whether or not to enable ch24.\\0: Invalid, No effect\\1: Enable + 24 + 1 + write-only + + + CH_SET25 + Configures whether or not to enable ch25.\\0: Invalid, No effect\\1: Enable + 25 + 1 + write-only + + + CH_SET26 + Configures whether or not to enable ch26.\\0: Invalid, No effect\\1: Enable + 26 + 1 + write-only + + + CH_SET27 + Configures whether or not to enable ch27.\\0: Invalid, No effect\\1: Enable + 27 + 1 + write-only + + + CH_SET28 + Configures whether or not to enable ch28.\\0: Invalid, No effect\\1: Enable + 28 + 1 + write-only + + + CH_SET29 + Configures whether or not to enable ch29.\\0: Invalid, No effect\\1: Enable + 29 + 1 + write-only + + + CH_SET30 + Configures whether or not to enable ch30.\\0: Invalid, No effect\\1: Enable + 30 + 1 + write-only + + + CH_SET31 + Configures whether or not to enable ch31.\\0: Invalid, No effect\\1: Enable + 31 + 1 + write-only + + + + + CH_ENA_AD0_CLR + Channel enable clear register + 0x8 + 0x20 + + + CH_CLR0 + Configures whether or not to clear ch0 enable.\\0: Invalid, No effect\\1: Clear + 0 + 1 + write-only + + + CH_CLR1 + Configures whether or not to clear ch1 enable.\\0: Invalid, No effect\\1: Clear + 1 + 1 + write-only + + + CH_CLR2 + Configures whether or not to clear ch2 enable.\\0: Invalid, No effect\\1: Clear + 2 + 1 + write-only + + + CH_CLR3 + Configures whether or not to clear ch3 enable.\\0: Invalid, No effect\\1: Clear + 3 + 1 + write-only + + + CH_CLR4 + Configures whether or not to clear ch4 enable.\\0: Invalid, No effect\\1: Clear + 4 + 1 + write-only + + + CH_CLR5 + Configures whether or not to clear ch5 enable.\\0: Invalid, No effect\\1: Clear + 5 + 1 + write-only + + + CH_CLR6 + Configures whether or not to clear ch6 enable.\\0: Invalid, No effect\\1: Clear + 6 + 1 + write-only + + + CH_CLR7 + Configures whether or not to clear ch7 enable.\\0: Invalid, No effect\\1: Clear + 7 + 1 + write-only + + + CH_CLR8 + Configures whether or not to clear ch8 enable.\\0: Invalid, No effect\\1: Clear + 8 + 1 + write-only + + + CH_CLR9 + Configures whether or not to clear ch9 enable.\\0: Invalid, No effect\\1: Clear + 9 + 1 + write-only + + + CH_CLR10 + Configures whether or not to clear ch10 enable.\\0: Invalid, No effect\\1: Clear + 10 + 1 + write-only + + + CH_CLR11 + Configures whether or not to clear ch11 enable.\\0: Invalid, No effect\\1: Clear + 11 + 1 + write-only + + + CH_CLR12 + Configures whether or not to clear ch12 enable.\\0: Invalid, No effect\\1: Clear + 12 + 1 + write-only + + + CH_CLR13 + Configures whether or not to clear ch13 enable.\\0: Invalid, No effect\\1: Clear + 13 + 1 + write-only + + + CH_CLR14 + Configures whether or not to clear ch14 enable.\\0: Invalid, No effect\\1: Clear + 14 + 1 + write-only + + + CH_CLR15 + Configures whether or not to clear ch15 enable.\\0: Invalid, No effect\\1: Clear + 15 + 1 + write-only + + + CH_CLR16 + Configures whether or not to clear ch16 enable.\\0: Invalid, No effect\\1: Clear + 16 + 1 + write-only + + + CH_CLR17 + Configures whether or not to clear ch17 enable.\\0: Invalid, No effect\\1: Clear + 17 + 1 + write-only + + + CH_CLR18 + Configures whether or not to clear ch18 enable.\\0: Invalid, No effect\\1: Clear + 18 + 1 + write-only + + + CH_CLR19 + Configures whether or not to clear ch19 enable.\\0: Invalid, No effect\\1: Clear + 19 + 1 + write-only + + + CH_CLR20 + Configures whether or not to clear ch20 enable.\\0: Invalid, No effect\\1: Clear + 20 + 1 + write-only + + + CH_CLR21 + Configures whether or not to clear ch21 enable.\\0: Invalid, No effect\\1: Clear + 21 + 1 + write-only + + + CH_CLR22 + Configures whether or not to clear ch22 enable.\\0: Invalid, No effect\\1: Clear + 22 + 1 + write-only + + + CH_CLR23 + Configures whether or not to clear ch23 enable.\\0: Invalid, No effect\\1: Clear + 23 + 1 + write-only + + + CH_CLR24 + Configures whether or not to clear ch24 enable.\\0: Invalid, No effect\\1: Clear + 24 + 1 + write-only + + + CH_CLR25 + Configures whether or not to clear ch25 enable.\\0: Invalid, No effect\\1: Clear + 25 + 1 + write-only + + + CH_CLR26 + Configures whether or not to clear ch26 enable.\\0: Invalid, No effect\\1: Clear + 26 + 1 + write-only + + + CH_CLR27 + Configures whether or not to clear ch27 enable.\\0: Invalid, No effect\\1: Clear + 27 + 1 + write-only + + + CH_CLR28 + Configures whether or not to clear ch28 enable.\\0: Invalid, No effect\\1: Clear + 28 + 1 + write-only + + + CH_CLR29 + Configures whether or not to clear ch29 enable.\\0: Invalid, No effect\\1: Clear + 29 + 1 + write-only + + + CH_CLR30 + Configures whether or not to clear ch30 enable.\\0: Invalid, No effect\\1: Clear + 30 + 1 + write-only + + + CH_CLR31 + Configures whether or not to clear ch31 enable.\\0: Invalid, No effect\\1: Clear + 31 + 1 + write-only + + + + + CH_ENA_AD1 + Channel enable status register + 0xC + 0x20 + + + CH_ENA32 + Represents ch32 enable status.\\0: Disable\\1: Enable + 0 + 1 + read-write + + + CH_ENA33 + Represents ch33 enable status.\\0: Disable\\1: Enable + 1 + 1 + read-write + + + CH_ENA34 + Represents ch34 enable status.\\0: Disable\\1: Enable + 2 + 1 + read-write + + + CH_ENA35 + Represents ch35 enable status.\\0: Disable\\1: Enable + 3 + 1 + read-write + + + CH_ENA36 + Represents ch36 enable status.\\0: Disable\\1: Enable + 4 + 1 + read-write + + + CH_ENA37 + Represents ch37 enable status.\\0: Disable\\1: Enable + 5 + 1 + read-write + + + CH_ENA38 + Represents ch38 enable status.\\0: Disable\\1: Enable + 6 + 1 + read-write + + + CH_ENA39 + Represents ch39 enable status.\\0: Disable\\1: Enable + 7 + 1 + read-write + + + CH_ENA40 + Represents ch40 enable status.\\0: Disable\\1: Enable + 8 + 1 + read-write + + + CH_ENA41 + Represents ch41 enable status.\\0: Disable\\1: Enable + 9 + 1 + read-write + + + CH_ENA42 + Represents ch42 enable status.\\0: Disable\\1: Enable + 10 + 1 + read-write + + + CH_ENA43 + Represents ch43 enable status.\\0: Disable\\1: Enable + 11 + 1 + read-write + + + CH_ENA44 + Represents ch44 enable status.\\0: Disable\\1: Enable + 12 + 1 + read-write + + + CH_ENA45 + Represents ch45 enable status.\\0: Disable\\1: Enable + 13 + 1 + read-write + + + CH_ENA46 + Represents ch46 enable status.\\0: Disable\\1: Enable + 14 + 1 + read-write + + + CH_ENA47 + Represents ch47 enable status.\\0: Disable\\1: Enable + 15 + 1 + read-write + + + CH_ENA48 + Represents ch48 enable status.\\0: Disable\\1: Enable + 16 + 1 + read-write + + + CH_ENA49 + Represents ch49 enable status.\\0: Disable\\1: Enable + 17 + 1 + read-write + + + + + CH_ENA_AD1_SET + Channel enable set register + 0x10 + 0x20 + + + CH_SET32 + Configures whether or not to enable ch32.\\0: Invalid, No effect\\1: Enable + 0 + 1 + write-only + + + CH_SET33 + Configures whether or not to enable ch33.\\0: Invalid, No effect\\1: Enable + 1 + 1 + write-only + + + CH_SET34 + Configures whether or not to enable ch34.\\0: Invalid, No effect\\1: Enable + 2 + 1 + write-only + + + CH_SET35 + Configures whether or not to enable ch35.\\0: Invalid, No effect\\1: Enable + 3 + 1 + write-only + + + CH_SET36 + Configures whether or not to enable ch36.\\0: Invalid, No effect\\1: Enable + 4 + 1 + write-only + + + CH_SET37 + Configures whether or not to enable ch37.\\0: Invalid, No effect\\1: Enable + 5 + 1 + write-only + + + CH_SET38 + Configures whether or not to enable ch38.\\0: Invalid, No effect\\1: Enable + 6 + 1 + write-only + + + CH_SET39 + Configures whether or not to enable ch39.\\0: Invalid, No effect\\1: Enable + 7 + 1 + write-only + + + CH_SET40 + Configures whether or not to enable ch40.\\0: Invalid, No effect\\1: Enable + 8 + 1 + write-only + + + CH_SET41 + Configures whether or not to enable ch41.\\0: Invalid, No effect\\1: Enable + 9 + 1 + write-only + + + CH_SET42 + Configures whether or not to enable ch42.\\0: Invalid, No effect\\1: Enable + 10 + 1 + write-only + + + CH_SET43 + Configures whether or not to enable ch43.\\0: Invalid, No effect\\1: Enable + 11 + 1 + write-only + + + CH_SET44 + Configures whether or not to enable ch44.\\0: Invalid, No effect\\1: Enable + 12 + 1 + write-only + + + CH_SET45 + Configures whether or not to enable ch45.\\0: Invalid, No effect\\1: Enable + 13 + 1 + write-only + + + CH_SET46 + Configures whether or not to enable ch46.\\0: Invalid, No effect\\1: Enable + 14 + 1 + write-only + + + CH_SET47 + Configures whether or not to enable ch47.\\0: Invalid, No effect\\1: Enable + 15 + 1 + write-only + + + CH_SET48 + Configures whether or not to enable ch48.\\0: Invalid, No effect\\1: Enable + 16 + 1 + write-only + + + CH_SET49 + Configures whether or not to enable ch49.\\0: Invalid, No effect\\1: Enable + 17 + 1 + write-only + + + + + CH_ENA_AD1_CLR + Channel enable clear register + 0x14 + 0x20 + + + CH_CLR32 + Configures whether or not to clear ch32 enable.\\0: Invalid, No effect\\1: Clear + 0 + 1 + write-only + + + CH_CLR33 + Configures whether or not to clear ch33 enable.\\0: Invalid, No effect\\1: Clear + 1 + 1 + write-only + + + CH_CLR34 + Configures whether or not to clear ch34 enable.\\0: Invalid, No effect\\1: Clear + 2 + 1 + write-only + + + CH_CLR35 + Configures whether or not to clear ch35 enable.\\0: Invalid, No effect\\1: Clear + 3 + 1 + write-only + + + CH_CLR36 + Configures whether or not to clear ch36 enable.\\0: Invalid, No effect\\1: Clear + 4 + 1 + write-only + + + CH_CLR37 + Configures whether or not to clear ch37 enable.\\0: Invalid, No effect\\1: Clear + 5 + 1 + write-only + + + CH_CLR38 + Configures whether or not to clear ch38 enable.\\0: Invalid, No effect\\1: Clear + 6 + 1 + write-only + + + CH_CLR39 + Configures whether or not to clear ch39 enable.\\0: Invalid, No effect\\1: Clear + 7 + 1 + write-only + + + CH_CLR40 + Configures whether or not to clear ch40 enable.\\0: Invalid, No effect\\1: Clear + 8 + 1 + write-only + + + CH_CLR41 + Configures whether or not to clear ch41 enable.\\0: Invalid, No effect\\1: Clear + 9 + 1 + write-only + + + CH_CLR42 + Configures whether or not to clear ch42 enable.\\0: Invalid, No effect\\1: Clear + 10 + 1 + write-only + + + CH_CLR43 + Configures whether or not to clear ch43 enable.\\0: Invalid, No effect\\1: Clear + 11 + 1 + write-only + + + CH_CLR44 + Configures whether or not to clear ch44 enable.\\0: Invalid, No effect\\1: Clear + 12 + 1 + write-only + + + CH_CLR45 + Configures whether or not to clear ch45 enable.\\0: Invalid, No effect\\1: Clear + 13 + 1 + write-only + + + CH_CLR46 + Configures whether or not to clear ch46 enable.\\0: Invalid, No effect\\1: Clear + 14 + 1 + write-only + + + CH_CLR47 + Configures whether or not to clear ch47 enable.\\0: Invalid, No effect\\1: Clear + 15 + 1 + write-only + + + CH_CLR48 + Configures whether or not to clear ch48 enable.\\0: Invalid, No effect\\1: Clear + 16 + 1 + write-only + + + CH_CLR49 + Configures whether or not to clear ch49 enable.\\0: Invalid, No effect\\1: Clear + 17 + 1 + write-only + + + + + CH0_EVT_ID + Channel0 event id register + 0x18 + 0x20 + + + CH0_EVT_ID + Configures ch0_evt_id + 0 + 8 + read-write + + + + + CH0_TASK_ID + Channel0 task id register + 0x1C + 0x20 + + + CH0_TASK_ID + Configures ch0_task_id + 0 + 8 + read-write + + + + + CH1_EVT_ID + Channel1 event id register + 0x20 + 0x20 + + + CH1_EVT_ID + Configures ch1_evt_id + 0 + 8 + read-write + + + + + CH1_TASK_ID + Channel1 task id register + 0x24 + 0x20 + + + CH1_TASK_ID + Configures ch1_task_id + 0 + 8 + read-write + + + + + CH2_EVT_ID + Channel2 event id register + 0x28 + 0x20 + + + CH2_EVT_ID + Configures ch2_evt_id + 0 + 8 + read-write + + + + + CH2_TASK_ID + Channel2 task id register + 0x2C + 0x20 + + + CH2_TASK_ID + Configures ch2_task_id + 0 + 8 + read-write + + + + + CH3_EVT_ID + Channel3 event id register + 0x30 + 0x20 + + + CH3_EVT_ID + Configures ch3_evt_id + 0 + 8 + read-write + + + + + CH3_TASK_ID + Channel3 task id register + 0x34 + 0x20 + + + CH3_TASK_ID + Configures ch3_task_id + 0 + 8 + read-write + + + + + CH4_EVT_ID + Channel4 event id register + 0x38 + 0x20 + + + CH4_EVT_ID + Configures ch4_evt_id + 0 + 8 + read-write + + + + + CH4_TASK_ID + Channel4 task id register + 0x3C + 0x20 + + + CH4_TASK_ID + Configures ch4_task_id + 0 + 8 + read-write + + + + + CH5_EVT_ID + Channel5 event id register + 0x40 + 0x20 + + + CH5_EVT_ID + Configures ch5_evt_id + 0 + 8 + read-write + + + + + CH5_TASK_ID + Channel5 task id register + 0x44 + 0x20 + + + CH5_TASK_ID + Configures ch5_task_id + 0 + 8 + read-write + + + + + CH6_EVT_ID + Channel6 event id register + 0x48 + 0x20 + + + CH6_EVT_ID + Configures ch6_evt_id + 0 + 8 + read-write + + + + + CH6_TASK_ID + Channel6 task id register + 0x4C + 0x20 + + + CH6_TASK_ID + Configures ch6_task_id + 0 + 8 + read-write + + + + + CH7_EVT_ID + Channel7 event id register + 0x50 + 0x20 + + + CH7_EVT_ID + Configures ch7_evt_id + 0 + 8 + read-write + + + + + CH7_TASK_ID + Channel7 task id register + 0x54 + 0x20 + + + CH7_TASK_ID + Configures ch7_task_id + 0 + 8 + read-write + + + + + CH8_EVT_ID + Channel8 event id register + 0x58 + 0x20 + + + CH8_EVT_ID + Configures ch8_evt_id + 0 + 8 + read-write + + + + + CH8_TASK_ID + Channel8 task id register + 0x5C + 0x20 + + + CH8_TASK_ID + Configures ch8_task_id + 0 + 8 + read-write + + + + + CH9_EVT_ID + Channel9 event id register + 0x60 + 0x20 + + + CH9_EVT_ID + Configures ch9_evt_id + 0 + 8 + read-write + + + + + CH9_TASK_ID + Channel9 task id register + 0x64 + 0x20 + + + CH9_TASK_ID + Configures ch9_task_id + 0 + 8 + read-write + + + + + CH10_EVT_ID + Channel10 event id register + 0x68 + 0x20 + + + CH10_EVT_ID + Configures ch10_evt_id + 0 + 8 + read-write + + + + + CH10_TASK_ID + Channel10 task id register + 0x6C + 0x20 + + + CH10_TASK_ID + Configures ch10_task_id + 0 + 8 + read-write + + + + + CH11_EVT_ID + Channel11 event id register + 0x70 + 0x20 + + + CH11_EVT_ID + Configures ch11_evt_id + 0 + 8 + read-write + + + + + CH11_TASK_ID + Channel11 task id register + 0x74 + 0x20 + + + CH11_TASK_ID + Configures ch11_task_id + 0 + 8 + read-write + + + + + CH12_EVT_ID + Channel12 event id register + 0x78 + 0x20 + + + CH12_EVT_ID + Configures ch12_evt_id + 0 + 8 + read-write + + + + + CH12_TASK_ID + Channel12 task id register + 0x7C + 0x20 + + + CH12_TASK_ID + Configures ch12_task_id + 0 + 8 + read-write + + + + + CH13_EVT_ID + Channel13 event id register + 0x80 + 0x20 + + + CH13_EVT_ID + Configures ch13_evt_id + 0 + 8 + read-write + + + + + CH13_TASK_ID + Channel13 task id register + 0x84 + 0x20 + + + CH13_TASK_ID + Configures ch13_task_id + 0 + 8 + read-write + + + + + CH14_EVT_ID + Channel14 event id register + 0x88 + 0x20 + + + CH14_EVT_ID + Configures ch14_evt_id + 0 + 8 + read-write + + + + + CH14_TASK_ID + Channel14 task id register + 0x8C + 0x20 + + + CH14_TASK_ID + Configures ch14_task_id + 0 + 8 + read-write + + + + + CH15_EVT_ID + Channel15 event id register + 0x90 + 0x20 + + + CH15_EVT_ID + Configures ch15_evt_id + 0 + 8 + read-write + + + + + CH15_TASK_ID + Channel15 task id register + 0x94 + 0x20 + + + CH15_TASK_ID + Configures ch15_task_id + 0 + 8 + read-write + + + + + CH16_EVT_ID + Channel16 event id register + 0x98 + 0x20 + + + CH16_EVT_ID + Configures ch16_evt_id + 0 + 8 + read-write + + + + + CH16_TASK_ID + Channel16 task id register + 0x9C + 0x20 + + + CH16_TASK_ID + Configures ch16_task_id + 0 + 8 + read-write + + + + + CH17_EVT_ID + Channel17 event id register + 0xA0 + 0x20 + + + CH17_EVT_ID + Configures ch17_evt_id + 0 + 8 + read-write + + + + + CH17_TASK_ID + Channel17 task id register + 0xA4 + 0x20 + + + CH17_TASK_ID + Configures ch17_task_id + 0 + 8 + read-write + + + + + CH18_EVT_ID + Channel18 event id register + 0xA8 + 0x20 + + + CH18_EVT_ID + Configures ch18_evt_id + 0 + 8 + read-write + + + + + CH18_TASK_ID + Channel18 task id register + 0xAC + 0x20 + + + CH18_TASK_ID + Configures ch18_task_id + 0 + 8 + read-write + + + + + CH19_EVT_ID + Channel19 event id register + 0xB0 + 0x20 + + + CH19_EVT_ID + Configures ch19_evt_id + 0 + 8 + read-write + + + + + CH19_TASK_ID + Channel19 task id register + 0xB4 + 0x20 + + + CH19_TASK_ID + Configures ch19_task_id + 0 + 8 + read-write + + + + + CH20_EVT_ID + Channel20 event id register + 0xB8 + 0x20 + + + CH20_EVT_ID + Configures ch20_evt_id + 0 + 8 + read-write + + + + + CH20_TASK_ID + Channel20 task id register + 0xBC + 0x20 + + + CH20_TASK_ID + Configures ch20_task_id + 0 + 8 + read-write + + + + + CH21_EVT_ID + Channel21 event id register + 0xC0 + 0x20 + + + CH21_EVT_ID + Configures ch21_evt_id + 0 + 8 + read-write + + + + + CH21_TASK_ID + Channel21 task id register + 0xC4 + 0x20 + + + CH21_TASK_ID + Configures ch21_task_id + 0 + 8 + read-write + + + + + CH22_EVT_ID + Channel22 event id register + 0xC8 + 0x20 + + + CH22_EVT_ID + Configures ch22_evt_id + 0 + 8 + read-write + + + + + CH22_TASK_ID + Channel22 task id register + 0xCC + 0x20 + + + CH22_TASK_ID + Configures ch22_task_id + 0 + 8 + read-write + + + + + CH23_EVT_ID + Channel23 event id register + 0xD0 + 0x20 + + + CH23_EVT_ID + Configures ch23_evt_id + 0 + 8 + read-write + + + + + CH23_TASK_ID + Channel23 task id register + 0xD4 + 0x20 + + + CH23_TASK_ID + Configures ch23_task_id + 0 + 8 + read-write + + + + + CH24_EVT_ID + Channel24 event id register + 0xD8 + 0x20 + + + CH24_EVT_ID + Configures ch24_evt_id + 0 + 8 + read-write + + + + + CH24_TASK_ID + Channel24 task id register + 0xDC + 0x20 + + + CH24_TASK_ID + Configures ch24_task_id + 0 + 8 + read-write + + + + + CH25_EVT_ID + Channel25 event id register + 0xE0 + 0x20 + + + CH25_EVT_ID + Configures ch25_evt_id + 0 + 8 + read-write + + + + + CH25_TASK_ID + Channel25 task id register + 0xE4 + 0x20 + + + CH25_TASK_ID + Configures ch25_task_id + 0 + 8 + read-write + + + + + CH26_EVT_ID + Channel26 event id register + 0xE8 + 0x20 + + + CH26_EVT_ID + Configures ch26_evt_id + 0 + 8 + read-write + + + + + CH26_TASK_ID + Channel26 task id register + 0xEC + 0x20 + + + CH26_TASK_ID + Configures ch26_task_id + 0 + 8 + read-write + + + + + CH27_EVT_ID + Channel27 event id register + 0xF0 + 0x20 + + + CH27_EVT_ID + Configures ch27_evt_id + 0 + 8 + read-write + + + + + CH27_TASK_ID + Channel27 task id register + 0xF4 + 0x20 + + + CH27_TASK_ID + Configures ch27_task_id + 0 + 8 + read-write + + + + + CH28_EVT_ID + Channel28 event id register + 0xF8 + 0x20 + + + CH28_EVT_ID + Configures ch28_evt_id + 0 + 8 + read-write + + + + + CH28_TASK_ID + Channel28 task id register + 0xFC + 0x20 + + + CH28_TASK_ID + Configures ch28_task_id + 0 + 8 + read-write + + + + + CH29_EVT_ID + Channel29 event id register + 0x100 + 0x20 + + + CH29_EVT_ID + Configures ch29_evt_id + 0 + 8 + read-write + + + + + CH29_TASK_ID + Channel29 task id register + 0x104 + 0x20 + + + CH29_TASK_ID + Configures ch29_task_id + 0 + 8 + read-write + + + + + CH30_EVT_ID + Channel30 event id register + 0x108 + 0x20 + + + CH30_EVT_ID + Configures ch30_evt_id + 0 + 8 + read-write + + + + + CH30_TASK_ID + Channel30 task id register + 0x10C + 0x20 + + + CH30_TASK_ID + Configures ch30_task_id + 0 + 8 + read-write + + + + + CH31_EVT_ID + Channel31 event id register + 0x110 + 0x20 + + + CH31_EVT_ID + Configures ch31_evt_id + 0 + 8 + read-write + + + + + CH31_TASK_ID + Channel31 task id register + 0x114 + 0x20 + + + CH31_TASK_ID + Configures ch31_task_id + 0 + 8 + read-write + + + + + CH32_EVT_ID + Channel32 event id register + 0x118 + 0x20 + + + CH32_EVT_ID + Configures ch32_evt_id + 0 + 8 + read-write + + + + + CH32_TASK_ID + Channel32 task id register + 0x11C + 0x20 + + + CH32_TASK_ID + Configures ch32_task_id + 0 + 8 + read-write + + + + + CH33_EVT_ID + Channel33 event id register + 0x120 + 0x20 + + + CH33_EVT_ID + Configures ch33_evt_id + 0 + 8 + read-write + + + + + CH33_TASK_ID + Channel33 task id register + 0x124 + 0x20 + + + CH33_TASK_ID + Configures ch33_task_id + 0 + 8 + read-write + + + + + CH34_EVT_ID + Channel34 event id register + 0x128 + 0x20 + + + CH34_EVT_ID + Configures ch34_evt_id + 0 + 8 + read-write + + + + + CH34_TASK_ID + Channel34 task id register + 0x12C + 0x20 + + + CH34_TASK_ID + Configures ch34_task_id + 0 + 8 + read-write + + + + + CH35_EVT_ID + Channel35 event id register + 0x130 + 0x20 + + + CH35_EVT_ID + Configures ch35_evt_id + 0 + 8 + read-write + + + + + CH35_TASK_ID + Channel35 task id register + 0x134 + 0x20 + + + CH35_TASK_ID + Configures ch35_task_id + 0 + 8 + read-write + + + + + CH36_EVT_ID + Channel36 event id register + 0x138 + 0x20 + + + CH36_EVT_ID + Configures ch36_evt_id + 0 + 8 + read-write + + + + + CH36_TASK_ID + Channel36 task id register + 0x13C + 0x20 + + + CH36_TASK_ID + Configures ch36_task_id + 0 + 8 + read-write + + + + + CH37_EVT_ID + Channel37 event id register + 0x140 + 0x20 + + + CH37_EVT_ID + Configures ch37_evt_id + 0 + 8 + read-write + + + + + CH37_TASK_ID + Channel37 task id register + 0x144 + 0x20 + + + CH37_TASK_ID + Configures ch37_task_id + 0 + 8 + read-write + + + + + CH38_EVT_ID + Channel38 event id register + 0x148 + 0x20 + + + CH38_EVT_ID + Configures ch38_evt_id + 0 + 8 + read-write + + + + + CH38_TASK_ID + Channel38 task id register + 0x14C + 0x20 + + + CH38_TASK_ID + Configures ch38_task_id + 0 + 8 + read-write + + + + + CH39_EVT_ID + Channel39 event id register + 0x150 + 0x20 + + + CH39_EVT_ID + Configures ch39_evt_id + 0 + 8 + read-write + + + + + CH39_TASK_ID + Channel39 task id register + 0x154 + 0x20 + + + CH39_TASK_ID + Configures ch39_task_id + 0 + 8 + read-write + + + + + CH40_EVT_ID + Channel40 event id register + 0x158 + 0x20 + + + CH40_EVT_ID + Configures ch40_evt_id + 0 + 8 + read-write + + + + + CH40_TASK_ID + Channel40 task id register + 0x15C + 0x20 + + + CH40_TASK_ID + Configures ch40_task_id + 0 + 8 + read-write + + + + + CH41_EVT_ID + Channel41 event id register + 0x160 + 0x20 + + + CH41_EVT_ID + Configures ch41_evt_id + 0 + 8 + read-write + + + + + CH41_TASK_ID + Channel41 task id register + 0x164 + 0x20 + + + CH41_TASK_ID + Configures ch41_task_id + 0 + 8 + read-write + + + + + CH42_EVT_ID + Channel42 event id register + 0x168 + 0x20 + + + CH42_EVT_ID + Configures ch42_evt_id + 0 + 8 + read-write + + + + + CH42_TASK_ID + Channel42 task id register + 0x16C + 0x20 + + + CH42_TASK_ID + Configures ch42_task_id + 0 + 8 + read-write + + + + + CH43_EVT_ID + Channel43 event id register + 0x170 + 0x20 + + + CH43_EVT_ID + Configures ch43_evt_id + 0 + 8 + read-write + + + + + CH43_TASK_ID + Channel43 task id register + 0x174 + 0x20 + + + CH43_TASK_ID + Configures ch43_task_id + 0 + 8 + read-write + + + + + CH44_EVT_ID + Channel44 event id register + 0x178 + 0x20 + + + CH44_EVT_ID + Configures ch44_evt_id + 0 + 8 + read-write + + + + + CH44_TASK_ID + Channel44 task id register + 0x17C + 0x20 + + + CH44_TASK_ID + Configures ch44_task_id + 0 + 8 + read-write + + + + + CH45_EVT_ID + Channel45 event id register + 0x180 + 0x20 + + + CH45_EVT_ID + Configures ch45_evt_id + 0 + 8 + read-write + + + + + CH45_TASK_ID + Channel45 task id register + 0x184 + 0x20 + + + CH45_TASK_ID + Configures ch45_task_id + 0 + 8 + read-write + + + + + CH46_EVT_ID + Channel46 event id register + 0x188 + 0x20 + + + CH46_EVT_ID + Configures ch46_evt_id + 0 + 8 + read-write + + + + + CH46_TASK_ID + Channel46 task id register + 0x18C + 0x20 + + + CH46_TASK_ID + Configures ch46_task_id + 0 + 8 + read-write + + + + + CH47_EVT_ID + Channel47 event id register + 0x190 + 0x20 + + + CH47_EVT_ID + Configures ch47_evt_id + 0 + 8 + read-write + + + + + CH47_TASK_ID + Channel47 task id register + 0x194 + 0x20 + + + CH47_TASK_ID + Configures ch47_task_id + 0 + 8 + read-write + + + + + CH48_EVT_ID + Channel48 event id register + 0x198 + 0x20 + + + CH48_EVT_ID + Configures ch48_evt_id + 0 + 8 + read-write + + + + + CH48_TASK_ID + Channel48 task id register + 0x19C + 0x20 + + + CH48_TASK_ID + Configures ch48_task_id + 0 + 8 + read-write + + + + + CH49_EVT_ID + Channel49 event id register + 0x1A0 + 0x20 + + + CH49_EVT_ID + Configures ch49_evt_id + 0 + 8 + read-write + + + + + CH49_TASK_ID + Channel49 task id register + 0x1A4 + 0x20 + + + CH49_TASK_ID + Configures ch49_task_id + 0 + 8 + read-write + + + + + EVT_ST0 + Events trigger status register + 0x1A8 + 0x20 + + + GPIO_EVT_CH0_RISE_EDGE_ST + Represents GPIO_evt_ch0_rise_edge trigger status.\\0: Not triggered\\1: Triggered + 0 + 1 + read-write + + + GPIO_EVT_CH1_RISE_EDGE_ST + Represents GPIO_evt_ch1_rise_edge trigger status.\\0: Not triggered\\1: Triggered + 1 + 1 + read-write + + + GPIO_EVT_CH2_RISE_EDGE_ST + Represents GPIO_evt_ch2_rise_edge trigger status.\\0: Not triggered\\1: Triggered + 2 + 1 + read-write + + + GPIO_EVT_CH3_RISE_EDGE_ST + Represents GPIO_evt_ch3_rise_edge trigger status.\\0: Not triggered\\1: Triggered + 3 + 1 + read-write + + + GPIO_EVT_CH4_RISE_EDGE_ST + Represents GPIO_evt_ch4_rise_edge trigger status.\\0: Not triggered\\1: Triggered + 4 + 1 + read-write + + + GPIO_EVT_CH5_RISE_EDGE_ST + Represents GPIO_evt_ch5_rise_edge trigger status.\\0: Not triggered\\1: Triggered + 5 + 1 + read-write + + + GPIO_EVT_CH6_RISE_EDGE_ST + Represents GPIO_evt_ch6_rise_edge trigger status.\\0: Not triggered\\1: Triggered + 6 + 1 + read-write + + + GPIO_EVT_CH7_RISE_EDGE_ST + Represents GPIO_evt_ch7_rise_edge trigger status.\\0: Not triggered\\1: Triggered + 7 + 1 + read-write + + + GPIO_EVT_CH0_FALL_EDGE_ST + Represents GPIO_evt_ch0_fall_edge trigger status.\\0: Not triggered\\1: Triggered + 8 + 1 + read-write + + + GPIO_EVT_CH1_FALL_EDGE_ST + Represents GPIO_evt_ch1_fall_edge trigger status.\\0: Not triggered\\1: Triggered + 9 + 1 + read-write + + + GPIO_EVT_CH2_FALL_EDGE_ST + Represents GPIO_evt_ch2_fall_edge trigger status.\\0: Not triggered\\1: Triggered + 10 + 1 + read-write + + + GPIO_EVT_CH3_FALL_EDGE_ST + Represents GPIO_evt_ch3_fall_edge trigger status.\\0: Not triggered\\1: Triggered + 11 + 1 + read-write + + + GPIO_EVT_CH4_FALL_EDGE_ST + Represents GPIO_evt_ch4_fall_edge trigger status.\\0: Not triggered\\1: Triggered + 12 + 1 + read-write + + + GPIO_EVT_CH5_FALL_EDGE_ST + Represents GPIO_evt_ch5_fall_edge trigger status.\\0: Not triggered\\1: Triggered + 13 + 1 + read-write + + + GPIO_EVT_CH6_FALL_EDGE_ST + Represents GPIO_evt_ch6_fall_edge trigger status.\\0: Not triggered\\1: Triggered + 14 + 1 + read-write + + + GPIO_EVT_CH7_FALL_EDGE_ST + Represents GPIO_evt_ch7_fall_edge trigger status.\\0: Not triggered\\1: Triggered + 15 + 1 + read-write + + + GPIO_EVT_CH0_ANY_EDGE_ST + Represents GPIO_evt_ch0_any_edge trigger status.\\0: Not triggered\\1: Triggered + 16 + 1 + read-write + + + GPIO_EVT_CH1_ANY_EDGE_ST + Represents GPIO_evt_ch1_any_edge trigger status.\\0: Not triggered\\1: Triggered + 17 + 1 + read-write + + + GPIO_EVT_CH2_ANY_EDGE_ST + Represents GPIO_evt_ch2_any_edge trigger status.\\0: Not triggered\\1: Triggered + 18 + 1 + read-write + + + GPIO_EVT_CH3_ANY_EDGE_ST + Represents GPIO_evt_ch3_any_edge trigger status.\\0: Not triggered\\1: Triggered + 19 + 1 + read-write + + + GPIO_EVT_CH4_ANY_EDGE_ST + Represents GPIO_evt_ch4_any_edge trigger status.\\0: Not triggered\\1: Triggered + 20 + 1 + read-write + + + GPIO_EVT_CH5_ANY_EDGE_ST + Represents GPIO_evt_ch5_any_edge trigger status.\\0: Not triggered\\1: Triggered + 21 + 1 + read-write + + + GPIO_EVT_CH6_ANY_EDGE_ST + Represents GPIO_evt_ch6_any_edge trigger status.\\0: Not triggered\\1: Triggered + 22 + 1 + read-write + + + GPIO_EVT_CH7_ANY_EDGE_ST + Represents GPIO_evt_ch7_any_edge trigger status.\\0: Not triggered\\1: Triggered + 23 + 1 + read-write + + + GPIO_EVT_ZERO_DET_POS0_ST + Represents GPIO_evt_zero_det_pos0 trigger status.\\0: Not triggered\\1: Triggered + 24 + 1 + read-write + + + GPIO_EVT_ZERO_DET_NEG0_ST + Represents GPIO_evt_zero_det_neg0 trigger status.\\0: Not triggered\\1: Triggered + 25 + 1 + read-write + + + GPIO_EVT_ZERO_DET_POS1_ST + Represents GPIO_evt_zero_det_pos1 trigger status.\\0: Not triggered\\1: Triggered + 26 + 1 + read-write + + + GPIO_EVT_ZERO_DET_NEG1_ST + Represents GPIO_evt_zero_det_neg1 trigger status.\\0: Not triggered\\1: Triggered + 27 + 1 + read-write + + + LEDC_EVT_DUTY_CHNG_END_CH0_ST + Represents LEDC_evt_duty_chng_end_ch0 trigger status.\\0: Not triggered\\1: Triggered + 28 + 1 + read-write + + + LEDC_EVT_DUTY_CHNG_END_CH1_ST + Represents LEDC_evt_duty_chng_end_ch1 trigger status.\\0: Not triggered\\1: Triggered + 29 + 1 + read-write + + + LEDC_EVT_DUTY_CHNG_END_CH2_ST + Represents LEDC_evt_duty_chng_end_ch2 trigger status.\\0: Not triggered\\1: Triggered + 30 + 1 + read-write + + + LEDC_EVT_DUTY_CHNG_END_CH3_ST + Represents LEDC_evt_duty_chng_end_ch3 trigger status.\\0: Not triggered\\1: Triggered + 31 + 1 + read-write + + + + + EVT_ST0_CLR + Events trigger status clear register + 0x1AC + 0x20 + + + GPIO_EVT_CH0_RISE_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch0_rise_edge trigger status.\\0: Invalid, No effect\\1: Clear + 0 + 1 + write-only + + + GPIO_EVT_CH1_RISE_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch1_rise_edge trigger status.\\0: Invalid, No effect\\1: Clear + 1 + 1 + write-only + + + GPIO_EVT_CH2_RISE_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch2_rise_edge trigger status.\\0: Invalid, No effect\\1: Clear + 2 + 1 + write-only + + + GPIO_EVT_CH3_RISE_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch3_rise_edge trigger status.\\0: Invalid, No effect\\1: Clear + 3 + 1 + write-only + + + GPIO_EVT_CH4_RISE_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch4_rise_edge trigger status.\\0: Invalid, No effect\\1: Clear + 4 + 1 + write-only + + + GPIO_EVT_CH5_RISE_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch5_rise_edge trigger status.\\0: Invalid, No effect\\1: Clear + 5 + 1 + write-only + + + GPIO_EVT_CH6_RISE_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch6_rise_edge trigger status.\\0: Invalid, No effect\\1: Clear + 6 + 1 + write-only + + + GPIO_EVT_CH7_RISE_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch7_rise_edge trigger status.\\0: Invalid, No effect\\1: Clear + 7 + 1 + write-only + + + GPIO_EVT_CH0_FALL_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch0_fall_edge trigger status.\\0: Invalid, No effect\\1: Clear + 8 + 1 + write-only + + + GPIO_EVT_CH1_FALL_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch1_fall_edge trigger status.\\0: Invalid, No effect\\1: Clear + 9 + 1 + write-only + + + GPIO_EVT_CH2_FALL_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch2_fall_edge trigger status.\\0: Invalid, No effect\\1: Clear + 10 + 1 + write-only + + + GPIO_EVT_CH3_FALL_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch3_fall_edge trigger status.\\0: Invalid, No effect\\1: Clear + 11 + 1 + write-only + + + GPIO_EVT_CH4_FALL_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch4_fall_edge trigger status.\\0: Invalid, No effect\\1: Clear + 12 + 1 + write-only + + + GPIO_EVT_CH5_FALL_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch5_fall_edge trigger status.\\0: Invalid, No effect\\1: Clear + 13 + 1 + write-only + + + GPIO_EVT_CH6_FALL_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch6_fall_edge trigger status.\\0: Invalid, No effect\\1: Clear + 14 + 1 + write-only + + + GPIO_EVT_CH7_FALL_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch7_fall_edge trigger status.\\0: Invalid, No effect\\1: Clear + 15 + 1 + write-only + + + GPIO_EVT_CH0_ANY_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch0_any_edge trigger status.\\0: Invalid, No effect\\1: Clear + 16 + 1 + write-only + + + GPIO_EVT_CH1_ANY_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch1_any_edge trigger status.\\0: Invalid, No effect\\1: Clear + 17 + 1 + write-only + + + GPIO_EVT_CH2_ANY_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch2_any_edge trigger status.\\0: Invalid, No effect\\1: Clear + 18 + 1 + write-only + + + GPIO_EVT_CH3_ANY_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch3_any_edge trigger status.\\0: Invalid, No effect\\1: Clear + 19 + 1 + write-only + + + GPIO_EVT_CH4_ANY_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch4_any_edge trigger status.\\0: Invalid, No effect\\1: Clear + 20 + 1 + write-only + + + GPIO_EVT_CH5_ANY_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch5_any_edge trigger status.\\0: Invalid, No effect\\1: Clear + 21 + 1 + write-only + + + GPIO_EVT_CH6_ANY_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch6_any_edge trigger status.\\0: Invalid, No effect\\1: Clear + 22 + 1 + write-only + + + GPIO_EVT_CH7_ANY_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch7_any_edge trigger status.\\0: Invalid, No effect\\1: Clear + 23 + 1 + write-only + + + GPIO_EVT_ZERO_DET_POS0_ST_CLR + Configures whether or not to clear GPIO_evt_zero_det_pos0 trigger status.\\0: Invalid, No effect\\1: Clear + 24 + 1 + write-only + + + GPIO_EVT_ZERO_DET_NEG0_ST_CLR + Configures whether or not to clear GPIO_evt_zero_det_neg0 trigger status.\\0: Invalid, No effect\\1: Clear + 25 + 1 + write-only + + + GPIO_EVT_ZERO_DET_POS1_ST_CLR + Configures whether or not to clear GPIO_evt_zero_det_pos1 trigger status.\\0: Invalid, No effect\\1: Clear + 26 + 1 + write-only + + + GPIO_EVT_ZERO_DET_NEG1_ST_CLR + Configures whether or not to clear GPIO_evt_zero_det_neg1 trigger status.\\0: Invalid, No effect\\1: Clear + 27 + 1 + write-only + + + LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR + Configures whether or not to clear LEDC_evt_duty_chng_end_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 28 + 1 + write-only + + + LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR + Configures whether or not to clear LEDC_evt_duty_chng_end_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 29 + 1 + write-only + + + LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR + Configures whether or not to clear LEDC_evt_duty_chng_end_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 30 + 1 + write-only + + + LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR + Configures whether or not to clear LEDC_evt_duty_chng_end_ch3 trigger status.\\0: Invalid, No effect\\1: Clear + 31 + 1 + write-only + + + + + EVT_ST1 + Events trigger status register + 0x1B0 + 0x20 + + + LEDC_EVT_DUTY_CHNG_END_CH4_ST + Represents LEDC_evt_duty_chng_end_ch4 trigger status.\\0: Not triggered\\1: Triggered + 0 + 1 + read-write + + + LEDC_EVT_DUTY_CHNG_END_CH5_ST + Represents LEDC_evt_duty_chng_end_ch5 trigger status.\\0: Not triggered\\1: Triggered + 1 + 1 + read-write + + + LEDC_EVT_DUTY_CHNG_END_CH6_ST + Represents LEDC_evt_duty_chng_end_ch6 trigger status.\\0: Not triggered\\1: Triggered + 2 + 1 + read-write + + + LEDC_EVT_DUTY_CHNG_END_CH7_ST + Represents LEDC_evt_duty_chng_end_ch7 trigger status.\\0: Not triggered\\1: Triggered + 3 + 1 + read-write + + + LEDC_EVT_OVF_CNT_PLS_CH0_ST + Represents LEDC_evt_ovf_cnt_pls_ch0 trigger status.\\0: Not triggered\\1: Triggered + 4 + 1 + read-write + + + LEDC_EVT_OVF_CNT_PLS_CH1_ST + Represents LEDC_evt_ovf_cnt_pls_ch1 trigger status.\\0: Not triggered\\1: Triggered + 5 + 1 + read-write + + + LEDC_EVT_OVF_CNT_PLS_CH2_ST + Represents LEDC_evt_ovf_cnt_pls_ch2 trigger status.\\0: Not triggered\\1: Triggered + 6 + 1 + read-write + + + LEDC_EVT_OVF_CNT_PLS_CH3_ST + Represents LEDC_evt_ovf_cnt_pls_ch3 trigger status.\\0: Not triggered\\1: Triggered + 7 + 1 + read-write + + + LEDC_EVT_OVF_CNT_PLS_CH4_ST + Represents LEDC_evt_ovf_cnt_pls_ch4 trigger status.\\0: Not triggered\\1: Triggered + 8 + 1 + read-write + + + LEDC_EVT_OVF_CNT_PLS_CH5_ST + Represents LEDC_evt_ovf_cnt_pls_ch5 trigger status.\\0: Not triggered\\1: Triggered + 9 + 1 + read-write + + + LEDC_EVT_OVF_CNT_PLS_CH6_ST + Represents LEDC_evt_ovf_cnt_pls_ch6 trigger status.\\0: Not triggered\\1: Triggered + 10 + 1 + read-write + + + LEDC_EVT_OVF_CNT_PLS_CH7_ST + Represents LEDC_evt_ovf_cnt_pls_ch7 trigger status.\\0: Not triggered\\1: Triggered + 11 + 1 + read-write + + + LEDC_EVT_TIME_OVF_TIMER0_ST + Represents LEDC_evt_time_ovf_timer0 trigger status.\\0: Not triggered\\1: Triggered + 12 + 1 + read-write + + + LEDC_EVT_TIME_OVF_TIMER1_ST + Represents LEDC_evt_time_ovf_timer1 trigger status.\\0: Not triggered\\1: Triggered + 13 + 1 + read-write + + + LEDC_EVT_TIME_OVF_TIMER2_ST + Represents LEDC_evt_time_ovf_timer2 trigger status.\\0: Not triggered\\1: Triggered + 14 + 1 + read-write + + + LEDC_EVT_TIME_OVF_TIMER3_ST + Represents LEDC_evt_time_ovf_timer3 trigger status.\\0: Not triggered\\1: Triggered + 15 + 1 + read-write + + + LEDC_EVT_TIMER0_CMP_ST + Represents LEDC_evt_timer0_cmp trigger status.\\0: Not triggered\\1: Triggered + 16 + 1 + read-write + + + LEDC_EVT_TIMER1_CMP_ST + Represents LEDC_evt_timer1_cmp trigger status.\\0: Not triggered\\1: Triggered + 17 + 1 + read-write + + + LEDC_EVT_TIMER2_CMP_ST + Represents LEDC_evt_timer2_cmp trigger status.\\0: Not triggered\\1: Triggered + 18 + 1 + read-write + + + LEDC_EVT_TIMER3_CMP_ST + Represents LEDC_evt_timer3_cmp trigger status.\\0: Not triggered\\1: Triggered + 19 + 1 + read-write + + + TG0_EVT_CNT_CMP_TIMER0_ST + Represents TG0_evt_cnt_cmp_timer0 trigger status.\\0: Not triggered\\1: Triggered + 20 + 1 + read-write + + + TG0_EVT_CNT_CMP_TIMER1_ST + Represents TG0_evt_cnt_cmp_timer1 trigger status.\\0: Not triggered\\1: Triggered + 21 + 1 + read-write + + + TG1_EVT_CNT_CMP_TIMER0_ST + Represents TG1_evt_cnt_cmp_timer0 trigger status.\\0: Not triggered\\1: Triggered + 22 + 1 + read-write + + + TG1_EVT_CNT_CMP_TIMER1_ST + Represents TG1_evt_cnt_cmp_timer1 trigger status.\\0: Not triggered\\1: Triggered + 23 + 1 + read-write + + + SYSTIMER_EVT_CNT_CMP0_ST + Represents SYSTIMER_evt_cnt_cmp0 trigger status.\\0: Not triggered\\1: Triggered + 24 + 1 + read-write + + + SYSTIMER_EVT_CNT_CMP1_ST + Represents SYSTIMER_evt_cnt_cmp1 trigger status.\\0: Not triggered\\1: Triggered + 25 + 1 + read-write + + + SYSTIMER_EVT_CNT_CMP2_ST + Represents SYSTIMER_evt_cnt_cmp2 trigger status.\\0: Not triggered\\1: Triggered + 26 + 1 + read-write + + + MCPWM0_EVT_TIMER0_STOP_ST + Represents MCPWM0_evt_timer0_stop trigger status.\\0: Not triggered\\1: Triggered + 27 + 1 + read-write + + + MCPWM0_EVT_TIMER1_STOP_ST + Represents MCPWM0_evt_timer1_stop trigger status.\\0: Not triggered\\1: Triggered + 28 + 1 + read-write + + + MCPWM0_EVT_TIMER2_STOP_ST + Represents MCPWM0_evt_timer2_stop trigger status.\\0: Not triggered\\1: Triggered + 29 + 1 + read-write + + + MCPWM0_EVT_TIMER0_TEZ_ST + Represents MCPWM0_evt_timer0_tez trigger status.\\0: Not triggered\\1: Triggered + 30 + 1 + read-write + + + MCPWM0_EVT_TIMER1_TEZ_ST + Represents MCPWM0_evt_timer1_tez trigger status.\\0: Not triggered\\1: Triggered + 31 + 1 + read-write + + + + + EVT_ST1_CLR + Events trigger status clear register + 0x1B4 + 0x20 + + + LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR + Configures whether or not to clear LEDC_evt_duty_chng_end_ch4 trigger status.\\0: Invalid, No effect\\1: Clear + 0 + 1 + write-only + + + LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR + Configures whether or not to clear LEDC_evt_duty_chng_end_ch5 trigger status.\\0: Invalid, No effect\\1: Clear + 1 + 1 + write-only + + + LEDC_EVT_DUTY_CHNG_END_CH6_ST_CLR + Configures whether or not to clear LEDC_evt_duty_chng_end_ch6 trigger status.\\0: Invalid, No effect\\1: Clear + 2 + 1 + write-only + + + LEDC_EVT_DUTY_CHNG_END_CH7_ST_CLR + Configures whether or not to clear LEDC_evt_duty_chng_end_ch7 trigger status.\\0: Invalid, No effect\\1: Clear + 3 + 1 + write-only + + + LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR + Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 4 + 1 + write-only + + + LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR + Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 5 + 1 + write-only + + + LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR + Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 6 + 1 + write-only + + + LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR + Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch3 trigger status.\\0: Invalid, No effect\\1: Clear + 7 + 1 + write-only + + + LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR + Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch4 trigger status.\\0: Invalid, No effect\\1: Clear + 8 + 1 + write-only + + + LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR + Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch5 trigger status.\\0: Invalid, No effect\\1: Clear + 9 + 1 + write-only + + + LEDC_EVT_OVF_CNT_PLS_CH6_ST_CLR + Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch6 trigger status.\\0: Invalid, No effect\\1: Clear + 10 + 1 + write-only + + + LEDC_EVT_OVF_CNT_PLS_CH7_ST_CLR + Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch7 trigger status.\\0: Invalid, No effect\\1: Clear + 11 + 1 + write-only + + + LEDC_EVT_TIME_OVF_TIMER0_ST_CLR + Configures whether or not to clear LEDC_evt_time_ovf_timer0 trigger status.\\0: Invalid, No effect\\1: Clear + 12 + 1 + write-only + + + LEDC_EVT_TIME_OVF_TIMER1_ST_CLR + Configures whether or not to clear LEDC_evt_time_ovf_timer1 trigger status.\\0: Invalid, No effect\\1: Clear + 13 + 1 + write-only + + + LEDC_EVT_TIME_OVF_TIMER2_ST_CLR + Configures whether or not to clear LEDC_evt_time_ovf_timer2 trigger status.\\0: Invalid, No effect\\1: Clear + 14 + 1 + write-only + + + LEDC_EVT_TIME_OVF_TIMER3_ST_CLR + Configures whether or not to clear LEDC_evt_time_ovf_timer3 trigger status.\\0: Invalid, No effect\\1: Clear + 15 + 1 + write-only + + + LEDC_EVT_TIMER0_CMP_ST_CLR + Configures whether or not to clear LEDC_evt_timer0_cmp trigger status.\\0: Invalid, No effect\\1: Clear + 16 + 1 + write-only + + + LEDC_EVT_TIMER1_CMP_ST_CLR + Configures whether or not to clear LEDC_evt_timer1_cmp trigger status.\\0: Invalid, No effect\\1: Clear + 17 + 1 + write-only + + + LEDC_EVT_TIMER2_CMP_ST_CLR + Configures whether or not to clear LEDC_evt_timer2_cmp trigger status.\\0: Invalid, No effect\\1: Clear + 18 + 1 + write-only + + + LEDC_EVT_TIMER3_CMP_ST_CLR + Configures whether or not to clear LEDC_evt_timer3_cmp trigger status.\\0: Invalid, No effect\\1: Clear + 19 + 1 + write-only + + + TG0_EVT_CNT_CMP_TIMER0_ST_CLR + Configures whether or not to clear TG0_evt_cnt_cmp_timer0 trigger status.\\0: Invalid, No effect\\1: Clear + 20 + 1 + write-only + + + TG0_EVT_CNT_CMP_TIMER1_ST_CLR + Configures whether or not to clear TG0_evt_cnt_cmp_timer1 trigger status.\\0: Invalid, No effect\\1: Clear + 21 + 1 + write-only + + + TG1_EVT_CNT_CMP_TIMER0_ST_CLR + Configures whether or not to clear TG1_evt_cnt_cmp_timer0 trigger status.\\0: Invalid, No effect\\1: Clear + 22 + 1 + write-only + + + TG1_EVT_CNT_CMP_TIMER1_ST_CLR + Configures whether or not to clear TG1_evt_cnt_cmp_timer1 trigger status.\\0: Invalid, No effect\\1: Clear + 23 + 1 + write-only + + + SYSTIMER_EVT_CNT_CMP0_ST_CLR + Configures whether or not to clear SYSTIMER_evt_cnt_cmp0 trigger status.\\0: Invalid, No effect\\1: Clear + 24 + 1 + write-only + + + SYSTIMER_EVT_CNT_CMP1_ST_CLR + Configures whether or not to clear SYSTIMER_evt_cnt_cmp1 trigger status.\\0: Invalid, No effect\\1: Clear + 25 + 1 + write-only + + + SYSTIMER_EVT_CNT_CMP2_ST_CLR + Configures whether or not to clear SYSTIMER_evt_cnt_cmp2 trigger status.\\0: Invalid, No effect\\1: Clear + 26 + 1 + write-only + + + MCPWM0_EVT_TIMER0_STOP_ST_CLR + Configures whether or not to clear MCPWM0_evt_timer0_stop trigger status.\\0: Invalid, No effect\\1: Clear + 27 + 1 + write-only + + + MCPWM0_EVT_TIMER1_STOP_ST_CLR + Configures whether or not to clear MCPWM0_evt_timer1_stop trigger status.\\0: Invalid, No effect\\1: Clear + 28 + 1 + write-only + + + MCPWM0_EVT_TIMER2_STOP_ST_CLR + Configures whether or not to clear MCPWM0_evt_timer2_stop trigger status.\\0: Invalid, No effect\\1: Clear + 29 + 1 + write-only + + + MCPWM0_EVT_TIMER0_TEZ_ST_CLR + Configures whether or not to clear MCPWM0_evt_timer0_tez trigger status.\\0: Invalid, No effect\\1: Clear + 30 + 1 + write-only + + + MCPWM0_EVT_TIMER1_TEZ_ST_CLR + Configures whether or not to clear MCPWM0_evt_timer1_tez trigger status.\\0: Invalid, No effect\\1: Clear + 31 + 1 + write-only + + + + + EVT_ST2 + Events trigger status register + 0x1B8 + 0x20 + + + MCPWM0_EVT_TIMER2_TEZ_ST + Represents MCPWM0_evt_timer2_tez trigger status.\\0: Not triggered\\1: Triggered + 0 + 1 + read-write + + + MCPWM0_EVT_TIMER0_TEP_ST + Represents MCPWM0_evt_timer0_tep trigger status.\\0: Not triggered\\1: Triggered + 1 + 1 + read-write + + + MCPWM0_EVT_TIMER1_TEP_ST + Represents MCPWM0_evt_timer1_tep trigger status.\\0: Not triggered\\1: Triggered + 2 + 1 + read-write + + + MCPWM0_EVT_TIMER2_TEP_ST + Represents MCPWM0_evt_timer2_tep trigger status.\\0: Not triggered\\1: Triggered + 3 + 1 + read-write + + + MCPWM0_EVT_OP0_TEA_ST + Represents MCPWM0_evt_op0_tea trigger status.\\0: Not triggered\\1: Triggered + 4 + 1 + read-write + + + MCPWM0_EVT_OP1_TEA_ST + Represents MCPWM0_evt_op1_tea trigger status.\\0: Not triggered\\1: Triggered + 5 + 1 + read-write + + + MCPWM0_EVT_OP2_TEA_ST + Represents MCPWM0_evt_op2_tea trigger status.\\0: Not triggered\\1: Triggered + 6 + 1 + read-write + + + MCPWM0_EVT_OP0_TEB_ST + Represents MCPWM0_evt_op0_teb trigger status.\\0: Not triggered\\1: Triggered + 7 + 1 + read-write + + + MCPWM0_EVT_OP1_TEB_ST + Represents MCPWM0_evt_op1_teb trigger status.\\0: Not triggered\\1: Triggered + 8 + 1 + read-write + + + MCPWM0_EVT_OP2_TEB_ST + Represents MCPWM0_evt_op2_teb trigger status.\\0: Not triggered\\1: Triggered + 9 + 1 + read-write + + + MCPWM0_EVT_F0_ST + Represents MCPWM0_evt_f0 trigger status.\\0: Not triggered\\1: Triggered + 10 + 1 + read-write + + + MCPWM0_EVT_F1_ST + Represents MCPWM0_evt_f1 trigger status.\\0: Not triggered\\1: Triggered + 11 + 1 + read-write + + + MCPWM0_EVT_F2_ST + Represents MCPWM0_evt_f2 trigger status.\\0: Not triggered\\1: Triggered + 12 + 1 + read-write + + + MCPWM0_EVT_F0_CLR_ST + Represents MCPWM0_evt_f0_clr trigger status.\\0: Not triggered\\1: Triggered + 13 + 1 + read-write + + + MCPWM0_EVT_F1_CLR_ST + Represents MCPWM0_evt_f1_clr trigger status.\\0: Not triggered\\1: Triggered + 14 + 1 + read-write + + + MCPWM0_EVT_F2_CLR_ST + Represents MCPWM0_evt_f2_clr trigger status.\\0: Not triggered\\1: Triggered + 15 + 1 + read-write + + + MCPWM0_EVT_TZ0_CBC_ST + Represents MCPWM0_evt_tz0_cbc trigger status.\\0: Not triggered\\1: Triggered + 16 + 1 + read-write + + + MCPWM0_EVT_TZ1_CBC_ST + Represents MCPWM0_evt_tz1_cbc trigger status.\\0: Not triggered\\1: Triggered + 17 + 1 + read-write + + + MCPWM0_EVT_TZ2_CBC_ST + Represents MCPWM0_evt_tz2_cbc trigger status.\\0: Not triggered\\1: Triggered + 18 + 1 + read-write + + + MCPWM0_EVT_TZ0_OST_ST + Represents MCPWM0_evt_tz0_ost trigger status.\\0: Not triggered\\1: Triggered + 19 + 1 + read-write + + + MCPWM0_EVT_TZ1_OST_ST + Represents MCPWM0_evt_tz1_ost trigger status.\\0: Not triggered\\1: Triggered + 20 + 1 + read-write + + + MCPWM0_EVT_TZ2_OST_ST + Represents MCPWM0_evt_tz2_ost trigger status.\\0: Not triggered\\1: Triggered + 21 + 1 + read-write + + + MCPWM0_EVT_CAP0_ST + Represents MCPWM0_evt_cap0 trigger status.\\0: Not triggered\\1: Triggered + 22 + 1 + read-write + + + MCPWM0_EVT_CAP1_ST + Represents MCPWM0_evt_cap1 trigger status.\\0: Not triggered\\1: Triggered + 23 + 1 + read-write + + + MCPWM0_EVT_CAP2_ST + Represents MCPWM0_evt_cap2 trigger status.\\0: Not triggered\\1: Triggered + 24 + 1 + read-write + + + MCPWM0_EVT_OP0_TEE1_ST + Represents MCPWM0_evt_op0_tee1 trigger status.\\0: Not triggered\\1: Triggered + 25 + 1 + read-write + + + MCPWM0_EVT_OP1_TEE1_ST + Represents MCPWM0_evt_op1_tee1 trigger status.\\0: Not triggered\\1: Triggered + 26 + 1 + read-write + + + MCPWM0_EVT_OP2_TEE1_ST + Represents MCPWM0_evt_op2_tee1 trigger status.\\0: Not triggered\\1: Triggered + 27 + 1 + read-write + + + MCPWM0_EVT_OP0_TEE2_ST + Represents MCPWM0_evt_op0_tee2 trigger status.\\0: Not triggered\\1: Triggered + 28 + 1 + read-write + + + MCPWM0_EVT_OP1_TEE2_ST + Represents MCPWM0_evt_op1_tee2 trigger status.\\0: Not triggered\\1: Triggered + 29 + 1 + read-write + + + MCPWM0_EVT_OP2_TEE2_ST + Represents MCPWM0_evt_op2_tee2 trigger status.\\0: Not triggered\\1: Triggered + 30 + 1 + read-write + + + MCPWM1_EVT_TIMER0_STOP_ST + Represents MCPWM1_evt_timer0_stop trigger status.\\0: Not triggered\\1: Triggered + 31 + 1 + read-write + + + + + EVT_ST2_CLR + Events trigger status clear register + 0x1BC + 0x20 + + + MCPWM0_EVT_TIMER2_TEZ_ST_CLR + Configures whether or not to clear MCPWM0_evt_timer2_tez trigger status.\\0: Invalid, No effect\\1: Clear + 0 + 1 + write-only + + + MCPWM0_EVT_TIMER0_TEP_ST_CLR + Configures whether or not to clear MCPWM0_evt_timer0_tep trigger status.\\0: Invalid, No effect\\1: Clear + 1 + 1 + write-only + + + MCPWM0_EVT_TIMER1_TEP_ST_CLR + Configures whether or not to clear MCPWM0_evt_timer1_tep trigger status.\\0: Invalid, No effect\\1: Clear + 2 + 1 + write-only + + + MCPWM0_EVT_TIMER2_TEP_ST_CLR + Configures whether or not to clear MCPWM0_evt_timer2_tep trigger status.\\0: Invalid, No effect\\1: Clear + 3 + 1 + write-only + + + MCPWM0_EVT_OP0_TEA_ST_CLR + Configures whether or not to clear MCPWM0_evt_op0_tea trigger status.\\0: Invalid, No effect\\1: Clear + 4 + 1 + write-only + + + MCPWM0_EVT_OP1_TEA_ST_CLR + Configures whether or not to clear MCPWM0_evt_op1_tea trigger status.\\0: Invalid, No effect\\1: Clear + 5 + 1 + write-only + + + MCPWM0_EVT_OP2_TEA_ST_CLR + Configures whether or not to clear MCPWM0_evt_op2_tea trigger status.\\0: Invalid, No effect\\1: Clear + 6 + 1 + write-only + + + MCPWM0_EVT_OP0_TEB_ST_CLR + Configures whether or not to clear MCPWM0_evt_op0_teb trigger status.\\0: Invalid, No effect\\1: Clear + 7 + 1 + write-only + + + MCPWM0_EVT_OP1_TEB_ST_CLR + Configures whether or not to clear MCPWM0_evt_op1_teb trigger status.\\0: Invalid, No effect\\1: Clear + 8 + 1 + write-only + + + MCPWM0_EVT_OP2_TEB_ST_CLR + Configures whether or not to clear MCPWM0_evt_op2_teb trigger status.\\0: Invalid, No effect\\1: Clear + 9 + 1 + write-only + + + MCPWM0_EVT_F0_ST_CLR + Configures whether or not to clear MCPWM0_evt_f0 trigger status.\\0: Invalid, No effect\\1: Clear + 10 + 1 + write-only + + + MCPWM0_EVT_F1_ST_CLR + Configures whether or not to clear MCPWM0_evt_f1 trigger status.\\0: Invalid, No effect\\1: Clear + 11 + 1 + write-only + + + MCPWM0_EVT_F2_ST_CLR + Configures whether or not to clear MCPWM0_evt_f2 trigger status.\\0: Invalid, No effect\\1: Clear + 12 + 1 + write-only + + + MCPWM0_EVT_F0_CLR_ST_CLR + Configures whether or not to clear MCPWM0_evt_f0_clr trigger status.\\0: Invalid, No effect\\1: Clear + 13 + 1 + write-only + + + MCPWM0_EVT_F1_CLR_ST_CLR + Configures whether or not to clear MCPWM0_evt_f1_clr trigger status.\\0: Invalid, No effect\\1: Clear + 14 + 1 + write-only + + + MCPWM0_EVT_F2_CLR_ST_CLR + Configures whether or not to clear MCPWM0_evt_f2_clr trigger status.\\0: Invalid, No effect\\1: Clear + 15 + 1 + write-only + + + MCPWM0_EVT_TZ0_CBC_ST_CLR + Configures whether or not to clear MCPWM0_evt_tz0_cbc trigger status.\\0: Invalid, No effect\\1: Clear + 16 + 1 + write-only + + + MCPWM0_EVT_TZ1_CBC_ST_CLR + Configures whether or not to clear MCPWM0_evt_tz1_cbc trigger status.\\0: Invalid, No effect\\1: Clear + 17 + 1 + write-only + + + MCPWM0_EVT_TZ2_CBC_ST_CLR + Configures whether or not to clear MCPWM0_evt_tz2_cbc trigger status.\\0: Invalid, No effect\\1: Clear + 18 + 1 + write-only + + + MCPWM0_EVT_TZ0_OST_ST_CLR + Configures whether or not to clear MCPWM0_evt_tz0_ost trigger status.\\0: Invalid, No effect\\1: Clear + 19 + 1 + write-only + + + MCPWM0_EVT_TZ1_OST_ST_CLR + Configures whether or not to clear MCPWM0_evt_tz1_ost trigger status.\\0: Invalid, No effect\\1: Clear + 20 + 1 + write-only + + + MCPWM0_EVT_TZ2_OST_ST_CLR + Configures whether or not to clear MCPWM0_evt_tz2_ost trigger status.\\0: Invalid, No effect\\1: Clear + 21 + 1 + write-only + + + MCPWM0_EVT_CAP0_ST_CLR + Configures whether or not to clear MCPWM0_evt_cap0 trigger status.\\0: Invalid, No effect\\1: Clear + 22 + 1 + write-only + + + MCPWM0_EVT_CAP1_ST_CLR + Configures whether or not to clear MCPWM0_evt_cap1 trigger status.\\0: Invalid, No effect\\1: Clear + 23 + 1 + write-only + + + MCPWM0_EVT_CAP2_ST_CLR + Configures whether or not to clear MCPWM0_evt_cap2 trigger status.\\0: Invalid, No effect\\1: Clear + 24 + 1 + write-only + + + MCPWM0_EVT_OP0_TEE1_ST_CLR + Configures whether or not to clear MCPWM0_evt_op0_tee1 trigger status.\\0: Invalid, No effect\\1: Clear + 25 + 1 + write-only + + + MCPWM0_EVT_OP1_TEE1_ST_CLR + Configures whether or not to clear MCPWM0_evt_op1_tee1 trigger status.\\0: Invalid, No effect\\1: Clear + 26 + 1 + write-only + + + MCPWM0_EVT_OP2_TEE1_ST_CLR + Configures whether or not to clear MCPWM0_evt_op2_tee1 trigger status.\\0: Invalid, No effect\\1: Clear + 27 + 1 + write-only + + + MCPWM0_EVT_OP0_TEE2_ST_CLR + Configures whether or not to clear MCPWM0_evt_op0_tee2 trigger status.\\0: Invalid, No effect\\1: Clear + 28 + 1 + write-only + + + MCPWM0_EVT_OP1_TEE2_ST_CLR + Configures whether or not to clear MCPWM0_evt_op1_tee2 trigger status.\\0: Invalid, No effect\\1: Clear + 29 + 1 + write-only + + + MCPWM0_EVT_OP2_TEE2_ST_CLR + Configures whether or not to clear MCPWM0_evt_op2_tee2 trigger status.\\0: Invalid, No effect\\1: Clear + 30 + 1 + write-only + + + MCPWM1_EVT_TIMER0_STOP_ST_CLR + Configures whether or not to clear MCPWM1_evt_timer0_stop trigger status.\\0: Invalid, No effect\\1: Clear + 31 + 1 + write-only + + + + + EVT_ST3 + Events trigger status register + 0x1C0 + 0x20 + + + MCPWM1_EVT_TIMER1_STOP_ST + Represents MCPWM1_evt_timer1_stop trigger status.\\0: Not triggered\\1: Triggered + 0 + 1 + read-write + + + MCPWM1_EVT_TIMER2_STOP_ST + Represents MCPWM1_evt_timer2_stop trigger status.\\0: Not triggered\\1: Triggered + 1 + 1 + read-write + + + MCPWM1_EVT_TIMER0_TEZ_ST + Represents MCPWM1_evt_timer0_tez trigger status.\\0: Not triggered\\1: Triggered + 2 + 1 + read-write + + + MCPWM1_EVT_TIMER1_TEZ_ST + Represents MCPWM1_evt_timer1_tez trigger status.\\0: Not triggered\\1: Triggered + 3 + 1 + read-write + + + MCPWM1_EVT_TIMER2_TEZ_ST + Represents MCPWM1_evt_timer2_tez trigger status.\\0: Not triggered\\1: Triggered + 4 + 1 + read-write + + + MCPWM1_EVT_TIMER0_TEP_ST + Represents MCPWM1_evt_timer0_tep trigger status.\\0: Not triggered\\1: Triggered + 5 + 1 + read-write + + + MCPWM1_EVT_TIMER1_TEP_ST + Represents MCPWM1_evt_timer1_tep trigger status.\\0: Not triggered\\1: Triggered + 6 + 1 + read-write + + + MCPWM1_EVT_TIMER2_TEP_ST + Represents MCPWM1_evt_timer2_tep trigger status.\\0: Not triggered\\1: Triggered + 7 + 1 + read-write + + + MCPWM1_EVT_OP0_TEA_ST + Represents MCPWM1_evt_op0_tea trigger status.\\0: Not triggered\\1: Triggered + 8 + 1 + read-write + + + MCPWM1_EVT_OP1_TEA_ST + Represents MCPWM1_evt_op1_tea trigger status.\\0: Not triggered\\1: Triggered + 9 + 1 + read-write + + + MCPWM1_EVT_OP2_TEA_ST + Represents MCPWM1_evt_op2_tea trigger status.\\0: Not triggered\\1: Triggered + 10 + 1 + read-write + + + MCPWM1_EVT_OP0_TEB_ST + Represents MCPWM1_evt_op0_teb trigger status.\\0: Not triggered\\1: Triggered + 11 + 1 + read-write + + + MCPWM1_EVT_OP1_TEB_ST + Represents MCPWM1_evt_op1_teb trigger status.\\0: Not triggered\\1: Triggered + 12 + 1 + read-write + + + MCPWM1_EVT_OP2_TEB_ST + Represents MCPWM1_evt_op2_teb trigger status.\\0: Not triggered\\1: Triggered + 13 + 1 + read-write + + + MCPWM1_EVT_F0_ST + Represents MCPWM1_evt_f0 trigger status.\\0: Not triggered\\1: Triggered + 14 + 1 + read-write + + + MCPWM1_EVT_F1_ST + Represents MCPWM1_evt_f1 trigger status.\\0: Not triggered\\1: Triggered + 15 + 1 + read-write + + + MCPWM1_EVT_F2_ST + Represents MCPWM1_evt_f2 trigger status.\\0: Not triggered\\1: Triggered + 16 + 1 + read-write + + + MCPWM1_EVT_F0_CLR_ST + Represents MCPWM1_evt_f0_clr trigger status.\\0: Not triggered\\1: Triggered + 17 + 1 + read-write + + + MCPWM1_EVT_F1_CLR_ST + Represents MCPWM1_evt_f1_clr trigger status.\\0: Not triggered\\1: Triggered + 18 + 1 + read-write + + + MCPWM1_EVT_F2_CLR_ST + Represents MCPWM1_evt_f2_clr trigger status.\\0: Not triggered\\1: Triggered + 19 + 1 + read-write + + + MCPWM1_EVT_TZ0_CBC_ST + Represents MCPWM1_evt_tz0_cbc trigger status.\\0: Not triggered\\1: Triggered + 20 + 1 + read-write + + + MCPWM1_EVT_TZ1_CBC_ST + Represents MCPWM1_evt_tz1_cbc trigger status.\\0: Not triggered\\1: Triggered + 21 + 1 + read-write + + + MCPWM1_EVT_TZ2_CBC_ST + Represents MCPWM1_evt_tz2_cbc trigger status.\\0: Not triggered\\1: Triggered + 22 + 1 + read-write + + + MCPWM1_EVT_TZ0_OST_ST + Represents MCPWM1_evt_tz0_ost trigger status.\\0: Not triggered\\1: Triggered + 23 + 1 + read-write + + + MCPWM1_EVT_TZ1_OST_ST + Represents MCPWM1_evt_tz1_ost trigger status.\\0: Not triggered\\1: Triggered + 24 + 1 + read-write + + + MCPWM1_EVT_TZ2_OST_ST + Represents MCPWM1_evt_tz2_ost trigger status.\\0: Not triggered\\1: Triggered + 25 + 1 + read-write + + + MCPWM1_EVT_CAP0_ST + Represents MCPWM1_evt_cap0 trigger status.\\0: Not triggered\\1: Triggered + 26 + 1 + read-write + + + MCPWM1_EVT_CAP1_ST + Represents MCPWM1_evt_cap1 trigger status.\\0: Not triggered\\1: Triggered + 27 + 1 + read-write + + + MCPWM1_EVT_CAP2_ST + Represents MCPWM1_evt_cap2 trigger status.\\0: Not triggered\\1: Triggered + 28 + 1 + read-write + + + MCPWM1_EVT_OP0_TEE1_ST + Represents MCPWM1_evt_op0_tee1 trigger status.\\0: Not triggered\\1: Triggered + 29 + 1 + read-write + + + MCPWM1_EVT_OP1_TEE1_ST + Represents MCPWM1_evt_op1_tee1 trigger status.\\0: Not triggered\\1: Triggered + 30 + 1 + read-write + + + MCPWM1_EVT_OP2_TEE1_ST + Represents MCPWM1_evt_op2_tee1 trigger status.\\0: Not triggered\\1: Triggered + 31 + 1 + read-write + + + + + EVT_ST3_CLR + Events trigger status clear register + 0x1C4 + 0x20 + + + MCPWM1_EVT_TIMER1_STOP_ST_CLR + Configures whether or not to clear MCPWM1_evt_timer1_stop trigger status.\\0: Invalid, No effect\\1: Clear + 0 + 1 + write-only + + + MCPWM1_EVT_TIMER2_STOP_ST_CLR + Configures whether or not to clear MCPWM1_evt_timer2_stop trigger status.\\0: Invalid, No effect\\1: Clear + 1 + 1 + write-only + + + MCPWM1_EVT_TIMER0_TEZ_ST_CLR + Configures whether or not to clear MCPWM1_evt_timer0_tez trigger status.\\0: Invalid, No effect\\1: Clear + 2 + 1 + write-only + + + MCPWM1_EVT_TIMER1_TEZ_ST_CLR + Configures whether or not to clear MCPWM1_evt_timer1_tez trigger status.\\0: Invalid, No effect\\1: Clear + 3 + 1 + write-only + + + MCPWM1_EVT_TIMER2_TEZ_ST_CLR + Configures whether or not to clear MCPWM1_evt_timer2_tez trigger status.\\0: Invalid, No effect\\1: Clear + 4 + 1 + write-only + + + MCPWM1_EVT_TIMER0_TEP_ST_CLR + Configures whether or not to clear MCPWM1_evt_timer0_tep trigger status.\\0: Invalid, No effect\\1: Clear + 5 + 1 + write-only + + + MCPWM1_EVT_TIMER1_TEP_ST_CLR + Configures whether or not to clear MCPWM1_evt_timer1_tep trigger status.\\0: Invalid, No effect\\1: Clear + 6 + 1 + write-only + + + MCPWM1_EVT_TIMER2_TEP_ST_CLR + Configures whether or not to clear MCPWM1_evt_timer2_tep trigger status.\\0: Invalid, No effect\\1: Clear + 7 + 1 + write-only + + + MCPWM1_EVT_OP0_TEA_ST_CLR + Configures whether or not to clear MCPWM1_evt_op0_tea trigger status.\\0: Invalid, No effect\\1: Clear + 8 + 1 + write-only + + + MCPWM1_EVT_OP1_TEA_ST_CLR + Configures whether or not to clear MCPWM1_evt_op1_tea trigger status.\\0: Invalid, No effect\\1: Clear + 9 + 1 + write-only + + + MCPWM1_EVT_OP2_TEA_ST_CLR + Configures whether or not to clear MCPWM1_evt_op2_tea trigger status.\\0: Invalid, No effect\\1: Clear + 10 + 1 + write-only + + + MCPWM1_EVT_OP0_TEB_ST_CLR + Configures whether or not to clear MCPWM1_evt_op0_teb trigger status.\\0: Invalid, No effect\\1: Clear + 11 + 1 + write-only + + + MCPWM1_EVT_OP1_TEB_ST_CLR + Configures whether or not to clear MCPWM1_evt_op1_teb trigger status.\\0: Invalid, No effect\\1: Clear + 12 + 1 + write-only + + + MCPWM1_EVT_OP2_TEB_ST_CLR + Configures whether or not to clear MCPWM1_evt_op2_teb trigger status.\\0: Invalid, No effect\\1: Clear + 13 + 1 + write-only + + + MCPWM1_EVT_F0_ST_CLR + Configures whether or not to clear MCPWM1_evt_f0 trigger status.\\0: Invalid, No effect\\1: Clear + 14 + 1 + write-only + + + MCPWM1_EVT_F1_ST_CLR + Configures whether or not to clear MCPWM1_evt_f1 trigger status.\\0: Invalid, No effect\\1: Clear + 15 + 1 + write-only + + + MCPWM1_EVT_F2_ST_CLR + Configures whether or not to clear MCPWM1_evt_f2 trigger status.\\0: Invalid, No effect\\1: Clear + 16 + 1 + write-only + + + MCPWM1_EVT_F0_CLR_ST_CLR + Configures whether or not to clear MCPWM1_evt_f0_clr trigger status.\\0: Invalid, No effect\\1: Clear + 17 + 1 + write-only + + + MCPWM1_EVT_F1_CLR_ST_CLR + Configures whether or not to clear MCPWM1_evt_f1_clr trigger status.\\0: Invalid, No effect\\1: Clear + 18 + 1 + write-only + + + MCPWM1_EVT_F2_CLR_ST_CLR + Configures whether or not to clear MCPWM1_evt_f2_clr trigger status.\\0: Invalid, No effect\\1: Clear + 19 + 1 + write-only + + + MCPWM1_EVT_TZ0_CBC_ST_CLR + Configures whether or not to clear MCPWM1_evt_tz0_cbc trigger status.\\0: Invalid, No effect\\1: Clear + 20 + 1 + write-only + + + MCPWM1_EVT_TZ1_CBC_ST_CLR + Configures whether or not to clear MCPWM1_evt_tz1_cbc trigger status.\\0: Invalid, No effect\\1: Clear + 21 + 1 + write-only + + + MCPWM1_EVT_TZ2_CBC_ST_CLR + Configures whether or not to clear MCPWM1_evt_tz2_cbc trigger status.\\0: Invalid, No effect\\1: Clear + 22 + 1 + write-only + + + MCPWM1_EVT_TZ0_OST_ST_CLR + Configures whether or not to clear MCPWM1_evt_tz0_ost trigger status.\\0: Invalid, No effect\\1: Clear + 23 + 1 + write-only + + + MCPWM1_EVT_TZ1_OST_ST_CLR + Configures whether or not to clear MCPWM1_evt_tz1_ost trigger status.\\0: Invalid, No effect\\1: Clear + 24 + 1 + write-only + + + MCPWM1_EVT_TZ2_OST_ST_CLR + Configures whether or not to clear MCPWM1_evt_tz2_ost trigger status.\\0: Invalid, No effect\\1: Clear + 25 + 1 + write-only + + + MCPWM1_EVT_CAP0_ST_CLR + Configures whether or not to clear MCPWM1_evt_cap0 trigger status.\\0: Invalid, No effect\\1: Clear + 26 + 1 + write-only + + + MCPWM1_EVT_CAP1_ST_CLR + Configures whether or not to clear MCPWM1_evt_cap1 trigger status.\\0: Invalid, No effect\\1: Clear + 27 + 1 + write-only + + + MCPWM1_EVT_CAP2_ST_CLR + Configures whether or not to clear MCPWM1_evt_cap2 trigger status.\\0: Invalid, No effect\\1: Clear + 28 + 1 + write-only + + + MCPWM1_EVT_OP0_TEE1_ST_CLR + Configures whether or not to clear MCPWM1_evt_op0_tee1 trigger status.\\0: Invalid, No effect\\1: Clear + 29 + 1 + write-only + + + MCPWM1_EVT_OP1_TEE1_ST_CLR + Configures whether or not to clear MCPWM1_evt_op1_tee1 trigger status.\\0: Invalid, No effect\\1: Clear + 30 + 1 + write-only + + + MCPWM1_EVT_OP2_TEE1_ST_CLR + Configures whether or not to clear MCPWM1_evt_op2_tee1 trigger status.\\0: Invalid, No effect\\1: Clear + 31 + 1 + write-only + + + + + EVT_ST4 + Events trigger status register + 0x1C8 + 0x20 + + + MCPWM1_EVT_OP0_TEE2_ST + Represents MCPWM1_evt_op0_tee2 trigger status.\\0: Not triggered\\1: Triggered + 0 + 1 + read-write + + + MCPWM1_EVT_OP1_TEE2_ST + Represents MCPWM1_evt_op1_tee2 trigger status.\\0: Not triggered\\1: Triggered + 1 + 1 + read-write + + + MCPWM1_EVT_OP2_TEE2_ST + Represents MCPWM1_evt_op2_tee2 trigger status.\\0: Not triggered\\1: Triggered + 2 + 1 + read-write + + + ADC_EVT_CONV_CMPLT0_ST + Represents ADC_evt_conv_cmplt0 trigger status.\\0: Not triggered\\1: Triggered + 3 + 1 + read-write + + + ADC_EVT_EQ_ABOVE_THRESH0_ST + Represents ADC_evt_eq_above_thresh0 trigger status.\\0: Not triggered\\1: Triggered + 4 + 1 + read-write + + + ADC_EVT_EQ_ABOVE_THRESH1_ST + Represents ADC_evt_eq_above_thresh1 trigger status.\\0: Not triggered\\1: Triggered + 5 + 1 + read-write + + + ADC_EVT_EQ_BELOW_THRESH0_ST + Represents ADC_evt_eq_below_thresh0 trigger status.\\0: Not triggered\\1: Triggered + 6 + 1 + read-write + + + ADC_EVT_EQ_BELOW_THRESH1_ST + Represents ADC_evt_eq_below_thresh1 trigger status.\\0: Not triggered\\1: Triggered + 7 + 1 + read-write + + + ADC_EVT_RESULT_DONE0_ST + Represents ADC_evt_result_done0 trigger status.\\0: Not triggered\\1: Triggered + 8 + 1 + read-write + + + ADC_EVT_STOPPED0_ST + Represents ADC_evt_stopped0 trigger status.\\0: Not triggered\\1: Triggered + 9 + 1 + read-write + + + ADC_EVT_STARTED0_ST + Represents ADC_evt_started0 trigger status.\\0: Not triggered\\1: Triggered + 10 + 1 + read-write + + + REGDMA_EVT_DONE0_ST + Represents REGDMA_evt_done0 trigger status.\\0: Not triggered\\1: Triggered + 11 + 1 + read-write + + + REGDMA_EVT_DONE1_ST + Represents REGDMA_evt_done1 trigger status.\\0: Not triggered\\1: Triggered + 12 + 1 + read-write + + + REGDMA_EVT_DONE2_ST + Represents REGDMA_evt_done2 trigger status.\\0: Not triggered\\1: Triggered + 13 + 1 + read-write + + + REGDMA_EVT_DONE3_ST + Represents REGDMA_evt_done3 trigger status.\\0: Not triggered\\1: Triggered + 14 + 1 + read-write + + + REGDMA_EVT_ERR0_ST + Represents REGDMA_evt_err0 trigger status.\\0: Not triggered\\1: Triggered + 15 + 1 + read-write + + + REGDMA_EVT_ERR1_ST + Represents REGDMA_evt_err1 trigger status.\\0: Not triggered\\1: Triggered + 16 + 1 + read-write + + + REGDMA_EVT_ERR2_ST + Represents REGDMA_evt_err2 trigger status.\\0: Not triggered\\1: Triggered + 17 + 1 + read-write + + + REGDMA_EVT_ERR3_ST + Represents REGDMA_evt_err3 trigger status.\\0: Not triggered\\1: Triggered + 18 + 1 + read-write + + + TMPSNSR_EVT_OVER_LIMIT_ST + Represents TMPSNSR_evt_over_limit trigger status.\\0: Not triggered\\1: Triggered + 19 + 1 + read-write + + + I2S0_EVT_RX_DONE_ST + Represents I2S0_evt_rx_done trigger status.\\0: Not triggered\\1: Triggered + 20 + 1 + read-write + + + I2S0_EVT_TX_DONE_ST + Represents I2S0_evt_tx_done trigger status.\\0: Not triggered\\1: Triggered + 21 + 1 + read-write + + + I2S0_EVT_X_WORDS_RECEIVED_ST + Represents I2S0_evt_x_words_received trigger status.\\0: Not triggered\\1: Triggered + 22 + 1 + read-write + + + I2S0_EVT_X_WORDS_SENT_ST + Represents I2S0_evt_x_words_sent trigger status.\\0: Not triggered\\1: Triggered + 23 + 1 + read-write + + + I2S1_EVT_RX_DONE_ST + Represents I2S1_evt_rx_done trigger status.\\0: Not triggered\\1: Triggered + 24 + 1 + read-write + + + I2S1_EVT_TX_DONE_ST + Represents I2S1_evt_tx_done trigger status.\\0: Not triggered\\1: Triggered + 25 + 1 + read-write + + + I2S1_EVT_X_WORDS_RECEIVED_ST + Represents I2S1_evt_x_words_received trigger status.\\0: Not triggered\\1: Triggered + 26 + 1 + read-write + + + I2S1_EVT_X_WORDS_SENT_ST + Represents I2S1_evt_x_words_sent trigger status.\\0: Not triggered\\1: Triggered + 27 + 1 + read-write + + + I2S2_EVT_RX_DONE_ST + Represents I2S2_evt_rx_done trigger status.\\0: Not triggered\\1: Triggered + 28 + 1 + read-write + + + I2S2_EVT_TX_DONE_ST + Represents I2S2_evt_tx_done trigger status.\\0: Not triggered\\1: Triggered + 29 + 1 + read-write + + + I2S2_EVT_X_WORDS_RECEIVED_ST + Represents I2S2_evt_x_words_received trigger status.\\0: Not triggered\\1: Triggered + 30 + 1 + read-write + + + I2S2_EVT_X_WORDS_SENT_ST + Represents I2S2_evt_x_words_sent trigger status.\\0: Not triggered\\1: Triggered + 31 + 1 + read-write + + + + + EVT_ST4_CLR + Events trigger status clear register + 0x1CC + 0x20 + + + MCPWM1_EVT_OP0_TEE2_ST_CLR + Configures whether or not to clear MCPWM1_evt_op0_tee2 trigger status.\\0: Invalid, No effect\\1: Clear + 0 + 1 + write-only + + + MCPWM1_EVT_OP1_TEE2_ST_CLR + Configures whether or not to clear MCPWM1_evt_op1_tee2 trigger status.\\0: Invalid, No effect\\1: Clear + 1 + 1 + write-only + + + MCPWM1_EVT_OP2_TEE2_ST_CLR + Configures whether or not to clear MCPWM1_evt_op2_tee2 trigger status.\\0: Invalid, No effect\\1: Clear + 2 + 1 + write-only + + + ADC_EVT_CONV_CMPLT0_ST_CLR + Configures whether or not to clear ADC_evt_conv_cmplt0 trigger status.\\0: Invalid, No effect\\1: Clear + 3 + 1 + write-only + + + ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR + Configures whether or not to clear ADC_evt_eq_above_thresh0 trigger status.\\0: Invalid, No effect\\1: Clear + 4 + 1 + write-only + + + ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR + Configures whether or not to clear ADC_evt_eq_above_thresh1 trigger status.\\0: Invalid, No effect\\1: Clear + 5 + 1 + write-only + + + ADC_EVT_EQ_BELOW_THRESH0_ST_CLR + Configures whether or not to clear ADC_evt_eq_below_thresh0 trigger status.\\0: Invalid, No effect\\1: Clear + 6 + 1 + write-only + + + ADC_EVT_EQ_BELOW_THRESH1_ST_CLR + Configures whether or not to clear ADC_evt_eq_below_thresh1 trigger status.\\0: Invalid, No effect\\1: Clear + 7 + 1 + write-only + + + ADC_EVT_RESULT_DONE0_ST_CLR + Configures whether or not to clear ADC_evt_result_done0 trigger status.\\0: Invalid, No effect\\1: Clear + 8 + 1 + write-only + + + ADC_EVT_STOPPED0_ST_CLR + Configures whether or not to clear ADC_evt_stopped0 trigger status.\\0: Invalid, No effect\\1: Clear + 9 + 1 + write-only + + + ADC_EVT_STARTED0_ST_CLR + Configures whether or not to clear ADC_evt_started0 trigger status.\\0: Invalid, No effect\\1: Clear + 10 + 1 + write-only + + + REGDMA_EVT_DONE0_ST_CLR + Configures whether or not to clear REGDMA_evt_done0 trigger status.\\0: Invalid, No effect\\1: Clear + 11 + 1 + write-only + + + REGDMA_EVT_DONE1_ST_CLR + Configures whether or not to clear REGDMA_evt_done1 trigger status.\\0: Invalid, No effect\\1: Clear + 12 + 1 + write-only + + + REGDMA_EVT_DONE2_ST_CLR + Configures whether or not to clear REGDMA_evt_done2 trigger status.\\0: Invalid, No effect\\1: Clear + 13 + 1 + write-only + + + REGDMA_EVT_DONE3_ST_CLR + Configures whether or not to clear REGDMA_evt_done3 trigger status.\\0: Invalid, No effect\\1: Clear + 14 + 1 + write-only + + + REGDMA_EVT_ERR0_ST_CLR + Configures whether or not to clear REGDMA_evt_err0 trigger status.\\0: Invalid, No effect\\1: Clear + 15 + 1 + write-only + + + REGDMA_EVT_ERR1_ST_CLR + Configures whether or not to clear REGDMA_evt_err1 trigger status.\\0: Invalid, No effect\\1: Clear + 16 + 1 + write-only + + + REGDMA_EVT_ERR2_ST_CLR + Configures whether or not to clear REGDMA_evt_err2 trigger status.\\0: Invalid, No effect\\1: Clear + 17 + 1 + write-only + + + REGDMA_EVT_ERR3_ST_CLR + Configures whether or not to clear REGDMA_evt_err3 trigger status.\\0: Invalid, No effect\\1: Clear + 18 + 1 + write-only + + + TMPSNSR_EVT_OVER_LIMIT_ST_CLR + Configures whether or not to clear TMPSNSR_evt_over_limit trigger status.\\0: Invalid, No effect\\1: Clear + 19 + 1 + write-only + + + I2S0_EVT_RX_DONE_ST_CLR + Configures whether or not to clear I2S0_evt_rx_done trigger status.\\0: Invalid, No effect\\1: Clear + 20 + 1 + write-only + + + I2S0_EVT_TX_DONE_ST_CLR + Configures whether or not to clear I2S0_evt_tx_done trigger status.\\0: Invalid, No effect\\1: Clear + 21 + 1 + write-only + + + I2S0_EVT_X_WORDS_RECEIVED_ST_CLR + Configures whether or not to clear I2S0_evt_x_words_received trigger status.\\0: Invalid, No effect\\1: Clear + 22 + 1 + write-only + + + I2S0_EVT_X_WORDS_SENT_ST_CLR + Configures whether or not to clear I2S0_evt_x_words_sent trigger status.\\0: Invalid, No effect\\1: Clear + 23 + 1 + write-only + + + I2S1_EVT_RX_DONE_ST_CLR + Configures whether or not to clear I2S1_evt_rx_done trigger status.\\0: Invalid, No effect\\1: Clear + 24 + 1 + write-only + + + I2S1_EVT_TX_DONE_ST_CLR + Configures whether or not to clear I2S1_evt_tx_done trigger status.\\0: Invalid, No effect\\1: Clear + 25 + 1 + write-only + + + I2S1_EVT_X_WORDS_RECEIVED_ST_CLR + Configures whether or not to clear I2S1_evt_x_words_received trigger status.\\0: Invalid, No effect\\1: Clear + 26 + 1 + write-only + + + I2S1_EVT_X_WORDS_SENT_ST_CLR + Configures whether or not to clear I2S1_evt_x_words_sent trigger status.\\0: Invalid, No effect\\1: Clear + 27 + 1 + write-only + + + I2S2_EVT_RX_DONE_ST_CLR + Configures whether or not to clear I2S2_evt_rx_done trigger status.\\0: Invalid, No effect\\1: Clear + 28 + 1 + write-only + + + I2S2_EVT_TX_DONE_ST_CLR + Configures whether or not to clear I2S2_evt_tx_done trigger status.\\0: Invalid, No effect\\1: Clear + 29 + 1 + write-only + + + I2S2_EVT_X_WORDS_RECEIVED_ST_CLR + Configures whether or not to clear I2S2_evt_x_words_received trigger status.\\0: Invalid, No effect\\1: Clear + 30 + 1 + write-only + + + I2S2_EVT_X_WORDS_SENT_ST_CLR + Configures whether or not to clear I2S2_evt_x_words_sent trigger status.\\0: Invalid, No effect\\1: Clear + 31 + 1 + write-only + + + + + EVT_ST5 + Events trigger status register + 0x1D0 + 0x20 + + + ULP_EVT_ERR_INTR_ST + Represents ULP_evt_err_intr trigger status.\\0: Not triggered\\1: Triggered + 0 + 1 + read-write + + + ULP_EVT_HALT_ST + Represents ULP_evt_halt trigger status.\\0: Not triggered\\1: Triggered + 1 + 1 + read-write + + + ULP_EVT_START_INTR_ST + Represents ULP_evt_start_intr trigger status.\\0: Not triggered\\1: Triggered + 2 + 1 + read-write + + + RTC_EVT_TICK_ST + Represents RTC_evt_tick trigger status.\\0: Not triggered\\1: Triggered + 3 + 1 + read-write + + + RTC_EVT_OVF_ST + Represents RTC_evt_ovf trigger status.\\0: Not triggered\\1: Triggered + 4 + 1 + read-write + + + RTC_EVT_CMP_ST + Represents RTC_evt_cmp trigger status.\\0: Not triggered\\1: Triggered + 5 + 1 + read-write + + + PDMA_AHB_EVT_IN_DONE_CH0_ST + Represents PDMA_AHB_evt_in_done_ch0 trigger status.\\0: Not triggered\\1: Triggered + 6 + 1 + read-write + + + PDMA_AHB_EVT_IN_DONE_CH1_ST + Represents PDMA_AHB_evt_in_done_ch1 trigger status.\\0: Not triggered\\1: Triggered + 7 + 1 + read-write + + + PDMA_AHB_EVT_IN_DONE_CH2_ST + Represents PDMA_AHB_evt_in_done_ch2 trigger status.\\0: Not triggered\\1: Triggered + 8 + 1 + read-write + + + PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST + Represents PDMA_AHB_evt_in_suc_eof_ch0 trigger status.\\0: Not triggered\\1: Triggered + 9 + 1 + read-write + + + PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST + Represents PDMA_AHB_evt_in_suc_eof_ch1 trigger status.\\0: Not triggered\\1: Triggered + 10 + 1 + read-write + + + PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST + Represents PDMA_AHB_evt_in_suc_eof_ch2 trigger status.\\0: Not triggered\\1: Triggered + 11 + 1 + read-write + + + PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST + Represents PDMA_AHB_evt_in_fifo_empty_ch0 trigger status.\\0: Not triggered\\1: Triggered + 12 + 1 + read-write + + + PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST + Represents PDMA_AHB_evt_in_fifo_empty_ch1 trigger status.\\0: Not triggered\\1: Triggered + 13 + 1 + read-write + + + PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST + Represents PDMA_AHB_evt_in_fifo_empty_ch2 trigger status.\\0: Not triggered\\1: Triggered + 14 + 1 + read-write + + + PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST + Represents PDMA_AHB_evt_in_fifo_full_ch0 trigger status.\\0: Not triggered\\1: Triggered + 15 + 1 + read-write + + + PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST + Represents PDMA_AHB_evt_in_fifo_full_ch1 trigger status.\\0: Not triggered\\1: Triggered + 16 + 1 + read-write + + + PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST + Represents PDMA_AHB_evt_in_fifo_full_ch2 trigger status.\\0: Not triggered\\1: Triggered + 17 + 1 + read-write + + + PDMA_AHB_EVT_OUT_DONE_CH0_ST + Represents PDMA_AHB_evt_out_done_ch0 trigger status.\\0: Not triggered\\1: Triggered + 18 + 1 + read-write + + + PDMA_AHB_EVT_OUT_DONE_CH1_ST + Represents PDMA_AHB_evt_out_done_ch1 trigger status.\\0: Not triggered\\1: Triggered + 19 + 1 + read-write + + + PDMA_AHB_EVT_OUT_DONE_CH2_ST + Represents PDMA_AHB_evt_out_done_ch2 trigger status.\\0: Not triggered\\1: Triggered + 20 + 1 + read-write + + + PDMA_AHB_EVT_OUT_EOF_CH0_ST + Represents PDMA_AHB_evt_out_eof_ch0 trigger status.\\0: Not triggered\\1: Triggered + 21 + 1 + read-write + + + PDMA_AHB_EVT_OUT_EOF_CH1_ST + Represents PDMA_AHB_evt_out_eof_ch1 trigger status.\\0: Not triggered\\1: Triggered + 22 + 1 + read-write + + + PDMA_AHB_EVT_OUT_EOF_CH2_ST + Represents PDMA_AHB_evt_out_eof_ch2 trigger status.\\0: Not triggered\\1: Triggered + 23 + 1 + read-write + + + PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST + Represents PDMA_AHB_evt_out_total_eof_ch0 trigger status.\\0: Not triggered\\1: Triggered + 24 + 1 + read-write + + + PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST + Represents PDMA_AHB_evt_out_total_eof_ch1 trigger status.\\0: Not triggered\\1: Triggered + 25 + 1 + read-write + + + PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST + Represents PDMA_AHB_evt_out_total_eof_ch2 trigger status.\\0: Not triggered\\1: Triggered + 26 + 1 + read-write + + + PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST + Represents PDMA_AHB_evt_out_fifo_empty_ch0 trigger status.\\0: Not triggered\\1: Triggered + 27 + 1 + read-write + + + PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST + Represents PDMA_AHB_evt_out_fifo_empty_ch1 trigger status.\\0: Not triggered\\1: Triggered + 28 + 1 + read-write + + + PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST + Represents PDMA_AHB_evt_out_fifo_empty_ch2 trigger status.\\0: Not triggered\\1: Triggered + 29 + 1 + read-write + + + PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST + Represents PDMA_AHB_evt_out_fifo_full_ch0 trigger status.\\0: Not triggered\\1: Triggered + 30 + 1 + read-write + + + PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST + Represents PDMA_AHB_evt_out_fifo_full_ch1 trigger status.\\0: Not triggered\\1: Triggered + 31 + 1 + read-write + + + + + EVT_ST5_CLR + Events trigger status clear register + 0x1D4 + 0x20 + + + ULP_EVT_ERR_INTR_ST_CLR + Configures whether or not to clear ULP_evt_err_intr trigger status.\\0: Invalid, No effect\\1: Clear + 0 + 1 + write-only + + + ULP_EVT_HALT_ST_CLR + Configures whether or not to clear ULP_evt_halt trigger status.\\0: Invalid, No effect\\1: Clear + 1 + 1 + write-only + + + ULP_EVT_START_INTR_ST_CLR + Configures whether or not to clear ULP_evt_start_intr trigger status.\\0: Invalid, No effect\\1: Clear + 2 + 1 + write-only + + + RTC_EVT_TICK_ST_CLR + Configures whether or not to clear RTC_evt_tick trigger status.\\0: Invalid, No effect\\1: Clear + 3 + 1 + write-only + + + RTC_EVT_OVF_ST_CLR + Configures whether or not to clear RTC_evt_ovf trigger status.\\0: Invalid, No effect\\1: Clear + 4 + 1 + write-only + + + RTC_EVT_CMP_ST_CLR + Configures whether or not to clear RTC_evt_cmp trigger status.\\0: Invalid, No effect\\1: Clear + 5 + 1 + write-only + + + PDMA_AHB_EVT_IN_DONE_CH0_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_in_done_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 6 + 1 + write-only + + + PDMA_AHB_EVT_IN_DONE_CH1_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_in_done_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 7 + 1 + write-only + + + PDMA_AHB_EVT_IN_DONE_CH2_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_in_done_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 8 + 1 + write-only + + + PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_in_suc_eof_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 9 + 1 + write-only + + + PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_in_suc_eof_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 10 + 1 + write-only + + + PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_in_suc_eof_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 11 + 1 + write-only + + + PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_in_fifo_empty_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 12 + 1 + write-only + + + PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_in_fifo_empty_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 13 + 1 + write-only + + + PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_in_fifo_empty_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 14 + 1 + write-only + + + PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_in_fifo_full_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 15 + 1 + write-only + + + PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_in_fifo_full_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 16 + 1 + write-only + + + PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_in_fifo_full_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 17 + 1 + write-only + + + PDMA_AHB_EVT_OUT_DONE_CH0_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_out_done_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 18 + 1 + write-only + + + PDMA_AHB_EVT_OUT_DONE_CH1_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_out_done_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 19 + 1 + write-only + + + PDMA_AHB_EVT_OUT_DONE_CH2_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_out_done_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 20 + 1 + write-only + + + PDMA_AHB_EVT_OUT_EOF_CH0_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_out_eof_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 21 + 1 + write-only + + + PDMA_AHB_EVT_OUT_EOF_CH1_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_out_eof_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 22 + 1 + write-only + + + PDMA_AHB_EVT_OUT_EOF_CH2_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_out_eof_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 23 + 1 + write-only + + + PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_out_total_eof_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 24 + 1 + write-only + + + PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_out_total_eof_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 25 + 1 + write-only + + + PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_out_total_eof_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 26 + 1 + write-only + + + PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_out_fifo_empty_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 27 + 1 + write-only + + + PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_out_fifo_empty_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 28 + 1 + write-only + + + PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_out_fifo_empty_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 29 + 1 + write-only + + + PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_out_fifo_full_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 30 + 1 + write-only + + + PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_out_fifo_full_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 31 + 1 + write-only + + + + + EVT_ST6 + Events trigger status register + 0x1D8 + 0x20 + + + PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST + Represents PDMA_AHB_evt_out_fifo_full_ch2 trigger status.\\0: Not triggered\\1: Triggered + 0 + 1 + read-write + + + PDMA_AXI_EVT_IN_DONE_CH0_ST + Represents PDMA_AXI_evt_in_done_ch0 trigger status.\\0: Not triggered\\1: Triggered + 1 + 1 + read-write + + + PDMA_AXI_EVT_IN_DONE_CH1_ST + Represents PDMA_AXI_evt_in_done_ch1 trigger status.\\0: Not triggered\\1: Triggered + 2 + 1 + read-write + + + PDMA_AXI_EVT_IN_DONE_CH2_ST + Represents PDMA_AXI_evt_in_done_ch2 trigger status.\\0: Not triggered\\1: Triggered + 3 + 1 + read-write + + + PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST + Represents PDMA_AXI_evt_in_suc_eof_ch0 trigger status.\\0: Not triggered\\1: Triggered + 4 + 1 + read-write + + + PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST + Represents PDMA_AXI_evt_in_suc_eof_ch1 trigger status.\\0: Not triggered\\1: Triggered + 5 + 1 + read-write + + + PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST + Represents PDMA_AXI_evt_in_suc_eof_ch2 trigger status.\\0: Not triggered\\1: Triggered + 6 + 1 + read-write + + + PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST + Represents PDMA_AXI_evt_in_fifo_empty_ch0 trigger status.\\0: Not triggered\\1: Triggered + 7 + 1 + read-write + + + PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST + Represents PDMA_AXI_evt_in_fifo_empty_ch1 trigger status.\\0: Not triggered\\1: Triggered + 8 + 1 + read-write + + + PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST + Represents PDMA_AXI_evt_in_fifo_empty_ch2 trigger status.\\0: Not triggered\\1: Triggered + 9 + 1 + read-write + + + PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST + Represents PDMA_AXI_evt_in_fifo_full_ch0 trigger status.\\0: Not triggered\\1: Triggered + 10 + 1 + read-write + + + PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST + Represents PDMA_AXI_evt_in_fifo_full_ch1 trigger status.\\0: Not triggered\\1: Triggered + 11 + 1 + read-write + + + PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST + Represents PDMA_AXI_evt_in_fifo_full_ch2 trigger status.\\0: Not triggered\\1: Triggered + 12 + 1 + read-write + + + PDMA_AXI_EVT_OUT_DONE_CH0_ST + Represents PDMA_AXI_evt_out_done_ch0 trigger status.\\0: Not triggered\\1: Triggered + 13 + 1 + read-write + + + PDMA_AXI_EVT_OUT_DONE_CH1_ST + Represents PDMA_AXI_evt_out_done_ch1 trigger status.\\0: Not triggered\\1: Triggered + 14 + 1 + read-write + + + PDMA_AXI_EVT_OUT_DONE_CH2_ST + Represents PDMA_AXI_evt_out_done_ch2 trigger status.\\0: Not triggered\\1: Triggered + 15 + 1 + read-write + + + PDMA_AXI_EVT_OUT_EOF_CH0_ST + Represents PDMA_AXI_evt_out_eof_ch0 trigger status.\\0: Not triggered\\1: Triggered + 16 + 1 + read-write + + + PDMA_AXI_EVT_OUT_EOF_CH1_ST + Represents PDMA_AXI_evt_out_eof_ch1 trigger status.\\0: Not triggered\\1: Triggered + 17 + 1 + read-write + + + PDMA_AXI_EVT_OUT_EOF_CH2_ST + Represents PDMA_AXI_evt_out_eof_ch2 trigger status.\\0: Not triggered\\1: Triggered + 18 + 1 + read-write + + + PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST + Represents PDMA_AXI_evt_out_total_eof_ch0 trigger status.\\0: Not triggered\\1: Triggered + 19 + 1 + read-write + + + PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST + Represents PDMA_AXI_evt_out_total_eof_ch1 trigger status.\\0: Not triggered\\1: Triggered + 20 + 1 + read-write + + + PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST + Represents PDMA_AXI_evt_out_total_eof_ch2 trigger status.\\0: Not triggered\\1: Triggered + 21 + 1 + read-write + + + PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST + Represents PDMA_AXI_evt_out_fifo_empty_ch0 trigger status.\\0: Not triggered\\1: Triggered + 22 + 1 + read-write + + + PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST + Represents PDMA_AXI_evt_out_fifo_empty_ch1 trigger status.\\0: Not triggered\\1: Triggered + 23 + 1 + read-write + + + PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST + Represents PDMA_AXI_evt_out_fifo_empty_ch2 trigger status.\\0: Not triggered\\1: Triggered + 24 + 1 + read-write + + + PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST + Represents PDMA_AXI_evt_out_fifo_full_ch0 trigger status.\\0: Not triggered\\1: Triggered + 25 + 1 + read-write + + + PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST + Represents PDMA_AXI_evt_out_fifo_full_ch1 trigger status.\\0: Not triggered\\1: Triggered + 26 + 1 + read-write + + + PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST + Represents PDMA_AXI_evt_out_fifo_full_ch2 trigger status.\\0: Not triggered\\1: Triggered + 27 + 1 + read-write + + + PMU_EVT_SLEEP_WEEKUP_ST + Represents PMU_evt_sleep_weekup trigger status.\\0: Not triggered\\1: Triggered + 28 + 1 + read-write + + + DMA2D_EVT_IN_DONE_CH0_ST + Represents DMA2D_evt_in_done_ch0 trigger status.\\0: Not triggered\\1: Triggered + 29 + 1 + read-write + + + DMA2D_EVT_IN_DONE_CH1_ST + Represents DMA2D_evt_in_done_ch1 trigger status.\\0: Not triggered\\1: Triggered + 30 + 1 + read-write + + + DMA2D_EVT_IN_SUC_EOF_CH0_ST + Represents DMA2D_evt_in_suc_eof_ch0 trigger status.\\0: Not triggered\\1: Triggered + 31 + 1 + read-write + + + + + EVT_ST6_CLR + Events trigger status clear register + 0x1DC + 0x20 + + + PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_out_fifo_full_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 0 + 1 + write-only + + + PDMA_AXI_EVT_IN_DONE_CH0_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_in_done_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 1 + 1 + write-only + + + PDMA_AXI_EVT_IN_DONE_CH1_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_in_done_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 2 + 1 + write-only + + + PDMA_AXI_EVT_IN_DONE_CH2_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_in_done_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 3 + 1 + write-only + + + PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_in_suc_eof_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 4 + 1 + write-only + + + PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_in_suc_eof_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 5 + 1 + write-only + + + PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_in_suc_eof_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 6 + 1 + write-only + + + PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_in_fifo_empty_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 7 + 1 + write-only + + + PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_in_fifo_empty_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 8 + 1 + write-only + + + PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_in_fifo_empty_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 9 + 1 + write-only + + + PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_in_fifo_full_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 10 + 1 + write-only + + + PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_in_fifo_full_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 11 + 1 + write-only + + + PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_in_fifo_full_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 12 + 1 + write-only + + + PDMA_AXI_EVT_OUT_DONE_CH0_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_out_done_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 13 + 1 + write-only + + + PDMA_AXI_EVT_OUT_DONE_CH1_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_out_done_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 14 + 1 + write-only + + + PDMA_AXI_EVT_OUT_DONE_CH2_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_out_done_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 15 + 1 + write-only + + + PDMA_AXI_EVT_OUT_EOF_CH0_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_out_eof_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 16 + 1 + write-only + + + PDMA_AXI_EVT_OUT_EOF_CH1_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_out_eof_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 17 + 1 + write-only + + + PDMA_AXI_EVT_OUT_EOF_CH2_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_out_eof_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 18 + 1 + write-only + + + PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_out_total_eof_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 19 + 1 + write-only + + + PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_out_total_eof_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 20 + 1 + write-only + + + PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_out_total_eof_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 21 + 1 + write-only + + + PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_out_fifo_empty_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 22 + 1 + write-only + + + PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_out_fifo_empty_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 23 + 1 + write-only + + + PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_out_fifo_empty_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 24 + 1 + write-only + + + PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_out_fifo_full_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 25 + 1 + write-only + + + PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_out_fifo_full_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 26 + 1 + write-only + + + PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_out_fifo_full_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 27 + 1 + write-only + + + PMU_EVT_SLEEP_WEEKUP_ST_CLR + Configures whether or not to clear PMU_evt_sleep_weekup trigger status.\\0: Invalid, No effect\\1: Clear + 28 + 1 + write-only + + + DMA2D_EVT_IN_DONE_CH0_ST_CLR + Configures whether or not to clear DMA2D_evt_in_done_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 29 + 1 + write-only + + + DMA2D_EVT_IN_DONE_CH1_ST_CLR + Configures whether or not to clear DMA2D_evt_in_done_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 30 + 1 + write-only + + + DMA2D_EVT_IN_SUC_EOF_CH0_ST_CLR + Configures whether or not to clear DMA2D_evt_in_suc_eof_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 31 + 1 + write-only + + + + + EVT_ST7 + Events trigger status register + 0x1E0 + 0x20 + + + DMA2D_EVT_IN_SUC_EOF_CH1_ST + Represents DMA2D_evt_in_suc_eof_ch1 trigger status.\\0: Not triggered\\1: Triggered + 0 + 1 + read-write + + + DMA2D_EVT_OUT_DONE_CH0_ST + Represents DMA2D_evt_out_done_ch0 trigger status.\\0: Not triggered\\1: Triggered + 1 + 1 + read-write + + + DMA2D_EVT_OUT_DONE_CH1_ST + Represents DMA2D_evt_out_done_ch1 trigger status.\\0: Not triggered\\1: Triggered + 2 + 1 + read-write + + + DMA2D_EVT_OUT_DONE_CH2_ST + Represents DMA2D_evt_out_done_ch2 trigger status.\\0: Not triggered\\1: Triggered + 3 + 1 + read-write + + + DMA2D_EVT_OUT_EOF_CH0_ST + Represents DMA2D_evt_out_eof_ch0 trigger status.\\0: Not triggered\\1: Triggered + 4 + 1 + read-write + + + DMA2D_EVT_OUT_EOF_CH1_ST + Represents DMA2D_evt_out_eof_ch1 trigger status.\\0: Not triggered\\1: Triggered + 5 + 1 + read-write + + + DMA2D_EVT_OUT_EOF_CH2_ST + Represents DMA2D_evt_out_eof_ch2 trigger status.\\0: Not triggered\\1: Triggered + 6 + 1 + read-write + + + DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST + Represents DMA2D_evt_out_total_eof_ch0 trigger status.\\0: Not triggered\\1: Triggered + 7 + 1 + read-write + + + DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST + Represents DMA2D_evt_out_total_eof_ch1 trigger status.\\0: Not triggered\\1: Triggered + 8 + 1 + read-write + + + DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST + Represents DMA2D_evt_out_total_eof_ch2 trigger status.\\0: Not triggered\\1: Triggered + 9 + 1 + read-write + + + + + EVT_ST7_CLR + Events trigger status clear register + 0x1E4 + 0x20 + + + DMA2D_EVT_IN_SUC_EOF_CH1_ST_CLR + Configures whether or not to clear DMA2D_evt_in_suc_eof_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 0 + 1 + write-only + + + DMA2D_EVT_OUT_DONE_CH0_ST_CLR + Configures whether or not to clear DMA2D_evt_out_done_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 1 + 1 + write-only + + + DMA2D_EVT_OUT_DONE_CH1_ST_CLR + Configures whether or not to clear DMA2D_evt_out_done_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 2 + 1 + write-only + + + DMA2D_EVT_OUT_DONE_CH2_ST_CLR + Configures whether or not to clear DMA2D_evt_out_done_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 3 + 1 + write-only + + + DMA2D_EVT_OUT_EOF_CH0_ST_CLR + Configures whether or not to clear DMA2D_evt_out_eof_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 4 + 1 + write-only + + + DMA2D_EVT_OUT_EOF_CH1_ST_CLR + Configures whether or not to clear DMA2D_evt_out_eof_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 5 + 1 + write-only + + + DMA2D_EVT_OUT_EOF_CH2_ST_CLR + Configures whether or not to clear DMA2D_evt_out_eof_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 6 + 1 + write-only + + + DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST_CLR + Configures whether or not to clear DMA2D_evt_out_total_eof_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 7 + 1 + write-only + + + DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST_CLR + Configures whether or not to clear DMA2D_evt_out_total_eof_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 8 + 1 + write-only + + + DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST_CLR + Configures whether or not to clear DMA2D_evt_out_total_eof_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 9 + 1 + write-only + + + + + TASK_ST0 + Tasks trigger status register + 0x1E8 + 0x20 + + + GPIO_TASK_CH0_SET_ST + Represents GPIO_task_ch0_set trigger status.\\0: Not triggered\\1: Triggered + 0 + 1 + read-write + + + GPIO_TASK_CH1_SET_ST + Represents GPIO_task_ch1_set trigger status.\\0: Not triggered\\1: Triggered + 1 + 1 + read-write + + + GPIO_TASK_CH2_SET_ST + Represents GPIO_task_ch2_set trigger status.\\0: Not triggered\\1: Triggered + 2 + 1 + read-write + + + GPIO_TASK_CH3_SET_ST + Represents GPIO_task_ch3_set trigger status.\\0: Not triggered\\1: Triggered + 3 + 1 + read-write + + + GPIO_TASK_CH4_SET_ST + Represents GPIO_task_ch4_set trigger status.\\0: Not triggered\\1: Triggered + 4 + 1 + read-write + + + GPIO_TASK_CH5_SET_ST + Represents GPIO_task_ch5_set trigger status.\\0: Not triggered\\1: Triggered + 5 + 1 + read-write + + + GPIO_TASK_CH6_SET_ST + Represents GPIO_task_ch6_set trigger status.\\0: Not triggered\\1: Triggered + 6 + 1 + read-write + + + GPIO_TASK_CH7_SET_ST + Represents GPIO_task_ch7_set trigger status.\\0: Not triggered\\1: Triggered + 7 + 1 + read-write + + + GPIO_TASK_CH0_CLEAR_ST + Represents GPIO_task_ch0_clear trigger status.\\0: Not triggered\\1: Triggered + 8 + 1 + read-write + + + GPIO_TASK_CH1_CLEAR_ST + Represents GPIO_task_ch1_clear trigger status.\\0: Not triggered\\1: Triggered + 9 + 1 + read-write + + + GPIO_TASK_CH2_CLEAR_ST + Represents GPIO_task_ch2_clear trigger status.\\0: Not triggered\\1: Triggered + 10 + 1 + read-write + + + GPIO_TASK_CH3_CLEAR_ST + Represents GPIO_task_ch3_clear trigger status.\\0: Not triggered\\1: Triggered + 11 + 1 + read-write + + + GPIO_TASK_CH4_CLEAR_ST + Represents GPIO_task_ch4_clear trigger status.\\0: Not triggered\\1: Triggered + 12 + 1 + read-write + + + GPIO_TASK_CH5_CLEAR_ST + Represents GPIO_task_ch5_clear trigger status.\\0: Not triggered\\1: Triggered + 13 + 1 + read-write + + + GPIO_TASK_CH6_CLEAR_ST + Represents GPIO_task_ch6_clear trigger status.\\0: Not triggered\\1: Triggered + 14 + 1 + read-write + + + GPIO_TASK_CH7_CLEAR_ST + Represents GPIO_task_ch7_clear trigger status.\\0: Not triggered\\1: Triggered + 15 + 1 + read-write + + + GPIO_TASK_CH0_TOGGLE_ST + Represents GPIO_task_ch0_toggle trigger status.\\0: Not triggered\\1: Triggered + 16 + 1 + read-write + + + GPIO_TASK_CH1_TOGGLE_ST + Represents GPIO_task_ch1_toggle trigger status.\\0: Not triggered\\1: Triggered + 17 + 1 + read-write + + + GPIO_TASK_CH2_TOGGLE_ST + Represents GPIO_task_ch2_toggle trigger status.\\0: Not triggered\\1: Triggered + 18 + 1 + read-write + + + GPIO_TASK_CH3_TOGGLE_ST + Represents GPIO_task_ch3_toggle trigger status.\\0: Not triggered\\1: Triggered + 19 + 1 + read-write + + + GPIO_TASK_CH4_TOGGLE_ST + Represents GPIO_task_ch4_toggle trigger status.\\0: Not triggered\\1: Triggered + 20 + 1 + read-write + + + GPIO_TASK_CH5_TOGGLE_ST + Represents GPIO_task_ch5_toggle trigger status.\\0: Not triggered\\1: Triggered + 21 + 1 + read-write + + + GPIO_TASK_CH6_TOGGLE_ST + Represents GPIO_task_ch6_toggle trigger status.\\0: Not triggered\\1: Triggered + 22 + 1 + read-write + + + GPIO_TASK_CH7_TOGGLE_ST + Represents GPIO_task_ch7_toggle trigger status.\\0: Not triggered\\1: Triggered + 23 + 1 + read-write + + + LEDC_TASK_TIMER0_RES_UPDATE_ST + Represents LEDC_task_timer0_res_update trigger status.\\0: Not triggered\\1: Triggered + 24 + 1 + read-write + + + LEDC_TASK_TIMER1_RES_UPDATE_ST + Represents LEDC_task_timer1_res_update trigger status.\\0: Not triggered\\1: Triggered + 25 + 1 + read-write + + + LEDC_TASK_TIMER2_RES_UPDATE_ST + Represents LEDC_task_timer2_res_update trigger status.\\0: Not triggered\\1: Triggered + 26 + 1 + read-write + + + LEDC_TASK_TIMER3_RES_UPDATE_ST + Represents LEDC_task_timer3_res_update trigger status.\\0: Not triggered\\1: Triggered + 27 + 1 + read-write + + + LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST + Represents LEDC_task_duty_scale_update_ch0 trigger status.\\0: Not triggered\\1: Triggered + 28 + 1 + read-write + + + LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST + Represents LEDC_task_duty_scale_update_ch1 trigger status.\\0: Not triggered\\1: Triggered + 29 + 1 + read-write + + + LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST + Represents LEDC_task_duty_scale_update_ch2 trigger status.\\0: Not triggered\\1: Triggered + 30 + 1 + read-write + + + LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST + Represents LEDC_task_duty_scale_update_ch3 trigger status.\\0: Not triggered\\1: Triggered + 31 + 1 + read-write + + + + + TASK_ST0_CLR + Tasks trigger status clear register + 0x1EC + 0x20 + + + GPIO_TASK_CH0_SET_ST_CLR + Configures whether or not to clear GPIO_task_ch0_set trigger status.\\0: Invalid, No effect\\1: Clear + 0 + 1 + write-only + + + GPIO_TASK_CH1_SET_ST_CLR + Configures whether or not to clear GPIO_task_ch1_set trigger status.\\0: Invalid, No effect\\1: Clear + 1 + 1 + write-only + + + GPIO_TASK_CH2_SET_ST_CLR + Configures whether or not to clear GPIO_task_ch2_set trigger status.\\0: Invalid, No effect\\1: Clear + 2 + 1 + write-only + + + GPIO_TASK_CH3_SET_ST_CLR + Configures whether or not to clear GPIO_task_ch3_set trigger status.\\0: Invalid, No effect\\1: Clear + 3 + 1 + write-only + + + GPIO_TASK_CH4_SET_ST_CLR + Configures whether or not to clear GPIO_task_ch4_set trigger status.\\0: Invalid, No effect\\1: Clear + 4 + 1 + write-only + + + GPIO_TASK_CH5_SET_ST_CLR + Configures whether or not to clear GPIO_task_ch5_set trigger status.\\0: Invalid, No effect\\1: Clear + 5 + 1 + write-only + + + GPIO_TASK_CH6_SET_ST_CLR + Configures whether or not to clear GPIO_task_ch6_set trigger status.\\0: Invalid, No effect\\1: Clear + 6 + 1 + write-only + + + GPIO_TASK_CH7_SET_ST_CLR + Configures whether or not to clear GPIO_task_ch7_set trigger status.\\0: Invalid, No effect\\1: Clear + 7 + 1 + write-only + + + GPIO_TASK_CH0_CLEAR_ST_CLR + Configures whether or not to clear GPIO_task_ch0_clear trigger status.\\0: Invalid, No effect\\1: Clear + 8 + 1 + write-only + + + GPIO_TASK_CH1_CLEAR_ST_CLR + Configures whether or not to clear GPIO_task_ch1_clear trigger status.\\0: Invalid, No effect\\1: Clear + 9 + 1 + write-only + + + GPIO_TASK_CH2_CLEAR_ST_CLR + Configures whether or not to clear GPIO_task_ch2_clear trigger status.\\0: Invalid, No effect\\1: Clear + 10 + 1 + write-only + + + GPIO_TASK_CH3_CLEAR_ST_CLR + Configures whether or not to clear GPIO_task_ch3_clear trigger status.\\0: Invalid, No effect\\1: Clear + 11 + 1 + write-only + + + GPIO_TASK_CH4_CLEAR_ST_CLR + Configures whether or not to clear GPIO_task_ch4_clear trigger status.\\0: Invalid, No effect\\1: Clear + 12 + 1 + write-only + + + GPIO_TASK_CH5_CLEAR_ST_CLR + Configures whether or not to clear GPIO_task_ch5_clear trigger status.\\0: Invalid, No effect\\1: Clear + 13 + 1 + write-only + + + GPIO_TASK_CH6_CLEAR_ST_CLR + Configures whether or not to clear GPIO_task_ch6_clear trigger status.\\0: Invalid, No effect\\1: Clear + 14 + 1 + write-only + + + GPIO_TASK_CH7_CLEAR_ST_CLR + Configures whether or not to clear GPIO_task_ch7_clear trigger status.\\0: Invalid, No effect\\1: Clear + 15 + 1 + write-only + + + GPIO_TASK_CH0_TOGGLE_ST_CLR + Configures whether or not to clear GPIO_task_ch0_toggle trigger status.\\0: Invalid, No effect\\1: Clear + 16 + 1 + write-only + + + GPIO_TASK_CH1_TOGGLE_ST_CLR + Configures whether or not to clear GPIO_task_ch1_toggle trigger status.\\0: Invalid, No effect\\1: Clear + 17 + 1 + write-only + + + GPIO_TASK_CH2_TOGGLE_ST_CLR + Configures whether or not to clear GPIO_task_ch2_toggle trigger status.\\0: Invalid, No effect\\1: Clear + 18 + 1 + write-only + + + GPIO_TASK_CH3_TOGGLE_ST_CLR + Configures whether or not to clear GPIO_task_ch3_toggle trigger status.\\0: Invalid, No effect\\1: Clear + 19 + 1 + write-only + + + GPIO_TASK_CH4_TOGGLE_ST_CLR + Configures whether or not to clear GPIO_task_ch4_toggle trigger status.\\0: Invalid, No effect\\1: Clear + 20 + 1 + write-only + + + GPIO_TASK_CH5_TOGGLE_ST_CLR + Configures whether or not to clear GPIO_task_ch5_toggle trigger status.\\0: Invalid, No effect\\1: Clear + 21 + 1 + write-only + + + GPIO_TASK_CH6_TOGGLE_ST_CLR + Configures whether or not to clear GPIO_task_ch6_toggle trigger status.\\0: Invalid, No effect\\1: Clear + 22 + 1 + write-only + + + GPIO_TASK_CH7_TOGGLE_ST_CLR + Configures whether or not to clear GPIO_task_ch7_toggle trigger status.\\0: Invalid, No effect\\1: Clear + 23 + 1 + write-only + + + LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR + Configures whether or not to clear LEDC_task_timer0_res_update trigger status.\\0: Invalid, No effect\\1: Clear + 24 + 1 + write-only + + + LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR + Configures whether or not to clear LEDC_task_timer1_res_update trigger status.\\0: Invalid, No effect\\1: Clear + 25 + 1 + write-only + + + LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR + Configures whether or not to clear LEDC_task_timer2_res_update trigger status.\\0: Invalid, No effect\\1: Clear + 26 + 1 + write-only + + + LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR + Configures whether or not to clear LEDC_task_timer3_res_update trigger status.\\0: Invalid, No effect\\1: Clear + 27 + 1 + write-only + + + LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR + Configures whether or not to clear LEDC_task_duty_scale_update_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 28 + 1 + write-only + + + LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR + Configures whether or not to clear LEDC_task_duty_scale_update_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 29 + 1 + write-only + + + LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR + Configures whether or not to clear LEDC_task_duty_scale_update_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 30 + 1 + write-only + + + LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR + Configures whether or not to clear LEDC_task_duty_scale_update_ch3 trigger status.\\0: Invalid, No effect\\1: Clear + 31 + 1 + write-only + + + + + TASK_ST1 + Tasks trigger status register + 0x1F0 + 0x20 + + + LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST + Represents LEDC_task_duty_scale_update_ch4 trigger status.\\0: Not triggered\\1: Triggered + 0 + 1 + read-write + + + LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST + Represents LEDC_task_duty_scale_update_ch5 trigger status.\\0: Not triggered\\1: Triggered + 1 + 1 + read-write + + + LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST + Represents LEDC_task_duty_scale_update_ch6 trigger status.\\0: Not triggered\\1: Triggered + 2 + 1 + read-write + + + LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST + Represents LEDC_task_duty_scale_update_ch7 trigger status.\\0: Not triggered\\1: Triggered + 3 + 1 + read-write + + + LEDC_TASK_TIMER0_CAP_ST + Represents LEDC_task_timer0_cap trigger status.\\0: Not triggered\\1: Triggered + 4 + 1 + read-write + + + LEDC_TASK_TIMER1_CAP_ST + Represents LEDC_task_timer1_cap trigger status.\\0: Not triggered\\1: Triggered + 5 + 1 + read-write + + + LEDC_TASK_TIMER2_CAP_ST + Represents LEDC_task_timer2_cap trigger status.\\0: Not triggered\\1: Triggered + 6 + 1 + read-write + + + LEDC_TASK_TIMER3_CAP_ST + Represents LEDC_task_timer3_cap trigger status.\\0: Not triggered\\1: Triggered + 7 + 1 + read-write + + + LEDC_TASK_SIG_OUT_DIS_CH0_ST + Represents LEDC_task_sig_out_dis_ch0 trigger status.\\0: Not triggered\\1: Triggered + 8 + 1 + read-write + + + LEDC_TASK_SIG_OUT_DIS_CH1_ST + Represents LEDC_task_sig_out_dis_ch1 trigger status.\\0: Not triggered\\1: Triggered + 9 + 1 + read-write + + + LEDC_TASK_SIG_OUT_DIS_CH2_ST + Represents LEDC_task_sig_out_dis_ch2 trigger status.\\0: Not triggered\\1: Triggered + 10 + 1 + read-write + + + LEDC_TASK_SIG_OUT_DIS_CH3_ST + Represents LEDC_task_sig_out_dis_ch3 trigger status.\\0: Not triggered\\1: Triggered + 11 + 1 + read-write + + + LEDC_TASK_SIG_OUT_DIS_CH4_ST + Represents LEDC_task_sig_out_dis_ch4 trigger status.\\0: Not triggered\\1: Triggered + 12 + 1 + read-write + + + LEDC_TASK_SIG_OUT_DIS_CH5_ST + Represents LEDC_task_sig_out_dis_ch5 trigger status.\\0: Not triggered\\1: Triggered + 13 + 1 + read-write + + + LEDC_TASK_SIG_OUT_DIS_CH6_ST + Represents LEDC_task_sig_out_dis_ch6 trigger status.\\0: Not triggered\\1: Triggered + 14 + 1 + read-write + + + LEDC_TASK_SIG_OUT_DIS_CH7_ST + Represents LEDC_task_sig_out_dis_ch7 trigger status.\\0: Not triggered\\1: Triggered + 15 + 1 + read-write + + + LEDC_TASK_OVF_CNT_RST_CH0_ST + Represents LEDC_task_ovf_cnt_rst_ch0 trigger status.\\0: Not triggered\\1: Triggered + 16 + 1 + read-write + + + LEDC_TASK_OVF_CNT_RST_CH1_ST + Represents LEDC_task_ovf_cnt_rst_ch1 trigger status.\\0: Not triggered\\1: Triggered + 17 + 1 + read-write + + + LEDC_TASK_OVF_CNT_RST_CH2_ST + Represents LEDC_task_ovf_cnt_rst_ch2 trigger status.\\0: Not triggered\\1: Triggered + 18 + 1 + read-write + + + LEDC_TASK_OVF_CNT_RST_CH3_ST + Represents LEDC_task_ovf_cnt_rst_ch3 trigger status.\\0: Not triggered\\1: Triggered + 19 + 1 + read-write + + + LEDC_TASK_OVF_CNT_RST_CH4_ST + Represents LEDC_task_ovf_cnt_rst_ch4 trigger status.\\0: Not triggered\\1: Triggered + 20 + 1 + read-write + + + LEDC_TASK_OVF_CNT_RST_CH5_ST + Represents LEDC_task_ovf_cnt_rst_ch5 trigger status.\\0: Not triggered\\1: Triggered + 21 + 1 + read-write + + + LEDC_TASK_OVF_CNT_RST_CH6_ST + Represents LEDC_task_ovf_cnt_rst_ch6 trigger status.\\0: Not triggered\\1: Triggered + 22 + 1 + read-write + + + LEDC_TASK_OVF_CNT_RST_CH7_ST + Represents LEDC_task_ovf_cnt_rst_ch7 trigger status.\\0: Not triggered\\1: Triggered + 23 + 1 + read-write + + + LEDC_TASK_TIMER0_RST_ST + Represents LEDC_task_timer0_rst trigger status.\\0: Not triggered\\1: Triggered + 24 + 1 + read-write + + + LEDC_TASK_TIMER1_RST_ST + Represents LEDC_task_timer1_rst trigger status.\\0: Not triggered\\1: Triggered + 25 + 1 + read-write + + + LEDC_TASK_TIMER2_RST_ST + Represents LEDC_task_timer2_rst trigger status.\\0: Not triggered\\1: Triggered + 26 + 1 + read-write + + + LEDC_TASK_TIMER3_RST_ST + Represents LEDC_task_timer3_rst trigger status.\\0: Not triggered\\1: Triggered + 27 + 1 + read-write + + + LEDC_TASK_TIMER0_RESUME_ST + Represents LEDC_task_timer0_resume trigger status.\\0: Not triggered\\1: Triggered + 28 + 1 + read-write + + + LEDC_TASK_TIMER1_RESUME_ST + Represents LEDC_task_timer1_resume trigger status.\\0: Not triggered\\1: Triggered + 29 + 1 + read-write + + + LEDC_TASK_TIMER2_RESUME_ST + Represents LEDC_task_timer2_resume trigger status.\\0: Not triggered\\1: Triggered + 30 + 1 + read-write + + + LEDC_TASK_TIMER3_RESUME_ST + Represents LEDC_task_timer3_resume trigger status.\\0: Not triggered\\1: Triggered + 31 + 1 + read-write + + + + + TASK_ST1_CLR + Tasks trigger status clear register + 0x1F4 + 0x20 + + + LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR + Configures whether or not to clear LEDC_task_duty_scale_update_ch4 trigger status.\\0: Invalid, No effect\\1: Clear + 0 + 1 + write-only + + + LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR + Configures whether or not to clear LEDC_task_duty_scale_update_ch5 trigger status.\\0: Invalid, No effect\\1: Clear + 1 + 1 + write-only + + + LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST_CLR + Configures whether or not to clear LEDC_task_duty_scale_update_ch6 trigger status.\\0: Invalid, No effect\\1: Clear + 2 + 1 + write-only + + + LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST_CLR + Configures whether or not to clear LEDC_task_duty_scale_update_ch7 trigger status.\\0: Invalid, No effect\\1: Clear + 3 + 1 + write-only + + + LEDC_TASK_TIMER0_CAP_ST_CLR + Configures whether or not to clear LEDC_task_timer0_cap trigger status.\\0: Invalid, No effect\\1: Clear + 4 + 1 + write-only + + + LEDC_TASK_TIMER1_CAP_ST_CLR + Configures whether or not to clear LEDC_task_timer1_cap trigger status.\\0: Invalid, No effect\\1: Clear + 5 + 1 + write-only + + + LEDC_TASK_TIMER2_CAP_ST_CLR + Configures whether or not to clear LEDC_task_timer2_cap trigger status.\\0: Invalid, No effect\\1: Clear + 6 + 1 + write-only + + + LEDC_TASK_TIMER3_CAP_ST_CLR + Configures whether or not to clear LEDC_task_timer3_cap trigger status.\\0: Invalid, No effect\\1: Clear + 7 + 1 + write-only + + + LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR + Configures whether or not to clear LEDC_task_sig_out_dis_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 8 + 1 + write-only + + + LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR + Configures whether or not to clear LEDC_task_sig_out_dis_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 9 + 1 + write-only + + + LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR + Configures whether or not to clear LEDC_task_sig_out_dis_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 10 + 1 + write-only + + + LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR + Configures whether or not to clear LEDC_task_sig_out_dis_ch3 trigger status.\\0: Invalid, No effect\\1: Clear + 11 + 1 + write-only + + + LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR + Configures whether or not to clear LEDC_task_sig_out_dis_ch4 trigger status.\\0: Invalid, No effect\\1: Clear + 12 + 1 + write-only + + + LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR + Configures whether or not to clear LEDC_task_sig_out_dis_ch5 trigger status.\\0: Invalid, No effect\\1: Clear + 13 + 1 + write-only + + + LEDC_TASK_SIG_OUT_DIS_CH6_ST_CLR + Configures whether or not to clear LEDC_task_sig_out_dis_ch6 trigger status.\\0: Invalid, No effect\\1: Clear + 14 + 1 + write-only + + + LEDC_TASK_SIG_OUT_DIS_CH7_ST_CLR + Configures whether or not to clear LEDC_task_sig_out_dis_ch7 trigger status.\\0: Invalid, No effect\\1: Clear + 15 + 1 + write-only + + + LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR + Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 16 + 1 + write-only + + + LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR + Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 17 + 1 + write-only + + + LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR + Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 18 + 1 + write-only + + + LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR + Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch3 trigger status.\\0: Invalid, No effect\\1: Clear + 19 + 1 + write-only + + + LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR + Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch4 trigger status.\\0: Invalid, No effect\\1: Clear + 20 + 1 + write-only + + + LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR + Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch5 trigger status.\\0: Invalid, No effect\\1: Clear + 21 + 1 + write-only + + + LEDC_TASK_OVF_CNT_RST_CH6_ST_CLR + Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch6 trigger status.\\0: Invalid, No effect\\1: Clear + 22 + 1 + write-only + + + LEDC_TASK_OVF_CNT_RST_CH7_ST_CLR + Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch7 trigger status.\\0: Invalid, No effect\\1: Clear + 23 + 1 + write-only + + + LEDC_TASK_TIMER0_RST_ST_CLR + Configures whether or not to clear LEDC_task_timer0_rst trigger status.\\0: Invalid, No effect\\1: Clear + 24 + 1 + write-only + + + LEDC_TASK_TIMER1_RST_ST_CLR + Configures whether or not to clear LEDC_task_timer1_rst trigger status.\\0: Invalid, No effect\\1: Clear + 25 + 1 + write-only + + + LEDC_TASK_TIMER2_RST_ST_CLR + Configures whether or not to clear LEDC_task_timer2_rst trigger status.\\0: Invalid, No effect\\1: Clear + 26 + 1 + write-only + + + LEDC_TASK_TIMER3_RST_ST_CLR + Configures whether or not to clear LEDC_task_timer3_rst trigger status.\\0: Invalid, No effect\\1: Clear + 27 + 1 + write-only + + + LEDC_TASK_TIMER0_RESUME_ST_CLR + Configures whether or not to clear LEDC_task_timer0_resume trigger status.\\0: Invalid, No effect\\1: Clear + 28 + 1 + write-only + + + LEDC_TASK_TIMER1_RESUME_ST_CLR + Configures whether or not to clear LEDC_task_timer1_resume trigger status.\\0: Invalid, No effect\\1: Clear + 29 + 1 + write-only + + + LEDC_TASK_TIMER2_RESUME_ST_CLR + Configures whether or not to clear LEDC_task_timer2_resume trigger status.\\0: Invalid, No effect\\1: Clear + 30 + 1 + write-only + + + LEDC_TASK_TIMER3_RESUME_ST_CLR + Configures whether or not to clear LEDC_task_timer3_resume trigger status.\\0: Invalid, No effect\\1: Clear + 31 + 1 + write-only + + + + + TASK_ST2 + Tasks trigger status register + 0x1F8 + 0x20 + + + LEDC_TASK_TIMER0_PAUSE_ST + Represents LEDC_task_timer0_pause trigger status.\\0: Not triggered\\1: Triggered + 0 + 1 + read-write + + + LEDC_TASK_TIMER1_PAUSE_ST + Represents LEDC_task_timer1_pause trigger status.\\0: Not triggered\\1: Triggered + 1 + 1 + read-write + + + LEDC_TASK_TIMER2_PAUSE_ST + Represents LEDC_task_timer2_pause trigger status.\\0: Not triggered\\1: Triggered + 2 + 1 + read-write + + + LEDC_TASK_TIMER3_PAUSE_ST + Represents LEDC_task_timer3_pause trigger status.\\0: Not triggered\\1: Triggered + 3 + 1 + read-write + + + LEDC_TASK_GAMMA_RESTART_CH0_ST + Represents LEDC_task_gamma_restart_ch0 trigger status.\\0: Not triggered\\1: Triggered + 4 + 1 + read-write + + + LEDC_TASK_GAMMA_RESTART_CH1_ST + Represents LEDC_task_gamma_restart_ch1 trigger status.\\0: Not triggered\\1: Triggered + 5 + 1 + read-write + + + LEDC_TASK_GAMMA_RESTART_CH2_ST + Represents LEDC_task_gamma_restart_ch2 trigger status.\\0: Not triggered\\1: Triggered + 6 + 1 + read-write + + + LEDC_TASK_GAMMA_RESTART_CH3_ST + Represents LEDC_task_gamma_restart_ch3 trigger status.\\0: Not triggered\\1: Triggered + 7 + 1 + read-write + + + LEDC_TASK_GAMMA_RESTART_CH4_ST + Represents LEDC_task_gamma_restart_ch4 trigger status.\\0: Not triggered\\1: Triggered + 8 + 1 + read-write + + + LEDC_TASK_GAMMA_RESTART_CH5_ST + Represents LEDC_task_gamma_restart_ch5 trigger status.\\0: Not triggered\\1: Triggered + 9 + 1 + read-write + + + LEDC_TASK_GAMMA_RESTART_CH6_ST + Represents LEDC_task_gamma_restart_ch6 trigger status.\\0: Not triggered\\1: Triggered + 10 + 1 + read-write + + + LEDC_TASK_GAMMA_RESTART_CH7_ST + Represents LEDC_task_gamma_restart_ch7 trigger status.\\0: Not triggered\\1: Triggered + 11 + 1 + read-write + + + LEDC_TASK_GAMMA_PAUSE_CH0_ST + Represents LEDC_task_gamma_pause_ch0 trigger status.\\0: Not triggered\\1: Triggered + 12 + 1 + read-write + + + LEDC_TASK_GAMMA_PAUSE_CH1_ST + Represents LEDC_task_gamma_pause_ch1 trigger status.\\0: Not triggered\\1: Triggered + 13 + 1 + read-write + + + LEDC_TASK_GAMMA_PAUSE_CH2_ST + Represents LEDC_task_gamma_pause_ch2 trigger status.\\0: Not triggered\\1: Triggered + 14 + 1 + read-write + + + LEDC_TASK_GAMMA_PAUSE_CH3_ST + Represents LEDC_task_gamma_pause_ch3 trigger status.\\0: Not triggered\\1: Triggered + 15 + 1 + read-write + + + LEDC_TASK_GAMMA_PAUSE_CH4_ST + Represents LEDC_task_gamma_pause_ch4 trigger status.\\0: Not triggered\\1: Triggered + 16 + 1 + read-write + + + LEDC_TASK_GAMMA_PAUSE_CH5_ST + Represents LEDC_task_gamma_pause_ch5 trigger status.\\0: Not triggered\\1: Triggered + 17 + 1 + read-write + + + LEDC_TASK_GAMMA_PAUSE_CH6_ST + Represents LEDC_task_gamma_pause_ch6 trigger status.\\0: Not triggered\\1: Triggered + 18 + 1 + read-write + + + LEDC_TASK_GAMMA_PAUSE_CH7_ST + Represents LEDC_task_gamma_pause_ch7 trigger status.\\0: Not triggered\\1: Triggered + 19 + 1 + read-write + + + LEDC_TASK_GAMMA_RESUME_CH0_ST + Represents LEDC_task_gamma_resume_ch0 trigger status.\\0: Not triggered\\1: Triggered + 20 + 1 + read-write + + + LEDC_TASK_GAMMA_RESUME_CH1_ST + Represents LEDC_task_gamma_resume_ch1 trigger status.\\0: Not triggered\\1: Triggered + 21 + 1 + read-write + + + LEDC_TASK_GAMMA_RESUME_CH2_ST + Represents LEDC_task_gamma_resume_ch2 trigger status.\\0: Not triggered\\1: Triggered + 22 + 1 + read-write + + + LEDC_TASK_GAMMA_RESUME_CH3_ST + Represents LEDC_task_gamma_resume_ch3 trigger status.\\0: Not triggered\\1: Triggered + 23 + 1 + read-write + + + LEDC_TASK_GAMMA_RESUME_CH4_ST + Represents LEDC_task_gamma_resume_ch4 trigger status.\\0: Not triggered\\1: Triggered + 24 + 1 + read-write + + + LEDC_TASK_GAMMA_RESUME_CH5_ST + Represents LEDC_task_gamma_resume_ch5 trigger status.\\0: Not triggered\\1: Triggered + 25 + 1 + read-write + + + LEDC_TASK_GAMMA_RESUME_CH6_ST + Represents LEDC_task_gamma_resume_ch6 trigger status.\\0: Not triggered\\1: Triggered + 26 + 1 + read-write + + + LEDC_TASK_GAMMA_RESUME_CH7_ST + Represents LEDC_task_gamma_resume_ch7 trigger status.\\0: Not triggered\\1: Triggered + 27 + 1 + read-write + + + TG0_TASK_CNT_START_TIMER0_ST + Represents TG0_task_cnt_start_timer0 trigger status.\\0: Not triggered\\1: Triggered + 28 + 1 + read-write + + + TG0_TASK_ALARM_START_TIMER0_ST + Represents TG0_task_alarm_start_timer0 trigger status.\\0: Not triggered\\1: Triggered + 29 + 1 + read-write + + + TG0_TASK_CNT_STOP_TIMER0_ST + Represents TG0_task_cnt_stop_timer0 trigger status.\\0: Not triggered\\1: Triggered + 30 + 1 + read-write + + + TG0_TASK_CNT_RELOAD_TIMER0_ST + Represents TG0_task_cnt_reload_timer0 trigger status.\\0: Not triggered\\1: Triggered + 31 + 1 + read-write + + + + + TASK_ST2_CLR + Tasks trigger status clear register + 0x1FC + 0x20 + + + LEDC_TASK_TIMER0_PAUSE_ST_CLR + Configures whether or not to clear LEDC_task_timer0_pause trigger status.\\0: Invalid, No effect\\1: Clear + 0 + 1 + write-only + + + LEDC_TASK_TIMER1_PAUSE_ST_CLR + Configures whether or not to clear LEDC_task_timer1_pause trigger status.\\0: Invalid, No effect\\1: Clear + 1 + 1 + write-only + + + LEDC_TASK_TIMER2_PAUSE_ST_CLR + Configures whether or not to clear LEDC_task_timer2_pause trigger status.\\0: Invalid, No effect\\1: Clear + 2 + 1 + write-only + + + LEDC_TASK_TIMER3_PAUSE_ST_CLR + Configures whether or not to clear LEDC_task_timer3_pause trigger status.\\0: Invalid, No effect\\1: Clear + 3 + 1 + write-only + + + LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR + Configures whether or not to clear LEDC_task_gamma_restart_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 4 + 1 + write-only + + + LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR + Configures whether or not to clear LEDC_task_gamma_restart_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 5 + 1 + write-only + + + LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR + Configures whether or not to clear LEDC_task_gamma_restart_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 6 + 1 + write-only + + + LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR + Configures whether or not to clear LEDC_task_gamma_restart_ch3 trigger status.\\0: Invalid, No effect\\1: Clear + 7 + 1 + write-only + + + LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR + Configures whether or not to clear LEDC_task_gamma_restart_ch4 trigger status.\\0: Invalid, No effect\\1: Clear + 8 + 1 + write-only + + + LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR + Configures whether or not to clear LEDC_task_gamma_restart_ch5 trigger status.\\0: Invalid, No effect\\1: Clear + 9 + 1 + write-only + + + LEDC_TASK_GAMMA_RESTART_CH6_ST_CLR + Configures whether or not to clear LEDC_task_gamma_restart_ch6 trigger status.\\0: Invalid, No effect\\1: Clear + 10 + 1 + write-only + + + LEDC_TASK_GAMMA_RESTART_CH7_ST_CLR + Configures whether or not to clear LEDC_task_gamma_restart_ch7 trigger status.\\0: Invalid, No effect\\1: Clear + 11 + 1 + write-only + + + LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR + Configures whether or not to clear LEDC_task_gamma_pause_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 12 + 1 + write-only + + + LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR + Configures whether or not to clear LEDC_task_gamma_pause_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 13 + 1 + write-only + + + LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR + Configures whether or not to clear LEDC_task_gamma_pause_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 14 + 1 + write-only + + + LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR + Configures whether or not to clear LEDC_task_gamma_pause_ch3 trigger status.\\0: Invalid, No effect\\1: Clear + 15 + 1 + write-only + + + LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR + Configures whether or not to clear LEDC_task_gamma_pause_ch4 trigger status.\\0: Invalid, No effect\\1: Clear + 16 + 1 + write-only + + + LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR + Configures whether or not to clear LEDC_task_gamma_pause_ch5 trigger status.\\0: Invalid, No effect\\1: Clear + 17 + 1 + write-only + + + LEDC_TASK_GAMMA_PAUSE_CH6_ST_CLR + Configures whether or not to clear LEDC_task_gamma_pause_ch6 trigger status.\\0: Invalid, No effect\\1: Clear + 18 + 1 + write-only + + + LEDC_TASK_GAMMA_PAUSE_CH7_ST_CLR + Configures whether or not to clear LEDC_task_gamma_pause_ch7 trigger status.\\0: Invalid, No effect\\1: Clear + 19 + 1 + write-only + + + LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR + Configures whether or not to clear LEDC_task_gamma_resume_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 20 + 1 + write-only + + + LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR + Configures whether or not to clear LEDC_task_gamma_resume_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 21 + 1 + write-only + + + LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR + Configures whether or not to clear LEDC_task_gamma_resume_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 22 + 1 + write-only + + + LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR + Configures whether or not to clear LEDC_task_gamma_resume_ch3 trigger status.\\0: Invalid, No effect\\1: Clear + 23 + 1 + write-only + + + LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR + Configures whether or not to clear LEDC_task_gamma_resume_ch4 trigger status.\\0: Invalid, No effect\\1: Clear + 24 + 1 + write-only + + + LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR + Configures whether or not to clear LEDC_task_gamma_resume_ch5 trigger status.\\0: Invalid, No effect\\1: Clear + 25 + 1 + write-only + + + LEDC_TASK_GAMMA_RESUME_CH6_ST_CLR + Configures whether or not to clear LEDC_task_gamma_resume_ch6 trigger status.\\0: Invalid, No effect\\1: Clear + 26 + 1 + write-only + + + LEDC_TASK_GAMMA_RESUME_CH7_ST_CLR + Configures whether or not to clear LEDC_task_gamma_resume_ch7 trigger status.\\0: Invalid, No effect\\1: Clear + 27 + 1 + write-only + + + TG0_TASK_CNT_START_TIMER0_ST_CLR + Configures whether or not to clear TG0_task_cnt_start_timer0 trigger status.\\0: Invalid, No effect\\1: Clear + 28 + 1 + write-only + + + TG0_TASK_ALARM_START_TIMER0_ST_CLR + Configures whether or not to clear TG0_task_alarm_start_timer0 trigger status.\\0: Invalid, No effect\\1: Clear + 29 + 1 + write-only + + + TG0_TASK_CNT_STOP_TIMER0_ST_CLR + Configures whether or not to clear TG0_task_cnt_stop_timer0 trigger status.\\0: Invalid, No effect\\1: Clear + 30 + 1 + write-only + + + TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR + Configures whether or not to clear TG0_task_cnt_reload_timer0 trigger status.\\0: Invalid, No effect\\1: Clear + 31 + 1 + write-only + + + + + TASK_ST3 + Tasks trigger status register + 0x200 + 0x20 + + + TG0_TASK_CNT_CAP_TIMER0_ST + Represents TG0_task_cnt_cap_timer0 trigger status.\\0: Not triggered\\1: Triggered + 0 + 1 + read-write + + + TG0_TASK_CNT_START_TIMER1_ST + Represents TG0_task_cnt_start_timer1 trigger status.\\0: Not triggered\\1: Triggered + 1 + 1 + read-write + + + TG0_TASK_ALARM_START_TIMER1_ST + Represents TG0_task_alarm_start_timer1 trigger status.\\0: Not triggered\\1: Triggered + 2 + 1 + read-write + + + TG0_TASK_CNT_STOP_TIMER1_ST + Represents TG0_task_cnt_stop_timer1 trigger status.\\0: Not triggered\\1: Triggered + 3 + 1 + read-write + + + TG0_TASK_CNT_RELOAD_TIMER1_ST + Represents TG0_task_cnt_reload_timer1 trigger status.\\0: Not triggered\\1: Triggered + 4 + 1 + read-write + + + TG0_TASK_CNT_CAP_TIMER1_ST + Represents TG0_task_cnt_cap_timer1 trigger status.\\0: Not triggered\\1: Triggered + 5 + 1 + read-write + + + TG1_TASK_CNT_START_TIMER0_ST + Represents TG1_task_cnt_start_timer0 trigger status.\\0: Not triggered\\1: Triggered + 6 + 1 + read-write + + + TG1_TASK_ALARM_START_TIMER0_ST + Represents TG1_task_alarm_start_timer0 trigger status.\\0: Not triggered\\1: Triggered + 7 + 1 + read-write + + + TG1_TASK_CNT_STOP_TIMER0_ST + Represents TG1_task_cnt_stop_timer0 trigger status.\\0: Not triggered\\1: Triggered + 8 + 1 + read-write + + + TG1_TASK_CNT_RELOAD_TIMER0_ST + Represents TG1_task_cnt_reload_timer0 trigger status.\\0: Not triggered\\1: Triggered + 9 + 1 + read-write + + + TG1_TASK_CNT_CAP_TIMER0_ST + Represents TG1_task_cnt_cap_timer0 trigger status.\\0: Not triggered\\1: Triggered + 10 + 1 + read-write + + + TG1_TASK_CNT_START_TIMER1_ST + Represents TG1_task_cnt_start_timer1 trigger status.\\0: Not triggered\\1: Triggered + 11 + 1 + read-write + + + TG1_TASK_ALARM_START_TIMER1_ST + Represents TG1_task_alarm_start_timer1 trigger status.\\0: Not triggered\\1: Triggered + 12 + 1 + read-write + + + TG1_TASK_CNT_STOP_TIMER1_ST + Represents TG1_task_cnt_stop_timer1 trigger status.\\0: Not triggered\\1: Triggered + 13 + 1 + read-write + + + TG1_TASK_CNT_RELOAD_TIMER1_ST + Represents TG1_task_cnt_reload_timer1 trigger status.\\0: Not triggered\\1: Triggered + 14 + 1 + read-write + + + TG1_TASK_CNT_CAP_TIMER1_ST + Represents TG1_task_cnt_cap_timer1 trigger status.\\0: Not triggered\\1: Triggered + 15 + 1 + read-write + + + MCPWM0_TASK_CMPR0_A_UP_ST + Represents MCPWM0_task_cmpr0_a_up trigger status.\\0: Not triggered\\1: Triggered + 16 + 1 + read-write + + + MCPWM0_TASK_CMPR1_A_UP_ST + Represents MCPWM0_task_cmpr1_a_up trigger status.\\0: Not triggered\\1: Triggered + 17 + 1 + read-write + + + MCPWM0_TASK_CMPR2_A_UP_ST + Represents MCPWM0_task_cmpr2_a_up trigger status.\\0: Not triggered\\1: Triggered + 18 + 1 + read-write + + + MCPWM0_TASK_CMPR0_B_UP_ST + Represents MCPWM0_task_cmpr0_b_up trigger status.\\0: Not triggered\\1: Triggered + 19 + 1 + read-write + + + MCPWM0_TASK_CMPR1_B_UP_ST + Represents MCPWM0_task_cmpr1_b_up trigger status.\\0: Not triggered\\1: Triggered + 20 + 1 + read-write + + + MCPWM0_TASK_CMPR2_B_UP_ST + Represents MCPWM0_task_cmpr2_b_up trigger status.\\0: Not triggered\\1: Triggered + 21 + 1 + read-write + + + MCPWM0_TASK_GEN_STOP_ST + Represents MCPWM0_task_gen_stop trigger status.\\0: Not triggered\\1: Triggered + 22 + 1 + read-write + + + MCPWM0_TASK_TIMER0_SYN_ST + Represents MCPWM0_task_timer0_syn trigger status.\\0: Not triggered\\1: Triggered + 23 + 1 + read-write + + + MCPWM0_TASK_TIMER1_SYN_ST + Represents MCPWM0_task_timer1_syn trigger status.\\0: Not triggered\\1: Triggered + 24 + 1 + read-write + + + MCPWM0_TASK_TIMER2_SYN_ST + Represents MCPWM0_task_timer2_syn trigger status.\\0: Not triggered\\1: Triggered + 25 + 1 + read-write + + + MCPWM0_TASK_TIMER0_PERIOD_UP_ST + Represents MCPWM0_task_timer0_period_up trigger status.\\0: Not triggered\\1: Triggered + 26 + 1 + read-write + + + MCPWM0_TASK_TIMER1_PERIOD_UP_ST + Represents MCPWM0_task_timer1_period_up trigger status.\\0: Not triggered\\1: Triggered + 27 + 1 + read-write + + + MCPWM0_TASK_TIMER2_PERIOD_UP_ST + Represents MCPWM0_task_timer2_period_up trigger status.\\0: Not triggered\\1: Triggered + 28 + 1 + read-write + + + MCPWM0_TASK_TZ0_OST_ST + Represents MCPWM0_task_tz0_ost trigger status.\\0: Not triggered\\1: Triggered + 29 + 1 + read-write + + + MCPWM0_TASK_TZ1_OST_ST + Represents MCPWM0_task_tz1_ost trigger status.\\0: Not triggered\\1: Triggered + 30 + 1 + read-write + + + MCPWM0_TASK_TZ2_OST_ST + Represents MCPWM0_task_tz2_ost trigger status.\\0: Not triggered\\1: Triggered + 31 + 1 + read-write + + + + + TASK_ST3_CLR + Tasks trigger status clear register + 0x204 + 0x20 + + + TG0_TASK_CNT_CAP_TIMER0_ST_CLR + Configures whether or not to clear TG0_task_cnt_cap_timer0 trigger status.\\0: Invalid, No effect\\1: Clear + 0 + 1 + write-only + + + TG0_TASK_CNT_START_TIMER1_ST_CLR + Configures whether or not to clear TG0_task_cnt_start_timer1 trigger status.\\0: Invalid, No effect\\1: Clear + 1 + 1 + write-only + + + TG0_TASK_ALARM_START_TIMER1_ST_CLR + Configures whether or not to clear TG0_task_alarm_start_timer1 trigger status.\\0: Invalid, No effect\\1: Clear + 2 + 1 + write-only + + + TG0_TASK_CNT_STOP_TIMER1_ST_CLR + Configures whether or not to clear TG0_task_cnt_stop_timer1 trigger status.\\0: Invalid, No effect\\1: Clear + 3 + 1 + write-only + + + TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR + Configures whether or not to clear TG0_task_cnt_reload_timer1 trigger status.\\0: Invalid, No effect\\1: Clear + 4 + 1 + write-only + + + TG0_TASK_CNT_CAP_TIMER1_ST_CLR + Configures whether or not to clear TG0_task_cnt_cap_timer1 trigger status.\\0: Invalid, No effect\\1: Clear + 5 + 1 + write-only + + + TG1_TASK_CNT_START_TIMER0_ST_CLR + Configures whether or not to clear TG1_task_cnt_start_timer0 trigger status.\\0: Invalid, No effect\\1: Clear + 6 + 1 + write-only + + + TG1_TASK_ALARM_START_TIMER0_ST_CLR + Configures whether or not to clear TG1_task_alarm_start_timer0 trigger status.\\0: Invalid, No effect\\1: Clear + 7 + 1 + write-only + + + TG1_TASK_CNT_STOP_TIMER0_ST_CLR + Configures whether or not to clear TG1_task_cnt_stop_timer0 trigger status.\\0: Invalid, No effect\\1: Clear + 8 + 1 + write-only + + + TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR + Configures whether or not to clear TG1_task_cnt_reload_timer0 trigger status.\\0: Invalid, No effect\\1: Clear + 9 + 1 + write-only + + + TG1_TASK_CNT_CAP_TIMER0_ST_CLR + Configures whether or not to clear TG1_task_cnt_cap_timer0 trigger status.\\0: Invalid, No effect\\1: Clear + 10 + 1 + write-only + + + TG1_TASK_CNT_START_TIMER1_ST_CLR + Configures whether or not to clear TG1_task_cnt_start_timer1 trigger status.\\0: Invalid, No effect\\1: Clear + 11 + 1 + write-only + + + TG1_TASK_ALARM_START_TIMER1_ST_CLR + Configures whether or not to clear TG1_task_alarm_start_timer1 trigger status.\\0: Invalid, No effect\\1: Clear + 12 + 1 + write-only + + + TG1_TASK_CNT_STOP_TIMER1_ST_CLR + Configures whether or not to clear TG1_task_cnt_stop_timer1 trigger status.\\0: Invalid, No effect\\1: Clear + 13 + 1 + write-only + + + TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR + Configures whether or not to clear TG1_task_cnt_reload_timer1 trigger status.\\0: Invalid, No effect\\1: Clear + 14 + 1 + write-only + + + TG1_TASK_CNT_CAP_TIMER1_ST_CLR + Configures whether or not to clear TG1_task_cnt_cap_timer1 trigger status.\\0: Invalid, No effect\\1: Clear + 15 + 1 + write-only + + + MCPWM0_TASK_CMPR0_A_UP_ST_CLR + Configures whether or not to clear MCPWM0_task_cmpr0_a_up trigger status.\\0: Invalid, No effect\\1: Clear + 16 + 1 + write-only + + + MCPWM0_TASK_CMPR1_A_UP_ST_CLR + Configures whether or not to clear MCPWM0_task_cmpr1_a_up trigger status.\\0: Invalid, No effect\\1: Clear + 17 + 1 + write-only + + + MCPWM0_TASK_CMPR2_A_UP_ST_CLR + Configures whether or not to clear MCPWM0_task_cmpr2_a_up trigger status.\\0: Invalid, No effect\\1: Clear + 18 + 1 + write-only + + + MCPWM0_TASK_CMPR0_B_UP_ST_CLR + Configures whether or not to clear MCPWM0_task_cmpr0_b_up trigger status.\\0: Invalid, No effect\\1: Clear + 19 + 1 + write-only + + + MCPWM0_TASK_CMPR1_B_UP_ST_CLR + Configures whether or not to clear MCPWM0_task_cmpr1_b_up trigger status.\\0: Invalid, No effect\\1: Clear + 20 + 1 + write-only + + + MCPWM0_TASK_CMPR2_B_UP_ST_CLR + Configures whether or not to clear MCPWM0_task_cmpr2_b_up trigger status.\\0: Invalid, No effect\\1: Clear + 21 + 1 + write-only + + + MCPWM0_TASK_GEN_STOP_ST_CLR + Configures whether or not to clear MCPWM0_task_gen_stop trigger status.\\0: Invalid, No effect\\1: Clear + 22 + 1 + write-only + + + MCPWM0_TASK_TIMER0_SYN_ST_CLR + Configures whether or not to clear MCPWM0_task_timer0_syn trigger status.\\0: Invalid, No effect\\1: Clear + 23 + 1 + write-only + + + MCPWM0_TASK_TIMER1_SYN_ST_CLR + Configures whether or not to clear MCPWM0_task_timer1_syn trigger status.\\0: Invalid, No effect\\1: Clear + 24 + 1 + write-only + + + MCPWM0_TASK_TIMER2_SYN_ST_CLR + Configures whether or not to clear MCPWM0_task_timer2_syn trigger status.\\0: Invalid, No effect\\1: Clear + 25 + 1 + write-only + + + MCPWM0_TASK_TIMER0_PERIOD_UP_ST_CLR + Configures whether or not to clear MCPWM0_task_timer0_period_up trigger status.\\0: Invalid, No effect\\1: Clear + 26 + 1 + write-only + + + MCPWM0_TASK_TIMER1_PERIOD_UP_ST_CLR + Configures whether or not to clear MCPWM0_task_timer1_period_up trigger status.\\0: Invalid, No effect\\1: Clear + 27 + 1 + write-only + + + MCPWM0_TASK_TIMER2_PERIOD_UP_ST_CLR + Configures whether or not to clear MCPWM0_task_timer2_period_up trigger status.\\0: Invalid, No effect\\1: Clear + 28 + 1 + write-only + + + MCPWM0_TASK_TZ0_OST_ST_CLR + Configures whether or not to clear MCPWM0_task_tz0_ost trigger status.\\0: Invalid, No effect\\1: Clear + 29 + 1 + write-only + + + MCPWM0_TASK_TZ1_OST_ST_CLR + Configures whether or not to clear MCPWM0_task_tz1_ost trigger status.\\0: Invalid, No effect\\1: Clear + 30 + 1 + write-only + + + MCPWM0_TASK_TZ2_OST_ST_CLR + Configures whether or not to clear MCPWM0_task_tz2_ost trigger status.\\0: Invalid, No effect\\1: Clear + 31 + 1 + write-only + + + + + TASK_ST4 + Tasks trigger status register + 0x208 + 0x20 + + + MCPWM0_TASK_CLR0_OST_ST + Represents MCPWM0_task_clr0_ost trigger status.\\0: Not triggered\\1: Triggered + 0 + 1 + read-write + + + MCPWM0_TASK_CLR1_OST_ST + Represents MCPWM0_task_clr1_ost trigger status.\\0: Not triggered\\1: Triggered + 1 + 1 + read-write + + + MCPWM0_TASK_CLR2_OST_ST + Represents MCPWM0_task_clr2_ost trigger status.\\0: Not triggered\\1: Triggered + 2 + 1 + read-write + + + MCPWM0_TASK_CAP0_ST + Represents MCPWM0_task_cap0 trigger status.\\0: Not triggered\\1: Triggered + 3 + 1 + read-write + + + MCPWM0_TASK_CAP1_ST + Represents MCPWM0_task_cap1 trigger status.\\0: Not triggered\\1: Triggered + 4 + 1 + read-write + + + MCPWM0_TASK_CAP2_ST + Represents MCPWM0_task_cap2 trigger status.\\0: Not triggered\\1: Triggered + 5 + 1 + read-write + + + MCPWM1_TASK_CMPR0_A_UP_ST + Represents MCPWM1_task_cmpr0_a_up trigger status.\\0: Not triggered\\1: Triggered + 6 + 1 + read-write + + + MCPWM1_TASK_CMPR1_A_UP_ST + Represents MCPWM1_task_cmpr1_a_up trigger status.\\0: Not triggered\\1: Triggered + 7 + 1 + read-write + + + MCPWM1_TASK_CMPR2_A_UP_ST + Represents MCPWM1_task_cmpr2_a_up trigger status.\\0: Not triggered\\1: Triggered + 8 + 1 + read-write + + + MCPWM1_TASK_CMPR0_B_UP_ST + Represents MCPWM1_task_cmpr0_b_up trigger status.\\0: Not triggered\\1: Triggered + 9 + 1 + read-write + + + MCPWM1_TASK_CMPR1_B_UP_ST + Represents MCPWM1_task_cmpr1_b_up trigger status.\\0: Not triggered\\1: Triggered + 10 + 1 + read-write + + + MCPWM1_TASK_CMPR2_B_UP_ST + Represents MCPWM1_task_cmpr2_b_up trigger status.\\0: Not triggered\\1: Triggered + 11 + 1 + read-write + + + MCPWM1_TASK_GEN_STOP_ST + Represents MCPWM1_task_gen_stop trigger status.\\0: Not triggered\\1: Triggered + 12 + 1 + read-write + + + MCPWM1_TASK_TIMER0_SYN_ST + Represents MCPWM1_task_timer0_syn trigger status.\\0: Not triggered\\1: Triggered + 13 + 1 + read-write + + + MCPWM1_TASK_TIMER1_SYN_ST + Represents MCPWM1_task_timer1_syn trigger status.\\0: Not triggered\\1: Triggered + 14 + 1 + read-write + + + MCPWM1_TASK_TIMER2_SYN_ST + Represents MCPWM1_task_timer2_syn trigger status.\\0: Not triggered\\1: Triggered + 15 + 1 + read-write + + + MCPWM1_TASK_TIMER0_PERIOD_UP_ST + Represents MCPWM1_task_timer0_period_up trigger status.\\0: Not triggered\\1: Triggered + 16 + 1 + read-write + + + MCPWM1_TASK_TIMER1_PERIOD_UP_ST + Represents MCPWM1_task_timer1_period_up trigger status.\\0: Not triggered\\1: Triggered + 17 + 1 + read-write + + + MCPWM1_TASK_TIMER2_PERIOD_UP_ST + Represents MCPWM1_task_timer2_period_up trigger status.\\0: Not triggered\\1: Triggered + 18 + 1 + read-write + + + MCPWM1_TASK_TZ0_OST_ST + Represents MCPWM1_task_tz0_ost trigger status.\\0: Not triggered\\1: Triggered + 19 + 1 + read-write + + + MCPWM1_TASK_TZ1_OST_ST + Represents MCPWM1_task_tz1_ost trigger status.\\0: Not triggered\\1: Triggered + 20 + 1 + read-write + + + MCPWM1_TASK_TZ2_OST_ST + Represents MCPWM1_task_tz2_ost trigger status.\\0: Not triggered\\1: Triggered + 21 + 1 + read-write + + + MCPWM1_TASK_CLR0_OST_ST + Represents MCPWM1_task_clr0_ost trigger status.\\0: Not triggered\\1: Triggered + 22 + 1 + read-write + + + MCPWM1_TASK_CLR1_OST_ST + Represents MCPWM1_task_clr1_ost trigger status.\\0: Not triggered\\1: Triggered + 23 + 1 + read-write + + + MCPWM1_TASK_CLR2_OST_ST + Represents MCPWM1_task_clr2_ost trigger status.\\0: Not triggered\\1: Triggered + 24 + 1 + read-write + + + MCPWM1_TASK_CAP0_ST + Represents MCPWM1_task_cap0 trigger status.\\0: Not triggered\\1: Triggered + 25 + 1 + read-write + + + MCPWM1_TASK_CAP1_ST + Represents MCPWM1_task_cap1 trigger status.\\0: Not triggered\\1: Triggered + 26 + 1 + read-write + + + MCPWM1_TASK_CAP2_ST + Represents MCPWM1_task_cap2 trigger status.\\0: Not triggered\\1: Triggered + 27 + 1 + read-write + + + ADC_TASK_SAMPLE0_ST + Represents ADC_task_sample0 trigger status.\\0: Not triggered\\1: Triggered + 28 + 1 + read-write + + + ADC_TASK_SAMPLE1_ST + Represents ADC_task_sample1 trigger status.\\0: Not triggered\\1: Triggered + 29 + 1 + read-write + + + ADC_TASK_START0_ST + Represents ADC_task_start0 trigger status.\\0: Not triggered\\1: Triggered + 30 + 1 + read-write + + + ADC_TASK_STOP0_ST + Represents ADC_task_stop0 trigger status.\\0: Not triggered\\1: Triggered + 31 + 1 + read-write + + + + + TASK_ST4_CLR + Tasks trigger status clear register + 0x20C + 0x20 + + + MCPWM0_TASK_CLR0_OST_ST_CLR + Configures whether or not to clear MCPWM0_task_clr0_ost trigger status.\\0: Invalid, No effect\\1: Clear + 0 + 1 + write-only + + + MCPWM0_TASK_CLR1_OST_ST_CLR + Configures whether or not to clear MCPWM0_task_clr1_ost trigger status.\\0: Invalid, No effect\\1: Clear + 1 + 1 + write-only + + + MCPWM0_TASK_CLR2_OST_ST_CLR + Configures whether or not to clear MCPWM0_task_clr2_ost trigger status.\\0: Invalid, No effect\\1: Clear + 2 + 1 + write-only + + + MCPWM0_TASK_CAP0_ST_CLR + Configures whether or not to clear MCPWM0_task_cap0 trigger status.\\0: Invalid, No effect\\1: Clear + 3 + 1 + write-only + + + MCPWM0_TASK_CAP1_ST_CLR + Configures whether or not to clear MCPWM0_task_cap1 trigger status.\\0: Invalid, No effect\\1: Clear + 4 + 1 + write-only + + + MCPWM0_TASK_CAP2_ST_CLR + Configures whether or not to clear MCPWM0_task_cap2 trigger status.\\0: Invalid, No effect\\1: Clear + 5 + 1 + write-only + + + MCPWM1_TASK_CMPR0_A_UP_ST_CLR + Configures whether or not to clear MCPWM1_task_cmpr0_a_up trigger status.\\0: Invalid, No effect\\1: Clear + 6 + 1 + write-only + + + MCPWM1_TASK_CMPR1_A_UP_ST_CLR + Configures whether or not to clear MCPWM1_task_cmpr1_a_up trigger status.\\0: Invalid, No effect\\1: Clear + 7 + 1 + write-only + + + MCPWM1_TASK_CMPR2_A_UP_ST_CLR + Configures whether or not to clear MCPWM1_task_cmpr2_a_up trigger status.\\0: Invalid, No effect\\1: Clear + 8 + 1 + write-only + + + MCPWM1_TASK_CMPR0_B_UP_ST_CLR + Configures whether or not to clear MCPWM1_task_cmpr0_b_up trigger status.\\0: Invalid, No effect\\1: Clear + 9 + 1 + write-only + + + MCPWM1_TASK_CMPR1_B_UP_ST_CLR + Configures whether or not to clear MCPWM1_task_cmpr1_b_up trigger status.\\0: Invalid, No effect\\1: Clear + 10 + 1 + write-only + + + MCPWM1_TASK_CMPR2_B_UP_ST_CLR + Configures whether or not to clear MCPWM1_task_cmpr2_b_up trigger status.\\0: Invalid, No effect\\1: Clear + 11 + 1 + write-only + + + MCPWM1_TASK_GEN_STOP_ST_CLR + Configures whether or not to clear MCPWM1_task_gen_stop trigger status.\\0: Invalid, No effect\\1: Clear + 12 + 1 + write-only + + + MCPWM1_TASK_TIMER0_SYN_ST_CLR + Configures whether or not to clear MCPWM1_task_timer0_syn trigger status.\\0: Invalid, No effect\\1: Clear + 13 + 1 + write-only + + + MCPWM1_TASK_TIMER1_SYN_ST_CLR + Configures whether or not to clear MCPWM1_task_timer1_syn trigger status.\\0: Invalid, No effect\\1: Clear + 14 + 1 + write-only + + + MCPWM1_TASK_TIMER2_SYN_ST_CLR + Configures whether or not to clear MCPWM1_task_timer2_syn trigger status.\\0: Invalid, No effect\\1: Clear + 15 + 1 + write-only + + + MCPWM1_TASK_TIMER0_PERIOD_UP_ST_CLR + Configures whether or not to clear MCPWM1_task_timer0_period_up trigger status.\\0: Invalid, No effect\\1: Clear + 16 + 1 + write-only + + + MCPWM1_TASK_TIMER1_PERIOD_UP_ST_CLR + Configures whether or not to clear MCPWM1_task_timer1_period_up trigger status.\\0: Invalid, No effect\\1: Clear + 17 + 1 + write-only + + + MCPWM1_TASK_TIMER2_PERIOD_UP_ST_CLR + Configures whether or not to clear MCPWM1_task_timer2_period_up trigger status.\\0: Invalid, No effect\\1: Clear + 18 + 1 + write-only + + + MCPWM1_TASK_TZ0_OST_ST_CLR + Configures whether or not to clear MCPWM1_task_tz0_ost trigger status.\\0: Invalid, No effect\\1: Clear + 19 + 1 + write-only + + + MCPWM1_TASK_TZ1_OST_ST_CLR + Configures whether or not to clear MCPWM1_task_tz1_ost trigger status.\\0: Invalid, No effect\\1: Clear + 20 + 1 + write-only + + + MCPWM1_TASK_TZ2_OST_ST_CLR + Configures whether or not to clear MCPWM1_task_tz2_ost trigger status.\\0: Invalid, No effect\\1: Clear + 21 + 1 + write-only + + + MCPWM1_TASK_CLR0_OST_ST_CLR + Configures whether or not to clear MCPWM1_task_clr0_ost trigger status.\\0: Invalid, No effect\\1: Clear + 22 + 1 + write-only + + + MCPWM1_TASK_CLR1_OST_ST_CLR + Configures whether or not to clear MCPWM1_task_clr1_ost trigger status.\\0: Invalid, No effect\\1: Clear + 23 + 1 + write-only + + + MCPWM1_TASK_CLR2_OST_ST_CLR + Configures whether or not to clear MCPWM1_task_clr2_ost trigger status.\\0: Invalid, No effect\\1: Clear + 24 + 1 + write-only + + + MCPWM1_TASK_CAP0_ST_CLR + Configures whether or not to clear MCPWM1_task_cap0 trigger status.\\0: Invalid, No effect\\1: Clear + 25 + 1 + write-only + + + MCPWM1_TASK_CAP1_ST_CLR + Configures whether or not to clear MCPWM1_task_cap1 trigger status.\\0: Invalid, No effect\\1: Clear + 26 + 1 + write-only + + + MCPWM1_TASK_CAP2_ST_CLR + Configures whether or not to clear MCPWM1_task_cap2 trigger status.\\0: Invalid, No effect\\1: Clear + 27 + 1 + write-only + + + ADC_TASK_SAMPLE0_ST_CLR + Configures whether or not to clear ADC_task_sample0 trigger status.\\0: Invalid, No effect\\1: Clear + 28 + 1 + write-only + + + ADC_TASK_SAMPLE1_ST_CLR + Configures whether or not to clear ADC_task_sample1 trigger status.\\0: Invalid, No effect\\1: Clear + 29 + 1 + write-only + + + ADC_TASK_START0_ST_CLR + Configures whether or not to clear ADC_task_start0 trigger status.\\0: Invalid, No effect\\1: Clear + 30 + 1 + write-only + + + ADC_TASK_STOP0_ST_CLR + Configures whether or not to clear ADC_task_stop0 trigger status.\\0: Invalid, No effect\\1: Clear + 31 + 1 + write-only + + + + + TASK_ST5 + Tasks trigger status register + 0x210 + 0x20 + + + REGDMA_TASK_START0_ST + Represents REGDMA_task_start0 trigger status.\\0: Not triggered\\1: Triggered + 0 + 1 + read-write + + + REGDMA_TASK_START1_ST + Represents REGDMA_task_start1 trigger status.\\0: Not triggered\\1: Triggered + 1 + 1 + read-write + + + REGDMA_TASK_START2_ST + Represents REGDMA_task_start2 trigger status.\\0: Not triggered\\1: Triggered + 2 + 1 + read-write + + + REGDMA_TASK_START3_ST + Represents REGDMA_task_start3 trigger status.\\0: Not triggered\\1: Triggered + 3 + 1 + read-write + + + TMPSNSR_TASK_START_SAMPLE_ST + Represents TMPSNSR_task_start_sample trigger status.\\0: Not triggered\\1: Triggered + 4 + 1 + read-write + + + TMPSNSR_TASK_STOP_SAMPLE_ST + Represents TMPSNSR_task_stop_sample trigger status.\\0: Not triggered\\1: Triggered + 5 + 1 + read-write + + + I2S0_TASK_START_RX_ST + Represents I2S0_task_start_rx trigger status.\\0: Not triggered\\1: Triggered + 6 + 1 + read-write + + + I2S0_TASK_START_TX_ST + Represents I2S0_task_start_tx trigger status.\\0: Not triggered\\1: Triggered + 7 + 1 + read-write + + + I2S0_TASK_STOP_RX_ST + Represents I2S0_task_stop_rx trigger status.\\0: Not triggered\\1: Triggered + 8 + 1 + read-write + + + I2S0_TASK_STOP_TX_ST + Represents I2S0_task_stop_tx trigger status.\\0: Not triggered\\1: Triggered + 9 + 1 + read-write + + + I2S1_TASK_START_RX_ST + Represents I2S1_task_start_rx trigger status.\\0: Not triggered\\1: Triggered + 10 + 1 + read-write + + + I2S1_TASK_START_TX_ST + Represents I2S1_task_start_tx trigger status.\\0: Not triggered\\1: Triggered + 11 + 1 + read-write + + + I2S1_TASK_STOP_RX_ST + Represents I2S1_task_stop_rx trigger status.\\0: Not triggered\\1: Triggered + 12 + 1 + read-write + + + I2S1_TASK_STOP_TX_ST + Represents I2S1_task_stop_tx trigger status.\\0: Not triggered\\1: Triggered + 13 + 1 + read-write + + + I2S2_TASK_START_RX_ST + Represents I2S2_task_start_rx trigger status.\\0: Not triggered\\1: Triggered + 14 + 1 + read-write + + + I2S2_TASK_START_TX_ST + Represents I2S2_task_start_tx trigger status.\\0: Not triggered\\1: Triggered + 15 + 1 + read-write + + + I2S2_TASK_STOP_RX_ST + Represents I2S2_task_stop_rx trigger status.\\0: Not triggered\\1: Triggered + 16 + 1 + read-write + + + I2S2_TASK_STOP_TX_ST + Represents I2S2_task_stop_tx trigger status.\\0: Not triggered\\1: Triggered + 17 + 1 + read-write + + + ULP_TASK_WAKEUP_CPU_ST + Represents ULP_task_wakeup_cpu trigger status.\\0: Not triggered\\1: Triggered + 18 + 1 + read-write + + + ULP_TASK_INT_CPU_ST + Represents ULP_task_int_cpu trigger status.\\0: Not triggered\\1: Triggered + 19 + 1 + read-write + + + RTC_TASK_START_ST + Represents RTC_task_start trigger status.\\0: Not triggered\\1: Triggered + 20 + 1 + read-write + + + RTC_TASK_STOP_ST + Represents RTC_task_stop trigger status.\\0: Not triggered\\1: Triggered + 21 + 1 + read-write + + + RTC_TASK_CLR_ST + Represents RTC_task_clr trigger status.\\0: Not triggered\\1: Triggered + 22 + 1 + read-write + + + RTC_TASK_TRIGGERFLW_ST + Represents RTC_task_triggerflw trigger status.\\0: Not triggered\\1: Triggered + 23 + 1 + read-write + + + PDMA_AHB_TASK_IN_START_CH0_ST + Represents PDMA_AHB_task_in_start_ch0 trigger status.\\0: Not triggered\\1: Triggered + 24 + 1 + read-write + + + PDMA_AHB_TASK_IN_START_CH1_ST + Represents PDMA_AHB_task_in_start_ch1 trigger status.\\0: Not triggered\\1: Triggered + 25 + 1 + read-write + + + PDMA_AHB_TASK_IN_START_CH2_ST + Represents PDMA_AHB_task_in_start_ch2 trigger status.\\0: Not triggered\\1: Triggered + 26 + 1 + read-write + + + PDMA_AHB_TASK_OUT_START_CH0_ST + Represents PDMA_AHB_task_out_start_ch0 trigger status.\\0: Not triggered\\1: Triggered + 27 + 1 + read-write + + + PDMA_AHB_TASK_OUT_START_CH1_ST + Represents PDMA_AHB_task_out_start_ch1 trigger status.\\0: Not triggered\\1: Triggered + 28 + 1 + read-write + + + PDMA_AHB_TASK_OUT_START_CH2_ST + Represents PDMA_AHB_task_out_start_ch2 trigger status.\\0: Not triggered\\1: Triggered + 29 + 1 + read-write + + + PDMA_AXI_TASK_IN_START_CH0_ST + Represents PDMA_AXI_task_in_start_ch0 trigger status.\\0: Not triggered\\1: Triggered + 30 + 1 + read-write + + + PDMA_AXI_TASK_IN_START_CH1_ST + Represents PDMA_AXI_task_in_start_ch1 trigger status.\\0: Not triggered\\1: Triggered + 31 + 1 + read-write + + + + + TASK_ST5_CLR + Tasks trigger status clear register + 0x214 + 0x20 + + + REGDMA_TASK_START0_ST_CLR + Configures whether or not to clear REGDMA_task_start0 trigger status.\\0: Invalid, No effect\\1: Clear + 0 + 1 + write-only + + + REGDMA_TASK_START1_ST_CLR + Configures whether or not to clear REGDMA_task_start1 trigger status.\\0: Invalid, No effect\\1: Clear + 1 + 1 + write-only + + + REGDMA_TASK_START2_ST_CLR + Configures whether or not to clear REGDMA_task_start2 trigger status.\\0: Invalid, No effect\\1: Clear + 2 + 1 + write-only + + + REGDMA_TASK_START3_ST_CLR + Configures whether or not to clear REGDMA_task_start3 trigger status.\\0: Invalid, No effect\\1: Clear + 3 + 1 + write-only + + + TMPSNSR_TASK_START_SAMPLE_ST_CLR + Configures whether or not to clear TMPSNSR_task_start_sample trigger status.\\0: Invalid, No effect\\1: Clear + 4 + 1 + write-only + + + TMPSNSR_TASK_STOP_SAMPLE_ST_CLR + Configures whether or not to clear TMPSNSR_task_stop_sample trigger status.\\0: Invalid, No effect\\1: Clear + 5 + 1 + write-only + + + I2S0_TASK_START_RX_ST_CLR + Configures whether or not to clear I2S0_task_start_rx trigger status.\\0: Invalid, No effect\\1: Clear + 6 + 1 + write-only + + + I2S0_TASK_START_TX_ST_CLR + Configures whether or not to clear I2S0_task_start_tx trigger status.\\0: Invalid, No effect\\1: Clear + 7 + 1 + write-only + + + I2S0_TASK_STOP_RX_ST_CLR + Configures whether or not to clear I2S0_task_stop_rx trigger status.\\0: Invalid, No effect\\1: Clear + 8 + 1 + write-only + + + I2S0_TASK_STOP_TX_ST_CLR + Configures whether or not to clear I2S0_task_stop_tx trigger status.\\0: Invalid, No effect\\1: Clear + 9 + 1 + write-only + + + I2S1_TASK_START_RX_ST_CLR + Configures whether or not to clear I2S1_task_start_rx trigger status.\\0: Invalid, No effect\\1: Clear + 10 + 1 + write-only + + + I2S1_TASK_START_TX_ST_CLR + Configures whether or not to clear I2S1_task_start_tx trigger status.\\0: Invalid, No effect\\1: Clear + 11 + 1 + write-only + + + I2S1_TASK_STOP_RX_ST_CLR + Configures whether or not to clear I2S1_task_stop_rx trigger status.\\0: Invalid, No effect\\1: Clear + 12 + 1 + write-only + + + I2S1_TASK_STOP_TX_ST_CLR + Configures whether or not to clear I2S1_task_stop_tx trigger status.\\0: Invalid, No effect\\1: Clear + 13 + 1 + write-only + + + I2S2_TASK_START_RX_ST_CLR + Configures whether or not to clear I2S2_task_start_rx trigger status.\\0: Invalid, No effect\\1: Clear + 14 + 1 + write-only + + + I2S2_TASK_START_TX_ST_CLR + Configures whether or not to clear I2S2_task_start_tx trigger status.\\0: Invalid, No effect\\1: Clear + 15 + 1 + write-only + + + I2S2_TASK_STOP_RX_ST_CLR + Configures whether or not to clear I2S2_task_stop_rx trigger status.\\0: Invalid, No effect\\1: Clear + 16 + 1 + write-only + + + I2S2_TASK_STOP_TX_ST_CLR + Configures whether or not to clear I2S2_task_stop_tx trigger status.\\0: Invalid, No effect\\1: Clear + 17 + 1 + write-only + + + ULP_TASK_WAKEUP_CPU_ST_CLR + Configures whether or not to clear ULP_task_wakeup_cpu trigger status.\\0: Invalid, No effect\\1: Clear + 18 + 1 + write-only + + + ULP_TASK_INT_CPU_ST_CLR + Configures whether or not to clear ULP_task_int_cpu trigger status.\\0: Invalid, No effect\\1: Clear + 19 + 1 + write-only + + + RTC_TASK_START_ST_CLR + Configures whether or not to clear RTC_task_start trigger status.\\0: Invalid, No effect\\1: Clear + 20 + 1 + write-only + + + RTC_TASK_STOP_ST_CLR + Configures whether or not to clear RTC_task_stop trigger status.\\0: Invalid, No effect\\1: Clear + 21 + 1 + write-only + + + RTC_TASK_CLR_ST_CLR + Configures whether or not to clear RTC_task_clr trigger status.\\0: Invalid, No effect\\1: Clear + 22 + 1 + write-only + + + RTC_TASK_TRIGGERFLW_ST_CLR + Configures whether or not to clear RTC_task_triggerflw trigger status.\\0: Invalid, No effect\\1: Clear + 23 + 1 + write-only + + + PDMA_AHB_TASK_IN_START_CH0_ST_CLR + Configures whether or not to clear PDMA_AHB_task_in_start_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 24 + 1 + write-only + + + PDMA_AHB_TASK_IN_START_CH1_ST_CLR + Configures whether or not to clear PDMA_AHB_task_in_start_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 25 + 1 + write-only + + + PDMA_AHB_TASK_IN_START_CH2_ST_CLR + Configures whether or not to clear PDMA_AHB_task_in_start_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 26 + 1 + write-only + + + PDMA_AHB_TASK_OUT_START_CH0_ST_CLR + Configures whether or not to clear PDMA_AHB_task_out_start_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 27 + 1 + write-only + + + PDMA_AHB_TASK_OUT_START_CH1_ST_CLR + Configures whether or not to clear PDMA_AHB_task_out_start_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 28 + 1 + write-only + + + PDMA_AHB_TASK_OUT_START_CH2_ST_CLR + Configures whether or not to clear PDMA_AHB_task_out_start_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 29 + 1 + write-only + + + PDMA_AXI_TASK_IN_START_CH0_ST_CLR + Configures whether or not to clear PDMA_AXI_task_in_start_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 30 + 1 + write-only + + + PDMA_AXI_TASK_IN_START_CH1_ST_CLR + Configures whether or not to clear PDMA_AXI_task_in_start_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 31 + 1 + write-only + + + + + TASK_ST6 + Tasks trigger status register + 0x218 + 0x20 + + + PDMA_AXI_TASK_IN_START_CH2_ST + Represents PDMA_AXI_task_in_start_ch2 trigger status.\\0: Not triggered\\1: Triggered + 0 + 1 + read-write + + + PDMA_AXI_TASK_OUT_START_CH0_ST + Represents PDMA_AXI_task_out_start_ch0 trigger status.\\0: Not triggered\\1: Triggered + 1 + 1 + read-write + + + PDMA_AXI_TASK_OUT_START_CH1_ST + Represents PDMA_AXI_task_out_start_ch1 trigger status.\\0: Not triggered\\1: Triggered + 2 + 1 + read-write + + + PDMA_AXI_TASK_OUT_START_CH2_ST + Represents PDMA_AXI_task_out_start_ch2 trigger status.\\0: Not triggered\\1: Triggered + 3 + 1 + read-write + + + PMU_TASK_SLEEP_REQ_ST + Represents PMU_task_sleep_req trigger status.\\0: Not triggered\\1: Triggered + 4 + 1 + read-write + + + DMA2D_TASK_IN_START_CH0_ST + Represents DMA2D_task_in_start_ch0 trigger status.\\0: Not triggered\\1: Triggered + 5 + 1 + read-write + + + DMA2D_TASK_IN_START_CH1_ST + Represents DMA2D_task_in_start_ch1 trigger status.\\0: Not triggered\\1: Triggered + 6 + 1 + read-write + + + DMA2D_TASK_IN_DSCR_READY_CH0_ST + Represents DMA2D_task_in_dscr_ready_ch0 trigger status.\\0: Not triggered\\1: Triggered + 7 + 1 + read-write + + + DMA2D_TASK_IN_DSCR_READY_CH1_ST + Represents DMA2D_task_in_dscr_ready_ch1 trigger status.\\0: Not triggered\\1: Triggered + 8 + 1 + read-write + + + DMA2D_TASK_OUT_START_CH0_ST + Represents DMA2D_task_out_start_ch0 trigger status.\\0: Not triggered\\1: Triggered + 9 + 1 + read-write + + + DMA2D_TASK_OUT_START_CH1_ST + Represents DMA2D_task_out_start_ch1 trigger status.\\0: Not triggered\\1: Triggered + 10 + 1 + read-write + + + DMA2D_TASK_OUT_START_CH2_ST + Represents DMA2D_task_out_start_ch2 trigger status.\\0: Not triggered\\1: Triggered + 11 + 1 + read-write + + + DMA2D_TASK_OUT_DSCR_READY_CH0_ST + Represents DMA2D_task_out_dscr_ready_ch0 trigger status.\\0: Not triggered\\1: Triggered + 12 + 1 + read-write + + + DMA2D_TASK_OUT_DSCR_READY_CH1_ST + Represents DMA2D_task_out_dscr_ready_ch1 trigger status.\\0: Not triggered\\1: Triggered + 13 + 1 + read-write + + + DMA2D_TASK_OUT_DSCR_READY_CH2_ST + Represents DMA2D_task_out_dscr_ready_ch2 trigger status.\\0: Not triggered\\1: Triggered + 14 + 1 + read-write + + + + + TASK_ST6_CLR + Tasks trigger status clear register + 0x21C + 0x20 + + + PDMA_AXI_TASK_IN_START_CH2_ST_CLR + Configures whether or not to clear PDMA_AXI_task_in_start_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 0 + 1 + write-only + + + PDMA_AXI_TASK_OUT_START_CH0_ST_CLR + Configures whether or not to clear PDMA_AXI_task_out_start_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 1 + 1 + write-only + + + PDMA_AXI_TASK_OUT_START_CH1_ST_CLR + Configures whether or not to clear PDMA_AXI_task_out_start_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 2 + 1 + write-only + + + PDMA_AXI_TASK_OUT_START_CH2_ST_CLR + Configures whether or not to clear PDMA_AXI_task_out_start_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 3 + 1 + write-only + + + PMU_TASK_SLEEP_REQ_ST_CLR + Configures whether or not to clear PMU_task_sleep_req trigger status.\\0: Invalid, No effect\\1: Clear + 4 + 1 + write-only + + + DMA2D_TASK_IN_START_CH0_ST_CLR + Configures whether or not to clear DMA2D_task_in_start_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 5 + 1 + write-only + + + DMA2D_TASK_IN_START_CH1_ST_CLR + Configures whether or not to clear DMA2D_task_in_start_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 6 + 1 + write-only + + + DMA2D_TASK_IN_DSCR_READY_CH0_ST_CLR + Configures whether or not to clear DMA2D_task_in_dscr_ready_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 7 + 1 + write-only + + + DMA2D_TASK_IN_DSCR_READY_CH1_ST_CLR + Configures whether or not to clear DMA2D_task_in_dscr_ready_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 8 + 1 + write-only + + + DMA2D_TASK_OUT_START_CH0_ST_CLR + Configures whether or not to clear DMA2D_task_out_start_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 9 + 1 + write-only + + + DMA2D_TASK_OUT_START_CH1_ST_CLR + Configures whether or not to clear DMA2D_task_out_start_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 10 + 1 + write-only + + + DMA2D_TASK_OUT_START_CH2_ST_CLR + Configures whether or not to clear DMA2D_task_out_start_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 11 + 1 + write-only + + + DMA2D_TASK_OUT_DSCR_READY_CH0_ST_CLR + Configures whether or not to clear DMA2D_task_out_dscr_ready_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 12 + 1 + write-only + + + DMA2D_TASK_OUT_DSCR_READY_CH1_ST_CLR + Configures whether or not to clear DMA2D_task_out_dscr_ready_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 13 + 1 + write-only + + + DMA2D_TASK_OUT_DSCR_READY_CH2_ST_CLR + Configures whether or not to clear DMA2D_task_out_dscr_ready_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 14 + 1 + write-only + + + + + CLK_EN + ETM clock enable register + 0x220 + 0x20 + + + CLK_EN + Configures whether or not to open register clock gate.\\0: Open the clock gate only when application writes registers\\1: Force open the clock gate for register + 0 + 1 + read-write + + + + + DATE + ETM date register + 0x224 + 0x20 + 0x02303031 + + + DATE + Configures the version. + 0 + 28 + read-write + + + + + + + SPI0 + SPI (Serial Peripheral Interface) Controller 0 + SPI0 + 0x5008C000 + + 0x0 + 0x14C + registers + + + + SPI_MEM_CMD + SPI0 FSM status register + 0x0 + 0x20 + + + SPI_MEM_MST_ST + The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT , 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent data is stored in SPI0 TX FIFO, 5: SPI0 write data state. + 0 + 4 + read-only + + + SPI_MEM_SLV_ST + The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state. + 4 + 4 + read-only + + + SPI_MEM_USR + SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 18 + 1 + read-only + + + + + SPI_MEM_CTRL + SPI0 control register. + 0x8 + 0x20 + 0x802C200C + + + SPI_MEM_WDUMMY_DQS_ALWAYS_OUT + In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_DQS is output by the MSPI controller. + 0 + 1 + read-write + + + SPI_MEM_WDUMMY_ALWAYS_OUT + In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller. + 1 + 1 + read-write + + + SPI_MEM_FDUMMY_RIN + In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller in the first half part of dummy phase. It is used to mask invalid SPI_DQS in the half part of dummy phase. + 2 + 1 + read-write + + + SPI_MEM_FDUMMY_WOUT + In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller in the second half part of dummy phase. It is used to pre-drive flash. + 3 + 1 + read-write + + + SPI_MEM_FDOUT_OCT + Apply 8 signals during write-data phase 1:enable 0: disable + 4 + 1 + read-write + + + SPI_MEM_FDIN_OCT + Apply 8 signals during read-data phase 1:enable 0: disable + 5 + 1 + read-write + + + SPI_MEM_FADDR_OCT + Apply 8 signals during address phase 1:enable 0: disable + 6 + 1 + read-write + + + SPI_MEM_FCMD_QUAD + Apply 4 signals during command phase 1:enable 0: disable + 8 + 1 + read-write + + + SPI_MEM_FCMD_OCT + Apply 8 signals during command phase 1:enable 0: disable + 9 + 1 + read-write + + + SPI_MEM_FASTRD_MODE + This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT and SPI_MEM_FREAD_DOUT. 1: enable 0: disable. + 13 + 1 + read-write + + + SPI_MEM_FREAD_DUAL + In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. + 14 + 1 + read-write + + + SPI_MEM_Q_POL + The bit is used to set MISO line polarity, 1: high 0, low + 18 + 1 + read-write + + + SPI_MEM_D_POL + The bit is used to set MOSI line polarity, 1: high 0, low + 19 + 1 + read-write + + + SPI_MEM_FREAD_QUAD + In the read operations read-data phase apply 4 signals. 1: enable 0: disable. + 20 + 1 + read-write + + + SPI_MEM_WP + Write protect signal output when SPI is idle. 1: output high, 0: output low. + 21 + 1 + read-write + + + SPI_MEM_FREAD_DIO + In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable. + 23 + 1 + read-write + + + SPI_MEM_FREAD_QIO + In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable. + 24 + 1 + read-write + + + SPI_MEM_DQS_IE_ALWAYS_ON + When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others. + 30 + 1 + read-write + + + SPI_MEM_DATA_IE_ALWAYS_ON + When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are always 1. 0: Others. + 31 + 1 + read-write + + + + + SPI_MEM_CTRL1 + SPI0 control1 register. + 0xC + 0x20 + 0x28E00000 + + + SPI_MEM_CLK_MODE + SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. + 0 + 2 + read-write + + + SPI_AR_SIZE0_1_SUPPORT_EN + 1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR. + 21 + 1 + read-write + + + SPI_AW_SIZE0_1_SUPPORT_EN + 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR. + 22 + 1 + read-write + + + SPI_AXI_RDATA_BACK_FAST + 1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: Reply AXI read data to AXI bus when all the read data is available. + 23 + 1 + read-write + + + SPI_MEM_RRESP_ECC_ERR_EN + 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY when there is a ECC error in AXI read data. The ECC error information is recorded in SPI_MEM_ECC_ERR_ADDR_REG. + 24 + 1 + read-write + + + SPI_MEM_AR_SPLICE_EN + Set this bit to enable AXI Read Splice-transfer. + 25 + 1 + read-write + + + SPI_MEM_AW_SPLICE_EN + Set this bit to enable AXI Write Splice-transfer. + 26 + 1 + read-write + + + SPI_MEM_RAM0_EN + When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be accessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 will be accessed. When SPI_MEM_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be accessed at the same time. + 27 + 1 + read-only + + + SPI_MEM_DUAL_RAM_EN + Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at the same time. + 28 + 1 + read-only + + + SPI_MEM_FAST_WRITE_EN + Set this bit to write data faster, do not wait write data has been stored in tx_bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored in tx_bus_fifo_l2. + 29 + 1 + read-write + + + SPI_MEM_RXFIFO_RST + The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to receive signals from AXI. Set this bit to reset these FIFO. + 30 + 1 + write-only + + + SPI_MEM_TXFIFO_RST + The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to send signals to AXI. Set this bit to reset these FIFO. + 31 + 1 + write-only + + + + + SPI_MEM_CTRL2 + SPI0 control2 register. + 0x10 + 0x20 + 0x01002C21 + + + SPI_MEM_CS_SETUP_TIME + (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with SPI_MEM_CS_SETUP bit. + 0 + 5 + read-write + + + SPI_MEM_CS_HOLD_TIME + SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with SPI_MEM_CS_HOLD bit. + 5 + 5 + read-write + + + SPI_MEM_ECC_CS_HOLD_TIME + SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC mode when accessed flash. + 10 + 3 + read-write + + + SPI_MEM_ECC_SKIP_PAGE_CORNER + 1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when accesses flash. + 13 + 1 + read-write + + + SPI_MEM_ECC_16TO18_BYTE_EN + Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses flash. + 14 + 1 + read-write + + + SPI_MEM_SPLIT_TRANS_EN + Set this bit to enable SPI0 split one AXI read flash transfer into two SPI transfers when one transfer will cross flash or EXT_RAM page corner, valid no matter whether there is an ECC region or not. + 24 + 1 + read-write + + + SPI_MEM_CS_HOLD_DELAY + These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles. + 25 + 6 + read-write + + + SPI_MEM_SYNC_RESET + The spi0_mst_st and spi0_slv_st will be reset. + 31 + 1 + write-only + + + + + SPI_MEM_CLOCK + SPI clock division control register. + 0x14 + 0x20 + 0x00030103 + + + SPI_MEM_CLKCNT_L + In the master mode it must be equal to spi_mem_clkcnt_N. + 0 + 8 + read-write + + + SPI_MEM_CLKCNT_H + In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). + 8 + 8 + read-write + + + SPI_MEM_CLKCNT_N + In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1) + 16 + 8 + read-write + + + SPI_MEM_CLK_EQU_SYSCLK + 1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module clock. + 31 + 1 + read-write + + + + + SPI_MEM_USER + SPI0 user register. + 0x18 + 0x20 + + + SPI_MEM_CS_HOLD + spi cs keep low when spi is in done phase. 1: enable 0: disable. + 6 + 1 + read-write + + + SPI_MEM_CS_SETUP + spi cs is enable when spi is in prepare phase. 1: enable 0: disable. + 7 + 1 + read-write + + + SPI_MEM_CK_OUT_EDGE + The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3. + 9 + 1 + read-write + + + SPI_MEM_USR_DUMMY_IDLE + spi clock is disable in dummy phase when the bit is enable. + 26 + 1 + read-write + + + SPI_MEM_USR_DUMMY + This bit enable the dummy phase of an operation. + 29 + 1 + read-write + + + + + SPI_MEM_USER1 + SPI0 user1 register. + 0x1C + 0x20 + 0x5C000047 + + + SPI_MEM_USR_DUMMY_CYCLELEN + The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1). + 0 + 6 + read-write + + + SPI_MEM_USR_DBYTELEN + SPI0 USR_CMD read or write data byte length -1 + 6 + 3 + read-only + + + SPI_MEM_USR_ADDR_BITLEN + The length in bits of address phase. The register value shall be (bit_num-1). + 26 + 6 + read-write + + + + + SPI_MEM_USER2 + SPI0 user2 register. + 0x20 + 0x20 + 0x70000000 + + + SPI_MEM_USR_COMMAND_VALUE + The value of command. + 0 + 16 + read-write + + + SPI_MEM_USR_COMMAND_BITLEN + The length in bits of command phase. The register value shall be (bit_num-1) + 28 + 4 + read-write + + + + + SPI_MEM_RD_STATUS + SPI0 read control register. + 0x2C + 0x20 + + + SPI_MEM_WB_MODE + Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. + 16 + 8 + read-write + + + + + SPI_MEM_MISC + SPI0 misc register + 0x34 + 0x20 + + + SPI_MEM_FSUB_PIN + For SPI0, flash is connected to SUBPINs. + 7 + 1 + read-write + + + SPI_MEM_SSUB_PIN + For SPI0, sram is connected to SUBPINs. + 8 + 1 + read-write + + + SPI_MEM_CK_IDLE_EDGE + 1: SPI_CLK line is high when idle 0: spi clk line is low when idle + 9 + 1 + read-write + + + SPI_MEM_CS_KEEP_ACTIVE + SPI_CS line keep low when the bit is set. + 10 + 1 + read-write + + + + + SPI_MEM_CACHE_FCTRL + SPI0 bit mode control register. + 0x3C + 0x20 + 0xC0000000 + + + SPI_MEM_AXI_REQ_EN + For SPI0, AXI master access enable, 1: enable, 0:disable. + 0 + 1 + read-write + + + SPI_MEM_CACHE_USR_ADDR_4BYTE + For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable. + 1 + 1 + read-write + + + SPI_MEM_CACHE_FLASH_USR_CMD + For SPI0, cache read flash for user define command, 1: enable, 0:disable. + 2 + 1 + read-write + + + SPI_MEM_FDIN_DUAL + For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. + 3 + 1 + read-write + + + SPI_MEM_FDOUT_DUAL + For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. + 4 + 1 + read-write + + + SPI_MEM_FADDR_DUAL + For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. + 5 + 1 + read-write + + + SPI_MEM_FDIN_QUAD + For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. + 6 + 1 + read-write + + + SPI_MEM_FDOUT_QUAD + For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. + 7 + 1 + read-write + + + SPI_MEM_FADDR_QUAD + For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. + 8 + 1 + read-write + + + SPI_SAME_AW_AR_ADDR_CHK_EN + Set this bit to check AXI read/write the same address region. + 30 + 1 + read-write + + + SPI_CLOSE_AXI_INF_EN + Set this bit to close AXI read/write transfer to MSPI, which means that only SLV_ERR will be replied to BRESP/RRESP. + 31 + 1 + read-write + + + + + SPI_MEM_CACHE_SCTRL + SPI0 external RAM control register + 0x40 + 0x20 + 0x0055C070 + + + SPI_MEM_CACHE_USR_SADDR_4BYTE + For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: enable, 0:disable. + 0 + 1 + read-write + + + SPI_MEM_USR_SRAM_DIO + For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disable + 1 + 1 + read-write + + + SPI_MEM_USR_SRAM_QIO + For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disable + 2 + 1 + read-write + + + SPI_MEM_USR_WR_SRAM_DUMMY + For SPI0, In the external RAM mode, it is the enable bit of dummy phase for write operations. + 3 + 1 + read-write + + + SPI_MEM_USR_RD_SRAM_DUMMY + For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read operations. + 4 + 1 + read-write + + + SPI_MEM_CACHE_SRAM_USR_RCMD + For SPI0, In the external RAM mode cache read external RAM for user define command. + 5 + 1 + read-write + + + SPI_MEM_SRAM_RDUMMY_CYCLELEN + For SPI0, In the external RAM mode, it is the length in bits of read dummy phase. The register value shall be (bit_num-1). + 6 + 6 + read-write + + + SPI_MEM_SRAM_ADDR_BITLEN + For SPI0, In the external RAM mode, it is the length in bits of address phase. The register value shall be (bit_num-1). + 14 + 6 + read-write + + + SPI_MEM_CACHE_SRAM_USR_WCMD + For SPI0, In the external RAM mode cache write sram for user define command + 20 + 1 + read-write + + + SPI_MEM_SRAM_OCT + reserved + 21 + 1 + read-write + + + SPI_MEM_SRAM_WDUMMY_CYCLELEN + For SPI0, In the external RAM mode, it is the length in bits of write dummy phase. The register value shall be (bit_num-1). + 22 + 6 + read-write + + + + + SPI_MEM_SRAM_CMD + SPI0 external RAM mode control register + 0x44 + 0x20 + 0x80C00000 + + + SPI_MEM_SCLK_MODE + SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on. + 0 + 2 + read-write + + + SPI_MEM_SWB_MODE + Mode bits in the external RAM fast read mode it is combined with spi_mem_fastrd_mode bit. + 2 + 8 + read-write + + + SPI_MEM_SDIN_DUAL + For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio. + 10 + 1 + read-write + + + SPI_MEM_SDOUT_DUAL + For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio. + 11 + 1 + read-write + + + SPI_MEM_SADDR_DUAL + For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio. + 12 + 1 + read-write + + + SPI_MEM_SDIN_QUAD + For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio. + 14 + 1 + read-write + + + SPI_MEM_SDOUT_QUAD + For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio. + 15 + 1 + read-write + + + SPI_MEM_SADDR_QUAD + For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio. + 16 + 1 + read-write + + + SPI_MEM_SCMD_QUAD + For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio. + 17 + 1 + read-write + + + SPI_MEM_SDIN_OCT + For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable. + 18 + 1 + read-write + + + SPI_MEM_SDOUT_OCT + For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable. + 19 + 1 + read-write + + + SPI_MEM_SADDR_OCT + For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. + 20 + 1 + read-write + + + SPI_MEM_SCMD_OCT + For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable. + 21 + 1 + read-write + + + SPI_MEM_SDUMMY_RIN + In the dummy phase of a MSPI read data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller. + 22 + 1 + read-write + + + SPI_MEM_SDUMMY_WOUT + In the dummy phase of a MSPI write data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller. + 23 + 1 + read-write + + + SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT + In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_DQS is output by the MSPI controller. + 24 + 1 + read-write + + + SPI_SMEM_WDUMMY_ALWAYS_OUT + In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_IO[7:0] is output by the MSPI controller. + 25 + 1 + read-write + + + SPI_MEM_SDIN_HEX + For SPI0 external RAM , din phase apply 16 signals. 1: enable 0: disable. + 26 + 1 + read-write + + + SPI_MEM_SDOUT_HEX + For SPI0 external RAM , dout phase apply 16 signals. 1: enable 0: disable. + 27 + 1 + read-write + + + SPI_SMEM_DQS_IE_ALWAYS_ON + When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others. + 30 + 1 + read-write + + + SPI_SMEM_DATA_IE_ALWAYS_ON + When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0] are always 1. 0: Others. + 31 + 1 + read-write + + + + + SPI_MEM_SRAM_DRD_CMD + SPI0 external RAM DDR read command control register + 0x48 + 0x20 + + + SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE + For SPI0,When cache mode is enable it is the read command value of command phase for sram. + 0 + 16 + read-write + + + SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN + For SPI0,When cache mode is enable it is the length in bits of command phase for sram. The register value shall be (bit_num-1). + 28 + 4 + read-write + + + + + SPI_MEM_SRAM_DWR_CMD + SPI0 external RAM DDR write command control register + 0x4C + 0x20 + + + SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE + For SPI0,When cache mode is enable it is the write command value of command phase for sram. + 0 + 16 + read-write + + + SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN + For SPI0,When cache mode is enable it is the in bits of command phase for sram. The register value shall be (bit_num-1). + 28 + 4 + read-write + + + + + SPI_MEM_SRAM_CLK + SPI0 external RAM clock control register + 0x50 + 0x20 + 0x00030103 + + + SPI_MEM_SCLKCNT_L + For SPI0 external RAM interface, it must be equal to spi_mem_clkcnt_N. + 0 + 8 + read-write + + + SPI_MEM_SCLKCNT_H + For SPI0 external RAM interface, it must be floor((spi_mem_clkcnt_N+1)/2-1). + 8 + 8 + read-write + + + SPI_MEM_SCLKCNT_N + For SPI0 external RAM interface, it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1) + 16 + 8 + read-write + + + SPI_MEM_SCLK_EQU_SYSCLK + For SPI0 external RAM interface, 1: spi_mem_clk is eqaul to system 0: spi_mem_clk is divided from system clock. + 31 + 1 + read-write + + + + + SPI_MEM_FSM + SPI0 FSM status register + 0x54 + 0x20 + 0x00000200 + + + SPI_MEM_LOCK_DELAY_TIME + The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1. + 7 + 5 + read-write + + + + + SPI_MEM_INT_ENA + SPI0 interrupt enable register + 0xC0 + 0x20 + + + SPI_MEM_SLV_ST_END_INT_ENA + The enable bit for SPI_MEM_SLV_ST_END_INT interrupt. + 3 + 1 + read-write + + + SPI_MEM_MST_ST_END_INT_ENA + The enable bit for SPI_MEM_MST_ST_END_INT interrupt. + 4 + 1 + read-write + + + SPI_MEM_ECC_ERR_INT_ENA + The enable bit for SPI_MEM_ECC_ERR_INT interrupt. + 5 + 1 + read-write + + + SPI_MEM_PMS_REJECT_INT_ENA + The enable bit for SPI_MEM_PMS_REJECT_INT interrupt. + 6 + 1 + read-write + + + SPI_MEM_AXI_RADDR_ERR_INT_ENA + The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. + 7 + 1 + read-write + + + SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA + The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. + 8 + 1 + read-write + + + SPI_MEM_AXI_WADDR_ERR_INT__ENA + The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. + 9 + 1 + read-write + + + SPI_MEM_DQS0_AFIFO_OVF_INT_ENA + The enable bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. + 28 + 1 + read-write + + + SPI_MEM_DQS1_AFIFO_OVF_INT_ENA + The enable bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. + 29 + 1 + read-write + + + SPI_MEM_BUS_FIFO1_UDF_INT_ENA + The enable bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. + 30 + 1 + read-write + + + SPI_MEM_BUS_FIFO0_UDF_INT_ENA + The enable bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. + 31 + 1 + read-write + + + + + SPI_MEM_INT_CLR + SPI0 interrupt clear register + 0xC4 + 0x20 + + + SPI_MEM_SLV_ST_END_INT_CLR + The clear bit for SPI_MEM_SLV_ST_END_INT interrupt. + 3 + 1 + write-only + + + SPI_MEM_MST_ST_END_INT_CLR + The clear bit for SPI_MEM_MST_ST_END_INT interrupt. + 4 + 1 + write-only + + + SPI_MEM_ECC_ERR_INT_CLR + The clear bit for SPI_MEM_ECC_ERR_INT interrupt. + 5 + 1 + write-only + + + SPI_MEM_PMS_REJECT_INT_CLR + The clear bit for SPI_MEM_PMS_REJECT_INT interrupt. + 6 + 1 + write-only + + + SPI_MEM_AXI_RADDR_ERR_INT_CLR + The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. + 7 + 1 + write-only + + + SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR + The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. + 8 + 1 + write-only + + + SPI_MEM_AXI_WADDR_ERR_INT_CLR + The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. + 9 + 1 + write-only + + + SPI_MEM_DQS0_AFIFO_OVF_INT_CLR + The clear bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. + 28 + 1 + write-only + + + SPI_MEM_DQS1_AFIFO_OVF_INT_CLR + The clear bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. + 29 + 1 + write-only + + + SPI_MEM_BUS_FIFO1_UDF_INT_CLR + The clear bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. + 30 + 1 + write-only + + + SPI_MEM_BUS_FIFO0_UDF_INT_CLR + The clear bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. + 31 + 1 + write-only + + + + + SPI_MEM_INT_RAW + SPI0 interrupt raw register + 0xC8 + 0x20 + + + SPI_MEM_SLV_ST_END_INT_RAW + The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others + 3 + 1 + read-write + + + SPI_MEM_MST_ST_END_INT_RAW + The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is changed from non idle state to idle state. 0: Others. + 4 + 1 + read-write + + + SPI_MEM_ECC_ERR_INT_RAW + The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set and SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN is cleared and SPI_SMEM_ECC_ERR_INT_EN is set, this bit is triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times of SPI0/1 ECC read external RAM and flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN are cleared, this bit will not be triggered. + 5 + 1 + read-write + + + SPI_MEM_PMS_REJECT_INT_RAW + The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is rejected. 0: Others. + 6 + 1 + read-write + + + SPI_MEM_AXI_RADDR_ERR_INT_RAW + The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read address is invalid by compared to MMU configuration. 0: Others. + 7 + 1 + read-write + + + SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW + The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write flash request is received. 0: Others. + 8 + 1 + read-write + + + SPI_MEM_AXI_WADDR_ERR_INT_RAW + The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write address is invalid by compared to MMU configuration. 0: Others. + 9 + 1 + read-write + + + SPI_MEM_DQS0_AFIFO_OVF_INT_RAW + The raw bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO connected to SPI_DQS1 is overflow. + 28 + 1 + read-write + + + SPI_MEM_DQS1_AFIFO_OVF_INT_RAW + The raw bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO connected to SPI_DQS is overflow. + 29 + 1 + read-write + + + SPI_MEM_BUS_FIFO1_UDF_INT_RAW + The raw bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. 1: Triggered when BUS1 FIFO is underflow. + 30 + 1 + read-write + + + SPI_MEM_BUS_FIFO0_UDF_INT_RAW + The raw bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. 1: Triggered when BUS0 FIFO is underflow. + 31 + 1 + read-write + + + + + SPI_MEM_INT_ST + SPI0 interrupt status register + 0xCC + 0x20 + + + SPI_MEM_SLV_ST_END_INT_ST + The status bit for SPI_MEM_SLV_ST_END_INT interrupt. + 3 + 1 + read-only + + + SPI_MEM_MST_ST_END_INT_ST + The status bit for SPI_MEM_MST_ST_END_INT interrupt. + 4 + 1 + read-only + + + SPI_MEM_ECC_ERR_INT_ST + The status bit for SPI_MEM_ECC_ERR_INT interrupt. + 5 + 1 + read-only + + + SPI_MEM_PMS_REJECT_INT_ST + The status bit for SPI_MEM_PMS_REJECT_INT interrupt. + 6 + 1 + read-only + + + SPI_MEM_AXI_RADDR_ERR_INT_ST + The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. + 7 + 1 + read-only + + + SPI_MEM_AXI_WR_FLASH_ERR_INT_ST + The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. + 8 + 1 + read-only + + + SPI_MEM_AXI_WADDR_ERR_INT_ST + The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. + 9 + 1 + read-only + + + SPI_MEM_DQS0_AFIFO_OVF_INT_ST + The status bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. + 28 + 1 + read-only + + + SPI_MEM_DQS1_AFIFO_OVF_INT_ST + The status bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. + 29 + 1 + read-only + + + SPI_MEM_BUS_FIFO1_UDF_INT_ST + The status bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. + 30 + 1 + read-only + + + SPI_MEM_BUS_FIFO0_UDF_INT_ST + The status bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. + 31 + 1 + read-only + + + + + SPI_MEM_DDR + SPI0 flash DDR mode control register + 0xD4 + 0x20 + 0x00003020 + + + SPI_FMEM_DDR_EN + 1: in DDR mode, 0 in SDR mode + 0 + 1 + read-write + + + SPI_FMEM_VAR_DUMMY + Set the bit to enable variable dummy cycle in spi DDR mode. + 1 + 1 + read-write + + + SPI_FMEM_DDR_RDAT_SWP + Set the bit to reorder rx data of the word in spi DDR mode. + 2 + 1 + read-write + + + SPI_FMEM_DDR_WDAT_SWP + Set the bit to reorder tx data of the word in spi DDR mode. + 3 + 1 + read-write + + + SPI_FMEM_DDR_CMD_DIS + the bit is used to disable dual edge in command phase when DDR mode. + 4 + 1 + read-write + + + SPI_FMEM_OUTMINBYTELEN + It is the minimum output data length in the panda device. + 5 + 7 + read-write + + + SPI_FMEM_TX_DDR_MSK_EN + Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when accesses to flash. + 12 + 1 + read-write + + + SPI_FMEM_RX_DDR_MSK_EN + Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when accesses to flash. + 13 + 1 + read-write + + + SPI_FMEM_USR_DDR_DQS_THD + The delay number of data strobe which from memory based on SPI clock. + 14 + 7 + read-write + + + SPI_FMEM_DDR_DQS_LOOP + 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS. + 21 + 1 + read-write + + + SPI_FMEM_CLK_DIFF_EN + Set this bit to enable the differential SPI_CLK#. + 24 + 1 + read-write + + + SPI_FMEM_DQS_CA_IN + Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + 26 + 1 + read-write + + + SPI_FMEM_HYPERBUS_DUMMY_2X + Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram. + 27 + 1 + read-write + + + SPI_FMEM_CLK_DIFF_INV + Set this bit to invert SPI_DIFF when accesses to flash. . + 28 + 1 + read-write + + + SPI_FMEM_OCTA_RAM_ADDR + Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. + 29 + 1 + read-write + + + SPI_FMEM_HYPERBUS_CA + Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. + 30 + 1 + read-write + + + + + SPI_SMEM_DDR + SPI0 external RAM DDR mode control register + 0xD8 + 0x20 + 0x00003020 + + + EN + 1: in DDR mode, 0 in SDR mode + 0 + 1 + read-write + + + SPI_SMEM_VAR_DUMMY + Set the bit to enable variable dummy cycle in spi DDR mode. + 1 + 1 + read-write + + + RDAT_SWP + Set the bit to reorder rx data of the word in spi DDR mode. + 2 + 1 + read-write + + + WDAT_SWP + Set the bit to reorder tx data of the word in spi DDR mode. + 3 + 1 + read-write + + + CMD_DIS + the bit is used to disable dual edge in command phase when DDR mode. + 4 + 1 + read-write + + + SPI_SMEM_OUTMINBYTELEN + It is the minimum output data length in the DDR psram. + 5 + 7 + read-write + + + SPI_SMEM_TX_DDR_MSK_EN + Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when accesses to external RAM. + 12 + 1 + read-write + + + SPI_SMEM_RX_DDR_MSK_EN + Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when accesses to external RAM. + 13 + 1 + read-write + + + SPI_SMEM_USR_DDR_DQS_THD + The delay number of data strobe which from memory based on SPI clock. + 14 + 7 + read-write + + + DQS_LOOP + 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS. + 21 + 1 + read-write + + + SPI_SMEM_CLK_DIFF_EN + Set this bit to enable the differential SPI_CLK#. + 24 + 1 + read-write + + + SPI_SMEM_DQS_CA_IN + Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + 26 + 1 + read-write + + + SPI_SMEM_HYPERBUS_DUMMY_2X + Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram. + 27 + 1 + read-write + + + SPI_SMEM_CLK_DIFF_INV + Set this bit to invert SPI_DIFF when accesses to external RAM. . + 28 + 1 + read-write + + + SPI_SMEM_OCTA_RAM_ADDR + Set this bit to enable octa_ram address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. + 29 + 1 + read-write + + + SPI_SMEM_HYPERBUS_CA + Set this bit to enable HyperRAM address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. + 30 + 1 + read-write + + + + + 4 + 0x4 + SPI_FMEM_PMS%s_ATTR + MSPI flash PMS section %s attribute register + 0x100 + 0x20 + 0x00000003 + + + SPI_FMEM_PMS_RD_ATTR + 1: SPI1 flash PMS section %s read accessible. 0: Not allowed. + 0 + 1 + read-write + + + SPI_FMEM_PMS_WR_ATTR + 1: SPI1 flash PMS section %s write accessible. 0: Not allowed. + 1 + 1 + read-write + + + SPI_FMEM_PMS_ECC + SPI1 flash PMS section %s ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS section %s is configured by registers SPI_FMEM_PMS%s_ADDR_REG and SPI_FMEM_PMS%s_SIZE_REG. + 2 + 1 + read-write + + + + + 4 + 0x4 + SPI_FMEM_PMS%s_ADDR + SPI1 flash PMS section %s start address register + 0x110 + 0x20 + + + S + SPI1 flash PMS section %s start address value + 0 + 27 + read-write + + + + + 4 + 0x4 + SPI_FMEM_PMS%s_SIZE + SPI1 flash PMS section %s start address register + 0x120 + 0x20 + 0x00001000 + + + SPI_FMEM_PMS_SIZE + SPI1 flash PMS section %s address region is (SPI_FMEM_PMS%s_ADDR_S, SPI_FMEM_PMS%s_ADDR_S + SPI_FMEM_PMS%s_SIZE) + 0 + 15 + read-write + + + + + 4 + 0x4 + SPI_SMEM_PMS%s_ATTR + SPI1 flash PMS section %s start address register + 0x130 + 0x20 + 0x00000003 + + + SPI_SMEM_PMS_RD_ATTR + 1: SPI1 external RAM PMS section %s read accessible. 0: Not allowed. + 0 + 1 + read-write + + + SPI_SMEM_PMS_WR_ATTR + 1: SPI1 external RAM PMS section %s write accessible. 0: Not allowed. + 1 + 1 + read-write + + + SPI_SMEM_PMS_ECC + SPI1 external RAM PMS section %s ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM PMS section %s is configured by registers SPI_SMEM_PMS%s_ADDR_REG and SPI_SMEM_PMS%s_SIZE_REG. + 2 + 1 + read-write + + + + + 4 + 0x4 + SPI_SMEM_PMS%s_ADDR + SPI1 external RAM PMS section %s start address register + 0x140 + 0x20 + + + S + SPI1 external RAM PMS section %s start address value + 0 + 27 + read-write + + + + + 4 + 0x4 + SPI_SMEM_PMS%s_SIZE + SPI1 external RAM PMS section %s start address register + 0x150 + 0x20 + 0x00001000 + + + SPI_SMEM_PMS_SIZE + SPI1 external RAM PMS section %s address region is (SPI_SMEM_PMS%s_ADDR_S, SPI_SMEM_PMS%s_ADDR_S + SPI_SMEM_PMS%s_SIZE) + 0 + 15 + read-write + + + + + SPI_MEM_PMS_REJECT + SPI1 access reject register + 0x164 + 0x20 + + + SPI_MEM_REJECT_ADDR + This bits show the first SPI1 access error address. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. + 0 + 27 + read-only + + + SPI_MEM_PM_EN + Set this bit to enable SPI0/1 transfer permission control function. + 27 + 1 + read-write + + + SPI_MEM_PMS_LD + 1: SPI1 write access error. 0: No write access error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. + 28 + 1 + read-only + + + SPI_MEM_PMS_ST + 1: SPI1 read access error. 0: No read access error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. + 29 + 1 + read-only + + + SPI_MEM_PMS_MULTI_HIT + 1: SPI1 access is rejected because of address miss. 0: No address miss error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. + 30 + 1 + read-only + + + SPI_MEM_PMS_IVD + 1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. + 31 + 1 + read-only + + + + + SPI_MEM_ECC_CTRL + MSPI ECC control register + 0x168 + 0x20 + 0x01005000 + + + SPI_MEM_ECC_ERR_CNT + This bits show the error times of MSPI ECC read. It is cleared by when SPI_MEM_ECC_ERR_INT_CLR bit is set. + 5 + 6 + read-only + + + SPI_FMEM_ECC_ERR_INT_NUM + Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt. + 11 + 6 + read-write + + + SPI_FMEM_ECC_ERR_INT_EN + Set this bit to calculate the error times of MSPI ECC read when accesses to flash. + 17 + 1 + read-write + + + SPI_FMEM_PAGE_SIZE + Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes. + 18 + 2 + read-write + + + SPI_FMEM_ECC_ADDR_EN + Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the ECC region or non-ECC region of flash. If there is no ECC region in flash, this bit should be 0. Otherwise, this bit should be 1. + 20 + 1 + read-write + + + SPI_MEM_USR_ECC_ADDR_EN + Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer. + 21 + 1 + read-write + + + SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN + 1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is updated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR record the first ECC error information. + 24 + 1 + read-write + + + SPI_MEM_ECC_ERR_BITS + Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding to byte 0 bit 0 to byte 15 bit 7) + 25 + 7 + read-only + + + + + SPI_MEM_ECC_ERR_ADDR + MSPI ECC error address register + 0x16C + 0x20 + + + SPI_MEM_ECC_ERR_ADDR + This bits show the first MSPI ECC error address. It is cleared by when SPI_MEM_ECC_ERR_INT_CLR bit is set. + 0 + 27 + read-only + + + + + SPI_MEM_AXI_ERR_ADDR + SPI0 AXI request error address. + 0x170 + 0x20 + + + SPI_MEM_AXI_ERR_ADDR + This bits show the first AXI write/read invalid error or AXI write flash error address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set. + 0 + 27 + read-only + + + + + SPI_SMEM_ECC_CTRL + MSPI ECC control register + 0x174 + 0x20 + 0x00080000 + + + SPI_SMEM_ECC_ERR_INT_EN + Set this bit to calculate the error times of MSPI ECC read when accesses to external RAM. + 17 + 1 + read-write + + + SPI_SMEM_PAGE_SIZE + Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes. + 18 + 2 + read-write + + + SPI_SMEM_ECC_ADDR_EN + Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the ECC region or non-ECC region of external RAM. If there is no ECC region in external RAM, this bit should be 0. Otherwise, this bit should be 1. + 20 + 1 + read-write + + + + + SPI_SMEM_AXI_ADDR_CTRL + SPI0 AXI address control register + 0x178 + 0x20 + 0xFC000000 + + + SPI_MEM_ALL_FIFO_EMPTY + The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers and SPI0 transfers are done. 0: Others. + 26 + 1 + read-only + + + SPI_RDATA_AFIFO_REMPTY + 1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending. + 27 + 1 + read-only + + + SPI_RADDR_AFIFO_REMPTY + 1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending. + 28 + 1 + read-only + + + SPI_WDATA_AFIFO_REMPTY + 1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending. + 29 + 1 + read-only + + + SPI_WBLEN_AFIFO_REMPTY + 1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending. + 30 + 1 + read-only + + + SPI_ALL_AXI_TRANS_AFIFO_EMPTY + This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO and RDATA_AFIFO are empty and spi0_mst_st is IDLE. + 31 + 1 + read-only + + + + + SPI_MEM_AXI_ERR_RESP_EN + SPI0 AXI error response enable register + 0x17C + 0x20 + + + SPI_MEM_AW_RESP_EN_MMU_VLD + Set this bit to enable AXI response function for mmu valid err in axi write trans. + 0 + 1 + read-write + + + SPI_MEM_AW_RESP_EN_MMU_GID + Set this bit to enable AXI response function for mmu gid err in axi write trans. + 1 + 1 + read-write + + + SPI_MEM_AW_RESP_EN_AXI_SIZE + Set this bit to enable AXI response function for axi size err in axi write trans. + 2 + 1 + read-write + + + SPI_MEM_AW_RESP_EN_AXI_FLASH + Set this bit to enable AXI response function for axi flash err in axi write trans. + 3 + 1 + read-write + + + SPI_MEM_AW_RESP_EN_MMU_ECC + Set this bit to enable AXI response function for mmu ecc err in axi write trans. + 4 + 1 + read-write + + + SPI_MEM_AW_RESP_EN_MMU_SENS + Set this bit to enable AXI response function for mmu sens in err axi write trans. + 5 + 1 + read-write + + + SPI_MEM_AW_RESP_EN_AXI_WSTRB + Set this bit to enable AXI response function for axi wstrb err in axi write trans. + 6 + 1 + read-write + + + SPI_MEM_AR_RESP_EN_MMU_VLD + Set this bit to enable AXI response function for mmu valid err in axi read trans. + 7 + 1 + read-write + + + SPI_MEM_AR_RESP_EN_MMU_GID + Set this bit to enable AXI response function for mmu gid err in axi read trans. + 8 + 1 + read-write + + + SPI_MEM_AR_RESP_EN_MMU_ECC + Set this bit to enable AXI response function for mmu ecc err in axi read trans. + 9 + 1 + read-write + + + SPI_MEM_AR_RESP_EN_MMU_SENS + Set this bit to enable AXI response function for mmu sensitive err in axi read trans. + 10 + 1 + read-write + + + SPI_MEM_AR_RESP_EN_AXI_SIZE + Set this bit to enable AXI response function for axi size err in axi read trans. + 11 + 1 + read-write + + + + + SPI_MEM_TIMING_CALI + SPI0 flash timing calibration register + 0x180 + 0x20 + 0x00000001 + + + SPI_MEM_TIMING_CLK_ENA + The bit is used to enable timing adjust clock for all reading operations. + 0 + 1 + read-write + + + SPI_MEM_TIMING_CALI + The bit is used to enable timing auto-calibration for all reading operations. + 1 + 1 + read-write + + + SPI_MEM_EXTRA_DUMMY_CYCLELEN + add extra dummy spi clock cycle length for spi clock calibration. + 2 + 3 + read-write + + + SPI_MEM_DLL_TIMING_CALI + Set this bit to enable DLL for timing calibration in DDR mode when accessed to flash. + 5 + 1 + read-write + + + UPDATE + Set this bit to update delay mode, delay num and extra dummy in MSPI. + 6 + 1 + write-only + + + + + SPI_MEM_DIN_MODE + MSPI flash input timing delay mode control register + 0x184 + 0x20 + + + SPI_MEM_DIN0_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 0 + 3 + read-write + + + SPI_MEM_DIN1_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 3 + 3 + read-write + + + SPI_MEM_DIN2_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 6 + 3 + read-write + + + SPI_MEM_DIN3_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 9 + 3 + read-write + + + SPI_MEM_DIN4_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk + 12 + 3 + read-write + + + SPI_MEM_DIN5_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk + 15 + 3 + read-write + + + SPI_MEM_DIN6_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk + 18 + 3 + read-write + + + SPI_MEM_DIN7_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk + 21 + 3 + read-write + + + SPI_MEM_DINS_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk + 24 + 3 + read-write + + + + + SPI_MEM_DIN_NUM + MSPI flash input timing delay number control register + 0x188 + 0x20 + + + SPI_MEM_DIN0_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 0 + 2 + read-write + + + SPI_MEM_DIN1_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 2 + 2 + read-write + + + SPI_MEM_DIN2_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 4 + 2 + read-write + + + SPI_MEM_DIN3_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 6 + 2 + read-write + + + SPI_MEM_DIN4_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 8 + 2 + read-write + + + SPI_MEM_DIN5_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 10 + 2 + read-write + + + SPI_MEM_DIN6_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 12 + 2 + read-write + + + SPI_MEM_DIN7_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 14 + 2 + read-write + + + SPI_MEM_DINS_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 16 + 2 + read-write + + + + + SPI_MEM_DOUT_MODE + MSPI flash output timing adjustment control register + 0x18C + 0x20 + + + SPI_MEM_DOUT0_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 0 + 1 + read-write + + + SPI_MEM_DOUT1_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 1 + 1 + read-write + + + SPI_MEM_DOUT2_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 2 + 1 + read-write + + + SPI_MEM_DOUT3_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 3 + 1 + read-write + + + SPI_MEM_DOUT4_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk + 4 + 1 + read-write + + + SPI_MEM_DOUT5_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk + 5 + 1 + read-write + + + SPI_MEM_DOUT6_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk + 6 + 1 + read-write + + + SPI_MEM_DOUT7_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk + 7 + 1 + read-write + + + SPI_MEM_DOUTS_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk + 8 + 1 + read-write + + + + + SPI_SMEM_TIMING_CALI + MSPI external RAM timing calibration register + 0x190 + 0x20 + 0x00000001 + + + SPI_SMEM_TIMING_CLK_ENA + For sram, the bit is used to enable timing adjust clock for all reading operations. + 0 + 1 + read-write + + + SPI_SMEM_TIMING_CALI + For sram, the bit is used to enable timing auto-calibration for all reading operations. + 1 + 1 + read-write + + + SPI_SMEM_EXTRA_DUMMY_CYCLELEN + For sram, add extra dummy spi clock cycle length for spi clock calibration. + 2 + 3 + read-write + + + SPI_SMEM_DLL_TIMING_CALI + Set this bit to enable DLL for timing calibration in DDR mode when accessed to EXT_RAM. + 5 + 1 + read-write + + + + + SPI_SMEM_DIN_MODE + MSPI external RAM input timing delay mode control register + 0x194 + 0x20 + + + SPI_SMEM_DIN0_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 0 + 3 + read-write + + + SPI_SMEM_DIN1_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 3 + 3 + read-write + + + SPI_SMEM_DIN2_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 6 + 3 + read-write + + + SPI_SMEM_DIN3_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 9 + 3 + read-write + + + SPI_SMEM_DIN4_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 12 + 3 + read-write + + + SPI_SMEM_DIN5_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 15 + 3 + read-write + + + SPI_SMEM_DIN6_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 18 + 3 + read-write + + + SPI_SMEM_DIN7_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 21 + 3 + read-write + + + SPI_SMEM_DINS_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 24 + 3 + read-write + + + + + SPI_SMEM_DIN_NUM + MSPI external RAM input timing delay number control register + 0x198 + 0x20 + + + SPI_SMEM_DIN0_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 0 + 2 + read-write + + + SPI_SMEM_DIN1_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 2 + 2 + read-write + + + SPI_SMEM_DIN2_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 4 + 2 + read-write + + + SPI_SMEM_DIN3_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 6 + 2 + read-write + + + SPI_SMEM_DIN4_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 8 + 2 + read-write + + + SPI_SMEM_DIN5_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 10 + 2 + read-write + + + SPI_SMEM_DIN6_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 12 + 2 + read-write + + + SPI_SMEM_DIN7_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 14 + 2 + read-write + + + SPI_SMEM_DINS_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 16 + 2 + read-write + + + + + SPI_SMEM_DOUT_MODE + MSPI external RAM output timing adjustment control register + 0x19C + 0x20 + + + SPI_SMEM_DOUT0_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 0 + 1 + read-write + + + SPI_SMEM_DOUT1_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 1 + 1 + read-write + + + SPI_SMEM_DOUT2_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 2 + 1 + read-write + + + SPI_SMEM_DOUT3_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 3 + 1 + read-write + + + SPI_SMEM_DOUT4_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 4 + 1 + read-write + + + SPI_SMEM_DOUT5_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 5 + 1 + read-write + + + SPI_SMEM_DOUT6_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 6 + 1 + read-write + + + SPI_SMEM_DOUT7_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 7 + 1 + read-write + + + SPI_SMEM_DOUTS_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 8 + 1 + read-write + + + + + SPI_SMEM_AC + MSPI external RAM ECC and SPI CS timing control register + 0x1A0 + 0x20 + 0x8000B084 + + + SPI_SMEM_CS_SETUP + For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: disable. + 0 + 1 + read-write + + + SPI_SMEM_CS_HOLD + For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disable. + 1 + 1 + read-write + + + SPI_SMEM_CS_SETUP_TIME + For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit. + 2 + 5 + read-write + + + SPI_SMEM_CS_HOLD_TIME + For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit. + 7 + 5 + read-write + + + SPI_SMEM_ECC_CS_HOLD_TIME + SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold cycles in ECC mode when accessed external RAM. + 12 + 3 + read-write + + + SPI_SMEM_ECC_SKIP_PAGE_CORNER + 1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner when accesses external RAM. + 15 + 1 + read-write + + + SPI_SMEM_ECC_16TO18_BYTE_EN + Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses external RAM. + 16 + 1 + read-write + + + SPI_SMEM_CS_HOLD_DELAY + These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles. + 25 + 6 + read-write + + + SPI_SMEM_SPLIT_TRANS_EN + Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI transfers when one transfer will cross flash/EXT_RAM page corner, valid no matter whether there is an ECC region or not. + 31 + 1 + read-write + + + + + SPI_SMEM_DIN_HEX_MODE + MSPI 16x external RAM input timing delay mode control register + 0x1A4 + 0x20 + + + SPI_SMEM_DIN08_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 0 + 3 + read-write + + + SPI_SMEM_DIN09_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 3 + 3 + read-write + + + SPI_SMEM_DIN10_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 6 + 3 + read-write + + + SPI_SMEM_DIN11_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 9 + 3 + read-write + + + SPI_SMEM_DIN12_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 12 + 3 + read-write + + + SPI_SMEM_DIN13_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 15 + 3 + read-write + + + SPI_SMEM_DIN14_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 18 + 3 + read-write + + + SPI_SMEM_DIN15_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 21 + 3 + read-write + + + SPI_SMEM_DINS_HEX_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 24 + 3 + read-write + + + + + SPI_SMEM_DIN_HEX_NUM + MSPI 16x external RAM input timing delay number control register + 0x1A8 + 0x20 + + + SPI_SMEM_DIN08_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 0 + 2 + read-write + + + SPI_SMEM_DIN09_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 2 + 2 + read-write + + + SPI_SMEM_DIN10_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 4 + 2 + read-write + + + SPI_SMEM_DIN11_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 6 + 2 + read-write + + + SPI_SMEM_DIN12_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 8 + 2 + read-write + + + SPI_SMEM_DIN13_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 10 + 2 + read-write + + + SPI_SMEM_DIN14_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 12 + 2 + read-write + + + SPI_SMEM_DIN15_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 14 + 2 + read-write + + + SPI_SMEM_DINS_HEX_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 16 + 2 + read-write + + + + + SPI_SMEM_DOUT_HEX_MODE + MSPI 16x external RAM output timing adjustment control register + 0x1AC + 0x20 + + + SPI_SMEM_DOUT08_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 0 + 1 + read-write + + + SPI_SMEM_DOUT09_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 1 + 1 + read-write + + + SPI_SMEM_DOUT10_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 2 + 1 + read-write + + + SPI_SMEM_DOUT11_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 3 + 1 + read-write + + + SPI_SMEM_DOUT12_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 4 + 1 + read-write + + + SPI_SMEM_DOUT13_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 5 + 1 + read-write + + + SPI_SMEM_DOUT14_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 6 + 1 + read-write + + + SPI_SMEM_DOUT15_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 7 + 1 + read-write + + + SPI_SMEM_DOUTS_HEX_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 8 + 1 + read-write + + + + + SPI_MEM_CLOCK_GATE + SPI0 clock gate register + 0x200 + 0x20 + 0x00000001 + + + SPI_CLK_EN + Register clock gate enable signal. 1: Enable. 0: Disable. + 0 + 1 + read-write + + + + + SPI_MEM_XTS_PLAIN_BASE + The base address of the memory that stores plaintext in Manual Encryption + 0x300 + 0x20 + + + SPI_XTS_PLAIN + This field is only used to generate include file in c case. This field is useless. Please do not use this field. + 0 + 32 + read-write + + + + + SPI_MEM_XTS_LINESIZE + Manual Encryption Line-Size register + 0x340 + 0x20 + + + SPI_XTS_LINESIZE + This bits stores the line-size parameter which will be used in manual encryption calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, 1: 32-bytes, 2: 64-bytes, 3:reserved. + 0 + 2 + read-write + + + + + SPI_MEM_XTS_DESTINATION + Manual Encryption destination register + 0x344 + 0x20 + + + SPI_XTS_DESTINATION + This bit stores the destination parameter which will be used in manual encryption calculation. 0: flash(default), 1: psram(reserved). Only default value can be used. + 0 + 1 + read-write + + + + + SPI_MEM_XTS_PHYSICAL_ADDRESS + Manual Encryption physical address register + 0x348 + 0x20 + + + SPI_XTS_PHYSICAL_ADDRESS + This bits stores the physical-address parameter which will be used in manual encryption calculation. This value should aligned with byte number decided by line-size parameter. + 0 + 26 + read-write + + + + + SPI_MEM_XTS_TRIGGER + Manual Encryption physical address register + 0x34C + 0x20 + + + SPI_XTS_TRIGGER + Set this bit to trigger the process of manual encryption calculation. This action should only be asserted when manual encryption status is 0. After this action, manual encryption status becomes 1. After calculation is done, manual encryption status becomes 2. + 0 + 1 + write-only + + + + + SPI_MEM_XTS_RELEASE + Manual Encryption physical address register + 0x350 + 0x20 + + + SPI_XTS_RELEASE + Set this bit to release encrypted result to mspi. This action should only be asserted when manual encryption status is 2. After this action, manual encryption status will become 3. + 0 + 1 + write-only + + + + + SPI_MEM_XTS_DESTROY + Manual Encryption physical address register + 0x354 + 0x20 + + + SPI_XTS_DESTROY + Set this bit to destroy encrypted result. This action should be asserted only when manual encryption status is 3. After this action, manual encryption status will become 0. + 0 + 1 + write-only + + + + + SPI_MEM_XTS_STATE + Manual Encryption physical address register + 0x358 + 0x20 + + + SPI_XTS_STATE + This bits stores the status of manual encryption. 0: idle, 1: busy of encryption calculation, 2: encryption calculation is done but the encrypted result is invisible to mspi, 3: the encrypted result is visible to mspi. + 0 + 2 + read-only + + + + + SPI_MEM_XTS_DATE + Manual Encryption version register + 0x35C + 0x20 + 0x20201010 + + + SPI_XTS_DATE + This bits stores the last modified-time of manual encryption feature. + 0 + 30 + read-write + + + + + SPI_MEM_MMU_ITEM_CONTENT + MSPI-MMU item content register + 0x37C + 0x20 + 0x0000037C + + + SPI_MMU_ITEM_CONTENT + MSPI-MMU item content + 0 + 32 + read-write + + + + + SPI_MEM_MMU_ITEM_INDEX + MSPI-MMU item index register + 0x380 + 0x20 + + + SPI_MMU_ITEM_INDEX + MSPI-MMU item index + 0 + 32 + read-write + + + + + SPI_MEM_MMU_POWER_CTRL + MSPI MMU power control register + 0x384 + 0x20 + 0x13200004 + + + SPI_MMU_MEM_FORCE_ON + Set this bit to enable mmu-memory clock force on + 0 + 1 + read-write + + + SPI_MMU_MEM_FORCE_PD + Set this bit to force mmu-memory powerdown + 1 + 1 + read-write + + + SPI_MMU_MEM_FORCE_PU + Set this bit to force mmu-memory powerup, in this case, the power should also be controlled by rtc. + 2 + 1 + read-write + + + SPI_MEM_AUX_CTRL + MMU PSRAM aux control register + 16 + 14 + read-write + + + SPI_MEM_RDN_ENA + ECO register enable bit + 30 + 1 + read-write + + + SPI_MEM_RDN_RESULT + MSPI module clock domain and AXI clock domain ECO register result register + 31 + 1 + read-only + + + + + SPI_MEM_DPA_CTRL + SPI memory cryption DPA register + 0x388 + 0x20 + 0x0000000F + + + SPI_CRYPT_SECURITY_LEVEL + Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-7: The bigger the number is, the more secure the cryption is. (Note that the performance of cryption will decrease together with this number increasing) + 0 + 3 + read-write + + + SPI_CRYPT_CALC_D_DPA_EN + Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that using key 1. + 3 + 1 + read-write + + + SPI_CRYPT_DPA_SELECT_REGISTER + 1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits. + 4 + 1 + read-write + + + + + SPI_MEM_REGISTERRND_ECO_HIGH + MSPI ECO high register + 0x3F0 + 0x20 + 0x0000037C + + + SPI_MEM_REGISTERRND_ECO_HIGH + ECO high register + 0 + 32 + read-write + + + + + SPI_MEM_REGISTERRND_ECO_LOW + MSPI ECO low register + 0x3F4 + 0x20 + 0x0000037C + + + SPI_MEM_REGISTERRND_ECO_LOW + ECO low register + 0 + 32 + read-write + + + + + SPI_MEM_DATE + SPI0 version control register + 0x3FC + 0x20 + 0x02303100 + + + SPI_MEM_DATE + SPI0 register version. + 0 + 28 + read-write + + + + + + + SPI1 + SPI (Serial Peripheral Interface) Controller 1 + SPI1 + 0x5008D000 + + 0x0 + 0xAC + registers + + + + SPI_MEM_CMD + SPI1 memory command register + 0x0 + 0x20 + + + SPI_MEM_MST_ST + The current status of SPI1 master FSM. + 0 + 4 + read-only + + + SPI_MEM_SLV_ST + The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state. + 4 + 4 + read-only + + + SPI_MEM_FLASH_PE + In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable. + 17 + 1 + read-write + + + SPI_MEM_USR + User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 18 + 1 + read-write + + + SPI_MEM_FLASH_HPM + Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable. + 19 + 1 + read-write + + + SPI_MEM_FLASH_RES + This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable. + 20 + 1 + read-write + + + SPI_MEM_FLASH_DP + Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 21 + 1 + read-write + + + SPI_MEM_FLASH_CE + Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 22 + 1 + read-write + + + SPI_MEM_FLASH_BE + Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 23 + 1 + read-write + + + SPI_MEM_FLASH_SE + Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 24 + 1 + read-write + + + SPI_MEM_FLASH_PP + Page program enable(1 byte ~256 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable. + 25 + 1 + read-write + + + SPI_MEM_FLASH_WRSR + Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 26 + 1 + read-write + + + SPI_MEM_FLASH_RDSR + Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 27 + 1 + read-write + + + SPI_MEM_FLASH_RDID + Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. + 28 + 1 + read-write + + + SPI_MEM_FLASH_WRDI + Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. + 29 + 1 + read-write + + + SPI_MEM_FLASH_WREN + Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. + 30 + 1 + read-write + + + SPI_MEM_FLASH_READ + Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. + 31 + 1 + read-write + + + + + SPI_MEM_ADDR + SPI1 address register + 0x4 + 0x20 + + + SPI_MEM_USR_ADDR_VALUE + In user mode, it is the memory address. other then the bit0-bit23 is the memory address, the bit24-bit31 are the byte length of a transfer. + 0 + 32 + read-write + + + + + SPI_MEM_CTRL + SPI1 control register. + 0x8 + 0x20 + 0x002CA00C + + + SPI_MEM_FDUMMY_RIN + In the dummy phase of a MSPI read data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller. + 2 + 1 + read-write + + + SPI_MEM_FDUMMY_WOUT + In the dummy phase of a MSPI write data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller. + 3 + 1 + read-write + + + SPI_MEM_FDOUT_OCT + Apply 8 signals during write-data phase 1:enable 0: disable + 4 + 1 + read-write + + + SPI_MEM_FDIN_OCT + Apply 8 signals during read-data phase 1:enable 0: disable + 5 + 1 + read-write + + + SPI_MEM_FADDR_OCT + Apply 8 signals during address phase 1:enable 0: disable + 6 + 1 + read-write + + + SPI_MEM_FCMD_QUAD + Apply 4 signals during command phase 1:enable 0: disable + 8 + 1 + read-write + + + SPI_MEM_FCMD_OCT + Apply 8 signals during command phase 1:enable 0: disable + 9 + 1 + read-write + + + SPI_MEM_FCS_CRC_EN + For SPI1, initialize crc32 module before writing encrypted data to flash. Active low. + 10 + 1 + read-write + + + SPI_MEM_TX_CRC_EN + For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable + 11 + 1 + read-write + + + SPI_MEM_FASTRD_MODE + This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable. + 13 + 1 + read-write + + + SPI_MEM_FREAD_DUAL + In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. + 14 + 1 + read-write + + + SPI_MEM_RESANDRES + The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable. + 15 + 1 + read-write + + + SPI_MEM_Q_POL + The bit is used to set MISO line polarity, 1: high 0, low + 18 + 1 + read-write + + + SPI_MEM_D_POL + The bit is used to set MOSI line polarity, 1: high 0, low + 19 + 1 + read-write + + + SPI_MEM_FREAD_QUAD + In the read operations read-data phase apply 4 signals. 1: enable 0: disable. + 20 + 1 + read-write + + + SPI_MEM_WP + Write protect signal output when SPI is idle. 1: output high, 0: output low. + 21 + 1 + read-write + + + SPI_MEM_WRSR_2B + two bytes data will be written to status register when it is set. 1: enable 0: disable. + 22 + 1 + read-write + + + SPI_MEM_FREAD_DIO + In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable. + 23 + 1 + read-write + + + SPI_MEM_FREAD_QIO + In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable. + 24 + 1 + read-write + + + + + SPI_MEM_CTRL1 + SPI1 control1 register. + 0xC + 0x20 + 0x00000FFC + + + SPI_MEM_CLK_MODE + SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. + 0 + 2 + read-write + + + SPI_MEM_CS_HOLD_DLY_RES + After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles. + 2 + 10 + read-write + + + + + SPI_MEM_CTRL2 + SPI1 control2 register. + 0x10 + 0x20 + + + SPI_MEM_SYNC_RESET + The FSM will be reset. + 31 + 1 + write-only + + + + + SPI_MEM_CLOCK + SPI1 clock division control register. + 0x14 + 0x20 + 0x00030103 + + + SPI_MEM_CLKCNT_L + In the master mode it must be equal to spi_mem_clkcnt_N. + 0 + 8 + read-write + + + SPI_MEM_CLKCNT_H + In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). + 8 + 8 + read-write + + + SPI_MEM_CLKCNT_N + In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1) + 16 + 8 + read-write + + + SPI_MEM_CLK_EQU_SYSCLK + reserved + 31 + 1 + read-write + + + + + SPI_MEM_USER + SPI1 user register. + 0x18 + 0x20 + 0x80000000 + + + SPI_MEM_CK_OUT_EDGE + the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode. + 9 + 1 + read-write + + + SPI_MEM_FWRITE_DUAL + In the write operations read-data phase apply 2 signals + 12 + 1 + read-write + + + SPI_MEM_FWRITE_QUAD + In the write operations read-data phase apply 4 signals + 13 + 1 + read-write + + + SPI_MEM_FWRITE_DIO + In the write operations address phase and read-data phase apply 2 signals. + 14 + 1 + read-write + + + SPI_MEM_FWRITE_QIO + In the write operations address phase and read-data phase apply 4 signals. + 15 + 1 + read-write + + + SPI_MEM_USR_MISO_HIGHPART + read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable. + 24 + 1 + read-write + + + SPI_MEM_USR_MOSI_HIGHPART + write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable. + 25 + 1 + read-write + + + SPI_MEM_USR_DUMMY_IDLE + SPI clock is disable in dummy phase when the bit is enable. + 26 + 1 + read-write + + + SPI_MEM_USR_MOSI + This bit enable the write-data phase of an operation. + 27 + 1 + read-write + + + SPI_MEM_USR_MISO + This bit enable the read-data phase of an operation. + 28 + 1 + read-write + + + SPI_MEM_USR_DUMMY + This bit enable the dummy phase of an operation. + 29 + 1 + read-write + + + SPI_MEM_USR_ADDR + This bit enable the address phase of an operation. + 30 + 1 + read-write + + + SPI_MEM_USR_COMMAND + This bit enable the command phase of an operation. + 31 + 1 + read-write + + + + + SPI_MEM_USER1 + SPI1 user1 register. + 0x1C + 0x20 + 0x5C000007 + + + SPI_MEM_USR_DUMMY_CYCLELEN + The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1). + 0 + 6 + read-write + + + SPI_MEM_USR_ADDR_BITLEN + The length in bits of address phase. The register value shall be (bit_num-1). + 26 + 6 + read-write + + + + + SPI_MEM_USER2 + SPI1 user2 register. + 0x20 + 0x20 + 0x70000000 + + + SPI_MEM_USR_COMMAND_VALUE + The value of command. + 0 + 16 + read-write + + + SPI_MEM_USR_COMMAND_BITLEN + The length in bits of command phase. The register value shall be (bit_num-1) + 28 + 4 + read-write + + + + + SPI_MEM_MOSI_DLEN + SPI1 send data bit length control register. + 0x24 + 0x20 + + + SPI_MEM_USR_MOSI_DBITLEN + The length in bits of write-data. The register value shall be (bit_num-1). + 0 + 10 + read-write + + + + + SPI_MEM_MISO_DLEN + SPI1 receive data bit length control register. + 0x28 + 0x20 + + + SPI_MEM_USR_MISO_DBITLEN + The length in bits of read-data. The register value shall be (bit_num-1). + 0 + 10 + read-write + + + + + SPI_MEM_RD_STATUS + SPI1 status register. + 0x2C + 0x20 + + + SPI_MEM_STATUS + The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit. + 0 + 16 + read-write + + + SPI_MEM_WB_MODE + Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. + 16 + 8 + read-write + + + + + SPI_MEM_MISC + SPI1 misc register + 0x34 + 0x20 + 0x00000002 + + + SPI_MEM_CS0_DIS + SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI device, such as flash, external RAM and so on. + 0 + 1 + read-write + + + SPI_MEM_CS1_DIS + SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI device, such as flash, external RAM and so on. + 1 + 1 + read-write + + + SPI_MEM_CK_IDLE_EDGE + 1: spi clk line is high when idle 0: spi clk line is low when idle + 9 + 1 + read-write + + + SPI_MEM_CS_KEEP_ACTIVE + spi cs line keep low when the bit is set. + 10 + 1 + read-write + + + + + SPI_MEM_TX_CRC + SPI1 TX CRC data register. + 0x38 + 0x20 + 0xFFFFFFFF + + + DATA + For SPI1, the value of crc32. + 0 + 32 + read-only + + + + + SPI_MEM_CACHE_FCTRL + SPI1 bit mode control register. + 0x3C + 0x20 + + + SPI_MEM_CACHE_USR_ADDR_4BYTE + For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable. + 1 + 1 + read-write + + + SPI_MEM_FDIN_DUAL + For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. + 3 + 1 + read-write + + + SPI_MEM_FDOUT_DUAL + For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. + 4 + 1 + read-write + + + SPI_MEM_FADDR_DUAL + For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. + 5 + 1 + read-write + + + SPI_MEM_FDIN_QUAD + For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. + 6 + 1 + read-write + + + SPI_MEM_FDOUT_QUAD + For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. + 7 + 1 + read-write + + + SPI_MEM_FADDR_QUAD + For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. + 8 + 1 + read-write + + + + + SPI_MEM_W0 + SPI1 memory data buffer0 + 0x58 + 0x20 + + + SPI_MEM_BUF0 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W1 + SPI1 memory data buffer1 + 0x5C + 0x20 + + + SPI_MEM_BUF1 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W2 + SPI1 memory data buffer2 + 0x60 + 0x20 + + + SPI_MEM_BUF2 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W3 + SPI1 memory data buffer3 + 0x64 + 0x20 + + + SPI_MEM_BUF3 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W4 + SPI1 memory data buffer4 + 0x68 + 0x20 + + + SPI_MEM_BUF4 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W5 + SPI1 memory data buffer5 + 0x6C + 0x20 + + + SPI_MEM_BUF5 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W6 + SPI1 memory data buffer6 + 0x70 + 0x20 + + + SPI_MEM_BUF6 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W7 + SPI1 memory data buffer7 + 0x74 + 0x20 + + + SPI_MEM_BUF7 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W8 + SPI1 memory data buffer8 + 0x78 + 0x20 + + + SPI_MEM_BUF8 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W9 + SPI1 memory data buffer9 + 0x7C + 0x20 + + + SPI_MEM_BUF9 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W10 + SPI1 memory data buffer10 + 0x80 + 0x20 + + + SPI_MEM_BUF10 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W11 + SPI1 memory data buffer11 + 0x84 + 0x20 + + + SPI_MEM_BUF11 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W12 + SPI1 memory data buffer12 + 0x88 + 0x20 + + + SPI_MEM_BUF12 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W13 + SPI1 memory data buffer13 + 0x8C + 0x20 + + + SPI_MEM_BUF13 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W14 + SPI1 memory data buffer14 + 0x90 + 0x20 + + + SPI_MEM_BUF14 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W15 + SPI1 memory data buffer15 + 0x94 + 0x20 + + + SPI_MEM_BUF15 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_FLASH_WAITI_CTRL + SPI1 wait idle control register + 0x98 + 0x20 + 0x00050001 + + + SPI_MEM_WAITI_EN + 1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto Suspend/Resume are not supported. + 0 + 1 + read-write + + + SPI_MEM_WAITI_DUMMY + The dummy phase enable when wait flash idle (RDSR) + 1 + 1 + read-write + + + SPI_MEM_WAITI_ADDR_EN + 1: Output address 0 in RDSR or read SUS command transfer. 0: Do not send out address in RDSR or read SUS command transfer. + 2 + 1 + read-write + + + SPI_MEM_WAITI_ADDR_CYCLELEN + When SPI_MEM_WAITI_ADDR_EN is set, the cycle length of sent out address is (SPI_MEM_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI bus clock cycles. It is not active when SPI_MEM_WAITI_ADDR_EN is cleared. + 3 + 2 + read-write + + + SPI_MEM_WAITI_CMD_2B + 1:The wait idle command bit length is 16. 0: The wait idle command bit length is 8. + 9 + 1 + read-write + + + SPI_MEM_WAITI_DUMMY_CYCLELEN + The dummy cycle length when wait flash idle(RDSR). + 10 + 6 + read-write + + + SPI_MEM_WAITI_CMD + The command value to wait flash idle(RDSR). + 16 + 16 + read-write + + + + + SPI_MEM_FLASH_SUS_CTRL + SPI1 flash suspend control register + 0x9C + 0x20 + 0x08002000 + + + SPI_MEM_FLASH_PER + program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 0 + 1 + read-write + + + SPI_MEM_FLASH_PES + program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 1 + 1 + read-write + + + SPI_MEM_FLASH_PER_WAIT_EN + 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase resume command is sent. 0: SPI1 does not wait after program erase resume command is sent. + 2 + 1 + read-write + + + SPI_MEM_FLASH_PES_WAIT_EN + 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase suspend command is sent. 0: SPI1 does not wait after program erase suspend command is sent. + 3 + 1 + read-write + + + SPI_MEM_PES_PER_EN + Set this bit to enable PES end triggers PER transfer option. If this bit is 0, application should send PER after PES is done. + 4 + 1 + read-write + + + SPI_MEM_FLASH_PES_EN + Set this bit to enable Auto-suspending function. + 5 + 1 + read-write + + + SPI_MEM_PESR_END_MSK + The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0]. + 6 + 16 + read-write + + + SPI_FMEM_RD_SUS_2B + 1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte when check flash SUS/SUS1/SUS2 status bit + 22 + 1 + read-write + + + SPI_MEM_PER_END_EN + 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0. + 23 + 1 + read-write + + + SPI_MEM_PES_END_EN + 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0. + 24 + 1 + read-write + + + SPI_MEM_SUS_TIMEOUT_CNT + When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, it will be treated as check pass. + 25 + 7 + read-write + + + + + SPI_MEM_FLASH_SUS_CMD + SPI1 flash suspend command register + 0xA0 + 0x20 + 0x00057575 + + + SPI_MEM_FLASH_PES_COMMAND + Program/Erase suspend command. + 0 + 16 + read-write + + + SPI_MEM_WAIT_PESR_COMMAND + Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash. + 16 + 16 + read-write + + + + + SPI_MEM_SUS_STATUS + SPI1 flash suspend status register + 0xA4 + 0x20 + 0x7A7A0000 + + + SPI_MEM_FLASH_SUS + The status of flash suspend, only used in SPI1. + 0 + 1 + read-write + + + SPI_MEM_WAIT_PESR_CMD_2B + 1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit. + 1 + 1 + read-write + + + SPI_MEM_FLASH_HPM_DLY_128 + 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent. + 2 + 1 + read-write + + + SPI_MEM_FLASH_RES_DLY_128 + 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent. + 3 + 1 + read-write + + + SPI_MEM_FLASH_DP_DLY_128 + 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent. + 4 + 1 + read-write + + + SPI_MEM_FLASH_PER_DLY_128 + Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent. + 5 + 1 + read-write + + + SPI_MEM_FLASH_PES_DLY_128 + Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent. + 6 + 1 + read-write + + + SPI_MEM_SPI0_LOCK_EN + 1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it. + 7 + 1 + read-write + + + SPI_MEM_FLASH_PESR_CMD_2B + 1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit length of Program/Erase Suspend/Resume command is 8. + 15 + 1 + read-write + + + SPI_MEM_FLASH_PER_COMMAND + Program/Erase resume command. + 16 + 16 + read-write + + + + + SPI_MEM_INT_ENA + SPI1 interrupt enable register + 0xC0 + 0x20 + + + SPI_MEM_PER_END_INT_ENA + The enable bit for SPI_MEM_PER_END_INT interrupt. + 0 + 1 + read-write + + + SPI_MEM_PES_END_INT_ENA + The enable bit for SPI_MEM_PES_END_INT interrupt. + 1 + 1 + read-write + + + SPI_MEM_WPE_END_INT_ENA + The enable bit for SPI_MEM_WPE_END_INT interrupt. + 2 + 1 + read-write + + + SPI_MEM_SLV_ST_END_INT_ENA + The enable bit for SPI_MEM_SLV_ST_END_INT interrupt. + 3 + 1 + read-write + + + SPI_MEM_MST_ST_END_INT_ENA + The enable bit for SPI_MEM_MST_ST_END_INT interrupt. + 4 + 1 + read-write + + + SPI_MEM_BROWN_OUT_INT_ENA + The enable bit for SPI_MEM_BROWN_OUT_INT interrupt. + 10 + 1 + read-write + + + + + SPI_MEM_INT_CLR + SPI1 interrupt clear register + 0xC4 + 0x20 + + + SPI_MEM_PER_END_INT_CLR + The clear bit for SPI_MEM_PER_END_INT interrupt. + 0 + 1 + write-only + + + SPI_MEM_PES_END_INT_CLR + The clear bit for SPI_MEM_PES_END_INT interrupt. + 1 + 1 + write-only + + + SPI_MEM_WPE_END_INT_CLR + The clear bit for SPI_MEM_WPE_END_INT interrupt. + 2 + 1 + write-only + + + SPI_MEM_SLV_ST_END_INT_CLR + The clear bit for SPI_MEM_SLV_ST_END_INT interrupt. + 3 + 1 + write-only + + + SPI_MEM_MST_ST_END_INT_CLR + The clear bit for SPI_MEM_MST_ST_END_INT interrupt. + 4 + 1 + write-only + + + SPI_MEM_BROWN_OUT_INT_CLR + The status bit for SPI_MEM_BROWN_OUT_INT interrupt. + 10 + 1 + write-only + + + + + SPI_MEM_INT_RAW + SPI1 interrupt raw register + 0xC8 + 0x20 + + + SPI_MEM_PER_END_INT_RAW + The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed successfully. 0: Others. + 0 + 1 + read-write + + + SPI_MEM_PES_END_INT_RAW + The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended successfully. 0: Others. + 1 + 1 + read-write + + + SPI_MEM_WPE_END_INT_RAW + The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others. + 2 + 1 + read-write + + + SPI_MEM_SLV_ST_END_INT_RAW + The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others + 3 + 1 + read-write + + + SPI_MEM_MST_ST_END_INT_RAW + The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is changed from non idle state to idle state. 0: Others. + 4 + 1 + read-write + + + SPI_MEM_BROWN_OUT_INT_RAW + The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is loosing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others. + 10 + 1 + read-write + + + + + SPI_MEM_INT_ST + SPI1 interrupt status register + 0xCC + 0x20 + + + SPI_MEM_PER_END_INT_ST + The status bit for SPI_MEM_PER_END_INT interrupt. + 0 + 1 + read-only + + + SPI_MEM_PES_END_INT_ST + The status bit for SPI_MEM_PES_END_INT interrupt. + 1 + 1 + read-only + + + SPI_MEM_WPE_END_INT_ST + The status bit for SPI_MEM_WPE_END_INT interrupt. + 2 + 1 + read-only + + + SPI_MEM_SLV_ST_END_INT_ST + The status bit for SPI_MEM_SLV_ST_END_INT interrupt. + 3 + 1 + read-only + + + SPI_MEM_MST_ST_END_INT_ST + The status bit for SPI_MEM_MST_ST_END_INT interrupt. + 4 + 1 + read-only + + + SPI_MEM_BROWN_OUT_INT_ST + The status bit for SPI_MEM_BROWN_OUT_INT interrupt. + 10 + 1 + read-only + + + + + SPI_MEM_DDR + SPI1 DDR control register + 0xD4 + 0x20 + 0x00000020 + + + SPI_FMEM_DDR_EN + 1: in ddr mode, 0 in sdr mode + 0 + 1 + read-write + + + SPI_FMEM_VAR_DUMMY + Set the bit to enable variable dummy cycle in spi ddr mode. + 1 + 1 + read-write + + + SPI_FMEM_DDR_RDAT_SWP + Set the bit to reorder rx data of the word in spi ddr mode. + 2 + 1 + read-write + + + SPI_FMEM_DDR_WDAT_SWP + Set the bit to reorder tx data of the word in spi ddr mode. + 3 + 1 + read-write + + + SPI_FMEM_DDR_CMD_DIS + the bit is used to disable dual edge in command phase when ddr mode. + 4 + 1 + read-write + + + SPI_FMEM_OUTMINBYTELEN + It is the minimum output data length in the panda device. + 5 + 7 + read-write + + + SPI_FMEM_USR_DDR_DQS_THD + The delay number of data strobe which from memory based on SPI clock. + 14 + 7 + read-write + + + SPI_FMEM_DDR_DQS_LOOP + 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS. + 21 + 1 + read-write + + + SPI_FMEM_CLK_DIFF_EN + Set this bit to enable the differential SPI_CLK#. + 24 + 1 + read-write + + + SPI_FMEM_DQS_CA_IN + Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + 26 + 1 + read-write + + + SPI_FMEM_HYPERBUS_DUMMY_2X + Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram. + 27 + 1 + read-write + + + SPI_FMEM_CLK_DIFF_INV + Set this bit to invert SPI_DIFF when accesses to flash. . + 28 + 1 + read-write + + + SPI_FMEM_OCTA_RAM_ADDR + Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. + 29 + 1 + read-write + + + SPI_FMEM_HYPERBUS_CA + Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. + 30 + 1 + read-write + + + + + SPI_MEM_TIMING_CALI + SPI1 timing control register + 0x180 + 0x20 + + + SPI_MEM_TIMING_CALI + The bit is used to enable timing auto-calibration for all reading operations. + 1 + 1 + read-write + + + SPI_MEM_EXTRA_DUMMY_CYCLELEN + add extra dummy spi clock cycle length for spi clock calibration. + 2 + 3 + read-write + + + + + SPI_MEM_CLOCK_GATE + SPI1 clk_gate register + 0x200 + 0x20 + 0x00000001 + + + SPI_MEM_CLK_EN + Register clock gate enable signal. 1: Enable. 0: Disable. + 0 + 1 + read-write + + + + + SPI_MEM_DATE + Version control register + 0x3FC + 0x20 + 0x02111240 + + + SPI_MEM_DATE + Version control register + 0 + 28 + read-write + + + + + + + SPI2 + SPI (Serial Peripheral Interface) Controller 2 + SPI2 + 0x500D0000 + + 0x0 + 0x98 + registers + + + SPI2 + 25 + + + + SPI_CMD + Command control register + 0x0 + 0x20 + + + SPI_CONF_BITLEN + Define the APB cycles of SPI_CONF state. Can be configured in CONF state. + 0 + 18 + read-write + + + SPI_UPDATE + Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode. + 23 + 1 + write-only + + + SPI_USR + User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf. + 24 + 1 + read-write + + + + + SPI_ADDR + Address value register + 0x4 + 0x20 + + + SPI_USR_ADDR_VALUE + Address to slave. Can be configured in CONF state. + 0 + 32 + read-write + + + + + SPI_CTRL + SPI control register + 0x8 + 0x20 + 0x003C0000 + + + SPI_DUMMY_OUT + 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state. + 3 + 1 + read-write + + + SPI_FADDR_DUAL + Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state. + 5 + 1 + read-write + + + SPI_FADDR_QUAD + Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state. + 6 + 1 + read-write + + + SPI_FADDR_OCT + Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF state. + 7 + 1 + read-write + + + SPI_FCMD_DUAL + Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state. + 8 + 1 + read-write + + + SPI_FCMD_QUAD + Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state. + 9 + 1 + read-write + + + SPI_FCMD_OCT + Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF state. + 10 + 1 + read-write + + + SPI_FREAD_DUAL + In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state. + 14 + 1 + read-write + + + SPI_FREAD_QUAD + In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state. + 15 + 1 + read-write + + + SPI_FREAD_OCT + In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can be configured in CONF state. + 16 + 1 + read-write + + + SPI_Q_POL + The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state. + 18 + 1 + read-write + + + SPI_D_POL + The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state. + 19 + 1 + read-write + + + SPI_HOLD_POL + SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state. + 20 + 1 + read-write + + + SPI_WP_POL + Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state. + 21 + 1 + read-write + + + SPI_RD_BIT_ORDER + In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state. + 23 + 2 + read-write + + + SPI_WR_BIT_ORDER + In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state. + 25 + 2 + read-write + + + + + SPI_CLOCK + SPI clock control register + 0xC + 0x20 + 0x80003043 + + + SPI_CLKCNT_L + In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state. + 0 + 6 + read-write + + + SPI_CLKCNT_H + In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state. + 6 + 6 + read-write + + + SPI_CLKCNT_N + In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state. + 12 + 6 + read-write + + + SPI_CLKDIV_PRE + In the master mode it is pre-divider of spi_clk. Can be configured in CONF state. + 18 + 4 + read-write + + + SPI_CLK_EQU_SYSCLK + In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state. + 31 + 1 + read-write + + + + + SPI_USER + SPI USER control register + 0x10 + 0x20 + 0x800000C0 + + + SPI_DOUTDIN + Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state. + 0 + 1 + read-write + + + SPI_QPI_MODE + Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state. + 3 + 1 + read-write + + + SPI_OPI_MODE + Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. Can be configured in CONF state. + 4 + 1 + read-write + + + SPI_TSCK_I_EDGE + In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i. + 5 + 1 + read-write + + + SPI_CS_HOLD + spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state. + 6 + 1 + read-write + + + SPI_CS_SETUP + spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state. + 7 + 1 + read-write + + + SPI_RSCK_I_EDGE + In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i. + 8 + 1 + read-write + + + SPI_CK_OUT_EDGE + the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state. + 9 + 1 + read-write + + + SPI_FWRITE_DUAL + In the write operations read-data phase apply 2 signals. Can be configured in CONF state. + 12 + 1 + read-write + + + SPI_FWRITE_QUAD + In the write operations read-data phase apply 4 signals. Can be configured in CONF state. + 13 + 1 + read-write + + + SPI_FWRITE_OCT + In the write operations read-data phase apply 8 signals. Can be configured in CONF state. + 14 + 1 + read-write + + + SPI_USR_CONF_NXT + 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state. + 15 + 1 + read-write + + + SPI_SIO + Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state. + 17 + 1 + read-write + + + SPI_USR_MISO_HIGHPART + read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state. + 24 + 1 + read-write + + + SPI_USR_MOSI_HIGHPART + write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state. + 25 + 1 + read-write + + + SPI_USR_DUMMY_IDLE + spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state. + 26 + 1 + read-write + + + SPI_USR_MOSI + This bit enable the write-data phase of an operation. Can be configured in CONF state. + 27 + 1 + read-write + + + SPI_USR_MISO + This bit enable the read-data phase of an operation. Can be configured in CONF state. + 28 + 1 + read-write + + + SPI_USR_DUMMY + This bit enable the dummy phase of an operation. Can be configured in CONF state. + 29 + 1 + read-write + + + SPI_USR_ADDR + This bit enable the address phase of an operation. Can be configured in CONF state. + 30 + 1 + read-write + + + SPI_USR_COMMAND + This bit enable the command phase of an operation. Can be configured in CONF state. + 31 + 1 + read-write + + + + + SPI_USER1 + SPI USER control register 1 + 0x14 + 0x20 + 0xB8410007 + + + SPI_USR_DUMMY_CYCLELEN + The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state. + 0 + 8 + read-write + + + SPI_MST_WFULL_ERR_END_EN + 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. + 16 + 1 + read-write + + + SPI_CS_SETUP_TIME + (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state. + 17 + 5 + read-write + + + SPI_CS_HOLD_TIME + delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state. + 22 + 5 + read-write + + + SPI_USR_ADDR_BITLEN + The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state. + 27 + 5 + read-write + + + + + SPI_USER2 + SPI USER control register 2 + 0x18 + 0x20 + 0x78000000 + + + SPI_USR_COMMAND_VALUE + The value of command. Can be configured in CONF state. + 0 + 16 + read-write + + + SPI_MST_REMPTY_ERR_END_EN + 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. + 27 + 1 + read-write + + + SPI_USR_COMMAND_BITLEN + The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state. + 28 + 4 + read-write + + + + + SPI_MS_DLEN + SPI data bit length control register + 0x1C + 0x20 + + + SPI_MS_DATA_BITLEN + The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state. + 0 + 18 + read-write + + + + + SPI_MISC + SPI misc register + 0x20 + 0x20 + 0x0000003E + + + SPI_CS0_DIS + SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state. + 0 + 1 + read-write + + + SPI_CS1_DIS + SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state. + 1 + 1 + read-write + + + SPI_CS2_DIS + SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state. + 2 + 1 + read-write + + + SPI_CS3_DIS + SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to CS3 pin. Can be configured in CONF state. + 3 + 1 + read-write + + + SPI_CS4_DIS + SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be configured in CONF state. + 4 + 1 + read-write + + + SPI_CS5_DIS + SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be configured in CONF state. + 5 + 1 + read-write + + + SPI_CK_DIS + 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state. + 6 + 1 + read-write + + + SPI_MASTER_CS_POL + In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state. + 7 + 6 + read-write + + + SPI_CLK_DATA_DTR_EN + 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR mode is only applied to spi_dqs. This bit should be used with bit 17/18/19. + 16 + 1 + read-write + + + SPI_DATA_DTR_EN + 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state. + 17 + 1 + read-write + + + SPI_ADDR_DTR_EN + 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state. + 18 + 1 + read-write + + + SPI_CMD_DTR_EN + 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state. + 19 + 1 + read-write + + + SPI_SLAVE_CS_POL + spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state. + 23 + 1 + read-write + + + SPI_DQS_IDLE_EDGE + The default value of spi_dqs. Can be configured in CONF state. + 24 + 1 + read-write + + + SPI_CK_IDLE_EDGE + 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state. + 29 + 1 + read-write + + + SPI_CS_KEEP_ACTIVE + spi cs line keep low when the bit is set. Can be configured in CONF state. + 30 + 1 + read-write + + + SPI_QUAD_DIN_PIN_SWAP + 1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0: spi quad input swap disable. Can be configured in CONF state. + 31 + 1 + read-write + + + + + SPI_DIN_MODE + SPI input delay mode configuration + 0x24 + 0x20 + + + SPI_DIN0_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 0 + 2 + read-write + + + SPI_DIN1_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 2 + 2 + read-write + + + SPI_DIN2_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 4 + 2 + read-write + + + SPI_DIN3_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 6 + 2 + read-write + + + SPI_DIN4_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 8 + 2 + read-write + + + SPI_DIN5_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 10 + 2 + read-write + + + SPI_DIN6_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 12 + 2 + read-write + + + SPI_DIN7_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 14 + 2 + read-write + + + SPI_TIMING_HCLK_ACTIVE + 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state. + 16 + 1 + read-write + + + + + SPI_DIN_NUM + SPI input delay number configuration + 0x28 + 0x20 + + + SPI_DIN0_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 0 + 2 + read-write + + + SPI_DIN1_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 2 + 2 + read-write + + + SPI_DIN2_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 4 + 2 + read-write + + + SPI_DIN3_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 6 + 2 + read-write + + + SPI_DIN4_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 8 + 2 + read-write + + + SPI_DIN5_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 10 + 2 + read-write + + + SPI_DIN6_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 12 + 2 + read-write + + + SPI_DIN7_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 14 + 2 + read-write + + + + + SPI_DOUT_MODE + SPI output delay mode configuration + 0x2C + 0x20 + + + SPI_DOUT0_MODE + The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 0 + 1 + read-write + + + SPI_DOUT1_MODE + The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 1 + 1 + read-write + + + SPI_DOUT2_MODE + The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 2 + 1 + read-write + + + SPI_DOUT3_MODE + The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 3 + 1 + read-write + + + SPI_DOUT4_MODE + The output signal 4 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 4 + 1 + read-write + + + SPI_DOUT5_MODE + The output signal 5 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 5 + 1 + read-write + + + SPI_DOUT6_MODE + The output signal 6 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 6 + 1 + read-write + + + SPI_DOUT7_MODE + The output signal 7 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 7 + 1 + read-write + + + SPI_D_DQS_MODE + The output signal SPI_DQS is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 8 + 1 + read-write + + + + + SPI_DMA_CONF + SPI DMA control register + 0x30 + 0x20 + 0x00000003 + + + SPI_DMA_OUTFIFO_EMPTY + Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: DMA TX FIFO is ready for sending data. + 0 + 1 + read-only + + + SPI_DMA_INFIFO_FULL + Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. 0: DMA RX FIFO is ready for receiving data. + 1 + 1 + read-only + + + SPI_DMA_SLV_SEG_TRANS_EN + Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable. + 18 + 1 + read-write + + + SPI_SLV_RX_SEG_TRANS_CLR_EN + 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done. + 19 + 1 + read-write + + + SPI_SLV_TX_SEG_TRANS_CLR_EN + 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done. + 20 + 1 + read-write + + + SPI_RX_EOF_EN + 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans. + 21 + 1 + read-write + + + SPI_DMA_RX_ENA + Set this bit to enable SPI DMA controlled receive data mode. + 27 + 1 + read-write + + + SPI_DMA_TX_ENA + Set this bit to enable SPI DMA controlled send data mode. + 28 + 1 + read-write + + + SPI_RX_AFIFO_RST + Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer. + 29 + 1 + write-only + + + SPI_BUF_AFIFO_RST + Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer. + 30 + 1 + write-only + + + SPI_DMA_AFIFO_RST + Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer. + 31 + 1 + write-only + + + + + SPI_DMA_INT_ENA + SPI interrupt enable register + 0x34 + 0x20 + + + SPI_DMA_INFIFO_FULL_ERR_INT_ENA + The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + 0 + 1 + read-write + + + SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA + The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + 1 + 1 + read-write + + + SPI_SLV_EX_QPI_INT_ENA + The enable bit for SPI slave Ex_QPI interrupt. + 2 + 1 + read-write + + + SPI_SLV_EN_QPI_INT_ENA + The enable bit for SPI slave En_QPI interrupt. + 3 + 1 + read-write + + + SPI_SLV_CMD7_INT_ENA + The enable bit for SPI slave CMD7 interrupt. + 4 + 1 + read-write + + + SPI_SLV_CMD8_INT_ENA + The enable bit for SPI slave CMD8 interrupt. + 5 + 1 + read-write + + + SPI_SLV_CMD9_INT_ENA + The enable bit for SPI slave CMD9 interrupt. + 6 + 1 + read-write + + + SPI_SLV_CMDA_INT_ENA + The enable bit for SPI slave CMDA interrupt. + 7 + 1 + read-write + + + SPI_SLV_RD_DMA_DONE_INT_ENA + The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + 8 + 1 + read-write + + + SPI_SLV_WR_DMA_DONE_INT_ENA + The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + 9 + 1 + read-write + + + SPI_SLV_RD_BUF_DONE_INT_ENA + The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + 10 + 1 + read-write + + + SPI_SLV_WR_BUF_DONE_INT_ENA + The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + 11 + 1 + read-write + + + SPI_TRANS_DONE_INT_ENA + The enable bit for SPI_TRANS_DONE_INT interrupt. + 12 + 1 + read-write + + + SPI_DMA_SEG_TRANS_DONE_INT_ENA + The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + 13 + 1 + read-write + + + SPI_SEG_MAGIC_ERR_INT_ENA + The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt. + 14 + 1 + read-write + + + SPI_SLV_BUF_ADDR_ERR_INT_ENA + The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + 15 + 1 + read-write + + + SPI_SLV_CMD_ERR_INT_ENA + The enable bit for SPI_SLV_CMD_ERR_INT interrupt. + 16 + 1 + read-write + + + SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA + The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + 17 + 1 + read-write + + + SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA + The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + 18 + 1 + read-write + + + SPI_APP2_INT_ENA + The enable bit for SPI_APP2_INT interrupt. + 19 + 1 + read-write + + + SPI_APP1_INT_ENA + The enable bit for SPI_APP1_INT interrupt. + 20 + 1 + read-write + + + + + SPI_DMA_INT_CLR + SPI interrupt clear register + 0x38 + 0x20 + + + SPI_DMA_INFIFO_FULL_ERR_INT_CLR + The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + 0 + 1 + write-only + + + SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR + The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + 1 + 1 + write-only + + + SPI_SLV_EX_QPI_INT_CLR + The clear bit for SPI slave Ex_QPI interrupt. + 2 + 1 + write-only + + + SPI_SLV_EN_QPI_INT_CLR + The clear bit for SPI slave En_QPI interrupt. + 3 + 1 + write-only + + + SPI_SLV_CMD7_INT_CLR + The clear bit for SPI slave CMD7 interrupt. + 4 + 1 + write-only + + + SPI_SLV_CMD8_INT_CLR + The clear bit for SPI slave CMD8 interrupt. + 5 + 1 + write-only + + + SPI_SLV_CMD9_INT_CLR + The clear bit for SPI slave CMD9 interrupt. + 6 + 1 + write-only + + + SPI_SLV_CMDA_INT_CLR + The clear bit for SPI slave CMDA interrupt. + 7 + 1 + write-only + + + SPI_SLV_RD_DMA_DONE_INT_CLR + The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + 8 + 1 + write-only + + + SPI_SLV_WR_DMA_DONE_INT_CLR + The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + 9 + 1 + write-only + + + SPI_SLV_RD_BUF_DONE_INT_CLR + The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + 10 + 1 + write-only + + + SPI_SLV_WR_BUF_DONE_INT_CLR + The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + 11 + 1 + write-only + + + SPI_TRANS_DONE_INT_CLR + The clear bit for SPI_TRANS_DONE_INT interrupt. + 12 + 1 + write-only + + + SPI_DMA_SEG_TRANS_DONE_INT_CLR + The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + 13 + 1 + write-only + + + SPI_SEG_MAGIC_ERR_INT_CLR + The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt. + 14 + 1 + write-only + + + SPI_SLV_BUF_ADDR_ERR_INT_CLR + The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + 15 + 1 + write-only + + + SPI_SLV_CMD_ERR_INT_CLR + The clear bit for SPI_SLV_CMD_ERR_INT interrupt. + 16 + 1 + write-only + + + SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR + The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + 17 + 1 + write-only + + + SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR + The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + 18 + 1 + write-only + + + SPI_APP2_INT_CLR + The clear bit for SPI_APP2_INT interrupt. + 19 + 1 + write-only + + + SPI_APP1_INT_CLR + The clear bit for SPI_APP1_INT interrupt. + 20 + 1 + write-only + + + + + SPI_DMA_INT_RAW + SPI interrupt raw register + 0x3C + 0x20 + + + SPI_DMA_INFIFO_FULL_ERR_INT_RAW + 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others. + 0 + 1 + read-write + + + SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW + 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode. 0: Others. + 1 + 1 + read-write + + + SPI_SLV_EX_QPI_INT_RAW + The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others. + 2 + 1 + read-write + + + SPI_SLV_EN_QPI_INT_RAW + The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others. + 3 + 1 + read-write + + + SPI_SLV_CMD7_INT_RAW + The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others. + 4 + 1 + read-write + + + SPI_SLV_CMD8_INT_RAW + The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others. + 5 + 1 + read-write + + + SPI_SLV_CMD9_INT_RAW + The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others. + 6 + 1 + read-write + + + SPI_SLV_CMDA_INT_RAW + The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others. + 7 + 1 + read-write + + + SPI_SLV_RD_DMA_DONE_INT_RAW + The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others. + 8 + 1 + read-write + + + SPI_SLV_WR_DMA_DONE_INT_RAW + The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others. + 9 + 1 + read-write + + + SPI_SLV_RD_BUF_DONE_INT_RAW + The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others. + 10 + 1 + read-write + + + SPI_SLV_WR_BUF_DONE_INT_RAW + The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others. + 11 + 1 + read-write + + + SPI_TRANS_DONE_INT_RAW + The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others. + 12 + 1 + read-write + + + SPI_DMA_SEG_TRANS_DONE_INT_RAW + The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is not ended or not occurred. + 13 + 1 + read-write + + + SPI_SEG_MAGIC_ERR_INT_RAW + The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others. + 14 + 1 + read-write + + + SPI_SLV_BUF_ADDR_ERR_INT_RAW + The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others. + 15 + 1 + read-write + + + SPI_SLV_CMD_ERR_INT_RAW + The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others. + 16 + 1 + read-write + + + SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW + The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others. + 17 + 1 + read-write + + + SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW + The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others. + 18 + 1 + read-write + + + SPI_APP2_INT_RAW + The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software. + 19 + 1 + read-write + + + SPI_APP1_INT_RAW + The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software. + 20 + 1 + read-write + + + + + SPI_DMA_INT_ST + SPI interrupt status register + 0x40 + 0x20 + + + SPI_DMA_INFIFO_FULL_ERR_INT_ST + The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + 0 + 1 + read-only + + + SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST + The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + 1 + 1 + read-only + + + SPI_SLV_EX_QPI_INT_ST + The status bit for SPI slave Ex_QPI interrupt. + 2 + 1 + read-only + + + SPI_SLV_EN_QPI_INT_ST + The status bit for SPI slave En_QPI interrupt. + 3 + 1 + read-only + + + SPI_SLV_CMD7_INT_ST + The status bit for SPI slave CMD7 interrupt. + 4 + 1 + read-only + + + SPI_SLV_CMD8_INT_ST + The status bit for SPI slave CMD8 interrupt. + 5 + 1 + read-only + + + SPI_SLV_CMD9_INT_ST + The status bit for SPI slave CMD9 interrupt. + 6 + 1 + read-only + + + SPI_SLV_CMDA_INT_ST + The status bit for SPI slave CMDA interrupt. + 7 + 1 + read-only + + + SPI_SLV_RD_DMA_DONE_INT_ST + The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + 8 + 1 + read-only + + + SPI_SLV_WR_DMA_DONE_INT_ST + The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + 9 + 1 + read-only + + + SPI_SLV_RD_BUF_DONE_INT_ST + The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + 10 + 1 + read-only + + + SPI_SLV_WR_BUF_DONE_INT_ST + The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + 11 + 1 + read-only + + + SPI_TRANS_DONE_INT_ST + The status bit for SPI_TRANS_DONE_INT interrupt. + 12 + 1 + read-only + + + SPI_DMA_SEG_TRANS_DONE_INT_ST + The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + 13 + 1 + read-only + + + SPI_SEG_MAGIC_ERR_INT_ST + The status bit for SPI_SEG_MAGIC_ERR_INT interrupt. + 14 + 1 + read-only + + + SPI_SLV_BUF_ADDR_ERR_INT_ST + The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + 15 + 1 + read-only + + + SPI_SLV_CMD_ERR_INT_ST + The status bit for SPI_SLV_CMD_ERR_INT interrupt. + 16 + 1 + read-only + + + SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST + The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + 17 + 1 + read-only + + + SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST + The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + 18 + 1 + read-only + + + SPI_APP2_INT_ST + The status bit for SPI_APP2_INT interrupt. + 19 + 1 + read-only + + + SPI_APP1_INT_ST + The status bit for SPI_APP1_INT interrupt. + 20 + 1 + read-only + + + + + SPI_DMA_INT_SET + SPI interrupt software set register + 0x44 + 0x20 + + + SPI_DMA_INFIFO_FULL_ERR_INT_SET + The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + 0 + 1 + write-only + + + SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET + The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + 1 + 1 + write-only + + + SPI_SLV_EX_QPI_INT_SET + The software set bit for SPI slave Ex_QPI interrupt. + 2 + 1 + write-only + + + SPI_SLV_EN_QPI_INT_SET + The software set bit for SPI slave En_QPI interrupt. + 3 + 1 + write-only + + + SPI_SLV_CMD7_INT_SET + The software set bit for SPI slave CMD7 interrupt. + 4 + 1 + write-only + + + SPI_SLV_CMD8_INT_SET + The software set bit for SPI slave CMD8 interrupt. + 5 + 1 + write-only + + + SPI_SLV_CMD9_INT_SET + The software set bit for SPI slave CMD9 interrupt. + 6 + 1 + write-only + + + SPI_SLV_CMDA_INT_SET + The software set bit for SPI slave CMDA interrupt. + 7 + 1 + write-only + + + SPI_SLV_RD_DMA_DONE_INT_SET + The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + 8 + 1 + write-only + + + SPI_SLV_WR_DMA_DONE_INT_SET + The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + 9 + 1 + write-only + + + SPI_SLV_RD_BUF_DONE_INT_SET + The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + 10 + 1 + write-only + + + SPI_SLV_WR_BUF_DONE_INT_SET + The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + 11 + 1 + write-only + + + SPI_TRANS_DONE_INT_SET + The software set bit for SPI_TRANS_DONE_INT interrupt. + 12 + 1 + write-only + + + SPI_DMA_SEG_TRANS_DONE_INT_SET + The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + 13 + 1 + write-only + + + SPI_SEG_MAGIC_ERR_INT_SET + The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt. + 14 + 1 + write-only + + + SPI_SLV_BUF_ADDR_ERR_INT_SET + The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + 15 + 1 + write-only + + + SPI_SLV_CMD_ERR_INT_SET + The software set bit for SPI_SLV_CMD_ERR_INT interrupt. + 16 + 1 + write-only + + + SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET + The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + 17 + 1 + write-only + + + SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET + The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + 18 + 1 + write-only + + + SPI_APP2_INT_SET + The software set bit for SPI_APP2_INT interrupt. + 19 + 1 + write-only + + + SPI_APP1_INT_SET + The software set bit for SPI_APP1_INT interrupt. + 20 + 1 + write-only + + + + + SPI_W0 + SPI CPU-controlled buffer0 + 0x98 + 0x20 + + + SPI_BUF0 + data buffer + 0 + 32 + read-write + + + + + SPI_W1 + SPI CPU-controlled buffer1 + 0x9C + 0x20 + + + SPI_BUF1 + data buffer + 0 + 32 + read-write + + + + + SPI_W2 + SPI CPU-controlled buffer2 + 0xA0 + 0x20 + + + SPI_BUF2 + data buffer + 0 + 32 + read-write + + + + + SPI_W3 + SPI CPU-controlled buffer3 + 0xA4 + 0x20 + + + SPI_BUF3 + data buffer + 0 + 32 + read-write + + + + + SPI_W4 + SPI CPU-controlled buffer4 + 0xA8 + 0x20 + + + SPI_BUF4 + data buffer + 0 + 32 + read-write + + + + + SPI_W5 + SPI CPU-controlled buffer5 + 0xAC + 0x20 + + + SPI_BUF5 + data buffer + 0 + 32 + read-write + + + + + SPI_W6 + SPI CPU-controlled buffer6 + 0xB0 + 0x20 + + + SPI_BUF6 + data buffer + 0 + 32 + read-write + + + + + SPI_W7 + SPI CPU-controlled buffer7 + 0xB4 + 0x20 + + + SPI_BUF7 + data buffer + 0 + 32 + read-write + + + + + SPI_W8 + SPI CPU-controlled buffer8 + 0xB8 + 0x20 + + + SPI_BUF8 + data buffer + 0 + 32 + read-write + + + + + SPI_W9 + SPI CPU-controlled buffer9 + 0xBC + 0x20 + + + SPI_BUF9 + data buffer + 0 + 32 + read-write + + + + + SPI_W10 + SPI CPU-controlled buffer10 + 0xC0 + 0x20 + + + SPI_BUF10 + data buffer + 0 + 32 + read-write + + + + + SPI_W11 + SPI CPU-controlled buffer11 + 0xC4 + 0x20 + + + SPI_BUF11 + data buffer + 0 + 32 + read-write + + + + + SPI_W12 + SPI CPU-controlled buffer12 + 0xC8 + 0x20 + + + SPI_BUF12 + data buffer + 0 + 32 + read-write + + + + + SPI_W13 + SPI CPU-controlled buffer13 + 0xCC + 0x20 + + + SPI_BUF13 + data buffer + 0 + 32 + read-write + + + + + SPI_W14 + SPI CPU-controlled buffer14 + 0xD0 + 0x20 + + + SPI_BUF14 + data buffer + 0 + 32 + read-write + + + + + SPI_W15 + SPI CPU-controlled buffer15 + 0xD4 + 0x20 + + + SPI_BUF15 + data buffer + 0 + 32 + read-write + + + + + SPI_SLAVE + SPI slave control register + 0xE0 + 0x20 + 0x02800000 + + + SPI_CLK_MODE + SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state. + 0 + 2 + read-write + + + SPI_CLK_MODE_13 + {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6]. + 2 + 1 + read-write + + + SPI_RSCK_DATA_OUT + It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge + 3 + 1 + read-write + + + SPI_SLV_RDDMA_BITLEN_EN + 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others + 8 + 1 + read-write + + + SPI_SLV_WRDMA_BITLEN_EN + 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others + 9 + 1 + read-write + + + SPI_SLV_RDBUF_BITLEN_EN + 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others + 10 + 1 + read-write + + + SPI_SLV_WRBUF_BITLEN_EN + 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others + 11 + 1 + read-write + + + SPI_SLV_LAST_BYTE_STRB + Represents the effective bit of the last received data byte in SPI slave FD and HD mode. + 12 + 8 + read-only + + + SPI_DMA_SEG_MAGIC_VALUE + The magic value of BM table in master DMA seg-trans. + 22 + 4 + read-write + + + MODE + Set SPI work mode. 1: slave mode 0: master mode. + 26 + 1 + read-write + + + SPI_SOFT_RESET + Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state. + 27 + 1 + write-only + + + SPI_USR_CONF + 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode. + 28 + 1 + read-write + + + SPI_MST_FD_WAIT_DMA_TX_DATA + In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI transfer. + 29 + 1 + read-write + + + + + SPI_SLAVE1 + SPI slave control register 1 + 0xE4 + 0x20 + + + SPI_SLV_DATA_BITLEN + The transferred data bit length in SPI slave FD and HD mode. + 0 + 18 + read-write + + + SPI_SLV_LAST_COMMAND + In the slave mode it is the value of command. + 18 + 8 + read-write + + + SPI_SLV_LAST_ADDR + In the slave mode it is the value of address. + 26 + 6 + read-write + + + + + SPI_CLK_GATE + SPI module clock and register clock control + 0xE8 + 0x20 + + + SPI_CLK_EN + Set this bit to enable clk gate + 0 + 1 + read-write + + + SPI_MST_CLK_ACTIVE + Set this bit to power on the SPI module clock. + 1 + 1 + read-write + + + SPI_MST_CLK_SEL + This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK. + 2 + 1 + read-write + + + + + SPI_DATE + Version control + 0xF0 + 0x20 + 0x02207202 + + + SPI_DATE + SPI register version. + 0 + 28 + read-write + + + + + + + SPI3 + SPI (Serial Peripheral Interface) Controller 3 + SPI3 + 0x500D1000 + + 0x0 + 0x98 + registers + + + SPI3 + 26 + + + + SPI_CMD + Command control register + 0x0 + 0x20 + + + SPI_UPDATE + Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode. + 23 + 1 + write-only + + + SPI_USR + User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf. + 24 + 1 + read-write + + + + + SPI_ADDR + Address value register + 0x4 + 0x20 + + + SPI_USR_ADDR_VALUE + Address to slave. Can be configured in CONF state. + 0 + 32 + read-write + + + + + SPI_CTRL + SPI control register + 0x8 + 0x20 + 0x003C0000 + + + SPI_DUMMY_OUT + 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state. + 3 + 1 + read-write + + + SPI_FADDR_DUAL + Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state. + 5 + 1 + read-write + + + SPI_FADDR_QUAD + Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state. + 6 + 1 + read-write + + + SPI_FCMD_DUAL + Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state. + 8 + 1 + read-write + + + SPI_FCMD_QUAD + Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state. + 9 + 1 + read-write + + + SPI_FREAD_DUAL + In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state. + 14 + 1 + read-write + + + SPI_FREAD_QUAD + In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state. + 15 + 1 + read-write + + + SPI_Q_POL + The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state. + 18 + 1 + read-write + + + SPI_D_POL + The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state. + 19 + 1 + read-write + + + SPI_HOLD_POL + SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state. + 20 + 1 + read-write + + + SPI_WP_POL + Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state. + 21 + 1 + read-write + + + SPI_RD_BIT_ORDER + In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state. + 23 + 2 + read-write + + + SPI_WR_BIT_ORDER + In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state. + 25 + 2 + read-write + + + + + SPI_CLOCK + SPI clock control register + 0xC + 0x20 + 0x80003043 + + + SPI_CLKCNT_L + In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state. + 0 + 6 + read-write + + + SPI_CLKCNT_H + In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state. + 6 + 6 + read-write + + + SPI_CLKCNT_N + In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state. + 12 + 6 + read-write + + + SPI_CLKDIV_PRE + In the master mode it is pre-divider of spi_clk. Can be configured in CONF state. + 18 + 4 + read-write + + + SPI_CLK_EQU_SYSCLK + In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state. + 31 + 1 + read-write + + + + + SPI_USER + SPI USER control register + 0x10 + 0x20 + 0x800000C0 + + + SPI_DOUTDIN + Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state. + 0 + 1 + read-write + + + SPI_QPI_MODE + Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state. + 3 + 1 + read-write + + + SPI_TSCK_I_EDGE + In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i. + 5 + 1 + read-write + + + SPI_CS_HOLD + spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state. + 6 + 1 + read-write + + + SPI_CS_SETUP + spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state. + 7 + 1 + read-write + + + SPI_RSCK_I_EDGE + In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i. + 8 + 1 + read-write + + + SPI_CK_OUT_EDGE + the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state. + 9 + 1 + read-write + + + SPI_FWRITE_DUAL + In the write operations read-data phase apply 2 signals. Can be configured in CONF state. + 12 + 1 + read-write + + + SPI_FWRITE_QUAD + In the write operations read-data phase apply 4 signals. Can be configured in CONF state. + 13 + 1 + read-write + + + SPI_SIO + Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state. + 17 + 1 + read-write + + + SPI_USR_MISO_HIGHPART + read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state. + 24 + 1 + read-write + + + SPI_USR_MOSI_HIGHPART + write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state. + 25 + 1 + read-write + + + SPI_USR_DUMMY_IDLE + spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state. + 26 + 1 + read-write + + + SPI_USR_MOSI + This bit enable the write-data phase of an operation. Can be configured in CONF state. + 27 + 1 + read-write + + + SPI_USR_MISO + This bit enable the read-data phase of an operation. Can be configured in CONF state. + 28 + 1 + read-write + + + SPI_USR_DUMMY + This bit enable the dummy phase of an operation. Can be configured in CONF state. + 29 + 1 + read-write + + + SPI_USR_ADDR + This bit enable the address phase of an operation. Can be configured in CONF state. + 30 + 1 + read-write + + + SPI_USR_COMMAND + This bit enable the command phase of an operation. Can be configured in CONF state. + 31 + 1 + read-write + + + + + SPI_USER1 + SPI USER control register 1 + 0x14 + 0x20 + 0xB8410007 + + + SPI_USR_DUMMY_CYCLELEN + The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state. + 0 + 8 + read-write + + + SPI_MST_WFULL_ERR_END_EN + 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. + 16 + 1 + read-write + + + SPI_CS_SETUP_TIME + (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state. + 17 + 5 + read-write + + + SPI_CS_HOLD_TIME + delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state. + 22 + 5 + read-write + + + SPI_USR_ADDR_BITLEN + The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state. + 27 + 5 + read-write + + + + + SPI_USER2 + SPI USER control register 2 + 0x18 + 0x20 + 0x78000000 + + + SPI_USR_COMMAND_VALUE + The value of command. Can be configured in CONF state. + 0 + 16 + read-write + + + SPI_MST_REMPTY_ERR_END_EN + 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. + 27 + 1 + read-write + + + SPI_USR_COMMAND_BITLEN + The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state. + 28 + 4 + read-write + + + + + SPI_MS_DLEN + SPI data bit length control register + 0x1C + 0x20 + + + SPI_MS_DATA_BITLEN + The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state. + 0 + 18 + read-write + + + + + SPI_MISC + SPI misc register + 0x20 + 0x20 + 0x00000006 + + + SPI_CS0_DIS + SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state. + 0 + 1 + read-write + + + SPI_CS1_DIS + SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state. + 1 + 1 + read-write + + + SPI_CS2_DIS + SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state. + 2 + 1 + read-write + + + SPI_CK_DIS + 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state. + 6 + 1 + read-write + + + SPI_MASTER_CS_POL + In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state. + 7 + 3 + read-write + + + SPI_SLAVE_CS_POL + spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state. + 23 + 1 + read-write + + + SPI_CK_IDLE_EDGE + 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state. + 29 + 1 + read-write + + + SPI_CS_KEEP_ACTIVE + spi cs line keep low when the bit is set. Can be configured in CONF state. + 30 + 1 + read-write + + + SPI_QUAD_DIN_PIN_SWAP + 1: spi quad input swap enable 0: spi quad input swap disable. Can be configured in CONF state. + 31 + 1 + read-write + + + + + SPI_DIN_MODE + SPI input delay mode configuration + 0x24 + 0x20 + + + SPI_DIN0_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 0 + 2 + read-write + + + SPI_DIN1_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 2 + 2 + read-write + + + SPI_DIN2_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 4 + 2 + read-write + + + SPI_DIN3_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 6 + 2 + read-write + + + SPI_TIMING_HCLK_ACTIVE + 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state. + 16 + 1 + read-write + + + + + SPI_DIN_NUM + SPI input delay number configuration + 0x28 + 0x20 + + + SPI_DIN0_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 0 + 2 + read-write + + + SPI_DIN1_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 2 + 2 + read-write + + + SPI_DIN2_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 4 + 2 + read-write + + + SPI_DIN3_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 6 + 2 + read-write + + + + + SPI_DOUT_MODE + SPI output delay mode configuration + 0x2C + 0x20 + + + SPI_DOUT0_MODE + The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 0 + 1 + read-write + + + SPI_DOUT1_MODE + The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 1 + 1 + read-write + + + SPI_DOUT2_MODE + The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 2 + 1 + read-write + + + SPI_DOUT3_MODE + The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 3 + 1 + read-write + + + + + SPI_DMA_CONF + SPI DMA control register + 0x30 + 0x20 + 0x00000003 + + + SPI_DMA_OUTFIFO_EMPTY + Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: DMA TX FIFO is ready for sending data. + 0 + 1 + read-only + + + SPI_DMA_INFIFO_FULL + Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. 0: DMA RX FIFO is ready for receiving data. + 1 + 1 + read-only + + + SPI_DMA_SLV_SEG_TRANS_EN + Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable. + 18 + 1 + read-write + + + SPI_SLV_RX_SEG_TRANS_CLR_EN + 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done. + 19 + 1 + read-write + + + SPI_SLV_TX_SEG_TRANS_CLR_EN + 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done. + 20 + 1 + read-write + + + SPI_RX_EOF_EN + 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans. + 21 + 1 + read-write + + + SPI_DMA_RX_ENA + Set this bit to enable SPI DMA controlled receive data mode. + 27 + 1 + read-write + + + SPI_DMA_TX_ENA + Set this bit to enable SPI DMA controlled send data mode. + 28 + 1 + read-write + + + SPI_RX_AFIFO_RST + Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer. + 29 + 1 + write-only + + + SPI_BUF_AFIFO_RST + Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer. + 30 + 1 + write-only + + + SPI_DMA_AFIFO_RST + Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer. + 31 + 1 + write-only + + + + + SPI_DMA_INT_ENA + SPI interrupt enable register + 0x34 + 0x20 + + + SPI_DMA_INFIFO_FULL_ERR_INT_ENA + The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + 0 + 1 + read-write + + + SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA + The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + 1 + 1 + read-write + + + SPI_SLV_EX_QPI_INT_ENA + The enable bit for SPI slave Ex_QPI interrupt. + 2 + 1 + read-write + + + SPI_SLV_EN_QPI_INT_ENA + The enable bit for SPI slave En_QPI interrupt. + 3 + 1 + read-write + + + SPI_SLV_CMD7_INT_ENA + The enable bit for SPI slave CMD7 interrupt. + 4 + 1 + read-write + + + SPI_SLV_CMD8_INT_ENA + The enable bit for SPI slave CMD8 interrupt. + 5 + 1 + read-write + + + SPI_SLV_CMD9_INT_ENA + The enable bit for SPI slave CMD9 interrupt. + 6 + 1 + read-write + + + SPI_SLV_CMDA_INT_ENA + The enable bit for SPI slave CMDA interrupt. + 7 + 1 + read-write + + + SPI_SLV_RD_DMA_DONE_INT_ENA + The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + 8 + 1 + read-write + + + SPI_SLV_WR_DMA_DONE_INT_ENA + The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + 9 + 1 + read-write + + + SPI_SLV_RD_BUF_DONE_INT_ENA + The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + 10 + 1 + read-write + + + SPI_SLV_WR_BUF_DONE_INT_ENA + The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + 11 + 1 + read-write + + + SPI_TRANS_DONE_INT_ENA + The enable bit for SPI_TRANS_DONE_INT interrupt. + 12 + 1 + read-write + + + SPI_DMA_SEG_TRANS_DONE_INT_ENA + The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + 13 + 1 + read-write + + + SPI_SLV_BUF_ADDR_ERR_INT_ENA + The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + 15 + 1 + read-write + + + SPI_SLV_CMD_ERR_INT_ENA + The enable bit for SPI_SLV_CMD_ERR_INT interrupt. + 16 + 1 + read-write + + + SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA + The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + 17 + 1 + read-write + + + SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA + The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + 18 + 1 + read-write + + + SPI_APP2_INT_ENA + The enable bit for SPI_APP2_INT interrupt. + 19 + 1 + read-write + + + SPI_APP1_INT_ENA + The enable bit for SPI_APP1_INT interrupt. + 20 + 1 + read-write + + + + + SPI_DMA_INT_CLR + SPI interrupt clear register + 0x38 + 0x20 + + + SPI_DMA_INFIFO_FULL_ERR_INT_CLR + The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + 0 + 1 + write-only + + + SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR + The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + 1 + 1 + write-only + + + SPI_SLV_EX_QPI_INT_CLR + The clear bit for SPI slave Ex_QPI interrupt. + 2 + 1 + write-only + + + SPI_SLV_EN_QPI_INT_CLR + The clear bit for SPI slave En_QPI interrupt. + 3 + 1 + write-only + + + SPI_SLV_CMD7_INT_CLR + The clear bit for SPI slave CMD7 interrupt. + 4 + 1 + write-only + + + SPI_SLV_CMD8_INT_CLR + The clear bit for SPI slave CMD8 interrupt. + 5 + 1 + write-only + + + SPI_SLV_CMD9_INT_CLR + The clear bit for SPI slave CMD9 interrupt. + 6 + 1 + write-only + + + SPI_SLV_CMDA_INT_CLR + The clear bit for SPI slave CMDA interrupt. + 7 + 1 + write-only + + + SPI_SLV_RD_DMA_DONE_INT_CLR + The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + 8 + 1 + write-only + + + SPI_SLV_WR_DMA_DONE_INT_CLR + The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + 9 + 1 + write-only + + + SPI_SLV_RD_BUF_DONE_INT_CLR + The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + 10 + 1 + write-only + + + SPI_SLV_WR_BUF_DONE_INT_CLR + The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + 11 + 1 + write-only + + + SPI_TRANS_DONE_INT_CLR + The clear bit for SPI_TRANS_DONE_INT interrupt. + 12 + 1 + write-only + + + SPI_DMA_SEG_TRANS_DONE_INT_CLR + The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + 13 + 1 + write-only + + + SPI_SLV_BUF_ADDR_ERR_INT_CLR + The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + 15 + 1 + write-only + + + SPI_SLV_CMD_ERR_INT_CLR + The clear bit for SPI_SLV_CMD_ERR_INT interrupt. + 16 + 1 + write-only + + + SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR + The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + 17 + 1 + write-only + + + SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR + The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + 18 + 1 + write-only + + + SPI_APP2_INT_CLR + The clear bit for SPI_APP2_INT interrupt. + 19 + 1 + write-only + + + SPI_APP1_INT_CLR + The clear bit for SPI_APP1_INT interrupt. + 20 + 1 + write-only + + + + + SPI_DMA_INT_RAW + SPI interrupt raw register + 0x3C + 0x20 + + + SPI_DMA_INFIFO_FULL_ERR_INT_RAW + 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others. + 0 + 1 + read-write + + + SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW + 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode. 0: Others. + 1 + 1 + read-write + + + SPI_SLV_EX_QPI_INT_RAW + The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others. + 2 + 1 + read-write + + + SPI_SLV_EN_QPI_INT_RAW + The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others. + 3 + 1 + read-write + + + SPI_SLV_CMD7_INT_RAW + The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others. + 4 + 1 + read-write + + + SPI_SLV_CMD8_INT_RAW + The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others. + 5 + 1 + read-write + + + SPI_SLV_CMD9_INT_RAW + The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others. + 6 + 1 + read-write + + + SPI_SLV_CMDA_INT_RAW + The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others. + 7 + 1 + read-write + + + SPI_SLV_RD_DMA_DONE_INT_RAW + The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others. + 8 + 1 + read-write + + + SPI_SLV_WR_DMA_DONE_INT_RAW + The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others. + 9 + 1 + read-write + + + SPI_SLV_RD_BUF_DONE_INT_RAW + The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others. + 10 + 1 + read-write + + + SPI_SLV_WR_BUF_DONE_INT_RAW + The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others. + 11 + 1 + read-write + + + SPI_TRANS_DONE_INT_RAW + The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others. + 12 + 1 + read-write + + + SPI_DMA_SEG_TRANS_DONE_INT_RAW + The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is not ended or not occurred. + 13 + 1 + read-write + + + SPI_SLV_BUF_ADDR_ERR_INT_RAW + The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others. + 15 + 1 + read-write + + + SPI_SLV_CMD_ERR_INT_RAW + The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others. + 16 + 1 + read-write + + + SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW + The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others. + 17 + 1 + read-write + + + SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW + The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others. + 18 + 1 + read-write + + + SPI_APP2_INT_RAW + The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software. + 19 + 1 + read-write + + + SPI_APP1_INT_RAW + The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software. + 20 + 1 + read-write + + + + + SPI_DMA_INT_ST + SPI interrupt status register + 0x40 + 0x20 + + + SPI_DMA_INFIFO_FULL_ERR_INT_ST + The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + 0 + 1 + read-only + + + SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST + The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + 1 + 1 + read-only + + + SPI_SLV_EX_QPI_INT_ST + The status bit for SPI slave Ex_QPI interrupt. + 2 + 1 + read-only + + + SPI_SLV_EN_QPI_INT_ST + The status bit for SPI slave En_QPI interrupt. + 3 + 1 + read-only + + + SPI_SLV_CMD7_INT_ST + The status bit for SPI slave CMD7 interrupt. + 4 + 1 + read-only + + + SPI_SLV_CMD8_INT_ST + The status bit for SPI slave CMD8 interrupt. + 5 + 1 + read-only + + + SPI_SLV_CMD9_INT_ST + The status bit for SPI slave CMD9 interrupt. + 6 + 1 + read-only + + + SPI_SLV_CMDA_INT_ST + The status bit for SPI slave CMDA interrupt. + 7 + 1 + read-only + + + SPI_SLV_RD_DMA_DONE_INT_ST + The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + 8 + 1 + read-only + + + SPI_SLV_WR_DMA_DONE_INT_ST + The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + 9 + 1 + read-only + + + SPI_SLV_RD_BUF_DONE_INT_ST + The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + 10 + 1 + read-only + + + SPI_SLV_WR_BUF_DONE_INT_ST + The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + 11 + 1 + read-only + + + SPI_TRANS_DONE_INT_ST + The status bit for SPI_TRANS_DONE_INT interrupt. + 12 + 1 + read-only + + + SPI_DMA_SEG_TRANS_DONE_INT_ST + The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + 13 + 1 + read-only + + + SPI_SLV_BUF_ADDR_ERR_INT_ST + The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + 15 + 1 + read-only + + + SPI_SLV_CMD_ERR_INT_ST + The status bit for SPI_SLV_CMD_ERR_INT interrupt. + 16 + 1 + read-only + + + SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST + The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + 17 + 1 + read-only + + + SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST + The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + 18 + 1 + read-only + + + SPI_APP2_INT_ST + The status bit for SPI_APP2_INT interrupt. + 19 + 1 + read-only + + + SPI_APP1_INT_ST + The status bit for SPI_APP1_INT interrupt. + 20 + 1 + read-only + + + + + SPI_DMA_INT_SET + SPI interrupt software set register + 0x44 + 0x20 + + + SPI_DMA_INFIFO_FULL_ERR_INT_SET + The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + 0 + 1 + write-only + + + SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET + The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + 1 + 1 + write-only + + + SPI_SLV_EX_QPI_INT_SET + The software set bit for SPI slave Ex_QPI interrupt. + 2 + 1 + write-only + + + SPI_SLV_EN_QPI_INT_SET + The software set bit for SPI slave En_QPI interrupt. + 3 + 1 + write-only + + + SPI_SLV_CMD7_INT_SET + The software set bit for SPI slave CMD7 interrupt. + 4 + 1 + write-only + + + SPI_SLV_CMD8_INT_SET + The software set bit for SPI slave CMD8 interrupt. + 5 + 1 + write-only + + + SPI_SLV_CMD9_INT_SET + The software set bit for SPI slave CMD9 interrupt. + 6 + 1 + write-only + + + SPI_SLV_CMDA_INT_SET + The software set bit for SPI slave CMDA interrupt. + 7 + 1 + write-only + + + SPI_SLV_RD_DMA_DONE_INT_SET + The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + 8 + 1 + write-only + + + SPI_SLV_WR_DMA_DONE_INT_SET + The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + 9 + 1 + write-only + + + SPI_SLV_RD_BUF_DONE_INT_SET + The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + 10 + 1 + write-only + + + SPI_SLV_WR_BUF_DONE_INT_SET + The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + 11 + 1 + write-only + + + SPI_TRANS_DONE_INT_SET + The software set bit for SPI_TRANS_DONE_INT interrupt. + 12 + 1 + write-only + + + SPI_DMA_SEG_TRANS_DONE_INT_SET + The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + 13 + 1 + write-only + + + SPI_SLV_BUF_ADDR_ERR_INT_SET + The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + 15 + 1 + write-only + + + SPI_SLV_CMD_ERR_INT_SET + The software set bit for SPI_SLV_CMD_ERR_INT interrupt. + 16 + 1 + write-only + + + SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET + The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + 17 + 1 + write-only + + + SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET + The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + 18 + 1 + write-only + + + SPI_APP2_INT_SET + The software set bit for SPI_APP2_INT interrupt. + 19 + 1 + write-only + + + SPI_APP1_INT_SET + The software set bit for SPI_APP1_INT interrupt. + 20 + 1 + write-only + + + + + SPI_W0 + SPI CPU-controlled buffer0 + 0x98 + 0x20 + + + SPI_BUF0 + data buffer + 0 + 32 + read-write + + + + + SPI_W1 + SPI CPU-controlled buffer1 + 0x9C + 0x20 + + + SPI_BUF1 + data buffer + 0 + 32 + read-write + + + + + SPI_W2 + SPI CPU-controlled buffer2 + 0xA0 + 0x20 + + + SPI_BUF2 + data buffer + 0 + 32 + read-write + + + + + SPI_W3 + SPI CPU-controlled buffer3 + 0xA4 + 0x20 + + + SPI_BUF3 + data buffer + 0 + 32 + read-write + + + + + SPI_W4 + SPI CPU-controlled buffer4 + 0xA8 + 0x20 + + + SPI_BUF4 + data buffer + 0 + 32 + read-write + + + + + SPI_W5 + SPI CPU-controlled buffer5 + 0xAC + 0x20 + + + SPI_BUF5 + data buffer + 0 + 32 + read-write + + + + + SPI_W6 + SPI CPU-controlled buffer6 + 0xB0 + 0x20 + + + SPI_BUF6 + data buffer + 0 + 32 + read-write + + + + + SPI_W7 + SPI CPU-controlled buffer7 + 0xB4 + 0x20 + + + SPI_BUF7 + data buffer + 0 + 32 + read-write + + + + + SPI_W8 + SPI CPU-controlled buffer8 + 0xB8 + 0x20 + + + SPI_BUF8 + data buffer + 0 + 32 + read-write + + + + + SPI_W9 + SPI CPU-controlled buffer9 + 0xBC + 0x20 + + + SPI_BUF9 + data buffer + 0 + 32 + read-write + + + + + SPI_W10 + SPI CPU-controlled buffer10 + 0xC0 + 0x20 + + + SPI_BUF10 + data buffer + 0 + 32 + read-write + + + + + SPI_W11 + SPI CPU-controlled buffer11 + 0xC4 + 0x20 + + + SPI_BUF11 + data buffer + 0 + 32 + read-write + + + + + SPI_W12 + SPI CPU-controlled buffer12 + 0xC8 + 0x20 + + + SPI_BUF12 + data buffer + 0 + 32 + read-write + + + + + SPI_W13 + SPI CPU-controlled buffer13 + 0xCC + 0x20 + + + SPI_BUF13 + data buffer + 0 + 32 + read-write + + + + + SPI_W14 + SPI CPU-controlled buffer14 + 0xD0 + 0x20 + + + SPI_BUF14 + data buffer + 0 + 32 + read-write + + + + + SPI_W15 + SPI CPU-controlled buffer15 + 0xD4 + 0x20 + + + SPI_BUF15 + data buffer + 0 + 32 + read-write + + + + + SPI_SLAVE + SPI slave control register + 0xE0 + 0x20 + + + SPI_CLK_MODE + SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state. + 0 + 2 + read-write + + + SPI_CLK_MODE_13 + {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6]. + 2 + 1 + read-write + + + SPI_RSCK_DATA_OUT + It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge + 3 + 1 + read-write + + + SPI_SLV_RDDMA_BITLEN_EN + 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others + 8 + 1 + read-write + + + SPI_SLV_WRDMA_BITLEN_EN + 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others + 9 + 1 + read-write + + + SPI_SLV_RDBUF_BITLEN_EN + 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others + 10 + 1 + read-write + + + SPI_SLV_WRBUF_BITLEN_EN + 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others + 11 + 1 + read-write + + + SPI_SLV_LAST_BYTE_STRB + Represents the effective bit of the last received data byte in SPI slave FD and HD mode. + 12 + 8 + read-only + + + MODE + Set SPI work mode. 1: slave mode 0: master mode. + 26 + 1 + read-write + + + SPI_SOFT_RESET + Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state. + 27 + 1 + write-only + + + SPI_MST_FD_WAIT_DMA_TX_DATA + In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI transfer. + 29 + 1 + read-write + + + + + SPI_SLAVE1 + SPI slave control register 1 + 0xE4 + 0x20 + + + SPI_SLV_DATA_BITLEN + The transferred data bit length in SPI slave FD and HD mode. + 0 + 18 + read-write + + + SPI_SLV_LAST_COMMAND + In the slave mode it is the value of command. + 18 + 8 + read-write + + + SPI_SLV_LAST_ADDR + In the slave mode it is the value of address. + 26 + 6 + read-write + + + + + SPI_CLK_GATE + SPI module clock and register clock control + 0xE8 + 0x20 + + + SPI_CLK_EN + Set this bit to enable clk gate + 0 + 1 + read-write + + + SPI_MST_CLK_ACTIVE + Set this bit to power on the SPI module clock. + 1 + 1 + read-write + + + SPI_MST_CLK_SEL + This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK. + 2 + 1 + read-write + + + + + SPI_DATE + Version control + 0xF0 + 0x20 + 0x02207202 + + + SPI_DATE + SPI register version. + 0 + 28 + read-write + + + + + + + SYSTIMER + System Timer + SYSTIMER + 0x500E2000 + + 0x0 + 0x90 + registers + + + SYSTIMER_TARGET0 + 53 + + + SYSTIMER_TARGET1 + 54 + + + SYSTIMER_TARGET2 + 55 + + + + CONF + Configure system timer clock + 0x0 + 0x20 + 0x46000000 + + + SYSTIMER_CLK_FO + systimer clock force on + 0 + 1 + read-write + + + ETM_EN + enable systimer's etm task and event + 1 + 1 + read-write + + + TARGET2_WORK_EN + target2 work enable + 22 + 1 + read-write + + + TARGET1_WORK_EN + target1 work enable + 23 + 1 + read-write + + + TARGET0_WORK_EN + target0 work enable + 24 + 1 + read-write + + + TIMER_UNIT1_CORE1_STALL_EN + If timer unit1 is stalled when core1 stalled + 25 + 1 + read-write + + + TIMER_UNIT1_CORE0_STALL_EN + If timer unit1 is stalled when core0 stalled + 26 + 1 + read-write + + + TIMER_UNIT0_CORE1_STALL_EN + If timer unit0 is stalled when core1 stalled + 27 + 1 + read-write + + + TIMER_UNIT0_CORE0_STALL_EN + If timer unit0 is stalled when core0 stalled + 28 + 1 + read-write + + + TIMER_UNIT1_WORK_EN + timer unit1 work enable + 29 + 1 + read-write + + + TIMER_UNIT0_WORK_EN + timer unit0 work enable + 30 + 1 + read-write + + + CLK_EN + register file clk gating + 31 + 1 + read-write + + + + + UNIT0_OP + system timer unit0 value update register + 0x4 + 0x20 + + + TIMER_UNIT0_VALUE_VALID + timer value is sync and valid + 29 + 1 + read-only + + + TIMER_UNIT0_UPDATE + update timer_unit0 + 30 + 1 + write-only + + + + + UNIT1_OP + system timer unit1 value update register + 0x8 + 0x20 + + + TIMER_UNIT1_VALUE_VALID + timer value is sync and valid + 29 + 1 + read-only + + + TIMER_UNIT1_UPDATE + update timer unit1 + 30 + 1 + write-only + + + + + UNIT0_LOAD_HI + system timer unit0 value high load register + 0xC + 0x20 + + + TIMER_UNIT0_LOAD_HI + timer unit0 load high 20 bits + 0 + 20 + read-write + + + + + UNIT0_LOAD_LO + system timer unit0 value low load register + 0x10 + 0x20 + + + TIMER_UNIT0_LOAD_LO + timer unit0 load low 32 bits + 0 + 32 + read-write + + + + + UNIT1_LOAD_HI + system timer unit1 value high load register + 0x14 + 0x20 + + + TIMER_UNIT1_LOAD_HI + timer unit1 load high 20 bits + 0 + 20 + read-write + + + + + UNIT1_LOAD_LO + system timer unit1 value low load register + 0x18 + 0x20 + + + TIMER_UNIT1_LOAD_LO + timer unit1 load low 32 bits + 0 + 32 + read-write + + + + + TARGET0_HI + system timer comp0 value high register + 0x1C + 0x20 + + + TIMER_TARGET0_HI + timer taget0 high 20 bits + 0 + 20 + read-write + + + + + TARGET0_LO + system timer comp0 value low register + 0x20 + 0x20 + + + TIMER_TARGET0_LO + timer taget0 low 32 bits + 0 + 32 + read-write + + + + + TARGET1_HI + system timer comp1 value high register + 0x24 + 0x20 + + + TIMER_TARGET1_HI + timer taget1 high 20 bits + 0 + 20 + read-write + + + + + TARGET1_LO + system timer comp1 value low register + 0x28 + 0x20 + + + TIMER_TARGET1_LO + timer taget1 low 32 bits + 0 + 32 + read-write + + + + + TARGET2_HI + system timer comp2 value high register + 0x2C + 0x20 + + + TIMER_TARGET2_HI + timer taget2 high 20 bits + 0 + 20 + read-write + + + + + TARGET2_LO + system timer comp2 value low register + 0x30 + 0x20 + + + TIMER_TARGET2_LO + timer taget2 low 32 bits + 0 + 32 + read-write + + + + + TARGET0_CONF + system timer comp0 target mode register + 0x34 + 0x20 + + + TARGET0_PERIOD + target0 period + 0 + 26 + read-write + + + TARGET0_PERIOD_MODE + Set target0 to period mode + 30 + 1 + read-write + + + TARGET0_TIMER_UNIT_SEL + select which unit to compare + 31 + 1 + read-write + + + + + TARGET1_CONF + system timer comp1 target mode register + 0x38 + 0x20 + + + TARGET1_PERIOD + target1 period + 0 + 26 + read-write + + + TARGET1_PERIOD_MODE + Set target1 to period mode + 30 + 1 + read-write + + + TARGET1_TIMER_UNIT_SEL + select which unit to compare + 31 + 1 + read-write + + + + + TARGET2_CONF + system timer comp2 target mode register + 0x3C + 0x20 + + + TARGET2_PERIOD + target2 period + 0 + 26 + read-write + + + TARGET2_PERIOD_MODE + Set target2 to period mode + 30 + 1 + read-write + + + TARGET2_TIMER_UNIT_SEL + select which unit to compare + 31 + 1 + read-write + + + + + UNIT0_VALUE_HI + system timer unit0 value high register + 0x40 + 0x20 + + + TIMER_UNIT0_VALUE_HI + timer read value high 20bits + 0 + 20 + read-only + + + + + UNIT0_VALUE_LO + system timer unit0 value low register + 0x44 + 0x20 + + + TIMER_UNIT0_VALUE_LO + timer read value low 32bits + 0 + 32 + read-only + + + + + UNIT1_VALUE_HI + system timer unit1 value high register + 0x48 + 0x20 + + + TIMER_UNIT1_VALUE_HI + timer read value high 20bits + 0 + 20 + read-only + + + + + UNIT1_VALUE_LO + system timer unit1 value low register + 0x4C + 0x20 + + + TIMER_UNIT1_VALUE_LO + timer read value low 32bits + 0 + 32 + read-only + + + + + COMP0_LOAD + system timer comp0 conf sync register + 0x50 + 0x20 + + + TIMER_COMP0_LOAD + timer comp0 sync enable signal + 0 + 1 + write-only + + + + + COMP1_LOAD + system timer comp1 conf sync register + 0x54 + 0x20 + + + TIMER_COMP1_LOAD + timer comp1 sync enable signal + 0 + 1 + write-only + + + + + COMP2_LOAD + system timer comp2 conf sync register + 0x58 + 0x20 + + + TIMER_COMP2_LOAD + timer comp2 sync enable signal + 0 + 1 + write-only + + + + + UNIT0_LOAD + system timer unit0 conf sync register + 0x5C + 0x20 + + + TIMER_UNIT0_LOAD + timer unit0 sync enable signal + 0 + 1 + write-only + + + + + UNIT1_LOAD + system timer unit1 conf sync register + 0x60 + 0x20 + + + TIMER_UNIT1_LOAD + timer unit1 sync enable signal + 0 + 1 + write-only + + + + + INT_ENA + systimer interrupt enable register + 0x64 + 0x20 + + + TARGET0_INT_ENA + interupt0 enable + 0 + 1 + read-write + + + TARGET1_INT_ENA + interupt1 enable + 1 + 1 + read-write + + + TARGET2_INT_ENA + interupt2 enable + 2 + 1 + read-write + + + + + INT_RAW + systimer interrupt raw register + 0x68 + 0x20 + + + TARGET0_INT_RAW + interupt0 raw + 0 + 1 + read-write + + + TARGET1_INT_RAW + interupt1 raw + 1 + 1 + read-write + + + TARGET2_INT_RAW + interupt2 raw + 2 + 1 + read-write + + + + + INT_CLR + systimer interrupt clear register + 0x6C + 0x20 + + + TARGET0_INT_CLR + interupt0 clear + 0 + 1 + write-only + + + TARGET1_INT_CLR + interupt1 clear + 1 + 1 + write-only + + + TARGET2_INT_CLR + interupt2 clear + 2 + 1 + write-only + + + + + INT_ST + systimer interrupt status register + 0x70 + 0x20 + + + TARGET0_INT_ST + interupt0 status + 0 + 1 + read-only + + + TARGET1_INT_ST + interupt1 status + 1 + 1 + read-only + + + TARGET2_INT_ST + interupt2 status + 2 + 1 + read-only + + + + + REAL_TARGET0_LO + system timer comp0 actual target value low register + 0x74 + 0x20 + + + TARGET0_LO_RO + actual target value value low 32bits + 0 + 32 + read-only + + + + + REAL_TARGET0_HI + system timer comp0 actual target value high register + 0x78 + 0x20 + + + TARGET0_HI_RO + actual target value value high 20bits + 0 + 20 + read-only + + + + + REAL_TARGET1_LO + system timer comp1 actual target value low register + 0x7C + 0x20 + + + TARGET1_LO_RO + actual target value value low 32bits + 0 + 32 + read-only + + + + + REAL_TARGET1_HI + system timer comp1 actual target value high register + 0x80 + 0x20 + + + TARGET1_HI_RO + actual target value value high 20bits + 0 + 20 + read-only + + + + + REAL_TARGET2_LO + system timer comp2 actual target value low register + 0x84 + 0x20 + + + TARGET2_LO_RO + actual target value value low 32bits + 0 + 32 + read-only + + + + + REAL_TARGET2_HI + system timer comp2 actual target value high register + 0x88 + 0x20 + + + TARGET2_HI_RO + actual target value value high 20bits + 0 + 20 + read-only + + + + + DATE + system timer version control register + 0xFC + 0x20 + 0x02201073 + + + DATE + systimer register version + 0 + 32 + read-write + + + + + + + TIMG0 + Timer Group 0 + TIMG + 0x500C2000 + + 0x0 + 0x68 + registers + + + TG0_T0 + 46 + + + TG0_T1 + 47 + + + TG0_WDT + 48 + + + + T0CONFIG + Timer %s configuration register + 0x0 + 0x20 + 0x60002000 + + + USE_XTAL + 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source clock of timer group. + 9 + 1 + read-write + + + ALARM_EN + When set, the alarm is enabled. This bit is automatically cleared once an +alarm occurs. + 10 + 1 + read-write + + + DIVCNT_RST + When set, Timer %s 's clock divider counter will be reset. + 12 + 1 + write-only + + + DIVIDER + Timer %s clock (T%s_clk) prescaler value. + 13 + 16 + read-write + + + AUTORELOAD + When set, timer %s auto-reload at alarm is enabled. + 29 + 1 + read-write + + + INCREASE + When set, the timer %s time-base counter will increment every clock tick. When +cleared, the timer %s time-base counter will decrement. + 30 + 1 + read-write + + + EN + When set, the timer %s time-base counter is enabled. + 31 + 1 + read-write + + + + + T0LO + Timer %s current value, low 32 bits + 0x4 + 0x20 + + + LO + After writing to TIMG_T%sUPDATE_REG, the low 32 bits of the time-base counter +of timer %s can be read here. + 0 + 32 + read-only + + + + + T0HI + Timer %s current value, high 22 bits + 0x8 + 0x20 + + + HI + After writing to TIMG_T%sUPDATE_REG, the high 22 bits of the time-base counter +of timer %s can be read here. + 0 + 22 + read-only + + + + + T0UPDATE + Write to copy current timer value to TIMGn_T%s_(LO/HI)_REG + 0xC + 0x20 + + + UPDATE + After writing 0 or 1 to TIMG_T%sUPDATE_REG, the counter value is latched. + 31 + 1 + read-write + + + + + T0ALARMLO + Timer %s alarm value, low 32 bits + 0x10 + 0x20 + + + ALARM_LO + Timer %s alarm trigger time-base counter value, low 32 bits. + 0 + 32 + read-write + + + + + T0ALARMHI + Timer %s alarm value, high bits + 0x14 + 0x20 + + + ALARM_HI + Timer %s alarm trigger time-base counter value, high 22 bits. + 0 + 22 + read-write + + + + + T0LOADLO + Timer %s reload value, low 32 bits + 0x18 + 0x20 + + + LOAD_LO + Low 32 bits of the value that a reload will load onto timer %s time-base +Counter. + 0 + 32 + read-write + + + + + T0LOADHI + Timer %s reload value, high 22 bits + 0x1C + 0x20 + + + LOAD_HI + High 22 bits of the value that a reload will load onto timer %s time-base +counter. + 0 + 22 + read-write + + + + + T0LOAD + Write to reload timer from TIMG_T%s_(LOADLOLOADHI)_REG + 0x20 + 0x20 + + + LOAD + Write any value to trigger a timer %s time-base counter reload. + 0 + 32 + write-only + + + + + WDTCONFIG0 + Watchdog timer configuration register + 0x48 + 0x20 + 0x0004C000 + + + WDT_APPCPU_RESET_EN + WDT reset CPU enable. + 12 + 1 + read-write + + + WDT_PROCPU_RESET_EN + WDT reset CPU enable. + 13 + 1 + read-write + + + WDT_FLASHBOOT_MOD_EN + When set, Flash boot protection is enabled. + 14 + 1 + read-write + + + WDT_SYS_RESET_LENGTH + System reset signal length selection. 0: 100 ns, 1: 200 ns, +2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. + 15 + 3 + read-write + + + WDT_CPU_RESET_LENGTH + CPU reset signal length selection. 0: 100 ns, 1: 200 ns, +2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. + 18 + 3 + read-write + + + WDT_USE_XTAL + choose WDT clock:0-apb_clk, 1-xtal_clk. + 21 + 1 + read-write + + + WDT_CONF_UPDATE_EN + update the WDT configuration registers + 22 + 1 + write-only + + + WDT_STG3 + Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + 23 + 2 + read-write + + + WDT_STG2 + Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + 25 + 2 + read-write + + + WDT_STG1 + Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + 27 + 2 + read-write + + + WDT_STG0 + Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + 29 + 2 + read-write + + + WDT_EN + When set, MWDT is enabled. + 31 + 1 + read-write + + + + + WDTCONFIG1 + Watchdog timer prescaler register + 0x4C + 0x20 + 0x00010000 + + + WDT_DIVCNT_RST + When set, WDT 's clock divider counter will be reset. + 0 + 1 + write-only + + + WDT_CLK_PRESCALE + MWDT clock prescaler value. MWDT clock period = 12.5 ns * +TIMG_WDT_CLK_PRESCALE. + 16 + 16 + read-write + + + + + WDTCONFIG2 + Watchdog timer stage 0 timeout value + 0x50 + 0x20 + 0x018CBA80 + + + WDT_STG0_HOLD + Stage 0 timeout value, in MWDT clock cycles. + 0 + 32 + read-write + + + + + WDTCONFIG3 + Watchdog timer stage 1 timeout value + 0x54 + 0x20 + 0x07FFFFFF + + + WDT_STG1_HOLD + Stage 1 timeout value, in MWDT clock cycles. + 0 + 32 + read-write + + + + + WDTCONFIG4 + Watchdog timer stage 2 timeout value + 0x58 + 0x20 + 0x000FFFFF + + + WDT_STG2_HOLD + Stage 2 timeout value, in MWDT clock cycles. + 0 + 32 + read-write + + + + + WDTCONFIG5 + Watchdog timer stage 3 timeout value + 0x5C + 0x20 + 0x000FFFFF + + + WDT_STG3_HOLD + Stage 3 timeout value, in MWDT clock cycles. + 0 + 32 + read-write + + + + + WDTFEED + Write to feed the watchdog timer + 0x60 + 0x20 + + + WDT_FEED + Write any value to feed the MWDT. (WO) + 0 + 32 + write-only + + + + + WDTWPROTECT + Watchdog write protect register + 0x64 + 0x20 + 0x50D83AA1 + + + WDT_WKEY + If the register contains a different value than its reset value, write +protection is enabled. + 0 + 32 + read-write + + + + + RTCCALICFG + RTC calibration configure register + 0x68 + 0x20 + 0x00011000 + + + RTC_CALI_START_CYCLING + 0: one-shot frequency calculation,1: periodic frequency calculation, + 12 + 1 + read-write + + + RTC_CALI_CLK_SEL + 0:rtc slow clock. 1:clk_8m, 2:xtal_32k. + 13 + 2 + read-write + + + RTC_CALI_RDY + indicate one-shot frequency calculation is done. + 15 + 1 + read-only + + + RTC_CALI_MAX + Configure the time to calculate RTC slow clock's frequency. + 16 + 15 + read-write + + + RTC_CALI_START + Set this bit to start one-shot frequency calculation. + 31 + 1 + read-write + + + + + RTCCALICFG1 + RTC calibration configure1 register + 0x6C + 0x20 + + + RTC_CALI_CYCLING_DATA_VLD + indicate periodic frequency calculation is done. + 0 + 1 + read-only + + + RTC_CALI_VALUE + When one-shot or periodic frequency calculation is done, read this value to calculate RTC slow clock's frequency. + 7 + 25 + read-only + + + + + INT_ENA_TIMERS + Interrupt enable bits + 0x70 + 0x20 + + + T0_INT_ENA + The interrupt enable bit for the TIMG_T0_INT interrupt. + 0 + 1 + read-write + + + T1_INT_ENA + The interrupt enable bit for the TIMG_T1_INT interrupt. + 1 + 1 + read-write + + + WDT_INT_ENA + The interrupt enable bit for the TIMG_WDT_INT interrupt. + 2 + 1 + read-write + + + + + INT_RAW_TIMERS + Raw interrupt status + 0x74 + 0x20 + + + T0_INT_RAW + The raw interrupt status bit for the TIMG_T0_INT interrupt. + 0 + 1 + read-only + + + T1_INT_RAW + The raw interrupt status bit for the TIMG_T1_INT interrupt. + 1 + 1 + read-only + + + WDT_INT_RAW + The raw interrupt status bit for the TIMG_WDT_INT interrupt. + 2 + 1 + read-only + + + + + INT_ST_TIMERS + Masked interrupt status + 0x78 + 0x20 + + + T0_INT_ST + The masked interrupt status bit for the TIMG_T0_INT interrupt. + 0 + 1 + read-only + + + T1_INT_ST + The masked interrupt status bit for the TIMG_T1_INT interrupt. + 1 + 1 + read-only + + + WDT_INT_ST + The masked interrupt status bit for the TIMG_WDT_INT interrupt. + 2 + 1 + read-only + + + + + INT_CLR_TIMERS + Interrupt clear bits + 0x7C + 0x20 + + + T0_INT_CLR + Set this bit to clear the TIMG_T0_INT interrupt. + 0 + 1 + write-only + + + T1_INT_CLR + Set this bit to clear the TIMG_T1_INT interrupt. + 1 + 1 + write-only + + + WDT_INT_CLR + Set this bit to clear the TIMG_WDT_INT interrupt. + 2 + 1 + write-only + + + + + RTCCALICFG2 + Timer group calibration register + 0x80 + 0x20 + 0xFFFFFF98 + + + RTC_CALI_TIMEOUT + RTC calibration timeout indicator + 0 + 1 + read-only + + + RTC_CALI_TIMEOUT_RST_CNT + Cycles that release calibration timeout reset + 3 + 4 + read-write + + + RTC_CALI_TIMEOUT_THRES + Threshold value for the RTC calibration timer. If the calibration timer's value exceeds this threshold, a timeout is triggered. + 7 + 25 + read-write + + + + + NTIMERS_DATE + Timer version control register + 0xF8 + 0x20 + 0x02209142 + + + NTIMGS_DATE + Timer version control register + 0 + 28 + read-write + + + + + REGCLK + Timer group clock gate register + 0xFC + 0x20 + 0x70000000 + + + ETM_EN + enable timer's etm task and event + 28 + 1 + read-write + + + WDT_CLK_IS_ACTIVE + enable WDT's clock + 29 + 1 + read-write + + + TIMER_CLK_IS_ACTIVE + enable Timer 30's clock + 30 + 1 + read-write + + + CLK_EN + Register clock gate signal. 1: Registers can be read and written to by software. 0: Registers can not be read or written to by software. + 31 + 1 + read-write + + + + + + + TIMG1 + Timer Group 1 + 0x500C3000 + + TG1_T0 + 49 + + + TG1_T1 + 50 + + + TG1_WDT + 51 + + + + TRACE0 + TRACE0 Peripheral + TRACE + 0x3FF04000 + + 0x0 + 0x4C + registers + + + + MEM_START_ADDR + mem start addr + 0x0 + 0x20 + + + MEM_START_ADDR + The start address of trace memory + 0 + 32 + read-write + + + + + MEM_END_ADDR + mem end addr + 0x4 + 0x20 + 0xFFFFFFFF + + + MEM_END_ADDR + The end address of trace memory + 0 + 32 + read-write + + + + + MEM_CURRENT_ADDR + mem current addr + 0x8 + 0x20 + + + MEM_CURRENT_ADDR + current_mem_addr,indicate that next writing addr + 0 + 32 + read-only + + + + + MEM_ADDR_UPDATE + mem addr update + 0xC + 0x20 + + + MEM_CURRENT_ADDR_UPDATE + when set, the will \hyperref[fielddesc:TRACEMEMCURRENTADDR]{TRACE_MEM_CURRENT_ADDR} update to \hyperref[fielddesc:TRACEMEMSTARTADDR]{TRACE_MEM_START_ADDR}. + 0 + 1 + write-only + + + + + FIFO_STATUS + fifo status register + 0x10 + 0x20 + 0x00000001 + + + FIFO_EMPTY + Represent whether the fifo is empty. \\1: empty \\0: not empty + 0 + 1 + read-only + + + WORK_STATUS + Represent trace work status: \\0: idle state \\1: working state\\ 2: wait state due to hart halted or havereset \\3: lost state + 1 + 2 + read-only + + + + + INTR_ENA + interrupt enable register + 0x14 + 0x20 + + + FIFO_OVERFLOW_INTR_ENA + Set 1 enable fifo_overflow interrupt + 0 + 1 + read-write + + + MEM_FULL_INTR_ENA + Set 1 enable mem_full interrupt + 1 + 1 + read-write + + + + + INTR_RAW + interrupt status register + 0x18 + 0x20 + + + FIFO_OVERFLOW_INTR_RAW + fifo_overflow interrupt status + 0 + 1 + read-only + + + MEM_FULL_INTR_RAW + mem_full interrupt status + 1 + 1 + read-only + + + + + INTR_CLR + interrupt clear register + 0x1C + 0x20 + + + FIFO_OVERFLOW_INTR_CLR + Set 1 clear fifo overflow interrupt + 0 + 1 + write-only + + + MEM_FULL_INTR_CLR + Set 1 clear mem full interrupt + 1 + 1 + write-only + + + + + TRIGGER + trigger register + 0x20 + 0x20 + 0x0000000C + + + ON + Configure whether or not start trace.\\1: start trace \\0: invalid\\ + 0 + 1 + write-only + + + OFF + Configure whether or not stop trace.\\1: stop trace \\0: invalid\\ + 1 + 1 + write-only + + + MEM_LOOP + Configure memory loop mode. \\1: trace will loop wrtie trace_mem. \\0: when mem_current_addr at mem_end_addr, it will stop at the mem_end_addr\\ + 2 + 1 + read-write + + + RESTART_ENA + Configure whether or not enable auto-restart.\\1: enable\\0: disable\\ + 3 + 1 + read-write + + + + + CONFIG + trace configuration register + 0x24 + 0x20 + + + DM_TRIGGER_ENA + Configure whether or not enable cpu trigger action.\\1: enable\\0:disable\\ + 0 + 1 + read-write + + + RESET_ENA + Configure whether or not enable trace cpu haverest, when enabeld, if cpu have reset, the encoder will output a packet to report the address of the last instruction, and upon reset deassertion, the encoder start again.\\1: enabeld\\0: disabled\\ + 1 + 1 + read-write + + + HALT_ENA + Configure whether or not enable trace cpu is halted, when enabeld, if the cpu halted, the encoder will output a packet to report the address of the last instruction, and upon halted deassertion, the encoder start again.When disabled, encoder will not report the last address before halted and first address after halted, cpu halted information will not be tracked. \\1: enabeld\\0: disabled\\ + 2 + 1 + read-write + + + STALL_ENA + Configure whether or not enable stall cpu. When enabled, when the fifo almost full, the cpu will be stalled until the packets is able to write to fifo.\\1: enabled.\\0: disabled\\ + 3 + 1 + read-write + + + FULL_ADDRESS + Configure whether or not enable full-address mode.\\1: full address mode.\\0: delta address mode\\ + 4 + 1 + read-write + + + IMPLICIT_EXCEPT + Configure whether or not enabel implicit exception mode. When enabled,, do not sent exception address, only exception cause in exception packets.\\1: enabled\\0: disabled\\ + 5 + 1 + read-write + + + + + FILTER_CONTROL + filter control register + 0x28 + 0x20 + + + FILTER_EN + Configure whether or not enable filter unit. \\1: enable filter.\\ 0: always match + 0 + 1 + read-write + + + MATCH_COMP + when set, the comparator must be high in order for the filter to match + 1 + 1 + read-write + + + MATCH_PRIVILEGE + when set, match privilege levels specified by \hyperref[fielddesc:TRACEMATCHCHOICEPRIVILEGE]{TRACE_MATCH_CHOICE_PRIVILEGE}. + 2 + 1 + read-write + + + MATCH_ECAUSE + when set, start matching from exception cause codes specified by \hyperref[fielddesc:TRACEMATCHCHOICEECAUSE]{TRACE_MATCH_CHOICE_ECAUSE}, and stop matching upon return from the 1st matching exception. + 3 + 1 + read-write + + + MATCH_INTERRUPT + when set, start matching from a trap with the interrupt level codes specified by \hyperref[fielddesc:TRACEMATCHVALUEINTERRUPT]{TRACE_MATCH_VALUE_INTERRUPT}, and stop matching upon return from the 1st matching trap. + 4 + 1 + read-write + + + + + FILTER_MATCH_CONTROL + filter match control register + 0x2C + 0x20 + + + MATCH_CHOICE_PRIVILEGE + Select match which privilege level when \hyperref[fielddesc:TRACEMATCHPRIVILEGE]{TRACE_MATCH_PRIVILEGE} is set. \\1: machine mode. \\0: user mode + 0 + 1 + read-write + + + MATCH_VALUE_INTERRUPT + Select which match which itype when \hyperref[fielddesc:TRACEMATCHINTERRUPT]{TRACE_MATCH_INTERRUP} is set. \\1: match itype of 2. \\0: match itype or 1. + 1 + 1 + read-write + + + MATCH_CHOICE_ECAUSE + specified which ecause matched. + 2 + 6 + read-write + + + + + FILTER_COMPARATOR_CONTROL + filter comparator match control register + 0x30 + 0x20 + + + P_INPUT + Determines which input to compare against the primary comparator, \\0: iaddr, \\1: tval. + 0 + 1 + read-write + + + P_FUNCTION + Select the primary comparator function. \\0: equal, \\1: not equal, \\2: less than, \\3: less than or equal, \\4: greater than, \\5: greater than or equal, \\other: always match + 2 + 3 + read-write + + + P_NOTIFY + Generate a trace packet explicitly reporting the address that cause the primary match + 5 + 1 + read-write + + + S_INPUT + Determines which input to compare against the secondary comparator, \\0: iaddr, \\1: tval. + 8 + 1 + read-write + + + S_FUNCTION + Select the secondary comparator function. \\0: equal, \\1: not equal, \\2: less than, \\3: less than or equal, \\4: greater than, \\5: greater than or equal, \\other: always match + 10 + 3 + read-write + + + S_NOTIFY + Generate a trace packet explicitly reporting the address that cause the secondary match + 13 + 1 + read-write + + + MATCH_MODE + 0: only primary matches, \\1: primary and secondary comparator both matches(P\&\&S),\\ 2:either primary or secondary comparator matches !(P\&\&S), \\3: set when primary matches and continue to match until after secondary comparator matches + 16 + 2 + read-write + + + + + FILTER_P_COMPARATOR_MATCH + primary comparator match value + 0x34 + 0x20 + + + P_MATCH + primary comparator match value + 0 + 32 + read-write + + + + + FILTER_S_COMPARATOR_MATCH + secondary comparator match value + 0x38 + 0x20 + + + S_MATCH + secondary comparator match value + 0 + 32 + read-write + + + + + RESYNC_PROLONGED + resync configuration register + 0x3C + 0x20 + 0x00000080 + + + RESYNC_PROLONGED + count number, when count to this value, send a sync package + 0 + 24 + read-write + + + RESYNC_MODE + resyc mode sel: \\0: off, \\2: cycle count \\3: package num count + 24 + 2 + read-write + + + + + AHB_CONFIG + AHB config register + 0x40 + 0x20 + + + HBURST + set hburst + 0 + 3 + read-write + + + MAX_INCR + set max continuous access for incr mode + 3 + 3 + read-write + + + + + CLOCK_GATE + Clock gate control register + 0x44 + 0x20 + 0x00000001 + + + CLK_EN + The bit is used to enable clock gate when access all registers in this module. + 0 + 1 + read-write + + + + + DATE + Version control register + 0x3FC + 0x20 + 0x02211300 + + + DATE + version control register. Note that this default value stored is the latest date when the hardware logic was updated. + 0 + 28 + read-write + + + + + + + TRACE1 + TRACE1 Peripheral + 0x3FF05000 + + + LP_TSENS + Low-power Temperature Sensor + TSENS + 0x5012F000 + + 0x0 + 0x38 + registers + + + LP_TSENS + 15 + + + + CTRL + Tsens configuration. + 0x0 + 0x20 + 0x00019400 + + + OUT + Temperature sensor data out. + 0 + 8 + read-only + + + READY + Indicate temperature sensor out ready. + 8 + 1 + read-only + + + SAMPLE_EN + Enable sample signal for wakeup module. + 9 + 1 + read-write + + + WAKEUP_MASK + Wake up signal mask. + 10 + 1 + read-write + + + INT_EN + Enable temperature sensor to send out interrupt. + 12 + 1 + read-write + + + IN_INV + Invert temperature sensor data. + 13 + 1 + read-write + + + CLK_DIV + Temperature sensor clock divider. + 14 + 8 + read-write + + + POWER_UP + Temperature sensor power up. + 22 + 1 + read-write + + + POWER_UP_FORCE + 1: dump out & power up controlled by SW, 0: by FSM. + 23 + 1 + read-write + + + + + CTRL2 + Tsens configuration. + 0x4 + 0x20 + 0x00004002 + + + XPD_WAIT + N/A + 0 + 12 + read-write + + + XPD_FORCE + N/A + 12 + 2 + read-write + + + CLK_INV + N/A + 14 + 1 + read-write + + + + + INT_RAW + Tsens interrupt raw registers. + 0x8 + 0x20 + + + COCPU_TSENS_WAKE_INT_RAW + Tsens wakeup interrupt raw. + 0 + 1 + read-write + + + + + INT_ST + Tsens interrupt status registers. + 0xC + 0x20 + + + COCPU_TSENS_WAKE_INT_ST + Tsens wakeup interrupt status. + 0 + 1 + read-only + + + + + INT_ENA + Tsens interrupt enable registers. + 0x10 + 0x20 + + + COCPU_TSENS_WAKE_INT_ENA + Tsens wakeup interrupt enable. + 0 + 1 + read-write + + + + + INT_CLR + Tsens interrupt clear registers. + 0x14 + 0x20 + + + COCPU_TSENS_WAKE_INT_CLR + Tsens wakeup interrupt clear. + 0 + 1 + write-only + + + + + CLK_CONF + Tsens regbank configuration registers. + 0x18 + 0x20 + + + CLK_EN + Tsens regbank clock gating enable. + 0 + 1 + read-write + + + + + INT_ENA_W1TS + Tsens wakeup interrupt enable assert. + 0x1C + 0x20 + + + COCPU_TSENS_WAKE_INT_ENA_W1TS + Write 1 to this field to assert interrupt enable. + 0 + 1 + write-only + + + + + INT_ENA_W1TC + Tsens wakeup interrupt enable deassert. + 0x20 + 0x20 + + + COCPU_TSENS_WAKE_INT_ENA_W1TC + Write 1 to this field to deassert interrupt enable. + 0 + 1 + write-only + + + + + WAKEUP_CTRL + Tsens wakeup control registers. + 0x24 + 0x20 + 0x003FC000 + + + WAKEUP_TH_LOW + Lower threshold. + 0 + 8 + read-write + + + WAKEUP_TH_HIGH + Upper threshold. + 14 + 8 + read-write + + + WAKEUP_OVER_UPPER_TH + Indicates that this wakeup event arose from exceeding upper threshold. + 29 + 1 + read-only + + + WAKEUP_EN + Tsens wakeup enable. + 30 + 1 + read-write + + + WAKEUP_MODE + 0:absolute value comparison mode. 1: relative value comparison mode. + 31 + 1 + read-write + + + + + SAMPLE_RATE + Hardware automatic sampling control registers. + 0x28 + 0x20 + 0x00000014 + + + SAMPLE_RATE + Hardware automatic sampling rate. + 0 + 16 + read-write + + + + + RND_ECO_LOW + N/A + 0x2C + 0x20 + + + RND_ECO_LOW + N/A + 0 + 32 + read-write + + + + + RND_ECO_HIGH + N/A + 0x30 + 0x20 + 0xFFFFFFFF + + + RND_ECO_HIGH + N/A + 0 + 32 + read-write + + + + + RND_ECO_CS + N/A + 0x34 + 0x20 + + + RND_ECO_EN + N/A + 0 + 1 + read-write + + + RND_ECO_RESULT + N/A + 1 + 1 + read-only + + + + + + + TWAI0 + Two-Wire Automotive Interface + TWAI + 0x500D7000 + + 0x0 + 0x8C + registers + + + TWAI0 + 40 + + + + MODE + TWAI mode register. + 0x0 + 0x20 + 0x00000001 + + + RESET_MODE + 1: reset, detection of a set reset mode bit results in aborting the current transmission/reception of a message and entering the reset mode. 0: normal, on the '1-to-0' transition of the reset mode bit, the TWAI controller returns to the operating mode. + 0 + 1 + read-write + + + LISTEN_ONLY_MODE + 1: listen only, in this mode the TWAI controller would give no acknowledge to the TWAI-bus, even if a message is received successfully. The error counters are stopped at the current value. 0: normal. + 1 + 1 + read-write + + + SELF_TEST_MODE + 1: self test, in this mode a full node test is possible without any other active node on the bus using the self reception request command. The TWAI controller will perform a successful transmission, even if there is no acknowledge received. 0: normal, an acknowledge is required for successful transmission. + 2 + 1 + read-write + + + ACCEPTANCE_FILTER_MODE + 1:single, the single acceptance filter option is enabled (one filter with the length of 32 bit is active). 0:dual, the dual acceptance filter option is enabled (two filters, each with the length of 16 bit are active). + 3 + 1 + read-write + + + + + CMD + TWAI command register. + 0x4 + 0x20 + + + TX_REQUEST + 1: present, a message shall be transmitted. 0: absent + 0 + 1 + write-only + + + ABORT_TX + 1: present, if not already in progress, a pending transmission request is cancelled. 0: absent + 1 + 1 + write-only + + + RELEASE_BUFFER + 1: released, the receive buffer, representing the message memory space in the RXFIFO is released. 0: no action + 2 + 1 + write-only + + + CLEAR_DATA_OVERRUN + 1: clear, the data overrun status bit is cleared. 0: no action. + 3 + 1 + write-only + + + SELF_RX_REQUEST + 1: present, a message shall be transmitted and received simultaneously. 0: absent. + 4 + 1 + write-only + + + + + STATUS + TWAI status register. + 0x8 + 0x20 + + + RECEIVE_BUFFER + 1: full, one or more complete messages are available in the RXFIFO. 0: empty, no message is available + 0 + 1 + read-only + + + OVERRUN + 1: overrun, a message was lost because there was not enough space for that message in the RXFIFO. 0: absent, no data overrun has occurred since the last clear data overrun command was given + 1 + 1 + read-only + + + TRANSMIT_BUFFER + 1: released, the CPU may write a message into the transmit buffer. 0: locked, the CPU cannot access the transmit buffer, a message is either waiting for transmission or is in the process of being transmitted + 2 + 1 + read-only + + + TRANSMISSION_COMPLETE + 1: complete, last requested transmission has been successfully completed. 0: incomplete, previously requested transmission is not yet completed + 3 + 1 + read-only + + + RECEIVE + 1: receive, the TWAI controller is receiving a message. 0: idle + 4 + 1 + read-only + + + TRANSMIT + 1: transmit, the TWAI controller is transmitting a message. 0: idle + 5 + 1 + read-only + + + ERR + 1: error, at least one of the error counters has reached or exceeded the CPU warning limit defined by the Error Warning Limit Register (EWLR). 0: ok, both error counters are below the warning limit + 6 + 1 + read-only + + + NODE_BUS_OFF + 1: bus-off, the TWAI controller is not involved in bus activities. 0: bus-on, the TWAI controller is involved in bus activities + 7 + 1 + read-only + + + MISS + 1: current message is destroyed because of FIFO overflow. + 8 + 1 + read-only + + + + + INTERRUPT + Interrupt signals' register. + 0xC + 0x20 + + + RECEIVE_INT_ST + 1: this bit is set while the receive FIFO is not empty and the RIE bit is set within the interrupt enable register. 0: reset + 0 + 1 + read-only + + + TRANSMIT_INT_ST + 1: this bit is set whenever the transmit buffer status changes from '0-to-1' (released) and the TIE bit is set within the interrupt enable register. 0: reset + 1 + 1 + read-only + + + ERR_WARNING_INT_ST + 1: this bit is set on every change (set and clear) of either the error status or bus status bits and the EIE bit is set within the interrupt enable register. 0: reset + 2 + 1 + read-only + + + DATA_OVERRUN_INT_ST + 1: this bit is set on a '0-to-1' transition of the data overrun status bit and the DOIE bit is set within the interrupt enable register. 0: reset + 3 + 1 + read-only + + + TS_COUNTER_OVFL_INT_ST + 1: this bit is set then the timestamp counter reaches the maximum value and overflow. + 4 + 1 + read-only + + + ERR_PASSIVE_INT_ST + 1: this bit is set whenever the TWAI controller has reached the error passive status (at least one error counter exceeds the protocol-defined level of 127) or if the TWAI controller is in the error passive status and enters the error active status again and the EPIE bit is set within the interrupt enable register. 0: reset + 5 + 1 + read-only + + + ARBITRATION_LOST_INT_ST + 1: this bit is set when the TWAI controller lost the arbitration and becomes a receiver and the ALIE bit is set within the interrupt enable register. 0: reset + 6 + 1 + read-only + + + BUS_ERR_INT_ST + 1: this bit is set when the TWAI controller detects an error on the TWAI-bus and the BEIE bit is set within the interrupt enable register. 0: reset + 7 + 1 + read-only + + + IDLE_INT_ST + 1: this bit is set when the TWAI controller detects state of TWAI become IDLE and this interrupt enable bit is set within the interrupt enable register. 0: reset + 8 + 1 + read-only + + + + + INTERRUPT_ENABLE + Interrupt enable register. + 0x10 + 0x20 + + + EXT_RECEIVE_INT_ENA + 1: enabled, when the receive buffer status is 'full' the TWAI controller requests the respective interrupt. 0: disable + 0 + 1 + read-write + + + EXT_TRANSMIT_INT_ENA + 1: enabled, when a message has been successfully transmitted or the transmit buffer is accessible again (e.g. after an abort transmission command), the TWAI controller requests the respective interrupt. 0: disable + 1 + 1 + read-write + + + EXT_ERR_WARNING_INT_ENA + 1: enabled, if the error or bus status change (see status register. Table 14), the TWAI controllerrequests the respective interrupt. 0: disable + 2 + 1 + read-write + + + EXT_DATA_OVERRUN_INT_ENA + 1: enabled, if the data overrun status bit is set (see status register. Table 14), the TWAI controllerrequests the respective interrupt. 0: disable + 3 + 1 + read-write + + + TS_COUNTER_OVFL_INT_ENA + enable the timestamp counter overflow interrupt request. + 4 + 1 + read-write + + + ERR_PASSIVE_INT_ENA + 1: enabled, if the error status of the TWAI controller changes from error active to error passive or vice versa, the respective interrupt is requested. 0: disable + 5 + 1 + read-write + + + ARBITRATION_LOST_INT_ENA + 1: enabled, if the TWAI controller has lost arbitration, the respective interrupt is requested. 0: disable + 6 + 1 + read-write + + + BUS_ERR_INT_ENA + 1: enabled, if an bus error has been detected, the TWAI controller requests the respective interrupt. 0: disable + 7 + 1 + read-write + + + IDLE_INT_ENA + 1: enabled, if state of TWAI become IDLE, the TWAI controller requests the respective interrupt. 0: disable + 8 + 1 + read-only + + + + + BUS_TIMING_0 + Bit timing configuration register 0. + 0x18 + 0x20 + + + BAUD_PRESC + The period of the TWAI system clock is programmable and determines the individual bit timing. Software has R/W permission in reset mode and RO permission in operation mode. + 0 + 14 + read-write + + + SYNC_JUMP_WIDTH + The synchronization jump width defines the maximum number of clock cycles a bit period may be shortened or lengthened. Software has R/W permission in reset mode and RO in operation mode. + 14 + 2 + read-write + + + + + BUS_TIMING_1 + Bit timing configuration register 1. + 0x1C + 0x20 + + + TIME_SEGMENT1 + The number of clock cycles in TSEG1 per bit timing. Software has R/W permission in reset mode and RO in operation mode. + 0 + 4 + read-write + + + TIME_SEGMENT2 + The number of clock cycles in TSEG2 per bit timing. Software has R/W permission in reset mode and RO in operation mode. + 4 + 3 + read-write + + + TIME_SAMPLING + 1: triple, the bus is sampled three times. 0: single, the bus is sampled once. Software has R/W permission in reset mode and RO in operation mode. + 7 + 1 + read-write + + + + + ARB_LOST_CAP + TWAI arbiter lost capture register. + 0x2C + 0x20 + + + ARBITRATION_LOST_CAPTURE + This register contains information about the bit position of losing arbitration. + 0 + 5 + read-only + + + + + ERR_CODE_CAP + TWAI error info capture register. + 0x30 + 0x20 + + + ERR_CAPTURE_CODE_SEGMENT + This register contains information about the location of errors on the bus. + 0 + 5 + read-only + + + ERR_CAPTURE_CODE_DIRECTION + 1: RX, error occurred during reception. 0: TX, error occurred during transmission. + 5 + 1 + read-only + + + ERR_CAPTURE_CODE_TYPE + 00: bit error. 01: form error. 10:stuff error. 11:other type of error. + 6 + 2 + read-only + + + + + ERR_WARNING_LIMIT + TWAI error threshold configuration register. + 0x34 + 0x20 + 0x00000060 + + + ERR_WARNING_LIMIT + The threshold that trigger error warning interrupt when this interrupt is enabled. Software has R/W permission in reset mode and RO in operation mode. + 0 + 8 + read-write + + + + + RX_ERR_CNT + Rx error counter register. + 0x38 + 0x20 + + + RX_ERR_CNT + The RX error counter register reflects the current value of the transmit error counter. Software has R/W permission in reset mode and RO in operation mode. + 0 + 8 + read-write + + + + + TX_ERR_CNT + Tx error counter register. + 0x3C + 0x20 + + + TX_ERR_CNT + The TX error counter register reflects the current value of the transmit error counter. Software has R/W permission in reset mode and RO in operation mode. + 0 + 8 + read-write + + + + + DATA_0 + Data register 0. + 0x40 + 0x20 + + + DATA_0 + In reset mode, it is acceptance code register 0 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 0 and when software initiate read operation, it is rx data register 0. + 0 + 8 + read-write + + + + + DATA_1 + Data register 1. + 0x44 + 0x20 + + + DATA_1 + In reset mode, it is acceptance code register 1 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 1 and when software initiate read operation, it is rx data register 1. + 0 + 8 + read-write + + + + + DATA_2 + Data register 2. + 0x48 + 0x20 + + + DATA_2 + In reset mode, it is acceptance code register 2 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 2 and when software initiate read operation, it is rx data register 2. + 0 + 8 + read-write + + + + + DATA_3 + Data register 3. + 0x4C + 0x20 + + + DATA_3 + In reset mode, it is acceptance code register 3 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 3 and when software initiate read operation, it is rx data register 3. + 0 + 8 + read-write + + + + + DATA_4 + Data register 4. + 0x50 + 0x20 + + + DATA_4 + In reset mode, it is acceptance mask register 0 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 4 and when software initiate read operation, it is rx data register 4. + 0 + 8 + read-write + + + + + DATA_5 + Data register 5. + 0x54 + 0x20 + + + DATA_5 + In reset mode, it is acceptance mask register 1 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 5 and when software initiate read operation, it is rx data register 5. + 0 + 8 + read-write + + + + + DATA_6 + Data register 6. + 0x58 + 0x20 + + + DATA_6 + In reset mode, it is acceptance mask register 2 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 6 and when software initiate read operation, it is rx data register 6. + 0 + 8 + read-write + + + + + DATA_7 + Data register 7. + 0x5C + 0x20 + + + DATA_7 + In reset mode, it is acceptance mask register 3 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 7 and when software initiate read operation, it is rx data register 7. + 0 + 8 + read-write + + + + + DATA_8 + Data register 8. + 0x60 + 0x20 + + + DATA_8 + In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 8 and when software initiate read operation, it is rx data register 8. + 0 + 8 + read-write + + + + + DATA_9 + Data register 9. + 0x64 + 0x20 + + + DATA_9 + In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 9 and when software initiate read operation, it is rx data register 9. + 0 + 8 + read-write + + + + + DATA_10 + Data register 10. + 0x68 + 0x20 + + + DATA_10 + In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 10 and when software initiate read operation, it is rx data register 10. + 0 + 8 + read-write + + + + + DATA_11 + Data register 11. + 0x6C + 0x20 + + + DATA_11 + In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 11 and when software initiate read operation, it is rx data register 11. + 0 + 8 + read-write + + + + + DATA_12 + Data register 12. + 0x70 + 0x20 + + + DATA_12 + In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 12 and when software initiate read operation, it is rx data register 12. + 0 + 8 + read-write + + + + + RX_MESSAGE_COUNTER + Received message counter register. + 0x74 + 0x20 + + + RX_MESSAGE_COUNTER + Reflects the number of messages available within the RXFIFO. The value is incremented with each receive event and decremented by the release receive buffer command. + 0 + 7 + read-only + + + + + CLOCK_DIVIDER + Clock divider register. + 0x7C + 0x20 + + + CD + These bits are used to define the frequency at the external CLKOUT pin. + 0 + 8 + read-write + + + CLOCK_OFF + 1: Disable the external CLKOUT pin. 0: Enable the external CLKOUT pin. Software has R/W permission in reset mode and RO in operation mode. + 8 + 1 + read-write + + + + + SW_STANDBY_CFG + Software configure standby pin directly. + 0x80 + 0x20 + 0x00000002 + + + SW_STANDBY_EN + Enable standby pin. + 0 + 1 + read-write + + + SW_STANDBY_CLR + Clear standby pin. + 1 + 1 + read-write + + + + + HW_CFG + Hardware configure standby pin. + 0x84 + 0x20 + + + HW_STANDBY_EN + Enable function that hardware control standby pin. + 0 + 1 + read-write + + + + + HW_STANDBY_CNT + Configure standby counter. + 0x88 + 0x20 + 0x00000001 + + + STANDBY_WAIT_CNT + Configure the number of cycles before standby becomes high when TWAI_HW_STANDBY_EN is enabled. + 0 + 32 + read-write + + + + + IDLE_INTR_CNT + Configure idle interrupt counter. + 0x8C + 0x20 + 0x00000001 + + + IDLE_INTR_CNT + Configure the number of cycles before triggering idle interrupt. + 0 + 32 + read-write + + + + + ECO_CFG + ECO configuration register. + 0x90 + 0x20 + 0x00000002 + + + RDN_ENA + Enable eco module. + 0 + 1 + read-write + + + RDN_RESULT + Output of eco module. + 1 + 1 + read-only + + + + + TIMESTAMP_DATA + Timestamp data register + 0x94 + 0x20 + + + TIMESTAMP_DATA + Data of timestamp of a CAN frame. + 0 + 32 + read-only + + + + + TIMESTAMP_PRESCALER + Timestamp configuration register + 0x98 + 0x20 + 0x0000001F + + + TS_DIV_NUM + Configures the clock division number of timestamp counter. + 0 + 16 + read-write + + + + + TIMESTAMP_CFG + Timestamp configuration register + 0x9C + 0x20 + + + TS_ENABLE + enable the timestamp collection function. + 0 + 1 + read-write + + + + + + + TWAI1 + Two-Wire Automotive Interface + 0x500D8000 + + TWAI1 + 41 + + + + TWAI2 + Two-Wire Automotive Interface + 0x500D9000 + + TWAI2 + 42 + + + + UART0 + UART (Universal Asynchronous Receiver-Transmitter) Controller 0 + UART + 0x500CA000 + + 0x0 + 0x98 + registers + + + UART0 + 31 + + + + FIFO + FIFO data register + 0x0 + 0x20 + + + RXFIFO_RD_BYTE + UART 0 accesses FIFO via this register. + 0 + 8 + read-only + + + + + INT_RAW + Raw interrupt status + 0x4 + 0x20 + 0x00000002 + + + RXFIFO_FULL_INT_RAW + This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies. + 0 + 1 + read-write + + + TXFIFO_EMPTY_INT_RAW + This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies . + 1 + 1 + read-write + + + PARITY_ERR_INT_RAW + This interrupt raw bit turns to high level when receiver detects a parity error in the data. + 2 + 1 + read-write + + + FRM_ERR_INT_RAW + This interrupt raw bit turns to high level when receiver detects a data frame error . + 3 + 1 + read-write + + + RXFIFO_OVF_INT_RAW + This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store. + 4 + 1 + read-write + + + DSR_CHG_INT_RAW + This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal. + 5 + 1 + read-write + + + CTS_CHG_INT_RAW + This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal. + 6 + 1 + read-write + + + BRK_DET_INT_RAW + This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit. + 7 + 1 + read-write + + + RXFIFO_TOUT_INT_RAW + This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte. + 8 + 1 + read-write + + + SW_XON_INT_RAW + This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1. + 9 + 1 + read-write + + + SW_XOFF_INT_RAW + This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1. + 10 + 1 + read-write + + + GLITCH_DET_INT_RAW + This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit. + 11 + 1 + read-write + + + TX_BRK_DONE_INT_RAW + This interrupt raw bit turns to high level when transmitter completes sending NULL characters after all data in Tx-FIFO are sent. + 12 + 1 + read-write + + + TX_BRK_IDLE_DONE_INT_RAW + This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data. + 13 + 1 + read-write + + + TX_DONE_INT_RAW + This interrupt raw bit turns to high level when transmitter has send out all data in FIFO. + 14 + 1 + read-write + + + RS485_PARITY_ERR_INT_RAW + This interrupt raw bit turns to high level when receiver detects a parity error from the echo of transmitter in rs485 mode. + 15 + 1 + read-write + + + RS485_FRM_ERR_INT_RAW + This interrupt raw bit turns to high level when receiver detects a data frame error from the echo of transmitter in rs485 mode. + 16 + 1 + read-write + + + RS485_CLASH_INT_RAW + This interrupt raw bit turns to high level when detects a clash between transmitter and receiver in rs485 mode. + 17 + 1 + read-write + + + AT_CMD_CHAR_DET_INT_RAW + This interrupt raw bit turns to high level when receiver detects the configured at_cmd char. + 18 + 1 + read-write + + + WAKEUP_INT_RAW + This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode. + 19 + 1 + read-write + + + + + INT_ST + Masked interrupt status + 0x8 + 0x20 + + + RXFIFO_FULL_INT_ST + This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. + 0 + 1 + read-only + + + TXFIFO_EMPTY_INT_ST + This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1. + 1 + 1 + read-only + + + PARITY_ERR_INT_ST + This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. + 2 + 1 + read-only + + + FRM_ERR_INT_ST + This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1. + 3 + 1 + read-only + + + RXFIFO_OVF_INT_ST + This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. + 4 + 1 + read-only + + + DSR_CHG_INT_ST + This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. + 5 + 1 + read-only + + + CTS_CHG_INT_ST + This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. + 6 + 1 + read-only + + + BRK_DET_INT_ST + This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. + 7 + 1 + read-only + + + RXFIFO_TOUT_INT_ST + This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. + 8 + 1 + read-only + + + SW_XON_INT_ST + This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. + 9 + 1 + read-only + + + SW_XOFF_INT_ST + This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. + 10 + 1 + read-only + + + GLITCH_DET_INT_ST + This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. + 11 + 1 + read-only + + + TX_BRK_DONE_INT_ST + This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. + 12 + 1 + read-only + + + TX_BRK_IDLE_DONE_INT_ST + This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1. + 13 + 1 + read-only + + + TX_DONE_INT_ST + This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. + 14 + 1 + read-only + + + RS485_PARITY_ERR_INT_ST + This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1. + 15 + 1 + read-only + + + RS485_FRM_ERR_INT_ST + This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set to 1. + 16 + 1 + read-only + + + RS485_CLASH_INT_ST + This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1. + 17 + 1 + read-only + + + AT_CMD_CHAR_DET_INT_ST + This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1. + 18 + 1 + read-only + + + WAKEUP_INT_ST + This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1. + 19 + 1 + read-only + + + + + INT_ENA + Interrupt enable bits + 0xC + 0x20 + + + RXFIFO_FULL_INT_ENA + This is the enable bit for rxfifo_full_int_st register. + 0 + 1 + read-write + + + TXFIFO_EMPTY_INT_ENA + This is the enable bit for txfifo_empty_int_st register. + 1 + 1 + read-write + + + PARITY_ERR_INT_ENA + This is the enable bit for parity_err_int_st register. + 2 + 1 + read-write + + + FRM_ERR_INT_ENA + This is the enable bit for frm_err_int_st register. + 3 + 1 + read-write + + + RXFIFO_OVF_INT_ENA + This is the enable bit for rxfifo_ovf_int_st register. + 4 + 1 + read-write + + + DSR_CHG_INT_ENA + This is the enable bit for dsr_chg_int_st register. + 5 + 1 + read-write + + + CTS_CHG_INT_ENA + This is the enable bit for cts_chg_int_st register. + 6 + 1 + read-write + + + BRK_DET_INT_ENA + This is the enable bit for brk_det_int_st register. + 7 + 1 + read-write + + + RXFIFO_TOUT_INT_ENA + This is the enable bit for rxfifo_tout_int_st register. + 8 + 1 + read-write + + + SW_XON_INT_ENA + This is the enable bit for sw_xon_int_st register. + 9 + 1 + read-write + + + SW_XOFF_INT_ENA + This is the enable bit for sw_xoff_int_st register. + 10 + 1 + read-write + + + GLITCH_DET_INT_ENA + This is the enable bit for glitch_det_int_st register. + 11 + 1 + read-write + + + TX_BRK_DONE_INT_ENA + This is the enable bit for tx_brk_done_int_st register. + 12 + 1 + read-write + + + TX_BRK_IDLE_DONE_INT_ENA + This is the enable bit for tx_brk_idle_done_int_st register. + 13 + 1 + read-write + + + TX_DONE_INT_ENA + This is the enable bit for tx_done_int_st register. + 14 + 1 + read-write + + + RS485_PARITY_ERR_INT_ENA + This is the enable bit for rs485_parity_err_int_st register. + 15 + 1 + read-write + + + RS485_FRM_ERR_INT_ENA + This is the enable bit for rs485_parity_err_int_st register. + 16 + 1 + read-write + + + RS485_CLASH_INT_ENA + This is the enable bit for rs485_clash_int_st register. + 17 + 1 + read-write + + + AT_CMD_CHAR_DET_INT_ENA + This is the enable bit for at_cmd_char_det_int_st register. + 18 + 1 + read-write + + + WAKEUP_INT_ENA + This is the enable bit for uart_wakeup_int_st register. + 19 + 1 + read-write + + + + + INT_CLR + Interrupt clear bits + 0x10 + 0x20 + + + RXFIFO_FULL_INT_CLR + Set this bit to clear the rxfifo_full_int_raw interrupt. + 0 + 1 + write-only + + + TXFIFO_EMPTY_INT_CLR + Set this bit to clear txfifo_empty_int_raw interrupt. + 1 + 1 + write-only + + + PARITY_ERR_INT_CLR + Set this bit to clear parity_err_int_raw interrupt. + 2 + 1 + write-only + + + FRM_ERR_INT_CLR + Set this bit to clear frm_err_int_raw interrupt. + 3 + 1 + write-only + + + RXFIFO_OVF_INT_CLR + Set this bit to clear rxfifo_ovf_int_raw interrupt. + 4 + 1 + write-only + + + DSR_CHG_INT_CLR + Set this bit to clear the dsr_chg_int_raw interrupt. + 5 + 1 + write-only + + + CTS_CHG_INT_CLR + Set this bit to clear the cts_chg_int_raw interrupt. + 6 + 1 + write-only + + + BRK_DET_INT_CLR + Set this bit to clear the brk_det_int_raw interrupt. + 7 + 1 + write-only + + + RXFIFO_TOUT_INT_CLR + Set this bit to clear the rxfifo_tout_int_raw interrupt. + 8 + 1 + write-only + + + SW_XON_INT_CLR + Set this bit to clear the sw_xon_int_raw interrupt. + 9 + 1 + write-only + + + SW_XOFF_INT_CLR + Set this bit to clear the sw_xoff_int_raw interrupt. + 10 + 1 + write-only + + + GLITCH_DET_INT_CLR + Set this bit to clear the glitch_det_int_raw interrupt. + 11 + 1 + write-only + + + TX_BRK_DONE_INT_CLR + Set this bit to clear the tx_brk_done_int_raw interrupt.. + 12 + 1 + write-only + + + TX_BRK_IDLE_DONE_INT_CLR + Set this bit to clear the tx_brk_idle_done_int_raw interrupt. + 13 + 1 + write-only + + + TX_DONE_INT_CLR + Set this bit to clear the tx_done_int_raw interrupt. + 14 + 1 + write-only + + + RS485_PARITY_ERR_INT_CLR + Set this bit to clear the rs485_parity_err_int_raw interrupt. + 15 + 1 + write-only + + + RS485_FRM_ERR_INT_CLR + Set this bit to clear the rs485_frm_err_int_raw interrupt. + 16 + 1 + write-only + + + RS485_CLASH_INT_CLR + Set this bit to clear the rs485_clash_int_raw interrupt. + 17 + 1 + write-only + + + AT_CMD_CHAR_DET_INT_CLR + Set this bit to clear the at_cmd_char_det_int_raw interrupt. + 18 + 1 + write-only + + + WAKEUP_INT_CLR + Set this bit to clear the uart_wakeup_int_raw interrupt. + 19 + 1 + write-only + + + + + CLKDIV_SYNC + Clock divider configuration + 0x14 + 0x20 + 0x000002B6 + + + CLKDIV + The integral part of the frequency divider factor. + 0 + 12 + read-write + + + CLKDIV_FRAG + The decimal part of the frequency divider factor. + 20 + 4 + read-write + + + + + RX_FILT + Rx Filter configuration + 0x18 + 0x20 + 0x00000008 + + + GLITCH_FILT + when input pulse width is lower than this value the pulse is ignored. + 0 + 8 + read-write + + + GLITCH_FILT_EN + Set this bit to enable Rx signal filter. + 8 + 1 + read-write + + + + + STATUS + UART status register + 0x1C + 0x20 + 0xE000C000 + + + RXFIFO_CNT + Stores the byte number of valid data in Rx-FIFO. + 0 + 8 + read-only + + + DSRN + The register represent the level value of the internal uart dsr signal. + 13 + 1 + read-only + + + CTSN + This register represent the level value of the internal uart cts signal. + 14 + 1 + read-only + + + RXD + This register represent the level value of the internal uart rxd signal. + 15 + 1 + read-only + + + TXFIFO_CNT + Stores the byte number of data in Tx-FIFO. + 16 + 8 + read-only + + + DTRN + This bit represents the level of the internal uart dtr signal. + 29 + 1 + read-only + + + RTSN + This bit represents the level of the internal uart rts signal. + 30 + 1 + read-only + + + TXD + This bit represents the level of the internal uart txd signal. + 31 + 1 + read-only + + + + + CONF0_SYNC + a + 0x20 + 0x20 + 0x0000001C + + + PARITY + This register is used to configure the parity check mode. + 0 + 1 + read-write + + + PARITY_EN + Set this bit to enable uart parity check. + 1 + 1 + read-write + + + BIT_NUM + This register is used to set the length of data. + 2 + 2 + read-write + + + STOP_BIT_NUM + This register is used to set the length of stop bit. + 4 + 2 + read-write + + + TXD_BRK + Set this bit to enbale transmitter to send NULL when the process of sending data is done. + 6 + 1 + read-write + + + IRDA_DPLX + Set this bit to enable IrDA loopback mode. + 7 + 1 + read-write + + + IRDA_TX_EN + This is the start enable bit for IrDA transmitter. + 8 + 1 + read-write + + + IRDA_WCTL + 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0. + 9 + 1 + read-write + + + IRDA_TX_INV + Set this bit to invert the level of IrDA transmitter. + 10 + 1 + read-write + + + IRDA_RX_INV + Set this bit to invert the level of IrDA receiver. + 11 + 1 + read-write + + + LOOPBACK + Set this bit to enable uart loopback test mode. + 12 + 1 + read-write + + + TX_FLOW_EN + Set this bit to enable flow control function for transmitter. + 13 + 1 + read-write + + + IRDA_EN + Set this bit to enable IrDA protocol. + 14 + 1 + read-write + + + RXD_INV + Set this bit to inverse the level value of uart rxd signal. + 15 + 1 + read-write + + + TXD_INV + Set this bit to inverse the level value of uart txd signal. + 16 + 1 + read-write + + + DIS_RX_DAT_OVF + Disable UART Rx data overflow detect. + 17 + 1 + read-write + + + ERR_WR_MASK + 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong. + 18 + 1 + read-write + + + AUTOBAUD_EN + This is the enable bit for detecting baudrate. + 19 + 1 + read-write + + + MEM_CLK_EN + UART memory clock gate enable signal. + 20 + 1 + read-write + + + SW_RTS + This register is used to configure the software rts signal which is used in software flow control. + 21 + 1 + read-write + + + RXFIFO_RST + Set this bit to reset the uart receive-FIFO. + 22 + 1 + read-write + + + TXFIFO_RST + Set this bit to reset the uart transmit-FIFO. + 23 + 1 + read-write + + + + + CONF1 + Configuration register 1 + 0x24 + 0x20 + 0x00006060 + + + RXFIFO_FULL_THRHD + It will produce rxfifo_full_int interrupt when receiver receives more data than this register value. + 0 + 8 + read-write + + + TXFIFO_EMPTY_THRHD + It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value. + 8 + 8 + read-write + + + CTS_INV + Set this bit to inverse the level value of uart cts signal. + 16 + 1 + read-write + + + DSR_INV + Set this bit to inverse the level value of uart dsr signal. + 17 + 1 + read-write + + + RTS_INV + Set this bit to inverse the level value of uart rts signal. + 18 + 1 + read-write + + + DTR_INV + Set this bit to inverse the level value of uart dtr signal. + 19 + 1 + read-write + + + SW_DTR + This register is used to configure the software dtr signal which is used in software flow control. + 20 + 1 + read-write + + + CLK_EN + 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers. + 21 + 1 + read-write + + + + + HWFC_CONF_SYNC + Hardware flow-control configuration + 0x2C + 0x20 + + + RX_FLOW_THRHD + This register is used to configure the maximum amount of data that can be received when hardware flow control works. + 0 + 8 + read-write + + + RX_FLOW_EN + This is the flow enable bit for UART receiver. + 8 + 1 + read-write + + + + + SLEEP_CONF0 + UART sleep configure register 0 + 0x30 + 0x20 + + + WK_CHAR1 + This register restores the specified wake up char1 to wake up + 0 + 8 + read-write + + + WK_CHAR2 + This register restores the specified wake up char2 to wake up + 8 + 8 + read-write + + + WK_CHAR3 + This register restores the specified wake up char3 to wake up + 16 + 8 + read-write + + + WK_CHAR4 + This register restores the specified wake up char4 to wake up + 24 + 8 + read-write + + + + + SLEEP_CONF1 + UART sleep configure register 1 + 0x34 + 0x20 + + + WK_CHAR0 + This register restores the specified char0 to wake up + 0 + 8 + read-write + + + + + SLEEP_CONF2 + UART sleep configure register 2 + 0x38 + 0x20 + 0x001404F0 + + + ACTIVE_THRESHOLD + The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value. + 0 + 10 + read-write + + + RX_WAKE_UP_THRHD + In wake up mode 1 this field is used to set the received data number threshold to wake up chip. + 10 + 8 + read-write + + + WK_CHAR_NUM + This register is used to select number of wake up char. + 18 + 3 + read-write + + + WK_CHAR_MASK + This register is used to mask wake up char. + 21 + 5 + read-write + + + WK_MODE_SEL + This register is used to select wake up mode. 0: RXD toggling to wake up. 1: received data number larger than + 26 + 2 + read-write + + + + + SWFC_CONF0_SYNC + Software flow-control character configuration + 0x3C + 0x20 + 0x00001311 + + + XON_CHAR + This register stores the Xon flow control char. + 0 + 8 + read-write + + + XOFF_CHAR + This register stores the Xoff flow control char. + 8 + 8 + read-write + + + XON_XOFF_STILL_SEND + In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In this status, UART Tx can not transmit XOFF even the received data number is larger than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when UART Tx is disabled. + 16 + 1 + read-write + + + SW_FLOW_CON_EN + Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff. + 17 + 1 + read-write + + + XONOFF_DEL + Set this bit to remove flow control char from the received data. + 18 + 1 + read-write + + + FORCE_XON + Set this bit to enable the transmitter to go on sending data. + 19 + 1 + read-write + + + FORCE_XOFF + Set this bit to stop the transmitter from sending data. + 20 + 1 + read-write + + + SEND_XON + Set this bit to send Xon char. It is cleared by hardware automatically. + 21 + 1 + read-write + + + SEND_XOFF + Set this bit to send Xoff char. It is cleared by hardware automatically. + 22 + 1 + read-write + + + + + SWFC_CONF1 + Software flow-control character configuration + 0x40 + 0x20 + 0x0000E000 + + + XON_THRESHOLD + When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1 it will send a Xon char. + 0 + 8 + read-write + + + XOFF_THRESHOLD + When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1 it will send a Xoff char. + 8 + 8 + read-write + + + + + TXBRK_CONF_SYNC + Tx Break character configuration + 0x44 + 0x20 + 0x0000000A + + + TX_BRK_NUM + This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1. + 0 + 8 + read-write + + + + + IDLE_CONF_SYNC + Frame-end idle configuration + 0x48 + 0x20 + 0x00040100 + + + RX_IDLE_THRHD + It will produce frame end signal when receiver takes more time to receive one byte data than this register value. + 0 + 10 + read-write + + + TX_IDLE_NUM + This register is used to configure the duration time between transfers. + 10 + 10 + read-write + + + + + RS485_CONF_SYNC + RS485 mode configuration + 0x4C + 0x20 + + + RS485_EN + Set this bit to choose the rs485 mode. + 0 + 1 + read-write + + + DL0_EN + Set this bit to delay the stop bit by 1 bit. + 1 + 1 + read-write + + + DL1_EN + Set this bit to delay the stop bit by 1 bit. + 2 + 1 + read-write + + + RS485TX_RX_EN + Set this bit to enable receiver could receive data when the transmitter is transmitting data in rs485 mode. + 3 + 1 + read-write + + + RS485RXBY_TX_EN + 1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy. + 4 + 1 + read-write + + + RS485_RX_DLY_NUM + This register is used to delay the receiver's internal data signal. + 5 + 1 + read-write + + + RS485_TX_DLY_NUM + This register is used to delay the transmitter's internal data signal. + 6 + 4 + read-write + + + + + AT_CMD_PRECNT_SYNC + Pre-sequence timing configuration + 0x50 + 0x20 + 0x00000901 + + + PRE_IDLE_NUM + This register is used to configure the idle duration time before the first at_cmd is received by receiver. + 0 + 16 + read-write + + + + + AT_CMD_POSTCNT_SYNC + Post-sequence timing configuration + 0x54 + 0x20 + 0x00000901 + + + POST_IDLE_NUM + This register is used to configure the duration time between the last at_cmd and the next data. + 0 + 16 + read-write + + + + + AT_CMD_GAPTOUT_SYNC + Timeout configuration + 0x58 + 0x20 + 0x0000000B + + + RX_GAP_TOUT + This register is used to configure the duration time between the at_cmd chars. + 0 + 16 + read-write + + + + + AT_CMD_CHAR_SYNC + AT escape sequence detection configuration + 0x5C + 0x20 + 0x0000032B + + + AT_CMD_CHAR + This register is used to configure the content of at_cmd char. + 0 + 8 + read-write + + + CHAR_NUM + This register is used to configure the num of continuous at_cmd chars received by receiver. + 8 + 8 + read-write + + + + + MEM_CONF + UART memory power configuration + 0x60 + 0x20 + + + MEM_FORCE_PD + Set this bit to force power down UART memory. + 25 + 1 + read-write + + + MEM_FORCE_PU + Set this bit to force power up UART memory. + 26 + 1 + read-write + + + + + TOUT_CONF_SYNC + UART threshold and allocation configuration + 0x64 + 0x20 + 0x00000028 + + + RX_TOUT_EN + This is the enble bit for uart receiver's timeout function. + 0 + 1 + read-write + + + RX_TOUT_FLOW_DIS + Set this bit to stop accumulating idle_cnt when hardware flow control works. + 1 + 1 + read-write + + + RX_TOUT_THRHD + This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1. + 2 + 10 + read-write + + + + + MEM_TX_STATUS + Tx-SRAM write and read offset address. + 0x68 + 0x20 + + + TX_SRAM_WADDR + This register stores the offset write address in Tx-SRAM. + 0 + 8 + read-only + + + TX_SRAM_RADDR + This register stores the offset read address in Tx-SRAM. + 9 + 8 + read-only + + + + + MEM_RX_STATUS + Rx-SRAM write and read offset address. + 0x6C + 0x20 + 0x00010080 + + + RX_SRAM_RADDR + This register stores the offset read address in RX-SRAM. + 0 + 8 + read-only + + + RX_SRAM_WADDR + This register stores the offset write address in Rx-SRAM. + 9 + 8 + read-only + + + + + FSM_STATUS + UART transmit and receive status. + 0x70 + 0x20 + + + ST_URX_OUT + This is the status register of receiver. + 0 + 4 + read-only + + + ST_UTX_OUT + This is the status register of transmitter. + 4 + 4 + read-only + + + + + POSPULSE + Autobaud high pulse register + 0x74 + 0x20 + 0x00000FFF + + + POSEDGE_MIN_CNT + This register stores the minimal input clock count between two positive edges. It is used in boudrate-detect process. + 0 + 12 + read-only + + + + + NEGPULSE + Autobaud low pulse register + 0x78 + 0x20 + 0x00000FFF + + + NEGEDGE_MIN_CNT + This register stores the minimal input clock count between two negative edges. It is used in boudrate-detect process. + 0 + 12 + read-only + + + + + LOWPULSE + Autobaud minimum low pulse duration register + 0x7C + 0x20 + 0x00000FFF + + + MIN_CNT + This register stores the value of the minimum duration time of the low level pulse. It is used in baud rate-detect process. + 0 + 12 + read-only + + + + + HIGHPULSE + Autobaud minimum high pulse duration register + 0x80 + 0x20 + 0x00000FFF + + + MIN_CNT + This register stores the value of the maxinum duration time for the high level pulse. It is used in baud rate-detect process. + 0 + 12 + read-only + + + + + RXD_CNT + Autobaud edge change count register + 0x84 + 0x20 + + + RXD_EDGE_CNT + This register stores the count of rxd edge change. It is used in baud rate-detect process. + 0 + 10 + read-only + + + + + CLK_CONF + UART core clock configuration + 0x88 + 0x20 + 0x03000000 + + + TX_SCLK_EN + Set this bit to enable UART Tx clock. + 24 + 1 + read-write + + + RX_SCLK_EN + Set this bit to enable UART Rx clock. + 25 + 1 + read-write + + + TX_RST_CORE + Write 1 then write 0 to this bit to reset UART Tx. + 26 + 1 + read-write + + + RX_RST_CORE + Write 1 then write 0 to this bit to reset UART Rx. + 27 + 1 + read-write + + + + + DATE + UART Version register + 0x8C + 0x20 + 0x02305050 + + + DATE + This is the version register. + 0 + 32 + read-write + + + + + AFIFO_STATUS + UART AFIFO Status + 0x90 + 0x20 + 0x0000000A + + + TX_AFIFO_FULL + Full signal of APB TX AFIFO. + 0 + 1 + read-only + + + TX_AFIFO_EMPTY + Empty signal of APB TX AFIFO. + 1 + 1 + read-only + + + RX_AFIFO_FULL + Full signal of APB RX AFIFO. + 2 + 1 + read-only + + + RX_AFIFO_EMPTY + Empty signal of APB RX AFIFO. + 3 + 1 + read-only + + + + + REG_UPDATE + UART Registers Configuration Update register + 0x98 + 0x20 + + + REG_UPDATE + Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done. + 0 + 1 + read-write + + + + + ID + UART ID register + 0x9C + 0x20 + 0x00000500 + + + ID + This register is used to configure the uart_id. + 0 + 32 + read-write + + + + + + + UART1 + UART (Universal Asynchronous Receiver-Transmitter) Controller 1 + 0x500CB000 + + UART1 + 32 + + + + UART2 + UART (Universal Asynchronous Receiver-Transmitter) Controller 2 + 0x500CC000 + + UART2 + 33 + + + + UART3 + UART (Universal Asynchronous Receiver-Transmitter) Controller 3 + 0x500CD000 + + UART3 + 34 + + + + UART4 + UART (Universal Asynchronous Receiver-Transmitter) Controller 4 + 0x500CE000 + + UART4 + 35 + + + + UHCI0 + Universal Host Controller Interface 0 + UHCI + 0x500DF000 + + 0x0 + 0x84 + registers + + + UHCI0 + 30 + + + + CONF0 + UHCI Configuration Register0 + 0x0 + 0x20 + 0x000006E0 + + + TX_RST + Write 1 then write 0 to this bit to reset decode state machine. + 0 + 1 + read-write + + + RX_RST + Write 1 then write 0 to this bit to reset encode state machine. + 1 + 1 + read-write + + + UART_SEL + Select which uart to connect with GDMA. + 2 + 3 + read-write + + + SEPER_EN + Set this bit to separate the data frame using a special char. + 5 + 1 + read-write + + + HEAD_EN + Set this bit to encode the data packet with a formatting header. + 6 + 1 + read-write + + + CRC_REC_EN + Set this bit to enable UHCI to receive the 16 bit CRC. + 7 + 1 + read-write + + + UART_IDLE_EOF_EN + If this bit is set to 1 UHCI will end the payload receiving process when UART has been in idle state. + 8 + 1 + read-write + + + LEN_EOF_EN + If this bit is set to 1 UHCI decoder receiving payload data is end when the receiving byte count has reached the specified value. The value is payload length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0 UHCI decoder receiving payload data is end when 0xc0 is received. + 9 + 1 + read-write + + + ENCODE_CRC_EN + Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to end of the payload. + 10 + 1 + read-write + + + CLK_EN + 1'b1: Force clock on for register. 1'b0: Support clock only when application writes registers. + 11 + 1 + read-write + + + UART_RX_BRK_EOF_EN + If this bit is set to 1 UHCI will end payload receive process when NULL frame is received by UART. + 12 + 1 + read-write + + + + + INT_RAW + UHCI Interrupt Raw Register + 0x4 + 0x20 + + + RX_START_INT_RAW + Indicates the raw interrupt of UHCI_RX_START_INT. Interrupt will be triggered when delimiter is sent successfully. + 0 + 1 + read-write + + + TX_START_INT_RAW + Indicates the raw interrupt of UHCI_TX_START_INT. Interrupt will be triggered when DMA detects delimiter. + 1 + 1 + read-write + + + RX_HUNG_INT_RAW + Indicates the raw interrupt of UHCI_RX_HUNG_INT. Interrupt will be triggered when the required time of DMA receiving data exceeds the configuration value. + 2 + 1 + read-write + + + TX_HUNG_INT_RAW + Indicates the raw interrupt of UHCI_TX_HUNG_INT. Interrupt will be triggered when the required time of DMA reading RAM data exceeds the configuration value. + 3 + 1 + read-write + + + SEND_S_REG_Q_INT_RAW + Indicates the raw interrupt of UHCI_SEND_S_REG_Q_INT. Interrupt will be triggered when UHCI sends short packet successfully with single_send mode. + 4 + 1 + read-write + + + SEND_A_REG_Q_INT_RAW + Indicates the raw interrupt of UHCI_SEND_A_REG_Q_INT. Interrupt will be triggered when UHCI sends short packet successfully with always_send mode. + 5 + 1 + read-write + + + OUT_EOF_INT_RAW + Indicates the raw interrupt of UHCI_OUT_EOF_INT. Interrupt will be triggered when there are errors in EOF. + 6 + 1 + read-write + + + APP_CTRL0_INT_RAW + Indicates the raw interrupt of UHCI_APP_CTRL0_INT. Interrupt will be triggered when UHCI_APP_CTRL0_IN_SET is set to 1. + 7 + 1 + read-write + + + APP_CTRL1_INT_RAW + Indicates the raw interrupt of UHCI_APP_CTRL1_INT. Interrupt will be triggered when UHCI_APP_CTRL1_IN_SET is set to 1. + 8 + 1 + read-write + + + + + INT_ST + UHCI Interrupt Status Register + 0x8 + 0x20 + + + RX_START_INT_ST + Indicates the interrupt status of UHCI_RX_START_INT. + 0 + 1 + read-only + + + TX_START_INT_ST + Indicates the interrupt status of UHCI_TX_START_INT. + 1 + 1 + read-only + + + RX_HUNG_INT_ST + Indicates the interrupt status of UHCI_RX_HUNG_INT. + 2 + 1 + read-only + + + TX_HUNG_INT_ST + Indicates the interrupt status of UHCI_TX_HUNG_INT. + 3 + 1 + read-only + + + SEND_S_REG_Q_INT_ST + Indicates the interrupt status of UHCI_SEND_S_REG_Q_INT. + 4 + 1 + read-only + + + SEND_A_REG_Q_INT_ST + Indicates the interrupt status of UHCI_SEND_A_REG_Q_INT. + 5 + 1 + read-only + + + OUTLINK_EOF_ERR_INT_ST + Indicates the interrupt status of UHCI_OUT_EOF_INT. + 6 + 1 + read-only + + + APP_CTRL0_INT_ST + Indicates the interrupt status of UHCI_APP_CTRL0_INT. + 7 + 1 + read-only + + + APP_CTRL1_INT_ST + Indicates the interrupt status of UHCI_APP_CTRL1_INT. + 8 + 1 + read-only + + + + + INT_ENA + UHCI Interrupt Enable Register + 0xC + 0x20 + + + RX_START_INT_ENA + Set this bit to enable the interrupt of UHCI_RX_START_INT. + 0 + 1 + read-write + + + TX_START_INT_ENA + Set this bit to enable the interrupt of UHCI_TX_START_INT. + 1 + 1 + read-write + + + RX_HUNG_INT_ENA + Set this bit to enable the interrupt of UHCI_RX_HUNG_INT. + 2 + 1 + read-write + + + TX_HUNG_INT_ENA + Set this bit to enable the interrupt of UHCI_TX_HUNG_INT. + 3 + 1 + read-write + + + SEND_S_REG_Q_INT_ENA + Set this bit to enable the interrupt of UHCI_SEND_S_REG_Q_INT. + 4 + 1 + read-write + + + SEND_A_REG_Q_INT_ENA + Set this bit to enable the interrupt of UHCI_SEND_A_REG_Q_INT. + 5 + 1 + read-write + + + OUTLINK_EOF_ERR_INT_ENA + Set this bit to enable the interrupt of UHCI_OUT_EOF_INT. + 6 + 1 + read-write + + + APP_CTRL0_INT_ENA + Set this bit to enable the interrupt of UHCI_APP_CTRL0_INT. + 7 + 1 + read-write + + + APP_CTRL1_INT_ENA + Set this bit to enable the interrupt of UHCI_APP_CTRL1_INT. + 8 + 1 + read-write + + + + + INT_CLR + UHCI Interrupt Clear Register + 0x10 + 0x20 + + + RX_START_INT_CLR + Set this bit to clear the raw interrupt of UHCI_RX_START_INT. + 0 + 1 + write-only + + + TX_START_INT_CLR + Set this bit to clear the raw interrupt of UHCI_TX_START_INT. + 1 + 1 + write-only + + + RX_HUNG_INT_CLR + Set this bit to clear the raw interrupt of UHCI_RX_HUNG_INT. + 2 + 1 + write-only + + + TX_HUNG_INT_CLR + Set this bit to clear the raw interrupt of UHCI_TX_HUNG_INT. + 3 + 1 + write-only + + + SEND_S_REG_Q_INT_CLR + Set this bit to clear the raw interrupt of UHCI_SEND_S_REG_Q_INT. + 4 + 1 + write-only + + + SEND_A_REG_Q_INT_CLR + Set this bit to clear the raw interrupt of UHCI_SEND_A_REG_Q_INT. + 5 + 1 + write-only + + + OUTLINK_EOF_ERR_INT_CLR + Set this bit to clear the raw interrupt of UHCI_OUT_EOF_INT. + 6 + 1 + write-only + + + APP_CTRL0_INT_CLR + Set this bit to clear the raw interrupt of UHCI_APP_CTRL0_INT. + 7 + 1 + write-only + + + APP_CTRL1_INT_CLR + Set this bit to clear the raw interrupt of UHCI_APP_CTRL1_INT. + 8 + 1 + write-only + + + + + CONF1 + UHCI Configuration Register1 + 0x14 + 0x20 + 0x00000033 + + + CHECK_SUM_EN + Set this bit to enable head checksum check when receiving. + 0 + 1 + read-write + + + CHECK_SEQ_EN + Set this bit to enable sequence number check when receiving. + 1 + 1 + read-write + + + CRC_DISABLE + Set this bit to support CRC calculation, and data integrity check bit should 1. + 2 + 1 + read-write + + + SAVE_HEAD + Set this bit to save data packet head when UHCI receive data. + 3 + 1 + read-write + + + TX_CHECK_SUM_RE + Set this bit to encode data packet with checksum. + 4 + 1 + read-write + + + TX_ACK_NUM_RE + Set this bit to encode data packet with ACK when reliable data packet is ready. + 5 + 1 + read-write + + + WAIT_SW_START + Set this bit to enable UHCI encoder transfer to ST_SW_WAIT status. + 7 + 1 + read-write + + + SW_START + Set this bit to transmit data packet if UCHI_ENCODE_STATE is ST_SW_WAIT. + 8 + 1 + write-only + + + + + STATE0 + UHCI Receive Status Register + 0x18 + 0x20 + + + RX_ERR_CAUSE + Indicates the error types when DMA receives the error frame. 3'b001: UHCI packet checksum error. 3'b010: UHCI packet sequence number error. 3'b011: UHCI packet CRC bit error. 3'b100: find 0xC0, but received packet is uncompleted. 3'b101: 0xC0 is not found, but received packet is completed. 3'b110: CRC check error. + 0 + 3 + read-only + + + DECODE_STATE + Indicates UHCI decoder status. + 3 + 3 + read-only + + + + + STATE1 + UHCI Transmit Status Register + 0x1C + 0x20 + + + ENCODE_STATE + Indicates UHCI encoder status. + 0 + 3 + read-only + + + + + ESCAPE_CONF + UHCI Escapes Configuration Register0 + 0x20 + 0x20 + 0x00000033 + + + TX_C0_ESC_EN + Set this bit to enable resolve char 0xC0 when DMA receiving data. + 0 + 1 + read-write + + + TX_DB_ESC_EN + Set this bit to enable resolve char 0xDB when DMA receiving data. + 1 + 1 + read-write + + + TX_11_ESC_EN + Set this bit to enable resolve flow control char 0x11 when DMA receiving data. + 2 + 1 + read-write + + + TX_13_ESC_EN + Set this bit to enable resolve flow control char 0x13 when DMA receiving data. + 3 + 1 + read-write + + + RX_C0_ESC_EN + Set this bit to enable replacing 0xC0 with special char when DMA receiving data. + 4 + 1 + read-write + + + RX_DB_ESC_EN + Set this bit to enable replacing 0xDB with special char when DMA receiving data. + 5 + 1 + read-write + + + RX_11_ESC_EN + Set this bit to enable replacing 0x11 with special char when DMA receiving data. + 6 + 1 + read-write + + + RX_13_ESC_EN + Set this bit to enable replacing 0x13 with special char when DMA receiving data. + 7 + 1 + read-write + + + + + HUNG_CONF + UHCI Hung Configuration Register0 + 0x24 + 0x20 + 0x00810810 + + + TXFIFO_TIMEOUT + Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for timeout when receiving data. + 0 + 8 + read-write + + + TXFIFO_TIMEOUT_SHIFT + Configures the maximum counter value. + 8 + 3 + read-write + + + TXFIFO_TIMEOUT_ENA + Set this bit to enable TX FIFO timeout when receiving. + 11 + 1 + read-write + + + RXFIFO_TIMEOUT + Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for timeout when reading RAM data. + 12 + 8 + read-write + + + RXFIFO_TIMEOUT_SHIFT + Configures the maximum counter value. + 20 + 3 + read-write + + + RXFIFO_TIMEOUT_ENA + Set this bit to enable TX FIFO timeout when DMA sending data. + 23 + 1 + read-write + + + + + ACK_NUM + UHCI Ack Value Configuration Register0 + 0x28 + 0x20 + + + ACK_NUM + Indicates the ACK number during software flow control. + 0 + 3 + read-write + + + LOAD + Set this bit to load the ACK value of UHCI_ACK_NUM. + 3 + 1 + write-only + + + + + RX_HEAD + UHCI Head Register + 0x2C + 0x20 + + + RX_HEAD + Stores the head of received packet. + 0 + 32 + read-only + + + + + QUICK_SENT + UCHI Quick send Register + 0x30 + 0x20 + + + SINGLE_SEND_NUM + Configures single_send mode. + 0 + 3 + read-write + + + SINGLE_SEND_EN + Set this bit to enable sending short packet with single_send mode. + 3 + 1 + write-only + + + ALWAYS_SEND_NUM + Configures always_send mode. + 4 + 3 + read-write + + + ALWAYS_SEND_EN + Set this bit to enable sending short packet with always_send mode. + 7 + 1 + read-write + + + + + REG_Q0_WORD0 + UHCI Q0_WORD0 Quick Send Register + 0x34 + 0x20 + + + SEND_Q0_WORD0 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q0_WORD1 + UHCI Q0_WORD1 Quick Send Register + 0x38 + 0x20 + + + SEND_Q0_WORD1 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q1_WORD0 + UHCI Q1_WORD0 Quick Send Register + 0x3C + 0x20 + + + SEND_Q1_WORD0 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q1_WORD1 + UHCI Q1_WORD1 Quick Send Register + 0x40 + 0x20 + + + SEND_Q1_WORD1 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q2_WORD0 + UHCI Q2_WORD0 Quick Send Register + 0x44 + 0x20 + + + SEND_Q2_WORD0 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q2_WORD1 + UHCI Q2_WORD1 Quick Send Register + 0x48 + 0x20 + + + SEND_Q2_WORD1 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q3_WORD0 + UHCI Q3_WORD0 Quick Send Register + 0x4C + 0x20 + + + SEND_Q3_WORD0 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q3_WORD1 + UHCI Q3_WORD1 Quick Send Register + 0x50 + 0x20 + + + SEND_Q3_WORD1 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q4_WORD0 + UHCI Q4_WORD0 Quick Send Register + 0x54 + 0x20 + + + SEND_Q4_WORD0 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q4_WORD1 + UHCI Q4_WORD1 Quick Send Register + 0x58 + 0x20 + + + SEND_Q4_WORD1 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q5_WORD0 + UHCI Q5_WORD0 Quick Send Register + 0x5C + 0x20 + + + SEND_Q5_WORD0 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q5_WORD1 + UHCI Q5_WORD1 Quick Send Register + 0x60 + 0x20 + + + SEND_Q5_WORD1 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q6_WORD0 + UHCI Q6_WORD0 Quick Send Register + 0x64 + 0x20 + + + SEND_Q6_WORD0 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q6_WORD1 + UHCI Q6_WORD1 Quick Send Register + 0x68 + 0x20 + + + SEND_Q6_WORD1 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + ESC_CONF0 + UHCI Escapes Sequence Configuration Register0 + 0x6C + 0x20 + 0x00DCDBC0 + + + SEPER_CHAR + Configures the delimiter for encoding, default value is 0xC0. + 0 + 8 + read-write + + + SEPER_ESC_CHAR0 + Configures the first char of SLIP escape character, default value is 0xDB. + 8 + 8 + read-write + + + SEPER_ESC_CHAR1 + Configures the second char of SLIP escape character, default value is 0xDC. + 16 + 8 + read-write + + + + + ESC_CONF1 + UHCI Escapes Sequence Configuration Register1 + 0x70 + 0x20 + 0x00DDDBDB + + + ESC_SEQ0 + Configures the char needing encoding, which is 0xDB as flow control char by default. + 0 + 8 + read-write + + + ESC_SEQ0_CHAR0 + Configures the first char of SLIP escape character, default value is 0xDB. + 8 + 8 + read-write + + + ESC_SEQ0_CHAR1 + Configures the second char of SLIP escape character, default value is 0xDD. + 16 + 8 + read-write + + + + + ESC_CONF2 + UHCI Escapes Sequence Configuration Register2 + 0x74 + 0x20 + 0x00DEDB11 + + + ESC_SEQ1 + Configures the char needing encoding, which is 0x11 as flow control char by default. + 0 + 8 + read-write + + + ESC_SEQ1_CHAR0 + Configures the first char of SLIP escape character, default value is 0xDB. + 8 + 8 + read-write + + + ESC_SEQ1_CHAR1 + Configures the second char of SLIP escape character, default value is 0xDE. + 16 + 8 + read-write + + + + + ESC_CONF3 + UHCI Escapes Sequence Configuration Register3 + 0x78 + 0x20 + 0x00DFDB13 + + + ESC_SEQ2 + Configures the char needing encoding, which is 0x13 as flow control char by default. + 0 + 8 + read-write + + + ESC_SEQ2_CHAR0 + Configures the first char of SLIP escape character, default value is 0xDB. + 8 + 8 + read-write + + + ESC_SEQ2_CHAR1 + Configures the second char of SLIP escape character, default value is 0xDF. + 16 + 8 + read-write + + + + + PKT_THRES + UCHI Packet Length Configuration Register + 0x7C + 0x20 + 0x00000080 + + + PKT_THRS + Configures the data packet's maximum length when UHCI_HEAD_EN is 0. + 0 + 13 + read-write + + + + + DATE + UHCI Version Register + 0x80 + 0x20 + 0x02201100 + + + DATE + Configures version. + 0 + 32 + read-write + + + + + + + USB_DEVICE + Full-speed USB Serial/JTAG Controller + USB_DEVICE + 0x500D2000 + + 0x0 + 0x8C + registers + + + USB_DEVICE + 22 + + + + EP1 + FIFO access for the CDC-ACM data IN and OUT endpoints. + 0x0 + 0x20 + + + USB_SERIAL_JTAG_RDWR_BYTE + Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is received, then read data from UART Rx FIFO. + 0 + 8 + read-only + + + + + EP1_CONF + Configuration and control registers for the CDC-ACM FIFOs. + 0x4 + 0x20 + 0x00000002 + + + USB_SERIAL_JTAG_WR_DONE + Set this bit to indicate writing byte data to UART Tx FIFO is done. + 0 + 1 + write-only + + + USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE + 1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by USB Host. + 1 + 1 + read-only + + + USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL + 1'b1: Indicate there is data in UART Rx FIFO. + 2 + 1 + read-only + + + + + INT_RAW + Interrupt raw status register. + 0x8 + 0x20 + 0x00000008 + + + USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW + The raw interrupt bit turns to high level when flush cmd is received for IN endpoint 2 of JTAG. + 0 + 1 + read-write + + + USB_SERIAL_JTAG_SOF_INT_RAW + The raw interrupt bit turns to high level when SOF frame is received. + 1 + 1 + read-write + + + USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW + The raw interrupt bit turns to high level when Serial Port OUT Endpoint received one packet. + 2 + 1 + read-write + + + USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW + The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty. + 3 + 1 + read-write + + + USB_SERIAL_JTAG_PID_ERR_INT_RAW + The raw interrupt bit turns to high level when pid error is detected. + 4 + 1 + read-write + + + USB_SERIAL_JTAG_CRC5_ERR_INT_RAW + The raw interrupt bit turns to high level when CRC5 error is detected. + 5 + 1 + read-write + + + USB_SERIAL_JTAG_CRC16_ERR_INT_RAW + The raw interrupt bit turns to high level when CRC16 error is detected. + 6 + 1 + read-write + + + USB_SERIAL_JTAG_STUFF_ERR_INT_RAW + The raw interrupt bit turns to high level when stuff error is detected. + 7 + 1 + read-write + + + USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW + The raw interrupt bit turns to high level when IN token for IN endpoint 1 is received. + 8 + 1 + read-write + + + USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW + The raw interrupt bit turns to high level when usb bus reset is detected. + 9 + 1 + read-write + + + USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW + The raw interrupt bit turns to high level when OUT endpoint 1 received packet with zero palyload. + 10 + 1 + read-write + + + USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW + The raw interrupt bit turns to high level when OUT endpoint 2 received packet with zero palyload. + 11 + 1 + read-write + + + USB_SERIAL_JTAG_RTS_CHG_INT_RAW + The raw interrupt bit turns to high level when level of RTS from usb serial channel is changed. + 12 + 1 + read-write + + + USB_SERIAL_JTAG_DTR_CHG_INT_RAW + The raw interrupt bit turns to high level when level of DTR from usb serial channel is changed. + 13 + 1 + read-write + + + USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW + The raw interrupt bit turns to high level when level of GET LINE CODING request is received. + 14 + 1 + read-write + + + USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW + The raw interrupt bit turns to high level when level of SET LINE CODING request is received. + 15 + 1 + read-write + + + + + INT_ST + Interrupt status register. + 0xC + 0x20 + + + USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST + The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. + 0 + 1 + read-only + + + USB_SERIAL_JTAG_SOF_INT_ST + The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt. + 1 + 1 + read-only + + + USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST + The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. + 2 + 1 + read-only + + + USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST + The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. + 3 + 1 + read-only + + + USB_SERIAL_JTAG_PID_ERR_INT_ST + The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt. + 4 + 1 + read-only + + + USB_SERIAL_JTAG_CRC5_ERR_INT_ST + The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt. + 5 + 1 + read-only + + + USB_SERIAL_JTAG_CRC16_ERR_INT_ST + The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt. + 6 + 1 + read-only + + + USB_SERIAL_JTAG_STUFF_ERR_INT_ST + The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt. + 7 + 1 + read-only + + + USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST + The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt. + 8 + 1 + read-only + + + USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST + The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt. + 9 + 1 + read-only + + + USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST + The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + 10 + 1 + read-only + + + USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST + The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + 11 + 1 + read-only + + + USB_SERIAL_JTAG_RTS_CHG_INT_ST + The raw interrupt status bit for the USB_DEVICE_RTS_CHG_INT interrupt. + 12 + 1 + read-only + + + USB_SERIAL_JTAG_DTR_CHG_INT_ST + The raw interrupt status bit for the USB_DEVICE_DTR_CHG_INT interrupt. + 13 + 1 + read-only + + + USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST + The raw interrupt status bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt. + 14 + 1 + read-only + + + USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST + The raw interrupt status bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt. + 15 + 1 + read-only + + + + + INT_ENA + Interrupt enable status register. + 0x10 + 0x20 + + + USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA + The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. + 0 + 1 + read-write + + + USB_SERIAL_JTAG_SOF_INT_ENA + The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt. + 1 + 1 + read-write + + + USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA + The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. + 2 + 1 + read-write + + + USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA + The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. + 3 + 1 + read-write + + + USB_SERIAL_JTAG_PID_ERR_INT_ENA + The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt. + 4 + 1 + read-write + + + USB_SERIAL_JTAG_CRC5_ERR_INT_ENA + The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt. + 5 + 1 + read-write + + + USB_SERIAL_JTAG_CRC16_ERR_INT_ENA + The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt. + 6 + 1 + read-write + + + USB_SERIAL_JTAG_STUFF_ERR_INT_ENA + The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt. + 7 + 1 + read-write + + + USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA + The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt. + 8 + 1 + read-write + + + USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA + The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt. + 9 + 1 + read-write + + + USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA + The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + 10 + 1 + read-write + + + USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA + The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + 11 + 1 + read-write + + + USB_SERIAL_JTAG_RTS_CHG_INT_ENA + The interrupt enable bit for the USB_DEVICE_RTS_CHG_INT interrupt. + 12 + 1 + read-write + + + USB_SERIAL_JTAG_DTR_CHG_INT_ENA + The interrupt enable bit for the USB_DEVICE_DTR_CHG_INT interrupt. + 13 + 1 + read-write + + + USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA + The interrupt enable bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt. + 14 + 1 + read-write + + + USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA + The interrupt enable bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt. + 15 + 1 + read-write + + + + + INT_CLR + Interrupt clear status register. + 0x14 + 0x20 + + + USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR + Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. + 0 + 1 + write-only + + + USB_SERIAL_JTAG_SOF_INT_CLR + Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt. + 1 + 1 + write-only + + + USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR + Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. + 2 + 1 + write-only + + + USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR + Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. + 3 + 1 + write-only + + + USB_SERIAL_JTAG_PID_ERR_INT_CLR + Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt. + 4 + 1 + write-only + + + USB_SERIAL_JTAG_CRC5_ERR_INT_CLR + Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt. + 5 + 1 + write-only + + + USB_SERIAL_JTAG_CRC16_ERR_INT_CLR + Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt. + 6 + 1 + write-only + + + USB_SERIAL_JTAG_STUFF_ERR_INT_CLR + Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt. + 7 + 1 + write-only + + + USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR + Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt. + 8 + 1 + write-only + + + USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR + Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt. + 9 + 1 + write-only + + + USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR + Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + 10 + 1 + write-only + + + USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR + Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + 11 + 1 + write-only + + + USB_SERIAL_JTAG_RTS_CHG_INT_CLR + Set this bit to clear the USB_DEVICE_RTS_CHG_INT interrupt. + 12 + 1 + write-only + + + USB_SERIAL_JTAG_DTR_CHG_INT_CLR + Set this bit to clear the USB_DEVICE_DTR_CHG_INT interrupt. + 13 + 1 + write-only + + + USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR + Set this bit to clear the USB_DEVICE_GET_LINE_CODE_INT interrupt. + 14 + 1 + write-only + + + USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR + Set this bit to clear the USB_DEVICE_SET_LINE_CODE_INT interrupt. + 15 + 1 + write-only + + + + + CONF0 + PHY hardware configuration. + 0x18 + 0x20 + 0x00004200 + + + USB_SERIAL_JTAG_PHY_SEL + Select internal/external PHY + 0 + 1 + read-write + + + USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE + Enable software control USB D+ D- exchange + 1 + 1 + read-write + + + USB_SERIAL_JTAG_EXCHG_PINS + USB D+ D- exchange + 2 + 1 + read-write + + + USB_SERIAL_JTAG_VREFH + Control single-end input high threshold,1.76V to 2V, step 80mV + 3 + 2 + read-write + + + USB_SERIAL_JTAG_VREFL + Control single-end input low threshold,0.8V to 1.04V, step 80mV + 5 + 2 + read-write + + + USB_SERIAL_JTAG_VREF_OVERRIDE + Enable software control input threshold + 7 + 1 + read-write + + + USB_SERIAL_JTAG_PAD_PULL_OVERRIDE + Enable software control USB D+ D- pullup pulldown + 8 + 1 + read-write + + + USB_SERIAL_JTAG_DP_PULLUP + Control USB D+ pull up. + 9 + 1 + read-write + + + USB_SERIAL_JTAG_DP_PULLDOWN + Control USB D+ pull down. + 10 + 1 + read-write + + + USB_SERIAL_JTAG_DM_PULLUP + Control USB D- pull up. + 11 + 1 + read-write + + + USB_SERIAL_JTAG_DM_PULLDOWN + Control USB D- pull down. + 12 + 1 + read-write + + + USB_SERIAL_JTAG_PULLUP_VALUE + Control pull up value. + 13 + 1 + read-write + + + USB_SERIAL_JTAG_USB_PAD_ENABLE + Enable USB pad function. + 14 + 1 + read-write + + + USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN + Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input through GPIO Matrix. + 15 + 1 + read-write + + + + + TEST + Registers used for debugging the PHY. + 0x1C + 0x20 + 0x00000030 + + + USB_SERIAL_JTAG_TEST_ENABLE + Enable test of the USB pad + 0 + 1 + read-write + + + USB_SERIAL_JTAG_TEST_USB_OE + USB pad oen in test + 1 + 1 + read-write + + + USB_SERIAL_JTAG_TEST_TX_DP + USB D+ tx value in test + 2 + 1 + read-write + + + USB_SERIAL_JTAG_TEST_TX_DM + USB D- tx value in test + 3 + 1 + read-write + + + USB_SERIAL_JTAG_TEST_RX_RCV + USB RCV value in test + 4 + 1 + read-only + + + USB_SERIAL_JTAG_TEST_RX_DP + USB D+ rx value in test + 5 + 1 + read-only + + + USB_SERIAL_JTAG_TEST_RX_DM + USB D- rx value in test + 6 + 1 + read-only + + + + + JFIFO_ST + JTAG FIFO status and control registers. + 0x20 + 0x20 + 0x00000044 + + + USB_SERIAL_JTAG_IN_FIFO_CNT + JTAT in fifo counter. + 0 + 2 + read-only + + + USB_SERIAL_JTAG_IN_FIFO_EMPTY + 1: JTAG in fifo is empty. + 2 + 1 + read-only + + + USB_SERIAL_JTAG_IN_FIFO_FULL + 1: JTAG in fifo is full. + 3 + 1 + read-only + + + USB_SERIAL_JTAG_OUT_FIFO_CNT + JTAT out fifo counter. + 4 + 2 + read-only + + + USB_SERIAL_JTAG_OUT_FIFO_EMPTY + 1: JTAG out fifo is empty. + 6 + 1 + read-only + + + USB_SERIAL_JTAG_OUT_FIFO_FULL + 1: JTAG out fifo is full. + 7 + 1 + read-only + + + USB_SERIAL_JTAG_IN_FIFO_RESET + Write 1 to reset JTAG in fifo. + 8 + 1 + read-write + + + USB_SERIAL_JTAG_OUT_FIFO_RESET + Write 1 to reset JTAG out fifo. + 9 + 1 + read-write + + + + + FRAM_NUM + Last received SOF frame index register. + 0x24 + 0x20 + + + USB_SERIAL_JTAG_SOF_FRAME_INDEX + Frame index of received SOF frame. + 0 + 11 + read-only + + + + + IN_EP0_ST + Control IN endpoint status information. + 0x28 + 0x20 + 0x00000001 + + + USB_SERIAL_JTAG_IN_EP0_STATE + State of IN Endpoint 0. + 0 + 2 + read-only + + + USB_SERIAL_JTAG_IN_EP0_WR_ADDR + Write data address of IN endpoint 0. + 2 + 7 + read-only + + + USB_SERIAL_JTAG_IN_EP0_RD_ADDR + Read data address of IN endpoint 0. + 9 + 7 + read-only + + + + + IN_EP1_ST + CDC-ACM IN endpoint status information. + 0x2C + 0x20 + 0x00000001 + + + USB_SERIAL_JTAG_IN_EP1_STATE + State of IN Endpoint 1. + 0 + 2 + read-only + + + USB_SERIAL_JTAG_IN_EP1_WR_ADDR + Write data address of IN endpoint 1. + 2 + 7 + read-only + + + USB_SERIAL_JTAG_IN_EP1_RD_ADDR + Read data address of IN endpoint 1. + 9 + 7 + read-only + + + + + IN_EP2_ST + CDC-ACM interrupt IN endpoint status information. + 0x30 + 0x20 + 0x00000001 + + + USB_SERIAL_JTAG_IN_EP2_STATE + State of IN Endpoint 2. + 0 + 2 + read-only + + + USB_SERIAL_JTAG_IN_EP2_WR_ADDR + Write data address of IN endpoint 2. + 2 + 7 + read-only + + + USB_SERIAL_JTAG_IN_EP2_RD_ADDR + Read data address of IN endpoint 2. + 9 + 7 + read-only + + + + + IN_EP3_ST + JTAG IN endpoint status information. + 0x34 + 0x20 + 0x00000001 + + + USB_SERIAL_JTAG_IN_EP3_STATE + State of IN Endpoint 3. + 0 + 2 + read-only + + + USB_SERIAL_JTAG_IN_EP3_WR_ADDR + Write data address of IN endpoint 3. + 2 + 7 + read-only + + + USB_SERIAL_JTAG_IN_EP3_RD_ADDR + Read data address of IN endpoint 3. + 9 + 7 + read-only + + + + + OUT_EP0_ST + Control OUT endpoint status information. + 0x38 + 0x20 + + + USB_SERIAL_JTAG_OUT_EP0_STATE + State of OUT Endpoint 0. + 0 + 2 + read-only + + + USB_SERIAL_JTAG_OUT_EP0_WR_ADDR + Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0. + 2 + 7 + read-only + + + USB_SERIAL_JTAG_OUT_EP0_RD_ADDR + Read data address of OUT endpoint 0. + 9 + 7 + read-only + + + + + OUT_EP1_ST + CDC-ACM OUT endpoint status information. + 0x3C + 0x20 + + + USB_SERIAL_JTAG_OUT_EP1_STATE + State of OUT Endpoint 1. + 0 + 2 + read-only + + + USB_SERIAL_JTAG_OUT_EP1_WR_ADDR + Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1. + 2 + 7 + read-only + + + USB_SERIAL_JTAG_OUT_EP1_RD_ADDR + Read data address of OUT endpoint 1. + 9 + 7 + read-only + + + USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT + Data count in OUT endpoint 1 when one packet is received. + 16 + 7 + read-only + + + + + OUT_EP2_ST + JTAG OUT endpoint status information. + 0x40 + 0x20 + + + USB_SERIAL_JTAG_OUT_EP2_STATE + State of OUT Endpoint 2. + 0 + 2 + read-only + + + USB_SERIAL_JTAG_OUT_EP2_WR_ADDR + Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2. + 2 + 7 + read-only + + + USB_SERIAL_JTAG_OUT_EP2_RD_ADDR + Read data address of OUT endpoint 2. + 9 + 7 + read-only + + + + + MISC_CONF + Clock enable control + 0x44 + 0x20 + + + USB_SERIAL_JTAG_CLK_EN + 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers. + 0 + 1 + read-write + + + + + MEM_CONF + Memory power control + 0x48 + 0x20 + 0x00000002 + + + USB_SERIAL_JTAG_USB_MEM_PD + 1: power down usb memory. + 0 + 1 + read-write + + + USB_SERIAL_JTAG_USB_MEM_CLK_EN + 1: Force clock on for usb memory. + 1 + 1 + read-write + + + + + CHIP_RST + CDC-ACM chip reset control. + 0x4C + 0x20 + + + USB_SERIAL_JTAG_RTS + 1: Chip reset is detected from usb serial channel. Software write 1 to clear it. + 0 + 1 + read-only + + + USB_SERIAL_JTAG_DTR + 1: Chip reset is detected from usb jtag channel. Software write 1 to clear it. + 1 + 1 + read-only + + + USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS + Set this bit to disable chip reset from usb serial channel to reset chip. + 2 + 1 + read-write + + + + + SET_LINE_CODE_W0 + W0 of SET_LINE_CODING command. + 0x50 + 0x20 + + + USB_SERIAL_JTAG_DW_DTE_RATE + The value of dwDTERate set by host through SET_LINE_CODING command. + 0 + 32 + read-only + + + + + SET_LINE_CODE_W1 + W1 of SET_LINE_CODING command. + 0x54 + 0x20 + + + USB_SERIAL_JTAG_BCHAR_FORMAT + The value of bCharFormat set by host through SET_LINE_CODING command. + 0 + 8 + read-only + + + USB_SERIAL_JTAG_BPARITY_TYPE + The value of bParityTpye set by host through SET_LINE_CODING command. + 8 + 8 + read-only + + + USB_SERIAL_JTAG_BDATA_BITS + The value of bDataBits set by host through SET_LINE_CODING command. + 16 + 8 + read-only + + + + + GET_LINE_CODE_W0 + W0 of GET_LINE_CODING command. + 0x58 + 0x20 + + + USB_SERIAL_JTAG_GET_DW_DTE_RATE + The value of dwDTERate set by software which is requested by GET_LINE_CODING command. + 0 + 32 + read-write + + + + + GET_LINE_CODE_W1 + W1 of GET_LINE_CODING command. + 0x5C + 0x20 + + + USB_SERIAL_JTAG_GET_BDATA_BITS + The value of bCharFormat set by software which is requested by GET_LINE_CODING command. + 0 + 8 + read-write + + + USB_SERIAL_JTAG_GET_BPARITY_TYPE + The value of bParityTpye set by software which is requested by GET_LINE_CODING command. + 8 + 8 + read-write + + + USB_SERIAL_JTAG_GET_BCHAR_FORMAT + The value of bDataBits set by software which is requested by GET_LINE_CODING command. + 16 + 8 + read-write + + + + + CONFIG_UPDATE + Configuration registers' value update + 0x60 + 0x20 + + + USB_SERIAL_JTAG_CONFIG_UPDATE + Write 1 to this register would update the value of configure registers from APB clock domain to 48MHz clock domain. + 0 + 1 + write-only + + + + + SER_AFIFO_CONFIG + Serial AFIFO configure register + 0x64 + 0x20 + 0x00000010 + + + USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR + Write 1 to reset CDC_ACM IN async FIFO write clock domain. + 0 + 1 + read-write + + + USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD + Write 1 to reset CDC_ACM IN async FIFO read clock domain. + 1 + 1 + read-write + + + USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR + Write 1 to reset CDC_ACM OUT async FIFO write clock domain. + 2 + 1 + read-write + + + USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD + Write 1 to reset CDC_ACM OUT async FIFO read clock domain. + 3 + 1 + read-write + + + USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY + CDC_ACM OUTOUT async FIFO empty signal in read clock domain. + 4 + 1 + read-only + + + USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL + CDC_ACM OUT IN async FIFO empty signal in write clock domain. + 5 + 1 + read-only + + + + + BUS_RESET_ST + USB Bus reset status register + 0x68 + 0x20 + 0x00000001 + + + USB_SERIAL_JTAG_USB_BUS_RESET_ST + USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset status. 1: USB bus reset is released. + 0 + 1 + read-only + + + + + ECO_LOW_48 + Reserved. + 0x6C + 0x20 + + + USB_SERIAL_JTAG_RND_ECO_LOW_48 + Reserved. + 0 + 32 + read-write + + + + + ECO_HIGH_48 + Reserved. + 0x70 + 0x20 + 0xFFFFFFFF + + + USB_SERIAL_JTAG_RND_ECO_HIGH_48 + Reserved. + 0 + 32 + read-write + + + + + ECO_CELL_CTRL_48 + Reserved. + 0x74 + 0x20 + + + USB_SERIAL_JTAG_RDN_RESULT_48 + Reserved. + 0 + 1 + read-only + + + USB_SERIAL_JTAG_RDN_ENA_48 + Reserved. + 1 + 1 + read-write + + + + + ECO_LOW_APB + Reserved. + 0x78 + 0x20 + + + USB_SERIAL_JTAG_RND_ECO_LOW_APB + Reserved. + 0 + 32 + read-write + + + + + ECO_HIGH_APB + Reserved. + 0x7C + 0x20 + 0xFFFFFFFF + + + USB_SERIAL_JTAG_RND_ECO_HIGH_APB + Reserved. + 0 + 32 + read-write + + + + + ECO_CELL_CTRL_APB + Reserved. + 0x80 + 0x20 + + + USB_SERIAL_JTAG_RDN_RESULT_APB + Reserved. + 0 + 1 + read-only + + + USB_SERIAL_JTAG_RDN_ENA_APB + Reserved. + 1 + 1 + read-write + + + + + SRAM_CTRL + PPA SRAM Control Register + 0x84 + 0x20 + 0x00001320 + + + USB_SERIAL_JTAG_MEM_AUX_CTRL + Control signals + 0 + 14 + read-write + + + + + DATE + Date register + 0x88 + 0x20 + 0x02112010 + + + USB_SERIAL_JTAG_DATE + register version. + 0 + 32 + read-write + + + + + + + USB_WRAP + USB_WRAP Peripheral + USB_WRAP + 0x50080000 + + 0x0 + 0xC + registers + + + + OTG_CONF + USB wrapper configuration registers. + 0x0 + 0x20 + 0x00100000 + + + SRP_SESSEND_OVERRIDE + This bit is used to enable the software over-ride of srp session end signal. 1'b0: the signal is controlled by the chip input, 1'b1: the signal is controlled by the software. + 0 + 1 + read-write + + + SRP_SESSEND_VALUE + Software over-ride value of srp session end signal. + 1 + 1 + read-write + + + PHY_SEL + Select internal external PHY. 1'b0: Select internal PHY, 1'b1: Select external PHY. + 2 + 1 + read-write + + + DFIFO_FORCE_PD + Force the dfifo to go into low power mode. The data in dfifo will not lost. + 3 + 1 + read-write + + + DBNCE_FLTR_BYPASS + Bypass Debounce filters for avalid,bvalid,vbusvalid,session end, id signals + 4 + 1 + read-write + + + EXCHG_PINS_OVERRIDE + Enable software controlle USB D+ D- exchange + 5 + 1 + read-write + + + EXCHG_PINS + USB D+ D- exchange. 1'b0: don't change, 1'b1: exchange D+ D-. + 6 + 1 + read-write + + + VREFH + Control single-end input high threshold,1.76V to 2V, step 80mV. + 7 + 2 + read-write + + + VREFL + Control single-end input low threshold,0.8V to 1.04V, step 80mV. + 9 + 2 + read-write + + + VREF_OVERRIDE + Enable software controlle input threshold. + 11 + 1 + read-write + + + PAD_PULL_OVERRIDE + Enable software controlle USB D+ D- pullup pulldown. + 12 + 1 + read-write + + + DP_PULLUP + Controlle USB D+ pullup. + 13 + 1 + read-write + + + DP_PULLDOWN + Controlle USB D+ pulldown. + 14 + 1 + read-write + + + DM_PULLUP + Controlle USB D+ pullup. + 15 + 1 + read-write + + + DM_PULLDOWN + Controlle USB D+ pulldown. + 16 + 1 + read-write + + + PULLUP_VALUE + Controlle pullup value. 1'b0: typical value is 2.4K, 1'b1: typical value is 1.2K. + 17 + 1 + read-write + + + USB_PAD_ENABLE + Enable USB pad function. + 18 + 1 + read-write + + + AHB_CLK_FORCE_ON + Force ahb clock always on. + 19 + 1 + read-write + + + PHY_CLK_FORCE_ON + Force phy clock always on. + 20 + 1 + read-write + + + PHY_TX_EDGE_SEL + Select phy tx signal output clock edge. 1'b0: negedge, 1'b1: posedge. + 21 + 1 + read-write + + + DFIFO_FORCE_PU + Disable the dfifo to go into low power mode. The data in dfifo will not lost. + 22 + 1 + read-write + + + CLK_EN + Disable auto clock gating of CSR registers. + 31 + 1 + read-write + + + + + TEST_CONF + USB wrapper test configuration registers. + 0x4 + 0x20 + + + TEST_ENABLE + Enable test of the USB pad. + 0 + 1 + read-write + + + TEST_USB_OE + USB pad oen in test. + 1 + 1 + read-write + + + TEST_TX_DP + USB D+ tx value in test. + 2 + 1 + read-write + + + TEST_TX_DM + USB D- tx value in test. + 3 + 1 + read-write + + + TEST_RX_RCV + USB differential rx value in test. + 4 + 1 + read-only + + + TEST_RX_DP + USB D+ rx value in test. + 5 + 1 + read-only + + + TEST_RX_DM + USB D- rx value in test. + 6 + 1 + read-only + + + + + DATE + Date register. + 0x3FC + 0x20 + 0x23030504 + + + USB_WRAP_DATE + Date register. + 0 + 32 + read-only + + + + + + + \ No newline at end of file diff --git a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/gpio.c b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/gpio.c new file mode 100644 index 000000000..4e65a4cff --- /dev/null +++ b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/gpio.c @@ -0,0 +1,148 @@ +/****************************************************************************************** + Filename : gpio.c + + Core : RISC-V + + MCU : ESP32-P4 + + Author : Chalandi Amine + + Owner : Chalandi Amine + + Date : 25.01.2026 + + Description : GPIO driver implementation + +******************************************************************************************/ + +//----------------------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------------------- +#include "gpio.h" + + +//----------------------------------------------------------------------------------------- +// Types +//----------------------------------------------------------------------------------------- + +typedef union { + volatile uint32_t reg; + + struct { + volatile uint32_t MCU_OE : 1; + volatile uint32_t SLP_SEL : 1; + volatile uint32_t MCU_WPD : 1; + volatile uint32_t MCU_WPU : 1; + volatile uint32_t MCU_IE : 1; + volatile uint32_t MCU_DRV : 2; + volatile uint32_t FUN_WPD : 1; + volatile uint32_t FUN_WPU : 1; + volatile uint32_t FUN_IE : 1; + volatile uint32_t FUN_DRV : 2; + volatile uint32_t MCU_SEL : 3; + volatile uint32_t FILTER_EN : 1; + uint32_t : 16; + } bit; +} IO_MUX_GPIO; + +typedef union { + __IOM uint32_t reg; + + struct { + __IOM uint32_t OUT_SEL : 9; + __IOM uint32_t INV_SEL : 1; + __IOM uint32_t OEN_SEL : 1; + __IOM uint32_t OEN_INV_SEL : 1; + uint32_t : 20; + } bit; +} GPIO_FUNC_OUT_SEL_CFG; + +typedef union { + __IOM uint32_t reg; + + struct { + __IOM uint32_t REG_PAD_DRV : 2; + __IOM uint32_t REG_PAD_RDE : 1; + __IOM uint32_t REG_PAD_RUE : 1; + __IOM uint32_t REG_PAD_MUX_SEL : 1; + __IOM uint32_t REG_PAD_FUN_SEL : 2; + __IOM uint32_t REG_PAD_SLP_SEL : 1; + __IOM uint32_t REG_PAD_SLP_IE : 1; + __IOM uint32_t REG_PAD_SLP_OE : 1; + __IOM uint32_t REG_PAD_FUN_IE : 1; + __IOM uint32_t REG_PAD_FILTER_EN : 1; + uint32_t : 20; + } bit; +} LP_IO_MUX_GPIO; + +//----------------------------------------------------------------------------------------- +/// \brief +/// +/// \param +/// +/// \return +//----------------------------------------------------------------------------------------- +void gpio_cfg_output(uint8_t pin) +{ + if(pin > 54) + return; + + volatile IO_MUX_GPIO* pIO_MUX_GPIO = (volatile IO_MUX_GPIO*)(IO_MUX_BASE + 4ul + 4ul*pin); + volatile GPIO_FUNC_OUT_SEL_CFG* pGPIO_FUNC_OUT_SEL_CFG = (volatile GPIO_FUNC_OUT_SEL_CFG*)(GPIO_BASE + 0x558ul + 4ul*pin); + volatile LP_IO_MUX_GPIO* pLP_IO_MUX_GPIO = (volatile LP_IO_MUX_GPIO*)(LP_IO_MUX_BASE + 8ul + 4ul*pin); + volatile uint32_t* pGPIO_OUTx_W1TC = (volatile uint32_t*)(GPIO_BASE + ((pin < 32u) ? (0x0Cul) : (0x18ul))); + volatile uint32_t* pGPIO_ENABLE1x_W1TS = (volatile uint32_t*)(GPIO_BASE + ((pin < 32u) ? (0x24ul) : (0x30ul))); + + /* configure the pinmux */ + pIO_MUX_GPIO->bit.FUN_DRV = 2; + pIO_MUX_GPIO->bit.FUN_IE = 0; + pIO_MUX_GPIO->bit.MCU_SEL = 1; + + /* set the output configuration */ + pGPIO_FUNC_OUT_SEL_CFG->bit.OUT_SEL = 256; + pGPIO_FUNC_OUT_SEL_CFG->bit.OEN_SEL = 1; + + if(pin < 16) + { + /* make LP_GPIO use HP_IO_MUX */ + pLP_IO_MUX_GPIO->bit.REG_PAD_MUX_SEL = 0; + } + + /* drive the IO output low */ + *pGPIO_OUTx_W1TC = (uint32_t)(1ul << ((pin < 32ul) ? (pin) : (pin - 32ul))); + *pGPIO_ENABLE1x_W1TS = (uint32_t)(1ul << ((pin < 32ul) ? (pin) : (pin - 32ul))); +} + +//----------------------------------------------------------------------------------------- +/// \brief +/// +/// \param +/// +/// \return +//----------------------------------------------------------------------------------------- +void gpio_set_output_level(uint8_t pin, uint8_t level) +{ + volatile uint32_t* pGPIO_OUT_W1Tx = (volatile uint32_t*)(GPIO_BASE + ((pin < 32u) ? (8ul) : (0x14ul)) + ((level == 1u) ? (0ul) : (4ul))); + + if((pin > 54) && (level > 1)) + return; + + *pGPIO_OUT_W1Tx = (uint32_t)(1ul << ((pin < 32ul) ? (pin) : (pin - 32ul))); +} + +//----------------------------------------------------------------------------------------- +/// \brief +/// +/// \param +/// +/// \return +//----------------------------------------------------------------------------------------- +void gpio_toggle_output_level(uint8_t pin) +{ + volatile uint32_t* pGPIO_OUT = (volatile uint32_t*)(GPIO_BASE + 4ul + ((pin < 32u) ? 0ul : 0xcul)); + + if(pin > 54) + return; + + *pGPIO_OUT ^= (uint32_t)(1ul << ((pin < 32u) ? (pin) : (pin - 32u))); +} \ No newline at end of file diff --git a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/gpio.h b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/gpio.h new file mode 100644 index 000000000..7cc4b305a --- /dev/null +++ b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/gpio.h @@ -0,0 +1,31 @@ +/****************************************************************************************** + Filename : gpio.h + + Core : RISC-V + + MCU : ESP32-P4 + + Author : Chalandi Amine + + Owner : Chalandi Amine + + Date : 25.01.2026 + + Description : GPIO driver header file + +******************************************************************************************/ +#ifndef __GPIO_H__ +#define __GPIO_H__ +//----------------------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------------------- +#include +#include +#include "esp32p4.h" + + +void gpio_cfg_output(uint8_t pin); +void gpio_set_output_level(uint8_t pin, uint8_t level); +void gpio_toggle_output_level(uint8_t pin); + +#endif /*__GPIO_H__*/ diff --git a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/interrupt.h b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/interrupt.h new file mode 100644 index 000000000..05df0841a --- /dev/null +++ b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/interrupt.h @@ -0,0 +1,85 @@ +/****************************************************************************************** + Filename : interrrupt.h + + Core : RISC-V + + MCU : ESP32-P4 + + Author : Chalandi Amine + + Owner : Chalandi Amine + + Date : 25.01.2026 + + Description : CLIC and CLINT register definition file + +******************************************************************************************/ + +#ifndef __INTERRUPT_H__ +#define __INTERRUPT_H__ + +#include + +typedef struct { + + uint8_t clicintip; /* Interrupt pending register */ + uint8_t clicintie; /* Interrupt enable register */ + uint8_t clicintattr; /* Interrupt attribute register */ + uint8_t clicintct; /* Interrupt level control register*/ +}clicint_t; + +typedef struct { + + uint32_t mcliccfg; /* CLIC machine mode global configuration register */ + uint32_t clicinfo; /* CLIC information register */ + uint32_t mintthresh; /* CLIC machine mode interrupt threshold register */ + clicint_t interrupt[48] __attribute__((aligned(0x1000))); /* CLIC interrupt configuration registers */ +}clic_t; + +#define CLIC_BASE 0x20800000ul +#define CLIC ((volatile clic_t*)(CLIC_BASE)) + +#define CLINT_BASE 0x20000000ul +#define CLINT_MTIMECMP (*(volatile uint64_t*)(CLINT_BASE + 0x4000ul)) +#define CLINT_MTIMELOAD (*(volatile uint64_t*)(CLINT_BASE + 0x4008ul)) +#define CLINT_MTIMECTL (*(volatile uint32_t*)(CLINT_BASE + 0x4010ul)) +#define CLINT_MTIME (*(volatile uint64_t*)(CLINT_BASE + 0xBFF8ul)) + + +#define INT_SW_ID 3 +#define INT_TIMER_ID 7 +#define EXT_INT00_ID 16 +#define EXT_INT01_ID 17 +#define EXT_INT02_ID 18 +#define EXT_INT03_ID 19 +#define EXT_INT04_ID 20 +#define EXT_INT05_ID 21 +#define EXT_INT06_ID 22 +#define EXT_INT07_ID 23 +#define EXT_INT08_ID 24 +#define EXT_INT09_ID 25 +#define EXT_INT10_ID 26 +#define EXT_INT11_ID 27 +#define EXT_INT12_ID 28 +#define EXT_INT13_ID 29 +#define EXT_INT14_ID 30 +#define EXT_INT15_ID 31 +#define EXT_INT16_ID 32 +#define EXT_INT17_ID 33 +#define EXT_INT18_ID 34 +#define EXT_INT19_ID 35 +#define EXT_INT20_ID 36 +#define EXT_INT21_ID 37 +#define EXT_INT22_ID 38 +#define EXT_INT23_ID 39 +#define EXT_INT24_ID 40 +#define EXT_INT25_ID 41 +#define EXT_INT26_ID 42 +#define EXT_INT27_ID 43 +#define EXT_INT28_ID 44 +#define EXT_INT29_ID 45 +#define EXT_INT30_ID 46 +#define EXT_INT31_ID 47 + + +#endif /* __INTERRUPT_H__ */ diff --git a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/riscv-csr.h b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/riscv-csr.h new file mode 100644 index 000000000..bdbc31b8d --- /dev/null +++ b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/riscv-csr.h @@ -0,0 +1,3791 @@ +/* + Register access functions for RISC-V system registers. + SPDX-License-Identifier: Unlicense + + https://five-embeddev.com/ + +*/ + +#ifndef RISCV_CSR_H +#define RISCV_CSR_H + +#include + +#if __riscv_xlen==32 +typedef uint32_t uint_xlen_t; +typedef uint32_t uint_csr32_t; +typedef uint32_t uint_csr64_t; +#elif __riscv_xlen==64 +typedef uint64_t uint_xlen_t; +typedef uint32_t uint_csr32_t; +typedef uint64_t uint_csr64_t; +#else +#error "Unknown XLEN" +#endif + +// Test for Zicsr extension, if relevant +#if defined(__riscv_arch_test) +#if !defined(__riscv_zicsr) +#error "-march must include zicsr to access CSRs" +#endif +#endif + +/******************************************* + * misa - MRW - Machine ISA + */ +static inline uint_xlen_t csr_read_misa(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, misa" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_misa(uint_xlen_t value) { + __asm__ volatile ("csrw misa, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_misa(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, misa, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * mvendorid - MRO - Machine Vendor ID + */ +static inline uint32_t csr_read_mvendorid(void) { + uint_csr32_t value; + __asm__ volatile ("csrr %0, mvendorid" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} + +/******************************************* + * marchid - MRO - Machine Architecture ID + */ +static inline uint_xlen_t csr_read_marchid(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, marchid" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} + +/******************************************* + * mimpid - MRO - Machine Implementation ID + */ +static inline uint_xlen_t csr_read_mimpid(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, mimpid" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} + +/******************************************* + * mhartid - MRO - Hardware Thread ID + */ +static inline uint_xlen_t csr_read_mhartid(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, mhartid" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} + +/******************************************* + * mstatus - MRW - Machine Status + */ +static inline uint_xlen_t csr_read_mstatus(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, mstatus" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_mstatus(uint_xlen_t value) { + __asm__ volatile ("csrw mstatus, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_mstatus(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, mstatus, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} +/* Register CSR bit set and clear instructions */ +static inline void csr_set_bits_mstatus(uint_xlen_t mask) { + __asm__ volatile ("csrrs zero, mstatus, %0" + : /* output: none */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); +} +static inline void csr_clr_bits_mstatus(uint_xlen_t mask) { + __asm__ volatile ("csrrc zero, mstatus, %0" + : /* output: none */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_set_bits_mstatus(uint_xlen_t mask) { + uint_xlen_t value; + __asm__ volatile ("csrrs %0, mstatus, %1" + : "=r" (value) /* output: register %0 */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); + return value; +} +static inline uint_xlen_t csr_read_clr_bits_mstatus(uint_xlen_t mask) { + uint_xlen_t value; + __asm__ volatile ("csrrc %0, mstatus, %1" + : "=r" (value) /* output: register %0 */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); + return value; +} +/* mstatus, CSR write value via immediate value (only up to 5 bits) */ +#define CSR_WRITE_IMM_MSTATUS(VALUE) \ + __asm__ volatile ("csrrwi zero, mstatus, %0" \ + : /* output: none */ \ + : "i" (VALUE) /* input : immediate */ \ + : /* clobbers: none */) + +/* mstatus, CSR set bits via immediate value mask (only up to 5 bits) */ +#define CSR_SET_BITS_IMM_MSTATUS(MASK) \ + __asm__ volatile ("csrrsi zero, mstatus, %0" \ + : /* output: none */ \ + : "i" (MASK) /* input : immediate */ \ + : /* clobbers: none */) + +/* mstatus, CSR clear bits via immediate value mask (only up to 5 bits) */ +#define CSR_CLR_BITS_IMM_MSTATUS(MASK) \ + __asm__ volatile ("csrrci zero, mstatus, %0" \ + : /* output: none */ \ + : "i" (MASK) /* input : immediate */ \ + : /* clobbers: none */) +#define MSTATUS_MIE_BIT_OFFSET 3 +#define MSTATUS_MIE_BIT_WIDTH 1 +#define MSTATUS_MIE_BIT_MASK 0x8 +#define MSTATUS_MIE_ALL_SET_MASK 0x1 +#define MSTATUS_SIE_BIT_OFFSET 2 +#define MSTATUS_SIE_BIT_WIDTH 1 +#define MSTATUS_SIE_BIT_MASK 0x4 +#define MSTATUS_SIE_ALL_SET_MASK 0x1 +#define MSTATUS_MPIE_BIT_OFFSET 7 +#define MSTATUS_MPIE_BIT_WIDTH 1 +#define MSTATUS_MPIE_BIT_MASK 0x80 +#define MSTATUS_MPIE_ALL_SET_MASK 0x1 +#define MSTATUS_SPIE_BIT_OFFSET 5 +#define MSTATUS_SPIE_BIT_WIDTH 1 +#define MSTATUS_SPIE_BIT_MASK 0x20 +#define MSTATUS_SPIE_ALL_SET_MASK 0x1 +#define MSTATUS_MPRV_BIT_OFFSET 17 +#define MSTATUS_MPRV_BIT_WIDTH 1 +#define MSTATUS_MPRV_BIT_MASK 0x20000 +#define MSTATUS_MPRV_ALL_SET_MASK 0x1 +#define MSTATUS_MPP_BIT_OFFSET 11 +#define MSTATUS_MPP_BIT_WIDTH 2 +#define MSTATUS_MPP_BIT_MASK 0x1800 +#define MSTATUS_MPP_ALL_SET_MASK 0x3 +#define MSTATUS_SPP_BIT_OFFSET 8 +#define MSTATUS_SPP_BIT_WIDTH 1 +#define MSTATUS_SPP_BIT_MASK 0x100 +#define MSTATUS_SPP_ALL_SET_MASK 0x1 + +/******************************************* + * mstatush - MRW - Additional machine status register, RV32 only. + */ +static inline uint_xlen_t csr_read_mstatush(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, mstatush" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_mstatush(uint_xlen_t value) { + __asm__ volatile ("csrw mstatush, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_mstatush(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, mstatush, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * mtvec - MRW - Machine Trap Vector Base Address + */ +static inline uint_xlen_t csr_read_mtvec(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, mtvec" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_mtvec(uint_xlen_t value) { + __asm__ volatile ("csrw mtvec, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_mtvec(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, mtvec, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} +/* Register CSR bit set and clear instructions */ +static inline void csr_set_bits_mtvec(uint_xlen_t mask) { + __asm__ volatile ("csrrs zero, mtvec, %0" + : /* output: none */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); +} +static inline void csr_clr_bits_mtvec(uint_xlen_t mask) { + __asm__ volatile ("csrrc zero, mtvec, %0" + : /* output: none */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_set_bits_mtvec(uint_xlen_t mask) { + uint_xlen_t value; + __asm__ volatile ("csrrs %0, mtvec, %1" + : "=r" (value) /* output: register %0 */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); + return value; +} +static inline uint_xlen_t csr_read_clr_bits_mtvec(uint_xlen_t mask) { + uint_xlen_t value; + __asm__ volatile ("csrrc %0, mtvec, %1" + : "=r" (value) /* output: register %0 */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); + return value; +} +/* mtvec, CSR write value via immediate value (only up to 5 bits) */ +#define CSR_WRITE_IMM_MTVEC(VALUE) \ + __asm__ volatile ("csrrwi zero, mtvec, %0" \ + : /* output: none */ \ + : "i" (VALUE) /* input : immediate */ \ + : /* clobbers: none */) + +/* mtvec, CSR set bits via immediate value mask (only up to 5 bits) */ +#define CSR_SET_BITS_IMM_MTVEC(MASK) \ + __asm__ volatile ("csrrsi zero, mtvec, %0" \ + : /* output: none */ \ + : "i" (MASK) /* input : immediate */ \ + : /* clobbers: none */) + +/* mtvec, CSR clear bits via immediate value mask (only up to 5 bits) */ +#define CSR_CLR_BITS_IMM_MTVEC(MASK) \ + __asm__ volatile ("csrrci zero, mtvec, %0" \ + : /* output: none */ \ + : "i" (MASK) /* input : immediate */ \ + : /* clobbers: none */) +#define MTVEC_BASE_BIT_OFFSET 2 +#define MTVEC_BASE_BIT_WIDTH ((__riscv_xlen-1)-(2) + 1) +#define MTVEC_BASE_BIT_MASK ((1UL<<(((__riscv_xlen-1)-(2) + 1)-1)) << (2)) +#define MTVEC_BASE_ALL_SET_MASK ((1UL<<(((__riscv_xlen-1)-(2) + 1)-1)) << (0)) +#define MTVEC_MODE_BIT_OFFSET 0 +#define MTVEC_MODE_BIT_WIDTH 2 +#define MTVEC_MODE_BIT_MASK 0x3 +#define MTVEC_MODE_ALL_SET_MASK 0x3 + +/******************************************* + * medeleg - MRW - Machine Exception Delegation + */ +static inline uint_xlen_t csr_read_medeleg(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, medeleg" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_medeleg(uint_xlen_t value) { + __asm__ volatile ("csrw medeleg, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_medeleg(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, medeleg, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * mideleg - MRW - Machine Interrupt Delegation + */ +static inline uint_xlen_t csr_read_mideleg(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, mideleg" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_mideleg(uint_xlen_t value) { + __asm__ volatile ("csrw mideleg, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_mideleg(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, mideleg, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * mip - MRW - Machine Interrupt Pending + */ +static inline uint_xlen_t csr_read_mip(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, mip" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_mip(uint_xlen_t value) { + __asm__ volatile ("csrw mip, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_mip(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, mip, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} +/* Register CSR bit set and clear instructions */ +static inline void csr_set_bits_mip(uint_xlen_t mask) { + __asm__ volatile ("csrrs zero, mip, %0" + : /* output: none */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); +} +static inline void csr_clr_bits_mip(uint_xlen_t mask) { + __asm__ volatile ("csrrc zero, mip, %0" + : /* output: none */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_set_bits_mip(uint_xlen_t mask) { + uint_xlen_t value; + __asm__ volatile ("csrrs %0, mip, %1" + : "=r" (value) /* output: register %0 */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); + return value; +} +static inline uint_xlen_t csr_read_clr_bits_mip(uint_xlen_t mask) { + uint_xlen_t value; + __asm__ volatile ("csrrc %0, mip, %1" + : "=r" (value) /* output: register %0 */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); + return value; +} +/* mip, CSR write value via immediate value (only up to 5 bits) */ +#define CSR_WRITE_IMM_MIP(VALUE) \ + __asm__ volatile ("csrrwi zero, mip, %0" \ + : /* output: none */ \ + : "i" (VALUE) /* input : immediate */ \ + : /* clobbers: none */) + +/* mip, CSR set bits via immediate value mask (only up to 5 bits) */ +#define CSR_SET_BITS_IMM_MIP(MASK) \ + __asm__ volatile ("csrrsi zero, mip, %0" \ + : /* output: none */ \ + : "i" (MASK) /* input : immediate */ \ + : /* clobbers: none */) + +/* mip, CSR clear bits via immediate value mask (only up to 5 bits) */ +#define CSR_CLR_BITS_IMM_MIP(MASK) \ + __asm__ volatile ("csrrci zero, mip, %0" \ + : /* output: none */ \ + : "i" (MASK) /* input : immediate */ \ + : /* clobbers: none */) +#define MIP_MSI_BIT_OFFSET 3 +#define MIP_MSI_BIT_WIDTH 1 +#define MIP_MSI_BIT_MASK 0x8 +#define MIP_MSI_ALL_SET_MASK 0x1 +#define MIP_MTI_BIT_OFFSET 7 +#define MIP_MTI_BIT_WIDTH 1 +#define MIP_MTI_BIT_MASK 0x80 +#define MIP_MTI_ALL_SET_MASK 0x1 +#define MIP_MEI_BIT_OFFSET 11 +#define MIP_MEI_BIT_WIDTH 1 +#define MIP_MEI_BIT_MASK 0x800 +#define MIP_MEI_ALL_SET_MASK 0x1 +#define MIP_SSI_BIT_OFFSET 1 +#define MIP_SSI_BIT_WIDTH 1 +#define MIP_SSI_BIT_MASK 0x2 +#define MIP_SSI_ALL_SET_MASK 0x1 +#define MIP_STI_BIT_OFFSET 5 +#define MIP_STI_BIT_WIDTH 1 +#define MIP_STI_BIT_MASK 0x20 +#define MIP_STI_ALL_SET_MASK 0x1 +#define MIP_SEI_BIT_OFFSET 9 +#define MIP_SEI_BIT_WIDTH 1 +#define MIP_SEI_BIT_MASK 0x200 +#define MIP_SEI_ALL_SET_MASK 0x1 +#define MIP_USI_BIT_OFFSET 0 +#define MIP_USI_BIT_WIDTH 1 +#define MIP_USI_BIT_MASK 0x1 +#define MIP_USI_ALL_SET_MASK 0x1 +#define MIP_UTI_BIT_OFFSET 4 +#define MIP_UTI_BIT_WIDTH 1 +#define MIP_UTI_BIT_MASK 0x10 +#define MIP_UTI_ALL_SET_MASK 0x1 +#define MIP_UEI_BIT_OFFSET 8 +#define MIP_UEI_BIT_WIDTH 1 +#define MIP_UEI_BIT_MASK 0x100 +#define MIP_UEI_ALL_SET_MASK 0x1 +#define MIP_PLATFORM_DEFINED_BIT_OFFSET 16 +#define MIP_PLATFORM_DEFINED_BIT_WIDTH ((__riscv_xlen)-(16) + 1) +#define MIP_PLATFORM_DEFINED_BIT_MASK ((1UL<<(((__riscv_xlen)-(16) + 1)-1)) << (16)) +#define MIP_PLATFORM_DEFINED_ALL_SET_MASK ((1UL<<(((__riscv_xlen)-(16) + 1)-1)) << (0)) + +/******************************************* + * mie - MRW - Machine Interrupt Enable + */ +static inline uint_xlen_t csr_read_mie(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, mie" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_mie(uint_xlen_t value) { + __asm__ volatile ("csrw mie, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_mie(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, mie, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} +/* Register CSR bit set and clear instructions */ +static inline void csr_set_bits_mie(uint_xlen_t mask) { + __asm__ volatile ("csrrs zero, mie, %0" + : /* output: none */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); +} +static inline void csr_clr_bits_mie(uint_xlen_t mask) { + __asm__ volatile ("csrrc zero, mie, %0" + : /* output: none */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_set_bits_mie(uint_xlen_t mask) { + uint_xlen_t value; + __asm__ volatile ("csrrs %0, mie, %1" + : "=r" (value) /* output: register %0 */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); + return value; +} +static inline uint_xlen_t csr_read_clr_bits_mie(uint_xlen_t mask) { + uint_xlen_t value; + __asm__ volatile ("csrrc %0, mie, %1" + : "=r" (value) /* output: register %0 */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); + return value; +} +/* mie, CSR write value via immediate value (only up to 5 bits) */ +#define CSR_WRITE_IMM_MIE(VALUE) \ + __asm__ volatile ("csrrwi zero, mie, %0" \ + : /* output: none */ \ + : "i" (VALUE) /* input : immediate */ \ + : /* clobbers: none */) + +/* mie, CSR set bits via immediate value mask (only up to 5 bits) */ +#define CSR_SET_BITS_IMM_MIE(MASK) \ + __asm__ volatile ("csrrsi zero, mie, %0" \ + : /* output: none */ \ + : "i" (MASK) /* input : immediate */ \ + : /* clobbers: none */) + +/* mie, CSR clear bits via immediate value mask (only up to 5 bits) */ +#define CSR_CLR_BITS_IMM_MIE(MASK) \ + __asm__ volatile ("csrrci zero, mie, %0" \ + : /* output: none */ \ + : "i" (MASK) /* input : immediate */ \ + : /* clobbers: none */) +#define MIE_MSI_BIT_OFFSET 3 +#define MIE_MSI_BIT_WIDTH 1 +#define MIE_MSI_BIT_MASK 0x8 +#define MIE_MSI_ALL_SET_MASK 0x1 +#define MIE_MTI_BIT_OFFSET 7 +#define MIE_MTI_BIT_WIDTH 1 +#define MIE_MTI_BIT_MASK 0x80 +#define MIE_MTI_ALL_SET_MASK 0x1 +#define MIE_MEI_BIT_OFFSET 11 +#define MIE_MEI_BIT_WIDTH 1 +#define MIE_MEI_BIT_MASK 0x800 +#define MIE_MEI_ALL_SET_MASK 0x1 +#define MIE_SSI_BIT_OFFSET 1 +#define MIE_SSI_BIT_WIDTH 1 +#define MIE_SSI_BIT_MASK 0x2 +#define MIE_SSI_ALL_SET_MASK 0x1 +#define MIE_STI_BIT_OFFSET 5 +#define MIE_STI_BIT_WIDTH 1 +#define MIE_STI_BIT_MASK 0x20 +#define MIE_STI_ALL_SET_MASK 0x1 +#define MIE_SEI_BIT_OFFSET 9 +#define MIE_SEI_BIT_WIDTH 1 +#define MIE_SEI_BIT_MASK 0x200 +#define MIE_SEI_ALL_SET_MASK 0x1 +#define MIE_USI_BIT_OFFSET 0 +#define MIE_USI_BIT_WIDTH 1 +#define MIE_USI_BIT_MASK 0x1 +#define MIE_USI_ALL_SET_MASK 0x1 +#define MIE_UTI_BIT_OFFSET 4 +#define MIE_UTI_BIT_WIDTH 1 +#define MIE_UTI_BIT_MASK 0x10 +#define MIE_UTI_ALL_SET_MASK 0x1 +#define MIE_UEI_BIT_OFFSET 8 +#define MIE_UEI_BIT_WIDTH 1 +#define MIE_UEI_BIT_MASK 0x100 +#define MIE_UEI_ALL_SET_MASK 0x1 +#define MIE_PLATFORM_DEFINED_BIT_OFFSET 16 +#define MIE_PLATFORM_DEFINED_BIT_WIDTH ((__riscv_xlen)-(16) + 1) +#define MIE_PLATFORM_DEFINED_BIT_MASK ((1UL<<(((__riscv_xlen)-(16) + 1)-1)) << (16)) +#define MIE_PLATFORM_DEFINED_ALL_SET_MASK ((1UL<<(((__riscv_xlen)-(16) + 1)-1)) << (0)) + +/******************************************* + * mcountinhibit - MRW - Machine Counter Inhibit + */ +static inline uint32_t csr_read_mcountinhibit(void) { + uint_csr32_t value; + __asm__ volatile ("csrr %0, mcountinhibit" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_mcountinhibit(uint_csr32_t value) { + __asm__ volatile ("csrw mcountinhibit, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint32_t csr_read_write_mcountinhibit(uint32_t new_value) { + uint_csr32_t prev_value; + __asm__ volatile ("csrrw %0, mcountinhibit, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} +/* Register CSR bit set and clear instructions */ +static inline void csr_set_bits_mcountinhibit(uint32_t mask) { + __asm__ volatile ("csrrs zero, mcountinhibit, %0" + : /* output: none */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); +} +static inline void csr_clr_bits_mcountinhibit(uint32_t mask) { + __asm__ volatile ("csrrc zero, mcountinhibit, %0" + : /* output: none */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); +} +static inline uint32_t csr_read_set_bits_mcountinhibit(uint32_t mask) { + uint_csr32_t value; + __asm__ volatile ("csrrs %0, mcountinhibit, %1" + : "=r" (value) /* output: register %0 */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); + return value; +} +static inline uint32_t csr_read_clr_bits_mcountinhibit(uint32_t mask) { + uint_csr32_t value; + __asm__ volatile ("csrrc %0, mcountinhibit, %1" + : "=r" (value) /* output: register %0 */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); + return value; +} +/* mcountinhibit, CSR write value via immediate value (only up to 5 bits) */ +#define CSR_WRITE_IMM_MCOUNTINHIBIT(VALUE) \ + __asm__ volatile ("csrrwi zero, mcountinhibit, %0" \ + : /* output: none */ \ + : "i" (VALUE) /* input : immediate */ \ + : /* clobbers: none */) + +/* mcountinhibit, CSR set bits via immediate value mask (only up to 5 bits) */ +#define CSR_SET_BITS_IMM_MCOUNTINHIBIT(MASK) \ + __asm__ volatile ("csrrsi zero, mcountinhibit, %0" \ + : /* output: none */ \ + : "i" (MASK) /* input : immediate */ \ + : /* clobbers: none */) + +/* mcountinhibit, CSR clear bits via immediate value mask (only up to 5 bits) */ +#define CSR_CLR_BITS_IMM_MCOUNTINHIBIT(MASK) \ + __asm__ volatile ("csrrci zero, mcountinhibit, %0" \ + : /* output: none */ \ + : "i" (MASK) /* input : immediate */ \ + : /* clobbers: none */) +#define MCOUNTINHIBIT_CY_BIT_OFFSET 0 +#define MCOUNTINHIBIT_CY_BIT_WIDTH 1 +#define MCOUNTINHIBIT_CY_BIT_MASK 0x1 +#define MCOUNTINHIBIT_CY_ALL_SET_MASK 0x1 +#define MCOUNTINHIBIT_IR_BIT_OFFSET 2 +#define MCOUNTINHIBIT_IR_BIT_WIDTH 1 +#define MCOUNTINHIBIT_IR_BIT_MASK 0x4 +#define MCOUNTINHIBIT_IR_ALL_SET_MASK 0x1 +#define MCOUNTINHIBIT_HPM_BIT_OFFSET 3 +#define MCOUNTINHIBIT_HPM_BIT_WIDTH 29 +#define MCOUNTINHIBIT_HPM_BIT_MASK 0xfffffff8 +#define MCOUNTINHIBIT_HPM_ALL_SET_MASK 0x1fffffff + +/******************************************* + * mcycle - MRW - Clock Cycles Executed Counter + */ +static inline uint64_t csr_read_mcycle(void) { + uint_csr64_t value; + __asm__ volatile ("csrr %0, mcycle" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_mcycle(uint_csr64_t value) { + __asm__ volatile ("csrw mcycle, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint64_t csr_read_write_mcycle(uint64_t new_value) { + uint_csr64_t prev_value; + __asm__ volatile ("csrrw %0, mcycle, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * minstret - MRW - Number of Instructions Retired Counter + */ +static inline uint64_t csr_read_minstret(void) { + uint_csr64_t value; + __asm__ volatile ("csrr %0, minstret" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_minstret(uint_csr64_t value) { + __asm__ volatile ("csrw minstret, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint64_t csr_read_write_minstret(uint64_t new_value) { + uint_csr64_t prev_value; + __asm__ volatile ("csrrw %0, minstret, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * mhpmcounter3 - MRW - Event Counters + */ +static inline uint64_t csr_read_mhpmcounter3(void) { + uint_csr64_t value; + __asm__ volatile ("csrr %0, mhpmcounter3" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_mhpmcounter3(uint_csr64_t value) { + __asm__ volatile ("csrw mhpmcounter3, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint64_t csr_read_write_mhpmcounter3(uint64_t new_value) { + uint_csr64_t prev_value; + __asm__ volatile ("csrrw %0, mhpmcounter3, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * mhpmevent3 - MRW - Event Counter Event Select + */ +static inline uint_xlen_t csr_read_mhpmevent3(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, mhpmevent3" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_mhpmevent3(uint_xlen_t value) { + __asm__ volatile ("csrw mhpmevent3, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_mhpmevent3(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, mhpmevent3, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * mcounteren - MRW - Counter Enable + */ +static inline uint32_t csr_read_mcounteren(void) { + uint_csr32_t value; + __asm__ volatile ("csrr %0, mcounteren" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_mcounteren(uint_csr32_t value) { + __asm__ volatile ("csrw mcounteren, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint32_t csr_read_write_mcounteren(uint32_t new_value) { + uint_csr32_t prev_value; + __asm__ volatile ("csrrw %0, mcounteren, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} +/* Register CSR bit set and clear instructions */ +static inline void csr_set_bits_mcounteren(uint32_t mask) { + __asm__ volatile ("csrrs zero, mcounteren, %0" + : /* output: none */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); +} +static inline void csr_clr_bits_mcounteren(uint32_t mask) { + __asm__ volatile ("csrrc zero, mcounteren, %0" + : /* output: none */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); +} +static inline uint32_t csr_read_set_bits_mcounteren(uint32_t mask) { + uint_csr32_t value; + __asm__ volatile ("csrrs %0, mcounteren, %1" + : "=r" (value) /* output: register %0 */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); + return value; +} +static inline uint32_t csr_read_clr_bits_mcounteren(uint32_t mask) { + uint_csr32_t value; + __asm__ volatile ("csrrc %0, mcounteren, %1" + : "=r" (value) /* output: register %0 */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); + return value; +} +/* mcounteren, CSR write value via immediate value (only up to 5 bits) */ +#define CSR_WRITE_IMM_MCOUNTEREN(VALUE) \ + __asm__ volatile ("csrrwi zero, mcounteren, %0" \ + : /* output: none */ \ + : "i" (VALUE) /* input : immediate */ \ + : /* clobbers: none */) + +/* mcounteren, CSR set bits via immediate value mask (only up to 5 bits) */ +#define CSR_SET_BITS_IMM_MCOUNTEREN(MASK) \ + __asm__ volatile ("csrrsi zero, mcounteren, %0" \ + : /* output: none */ \ + : "i" (MASK) /* input : immediate */ \ + : /* clobbers: none */) + +/* mcounteren, CSR clear bits via immediate value mask (only up to 5 bits) */ +#define CSR_CLR_BITS_IMM_MCOUNTEREN(MASK) \ + __asm__ volatile ("csrrci zero, mcounteren, %0" \ + : /* output: none */ \ + : "i" (MASK) /* input : immediate */ \ + : /* clobbers: none */) +#define MCOUNTEREN_CY_BIT_OFFSET 0 +#define MCOUNTEREN_CY_BIT_WIDTH 1 +#define MCOUNTEREN_CY_BIT_MASK 0x1 +#define MCOUNTEREN_CY_ALL_SET_MASK 0x1 +#define MCOUNTEREN_TM_BIT_OFFSET 1 +#define MCOUNTEREN_TM_BIT_WIDTH 1 +#define MCOUNTEREN_TM_BIT_MASK 0x2 +#define MCOUNTEREN_TM_ALL_SET_MASK 0x1 +#define MCOUNTEREN_IR_BIT_OFFSET 2 +#define MCOUNTEREN_IR_BIT_WIDTH 1 +#define MCOUNTEREN_IR_BIT_MASK 0x4 +#define MCOUNTEREN_IR_ALL_SET_MASK 0x1 +#define MCOUNTEREN_HPM_BIT_OFFSET 3 +#define MCOUNTEREN_HPM_BIT_WIDTH 29 +#define MCOUNTEREN_HPM_BIT_MASK 0xfffffff8 +#define MCOUNTEREN_HPM_ALL_SET_MASK 0x1fffffff + +/******************************************* + * scounteren - SRW - Counter Enable + */ +static inline uint_xlen_t csr_read_scounteren(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, scounteren" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_scounteren(uint_xlen_t value) { + __asm__ volatile ("csrw scounteren, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_scounteren(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, scounteren, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * mscratch - MRW - Machine Mode Scratch Register + */ +static inline uint_xlen_t csr_read_mscratch(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, mscratch" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_mscratch(uint_xlen_t value) { + __asm__ volatile ("csrw mscratch, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_mscratch(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, mscratch, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * mepc - MRW - Machine Exception Program Counter + */ +static inline uint_xlen_t csr_read_mepc(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, mepc" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_mepc(uint_xlen_t value) { + __asm__ volatile ("csrw mepc, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_mepc(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, mepc, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * mcause - MRW - Machine Exception Cause + */ +static inline uint_xlen_t csr_read_mcause(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, mcause" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_mcause(uint_xlen_t value) { + __asm__ volatile ("csrw mcause, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_mcause(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, mcause, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} +/* Register CSR bit set and clear instructions */ +static inline void csr_set_bits_mcause(uint_xlen_t mask) { + __asm__ volatile ("csrrs zero, mcause, %0" + : /* output: none */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); +} +static inline void csr_clr_bits_mcause(uint_xlen_t mask) { + __asm__ volatile ("csrrc zero, mcause, %0" + : /* output: none */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_set_bits_mcause(uint_xlen_t mask) { + uint_xlen_t value; + __asm__ volatile ("csrrs %0, mcause, %1" + : "=r" (value) /* output: register %0 */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); + return value; +} +static inline uint_xlen_t csr_read_clr_bits_mcause(uint_xlen_t mask) { + uint_xlen_t value; + __asm__ volatile ("csrrc %0, mcause, %1" + : "=r" (value) /* output: register %0 */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); + return value; +} +/* mcause, CSR write value via immediate value (only up to 5 bits) */ +#define CSR_WRITE_IMM_MCAUSE(VALUE) \ + __asm__ volatile ("csrrwi zero, mcause, %0" \ + : /* output: none */ \ + : "i" (VALUE) /* input : immediate */ \ + : /* clobbers: none */) + +/* mcause, CSR set bits via immediate value mask (only up to 5 bits) */ +#define CSR_SET_BITS_IMM_MCAUSE(MASK) \ + __asm__ volatile ("csrrsi zero, mcause, %0" \ + : /* output: none */ \ + : "i" (MASK) /* input : immediate */ \ + : /* clobbers: none */) + +/* mcause, CSR clear bits via immediate value mask (only up to 5 bits) */ +#define CSR_CLR_BITS_IMM_MCAUSE(MASK) \ + __asm__ volatile ("csrrci zero, mcause, %0" \ + : /* output: none */ \ + : "i" (MASK) /* input : immediate */ \ + : /* clobbers: none */) +#define MCAUSE_INTERRUPT_BIT_OFFSET (__riscv_xlen-1) +#define MCAUSE_INTERRUPT_BIT_WIDTH 1 +#define MCAUSE_INTERRUPT_BIT_MASK (0x1UL << ((__riscv_xlen-1))) +#define MCAUSE_INTERRUPT_ALL_SET_MASK 0x1 +#define MCAUSE_EXCEPTION_CODE_BIT_OFFSET 0 +#define MCAUSE_EXCEPTION_CODE_BIT_WIDTH ((__riscv_xlen-2)-(0) + 1) +#define MCAUSE_EXCEPTION_CODE_BIT_MASK ((1UL<<(((__riscv_xlen-2)-(0) + 1)-1)) << (0)) +#define MCAUSE_EXCEPTION_CODE_ALL_SET_MASK ((1UL<<(((__riscv_xlen-2)-(0) + 1)-1)) << (0)) + +/******************************************* + * mtval - MRW - Machine Trap Value + */ +static inline uint_xlen_t csr_read_mtval(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, mtval" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_mtval(uint_xlen_t value) { + __asm__ volatile ("csrw mtval, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_mtval(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, mtval, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * sscratch - SRW - Supervisor Mode Scratch Register + */ +static inline uint_xlen_t csr_read_sscratch(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, sscratch" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_sscratch(uint_xlen_t value) { + __asm__ volatile ("csrw sscratch, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_sscratch(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, sscratch, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * sepc - SRW - Supervisor Exception Program Counter + */ +static inline uint_xlen_t csr_read_sepc(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, sepc" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_sepc(uint_xlen_t value) { + __asm__ volatile ("csrw sepc, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_sepc(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, sepc, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * scause - SRW - Supervisor Exception Cause + */ +static inline uint_xlen_t csr_read_scause(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, scause" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_scause(uint_xlen_t value) { + __asm__ volatile ("csrw scause, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_scause(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, scause, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} +/* Register CSR bit set and clear instructions */ +static inline void csr_set_bits_scause(uint_xlen_t mask) { + __asm__ volatile ("csrrs zero, scause, %0" + : /* output: none */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); +} +static inline void csr_clr_bits_scause(uint_xlen_t mask) { + __asm__ volatile ("csrrc zero, scause, %0" + : /* output: none */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_set_bits_scause(uint_xlen_t mask) { + uint_xlen_t value; + __asm__ volatile ("csrrs %0, scause, %1" + : "=r" (value) /* output: register %0 */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); + return value; +} +static inline uint_xlen_t csr_read_clr_bits_scause(uint_xlen_t mask) { + uint_xlen_t value; + __asm__ volatile ("csrrc %0, scause, %1" + : "=r" (value) /* output: register %0 */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); + return value; +} +/* scause, CSR write value via immediate value (only up to 5 bits) */ +#define CSR_WRITE_IMM_SCAUSE(VALUE) \ + __asm__ volatile ("csrrwi zero, scause, %0" \ + : /* output: none */ \ + : "i" (VALUE) /* input : immediate */ \ + : /* clobbers: none */) + +/* scause, CSR set bits via immediate value mask (only up to 5 bits) */ +#define CSR_SET_BITS_IMM_SCAUSE(MASK) \ + __asm__ volatile ("csrrsi zero, scause, %0" \ + : /* output: none */ \ + : "i" (MASK) /* input : immediate */ \ + : /* clobbers: none */) + +/* scause, CSR clear bits via immediate value mask (only up to 5 bits) */ +#define CSR_CLR_BITS_IMM_SCAUSE(MASK) \ + __asm__ volatile ("csrrci zero, scause, %0" \ + : /* output: none */ \ + : "i" (MASK) /* input : immediate */ \ + : /* clobbers: none */) +#define SCAUSE_INTERRUPT_BIT_OFFSET (__riscv_xlen-1) +#define SCAUSE_INTERRUPT_BIT_WIDTH 1 +#define SCAUSE_INTERRUPT_BIT_MASK (0x1UL << ((__riscv_xlen-1))) +#define SCAUSE_INTERRUPT_ALL_SET_MASK 0x1 +#define SCAUSE_EXCEPTION_CODE_BIT_OFFSET 0 +#define SCAUSE_EXCEPTION_CODE_BIT_WIDTH ((__riscv_xlen-2)-(0) + 1) +#define SCAUSE_EXCEPTION_CODE_BIT_MASK ((1UL<<(((__riscv_xlen-2)-(0) + 1)-1)) << (0)) +#define SCAUSE_EXCEPTION_CODE_ALL_SET_MASK ((1UL<<(((__riscv_xlen-2)-(0) + 1)-1)) << (0)) + +/******************************************* + * sstatus - SRW - Supervisor Status + */ +static inline uint_xlen_t csr_read_sstatus(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, sstatus" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_sstatus(uint_xlen_t value) { + __asm__ volatile ("csrw sstatus, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_sstatus(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, sstatus, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} +/* Register CSR bit set and clear instructions */ +static inline void csr_set_bits_sstatus(uint_xlen_t mask) { + __asm__ volatile ("csrrs zero, sstatus, %0" + : /* output: none */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); +} +static inline void csr_clr_bits_sstatus(uint_xlen_t mask) { + __asm__ volatile ("csrrc zero, sstatus, %0" + : /* output: none */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_set_bits_sstatus(uint_xlen_t mask) { + uint_xlen_t value; + __asm__ volatile ("csrrs %0, sstatus, %1" + : "=r" (value) /* output: register %0 */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); + return value; +} +static inline uint_xlen_t csr_read_clr_bits_sstatus(uint_xlen_t mask) { + uint_xlen_t value; + __asm__ volatile ("csrrc %0, sstatus, %1" + : "=r" (value) /* output: register %0 */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); + return value; +} +/* sstatus, CSR write value via immediate value (only up to 5 bits) */ +#define CSR_WRITE_IMM_SSTATUS(VALUE) \ + __asm__ volatile ("csrrwi zero, sstatus, %0" \ + : /* output: none */ \ + : "i" (VALUE) /* input : immediate */ \ + : /* clobbers: none */) + +/* sstatus, CSR set bits via immediate value mask (only up to 5 bits) */ +#define CSR_SET_BITS_IMM_SSTATUS(MASK) \ + __asm__ volatile ("csrrsi zero, sstatus, %0" \ + : /* output: none */ \ + : "i" (MASK) /* input : immediate */ \ + : /* clobbers: none */) + +/* sstatus, CSR clear bits via immediate value mask (only up to 5 bits) */ +#define CSR_CLR_BITS_IMM_SSTATUS(MASK) \ + __asm__ volatile ("csrrci zero, sstatus, %0" \ + : /* output: none */ \ + : "i" (MASK) /* input : immediate */ \ + : /* clobbers: none */) +#define SSTATUS_SIE_BIT_OFFSET 2 +#define SSTATUS_SIE_BIT_WIDTH 1 +#define SSTATUS_SIE_BIT_MASK 0x4 +#define SSTATUS_SIE_ALL_SET_MASK 0x1 +#define SSTATUS_SPIE_BIT_OFFSET 5 +#define SSTATUS_SPIE_BIT_WIDTH 1 +#define SSTATUS_SPIE_BIT_MASK 0x20 +#define SSTATUS_SPIE_ALL_SET_MASK 0x1 +#define SSTATUS_SPP_BIT_OFFSET 8 +#define SSTATUS_SPP_BIT_WIDTH 1 +#define SSTATUS_SPP_BIT_MASK 0x100 +#define SSTATUS_SPP_ALL_SET_MASK 0x1 + +/******************************************* + * stvec - SRW - Supervisor Trap Vector Base Address + */ +static inline uint_xlen_t csr_read_stvec(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, stvec" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_stvec(uint_xlen_t value) { + __asm__ volatile ("csrw stvec, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_stvec(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, stvec, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} +/* Register CSR bit set and clear instructions */ +static inline void csr_set_bits_stvec(uint_xlen_t mask) { + __asm__ volatile ("csrrs zero, stvec, %0" + : /* output: none */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); +} +static inline void csr_clr_bits_stvec(uint_xlen_t mask) { + __asm__ volatile ("csrrc zero, stvec, %0" + : /* output: none */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_set_bits_stvec(uint_xlen_t mask) { + uint_xlen_t value; + __asm__ volatile ("csrrs %0, stvec, %1" + : "=r" (value) /* output: register %0 */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); + return value; +} +static inline uint_xlen_t csr_read_clr_bits_stvec(uint_xlen_t mask) { + uint_xlen_t value; + __asm__ volatile ("csrrc %0, stvec, %1" + : "=r" (value) /* output: register %0 */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); + return value; +} +/* stvec, CSR write value via immediate value (only up to 5 bits) */ +#define CSR_WRITE_IMM_STVEC(VALUE) \ + __asm__ volatile ("csrrwi zero, stvec, %0" \ + : /* output: none */ \ + : "i" (VALUE) /* input : immediate */ \ + : /* clobbers: none */) + +/* stvec, CSR set bits via immediate value mask (only up to 5 bits) */ +#define CSR_SET_BITS_IMM_STVEC(MASK) \ + __asm__ volatile ("csrrsi zero, stvec, %0" \ + : /* output: none */ \ + : "i" (MASK) /* input : immediate */ \ + : /* clobbers: none */) + +/* stvec, CSR clear bits via immediate value mask (only up to 5 bits) */ +#define CSR_CLR_BITS_IMM_STVEC(MASK) \ + __asm__ volatile ("csrrci zero, stvec, %0" \ + : /* output: none */ \ + : "i" (MASK) /* input : immediate */ \ + : /* clobbers: none */) +#define STVEC_BASE_BIT_OFFSET 2 +#define STVEC_BASE_BIT_WIDTH ((__riscv_xlen-1)-(2) + 1) +#define STVEC_BASE_BIT_MASK ((1UL<<(((__riscv_xlen-1)-(2) + 1)-1)) << (2)) +#define STVEC_BASE_ALL_SET_MASK ((1UL<<(((__riscv_xlen-1)-(2) + 1)-1)) << (0)) +#define STVEC_MODE_BIT_OFFSET 0 +#define STVEC_MODE_BIT_WIDTH 2 +#define STVEC_MODE_BIT_MASK 0x3 +#define STVEC_MODE_ALL_SET_MASK 0x3 + +/******************************************* + * sideleg - SRW - Supervisor Interrupt Delegation + */ +static inline uint_xlen_t csr_read_sideleg(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, sideleg" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_sideleg(uint_xlen_t value) { + __asm__ volatile ("csrw sideleg, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_sideleg(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, sideleg, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * sedeleg - SRW - Supervisor Exception Delegation + */ +static inline uint_xlen_t csr_read_sedeleg(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, sedeleg" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_sedeleg(uint_xlen_t value) { + __asm__ volatile ("csrw sedeleg, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_sedeleg(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, sedeleg, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * sip - SRW - Supervisor Interrupt Pending + */ +static inline uint_xlen_t csr_read_sip(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, sip" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_sip(uint_xlen_t value) { + __asm__ volatile ("csrw sip, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_sip(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, sip, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} +/* Register CSR bit set and clear instructions */ +static inline void csr_set_bits_sip(uint_xlen_t mask) { + __asm__ volatile ("csrrs zero, sip, %0" + : /* output: none */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); +} +static inline void csr_clr_bits_sip(uint_xlen_t mask) { + __asm__ volatile ("csrrc zero, sip, %0" + : /* output: none */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_set_bits_sip(uint_xlen_t mask) { + uint_xlen_t value; + __asm__ volatile ("csrrs %0, sip, %1" + : "=r" (value) /* output: register %0 */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); + return value; +} +static inline uint_xlen_t csr_read_clr_bits_sip(uint_xlen_t mask) { + uint_xlen_t value; + __asm__ volatile ("csrrc %0, sip, %1" + : "=r" (value) /* output: register %0 */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); + return value; +} +/* sip, CSR write value via immediate value (only up to 5 bits) */ +#define CSR_WRITE_IMM_SIP(VALUE) \ + __asm__ volatile ("csrrwi zero, sip, %0" \ + : /* output: none */ \ + : "i" (VALUE) /* input : immediate */ \ + : /* clobbers: none */) + +/* sip, CSR set bits via immediate value mask (only up to 5 bits) */ +#define CSR_SET_BITS_IMM_SIP(MASK) \ + __asm__ volatile ("csrrsi zero, sip, %0" \ + : /* output: none */ \ + : "i" (MASK) /* input : immediate */ \ + : /* clobbers: none */) + +/* sip, CSR clear bits via immediate value mask (only up to 5 bits) */ +#define CSR_CLR_BITS_IMM_SIP(MASK) \ + __asm__ volatile ("csrrci zero, sip, %0" \ + : /* output: none */ \ + : "i" (MASK) /* input : immediate */ \ + : /* clobbers: none */) +#define SIP_SSI_BIT_OFFSET 1 +#define SIP_SSI_BIT_WIDTH 1 +#define SIP_SSI_BIT_MASK 0x2 +#define SIP_SSI_ALL_SET_MASK 0x1 +#define SIP_STI_BIT_OFFSET 5 +#define SIP_STI_BIT_WIDTH 1 +#define SIP_STI_BIT_MASK 0x20 +#define SIP_STI_ALL_SET_MASK 0x1 +#define SIP_SEI_BIT_OFFSET 9 +#define SIP_SEI_BIT_WIDTH 1 +#define SIP_SEI_BIT_MASK 0x200 +#define SIP_SEI_ALL_SET_MASK 0x1 +#define SIP_USI_BIT_OFFSET 0 +#define SIP_USI_BIT_WIDTH 1 +#define SIP_USI_BIT_MASK 0x1 +#define SIP_USI_ALL_SET_MASK 0x1 +#define SIP_UTI_BIT_OFFSET 4 +#define SIP_UTI_BIT_WIDTH 1 +#define SIP_UTI_BIT_MASK 0x10 +#define SIP_UTI_ALL_SET_MASK 0x1 +#define SIP_UEI_BIT_OFFSET 8 +#define SIP_UEI_BIT_WIDTH 1 +#define SIP_UEI_BIT_MASK 0x100 +#define SIP_UEI_ALL_SET_MASK 0x1 + +/******************************************* + * sie - SRW - Supervisor Interrupt Enable + */ +static inline uint_xlen_t csr_read_sie(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, sie" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_sie(uint_xlen_t value) { + __asm__ volatile ("csrw sie, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_sie(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, sie, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} +/* Register CSR bit set and clear instructions */ +static inline void csr_set_bits_sie(uint_xlen_t mask) { + __asm__ volatile ("csrrs zero, sie, %0" + : /* output: none */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); +} +static inline void csr_clr_bits_sie(uint_xlen_t mask) { + __asm__ volatile ("csrrc zero, sie, %0" + : /* output: none */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_set_bits_sie(uint_xlen_t mask) { + uint_xlen_t value; + __asm__ volatile ("csrrs %0, sie, %1" + : "=r" (value) /* output: register %0 */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); + return value; +} +static inline uint_xlen_t csr_read_clr_bits_sie(uint_xlen_t mask) { + uint_xlen_t value; + __asm__ volatile ("csrrc %0, sie, %1" + : "=r" (value) /* output: register %0 */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); + return value; +} +/* sie, CSR write value via immediate value (only up to 5 bits) */ +#define CSR_WRITE_IMM_SIE(VALUE) \ + __asm__ volatile ("csrrwi zero, sie, %0" \ + : /* output: none */ \ + : "i" (VALUE) /* input : immediate */ \ + : /* clobbers: none */) + +/* sie, CSR set bits via immediate value mask (only up to 5 bits) */ +#define CSR_SET_BITS_IMM_SIE(MASK) \ + __asm__ volatile ("csrrsi zero, sie, %0" \ + : /* output: none */ \ + : "i" (MASK) /* input : immediate */ \ + : /* clobbers: none */) + +/* sie, CSR clear bits via immediate value mask (only up to 5 bits) */ +#define CSR_CLR_BITS_IMM_SIE(MASK) \ + __asm__ volatile ("csrrci zero, sie, %0" \ + : /* output: none */ \ + : "i" (MASK) /* input : immediate */ \ + : /* clobbers: none */) +#define SIE_SSI_BIT_OFFSET 1 +#define SIE_SSI_BIT_WIDTH 1 +#define SIE_SSI_BIT_MASK 0x2 +#define SIE_SSI_ALL_SET_MASK 0x1 +#define SIE_STI_BIT_OFFSET 5 +#define SIE_STI_BIT_WIDTH 1 +#define SIE_STI_BIT_MASK 0x20 +#define SIE_STI_ALL_SET_MASK 0x1 +#define SIE_SEI_BIT_OFFSET 9 +#define SIE_SEI_BIT_WIDTH 1 +#define SIE_SEI_BIT_MASK 0x200 +#define SIE_SEI_ALL_SET_MASK 0x1 +#define SIE_USI_BIT_OFFSET 0 +#define SIE_USI_BIT_WIDTH 1 +#define SIE_USI_BIT_MASK 0x1 +#define SIE_USI_ALL_SET_MASK 0x1 +#define SIE_UTI_BIT_OFFSET 4 +#define SIE_UTI_BIT_WIDTH 1 +#define SIE_UTI_BIT_MASK 0x10 +#define SIE_UTI_ALL_SET_MASK 0x1 +#define SIE_UEI_BIT_OFFSET 8 +#define SIE_UEI_BIT_WIDTH 1 +#define SIE_UEI_BIT_MASK 0x100 +#define SIE_UEI_ALL_SET_MASK 0x1 + +/******************************************* + * ustatus - URW - User mode restricted view of mstatus + */ +static inline uint_xlen_t csr_read_ustatus(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, ustatus" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_ustatus(uint_xlen_t value) { + __asm__ volatile ("csrw ustatus, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_ustatus(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, ustatus, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} +/* Register CSR bit set and clear instructions */ +static inline void csr_set_bits_ustatus(uint_xlen_t mask) { + __asm__ volatile ("csrrs zero, ustatus, %0" + : /* output: none */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); +} +static inline void csr_clr_bits_ustatus(uint_xlen_t mask) { + __asm__ volatile ("csrrc zero, ustatus, %0" + : /* output: none */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_set_bits_ustatus(uint_xlen_t mask) { + uint_xlen_t value; + __asm__ volatile ("csrrs %0, ustatus, %1" + : "=r" (value) /* output: register %0 */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); + return value; +} +static inline uint_xlen_t csr_read_clr_bits_ustatus(uint_xlen_t mask) { + uint_xlen_t value; + __asm__ volatile ("csrrc %0, ustatus, %1" + : "=r" (value) /* output: register %0 */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); + return value; +} +/* ustatus, CSR write value via immediate value (only up to 5 bits) */ +#define CSR_WRITE_IMM_USTATUS(VALUE) \ + __asm__ volatile ("csrrwi zero, ustatus, %0" \ + : /* output: none */ \ + : "i" (VALUE) /* input : immediate */ \ + : /* clobbers: none */) + +/* ustatus, CSR set bits via immediate value mask (only up to 5 bits) */ +#define CSR_SET_BITS_IMM_USTATUS(MASK) \ + __asm__ volatile ("csrrsi zero, ustatus, %0" \ + : /* output: none */ \ + : "i" (MASK) /* input : immediate */ \ + : /* clobbers: none */) + +/* ustatus, CSR clear bits via immediate value mask (only up to 5 bits) */ +#define CSR_CLR_BITS_IMM_USTATUS(MASK) \ + __asm__ volatile ("csrrci zero, ustatus, %0" \ + : /* output: none */ \ + : "i" (MASK) /* input : immediate */ \ + : /* clobbers: none */) +#define USTATUS_UIE_BIT_OFFSET 1 +#define USTATUS_UIE_BIT_WIDTH 1 +#define USTATUS_UIE_BIT_MASK 0x2 +#define USTATUS_UIE_ALL_SET_MASK 0x1 +#define USTATUS_UPIE_BIT_OFFSET 3 +#define USTATUS_UPIE_BIT_WIDTH 1 +#define USTATUS_UPIE_BIT_MASK 0x8 +#define USTATUS_UPIE_ALL_SET_MASK 0x1 + +/******************************************* + * uip - URW - User Interrupt Pending + */ +static inline uint_xlen_t csr_read_uip(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, uip" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_uip(uint_xlen_t value) { + __asm__ volatile ("csrw uip, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_uip(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, uip, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} +/* Register CSR bit set and clear instructions */ +static inline void csr_set_bits_uip(uint_xlen_t mask) { + __asm__ volatile ("csrrs zero, uip, %0" + : /* output: none */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); +} +static inline void csr_clr_bits_uip(uint_xlen_t mask) { + __asm__ volatile ("csrrc zero, uip, %0" + : /* output: none */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_set_bits_uip(uint_xlen_t mask) { + uint_xlen_t value; + __asm__ volatile ("csrrs %0, uip, %1" + : "=r" (value) /* output: register %0 */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); + return value; +} +static inline uint_xlen_t csr_read_clr_bits_uip(uint_xlen_t mask) { + uint_xlen_t value; + __asm__ volatile ("csrrc %0, uip, %1" + : "=r" (value) /* output: register %0 */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); + return value; +} +/* uip, CSR write value via immediate value (only up to 5 bits) */ +#define CSR_WRITE_IMM_UIP(VALUE) \ + __asm__ volatile ("csrrwi zero, uip, %0" \ + : /* output: none */ \ + : "i" (VALUE) /* input : immediate */ \ + : /* clobbers: none */) + +/* uip, CSR set bits via immediate value mask (only up to 5 bits) */ +#define CSR_SET_BITS_IMM_UIP(MASK) \ + __asm__ volatile ("csrrsi zero, uip, %0" \ + : /* output: none */ \ + : "i" (MASK) /* input : immediate */ \ + : /* clobbers: none */) + +/* uip, CSR clear bits via immediate value mask (only up to 5 bits) */ +#define CSR_CLR_BITS_IMM_UIP(MASK) \ + __asm__ volatile ("csrrci zero, uip, %0" \ + : /* output: none */ \ + : "i" (MASK) /* input : immediate */ \ + : /* clobbers: none */) +#define UIP_USI_BIT_OFFSET 0 +#define UIP_USI_BIT_WIDTH 1 +#define UIP_USI_BIT_MASK 0x1 +#define UIP_USI_ALL_SET_MASK 0x1 +#define UIP_UTI_BIT_OFFSET 4 +#define UIP_UTI_BIT_WIDTH 1 +#define UIP_UTI_BIT_MASK 0x10 +#define UIP_UTI_ALL_SET_MASK 0x1 +#define UIP_UEI_BIT_OFFSET 8 +#define UIP_UEI_BIT_WIDTH 1 +#define UIP_UEI_BIT_MASK 0x100 +#define UIP_UEI_ALL_SET_MASK 0x1 + +/******************************************* + * uie - URW - User Interrupt Enable + */ +static inline uint_xlen_t csr_read_uie(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, uie" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_uie(uint_xlen_t value) { + __asm__ volatile ("csrw uie, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_uie(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, uie, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} +/* Register CSR bit set and clear instructions */ +static inline void csr_set_bits_uie(uint_xlen_t mask) { + __asm__ volatile ("csrrs zero, uie, %0" + : /* output: none */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); +} +static inline void csr_clr_bits_uie(uint_xlen_t mask) { + __asm__ volatile ("csrrc zero, uie, %0" + : /* output: none */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_set_bits_uie(uint_xlen_t mask) { + uint_xlen_t value; + __asm__ volatile ("csrrs %0, uie, %1" + : "=r" (value) /* output: register %0 */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); + return value; +} +static inline uint_xlen_t csr_read_clr_bits_uie(uint_xlen_t mask) { + uint_xlen_t value; + __asm__ volatile ("csrrc %0, uie, %1" + : "=r" (value) /* output: register %0 */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); + return value; +} +/* uie, CSR write value via immediate value (only up to 5 bits) */ +#define CSR_WRITE_IMM_UIE(VALUE) \ + __asm__ volatile ("csrrwi zero, uie, %0" \ + : /* output: none */ \ + : "i" (VALUE) /* input : immediate */ \ + : /* clobbers: none */) + +/* uie, CSR set bits via immediate value mask (only up to 5 bits) */ +#define CSR_SET_BITS_IMM_UIE(MASK) \ + __asm__ volatile ("csrrsi zero, uie, %0" \ + : /* output: none */ \ + : "i" (MASK) /* input : immediate */ \ + : /* clobbers: none */) + +/* uie, CSR clear bits via immediate value mask (only up to 5 bits) */ +#define CSR_CLR_BITS_IMM_UIE(MASK) \ + __asm__ volatile ("csrrci zero, uie, %0" \ + : /* output: none */ \ + : "i" (MASK) /* input : immediate */ \ + : /* clobbers: none */) +#define UIE_USI_BIT_OFFSET 0 +#define UIE_USI_BIT_WIDTH 1 +#define UIE_USI_BIT_MASK 0x1 +#define UIE_USI_ALL_SET_MASK 0x1 +#define UIE_UTI_BIT_OFFSET 4 +#define UIE_UTI_BIT_WIDTH 1 +#define UIE_UTI_BIT_MASK 0x10 +#define UIE_UTI_ALL_SET_MASK 0x1 +#define UIE_UEI_BIT_OFFSET 8 +#define UIE_UEI_BIT_WIDTH 1 +#define UIE_UEI_BIT_MASK 0x100 +#define UIE_UEI_ALL_SET_MASK 0x1 + +/******************************************* + * uscratch - URW - User Mode Scratch Register + */ +static inline uint_xlen_t csr_read_uscratch(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, uscratch" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_uscratch(uint_xlen_t value) { + __asm__ volatile ("csrw uscratch, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_uscratch(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, uscratch, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * uepc - URW - User Exception Program Counter + */ +static inline uint_xlen_t csr_read_uepc(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, uepc" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_uepc(uint_xlen_t value) { + __asm__ volatile ("csrw uepc, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_uepc(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, uepc, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * ucause - URW - User Exception Cause + */ +static inline uint_xlen_t csr_read_ucause(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, ucause" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_ucause(uint_xlen_t value) { + __asm__ volatile ("csrw ucause, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_ucause(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, ucause, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} +/* Register CSR bit set and clear instructions */ +static inline void csr_set_bits_ucause(uint_xlen_t mask) { + __asm__ volatile ("csrrs zero, ucause, %0" + : /* output: none */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); +} +static inline void csr_clr_bits_ucause(uint_xlen_t mask) { + __asm__ volatile ("csrrc zero, ucause, %0" + : /* output: none */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_set_bits_ucause(uint_xlen_t mask) { + uint_xlen_t value; + __asm__ volatile ("csrrs %0, ucause, %1" + : "=r" (value) /* output: register %0 */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); + return value; +} +static inline uint_xlen_t csr_read_clr_bits_ucause(uint_xlen_t mask) { + uint_xlen_t value; + __asm__ volatile ("csrrc %0, ucause, %1" + : "=r" (value) /* output: register %0 */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); + return value; +} +/* ucause, CSR write value via immediate value (only up to 5 bits) */ +#define CSR_WRITE_IMM_UCAUSE(VALUE) \ + __asm__ volatile ("csrrwi zero, ucause, %0" \ + : /* output: none */ \ + : "i" (VALUE) /* input : immediate */ \ + : /* clobbers: none */) + +/* ucause, CSR set bits via immediate value mask (only up to 5 bits) */ +#define CSR_SET_BITS_IMM_UCAUSE(MASK) \ + __asm__ volatile ("csrrsi zero, ucause, %0" \ + : /* output: none */ \ + : "i" (MASK) /* input : immediate */ \ + : /* clobbers: none */) + +/* ucause, CSR clear bits via immediate value mask (only up to 5 bits) */ +#define CSR_CLR_BITS_IMM_UCAUSE(MASK) \ + __asm__ volatile ("csrrci zero, ucause, %0" \ + : /* output: none */ \ + : "i" (MASK) /* input : immediate */ \ + : /* clobbers: none */) +#define UCAUSE_INTERRUPT_BIT_OFFSET (__riscv_xlen-1) +#define UCAUSE_INTERRUPT_BIT_WIDTH 1 +#define UCAUSE_INTERRUPT_BIT_MASK (0x1UL << ((__riscv_xlen-1))) +#define UCAUSE_INTERRUPT_ALL_SET_MASK 0x1 +#define UCAUSE_EXCEPTION_CODE_BIT_OFFSET 0 +#define UCAUSE_EXCEPTION_CODE_BIT_WIDTH ((__riscv_xlen-2)-(0) + 1) +#define UCAUSE_EXCEPTION_CODE_BIT_MASK ((1UL<<(((__riscv_xlen-2)-(0) + 1)-1)) << (0)) +#define UCAUSE_EXCEPTION_CODE_ALL_SET_MASK ((1UL<<(((__riscv_xlen-2)-(0) + 1)-1)) << (0)) + +/******************************************* + * utvec - URW - User Trap Vector Base Address + */ +static inline uint_xlen_t csr_read_utvec(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, utvec" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_utvec(uint_xlen_t value) { + __asm__ volatile ("csrw utvec, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_utvec(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, utvec, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} +/* Register CSR bit set and clear instructions */ +static inline void csr_set_bits_utvec(uint_xlen_t mask) { + __asm__ volatile ("csrrs zero, utvec, %0" + : /* output: none */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); +} +static inline void csr_clr_bits_utvec(uint_xlen_t mask) { + __asm__ volatile ("csrrc zero, utvec, %0" + : /* output: none */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_set_bits_utvec(uint_xlen_t mask) { + uint_xlen_t value; + __asm__ volatile ("csrrs %0, utvec, %1" + : "=r" (value) /* output: register %0 */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); + return value; +} +static inline uint_xlen_t csr_read_clr_bits_utvec(uint_xlen_t mask) { + uint_xlen_t value; + __asm__ volatile ("csrrc %0, utvec, %1" + : "=r" (value) /* output: register %0 */ + : "r" (mask) /* input : register */ + : /* clobbers: none */); + return value; +} +/* utvec, CSR write value via immediate value (only up to 5 bits) */ +#define CSR_WRITE_IMM_UTVEC(VALUE) \ + __asm__ volatile ("csrrwi zero, utvec, %0" \ + : /* output: none */ \ + : "i" (VALUE) /* input : immediate */ \ + : /* clobbers: none */) + +/* utvec, CSR set bits via immediate value mask (only up to 5 bits) */ +#define CSR_SET_BITS_IMM_UTVEC(MASK) \ + __asm__ volatile ("csrrsi zero, utvec, %0" \ + : /* output: none */ \ + : "i" (MASK) /* input : immediate */ \ + : /* clobbers: none */) + +/* utvec, CSR clear bits via immediate value mask (only up to 5 bits) */ +#define CSR_CLR_BITS_IMM_UTVEC(MASK) \ + __asm__ volatile ("csrrci zero, utvec, %0" \ + : /* output: none */ \ + : "i" (MASK) /* input : immediate */ \ + : /* clobbers: none */) +#define UTVEC_BASE_BIT_OFFSET 2 +#define UTVEC_BASE_BIT_WIDTH ((__riscv_xlen-1)-(2) + 1) +#define UTVEC_BASE_BIT_MASK ((1UL<<(((__riscv_xlen-1)-(2) + 1)-1)) << (2)) +#define UTVEC_BASE_ALL_SET_MASK ((1UL<<(((__riscv_xlen-1)-(2) + 1)-1)) << (0)) +#define UTVEC_MODE_BIT_OFFSET 0 +#define UTVEC_MODE_BIT_WIDTH 2 +#define UTVEC_MODE_BIT_MASK 0x3 +#define UTVEC_MODE_ALL_SET_MASK 0x3 + +/******************************************* + * utval - URW - User Trap Value + */ +static inline uint_xlen_t csr_read_utval(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, utval" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_utval(uint_xlen_t value) { + __asm__ volatile ("csrw utval, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_utval(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, utval, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * fflags - URW - Floating-Point Accrued Exceptions. + */ +static inline uint_xlen_t csr_read_fflags(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, fflags" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_fflags(uint_xlen_t value) { + __asm__ volatile ("csrw fflags, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_fflags(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, fflags, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * frm - URW - Floating-Point Dynamic Rounding Mode. + */ +static inline uint_xlen_t csr_read_frm(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, frm" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_frm(uint_xlen_t value) { + __asm__ volatile ("csrw frm, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_frm(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, frm, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * fcsr - URW - Floating-Point Control and Status + */ +static inline uint_xlen_t csr_read_fcsr(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, fcsr" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_fcsr(uint_xlen_t value) { + __asm__ volatile ("csrw fcsr, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_fcsr(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, fcsr, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * cycle - URO - Cycle counter for RDCYCLE instruction. + */ +static inline uint_xlen_t csr_read_cycle(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, cycle" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} + +/******************************************* + * time - URO - Timer for RDTIME instruction. + */ +static inline uint_xlen_t csr_read_time(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, time" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} + +/******************************************* + * instret - URO - Instructions-retired counter for RDINSTRET instruction. + */ +static inline uint_xlen_t csr_read_instret(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, instret" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} + +/******************************************* + * hpmcounter3 - URO - Performance-monitoring counter. + */ +static inline uint_xlen_t csr_read_hpmcounter3(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, hpmcounter3" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} + +/******************************************* + * hpmcounter4 - URO - Performance-monitoring counter. + */ +static inline uint_xlen_t csr_read_hpmcounter4(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, hpmcounter4" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} + +/******************************************* + * hpmcounter31 - URO - Performance-monitoring counter. + */ +static inline uint_xlen_t csr_read_hpmcounter31(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, hpmcounter31" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} + +/******************************************* + * cycleh - URO - Upper 32 bits of cycle, RV32I only. + */ +static inline uint_xlen_t csr_read_cycleh(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, cycleh" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} + +/******************************************* + * timeh - URO - Upper 32 bits of time, RV32I only. + */ +static inline uint_xlen_t csr_read_timeh(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, timeh" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} + +/******************************************* + * instreth - URO - Upper 32 bits of instret, RV32I only. + */ +static inline uint_xlen_t csr_read_instreth(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, instreth" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} + +/******************************************* + * hpmcounter3h - URO - Upper 32 bits of hpmcounter3, RV32I only. + */ +static inline uint_xlen_t csr_read_hpmcounter3h(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, hpmcounter3h" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} + +/******************************************* + * hpmcounter4h - URO - Upper 32 bits of hpmcounter4, RV32I only. + */ +static inline uint_xlen_t csr_read_hpmcounter4h(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, hpmcounter4h" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} + +/******************************************* + * hpmcounter31h - URO - Upper 32 bits of hpmcounter31, RV32I only. + */ +static inline uint_xlen_t csr_read_hpmcounter31h(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, hpmcounter31h" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} + +/******************************************* + * stval - SRW - Supervisor bad address or instruction. + */ +static inline uint_xlen_t csr_read_stval(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, stval" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_stval(uint_xlen_t value) { + __asm__ volatile ("csrw stval, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_stval(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, stval, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * satp - SRW - Supervisor address translation and protection. + */ +static inline uint_xlen_t csr_read_satp(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, satp" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_satp(uint_xlen_t value) { + __asm__ volatile ("csrw satp, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_satp(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, satp, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * hstatus - HRW - Hypervisor status register. + */ +static inline uint_xlen_t csr_read_hstatus(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, hstatus" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_hstatus(uint_xlen_t value) { + __asm__ volatile ("csrw hstatus, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_hstatus(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, hstatus, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * hedeleg - HRW - Hypervisor exception delegation register. + */ +static inline uint_xlen_t csr_read_hedeleg(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, hedeleg" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_hedeleg(uint_xlen_t value) { + __asm__ volatile ("csrw hedeleg, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_hedeleg(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, hedeleg, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * hideleg - HRW - Hypervisor interrupt delegation register. + */ +static inline uint_xlen_t csr_read_hideleg(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, hideleg" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_hideleg(uint_xlen_t value) { + __asm__ volatile ("csrw hideleg, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_hideleg(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, hideleg, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * hcounteren - HRW - Hypervisor counter enable. + */ +static inline uint_xlen_t csr_read_hcounteren(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, hcounteren" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_hcounteren(uint_xlen_t value) { + __asm__ volatile ("csrw hcounteren, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_hcounteren(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, hcounteren, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * hgatp - HRW - Hypervisor guest address translation and protection. + */ +static inline uint_xlen_t csr_read_hgatp(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, hgatp" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_hgatp(uint_xlen_t value) { + __asm__ volatile ("csrw hgatp, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_hgatp(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, hgatp, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * htimedelta - HRW - Delta for VS/VU-mode timer. + */ +static inline uint_xlen_t csr_read_htimedelta(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, htimedelta" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_htimedelta(uint_xlen_t value) { + __asm__ volatile ("csrw htimedelta, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_htimedelta(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, htimedelta, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * htimedeltah - HRW - Upper 32 bits of htimedelta, RV32I only. + */ +static inline uint_xlen_t csr_read_htimedeltah(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, htimedeltah" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_htimedeltah(uint_xlen_t value) { + __asm__ volatile ("csrw htimedeltah, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_htimedeltah(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, htimedeltah, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * vsstatus - HRW - Virtual supervisor status register. + */ +static inline uint_xlen_t csr_read_vsstatus(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, vsstatus" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_vsstatus(uint_xlen_t value) { + __asm__ volatile ("csrw vsstatus, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_vsstatus(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, vsstatus, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * vsie - HRW - Virtual supervisor interrupt-enable register. + */ +static inline uint_xlen_t csr_read_vsie(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, vsie" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_vsie(uint_xlen_t value) { + __asm__ volatile ("csrw vsie, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_vsie(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, vsie, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * vstvec - HRW - Virtual supervisor trap handler base address. + */ +static inline uint_xlen_t csr_read_vstvec(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, vstvec" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_vstvec(uint_xlen_t value) { + __asm__ volatile ("csrw vstvec, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_vstvec(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, vstvec, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * vsscratch - HRW - Virtual supervisor scratch register. + */ +static inline uint_xlen_t csr_read_vsscratch(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, vsscratch" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_vsscratch(uint_xlen_t value) { + __asm__ volatile ("csrw vsscratch, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_vsscratch(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, vsscratch, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * vsepc - HRW - Virtual supervisor exception program counter. + */ +static inline uint_xlen_t csr_read_vsepc(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, vsepc" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_vsepc(uint_xlen_t value) { + __asm__ volatile ("csrw vsepc, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_vsepc(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, vsepc, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * vscause - HRW - Virtual supervisor trap cause. + */ +static inline uint_xlen_t csr_read_vscause(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, vscause" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_vscause(uint_xlen_t value) { + __asm__ volatile ("csrw vscause, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_vscause(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, vscause, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * vstval - HRW - Virtual supervisor bad address or instruction. + */ +static inline uint_xlen_t csr_read_vstval(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, vstval" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_vstval(uint_xlen_t value) { + __asm__ volatile ("csrw vstval, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_vstval(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, vstval, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * vsip - HRW - Virtual supervisor interrupt pending. + */ +static inline uint_xlen_t csr_read_vsip(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, vsip" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_vsip(uint_xlen_t value) { + __asm__ volatile ("csrw vsip, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_vsip(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, vsip, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * vsatp - HRW - Virtual supervisor address translation and protection. + */ +static inline uint_xlen_t csr_read_vsatp(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, vsatp" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_vsatp(uint_xlen_t value) { + __asm__ volatile ("csrw vsatp, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_vsatp(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, vsatp, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * mbase - MRW - Base register. + */ +static inline uint_xlen_t csr_read_mbase(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, mbase" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_mbase(uint_xlen_t value) { + __asm__ volatile ("csrw mbase, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_mbase(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, mbase, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * mbound - MRW - Bound register. + */ +static inline uint_xlen_t csr_read_mbound(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, mbound" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_mbound(uint_xlen_t value) { + __asm__ volatile ("csrw mbound, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_mbound(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, mbound, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * mibase - MRW - Instruction base register. + */ +static inline uint_xlen_t csr_read_mibase(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, mibase" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_mibase(uint_xlen_t value) { + __asm__ volatile ("csrw mibase, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_mibase(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, mibase, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * mibound - MRW - Instruction bound register. + */ +static inline uint_xlen_t csr_read_mibound(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, mibound" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_mibound(uint_xlen_t value) { + __asm__ volatile ("csrw mibound, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_mibound(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, mibound, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * mdbase - MRW - Data base register. + */ +static inline uint_xlen_t csr_read_mdbase(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, mdbase" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_mdbase(uint_xlen_t value) { + __asm__ volatile ("csrw mdbase, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_mdbase(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, mdbase, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * mdbound - MRW - Data bound register. + */ +static inline uint_xlen_t csr_read_mdbound(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, mdbound" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_mdbound(uint_xlen_t value) { + __asm__ volatile ("csrw mdbound, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_mdbound(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, mdbound, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * pmpcfg0 - MRW - Physical memory protection configuration. + */ +static inline uint_xlen_t csr_read_pmpcfg0(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, pmpcfg0" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_pmpcfg0(uint_xlen_t value) { + __asm__ volatile ("csrw pmpcfg0, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_pmpcfg0(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, pmpcfg0, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * pmpcfg1 - MRW - Physical memory protection configuration, RV32 only. + */ +static inline uint_xlen_t csr_read_pmpcfg1(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, pmpcfg1" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_pmpcfg1(uint_xlen_t value) { + __asm__ volatile ("csrw pmpcfg1, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_pmpcfg1(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, pmpcfg1, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * pmpcfg2 - MRW - Physical memory protection configuration. + */ +static inline uint_xlen_t csr_read_pmpcfg2(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, pmpcfg2" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_pmpcfg2(uint_xlen_t value) { + __asm__ volatile ("csrw pmpcfg2, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_pmpcfg2(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, pmpcfg2, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * pmpcfg3 - MRW - Physical memory protection configuration, RV32 only. + */ +static inline uint_xlen_t csr_read_pmpcfg3(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, pmpcfg3" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_pmpcfg3(uint_xlen_t value) { + __asm__ volatile ("csrw pmpcfg3, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_pmpcfg3(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, pmpcfg3, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * pmpaddr0 - MRW - Physical memory protection address register. + */ +static inline uint_xlen_t csr_read_pmpaddr0(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, pmpaddr0" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_pmpaddr0(uint_xlen_t value) { + __asm__ volatile ("csrw pmpaddr0, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_pmpaddr0(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, pmpaddr0, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * pmpaddr1 - MRW - Physical memory protection address register. + */ +static inline uint_xlen_t csr_read_pmpaddr1(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, pmpaddr1" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_pmpaddr1(uint_xlen_t value) { + __asm__ volatile ("csrw pmpaddr1, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_pmpaddr1(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, pmpaddr1, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * pmpaddr15 - MRW - Physical memory protection address register. + */ +static inline uint_xlen_t csr_read_pmpaddr15(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, pmpaddr15" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_pmpaddr15(uint_xlen_t value) { + __asm__ volatile ("csrw pmpaddr15, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_pmpaddr15(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, pmpaddr15, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * mhpmcounter4 - MRW - Machine performance-monitoring counter. + */ +static inline uint_xlen_t csr_read_mhpmcounter4(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, mhpmcounter4" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_mhpmcounter4(uint_xlen_t value) { + __asm__ volatile ("csrw mhpmcounter4, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_mhpmcounter4(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, mhpmcounter4, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * mhpmcounter31 - MRW - Machine performance-monitoring counter. + */ +static inline uint_xlen_t csr_read_mhpmcounter31(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, mhpmcounter31" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_mhpmcounter31(uint_xlen_t value) { + __asm__ volatile ("csrw mhpmcounter31, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_mhpmcounter31(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, mhpmcounter31, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * mcycleh - MRW - Upper 32 bits of mcycle, RV32I only. + */ +static inline uint32_t csr_read_mcycleh(void) { + uint_csr32_t value; + __asm__ volatile ("csrr %0, mcycleh" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_mcycleh(uint_csr32_t value) { + __asm__ volatile ("csrw mcycleh, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint32_t csr_read_write_mcycleh(uint32_t new_value) { + uint_csr32_t prev_value; + __asm__ volatile ("csrrw %0, mcycleh, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * minstreth - MRW - Upper 32 bits of minstret, RV32I only. + */ +static inline uint32_t csr_read_minstreth(void) { + uint_csr32_t value; + __asm__ volatile ("csrr %0, minstreth" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_minstreth(uint_csr32_t value) { + __asm__ volatile ("csrw minstreth, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint32_t csr_read_write_minstreth(uint32_t new_value) { + uint_csr32_t prev_value; + __asm__ volatile ("csrrw %0, minstreth, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * mhpmcounter3h - MRW - Upper 32 bits of mhpmcounter3, RV32I only. + */ +static inline uint32_t csr_read_mhpmcounter3h(void) { + uint_csr32_t value; + __asm__ volatile ("csrr %0, mhpmcounter3h" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_mhpmcounter3h(uint_csr32_t value) { + __asm__ volatile ("csrw mhpmcounter3h, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint32_t csr_read_write_mhpmcounter3h(uint32_t new_value) { + uint_csr32_t prev_value; + __asm__ volatile ("csrrw %0, mhpmcounter3h, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * mhpmcounter4h - MRW - Upper 32 bits of mhpmcounter4, RV32I only. + */ +static inline uint32_t csr_read_mhpmcounter4h(void) { + uint_csr32_t value; + __asm__ volatile ("csrr %0, mhpmcounter4h" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_mhpmcounter4h(uint_csr32_t value) { + __asm__ volatile ("csrw mhpmcounter4h, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint32_t csr_read_write_mhpmcounter4h(uint32_t new_value) { + uint_csr32_t prev_value; + __asm__ volatile ("csrrw %0, mhpmcounter4h, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * mhpmcounter31h - MRW - Upper 32 bits of mhpmcounter31, RV32I only. + */ +static inline uint32_t csr_read_mhpmcounter31h(void) { + uint_csr32_t value; + __asm__ volatile ("csrr %0, mhpmcounter31h" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_mhpmcounter31h(uint_csr32_t value) { + __asm__ volatile ("csrw mhpmcounter31h, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint32_t csr_read_write_mhpmcounter31h(uint32_t new_value) { + uint_csr32_t prev_value; + __asm__ volatile ("csrrw %0, mhpmcounter31h, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * mhpmevent4 - MRW - Machine performance-monitoring event selector. + */ +static inline uint_xlen_t csr_read_mhpmevent4(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, mhpmevent4" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_mhpmevent4(uint_xlen_t value) { + __asm__ volatile ("csrw mhpmevent4, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_mhpmevent4(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, mhpmevent4, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * mhpmevent31 - MRW - Machine performance-monitoring event selector. + */ +static inline uint_xlen_t csr_read_mhpmevent31(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, mhpmevent31" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_mhpmevent31(uint_xlen_t value) { + __asm__ volatile ("csrw mhpmevent31, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_mhpmevent31(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, mhpmevent31, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * tselect - MRW - Debug/Trace trigger register select. + */ +static inline uint_xlen_t csr_read_tselect(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, tselect" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_tselect(uint_xlen_t value) { + __asm__ volatile ("csrw tselect, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_tselect(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, tselect, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * tdata1 - MRW - First Debug/Trace trigger data register. + */ +static inline uint_xlen_t csr_read_tdata1(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, tdata1" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_tdata1(uint_xlen_t value) { + __asm__ volatile ("csrw tdata1, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_tdata1(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, tdata1, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * tdata2 - MRW - Second Debug/Trace trigger data register. + */ +static inline uint_xlen_t csr_read_tdata2(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, tdata2" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_tdata2(uint_xlen_t value) { + __asm__ volatile ("csrw tdata2, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_tdata2(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, tdata2, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * tdata3 - MRW - Third Debug/Trace trigger data register. + */ +static inline uint_xlen_t csr_read_tdata3(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, tdata3" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_tdata3(uint_xlen_t value) { + __asm__ volatile ("csrw tdata3, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_tdata3(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, tdata3, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * dcsr - DRW - Debug control and status register. + */ +static inline uint_xlen_t csr_read_dcsr(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, dcsr" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_dcsr(uint_xlen_t value) { + __asm__ volatile ("csrw dcsr, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_dcsr(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, dcsr, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * dpc - DRW - Debug PC. + */ +static inline uint_xlen_t csr_read_dpc(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, dpc" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_dpc(uint_xlen_t value) { + __asm__ volatile ("csrw dpc, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_dpc(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, dpc, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * dscratch0 - DRW - Debug scratch register 0. + */ +static inline uint_xlen_t csr_read_dscratch0(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, dscratch0" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_dscratch0(uint_xlen_t value) { + __asm__ volatile ("csrw dscratch0, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_dscratch0(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, dscratch0, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * dscratch1 - DRW - Debug scratch register 1. + */ +static inline uint_xlen_t csr_read_dscratch1(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, dscratch1" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_dscratch1(uint_xlen_t value) { + __asm__ volatile ("csrw dscratch1, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_dscratch1(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, dscratch1, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * hie - HRW - Hypervisor interrupt-enable register. + */ +static inline uint_xlen_t csr_read_hie(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, hie" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_hie(uint_xlen_t value) { + __asm__ volatile ("csrw hie, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_hie(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, hie, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * hgeie - HRW - Hypervisor guest external interrupt-enable register. + */ +static inline uint_xlen_t csr_read_hgeie(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, hgeie" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_hgeie(uint_xlen_t value) { + __asm__ volatile ("csrw hgeie, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_hgeie(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, hgeie, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * htval - HRW - Hypervisor bad guest physical address. + */ +static inline uint_xlen_t csr_read_htval(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, htval" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_htval(uint_xlen_t value) { + __asm__ volatile ("csrw htval, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_htval(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, htval, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * hip - HRW - Hypervisor interrupt pending. + */ +static inline uint_xlen_t csr_read_hip(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, hip" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_hip(uint_xlen_t value) { + __asm__ volatile ("csrw hip, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_hip(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, hip, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * htinst - HRW - Hypervisor trap instruction (transformed). + */ +static inline uint_xlen_t csr_read_htinst(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, htinst" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_htinst(uint_xlen_t value) { + __asm__ volatile ("csrw htinst, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_htinst(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, htinst, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * hgeip - HRO - Hypervisor guest external interrupt pending. + */ +static inline uint_xlen_t csr_read_hgeip(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, hgeip" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} + +/******************************************* + * mtinst - MRW - Machine trap instruction (transformed). + */ +static inline uint_xlen_t csr_read_mtinst(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, mtinst" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_mtinst(uint_xlen_t value) { + __asm__ volatile ("csrw mtinst, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_mtinst(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, mtinst, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + +/******************************************* + * mtval2 - MRW - Machine bad guest physical address. + */ +static inline uint_xlen_t csr_read_mtval2(void) { + uint_xlen_t value; + __asm__ volatile ("csrr %0, mtval2" + : "=r" (value) /* output : register */ + : /* input : none */ + : /* clobbers: none */); + return value; +} +static inline void csr_write_mtval2(uint_xlen_t value) { + __asm__ volatile ("csrw mtval2, %0" + : /* output: none */ + : "r" (value) /* input : from register */ + : /* clobbers: none */); +} +static inline uint_xlen_t csr_read_write_mtval2(uint_xlen_t new_value) { + uint_xlen_t prev_value; + __asm__ volatile ("csrrw %0, mtval2, %1" + : "=r" (prev_value) /* output: register %0 */ + : "r" (new_value) /* input : register */ + : /* clobbers: none */); + return prev_value; +} + + +#endif // #define RISCV_CSR_H diff --git a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/SBL/Output/SBL.bin b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/SBL/Output/SBL.bin new file mode 100644 index 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zx8eGfixMnkxu-%&Qr&$+N~6~ltW?(dH>k@#Y9d)2!+Af*Nz(lS9IJH!BXmYJpXzma z+mpyOQ7e)WD#YU()d+70M*SrgkrNr!ljWx*X&Yr2CVBOsOcjYXa-=n$X!Qtw$}cHs zR7T4XX*JZO)D>LB_*z97PQxZuehjG*@xviPNgNrxZG#+=lyREnMZ}LF*%(1pg`m+@ zu0H`)5yyRaDJjR7H)98H)?@MrfX7^g)CVHkns7eEk#at}jAz#Zcjs|Wt*NpF#ueu+ zhmG^nnRG4Fr>$#D#LnvsThXY9ilLB(!2RsR8{oo&0~P{=%`99oRRa}9HeNf>$i$9Y zC*MQi<;Z$!K@jh+bxVyUuAxyt6CyKrVk?vR%$%`VE{PAs2NQ$Nw0(*jiOpHFR9B?> ziI2I_QcQR-y$R!1rohxkB+;a?G9L}@uOHN9hx9$u_rtTydGNa)@TcXKy_W9^>{a1> zAvmc70RBtfuESO9ez>z5Ep4Xfp`GNQuv;O4K(aZGV{$jaCy7%j*jZ`vS6nc6N{a4Y z(k>8<-VyV7S9q0}zp+qW;|=FpK%$?lE9C`%jCpBi~%F*CFC$5qn~IO>8^eXsE>PPxg+#0+)azfbm6kg3le4lWxnSc zbV~#a1r%%`N(>Sm-)FAjL0_6EIon^9iD8R9*~nvuA)&;{mX#@CB6bYNZJ~~Mwi14R zGmy>cHs;>&T9;4g@u$dNIbFBlhF0=kMe`BTK;+@?uMaXpGK zS7mFKWk11RIV;^=+S-z_%)ckHZI!p-x7qz2s9!2=tNe14`iynVmEO?O(yjNKjdwrVJ&N|d_|4rvuO+*Z_wer@ zasQ1QWIXAwd+VmGeD{V=cYl6s%eLZ?H(<4zo8_}-m?LXP&^;~cz@S! z-Bx+9h5e1h{$AH2{f#93ed_#emB;a1+OFldL$lD|-4|@Dyjt4b9Qtcnk#;w8U?2C# zX!n@3tHgF6kaiWeJC1wP_&1M##Lutd-+S!e|Aya(@$Vz}_tbyeD!dPzOS8wec^M1F z-?u}#EM@<%oNe$+`7LLyh4MLt^2S1WQ=z=MP(HU%-cl$N`|+=woo6f1x((U)f5H)_ zOBa&#@b~?nT!#Oz&0={s%9p(C{BZwyC_kQ*52F0Ck$As`^7E7OeJJ}M$9n?`gcny{ z0z`iWzfLP49U<0!wZH9r4kw#WE_!Z#izCg|Y-jf$b6s{Bf(uh*~f9ijLju}00HU;DGM9(<{-=MY~` zKsD3YK-4u4O4=)d_8?B%{8d5g9D{4B^ zd)c1lMVg|#UEQ-U+j9ah58ShiMAtj^Flab;Vs!;p{~qq;@_TW6re{v9p48Ra_2h{Y z%QJWQ9qe!TRBA33-$H{c;;vPqx>dIt7d^*+LmRXz(4AT!_qQL{XtN}h_>b*w^#Xp` z7ytV4&--Qhg*&s1I>Y~XkN-yO*X!Snb{l4SNB{ha`rWU2=Y6j)W$#SXsNZ{eq1|); zT`7AVAFw}fw~De~^VZ{N_g-GupWk~e%6`pTFM}ZcPy%PacfYl(uo3>YzOR%meNM0W zKil!&yX+S~@^|;Cmh4gQ1T_xlM{u1~XV<^HMR24~#d~Z+QR{!l(QXL{x&Red;vf6t fbZJqfR?8Ppqh0c#k9A?8-Sg4t6R7h)Z}: +30100000: f1402573 csrr a0,mhartid +30100004: ,-- ed39 bnez a0,30100062 <_start+0x62> +30100006: | 500e57b7 lui a5,0x500e5 +3010000a: | 06078793 addi a5,a5,96 # 500e5060 +3010000e: | 500e5837 lui a6,0x500e5 +30100012: | 03c80813 addi a6,a6,60 # 500e503c +30100016: | 4505 li a0,1 +30100018: | c388 sw a0,0(a5) +3010001a: | 00a82023 sw a0,0(a6) +3010001e: | 4ffa0137 lui sp,0x4ffa0 +30100022: | 28e000ef jal 301002b0 +30100026: | 22a000ef jal 30100250 +3010002a: | 2cc000ef jal 301002f6 +3010002e: | 0aa000ef jal 301000d8 +30100032: | 00000517 auipc a0,0x0 +30100036: | 03050513 addi a0,a0,48 # 30100062 <_start+0x62> +3010003a: | 501107b7 lui a5,0x50110 +3010003e: | 16478793 addi a5,a5,356 # 50110164 +30100042: | c388 sw a0,0(a5) +30100044: | 500e67b7 lui a5,0x500e6 +30100048: | 07d1 addi a5,a5,20 # 500e6014 +3010004a: | 4388 lw a0,0(a5) +3010004c: | 01056513 ori a0,a0,16 +30100050: | c388 sw a0,0(a5) +30100052: | 500e67b7 lui a5,0x500e6 +30100056: | 0c078793 addi a5,a5,192 # 500e60c0 +3010005a: | 4388 lw a0,0(a5) +3010005c: | eff57513 andi a0,a0,-257 +30100060: | c388 sw a0,0(a5) +30100062: '-> 0ff05797 auipc a5,0xff05 +30100066: f9e78793 addi a5,a5,-98 # 40005000 <__app_entry_point> +3010006a: 8782 jr a5 +3010006c: ,-- a001 j 3010006c <_start+0x6c> +3010006e: 0000 unimp +30100070: 5350 lw a2,36(a4) +30100072: 4152 lw sp,20(sp) +30100074: 204d jal 30100116 +30100076: 70696863 bltu s2,t1,30100786 +3010007a: 6920 flw fs0,80(a0) +3010007c: 6f6e2073 csrs 0x6f6,t3 +30100080: 2074 .insn 2, 0x2074 +30100082: 6e6e6f63 bltu t3,t1,30100780 +30100086: 6365 lui t1,0x19 +30100088: 6574 flw fa3,76(a0) +3010008a: 0a64 addi s1,sp,284 +3010008c: 000d c.nop 3 +3010008e: 0000 unimp +30100090: 5350 lw a2,36(a4) +30100092: 4152 lw sp,20(sp) +30100094: 204d jal 30100136 +30100096: 4449 li s0,18 +30100098: 7220 flw fs0,96(a2) +3010009a: 6165 addi sp,sp,112 +3010009c: 2064 .insn 2, 0x2064 +3010009e: 7265 lui tp,0xffff9 +301000a0: 6f72 flw ft10,28(sp) +301000a2: 3a72 .insn 2, 0x3a72 +301000a4: 3020 .insn 2, 0x3020 +301000a6: 2578 .insn 2, 0x2578 +301000a8: 3830 .insn 2, 0x3830 +301000aa: 2c78 .insn 2, 0x2c78 +301000ac: 6620 flw fs0,72(a2) +301000ae: 6c61 lui s8,0x18 +301000b0: 626c flw fa1,68(a2) +301000b2: 6361 lui t1,0x18 +301000b4: 6f74206b .insn 4, 0x6f74206b +301000b8: 7520 flw fs0,104(a0) +301000ba: 64206573 csrrsi a0,0x642,0 +301000be: 6665 lui a2,0x19 +301000c0: 7561 lui a0,0xffff8 +301000c2: 746c flw fa1,108(s0) +301000c4: 6420 flw fs0,72(s0) +301000c6: 6972 flw fs2,28(sp) +301000c8: 6576 flw fa0,92(sp) +301000ca: 2072 .insn 2, 0x2072 +301000cc: 6170 flw fa2,68(a0) +301000ce: 7474 flw fa3,108(s0) +301000d0: 7265 lui tp,0xffff9 +301000d2: 0a6e slli s4,s4,0x1b +301000d4: 000d c.nop 3 + ... + +301000d8 : +301000d8: 5008c6b7 lui a3,0x5008c +301000dc: 8736 mv a4,a3 +301000de: 37c70713 addi a4,a4,892 +301000e2: 38068693 addi a3,a3,896 # 5008c380 +301000e6: 4781 li a5,0 +301000e8: 40000613 li a2,1024 +301000ec: ,-> c29c sw a5,0(a3) +301000ee: | 00072023 sw zero,0(a4) +301000f2: | 0785 addi a5,a5,1 +301000f4: '-- fec79ce3 bne a5,a2,301000ec +301000f8: 5008c637 lui a2,0x5008c +301000fc: 86b2 mv a3,a2 +301000fe: 37c68693 addi a3,a3,892 +30100102: 38060613 addi a2,a2,896 # 5008c380 +30100106: 4781 li a5,0 +30100108: 6505 lui a0,0x1 +3010010a: 20000593 li a1,512 +3010010e: ,-> 01079713 slli a4,a5,0x10 +30100112: | 8341 srli a4,a4,0x10 +30100114: | c21c sw a5,0(a2) +30100116: | 8f49 or a4,a4,a0 +30100118: | 0785 addi a5,a5,1 +3010011a: | c298 sw a4,0(a3) +3010011c: '-- feb799e3 bne a5,a1,3010010e +30100120: 5008e6b7 lui a3,0x5008e +30100124: 8736 mv a4,a3 +30100126: 37c70713 addi a4,a4,892 +3010012a: 38068693 addi a3,a3,896 # 5008e380 +3010012e: 4781 li a5,0 +30100130: 40000613 li a2,1024 +30100134: ,-> c29c sw a5,0(a3) +30100136: | 00072023 sw zero,0(a4) +3010013a: | 0785 addi a5,a5,1 +3010013c: '-- fec79ce3 bne a5,a2,30100134 +30100140: 5008e5b7 lui a1,0x5008e +30100144: 86ae mv a3,a1 +30100146: 6605 lui a2,0x1 +30100148: 38058593 addi a1,a1,896 # 5008e380 +3010014c: c0060613 addi a2,a2,-1024 # c00 <_start-0x300ff400> +30100150: 37c68693 addi a3,a3,892 +30100154: 4781 li a5,0 +30100156: 20000513 li a0,512 +3010015a: ,-> 01079713 slli a4,a5,0x10 +3010015e: | 8341 srli a4,a4,0x10 +30100160: | c19c sw a5,0(a1) +30100162: | 8f51 or a4,a4,a2 +30100164: | 0785 addi a5,a5,1 +30100166: | c298 sw a4,0(a3) +30100168: '-- fea799e3 bne a5,a0,3010015a +3010016c: 8082 ret + ... + +30100170 : +30100170: 40008737 lui a4,0x40008 +30100174: 501107b7 lui a5,0x50110 +30100178: 00070713 mv a4,a4 +3010017c: d798 sw a4,40(a5) +3010017e: 501157b7 lui a5,0x50115 +30100182: 1847a703 lw a4,388(a5) # 50115184 +30100186: 200006b7 lui a3,0x20000 +3010018a: 40000637 lui a2,0x40000 +3010018e: 8f55 or a4,a4,a3 +30100190: 18e7a223 sw a4,388(a5) +30100194: 1847a683 lw a3,388(a5) +30100198: 80000737 lui a4,0x80000 +3010019c: 00400537 lui a0,0x400 +301001a0: 8ed1 or a3,a3,a2 +301001a2: 18d7a223 sw a3,388(a5) +301001a6: 1887a683 lw a3,392(a5) +301001aa: 50120637 lui a2,0x50120 +301001ae: 501115b7 lui a1,0x50111 +301001b2: 8ed9 or a3,a3,a4 +301001b4: 18d7a423 sw a3,392(a5) +301001b8: 18c7a683 lw a3,396(a5) +301001bc: 8ef9 and a3,a3,a4 +301001be: 8ec9 or a3,a3,a0 +301001c0: 18d7a623 sw a3,396(a5) +301001c4: 4614 lw a3,8(a2) +301001c6: 8ed9 or a3,a3,a4 +301001c8: c614 sw a3,8(a2) +301001ca: 4194 lw a3,0(a1) +301001cc: 9acd andi a3,a3,-13 +301001ce: c194 sw a3,0(a1) +301001d0: 4214 lw a3,0(a2) +301001d2: 8ed9 or a3,a3,a4 +301001d4: c214 sw a3,0(a2) +301001d6: 19c7a683 lw a3,412(a5) +301001da: 8f55 or a4,a4,a3 +301001dc: 18e7ae23 sw a4,412(a5) +301001e0: ,-> 1847a703 lw a4,388(a5) +301001e4: | 00b71693 slli a3,a4,0xb +301001e8: '-- fe06dce3 bgez a3,301001e0 +301001ec: 1847a703 lw a4,388(a5) +301001f0: e00006b7 lui a3,0xe0000 +301001f4: 16fd addi a3,a3,-1 # dfffffff +301001f6: 8f75 and a4,a4,a3 +301001f8: 18e7a223 sw a4,388(a5) +301001fc: 8082 ret + ... + +30100200 : +30100200: 1141 addi sp,sp,-16 +30100202: c422 sw s0,8(sp) +30100204: 431be437 lui s0,0x431be +30100208: c606 sw ra,12(sp) +3010020a: e8340413 addi s0,s0,-381 # 431bde83 <__ulp_entry_point+0x31b5e83> +3010020e: 1fb00097 auipc ra,0x1fb00 +30100212: 34e080e7 jalr 846(ra) # 4fc0055c +30100216: 028535b3 mulhu a1,a0,s0 +3010021a: 30101537 lui a0,0x30101 +3010021e: 0b850513 addi a0,a0,184 # 301010b8 +30100222: 81c9 srli a1,a1,0x12 +30100224: 1fb00097 auipc ra,0x1fb00 +30100228: e00080e7 jalr -512(ra) # 4fc00024 +3010022c: 1fb00097 auipc ra,0x1fb00 +30100230: 334080e7 jalr 820(ra) # 4fc00560 +30100234: 028535b3 mulhu a1,a0,s0 +30100238: 4422 lw s0,8(sp) +3010023a: 40b2 lw ra,12(sp) +3010023c: 30101537 lui a0,0x30101 +30100240: 0d050513 addi a0,a0,208 # 301010d0 +30100244: 0141 addi sp,sp,16 +30100246: 81c9 srli a1,a1,0x12 +30100248: 1fb00317 auipc t1,0x1fb00 +3010024c: ddc30067 jr -548(t1) # 4fc00024 + +30100250 : +30100250: 1141 addi sp,sp,-16 +30100252: c606 sw ra,12(sp) +30100254: c422 sw s0,8(sp) +30100256: 50111737 lui a4,0x50111 +3010025a: 433c lw a5,64(a4) +3010025c: 431be437 lui s0,0x431be +30100260: e8340413 addi s0,s0,-381 # 431bde83 <__ulp_entry_point+0x31b5e83> +30100264: 9bf1 andi a5,a5,-4 +30100266: 0017e793 ori a5,a5,1 +3010026a: c33c sw a5,64(a4) +3010026c: 1fb00097 auipc ra,0x1fb00 +30100270: 2f0080e7 jalr 752(ra) # 4fc0055c +30100274: 028535b3 mulhu a1,a0,s0 +30100278: 30101537 lui a0,0x30101 +3010027c: 0b850513 addi a0,a0,184 # 301010b8 +30100280: 81c9 srli a1,a1,0x12 +30100282: 1fb00097 auipc ra,0x1fb00 +30100286: da2080e7 jalr -606(ra) # 4fc00024 +3010028a: 1fb00097 auipc ra,0x1fb00 +3010028e: 2d6080e7 jalr 726(ra) # 4fc00560 +30100292: 028535b3 mulhu a1,a0,s0 +30100296: 4422 lw s0,8(sp) +30100298: 40b2 lw ra,12(sp) +3010029a: 30101537 lui a0,0x30101 +3010029e: 0d050513 addi a0,a0,208 # 301010d0 +301002a2: 0141 addi sp,sp,16 +301002a4: 81c9 srli a1,a1,0x12 +301002a6: 1fb00317 auipc t1,0x1fb00 +301002aa: d7e30067 jr -642(t1) # 4fc00024 + ... + +301002b0 : +301002b0: 50d84737 lui a4,0x50d84 +301002b4: 501167b7 lui a5,0x50116 +301002b8: aa170713 addi a4,a4,-1375 # 50d83aa1 +301002bc: cf98 sw a4,24(a5) +301002be: 0007a023 sw zero,0(a5) # 50116000 +301002c2: 0007ac23 sw zero,24(a5) +301002c6: d398 sw a4,32(a5) +301002c8: 4fd0 lw a2,28(a5) +301002ca: 400005b7 lui a1,0x40000 +301002ce: 500c26b7 lui a3,0x500c2 +301002d2: 8e4d or a2,a2,a1 +301002d4: cfd0 sw a2,28(a5) +301002d6: 0207a023 sw zero,32(a5) +301002da: d2f8 sw a4,100(a3) +301002dc: 0406a423 sw zero,72(a3) # 500c2048 +301002e0: 0606a223 sw zero,100(a3) +301002e4: 500c37b7 lui a5,0x500c3 +301002e8: d3f8 sw a4,100(a5) +301002ea: 0407a423 sw zero,72(a5) # 500c3048 +301002ee: 0607a223 sw zero,100(a5) +301002f2: 8082 ret + ... + +301002f6 : +301002f6: 1141 addi sp,sp,-16 +301002f8: c606 sw ra,12(sp) +301002fa: c422 sw s0,8(sp) +301002fc: 0800 addi s0,sp,16 +301002fe: 501157b7 lui a5,0x50115 +30100302: 5f000737 lui a4,0x5f000 +30100306: 1ce7aa23 sw a4,468(a5) # 501151d4 +3010030a: 501157b7 lui a5,0x50115 +3010030e: 40200737 lui a4,0x40200 +30100312: 08070713 addi a4,a4,128 # 40200080 <__ulp_entry_point+0x1f8080> +30100316: 1ce7a823 sw a4,464(a5) # 501151d0 +3010031a: 501157b7 lui a5,0x50115 +3010031e: 1d07a703 lw a4,464(a5) # 501151d0 +30100322: 10076713 ori a4,a4,256 +30100326: 1ce7a823 sw a4,464(a5) +3010032a: 501157b7 lui a5,0x50115 +3010032e: 15c7a683 lw a3,348(a5) # 5011515c +30100332: 01000737 lui a4,0x1000 +30100336: 8f55 or a4,a4,a3 +30100338: 14e7ae23 sw a4,348(a5) +3010033c: 501117b7 lui a5,0x50111 +30100340: 43b4 lw a3,64(a5) +30100342: 10000737 lui a4,0x10000 +30100346: 8f55 or a4,a4,a3 +30100348: c3b8 sw a4,64(a5) +3010034a: 500e67b7 lui a5,0x500e6 +3010034e: 5b94 lw a3,48(a5) +30100350: 7775 lui a4,0xffffd +30100352: 177d addi a4,a4,-1 # ffffcfff +30100354: 8ef9 and a3,a3,a4 +30100356: 6705 lui a4,0x1 +30100358: 8f55 or a4,a4,a3 +3010035a: db98 sw a4,48(a5) +3010035c: 500e17b7 lui a5,0x500e1 +30100360: 21c78793 addi a5,a5,540 # 500e121c +30100364: 4394 lw a3,0(a5) +30100366: 7775 lui a4,0xffffd +30100368: 177d addi a4,a4,-1 # ffffcfff +3010036a: 8ef9 and a3,a3,a4 +3010036c: 6709 lui a4,0x2 +3010036e: 8f55 or a4,a4,a3 +30100370: c398 sw a4,0(a5) +30100372: 500e17b7 lui a5,0x500e1 +30100376: 21c78793 addi a5,a5,540 # 500e121c +3010037a: 43d4 lw a3,4(a5) +3010037c: 7775 lui a4,0xffffd +3010037e: 177d addi a4,a4,-1 # ffffcfff +30100380: 8ef9 and a3,a3,a4 +30100382: 6709 lui a4,0x2 +30100384: 8f55 or a4,a4,a3 +30100386: c3d8 sw a4,4(a5) +30100388: 500e17b7 lui a5,0x500e1 +3010038c: 21c78793 addi a5,a5,540 # 500e121c +30100390: 4794 lw a3,8(a5) +30100392: 7775 lui a4,0xffffd +30100394: 177d addi a4,a4,-1 # ffffcfff +30100396: 8ef9 and a3,a3,a4 +30100398: 6709 lui a4,0x2 +3010039a: 8f55 or a4,a4,a3 +3010039c: c798 sw a4,8(a5) +3010039e: 500e17b7 lui a5,0x500e1 +301003a2: 21c78793 addi a5,a5,540 # 500e121c +301003a6: 47d4 lw a3,12(a5) +301003a8: 7775 lui a4,0xffffd +301003aa: 177d addi a4,a4,-1 # ffffcfff +301003ac: 8ef9 and a3,a3,a4 +301003ae: 6709 lui a4,0x2 +301003b0: 8f55 or a4,a4,a3 +301003b2: c7d8 sw a4,12(a5) +301003b4: 500e17b7 lui a5,0x500e1 +301003b8: 21c78793 addi a5,a5,540 # 500e121c +301003bc: 4b94 lw a3,16(a5) +301003be: 7775 lui a4,0xffffd +301003c0: 177d addi a4,a4,-1 # ffffcfff +301003c2: 8ef9 and a3,a3,a4 +301003c4: 6709 lui a4,0x2 +301003c6: 8f55 or a4,a4,a3 +301003c8: cb98 sw a4,16(a5) +301003ca: 500e17b7 lui a5,0x500e1 +301003ce: 21c78793 addi a5,a5,540 # 500e121c +301003d2: 4bd4 lw a3,20(a5) +301003d4: 7775 lui a4,0xffffd +301003d6: 177d addi a4,a4,-1 # ffffcfff +301003d8: 8ef9 and a3,a3,a4 +301003da: 6709 lui a4,0x2 +301003dc: 8f55 or a4,a4,a3 +301003de: cbd8 sw a4,20(a5) +301003e0: 500e17b7 lui a5,0x500e1 +301003e4: 21c78793 addi a5,a5,540 # 500e121c +301003e8: 4f94 lw a3,24(a5) +301003ea: 7775 lui a4,0xffffd +301003ec: 177d addi a4,a4,-1 # ffffcfff +301003ee: 8ef9 and a3,a3,a4 +301003f0: 6709 lui a4,0x2 +301003f2: 8f55 or a4,a4,a3 +301003f4: cf98 sw a4,24(a5) +301003f6: 500e17b7 lui a5,0x500e1 +301003fa: 21c78793 addi a5,a5,540 # 500e121c +301003fe: 4fd4 lw a3,28(a5) +30100400: 7775 lui a4,0xffffd +30100402: 177d addi a4,a4,-1 # ffffcfff +30100404: 8ef9 and a3,a3,a4 +30100406: 6709 lui a4,0x2 +30100408: 8f55 or a4,a4,a3 +3010040a: cfd8 sw a4,28(a5) +3010040c: 500e17b7 lui a5,0x500e1 +30100410: 21c78793 addi a5,a5,540 # 500e121c +30100414: 5394 lw a3,32(a5) +30100416: 7721 lui a4,0xfffe8 +30100418: 177d addi a4,a4,-1 # fffe7fff +3010041a: 8ef9 and a3,a3,a4 +3010041c: 6741 lui a4,0x10 +3010041e: 8f55 or a4,a4,a3 +30100420: d398 sw a4,32(a5) +30100422: 500e17b7 lui a5,0x500e1 +30100426: 21c78793 addi a5,a5,540 # 500e121c +3010042a: 53d4 lw a3,36(a5) +3010042c: 7775 lui a4,0xffffd +3010042e: 177d addi a4,a4,-1 # ffffcfff +30100430: 8ef9 and a3,a3,a4 +30100432: 6709 lui a4,0x2 +30100434: 8f55 or a4,a4,a3 +30100436: d3d8 sw a4,36(a5) +30100438: 500e17b7 lui a5,0x500e1 +3010043c: 21c78793 addi a5,a5,540 # 500e121c +30100440: 5794 lw a3,40(a5) +30100442: 7775 lui a4,0xffffd +30100444: 177d addi a4,a4,-1 # ffffcfff +30100446: 8ef9 and a3,a3,a4 +30100448: 6709 lui a4,0x2 +3010044a: 8f55 or a4,a4,a3 +3010044c: d798 sw a4,40(a5) +3010044e: 500e17b7 lui a5,0x500e1 +30100452: 21c78793 addi a5,a5,540 # 500e121c +30100456: 57d4 lw a3,44(a5) +30100458: 7775 lui a4,0xffffd +3010045a: 177d addi a4,a4,-1 # ffffcfff +3010045c: 8ef9 and a3,a3,a4 +3010045e: 6709 lui a4,0x2 +30100460: 8f55 or a4,a4,a3 +30100462: d7d8 sw a4,44(a5) +30100464: 500e17b7 lui a5,0x500e1 +30100468: 21c78793 addi a5,a5,540 # 500e121c +3010046c: 5b94 lw a3,48(a5) +3010046e: 7775 lui a4,0xffffd +30100470: 177d addi a4,a4,-1 # ffffcfff +30100472: 8ef9 and a3,a3,a4 +30100474: 6709 lui a4,0x2 +30100476: 8f55 or a4,a4,a3 +30100478: db98 sw a4,48(a5) +3010047a: 500e17b7 lui a5,0x500e1 +3010047e: 21c78793 addi a5,a5,540 # 500e121c +30100482: 5bd4 lw a3,52(a5) +30100484: 7775 lui a4,0xffffd +30100486: 177d addi a4,a4,-1 # ffffcfff +30100488: 8ef9 and a3,a3,a4 +3010048a: 6709 lui a4,0x2 +3010048c: 8f55 or a4,a4,a3 +3010048e: dbd8 sw a4,52(a5) +30100490: 500e17b7 lui a5,0x500e1 +30100494: 21c78793 addi a5,a5,540 # 500e121c +30100498: 5f94 lw a3,56(a5) +3010049a: 7775 lui a4,0xffffd +3010049c: 177d addi a4,a4,-1 # ffffcfff +3010049e: 8ef9 and a3,a3,a4 +301004a0: 6709 lui a4,0x2 +301004a2: 8f55 or a4,a4,a3 +301004a4: df98 sw a4,56(a5) +301004a6: 500e17b7 lui a5,0x500e1 +301004aa: 21c78793 addi a5,a5,540 # 500e121c +301004ae: 5fd4 lw a3,60(a5) +301004b0: 7775 lui a4,0xffffd +301004b2: 177d addi a4,a4,-1 # ffffcfff +301004b4: 8ef9 and a3,a3,a4 +301004b6: 6709 lui a4,0x2 +301004b8: 8f55 or a4,a4,a3 +301004ba: dfd8 sw a4,60(a5) +301004bc: 500e17b7 lui a5,0x500e1 +301004c0: 21c78793 addi a5,a5,540 # 500e121c +301004c4: 43b4 lw a3,64(a5) +301004c6: 7775 lui a4,0xffffd +301004c8: 177d addi a4,a4,-1 # ffffcfff +301004ca: 8ef9 and a3,a3,a4 +301004cc: 6709 lui a4,0x2 +301004ce: 8f55 or a4,a4,a3 +301004d0: c3b8 sw a4,64(a5) +301004d2: 500e17b7 lui a5,0x500e1 +301004d6: 21c78793 addi a5,a5,540 # 500e121c +301004da: 43f4 lw a3,68(a5) +301004dc: 7775 lui a4,0xffffd +301004de: 177d addi a4,a4,-1 # ffffcfff +301004e0: 8ef9 and a3,a3,a4 +301004e2: 6709 lui a4,0x2 +301004e4: 8f55 or a4,a4,a3 +301004e6: c3f8 sw a4,68(a5) +301004e8: 500e17b7 lui a5,0x500e1 +301004ec: 21c78793 addi a5,a5,540 # 500e121c +301004f0: 47b4 lw a3,72(a5) +301004f2: 7775 lui a4,0xffffd +301004f4: 177d addi a4,a4,-1 # ffffcfff +301004f6: 8ef9 and a3,a3,a4 +301004f8: 6709 lui a4,0x2 +301004fa: 8f55 or a4,a4,a3 +301004fc: c7b8 sw a4,72(a5) +301004fe: 500e17b7 lui a5,0x500e1 +30100502: 21c78793 addi a5,a5,540 # 500e121c +30100506: 47f4 lw a3,76(a5) +30100508: 7721 lui a4,0xfffe8 +3010050a: 177d addi a4,a4,-1 # fffe7fff +3010050c: 8ef9 and a3,a3,a4 +3010050e: 6741 lui a4,0x10 +30100510: 8f55 or a4,a4,a3 +30100512: c7f8 sw a4,76(a5) +30100514: 500e17b7 lui a5,0x500e1 +30100518: 21c78793 addi a5,a5,540 # 500e121c +3010051c: 5398 lw a4,32(a5) +3010051e: 00176713 ori a4,a4,1 +30100522: d398 sw a4,32(a5) +30100524: 500e17b7 lui a5,0x500e1 +30100528: 21c78793 addi a5,a5,540 # 500e121c +3010052c: 47f8 lw a4,76(a5) +3010052e: 00176713 ori a4,a4,1 +30100532: c7f8 sw a4,76(a5) +30100534: 5008e7b7 lui a5,0x5008e +30100538: 00078793 mv a5,a5 +3010053c: 1a07a703 lw a4,416(a5) # 5008e1a0 +30100540: 00176713 ori a4,a4,1 +30100544: 1ae7a023 sw a4,416(a5) +30100548: 5008e7b7 lui a5,0x5008e +3010054c: 00078793 mv a5,a5 +30100550: 1a07a703 lw a4,416(a5) # 5008e1a0 +30100554: f8377713 andi a4,a4,-125 +30100558: 00c76713 ori a4,a4,12 +3010055c: 1ae7a023 sw a4,416(a5) +30100560: 5008e7b7 lui a5,0x5008e +30100564: 00078793 mv a5,a5 +30100568: 1a07a703 lw a4,416(a5) # 5008e1a0 +3010056c: 00276713 ori a4,a4,2 +30100570: 1ae7a023 sw a4,416(a5) +30100574: 5008e7b7 lui a5,0x5008e +30100578: 00078793 mv a5,a5 +3010057c: 1a07a683 lw a3,416(a5) # 5008e1a0 +30100580: 777d lui a4,0xfffff +30100582: 07f70713 addi a4,a4,127 # fffff07f +30100586: 8f75 and a4,a4,a3 +30100588: 18076713 ori a4,a4,384 +3010058c: 1ae7a023 sw a4,416(a5) +30100590: 5008e7b7 lui a5,0x5008e +30100594: 00078793 mv a5,a5 +30100598: 1a07a683 lw a3,416(a5) # 5008e1a0 +3010059c: 82000737 lui a4,0x82000 +301005a0: 177d addi a4,a4,-1 # 81ffffff +301005a2: 8ef9 and a3,a3,a4 +301005a4: 04000737 lui a4,0x4000 +301005a8: 8f55 or a4,a4,a3 +301005aa: 1ae7a023 sw a4,416(a5) +301005ae: 5008e7b7 lui a5,0x5008e +301005b2: 00078793 mv a5,a5 +301005b6: 1a07a683 lw a3,416(a5) # 5008e1a0 +301005ba: 80000737 lui a4,0x80000 +301005be: 8f55 or a4,a4,a3 +301005c0: 1ae7a023 sw a4,416(a5) +301005c4: 5008e7b7 lui a5,0x5008e +301005c8: 00078793 mv a5,a5 +301005cc: 1747a683 lw a3,372(a5) # 5008e174 +301005d0: 000c0737 lui a4,0xc0 +301005d4: 8f55 or a4,a4,a3 +301005d6: 16e7aa23 sw a4,372(a5) +301005da: 5008e7b7 lui a5,0x5008e +301005de: 00078793 mv a5,a5 +301005e2: 6741 lui a4,0x10 +301005e4: 0705 addi a4,a4,1 # 10001 <_start-0x300effff> +301005e6: cbb8 sw a4,80(a5) +301005e8: 5008f7b7 lui a5,0x5008f +301005ec: 00078793 mv a5,a5 +301005f0: 6741 lui a4,0x10 +301005f2: 0705 addi a4,a4,1 # 10001 <_start-0x300effff> +301005f4: cbd8 sw a4,20(a5) +301005f6: 5008e7b7 lui a5,0x5008e +301005fa: 00078793 mv a5,a5 +301005fe: 1907a703 lw a4,400(a5) # 5008e190 +30100602: 02076713 ori a4,a4,32 +30100606: 18e7a823 sw a4,400(a5) +3010060a: 5008e7b7 lui a5,0x5008e +3010060e: 00078793 mv a5,a5 +30100612: 1807a703 lw a4,384(a5) # 5008e180 +30100616: 02076713 ori a4,a4,32 +3010061a: 18e7a023 sw a4,384(a5) +3010061e: 301017b7 lui a5,0x30101 +30100622: 0e878793 addi a5,a5,232 # 301010e8 +30100626: 0007c703 lbu a4,0(a5) +3010062a: 02076713 ori a4,a4,32 +3010062e: 00e78023 sb a4,0(a5) +30100632: 301017b7 lui a5,0x30101 +30100636: 0e878793 addi a5,a5,232 # 301010e8 +3010063a: 0007c703 lbu a4,0(a5) +3010063e: 9b0d andi a4,a4,-29 +30100640: 01076713 ori a4,a4,16 +30100644: 00e78023 sb a4,0(a5) +30100648: 301017b7 lui a5,0x30101 +3010064c: 0e878793 addi a5,a5,232 # 301010e8 +30100650: 0007c703 lbu a4,0(a5) +30100654: 9b71 andi a4,a4,-4 +30100656: 00e78023 sb a4,0(a5) +3010065a: 301017b7 lui a5,0x30101 +3010065e: 0e878793 addi a5,a5,232 # 301010e8 +30100662: 0047c703 lbu a4,4(a5) +30100666: 8b7d andi a4,a4,31 +30100668: 02076713 ori a4,a4,32 +3010066c: 00e78223 sb a4,4(a5) +30100670: 301017b7 lui a5,0x30101 +30100674: 0e878793 addi a5,a5,232 # 301010e8 +30100678: 0057c703 lbu a4,5(a5) +3010067c: 00376713 ori a4,a4,3 +30100680: 00e782a3 sb a4,5(a5) +30100684: 301017b7 lui a5,0x30101 +30100688: 0e878793 addi a5,a5,232 # 301010e8 +3010068c: 0057c703 lbu a4,5(a5) +30100690: 9b6d andi a4,a4,-5 +30100692: 00e782a3 sb a4,5(a5) +30100696: 301017b7 lui a5,0x30101 +3010069a: 0e878793 addi a5,a5,232 # 301010e8 +3010069e: 0057c703 lbu a4,5(a5) +301006a2: 00876713 ori a4,a4,8 +301006a6: 00e782a3 sb a4,5(a5) +301006aa: 301017b7 lui a5,0x30101 +301006ae: 0e878793 addi a5,a5,232 # 301010e8 +301006b2: 0057c703 lbu a4,5(a5) +301006b6: 04076713 ori a4,a4,64 +301006ba: 00e782a3 sb a4,5(a5) +301006be: 301017b7 lui a5,0x30101 +301006c2: 0e878593 addi a1,a5,232 # 301010e8 +301006c6: 450d li a0,3 +301006c8: 2385 jal 30100c28 +301006ca: 450d li a0,3 +301006cc: 0b1000ef jal 30100f7c +301006d0: 87aa mv a5,a0 +301006d2: ,-- cb99 beqz a5,301006e8 +301006d4: | 301007b7 lui a5,0x30100 +301006d8: | 07078513 addi a0,a5,112 # 30100070 <_start+0x70> +301006dc: | 1fb00097 auipc ra,0x1fb00 +301006e0: | 948080e7 jalr -1720(ra) # 4fc00024 +301006e4: | 57fd li a5,-1 +301006e6: ,--|-- a841 j 30100776 +301006e8: | '-> 301017b7 lui a5,0x30101 +301006ec: | 0e878593 addi a1,a5,232 # 301010e8 +301006f0: | 450d li a0,3 +301006f2: | 10d000ef jal 30100ffe +301006f6: | 301017b7 lui a5,0x30101 +301006fa: | 0e878793 addi a5,a5,232 # 301010e8 +301006fe: | 0017c783 lbu a5,1(a5) +30100702: | 8bfd andi a5,a5,31 +30100704: | 0ff7f713 zext.b a4,a5 +30100708: | 47b5 li a5,13 +3010070a: | ,-- 04f70063 beq a4,a5,3010074a +3010070e: | | 301017b7 lui a5,0x30101 +30100712: | | 0e878793 addi a5,a5,232 # 301010e8 +30100716: | | 0017c783 lbu a5,1(a5) +3010071a: | | 8bfd andi a5,a5,31 +3010071c: | | 0ff7f713 zext.b a4,a5 +30100720: | | 47e9 li a5,26 +30100722: | +-- 02f70463 beq a4,a5,3010074a +30100726: | | 301017b7 lui a5,0x30101 +3010072a: | | 0e878793 addi a5,a5,232 # 301010e8 +3010072e: | | 439c lw a5,0(a5) +30100730: | | 83a1 srli a5,a5,0x8 +30100732: | | 8bfd andi a5,a5,31 +30100734: | | 0ff7f793 zext.b a5,a5 +30100738: | | 85be mv a1,a5 +3010073a: | | 301007b7 lui a5,0x30100 +3010073e: | | 09078513 addi a0,a5,144 # 30100090 <_start+0x90> +30100742: | | 1fb00097 auipc ra,0x1fb00 +30100746: | | 8e2080e7 jalr -1822(ra) # 4fc00024 +3010074a: | '-> 281d jal 30100780 +3010074c: | 5008e7b7 lui a5,0x5008e +30100750: | 00078793 mv a5,a5 +30100754: | 0d87a703 lw a4,216(a5) # 5008e0d8 +30100758: | 00276713 ori a4,a4,2 +3010075c: | 0ce7ac23 sw a4,216(a5) +30100760: | 5008f7b7 lui a5,0x5008f +30100764: | 00078793 mv a5,a5 +30100768: | 0d47a703 lw a4,212(a5) # 5008f0d4 +3010076c: | 00276713 ori a4,a4,2 +30100770: | 0ce7aa23 sw a4,212(a5) +30100774: | 4781 li a5,0 +30100776: '----> 853e mv a0,a5 +30100778: 40b2 lw ra,12(sp) +3010077a: 4422 lw s0,8(sp) +3010077c: 0141 addi sp,sp,16 +3010077e: 8082 ret + +30100780 : +30100780: 7171 addi sp,sp,-176 +30100782: d722 sw s0,172(sp) +30100784: 1900 addi s0,sp,176 +30100786: 4789 li a5,2 +30100788: f6f42623 sw a5,-148(s0) +3010078c: 47c1 li a5,16 +3010078e: f6f42423 sw a5,-152(s0) +30100792: 67a1 lui a5,0x8 +30100794: 08078793 addi a5,a5,128 # 8080 <_start-0x300f7f80> +30100798: f6f42223 sw a5,-156(s0) +3010079c: 5008e7b7 lui a5,0x5008e +301007a0: 00078793 mv a5,a5 +301007a4: 43b4 lw a3,64(a5) +301007a6: 00100737 lui a4,0x100 +301007aa: 8f55 or a4,a4,a3 +301007ac: c3b8 sw a4,64(a5) +301007ae: f6842783 lw a5,-152(s0) +301007b2: 0ff7f793 zext.b a5,a5 +301007b6: 17fd addi a5,a5,-1 # 5008dfff +301007b8: 0ff7f793 zext.b a5,a5 +301007bc: 8bbd andi a5,a5,15 +301007be: 0ff7f713 zext.b a4,a5 +301007c2: 5008e7b7 lui a5,0x5008e +301007c6: 00078793 mv a5,a5 +301007ca: 0772 slli a4,a4,0x1c +301007cc: 47f0 lw a2,76(a5) +301007ce: 100006b7 lui a3,0x10000 +301007d2: 16fd addi a3,a3,-1 # fffffff <_start-0x20100001> +301007d4: 8ef1 and a3,a3,a2 +301007d6: 8f55 or a4,a4,a3 +301007d8: c7f8 sw a4,76(a5) +301007da: 5008e7b7 lui a5,0x5008e +301007de: 00078793 mv a5,a5 +301007e2: 47fc lw a5,76(a5) +301007e4: f6f42023 sw a5,-160(s0) +301007e8: f6042783 lw a5,-160(s0) +301007ec: f4f42e23 sw a5,-164(s0) +301007f0: f6442783 lw a5,-156(s0) +301007f4: 07c2 slli a5,a5,0x10 +301007f6: 83c1 srli a5,a5,0x10 +301007f8: f4f41e23 sh a5,-164(s0) +301007fc: f5c42703 lw a4,-164(s0) +30100800: 5008e7b7 lui a5,0x5008e +30100804: 00078793 mv a5,a5 +30100808: c7f8 sw a4,76(a5) +3010080a: 0001 nop +3010080c: 4789 li a5,2 +3010080e: f6f42e23 sw a5,-132(s0) +30100812: 47c1 li a5,16 +30100814: f6f42c23 sw a5,-136(s0) +30100818: f6042a23 sw zero,-140(s0) +3010081c: 5008e7b7 lui a5,0x5008e +30100820: 00078793 mv a5,a5 +30100824: 43b8 lw a4,64(a5) +30100826: 02076713 ori a4,a4,32 +3010082a: c3b8 sw a4,64(a5) +3010082c: f7842783 lw a5,-136(s0) +30100830: 0ff7f793 zext.b a5,a5 +30100834: 17fd addi a5,a5,-1 # 5008dfff +30100836: 0ff7f793 zext.b a5,a5 +3010083a: 8bbd andi a5,a5,15 +3010083c: 0ff7f713 zext.b a4,a5 +30100840: 5008e7b7 lui a5,0x5008e +30100844: 00078793 mv a5,a5 +30100848: 0772 slli a4,a4,0x1c +3010084a: 47b0 lw a2,72(a5) +3010084c: 100006b7 lui a3,0x10000 +30100850: 16fd addi a3,a3,-1 # fffffff <_start-0x20100001> +30100852: 8ef1 and a3,a3,a2 +30100854: 8f55 or a4,a4,a3 +30100856: c7b8 sw a4,72(a5) +30100858: 5008e7b7 lui a5,0x5008e +3010085c: 00078793 mv a5,a5 +30100860: 47bc lw a5,72(a5) +30100862: f6f42823 sw a5,-144(s0) +30100866: f7042783 lw a5,-144(s0) +3010086a: f4f42c23 sw a5,-168(s0) +3010086e: f7442783 lw a5,-140(s0) +30100872: 07c2 slli a5,a5,0x10 +30100874: 83c1 srli a5,a5,0x10 +30100876: f4f41c23 sh a5,-168(s0) +3010087a: f5842703 lw a4,-168(s0) +3010087e: 5008e7b7 lui a5,0x5008e +30100882: 00078793 mv a5,a5 +30100886: c7b8 sw a4,72(a5) +30100888: 0001 nop +3010088a: 4789 li a5,2 +3010088c: f8f42223 sw a5,-124(s0) +30100890: 02000793 li a5,32 +30100894: f8f42023 sw a5,-128(s0) +30100898: f8042783 lw a5,-128(s0) +3010089c: 0ff7f793 zext.b a5,a5 +301008a0: 17fd addi a5,a5,-1 # 5008dfff +301008a2: 0ff7f793 zext.b a5,a5 +301008a6: 03f7f793 andi a5,a5,63 +301008aa: 0ff7f713 zext.b a4,a5 +301008ae: 5008e7b7 lui a5,0x5008e +301008b2: 00078793 mv a5,a5 +301008b6: 03f77713 andi a4,a4,63 +301008ba: 073a slli a4,a4,0xe +301008bc: 43b0 lw a2,64(a5) +301008be: fff046b7 lui a3,0xfff04 +301008c2: 16fd addi a3,a3,-1 # fff03fff +301008c4: 8ef1 and a3,a3,a2 +301008c6: 8f55 or a4,a4,a3 +301008c8: c3b8 sw a4,64(a5) +301008ca: 0001 nop +301008cc: 4789 li a5,2 +301008ce: f8f42623 sw a5,-116(s0) +301008d2: 4785 li a5,1 +301008d4: f8f405a3 sb a5,-117(s0) +301008d8: 5008e7b7 lui a5,0x5008e +301008dc: 00078793 mv a5,a5 +301008e0: f8b44703 lbu a4,-117(s0) +301008e4: 8b05 andi a4,a4,1 +301008e6: 43b4 lw a3,64(a5) +301008e8: 9af9 andi a3,a3,-2 +301008ea: 8f55 or a4,a4,a3 +301008ec: c3b8 sw a4,64(a5) +301008ee: 0001 nop +301008f0: 4789 li a5,2 +301008f2: f8f42a23 sw a5,-108(s0) +301008f6: 47b1 li a5,12 +301008f8: f8f42823 sw a5,-112(s0) +301008fc: 5008e7b7 lui a5,0x5008e +30100900: 00078793 mv a5,a5 +30100904: 43b8 lw a4,64(a5) +30100906: 00876713 ori a4,a4,8 +3010090a: c3b8 sw a4,64(a5) +3010090c: f9042783 lw a5,-112(s0) +30100910: 0ff7f793 zext.b a5,a5 +30100914: 17fd addi a5,a5,-1 # 5008dfff +30100916: 0ff7f793 zext.b a5,a5 +3010091a: 03f7f793 andi a5,a5,63 +3010091e: 0ff7f713 zext.b a4,a5 +30100922: 5008e7b7 lui a5,0x5008e +30100926: 00078793 mv a5,a5 +3010092a: 03f77713 andi a4,a4,63 +3010092e: 075a slli a4,a4,0x16 +30100930: 43b0 lw a2,64(a5) +30100932: f04006b7 lui a3,0xf0400 +30100936: 16fd addi a3,a3,-1 # f03fffff +30100938: 8ef1 and a3,a3,a2 +3010093a: 8f55 or a4,a4,a3 +3010093c: c3b8 sw a4,64(a5) +3010093e: 0001 nop +30100940: 4789 li a5,2 +30100942: f8f42e23 sw a5,-100(s0) +30100946: 47e9 li a5,26 +30100948: f8f42c23 sw a5,-104(s0) +3010094c: 5008e7b7 lui a5,0x5008e +30100950: 00078793 mv a5,a5 +30100954: 43b8 lw a4,64(a5) +30100956: 01076713 ori a4,a4,16 +3010095a: c3b8 sw a4,64(a5) +3010095c: f9842783 lw a5,-104(s0) +30100960: 0ff7f793 zext.b a5,a5 +30100964: 17fd addi a5,a5,-1 # 5008dfff +30100966: 0ff7f793 zext.b a5,a5 +3010096a: 03f7f793 andi a5,a5,63 +3010096e: 0ff7f713 zext.b a4,a5 +30100972: 5008e7b7 lui a5,0x5008e +30100976: 00078793 mv a5,a5 +3010097a: 03f77713 andi a4,a4,63 +3010097e: 071a slli a4,a4,0x6 +30100980: 43b0 lw a2,64(a5) +30100982: 76fd lui a3,0xfffff +30100984: 03f68693 addi a3,a3,63 # fffff03f +30100988: 8ef1 and a3,a3,a2 +3010098a: 8f55 or a4,a4,a3 +3010098c: c3b8 sw a4,64(a5) +3010098e: 0001 nop +30100990: 4789 li a5,2 +30100992: faf42223 sw a5,-92(s0) +30100996: 4785 li a5,1 +30100998: faf401a3 sb a5,-93(s0) +3010099c: fa442703 lw a4,-92(s0) +301009a0: 4789 li a5,2 +301009a2: ,-- 02f71163 bne a4,a5,301009c4 +301009a6: | 5008e7b7 lui a5,0x5008e +301009aa: | 00078793 mv a5,a5 +301009ae: | fa344703 lbu a4,-93(s0) +301009b2: | 8b05 andi a4,a4,1 +301009b4: | 0706 slli a4,a4,0x1 +301009b6: | 0d87a683 lw a3,216(a5) # 5008e0d8 +301009ba: | 9af5 andi a3,a3,-3 +301009bc: | 8f55 or a4,a4,a3 +301009be: | 0ce7ac23 sw a4,216(a5) +301009c2: ,--|-- a025 j 301009ea +301009c4: | '-> fa442703 lw a4,-92(s0) +301009c8: | 478d li a5,3 +301009ca: +----- 02f71063 bne a4,a5,301009ea +301009ce: | 5008f7b7 lui a5,0x5008f +301009d2: | 00078793 mv a5,a5 +301009d6: | fa344703 lbu a4,-93(s0) +301009da: | 8b05 andi a4,a4,1 +301009dc: | 0706 slli a4,a4,0x1 +301009de: | 0d47a683 lw a3,212(a5) # 5008f0d4 +301009e2: | 9af5 andi a3,a3,-3 +301009e4: | 8f55 or a4,a4,a3 +301009e6: | 0ce7aa23 sw a4,212(a5) +301009ea: '----> 0001 nop +301009ec: 4789 li a5,2 +301009ee: faf42623 sw a5,-84(s0) +301009f2: 4785 li a5,1 +301009f4: faf405a3 sb a5,-85(s0) +301009f8: 5008e7b7 lui a5,0x5008e +301009fc: 00078793 mv a5,a5 +30100a00: fab44703 lbu a4,-85(s0) +30100a04: 8b05 andi a4,a4,1 +30100a06: 075e slli a4,a4,0x17 +30100a08: 43f0 lw a2,68(a5) +30100a0a: ff8006b7 lui a3,0xff800 +30100a0e: 16fd addi a3,a3,-1 # ff7fffff +30100a10: 8ef1 and a3,a3,a2 +30100a12: 8f55 or a4,a4,a3 +30100a14: c3f8 sw a4,68(a5) +30100a16: 0001 nop +30100a18: 4789 li a5,2 +30100a1a: faf42a23 sw a5,-76(s0) +30100a1e: fa0409a3 sb zero,-77(s0) +30100a22: 5008e7b7 lui a5,0x5008e +30100a26: 00078793 mv a5,a5 +30100a2a: fb344703 lbu a4,-77(s0) +30100a2e: 8b05 andi a4,a4,1 +30100a30: 070e slli a4,a4,0x3 +30100a32: 0d87a683 lw a3,216(a5) # 5008e0d8 +30100a36: 9add andi a3,a3,-9 +30100a38: 8f55 or a4,a4,a3 +30100a3a: 0ce7ac23 sw a4,216(a5) +30100a3e: 0001 nop +30100a40: 4789 li a5,2 +30100a42: faf42e23 sw a5,-68(s0) +30100a46: fa040da3 sb zero,-69(s0) +30100a4a: 5008e7b7 lui a5,0x5008e +30100a4e: 00078793 mv a5,a5 +30100a52: fbb44703 lbu a4,-69(s0) +30100a56: 8b05 andi a4,a4,1 +30100a58: 070a slli a4,a4,0x2 +30100a5a: 0d87a683 lw a3,216(a5) # 5008e0d8 +30100a5e: 9aed andi a3,a3,-5 +30100a60: 8f55 or a4,a4,a3 +30100a62: 0ce7ac23 sw a4,216(a5) +30100a66: 0001 nop +30100a68: 4789 li a5,2 +30100a6a: fcf42223 sw a5,-60(s0) +30100a6e: 4785 li a5,1 +30100a70: fcf401a3 sb a5,-61(s0) +30100a74: 5008e7b7 lui a5,0x5008e +30100a78: 00078793 mv a5,a5 +30100a7c: fc344703 lbu a4,-61(s0) +30100a80: 8b05 andi a4,a4,1 +30100a82: 0d87a683 lw a3,216(a5) # 5008e0d8 +30100a86: 9af9 andi a3,a3,-2 +30100a88: 8f55 or a4,a4,a3 +30100a8a: 0ce7ac23 sw a4,216(a5) +30100a8e: 0001 nop +30100a90: 4789 li a5,2 +30100a92: fcf42623 sw a5,-52(s0) +30100a96: 4785 li a5,1 +30100a98: fcf405a3 sb a5,-53(s0) +30100a9c: 5008e7b7 lui a5,0x5008e +30100aa0: 00078793 mv a5,a5 +30100aa4: fcb44703 lbu a4,-53(s0) +30100aa8: 8b05 andi a4,a4,1 +30100aaa: 0756 slli a4,a4,0x15 +30100aac: 43b0 lw a2,64(a5) +30100aae: ffe006b7 lui a3,0xffe00 +30100ab2: 16fd addi a3,a3,-1 # ffdfffff +30100ab4: 8ef1 and a3,a3,a2 +30100ab6: 8f55 or a4,a4,a3 +30100ab8: c3b8 sw a4,64(a5) +30100aba: 5008e7b7 lui a5,0x5008e +30100abe: 00078793 mv a5,a5 +30100ac2: fcb44703 lbu a4,-53(s0) +30100ac6: 8b05 andi a4,a4,1 +30100ac8: 0756 slli a4,a4,0x15 +30100aca: 43f0 lw a2,68(a5) +30100acc: ffe006b7 lui a3,0xffe00 +30100ad0: 16fd addi a3,a3,-1 # ffdfffff +30100ad2: 8ef1 and a3,a3,a2 +30100ad4: 8f55 or a4,a4,a3 +30100ad6: c3f8 sw a4,68(a5) +30100ad8: 5008e7b7 lui a5,0x5008e +30100adc: 00078793 mv a5,a5 +30100ae0: fcb44703 lbu a4,-53(s0) +30100ae4: 8b05 andi a4,a4,1 +30100ae6: 0752 slli a4,a4,0x14 +30100ae8: 43f0 lw a2,68(a5) +30100aea: fff006b7 lui a3,0xfff00 +30100aee: 16fd addi a3,a3,-1 # ffefffff +30100af0: 8ef1 and a3,a3,a2 +30100af2: 8f55 or a4,a4,a3 +30100af4: c3f8 sw a4,68(a5) +30100af6: 5008e7b7 lui a5,0x5008e +30100afa: 00078793 mv a5,a5 +30100afe: fcb44703 lbu a4,-53(s0) +30100b02: 8b05 andi a4,a4,1 +30100b04: 074e slli a4,a4,0x13 +30100b06: 43f0 lw a2,68(a5) +30100b08: fff806b7 lui a3,0xfff80 +30100b0c: 16fd addi a3,a3,-1 # fff7ffff +30100b0e: 8ef1 and a3,a3,a2 +30100b10: 8f55 or a4,a4,a3 +30100b12: c3f8 sw a4,68(a5) +30100b14: 5008e7b7 lui a5,0x5008e +30100b18: 00078793 mv a5,a5 +30100b1c: fcb44703 lbu a4,-53(s0) +30100b20: 8b05 andi a4,a4,1 +30100b22: 074a slli a4,a4,0x12 +30100b24: 43f0 lw a2,68(a5) +30100b26: fffc06b7 lui a3,0xfffc0 +30100b2a: 16fd addi a3,a3,-1 # fffbffff +30100b2c: 8ef1 and a3,a3,a2 +30100b2e: 8f55 or a4,a4,a3 +30100b30: c3f8 sw a4,68(a5) +30100b32: 0001 nop +30100b34: 4789 li a5,2 +30100b36: fcf42a23 sw a5,-44(s0) +30100b3a: 4785 li a5,1 +30100b3c: fcf409a3 sb a5,-45(s0) +30100b40: 5008e7b7 lui a5,0x5008e +30100b44: 00078793 mv a5,a5 +30100b48: fd344703 lbu a4,-45(s0) +30100b4c: 8b05 andi a4,a4,1 +30100b4e: 076a slli a4,a4,0x1a +30100b50: 43f0 lw a2,68(a5) +30100b52: fc0006b7 lui a3,0xfc000 +30100b56: 16fd addi a3,a3,-1 # fbffffff +30100b58: 8ef1 and a3,a3,a2 +30100b5a: 8f55 or a4,a4,a3 +30100b5c: c3f8 sw a4,68(a5) +30100b5e: 5008e7b7 lui a5,0x5008e +30100b62: 00078793 mv a5,a5 +30100b66: fd344703 lbu a4,-45(s0) +30100b6a: 8b05 andi a4,a4,1 +30100b6c: 076e slli a4,a4,0x1b +30100b6e: 43f0 lw a2,68(a5) +30100b70: f80006b7 lui a3,0xf8000 +30100b74: 16fd addi a3,a3,-1 # f7ffffff +30100b76: 8ef1 and a3,a3,a2 +30100b78: 8f55 or a4,a4,a3 +30100b7a: c3f8 sw a4,68(a5) +30100b7c: 0001 nop +30100b7e: 4789 li a5,2 +30100b80: fcf42e23 sw a5,-36(s0) +30100b84: 4785 li a5,1 +30100b86: fcf40da3 sb a5,-37(s0) +30100b8a: 5008e7b7 lui a5,0x5008e +30100b8e: 00078793 mv a5,a5 +30100b92: fdb44703 lbu a4,-37(s0) +30100b96: 8b05 andi a4,a4,1 +30100b98: 5fd4 lw a3,60(a5) +30100b9a: 9af9 andi a3,a3,-2 +30100b9c: 8f55 or a4,a4,a3 +30100b9e: dfd8 sw a4,60(a5) +30100ba0: fdb44783 lbu a5,-37(s0) +30100ba4: 0017c793 xori a5,a5,1 +30100ba8: 0ff7f713 zext.b a4,a5 +30100bac: 5008e7b7 lui a5,0x5008e +30100bb0: 00078793 mv a5,a5 +30100bb4: 077e slli a4,a4,0x1f +30100bb6: 5fd0 lw a2,60(a5) +30100bb8: 800006b7 lui a3,0x80000 +30100bbc: fff6c693 not a3,a3 +30100bc0: 8ef1 and a3,a3,a2 +30100bc2: 8f55 or a4,a4,a3 +30100bc4: dfd8 sw a4,60(a5) +30100bc6: 0001 nop +30100bc8: 4789 li a5,2 +30100bca: fef42223 sw a5,-28(s0) +30100bce: 4785 li a5,1 +30100bd0: fef401a3 sb a5,-29(s0) +30100bd4: 5008e7b7 lui a5,0x5008e +30100bd8: 00078793 mv a5,a5 +30100bdc: fe344703 lbu a4,-29(s0) +30100be0: 8b05 andi a4,a4,1 +30100be2: 076a slli a4,a4,0x1a +30100be4: 47d0 lw a2,12(a5) +30100be6: fc0006b7 lui a3,0xfc000 +30100bea: 16fd addi a3,a3,-1 # fbffffff +30100bec: 8ef1 and a3,a3,a2 +30100bee: 8f55 or a4,a4,a3 +30100bf0: c7d8 sw a4,12(a5) +30100bf2: 0001 nop +30100bf4: 4789 li a5,2 +30100bf6: fef42623 sw a5,-20(s0) +30100bfa: 4785 li a5,1 +30100bfc: fef405a3 sb a5,-21(s0) +30100c00: 5008e7b7 lui a5,0x5008e +30100c04: 00078793 mv a5,a5 +30100c08: feb44703 lbu a4,-21(s0) +30100c0c: 8b05 andi a4,a4,1 +30100c0e: 0766 slli a4,a4,0x19 +30100c10: 47d0 lw a2,12(a5) +30100c12: fe0006b7 lui a3,0xfe000 +30100c16: 16fd addi a3,a3,-1 # fdffffff +30100c18: 8ef1 and a3,a3,a2 +30100c1a: 8f55 or a4,a4,a3 +30100c1c: c7d8 sw a4,12(a5) +30100c1e: 0001 nop +30100c20: 0001 nop +30100c22: 543a lw s0,172(sp) +30100c24: 614d addi sp,sp,176 +30100c26: 8082 ret + +30100c28 : +30100c28: 715d addi sp,sp,-80 +30100c2a: c686 sw ra,76(sp) +30100c2c: c4a2 sw s0,72(sp) +30100c2e: 0880 addi s0,sp,80 +30100c30: fca42623 sw a0,-52(s0) +30100c34: fcb42423 sw a1,-56(s0) +30100c38: 47c1 li a5,16 +30100c3a: fef42623 sw a5,-20(s0) +30100c3e: fe042423 sw zero,-24(s0) +30100c42: 02000793 li a5,32 +30100c46: fef42223 sw a5,-28(s0) +30100c4a: 47b1 li a5,12 +30100c4c: fef42023 sw a5,-32(s0) +30100c50: fc042a23 sw zero,-44(s0) +30100c54: fc041c23 sh zero,-40(s0) +30100c58: 47c1 li a5,16 +30100c5a: fcf42e23 sw a5,-36(s0) +30100c5e: fcc42503 lw a0,-52(s0) +30100c62: fec42603 lw a2,-20(s0) +30100c66: fe442703 lw a4,-28(s0) +30100c6a: fe042683 lw a3,-32(s0) +30100c6e: fdc42783 lw a5,-36(s0) +30100c72: c402 sw zero,8(sp) +30100c74: c23e sw a5,4(sp) +30100c76: fd440793 addi a5,s0,-44 +30100c7a: c03e sw a5,0(sp) +30100c7c: 4881 li a7,0 +30100c7e: 4801 li a6,0 +30100c80: 87b6 mv a5,a3 +30100c82: fe842683 lw a3,-24(s0) +30100c86: 6591 lui a1,0x4 +30100c88: 04058593 addi a1,a1,64 # 4040 <_start-0x300fbfc0> +30100c8c: 2c05 jal 30100ebc +30100c8e: 4791 li a5,4 +30100c90: fef42423 sw a5,-24(s0) +30100c94: fcc42503 lw a0,-52(s0) +30100c98: fec42603 lw a2,-20(s0) +30100c9c: fe442703 lw a4,-28(s0) +30100ca0: fe042683 lw a3,-32(s0) +30100ca4: fdc42783 lw a5,-36(s0) +30100ca8: c402 sw zero,8(sp) +30100caa: c23e sw a5,4(sp) +30100cac: fd440793 addi a5,s0,-44 +30100cb0: 0791 addi a5,a5,4 +30100cb2: c03e sw a5,0(sp) +30100cb4: 4881 li a7,0 +30100cb6: 4801 li a6,0 +30100cb8: 87b6 mv a5,a3 +30100cba: fe842683 lw a3,-24(s0) +30100cbe: 6591 lui a1,0x4 +30100cc0: 04058593 addi a1,a1,64 # 4040 <_start-0x300fbfc0> +30100cc4: 2ae5 jal 30100ebc +30100cc6: fc842783 lw a5,-56(s0) +30100cca: 0007c783 lbu a5,0(a5) +30100cce: 8395 srli a5,a5,0x5 +30100cd0: 8b85 andi a5,a5,1 +30100cd2: 0ff7f793 zext.b a5,a5 +30100cd6: 8b85 andi a5,a5,1 +30100cd8: 00579693 slli a3,a5,0x5 +30100cdc: fd444783 lbu a5,-44(s0) +30100ce0: fdf7f793 andi a5,a5,-33 +30100ce4: 873e mv a4,a5 +30100ce6: 87b6 mv a5,a3 +30100ce8: 8fd9 or a5,a5,a4 +30100cea: fcf40a23 sb a5,-44(s0) +30100cee: fc842783 lw a5,-56(s0) +30100cf2: 0007c783 lbu a5,0(a5) +30100cf6: 8389 srli a5,a5,0x2 +30100cf8: 8b9d andi a5,a5,7 +30100cfa: 0ff7f793 zext.b a5,a5 +30100cfe: 8b9d andi a5,a5,7 +30100d00: 00279693 slli a3,a5,0x2 +30100d04: fd444783 lbu a5,-44(s0) +30100d08: 9b8d andi a5,a5,-29 +30100d0a: 873e mv a4,a5 +30100d0c: 87b6 mv a5,a3 +30100d0e: 8fd9 or a5,a5,a4 +30100d10: fcf40a23 sb a5,-44(s0) +30100d14: fc842783 lw a5,-56(s0) +30100d18: 0007c783 lbu a5,0(a5) +30100d1c: 8b8d andi a5,a5,3 +30100d1e: 0ff7f793 zext.b a5,a5 +30100d22: 0037f693 andi a3,a5,3 +30100d26: fd444783 lbu a5,-44(s0) +30100d2a: 9bf1 andi a5,a5,-4 +30100d2c: 873e mv a4,a5 +30100d2e: 87b6 mv a5,a3 +30100d30: 8fd9 or a5,a5,a4 +30100d32: fcf40a23 sb a5,-44(s0) +30100d36: fc842783 lw a5,-56(s0) +30100d3a: 0047c783 lbu a5,4(a5) +30100d3e: 8395 srli a5,a5,0x5 +30100d40: 0ff7f793 zext.b a5,a5 +30100d44: 00579693 slli a3,a5,0x5 +30100d48: fd844783 lbu a5,-40(s0) +30100d4c: 8bfd andi a5,a5,31 +30100d4e: 873e mv a4,a5 +30100d50: 87b6 mv a5,a3 +30100d52: 8fd9 or a5,a5,a4 +30100d54: fcf40c23 sb a5,-40(s0) +30100d58: fe042423 sw zero,-24(s0) +30100d5c: fcc42503 lw a0,-52(s0) +30100d60: fec42603 lw a2,-20(s0) +30100d64: fe442703 lw a4,-28(s0) +30100d68: fd440793 addi a5,s0,-44 +30100d6c: c402 sw zero,8(sp) +30100d6e: c202 sw zero,4(sp) +30100d70: c002 sw zero,0(sp) +30100d72: 48c1 li a7,16 +30100d74: 883e mv a6,a5 +30100d76: 4781 li a5,0 +30100d78: fe842683 lw a3,-24(s0) +30100d7c: 65b1 lui a1,0xc +30100d7e: 0c058593 addi a1,a1,192 # c0c0 <_start-0x300f3f40> +30100d82: 2a2d jal 30100ebc +30100d84: 4791 li a5,4 +30100d86: fef42423 sw a5,-24(s0) +30100d8a: fcc42503 lw a0,-52(s0) +30100d8e: fec42603 lw a2,-20(s0) +30100d92: fe442703 lw a4,-28(s0) +30100d96: fd440793 addi a5,s0,-44 +30100d9a: 0791 addi a5,a5,4 +30100d9c: c402 sw zero,8(sp) +30100d9e: c202 sw zero,4(sp) +30100da0: c002 sw zero,0(sp) +30100da2: 48c1 li a7,16 +30100da4: 883e mv a6,a5 +30100da6: 4781 li a5,0 +30100da8: fe842683 lw a3,-24(s0) +30100dac: 65b1 lui a1,0xc +30100dae: 0c058593 addi a1,a1,192 # c0c0 <_start-0x300f3f40> +30100db2: 2229 jal 30100ebc +30100db4: 47a1 li a5,8 +30100db6: fef42423 sw a5,-24(s0) +30100dba: 47a1 li a5,8 +30100dbc: fcf42e23 sw a5,-36(s0) +30100dc0: fcc42503 lw a0,-52(s0) +30100dc4: fec42603 lw a2,-20(s0) +30100dc8: fe442703 lw a4,-28(s0) +30100dcc: fe042683 lw a3,-32(s0) +30100dd0: fdc42783 lw a5,-36(s0) +30100dd4: c402 sw zero,8(sp) +30100dd6: c23e sw a5,4(sp) +30100dd8: fd440793 addi a5,s0,-44 +30100ddc: 0795 addi a5,a5,5 +30100dde: c03e sw a5,0(sp) +30100de0: 4881 li a7,0 +30100de2: 4801 li a6,0 +30100de4: 87b6 mv a5,a3 +30100de6: fe842683 lw a3,-24(s0) +30100dea: 6591 lui a1,0x4 +30100dec: 04058593 addi a1,a1,64 # 4040 <_start-0x300fbfc0> +30100df0: 20f1 jal 30100ebc +30100df2: fc842783 lw a5,-56(s0) +30100df6: 0057c783 lbu a5,5(a5) +30100dfa: 8389 srli a5,a5,0x2 +30100dfc: 8b85 andi a5,a5,1 +30100dfe: 0ff7f793 zext.b a5,a5 +30100e02: 8b85 andi a5,a5,1 +30100e04: 00279693 slli a3,a5,0x2 +30100e08: fd944783 lbu a5,-39(s0) +30100e0c: 9bed andi a5,a5,-5 +30100e0e: 873e mv a4,a5 +30100e10: 87b6 mv a5,a3 +30100e12: 8fd9 or a5,a5,a4 +30100e14: fcf40ca3 sb a5,-39(s0) +30100e18: fc842783 lw a5,-56(s0) +30100e1c: 0057c783 lbu a5,5(a5) +30100e20: 8b8d andi a5,a5,3 +30100e22: 0ff7f793 zext.b a5,a5 +30100e26: 0037f693 andi a3,a5,3 +30100e2a: fd944783 lbu a5,-39(s0) +30100e2e: 9bf1 andi a5,a5,-4 +30100e30: 873e mv a4,a5 +30100e32: 87b6 mv a5,a3 +30100e34: 8fd9 or a5,a5,a4 +30100e36: fcf40ca3 sb a5,-39(s0) +30100e3a: fc842783 lw a5,-56(s0) +30100e3e: 0057c783 lbu a5,5(a5) +30100e42: 838d srli a5,a5,0x3 +30100e44: 8b85 andi a5,a5,1 +30100e46: 0ff7f793 zext.b a5,a5 +30100e4a: 8b85 andi a5,a5,1 +30100e4c: 00379693 slli a3,a5,0x3 +30100e50: fd944783 lbu a5,-39(s0) +30100e54: 9bdd andi a5,a5,-9 +30100e56: 873e mv a4,a5 +30100e58: 87b6 mv a5,a3 +30100e5a: 8fd9 or a5,a5,a4 +30100e5c: fcf40ca3 sb a5,-39(s0) +30100e60: fc842783 lw a5,-56(s0) +30100e64: 0057c783 lbu a5,5(a5) +30100e68: 8399 srli a5,a5,0x6 +30100e6a: 8b85 andi a5,a5,1 +30100e6c: 0ff7f793 zext.b a5,a5 +30100e70: 8b85 andi a5,a5,1 +30100e72: 00679693 slli a3,a5,0x6 +30100e76: fd944783 lbu a5,-39(s0) +30100e7a: fbf7f793 andi a5,a5,-65 +30100e7e: 873e mv a4,a5 +30100e80: 87b6 mv a5,a3 +30100e82: 8fd9 or a5,a5,a4 +30100e84: fcf40ca3 sb a5,-39(s0) +30100e88: fcc42503 lw a0,-52(s0) +30100e8c: fec42603 lw a2,-20(s0) +30100e90: fe442703 lw a4,-28(s0) +30100e94: fd440793 addi a5,s0,-44 +30100e98: 0795 addi a5,a5,5 +30100e9a: c402 sw zero,8(sp) +30100e9c: c202 sw zero,4(sp) +30100e9e: c002 sw zero,0(sp) +30100ea0: 48c1 li a7,16 +30100ea2: 883e mv a6,a5 +30100ea4: 4781 li a5,0 +30100ea6: fe842683 lw a3,-24(s0) +30100eaa: 65b1 lui a1,0xc +30100eac: 0c058593 addi a1,a1,192 # c0c0 <_start-0x300f3f40> +30100eb0: 2031 jal 30100ebc +30100eb2: 0001 nop +30100eb4: 40b6 lw ra,76(sp) +30100eb6: 4426 lw s0,72(sp) +30100eb8: 6161 addi sp,sp,80 +30100eba: 8082 ret + +30100ebc : +30100ebc: 715d addi sp,sp,-80 +30100ebe: c686 sw ra,76(sp) +30100ec0: c4a2 sw s0,72(sp) +30100ec2: 0880 addi s0,sp,80 +30100ec4: fca42623 sw a0,-52(s0) +30100ec8: fcb42423 sw a1,-56(s0) +30100ecc: fcc42223 sw a2,-60(s0) +30100ed0: fcd42023 sw a3,-64(s0) +30100ed4: fae42e23 sw a4,-68(s0) +30100ed8: faf42c23 sw a5,-72(s0) +30100edc: fb042a23 sw a6,-76(s0) +30100ee0: fb142823 sw a7,-80(s0) +30100ee4: fcc42783 lw a5,-52(s0) +30100ee8: 459d li a1,7 +30100eea: 853e mv a0,a5 +30100eec: 1faff097 auipc ra,0x1faff +30100ef0: 224080e7 jalr 548(ra) # 4fc00110 +30100ef4: fc842783 lw a5,-56(s0) +30100ef8: 07c2 slli a5,a5,0x10 +30100efa: 83c1 srli a5,a5,0x10 +30100efc: fcf41823 sh a5,-48(s0) +30100f00: fc442783 lw a5,-60(s0) +30100f04: 07c2 slli a5,a5,0x10 +30100f06: 83c1 srli a5,a5,0x10 +30100f08: fcf41923 sh a5,-46(s0) +30100f0c: fc040793 addi a5,s0,-64 +30100f10: fcf42a23 sw a5,-44(s0) +30100f14: fbc42783 lw a5,-68(s0) +30100f18: fcf42c23 sw a5,-40(s0) +30100f1c: fb442783 lw a5,-76(s0) +30100f20: fcf42e23 sw a5,-36(s0) +30100f24: fb042783 lw a5,-80(s0) +30100f28: fef42023 sw a5,-32(s0) +30100f2c: 401c lw a5,0(s0) +30100f2e: fef42223 sw a5,-28(s0) +30100f32: 405c lw a5,4(s0) +30100f34: fef42423 sw a5,-24(s0) +30100f38: fb842783 lw a5,-72(s0) +30100f3c: fef42623 sw a5,-20(s0) +30100f40: fcc42783 lw a5,-52(s0) +30100f44: fd040713 addi a4,s0,-48 +30100f48: 85ba mv a1,a4 +30100f4a: 853e mv a0,a5 +30100f4c: 1faff097 auipc ra,0x1faff +30100f50: 1bc080e7 jalr 444(ra) # 4fc00108 +30100f54: fcc42503 lw a0,-52(s0) +30100f58: 405c lw a5,4(s0) +30100f5a: 838d srli a5,a5,0x3 +30100f5c: 07c2 slli a5,a5,0x10 +30100f5e: 83c1 srli a5,a5,0x10 +30100f60: 00844703 lbu a4,8(s0) +30100f64: 4689 li a3,2 +30100f66: 863e mv a2,a5 +30100f68: 400c lw a1,0(s0) +30100f6a: 1faff097 auipc ra,0x1faff +30100f6e: 1a2080e7 jalr 418(ra) # 4fc0010c +30100f72: 0001 nop +30100f74: 40b6 lw ra,76(sp) +30100f76: 4426 lw s0,72(sp) +30100f78: 6161 addi sp,sp,80 +30100f7a: 8082 ret + +30100f7c : +30100f7c: 7139 addi sp,sp,-64 +30100f7e: de06 sw ra,60(sp) +30100f80: dc22 sw s0,56(sp) +30100f82: 0080 addi s0,sp,64 +30100f84: fca42e23 sw a0,-36(s0) +30100f88: 5a6b87b7 lui a5,0x5a6b8 +30100f8c: c8d78793 addi a5,a5,-883 # 5a6b7c8d +30100f90: fef42623 sw a5,-20(s0) +30100f94: fe042423 sw zero,-24(s0) +30100f98: fdc42503 lw a0,-36(s0) +30100f9c: fec40793 addi a5,s0,-20 +30100fa0: c402 sw zero,8(sp) +30100fa2: c202 sw zero,4(sp) +30100fa4: c002 sw zero,0(sp) +30100fa6: 02000893 li a7,32 +30100faa: 883e mv a6,a5 +30100fac: 47b1 li a5,12 +30100fae: 02000713 li a4,32 +30100fb2: 4681 li a3,0 +30100fb4: 4641 li a2,16 +30100fb6: 65a1 lui a1,0x8 +30100fb8: 08058593 addi a1,a1,128 # 8080 <_start-0x300f7f80> +30100fbc: 3701 jal 30100ebc +30100fbe: fdc42503 lw a0,-36(s0) +30100fc2: c402 sw zero,8(sp) +30100fc4: 02000793 li a5,32 +30100fc8: c23e sw a5,4(sp) +30100fca: fe840793 addi a5,s0,-24 +30100fce: c03e sw a5,0(sp) +30100fd0: 4881 li a7,0 +30100fd2: 4801 li a6,0 +30100fd4: 47e9 li a5,26 +30100fd6: 02000713 li a4,32 +30100fda: 4681 li a3,0 +30100fdc: 4641 li a2,16 +30100fde: 4581 li a1,0 +30100fe0: 3df1 jal 30100ebc +30100fe2: fe842703 lw a4,-24(s0) +30100fe6: fec42783 lw a5,-20(s0) +30100fea: ,----- 00f71463 bne a4,a5,30100ff2 +30100fee: | 4781 li a5,0 +30100ff0: | ,-- a011 j 30100ff4 +30100ff2: '--|-> 57fd li a5,-1 +30100ff4: '-> 853e mv a0,a5 +30100ff6: 50f2 lw ra,60(sp) +30100ff8: 5462 lw s0,56(sp) +30100ffa: 6121 addi sp,sp,64 +30100ffc: 8082 ret + +30100ffe : +30100ffe: 7179 addi sp,sp,-48 +30101000: d606 sw ra,44(sp) +30101002: d422 sw s0,40(sp) +30101004: 1800 addi s0,sp,48 +30101006: fea42623 sw a0,-20(s0) +3010100a: feb42423 sw a1,-24(s0) +3010100e: fec42503 lw a0,-20(s0) +30101012: fe842783 lw a5,-24(s0) +30101016: c402 sw zero,8(sp) +30101018: 4741 li a4,16 +3010101a: c23a sw a4,4(sp) +3010101c: c03e sw a5,0(sp) +3010101e: 4881 li a7,0 +30101020: 4801 li a6,0 +30101022: 47b1 li a5,12 +30101024: 02000713 li a4,32 +30101028: 4681 li a3,0 +3010102a: 4641 li a2,16 +3010102c: 6591 lui a1,0x4 +3010102e: 04058593 addi a1,a1,64 # 4040 <_start-0x300fbfc0> +30101032: 3569 jal 30100ebc +30101034: fec42503 lw a0,-20(s0) +30101038: fe842783 lw a5,-24(s0) +3010103c: 0789 addi a5,a5,2 +3010103e: c402 sw zero,8(sp) +30101040: 4741 li a4,16 +30101042: c23a sw a4,4(sp) +30101044: c03e sw a5,0(sp) +30101046: 4881 li a7,0 +30101048: 4801 li a6,0 +3010104a: 47b1 li a5,12 +3010104c: 02000713 li a4,32 +30101050: 4689 li a3,2 +30101052: 4641 li a2,16 +30101054: 6591 lui a1,0x4 +30101056: 04058593 addi a1,a1,64 # 4040 <_start-0x300fbfc0> +3010105a: 358d jal 30100ebc +3010105c: fec42503 lw a0,-20(s0) +30101060: fe842783 lw a5,-24(s0) +30101064: 0791 addi a5,a5,4 +30101066: c402 sw zero,8(sp) +30101068: 4721 li a4,8 +3010106a: c23a sw a4,4(sp) +3010106c: c03e sw a5,0(sp) +3010106e: 4881 li a7,0 +30101070: 4801 li a6,0 +30101072: 47b1 li a5,12 +30101074: 02000713 li a4,32 +30101078: 4691 li a3,4 +3010107a: 4641 li a2,16 +3010107c: 6591 lui a1,0x4 +3010107e: 04058593 addi a1,a1,64 # 4040 <_start-0x300fbfc0> +30101082: 3d2d jal 30100ebc +30101084: fec42503 lw a0,-20(s0) +30101088: fe842783 lw a5,-24(s0) +3010108c: 0795 addi a5,a5,5 +3010108e: c402 sw zero,8(sp) +30101090: 4721 li a4,8 +30101092: c23a sw a4,4(sp) +30101094: c03e sw a5,0(sp) +30101096: 4881 li a7,0 +30101098: 4801 li a6,0 +3010109a: 47b1 li a5,12 +3010109c: 02000713 li a4,32 +301010a0: 46a1 li a3,8 +301010a2: 4641 li a2,16 +301010a4: 6591 lui a1,0x4 +301010a6: 04058593 addi a1,a1,64 # 4040 <_start-0x300fbfc0> +301010aa: 3d09 jal 30100ebc +301010ac: 0001 nop +301010ae: 50b2 lw ra,44(sp) +301010b0: 5422 lw s0,40(sp) +301010b2: 6145 addi sp,sp,48 +301010b4: 8082 ret diff --git a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Startup/Startup.c b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Startup/Startup.c new file mode 100644 index 000000000..22fe90751 --- /dev/null +++ b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Startup/Startup.c @@ -0,0 +1,187 @@ +// *************************************************************************************** +// Filename : Startup.c +// +// Author : Chalandi Amine +// +// Owner : Chalandi Amine +// +// Date : 11.03.2020 +// +// Description : C/C++ Runtime Setup (Crt0) +// +// *************************************************************************************** + +#include + +//========================================================================================= +// Types definitions +//========================================================================================= +typedef struct +{ + unsigned long sourceAddr; /* Source Address (section in ROM memory) */ + unsigned long targetAddr; /* Target Address (section in RAM memory) */ + unsigned long size; /* length of section (bytes) */ +} runtimeCopyTable_t; + +typedef struct +{ + unsigned long addr; /* Source Address (section in RAM memory) */ + unsigned long size; /* Length of section (bytes) */ +} runtimeClearTable_t; + +//========================================================================================= +// Linker variables +//========================================================================================= +extern const runtimeCopyTable_t __RUNTIME_COPY_TABLE[]; +extern const runtimeClearTable_t __RUNTIME_CLEAR_TABLE[]; +extern unsigned long __CTOR_LIST__[]; + +//========================================================================================= +// Defines +//========================================================================================= +#define __STARTUP_RUNTIME_COPYTABLE (runtimeCopyTable_t*)(&__RUNTIME_COPY_TABLE[0]) +#define __STARTUP_RUNTIME_CLEARTABLE (runtimeClearTable_t*)(&__RUNTIME_CLEAR_TABLE[0]) +#define __STARTUP_RUNTIME_CTORS (unsigned long*)(&__CTOR_LIST__[0]) + +//========================================================================================= +// Function prototype +//========================================================================================= +void Startup_Init(void); +static void Startup_InitRam(void); +static void Startup_InitCtors(void); +static void Startup_RunApplication(void); +static void Startup_Unexpected_Exit(void); +static void Startup_InitMcuSystem(void); + +//========================================================================================= +// Extern function prototype +//========================================================================================= +int main(void) __attribute__((weak)); + +//----------------------------------------------------------------------------------------- +/// \brief Startup_Init function +/// +/// \param void +/// +/// \return void +//----------------------------------------------------------------------------------------- +void Startup_Init(void) +{ + /* Initialize the MCU system */ + Startup_InitMcuSystem(); + + /* Initialize the RAM memory */ + Startup_InitRam(); + + /* Initialize the non-local C++ objects */ + Startup_InitCtors(); + + /* Run the main application */ + Startup_RunApplication(); + +} + +//----------------------------------------------------------------------------------------- +/// \brief Startup_InitRam function +/// +/// \param void +/// +/// \return void +//----------------------------------------------------------------------------------------- +static void Startup_InitRam(void) +{ + unsigned long ClearTableIdx = 0; + unsigned long CopyTableIdx = 0; + + /* Clear Table */ + while((__STARTUP_RUNTIME_CLEARTABLE)[ClearTableIdx].addr != (unsigned long)-1 && (__STARTUP_RUNTIME_CLEARTABLE)[ClearTableIdx].size != (unsigned long)-1) + { + for(unsigned long idx = 0; idx < ((unsigned long)((__STARTUP_RUNTIME_CLEARTABLE)[ClearTableIdx].size) / 4); idx++) + { + ((unsigned long*)((__STARTUP_RUNTIME_CLEARTABLE)[ClearTableIdx].addr))[idx] = 0; + } + + ClearTableIdx++; + } + + /* Copy Table */ + while((__STARTUP_RUNTIME_COPYTABLE)[CopyTableIdx].sourceAddr != (unsigned long)-1 && + (__STARTUP_RUNTIME_COPYTABLE)[CopyTableIdx].targetAddr != (unsigned long)-1 && + (__STARTUP_RUNTIME_COPYTABLE)[CopyTableIdx].size != (unsigned long)-1 + ) + { + for(unsigned long idx = 0; idx < ((unsigned long)((__STARTUP_RUNTIME_COPYTABLE)[CopyTableIdx].size) / 4); idx++) + { + ((unsigned long*)((__STARTUP_RUNTIME_COPYTABLE)[CopyTableIdx].targetAddr))[idx] = + ((unsigned long*)((__STARTUP_RUNTIME_COPYTABLE)[CopyTableIdx].sourceAddr))[idx]; + } + + CopyTableIdx++; + } +} + +//----------------------------------------------------------------------------------------- +/// \brief Startup_InitCtors function +/// +/// \param void +/// +/// \return void +//----------------------------------------------------------------------------------------- +static void Startup_InitCtors(void) +{ + unsigned long CtorIdx = 0U; + + while((__STARTUP_RUNTIME_CTORS)[CtorIdx] != ((unsigned long)-1)) + { + ((void (*)(void))((__STARTUP_RUNTIME_CTORS)[CtorIdx++]))(); + } +} + +//----------------------------------------------------------------------------------------- +/// \brief Startup_RunApplication function +/// +/// \param void +/// +/// \return void +//----------------------------------------------------------------------------------------- +static void Startup_RunApplication(void) +{ + /* check the weak function */ + if((unsigned int) &main != 0) + { +#ifdef HP_CORES_SMP_MODE + /* note: RISC-V has no WFE/SEV instructions to synchronize SMP system + so I'm using CLINT to synchronize both HP cores on ESP32-P4 */ + /* notify core1 that the setup of the runtime environment is done (by setting the SW interrupt pending bit on the core1's CLINT) */ + *(volatile uint32_t*)0x20010000 = 1; +#endif + /* Call the main function */ + main(); + } + + /* Catch unexpected exit from main or if main does not exist */ + Startup_Unexpected_Exit(); +} + +//----------------------------------------------------------------------------------------- +/// \brief Startup_Unexpected_Exit function +/// +/// \param void +/// +/// \return void +//----------------------------------------------------------------------------------------- +static void Startup_Unexpected_Exit(void) +{ + for(;;); +} +//----------------------------------------------------------------------------------------- +/// \brief Startup_InitMcuSystem function +/// +/// \param void +/// +/// \return void +//----------------------------------------------------------------------------------------- +static void Startup_InitMcuSystem(void) +{ + /* system clock is set by the SBL */ +} \ No newline at end of file diff --git a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Startup/boot.s b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Startup/boot.s new file mode 100644 index 000000000..9b87376bb --- /dev/null +++ b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Startup/boot.s @@ -0,0 +1,199 @@ +/****************************************************************************************** + Filename : boot.s + + Core : RISC-V + + MCU : ESP32-P4 + + Author : Chalandi Amine + + Owner : Chalandi Amine + + Date : 06.01.2026 + + Description : boot routine for HP cores + +******************************************************************************************/ + +/******************************************************************************************* + \brief + + \param + + \return +********************************************************************************************/ +.section .boot +.type _start, @function +.align 2 +.globl _start + +.set mtvt, 0x307 +.set msip, 0x20000000 + +_start: + /* setup the interrupt vector table (CLIC) */ + la t0, InterruptVectorTable + csrw mtvt, t0 + + /* setup the exception vector table (CLINT) */ + la t0, ExceptionVectorTable + csrw mtvec, t0 + + /* Enable FPU by setting FS bits in mstatus */ + li t0, 0x00006000 + csrs mstatus, t0 + fscsr x0 + + /* Read machine hart ID */ + csrr a0, mhartid + bnez a0, .L_core1 + la sp, __CORE0_STACK_TOP + jal Startup_Init + j . + +.L_core1: + /* note: - RISC-V has no WFE/SEV instructions to synchronize SMP system + so I'm using CLINT to synchronize both HP cores on ESP32-P4. + - Core0 will set the software interrupt pending flag in Core1's CLINT + once the runtime environment setup is complete. + */ + li a5, msip + lw a0, 0(a5) + beqz a0, .L_core1 + li a0, 0 + sw a0, 0(a5) + la sp, __CORE1_STACK_TOP + jal main + j . + +/******************************************************************************************* + \brief + + \param + + \return +********************************************************************************************/ +.section .text +.type ExceptionVectorTable, @function +.align 6 +.globl ExceptionVectorTable + +ExceptionVectorTable: + j . + +.size ExceptionVectorTable, .-ExceptionVectorTable + +/******************************************************************************************* + \brief uint32_t osGetActiveCore(void) + + \param void + + \return uint32_t : Active Core ID +********************************************************************************************/ +.section ".text", "ax" +.align 2 +.globl osGetActiveCore +.type osGetActiveCore, @function + + +osGetActiveCore: + csrr a0, mhartid + ret + +.size osGetActiveCore, .-osGetActiveCore + +/******************************************************************************************* + \brief void osHwAcquireSpinLock(uint32* lock) + + \param lock: pointer to the lock variable + + \return void +********************************************************************************************/ +.section ".text", "ax" +.align 2 +.globl osHwAcquireSpinLock +.type osHwAcquireSpinLock, @function + + +osHwAcquireSpinLock: lr.w a1, (a0) + bne zero, a1, osHwAcquireSpinLock + add a1, zero, 1 + sc.w t0, a1, (a0) + bnez t0, osHwAcquireSpinLock + ret + +.size osHwAcquireSpinLock, .-osHwAcquireSpinLock + +/******************************************************************************************* + \brief uint32_t osHwTryToAcquireSpinLock(uint32_t* lock) + + \param lock: pointer to the lock variable + + \return uint32_t 0 -> not acquired, 1 -> acquired +********************************************************************************************/ +.section ".text", "ax" +.align 2 +.globl osHwTryToAcquireSpinLock +.type osHwTryToAcquireSpinLock, @function + + +osHwTryToAcquireSpinLock: + lr.w a1, (a0) + bne zero, a1, .L_not_acquired + add a1, zero, 1 + sc.w t0, a1, (a0) + bnez t0, .L_not_acquired + add a0, x0, 1 + ret +.L_not_acquired: + mv a0, x0 + ret + +.size osHwTryToAcquireSpinLock, .-osHwTryToAcquireSpinLock + +/******************************************************************************************* + \brief void osHwReleaseSpinLock(uint32_t* lock) + + \param lock: pointer to the lock variable + + \return void +********************************************************************************************/ +.section ".text", "ax" +.align 2 +.globl osHwReleaseSpinLock +.type osHwReleaseSpinLock, @function + + +osHwReleaseSpinLock: lr.w a1, (a0) + add a2, zero, 1 + bne a2, a1, osHwReleaseSpinLock + sc.w t0, zero, (a0) + bnez t0, osHwReleaseSpinLock + ret + +.size osHwReleaseSpinLock, .-osHwReleaseSpinLock + +/* +----------------------------------------------------------------- + Register | ABI Name | Description | Saver +----------------------------------------------------------------- + x0 | zero | Hard-wired zero | - + x1 | ra | Return address | Caller + x2 | sp | Stack pointer | Callee + x3 | gp | Global pointer | - + x4 | tp | Thread pointer | - + x5-7 | t0-2 | Temporaries | Caller + x8 | s0/fp | Saved register/frame pointer | Callee + x9 | s1 | Saved register | Callee + x10-11 | a0-1 | Function arguments/return values | Caller + x12-17 | a2-7 | Function arguments | Caller + x18-27 | s2-11 | Saved registers | Callee + x28-31 | t3-6 | Temporaries | Caller + f0-7 | ft0-7 | FP temporaries | Caller + f8-9 | fs0-1 | FP saved registers | Callee + f10-11 | fa0-1 | FP arguments/return values | Caller + f12-17 | fa2-7 | FP arguments | Caller + f18-27 | fs2-11 | FP saved registers | Callee + f28-31 | ft8-11 | FP temporaries | Caller +----------------------------------------------------------------- +*/ \ No newline at end of file diff --git a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Startup/intvect.c b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Startup/intvect.c new file mode 100644 index 000000000..a28c2f9ef --- /dev/null +++ b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Startup/intvect.c @@ -0,0 +1,119 @@ +/****************************************************************************************************** + Filename : intvect.c + + Core : RISC-V + + MCU : ESP32-P4 + + Author : Chalandi Amine + + Owner : Chalandi Amine + + Date : 22.01.2026 + + Description : Interrupt vector table implementation + +******************************************************************************************************/ + +//===================================================================================================== +// Includes +//===================================================================================================== +#include + +//===================================================================================================== +// Functions prototype +//===================================================================================================== +static void UndefinedHandler(void); +static void UndefinedHandler(void){ for(;;); } + +void Isr_SW_Interrupt (void) __attribute__((weak, alias("UndefinedHandler"))); +void Isr_TIMER_Interrupt (void) __attribute__((weak, alias("UndefinedHandler"))); +void Isr_ExtInt00 (void) __attribute__((weak, alias("UndefinedHandler"))); +void Isr_ExtInt01 (void) __attribute__((weak, alias("UndefinedHandler"))); +void Isr_ExtInt02 (void) __attribute__((weak, alias("UndefinedHandler"))); +void Isr_ExtInt03 (void) __attribute__((weak, alias("UndefinedHandler"))); +void Isr_ExtInt04 (void) __attribute__((weak, alias("UndefinedHandler"))); +void Isr_ExtInt05 (void) __attribute__((weak, alias("UndefinedHandler"))); +void Isr_ExtInt06 (void) __attribute__((weak, alias("UndefinedHandler"))); +void Isr_ExtInt07 (void) __attribute__((weak, alias("UndefinedHandler"))); +void Isr_ExtInt08 (void) __attribute__((weak, alias("UndefinedHandler"))); +void Isr_ExtInt09 (void) __attribute__((weak, alias("UndefinedHandler"))); +void Isr_ExtInt10 (void) __attribute__((weak, alias("UndefinedHandler"))); +void Isr_ExtInt11 (void) __attribute__((weak, alias("UndefinedHandler"))); +void Isr_ExtInt12 (void) __attribute__((weak, alias("UndefinedHandler"))); +void Isr_ExtInt13 (void) __attribute__((weak, alias("UndefinedHandler"))); +void Isr_ExtInt14 (void) __attribute__((weak, alias("UndefinedHandler"))); +void Isr_ExtInt15 (void) __attribute__((weak, alias("UndefinedHandler"))); +void Isr_ExtInt16 (void) __attribute__((weak, alias("UndefinedHandler"))); +void Isr_ExtInt17 (void) __attribute__((weak, alias("UndefinedHandler"))); +void Isr_ExtInt18 (void) __attribute__((weak, alias("UndefinedHandler"))); +void Isr_ExtInt19 (void) __attribute__((weak, alias("UndefinedHandler"))); +void Isr_ExtInt20 (void) __attribute__((weak, alias("UndefinedHandler"))); +void Isr_ExtInt21 (void) __attribute__((weak, alias("UndefinedHandler"))); +void Isr_ExtInt22 (void) __attribute__((weak, alias("UndefinedHandler"))); +void Isr_ExtInt23 (void) __attribute__((weak, alias("UndefinedHandler"))); +void Isr_ExtInt24 (void) __attribute__((weak, alias("UndefinedHandler"))); +void Isr_ExtInt25 (void) __attribute__((weak, alias("UndefinedHandler"))); +void Isr_ExtInt26 (void) __attribute__((weak, alias("UndefinedHandler"))); +void Isr_ExtInt27 (void) __attribute__((weak, alias("UndefinedHandler"))); +void Isr_ExtInt28 (void) __attribute__((weak, alias("UndefinedHandler"))); +void Isr_ExtInt29 (void) __attribute__((weak, alias("UndefinedHandler"))); +void Isr_ExtInt30 (void) __attribute__((weak, alias("UndefinedHandler"))); +void Isr_ExtInt31 (void) __attribute__((weak, alias("UndefinedHandler"))); + +typedef void (*InterruptHandler)(void); + +//===================================================================================================== +// Interrupt vector table +//===================================================================================================== +const InterruptHandler __attribute__((aligned(64))) InterruptVectorTable[] = +{ + (InterruptHandler)&UndefinedHandler, /* IRQ 00 Reserved */ + (InterruptHandler)&UndefinedHandler, /* IRQ 01 Reserved */ + (InterruptHandler)&UndefinedHandler, /* IRQ 02 Reserved */ + (InterruptHandler)&Isr_SW_Interrupt, /* IRQ 03 M mode software interrupt */ + (InterruptHandler)&UndefinedHandler, /* IRQ 04 Reserved */ + (InterruptHandler)&UndefinedHandler, /* IRQ 05 Reserved */ + (InterruptHandler)&UndefinedHandler, /* IRQ 06 Reserved */ + (InterruptHandler)&Isr_TIMER_Interrupt, /* IRQ 07 M mode timer interrupt */ + (InterruptHandler)&UndefinedHandler, /* IRQ 08 Reserved */ + (InterruptHandler)&UndefinedHandler, /* IRQ 09 Reserved */ + (InterruptHandler)&UndefinedHandler, /* IRQ 10 Reserved */ + (InterruptHandler)&UndefinedHandler, /* IRQ 11 Reserved */ + (InterruptHandler)&UndefinedHandler, /* IRQ 12 Reserved */ + (InterruptHandler)&UndefinedHandler, /* IRQ 13 Reserved */ + (InterruptHandler)&UndefinedHandler, /* IRQ 14 Reserved */ + (InterruptHandler)&UndefinedHandler, /* IRQ 15 Reserved */ + (InterruptHandler)&Isr_ExtInt00, /* IRQ 16 External Interrupt (00) */ + (InterruptHandler)&Isr_ExtInt01, /* IRQ 17 External Interrupt (01) */ + (InterruptHandler)&Isr_ExtInt02, /* IRQ 18 External Interrupt (02) */ + (InterruptHandler)&Isr_ExtInt03, /* IRQ 19 External Interrupt (03) */ + (InterruptHandler)&Isr_ExtInt04, /* IRQ 20 External Interrupt (04) */ + (InterruptHandler)&Isr_ExtInt05, /* IRQ 21 External Interrupt (05) */ + (InterruptHandler)&Isr_ExtInt06, /* IRQ 22 External Interrupt (06) */ + (InterruptHandler)&Isr_ExtInt07, /* IRQ 23 External Interrupt (07) */ + (InterruptHandler)&Isr_ExtInt08, /* IRQ 24 External Interrupt (08) */ + (InterruptHandler)&Isr_ExtInt09, /* IRQ 25 External Interrupt (09) */ + (InterruptHandler)&Isr_ExtInt10, /* IRQ 26 External Interrupt (10) */ + (InterruptHandler)&Isr_ExtInt11, /* IRQ 27 External Interrupt (11) */ + (InterruptHandler)&Isr_ExtInt12, /* IRQ 28 External Interrupt (12) */ + (InterruptHandler)&Isr_ExtInt13, /* IRQ 29 External Interrupt (13) */ + (InterruptHandler)&Isr_ExtInt14, /* IRQ 30 External Interrupt (14) */ + (InterruptHandler)&Isr_ExtInt15, /* IRQ 31 External Interrupt (15) */ + (InterruptHandler)&Isr_ExtInt16, /* IRQ 32 External Interrupt (16) */ + (InterruptHandler)&Isr_ExtInt17, /* IRQ 33 External Interrupt (17) */ + (InterruptHandler)&Isr_ExtInt18, /* IRQ 34 External Interrupt (18) */ + (InterruptHandler)&Isr_ExtInt19, /* IRQ 35 External Interrupt (19) */ + (InterruptHandler)&Isr_ExtInt20, /* IRQ 36 External Interrupt (20) */ + (InterruptHandler)&Isr_ExtInt21, /* IRQ 37 External Interrupt (21) */ + (InterruptHandler)&Isr_ExtInt22, /* IRQ 38 External Interrupt (22) */ + (InterruptHandler)&Isr_ExtInt23, /* IRQ 39 External Interrupt (23) */ + (InterruptHandler)&Isr_ExtInt24, /* IRQ 40 External Interrupt (24) */ + (InterruptHandler)&Isr_ExtInt25, /* IRQ 41 External Interrupt (25) */ + (InterruptHandler)&Isr_ExtInt26, /* IRQ 42 External Interrupt (26) */ + (InterruptHandler)&Isr_ExtInt27, /* IRQ 43 External Interrupt (27) */ + (InterruptHandler)&Isr_ExtInt28, /* IRQ 44 External Interrupt (28) */ + (InterruptHandler)&Isr_ExtInt29, /* IRQ 45 External Interrupt (29) */ + (InterruptHandler)&Isr_ExtInt30, /* IRQ 46 External Interrupt (30) */ + (InterruptHandler)&Isr_ExtInt31, /* IRQ 47 External Interrupt (31) */ +}; From 9d0124165794d9cd2dabe5f4a1fa27f3111bbb30 Mon Sep 17 00:00:00 2001 From: ckormanyos Date: Tue, 10 Feb 2026 10:40:14 +0100 Subject: [PATCH 02/11] Add esp32_p4 to CI --- .github/workflows/real-time-cpp.yml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/.github/workflows/real-time-cpp.yml b/.github/workflows/real-time-cpp.yml index 5b15df3f6..2fafaae2f 100644 --- a/.github/workflows/real-time-cpp.yml +++ b/.github/workflows/real-time-cpp.yml @@ -236,19 +236,19 @@ jobs: strategy: fail-fast: false matrix: - suite: [ bl602_sifive_e24_riscv, riscvfe310, wch_ch32v307, xtensa_esp32_s3_riscv_cop ] + suite: [ bl602_sifive_e24_riscv, riscvfe310, wch_ch32v307, xtensa_esp32_p4, xtensa_esp32_s3_riscv_cop ] steps: - uses: actions/checkout@v4 with: fetch-depth: '0' - name: update-tools run: | - wget --no-check-certificate https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack/releases/download/v15.2.0-1/xpack-riscv-none-elf-gcc-15.2.0-1-linux-x64.tar.gz - tar -xzf xpack-riscv-none-elf-gcc-15.2.0-1-linux-x64.tar.gz -C ${{ runner.workspace }} + wget --no-check-certificate https://github.com/espressif/crosstool-NG/releases/download/esp-14.2.0_20260121/riscv32-esp-elf-14.2.0_20260121-x86_64-linux-gnu.tar.gz + tar -xzf riscv32-esp-elf-14.2.0_20260121-x86_64-linux-gnu.tar.gz -C ${{ runner.workspace }} working-directory: ./ - name: target-riscv-${{ matrix.suite }} run: | - PATH="${{ runner.workspace }}/xpack-riscv-none-elf-gcc-15.2.0-1/bin:$PATH" + PATH="${{ runner.workspace }}/riscv32-esp-elf/bin:$PATH" ./target/build/build.sh ${{ matrix.suite }} rebuild ls -la ./bin/ref_app.elf ./bin/ref_app.hex ./bin/ref_app.map ./bin/ref_app.s19 working-directory: ./ref_app/ From 1cc576e87c5cce7e084a02bd7476ddd6f8251939 Mon Sep 17 00:00:00 2001 From: ckormanyos Date: Tue, 10 Feb 2026 11:15:02 +0100 Subject: [PATCH 03/11] Sync up compiler downgrade --- ref_app/target/build/test_app_benchmarks_stm32f446.sh | 3 +++ .../make/bl602_sifive_e24_riscv_flags.gmk | 8 ++++---- .../target/micros/riscvfe310/make/riscvfe310_flags.gmk | 8 ++++---- .../micros/wch_ch32v307/make/wch_ch32v307_flags.gmk | 8 ++++---- .../micros/xtensa_esp32_p4/make/xtensa_esp32_p4_flags.gmk | 2 +- .../make/xtensa_esp32_s3_riscv_cop_flags.gmk | 8 ++++---- 6 files changed, 20 insertions(+), 17 deletions(-) diff --git a/ref_app/target/build/test_app_benchmarks_stm32f446.sh b/ref_app/target/build/test_app_benchmarks_stm32f446.sh index 62a82c4ed..ab93bdfa1 100755 --- a/ref_app/target/build/test_app_benchmarks_stm32f446.sh +++ b/ref_app/target/build/test_app_benchmarks_stm32f446.sh @@ -38,6 +38,9 @@ $GCC -std=$STD -Werror -Wall $wflags -O2 -g -gdwarf-2 -fno-exceptions -ffunction $GCC -std=$STD -Werror -Wall $wflags -O2 -g -gdwarf-2 -fno-exceptions -ffunction-sections -fdata-sections -x c++ -fno-rtti -fno-use-cxa-atexit -fno-exceptions -fno-nonansi-builtins -fno-threadsafe-statics -fno-enforce-eh-specs -ftemplate-depth=128 -Wzero-as-null-pointer-constant -mcpu=cortex-m4 -mtune=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -ffast-math -mno-unaligned-access -mno-long-calls -I./src/mcal/stm32f446 -I./src -DAPP_BENCHMARK_TYPE=APP_BENCHMARK_TYPE_TRAPEZOID_INTEGRAL -DAPP_BENCHMARK_STANDALONE_MAIN ./src/app/benchmark/app_benchmark_trapezoid_integral.cpp ./target/micros/stm32f446/make/single/crt.cpp -nostartfiles -Wl,--gc-sections -Wl,-Map,./bin/app_benchmark_trapezoid_integral.map -T ./target/micros/stm32f446/make/stm32f446.ld --specs=nano.specs --specs=nosys.specs -o ./bin/app_benchmark_trapezoid_integral.elf $GCC -std=$STD -Werror -Wall $wflags -O2 -g -gdwarf-2 -fno-exceptions -ffunction-sections -fdata-sections -x c++ -fno-rtti -fno-use-cxa-atexit -fno-exceptions -fno-nonansi-builtins -fno-threadsafe-statics -fno-enforce-eh-specs -ftemplate-depth=128 -Wzero-as-null-pointer-constant -mcpu=cortex-m4 -mtune=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -ffast-math -mno-unaligned-access -mno-long-calls -I./src/mcal/stm32f446 -I./src -DAPP_BENCHMARK_TYPE=APP_BENCHMARK_TYPE_WIDE_DECIMAL -DAPP_BENCHMARK_STANDALONE_MAIN ./src/app/benchmark/app_benchmark_wide_decimal.cpp ./target/micros/stm32f446/make/single/crt.cpp -nostartfiles -Wl,--gc-sections -Wl,-Map,./bin/app_benchmark_wide_decimal.map -T ./target/micros/stm32f446/make/stm32f446.ld --specs=nano.specs --specs=nosys.specs -o ./bin/app_benchmark_wide_decimal.elf $GCC -std=$STD -Werror -Wall $wflags -O2 -g -gdwarf-2 -fno-exceptions -ffunction-sections -fdata-sections -x c++ -fno-rtti -fno-use-cxa-atexit -fno-exceptions -fno-nonansi-builtins -fno-threadsafe-statics -fno-enforce-eh-specs -ftemplate-depth=128 -Wzero-as-null-pointer-constant -mcpu=cortex-m4 -mtune=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -ffast-math -mno-unaligned-access -mno-long-calls -I./src/mcal/stm32f446 -I./src -DAPP_BENCHMARK_TYPE=APP_BENCHMARK_TYPE_WIDE_INTEGER -DAPP_BENCHMARK_STANDALONE_MAIN ./src/app/benchmark/app_benchmark_wide_integer.cpp ./target/micros/stm32f446/make/single/crt.cpp -nostartfiles -Wl,--gc-sections -Wl,-Map,./bin/app_benchmark_wide_integer.map -T ./target/micros/stm32f446/make/stm32f446.ld --specs=nano.specs --specs=nosys.specs -o ./bin/app_benchmark_wide_integer.elf +$GCC -std=$STD -Werror -Wall -O2 -g -gdwarf-2 -fno-exceptions -ffunction-sections -fdata-sections -x c++ -fno-rtti -fno-use-cxa-atexit -fno-exceptions -fno-nonansi-builtins -fno-threadsafe-statics -fno-enforce-eh-specs -ftemplate-depth=128 -mcpu=cortex-m4 -mtune=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -ffast-math -mno-unaligned-access -mno-long-calls -I./src/mcal/stm32f446 -I./src -I../../boost-root -DAPP_BENCHMARK_TYPE=APP_BENCHMARK_TYPE_BOOST_MATH_CBRT_TGAMMA -DAPP_BENCHMARK_STANDALONE_MAIN ./src/app/benchmark/app_benchmark_boost_math_cbrt_tgamma.cpp ./target/micros/stm32f446/make/single/crt.cpp -nostartfiles -Wl,--gc-sections -Wl,-Map,./bin/app_benchmark_boost_math_cbrt_tgamma.map -T ./target/micros/stm32f446/make/stm32f446_with_stdlib.ld --specs=nano.specs --specs=nosys.specs -o ./bin/app_benchmark_boost_math_cbrt_tgamma.elf +$GCC -std=$STD -Werror -Wall -O2 -g -gdwarf-2 -fno-exceptions -ffunction-sections -fdata-sections -x c++ -fno-rtti -fno-use-cxa-atexit -fno-exceptions -fno-nonansi-builtins -fno-threadsafe-statics -fno-enforce-eh-specs -ftemplate-depth=128 -mcpu=cortex-m4 -mtune=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -ffast-math -mno-unaligned-access -mno-long-calls -I./src/mcal/stm32f446 -I./src -I../../boost-root -DAPP_BENCHMARK_TYPE=APP_BENCHMARK_TYPE_BOOST_MATH_CYL_BESSEL_J -DAPP_BENCHMARK_STANDALONE_MAIN ./src/app/benchmark/app_benchmark_boost_math_cyl_bessel_j.cpp ./target/micros/stm32f446/make/single/crt.cpp -nostartfiles -Wl,--gc-sections -Wl,-Map,./bin/app_benchmark_boost_math_cyl_bessel_j.map -T ./target/micros/stm32f446/make/stm32f446_with_stdlib.ld --specs=nano.specs --specs=nosys.specs -o ./bin/app_benchmark_boost_math_cyl_bessel_j.elf +$GCC -std=$STD -Werror -Wall -O2 -g -gdwarf-2 -fno-exceptions -ffunction-sections -fdata-sections -x c++ -fno-rtti -fno-use-cxa-atexit -fno-exceptions -fno-nonansi-builtins -fno-threadsafe-statics -fno-enforce-eh-specs -ftemplate-depth=128 -mcpu=cortex-m4 -mtune=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -ffast-math -mno-unaligned-access -mno-long-calls -I./src/mcal/stm32f446 -I./src -I../../boost-root -DAPP_BENCHMARK_TYPE=APP_BENCHMARK_TYPE_BOOST_MULTIPRECISION_CBRT -DAPP_BENCHMARK_STANDALONE_MAIN ./src/app/benchmark/app_benchmark_boost_multiprecision_cbrt.cpp ./target/micros/stm32f446/make/single/crt.cpp -nostartfiles -Wl,--gc-sections -Wl,-Map,./bin/app_benchmark_boost_multiprecision_cbrt.map -T ./target/micros/stm32f446/make/stm32f446_with_stdlib.ld --specs=nano.specs --specs=nosys.specs -o ./bin/app_benchmark_boost_multiprecision_cbrt.elf $GCC -std=$STD -Werror -Wall $wflags -O2 -g -gdwarf-2 -fno-exceptions -ffunction-sections -fdata-sections -x c++ -fno-rtti -fno-use-cxa-atexit -fno-exceptions -fno-nonansi-builtins -fno-threadsafe-statics -fno-enforce-eh-specs -ftemplate-depth=128 -Wzero-as-null-pointer-constant -mcpu=cortex-m4 -mtune=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -ffast-math -mno-unaligned-access -mno-long-calls -I./src/mcal/stm32f446 -I./src -DAPP_BENCHMARK_TYPE=APP_BENCHMARK_TYPE_HASH_SHA256 -DAPP_BENCHMARK_STANDALONE_MAIN ./src/app/benchmark/app_benchmark_hash_sha256.cpp ./target/micros/stm32f446/make/single/crt.cpp -nostartfiles -Wl,--gc-sections -Wl,-Map,./bin/app_benchmark_hash_sha256.map -T ./target/micros/stm32f446/make/stm32f446.ld --specs=nano.specs --specs=nosys.specs -o ./bin/app_benchmark_hash_sha256.elf $GCC -std=$STD -Werror -Wall $wflags -Os -g -gdwarf-2 -fno-exceptions -ffunction-sections -fdata-sections -x c++ -fno-rtti -fno-use-cxa-atexit -fno-exceptions -fno-nonansi-builtins -fno-threadsafe-statics -fno-enforce-eh-specs -ftemplate-depth=128 -Wzero-as-null-pointer-constant -mcpu=cortex-m4 -mtune=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -ffast-math -mno-unaligned-access -mno-long-calls -I./src/mcal/stm32f446 -I./src -DAPP_BENCHMARK_TYPE=APP_BENCHMARK_TYPE_ECC_GENERIC_ECC -DAPP_BENCHMARK_STANDALONE_MAIN ./src/app/benchmark/app_benchmark_ecc_generic_ecc.cpp ./target/micros/stm32f446/make/single/crt.cpp -nostartfiles -Wl,--gc-sections -Wl,-Map,./bin/app_benchmark_ecc_generic_ecc.map -T ./target/micros/stm32f446/make/stm32f446_with_stdlib.ld --specs=nano.specs --specs=nosys.specs -o ./bin/app_benchmark_ecc_generic_ecc.elf $GCC -std=$STD -Werror -Wall -O2 -g -gdwarf-2 -fno-exceptions -ffunction-sections -fdata-sections -x c++ -fno-rtti -fno-use-cxa-atexit -fno-exceptions -fno-nonansi-builtins -fno-threadsafe-statics -fno-enforce-eh-specs -ftemplate-depth=128 -Wzero-as-null-pointer-constant -mcpu=cortex-m4 -mtune=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -ffast-math -mno-unaligned-access -mno-long-calls -I./src/mcal/stm32f446 -I./src -I../../cppalliance-decimal-root/include -I../../boost-root -DAPP_BENCHMARK_TYPE=APP_BENCHMARK_TYPE_NON_STD_DECIMAL -DAPP_BENCHMARK_STANDALONE_MAIN ./src/app/benchmark/app_benchmark_non_std_decimal.cpp ./target/micros/stm32f446/make/single/crt.cpp -nostartfiles -Wl,--gc-sections -Wl,-Map,./bin/app_benchmark_non_std_decimal.map -T ./target/micros/stm32f446/make/stm32f446_with_stdlib.ld --specs=nano.specs --specs=nosys.specs -o ./bin/app_benchmark_non_std_decimal.elf diff --git a/ref_app/target/micros/bl602_sifive_e24_riscv/make/bl602_sifive_e24_riscv_flags.gmk b/ref_app/target/micros/bl602_sifive_e24_riscv/make/bl602_sifive_e24_riscv_flags.gmk index 8cf5163f5..f8be8428f 100644 --- a/ref_app/target/micros/bl602_sifive_e24_riscv/make/bl602_sifive_e24_riscv_flags.gmk +++ b/ref_app/target/micros/bl602_sifive_e24_riscv/make/bl602_sifive_e24_riscv_flags.gmk @@ -1,4 +1,4 @@ -# Copyright Christopher Kormanyos 2025. +# Copyright Christopher Kormanyos 2025 - 2026. # Distributed under the Boost Software License, # Version 1.0. (See accompanying file LICENSE_1_0.txt # or copy at http://www.boost.org/LICENSE_1_0.txt) @@ -8,10 +8,10 @@ # compiler flags for the target architecture # ------------------------------------------------------------------------------ -GCC_TARGET := riscv-none-elf -GCC_PREFIX := riscv-none-elf +GCC_TARGET := riscv32-esp-elf +GCC_PREFIX := riscv32-esp-elf -GCC_VERSION := 15.2.0 +GCC_VERSION := 14.2.0 TGT_SUFFIX = elf diff --git a/ref_app/target/micros/riscvfe310/make/riscvfe310_flags.gmk b/ref_app/target/micros/riscvfe310/make/riscvfe310_flags.gmk index bf223c937..989dff60e 100644 --- a/ref_app/target/micros/riscvfe310/make/riscvfe310_flags.gmk +++ b/ref_app/target/micros/riscvfe310/make/riscvfe310_flags.gmk @@ -1,4 +1,4 @@ -# Copyright Christopher Kormanyos 2022 - 2025. +# Copyright Christopher Kormanyos 2022 - 2026. # Distributed under the Boost Software License, # Version 1.0. (See accompanying file LICENSE_1_0.txt # or copy at http://www.boost.org/LICENSE_1_0.txt) @@ -8,10 +8,10 @@ # compiler flags for the target architecture # ------------------------------------------------------------------------------ -GCC_TARGET := riscv-none-elf -GCC_PREFIX := riscv-none-elf +GCC_TARGET := riscv32-esp-elf +GCC_PREFIX := riscv32-esp-elf -GCC_VERSION := 15.2.0 +GCC_VERSION := 14.2.0 TGT_SUFFIX = elf diff --git a/ref_app/target/micros/wch_ch32v307/make/wch_ch32v307_flags.gmk b/ref_app/target/micros/wch_ch32v307/make/wch_ch32v307_flags.gmk index daa9a8f93..f66fa5526 100644 --- a/ref_app/target/micros/wch_ch32v307/make/wch_ch32v307_flags.gmk +++ b/ref_app/target/micros/wch_ch32v307/make/wch_ch32v307_flags.gmk @@ -1,4 +1,4 @@ -# Copyright Christopher Kormanyos 2022 - 2025. +# Copyright Christopher Kormanyos 2022 - 2026. # Distributed under the Boost Software License, # Version 1.0. (See accompanying file LICENSE_1_0.txt # or copy at http://www.boost.org/LICENSE_1_0.txt) @@ -8,10 +8,10 @@ # compiler flags for the target architecture # ------------------------------------------------------------------------------ -GCC_TARGET := riscv-none-elf -GCC_PREFIX := riscv-none-elf +GCC_TARGET := riscv32-esp-elf +GCC_PREFIX := riscv32-esp-elf -GCC_VERSION := 15.2.0 +GCC_VERSION := 14.2.0 TGT_SUFFIX = elf diff --git a/ref_app/target/micros/xtensa_esp32_p4/make/xtensa_esp32_p4_flags.gmk b/ref_app/target/micros/xtensa_esp32_p4/make/xtensa_esp32_p4_flags.gmk index a205b0bc5..9cb63a7ce 100644 --- a/ref_app/target/micros/xtensa_esp32_p4/make/xtensa_esp32_p4_flags.gmk +++ b/ref_app/target/micros/xtensa_esp32_p4/make/xtensa_esp32_p4_flags.gmk @@ -1,5 +1,5 @@ # -# Copyright Christopher Kormanyos 2018 - 2025. +# Copyright Christopher Kormanyos 2026. # Distributed under the Boost Software License, # Version 1.0. (See accompanying file LICENSE_1_0.txt # or copy at http://www.boost.org/LICENSE_1_0.txt) diff --git a/ref_app/target/micros/xtensa_esp32_s3_riscv_cop/make/xtensa_esp32_s3_riscv_cop_flags.gmk b/ref_app/target/micros/xtensa_esp32_s3_riscv_cop/make/xtensa_esp32_s3_riscv_cop_flags.gmk index 89cfcb7dc..bce3b52d6 100644 --- a/ref_app/target/micros/xtensa_esp32_s3_riscv_cop/make/xtensa_esp32_s3_riscv_cop_flags.gmk +++ b/ref_app/target/micros/xtensa_esp32_s3_riscv_cop/make/xtensa_esp32_s3_riscv_cop_flags.gmk @@ -1,4 +1,4 @@ -# Copyright Christopher Kormanyos 2022 - 2025. +# Copyright Christopher Kormanyos 2022 - 2026. # Distributed under the Boost Software License, # Version 1.0. (See accompanying file LICENSE_1_0.txt # or copy at http://www.boost.org/LICENSE_1_0.txt) @@ -8,10 +8,10 @@ # compiler flags for the target architecture # ------------------------------------------------------------------------------ -GCC_TARGET := riscv-none-elf -GCC_PREFIX := riscv-none-elf +GCC_TARGET := riscv32-esp-elf +GCC_PREFIX := riscv32-esp-elf -GCC_VERSION := 15.2.0 +GCC_VERSION := 14.2.0 TGT_SUFFIX := elf From 63c9916b5e656f3ab6be78e2251255fcd48b4cae Mon Sep 17 00:00:00 2001 From: ckormanyos Date: Tue, 10 Feb 2026 12:45:57 +0100 Subject: [PATCH 04/11] Restore stm32f446 Boost benches --- .../target/build/test_app_benchmarks_stm32f446.sh | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/ref_app/target/build/test_app_benchmarks_stm32f446.sh b/ref_app/target/build/test_app_benchmarks_stm32f446.sh index ab93bdfa1..9b4312032 100755 --- a/ref_app/target/build/test_app_benchmarks_stm32f446.sh +++ b/ref_app/target/build/test_app_benchmarks_stm32f446.sh @@ -94,6 +94,15 @@ result_ls_wide_decimal=$? ls -la ./bin/app_benchmark_wide_integer.elf ./bin/app_benchmark_wide_integer.map result_ls_wide_integer=$? +ls -la ./bin/app_benchmark_boost_math_cbrt_tgamma.elf ./bin/app_benchmark_boost_math_cbrt_tgamma.map +result_ls_boost_math_cbrt_tgamma=$? + +ls -la ./bin/app_benchmark_boost_math_cyl_bessel_j.elf ./bin/app_benchmark_boost_math_cyl_bessel_j.map +result_ls_boost_math_cyl_bessel_j=$? + +ls -la ./bin/app_benchmark_boost_multiprecision_cbrt.elf ./bin/app_benchmark_boost_multiprecision_cbrt.map +result_ls_boost_multiprecision_cbrt=$? + ls -la ./bin/app_benchmark_hash_sha256.elf ./bin/app_benchmark_hash_sha256.map result_ls_hash_sha256=$? @@ -121,6 +130,9 @@ echo "result_ls_soft_double_h2f1 : " "$result_ls_soft_double_h2f1" echo "result_ls_trapezoid_integral : " "$result_ls_trapezoid_integral" echo "result_ls_wide_decimal : " "$result_ls_wide_decimal" echo "result_ls_wide_integer : " "$result_ls_wide_integer" +echo "result_ls_boost_math_cbrt_tgamma : " "$result_ls_boost_math_cbrt_tgamma" +echo "result_ls_boost_math_cyl_bessel_j : " "$result_ls_boost_math_cyl_bessel_j" +echo "result_ls_boost_multiprecision_cbrt : " "$result_ls_boost_multiprecision_cbrt" echo "result_ls_hash_sha256 : " "$result_ls_hash_sha256" echo "result_ls_ecc_generic_ecc : " "$result_ls_ecc_generic_ecc" echo "result_ls_non_std_decimal : " "$result_ls_non_std_decimal" From 5ef0b8d22e006b4d93b61fcbcaa4aa7916e604e2 Mon Sep 17 00:00:00 2001 From: ckormanyos Date: Wed, 11 Feb 2026 16:03:40 +0100 Subject: [PATCH 05/11] Recover PP-def and ensure both Cores run --- ref_app/src/mcal/am6254_soc/mcal_gpt.cpp | 20 +++- .../mcal/xtensa32/from_sdk/esp32-hal-gpio.h | 4 +- .../mcal/xtensa32/from_sdk/soc/gpio_struct.h | 4 +- ref_app/target.vcxproj | 3 +- ref_app/target.vcxproj.filters | 6 ++ .../xtensa_esp32_p4/make/xtensa_esp32_p4.ld | 2 + .../make/xtensa_esp32_p4_files.gmk | 3 +- .../make/xtensa_esp32_p4_flags.gmk | 9 +- .../xtensa_esp32_p4/startup/Code/Appli/main.c | 10 +- .../startup/Code/Startup/boot.s | 6 +- .../startup/Code/StdLib/StdLib.c | 99 +++++++++++++++++++ 11 files changed, 142 insertions(+), 24 deletions(-) create mode 100644 ref_app/target/micros/xtensa_esp32_p4/startup/Code/StdLib/StdLib.c diff --git a/ref_app/src/mcal/am6254_soc/mcal_gpt.cpp b/ref_app/src/mcal/am6254_soc/mcal_gpt.cpp index 61de864ea..6a4194859 100644 --- a/ref_app/src/mcal/am6254_soc/mcal_gpt.cpp +++ b/ref_app/src/mcal/am6254_soc/mcal_gpt.cpp @@ -1,5 +1,5 @@ /////////////////////////////////////////////////////////////////////////////// -// Copyright Christopher Kormanyos 2007 - 2025. +// Copyright Christopher Kormanyos 2007 - 2026. // Distributed under the Boost Software License, // Version 1.0. (See accompanying file LICENSE_1_0.txt // or copy at http://www.boost.org/LICENSE_1_0.txt) @@ -32,7 +32,11 @@ auto mcal::gpt::secure::get_time_elapsed_core1() -> mcal::gpt::value_type_core1 const value_type_core1 consistent_microsecond_tick = static_cast(ARM64_READ_SYSREG(CNTPCT_EL0)); // Convert the consistent tick to microseconds. - return static_cast(static_cast(consistent_microsecond_tick + UINT64_C(100)) / UINT64_C(200)); + return + static_cast + ( + static_cast(consistent_microsecond_tick + UINT64_C(100)) / UINT64_C(200) + ); } auto mcal::gpt::secure::get_time_elapsed_core2() -> mcal::gpt::value_type_core2 @@ -41,7 +45,11 @@ auto mcal::gpt::secure::get_time_elapsed_core2() -> mcal::gpt::value_type_core2 const value_type_core2 consistent_microsecond_tick = static_cast(ARM64_READ_SYSREG(CNTPCT_EL0)); // Convert the consistent tick to microseconds. - return static_cast(static_cast(consistent_microsecond_tick + UINT64_C(100)) / UINT64_C(200)); + return + static_cast + ( + static_cast(consistent_microsecond_tick + UINT64_C(100)) / UINT64_C(200) + ); } auto mcal::gpt::secure::get_time_elapsed_core3() -> mcal::gpt::value_type_core3 @@ -50,5 +58,9 @@ auto mcal::gpt::secure::get_time_elapsed_core3() -> mcal::gpt::value_type_core3 const value_type_core3 consistent_microsecond_tick = static_cast(ARM64_READ_SYSREG(CNTPCT_EL0)); // Convert the consistent tick to microseconds. - return static_cast(static_cast(consistent_microsecond_tick + UINT64_C(100)) / UINT64_C(200)); + return + static_cast + ( + static_cast(consistent_microsecond_tick + UINT64_C(100)) / UINT64_C(200) + ); } diff --git a/ref_app/src/mcal/xtensa32/from_sdk/esp32-hal-gpio.h b/ref_app/src/mcal/xtensa32/from_sdk/esp32-hal-gpio.h index 25478216c..c748b1251 100644 --- a/ref_app/src/mcal/xtensa32/from_sdk/esp32-hal-gpio.h +++ b/ref_app/src/mcal/xtensa32/from_sdk/esp32-hal-gpio.h @@ -28,7 +28,7 @@ #include - #ifdef __cplusplus + #if defined(__cplusplus) extern "C" { #endif @@ -57,7 +57,7 @@ void digitalWrite(const uint8_t pin, const uint8_t val); int digitalRead (const uint8_t pin); - #ifdef __cplusplus + #if defined(__cplusplus) } #endif diff --git a/ref_app/src/mcal/xtensa32/from_sdk/soc/gpio_struct.h b/ref_app/src/mcal/xtensa32/from_sdk/soc/gpio_struct.h index 4897726a2..fe328f5ed 100644 --- a/ref_app/src/mcal/xtensa32/from_sdk/soc/gpio_struct.h +++ b/ref_app/src/mcal/xtensa32/from_sdk/soc/gpio_struct.h @@ -27,7 +27,7 @@ #include -#ifdef __cplusplus +#if defined(__cplusplus) extern "C" { #endif @@ -222,7 +222,7 @@ typedef struct gpio_dev_t extern gpio_dev_t GPIO; -#ifdef __cplusplus +#if defined(__cplusplus) } #endif diff --git a/ref_app/target.vcxproj b/ref_app/target.vcxproj index 06bd2b8e0..78f80a38e 100644 --- a/ref_app/target.vcxproj +++ b/ref_app/target.vcxproj @@ -634,7 +634,7 @@ $(SolutionDir)src\util\STL_C++XX_stdfloat;$(SolutionDir)src\util\STL;$(SolutionDir)/src;$(SolutionDir)/src/mcal/stm32f446 $(ProjectDir)/src/util/STL_C++XX_stdfloat; $(ProjectDir)/src/util/STL; $(ProjectDir)/src; $(ProjectDir)/src/mcal/xtensa32; $(ProjectDir)/src/util/STL_C++XX_stdfloat; $(ProjectDir)/src/util/STL; $(ProjectDir)/src; $(ProjectDir)/src/mcal/xtensa_esp32_s3; - $(ProjectDir)/src/util/STL_C++XX_stdfloat; $(ProjectDir)/src/util/STL; $(ProjectDir)/src; $(ProjectDir)/src/mcal/xtensa_esp32_p4; + $(ProjectDir)/target/micros/xtensa_esp32_p4/startup/Code; $(ProjectDir)/target/micros/xtensa_esp32_p4/startup/Code/Appli; $(ProjectDir)/target/micros/xtensa_esp32_p4/startup/Code/Mcal; $(ProjectDir)/target/micros/xtensa_esp32_p4/startup/Code/Startup; $(ProjectDir)/src; $(ProjectDir)/src/mcal/xtensa_esp32_p4; $(ProjectDir)/src/util/STL_C++XX_stdfloat; $(ProjectDir)/src/util/STL; $(ProjectDir)/src; $(ProjectDir)/src/mcal/xtensa_esp32_s3; $(SolutionDir)src\util\STL_C++XX_stdfloat;$(SolutionDir)src\util\STL;$(SolutionDir)/src;$(SolutionDir)/src/mcal/stm32f429 $(SolutionDir)/src;$(SolutionDir)/src/mcal/am335x @@ -1287,6 +1287,7 @@ + diff --git a/ref_app/target.vcxproj.filters b/ref_app/target.vcxproj.filters index 0454f1c37..1613d4129 100644 --- a/ref_app/target.vcxproj.filters +++ b/ref_app/target.vcxproj.filters @@ -361,6 +361,9 @@ {17889d6f-9174-40cb-bcad-01e3995207e5} + + {509b8385-c65b-4236-9b5a-93e8cc7bf887} + @@ -1178,6 +1181,9 @@ micros\xtensa_esp32_p4\startup\Code\Startup + + micros\xtensa_esp32_p4\startup\StdLib + diff --git a/ref_app/target/micros/xtensa_esp32_p4/make/xtensa_esp32_p4.ld b/ref_app/target/micros/xtensa_esp32_p4/make/xtensa_esp32_p4.ld index 0685130e3..8e6286084 100644 --- a/ref_app/target/micros/xtensa_esp32_p4/make/xtensa_esp32_p4.ld +++ b/ref_app/target/micros/xtensa_esp32_p4/make/xtensa_esp32_p4.ld @@ -56,6 +56,7 @@ SECTIONS PROVIDE(__CODE_BASE_ADDRESS = .); *(.boot) *(.text) + *(.text*) . = ALIGN(4); } > FLASH @@ -64,6 +65,7 @@ SECTIONS { PROVIDE(__RODATA_BASE_ADDRESS = .); *(.rodata) + *(.rodata*) } > FLASH /* Section for constructors */ diff --git a/ref_app/target/micros/xtensa_esp32_p4/make/xtensa_esp32_p4_files.gmk b/ref_app/target/micros/xtensa_esp32_p4/make/xtensa_esp32_p4_files.gmk index d8463cb19..c78a6822a 100644 --- a/ref_app/target/micros/xtensa_esp32_p4/make/xtensa_esp32_p4_files.gmk +++ b/ref_app/target/micros/xtensa_esp32_p4/make/xtensa_esp32_p4_files.gmk @@ -15,4 +15,5 @@ FILES_TGT := $(PATH_TGT)/startup/Code/Appli/main $(PATH_TGT)/startup/Code/Mcal/gpio \ $(PATH_TGT)/startup/Code/Startup/boot \ $(PATH_TGT)/startup/Code/Startup/intvect \ - $(PATH_TGT)/startup/Code/Startup/Startup + $(PATH_TGT)/startup/Code/Startup/Startup \ + $(PATH_TGT)/startup/Code/StdLib/StdLib diff --git a/ref_app/target/micros/xtensa_esp32_p4/make/xtensa_esp32_p4_flags.gmk b/ref_app/target/micros/xtensa_esp32_p4/make/xtensa_esp32_p4_flags.gmk index 9cb63a7ce..005bcddad 100644 --- a/ref_app/target/micros/xtensa_esp32_p4/make/xtensa_esp32_p4_flags.gmk +++ b/ref_app/target/micros/xtensa_esp32_p4/make/xtensa_esp32_p4_flags.gmk @@ -23,11 +23,12 @@ TGT_ALLFLAGS = -O2 -msmall-data-limit=0 \ -ffreestanding \ -falign-functions=4 \ - -fomit-frame-pointer + -fomit-frame-pointer \ + -fno-reorder-blocks-and-partition \ + -fno-reorder-functions \ + -DHP_CORES_SMP_MODE - -TGT_CFLAGS = -std=c23 \ - -nostdlib \ +TGT_CFLAGS = -std=c11 \ $(TGT_ALLFLAGS) TGT_CXXFLAGS = -std=c++23 \ diff --git a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Appli/main.c b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Appli/main.c index 1742764f1..a88fb39a0 100644 --- a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Appli/main.c +++ b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Appli/main.c @@ -55,9 +55,7 @@ void __attribute__((interrupt)) Isr_TIMER_Interrupt(void); /// /// \return //----------------------------------------------------------------------------------------- -int main(void); - -int main(void) +void main(void) { osHwAcquireSpinLock(&sync_lock); /* output a text message on the uart console */ @@ -100,12 +98,10 @@ int main(void) CLINT_MTIMECTL |= (3ul << 4); /* set MTIME timeout to 500ms */ - CLINT_MTIMECMP = (uint64_t)(CLINT_MTIME + (TIMEOUT_500MS + TIMEOUT_500MS)); + CLINT_MTIMECMP = (uint64_t)(CLINT_MTIME + TIMEOUT_1S); /* endless loop */ while(1); - - return 0; } //----------------------------------------------------------------------------------------- @@ -117,7 +113,7 @@ int main(void) //----------------------------------------------------------------------------------------- void Isr_TIMER_Interrupt(void) { - CLINT_MTIMECMP = (uint64_t)(CLINT_MTIME + (TIMEOUT_500MS + TIMEOUT_500MS)); + CLINT_MTIMECMP = (uint64_t)(CLINT_MTIME + TIMEOUT_1S); if(0 == osGetActiveCore()) { diff --git a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Startup/boot.s b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Startup/boot.s index 9b87376bb..712babf48 100644 --- a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Startup/boot.s +++ b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Startup/boot.s @@ -53,8 +53,8 @@ _start: .L_core1: /* note: - RISC-V has no WFE/SEV instructions to synchronize SMP system - so I'm using CLINT to synchronize both HP cores on ESP32-P4. - - Core0 will set the software interrupt pending flag in Core1's CLINT + so I am using CLINT to synchronize both HP cores on ESP32-P4. + - Core0 will set the software interrupt pending flag in CLINT on Core1 once the runtime environment setup is complete. */ li a5, msip @@ -196,4 +196,4 @@ osHwReleaseSpinLock: lr.w a1, (a0) f18-27 | fs2-11 | FP saved registers | Callee f28-31 | ft8-11 | FP temporaries | Caller ----------------------------------------------------------------- -*/ \ No newline at end of file +*/ diff --git a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/StdLib/StdLib.c b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/StdLib/StdLib.c new file mode 100644 index 000000000..a7d98a5aa --- /dev/null +++ b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/StdLib/StdLib.c @@ -0,0 +1,99 @@ +/****************************************************************************************** + Filename : StdLib.c + + Author : Chalandi Amine + + Owner : Chalandi Amine + + Date : 22.02.2025 + + Description : Handwritten StdLib functions + +******************************************************************************************/ + +//============================================================================= +// Includes +//============================================================================= +#include +#include +#include + +//----------------------------------------------------------------------------- +/// \brief +/// +/// \descr +/// +/// \param +/// +/// \return +//----------------------------------------------------------------------------- +void *memset(void *str, int c, size_t n) +{ + uint8_t *ptr = (uint8_t *)str; + uint32_t value = (uint8_t)c; + + // Set value to repeat the byte across a 32-bit word + value |= value << 8; + value |= value << 16; + + // Align to the next 32-bit boundary + while (((uintptr_t)ptr & 3) && n > 0) { + *ptr++ = (uint8_t)c; + n--; + } + + // Set memory in 32-bit chunks + uint32_t *ptr32 = (uint32_t *)ptr; + while (n >= 4) { + *ptr32++ = value; + n -= 4; + } + + // Handle any remaining bytes + ptr = (uint8_t *)ptr32; + while (n > 0) { + *ptr++ = (uint8_t)c; + n--; + } + + return str; +} + +//----------------------------------------------------------------------------- +/// \brief +/// +/// \descr +/// +/// \param +/// +/// \return +//----------------------------------------------------------------------------- +void* memcpy (void* dest, const void * src, size_t n) +{ + uint8_t *d = (uint8_t *)dest; + const uint8_t *s = (const uint8_t *)src; + + // Align destination to the next 32-bit boundary + while (((uintptr_t)d & 3) && n > 0) { + *d++ = *s++; + n--; + } + + // Copy memory in 32-bit chunks + uint32_t *d32 = (uint32_t *)d; + const uint32_t *s32 = (const uint32_t *)s; + while (n >= 4) { + *d32++ = *s32++; + n -= 4; + } + + // Handle any remaining bytes + d = (uint8_t *)d32; + s = (const uint8_t *)s32; + while (n > 0) { + *d++ = *s++; + n--; + } + + return dest; +} From b7b45bf7501c633dbc84ecaa94f38d1152726315 Mon Sep 17 00:00:00 2001 From: ckormanyos Date: Wed, 11 Feb 2026 17:29:49 +0100 Subject: [PATCH 06/11] Very preliminary adaptions toward CPP --- ref_app/target.vcxproj | 3 +- ref_app/target.vcxproj.filters | 8 +- .../make/xtensa_esp32_p4_files.gmk | 3 +- .../xtensa_esp32_p4/startup/Code/Appli/main.c | 127 ------------------ .../startup/Code/Appli/main.cpp | 106 +++++++++++++++ .../startup/Code/Mcal/esp32p4.h | 12 +- .../xtensa_esp32_p4/startup/Code/Mcal/gpio.h | 12 +- .../startup/Code/Mcal/interrupt.h | 8 ++ .../startup/Code/Mcal/riscv-csr.h | 8 ++ .../startup/Code/Startup/Startup.c | 2 +- .../startup/Code/StdLib/StdLib.c | 99 -------------- 11 files changed, 143 insertions(+), 245 deletions(-) delete mode 100644 ref_app/target/micros/xtensa_esp32_p4/startup/Code/Appli/main.c create mode 100644 ref_app/target/micros/xtensa_esp32_p4/startup/Code/Appli/main.cpp delete mode 100644 ref_app/target/micros/xtensa_esp32_p4/startup/Code/StdLib/StdLib.c diff --git a/ref_app/target.vcxproj b/ref_app/target.vcxproj index 78f80a38e..219b3e6d3 100644 --- a/ref_app/target.vcxproj +++ b/ref_app/target.vcxproj @@ -1283,11 +1283,10 @@ - + - diff --git a/ref_app/target.vcxproj.filters b/ref_app/target.vcxproj.filters index 1613d4129..4a36470f9 100644 --- a/ref_app/target.vcxproj.filters +++ b/ref_app/target.vcxproj.filters @@ -361,9 +361,6 @@ {17889d6f-9174-40cb-bcad-01e3995207e5} - - {509b8385-c65b-4236-9b5a-93e8cc7bf887} - @@ -1169,7 +1166,7 @@ micros\r7fa4m1ab\startup - + micros\xtensa_esp32_p4\startup\Code\Appli @@ -1181,9 +1178,6 @@ micros\xtensa_esp32_p4\startup\Code\Startup - - micros\xtensa_esp32_p4\startup\StdLib - diff --git a/ref_app/target/micros/xtensa_esp32_p4/make/xtensa_esp32_p4_files.gmk b/ref_app/target/micros/xtensa_esp32_p4/make/xtensa_esp32_p4_files.gmk index c78a6822a..d8463cb19 100644 --- a/ref_app/target/micros/xtensa_esp32_p4/make/xtensa_esp32_p4_files.gmk +++ b/ref_app/target/micros/xtensa_esp32_p4/make/xtensa_esp32_p4_files.gmk @@ -15,5 +15,4 @@ FILES_TGT := $(PATH_TGT)/startup/Code/Appli/main $(PATH_TGT)/startup/Code/Mcal/gpio \ $(PATH_TGT)/startup/Code/Startup/boot \ $(PATH_TGT)/startup/Code/Startup/intvect \ - $(PATH_TGT)/startup/Code/Startup/Startup \ - $(PATH_TGT)/startup/Code/StdLib/StdLib + $(PATH_TGT)/startup/Code/Startup/Startup diff --git a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Appli/main.c b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Appli/main.c deleted file mode 100644 index a88fb39a0..000000000 --- a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Appli/main.c +++ /dev/null @@ -1,127 +0,0 @@ -/****************************************************************************************** - Filename : main.c - - Core : RISC-V - - MCU : ESP32-P4 - - Author : Chalandi Amine - - Owner : Chalandi Amine - - Date : 25.01.2026 - - Description : Application main function - -******************************************************************************************/ - -//----------------------------------------------------------------------------------------- -// Includes -//----------------------------------------------------------------------------------------- -#include -#include -#include "riscv-csr.h" -#include "esp32p4.h" -#include "interrupt.h" -#include "gpio.h" - -//----------------------------------------------------------------------------------------- -// Defines -//----------------------------------------------------------------------------------------- -#define TIMEOUT_500MS 160000000ull -#define TIMEOUT_1S 320000000ull - -//----------------------------------------------------------------------------------------- -// Macros -//----------------------------------------------------------------------------------------- - -//----------------------------------------------------------------------------------------- -// Globals -//----------------------------------------------------------------------------------------- -uint32_t sync_lock = 0; - -//----------------------------------------------------------------------------------------- -// Function Prototypes -//----------------------------------------------------------------------------------------- -void osHwAcquireSpinLock(uint32_t* lock); -void osHwReleaseSpinLock(uint32_t* lock); -uint32_t osGetActiveCore(void); -void __attribute__((interrupt)) Isr_TIMER_Interrupt(void); - -//----------------------------------------------------------------------------------------- -/// \brief -/// -/// \param -/// -/// \return -//----------------------------------------------------------------------------------------- -void main(void) -{ - osHwAcquireSpinLock(&sync_lock); - /* output a text message on the uart console */ - printf("BareMetal ESP32-P4 SW is Alive on HP core%ld!\n\r", osGetActiveCore()); - osHwReleaseSpinLock(&sync_lock); - - if(0 == osGetActiveCore()) - { - gpio_cfg_output(7); - gpio_cfg_output(8); - gpio_cfg_output(24); - gpio_cfg_output(25); - gpio_cfg_output(46); - gpio_cfg_output(47); - gpio_cfg_output(48); - gpio_cfg_output(54); - gpio_cfg_output(20); - gpio_cfg_output(19); - gpio_cfg_output(18); - gpio_cfg_output(17); - gpio_cfg_output(16); - gpio_cfg_output(15); - gpio_cfg_output(14); - gpio_cfg_output(33); - gpio_cfg_output(32); - gpio_cfg_output(27); - gpio_cfg_output(26); - gpio_cfg_output(23); - gpio_cfg_output(32); - gpio_cfg_output(21); - } - - /* set the timer interrupt as hardware vectored in the CLIC */ - CLIC->interrupt[INT_TIMER_ID].clicintattr = 1; - - /* enable timer machine interrupt in the CLIC */ - CLIC->interrupt[INT_TIMER_ID].clicintie = 1; - - /* configure the sampling mode of MTIME */ - CLINT_MTIMECTL |= (3ul << 4); - - /* set MTIME timeout to 500ms */ - CLINT_MTIMECMP = (uint64_t)(CLINT_MTIME + TIMEOUT_1S); - - /* endless loop */ - while(1); -} - -//----------------------------------------------------------------------------------------- -/// \brief -/// -/// \param -/// -/// \return -//----------------------------------------------------------------------------------------- -void Isr_TIMER_Interrupt(void) -{ - CLINT_MTIMECMP = (uint64_t)(CLINT_MTIME + TIMEOUT_1S); - - if(0 == osGetActiveCore()) - { - gpio_toggle_output_level(54); - } - else - { - gpio_toggle_output_level(19); - } -} - diff --git a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Appli/main.cpp b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Appli/main.cpp new file mode 100644 index 000000000..b85aa8e5e --- /dev/null +++ b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Appli/main.cpp @@ -0,0 +1,106 @@ +/****************************************************************************************** + Filename : main.c + + Core : RISC-V + + MCU : ESP32-P4 + + Author : Chalandi Amine + + Owner : Chalandi Amine + + Date : 25.01.2026 + + Description : Application main function + +******************************************************************************************/ + +#include +#include +#include +#include + +#include +#include + +constexpr unsigned TIMEOUT_500MS { 160000000u }; +constexpr unsigned TIMEOUT_1S { 320000000u }; + +extern "C" +{ + uint32_t sync_lock; + + void osHwAcquireSpinLock(uint32_t* lock); + void osHwReleaseSpinLock(uint32_t* lock); + uint32_t osGetActiveCore(void); + void __attribute__((interrupt)) Isr_TIMER_Interrupt(void); +} + +auto main(void) -> int __attribute__((used,noinline)); + +auto main(void) -> int +{ + osHwAcquireSpinLock(&sync_lock); + /* output a text message on the uart console */ + printf("BareMetal ESP32-P4 SW is Alive on HP core%ld!\n\r", osGetActiveCore()); + osHwReleaseSpinLock(&sync_lock); + + if(0 == osGetActiveCore()) + { + gpio_cfg_output(7); + gpio_cfg_output(8); + gpio_cfg_output(24); + gpio_cfg_output(25); + gpio_cfg_output(46); + gpio_cfg_output(47); + gpio_cfg_output(48); + gpio_cfg_output(54); + gpio_cfg_output(20); + gpio_cfg_output(19); + gpio_cfg_output(18); + gpio_cfg_output(17); + gpio_cfg_output(16); + gpio_cfg_output(15); + gpio_cfg_output(14); + gpio_cfg_output(33); + gpio_cfg_output(32); + gpio_cfg_output(27); + gpio_cfg_output(26); + gpio_cfg_output(23); + gpio_cfg_output(32); + gpio_cfg_output(21); + } + + /* set the timer interrupt as hardware vectored in the CLIC */ + CLIC->interrupt[INT_TIMER_ID].clicintattr = 1; + + /* enable timer machine interrupt in the CLIC */ + CLIC->interrupt[INT_TIMER_ID].clicintie = 1; + + /* configure the sampling mode of MTIME */ + CLINT_MTIMECTL |= (3ul << 4); + + /* set MTIME timeout to 500ms */ + CLINT_MTIMECMP = (uint64_t)(CLINT_MTIME + TIMEOUT_1S); + + /* endless loop */ + while(1) + { + asm volatile("nop"); + } +} + +extern "C" +void Isr_TIMER_Interrupt(void) +{ + CLINT_MTIMECMP = (uint64_t)(CLINT_MTIME + TIMEOUT_1S); + + if(0 == osGetActiveCore()) + { + gpio_toggle_output_level(54); + } + else + { + gpio_toggle_output_level(19); + } +} diff --git a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/esp32p4.h b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/esp32p4.h index d4c2d5dc2..ea7077918 100644 --- a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/esp32p4.h +++ b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/esp32p4.h @@ -2,19 +2,19 @@ #ifndef ESP32_P4_H #define ESP32_P4_H -#ifdef __cplusplus -extern "C" { -#endif - - #include #include #include + #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ +#if defined(__cplusplus) +extern "C" +{ +#endif /* =========================================================================================================================== */ /* ================ Interrupt Number Definition ================ */ @@ -63857,7 +63857,7 @@ typedef struct { /*!< USB_WRAP Structure #define USB_WRAP ((USB_WRAP_Type*) USB_WRAP_BASE) -#ifdef __cplusplus +#if defined(__cplusplus) } #endif diff --git a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/gpio.h b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/gpio.h index 7cc4b305a..63ad51656 100644 --- a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/gpio.h +++ b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/gpio.h @@ -19,13 +19,23 @@ //----------------------------------------------------------------------------------------- // Includes //----------------------------------------------------------------------------------------- + +#include + #include #include -#include "esp32p4.h" +#if defined(__cplusplus) +extern "C" +{ +#endif void gpio_cfg_output(uint8_t pin); void gpio_set_output_level(uint8_t pin, uint8_t level); void gpio_toggle_output_level(uint8_t pin); +#if defined(__cplusplus) +} +#endif + #endif /*__GPIO_H__*/ diff --git a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/interrupt.h b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/interrupt.h index 05df0841a..a49c2f105 100644 --- a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/interrupt.h +++ b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/interrupt.h @@ -20,6 +20,11 @@ #include +#if defined(__cplusplus) +extern "C" +{ +#endif + typedef struct { uint8_t clicintip; /* Interrupt pending register */ @@ -81,5 +86,8 @@ typedef struct { #define EXT_INT30_ID 46 #define EXT_INT31_ID 47 +#if defined(__cplusplus) +} +#endif #endif /* __INTERRUPT_H__ */ diff --git a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/riscv-csr.h b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/riscv-csr.h index bdbc31b8d..9a7c4f779 100644 --- a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/riscv-csr.h +++ b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/riscv-csr.h @@ -11,6 +11,11 @@ #include +#if defined(__cplusplus) +extern "C" +{ +#endif + #if __riscv_xlen==32 typedef uint32_t uint_xlen_t; typedef uint32_t uint_csr32_t; @@ -3787,5 +3792,8 @@ static inline uint_xlen_t csr_read_write_mtval2(uint_xlen_t new_value) { return prev_value; } +#if defined(__cplusplus) +} +#endif #endif // #define RISCV_CSR_H diff --git a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Startup/Startup.c b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Startup/Startup.c index 22fe90751..7545ffb45 100644 --- a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Startup/Startup.c +++ b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Startup/Startup.c @@ -56,7 +56,7 @@ static void Startup_InitMcuSystem(void); //========================================================================================= // Extern function prototype //========================================================================================= -int main(void) __attribute__((weak)); +extern int main(void) __attribute__((used,noinline)); //----------------------------------------------------------------------------------------- /// \brief Startup_Init function diff --git a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/StdLib/StdLib.c b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/StdLib/StdLib.c deleted file mode 100644 index a7d98a5aa..000000000 --- a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/StdLib/StdLib.c +++ /dev/null @@ -1,99 +0,0 @@ -/****************************************************************************************** - Filename : StdLib.c - - Author : Chalandi Amine - - Owner : Chalandi Amine - - Date : 22.02.2025 - - Description : Handwritten StdLib functions - -******************************************************************************************/ - -//============================================================================= -// Includes -//============================================================================= -#include -#include -#include - -//----------------------------------------------------------------------------- -/// \brief -/// -/// \descr -/// -/// \param -/// -/// \return -//----------------------------------------------------------------------------- -void *memset(void *str, int c, size_t n) -{ - uint8_t *ptr = (uint8_t *)str; - uint32_t value = (uint8_t)c; - - // Set value to repeat the byte across a 32-bit word - value |= value << 8; - value |= value << 16; - - // Align to the next 32-bit boundary - while (((uintptr_t)ptr & 3) && n > 0) { - *ptr++ = (uint8_t)c; - n--; - } - - // Set memory in 32-bit chunks - uint32_t *ptr32 = (uint32_t *)ptr; - while (n >= 4) { - *ptr32++ = value; - n -= 4; - } - - // Handle any remaining bytes - ptr = (uint8_t *)ptr32; - while (n > 0) { - *ptr++ = (uint8_t)c; - n--; - } - - return str; -} - -//----------------------------------------------------------------------------- -/// \brief -/// -/// \descr -/// -/// \param -/// -/// \return -//----------------------------------------------------------------------------- -void* memcpy (void* dest, const void * src, size_t n) -{ - uint8_t *d = (uint8_t *)dest; - const uint8_t *s = (const uint8_t *)src; - - // Align destination to the next 32-bit boundary - while (((uintptr_t)d & 3) && n > 0) { - *d++ = *s++; - n--; - } - - // Copy memory in 32-bit chunks - uint32_t *d32 = (uint32_t *)d; - const uint32_t *s32 = (const uint32_t *)s; - while (n >= 4) { - *d32++ = *s32++; - n -= 4; - } - - // Handle any remaining bytes - d = (uint8_t *)d32; - s = (const uint8_t *)s32; - while (n > 0) { - *d++ = *s++; - n--; - } - - return dest; -} From 8fbf20dfee59fe826d07ef5d73ae58f515c818d6 Mon Sep 17 00:00:00 2001 From: ckormanyos Date: Thu, 12 Feb 2026 09:10:27 +0100 Subject: [PATCH 07/11] Additional slight adaptions --- ref_app/ref_app.vcxproj | 7 +- ref_app/ref_app.vcxproj.filters | 6 +- ref_app/src/mcal/riscvfe310/mcal_gpt.cpp | 6 +- ref_app/src/mcal/xtensa_esp32_p4/mcal_reg.h | 30 +++++++ .../mcal/xtensa_esp32_p4/xtensa_esp32_p4.txt | 1 - .../startup/Code/Appli/main.cpp | 26 ++---- .../xtensa_esp32_p4/startup/Code/Mcal/gpio.c | 84 +++++++++++-------- .../startup/Code/Mcal/interrupt.h | 13 +-- .../startup/Code/Startup/Startup.c | 32 ++++--- 9 files changed, 127 insertions(+), 78 deletions(-) create mode 100644 ref_app/src/mcal/xtensa_esp32_p4/mcal_reg.h delete mode 100644 ref_app/src/mcal/xtensa_esp32_p4/xtensa_esp32_p4.txt diff --git a/ref_app/ref_app.vcxproj b/ref_app/ref_app.vcxproj index ca04871fe..011c2df94 100644 --- a/ref_app/ref_app.vcxproj +++ b/ref_app/ref_app.vcxproj @@ -3233,6 +3233,10 @@ true true + + true + true + true true @@ -3733,9 +3737,6 @@ true true - - true - diff --git a/ref_app/ref_app.vcxproj.filters b/ref_app/ref_app.vcxproj.filters index 414c0eb0a..03e4b9955 100644 --- a/ref_app/ref_app.vcxproj.filters +++ b/ref_app/ref_app.vcxproj.filters @@ -3123,6 +3123,9 @@ src\mcal\r7fa4m1ab + + src\mcal\xtensa_esp32_p4 + @@ -3368,8 +3371,5 @@ tools\Util\msys64\usr\bin - - src\mcal\xtensa_esp32_p4 - \ No newline at end of file diff --git a/ref_app/src/mcal/riscvfe310/mcal_gpt.cpp b/ref_app/src/mcal/riscvfe310/mcal_gpt.cpp index 913549e1a..b2dc1aca6 100644 --- a/ref_app/src/mcal/riscvfe310/mcal_gpt.cpp +++ b/ref_app/src/mcal/riscvfe310/mcal_gpt.cpp @@ -87,18 +87,18 @@ void mcal::gpt::init(const config_type*) using clint_mtimecmp_reg_address_type = std::uint32_t; using clint_mtimecmp_reg_value_type = std::uint64_t; - using clint_mtimecmp_reg_access_type = + using clint_mtimecmp_reg_set_type = mcal::reg::reg_access_static::max)()>; - static_assert(std::is_same::value, + static_assert(std::is_same::value, "Error: Unexpected clint_mtimecmp register value type"); // Set the 64-bit mtimer compare register to its maximum value. // This results in an essentially infinite timeout. - clint_mtimecmp_reg_access_type::reg_set(); + clint_mtimecmp_reg_set_type::reg_set(); gpt_is_initialized() = true; } diff --git a/ref_app/src/mcal/xtensa_esp32_p4/mcal_reg.h b/ref_app/src/mcal/xtensa_esp32_p4/mcal_reg.h new file mode 100644 index 000000000..f2075b04e --- /dev/null +++ b/ref_app/src/mcal/xtensa_esp32_p4/mcal_reg.h @@ -0,0 +1,30 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright Christopher Kormanyos 2026. +// Distributed under the Boost Software License, +// Version 1.0. (See accompanying file LICENSE_1_0.txt +// or copy at http://www.boost.org/LICENSE_1_0.txt) +// + +#ifndef MCAL_REG_2026_02_11_H + #define MCAL_REG_2026_02_11_H + + #include + + namespace mcal + { + namespace reg + { + constexpr std::uint32_t clint_base { UINT32_C(0x02000000) }; + constexpr std::uint32_t clint_mtime { clint_base + static_cast(UINT32_C(0x0000BFF8)) }; + constexpr std::uint32_t clint_mtimeh { clint_base + static_cast(UINT32_C(0x0000BFFC)) }; + constexpr std::uint32_t clint_mtimecmp { clint_base + static_cast(UINT32_C(0x00004000)) }; + constexpr std::uint32_t clint_mtimecmph { clint_base + static_cast(UINT32_C(0x00004004)) }; + + constexpr std::uint32_t clic_base { UINT32_C(0x20800000) }; + } + } + + #include + #include + +#endif // MCAL_REG_2026_02_11_H diff --git a/ref_app/src/mcal/xtensa_esp32_p4/xtensa_esp32_p4.txt b/ref_app/src/mcal/xtensa_esp32_p4/xtensa_esp32_p4.txt deleted file mode 100644 index 86696a278..000000000 --- a/ref_app/src/mcal/xtensa_esp32_p4/xtensa_esp32_p4.txt +++ /dev/null @@ -1 +0,0 @@ -xtensa_esp32_p4.txt diff --git a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Appli/main.cpp b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Appli/main.cpp index b85aa8e5e..ab0da8236 100644 --- a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Appli/main.cpp +++ b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Appli/main.cpp @@ -20,7 +20,6 @@ #include #include -#include #include constexpr unsigned TIMEOUT_500MS { 160000000u }; @@ -28,10 +27,6 @@ constexpr unsigned TIMEOUT_1S { 320000000u }; extern "C" { - uint32_t sync_lock; - - void osHwAcquireSpinLock(uint32_t* lock); - void osHwReleaseSpinLock(uint32_t* lock); uint32_t osGetActiveCore(void); void __attribute__((interrupt)) Isr_TIMER_Interrupt(void); } @@ -40,11 +35,6 @@ auto main(void) -> int __attribute__((used,noinline)); auto main(void) -> int { - osHwAcquireSpinLock(&sync_lock); - /* output a text message on the uart console */ - printf("BareMetal ESP32-P4 SW is Alive on HP core%ld!\n\r", osGetActiveCore()); - osHwReleaseSpinLock(&sync_lock); - if(0 == osGetActiveCore()) { gpio_cfg_output(7); @@ -71,19 +61,19 @@ auto main(void) -> int gpio_cfg_output(21); } - /* set the timer interrupt as hardware vectored in the CLIC */ + // Set the timer interrupt as hardware vectored in the CLIC. CLIC->interrupt[INT_TIMER_ID].clicintattr = 1; - /* enable timer machine interrupt in the CLIC */ + // Enable the timer machine interrupt in the CLIC. CLIC->interrupt[INT_TIMER_ID].clicintie = 1; - /* configure the sampling mode of MTIME */ + // Configure the sampling mode of MTIME. CLINT_MTIMECTL |= (3ul << 4); - /* set MTIME timeout to 500ms */ + // Set the MTIME timeout. CLINT_MTIMECMP = (uint64_t)(CLINT_MTIME + TIMEOUT_1S); - /* endless loop */ + // Endless loop: Never return or break. while(1) { asm volatile("nop"); @@ -95,11 +85,13 @@ void Isr_TIMER_Interrupt(void) { CLINT_MTIMECMP = (uint64_t)(CLINT_MTIME + TIMEOUT_1S); - if(0 == osGetActiveCore()) + const std::uint32_t core_id { osGetActiveCore() }; + + if(std::uint32_t { UINT8_C(0) } == core_id) { gpio_toggle_output_level(54); } - else + else if(std::uint32_t { UINT8_C(1) } == core_id) { gpio_toggle_output_level(19); } diff --git a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/gpio.c b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/gpio.c index 4e65a4cff..d13f265b4 100644 --- a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/gpio.c +++ b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/gpio.c @@ -18,17 +18,19 @@ //----------------------------------------------------------------------------------------- // Includes //----------------------------------------------------------------------------------------- -#include "gpio.h" +#include //----------------------------------------------------------------------------------------- // Types //----------------------------------------------------------------------------------------- -typedef union { +typedef union +{ volatile uint32_t reg; - - struct { + + struct + { volatile uint32_t MCU_OE : 1; volatile uint32_t SLP_SEL : 1; volatile uint32_t MCU_WPD : 1; @@ -42,25 +44,33 @@ typedef union { volatile uint32_t MCU_SEL : 3; volatile uint32_t FILTER_EN : 1; uint32_t : 16; - } bit; -} IO_MUX_GPIO; + } + bit; +} +IO_MUX_GPIO; -typedef union { +typedef union +{ __IOM uint32_t reg; - - struct { + + struct + { __IOM uint32_t OUT_SEL : 9; __IOM uint32_t INV_SEL : 1; __IOM uint32_t OEN_SEL : 1; __IOM uint32_t OEN_INV_SEL : 1; uint32_t : 20; - } bit; -} GPIO_FUNC_OUT_SEL_CFG; + } + bit; +} +GPIO_FUNC_OUT_SEL_CFG; -typedef union { +typedef union +{ __IOM uint32_t reg; - - struct { + + struct + { __IOM uint32_t REG_PAD_DRV : 2; __IOM uint32_t REG_PAD_RDE : 1; __IOM uint32_t REG_PAD_RUE : 1; @@ -72,8 +82,10 @@ typedef union { __IOM uint32_t REG_PAD_FUN_IE : 1; __IOM uint32_t REG_PAD_FILTER_EN : 1; uint32_t : 20; - } bit; -} LP_IO_MUX_GPIO; + } + bit; +} +LP_IO_MUX_GPIO; //----------------------------------------------------------------------------------------- /// \brief @@ -84,14 +96,16 @@ typedef union { //----------------------------------------------------------------------------------------- void gpio_cfg_output(uint8_t pin) { - if(pin > 54) - return; - - volatile IO_MUX_GPIO* pIO_MUX_GPIO = (volatile IO_MUX_GPIO*)(IO_MUX_BASE + 4ul + 4ul*pin); - volatile GPIO_FUNC_OUT_SEL_CFG* pGPIO_FUNC_OUT_SEL_CFG = (volatile GPIO_FUNC_OUT_SEL_CFG*)(GPIO_BASE + 0x558ul + 4ul*pin); - volatile LP_IO_MUX_GPIO* pLP_IO_MUX_GPIO = (volatile LP_IO_MUX_GPIO*)(LP_IO_MUX_BASE + 8ul + 4ul*pin); - volatile uint32_t* pGPIO_OUTx_W1TC = (volatile uint32_t*)(GPIO_BASE + ((pin < 32u) ? (0x0Cul) : (0x18ul))); - volatile uint32_t* pGPIO_ENABLE1x_W1TS = (volatile uint32_t*)(GPIO_BASE + ((pin < 32u) ? (0x24ul) : (0x30ul))); + if((unsigned) pin > 54u) + { + return; + } + + volatile IO_MUX_GPIO* pIO_MUX_GPIO = (volatile IO_MUX_GPIO*)(IO_MUX_BASE + 4u + 4u * (unsigned) pin); + volatile GPIO_FUNC_OUT_SEL_CFG* pGPIO_FUNC_OUT_SEL_CFG = (volatile GPIO_FUNC_OUT_SEL_CFG*)(GPIO_BASE + 0x558ul + 4u * (unsigned) pin); + volatile LP_IO_MUX_GPIO* pLP_IO_MUX_GPIO = (volatile LP_IO_MUX_GPIO*)(LP_IO_MUX_BASE + 8u + 4u * (unsigned) pin); + volatile uint32_t* pGPIO_OUTx_W1TC = (volatile uint32_t*)(GPIO_BASE + (((unsigned) pin < 32u) ? 0x0Cu : 0x18u)); + volatile uint32_t* pGPIO_ENABLE1x_W1TS = (volatile uint32_t*)(GPIO_BASE + (((unsigned) pin < 32u) ? 0x24u : 0x30u)); /* configure the pinmux */ pIO_MUX_GPIO->bit.FUN_DRV = 2; @@ -109,8 +123,8 @@ void gpio_cfg_output(uint8_t pin) } /* drive the IO output low */ - *pGPIO_OUTx_W1TC = (uint32_t)(1ul << ((pin < 32ul) ? (pin) : (pin - 32ul))); - *pGPIO_ENABLE1x_W1TS = (uint32_t)(1ul << ((pin < 32ul) ? (pin) : (pin - 32ul))); + *pGPIO_OUTx_W1TC = (uint32_t)(1u << (((unsigned) pin < 32u) ? (unsigned) pin : ((unsigned) pin - 32u))); + *pGPIO_ENABLE1x_W1TS = (uint32_t)(1u << (((unsigned) pin < 32u) ? (unsigned) pin : ((unsigned) pin - 32u))); } //----------------------------------------------------------------------------------------- @@ -122,12 +136,14 @@ void gpio_cfg_output(uint8_t pin) //----------------------------------------------------------------------------------------- void gpio_set_output_level(uint8_t pin, uint8_t level) { - volatile uint32_t* pGPIO_OUT_W1Tx = (volatile uint32_t*)(GPIO_BASE + ((pin < 32u) ? (8ul) : (0x14ul)) + ((level == 1u) ? (0ul) : (4ul))); + volatile uint32_t* pGPIO_OUT_W1Tx = (volatile uint32_t*)(GPIO_BASE + (((unsigned) pin < 32u) ? 8u : 0x14u) + (((unsigned) level == 1u) ? (0u) : (4u))); - if((pin > 54) && (level > 1)) + if(((unsigned) pin > 54u) || ((unsigned) level > 1u)) + { return; + } - *pGPIO_OUT_W1Tx = (uint32_t)(1ul << ((pin < 32ul) ? (pin) : (pin - 32ul))); + *pGPIO_OUT_W1Tx = (uint32_t)(1u << (((unsigned) pin < 32u) ? (unsigned) pin : ((unsigned) pin - 32u))); } //----------------------------------------------------------------------------------------- @@ -139,10 +155,12 @@ void gpio_set_output_level(uint8_t pin, uint8_t level) //----------------------------------------------------------------------------------------- void gpio_toggle_output_level(uint8_t pin) { - volatile uint32_t* pGPIO_OUT = (volatile uint32_t*)(GPIO_BASE + 4ul + ((pin < 32u) ? 0ul : 0xcul)); + volatile uint32_t* pGPIO_OUT = (volatile uint32_t*)(GPIO_BASE + 4u + (((unsigned) pin < 32u) ? 0u : 0xCu)); - if(pin > 54) + if((unsigned) pin > 54u) + { return; + } - *pGPIO_OUT ^= (uint32_t)(1ul << ((pin < 32u) ? (pin) : (pin - 32u))); -} \ No newline at end of file + *pGPIO_OUT ^= (uint32_t)(1u << (((unsigned) pin < 32u) ? (unsigned) pin : ((unsigned) pin - 32u))); +} diff --git a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/interrupt.h b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/interrupt.h index a49c2f105..d82de87c6 100644 --- a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/interrupt.h +++ b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/interrupt.h @@ -25,21 +25,24 @@ extern "C" { #endif -typedef struct { +typedef struct +{ uint8_t clicintip; /* Interrupt pending register */ uint8_t clicintie; /* Interrupt enable register */ uint8_t clicintattr; /* Interrupt attribute register */ uint8_t clicintct; /* Interrupt level control register*/ -}clicint_t; - -typedef struct { +} +clicint_t; +typedef struct +{ uint32_t mcliccfg; /* CLIC machine mode global configuration register */ uint32_t clicinfo; /* CLIC information register */ uint32_t mintthresh; /* CLIC machine mode interrupt threshold register */ clicint_t interrupt[48] __attribute__((aligned(0x1000))); /* CLIC interrupt configuration registers */ -}clic_t; +} +clic_t; #define CLIC_BASE 0x20800000ul #define CLIC ((volatile clic_t*)(CLIC_BASE)) diff --git a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Startup/Startup.c b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Startup/Startup.c index 7545ffb45..0fd67d085 100644 --- a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Startup/Startup.c +++ b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Startup/Startup.c @@ -21,13 +21,15 @@ typedef struct unsigned long sourceAddr; /* Source Address (section in ROM memory) */ unsigned long targetAddr; /* Target Address (section in RAM memory) */ unsigned long size; /* length of section (bytes) */ -} runtimeCopyTable_t; +} +runtimeCopyTable_t; typedef struct { unsigned long addr; /* Source Address (section in RAM memory) */ unsigned long size; /* Length of section (bytes) */ -} runtimeClearTable_t; +} +runtimeClearTable_t; //========================================================================================= // Linker variables @@ -69,16 +71,15 @@ void Startup_Init(void) { /* Initialize the MCU system */ Startup_InitMcuSystem(); - + /* Initialize the RAM memory */ Startup_InitRam(); - + /* Initialize the non-local C++ objects */ Startup_InitCtors(); - + /* Run the main application */ Startup_RunApplication(); - } //----------------------------------------------------------------------------------------- @@ -150,16 +151,20 @@ static void Startup_RunApplication(void) if((unsigned int) &main != 0) { #ifdef HP_CORES_SMP_MODE - /* note: RISC-V has no WFE/SEV instructions to synchronize SMP system - so I'm using CLINT to synchronize both HP cores on ESP32-P4 */ - /* notify core1 that the setup of the runtime environment is done (by setting the SW interrupt pending bit on the core1's CLINT) */ + // note: RISC-V has no WFE/SEV instructions to synchronize SMP system + // so I am using CLINT to synchronize both HP cores on ESP32-P4 + + // Notify core1 that the setup of the runtime environment is done + // by setting the SW interrupt pending bit in CLINT on core1. + *(volatile uint32_t*)0x20010000 = 1; #endif - /* Call the main function */ + + // Call the main function. main(); } - /* Catch unexpected exit from main or if main does not exist */ + // Catch unexpected exit from main or if main does not exist. Startup_Unexpected_Exit(); } @@ -174,6 +179,7 @@ static void Startup_Unexpected_Exit(void) { for(;;); } + //----------------------------------------------------------------------------------------- /// \brief Startup_InitMcuSystem function /// @@ -183,5 +189,5 @@ static void Startup_Unexpected_Exit(void) //----------------------------------------------------------------------------------------- static void Startup_InitMcuSystem(void) { - /* system clock is set by the SBL */ -} \ No newline at end of file + // The system clock is set by the SBL. +} From d414c59321114c3a8947e1d7a2fb679b7cf226e9 Mon Sep 17 00:00:00 2001 From: ckormanyos Date: Thu, 12 Feb 2026 14:40:38 +0100 Subject: [PATCH 08/11] Very prelim multi-channel GPT cores0/1 --- ref_app/ref_app.vcxproj | 16 ++++ ref_app/ref_app.vcxproj.filters | 12 +++ ref_app/src/mcal/xtensa_esp32_p4/mcal_gpt.cpp | 56 ++++++++++++++ ref_app/src/mcal/xtensa_esp32_p4/mcal_gpt.h | 37 ++++++++++ ref_app/src/mcal/xtensa_esp32_p4/mcal_reg.h | 2 +- ref_app/src/mcal/xtensa_esp32_p4/mcal_wdg.cpp | 17 +++++ ref_app/src/mcal/xtensa_esp32_p4/mcal_wdg.h | 26 +++++++ .../xtensa_esp32_p4/make/xtensa_esp32_p4.ld | 43 ++++++++++- .../make/xtensa_esp32_p4_files.gmk | 6 +- .../startup/Code/Appli/main.cpp | 73 +++++++++++++------ .../startup/Code/Startup/intvect.c | 3 +- 11 files changed, 263 insertions(+), 28 deletions(-) create mode 100644 ref_app/src/mcal/xtensa_esp32_p4/mcal_gpt.cpp create mode 100644 ref_app/src/mcal/xtensa_esp32_p4/mcal_gpt.h create mode 100644 ref_app/src/mcal/xtensa_esp32_p4/mcal_wdg.cpp create mode 100644 ref_app/src/mcal/xtensa_esp32_p4/mcal_wdg.h diff --git a/ref_app/ref_app.vcxproj b/ref_app/ref_app.vcxproj index 011c2df94..2e07d634a 100644 --- a/ref_app/ref_app.vcxproj +++ b/ref_app/ref_app.vcxproj @@ -1401,6 +1401,14 @@ true true + + true + true + + + true + true + true true @@ -3233,10 +3241,18 @@ true true + + true + true + true true + + true + true + true true diff --git a/ref_app/ref_app.vcxproj.filters b/ref_app/ref_app.vcxproj.filters index 03e4b9955..22537c80b 100644 --- a/ref_app/ref_app.vcxproj.filters +++ b/ref_app/ref_app.vcxproj.filters @@ -1372,6 +1372,12 @@ src\mcal\r7fa4m1ab + + src\mcal\xtensa_esp32_p4 + + + src\mcal\xtensa_esp32_p4 + @@ -3126,6 +3132,12 @@ src\mcal\xtensa_esp32_p4 + + src\mcal\xtensa_esp32_p4 + + + src\mcal\xtensa_esp32_p4 + diff --git a/ref_app/src/mcal/xtensa_esp32_p4/mcal_gpt.cpp b/ref_app/src/mcal/xtensa_esp32_p4/mcal_gpt.cpp new file mode 100644 index 000000000..bff017a1b --- /dev/null +++ b/ref_app/src/mcal/xtensa_esp32_p4/mcal_gpt.cpp @@ -0,0 +1,56 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright Christopher Kormanyos 2022 - 2026. +// Distributed under the Boost Software License, +// Version 1.0. (See accompanying file LICENSE_1_0.txt +// or copy at http://www.boost.org/LICENSE_1_0.txt) +// + +#include +#include + +#include + +#include + +#include +#include +#include +#include + +extern "C" +{ + uint32_t osGetActiveCore(void); +} + +namespace +{ + constexpr unsigned TIMEOUT_1S { 320000000u }; +} + +void mcal::gpt::init(const config_type*) +{ + // Set the MTIME timeout. + CLINT_MTIMECMP = (uint64_t) UINT64_C(0xFFFFFFFFFFFFFFFF); +} + +mcal::gpt::value_type mcal::gpt::secure::get_time_elapsed() +{ + const std::uint64_t tick_unscaled_01 = (uint64_t) CLINT_MTIME; + const std::uint64_t tick_unscaled_02 = (uint64_t) CLINT_MTIME; + + const std::uint64_t tick_unscaled = + (uint64_t) (((uint32_t) tick_unscaled_02 > (uint32_t) tick_unscaled_01) ? tick_unscaled_01 : (uint64_t) CLINT_MTIME); + + return (std::uint64_t) ((std::uint64_t) (tick_unscaled + 160U) / 320U); +} + +mcal::gpt::value_type mcal::gpt::secure::get_time_elapsed_core1() +{ + const std::uint64_t tick_unscaled_01 = (uint64_t) CLINT_MTIME; + const std::uint64_t tick_unscaled_02 = (uint64_t) CLINT_MTIME; + + const std::uint64_t tick_unscaled = + (uint64_t) (((uint32_t) tick_unscaled_02 > (uint32_t) tick_unscaled_01) ? tick_unscaled_01 : (uint64_t) CLINT_MTIME); + + return (std::uint64_t) ((std::uint64_t) (tick_unscaled + 160U) / 320U); +} diff --git a/ref_app/src/mcal/xtensa_esp32_p4/mcal_gpt.h b/ref_app/src/mcal/xtensa_esp32_p4/mcal_gpt.h new file mode 100644 index 000000000..95dc05177 --- /dev/null +++ b/ref_app/src/mcal/xtensa_esp32_p4/mcal_gpt.h @@ -0,0 +1,37 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright Christopher Kormanyos 2007 - 2025. +// Distributed under the Boost Software License, +// Version 1.0. (See accompanying file LICENSE_1_0.txt +// or copy at http://www.boost.org/LICENSE_1_0.txt) +// + +#ifndef MCAL_GPT_2022_12_16_H + #define MCAL_GPT_2022_12_16_H + + #include + + namespace mcal + { + namespace gpt + { + using config_type = void; + using value_type = std::uint64_t; + + auto init(const config_type*) -> void; + + struct secure final + { + static auto get_time_elapsed() -> value_type; + static auto get_time_elapsed_core1() -> value_type; + }; + + struct timer_core1_backend + { + using tick_type = std::uint64_t; + + static auto get_now() -> tick_type { return static_cast(mcal::gpt::secure::get_time_elapsed_core1()); } + }; + } + } + +#endif // MCAL_GPT_2022_12_16_H diff --git a/ref_app/src/mcal/xtensa_esp32_p4/mcal_reg.h b/ref_app/src/mcal/xtensa_esp32_p4/mcal_reg.h index f2075b04e..fcec144d1 100644 --- a/ref_app/src/mcal/xtensa_esp32_p4/mcal_reg.h +++ b/ref_app/src/mcal/xtensa_esp32_p4/mcal_reg.h @@ -14,7 +14,7 @@ { namespace reg { - constexpr std::uint32_t clint_base { UINT32_C(0x02000000) }; + constexpr std::uint32_t clint_base { UINT32_C(0x20000000) }; constexpr std::uint32_t clint_mtime { clint_base + static_cast(UINT32_C(0x0000BFF8)) }; constexpr std::uint32_t clint_mtimeh { clint_base + static_cast(UINT32_C(0x0000BFFC)) }; constexpr std::uint32_t clint_mtimecmp { clint_base + static_cast(UINT32_C(0x00004000)) }; diff --git a/ref_app/src/mcal/xtensa_esp32_p4/mcal_wdg.cpp b/ref_app/src/mcal/xtensa_esp32_p4/mcal_wdg.cpp new file mode 100644 index 000000000..d479c203e --- /dev/null +++ b/ref_app/src/mcal/xtensa_esp32_p4/mcal_wdg.cpp @@ -0,0 +1,17 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright Christopher Kormanyos 2007 - 2020. +// Distributed under the Boost Software License, +// Version 1.0. (See accompanying file LICENSE_1_0.txt +// or copy at http://www.boost.org/LICENSE_1_0.txt) +// + +#include +#include + +void mcal::wdg::init(const config_type*) +{ +} + +void mcal::wdg::secure::trigger() +{ +} diff --git a/ref_app/src/mcal/xtensa_esp32_p4/mcal_wdg.h b/ref_app/src/mcal/xtensa_esp32_p4/mcal_wdg.h new file mode 100644 index 000000000..996659eea --- /dev/null +++ b/ref_app/src/mcal/xtensa_esp32_p4/mcal_wdg.h @@ -0,0 +1,26 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright Christopher Kormanyos 2007 - 2025. +// Distributed under the Boost Software License, +// Version 1.0. (See accompanying file LICENSE_1_0.txt +// or copy at http://www.boost.org/LICENSE_1_0.txt) +// + +#ifndef MCAL_WDG_2010_04_10_H + #define MCAL_WDG_2010_04_10_H + + namespace mcal + { + namespace wdg + { + using config_type = void; + + auto init(const config_type*) -> void; + + struct secure final + { + static auto trigger() -> void; + }; + } + } + +#endif // MCAL_WDG_2010_04_10_H diff --git a/ref_app/target/micros/xtensa_esp32_p4/make/xtensa_esp32_p4.ld b/ref_app/target/micros/xtensa_esp32_p4/make/xtensa_esp32_p4.ld index 8e6286084..df26f371d 100644 --- a/ref_app/target/micros/xtensa_esp32_p4/make/xtensa_esp32_p4.ld +++ b/ref_app/target/micros/xtensa_esp32_p4/make/xtensa_esp32_p4.ld @@ -54,18 +54,34 @@ SECTIONS .text : ALIGN(4) { PROVIDE(__CODE_BASE_ADDRESS = .); + . = ALIGN(4); *(.boot) + . = ALIGN(4); + *(.progmem*) + . = ALIGN(4); *(.text) + . = ALIGN(4); *(.text*) . = ALIGN(4); + *(.glue_7) + . = ALIGN(4); + *(.glue_7t) + . = ALIGN(4); + . = ALIGN(4); } > FLASH /* Read-only data (.rodata) */ .rodata : ALIGN(4) { PROVIDE(__RODATA_BASE_ADDRESS = .); + . = ALIGN(4); *(.rodata) + . = ALIGN(4); *(.rodata*) + . = ALIGN(4); + *(.srodata) + . = ALIGN(4); + *(.srodata*) } > FLASH /* Section for constructors */ @@ -114,6 +130,29 @@ SECTIONS PROVIDE(__CODE_END_ADDRESS = .); } > FLASH + .riscv.extab : + { + . = ALIGN(4); + *(.riscv.extab) + *(.gnu.linkonce.riscvextab.*) + . = ALIGN(4); + } > FLASH + + .exidx : + { + . = ALIGN(4); + PROVIDE(__exidx_start = .); + *(.riscv.exidx*) + . = ALIGN(4); + PROVIDE(__exidx_end = .); + } > FLASH + + .riscv.attributes : ALIGN(4) + { + *(.riscv.attributes) + . = ALIGN(4); + } > FLASH + /* The ROM-to-RAM initialized data sections */ .data : ALIGN(4) { @@ -130,6 +169,9 @@ SECTIONS . = ALIGN(4); } > RAM + PROVIDE(end = .); + PROVIDE(_fini = .); + /* stack definition */ .stack_core0 : { @@ -149,5 +191,4 @@ SECTIONS /* ROM APIs */ printf = 0x4fc00024; - } diff --git a/ref_app/target/micros/xtensa_esp32_p4/make/xtensa_esp32_p4_files.gmk b/ref_app/target/micros/xtensa_esp32_p4/make/xtensa_esp32_p4_files.gmk index d8463cb19..730a0b335 100644 --- a/ref_app/target/micros/xtensa_esp32_p4/make/xtensa_esp32_p4_files.gmk +++ b/ref_app/target/micros/xtensa_esp32_p4/make/xtensa_esp32_p4_files.gmk @@ -1,5 +1,5 @@ # -# Copyright Christopher Kormanyos 2025. +# Copyright Christopher Kormanyos 2025 - 2026. # Distributed under the Boost Software License, # Version 1.0. (See accompanying file LICENSE_1_0.txt # or copy at http://www.boost.org/LICENSE_1_0.txt) @@ -11,7 +11,9 @@ FILES_CPP := -FILES_TGT := $(PATH_TGT)/startup/Code/Appli/main \ +FILES_TGT := $(PATH_APP)/mcal/$(TGT)/mcal_gpt \ + $(PATH_APP)/mcal/$(TGT)/mcal_wdg \ + $(PATH_TGT)/startup/Code/Appli/main \ $(PATH_TGT)/startup/Code/Mcal/gpio \ $(PATH_TGT)/startup/Code/Startup/boot \ $(PATH_TGT)/startup/Code/Startup/intvect \ diff --git a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Appli/main.cpp b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Appli/main.cpp index ab0da8236..f66e53389 100644 --- a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Appli/main.cpp +++ b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Appli/main.cpp @@ -16,10 +16,13 @@ ******************************************************************************************/ #include -#include #include #include +#include + +#include + #include constexpr unsigned TIMEOUT_500MS { 160000000u }; @@ -28,14 +31,18 @@ constexpr unsigned TIMEOUT_1S { 320000000u }; extern "C" { uint32_t osGetActiveCore(void); - void __attribute__((interrupt)) Isr_TIMER_Interrupt(void); } +auto main_core0() -> void; +auto main_core1() -> void; + auto main(void) -> int __attribute__((used,noinline)); auto main(void) -> int { - if(0 == osGetActiveCore()) + const std::uint32_t core_id { osGetActiveCore() }; + + if(std::uint32_t { UINT8_C(0) } == core_id) { gpio_cfg_output(7); gpio_cfg_output(8); @@ -61,38 +68,60 @@ auto main(void) -> int gpio_cfg_output(21); } - // Set the timer interrupt as hardware vectored in the CLIC. - CLIC->interrupt[INT_TIMER_ID].clicintattr = 1; + // Go to the core-specific main subroutines. + if(std::uint32_t { UINT8_C(0) } == core_id) + { + mcal::gpt::init(nullptr); + + ::main_core0(); + } + else + { + mcal::gpt::init(nullptr); + + ::main_core1(); + } +} + +namespace local +{ + using timer_type = util::timer; - // Enable the timer machine interrupt in the CLIC. - CLIC->interrupt[INT_TIMER_ID].clicintie = 1; + using timer_core1_type = util::timer; +} // namespace local - // Configure the sampling mode of MTIME. - CLINT_MTIMECTL |= (3ul << 4); +auto main_core0() -> void +{ + gpio_toggle_output_level(54); - // Set the MTIME timeout. - CLINT_MTIMECMP = (uint64_t)(CLINT_MTIME + TIMEOUT_1S); + local::timer_type led_timer(local::timer_type::seconds(1U)); // Endless loop: Never return or break. while(1) { - asm volatile("nop"); + if(led_timer.timeout()) + { + gpio_toggle_output_level(54); + + led_timer.start_interval(local::timer_type::seconds(1U)); + } } } -extern "C" -void Isr_TIMER_Interrupt(void) +auto main_core1() -> void { - CLINT_MTIMECMP = (uint64_t)(CLINT_MTIME + TIMEOUT_1S); + gpio_toggle_output_level(19); - const std::uint32_t core_id { osGetActiveCore() }; + local::timer_core1_type led_timer(local::timer_type::seconds(1U)); - if(std::uint32_t { UINT8_C(0) } == core_id) - { - gpio_toggle_output_level(54); - } - else if(std::uint32_t { UINT8_C(1) } == core_id) + // Endless loop: Never return or break. + while(1) { - gpio_toggle_output_level(19); + if(led_timer.timeout()) + { + gpio_toggle_output_level(19); + + led_timer.start_interval(local::timer_type::seconds(1U)); + } } } diff --git a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Startup/intvect.c b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Startup/intvect.c index a28c2f9ef..077bc0493 100644 --- a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Startup/intvect.c +++ b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Startup/intvect.c @@ -27,7 +27,6 @@ static void UndefinedHandler(void); static void UndefinedHandler(void){ for(;;); } void Isr_SW_Interrupt (void) __attribute__((weak, alias("UndefinedHandler"))); -void Isr_TIMER_Interrupt (void) __attribute__((weak, alias("UndefinedHandler"))); void Isr_ExtInt00 (void) __attribute__((weak, alias("UndefinedHandler"))); void Isr_ExtInt01 (void) __attribute__((weak, alias("UndefinedHandler"))); void Isr_ExtInt02 (void) __attribute__((weak, alias("UndefinedHandler"))); @@ -75,7 +74,7 @@ const InterruptHandler __attribute__((aligned(64))) InterruptVectorTable[] = (InterruptHandler)&UndefinedHandler, /* IRQ 04 Reserved */ (InterruptHandler)&UndefinedHandler, /* IRQ 05 Reserved */ (InterruptHandler)&UndefinedHandler, /* IRQ 06 Reserved */ - (InterruptHandler)&Isr_TIMER_Interrupt, /* IRQ 07 M mode timer interrupt */ + (InterruptHandler)&UndefinedHandler, /* IRQ 07 M mode timer interrupt */ (InterruptHandler)&UndefinedHandler, /* IRQ 08 Reserved */ (InterruptHandler)&UndefinedHandler, /* IRQ 09 Reserved */ (InterruptHandler)&UndefinedHandler, /* IRQ 10 Reserved */ From e24409ce932b31d4d43e12d4425d984679f51594 Mon Sep 17 00:00:00 2001 From: ckormanyos Date: Thu, 12 Feb 2026 15:19:09 +0100 Subject: [PATCH 09/11] Further architectural adaptions --- ref_app/src/mcal/xtensa_esp32_p4/mcal_gpt.cpp | 20 +++---- ref_app/src/mcal/xtensa_esp32_p4/mcal_gpt.h | 7 --- .../startup/Code/Appli/main.cpp | 56 ++++++++++--------- 3 files changed, 39 insertions(+), 44 deletions(-) diff --git a/ref_app/src/mcal/xtensa_esp32_p4/mcal_gpt.cpp b/ref_app/src/mcal/xtensa_esp32_p4/mcal_gpt.cpp index bff017a1b..b79878402 100644 --- a/ref_app/src/mcal/xtensa_esp32_p4/mcal_gpt.cpp +++ b/ref_app/src/mcal/xtensa_esp32_p4/mcal_gpt.cpp @@ -8,14 +8,10 @@ #include #include -#include - #include -#include #include #include -#include extern "C" { @@ -24,33 +20,33 @@ extern "C" namespace { - constexpr unsigned TIMEOUT_1S { 320000000u }; + constexpr std::uint32_t TIMEOUT_1S { UINT32_C(320000000) }; } void mcal::gpt::init(const config_type*) { // Set the MTIME timeout. - CLINT_MTIMECMP = (uint64_t) UINT64_C(0xFFFFFFFFFFFFFFFF); + CLINT_MTIMECMP = (std::numeric_limits::max)(); } mcal::gpt::value_type mcal::gpt::secure::get_time_elapsed() { - const std::uint64_t tick_unscaled_01 = (uint64_t) CLINT_MTIME; - const std::uint64_t tick_unscaled_02 = (uint64_t) CLINT_MTIME; + const std::uint64_t tick_unscaled_01 = (std::uint64_t) CLINT_MTIME; + const std::uint64_t tick_unscaled_02 = (std::uint64_t) CLINT_MTIME; const std::uint64_t tick_unscaled = - (uint64_t) (((uint32_t) tick_unscaled_02 > (uint32_t) tick_unscaled_01) ? tick_unscaled_01 : (uint64_t) CLINT_MTIME); + (std::uint64_t) (((std::uint32_t) tick_unscaled_02 > (std::uint32_t) tick_unscaled_01) ? tick_unscaled_01 : (std::uint64_t) CLINT_MTIME); return (std::uint64_t) ((std::uint64_t) (tick_unscaled + 160U) / 320U); } mcal::gpt::value_type mcal::gpt::secure::get_time_elapsed_core1() { - const std::uint64_t tick_unscaled_01 = (uint64_t) CLINT_MTIME; - const std::uint64_t tick_unscaled_02 = (uint64_t) CLINT_MTIME; + const std::uint64_t tick_unscaled_01 = (std::uint64_t) CLINT_MTIME; + const std::uint64_t tick_unscaled_02 = (std::uint64_t) CLINT_MTIME; const std::uint64_t tick_unscaled = - (uint64_t) (((uint32_t) tick_unscaled_02 > (uint32_t) tick_unscaled_01) ? tick_unscaled_01 : (uint64_t) CLINT_MTIME); + (std::uint64_t) (((std::uint32_t) tick_unscaled_02 > (std::uint32_t) tick_unscaled_01) ? tick_unscaled_01 : (std::uint64_t) CLINT_MTIME); return (std::uint64_t) ((std::uint64_t) (tick_unscaled + 160U) / 320U); } diff --git a/ref_app/src/mcal/xtensa_esp32_p4/mcal_gpt.h b/ref_app/src/mcal/xtensa_esp32_p4/mcal_gpt.h index 95dc05177..d368faf20 100644 --- a/ref_app/src/mcal/xtensa_esp32_p4/mcal_gpt.h +++ b/ref_app/src/mcal/xtensa_esp32_p4/mcal_gpt.h @@ -24,13 +24,6 @@ static auto get_time_elapsed() -> value_type; static auto get_time_elapsed_core1() -> value_type; }; - - struct timer_core1_backend - { - using tick_type = std::uint64_t; - - static auto get_now() -> tick_type { return static_cast(mcal::gpt::secure::get_time_elapsed_core1()); } - }; } } diff --git a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Appli/main.cpp b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Appli/main.cpp index f66e53389..5980608ec 100644 --- a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Appli/main.cpp +++ b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Appli/main.cpp @@ -15,19 +15,12 @@ ******************************************************************************************/ -#include -#include #include #include #include -#include - -constexpr unsigned TIMEOUT_500MS { 160000000u }; -constexpr unsigned TIMEOUT_1S { 320000000u }; - extern "C" { uint32_t osGetActiveCore(void); @@ -40,9 +33,9 @@ auto main(void) -> int __attribute__((used,noinline)); auto main(void) -> int { - const std::uint32_t core_id { osGetActiveCore() }; + const bool core_id_is_zero { (std::uint32_t { UINT8_C(0) } == osGetActiveCore()) }; - if(std::uint32_t { UINT8_C(0) } == core_id) + if(core_id_is_zero) { gpio_cfg_output(7); gpio_cfg_output(8); @@ -69,41 +62,52 @@ auto main(void) -> int } // Go to the core-specific main subroutines. - if(std::uint32_t { UINT8_C(0) } == core_id) + if(core_id_is_zero) { - mcal::gpt::init(nullptr); - ::main_core0(); } else { - mcal::gpt::init(nullptr); - ::main_core1(); } } namespace local { + struct timer_core1_backend + { + using tick_type = std::uint64_t; + + static auto get_now() -> tick_type { return static_cast(mcal::gpt::secure::get_time_elapsed_core1()); } + }; + using timer_type = util::timer; - using timer_core1_type = util::timer; + constexpr typename timer_type::tick_type + led_timeout + { + static_cast(timer_type::seconds(UINT8_C(1))) + }; + + using timer_core1_type = util::timer; } // namespace local auto main_core0() -> void { gpio_toggle_output_level(54); - local::timer_type led_timer(local::timer_type::seconds(1U)); + mcal::gpt::init(nullptr); - // Endless loop: Never return or break. - while(1) + local::timer_type local_led_timer(local::led_timeout); + + // Endless LED tollge-loop: Never return or break. + for(;;) { - if(led_timer.timeout()) + if(local_led_timer.timeout()) { gpio_toggle_output_level(54); - led_timer.start_interval(local::timer_type::seconds(1U)); + local_led_timer.start_interval(local::led_timeout); } } } @@ -112,16 +116,18 @@ auto main_core1() -> void { gpio_toggle_output_level(19); - local::timer_core1_type led_timer(local::timer_type::seconds(1U)); + mcal::gpt::init(nullptr); + + local::timer_core1_type local_led_timer(local::led_timeout); - // Endless loop: Never return or break. - while(1) + // Endless LED tollge-loop: Never return or break. + for(;;) { - if(led_timer.timeout()) + if(local_led_timer.timeout()) { gpio_toggle_output_level(19); - led_timer.start_interval(local::timer_type::seconds(1U)); + local_led_timer.start_interval(local::led_timeout); } } } From 3926b057bb9e8648192d6e95c3025773dc6b35a5 Mon Sep 17 00:00:00 2001 From: ckormanyos Date: Thu, 12 Feb 2026 20:24:14 +0100 Subject: [PATCH 10/11] Next architectural adaptions --- ref_app/ref_app.vcxproj | 76 +++++++++++++++++++ ref_app/ref_app.vcxproj.filters | 57 ++++++++++++++ .../src/mcal/xtensa_esp32_p4/mcal_benchmark.h | 24 ++++++ ref_app/src/mcal/xtensa_esp32_p4/mcal_cpu.cpp | 12 +++ ref_app/src/mcal/xtensa_esp32_p4/mcal_cpu.h | 25 ++++++ ref_app/src/mcal/xtensa_esp32_p4/mcal_eep.cpp | 21 +++++ ref_app/src/mcal/xtensa_esp32_p4/mcal_eep.h | 27 +++++++ ref_app/src/mcal/xtensa_esp32_p4/mcal_gpt.cpp | 76 ++++++++++++++----- ref_app/src/mcal/xtensa_esp32_p4/mcal_irq.cpp | 12 +++ ref_app/src/mcal/xtensa_esp32_p4/mcal_irq.h | 25 ++++++ ref_app/src/mcal/xtensa_esp32_p4/mcal_led.cpp | 59 ++++++++++++++ ref_app/src/mcal/xtensa_esp32_p4/mcal_led.h | 24 ++++++ .../xtensa_esp32_p4/mcal_memory_progmem.h | 72 ++++++++++++++++++ ref_app/src/mcal/xtensa_esp32_p4/mcal_osc.cpp | 12 +++ ref_app/src/mcal/xtensa_esp32_p4/mcal_osc.h | 21 +++++ .../src/mcal/xtensa_esp32_p4/mcal_port.cpp | 12 +++ ref_app/src/mcal/xtensa_esp32_p4/mcal_port.h | 69 +++++++++++++++++ ref_app/src/mcal/xtensa_esp32_p4/mcal_pwm.cpp | 12 +++ ref_app/src/mcal/xtensa_esp32_p4/mcal_pwm.h | 21 +++++ ref_app/src/mcal/xtensa_esp32_p4/mcal_ser.h | 21 +++++ ref_app/src/mcal/xtensa_esp32_p4/mcal_spi.cpp | 12 +++ ref_app/src/mcal/xtensa_esp32_p4/mcal_spi.h | 19 +++++ ref_app/target.vcxproj | 3 +- ref_app/target.vcxproj.filters | 5 +- .../make/xtensa_esp32_p4_files.gmk | 1 + .../xtensa_esp32_p4/startup/Code/Appli/main.c | 68 +++++++++++++++++ .../Code/Appli/{main.cpp => main_cores.cpp} | 51 ++----------- .../startup/Code/Startup/Startup.c | 6 +- .../startup/Code/Startup/boot.s | 3 +- 29 files changed, 775 insertions(+), 71 deletions(-) create mode 100644 ref_app/src/mcal/xtensa_esp32_p4/mcal_benchmark.h create mode 100644 ref_app/src/mcal/xtensa_esp32_p4/mcal_cpu.cpp create mode 100644 ref_app/src/mcal/xtensa_esp32_p4/mcal_cpu.h create mode 100644 ref_app/src/mcal/xtensa_esp32_p4/mcal_eep.cpp create mode 100644 ref_app/src/mcal/xtensa_esp32_p4/mcal_eep.h create mode 100644 ref_app/src/mcal/xtensa_esp32_p4/mcal_irq.cpp create mode 100644 ref_app/src/mcal/xtensa_esp32_p4/mcal_irq.h create mode 100644 ref_app/src/mcal/xtensa_esp32_p4/mcal_led.cpp create mode 100644 ref_app/src/mcal/xtensa_esp32_p4/mcal_led.h create mode 100644 ref_app/src/mcal/xtensa_esp32_p4/mcal_memory_progmem.h create mode 100644 ref_app/src/mcal/xtensa_esp32_p4/mcal_osc.cpp create mode 100644 ref_app/src/mcal/xtensa_esp32_p4/mcal_osc.h create mode 100644 ref_app/src/mcal/xtensa_esp32_p4/mcal_port.cpp create mode 100644 ref_app/src/mcal/xtensa_esp32_p4/mcal_port.h create mode 100644 ref_app/src/mcal/xtensa_esp32_p4/mcal_pwm.cpp create mode 100644 ref_app/src/mcal/xtensa_esp32_p4/mcal_pwm.h create mode 100644 ref_app/src/mcal/xtensa_esp32_p4/mcal_ser.h create mode 100644 ref_app/src/mcal/xtensa_esp32_p4/mcal_spi.cpp create mode 100644 ref_app/src/mcal/xtensa_esp32_p4/mcal_spi.h create mode 100644 ref_app/target/micros/xtensa_esp32_p4/startup/Code/Appli/main.c rename ref_app/target/micros/xtensa_esp32_p4/startup/Code/Appli/{main.cpp => main_cores.cpp} (66%) diff --git a/ref_app/ref_app.vcxproj b/ref_app/ref_app.vcxproj index 2e07d634a..9faabde92 100644 --- a/ref_app/ref_app.vcxproj +++ b/ref_app/ref_app.vcxproj @@ -1401,10 +1401,42 @@ true true + + true + true + + + true + true + true true + + true + true + + + true + true + + + true + true + + + true + true + + + true + true + + + true + true + true true @@ -3241,14 +3273,58 @@ true true + + true + true + + + true + true + + + true + true + true true + + true + true + + + true + true + + + true + true + + + true + true + + + true + true + + + true + true + true true + + true + true + + + true + true + true true diff --git a/ref_app/ref_app.vcxproj.filters b/ref_app/ref_app.vcxproj.filters index 22537c80b..3c8d1f3da 100644 --- a/ref_app/ref_app.vcxproj.filters +++ b/ref_app/ref_app.vcxproj.filters @@ -1378,6 +1378,30 @@ src\mcal\xtensa_esp32_p4 + + src\mcal\xtensa_esp32_p4 + + + src\mcal\xtensa_esp32_p4 + + + src\mcal\xtensa_esp32_p4 + + + src\mcal\xtensa_esp32_p4 + + + src\mcal\xtensa_esp32_p4 + + + src\mcal\xtensa_esp32_p4 + + + src\mcal\xtensa_esp32_p4 + + + src\mcal\xtensa_esp32_p4 + @@ -3138,6 +3162,39 @@ src\mcal\xtensa_esp32_p4 + + src\mcal\xtensa_esp32_p4 + + + src\mcal\xtensa_esp32_p4 + + + src\mcal\xtensa_esp32_p4 + + + src\mcal\xtensa_esp32_p4 + + + src\mcal\xtensa_esp32_p4 + + + src\mcal\xtensa_esp32_p4 + + + src\mcal\xtensa_esp32_p4 + + + src\mcal\xtensa_esp32_p4 + + + src\mcal\xtensa_esp32_p4 + + + src\mcal\xtensa_esp32_p4 + + + src\mcal\xtensa_esp32_p4 + diff --git a/ref_app/src/mcal/xtensa_esp32_p4/mcal_benchmark.h b/ref_app/src/mcal/xtensa_esp32_p4/mcal_benchmark.h new file mode 100644 index 000000000..790060f1a --- /dev/null +++ b/ref_app/src/mcal/xtensa_esp32_p4/mcal_benchmark.h @@ -0,0 +1,24 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright Christopher Kormanyos 2014 - 2026. +// Distributed under the Boost Software License, +// Version 1.0. (See accompanying file LICENSE_1_0.txt +// or copy at http://www.boost.org/LICENSE_1_0.txt) +// + +#ifndef MCAL_BENCHMARK_2014_04_16_H_ + #define MCAL_BENCHMARK_2014_04_16_H_ + + #include + #include + + #include + + namespace mcal + { + namespace benchmark + { + typedef mcal::port::port_pin benchmark_port_type; + } + } + +#endif // MCAL_BENCHMARK_2014_04_16_H_ diff --git a/ref_app/src/mcal/xtensa_esp32_p4/mcal_cpu.cpp b/ref_app/src/mcal/xtensa_esp32_p4/mcal_cpu.cpp new file mode 100644 index 000000000..ad5a9e94f --- /dev/null +++ b/ref_app/src/mcal/xtensa_esp32_p4/mcal_cpu.cpp @@ -0,0 +1,12 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright Christopher Kormanyos 2007 - 2026. +// Distributed under the Boost Software License, +// Version 1.0. (See accompanying file LICENSE_1_0.txt +// or copy at http://www.boost.org/LICENSE_1_0.txt) +// + +#include + +auto mcal::cpu::init() -> void +{ +} diff --git a/ref_app/src/mcal/xtensa_esp32_p4/mcal_cpu.h b/ref_app/src/mcal/xtensa_esp32_p4/mcal_cpu.h new file mode 100644 index 000000000..283f5418a --- /dev/null +++ b/ref_app/src/mcal/xtensa_esp32_p4/mcal_cpu.h @@ -0,0 +1,25 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright Christopher Kormanyos 2025 - 2026. +// Distributed under the Boost Software License, +// Version 1.0. (See accompanying file LICENSE_1_0.txt +// or copy at http://www.boost.org/LICENSE_1_0.txt) +// + +#ifndef MCAL_CPU_2025_07_30_H + #define MCAL_CPU_2025_07_30_H + + #include + + namespace mcal + { + namespace cpu + { + auto init() -> void; + + inline auto post_init() -> void { } + + inline auto nop() noexcept -> void { asm volatile("nop"); } + } + } + +#endif // MCAL_CPU_2025_07_30_H diff --git a/ref_app/src/mcal/xtensa_esp32_p4/mcal_eep.cpp b/ref_app/src/mcal/xtensa_esp32_p4/mcal_eep.cpp new file mode 100644 index 000000000..d3e733806 --- /dev/null +++ b/ref_app/src/mcal/xtensa_esp32_p4/mcal_eep.cpp @@ -0,0 +1,21 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright Christopher Kormanyos 2007 - 2026. +// Distributed under the Boost Software License, +// Version 1.0. (See accompanying file LICENSE_1_0.txt +// or copy at http://www.boost.org/LICENSE_1_0.txt) +// + +#include + +auto mcal::eep::write(const address_type addr, const std::uint8_t data) -> void +{ + static_cast(addr); + static_cast(data); +} + +auto mcal::eep::read(const address_type addr) -> std::uint8_t +{ + static_cast(addr); + + return UINT8_C(0); +} diff --git a/ref_app/src/mcal/xtensa_esp32_p4/mcal_eep.h b/ref_app/src/mcal/xtensa_esp32_p4/mcal_eep.h new file mode 100644 index 000000000..eec30e756 --- /dev/null +++ b/ref_app/src/mcal/xtensa_esp32_p4/mcal_eep.h @@ -0,0 +1,27 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright Christopher Kormanyos 2007 - 2026. +// Distributed under the Boost Software License, +// Version 1.0. (See accompanying file LICENSE_1_0.txt +// or copy at http://www.boost.org/LICENSE_1_0.txt) +// + +#ifndef MCAL_EEP_2018_12_15_H + #define MCAL_EEP_2018_12_15_H + + #include + + namespace mcal + { + namespace eep + { + using config_type = void; + using address_type = std::uint32_t; + + inline auto init(const config_type*) -> void { } + + auto write(const address_type addr, const std::uint8_t data) -> void; + auto read (const address_type addr) -> std::uint8_t; + } + } + +#endif // MCAL_EEP_2018_12_15_H diff --git a/ref_app/src/mcal/xtensa_esp32_p4/mcal_gpt.cpp b/ref_app/src/mcal/xtensa_esp32_p4/mcal_gpt.cpp index b79878402..5117e319e 100644 --- a/ref_app/src/mcal/xtensa_esp32_p4/mcal_gpt.cpp +++ b/ref_app/src/mcal/xtensa_esp32_p4/mcal_gpt.cpp @@ -8,45 +8,81 @@ #include #include -#include - -#include #include extern "C" { - uint32_t osGetActiveCore(void); + extern auto osGetActiveCore(void) -> std::uint32_t; } namespace { - constexpr std::uint32_t TIMEOUT_1S { UINT32_C(320000000) }; + auto gpt_is_initialized_core0() -> bool& __attribute__((used, noinline)); + auto gpt_is_initialized_core1() -> bool& __attribute__((used, noinline)); + + auto gpt_is_initialized_core0() -> bool& { static bool is_init { }; return is_init; } + auto gpt_is_initialized_core1() -> bool& { static bool is_init { }; return is_init; } } -void mcal::gpt::init(const config_type*) +auto mcal::gpt::init(const config_type*) -> void { - // Set the MTIME timeout. - CLINT_MTIMECMP = (std::numeric_limits::max)(); + const std::uint32_t core_id { ::osGetActiveCore() }; + + if(core_id == std::uint32_t { UINT8_C(0) }) + { + gpt_is_initialized_core0() = true; + } + else + { + gpt_is_initialized_core1() = true; + } + + // Set the MTIME timeout to essentially infinite. + mcal::reg::reg_access_static::max)()>::reg_set(); } -mcal::gpt::value_type mcal::gpt::secure::get_time_elapsed() +auto mcal::gpt::secure::get_time_elapsed() -> mcal::gpt::value_type { - const std::uint64_t tick_unscaled_01 = (std::uint64_t) CLINT_MTIME; - const std::uint64_t tick_unscaled_02 = (std::uint64_t) CLINT_MTIME; + std::uint64_t tick_unscaled { }; - const std::uint64_t tick_unscaled = - (std::uint64_t) (((std::uint32_t) tick_unscaled_02 > (std::uint32_t) tick_unscaled_01) ? tick_unscaled_01 : (std::uint64_t) CLINT_MTIME); + if(gpt_is_initialized_core0()) + { + const std::uint64_t tick_unscaled_01 { mcal::reg::reg_access_static::reg_get() }; + const std::uint64_t tick_unscaled_02 { mcal::reg::reg_access_static::reg_get() }; - return (std::uint64_t) ((std::uint64_t) (tick_unscaled + 160U) / 320U); + tick_unscaled = + static_cast + ( + (static_cast(tick_unscaled_02) > static_cast(tick_unscaled_01)) + ? tick_unscaled_01 + : mcal::reg::reg_access_static::reg_get() + ); + + tick_unscaled = static_cast(static_cast(tick_unscaled + 160U) / 320U); + } + + return static_cast(tick_unscaled); } -mcal::gpt::value_type mcal::gpt::secure::get_time_elapsed_core1() +auto mcal::gpt::secure::get_time_elapsed_core1() -> mcal::gpt::value_type { - const std::uint64_t tick_unscaled_01 = (std::uint64_t) CLINT_MTIME; - const std::uint64_t tick_unscaled_02 = (std::uint64_t) CLINT_MTIME; + std::uint64_t tick_unscaled { }; + + if(gpt_is_initialized_core1()) + { + const std::uint64_t tick_unscaled_01 { mcal::reg::reg_access_static::reg_get() }; + const std::uint64_t tick_unscaled_02 { mcal::reg::reg_access_static::reg_get() }; + + tick_unscaled = + static_cast + ( + (static_cast(tick_unscaled_02) > static_cast(tick_unscaled_01)) + ? tick_unscaled_01 + : mcal::reg::reg_access_static::reg_get() + ); - const std::uint64_t tick_unscaled = - (std::uint64_t) (((std::uint32_t) tick_unscaled_02 > (std::uint32_t) tick_unscaled_01) ? tick_unscaled_01 : (std::uint64_t) CLINT_MTIME); + tick_unscaled = static_cast(static_cast(tick_unscaled + 160U) / 320U); + } - return (std::uint64_t) ((std::uint64_t) (tick_unscaled + 160U) / 320U); + return static_cast(tick_unscaled); } diff --git a/ref_app/src/mcal/xtensa_esp32_p4/mcal_irq.cpp b/ref_app/src/mcal/xtensa_esp32_p4/mcal_irq.cpp new file mode 100644 index 000000000..31797b977 --- /dev/null +++ b/ref_app/src/mcal/xtensa_esp32_p4/mcal_irq.cpp @@ -0,0 +1,12 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright Christopher Kormanyos 2007 - 2026. +// Distributed under the Boost Software License, +// Version 1.0. (See accompanying file LICENSE_1_0.txt +// or copy at http://www.boost.org/LICENSE_1_0.txt) +// + +#include + +auto mcal::irq::init(const config_type*) -> void +{ +} diff --git a/ref_app/src/mcal/xtensa_esp32_p4/mcal_irq.h b/ref_app/src/mcal/xtensa_esp32_p4/mcal_irq.h new file mode 100644 index 000000000..d10feb0d8 --- /dev/null +++ b/ref_app/src/mcal/xtensa_esp32_p4/mcal_irq.h @@ -0,0 +1,25 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright Christopher Kormanyos 2007 - 2026. +// Distributed under the Boost Software License, +// Version 1.0. (See accompanying file LICENSE_1_0.txt +// or copy at http://www.boost.org/LICENSE_1_0.txt) +// + +#ifndef MCAL_IRQ_2010_04_10_H + #define MCAL_IRQ_2010_04_10_H + + namespace mcal + { + namespace irq + { + using config_type = void; + + void init(const config_type*); + + // Not yet implemented. + inline void enable_all() { } + inline void disable_all() { } + } + } + +#endif // MCAL_IRQ_2010_04_10_H diff --git a/ref_app/src/mcal/xtensa_esp32_p4/mcal_led.cpp b/ref_app/src/mcal/xtensa_esp32_p4/mcal_led.cpp new file mode 100644 index 000000000..c2c8d6ee3 --- /dev/null +++ b/ref_app/src/mcal/xtensa_esp32_p4/mcal_led.cpp @@ -0,0 +1,59 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright Christopher Kormanyos 2007 - 2026. +// Distributed under the Boost Software License, +// Version 1.0. (See accompanying file LICENSE_1_0.txt +// or copy at http://www.boost.org/LICENSE_1_0.txt) +// + +#include + +#include +#include +#include +#include + +namespace local +{ + class led_port54 : public mcal::led::led_boolean_state_base + { + public: + led_port54() noexcept + { + gpio_cfg_output(54); + } + + ~led_port54() override = default; + + auto toggle() noexcept -> void override + { + using base_class_type = led_boolean_state_base; + + gpio_toggle_output_level(54); + + base_class_type::toggle(); + } + }; + + class led_port19 : public mcal::led::led_boolean_state_base + { + public: + led_port19() noexcept + { + gpio_cfg_output(19); + } + + ~led_port19() override = default; + + auto toggle() noexcept -> void override + { + using base_class_type = led_boolean_state_base; + + gpio_toggle_output_level(19); + + base_class_type::toggle(); + } + }; +} // namespace local + +auto mcal::led::led0() -> mcal::led::led_base& { static local::led_port54 my_led { }; return my_led; } +auto mcal::led::led1() -> mcal::led::led_base& { static local::led_port19 my_led { }; return my_led; } diff --git a/ref_app/src/mcal/xtensa_esp32_p4/mcal_led.h b/ref_app/src/mcal/xtensa_esp32_p4/mcal_led.h new file mode 100644 index 000000000..d25db29c7 --- /dev/null +++ b/ref_app/src/mcal/xtensa_esp32_p4/mcal_led.h @@ -0,0 +1,24 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright Christopher Kormanyos 2007 - 2024. +// Distributed under the Boost Software License, +// Version 1.0. (See accompanying file LICENSE_1_0.txt +// or copy at http://www.boost.org/LICENSE_1_0.txt) +// + +#ifndef MCAL_LED_2010_09_14_H + #define MCAL_LED_2010_09_14_H + + #include + + #include + + namespace mcal + { + namespace led + { + auto led0() -> led_base&; + auto led1() -> led_base&; + } + } + +#endif // MCAL_LED_2010_09_14_H diff --git a/ref_app/src/mcal/xtensa_esp32_p4/mcal_memory_progmem.h b/ref_app/src/mcal/xtensa_esp32_p4/mcal_memory_progmem.h new file mode 100644 index 000000000..9668b68c4 --- /dev/null +++ b/ref_app/src/mcal/xtensa_esp32_p4/mcal_memory_progmem.h @@ -0,0 +1,72 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright Christopher Kormanyos 2019 - 2020. +// Distributed under the Boost Software License, +// Version 1.0. (See accompanying file LICENSE_1_0.txt +// or copy at http://www.boost.org/LICENSE_1_0.txt) +// + +#ifndef MCAL_MEMORY_PROGMEM_2019_08_17_H_ + #define MCAL_MEMORY_PROGMEM_2019_08_17_H_ + + #include + + #define MY_PROGMEM + + #if defined(__cplusplus) + extern "C" + { + #endif + + typedef uintptr_t mcal_progmem_uintptr_t; + typedef ptrdiff_t mcal_progmem_ptrdiff_t; + + #define MCAL_PROGMEM_ADDRESSOF(x) ((mcal_progmem_uintptr_t) (&(x))) + + static inline uint8_t mcal_memory_progmem_read_byte(const mcal_progmem_uintptr_t src_addr) + { + return *(const uint8_t*) src_addr; + } + + static inline uint16_t mcal_memory_progmem_read_word(const mcal_progmem_uintptr_t src_addr) + { + uint16_t dest; + + *(((uint8_t*) &dest) + 0U) = *((const uint8_t*) (src_addr + 0U)); + *(((uint8_t*) &dest) + 1U) = *((const uint8_t*) (src_addr + 1U)); + + return dest; + } + + static inline uint32_t mcal_memory_progmem_read_dword(const mcal_progmem_uintptr_t src_addr) + { + uint32_t dest; + + *(((uint8_t*) &dest) + 0U) = *((const uint8_t*) (src_addr + 0U)); + *(((uint8_t*) &dest) + 1U) = *((const uint8_t*) (src_addr + 1U)); + *(((uint8_t*) &dest) + 2U) = *((const uint8_t*) (src_addr + 2U)); + *(((uint8_t*) &dest) + 3U) = *((const uint8_t*) (src_addr + 3U)); + + return dest; + } + + static inline uint64_t mcal_memory_progmem_read_qword(const mcal_progmem_uintptr_t src_addr) + { + uint64_t dest; + + *(((uint8_t*) &dest) + 0U) = *((const uint8_t*) (src_addr + 0U)); + *(((uint8_t*) &dest) + 1U) = *((const uint8_t*) (src_addr + 1U)); + *(((uint8_t*) &dest) + 2U) = *((const uint8_t*) (src_addr + 2U)); + *(((uint8_t*) &dest) + 3U) = *((const uint8_t*) (src_addr + 3U)); + *(((uint8_t*) &dest) + 4U) = *((const uint8_t*) (src_addr + 4U)); + *(((uint8_t*) &dest) + 5U) = *((const uint8_t*) (src_addr + 5U)); + *(((uint8_t*) &dest) + 6U) = *((const uint8_t*) (src_addr + 6U)); + *(((uint8_t*) &dest) + 7U) = *((const uint8_t*) (src_addr + 7U)); + + return dest; + } + + #if defined(__cplusplus) + } + #endif + +#endif // MCAL_MEMORY_PROGMEM_2019_08_17_H_ diff --git a/ref_app/src/mcal/xtensa_esp32_p4/mcal_osc.cpp b/ref_app/src/mcal/xtensa_esp32_p4/mcal_osc.cpp new file mode 100644 index 000000000..65f51ae6a --- /dev/null +++ b/ref_app/src/mcal/xtensa_esp32_p4/mcal_osc.cpp @@ -0,0 +1,12 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright Christopher Kormanyos 2007 - 2024. +// Distributed under the Boost Software License, +// Version 1.0. (See accompanying file LICENSE_1_0.txt +// or copy at http://www.boost.org/LICENSE_1_0.txt) +// + +#include + +auto mcal::osc::init(const config_type*) -> void +{ +} diff --git a/ref_app/src/mcal/xtensa_esp32_p4/mcal_osc.h b/ref_app/src/mcal/xtensa_esp32_p4/mcal_osc.h new file mode 100644 index 000000000..cb8944d84 --- /dev/null +++ b/ref_app/src/mcal/xtensa_esp32_p4/mcal_osc.h @@ -0,0 +1,21 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright Christopher Kormanyos 2007 - 2025. +// Distributed under the Boost Software License, +// Version 1.0. (See accompanying file LICENSE_1_0.txt +// or copy at http://www.boost.org/LICENSE_1_0.txt) +// + +#ifndef MCAL_OSC_2011_10_20_H + #define MCAL_OSC_2011_10_20_H + + namespace mcal + { + namespace osc + { + using config_type = void; + + auto init(const config_type*) -> void; + } + } + +#endif // MCAL_OSC_2011_10_20_H diff --git a/ref_app/src/mcal/xtensa_esp32_p4/mcal_port.cpp b/ref_app/src/mcal/xtensa_esp32_p4/mcal_port.cpp new file mode 100644 index 000000000..85e46c9cb --- /dev/null +++ b/ref_app/src/mcal/xtensa_esp32_p4/mcal_port.cpp @@ -0,0 +1,12 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright Christopher Kormanyos 2007 - 2025. +// Distributed under the Boost Software License, +// Version 1.0. (See accompanying file LICENSE_1_0.txt +// or copy at http://www.boost.org/LICENSE_1_0.txt) +// + +#include + +void mcal::port::init(const config_type*) +{ +} diff --git a/ref_app/src/mcal/xtensa_esp32_p4/mcal_port.h b/ref_app/src/mcal/xtensa_esp32_p4/mcal_port.h new file mode 100644 index 000000000..fea773022 --- /dev/null +++ b/ref_app/src/mcal/xtensa_esp32_p4/mcal_port.h @@ -0,0 +1,69 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright Christopher Kormanyos 2007 - 2026. +// Distributed under the Boost Software License, +// Version 1.0. (See accompanying file LICENSE_1_0.txt +// or copy at http://www.boost.org/LICENSE_1_0.txt) +// + +#ifndef MCAL_PORT_2025_02_22_H + #define MCAL_PORT_2025_02_22_H + + #include + + #include + + namespace mcal + { + namespace port + { + typedef void config_type; + + void init(const config_type*); + + template + class port_pin + { + private: + static constexpr auto my_pfs_base() -> std::uint32_t { return PfsBase; } + + public: + static auto set_direction_output() -> void + { + // Configure the pin as output. + // Disable register write protection for PFS. + // PMISC->PWPR.bit.B0WI = 0; + // PMISC->PWPR.bit.PFSWE = 1; + // PFS->PxxxPFS.bit.PDR = 1; + + mcal::reg::reg_access_static::bit_clr(); + mcal::reg::reg_access_static::bit_set(); + mcal::reg::reg_access_static::bit_set(); + } + + static auto set_direction_input() -> void + { + } + + static auto set_pin_high() -> void + { + } + + static auto set_pin_low() -> void + { + } + + static auto read_input_value() -> bool + { + return false; + } + + static auto toggle_pin() -> void + { + // PFS->P111PFS.bit.PODR ^= 1; + mcal::reg::reg_access_static::bit_not(); + } + }; + } + } + +#endif // MCAL_PORT_2025_02_22_H diff --git a/ref_app/src/mcal/xtensa_esp32_p4/mcal_pwm.cpp b/ref_app/src/mcal/xtensa_esp32_p4/mcal_pwm.cpp new file mode 100644 index 000000000..cf0b192b5 --- /dev/null +++ b/ref_app/src/mcal/xtensa_esp32_p4/mcal_pwm.cpp @@ -0,0 +1,12 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright Christopher Kormanyos 2007 - 2025. +// Distributed under the Boost Software License, +// Version 1.0. (See accompanying file LICENSE_1_0.txt +// or copy at http://www.boost.org/LICENSE_1_0.txt) +// + +#include + +auto mcal::pwm::init(const config_type*) -> void +{ +} diff --git a/ref_app/src/mcal/xtensa_esp32_p4/mcal_pwm.h b/ref_app/src/mcal/xtensa_esp32_p4/mcal_pwm.h new file mode 100644 index 000000000..a0bcf067a --- /dev/null +++ b/ref_app/src/mcal/xtensa_esp32_p4/mcal_pwm.h @@ -0,0 +1,21 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright Christopher Kormanyos 2007 - 2020. +// Distributed under the Boost Software License, +// Version 1.0. (See accompanying file LICENSE_1_0.txt +// or copy at http://www.boost.org/LICENSE_1_0.txt) +// + +#ifndef MCAL_PWM_2010_09_14_H + #define MCAL_PWM_2010_09_14_H + + namespace mcal + { + namespace pwm + { + using config_type = void; + + void init(const config_type*); + } + } + +#endif // MCAL_PWM_2010_09_14_H diff --git a/ref_app/src/mcal/xtensa_esp32_p4/mcal_ser.h b/ref_app/src/mcal/xtensa_esp32_p4/mcal_ser.h new file mode 100644 index 000000000..7eb790916 --- /dev/null +++ b/ref_app/src/mcal/xtensa_esp32_p4/mcal_ser.h @@ -0,0 +1,21 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright Christopher Kormanyos 2007 - 2025. +// Distributed under the Boost Software License, +// Version 1.0. (See accompanying file LICENSE_1_0.txt +// or copy at http://www.boost.org/LICENSE_1_0.txt) +// + +#ifndef MCAL_SER_2011_10_20_H + #define MCAL_SER_2011_10_20_H + + namespace mcal + { + namespace ser + { + using config_type = void; + + inline void init(const config_type*) { } + } + } + +#endif // MCAL_SER_2011_10_20_H diff --git a/ref_app/src/mcal/xtensa_esp32_p4/mcal_spi.cpp b/ref_app/src/mcal/xtensa_esp32_p4/mcal_spi.cpp new file mode 100644 index 000000000..90723f45f --- /dev/null +++ b/ref_app/src/mcal/xtensa_esp32_p4/mcal_spi.cpp @@ -0,0 +1,12 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright Christopher Kormanyos 2012 - 2025. +// Distributed under the Boost Software License, +// Version 1.0. (See accompanying file LICENSE_1_0.txt +// or copy at http://www.boost.org/LICENSE_1_0.txt) +// + +#include + +void mcal::spi::init(const mcal::spi::config_type*) +{ +} diff --git a/ref_app/src/mcal/xtensa_esp32_p4/mcal_spi.h b/ref_app/src/mcal/xtensa_esp32_p4/mcal_spi.h new file mode 100644 index 000000000..26563e885 --- /dev/null +++ b/ref_app/src/mcal/xtensa_esp32_p4/mcal_spi.h @@ -0,0 +1,19 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright Christopher Kormanyos 2012 - 2025. +// Distributed under the Boost Software License, +// Version 1.0. (See accompanying file LICENSE_1_0.txt +// or copy at http://www.boost.org/LICENSE_1_0.txt) +// + +#ifndef MCAL_SPI_2012_05_24_H + #define MCAL_SPI_2012_05_24_H + + namespace mcal { namespace spi { + + using config_type = void; + + auto init(const config_type*) -> void; + + } } + +#endif // MCAL_SPI_2012_05_24_H diff --git a/ref_app/target.vcxproj b/ref_app/target.vcxproj index 219b3e6d3..1d92c075c 100644 --- a/ref_app/target.vcxproj +++ b/ref_app/target.vcxproj @@ -1283,7 +1283,8 @@ - + + diff --git a/ref_app/target.vcxproj.filters b/ref_app/target.vcxproj.filters index 4a36470f9..391fc26eb 100644 --- a/ref_app/target.vcxproj.filters +++ b/ref_app/target.vcxproj.filters @@ -1166,7 +1166,7 @@ micros\r7fa4m1ab\startup - + micros\xtensa_esp32_p4\startup\Code\Appli @@ -1178,6 +1178,9 @@ micros\xtensa_esp32_p4\startup\Code\Startup + + micros\xtensa_esp32_p4\startup\Code\Appli + diff --git a/ref_app/target/micros/xtensa_esp32_p4/make/xtensa_esp32_p4_files.gmk b/ref_app/target/micros/xtensa_esp32_p4/make/xtensa_esp32_p4_files.gmk index 730a0b335..0a85be386 100644 --- a/ref_app/target/micros/xtensa_esp32_p4/make/xtensa_esp32_p4_files.gmk +++ b/ref_app/target/micros/xtensa_esp32_p4/make/xtensa_esp32_p4_files.gmk @@ -14,6 +14,7 @@ FILES_CPP := FILES_TGT := $(PATH_APP)/mcal/$(TGT)/mcal_gpt \ $(PATH_APP)/mcal/$(TGT)/mcal_wdg \ $(PATH_TGT)/startup/Code/Appli/main \ + $(PATH_TGT)/startup/Code/Appli/main_cores \ $(PATH_TGT)/startup/Code/Mcal/gpio \ $(PATH_TGT)/startup/Code/Startup/boot \ $(PATH_TGT)/startup/Code/Startup/intvect \ diff --git a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Appli/main.c b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Appli/main.c new file mode 100644 index 000000000..3ff623e20 --- /dev/null +++ b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Appli/main.c @@ -0,0 +1,68 @@ +/****************************************************************************************** + Filename : main.c + + Core : RISC-V + + MCU : ESP32-P4 + + Author : Chalandi Amine + + Owner : Chalandi Amine + + Date : 25.01.2026 + + Description : Application main function + +******************************************************************************************/ + +#include + +#include + +extern uint32_t osGetActiveCore(void); + +extern void main_core0(void); +extern void main_core1(void); + +void main_x(void) __attribute__((used,noinline)); + +void main_x(void) +{ + const bool core_id_is_zero = ((uint32_t) UINT8_C(0) == osGetActiveCore()); + + if(core_id_is_zero) + { + gpio_cfg_output(7); + gpio_cfg_output(8); + gpio_cfg_output(24); + gpio_cfg_output(25); + gpio_cfg_output(46); + gpio_cfg_output(47); + gpio_cfg_output(48); + gpio_cfg_output(54); + gpio_cfg_output(20); + gpio_cfg_output(19); + gpio_cfg_output(18); + gpio_cfg_output(17); + gpio_cfg_output(16); + gpio_cfg_output(15); + gpio_cfg_output(14); + gpio_cfg_output(33); + gpio_cfg_output(32); + gpio_cfg_output(27); + gpio_cfg_output(26); + gpio_cfg_output(23); + gpio_cfg_output(32); + gpio_cfg_output(21); + } + + // Go to the core-specific main subroutines. + if(core_id_is_zero) + { + main_core0(); + } + else + { + main_core1(); + } +} diff --git a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Appli/main.cpp b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Appli/main_cores.cpp similarity index 66% rename from ref_app/target/micros/xtensa_esp32_p4/startup/Code/Appli/main.cpp rename to ref_app/target/micros/xtensa_esp32_p4/startup/Code/Appli/main_cores.cpp index 5980608ec..aac06b878 100644 --- a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Appli/main.cpp +++ b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Appli/main_cores.cpp @@ -23,55 +23,14 @@ extern "C" { - uint32_t osGetActiveCore(void); -} + extern auto osGetActiveCore(void) -> std::uint32_t; -auto main_core0() -> void; -auto main_core1() -> void; + auto main_core0() -> void; + auto main_core1() -> void; +} auto main(void) -> int __attribute__((used,noinline)); -auto main(void) -> int -{ - const bool core_id_is_zero { (std::uint32_t { UINT8_C(0) } == osGetActiveCore()) }; - - if(core_id_is_zero) - { - gpio_cfg_output(7); - gpio_cfg_output(8); - gpio_cfg_output(24); - gpio_cfg_output(25); - gpio_cfg_output(46); - gpio_cfg_output(47); - gpio_cfg_output(48); - gpio_cfg_output(54); - gpio_cfg_output(20); - gpio_cfg_output(19); - gpio_cfg_output(18); - gpio_cfg_output(17); - gpio_cfg_output(16); - gpio_cfg_output(15); - gpio_cfg_output(14); - gpio_cfg_output(33); - gpio_cfg_output(32); - gpio_cfg_output(27); - gpio_cfg_output(26); - gpio_cfg_output(23); - gpio_cfg_output(32); - gpio_cfg_output(21); - } - - // Go to the core-specific main subroutines. - if(core_id_is_zero) - { - ::main_core0(); - } - else - { - ::main_core1(); - } -} - namespace local { struct timer_core1_backend @@ -92,6 +51,7 @@ namespace local using timer_core1_type = util::timer; } // namespace local +extern "C" auto main_core0() -> void { gpio_toggle_output_level(54); @@ -112,6 +72,7 @@ auto main_core0() -> void } } +extern "C" auto main_core1() -> void { gpio_toggle_output_level(19); diff --git a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Startup/Startup.c b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Startup/Startup.c index 0fd67d085..45457473f 100644 --- a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Startup/Startup.c +++ b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Startup/Startup.c @@ -58,7 +58,7 @@ static void Startup_InitMcuSystem(void); //========================================================================================= // Extern function prototype //========================================================================================= -extern int main(void) __attribute__((used,noinline)); +extern int main_x(void) __attribute__((used,noinline)); //----------------------------------------------------------------------------------------- /// \brief Startup_Init function @@ -148,7 +148,7 @@ static void Startup_InitCtors(void) static void Startup_RunApplication(void) { /* check the weak function */ - if((unsigned int) &main != 0) + if((unsigned int) &main_x != 0) { #ifdef HP_CORES_SMP_MODE // note: RISC-V has no WFE/SEV instructions to synchronize SMP system @@ -161,7 +161,7 @@ static void Startup_RunApplication(void) #endif // Call the main function. - main(); + main_x(); } // Catch unexpected exit from main or if main does not exist. diff --git a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Startup/boot.s b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Startup/boot.s index 712babf48..e207f85ee 100644 --- a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Startup/boot.s +++ b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Startup/boot.s @@ -26,6 +26,7 @@ .type _start, @function .align 2 .globl _start +.extern main_x .set mtvt, 0x307 .set msip, 0x20000000 @@ -63,7 +64,7 @@ _start: li a0, 0 sw a0, 0(a5) la sp, __CORE1_STACK_TOP - jal main + jal main_x j . /******************************************************************************************* From 37d10a5d17222bc107e4cb290d473757fcfeeb6e Mon Sep 17 00:00:00 2001 From: ckormanyos Date: Thu, 12 Feb 2026 21:02:40 +0100 Subject: [PATCH 11/11] ref_app runs with second blinky on core1 --- readme.md | 1 + ref_app/src/mcal/xtensa_esp32_p4/mcal_port.h | 16 +- ref_app/target.vcxproj | 3 - ref_app/target.vcxproj.filters | 9 - .../make/xtensa_esp32_p4_files.gmk | 5 +- .../make/xtensa_esp32_p4_flags.gmk | 1 - .../xtensa_esp32_p4/startup/Code/Appli/main.c | 47 +- .../startup/Code/Appli/main_cores.cpp | 58 +- .../startup/Code/Mcal/esp32p4.h | 63864 ------- .../startup/Code/Mcal/esp32p4.svd | 133701 --------------- .../xtensa_esp32_p4/startup/Code/Mcal/gpio.c | 23 +- .../xtensa_esp32_p4/startup/Code/Mcal/gpio.h | 11 +- .../startup/Code/Mcal/interrupt.h | 96 - .../startup/Code/Mcal/riscv-csr.h | 3799 - .../startup/Code/Startup/Startup.c | 9 + .../startup/Code/Startup/boot.s | 11 + .../startup/Code/Startup/intvect.c | 9 + 17 files changed, 100 insertions(+), 201563 deletions(-) delete mode 100644 ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/esp32p4.h delete mode 100644 ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/esp32p4.svd delete mode 100644 ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/interrupt.h delete mode 100644 ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/riscv-csr.h diff --git a/readme.md b/readme.md index 043e56567..6473bda34 100644 --- a/readme.md +++ b/readme.md @@ -96,6 +96,7 @@ The reference application supports the following targets (in alpha-numeric order | `wch_ch32v307` | WCH CH32v307 RISC-V board | | | `wch_ch32v307_llvm` | WCH CH32v307 RISC-V board (but using an LLVM toolchain) | | | `x86_64-w64-mingw32` | PC on `Win*`/`mingw64` via GNU/GCC x86_x64 compiler | | +| `xtensa_esp32_p4` | Espressif (XTENSA) ESP32-P4 multicore RISC-V SoC | X | | `xtensa_esp32_s3` | Espressif (XTENSA) NodeMCU ESP32-S3 | X | | `xtensa32` | Espressif (XTENSA) NodeMCU ESP32 | X | diff --git a/ref_app/src/mcal/xtensa_esp32_p4/mcal_port.h b/ref_app/src/mcal/xtensa_esp32_p4/mcal_port.h index fea773022..923546a35 100644 --- a/ref_app/src/mcal/xtensa_esp32_p4/mcal_port.h +++ b/ref_app/src/mcal/xtensa_esp32_p4/mcal_port.h @@ -20,24 +20,12 @@ void init(const config_type*); - template + template class port_pin { - private: - static constexpr auto my_pfs_base() -> std::uint32_t { return PfsBase; } - public: static auto set_direction_output() -> void { - // Configure the pin as output. - // Disable register write protection for PFS. - // PMISC->PWPR.bit.B0WI = 0; - // PMISC->PWPR.bit.PFSWE = 1; - // PFS->PxxxPFS.bit.PDR = 1; - - mcal::reg::reg_access_static::bit_clr(); - mcal::reg::reg_access_static::bit_set(); - mcal::reg::reg_access_static::bit_set(); } static auto set_direction_input() -> void @@ -59,8 +47,6 @@ static auto toggle_pin() -> void { - // PFS->P111PFS.bit.PODR ^= 1; - mcal::reg::reg_access_static::bit_not(); } }; } diff --git a/ref_app/target.vcxproj b/ref_app/target.vcxproj index 1d92c075c..5e39c477e 100644 --- a/ref_app/target.vcxproj +++ b/ref_app/target.vcxproj @@ -1304,10 +1304,7 @@ - - - diff --git a/ref_app/target.vcxproj.filters b/ref_app/target.vcxproj.filters index 391fc26eb..6f2821d34 100644 --- a/ref_app/target.vcxproj.filters +++ b/ref_app/target.vcxproj.filters @@ -1200,18 +1200,9 @@ micros\am6254_soc\Code\Startup\Core\a53 - - micros\xtensa_esp32_p4\startup\Code\Mcal - micros\xtensa_esp32_p4\startup\Code\Mcal - - micros\xtensa_esp32_p4\startup\Code\Mcal - - - micros\xtensa_esp32_p4\startup\Code\Mcal - diff --git a/ref_app/target/micros/xtensa_esp32_p4/make/xtensa_esp32_p4_files.gmk b/ref_app/target/micros/xtensa_esp32_p4/make/xtensa_esp32_p4_files.gmk index 0a85be386..d32bfc510 100644 --- a/ref_app/target/micros/xtensa_esp32_p4/make/xtensa_esp32_p4_files.gmk +++ b/ref_app/target/micros/xtensa_esp32_p4/make/xtensa_esp32_p4_files.gmk @@ -9,10 +9,7 @@ # File list of the target-specific files in the project # ------------------------------------------------------------------------------ -FILES_CPP := - -FILES_TGT := $(PATH_APP)/mcal/$(TGT)/mcal_gpt \ - $(PATH_APP)/mcal/$(TGT)/mcal_wdg \ +FILES_TGT := $(PATH_APP)/mcal/mcal_gcc_cxx_completion \ $(PATH_TGT)/startup/Code/Appli/main \ $(PATH_TGT)/startup/Code/Appli/main_cores \ $(PATH_TGT)/startup/Code/Mcal/gpio \ diff --git a/ref_app/target/micros/xtensa_esp32_p4/make/xtensa_esp32_p4_flags.gmk b/ref_app/target/micros/xtensa_esp32_p4/make/xtensa_esp32_p4_flags.gmk index 005bcddad..3d828a72a 100644 --- a/ref_app/target/micros/xtensa_esp32_p4/make/xtensa_esp32_p4_flags.gmk +++ b/ref_app/target/micros/xtensa_esp32_p4/make/xtensa_esp32_p4_flags.gmk @@ -21,7 +21,6 @@ TGT_ALLFLAGS = -O2 -march=rv32imafc_zicsr_zifencei_xesppie \ -mabi=ilp32f \ -msmall-data-limit=0 \ - -ffreestanding \ -falign-functions=4 \ -fomit-frame-pointer \ -fno-reorder-blocks-and-partition \ diff --git a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Appli/main.c b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Appli/main.c index 3ff623e20..6c7036b84 100644 --- a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Appli/main.c +++ b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Appli/main.c @@ -1,3 +1,12 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright Christopher Kormanyos 2026. +// Distributed under the Boost Software License, +// Version 1.0. (See accompanying file LICENSE_1_0.txt +// or copy at http://www.boost.org/LICENSE_1_0.txt) +// + +// Originally from: + /****************************************************************************************** Filename : main.c @@ -15,9 +24,8 @@ ******************************************************************************************/ -#include - #include +#include extern uint32_t osGetActiveCore(void); @@ -30,32 +38,6 @@ void main_x(void) { const bool core_id_is_zero = ((uint32_t) UINT8_C(0) == osGetActiveCore()); - if(core_id_is_zero) - { - gpio_cfg_output(7); - gpio_cfg_output(8); - gpio_cfg_output(24); - gpio_cfg_output(25); - gpio_cfg_output(46); - gpio_cfg_output(47); - gpio_cfg_output(48); - gpio_cfg_output(54); - gpio_cfg_output(20); - gpio_cfg_output(19); - gpio_cfg_output(18); - gpio_cfg_output(17); - gpio_cfg_output(16); - gpio_cfg_output(15); - gpio_cfg_output(14); - gpio_cfg_output(33); - gpio_cfg_output(32); - gpio_cfg_output(27); - gpio_cfg_output(26); - gpio_cfg_output(23); - gpio_cfg_output(32); - gpio_cfg_output(21); - } - // Go to the core-specific main subroutines. if(core_id_is_zero) { @@ -66,3 +48,12 @@ void main_x(void) main_core1(); } } + +int main(void) __attribute__((used,noinline)); + +void main_caller(); + +void main_caller() +{ + (void) main(); +} diff --git a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Appli/main_cores.cpp b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Appli/main_cores.cpp index aac06b878..084834b1e 100644 --- a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Appli/main_cores.cpp +++ b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Appli/main_cores.cpp @@ -1,23 +1,15 @@ -/****************************************************************************************** - Filename : main.c - - Core : RISC-V - - MCU : ESP32-P4 - - Author : Chalandi Amine - - Owner : Chalandi Amine - - Date : 25.01.2026 - - Description : Application main function - -******************************************************************************************/ - -#include +/////////////////////////////////////////////////////////////////////////////// +// Copyright Christopher Kormanyos 2026. +// Distributed under the Boost Software License, +// Version 1.0. (See accompanying file LICENSE_1_0.txt +// or copy at http://www.boost.org/LICENSE_1_0.txt) +// #include +#include +#include +#include +#include #include @@ -27,6 +19,7 @@ extern "C" auto main_core0() -> void; auto main_core1() -> void; + auto main_caller() -> void; } auto main(void) -> int __attribute__((used,noinline)); @@ -54,39 +47,34 @@ namespace local extern "C" auto main_core0() -> void { - gpio_toggle_output_level(54); + mcal::wdg::init(nullptr); + mcal::osc::init(nullptr); - mcal::gpt::init(nullptr); - - local::timer_type local_led_timer(local::led_timeout); - - // Endless LED tollge-loop: Never return or break. - for(;;) - { - if(local_led_timer.timeout()) - { - gpio_toggle_output_level(54); + mcal::port::init(nullptr); - local_led_timer.start_interval(local::led_timeout); - } - } + ::main_caller(); } extern "C" auto main_core1() -> void { - gpio_toggle_output_level(19); + mcal::wdg::init(nullptr); + mcal::osc::init(nullptr); mcal::gpt::init(nullptr); local::timer_core1_type local_led_timer(local::led_timeout); - // Endless LED tollge-loop: Never return or break. + auto& my_led1_ref { mcal::led::led1() }; + + my_led1_ref.toggle(); + + // Endless LED1 togglee-loop: Never return or break. for(;;) { if(local_led_timer.timeout()) { - gpio_toggle_output_level(19); + my_led1_ref.toggle(); local_led_timer.start_interval(local::led_timeout); } diff --git a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/esp32p4.h b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/esp32p4.h deleted file mode 100644 index ea7077918..000000000 --- a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/esp32p4.h +++ /dev/null @@ -1,63864 +0,0 @@ - -#ifndef ESP32_P4_H -#define ESP32_P4_H - -#include -#include -#include - - -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -#if defined(__cplusplus) -extern "C" -{ -#endif - -/* =========================================================================================================================== */ -/* ================ Interrupt Number Definition ================ */ -/* =========================================================================================================================== */ - -typedef enum { -/* ======================================= RISC-V Specific Interrupt Numbers ======================================= */ -/* ========================================== ESP32_P4 Specific Interrupt Numbers ========================================== */ - LP_WDT_IRQn = 1, /*!< 1 LP_WDT */ - LP_TIMER0_IRQn = 2, /*!< 2 LP_TIMER0 */ - LP_TIMER1_IRQn = 3, /*!< 3 LP_TIMER1 */ - PMU0_IRQn = 6, /*!< 6 PMU0 */ - PMU1_IRQn = 7, /*!< 7 PMU1 */ - LP_ANA_IRQn = 8, /*!< 8 LP_ANA */ - LP_ADC_IRQn = 9, /*!< 9 LP_ADC */ - LP_GPIO_IRQn = 10, /*!< 10 LP_GPIO */ - LP_I2C0_IRQn = 11, /*!< 11 LP_I2C0 */ - LP_I2S0_IRQn = 12, /*!< 12 LP_I2S0 */ - LP_TOUCH_IRQn = 14, /*!< 14 LP_TOUCH */ - LP_TSENS_IRQn = 15, /*!< 15 LP_TSENS */ - LP_UART_IRQn = 16, /*!< 16 LP_UART */ - LP_SYS_IRQn = 19, /*!< 19 LP_SYS */ - LP_HUK_IRQn = 20, /*!< 20 LP_HUK */ - USB_DEVICE_IRQn = 22, /*!< 22 USB_DEVICE */ - DMA_IRQn = 24, /*!< 24 DMA */ - SPI2_IRQn = 25, /*!< 25 SPI2 */ - SPI3_IRQn = 26, /*!< 26 SPI3 */ - I2S0_IRQn = 27, /*!< 27 I2S0 */ - I2S1_IRQn = 28, /*!< 28 I2S1 */ - I2S2_IRQn = 29, /*!< 29 I2S2 */ - UHCI0_IRQn = 30, /*!< 30 UHCI0 */ - UART0_IRQn = 31, /*!< 31 UART0 */ - UART1_IRQn = 32, /*!< 32 UART1 */ - UART2_IRQn = 33, /*!< 33 UART2 */ - UART3_IRQn = 34, /*!< 34 UART3 */ - UART4_IRQn = 35, /*!< 35 UART4 */ - PWM0_IRQn = 38, /*!< 38 PWM0 */ - PWM1_IRQn = 39, /*!< 39 PWM1 */ - TWAI0_IRQn = 40, /*!< 40 TWAI0 */ - TWAI1_IRQn = 41, /*!< 41 TWAI1 */ - TWAI2_IRQn = 42, /*!< 42 TWAI2 */ - RMT_IRQn = 43, /*!< 43 RMT */ - I2C0_IRQn = 44, /*!< 44 I2C0 */ - I2C1_IRQn = 45, /*!< 45 I2C1 */ - TG0_T0_IRQn = 46, /*!< 46 TG0_T0 */ - TG0_T1_IRQn = 47, /*!< 47 TG0_T1 */ - TG0_WDT_IRQn = 48, /*!< 48 TG0_WDT */ - TG1_T0_IRQn = 49, /*!< 49 TG1_T0 */ - TG1_T1_IRQn = 50, /*!< 50 TG1_T1 */ - TG1_WDT_IRQn = 51, /*!< 51 TG1_WDT */ - LEDC_IRQn = 52, /*!< 52 LEDC */ - SYSTIMER_TARGET0_IRQn = 53, /*!< 53 SYSTIMER_TARGET0 */ - SYSTIMER_TARGET1_IRQn = 54, /*!< 54 SYSTIMER_TARGET1 */ - SYSTIMER_TARGET2_IRQn = 55, /*!< 55 SYSTIMER_TARGET2 */ - AHB_PDMA_IN_CH0_IRQn = 56, /*!< 56 AHB_PDMA_IN_CH0 */ - AHB_PDMA_IN_CH1_IRQn = 57, /*!< 57 AHB_PDMA_IN_CH1 */ - AHB_PDMA_IN_CH2_IRQn = 58, /*!< 58 AHB_PDMA_IN_CH2 */ - AHB_PDMA_OUT_CH0_IRQn = 59, /*!< 59 AHB_PDMA_OUT_CH0 */ - AHB_PDMA_OUT_CH1_IRQn = 60, /*!< 60 AHB_PDMA_OUT_CH1 */ - AHB_PDMA_OUT_CH2_IRQn = 61, /*!< 61 AHB_PDMA_OUT_CH2 */ - AXI_PDMA_IN_CH0_IRQn = 62, /*!< 62 AXI_PDMA_IN_CH0 */ - AXI_PDMA_IN_CH1_IRQn = 63, /*!< 63 AXI_PDMA_IN_CH1 */ - AXI_PDMA_IN_CH2_IRQn = 64, /*!< 64 AXI_PDMA_IN_CH2 */ - AXI_PDMA_OUT_CH0_IRQn = 65, /*!< 65 AXI_PDMA_OUT_CH0 */ - AXI_PDMA_OUT_CH1_IRQn = 66, /*!< 66 AXI_PDMA_OUT_CH1 */ - AXI_PDMA_OUT_CH2_IRQn = 67, /*!< 67 AXI_PDMA_OUT_CH2 */ - RSA_IRQn = 68, /*!< 68 RSA */ - AES_IRQn = 69, /*!< 69 AES */ - SHA_IRQn = 70, /*!< 70 SHA */ - ECC_IRQn = 71, /*!< 71 ECC */ - GPIO_INT0_IRQn = 74, /*!< 74 GPIO_INT0 */ - GPIO_INT1_IRQn = 75, /*!< 75 GPIO_INT1 */ - GPIO_INT2_IRQn = 76, /*!< 76 GPIO_INT2 */ - GPIO_INT3_IRQn = 77, /*!< 77 GPIO_INT3 */ - GPIO_PAD_COMP_IRQn = 78, /*!< 78 GPIO_PAD_COMP */ - CACHE_IRQn = 83, /*!< 83 CACHE */ - CSI_BRIDGE_IRQn = 85, /*!< 85 CSI_BRIDGE */ - DSI_BRIDGE_IRQn = 86, /*!< 86 DSI_BRIDGE */ - CSI_IRQn = 87, /*!< 87 CSI */ - DSI_IRQn = 88, /*!< 88 DSI */ - JPEG_IRQn = 95, /*!< 95 JPEG */ - PPA_IRQn = 96, /*!< 96 PPA */ - ISP_IRQn = 100, /*!< 100 ISP */ - I3C_IRQn = 101, /*!< 101 I3C */ - I3C_SLV_IRQn = 102, /*!< 102 I3C_SLV */ - HP_SYS_IRQn = 110, /*!< 110 HP_SYS */ - PCNT_IRQn = 111, /*!< 111 PCNT */ - PAU_IRQn = 112, /*!< 112 PAU */ - PARLIO_RX_IRQn = 113, /*!< 113 PARLIO_RX */ - PARLIO_TX_IRQn = 114, /*!< 114 PARLIO_TX */ - H264_DMA2D_OUT_CH0_IRQn = 115, /*!< 115 H264_DMA2D_OUT_CH0 */ - H264_DMA2D_OUT_CH1_IRQn = 116, /*!< 116 H264_DMA2D_OUT_CH1 */ - H264_DMA2D_OUT_CH2_IRQn = 117, /*!< 117 H264_DMA2D_OUT_CH2 */ - H264_DMA2D_OUT_CH3_IRQn = 118, /*!< 118 H264_DMA2D_OUT_CH3 */ - H264_DMA2D_OUT_CH4_IRQn = 119, /*!< 119 H264_DMA2D_OUT_CH4 */ - H264_DMA2D_IN_CH0_IRQn = 120, /*!< 120 H264_DMA2D_IN_CH0 */ - H264_DMA2D_IN_CH1_IRQn = 121, /*!< 121 H264_DMA2D_IN_CH1 */ - H264_DMA2D_IN_CH2_IRQn = 122, /*!< 122 H264_DMA2D_IN_CH2 */ - H264_DMA2D_IN_CH3_IRQn = 123, /*!< 123 H264_DMA2D_IN_CH3 */ - H264_DMA2D_IN_CH4_IRQn = 124, /*!< 124 H264_DMA2D_IN_CH4 */ - H264_DMA2D_IN_CH5_IRQn = 125, /*!< 125 H264_DMA2D_IN_CH5 */ - H264_REG_IRQn = 126, /*!< 126 H264_REG */ - ASSIST_DEBUG_IRQn = 127 /*!< 127 ASSIST_DEBUG */ -} IRQn_Type; - - -/* =========================================================================================================================== */ -/* ================ Device Specific Peripheral Section ================ */ -/* =========================================================================================================================== */ - - -/** @addtogroup Device_Peripheral_peripherals - * @{ - */ - - - -/* =========================================================================================================================== */ -/* ================ ADC ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief ADC (Analog to Digital Converter) (ADC) - */ - -typedef struct { /*!< ADC Structure */ - - union { - __IOM uint32_t reg; /*!< Register */ - - struct { - __IOM uint32_t START_FORCE : 1; /*!< need_des */ - __IOM uint32_t START : 1; /*!< need_des */ - __IOM uint32_t WORK_MODE : 2; /*!< 0: single mode, 1: double mode, 2: alternate mode */ - __IOM uint32_t SAR_SEL : 1; /*!< 0: SAR1, 1: SAR2, only work for single SAR mode */ - __IOM uint32_t SAR_CLK_GATED : 1; /*!< need_des */ - __IOM uint32_t SAR_CLK_DIV : 8; /*!< SAR clock divider */ - __IOM uint32_t SAR1_PATT_LEN : 4; /*!< 0 ~ 15 means length 1 ~ 16 */ - __IOM uint32_t SAR2_PATT_LEN : 4; /*!< 0 ~ 15 means length 1 ~ 16 */ - __IOM uint32_t SAR1_PATT_P_CLEAR : 1; /*!< clear the pointer of pattern table for DIG ADC1 CTRL */ - __IOM uint32_t SAR2_PATT_P_CLEAR : 1; /*!< clear the pointer of pattern table for DIG ADC2 CTRL */ - __IOM uint32_t DATA_SAR_SEL : 1; /*!< 1: sar_sel will be coded by the MSB of the 16-bit output data, - in this case the resolution should not be larger than 11 - bits. */ - __IOM uint32_t DATA_TO_I2S : 1; /*!< 1: I2S input data is from SAR ADC (for DMA), 0: I2S input data - is from GPIO matrix */ - __IOM uint32_t XPD_SAR1_FORCE : 2; /*!< force option to xpd sar1 blocks */ - __IOM uint32_t XPD_SAR2_FORCE : 2; /*!< force option to xpd sar2 blocks */ - __IOM uint32_t WAIT_ARB_CYCLE : 2; /*!< wait arbit signal stable after sar_done */ - } bit; - } CTRL; - - union { - __IOM uint32_t reg; /*!< Register */ - - struct { - __IOM uint32_t MEAS_NUM_LIMIT : 1; /*!< need_des */ - __IOM uint32_t MAX_MEAS_NUM : 8; /*!< max conversion number */ - __IOM uint32_t SAR1_INV : 1; /*!< 1: data to DIG ADC1 CTRL is inverted, otherwise not */ - __IOM uint32_t SAR2_INV : 1; /*!< 1: data to DIG ADC2 CTRL is inverted, otherwise not */ - __IOM uint32_t TIMER_SEL : 1; /*!< 1: select saradc timer 0: i2s_ws trigger */ - __IOM uint32_t TIMER_TARGET : 12; /*!< to set saradc timer target */ - __IOM uint32_t TIMER_EN : 1; /*!< to enable saradc timer trigger */ - uint32_t : 7; - } bit; - } CTRL2; - - union { - __IOM uint32_t reg; /*!< Register */ - - struct { - uint32_t : 26; - __IOM uint32_t FILTER_FACTOR1 : 3; /*!< need_des */ - __IOM uint32_t FILTER_FACTOR0 : 3; /*!< need_des */ - } bit; - } FILTER_CTRL1; - - union { - __IOM uint32_t reg; /*!< Register */ - - struct { - __IOM uint32_t XPD_WAIT : 8; /*!< need_des */ - __IOM uint32_t RSTB_WAIT : 8; /*!< need_des */ - __IOM uint32_t STANDBY_WAIT : 8; /*!< need_des */ - uint32_t : 8; - } bit; - } FSM_WAIT; - - union { - __IOM uint32_t reg; /*!< Register */ - - struct { - __IM uint32_t SAR1_STATUS : 32; /*!< SAR1_STATUS */ - } bit; - } SAR1_STATUS; - - union { - __IOM uint32_t reg; /*!< Register */ - - struct { - __IM uint32_t SAR2_STATUS : 32; /*!< SAR2_STATUS */ - } bit; - } SAR2_STATUS; - - union { - __IOM uint32_t reg; /*!< Register */ - - struct { - __IOM uint32_t SAR1_PATT_TAB1 : 24; /*!< item 0 ~ 3 for pattern table 1 (each item one byte) */ - uint32_t : 8; - } bit; - } SAR1_PATT_TAB1; - - union { - __IOM uint32_t reg; /*!< Register */ - - struct { - __IOM uint32_t SAR1_PATT_TAB2 : 24; /*!< Item 4 ~ 7 for pattern table 1 (each item one byte) */ - uint32_t : 8; - } bit; - } SAR1_PATT_TAB2; - - union { - __IOM uint32_t reg; /*!< Register */ - - struct { - __IOM uint32_t SAR1_PATT_TAB3 : 24; /*!< Item 8 ~ 11 for pattern table 1 (each item one byte) */ - uint32_t : 8; - } bit; - } SAR1_PATT_TAB3; - - union { - __IOM uint32_t reg; /*!< Register */ - - struct { - __IOM uint32_t SAR1_PATT_TAB4 : 24; /*!< Item 12 ~ 15 for pattern table 1 (each item one byte) */ - uint32_t : 8; - } bit; - } SAR1_PATT_TAB4; - - union { - __IOM uint32_t reg; /*!< Register */ - - struct { - __IOM uint32_t SAR2_PATT_TAB1 : 24; /*!< item 0 ~ 3 for pattern table 2 (each item one byte) */ - uint32_t : 8; - } bit; - } SAR2_PATT_TAB1; - - union { - __IOM uint32_t reg; /*!< Register */ - - struct { - __IOM uint32_t SAR2_PATT_TAB2 : 24; /*!< Item 4 ~ 7 for pattern table 2 (each item one byte) */ - uint32_t : 8; - } bit; - } SAR2_PATT_TAB2; - - union { - __IOM uint32_t reg; /*!< Register */ - - struct { - __IOM uint32_t SAR2_PATT_TAB3 : 24; /*!< Item 8 ~ 11 for pattern table 2 (each item one byte) */ - uint32_t : 8; - } bit; - } SAR2_PATT_TAB3; - - union { - __IOM uint32_t reg; /*!< Register */ - - struct { - __IOM uint32_t SAR2_PATT_TAB4 : 24; /*!< Item 12 ~ 15 for pattern table 2 (each item one byte) */ - uint32_t : 8; - } bit; - } SAR2_PATT_TAB4; - - union { - __IOM uint32_t reg; /*!< Register */ - - struct { - uint32_t : 2; - __IOM uint32_t ARB_APB_FORCE : 1; /*!< adc2 arbiter force to enableapb controller */ - __IOM uint32_t ARB_RTC_FORCE : 1; /*!< adc2 arbiter force to enable rtc controller */ - __IOM uint32_t ARB_WIFI_FORCE : 1; /*!< adc2 arbiter force to enable wifi controller */ - __IOM uint32_t ARB_GRANT_FORCE : 1; /*!< adc2 arbiter force grant */ - __IOM uint32_t ARB_APB_PRIORITY : 2; /*!< Set adc2 arbiterapb priority */ - __IOM uint32_t ARB_RTC_PRIORITY : 2; /*!< Set adc2 arbiter rtc priority */ - __IOM uint32_t ARB_WIFI_PRIORITY : 2; /*!< Set adc2 arbiter wifi priority */ - __IOM uint32_t ARB_FIX_PRIORITY : 1; /*!< adc2 arbiter uses fixed priority */ - uint32_t : 19; - } bit; - } ARB_CTRL; - - union { - __IOM uint32_t reg; /*!< Register */ - - struct { - uint32_t : 14; - __IOM uint32_t FILTER_CHANNEL1 : 5; /*!< need_des */ - __IOM uint32_t FILTER_CHANNEL0 : 5; /*!< apb_adc1_filter_factor */ - uint32_t : 7; - __IOM uint32_t FILTER_RESET : 1; /*!< enable apb_adc1_filter */ - } bit; - } FILTER_CTRL0; - - union { - __IOM uint32_t reg; /*!< Register */ - - struct { - __IM uint32_t APB_SARADC1_DATA : 17; /*!< need_des */ - uint32_t : 15; - } bit; - } SAR1_DATA_STATUS; - - union { - __IOM uint32_t reg; /*!< Register */ - - struct { - __IOM uint32_t THRES0_CHANNEL : 5; /*!< need_des */ - __IOM uint32_t THRES0_HIGH : 13; /*!< saradc1's thres0 monitor thres */ - __IOM uint32_t THRES0_LOW : 13; /*!< saradc1's thres0 monitor thres */ - uint32_t : 1; - } bit; - } THRES0_CTRL; - - union { - __IOM uint32_t reg; /*!< Register */ - - struct { - __IOM uint32_t THRES1_CHANNEL : 5; /*!< need_des */ - __IOM uint32_t THRES1_HIGH : 13; /*!< saradc1's thres0 monitor thres */ - __IOM uint32_t THRES1_LOW : 13; /*!< saradc1's thres0 monitor thres */ - uint32_t : 1; - } bit; - } THRES1_CTRL; - - union { - __IOM uint32_t reg; /*!< Register */ - - struct { - uint32_t : 27; - __IOM uint32_t THRES_ALL_EN : 1; /*!< need_des */ - __IOM uint32_t THRES3_EN : 1; /*!< need_des */ - __IOM uint32_t THRES2_EN : 1; /*!< need_des */ - __IOM uint32_t THRES1_EN : 1; /*!< need_des */ - __IOM uint32_t THRES0_EN : 1; /*!< need_des */ - } bit; - } THRES_CTRL; - - union { - __IOM uint32_t reg; /*!< Register */ - - struct { - uint32_t : 26; - __IOM uint32_t THRES1_LOW_INT_ENA : 1; /*!< need_des */ - __IOM uint32_t THRES0_LOW_INT_ENA : 1; /*!< need_des */ - __IOM uint32_t THRES1_HIGH_INT_ENA : 1; /*!< need_des */ - __IOM uint32_t THRES0_HIGH_INT_ENA : 1; /*!< need_des */ - __IOM uint32_t SAR2_DONE_INT_ENA : 1; /*!< need_des */ - __IOM uint32_t SAR1_DONE_INT_ENA : 1; /*!< need_des */ - } bit; - } INT_ENA; - - union { - __IOM uint32_t reg; /*!< Register */ - - struct { - uint32_t : 26; - __IOM uint32_t THRES1_LOW_INT_RAW : 1; /*!< need_des */ - __IOM uint32_t THRES0_LOW_INT_RAW : 1; /*!< need_des */ - __IOM uint32_t THRES1_HIGH_INT_RAW : 1; /*!< need_des */ - __IOM uint32_t THRES0_HIGH_INT_RAW : 1; /*!< need_des */ - __IOM uint32_t SAR2_DONE_INT_RAW : 1; /*!< need_des */ - __IOM uint32_t SAR1_DONE_INT_RAW : 1; /*!< need_des */ - } bit; - } INT_RAW; - - union { - __IOM uint32_t reg; /*!< Register */ - - struct { - uint32_t : 26; - __IM uint32_t THRES1_LOW_INT_ST : 1; /*!< need_des */ - __IM uint32_t THRES0_LOW_INT_ST : 1; /*!< need_des */ - __IM uint32_t THRES1_HIGH_INT_ST : 1; /*!< need_des */ - __IM uint32_t THRES0_HIGH_INT_ST : 1; /*!< need_des */ - __IM uint32_t APB_SARADC2_DONE_INT_ST : 1;/*!< need_des */ - __IM uint32_t APB_SARADC1_DONE_INT_ST : 1;/*!< need_des */ - } bit; - } INT_ST; - - union { - __IOM uint32_t reg; /*!< Register */ - - struct { - uint32_t : 26; - __OM uint32_t THRES1_LOW_INT_CLR : 1; /*!< need_des */ - __OM uint32_t THRES0_LOW_INT_CLR : 1; /*!< need_des */ - __OM uint32_t THRES1_HIGH_INT_CLR : 1; /*!< need_des */ - __OM uint32_t THRES0_HIGH_INT_CLR : 1; /*!< need_des */ - __OM uint32_t APB_SARADC2_DONE_INT_CLR : 1;/*!< need_des */ - __OM uint32_t APB_SARADC1_DONE_INT_CLR : 1;/*!< need_des */ - } bit; - } INT_CLR; - - union { - __IOM uint32_t reg; /*!< Register */ - - struct { - __IOM uint32_t APB_ADC_EOF_NUM : 16; /*!< the dma_in_suc_eof gen when sample cnt = spi_eof_num */ - uint32_t : 14; - __IOM uint32_t APB_ADC_RESET_FSM : 1; /*!< reset_apb_adc_state */ - __IOM uint32_t APB_ADC_TRANS : 1; /*!< enable apb_adc use spi_dma */ - } bit; - } DMA_CONF; - - union { - __IOM uint32_t reg; /*!< Register */ - - struct { - __IM uint32_t APB_SARADC2_DATA : 17; /*!< need_des */ - uint32_t : 15; - } bit; - } SAR2_DATA_STATUS; - - union { - __IOM uint32_t reg; /*!< Register */ - - struct { - __IOM uint32_t CFG : 17; /*!< need_des */ - uint32_t : 15; - } bit; - } CALI; - - union { - __IOM uint32_t reg; /*!< Register */ - - struct { - __IOM uint32_t RND_ECO_LOW : 32; /*!< rnd eco low */ - } bit; - } RND_ECO_LOW; - - union { - __IOM uint32_t reg; /*!< Register */ - - struct { - __IOM uint32_t RND_ECO_HIGH : 32; /*!< rnd eco high */ - } bit; - } RND_ECO_HIGH; - - union { - __IOM uint32_t reg; /*!< Register */ - - struct { - __IOM uint32_t RND_ECO_EN : 1; /*!< need_des */ - __IM uint32_t RND_ECO_RESULT : 1; /*!< need_des */ - uint32_t : 30; - } bit; - } RND_ECO_CS; - __IM uint32_t RESERVED[225]; - - union { - __IOM uint32_t reg; /*!< Register */ - - struct { - __IOM uint32_t CTRL_DATE : 31; /*!< need_des */ - __IOM uint32_t CLK_EN : 1; /*!< need_des */ - } bit; - } CTRL_DATE; -} ADC_Type; /*!< Size = 1024 (0x400) */ - - - -/* =========================================================================================================================== */ -/* ================ AES ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief AES (Advanced Encryption Standard) Accelerator (AES) - */ - -typedef struct { /*!< AES Structure */ - - union { - __IOM uint32_t reg; /*!< Key material key_0 configure register */ - - struct { - __IOM uint32_t KEY_0 : 32; /*!< This bits stores key_0 that is a part of key material. */ - } bit; - } KEY_0; - - union { - __IOM uint32_t reg; /*!< Key material key_1 configure register */ - - struct { - __IOM uint32_t KEY_1 : 32; /*!< This bits stores key_1 that is a part of key material. */ - } bit; - } KEY_1; - - union { - __IOM uint32_t reg; /*!< Key material key_2 configure register */ - - struct { - __IOM uint32_t KEY_2 : 32; /*!< This bits stores key_2 that is a part of key material. */ - } bit; - } KEY_2; - - union { - __IOM uint32_t reg; /*!< Key material key_3 configure register */ - - struct { - __IOM uint32_t KEY_3 : 32; /*!< This bits stores key_3 that is a part of key material. */ - } bit; - } KEY_3; - - union { - __IOM uint32_t reg; /*!< Key material key_4 configure register */ - - struct { - __IOM uint32_t KEY_4 : 32; /*!< This bits stores key_4 that is a part of key material. */ - } bit; - } KEY_4; - - union { - __IOM uint32_t reg; /*!< Key material key_5 configure register */ - - struct { - __IOM uint32_t KEY_5 : 32; /*!< This bits stores key_5 that is a part of key material. */ - } bit; - } KEY_5; - - union { - __IOM uint32_t reg; /*!< Key material key_6 configure register */ - - struct { - __IOM uint32_t KEY_6 : 32; /*!< This bits stores key_6 that is a part of key material. */ - } bit; - } KEY_6; - - union { - __IOM uint32_t reg; /*!< Key material key_7 configure register */ - - struct { - __IOM uint32_t KEY_7 : 32; /*!< This bits stores key_7 that is a part of key material. */ - } bit; - } KEY_7; - - union { - __IOM uint32_t reg; /*!< source text material text_in_0 configure register */ - - struct { - __IOM uint32_t TEXT_IN_0 : 32; /*!< This bits stores text_in_0 that is a part of source text material. */ - } bit; - } TEXT_IN_0; - - union { - __IOM uint32_t reg; /*!< source text material text_in_1 configure register */ - - struct { - __IOM uint32_t TEXT_IN_1 : 32; /*!< This bits stores text_in_1 that is a part of source text material. */ - } bit; - } TEXT_IN_1; - - union { - __IOM uint32_t reg; /*!< source text material text_in_2 configure register */ - - struct { - __IOM uint32_t TEXT_IN_2 : 32; /*!< This bits stores text_in_2 that is a part of source text material. */ - } bit; - } TEXT_IN_2; - - union { - __IOM uint32_t reg; /*!< source text material text_in_3 configure register */ - - struct { - __IOM uint32_t TEXT_IN_3 : 32; /*!< This bits stores text_in_3 that is a part of source text material. */ - } bit; - } TEXT_IN_3; - - union { - __IOM uint32_t reg; /*!< result text material text_out_0 configure register */ - - struct { - __IOM uint32_t TEXT_OUT_0 : 32; /*!< This bits stores text_out_0 that is a part of result text material. */ - } bit; - } TEXT_OUT_0; - - union { - __IOM uint32_t reg; /*!< result text material text_out_1 configure register */ - - struct { - __IOM uint32_t TEXT_OUT_1 : 32; /*!< This bits stores text_out_1 that is a part of result text material. */ - } bit; - } TEXT_OUT_1; - - union { - __IOM uint32_t reg; /*!< result text material text_out_2 configure register */ - - struct { - __IOM uint32_t TEXT_OUT_2 : 32; /*!< This bits stores text_out_2 that is a part of result text material. */ - } bit; - } TEXT_OUT_2; - - union { - __IOM uint32_t reg; /*!< result text material text_out_3 configure register */ - - struct { - __IOM uint32_t TEXT_OUT_3 : 32; /*!< This bits stores text_out_3 that is a part of result text material. */ - } bit; - } TEXT_OUT_3; - - union { - __IOM uint32_t reg; /*!< AES Mode register */ - - struct { - __IOM uint32_t MODE : 3; /*!< This bits decides which one operation mode will be used. 3'd0: - AES-EN-128, 3'd1: AES-EN-192, 3'd2: AES-EN-256, 3'd4: AES-DE-128, - 3'd5: AES-DE-192, 3'd6: AES-DE-256. */ - uint32_t : 29; - } bit; - } MODE; - - union { - __IOM uint32_t reg; /*!< AES Endian configure register */ - - struct { - __IOM uint32_t ENDIAN : 6; /*!< endian. [1:0] key endian, [3:2] text_in endian or in_stream - endian, [5:4] text_out endian or out_stream endian */ - uint32_t : 26; - } bit; - } ENDIAN; - - union { - __IOM uint32_t reg; /*!< AES trigger register */ - - struct { - __OM uint32_t TRIGGER : 1; /*!< Set this bit to start AES calculation. */ - uint32_t : 31; - } bit; - } TRIGGER; - - union { - __IOM uint32_t reg; /*!< AES state register */ - - struct { - __IM uint32_t STATE : 2; /*!< Those bits shows AES status. For typical AES, 0: idle, 1: busy. - For DMA-AES, 0: idle, 1: busy, 2: calculation_done. */ - uint32_t : 30; - } bit; - } STATE; - __IOM uint32_t IV_MEM[4]; /*!< The memory that stores initialization vector */ - __IOM uint32_t H_MEM[4]; /*!< The memory that stores GCM hash subkey */ - __IOM uint32_t J0_MEM[4]; /*!< The memory that stores J0 */ - __IOM uint32_t T0_MEM[4]; /*!< The memory that stores T0 */ - - union { - __IOM uint32_t reg; /*!< DMA-AES working mode register */ - - struct { - __IOM uint32_t DMA_ENABLE : 1; /*!< 1'b0: typical AES working mode, 1'b1: DMA-AES working mode. */ - uint32_t : 31; - } bit; - } DMA_ENABLE; - - union { - __IOM uint32_t reg; /*!< AES cipher block mode register */ - - struct { - __IOM uint32_t BLOCK_MODE : 3; /*!< Those bits decides which block mode will be used. 0x0: ECB, - 0x1: CBC, 0x2: OFB, 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, - 0x6: GCM, 0x7: reserved. */ - uint32_t : 29; - } bit; - } BLOCK_MODE; - - union { - __IOM uint32_t reg; /*!< AES block number register */ - - struct { - __IOM uint32_t BLOCK_NUM : 32; /*!< Those bits stores the number of Plaintext/ciphertext block. */ - } bit; - } BLOCK_NUM; - - union { - __IOM uint32_t reg; /*!< Standard incrementing function configure register */ - - struct { - __IOM uint32_t INC_SEL : 1; /*!< This bit decides the standard incrementing function. 0: INC32. - 1: INC128. */ - uint32_t : 31; - } bit; - } INC_SEL; - - union { - __IOM uint32_t reg; /*!< Additional Authential Data block number register */ - - struct { - __IOM uint32_t AAD_BLOCK_NUM : 32; /*!< Those bits stores the number of AAD block. */ - } bit; - } AAD_BLOCK_NUM; - - union { - __IOM uint32_t reg; /*!< AES remainder bit number register */ - - struct { - __IOM uint32_t REMAINDER_BIT_NUM : 7; /*!< Those bits stores the number of remainder bit. */ - uint32_t : 25; - } bit; - } REMAINDER_BIT_NUM; - - union { - __IOM uint32_t reg; /*!< AES continue register */ - - struct { - __OM uint32_t CONTINUE : 1; /*!< Set this bit to continue GCM operation. */ - uint32_t : 31; - } bit; - } CONTINUE; - - union { - __IOM uint32_t reg; /*!< AES Interrupt clear register */ - - struct { - __OM uint32_t INT_CLEAR : 1; /*!< Set this bit to clear the AES interrupt. */ - uint32_t : 31; - } bit; - } INT_CLEAR; - - union { - __IOM uint32_t reg; /*!< AES Interrupt enable register */ - - struct { - __IOM uint32_t INT_ENA : 1; /*!< Set this bit to enable interrupt that occurs when DMA-AES calculation - is done. */ - uint32_t : 31; - } bit; - } INT_ENA; - - union { - __IOM uint32_t reg; /*!< AES version control register */ - - struct { - __IOM uint32_t DATE : 30; /*!< This bits stores the version information of AES. */ - uint32_t : 2; - } bit; - } DATE; - - union { - __IOM uint32_t reg; /*!< AES-DMA exit config */ - - struct { - __OM uint32_t DMA_EXIT : 1; /*!< Set this register to leave calculation done stage. Recommend - to use it after software finishes reading DMA's output - buffer. */ - uint32_t : 31; - } bit; - } DMA_EXIT; -} AES_Type; /*!< Size = 188 (0xbc) */ - - - -/* =========================================================================================================================== */ -/* ================ AHB_DMA ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief AHB_DMA Peripheral (AHB_DMA) - */ - -typedef struct { /*!< AHB_DMA Structure */ - - union { - __IOM uint32_t reg; /*!< Raw status interrupt of channel 0 */ - - struct { - __IOM uint32_t IN_DONE_CH_INT_RAW : 1; /*!< The raw interrupt bit turns to high level when the last data - pointed by one inlink descriptor has been received for - Rx channel 0. */ - __IOM uint32_t IN_SUC_EOF_CH_INT_RAW : 1; /*!< The raw interrupt bit turns to high level when the last data - pointed by one inlink descriptor has been received for - Rx channel 0. For UHCI0 the raw interrupt bit turns to - high level when the last data pointed by one inlink descriptor - has been received and no data error is detected for Rx - channel 0. */ - __IOM uint32_t IN_ERR_EOF_CH_INT_RAW : 1; /*!< The raw interrupt bit turns to high level when data error is - detected only in the case that the peripheral is UHCI0 - for Rx channel 0. For other peripherals this raw interrupt - is reserved. */ - __IOM uint32_t IN_DSCR_ERR_CH_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when detecting inlink - descriptor error including owner error and the second and - third word error of inlink descriptor for Rx channel 0. */ - __IOM uint32_t IN_DSCR_EMPTY_CH_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when Rx buffer pointed - by inlink is full and receiving data is not completed but - there is no more inlink for Rx channel 0. */ - __IOM uint32_t INFIFO_OVF_CH_INT_RAW : 1; /*!< This raw interrupt bit turns to high level when level 1 fifo - of Rx channel 0 is overflow. */ - __IOM uint32_t INFIFO_UDF_CH_INT_RAW : 1; /*!< This raw interrupt bit turns to high level when level 1 fifo - of Rx channel 0 is underflow. */ - uint32_t : 25; - } bit; - } IN_INT_RAW_CH0; - - union { - __IOM uint32_t reg; /*!< Masked interrupt of channel 0 */ - - struct { - __IM uint32_t IN_DONE_CH_INT_ST : 1; /*!< The raw interrupt status bit for the IN_DONE_CH_INT interrupt. */ - __IM uint32_t IN_SUC_EOF_CH_INT_ST : 1; /*!< The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. */ - __IM uint32_t IN_ERR_EOF_CH_INT_ST : 1; /*!< The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. */ - __IM uint32_t IN_DSCR_ERR_CH_INT_ST : 1; /*!< The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. */ - __IM uint32_t IN_DSCR_EMPTY_CH_INT_ST : 1;/*!< The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. */ - __IM uint32_t INFIFO_OVF_CH_INT_ST : 1; /*!< The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. */ - __IM uint32_t INFIFO_UDF_CH_INT_ST : 1; /*!< The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. */ - uint32_t : 25; - } bit; - } IN_INT_ST_CH0; - - union { - __IOM uint32_t reg; /*!< Interrupt enable bits of channel 0 */ - - struct { - __IOM uint32_t IN_DONE_CH_INT_ENA : 1; /*!< The interrupt enable bit for the IN_DONE_CH_INT interrupt. */ - __IOM uint32_t IN_SUC_EOF_CH_INT_ENA : 1; /*!< The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. */ - __IOM uint32_t IN_ERR_EOF_CH_INT_ENA : 1; /*!< The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. */ - __IOM uint32_t IN_DSCR_ERR_CH_INT_ENA : 1;/*!< The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. */ - __IOM uint32_t IN_DSCR_EMPTY_CH_INT_ENA : 1;/*!< The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. */ - __IOM uint32_t INFIFO_OVF_CH_INT_ENA : 1; /*!< The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. */ - __IOM uint32_t INFIFO_UDF_CH_INT_ENA : 1; /*!< The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. */ - uint32_t : 25; - } bit; - } IN_INT_ENA_CH0; - - union { - __IOM uint32_t reg; /*!< Interrupt clear bits of channel 0 */ - - struct { - __OM uint32_t IN_DONE_CH_INT_CLR : 1; /*!< Set this bit to clear the IN_DONE_CH_INT interrupt. */ - __OM uint32_t IN_SUC_EOF_CH_INT_CLR : 1; /*!< Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. */ - __OM uint32_t IN_ERR_EOF_CH_INT_CLR : 1; /*!< Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. */ - __OM uint32_t IN_DSCR_ERR_CH_INT_CLR : 1;/*!< Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. */ - __OM uint32_t IN_DSCR_EMPTY_CH_INT_CLR : 1;/*!< Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. */ - __OM uint32_t INFIFO_OVF_CH_INT_CLR : 1; /*!< Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. */ - __OM uint32_t INFIFO_UDF_CH_INT_CLR : 1; /*!< Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. */ - uint32_t : 25; - } bit; - } IN_INT_CLR_CH0; - __IM uint32_t RESERVED[8]; - - union { - __IOM uint32_t reg; /*!< Raw status interrupt of channel 0 */ - - struct { - __IOM uint32_t OUT_DONE_CH_INT_RAW : 1; /*!< The raw interrupt bit turns to high level when the last data - pointed by one outlink descriptor has been transmitted - to peripherals for Tx channel 0. */ - __IOM uint32_t OUT_EOF_CH_INT_RAW : 1; /*!< The raw interrupt bit turns to high level when the last data - pointed by one outlink descriptor has been read from memory - for Tx channel 0. */ - __IOM uint32_t OUT_DSCR_ERR_CH_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when detecting outlink - descriptor error including owner error and the second and - third word error of outlink descriptor for Tx channel 0. */ - __IOM uint32_t OUT_TOTAL_EOF_CH_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when data corresponding - a outlink (includes one link descriptor or few link descriptors) - is transmitted out for Tx channel 0. */ - __IOM uint32_t OUTFIFO_OVF_CH_INT_RAW : 1;/*!< This raw interrupt bit turns to high level when level 1 fifo - of Tx channel 0 is overflow. */ - __IOM uint32_t OUTFIFO_UDF_CH_INT_RAW : 1;/*!< This raw interrupt bit turns to high level when level 1 fifo - of Tx channel 0 is underflow. */ - uint32_t : 26; - } bit; - } OUT_INT_RAW_CH0; - - union { - __IOM uint32_t reg; /*!< Masked interrupt of channel 0 */ - - struct { - __IM uint32_t OUT_DONE_CH_INT_ST : 1; /*!< The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. */ - __IM uint32_t OUT_EOF_CH_INT_ST : 1; /*!< The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. */ - __IM uint32_t OUT_DSCR_ERR_CH_INT_ST : 1;/*!< The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. */ - __IM uint32_t OUT_TOTAL_EOF_CH_INT_ST : 1;/*!< The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. */ - __IM uint32_t OUTFIFO_OVF_CH_INT_ST : 1; /*!< The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. */ - __IM uint32_t OUTFIFO_UDF_CH_INT_ST : 1; /*!< The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. */ - uint32_t : 26; - } bit; - } OUT_INT_ST_CH0; - - union { - __IOM uint32_t reg; /*!< Interrupt enable bits of channel 0 */ - - struct { - __IOM uint32_t OUT_DONE_CH_INT_ENA : 1; /*!< The interrupt enable bit for the OUT_DONE_CH_INT interrupt. */ - __IOM uint32_t OUT_EOF_CH_INT_ENA : 1; /*!< The interrupt enable bit for the OUT_EOF_CH_INT interrupt. */ - __IOM uint32_t OUT_DSCR_ERR_CH_INT_ENA : 1;/*!< The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. */ - __IOM uint32_t OUT_TOTAL_EOF_CH_INT_ENA : 1;/*!< The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. */ - __IOM uint32_t OUTFIFO_OVF_CH_INT_ENA : 1;/*!< The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. */ - __IOM uint32_t OUTFIFO_UDF_CH_INT_ENA : 1;/*!< The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. */ - uint32_t : 26; - } bit; - } OUT_INT_ENA_CH0; - - union { - __IOM uint32_t reg; /*!< Interrupt clear bits of channel 0 */ - - struct { - __OM uint32_t OUT_DONE_CH_INT_CLR : 1; /*!< Set this bit to clear the OUT_DONE_CH_INT interrupt. */ - __OM uint32_t OUT_EOF_CH_INT_CLR : 1; /*!< Set this bit to clear the OUT_EOF_CH_INT interrupt. */ - __OM uint32_t OUT_DSCR_ERR_CH_INT_CLR : 1;/*!< Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. */ - __OM uint32_t OUT_TOTAL_EOF_CH_INT_CLR : 1;/*!< Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. */ - __OM uint32_t OUTFIFO_OVF_CH_INT_CLR : 1;/*!< Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. */ - __OM uint32_t OUTFIFO_UDF_CH_INT_CLR : 1;/*!< Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. */ - uint32_t : 26; - } bit; - } OUT_INT_CLR_CH0; - - union { - __IOM uint32_t reg; /*!< Raw status interrupt of channel 0 */ - - struct { - __IOM uint32_t IN_DONE_CH_INT_RAW : 1; /*!< The raw interrupt bit turns to high level when the last data - pointed by one inlink descriptor has been received for - Rx channel 0. */ - __IOM uint32_t IN_SUC_EOF_CH_INT_RAW : 1; /*!< The raw interrupt bit turns to high level when the last data - pointed by one inlink descriptor has been received for - Rx channel 0. For UHCI0 the raw interrupt bit turns to - high level when the last data pointed by one inlink descriptor - has been received and no data error is detected for Rx - channel 0. */ - __IOM uint32_t IN_ERR_EOF_CH_INT_RAW : 1; /*!< The raw interrupt bit turns to high level when data error is - detected only in the case that the peripheral is UHCI0 - for Rx channel 0. For other peripherals this raw interrupt - is reserved. */ - __IOM uint32_t IN_DSCR_ERR_CH_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when detecting inlink - descriptor error including owner error and the second and - third word error of inlink descriptor for Rx channel 0. */ - __IOM uint32_t IN_DSCR_EMPTY_CH_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when Rx buffer pointed - by inlink is full and receiving data is not completed but - there is no more inlink for Rx channel 0. */ - __IOM uint32_t INFIFO_OVF_CH_INT_RAW : 1; /*!< This raw interrupt bit turns to high level when level 1 fifo - of Rx channel 0 is overflow. */ - __IOM uint32_t INFIFO_UDF_CH_INT_RAW : 1; /*!< This raw interrupt bit turns to high level when level 1 fifo - of Rx channel 0 is underflow. */ - uint32_t : 25; - } bit; - } IN_INT_RAW_CH1; - - union { - __IOM uint32_t reg; /*!< Masked interrupt of channel 0 */ - - struct { - __IM uint32_t IN_DONE_CH_INT_ST : 1; /*!< The raw interrupt status bit for the IN_DONE_CH_INT interrupt. */ - __IM uint32_t IN_SUC_EOF_CH_INT_ST : 1; /*!< The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. */ - __IM uint32_t IN_ERR_EOF_CH_INT_ST : 1; /*!< The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. */ - __IM uint32_t IN_DSCR_ERR_CH_INT_ST : 1; /*!< The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. */ - __IM uint32_t IN_DSCR_EMPTY_CH_INT_ST : 1;/*!< The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. */ - __IM uint32_t INFIFO_OVF_CH_INT_ST : 1; /*!< The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. */ - __IM uint32_t INFIFO_UDF_CH_INT_ST : 1; /*!< The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. */ - uint32_t : 25; - } bit; - } IN_INT_ST_CH1; - - union { - __IOM uint32_t reg; /*!< Interrupt enable bits of channel 0 */ - - struct { - __IOM uint32_t IN_DONE_CH_INT_ENA : 1; /*!< The interrupt enable bit for the IN_DONE_CH_INT interrupt. */ - __IOM uint32_t IN_SUC_EOF_CH_INT_ENA : 1; /*!< The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. */ - __IOM uint32_t IN_ERR_EOF_CH_INT_ENA : 1; /*!< The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. */ - __IOM uint32_t IN_DSCR_ERR_CH_INT_ENA : 1;/*!< The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. */ - __IOM uint32_t IN_DSCR_EMPTY_CH_INT_ENA : 1;/*!< The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. */ - __IOM uint32_t INFIFO_OVF_CH_INT_ENA : 1; /*!< The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. */ - __IOM uint32_t INFIFO_UDF_CH_INT_ENA : 1; /*!< The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. */ - uint32_t : 25; - } bit; - } IN_INT_ENA_CH1; - - union { - __IOM uint32_t reg; /*!< Interrupt clear bits of channel 0 */ - - struct { - __OM uint32_t IN_DONE_CH_INT_CLR : 1; /*!< Set this bit to clear the IN_DONE_CH_INT interrupt. */ - __OM uint32_t IN_SUC_EOF_CH_INT_CLR : 1; /*!< Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. */ - __OM uint32_t IN_ERR_EOF_CH_INT_CLR : 1; /*!< Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. */ - __OM uint32_t IN_DSCR_ERR_CH_INT_CLR : 1;/*!< Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. */ - __OM uint32_t IN_DSCR_EMPTY_CH_INT_CLR : 1;/*!< Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. */ - __OM uint32_t INFIFO_OVF_CH_INT_CLR : 1; /*!< Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. */ - __OM uint32_t INFIFO_UDF_CH_INT_CLR : 1; /*!< Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. */ - uint32_t : 25; - } bit; - } IN_INT_CLR_CH1; - __IM uint32_t RESERVED1[4]; - - union { - __IOM uint32_t reg; /*!< reserved */ - - struct { - __IOM uint32_t AHB_TESTMODE : 3; /*!< reserved */ - uint32_t : 1; - __IOM uint32_t AHB_TESTADDR : 2; /*!< reserved */ - uint32_t : 26; - } bit; - } AHB_TEST; - - union { - __IOM uint32_t reg; /*!< MISC register */ - - struct { - __IOM uint32_t AHBM_RST_INTER : 1; /*!< Set this bit then clear this bit to reset the internal ahb FSM. */ - uint32_t : 1; - __IOM uint32_t ARB_PRI_DIS : 1; /*!< Set this bit to disable priority arbitration function. */ - __IOM uint32_t CLK_EN : 1; /*!< 1'h1: Force clock on for register. 1'h0: Support clock only - when application writes registers. */ - uint32_t : 28; - } bit; - } MISC_CONF; - - union { - __IOM uint32_t reg; /*!< Version control register */ - - struct { - __IOM uint32_t DATE : 32; /*!< register version. */ - } bit; - } DATE; - __IM uint32_t RESERVED2; - - union { - union { - __IOM uint32_t reg; /*!< Raw status interrupt of channel 0 */ - - struct { - __IOM uint32_t OUT_DONE_CH_INT_RAW : 1; /*!< The raw interrupt bit turns to high level when the last data - pointed by one outlink descriptor has been transmitted - to peripherals for Tx channel 0. */ - __IOM uint32_t OUT_EOF_CH_INT_RAW : 1; /*!< The raw interrupt bit turns to high level when the last data - pointed by one outlink descriptor has been read from memory - for Tx channel 0. */ - __IOM uint32_t OUT_DSCR_ERR_CH_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when detecting outlink - descriptor error including owner error and the second and - third word error of outlink descriptor for Tx channel 0. */ - __IOM uint32_t OUT_TOTAL_EOF_CH_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when data corresponding - a outlink (includes one link descriptor or few link descriptors) - is transmitted out for Tx channel 0. */ - __IOM uint32_t OUTFIFO_OVF_CH_INT_RAW : 1;/*!< This raw interrupt bit turns to high level when level 1 fifo - of Tx channel 0 is overflow. */ - __IOM uint32_t OUTFIFO_UDF_CH_INT_RAW : 1;/*!< This raw interrupt bit turns to high level when level 1 fifo - of Tx channel 0 is underflow. */ - uint32_t : 26; - } bit; - } OUT_INT_RAW_CH1; - - union { - __IOM uint32_t reg; /*!< Configure 0 register of Rx channel 0 */ - - struct { - __IOM uint32_t IN_RST_CH : 1; /*!< This bit is used to reset AHB_DMA channel 0 Rx FSM and Rx FIFO - pointer. */ - __IOM uint32_t IN_LOOP_TEST_CH : 1; /*!< reserved */ - __IOM uint32_t INDSCR_BURST_EN_CH : 1; /*!< Set this bit to 1 to enable INCR burst transfer for Rx channel - 0 reading link descriptor when accessing internal SRAM. */ - __IOM uint32_t IN_DATA_BURST_EN_CH : 1; /*!< Set this bit to 1 to enable INCR burst transfer for Rx channel - 0 receiving data when accessing internal SRAM. */ - __IOM uint32_t MEM_TRANS_EN_CH : 1; /*!< Set this bit 1 to enable automatic transmitting data from memory - to memory via AHB_DMA. */ - __IOM uint32_t IN_ETM_EN_CH : 1; /*!< Set this bit to 1 to enable etm control mode, dma Rx channel - 0 is triggered by etm task. */ - uint32_t : 26; - } bit; - } IN_CONF0_CH0; - }; - - union { - union { - __IOM uint32_t reg; /*!< Masked interrupt of channel 0 */ - - struct { - __IM uint32_t OUT_DONE_CH_INT_ST : 1; /*!< The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. */ - __IM uint32_t OUT_EOF_CH_INT_ST : 1; /*!< The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. */ - __IM uint32_t OUT_DSCR_ERR_CH_INT_ST : 1;/*!< The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. */ - __IM uint32_t OUT_TOTAL_EOF_CH_INT_ST : 1;/*!< The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. */ - __IM uint32_t OUTFIFO_OVF_CH_INT_ST : 1;/*!< The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. */ - __IM uint32_t OUTFIFO_UDF_CH_INT_ST : 1;/*!< The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. */ - uint32_t : 26; - } bit; - } OUT_INT_ST_CH1; - - union { - __IOM uint32_t reg; /*!< Configure 1 register of Rx channel 0 */ - - struct { - uint32_t : 12; - __IOM uint32_t IN_CHECK_OWNER_CH : 1; /*!< Set this bit to enable checking the owner attribute of the link - descriptor. */ - uint32_t : 19; - } bit; - } IN_CONF1_CH0; - }; - - union { - union { - __IOM uint32_t reg; /*!< Interrupt enable bits of channel 0 */ - - struct { - __IOM uint32_t OUT_DONE_CH_INT_ENA : 1; /*!< The interrupt enable bit for the OUT_DONE_CH_INT interrupt. */ - __IOM uint32_t OUT_EOF_CH_INT_ENA : 1; /*!< The interrupt enable bit for the OUT_EOF_CH_INT interrupt. */ - __IOM uint32_t OUT_DSCR_ERR_CH_INT_ENA : 1;/*!< The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. */ - __IOM uint32_t OUT_TOTAL_EOF_CH_INT_ENA : 1;/*!< The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. */ - __IOM uint32_t OUTFIFO_OVF_CH_INT_ENA : 1;/*!< The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. */ - __IOM uint32_t OUTFIFO_UDF_CH_INT_ENA : 1;/*!< The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. */ - uint32_t : 26; - } bit; - } OUT_INT_ENA_CH1; - - union { - __IOM uint32_t reg; /*!< Receive FIFO status of Rx channel 0 */ - - struct { - __IM uint32_t INFIFO_FULL_CH : 1; /*!< L1 Rx FIFO full signal for Rx channel 0. */ - __IM uint32_t INFIFO_EMPTY_CH : 1; /*!< L1 Rx FIFO empty signal for Rx channel 0. */ - __IM uint32_t INFIFO_CNT_CH : 6; /*!< The register stores the byte number of the data in L1 Rx FIFO - for Rx channel 0. */ - uint32_t : 15; - __IM uint32_t IN_REMAIN_UNDER_1B_CH : 1;/*!< reserved */ - __IM uint32_t IN_REMAIN_UNDER_2B_CH : 1;/*!< reserved */ - __IM uint32_t IN_REMAIN_UNDER_3B_CH : 1;/*!< reserved */ - __IM uint32_t IN_REMAIN_UNDER_4B_CH : 1;/*!< reserved */ - __IM uint32_t IN_BUF_HUNGRY_CH : 1; /*!< reserved */ - uint32_t : 4; - } bit; - } INFIFO_STATUS_CH0; - }; - - union { - union { - __IOM uint32_t reg; /*!< Interrupt clear bits of channel 0 */ - - struct { - __OM uint32_t OUT_DONE_CH_INT_CLR : 1; /*!< Set this bit to clear the OUT_DONE_CH_INT interrupt. */ - __OM uint32_t OUT_EOF_CH_INT_CLR : 1; /*!< Set this bit to clear the OUT_EOF_CH_INT interrupt. */ - __OM uint32_t OUT_DSCR_ERR_CH_INT_CLR : 1;/*!< Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. */ - __OM uint32_t OUT_TOTAL_EOF_CH_INT_CLR : 1;/*!< Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. */ - __OM uint32_t OUTFIFO_OVF_CH_INT_CLR : 1;/*!< Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. */ - __OM uint32_t OUTFIFO_UDF_CH_INT_CLR : 1;/*!< Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. */ - uint32_t : 26; - } bit; - } OUT_INT_CLR_CH1; - - union { - __IOM uint32_t reg; /*!< Pop control register of Rx channel 0 */ - - struct { - __IM uint32_t INFIFO_RDATA_CH : 12; /*!< This register stores the data popping from AHB_DMA FIFO. */ - __OM uint32_t INFIFO_POP_CH : 1; /*!< Set this bit to pop data from AHB_DMA FIFO. */ - uint32_t : 19; - } bit; - } IN_POP_CH0; - }; - - union { - union { - __IOM uint32_t reg; /*!< Raw status interrupt of channel 0 */ - - struct { - __IOM uint32_t IN_DONE_CH_INT_RAW : 1; /*!< The raw interrupt bit turns to high level when the last data - pointed by one inlink descriptor has been received for - Rx channel 0. */ - __IOM uint32_t IN_SUC_EOF_CH_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when the last data - pointed by one inlink descriptor has been received for - Rx channel 0. For UHCI0 the raw interrupt bit turns to - high level when the last data pointed by one inlink descriptor - has been received and no data error is detected for Rx - channel 0. */ - __IOM uint32_t IN_ERR_EOF_CH_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when data error is - detected only in the case that the peripheral is UHCI0 - for Rx channel 0. For other peripherals this raw interrupt - is reserved. */ - __IOM uint32_t IN_DSCR_ERR_CH_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when detecting inlink - descriptor error including owner error and the second and - third word error of inlink descriptor for Rx channel 0. */ - __IOM uint32_t IN_DSCR_EMPTY_CH_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when Rx buffer pointed - by inlink is full and receiving data is not completed but - there is no more inlink for Rx channel 0. */ - __IOM uint32_t INFIFO_OVF_CH_INT_RAW : 1;/*!< This raw interrupt bit turns to high level when level 1 fifo - of Rx channel 0 is overflow. */ - __IOM uint32_t INFIFO_UDF_CH_INT_RAW : 1;/*!< This raw interrupt bit turns to high level when level 1 fifo - of Rx channel 0 is underflow. */ - uint32_t : 25; - } bit; - } IN_INT_RAW_CH2; - - union { - __IOM uint32_t reg; /*!< Link descriptor configure and control register of Rx channel - 0 */ - - struct { - __IOM uint32_t INLINK_AUTO_RET_CH : 1; /*!< Set this bit to return to current inlink descriptor's address - when there are some errors in current receiving data. */ - __OM uint32_t INLINK_STOP_CH : 1; /*!< Set this bit to stop dealing with the inlink descriptors. */ - __OM uint32_t INLINK_START_CH : 1; /*!< Set this bit to start dealing with the inlink descriptors. */ - __OM uint32_t INLINK_RESTART_CH : 1; /*!< Set this bit to mount a new inlink descriptor. */ - __IM uint32_t INLINK_PARK_CH : 1; /*!< 1: the inlink descriptor's FSM is in idle state. 0: the inlink - descriptor's FSM is working. */ - uint32_t : 27; - } bit; - } IN_LINK_CH0; - }; - - union { - union { - __IOM uint32_t reg; /*!< Masked interrupt of channel 0 */ - - struct { - __IM uint32_t IN_DONE_CH_INT_ST : 1; /*!< The raw interrupt status bit for the IN_DONE_CH_INT interrupt. */ - __IM uint32_t IN_SUC_EOF_CH_INT_ST : 1;/*!< The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. */ - __IM uint32_t IN_ERR_EOF_CH_INT_ST : 1;/*!< The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. */ - __IM uint32_t IN_DSCR_ERR_CH_INT_ST : 1;/*!< The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. */ - __IM uint32_t IN_DSCR_EMPTY_CH_INT_ST : 1;/*!< The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. */ - __IM uint32_t INFIFO_OVF_CH_INT_ST : 1;/*!< The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. */ - __IM uint32_t INFIFO_UDF_CH_INT_ST : 1;/*!< The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. */ - uint32_t : 25; - } bit; - } IN_INT_ST_CH2; - - union { - __IOM uint32_t reg; /*!< Receive status of Rx channel 0 */ - - struct { - __IM uint32_t INLINK_DSCR_ADDR_CH : 18;/*!< This register stores the current inlink descriptor's address. */ - __IM uint32_t IN_DSCR_STATE_CH : 2; /*!< reserved */ - __IM uint32_t IN_STATE_CH : 3; /*!< reserved */ - uint32_t : 9; - } bit; - } IN_STATE_CH0; - }; - - union { - union { - __IOM uint32_t reg; /*!< Interrupt enable bits of channel 0 */ - - struct { - __IOM uint32_t IN_DONE_CH_INT_ENA : 1; /*!< The interrupt enable bit for the IN_DONE_CH_INT interrupt. */ - __IOM uint32_t IN_SUC_EOF_CH_INT_ENA : 1;/*!< The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. */ - __IOM uint32_t IN_ERR_EOF_CH_INT_ENA : 1;/*!< The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. */ - __IOM uint32_t IN_DSCR_ERR_CH_INT_ENA : 1;/*!< The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. */ - __IOM uint32_t IN_DSCR_EMPTY_CH_INT_ENA : 1;/*!< The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. */ - __IOM uint32_t INFIFO_OVF_CH_INT_ENA : 1;/*!< The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. */ - __IOM uint32_t INFIFO_UDF_CH_INT_ENA : 1;/*!< The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. */ - uint32_t : 25; - } bit; - } IN_INT_ENA_CH2; - - union { - __IOM uint32_t reg; /*!< Inlink descriptor address when EOF occurs of Rx channel 0 */ - - struct { - __IM uint32_t IN_SUC_EOF_DES_ADDR_CH : 32;/*!< This register stores the address of the inlink descriptor when - the EOF bit in this descriptor is 1. */ - } bit; - } IN_SUC_EOF_DES_ADDR_CH0; - }; - - union { - union { - __IOM uint32_t reg; /*!< Interrupt clear bits of channel 0 */ - - struct { - __OM uint32_t IN_DONE_CH_INT_CLR : 1; /*!< Set this bit to clear the IN_DONE_CH_INT interrupt. */ - __OM uint32_t IN_SUC_EOF_CH_INT_CLR : 1;/*!< Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. */ - __OM uint32_t IN_ERR_EOF_CH_INT_CLR : 1;/*!< Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. */ - __OM uint32_t IN_DSCR_ERR_CH_INT_CLR : 1;/*!< Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. */ - __OM uint32_t IN_DSCR_EMPTY_CH_INT_CLR : 1;/*!< Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. */ - __OM uint32_t INFIFO_OVF_CH_INT_CLR : 1;/*!< Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. */ - __OM uint32_t INFIFO_UDF_CH_INT_CLR : 1;/*!< Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. */ - uint32_t : 25; - } bit; - } IN_INT_CLR_CH2; - - union { - __IOM uint32_t reg; /*!< Inlink descriptor address when errors occur of Rx channel 0 */ - - struct { - __IM uint32_t IN_ERR_EOF_DES_ADDR_CH : 32;/*!< This register stores the address of the inlink descriptor when - there are some errors in current receiving data. Only used - when peripheral is UHCI0. */ - } bit; - } IN_ERR_EOF_DES_ADDR_CH0; - }; - - union { - __IOM uint32_t reg; /*!< Current inlink descriptor address of Rx channel 0 */ - - struct { - __IM uint32_t INLINK_DSCR_CH : 32; /*!< The address of the current inlink descriptor x. */ - } bit; - } IN_DSCR_CH0; - - union { - __IOM uint32_t reg; /*!< The last inlink descriptor address of Rx channel 0 */ - - struct { - __IM uint32_t INLINK_DSCR_BF0_CH : 32; /*!< The address of the last inlink descriptor x-1. */ - } bit; - } IN_DSCR_BF0_CH0; - - union { - __IOM uint32_t reg; /*!< The second-to-last inlink descriptor address of Rx channel 0 */ - - struct { - __IM uint32_t INLINK_DSCR_BF1_CH : 32; /*!< The address of the second-to-last inlink descriptor x-2. */ - } bit; - } IN_DSCR_BF1_CH0; - - union { - __IOM uint32_t reg; /*!< Priority register of Rx channel 0 */ - - struct { - __IOM uint32_t RX_PRI_CH : 4; /*!< The priority of Rx channel 0. The larger of the value the higher - of the priority. */ - uint32_t : 28; - } bit; - } IN_PRI_CH0; - - union { - __IOM uint32_t reg; /*!< Peripheral selection of Rx channel 0 */ - - struct { - __IOM uint32_t PERI_IN_SEL_CH : 6; /*!< This register is used to select peripheral for Rx channel 0. - I3C. 1: Dummy. 2: UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: - Dummy. 7: Dummy. 8: ADC_DAC. 9: Dummy. 10: RMT,11~15: Dummy */ - uint32_t : 26; - } bit; - } IN_PERI_SEL_CH0; - __IM uint32_t RESERVED3[3]; - - union { - __IOM uint32_t reg; /*!< Raw status interrupt of channel 0 */ - - struct { - __IOM uint32_t OUT_DONE_CH_INT_RAW : 1; /*!< The raw interrupt bit turns to high level when the last data - pointed by one outlink descriptor has been transmitted - to peripherals for Tx channel 0. */ - __IOM uint32_t OUT_EOF_CH_INT_RAW : 1; /*!< The raw interrupt bit turns to high level when the last data - pointed by one outlink descriptor has been read from memory - for Tx channel 0. */ - __IOM uint32_t OUT_DSCR_ERR_CH_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when detecting outlink - descriptor error including owner error and the second and - third word error of outlink descriptor for Tx channel 0. */ - __IOM uint32_t OUT_TOTAL_EOF_CH_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when data corresponding - a outlink (includes one link descriptor or few link descriptors) - is transmitted out for Tx channel 0. */ - __IOM uint32_t OUTFIFO_OVF_CH_INT_RAW : 1;/*!< This raw interrupt bit turns to high level when level 1 fifo - of Tx channel 0 is overflow. */ - __IOM uint32_t OUTFIFO_UDF_CH_INT_RAW : 1;/*!< This raw interrupt bit turns to high level when level 1 fifo - of Tx channel 0 is underflow. */ - uint32_t : 26; - } bit; - } OUT_INT_RAW_CH2; - - union { - __IOM uint32_t reg; /*!< Masked interrupt of channel 0 */ - - struct { - __IM uint32_t OUT_DONE_CH_INT_ST : 1; /*!< The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. */ - __IM uint32_t OUT_EOF_CH_INT_ST : 1; /*!< The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. */ - __IM uint32_t OUT_DSCR_ERR_CH_INT_ST : 1;/*!< The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. */ - __IM uint32_t OUT_TOTAL_EOF_CH_INT_ST : 1;/*!< The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. */ - __IM uint32_t OUTFIFO_OVF_CH_INT_ST : 1; /*!< The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. */ - __IM uint32_t OUTFIFO_UDF_CH_INT_ST : 1; /*!< The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. */ - uint32_t : 26; - } bit; - } OUT_INT_ST_CH2; - - union { - __IOM uint32_t reg; /*!< Interrupt enable bits of channel 0 */ - - struct { - __IOM uint32_t OUT_DONE_CH_INT_ENA : 1; /*!< The interrupt enable bit for the OUT_DONE_CH_INT interrupt. */ - __IOM uint32_t OUT_EOF_CH_INT_ENA : 1; /*!< The interrupt enable bit for the OUT_EOF_CH_INT interrupt. */ - __IOM uint32_t OUT_DSCR_ERR_CH_INT_ENA : 1;/*!< The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. */ - __IOM uint32_t OUT_TOTAL_EOF_CH_INT_ENA : 1;/*!< The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. */ - __IOM uint32_t OUTFIFO_OVF_CH_INT_ENA : 1;/*!< The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. */ - __IOM uint32_t OUTFIFO_UDF_CH_INT_ENA : 1;/*!< The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. */ - uint32_t : 26; - } bit; - } OUT_INT_ENA_CH2; - - union { - __IOM uint32_t reg; /*!< Interrupt clear bits of channel 0 */ - - struct { - __OM uint32_t OUT_DONE_CH_INT_CLR : 1; /*!< Set this bit to clear the OUT_DONE_CH_INT interrupt. */ - __OM uint32_t OUT_EOF_CH_INT_CLR : 1; /*!< Set this bit to clear the OUT_EOF_CH_INT interrupt. */ - __OM uint32_t OUT_DSCR_ERR_CH_INT_CLR : 1;/*!< Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. */ - __OM uint32_t OUT_TOTAL_EOF_CH_INT_CLR : 1;/*!< Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. */ - __OM uint32_t OUTFIFO_OVF_CH_INT_CLR : 1;/*!< Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. */ - __OM uint32_t OUTFIFO_UDF_CH_INT_CLR : 1;/*!< Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. */ - uint32_t : 26; - } bit; - } OUT_INT_CLR_CH2; - __IM uint32_t RESERVED4[4]; - - union { - __IOM uint32_t reg; /*!< Configure 0 register of Tx channel 0 */ - - struct { - __IOM uint32_t OUT_RST_CH0 : 1; /*!< This bit is used to reset AHB_DMA channel 0 Tx FSM and Tx FIFO - pointer. */ - __IOM uint32_t OUT_LOOP_TEST_CH0 : 1; /*!< reserved */ - __IOM uint32_t OUT_AUTO_WRBACK_CH0 : 1; /*!< Set this bit to enable automatic outlink-writeback when all - the data in tx buffer has been transmitted. */ - __IOM uint32_t OUT_EOF_MODE_CH0 : 1; /*!< EOF flag generation mode when transmitting data. 1: EOF flag - for Tx channel 0 is generated when data need to transmit - has been popped from FIFO in AHB_DMA */ - __IOM uint32_t OUTDSCR_BURST_EN_CH0 : 1; /*!< Set this bit to 1 to enable INCR burst transfer for Tx channel - 0 reading link descriptor when accessing internal SRAM. */ - __IOM uint32_t OUT_DATA_BURST_EN_CH0 : 1; /*!< Set this bit to 1 to enable INCR burst transfer for Tx channel - 0 transmitting data when accessing internal SRAM. */ - __IOM uint32_t OUT_ETM_EN_CH0 : 1; /*!< Set this bit to 1 to enable etm control mode, dma Tx channel - 0 is triggered by etm task. */ - uint32_t : 25; - } bit; - } OUT_CONF0_CH0; - - union { - __IOM uint32_t reg; /*!< Configure 1 register of Tx channel 0 */ - - struct { - uint32_t : 12; - __IOM uint32_t OUT_CHECK_OWNER_CH : 1; /*!< Set this bit to enable checking the owner attribute of the link - descriptor. */ - uint32_t : 19; - } bit; - } OUT_CONF1_CH0; - - union { - __IOM uint32_t reg; /*!< Transmit FIFO status of Tx channel 0 */ - - struct { - __IM uint32_t OUTFIFO_FULL_CH : 1; /*!< L1 Tx FIFO full signal for Tx channel 0. */ - __IM uint32_t OUTFIFO_EMPTY_CH : 1; /*!< L1 Tx FIFO empty signal for Tx channel 0. */ - __IM uint32_t OUTFIFO_CNT_CH : 6; /*!< The register stores the byte number of the data in L1 Tx FIFO - for Tx channel 0. */ - uint32_t : 15; - __IM uint32_t OUT_REMAIN_UNDER_1B_CH : 1;/*!< reserved */ - __IM uint32_t OUT_REMAIN_UNDER_2B_CH : 1;/*!< reserved */ - __IM uint32_t OUT_REMAIN_UNDER_3B_CH : 1;/*!< reserved */ - __IM uint32_t OUT_REMAIN_UNDER_4B_CH : 1;/*!< reserved */ - uint32_t : 5; - } bit; - } OUTFIFO_STATUS_CH0; - - union { - __IOM uint32_t reg; /*!< Push control register of Rx channel 0 */ - - struct { - __IOM uint32_t OUTFIFO_WDATA_CH : 9; /*!< This register stores the data that need to be pushed into AHB_DMA - FIFO. */ - __OM uint32_t OUTFIFO_PUSH_CH : 1; /*!< Set this bit to push data into AHB_DMA FIFO. */ - uint32_t : 22; - } bit; - } OUT_PUSH_CH0; - - union { - __IOM uint32_t reg; /*!< Link descriptor configure and control register of Tx channel - 0 */ - - struct { - __OM uint32_t OUTLINK_STOP_CH : 1; /*!< Set this bit to stop dealing with the outlink descriptors. */ - __OM uint32_t OUTLINK_START_CH : 1; /*!< Set this bit to start dealing with the outlink descriptors. */ - __OM uint32_t OUTLINK_RESTART_CH : 1; /*!< Set this bit to restart a new outlink from the last address. */ - __IM uint32_t OUTLINK_PARK_CH : 1; /*!< 1: the outlink descriptor's FSM is in idle state. 0: the outlink - descriptor's FSM is working. */ - uint32_t : 28; - } bit; - } OUT_LINK_CH0; - - union { - __IOM uint32_t reg; /*!< Transmit status of Tx channel 0 */ - - struct { - __IM uint32_t OUTLINK_DSCR_ADDR_CH : 18; /*!< This register stores the current outlink descriptor's address. */ - __IM uint32_t OUT_DSCR_STATE_CH : 2; /*!< reserved */ - __IM uint32_t OUT_STATE_CH : 3; /*!< reserved */ - uint32_t : 9; - } bit; - } OUT_STATE_CH0; - - union { - __IOM uint32_t reg; /*!< Outlink descriptor address when EOF occurs of Tx channel 0 */ - - struct { - __IM uint32_t OUT_EOF_DES_ADDR_CH : 32; /*!< This register stores the address of the outlink descriptor when - the EOF bit in this descriptor is 1. */ - } bit; - } OUT_EOF_DES_ADDR_CH0; - - union { - __IOM uint32_t reg; /*!< The last outlink descriptor address when EOF occurs of Tx channel - 0 */ - - struct { - __IM uint32_t OUT_EOF_BFR_DES_ADDR_CH : 32;/*!< This register stores the address of the outlink descriptor before - the last outlink descriptor. */ - } bit; - } OUT_EOF_BFR_DES_ADDR_CH0; - - union { - __IOM uint32_t reg; /*!< Current inlink descriptor address of Tx channel 0 */ - - struct { - __IM uint32_t OUTLINK_DSCR_CH : 32; /*!< The address of the current outlink descriptor y. */ - } bit; - } OUT_DSCR_CH0; - - union { - __IOM uint32_t reg; /*!< The last inlink descriptor address of Tx channel 0 */ - - struct { - __IM uint32_t OUTLINK_DSCR_BF0_CH : 32; /*!< The address of the last outlink descriptor y-1. */ - } bit; - } OUT_DSCR_BF0_CH0; - - union { - __IOM uint32_t reg; /*!< The second-to-last inlink descriptor address of Tx channel 0 */ - - struct { - __IM uint32_t OUTLINK_DSCR_BF1_CH : 32; /*!< The address of the second-to-last inlink descriptor x-2. */ - } bit; - } OUT_DSCR_BF1_CH0; - - union { - __IOM uint32_t reg; /*!< Priority register of Tx channel 0. */ - - struct { - __IOM uint32_t TX_PRI_CH : 4; /*!< The priority of Tx channel 0. The larger of the value the higher - of the priority. */ - uint32_t : 28; - } bit; - } OUT_PRI_CH0; - - union { - __IOM uint32_t reg; /*!< Peripheral selection of Tx channel 0 */ - - struct { - __IOM uint32_t PERI_OUT_SEL_CH : 6; /*!< This register is used to select peripheral for Tx channel 0. - I3C. 1: Dummy. 2: UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: - Dummy. 7: Dummy. 8: ADC_DAC. 9: Dummy. 10: RMT,11~15: Dummy */ - uint32_t : 26; - } bit; - } OUT_PERI_SEL_CH0; - __IM uint32_t RESERVED5[110]; - - union { - __IOM uint32_t reg; /*!< This register is used to config ch0 crc initial data(max 32 - bit) */ - - struct { - __IOM uint32_t OUT_CRC_INIT_DATA_CH : 32; /*!< This register is used to config ch0 of tx crc initial value */ - } bit; - } OUT_CRC_INIT_DATA_CH0; - - union { - __IOM uint32_t reg; /*!< This register is used to confiig tx ch0 crc result width,2'b00 - mean crc_width <=8bit,2'b01 8 reg_vdisp+reg_vsync+reg_vbank */ - uint32_t : 4; - __IOM uint32_t VDISP : 12; /*!< this field configures the length of valid line (by line) for - dpi output */ - uint32_t : 4; - } bit; - } DPI_V_CFG0; - - union { - __IOM uint32_t reg; /*!< dsi bridge dpi v config register 1 */ - - struct { - __IOM uint32_t VBANK : 12; /*!< this field configures the length between vsync and valid line - (by line) for dpi output */ - uint32_t : 4; - __IOM uint32_t VSYNC : 12; /*!< this field configures the length of vsync (by line) for dpi - output */ - uint32_t : 4; - } bit; - } DPI_V_CFG1; - - union { - __IOM uint32_t reg; /*!< dsi bridge dpi h config register 0 */ - - struct { - __IOM uint32_t HTOTAL : 12; /*!< this field configures the total length of one line (by pixel - num) for dpi output, must meet: reg_htotal > reg_hdisp+reg_hsync+reg_hban - */ - uint32_t : 4; - __IOM uint32_t HDISP : 12; /*!< this field configures the length of valid pixel data (by pixel - num) for dpi output */ - uint32_t : 4; - } bit; - } DPI_H_CFG0; - - union { - __IOM uint32_t reg; /*!< dsi bridge dpi h config register 1 */ - - struct { - __IOM uint32_t HBANK : 12; /*!< this field configures the length between hsync and pixel data - valid (by pixel num) for dpi output */ - uint32_t : 4; - __IOM uint32_t HSYNC : 12; /*!< this field configures the length of hsync (by pixel num) for - dpi output */ - uint32_t : 4; - } bit; - } DPI_H_CFG1; - - union { - __IOM uint32_t reg; /*!< dsi_bridge dpi misc config register */ - - struct { - __IOM uint32_t DPI_EN : 1; /*!< this bit configures enable of dpi output, 0: disable, 1: enable */ - uint32_t : 3; - __IOM uint32_t FIFO_UNDERRUN_DISCARD_VCNT : 12;/*!< this field configures the underrun interrupt musk, when underrun - occurs and line cnt is less then this field */ - uint32_t : 16; - } bit; - } DPI_MISC_CONFIG; - - union { - __IOM uint32_t reg; /*!< dsi_bridge dpi config update register */ - - struct { - __OM uint32_t DPI_CONFIG_UPDATE : 1; /*!< write 1 to this bit to update dpi config register MIPI_DSI_BRG_DPI_* */ - uint32_t : 31; - } bit; - } DPI_CONFIG_UPDATE; - __IM uint32_t RESERVED1[2]; - - union { - __IOM uint32_t reg; /*!< dsi_bridge interrupt enable register */ - - struct { - __IOM uint32_t UNDERRUN_INT_ENA : 1; /*!< write 1 to enables dpi_underrun_int_st field of MIPI_DSI_BRG_INT_ST_REG - controlled by dpi_underrun interrupt signal */ - uint32_t : 31; - } bit; - } INT_ENA; - - union { - __IOM uint32_t reg; /*!< dsi_bridge interrupt clear register */ - - struct { - __OM uint32_t UNDERRUN_INT_CLR : 1; /*!< write 1 to this bit to clear dpi_underrun_int_raw field of MIPI_DSI_BRG_INT_RA - _REG */ - uint32_t : 31; - } bit; - } INT_CLR; - - union { - __IOM uint32_t reg; /*!< dsi_bridge raw interrupt register */ - - struct { - __IOM uint32_t UNDERRUN_INT_RAW : 1; /*!< the raw interrupt status of dpi_underrun */ - uint32_t : 31; - } bit; - } INT_RAW; - - union { - __IOM uint32_t reg; /*!< dsi_bridge masked interrupt register */ - - struct { - __IM uint32_t UNDERRUN_INT_ST : 1; /*!< the masked interrupt status of dpi_underrun */ - uint32_t : 31; - } bit; - } INT_ST; - - union { - __IOM uint32_t reg; /*!< dsi_bridge host bist control register */ - - struct { - __IM uint32_t BISTOK : 1; /*!< bistok */ - __IOM uint32_t BISTON : 1; /*!< biston */ - uint32_t : 30; - } bit; - } HOST_BIST_CTL; - - union { - __IOM uint32_t reg; /*!< dsi_bridge host trigger reverse control register */ - - struct { - __IOM uint32_t TX_TRIGGER_REV_EN : 1; /*!< tx_trigger reverse. 0: disable, 1: enable */ - __IOM uint32_t RX_TRIGGER_REV_EN : 1; /*!< rx_trigger reverse. 0: disable, 1: enable */ - uint32_t : 30; - } bit; - } HOST_TRIGGER_REV; - - union { - __IOM uint32_t reg; /*!< dsi_bridge block raw number control register */ - - struct { - __IOM uint32_t BLK_RAW_NUM_TOTAL : 22; /*!< this field configures number of total block pix bits/64 */ - uint32_t : 9; - __OM uint32_t BLK_RAW_NUM_TOTAL_SET : 1; /*!< write 1 to reload reg_blk_raw_num_total to internal cnt */ - } bit; - } BLK_RAW_NUM_CFG; - - union { - __IOM uint32_t reg; /*!< dsi_bridge dam frame interval control register */ - - struct { - __IOM uint32_t DMA_FRAME_SLOT : 10; /*!< this field configures the max frame_slot_cnt */ - __IOM uint32_t DMA_FRAME_INTERVAL : 18; /*!< this field configures the max frame_interval_cnt, frame_interval_cnt - increased by 1 when frame_slot_cnt if full */ - __IOM uint32_t DMA_MULTIBLK_EN : 1; /*!< this bit configures enable multi-blk transfer, 0: disable, 1: - enable */ - __IOM uint32_t EN : 1; /*!< this bit configures enable interval between frame transfer, - 0: disable, 1: enable */ - uint32_t : 2; - } bit; - } DMA_FRAME_INTERVAL; - - union { - __IOM uint32_t reg; /*!< dsi_bridge mem aux control register */ - - struct { - __IOM uint32_t DSI_MEM_AUX_CTRL : 14; /*!< this field configures dsi_bridge fifo memory aux ctrl */ - uint32_t : 18; - } bit; - } MEM_AUX_CTRL; - - union { - __IOM uint32_t reg; /*!< dsi_bridge rdn eco cs register */ - - struct { - __IOM uint32_t RDN_ECO_EN : 1; /*!< rdn_eco_en */ - __IM uint32_t RDN_ECO_RESULT : 1; /*!< rdn_eco_result */ - uint32_t : 30; - } bit; - } RDN_ECO_CS; - - union { - __IOM uint32_t reg; /*!< dsi_bridge rdn eco all low register */ - - struct { - __IOM uint32_t RDN_ECO_LOW : 32; /*!< rdn_eco_low */ - } bit; - } RDN_ECO_LOW; - - union { - __IOM uint32_t reg; /*!< dsi_bridge rdn eco all high register */ - - struct { - __IOM uint32_t RDN_ECO_HIGH : 32; /*!< rdn_eco_high */ - } bit; - } RDN_ECO_HIGH; - - union { - __IOM uint32_t reg; /*!< dsi_bridge host control register */ - - struct { - __IOM uint32_t DSI_CFG_REF_CLK_EN : 1; /*!< this bit configures the clk enable refclk and cfg_clk of dsi_host. - 0: disable, 1: enable */ - uint32_t : 31; - } bit; - } HOST_CTRL; - - union { - __IOM uint32_t reg; /*!< dsi_bridge mem force on control register */ - - struct { - __IOM uint32_t DSI_BRIDGE_MEM_CLK_FORCE_ON : 1;/*!< this bit configures the clock force on of dsi_bridge fifo memory. - 0: disable, 1: force on */ - __IOM uint32_t DSI_MEM_CLK_FORCE_ON : 1; /*!< this bit configures the clock force on of dpi fifo memory. 0: - disable, 1: force on */ - uint32_t : 30; - } bit; - } MEM_CLK_CTRL; - - union { - __IOM uint32_t reg; /*!< dsi_bridge dma flow controller register */ - - struct { - __IOM uint32_t DSI_DMA_FLOW_CONTROLLER : 1;/*!< this bit configures the flow controller, 0: dmac as flow controller, - 1:dsi_bridge as flow controller */ - uint32_t : 3; - __IOM uint32_t DMA_FLOW_MULTIBLK_NUM : 4; /*!< this field configures the num of blocks when multi-blk is enable - and dmac as flow controller */ - uint32_t : 24; - } bit; - } DMA_FLOW_CTRL; - - union { - __IOM uint32_t reg; /*!< dsi_bridge buffer empty threshold register */ - - struct { - __IOM uint32_t DSI_RAW_BUF_ALMOST_EMPTY_THRD : 11;/*!< this field configures the fifo almost empty threshold, is valid - only when dmac as flow controller */ - uint32_t : 21; - } bit; - } RAW_BUF_ALMOST_EMPTY_THRD; - - union { - __IOM uint32_t reg; /*!< dsi_bridge yuv format config register */ - - struct { - __IOM uint32_t PROTOCAL : 1; /*!< this bit configures yuv protoocl, 0: bt.601, 1: bt.709 */ - __IOM uint32_t YUV_PIX_ENDIAN : 1; /*!< this bit configures yuv pixel endian, 0: y0u0y1v1y2u2y3v3, 1: - y3u3y2v2y1u1y0v0 */ - __IOM uint32_t YUV422_FORMAT : 2; /*!< this field configures yuv422 store format, 0: yuyv, 1: yvyu, - 2: uyvy, 3: vyuy */ - uint32_t : 28; - } bit; - } YUV_CFG; - - union { - __IOM uint32_t reg; /*!< dsi phy lp_loopback test ctrl */ - - struct { - __IOM uint32_t PHY_LP_TXDATAESC_1 : 8; /*!< txdataesc_1 ctrl when enable dsi phy lp_loopback_test */ - __IOM uint32_t PHY_LP_TXREQUESTESC_1 : 1; /*!< txrequestesc_1 ctrl when enable dsi phy lp_loopback_test */ - __IOM uint32_t PHY_LP_TXVALIDESC_1 : 1; /*!< txvalidesc_1 ctrl when enable dsi phy lp_loopback_test */ - __IOM uint32_t PHY_LP_TXLPDTESC_1 : 1; /*!< txlpdtesc_1 ctrl when enable dsi phy lp_loopback_test */ - __IOM uint32_t PHY_LP_BASEDIR_1 : 1; /*!< basedir_1 ctrl when enable dsi phy lp_loopback_test */ - uint32_t : 4; - __IOM uint32_t PHY_LP_TXDATAESC_0 : 8; /*!< txdataesc_0 ctrl when enable dsi phy lp_loopback_test */ - __IOM uint32_t PHY_LP_TXREQUESTESC_0 : 1; /*!< txrequestesc_0 ctrl when enable dsi phy lp_loopback_test */ - __IOM uint32_t PHY_LP_TXVALIDESC_0 : 1; /*!< txvalidesc_0 ctrl when enable dsi phy lp_loopback_test */ - __IOM uint32_t PHY_LP_TXLPDTESC_0 : 1; /*!< txlpdtesc_0 ctrl when enable dsi phy lp_loopback_test */ - __IOM uint32_t PHY_LP_BASEDIR_0 : 1; /*!< basedir_0 ctrl when enable dsi phy lp_loopback_test */ - __OM uint32_t PHY_LP_LOOPBACK_CHECK : 1; /*!< dsi phy lp_loopback test start check */ - __IM uint32_t PHY_LP_LOOPBACK_CHECK_DONE : 1;/*!< dsi phy lp_loopback test check done */ - __IOM uint32_t PHY_LP_LOOPBACK_EN : 1; /*!< dsi phy lp_loopback ctrl en */ - __IM uint32_t PHY_LP_LOOPBACK_OK : 1; /*!< result of dsi phy lp_loopback test */ - } bit; - } PHY_LP_LOOPBACK_CTRL; - - union { - __IOM uint32_t reg; /*!< dsi phy hp_loopback test ctrl */ - - struct { - __IOM uint32_t PHY_HS_TXDATAHS_1 : 8; /*!< txdatahs_1 ctrl when enable dsi phy hs_loopback_test */ - __IOM uint32_t PHY_HS_TXREQUESTDATAHS_1 : 1;/*!< txrequestdatahs_1 ctrl when enable dsi phy hs_loopback_test */ - __IOM uint32_t PHY_HS_BASEDIR_1 : 1; /*!< basedir_1 ctrl when enable dsi phy hs_loopback_test */ - uint32_t : 6; - __IOM uint32_t PHY_HS_TXDATAHS_0 : 8; /*!< txdatahs_0 ctrl when enable dsi phy hs_loopback_test */ - __IOM uint32_t PHY_HS_TXREQUESTDATAHS_0 : 1;/*!< txrequestdatahs_0 ctrl when enable dsi phy hs_loopback_test */ - __IOM uint32_t PHY_HS_BASEDIR_0 : 1; /*!< basedir_0 ctrl when enable dsi phy hs_loopback_test */ - uint32_t : 1; - __IOM uint32_t PHY_HS_TXREQUESTHSCLK : 1; /*!< txrequesthsclk when enable dsi phy hs_loopback_test */ - __OM uint32_t PHY_HS_LOOPBACK_CHECK : 1; /*!< dsi phy hs_loopback test start check */ - __IM uint32_t PHY_HS_LOOPBACK_CHECK_DONE : 1;/*!< dsi phy hs_loopback test check done */ - __IOM uint32_t PHY_HS_LOOPBACK_EN : 1; /*!< dsi phy hs_loopback ctrl en */ - __IM uint32_t PHY_HS_LOOPBACK_OK : 1; /*!< result of dsi phy hs_loopback test */ - } bit; - } PHY_HS_LOOPBACK_CTRL; - - union { - __IOM uint32_t reg; /*!< loopback test cnt */ - - struct { - __IOM uint32_t PHY_HS_CHECK_CNT_TH : 8; /*!< hs_loopback test check cnt */ - uint32_t : 8; - __IOM uint32_t PHY_LP_CHECK_CNT_TH : 8; /*!< lp_loopback test check cnt */ - uint32_t : 8; - } bit; - } PHY_LOOPBACK_CNT; -} MIPI_DSI_BRIDGE_Type; /*!< Size = 160 (0xa0) */ - - - -/* =========================================================================================================================== */ -/* ================ MIPI_DSI_HOST ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief MIPI Display Interface Host (MIPI_DSI_HOST) - */ - -typedef struct { /*!< MIPI_DSI_HOST Structure */ - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t VERSION : 32; /*!< NA */ - } bit; - } VERSION; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t SHUTDOWNZ : 1; /*!< NA */ - uint32_t : 31; - } bit; - } PWR_UP; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t TX_ESC_CLK_DIVISION : 8; /*!< NA */ - __IOM uint32_t TO_CLK_DIVISION : 8; /*!< NA */ - uint32_t : 16; - } bit; - } CLKMGR_CFG; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t DPI_VCID : 2; /*!< NA */ - uint32_t : 30; - } bit; - } DPI_VCID; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t DPI_COLOR_CODING : 4; /*!< NA */ - uint32_t : 4; - __IOM uint32_t LOOSELY18_EN : 1; /*!< NA */ - uint32_t : 23; - } bit; - } DPI_COLOR_CODING; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t DATAEN_ACTIVE_LOW : 1; /*!< NA */ - __IOM uint32_t VSYNC_ACTIVE_LOW : 1; /*!< NA */ - __IOM uint32_t HSYNC_ACTIVE_LOW : 1; /*!< NA */ - __IOM uint32_t SHUTD_ACTIVE_LOW : 1; /*!< NA */ - __IOM uint32_t COLORM_ACTIVE_LOW : 1; /*!< NA */ - uint32_t : 27; - } bit; - } DPI_CFG_POL; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t INVACT_LPCMD_TIME : 8; /*!< NA */ - uint32_t : 8; - __IOM uint32_t OUTVACT_LPCMD_TIME : 8; /*!< NA */ - uint32_t : 8; - } bit; - } DPI_LP_CMD_TIM; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t DBI_VCID : 2; /*!< NA */ - uint32_t : 30; - } bit; - } DBI_VCID; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t IN_DBI_CONF : 4; /*!< NA */ - uint32_t : 4; - __IOM uint32_t OUT_DBI_CONF : 4; /*!< NA */ - uint32_t : 4; - __IOM uint32_t LUT_SIZE_CONF : 2; /*!< NA */ - uint32_t : 14; - } bit; - } DBI_CFG; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t PARTITIONING_EN : 1; /*!< NA */ - uint32_t : 31; - } bit; - } DBI_PARTITIONING_EN; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t WR_CMD_SIZE : 16; /*!< NA */ - __IOM uint32_t ALLOWED_CMD_SIZE : 16; /*!< NA */ - } bit; - } DBI_CMDSIZE; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t EOTP_TX_EN : 1; /*!< NA */ - __IOM uint32_t EOTP_RX_EN : 1; /*!< NA */ - __IOM uint32_t BTA_EN : 1; /*!< NA */ - __IOM uint32_t ECC_RX_EN : 1; /*!< NA */ - __IOM uint32_t CRC_RX_EN : 1; /*!< NA */ - __IOM uint32_t EOTP_TX_LP_EN : 1; /*!< NA */ - uint32_t : 26; - } bit; - } PCKHDL_CFG; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t RX : 2; /*!< NA */ - uint32_t : 6; - __IOM uint32_t TEAR_AUTO : 2; /*!< NA */ - uint32_t : 6; - __IOM uint32_t TX_AUTO : 2; /*!< NA */ - uint32_t : 14; - } bit; - } GEN_VCID; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t CMD_VIDEO_MODE : 1; /*!< NA */ - uint32_t : 31; - } bit; - } MODE_CFG; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t VID_MODE_TYPE : 2; /*!< NA */ - uint32_t : 6; - __IOM uint32_t LP_VSA_EN : 1; /*!< NA */ - __IOM uint32_t LP_VBP_EN : 1; /*!< NA */ - __IOM uint32_t LP_VFP_EN : 1; /*!< NA */ - __IOM uint32_t LP_VACT_EN : 1; /*!< NA */ - __IOM uint32_t LP_HBP_EN : 1; /*!< NA */ - __IOM uint32_t LP_HFP_EN : 1; /*!< NA */ - __IOM uint32_t FRAME_BTA_ACK_EN : 1; /*!< NA */ - __IOM uint32_t LP_CMD_EN : 1; /*!< NA */ - __IOM uint32_t VPG_EN : 1; /*!< NA */ - uint32_t : 3; - __IOM uint32_t VPG_MODE : 1; /*!< NA */ - uint32_t : 3; - __IOM uint32_t VPG_ORIENTATION : 1; /*!< NA */ - uint32_t : 7; - } bit; - } VID_MODE_CFG; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t VID_PKT_SIZE : 14; /*!< NA */ - uint32_t : 18; - } bit; - } VID_PKT_SIZE; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t VID_NUM_CHUNKS : 13; /*!< NA */ - uint32_t : 19; - } bit; - } VID_NUM_CHUNKS; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t VID_NULL_SIZE : 13; /*!< NA */ - uint32_t : 19; - } bit; - } VID_NULL_SIZE; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t VID_HSA_TIME : 12; /*!< NA */ - uint32_t : 20; - } bit; - } VID_HSA_TIME; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t VID_HBP_TIME : 12; /*!< NA */ - uint32_t : 20; - } bit; - } VID_HBP_TIME; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t VID_HLINE_TIME : 15; /*!< NA */ - uint32_t : 17; - } bit; - } VID_HLINE_TIME; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t VSA_LINES : 10; /*!< NA */ - uint32_t : 22; - } bit; - } VID_VSA_LINES; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t VBP_LINES : 10; /*!< NA */ - uint32_t : 22; - } bit; - } VID_VBP_LINES; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t VFP_LINES : 10; /*!< NA */ - uint32_t : 22; - } bit; - } VID_VFP_LINES; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t V_ACTIVE_LINES : 14; /*!< NA */ - uint32_t : 18; - } bit; - } VID_VACTIVE_LINES; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t EDPI_ALLOWED_CMD_SIZE : 16;/*!< NA */ - uint32_t : 16; - } bit; - } EDPI_CMD_SIZE; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t TEAR_FX_EN : 1; /*!< NA */ - __IOM uint32_t ACK_RQST_EN : 1; /*!< NA */ - uint32_t : 6; - __IOM uint32_t GEN_SW_0P_TX : 1; /*!< NA */ - __IOM uint32_t GEN_SW_1P_TX : 1; /*!< NA */ - __IOM uint32_t GEN_SW_2P_TX : 1; /*!< NA */ - __IOM uint32_t GEN_SR_0P_TX : 1; /*!< NA */ - __IOM uint32_t GEN_SR_1P_TX : 1; /*!< NA */ - __IOM uint32_t GEN_SR_2P_TX : 1; /*!< NA */ - __IOM uint32_t GEN_LW_TX : 1; /*!< NA */ - uint32_t : 1; - __IOM uint32_t DCS_SW_0P_TX : 1; /*!< NA */ - __IOM uint32_t DCS_SW_1P_TX : 1; /*!< NA */ - __IOM uint32_t DCS_SR_0P_TX : 1; /*!< NA */ - __IOM uint32_t DCS_LW_TX : 1; /*!< NA */ - uint32_t : 4; - __IOM uint32_t MAX_RD_PKT_SIZE : 1; /*!< NA */ - uint32_t : 7; - } bit; - } CMD_MODE_CFG; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t GEN_DT : 6; /*!< NA */ - __IOM uint32_t GEN_VC : 2; /*!< NA */ - __IOM uint32_t GEN_WC_LSBYTE : 8; /*!< NA */ - __IOM uint32_t GEN_WC_MSBYTE : 8; /*!< NA */ - uint32_t : 8; - } bit; - } GEN_HDR; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t GEN_PLD_B1 : 8; /*!< NA */ - __IOM uint32_t GEN_PLD_B2 : 8; /*!< NA */ - __IOM uint32_t GEN_PLD_B3 : 8; /*!< NA */ - __IOM uint32_t GEN_PLD_B4 : 8; /*!< NA */ - } bit; - } GEN_PLD_DATA; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t GEN_CMD_EMPTY : 1; /*!< NA */ - __IM uint32_t GEN_CMD_FULL : 1; /*!< NA */ - __IM uint32_t GEN_PLD_W_EMPTY : 1; /*!< NA */ - __IM uint32_t GEN_PLD_W_FULL : 1; /*!< NA */ - __IM uint32_t GEN_PLD_R_EMPTY : 1; /*!< NA */ - __IM uint32_t GEN_PLD_R_FULL : 1; /*!< NA */ - __IM uint32_t GEN_RD_CMD_BUSY : 1; /*!< NA */ - uint32_t : 9; - __IM uint32_t GEN_BUFF_CMD_EMPTY : 1; /*!< NA */ - __IM uint32_t GEN_BUFF_CMD_FULL : 1; /*!< NA */ - __IM uint32_t GEN_BUFF_PLD_EMPTY : 1; /*!< NA */ - __IM uint32_t GEN_BUFF_PLD_FULL : 1; /*!< NA */ - uint32_t : 12; - } bit; - } CMD_PKT_STATUS; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t LPRX_TO_CNT : 16; /*!< NA */ - __IOM uint32_t HSTX_TO_CNT : 16; /*!< NA */ - } bit; - } TO_CNT_CFG; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t HS_RD_TO_CNT : 16; /*!< NA */ - uint32_t : 16; - } bit; - } HS_RD_TO_CNT; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t LP_RD_TO_CNT : 16; /*!< NA */ - uint32_t : 16; - } bit; - } LP_RD_TO_CNT; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t HS_WR_TO_CNT : 16; /*!< NA */ - uint32_t : 16; - } bit; - } HS_WR_TO_CNT; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t LP_WR_TO_CNT : 16; /*!< NA */ - uint32_t : 16; - } bit; - } LP_WR_TO_CNT; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t BTA_TO_CNT : 16; /*!< NA */ - uint32_t : 16; - } bit; - } BTA_TO_CNT; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t MODE_3D : 2; /*!< NA */ - __IOM uint32_t FORMAT_3D : 2; /*!< NA */ - __IOM uint32_t SECOND_VSYNC : 1; /*!< NA */ - __IOM uint32_t RIGHT_FIRST : 1; /*!< NA */ - uint32_t : 10; - __IOM uint32_t SEND_3D_CFG : 1; /*!< NA */ - uint32_t : 15; - } bit; - } SDF_3D; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t PHY_TXREQUESTCLKHS : 1; /*!< NA */ - __IOM uint32_t AUTO_CLKLANE_CTRL : 1; /*!< NA */ - uint32_t : 30; - } bit; - } LPCLK_CTRL; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t PHY_CLKLP2HS_TIME : 10; /*!< NA */ - uint32_t : 6; - __IOM uint32_t PHY_CLKHS2LP_TIME : 10; /*!< NA */ - uint32_t : 6; - } bit; - } PHY_TMR_LPCLK_CFG; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t PHY_LP2HS_TIME : 10; /*!< NA */ - uint32_t : 6; - __IOM uint32_t PHY_HS2LP_TIME : 10; /*!< NA */ - uint32_t : 6; - } bit; - } PHY_TMR_CFG; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t PHY_SHUTDOWNZ : 1; /*!< NA */ - __IOM uint32_t PHY_RSTZ : 1; /*!< NA */ - __IOM uint32_t PHY_ENABLECLK : 1; /*!< NA */ - __IOM uint32_t PHY_FORCEPLL : 1; /*!< NA */ - uint32_t : 28; - } bit; - } PHY_RSTZ; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t N_LANES : 2; /*!< NA */ - uint32_t : 6; - __IOM uint32_t PHY_STOP_WAIT_TIME : 8; /*!< NA */ - uint32_t : 16; - } bit; - } PHY_IF_CFG; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t PHY_TXREQULPSCLK : 1; /*!< NA */ - __IOM uint32_t PHY_TXEXITULPSCLK : 1; /*!< NA */ - __IOM uint32_t PHY_TXREQULPSLAN : 1; /*!< NA */ - __IOM uint32_t PHY_TXEXITULPSLAN : 1; /*!< NA */ - uint32_t : 28; - } bit; - } PHY_ULPS_CTRL; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t PHY_TX_TRIGGERS : 4; /*!< NA */ - uint32_t : 28; - } bit; - } PHY_TX_TRIGGERS; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t PHY_LOCK : 1; /*!< NA */ - __IM uint32_t PHY_DIRECTION : 1; /*!< NA */ - __IM uint32_t PHY_STOPSTATECLKLANE : 1; /*!< NA */ - __IM uint32_t PHY_ULPSACTIVENOTCLK : 1; /*!< NA */ - __IM uint32_t PHY_STOPSTATE0LANE : 1; /*!< NA */ - __IM uint32_t PHY_ULPSACTIVENOT0LANE : 1;/*!< NA */ - __IM uint32_t PHY_RXULPSESC0LANE : 1; /*!< NA */ - __IM uint32_t PHY_STOPSTATE1LANE : 1; /*!< NA */ - __IM uint32_t PHY_ULPSACTIVENOT1LANE : 1;/*!< NA */ - uint32_t : 23; - } bit; - } PHY_STATUS; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t PHY_TESTCLR : 1; /*!< NA */ - __IOM uint32_t PHY_TESTCLK : 1; /*!< NA */ - uint32_t : 30; - } bit; - } PHY_TST_CTRL0; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t PHY_TESTDIN : 8; /*!< NA */ - __IM uint32_t PHT_TESTDOUT : 8; /*!< NA */ - __IOM uint32_t PHY_TESTEN : 1; /*!< NA */ - uint32_t : 15; - } bit; - } PHY_TST_CTRL1; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t ACK_WITH_ERR_0 : 1; /*!< NA */ - __IM uint32_t ACK_WITH_ERR_1 : 1; /*!< NA */ - __IM uint32_t ACK_WITH_ERR_2 : 1; /*!< NA */ - __IM uint32_t ACK_WITH_ERR_3 : 1; /*!< NA */ - __IM uint32_t ACK_WITH_ERR_4 : 1; /*!< NA */ - __IM uint32_t ACK_WITH_ERR_5 : 1; /*!< NA */ - __IM uint32_t ACK_WITH_ERR_6 : 1; /*!< NA */ - __IM uint32_t ACK_WITH_ERR_7 : 1; /*!< NA */ - __IM uint32_t ACK_WITH_ERR_8 : 1; /*!< NA */ - __IM uint32_t ACK_WITH_ERR_9 : 1; /*!< NA */ - __IM uint32_t ACK_WITH_ERR_10 : 1; /*!< NA */ - __IM uint32_t ACK_WITH_ERR_11 : 1; /*!< NA */ - __IM uint32_t ACK_WITH_ERR_12 : 1; /*!< NA */ - __IM uint32_t ACK_WITH_ERR_13 : 1; /*!< NA */ - __IM uint32_t ACK_WITH_ERR_14 : 1; /*!< NA */ - __IM uint32_t ACK_WITH_ERR_15 : 1; /*!< NA */ - __IM uint32_t DPHY_ERRORS_0 : 1; /*!< NA */ - __IM uint32_t DPHY_ERRORS_1 : 1; /*!< NA */ - __IM uint32_t DPHY_ERRORS_2 : 1; /*!< NA */ - __IM uint32_t DPHY_ERRORS_3 : 1; /*!< NA */ - __IM uint32_t DPHY_ERRORS_4 : 1; /*!< NA */ - uint32_t : 11; - } bit; - } INT_ST0; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t TO_HS_TX : 1; /*!< NA */ - __IM uint32_t TO_LP_RX : 1; /*!< NA */ - __IM uint32_t ECC_SINGLE_ERR : 1; /*!< NA */ - __IM uint32_t ECC_MILTI_ERR : 1; /*!< NA */ - __IM uint32_t CRC_ERR : 1; /*!< NA */ - __IM uint32_t PKT_SIZE_ERR : 1; /*!< NA */ - __IM uint32_t EOPT_ERR : 1; /*!< NA */ - __IM uint32_t DPI_PLD_WR_ERR : 1; /*!< NA */ - __IM uint32_t GEN_CMD_WR_ERR : 1; /*!< NA */ - __IM uint32_t GEN_PLD_WR_ERR : 1; /*!< NA */ - __IM uint32_t GEN_PLD_SEND_ERR : 1; /*!< NA */ - __IM uint32_t GEN_PLD_RD_ERR : 1; /*!< NA */ - __IM uint32_t GEN_PLD_RECEV_ERR : 1; /*!< NA */ - uint32_t : 6; - __IM uint32_t DPI_BUFF_PLD_UNDER : 1; /*!< NA */ - uint32_t : 12; - } bit; - } INT_ST1; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t MASK_ACK_WITH_ERR_0 : 1; /*!< NA */ - __IOM uint32_t MASK_ACK_WITH_ERR_1 : 1; /*!< NA */ - __IOM uint32_t MASK_ACK_WITH_ERR_2 : 1; /*!< NA */ - __IOM uint32_t MASK_ACK_WITH_ERR_3 : 1; /*!< NA */ - __IOM uint32_t MASK_ACK_WITH_ERR_4 : 1; /*!< NA */ - __IOM uint32_t MASK_ACK_WITH_ERR_5 : 1; /*!< NA */ - __IOM uint32_t MASK_ACK_WITH_ERR_6 : 1; /*!< NA */ - __IOM uint32_t MASK_ACK_WITH_ERR_7 : 1; /*!< NA */ - __IOM uint32_t MASK_ACK_WITH_ERR_8 : 1; /*!< NA */ - __IOM uint32_t MASK_ACK_WITH_ERR_9 : 1; /*!< NA */ - __IOM uint32_t MASK_ACK_WITH_ERR_10 : 1; /*!< NA */ - __IOM uint32_t MASK_ACK_WITH_ERR_11 : 1; /*!< NA */ - __IOM uint32_t MASK_ACK_WITH_ERR_12 : 1; /*!< NA */ - __IOM uint32_t MASK_ACK_WITH_ERR_13 : 1; /*!< NA */ - __IOM uint32_t MASK_ACK_WITH_ERR_14 : 1; /*!< NA */ - __IOM uint32_t MASK_ACK_WITH_ERR_15 : 1; /*!< NA */ - __IOM uint32_t MASK_DPHY_ERRORS_0 : 1; /*!< NA */ - __IOM uint32_t MASK_DPHY_ERRORS_1 : 1; /*!< NA */ - __IOM uint32_t MASK_DPHY_ERRORS_2 : 1; /*!< NA */ - __IOM uint32_t MASK_DPHY_ERRORS_3 : 1; /*!< NA */ - __IOM uint32_t MASK_DPHY_ERRORS_4 : 1; /*!< NA */ - uint32_t : 11; - } bit; - } INT_MSK0; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t MASK_TO_HS_TX : 1; /*!< NA */ - __IOM uint32_t MASK_TO_LP_RX : 1; /*!< NA */ - __IOM uint32_t MASK_ECC_SINGLE_ERR : 1; /*!< NA */ - __IOM uint32_t MASK_ECC_MILTI_ERR : 1; /*!< NA */ - __IOM uint32_t MASK_CRC_ERR : 1; /*!< NA */ - __IOM uint32_t MASK_PKT_SIZE_ERR : 1; /*!< NA */ - __IOM uint32_t MASK_EOPT_ERR : 1; /*!< NA */ - __IOM uint32_t MASK_DPI_PLD_WR_ERR : 1; /*!< NA */ - __IOM uint32_t MASK_GEN_CMD_WR_ERR : 1; /*!< NA */ - __IOM uint32_t MASK_GEN_PLD_WR_ERR : 1; /*!< NA */ - __IOM uint32_t MASK_GEN_PLD_SEND_ERR : 1; /*!< NA */ - __IOM uint32_t MASK_GEN_PLD_RD_ERR : 1; /*!< NA */ - __IOM uint32_t MASK_GEN_PLD_RECEV_ERR : 1;/*!< NA */ - uint32_t : 6; - __IOM uint32_t MASK_DPI_BUFF_PLD_UNDER : 1;/*!< NA */ - uint32_t : 12; - } bit; - } INT_MSK1; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t TXSKEWCALHS : 1; /*!< NA */ - uint32_t : 31; - } bit; - } PHY_CAL; - __IM uint32_t RESERVED[2]; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t FORCE_ACK_WITH_ERR_0 : 1; /*!< NA */ - __IOM uint32_t FORCE_ACK_WITH_ERR_1 : 1; /*!< NA */ - __IOM uint32_t FORCE_ACK_WITH_ERR_2 : 1; /*!< NA */ - __IOM uint32_t FORCE_ACK_WITH_ERR_3 : 1; /*!< NA */ - __IOM uint32_t FORCE_ACK_WITH_ERR_4 : 1; /*!< NA */ - __IOM uint32_t FORCE_ACK_WITH_ERR_5 : 1; /*!< NA */ - __IOM uint32_t FORCE_ACK_WITH_ERR_6 : 1; /*!< NA */ - __IOM uint32_t FORCE_ACK_WITH_ERR_7 : 1; /*!< NA */ - __IOM uint32_t FORCE_ACK_WITH_ERR_8 : 1; /*!< NA */ - __IOM uint32_t FORCE_ACK_WITH_ERR_9 : 1; /*!< NA */ - __IOM uint32_t FORCE_ACK_WITH_ERR_10 : 1; /*!< NA */ - __IOM uint32_t FORCE_ACK_WITH_ERR_11 : 1; /*!< NA */ - __IOM uint32_t FORCE_ACK_WITH_ERR_12 : 1; /*!< NA */ - __IOM uint32_t FORCE_ACK_WITH_ERR_13 : 1; /*!< NA */ - __IOM uint32_t FORCE_ACK_WITH_ERR_14 : 1; /*!< NA */ - __IOM uint32_t FORCE_ACK_WITH_ERR_15 : 1; /*!< NA */ - __IOM uint32_t FORCE_DPHY_ERRORS_0 : 1; /*!< NA */ - __IOM uint32_t FORCE_DPHY_ERRORS_1 : 1; /*!< NA */ - __IOM uint32_t FORCE_DPHY_ERRORS_2 : 1; /*!< NA */ - __IOM uint32_t FORCE_DPHY_ERRORS_3 : 1; /*!< NA */ - __IOM uint32_t FORCE_DPHY_ERRORS_4 : 1; /*!< NA */ - uint32_t : 11; - } bit; - } INT_FORCE0; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t FORCE_TO_HS_TX : 1; /*!< NA */ - __IOM uint32_t FORCE_TO_LP_RX : 1; /*!< NA */ - __IOM uint32_t FORCE_ECC_SINGLE_ERR : 1; /*!< NA */ - __IOM uint32_t FORCE_ECC_MILTI_ERR : 1; /*!< NA */ - __IOM uint32_t FORCE_CRC_ERR : 1; /*!< NA */ - __IOM uint32_t FORCE_PKT_SIZE_ERR : 1; /*!< NA */ - __IOM uint32_t FORCE_EOPT_ERR : 1; /*!< NA */ - __IOM uint32_t FORCE_DPI_PLD_WR_ERR : 1; /*!< NA */ - __IOM uint32_t FORCE_GEN_CMD_WR_ERR : 1; /*!< NA */ - __IOM uint32_t FORCE_GEN_PLD_WR_ERR : 1; /*!< NA */ - __IOM uint32_t FORCE_GEN_PLD_SEND_ERR : 1;/*!< NA */ - __IOM uint32_t FORCE_GEN_PLD_RD_ERR : 1; /*!< NA */ - __IOM uint32_t FORCE_GEN_PLD_RECEV_ERR : 1;/*!< NA */ - uint32_t : 6; - __IOM uint32_t FORCE_DPI_BUFF_PLD_UNDER : 1;/*!< NA */ - uint32_t : 12; - } bit; - } INT_FORCE1; - __IM uint32_t RESERVED1[4]; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t COMPRESSION_MODE : 1; /*!< NA */ - uint32_t : 7; - __IOM uint32_t COMPRESS_ALGO : 2; /*!< NA */ - uint32_t : 6; - __IOM uint32_t PPS_SEL : 2; /*!< NA */ - uint32_t : 14; - } bit; - } DSC_PARAMETER; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t MAX_RD_TIME : 15; /*!< NA */ - uint32_t : 17; - } bit; - } PHY_TMR_RD_CFG; - __IM uint32_t RESERVED2[2]; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t VID_SHADOW_EN : 1; /*!< NA */ - uint32_t : 7; - __IOM uint32_t VID_SHADOW_REQ : 1; /*!< NA */ - uint32_t : 7; - __IOM uint32_t VID_SHADOW_PIN_REQ : 1; /*!< NA */ - uint32_t : 15; - } bit; - } VID_SHADOW_CTRL; - __IM uint32_t RESERVED3[2]; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t DPI_VCID_ACT : 2; /*!< NA */ - uint32_t : 30; - } bit; - } DPI_VCID_ACT; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t DPI_COLOR_CODING_ACT : 4; /*!< NA */ - uint32_t : 4; - __IM uint32_t LOOSELY18_EN_ACT : 1; /*!< NA */ - uint32_t : 23; - } bit; - } DPI_COLOR_CODING_ACT; - __IM uint32_t RESERVED4; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t INVACT_LPCMD_TIME_ACT : 8; /*!< NA */ - uint32_t : 8; - __IM uint32_t OUTVACT_LPCMD_TIME_ACT : 8;/*!< NA */ - uint32_t : 8; - } bit; - } DPI_LP_CMD_TIM_ACT; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t HW_TEAR_EFFECT_ON : 1; /*!< NA */ - __IOM uint32_t HW_TEAR_EFFECT_GEN : 1; /*!< NA */ - uint32_t : 2; - __IOM uint32_t HW_SET_SCAN_LINE : 1; /*!< NA */ - uint32_t : 11; - __IOM uint32_t SCAN_LINE_PARAMETER : 16; /*!< NA */ - } bit; - } EDPI_TE_HW_CFG; - __IM uint32_t RESERVED5[6]; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t VID_MODE_TYPE_ACT : 2; /*!< NA */ - __IM uint32_t LP_VSA_EN_ACT : 1; /*!< NA */ - __IM uint32_t LP_VBP_EN_ACT : 1; /*!< NA */ - __IM uint32_t LP_VFP_EN_ACT : 1; /*!< NA */ - __IM uint32_t LP_VACT_EN_ACT : 1; /*!< NA */ - __IM uint32_t LP_HBP_EN_ACT : 1; /*!< NA */ - __IM uint32_t LP_HFP_EN_ACT : 1; /*!< NA */ - __IM uint32_t FRAME_BTA_ACK_EN_ACT : 1; /*!< NA */ - __IM uint32_t LP_CMD_EN_ACT : 1; /*!< NA */ - uint32_t : 22; - } bit; - } VID_MODE_CFG_ACT; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t VID_PKT_SIZE_ACT : 14; /*!< NA */ - uint32_t : 18; - } bit; - } VID_PKT_SIZE_ACT; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t VID_NUM_CHUNKS_ACT : 13; /*!< NA */ - uint32_t : 19; - } bit; - } VID_NUM_CHUNKS_ACT; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t VID_NULL_SIZE_ACT : 13; /*!< NA */ - uint32_t : 19; - } bit; - } VID_NULL_SIZE_ACT; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t VID_HSA_TIME_ACT : 12; /*!< NA */ - uint32_t : 20; - } bit; - } VID_HSA_TIME_ACT; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t VID_HBP_TIME_ACT : 12; /*!< NA */ - uint32_t : 20; - } bit; - } VID_HBP_TIME_ACT; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t VID_HLINE_TIME_ACT : 15; /*!< NA */ - uint32_t : 17; - } bit; - } VID_HLINE_TIME_ACT; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t VSA_LINES_ACT : 10; /*!< NA */ - uint32_t : 22; - } bit; - } VID_VSA_LINES_ACT; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t VBP_LINES_ACT : 10; /*!< NA */ - uint32_t : 22; - } bit; - } VID_VBP_LINES_ACT; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t VFP_LINES_ACT : 10; /*!< NA */ - uint32_t : 22; - } bit; - } VID_VFP_LINES_ACT; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t V_ACTIVE_LINES_ACT : 14; /*!< NA */ - uint32_t : 18; - } bit; - } VID_VACTIVE_LINES_ACT; - __IM uint32_t RESERVED6; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t DPI_CMD_W_EMPTY : 1; /*!< NA */ - __IM uint32_t DPI_CMD_W_FULL : 1; /*!< NA */ - __IM uint32_t DPI_PLD_W_EMPTY : 1; /*!< NA */ - __IM uint32_t DPI_PLD_W_FULL : 1; /*!< NA */ - uint32_t : 12; - __IM uint32_t DPI_BUFF_PLD_EMPTY : 1; /*!< NA */ - __IM uint32_t DPI_BUFF_PLD_FULL : 1; /*!< NA */ - uint32_t : 14; - } bit; - } VID_PKT_STATUS; - __IM uint32_t RESERVED7[9]; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t MODE_3D_ACT : 2; /*!< NA */ - __IM uint32_t FORMAT_3D_ACT : 2; /*!< NA */ - __IM uint32_t SECOND_VSYNC_ACT : 1; /*!< NA */ - __IM uint32_t RIGHT_FIRST_ACT : 1; /*!< NA */ - uint32_t : 10; - __IM uint32_t SEND_3D_CFG_ACT : 1; /*!< NA */ - uint32_t : 15; - } bit; - } SDF_3D_ACT; -} MIPI_DSI_HOST_Type; /*!< Size = 404 (0x194) */ - - - -/* =========================================================================================================================== */ -/* ================ ECC ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief ECC (ECC Hardware Accelerator) (ECC) - */ - -typedef struct { /*!< ECC Structure */ - __IM uint32_t RESERVED[3]; - - union { - __IOM uint32_t reg; /*!< ECC interrupt raw register, valid in level. */ - - struct { - __IM uint32_t CALC_DONE_INT_RAW : 1; /*!< The raw interrupt status bit for the ecc_calc_done_int interrupt */ - uint32_t : 31; - } bit; - } MULT_INT_RAW; - - union { - __IOM uint32_t reg; /*!< ECC interrupt status register. */ - - struct { - __IM uint32_t CALC_DONE_INT_ST : 1; /*!< The masked interrupt status bit for the ecc_calc_done_int interrupt */ - uint32_t : 31; - } bit; - } MULT_INT_ST; - - union { - __IOM uint32_t reg; /*!< ECC interrupt enable register. */ - - struct { - __IOM uint32_t CALC_DONE_INT_ENA : 1; /*!< The interrupt enable bit for the ecc_calc_done_int interrupt */ - uint32_t : 31; - } bit; - } MULT_INT_ENA; - - union { - __IOM uint32_t reg; /*!< ECC interrupt clear register. */ - - struct { - __OM uint32_t CALC_DONE_INT_CLR : 1; /*!< Set this bit to clear the ecc_calc_done_int interrupt */ - uint32_t : 31; - } bit; - } MULT_INT_CLR; - - union { - __IOM uint32_t reg; /*!< ECC configure register */ - - struct { - __IOM uint32_t START : 1; /*!< Write 1 to start caculation of ECC Accelerator. This bit will - be self-cleared after the caculatrion is done. */ - __OM uint32_t RESET : 1; /*!< Write 1 to reset ECC Accelerator. */ - __IOM uint32_t KEY_LENGTH : 1; /*!< The key length mode bit of ECC Accelerator. 0: P-192. 1: P-256. */ - __IOM uint32_t MOD_BASE : 1; /*!< The mod base of mod operation, only valid in work_mode 8-11. - 0: n(order of curve). 1: p(mod base of curve) */ - __IOM uint32_t WORK_MODE : 4; /*!< The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: - Reserved. 2: Point verification mode. 3: Point Verif+mult - mode. 4: Jacobian Point Mult Mode. 5: Point Add Mode. 6: - Jacobian Point Verification Mode. 7: Point Verif + Jacobian - Mult Mode. 8: mod addition. 9. mod substraction. 10: mod - multiplication. 11: mod division. */ - __IOM uint32_t SECURITY_MODE : 1; /*!< Reserved */ - uint32_t : 20; - __IM uint32_t VERIFICATION_RESULT : 1; /*!< The verification result bit of ECC Accelerator, only valid when - calculation is done. */ - __IOM uint32_t CLK_EN : 1; /*!< Write 1 to force on register clock gate. */ - __IOM uint32_t MEM_CLOCK_GATE_FORCE_ON : 1;/*!< ECC memory clock gate force on register */ - } bit; - } MULT_CONF; - __IM uint32_t RESERVED1[55]; - - union { - __IOM uint32_t reg; /*!< Version control register */ - - struct { - __IOM uint32_t DATE : 28; /*!< ECC mult version control register */ - uint32_t : 4; - } bit; - } MULT_DATE; - __IOM uint32_t K_MEM[8]; /*!< The memory that stores k. */ - __IOM uint32_t PX_MEM[8]; /*!< The memory that stores Px. */ - __IOM uint32_t PY_MEM[8]; /*!< The memory that stores Py. */ -} ECC_Type; /*!< Size = 352 (0x160) */ - - - -/* =========================================================================================================================== */ -/* ================ ECDSA ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief ECDSA (Elliptic Curve Digital Signature Algorithm) Accelerator (ECDSA) - */ - -typedef struct { /*!< ECDSA Structure */ - __IM uint32_t RESERVED; - - union { - __IOM uint32_t reg; /*!< ECDSA configure register */ - - struct { - __IOM uint32_t WORK_MODE : 2; /*!< The work mode bits of ECDSA Accelerator. 0: Signature Verify - Mode. 1: Signature Generate Mode. 2: Export Public Key - Mode. 3: invalid. */ - __IOM uint32_t ECC_CURVE : 1; /*!< The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: - P-256. */ - __IOM uint32_t SOFTWARE_SET_K : 1; /*!< The source of k select bit. 0: k is automatically generated - by hardware. 1: k is written by software. */ - __IOM uint32_t SOFTWARE_SET_Z : 1; /*!< The source of z select bit. 0: z is generated from SHA result. - 1: z is written by software. */ - __IOM uint32_t DETERMINISTIC_K : 1; /*!< The source of hardware generated k. 0: k is generated by TRNG. - 1: k is generated by deterministic derivation algorithm. */ - __IOM uint32_t DETERMINISTIC_LOOP : 16; /*!< The (loop number - 1) value in the deterministic derivation - algorithm to derive k. */ - uint32_t : 10; - } bit; - } CONF; - - union { - __IOM uint32_t reg; /*!< ECDSA clock gate register */ - - struct { - __IOM uint32_t GATE_FORCE_ON : 1; /*!< Write 1 to force on register clock gate. */ - uint32_t : 31; - } bit; - } CLK; - - union { - __IOM uint32_t reg; /*!< ECDSA interrupt raw register, valid in level. */ - - struct { - __IM uint32_t CALC_DONE_INT_RAW : 1; /*!< The raw interrupt status bit for the ecdsa_calc_done_int interrupt */ - __IM uint32_t SHA_RELEASE_INT_RAW : 1; /*!< The raw interrupt status bit for the ecdsa_sha_release_int interrupt */ - uint32_t : 30; - } bit; - } INT_RAW; - - union { - __IOM uint32_t reg; /*!< ECDSA interrupt status register. */ - - struct { - __IM uint32_t CALC_DONE_INT_ST : 1; /*!< The masked interrupt status bit for the ecdsa_calc_done_int - interrupt */ - __IM uint32_t SHA_RELEASE_INT_ST : 1; /*!< The masked interrupt status bit for the ecdsa_sha_release_int - interrupt */ - uint32_t : 30; - } bit; - } INT_ST; - - union { - __IOM uint32_t reg; /*!< ECDSA interrupt enable register. */ - - struct { - __IOM uint32_t CALC_DONE_INT_ENA : 1; /*!< The interrupt enable bit for the ecdsa_calc_done_int interrupt */ - __IOM uint32_t SHA_RELEASE_INT_ENA : 1; /*!< The interrupt enable bit for the ecdsa_sha_release_int interrupt */ - uint32_t : 30; - } bit; - } INT_ENA; - - union { - __IOM uint32_t reg; /*!< ECDSA interrupt clear register. */ - - struct { - __OM uint32_t CALC_DONE_INT_CLR : 1; /*!< Set this bit to clear the ecdsa_calc_done_int interrupt */ - __OM uint32_t SHA_RELEASE_INT_CLR : 1; /*!< Set this bit to clear the ecdsa_sha_release_int interrupt */ - uint32_t : 30; - } bit; - } INT_CLR; - - union { - __IOM uint32_t reg; /*!< ECDSA start register */ - - struct { - __OM uint32_t START : 1; /*!< Write 1 to start caculation of ECDSA Accelerator. This bit will - be self-cleared after configuration. */ - __OM uint32_t LOAD_DONE : 1; /*!< Write 1 to input load done signal of ECDSA Accelerator. This - bit will be self-cleared after configuration. */ - __OM uint32_t GET_DONE : 1; /*!< Write 1 to input get done signal of ECDSA Accelerator. This - bit will be self-cleared after configuration. */ - uint32_t : 29; - } bit; - } START; - - union { - __IOM uint32_t reg; /*!< ECDSA status register */ - - struct { - __IM uint32_t BUSY : 2; /*!< The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: - LOAD, 2: GET, 3: BUSY state. */ - uint32_t : 30; - } bit; - } STATE; - - union { - __IOM uint32_t reg; /*!< ECDSA result register */ - - struct { - __IM uint32_t OPERATION_RESULT : 1; /*!< The operation result bit of ECDSA Accelerator, only valid when - ECDSA calculation is done. */ - __IM uint32_t K_VALUE_WARNING : 1; /*!< The k value warning bit of ECDSA Accelerator, valid when k value - is bigger than the curve order, then actually taken k = - k mod n. */ - uint32_t : 30; - } bit; - } RESULT; - __IM uint32_t RESERVED1[53]; - - union { - __IOM uint32_t reg; /*!< Version control register */ - - struct { - __IOM uint32_t DATE : 28; /*!< ECDSA version control register */ - uint32_t : 4; - } bit; - } DATE; - __IM uint32_t RESERVED2[64]; - - union { - __IOM uint32_t reg; /*!< ECDSA control SHA register */ - - struct { - __IOM uint32_t SHA_MODE : 3; /*!< The work mode bits of SHA Calculator in ECDSA Accelerator. 1: - SHA-224. 2: SHA-256. Others: invalid. */ - uint32_t : 29; - } bit; - } SHA_MODE; - __IM uint32_t RESERVED3[3]; - - union { - __IOM uint32_t reg; /*!< ECDSA control SHA register */ - - struct { - __OM uint32_t SHA_START : 1; /*!< Write 1 to start the first caculation of SHA Calculator in ECDSA - Accelerator. This bit will be self-cleared after configuration. */ - uint32_t : 31; - } bit; - } SHA_START; - - union { - __IOM uint32_t reg; /*!< ECDSA control SHA register */ - - struct { - __OM uint32_t SHA_CONTINUE : 1; /*!< Write 1 to start the latter caculation of SHA Calculator in - ECDSA Accelerator. This bit will be self-cleared after - configuration. */ - uint32_t : 31; - } bit; - } SHA_CONTINUE; - - union { - __IOM uint32_t reg; /*!< ECDSA status register */ - - struct { - __IM uint32_t SHA_BUSY : 1; /*!< The busy status bit of SHA Calculator in ECDSA Accelerator. - 1:SHA is in calculation. 0: SHA is idle. */ - uint32_t : 31; - } bit; - } SHA_BUSY; - __IM uint32_t RESERVED4[25]; - __IOM uint32_t MESSAGE_MEM[8]; /*!< The memory that stores message. */ - __IM uint32_t RESERVED5[472]; - __IOM uint32_t R_MEM[8]; /*!< The memory that stores r. */ - __IOM uint32_t S_MEM[8]; /*!< The memory that stores s. */ - __IOM uint32_t Z_MEM[8]; /*!< The memory that stores software written z. */ - __IOM uint32_t QAX_MEM[8]; /*!< The memory that stores x coordinates of QA or software written - k. */ - __IOM uint32_t QAY_MEM[8]; /*!< The memory that stores y coordinates of QA. */ -} ECDSA_Type; /*!< Size = 2720 (0xaa0) */ - - - -/* =========================================================================================================================== */ -/* ================ EFUSE ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief eFuse Controller (EFUSE) - */ - -typedef struct { /*!< EFUSE Structure */ - - union { - __IOM uint32_t reg; /*!< Register 0 that stores data to be programmed. */ - - struct { - __IOM uint32_t PGM_DATA_0 : 32; /*!< Configures the 0th 32-bit data to be programmed. */ - } bit; - } PGM_DATA0; - - union { - __IOM uint32_t reg; /*!< Register 1 that stores data to be programmed. */ - - struct { - __IOM uint32_t PGM_DATA_1 : 32; /*!< Configures the 1st 32-bit data to be programmed. */ - } bit; - } PGM_DATA1; - - union { - __IOM uint32_t reg; /*!< Register 2 that stores data to be programmed. */ - - struct { - __IOM uint32_t PGM_DATA_2 : 32; /*!< Configures the 2nd 32-bit data to be programmed. */ - } bit; - } PGM_DATA2; - - union { - __IOM uint32_t reg; /*!< Register 3 that stores data to be programmed. */ - - struct { - __IOM uint32_t PGM_DATA_3 : 32; /*!< Configures the 3rd 32-bit data to be programmed. */ - } bit; - } PGM_DATA3; - - union { - __IOM uint32_t reg; /*!< Register 4 that stores data to be programmed. */ - - struct { - __IOM uint32_t PGM_DATA_4 : 32; /*!< Configures the 4th 32-bit data to be programmed. */ - } bit; - } PGM_DATA4; - - union { - __IOM uint32_t reg; /*!< Register 5 that stores data to be programmed. */ - - struct { - __IOM uint32_t PGM_DATA_5 : 32; /*!< Configures the 5th 32-bit data to be programmed. */ - } bit; - } PGM_DATA5; - - union { - __IOM uint32_t reg; /*!< Register 6 that stores data to be programmed. */ - - struct { - __IOM uint32_t PGM_DATA_6 : 32; /*!< Configures the 6th 32-bit data to be programmed. */ - } bit; - } PGM_DATA6; - - union { - __IOM uint32_t reg; /*!< Register 7 that stores data to be programmed. */ - - struct { - __IOM uint32_t PGM_DATA_7 : 32; /*!< Configures the 7th 32-bit data to be programmed. */ - } bit; - } PGM_DATA7; - - union { - __IOM uint32_t reg; /*!< Register 0 that stores the RS code to be programmed. */ - - struct { - __IOM uint32_t PGM_RS_DATA_0 : 32; /*!< Configures the 0th 32-bit RS code to be programmed. */ - } bit; - } PGM_CHECK_VALUE0; - - union { - __IOM uint32_t reg; /*!< Register 1 that stores the RS code to be programmed. */ - - struct { - __IOM uint32_t PGM_RS_DATA_1 : 32; /*!< Configures the 1st 32-bit RS code to be programmed. */ - } bit; - } PGM_CHECK_VALUE1; - - union { - __IOM uint32_t reg; /*!< Register 2 that stores the RS code to be programmed. */ - - struct { - __IOM uint32_t PGM_RS_DATA_2 : 32; /*!< Configures the 2nd 32-bit RS code to be programmed. */ - } bit; - } PGM_CHECK_VALUE2; - - union { - __IOM uint32_t reg; /*!< BLOCK0 data register 0. */ - - struct { - __IM uint32_t WR_DIS : 32; /*!< Represents whether programming of individual eFuse memory bit - is disabled or enabled. 1: Disabled. 0 Enabled. */ - } bit; - } RD_WR_DIS; - - union { - __IOM uint32_t reg; /*!< BLOCK0 data register 1. */ - - struct { - __IM uint32_t RD_DIS : 7; /*!< Represents whether reading of individual eFuse block(block4~block10) - is disabled or enabled. 1: disabled. 0: enabled. */ - __IM uint32_t USB_DEVICE_EXCHG_PINS : 1; /*!< Enable usb device exchange pins of D+ and D-. */ - __IM uint32_t USB_OTG11_EXCHG_PINS : 1; /*!< Enable usb otg11 exchange pins of D+ and D-. */ - __IM uint32_t DIS_USB_JTAG : 1; /*!< Represents whether the function of usb switch to jtag is disabled - or enabled. 1: disabled. 0: enabled. */ - __IM uint32_t POWERGLITCH_EN : 1; /*!< Represents whether power glitch function is enabled. 1: enabled. - 0: disabled. */ - __IM uint32_t DIS_USB_SERIAL_JTAG : 1; /*!< Represents whether USB-Serial-JTAG is disabled or enabled. 1: - disabled. 0: enabled. */ - __IM uint32_t DIS_FORCE_DOWNLOAD : 1; /*!< Represents whether the function that forces chip into download - mode is disabled or enabled. 1: disabled. 0: enabled. */ - __IM uint32_t SPI_DOWNLOAD_MSPI_DIS : 1; /*!< Set this bit to disable accessing MSPI flash/MSPI ram by SYS - AXI matrix during boot_mode_download. */ - __IM uint32_t DIS_TWAI : 1; /*!< Represents whether TWAI function is disabled or enabled. 1: - disabled. 0: enabled. */ - __IM uint32_t JTAG_SEL_ENABLE : 1; /*!< Represents whether the selection between usb_to_jtag and pad_to_jtag - through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and - EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. - 1: enabled. 0: disabled. */ - __IM uint32_t SOFT_DIS_JTAG : 3; /*!< Represents whether JTAG is disabled in soft way. Odd number: - disabled. Even number: enabled. */ - __IM uint32_t DIS_PAD_JTAG : 1; /*!< Represents whether JTAG is disabled in the hard way(permanently). - 1: disabled. 0: enabled. */ - __IM uint32_t DIS_DOWNLOAD_MANUAL_ENCRYPT : 1;/*!< Represents whether flash encrypt function is disabled or enabled(except - in SPI boot mode). 1: disabled. 0: enabled. */ - __IM uint32_t USB_DEVICE_DREFH : 2; /*!< USB intphy of usb device signle-end input high threshold, 1.76V - to 2V. Step by 80mV */ - __IM uint32_t USB_OTG11_DREFH : 2; /*!< USB intphy of usb otg11 signle-end input high threshold, 1.76V - to 2V. Step by 80mV */ - __IM uint32_t USB_PHY_SEL : 1; /*!< TBD */ - __IM uint32_t KM_HUK_GEN_STATE_LOW : 6; /*!< Set this bit to control validation of HUK generate mode. Odd - of 1 is invalid, even of 1 is valid. */ - } bit; - } RD_REPEAT_DATA0; - - union { - __IOM uint32_t reg; /*!< BLOCK0 data register 2. */ - - struct { - __IM uint32_t KM_HUK_GEN_STATE_HIGH : 3; /*!< Set this bit to control validation of HUK generate mode. Odd - of 1 is invalid, even of 1 is valid. */ - __IM uint32_t KM_RND_SWITCH_CYCLE : 2; /*!< Set bits to control key manager random number switch cycle. - 0: control by register. 1: 8 km clk cycles. 2: 16 km cycles. - 3: 32 km cycles. */ - __IM uint32_t KM_DEPLOY_ONLY_ONCE : 4; /*!< Set each bit to control whether corresponding key can only be - deployed once. 1 is true, 0 is false. Bit0: ecdsa. Bit1: - xts. Bit2: hmac. Bit3: ds. */ - __IM uint32_t FORCE_USE_KEY_MANAGER_KEY : 4;/*!< Set each bit to control whether corresponding key must come - from key manager.. 1 is true, 0 is false. Bit0: ecdsa. - Bit1: xts. Bit2: hmac. Bit3: ds. */ - __IM uint32_t FORCE_DISABLE_SW_INIT_KEY : 1;/*!< Set this bit to disable software written init key, and force - use efuse_init_key. */ - __IM uint32_t XTS_KEY_LENGTH_256 : 1; /*!< Set this bit to configure flash encryption use xts-128 key, - else use xts-256 key. */ - uint32_t : 1; - __IM uint32_t WDT_DELAY_SEL : 2; /*!< Represents whether RTC watchdog timeout threshold is selected - at startup. 1: selected. 0: not selected. */ - __IM uint32_t SPI_BOOT_CRYPT_CNT : 3; /*!< Represents whether SPI boot encrypt/decrypt is disabled or enabled. - Odd number of 1: enabled. Even number of 1: disabled. */ - __IM uint32_t SECURE_BOOT_KEY_REVOKE0 : 1;/*!< Represents whether revoking first secure boot key is enabled - or disabled. 1: enabled. 0: disabled. */ - __IM uint32_t SECURE_BOOT_KEY_REVOKE1 : 1;/*!< Represents whether revoking second secure boot key is enabled - or disabled. 1: enabled. 0: disabled. */ - __IM uint32_t SECURE_BOOT_KEY_REVOKE2 : 1;/*!< Represents whether revoking third secure boot key is enabled - or disabled. 1: enabled. 0: disabled. */ - __IM uint32_t KEY_PURPOSE_0 : 4; /*!< Represents the purpose of Key0. */ - __IM uint32_t KEY_PURPOSE_1 : 4; /*!< Represents the purpose of Key1. */ - } bit; - } RD_REPEAT_DATA1; - - union { - __IOM uint32_t reg; /*!< BLOCK0 data register 3. */ - - struct { - __IM uint32_t KEY_PURPOSE_2 : 4; /*!< Represents the purpose of Key2. */ - __IM uint32_t KEY_PURPOSE_3 : 4; /*!< Represents the purpose of Key3. */ - __IM uint32_t KEY_PURPOSE_4 : 4; /*!< Represents the purpose of Key4. */ - __IM uint32_t KEY_PURPOSE_5 : 4; /*!< Represents the purpose of Key5. */ - __IM uint32_t SEC_DPA_LEVEL : 2; /*!< Represents the spa secure level by configuring the clock random - divide mode. */ - __IM uint32_t ECDSA_ENABLE_SOFT_K : 1; /*!< Represents whether hardware random number k is forced used in - ESDCA. 1: force used. 0: not force used. */ - __IM uint32_t CRYPT_DPA_ENABLE : 1; /*!< Represents whether anti-dpa attack is enabled. 1:enabled. 0: - disabled. */ - __IM uint32_t SECURE_BOOT_EN : 1; /*!< Represents whether secure boot is enabled or disabled. 1: enabled. - 0: disabled. */ - __IM uint32_t SECURE_BOOT_AGGRESSIVE_REVOKE : 1;/*!< Represents whether revoking aggressive secure boot is enabled - or disabled. 1: enabled. 0: disabled. */ - uint32_t : 1; - __IM uint32_t FLASH_TYPE : 1; /*!< The type of interfaced flash. 0: four data lines, 1: eight data - lines. */ - __IM uint32_t FLASH_PAGE_SIZE : 2; /*!< Set flash page size. */ - __IM uint32_t FLASH_ECC_EN : 1; /*!< Set this bit to enable ecc for flash boot. */ - __IM uint32_t DIS_USB_OTG_DOWNLOAD_MODE : 1;/*!< Set this bit to disable download via USB-OTG. */ - __IM uint32_t FLASH_TPUW : 4; /*!< Represents the flash waiting time after power-up, in unit of - ms. When the value less than 15, the waiting time is the - programmed value. Otherwise, the waiting time is 2 times - the programmed value. */ - } bit; - } RD_REPEAT_DATA2; - - union { - __IOM uint32_t reg; /*!< BLOCK0 data register 4. */ - - struct { - __IM uint32_t DIS_DOWNLOAD_MODE : 1; /*!< Represents whether Download mode is disabled or enabled. 1: - disabled. 0: enabled. */ - __IM uint32_t DIS_DIRECT_BOOT : 1; /*!< Represents whether direct boot mode is disabled or enabled. - 1: disabled. 0: enabled. */ - __IM uint32_t DIS_USB_SERIAL_JTAG_ROM_PRINT : 1;/*!< Represents whether print from USB-Serial-JTAG is disabled or - enabled. 1: disabled. 0: enabled. */ - __IM uint32_t LOCK_KM_KEY : 1; /*!< TBD */ - __IM uint32_t DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE : 1;/*!< Represents whether the USB-Serial-JTAG download function is - disabled or enabled. 1: disabled. 0: enabled. */ - __IM uint32_t ENABLE_SECURITY_DOWNLOAD : 1;/*!< Represents whether security download is enabled or disabled. - 1: enabled. 0: disabled. */ - __IM uint32_t UART_PRINT_CONTROL : 2; /*!< Represents the type of UART printing. 00: force enable printing. - 01: enable printing when GPIO8 is reset at low level. 10: - enable printing when GPIO8 is reset at high level. 11: - force disable printing. */ - __IM uint32_t FORCE_SEND_RESUME : 1; /*!< Represents whether ROM code is forced to send a resume command - during SPI boot. 1: forced. 0:not forced. */ - __IM uint32_t SECURE_VERSION : 16; /*!< Represents the version used by ESP-IDF anti-rollback feature. */ - __IM uint32_t SECURE_BOOT_DISABLE_FAST_WAKE : 1;/*!< Represents whether FAST VERIFY ON WAKE is disabled or enabled - when Secure Boot is enabled. 1: disabled. 0: enabled. */ - __IM uint32_t HYS_EN_PAD : 1; /*!< Represents whether the hysteresis function of corresponding - PAD is enabled. 1: enabled. 0:disabled. */ - __IM uint32_t DCDC_VSET : 5; /*!< Set the dcdc voltage default. */ - } bit; - } RD_REPEAT_DATA3; - - union { - __IOM uint32_t reg; /*!< BLOCK0 data register 5. */ - - struct { - __IM uint32_t _0PXA_TIEH_SEL_0 : 2; /*!< TBD */ - __IM uint32_t _0PXA_TIEH_SEL_1 : 2; /*!< TBD. */ - __IM uint32_t _0PXA_TIEH_SEL_2 : 2; /*!< TBD. */ - __IM uint32_t _0PXA_TIEH_SEL_3 : 2; /*!< TBD. */ - __IM uint32_t KM_DISABLE_DEPLOY_MODE : 4;/*!< TBD. */ - __IM uint32_t USB_DEVICE_DREFL : 2; /*!< Represents the usb device single-end input low threhold, 0.8 - V to 1.04 V with step of 80 mV. */ - __IM uint32_t USB_OTG11_DREFL : 2; /*!< Represents the usb otg11 single-end input low threhold, 0.8 - V to 1.04 V with step of 80 mV. */ - uint32_t : 2; - __IM uint32_t HP_PWR_SRC_SEL : 1; /*!< HP system power source select. 0:LDO. 1: DCDC. */ - __IM uint32_t DCDC_VSET_EN : 1; /*!< Select dcdc vset use efuse_dcdc_vset. */ - __IM uint32_t DIS_WDT : 1; /*!< Set this bit to disable watch dog. */ - __IM uint32_t DIS_SWD : 1; /*!< Set this bit to disable super-watchdog. */ - uint32_t : 10; - } bit; - } RD_REPEAT_DATA4; - - union { - __IOM uint32_t reg; /*!< BLOCK1 data register $n. */ - - struct { - __IM uint32_t MAC_0 : 32; /*!< Stores the low 32 bits of MAC address. */ - } bit; - } RD_MAC_SYS_0; - - union { - __IOM uint32_t reg; /*!< BLOCK1 data register $n. */ - - struct { - __IM uint32_t MAC_1 : 16; /*!< Stores the high 16 bits of MAC address. */ - __IM uint32_t MAC_EXT : 16; /*!< Stores the extended bits of MAC address. */ - } bit; - } RD_MAC_SYS_1; - - union { - __IOM uint32_t reg; /*!< BLOCK1 data register $n. */ - - struct { - __IM uint32_t MAC_RESERVED_1 : 14; /*!< Reserved. */ - __IM uint32_t MAC_RESERVED_0 : 18; /*!< Reserved. */ - } bit; - } RD_MAC_SYS_2; - - union { - __IOM uint32_t reg; /*!< BLOCK1 data register $n. */ - - struct { - __IM uint32_t MAC_RESERVED_2 : 18; /*!< Reserved. */ - __IM uint32_t SYS_DATA_PART0_0 : 14; /*!< Stores the first 14 bits of the zeroth part of system data. */ - } bit; - } RD_MAC_SYS_3; - - union { - __IOM uint32_t reg; /*!< BLOCK1 data register $n. */ - - struct { - __IM uint32_t SYS_DATA_PART0_1 : 32; /*!< Stores the first 32 bits of the zeroth part of system data. */ - } bit; - } RD_MAC_SYS_4; - - union { - __IOM uint32_t reg; /*!< BLOCK1 data register $n. */ - - struct { - __IM uint32_t SYS_DATA_PART0_2 : 32; /*!< Stores the second 32 bits of the zeroth part of system data. */ - } bit; - } RD_MAC_SYS_5; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK2 (system). */ - - struct { - __IM uint32_t SYS_DATA_PART1_0 : 32; /*!< Stores the zeroth 32 bits of the first part of system data. */ - } bit; - } RD_SYS_PART1_DATA0; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK2 (system). */ - - struct { - __IM uint32_t SYS_DATA_PART1_1 : 32; /*!< Stores the first 32 bits of the first part of system data. */ - } bit; - } RD_SYS_PART1_DATA1; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK2 (system). */ - - struct { - __IM uint32_t SYS_DATA_PART1_2 : 32; /*!< Stores the second 32 bits of the first part of system data. */ - } bit; - } RD_SYS_PART1_DATA2; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK2 (system). */ - - struct { - __IM uint32_t SYS_DATA_PART1_3 : 32; /*!< Stores the third 32 bits of the first part of system data. */ - } bit; - } RD_SYS_PART1_DATA3; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK2 (system). */ - - struct { - __IM uint32_t SYS_DATA_PART1_4 : 32; /*!< Stores the fourth 32 bits of the first part of system data. */ - } bit; - } RD_SYS_PART1_DATA4; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK2 (system). */ - - struct { - __IM uint32_t SYS_DATA_PART1_5 : 32; /*!< Stores the fifth 32 bits of the first part of system data. */ - } bit; - } RD_SYS_PART1_DATA5; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK2 (system). */ - - struct { - __IM uint32_t SYS_DATA_PART1_6 : 32; /*!< Stores the sixth 32 bits of the first part of system data. */ - } bit; - } RD_SYS_PART1_DATA6; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK2 (system). */ - - struct { - __IM uint32_t SYS_DATA_PART1_7 : 32; /*!< Stores the seventh 32 bits of the first part of system data. */ - } bit; - } RD_SYS_PART1_DATA7; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK3 (user). */ - - struct { - __IM uint32_t USR_DATA0 : 32; /*!< Stores the zeroth 32 bits of BLOCK3 (user). */ - } bit; - } RD_USR_DATA0; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK3 (user). */ - - struct { - __IM uint32_t USR_DATA1 : 32; /*!< Stores the first 32 bits of BLOCK3 (user). */ - } bit; - } RD_USR_DATA1; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK3 (user). */ - - struct { - __IM uint32_t USR_DATA2 : 32; /*!< Stores the second 32 bits of BLOCK3 (user). */ - } bit; - } RD_USR_DATA2; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK3 (user). */ - - struct { - __IM uint32_t USR_DATA3 : 32; /*!< Stores the third 32 bits of BLOCK3 (user). */ - } bit; - } RD_USR_DATA3; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK3 (user). */ - - struct { - __IM uint32_t USR_DATA4 : 32; /*!< Stores the fourth 32 bits of BLOCK3 (user). */ - } bit; - } RD_USR_DATA4; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK3 (user). */ - - struct { - __IM uint32_t USR_DATA5 : 32; /*!< Stores the fifth 32 bits of BLOCK3 (user). */ - } bit; - } RD_USR_DATA5; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK3 (user). */ - - struct { - __IM uint32_t USR_DATA6 : 32; /*!< Stores the sixth 32 bits of BLOCK3 (user). */ - } bit; - } RD_USR_DATA6; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK3 (user). */ - - struct { - __IM uint32_t USR_DATA7 : 32; /*!< Stores the seventh 32 bits of BLOCK3 (user). */ - } bit; - } RD_USR_DATA7; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK4 (KEY0). */ - - struct { - __IM uint32_t KEY0_DATA0 : 32; /*!< Stores the zeroth 32 bits of KEY0. */ - } bit; - } RD_KEY0_DATA0; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK4 (KEY0). */ - - struct { - __IM uint32_t KEY0_DATA1 : 32; /*!< Stores the first 32 bits of KEY0. */ - } bit; - } RD_KEY0_DATA1; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK4 (KEY0). */ - - struct { - __IM uint32_t KEY0_DATA2 : 32; /*!< Stores the second 32 bits of KEY0. */ - } bit; - } RD_KEY0_DATA2; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK4 (KEY0). */ - - struct { - __IM uint32_t KEY0_DATA3 : 32; /*!< Stores the third 32 bits of KEY0. */ - } bit; - } RD_KEY0_DATA3; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK4 (KEY0). */ - - struct { - __IM uint32_t KEY0_DATA4 : 32; /*!< Stores the fourth 32 bits of KEY0. */ - } bit; - } RD_KEY0_DATA4; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK4 (KEY0). */ - - struct { - __IM uint32_t KEY0_DATA5 : 32; /*!< Stores the fifth 32 bits of KEY0. */ - } bit; - } RD_KEY0_DATA5; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK4 (KEY0). */ - - struct { - __IM uint32_t KEY0_DATA6 : 32; /*!< Stores the sixth 32 bits of KEY0. */ - } bit; - } RD_KEY0_DATA6; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK4 (KEY0). */ - - struct { - __IM uint32_t KEY0_DATA7 : 32; /*!< Stores the seventh 32 bits of KEY0. */ - } bit; - } RD_KEY0_DATA7; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK5 (KEY1). */ - - struct { - __IM uint32_t KEY1_DATA0 : 32; /*!< Stores the zeroth 32 bits of KEY1. */ - } bit; - } RD_KEY1_DATA0; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK5 (KEY1). */ - - struct { - __IM uint32_t KEY1_DATA1 : 32; /*!< Stores the first 32 bits of KEY1. */ - } bit; - } RD_KEY1_DATA1; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK5 (KEY1). */ - - struct { - __IM uint32_t KEY1_DATA2 : 32; /*!< Stores the second 32 bits of KEY1. */ - } bit; - } RD_KEY1_DATA2; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK5 (KEY1). */ - - struct { - __IM uint32_t KEY1_DATA3 : 32; /*!< Stores the third 32 bits of KEY1. */ - } bit; - } RD_KEY1_DATA3; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK5 (KEY1). */ - - struct { - __IM uint32_t KEY1_DATA4 : 32; /*!< Stores the fourth 32 bits of KEY1. */ - } bit; - } RD_KEY1_DATA4; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK5 (KEY1). */ - - struct { - __IM uint32_t KEY1_DATA5 : 32; /*!< Stores the fifth 32 bits of KEY1. */ - } bit; - } RD_KEY1_DATA5; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK5 (KEY1). */ - - struct { - __IM uint32_t KEY1_DATA6 : 32; /*!< Stores the sixth 32 bits of KEY1. */ - } bit; - } RD_KEY1_DATA6; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK5 (KEY1). */ - - struct { - __IM uint32_t KEY1_DATA7 : 32; /*!< Stores the seventh 32 bits of KEY1. */ - } bit; - } RD_KEY1_DATA7; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK6 (KEY2). */ - - struct { - __IM uint32_t KEY2_DATA0 : 32; /*!< Stores the zeroth 32 bits of KEY2. */ - } bit; - } RD_KEY2_DATA0; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK6 (KEY2). */ - - struct { - __IM uint32_t KEY2_DATA1 : 32; /*!< Stores the first 32 bits of KEY2. */ - } bit; - } RD_KEY2_DATA1; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK6 (KEY2). */ - - struct { - __IM uint32_t KEY2_DATA2 : 32; /*!< Stores the second 32 bits of KEY2. */ - } bit; - } RD_KEY2_DATA2; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK6 (KEY2). */ - - struct { - __IM uint32_t KEY2_DATA3 : 32; /*!< Stores the third 32 bits of KEY2. */ - } bit; - } RD_KEY2_DATA3; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK6 (KEY2). */ - - struct { - __IM uint32_t KEY2_DATA4 : 32; /*!< Stores the fourth 32 bits of KEY2. */ - } bit; - } RD_KEY2_DATA4; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK6 (KEY2). */ - - struct { - __IM uint32_t KEY2_DATA5 : 32; /*!< Stores the fifth 32 bits of KEY2. */ - } bit; - } RD_KEY2_DATA5; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK6 (KEY2). */ - - struct { - __IM uint32_t KEY2_DATA6 : 32; /*!< Stores the sixth 32 bits of KEY2. */ - } bit; - } RD_KEY2_DATA6; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK6 (KEY2). */ - - struct { - __IM uint32_t KEY2_DATA7 : 32; /*!< Stores the seventh 32 bits of KEY2. */ - } bit; - } RD_KEY2_DATA7; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK7 (KEY3). */ - - struct { - __IM uint32_t KEY3_DATA0 : 32; /*!< Stores the zeroth 32 bits of KEY3. */ - } bit; - } RD_KEY3_DATA0; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK7 (KEY3). */ - - struct { - __IM uint32_t KEY3_DATA1 : 32; /*!< Stores the first 32 bits of KEY3. */ - } bit; - } RD_KEY3_DATA1; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK7 (KEY3). */ - - struct { - __IM uint32_t KEY3_DATA2 : 32; /*!< Stores the second 32 bits of KEY3. */ - } bit; - } RD_KEY3_DATA2; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK7 (KEY3). */ - - struct { - __IM uint32_t KEY3_DATA3 : 32; /*!< Stores the third 32 bits of KEY3. */ - } bit; - } RD_KEY3_DATA3; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK7 (KEY3). */ - - struct { - __IM uint32_t KEY3_DATA4 : 32; /*!< Stores the fourth 32 bits of KEY3. */ - } bit; - } RD_KEY3_DATA4; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK7 (KEY3). */ - - struct { - __IM uint32_t KEY3_DATA5 : 32; /*!< Stores the fifth 32 bits of KEY3. */ - } bit; - } RD_KEY3_DATA5; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK7 (KEY3). */ - - struct { - __IM uint32_t KEY3_DATA6 : 32; /*!< Stores the sixth 32 bits of KEY3. */ - } bit; - } RD_KEY3_DATA6; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK7 (KEY3). */ - - struct { - __IM uint32_t KEY3_DATA7 : 32; /*!< Stores the seventh 32 bits of KEY3. */ - } bit; - } RD_KEY3_DATA7; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK8 (KEY4). */ - - struct { - __IM uint32_t KEY4_DATA0 : 32; /*!< Stores the zeroth 32 bits of KEY4. */ - } bit; - } RD_KEY4_DATA0; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK8 (KEY4). */ - - struct { - __IM uint32_t KEY4_DATA1 : 32; /*!< Stores the first 32 bits of KEY4. */ - } bit; - } RD_KEY4_DATA1; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK8 (KEY4). */ - - struct { - __IM uint32_t KEY4_DATA2 : 32; /*!< Stores the second 32 bits of KEY4. */ - } bit; - } RD_KEY4_DATA2; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK8 (KEY4). */ - - struct { - __IM uint32_t KEY4_DATA3 : 32; /*!< Stores the third 32 bits of KEY4. */ - } bit; - } RD_KEY4_DATA3; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK8 (KEY4). */ - - struct { - __IM uint32_t KEY4_DATA4 : 32; /*!< Stores the fourth 32 bits of KEY4. */ - } bit; - } RD_KEY4_DATA4; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK8 (KEY4). */ - - struct { - __IM uint32_t KEY4_DATA5 : 32; /*!< Stores the fifth 32 bits of KEY4. */ - } bit; - } RD_KEY4_DATA5; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK8 (KEY4). */ - - struct { - __IM uint32_t KEY4_DATA6 : 32; /*!< Stores the sixth 32 bits of KEY4. */ - } bit; - } RD_KEY4_DATA6; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK8 (KEY4). */ - - struct { - __IM uint32_t KEY4_DATA7 : 32; /*!< Stores the seventh 32 bits of KEY4. */ - } bit; - } RD_KEY4_DATA7; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK9 (KEY5). */ - - struct { - __IM uint32_t KEY5_DATA0 : 32; /*!< Stores the zeroth 32 bits of KEY5. */ - } bit; - } RD_KEY5_DATA0; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK9 (KEY5). */ - - struct { - __IM uint32_t KEY5_DATA1 : 32; /*!< Stores the first 32 bits of KEY5. */ - } bit; - } RD_KEY5_DATA1; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK9 (KEY5). */ - - struct { - __IM uint32_t KEY5_DATA2 : 32; /*!< Stores the second 32 bits of KEY5. */ - } bit; - } RD_KEY5_DATA2; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK9 (KEY5). */ - - struct { - __IM uint32_t KEY5_DATA3 : 32; /*!< Stores the third 32 bits of KEY5. */ - } bit; - } RD_KEY5_DATA3; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK9 (KEY5). */ - - struct { - __IM uint32_t KEY5_DATA4 : 32; /*!< Stores the fourth 32 bits of KEY5. */ - } bit; - } RD_KEY5_DATA4; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK9 (KEY5). */ - - struct { - __IM uint32_t KEY5_DATA5 : 32; /*!< Stores the fifth 32 bits of KEY5. */ - } bit; - } RD_KEY5_DATA5; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK9 (KEY5). */ - - struct { - __IM uint32_t KEY5_DATA6 : 32; /*!< Stores the sixth 32 bits of KEY5. */ - } bit; - } RD_KEY5_DATA6; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK9 (KEY5). */ - - struct { - __IM uint32_t KEY5_DATA7 : 32; /*!< Stores the seventh 32 bits of KEY5. */ - } bit; - } RD_KEY5_DATA7; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK10 (system). */ - - struct { - __IM uint32_t SYS_DATA_PART2_0 : 32; /*!< Stores the 0th 32 bits of the 2nd part of system data. */ - } bit; - } RD_SYS_PART2_DATA0; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK9 (KEY5). */ - - struct { - __IM uint32_t SYS_DATA_PART2_1 : 32; /*!< Stores the 0th 32 bits of the 2nd part of system data. */ - } bit; - } RD_SYS_PART2_DATA1; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK10 (system). */ - - struct { - __IM uint32_t SYS_DATA_PART2_2 : 32; /*!< Stores the 0th 32 bits of the 2nd part of system data. */ - } bit; - } RD_SYS_PART2_DATA2; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK10 (system). */ - - struct { - __IM uint32_t SYS_DATA_PART2_3 : 32; /*!< Stores the 0th 32 bits of the 2nd part of system data. */ - } bit; - } RD_SYS_PART2_DATA3; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK10 (system). */ - - struct { - __IM uint32_t SYS_DATA_PART2_4 : 32; /*!< Stores the 0th 32 bits of the 2nd part of system data. */ - } bit; - } RD_SYS_PART2_DATA4; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK10 (system). */ - - struct { - __IM uint32_t SYS_DATA_PART2_5 : 32; /*!< Stores the 0th 32 bits of the 2nd part of system data. */ - } bit; - } RD_SYS_PART2_DATA5; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK10 (system). */ - - struct { - __IM uint32_t SYS_DATA_PART2_6 : 32; /*!< Stores the 0th 32 bits of the 2nd part of system data. */ - } bit; - } RD_SYS_PART2_DATA6; - - union { - __IOM uint32_t reg; /*!< Register $n of BLOCK10 (system). */ - - struct { - __IM uint32_t SYS_DATA_PART2_7 : 32; /*!< Stores the 0th 32 bits of the 2nd part of system data. */ - } bit; - } RD_SYS_PART2_DATA7; - - union { - __IOM uint32_t reg; /*!< Programming error record register 0 of BLOCK0. */ - - struct { - __IM uint32_t RD_DIS_ERR : 7; /*!< Indicates a programming error of RD_DIS. */ - __IM uint32_t DIS_USB_DEVICE_EXCHG_PINS_ERR : 1;/*!< Indicates a programming error of DIS_USB_DEVICE_EXCHG_PINS. */ - __IM uint32_t DIS_USB_OTG11_EXCHG_PINS_ERR : 1;/*!< Indicates a programming error of DIS_USB_OTG11_EXCHG_PINS. */ - __IM uint32_t DIS_USB_JTAG_ERR : 1; /*!< Indicates a programming error of DIS_USB_JTAG. */ - __IM uint32_t POWERGLITCH_EN_ERR : 1; /*!< Indicates a programming error of POWERGLITCH_EN. */ - __IM uint32_t DIS_USB_SERIAL_JTAG_ERR : 1;/*!< Indicates a programming error of DIS_USB_SERIAL_JTAG. */ - __IM uint32_t DIS_FORCE_DOWNLOAD_ERR : 1;/*!< Indicates a programming error of DIS_FORCE_DOWNLOAD. */ - __IM uint32_t SPI_DOWNLOAD_MSPI_DIS_ERR : 1;/*!< Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS. */ - __IM uint32_t DIS_TWAI_ERR : 1; /*!< Indicates a programming error of DIS_TWAI. */ - __IM uint32_t JTAG_SEL_ENABLE_ERR : 1; /*!< Indicates a programming error of JTAG_SEL_ENABLE. */ - __IM uint32_t SOFT_DIS_JTAG_ERR : 3; /*!< Indicates a programming error of SOFT_DIS_JTAG. */ - __IM uint32_t DIS_PAD_JTAG_ERR : 1; /*!< Indicates a programming error of DIS_PAD_JTAG. */ - __IM uint32_t DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : 1;/*!< Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT. */ - __IM uint32_t USB_DEVICE_DREFH_ERR : 2; /*!< Indicates a programming error of USB_DEVICE_DREFH. */ - __IM uint32_t USB_OTG11_DREFH_ERR : 2; /*!< Indicates a programming error of USB_OTG11_DREFH. */ - __IM uint32_t USB_PHY_SEL_ERR : 1; /*!< Indicates a programming error of USB_PHY_SEL. */ - __IM uint32_t HUK_GEN_STATE_LOW_ERR : 6; /*!< Indicates a programming error of HUK_GEN_STATE_LOW. */ - } bit; - } RD_REPEAT_ERR0; - - union { - __IOM uint32_t reg; /*!< Programming error record register 1 of BLOCK0. */ - - struct { - __IM uint32_t KM_HUK_GEN_STATE_HIGH_ERR : 3;/*!< Indicates a programming error of HUK_GEN_STATE_HIGH. */ - __IM uint32_t KM_RND_SWITCH_CYCLE_ERR : 2;/*!< Indicates a programming error of KM_RND_SWITCH_CYCLE. */ - __IM uint32_t KM_DEPLOY_ONLY_ONCE_ERR : 4;/*!< Indicates a programming error of KM_DEPLOY_ONLY_ONCE. */ - __IM uint32_t FORCE_USE_KEY_MANAGER_KEY_ERR : 4;/*!< Indicates a programming error of FORCE_USE_KEY_MANAGER_KEY. */ - __IM uint32_t FORCE_DISABLE_SW_INIT_KEY_ERR : 1;/*!< Indicates a programming error of FORCE_DISABLE_SW_INIT_KEY. */ - __IM uint32_t XTS_KEY_LENGTH_256_ERR : 1;/*!< Indicates a programming error of XTS_KEY_LENGTH_256. */ - uint32_t : 1; - __IM uint32_t WDT_DELAY_SEL_ERR : 2; /*!< Indicates a programming error of WDT_DELAY_SEL. */ - __IM uint32_t SPI_BOOT_CRYPT_CNT_ERR : 3;/*!< Indicates a programming error of SPI_BOOT_CRYPT_CNT. */ - __IM uint32_t SECURE_BOOT_KEY_REVOKE0_ERR : 1;/*!< Indicates a programming error of SECURE_BOOT_KEY_REVOKE0. */ - __IM uint32_t SECURE_BOOT_KEY_REVOKE1_ERR : 1;/*!< Indicates a programming error of SECURE_BOOT_KEY_REVOKE1. */ - __IM uint32_t SECURE_BOOT_KEY_REVOKE2_ERR : 1;/*!< Indicates a programming error of SECURE_BOOT_KEY_REVOKE2. */ - __IM uint32_t KEY_PURPOSE_0_ERR : 4; /*!< Indicates a programming error of KEY_PURPOSE_0. */ - __IM uint32_t KEY_PURPOSE_1_ERR : 4; /*!< Indicates a programming error of KEY_PURPOSE_1. */ - } bit; - } RD_REPEAT_ERR1; - - union { - __IOM uint32_t reg; /*!< Programming error record register 2 of BLOCK0. */ - - struct { - __IM uint32_t KEY_PURPOSE_2_ERR : 4; /*!< Indicates a programming error of KEY_PURPOSE_2. */ - __IM uint32_t KEY_PURPOSE_3_ERR : 4; /*!< Indicates a programming error of KEY_PURPOSE_3. */ - __IM uint32_t KEY_PURPOSE_4_ERR : 4; /*!< Indicates a programming error of KEY_PURPOSE_4. */ - __IM uint32_t KEY_PURPOSE_5_ERR : 4; /*!< Indicates a programming error of KEY_PURPOSE_5. */ - __IM uint32_t SEC_DPA_LEVEL_ERR : 2; /*!< Indicates a programming error of SEC_DPA_LEVEL. */ - __IM uint32_t ECDSA_ENABLE_SOFT_K_ERR : 1;/*!< Indicates a programming error of ECDSA_FORCE_USE_HARDWARE_K. */ - __IM uint32_t CRYPT_DPA_ENABLE_ERR : 1; /*!< Indicates a programming error of CRYPT_DPA_ENABLE. */ - __IM uint32_t SECURE_BOOT_EN_ERR : 1; /*!< Indicates a programming error of SECURE_BOOT_EN. */ - __IM uint32_t SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : 1;/*!< Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE. */ - uint32_t : 1; - __IM uint32_t FLASH_TYPE_ERR : 1; /*!< Indicates a programming error of FLASH_TYPE. */ - __IM uint32_t FLASH_PAGE_SIZE_ERR : 2; /*!< Indicates a programming error of FLASH_PAGE_SIZE. */ - __IM uint32_t FLASH_ECC_EN_ERR : 1; /*!< Indicates a programming error of FLASH_ECC_EN. */ - __IM uint32_t DIS_USB_OTG_DOWNLOAD_MODE_ERR : 1;/*!< Indicates a programming error of DIS_USB_OTG_DOWNLOAD_MODE. */ - __IM uint32_t FLASH_TPUW_ERR : 4; /*!< Indicates a programming error of FLASH_TPUW. */ - } bit; - } RD_REPEAT_ERR2; - - union { - __IOM uint32_t reg; /*!< Programming error record register 3 of BLOCK0. */ - - struct { - __IM uint32_t DIS_DOWNLOAD_MODE_ERR : 1; /*!< Indicates a programming error of DIS_DOWNLOAD_MODE. */ - __IM uint32_t DIS_DIRECT_BOOT_ERR : 1; /*!< Indicates a programming error of DIS_DIRECT_BOOT. */ - __IM uint32_t DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR : 1;/*!< Indicates a programming error of DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR. */ - __IM uint32_t LOCK_KM_KEY_ERR : 1; /*!< TBD */ - __IM uint32_t DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR : 1;/*!< Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE. */ - __IM uint32_t ENABLE_SECURITY_DOWNLOAD_ERR : 1;/*!< Indicates a programming error of ENABLE_SECURITY_DOWNLOAD. */ - __IM uint32_t UART_PRINT_CONTROL_ERR : 2;/*!< Indicates a programming error of UART_PRINT_CONTROL. */ - __IM uint32_t FORCE_SEND_RESUME_ERR : 1; /*!< Indicates a programming error of FORCE_SEND_RESUME. */ - __IM uint32_t SECURE_VERSION_ERR : 16; /*!< Indicates a programming error of SECURE VERSION. */ - __IM uint32_t SECURE_BOOT_DISABLE_FAST_WAKE_ERR : 1;/*!< Indicates a programming error of SECURE_BOOT_DISABLE_FAST_WAKE. */ - __IM uint32_t HYS_EN_PAD_ERR : 1; /*!< Indicates a programming error of HYS_EN_PAD. */ - __IM uint32_t DCDC_VSET_ERR : 5; /*!< Indicates a programming error of DCDC_VSET. */ - } bit; - } RD_REPEAT_ERR3; - - union { - __IOM uint32_t reg; /*!< Programming error record register 4 of BLOCK0. */ - - struct { - __IM uint32_t _0PXA_TIEH_SEL_0_ERR : 2; /*!< Indicates a programming error of 0PXA_TIEH_SEL_0. */ - __IM uint32_t _0PXA_TIEH_SEL_1_ERR : 2; /*!< Indicates a programming error of 0PXA_TIEH_SEL_1. */ - __IM uint32_t _0PXA_TIEH_SEL_2_ERR : 2; /*!< Indicates a programming error of 0PXA_TIEH_SEL_2. */ - __IM uint32_t _0PXA_TIEH_SEL_3_ERR : 2; /*!< Indicates a programming error of 0PXA_TIEH_SEL_3. */ - __IM uint32_t KM_DISABLE_DEPLOY_MODE_ERR : 4;/*!< TBD. */ - __IM uint32_t USB_DEVICE_DREFL_ERR : 2; /*!< Indicates a programming error of USB_DEVICE_DREFL. */ - __IM uint32_t USB_OTG11_DREFL_ERR : 2; /*!< Indicates a programming error of USB_OTG11_DREFL. */ - uint32_t : 2; - __IM uint32_t HP_PWR_SRC_SEL_ERR : 1; /*!< Indicates a programming error of HP_PWR_SRC_SEL. */ - __IM uint32_t DCDC_VSET_EN_ERR : 1; /*!< Indicates a programming error of DCDC_VSET_EN. */ - __IM uint32_t DIS_WDT_ERR : 1; /*!< Indicates a programming error of DIS_WDT. */ - __IM uint32_t DIS_SWD_ERR : 1; /*!< Indicates a programming error of DIS_SWD. */ - uint32_t : 10; - } bit; - } RD_REPEAT_ERR4; - __IM uint32_t RESERVED[12]; - - union { - __IOM uint32_t reg; /*!< Programming error record register 0 of BLOCK1-10. */ - - struct { - __IM uint32_t MAC_SYS_ERR_NUM : 3; /*!< The value of this signal means the number of error bytes. */ - __IM uint32_t MAC_SYS_FAIL : 1; /*!< 0: Means no failure and that the data of MAC_SPI_8M is reliable - 1: Means that programming user data failed and the number - of error bytes is over 6. */ - __IM uint32_t SYS_PART1_ERR_NUM : 3; /*!< The value of this signal means the number of error bytes. */ - __IM uint32_t SYS_PART1_FAIL : 1; /*!< 0: Means no failure and that the data of system part1 is reliable - 1: Means that programming user data failed and the number - of error bytes is over 6. */ - __IM uint32_t USR_DATA_ERR_NUM : 3; /*!< The value of this signal means the number of error bytes. */ - __IM uint32_t USR_DATA_FAIL : 1; /*!< 0: Means no failure and that the user data is reliable 1: Means - that programming user data failed and the number of error - bytes is over 6. */ - __IM uint32_t KEY0_ERR_NUM : 3; /*!< The value of this signal means the number of error bytes. */ - __IM uint32_t KEY0_FAIL : 1; /*!< 0: Means no failure and that the data of key0 is reliable 1: - Means that programming key0 failed and the number of error - bytes is over 6. */ - __IM uint32_t KEY1_ERR_NUM : 3; /*!< The value of this signal means the number of error bytes. */ - __IM uint32_t KEY1_FAIL : 1; /*!< 0: Means no failure and that the data of key1 is reliable 1: - Means that programming key1 failed and the number of error - bytes is over 6. */ - __IM uint32_t KEY2_ERR_NUM : 3; /*!< The value of this signal means the number of error bytes. */ - __IM uint32_t KEY2_FAIL : 1; /*!< 0: Means no failure and that the data of key2 is reliable 1: - Means that programming key2 failed and the number of error - bytes is over 6. */ - __IM uint32_t KEY3_ERR_NUM : 3; /*!< The value of this signal means the number of error bytes. */ - __IM uint32_t KEY3_FAIL : 1; /*!< 0: Means no failure and that the data of key3 is reliable 1: - Means that programming key3 failed and the number of error - bytes is over 6. */ - __IM uint32_t KEY4_ERR_NUM : 3; /*!< The value of this signal means the number of error bytes. */ - __IM uint32_t KEY4_FAIL : 1; /*!< 0: Means no failure and that the data of key4 is reliable 1: - Means that programming key4 failed and the number of error - bytes is over 6. */ - } bit; - } RD_RS_ERR0; - - union { - __IOM uint32_t reg; /*!< Programming error record register 1 of BLOCK1-10. */ - - struct { - __IM uint32_t KEY5_ERR_NUM : 3; /*!< The value of this signal means the number of error bytes. */ - __IM uint32_t KEY5_FAIL : 1; /*!< 0: Means no failure and that the data of key5 is reliable 1: - Means that programming key5 failed and the number of error - bytes is over 6. */ - __IM uint32_t SYS_PART2_ERR_NUM : 3; /*!< The value of this signal means the number of error bytes. */ - __IM uint32_t SYS_PART2_FAIL : 1; /*!< 0: Means no failure and that the data of system part2 is reliable - 1: Means that programming user data failed and the number - of error bytes is over 6. */ - uint32_t : 24; - } bit; - } RD_RS_ERR1; - - union { - __IOM uint32_t reg; /*!< eFuse clcok configuration register. */ - - struct { - __IOM uint32_t MEM_FORCE_PD : 1; /*!< Set this bit to force eFuse SRAM into power-saving mode. */ - __IOM uint32_t MEM_CLK_FORCE_ON : 1; /*!< Set this bit and force to activate clock signal of eFuse SRAM. */ - __IOM uint32_t MEM_FORCE_PU : 1; /*!< Set this bit to force eFuse SRAM into working mode. */ - uint32_t : 13; - __IOM uint32_t EN : 1; /*!< Set this bit to force enable eFuse register configuration clock - signal. */ - uint32_t : 15; - } bit; - } CLK; - - union { - __IOM uint32_t reg; /*!< eFuse operation mode configuraiton register */ - - struct { - __IOM uint32_t OP_CODE : 16; /*!< 0x5A5A: programming operation command 0x5AA5: read operation - command. */ - __IOM uint32_t CFG_ECDSA_BLK : 4; /*!< Configures which block to use for ECDSA key output. */ - uint32_t : 12; - } bit; - } CONF; - - union { - __IOM uint32_t reg; /*!< eFuse status register. */ - - struct { - __IM uint32_t STATE : 4; /*!< Indicates the state of the eFuse state machine. */ - __IM uint32_t OTP_LOAD_SW : 1; /*!< The value of OTP_LOAD_SW. */ - __IM uint32_t OTP_VDDQ_C_SYNC2 : 1; /*!< The value of OTP_VDDQ_C_SYNC2. */ - __IM uint32_t OTP_STROBE_SW : 1; /*!< The value of OTP_STROBE_SW. */ - __IM uint32_t OTP_CSB_SW : 1; /*!< The value of OTP_CSB_SW. */ - __IM uint32_t OTP_PGENB_SW : 1; /*!< The value of OTP_PGENB_SW. */ - __IM uint32_t OTP_VDDQ_IS_SW : 1; /*!< The value of OTP_VDDQ_IS_SW. */ - __IM uint32_t BLK0_VALID_BIT_CNT : 10; /*!< Indicates the number of block valid bit. */ - __IM uint32_t CUR_ECDSA_BLK : 4; /*!< Indicates which block is used for ECDSA key output. */ - uint32_t : 8; - } bit; - } STATUS; - - union { - __IOM uint32_t reg; /*!< eFuse command register. */ - - struct { - __IOM uint32_t READ_CMD : 1; /*!< Set this bit to send read command. */ - __IOM uint32_t PGM_CMD : 1; /*!< Set this bit to send programming command. */ - __IOM uint32_t BLK_NUM : 4; /*!< The serial number of the block to be programmed. Value 0-10 - corresponds to block number 0-10, respectively. */ - uint32_t : 26; - } bit; - } CMD; - - union { - __IOM uint32_t reg; /*!< eFuse raw interrupt register. */ - - struct { - __IM uint32_t READ_DONE_INT_RAW : 1; /*!< The raw bit signal for read_done interrupt. */ - __IM uint32_t PGM_DONE_INT_RAW : 1; /*!< The raw bit signal for pgm_done interrupt. */ - uint32_t : 30; - } bit; - } INT_RAW; - - union { - __IOM uint32_t reg; /*!< eFuse interrupt status register. */ - - struct { - __IM uint32_t READ_DONE_INT_ST : 1; /*!< The status signal for read_done interrupt. */ - __IM uint32_t PGM_DONE_INT_ST : 1; /*!< The status signal for pgm_done interrupt. */ - uint32_t : 30; - } bit; - } INT_ST; - - union { - __IOM uint32_t reg; /*!< eFuse interrupt enable register. */ - - struct { - __IOM uint32_t READ_DONE_INT_ENA : 1; /*!< The enable signal for read_done interrupt. */ - __IOM uint32_t PGM_DONE_INT_ENA : 1; /*!< The enable signal for pgm_done interrupt. */ - uint32_t : 30; - } bit; - } INT_ENA; - - union { - __IOM uint32_t reg; /*!< eFuse interrupt clear register. */ - - struct { - __OM uint32_t READ_DONE_INT_CLR : 1; /*!< The clear signal for read_done interrupt. */ - __OM uint32_t PGM_DONE_INT_CLR : 1; /*!< The clear signal for pgm_done interrupt. */ - uint32_t : 30; - } bit; - } INT_CLR; - - union { - __IOM uint32_t reg; /*!< Controls the eFuse programming voltage. */ - - struct { - __IOM uint32_t DAC_CLK_DIV : 8; /*!< Controls the division factor of the rising clock of the programming - voltage. */ - __IOM uint32_t DAC_CLK_PAD_SEL : 1; /*!< Don't care. */ - __IOM uint32_t DAC_NUM : 8; /*!< Controls the rising period of the programming voltage. */ - __IOM uint32_t OE_CLR : 1; /*!< Reduces the power supply of the programming voltage. */ - uint32_t : 14; - } bit; - } DAC_CONF; - - union { - __IOM uint32_t reg; /*!< Configures read timing parameters. */ - - struct { - __IOM uint32_t THR_A : 8; /*!< Configures the read hold time. */ - __IOM uint32_t TRD : 8; /*!< Configures the read time. */ - __IOM uint32_t TSUR_A : 8; /*!< Configures the read setup time. */ - __IOM uint32_t READ_INIT_NUM : 8; /*!< Configures the waiting time of reading eFuse memory. */ - } bit; - } RD_TIM_CONF; - - union { - __IOM uint32_t reg; /*!< Configurarion register 1 of eFuse programming timing parameters. */ - - struct { - __IOM uint32_t TSUP_A : 8; /*!< Configures the programming setup time. */ - __IOM uint32_t PWR_ON_NUM : 16; /*!< Configures the power up time for VDDQ. */ - __IOM uint32_t THP_A : 8; /*!< Configures the programming hold time. */ - } bit; - } WR_TIM_CONF1; - - union { - __IOM uint32_t reg; /*!< Configurarion register 2 of eFuse programming timing parameters. */ - - struct { - __IOM uint32_t PWR_OFF_NUM : 16; /*!< Configures the power outage time for VDDQ. */ - __IOM uint32_t TPGM : 16; /*!< Configures the active programming time. */ - } bit; - } WR_TIM_CONF2; - - union { - __IOM uint32_t reg; /*!< Configurarion register0 of eFuse programming time parameters - and rs bypass operation. */ - - struct { - __IOM uint32_t BYPASS_RS_CORRECTION : 1; /*!< Set this bit to bypass reed solomon correction step. */ - __IOM uint32_t BYPASS_RS_BLK_NUM : 11; /*!< Configures block number of programming twice operation. */ - __OM uint32_t UPDATE : 1; /*!< Set this bit to update multi-bit register signals. */ - __IOM uint32_t TPGM_INACTIVE : 8; /*!< Configures the inactive programming time. */ - uint32_t : 11; - } bit; - } WR_TIM_CONF0_RS_BYPASS; - - union { - __IOM uint32_t reg; /*!< eFuse version register. */ - - struct { - __IOM uint32_t DATE : 28; /*!< Stores eFuse version. */ - uint32_t : 4; - } bit; - } DATE; - __IM uint32_t RESERVED1[384]; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block0 data register1. */ - - struct { - __IM uint32_t APB2OTP_BLOCK0_WR_DIS : 32;/*!< Otp block0 write disable data. */ - } bit; - } APB2OTP_WR_DIS; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block0 data register2. */ - - struct { - __IM uint32_t APB2OTP_BLOCK0_BACKUP1_W1 : 32;/*!< Otp block0 backup1 word1 data. */ - } bit; - } APB2OTP_BLK0_BACKUP1_W1; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block0 data register3. */ - - struct { - __IM uint32_t APB2OTP_BLOCK0_BACKUP1_W2 : 32;/*!< Otp block0 backup1 word2 data. */ - } bit; - } APB2OTP_BLK0_BACKUP1_W2; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block0 data register4. */ - - struct { - __IM uint32_t APB2OTP_BLOCK0_BACKUP1_W3 : 32;/*!< Otp block0 backup1 word3 data. */ - } bit; - } APB2OTP_BLK0_BACKUP1_W3; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block0 data register5. */ - - struct { - __IM uint32_t APB2OTP_BLOCK0_BACKUP1_W4 : 32;/*!< Otp block0 backup1 word4 data. */ - } bit; - } APB2OTP_BLK0_BACKUP1_W4; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block0 data register6. */ - - struct { - __IM uint32_t APB2OTP_BLOCK0_BACKUP1_W5 : 32;/*!< Otp block0 backup1 word5 data. */ - } bit; - } APB2OTP_BLK0_BACKUP1_W5; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block0 data register7. */ - - struct { - __IM uint32_t APB2OTP_BLOCK0_BACKUP2_W1 : 32;/*!< Otp block0 backup2 word1 data. */ - } bit; - } APB2OTP_BLK0_BACKUP2_W1; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block0 data register8. */ - - struct { - __IM uint32_t APB2OTP_BLOCK0_BACKUP2_W2 : 32;/*!< Otp block0 backup2 word2 data. */ - } bit; - } APB2OTP_BLK0_BACKUP2_W2; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block0 data register9. */ - - struct { - __IM uint32_t APB2OTP_BLOCK0_BACKUP2_W3 : 32;/*!< Otp block0 backup2 word3 data. */ - } bit; - } APB2OTP_BLK0_BACKUP2_W3; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block0 data register10. */ - - struct { - __IM uint32_t APB2OTP_BLOCK0_BACKUP2_W4 : 32;/*!< Otp block0 backup2 word4 data. */ - } bit; - } APB2OTP_BLK0_BACKUP2_W4; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block0 data register11. */ - - struct { - __IM uint32_t APB2OTP_BLOCK0_BACKUP2_W5 : 32;/*!< Otp block0 backup2 word5 data. */ - } bit; - } APB2OTP_BLK0_BACKUP2_W5; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block0 data register12. */ - - struct { - __IM uint32_t APB2OTP_BLOCK0_BACKUP3_W1 : 32;/*!< Otp block0 backup3 word1 data. */ - } bit; - } APB2OTP_BLK0_BACKUP3_W1; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block0 data register13. */ - - struct { - __IM uint32_t APB2OTP_BLOCK0_BACKUP3_W2 : 32;/*!< Otp block0 backup3 word2 data. */ - } bit; - } APB2OTP_BLK0_BACKUP3_W2; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block0 data register14. */ - - struct { - __IM uint32_t APB2OTP_BLOCK0_BACKUP3_W3 : 32;/*!< Otp block0 backup3 word3 data. */ - } bit; - } APB2OTP_BLK0_BACKUP3_W3; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block0 data register15. */ - - struct { - __IM uint32_t APB2OTP_BLOCK0_BACKUP3_W4 : 32;/*!< Otp block0 backup3 word4 data. */ - } bit; - } APB2OTP_BLK0_BACKUP3_W4; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block0 data register16. */ - - struct { - __IM uint32_t APB2OTP_BLOCK0_BACKUP3_W5 : 32;/*!< Otp block0 backup3 word5 data. */ - } bit; - } APB2OTP_BLK0_BACKUP3_W5; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block0 data register17. */ - - struct { - __IM uint32_t APB2OTP_BLOCK0_BACKUP4_W1 : 32;/*!< Otp block0 backup4 word1 data. */ - } bit; - } APB2OTP_BLK0_BACKUP4_W1; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block0 data register18. */ - - struct { - __IM uint32_t APB2OTP_BLOCK0_BACKUP4_W2 : 32;/*!< Otp block0 backup4 word2 data. */ - } bit; - } APB2OTP_BLK0_BACKUP4_W2; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block0 data register19. */ - - struct { - __IM uint32_t APB2OTP_BLOCK0_BACKUP4_W3 : 32;/*!< Otp block0 backup4 word3 data. */ - } bit; - } APB2OTP_BLK0_BACKUP4_W3; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block0 data register20. */ - - struct { - __IM uint32_t APB2OTP_BLOCK0_BACKUP4_W4 : 32;/*!< Otp block0 backup4 word4 data. */ - } bit; - } APB2OTP_BLK0_BACKUP4_W4; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block0 data register21. */ - - struct { - __IM uint32_t APB2OTP_BLOCK0_BACKUP4_W5 : 32;/*!< Otp block0 backup4 word5 data. */ - } bit; - } APB2OTP_BLK0_BACKUP4_W5; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block1 data register1. */ - - struct { - __IM uint32_t APB2OTP_BLOCK1_W1 : 32; /*!< Otp block1 word1 data. */ - } bit; - } APB2OTP_BLK1_W1; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block1 data register2. */ - - struct { - __IM uint32_t APB2OTP_BLOCK1_W2 : 32; /*!< Otp block1 word2 data. */ - } bit; - } APB2OTP_BLK1_W2; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block1 data register3. */ - - struct { - __IM uint32_t APB2OTP_BLOCK1_W3 : 32; /*!< Otp block1 word3 data. */ - } bit; - } APB2OTP_BLK1_W3; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block1 data register4. */ - - struct { - __IM uint32_t APB2OTP_BLOCK1_W4 : 32; /*!< Otp block1 word4 data. */ - } bit; - } APB2OTP_BLK1_W4; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block1 data register5. */ - - struct { - __IM uint32_t APB2OTP_BLOCK1_W5 : 32; /*!< Otp block1 word5 data. */ - } bit; - } APB2OTP_BLK1_W5; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block1 data register6. */ - - struct { - __IM uint32_t APB2OTP_BLOCK1_W6 : 32; /*!< Otp block1 word6 data. */ - } bit; - } APB2OTP_BLK1_W6; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block1 data register7. */ - - struct { - __IM uint32_t APB2OTP_BLOCK1_W7 : 32; /*!< Otp block1 word7 data. */ - } bit; - } APB2OTP_BLK1_W7; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block1 data register8. */ - - struct { - __IM uint32_t APB2OTP_BLOCK1_W8 : 32; /*!< Otp block1 word8 data. */ - } bit; - } APB2OTP_BLK1_W8; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block1 data register9. */ - - struct { - __IM uint32_t APB2OTP_BLOCK1_W9 : 32; /*!< Otp block1 word9 data. */ - } bit; - } APB2OTP_BLK1_W9; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block2 data register1. */ - - struct { - __IM uint32_t APB2OTP_BLOCK2_W1 : 32; /*!< Otp block2 word1 data. */ - } bit; - } APB2OTP_BLK2_W1; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block2 data register2. */ - - struct { - __IM uint32_t APB2OTP_BLOCK2_W2 : 32; /*!< Otp block2 word2 data. */ - } bit; - } APB2OTP_BLK2_W2; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block2 data register3. */ - - struct { - __IM uint32_t APB2OTP_BLOCK2_W3 : 32; /*!< Otp block2 word3 data. */ - } bit; - } APB2OTP_BLK2_W3; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block2 data register4. */ - - struct { - __IM uint32_t APB2OTP_BLOCK2_W4 : 32; /*!< Otp block2 word4 data. */ - } bit; - } APB2OTP_BLK2_W4; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block2 data register5. */ - - struct { - __IM uint32_t APB2OTP_BLOCK2_W5 : 32; /*!< Otp block2 word5 data. */ - } bit; - } APB2OTP_BLK2_W5; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block2 data register6. */ - - struct { - __IM uint32_t APB2OTP_BLOCK2_W6 : 32; /*!< Otp block2 word6 data. */ - } bit; - } APB2OTP_BLK2_W6; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block2 data register7. */ - - struct { - __IM uint32_t APB2OTP_BLOCK2_W7 : 32; /*!< Otp block2 word7 data. */ - } bit; - } APB2OTP_BLK2_W7; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block2 data register8. */ - - struct { - __IM uint32_t APB2OTP_BLOCK2_W8 : 32; /*!< Otp block2 word8 data. */ - } bit; - } APB2OTP_BLK2_W8; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block2 data register9. */ - - struct { - __IM uint32_t APB2OTP_BLOCK2_W9 : 32; /*!< Otp block2 word9 data. */ - } bit; - } APB2OTP_BLK2_W9; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block2 data register10. */ - - struct { - __IM uint32_t APB2OTP_BLOCK2_W10 : 32; /*!< Otp block2 word10 data. */ - } bit; - } APB2OTP_BLK2_W10; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block2 data register11. */ - - struct { - __IM uint32_t APB2OTP_BLOCK2_W11 : 32; /*!< Otp block2 word11 data. */ - } bit; - } APB2OTP_BLK2_W11; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block3 data register1. */ - - struct { - __IM uint32_t APB2OTP_BLOCK3_W1 : 32; /*!< Otp block3 word1 data. */ - } bit; - } APB2OTP_BLK3_W1; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block3 data register2. */ - - struct { - __IM uint32_t APB2OTP_BLOCK3_W2 : 32; /*!< Otp block3 word2 data. */ - } bit; - } APB2OTP_BLK3_W2; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block3 data register3. */ - - struct { - __IM uint32_t APB2OTP_BLOCK3_W3 : 32; /*!< Otp block3 word3 data. */ - } bit; - } APB2OTP_BLK3_W3; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block3 data register4. */ - - struct { - __IM uint32_t APB2OTP_BLOCK3_W4 : 32; /*!< Otp block3 word4 data. */ - } bit; - } APB2OTP_BLK3_W4; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block3 data register5. */ - - struct { - __IM uint32_t APB2OTP_BLOCK3_W5 : 32; /*!< Otp block3 word5 data. */ - } bit; - } APB2OTP_BLK3_W5; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block3 data register6. */ - - struct { - __IM uint32_t APB2OTP_BLOCK3_W6 : 32; /*!< Otp block3 word6 data. */ - } bit; - } APB2OTP_BLK3_W6; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block3 data register7. */ - - struct { - __IM uint32_t APB2OTP_BLOCK3_W7 : 32; /*!< Otp block3 word7 data. */ - } bit; - } APB2OTP_BLK3_W7; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block3 data register8. */ - - struct { - __IM uint32_t APB2OTP_BLOCK3_W8 : 32; /*!< Otp block3 word8 data. */ - } bit; - } APB2OTP_BLK3_W8; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block3 data register9. */ - - struct { - __IM uint32_t APB2OTP_BLOCK3_W9 : 32; /*!< Otp block3 word9 data. */ - } bit; - } APB2OTP_BLK3_W9; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block3 data register10. */ - - struct { - __IM uint32_t APB2OTP_BLOCK3_W10 : 32; /*!< Otp block3 word10 data. */ - } bit; - } APB2OTP_BLK3_W10; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block3 data register11. */ - - struct { - __IM uint32_t APB2OTP_BLOCK3_W11 : 32; /*!< Otp block3 word11 data. */ - } bit; - } APB2OTP_BLK3_W11; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block4 data register1. */ - - struct { - __IM uint32_t APB2OTP_BLOCK4_W1 : 32; /*!< Otp block4 word1 data. */ - } bit; - } APB2OTP_BLK4_W1; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block4 data register2. */ - - struct { - __IM uint32_t APB2OTP_BLOCK4_W2 : 32; /*!< Otp block4 word2 data. */ - } bit; - } APB2OTP_BLK4_W2; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block4 data register3. */ - - struct { - __IM uint32_t APB2OTP_BLOCK4_W3 : 32; /*!< Otp block4 word3 data. */ - } bit; - } APB2OTP_BLK4_W3; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block4 data register4. */ - - struct { - __IM uint32_t APB2OTP_BLOCK4_W4 : 32; /*!< Otp block4 word4 data. */ - } bit; - } APB2OTP_BLK4_W4; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block4 data register5. */ - - struct { - __IM uint32_t APB2OTP_BLOCK4_W5 : 32; /*!< Otp block4 word5 data. */ - } bit; - } APB2OTP_BLK4_W5; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block4 data register6. */ - - struct { - __IM uint32_t APB2OTP_BLOCK4_W6 : 32; /*!< Otp block4 word6 data. */ - } bit; - } APB2OTP_BLK4_W6; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block4 data register7. */ - - struct { - __IM uint32_t APB2OTP_BLOCK4_W7 : 32; /*!< Otp block4 word7 data. */ - } bit; - } APB2OTP_BLK4_W7; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block4 data register8. */ - - struct { - __IM uint32_t APB2OTP_BLOCK4_W8 : 32; /*!< Otp block4 word8 data. */ - } bit; - } APB2OTP_BLK4_W8; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block4 data register9. */ - - struct { - __IM uint32_t APB2OTP_BLOCK4_W9 : 32; /*!< Otp block4 word9 data. */ - } bit; - } APB2OTP_BLK4_W9; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block4 data registe10. */ - - struct { - __IM uint32_t APB2OTP_BLOCK4_W10 : 32; /*!< Otp block4 word10 data. */ - } bit; - } APB2OTP_BLK4_W10; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block4 data register11. */ - - struct { - __IM uint32_t APB2OTP_BLOCK4_W11 : 32; /*!< Otp block4 word11 data. */ - } bit; - } APB2OTP_BLK4_W11; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block5 data register1. */ - - struct { - __IM uint32_t APB2OTP_BLOCK5_W1 : 32; /*!< Otp block5 word1 data. */ - } bit; - } APB2OTP_BLK5_W1; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block5 data register2. */ - - struct { - __IM uint32_t APB2OTP_BLOCK5_W2 : 32; /*!< Otp block5 word2 data. */ - } bit; - } APB2OTP_BLK5_W2; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block5 data register3. */ - - struct { - __IM uint32_t APB2OTP_BLOCK5_W3 : 32; /*!< Otp block5 word3 data. */ - } bit; - } APB2OTP_BLK5_W3; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block5 data register4. */ - - struct { - __IM uint32_t APB2OTP_BLOCK5_W4 : 32; /*!< Otp block5 word4 data. */ - } bit; - } APB2OTP_BLK5_W4; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block5 data register5. */ - - struct { - __IM uint32_t APB2OTP_BLOCK5_W5 : 32; /*!< Otp block5 word5 data. */ - } bit; - } APB2OTP_BLK5_W5; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block5 data register6. */ - - struct { - __IM uint32_t APB2OTP_BLOCK5_W6 : 32; /*!< Otp block5 word6 data. */ - } bit; - } APB2OTP_BLK5_W6; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block5 data register7. */ - - struct { - __IM uint32_t APB2OTP_BLOCK5_W7 : 32; /*!< Otp block5 word7 data. */ - } bit; - } APB2OTP_BLK5_W7; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block5 data register8. */ - - struct { - __IM uint32_t APB2OTP_BLOCK5_W8 : 32; /*!< Otp block5 word8 data. */ - } bit; - } APB2OTP_BLK5_W8; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block5 data register9. */ - - struct { - __IM uint32_t APB2OTP_BLOCK5_W9 : 32; /*!< Otp block5 word9 data. */ - } bit; - } APB2OTP_BLK5_W9; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block5 data register10. */ - - struct { - __IM uint32_t APB2OTP_BLOCK5_W10 : 32; /*!< Otp block5 word10 data. */ - } bit; - } APB2OTP_BLK5_W10; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block5 data register11. */ - - struct { - __IM uint32_t APB2OTP_BLOCK5_W11 : 32; /*!< Otp block5 word11 data. */ - } bit; - } APB2OTP_BLK5_W11; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block6 data register1. */ - - struct { - __IM uint32_t APB2OTP_BLOCK6_W1 : 32; /*!< Otp block6 word1 data. */ - } bit; - } APB2OTP_BLK6_W1; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block6 data register2. */ - - struct { - __IM uint32_t APB2OTP_BLOCK6_W2 : 32; /*!< Otp block6 word2 data. */ - } bit; - } APB2OTP_BLK6_W2; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block6 data register3. */ - - struct { - __IM uint32_t APB2OTP_BLOCK6_W3 : 32; /*!< Otp block6 word3 data. */ - } bit; - } APB2OTP_BLK6_W3; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block6 data register4. */ - - struct { - __IM uint32_t APB2OTP_BLOCK6_W4 : 32; /*!< Otp block6 word4 data. */ - } bit; - } APB2OTP_BLK6_W4; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block6 data register5. */ - - struct { - __IM uint32_t APB2OTP_BLOCK6_W5 : 32; /*!< Otp block6 word5 data. */ - } bit; - } APB2OTP_BLK6_W5; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block6 data register6. */ - - struct { - __IM uint32_t APB2OTP_BLOCK6_W6 : 32; /*!< Otp block6 word6 data. */ - } bit; - } APB2OTP_BLK6_W6; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block6 data register7. */ - - struct { - __IM uint32_t APB2OTP_BLOCK6_W7 : 32; /*!< Otp block6 word7 data. */ - } bit; - } APB2OTP_BLK6_W7; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block6 data register8. */ - - struct { - __IM uint32_t APB2OTP_BLOCK6_W8 : 32; /*!< Otp block6 word8 data. */ - } bit; - } APB2OTP_BLK6_W8; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block6 data register9. */ - - struct { - __IM uint32_t APB2OTP_BLOCK6_W9 : 32; /*!< Otp block6 word9 data. */ - } bit; - } APB2OTP_BLK6_W9; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block6 data register10. */ - - struct { - __IM uint32_t APB2OTP_BLOCK6_W10 : 32; /*!< Otp block6 word10 data. */ - } bit; - } APB2OTP_BLK6_W10; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block6 data register11. */ - - struct { - __IM uint32_t APB2OTP_BLOCK6_W11 : 32; /*!< Otp block6 word11 data. */ - } bit; - } APB2OTP_BLK6_W11; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block7 data register1. */ - - struct { - __IM uint32_t APB2OTP_BLOCK7_W1 : 32; /*!< Otp block7 word1 data. */ - } bit; - } APB2OTP_BLK7_W1; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block7 data register2. */ - - struct { - __IM uint32_t APB2OTP_BLOCK7_W2 : 32; /*!< Otp block7 word2 data. */ - } bit; - } APB2OTP_BLK7_W2; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block7 data register3. */ - - struct { - __IM uint32_t APB2OTP_BLOCK7_W3 : 32; /*!< Otp block7 word3 data. */ - } bit; - } APB2OTP_BLK7_W3; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block7 data register4. */ - - struct { - __IM uint32_t APB2OTP_BLOCK7_W4 : 32; /*!< Otp block7 word4 data. */ - } bit; - } APB2OTP_BLK7_W4; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block7 data register5. */ - - struct { - __IM uint32_t APB2OTP_BLOCK7_W5 : 32; /*!< Otp block7 word5 data. */ - } bit; - } APB2OTP_BLK7_W5; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block7 data register6. */ - - struct { - __IM uint32_t APB2OTP_BLOCK7_W6 : 32; /*!< Otp block7 word6 data. */ - } bit; - } APB2OTP_BLK7_W6; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block7 data register7. */ - - struct { - __IM uint32_t APB2OTP_BLOCK7_W7 : 32; /*!< Otp block7 word7 data. */ - } bit; - } APB2OTP_BLK7_W7; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block7 data register8. */ - - struct { - __IM uint32_t APB2OTP_BLOCK7_W8 : 32; /*!< Otp block7 word8 data. */ - } bit; - } APB2OTP_BLK7_W8; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block7 data register9. */ - - struct { - __IM uint32_t APB2OTP_BLOCK7_W9 : 32; /*!< Otp block7 word9 data. */ - } bit; - } APB2OTP_BLK7_W9; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block7 data register10. */ - - struct { - __IM uint32_t APB2OTP_BLOCK7_W10 : 32; /*!< Otp block7 word10 data. */ - } bit; - } APB2OTP_BLK7_W10; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block7 data register11. */ - - struct { - __IM uint32_t APB2OTP_BLOCK7_W11 : 32; /*!< Otp block7 word11 data. */ - } bit; - } APB2OTP_BLK7_W11; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block8 data register1. */ - - struct { - __IM uint32_t APB2OTP_BLOCK8_W1 : 32; /*!< Otp block8 word1 data. */ - } bit; - } APB2OTP_BLK8_W1; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block8 data register2. */ - - struct { - __IM uint32_t APB2OTP_BLOCK8_W2 : 32; /*!< Otp block8 word2 data. */ - } bit; - } APB2OTP_BLK8_W2; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block8 data register3. */ - - struct { - __IM uint32_t APB2OTP_BLOCK8_W3 : 32; /*!< Otp block8 word3 data. */ - } bit; - } APB2OTP_BLK8_W3; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block8 data register4. */ - - struct { - __IM uint32_t APB2OTP_BLOCK8_W4 : 32; /*!< Otp block8 word4 data. */ - } bit; - } APB2OTP_BLK8_W4; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block8 data register5. */ - - struct { - __IM uint32_t APB2OTP_BLOCK8_W5 : 32; /*!< Otp block8 word5 data. */ - } bit; - } APB2OTP_BLK8_W5; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block8 data register6. */ - - struct { - __IM uint32_t APB2OTP_BLOCK8_W6 : 32; /*!< Otp block8 word6 data. */ - } bit; - } APB2OTP_BLK8_W6; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block8 data register7. */ - - struct { - __IM uint32_t APB2OTP_BLOCK8_W7 : 32; /*!< Otp block8 word7 data. */ - } bit; - } APB2OTP_BLK8_W7; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block8 data register8. */ - - struct { - __IM uint32_t APB2OTP_BLOCK8_W8 : 32; /*!< Otp block8 word8 data. */ - } bit; - } APB2OTP_BLK8_W8; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block8 data register9. */ - - struct { - __IM uint32_t APB2OTP_BLOCK8_W9 : 32; /*!< Otp block8 word9 data. */ - } bit; - } APB2OTP_BLK8_W9; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block8 data register10. */ - - struct { - __IM uint32_t APB2OTP_BLOCK8_W10 : 32; /*!< Otp block8 word10 data. */ - } bit; - } APB2OTP_BLK8_W10; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block8 data register11. */ - - struct { - __IM uint32_t APB2OTP_BLOCK8_W11 : 32; /*!< Otp block8 word11 data. */ - } bit; - } APB2OTP_BLK8_W11; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block9 data register1. */ - - struct { - __IM uint32_t APB2OTP_BLOCK9_W1 : 32; /*!< Otp block9 word1 data. */ - } bit; - } APB2OTP_BLK9_W1; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block9 data register2. */ - - struct { - __IM uint32_t APB2OTP_BLOCK9_W2 : 32; /*!< Otp block9 word2 data. */ - } bit; - } APB2OTP_BLK9_W2; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block9 data register3. */ - - struct { - __IM uint32_t APB2OTP_BLOCK9_W3 : 32; /*!< Otp block9 word3 data. */ - } bit; - } APB2OTP_BLK9_W3; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block9 data register4. */ - - struct { - __IM uint32_t APB2OTP_BLOCK9_W4 : 32; /*!< Otp block9 word4 data. */ - } bit; - } APB2OTP_BLK9_W4; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block9 data register5. */ - - struct { - __IM uint32_t APB2OTP_BLOCK9_W5 : 32; /*!< Otp block9 word5 data. */ - } bit; - } APB2OTP_BLK9_W5; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block9 data register6. */ - - struct { - __IM uint32_t APB2OTP_BLOCK9_W6 : 32; /*!< Otp block9 word6 data. */ - } bit; - } APB2OTP_BLK9_W6; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block9 data register7. */ - - struct { - __IM uint32_t APB2OTP_BLOCK9_W7 : 32; /*!< Otp block9 word7 data. */ - } bit; - } APB2OTP_BLK9_W7; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block9 data register8. */ - - struct { - __IM uint32_t APB2OTP_BLOCK9_W8 : 32; /*!< Otp block9 word8 data. */ - } bit; - } APB2OTP_BLK9_W8; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block9 data register9. */ - - struct { - __IM uint32_t APB2OTP_BLOCK9_W9 : 32; /*!< Otp block9 word9 data. */ - } bit; - } APB2OTP_BLK9_W9; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block9 data register10. */ - - struct { - __IM uint32_t APB2OTP_BLOCK9_W10 : 32; /*!< Otp block9 word10 data. */ - } bit; - } APB2OTP_BLK9_W10; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block9 data register11. */ - - struct { - __IM uint32_t APB2OTP_BLOCK9_W11 : 32; /*!< Otp block9 word11 data. */ - } bit; - } APB2OTP_BLK9_W11; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block10 data register1. */ - - struct { - __IM uint32_t APB2OTP_BLOCK10_W1 : 32; /*!< Otp block10 word1 data. */ - } bit; - } APB2OTP_BLK10_W1; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block10 data register2. */ - - struct { - __IM uint32_t APB2OTP_BLOCK10_W2 : 32; /*!< Otp block10 word2 data. */ - } bit; - } APB2OTP_BLK10_W2; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block10 data register3. */ - - struct { - __IM uint32_t APB2OTP_BLOCK10_W3 : 32; /*!< Otp block10 word3 data. */ - } bit; - } APB2OTP_BLK10_W3; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block10 data register4. */ - - struct { - __IM uint32_t APB2OTP_BLOCK10_W4 : 32; /*!< Otp block10 word4 data. */ - } bit; - } APB2OTP_BLK10_W4; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block10 data register5. */ - - struct { - __IM uint32_t APB2OTP_BLOCK10_W5 : 32; /*!< Otp block10 word5 data. */ - } bit; - } APB2OTP_BLK10_W5; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block10 data register6. */ - - struct { - __IM uint32_t APB2OTP_BLOCK10_W6 : 32; /*!< Otp block10 word6 data. */ - } bit; - } APB2OTP_BLK10_W6; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block10 data register7. */ - - struct { - __IM uint32_t APB2OTP_BLOCK10_W7 : 32; /*!< Otp block10 word7 data. */ - } bit; - } APB2OTP_BLK10_W7; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block10 data register8. */ - - struct { - __IM uint32_t APB2OTP_BLOCK10_W8 : 32; /*!< Otp block10 word8 data. */ - } bit; - } APB2OTP_BLK10_W8; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block10 data register9. */ - - struct { - __IM uint32_t APB2OTP_BLOCK10_W9 : 32; /*!< Otp block10 word9 data. */ - } bit; - } APB2OTP_BLK10_W9; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block10 data register10. */ - - struct { - __IM uint32_t APB2OTP_BLOCK19_W10 : 32; /*!< Otp block10 word10 data. */ - } bit; - } APB2OTP_BLK10_W10; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp block10 data register11. */ - - struct { - __IM uint32_t APB2OTP_BLOCK10_W11 : 32; /*!< Otp block10 word11 data. */ - } bit; - } APB2OTP_BLK10_W11; - __IM uint32_t RESERVED2; - - union { - __IOM uint32_t reg; /*!< eFuse apb2otp enable configuration register. */ - - struct { - __IOM uint32_t APB2OTP_APB2OTP_EN : 1; /*!< Apb2otp mode enable signal. */ - uint32_t : 31; - } bit; - } APB2OTP_EN; -} EFUSE_Type; /*!< Size = 2572 (0xa0c) */ - - - -/* =========================================================================================================================== */ -/* ================ GPIO ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief General Purpose Input/Output (GPIO) - */ - -typedef struct { /*!< GPIO Structure */ - - union { - __IOM uint32_t reg; /*!< GPIO bit select register */ - - struct { - __IOM uint32_t BT_SEL : 32; /*!< GPIO bit select register */ - } bit; - } BT_SELECT; - - union { - __IOM uint32_t reg; /*!< GPIO output register for GPIO0-31 */ - - struct { - __IOM uint32_t DATA_ORIG : 32; /*!< GPIO output register for GPIO0-31 */ - } bit; - } OUT; - - union { - __IOM uint32_t reg; /*!< GPIO output set register for GPIO0-31 */ - - struct { - __OM uint32_t OUT_W1TS : 32; /*!< GPIO output set register for GPIO0-31 */ - } bit; - } OUT_W1TS; - - union { - __IOM uint32_t reg; /*!< GPIO output clear register for GPIO0-31 */ - - struct { - __OM uint32_t OUT_W1TC : 32; /*!< GPIO output clear register for GPIO0-31 */ - } bit; - } OUT_W1TC; - - union { - __IOM uint32_t reg; /*!< GPIO output register for GPIO32-56 */ - - struct { - __IOM uint32_t DATA_ORIG : 25; /*!< GPIO output register for GPIO32-56 */ - uint32_t : 7; - } bit; - } OUT1; - - union { - __IOM uint32_t reg; /*!< GPIO output set register for GPIO32-56 */ - - struct { - __OM uint32_t OUT1_W1TS : 25; /*!< GPIO output set register for GPIO32-56 */ - uint32_t : 7; - } bit; - } OUT1_W1TS; - - union { - __IOM uint32_t reg; /*!< GPIO output clear register for GPIO32-56 */ - - struct { - __OM uint32_t OUT1_W1TC : 25; /*!< GPIO output clear register for GPIO32-56 */ - uint32_t : 7; - } bit; - } OUT1_W1TC; - __IM uint32_t RESERVED; - - union { - __IOM uint32_t reg; /*!< GPIO output enable register for GPIO0-31 */ - - struct { - __IOM uint32_t DATA : 32; /*!< GPIO output enable register for GPIO0-31 */ - } bit; - } ENABLE; - - union { - __IOM uint32_t reg; /*!< GPIO output enable set register for GPIO0-31 */ - - struct { - __OM uint32_t ENABLE_W1TS : 32; /*!< GPIO output enable set register for GPIO0-31 */ - } bit; - } ENABLE_W1TS; - - union { - __IOM uint32_t reg; /*!< GPIO output enable clear register for GPIO0-31 */ - - struct { - __OM uint32_t ENABLE_W1TC : 32; /*!< GPIO output enable clear register for GPIO0-31 */ - } bit; - } ENABLE_W1TC; - - union { - __IOM uint32_t reg; /*!< GPIO output enable register for GPIO32-56 */ - - struct { - __IOM uint32_t DATA : 25; /*!< GPIO output enable register for GPIO32-56 */ - uint32_t : 7; - } bit; - } ENABLE1; - - union { - __IOM uint32_t reg; /*!< GPIO output enable set register for GPIO32-56 */ - - struct { - __OM uint32_t ENABLE1_W1TS : 25; /*!< GPIO output enable set register for GPIO32-56 */ - uint32_t : 7; - } bit; - } ENABLE1_W1TS; - - union { - __IOM uint32_t reg; /*!< GPIO output enable clear register for GPIO32-56 */ - - struct { - __OM uint32_t ENABLE1_W1TC : 25; /*!< GPIO output enable clear register for GPIO32-56 */ - uint32_t : 7; - } bit; - } ENABLE1_W1TC; - - union { - __IOM uint32_t reg; /*!< pad strapping register */ - - struct { - __IM uint32_t STRAPPING : 16; /*!< pad strapping register */ - uint32_t : 16; - } bit; - } STRAP; - - union { - __IOM uint32_t reg; /*!< GPIO input register for GPIO0-31 */ - - struct { - __IM uint32_t DATA_NEXT : 32; /*!< GPIO input register for GPIO0-31 */ - } bit; - } IN; - - union { - __IOM uint32_t reg; /*!< GPIO input register for GPIO32-56 */ - - struct { - __IM uint32_t DATA_NEXT : 25; /*!< GPIO input register for GPIO32-56 */ - uint32_t : 7; - } bit; - } IN1; - - union { - __IOM uint32_t reg; /*!< GPIO interrupt status register for GPIO0-31 */ - - struct { - __IOM uint32_t INTERRUPT : 32; /*!< GPIO interrupt status register for GPIO0-31 */ - } bit; - } STATUS; - - union { - __IOM uint32_t reg; /*!< GPIO interrupt status set register for GPIO0-31 */ - - struct { - __OM uint32_t STATUS_W1TS : 32; /*!< GPIO interrupt status set register for GPIO0-31 */ - } bit; - } STATUS_W1TS; - - union { - __IOM uint32_t reg; /*!< GPIO interrupt status clear register for GPIO0-31 */ - - struct { - __OM uint32_t STATUS_W1TC : 32; /*!< GPIO interrupt status clear register for GPIO0-31 */ - } bit; - } STATUS_W1TC; - - union { - __IOM uint32_t reg; /*!< GPIO interrupt status register for GPIO32-56 */ - - struct { - __IOM uint32_t INTERRUPT : 25; /*!< GPIO interrupt status register for GPIO32-56 */ - uint32_t : 7; - } bit; - } STATUS1; - - union { - __IOM uint32_t reg; /*!< GPIO interrupt status set register for GPIO32-56 */ - - struct { - __OM uint32_t STATUS1_W1TS : 25; /*!< GPIO interrupt status set register for GPIO32-56 */ - uint32_t : 7; - } bit; - } STATUS1_W1TS; - - union { - __IOM uint32_t reg; /*!< GPIO interrupt status clear register for GPIO32-56 */ - - struct { - __OM uint32_t STATUS1_W1TC : 25; /*!< GPIO interrupt status clear register for GPIO32-56 */ - uint32_t : 7; - } bit; - } STATUS1_W1TC; - - union { - __IOM uint32_t reg; /*!< GPIO interrupt 0 status register for GPIO0-31 */ - - struct { - __IM uint32_t INT_0 : 32; /*!< GPIO interrupt 0 status register for GPIO0-31 */ - } bit; - } INTR_0; - - union { - __IOM uint32_t reg; /*!< GPIO interrupt 0 status register for GPIO32-56 */ - - struct { - __IM uint32_t INT1_0 : 25; /*!< GPIO interrupt 0 status register for GPIO32-56 */ - uint32_t : 7; - } bit; - } INTR1_0; - - union { - __IOM uint32_t reg; /*!< GPIO interrupt 1 status register for GPIO0-31 */ - - struct { - __IM uint32_t INT_1 : 32; /*!< GPIO interrupt 1 status register for GPIO0-31 */ - } bit; - } INTR_1; - - union { - __IOM uint32_t reg; /*!< GPIO interrupt 1 status register for GPIO32-56 */ - - struct { - __IM uint32_t INT1_1 : 25; /*!< GPIO interrupt 1 status register for GPIO32-56 */ - uint32_t : 7; - } bit; - } INTR1_1; - - union { - __IOM uint32_t reg; /*!< GPIO interrupt source register for GPIO0-31 */ - - struct { - __IM uint32_t STATUS_INTERRUPT_NEXT : 32;/*!< GPIO interrupt source register for GPIO0-31 */ - } bit; - } STATUS_NEXT; - - union { - __IOM uint32_t reg; /*!< GPIO interrupt source register for GPIO32-56 */ - - struct { - __IM uint32_t STATUS_INTERRUPT_NEXT1 : 25;/*!< GPIO interrupt source register for GPIO32-56 */ - uint32_t : 7; - } bit; - } STATUS_NEXT1; - - union { - __IOM uint32_t reg; /*!< GPIO pin configuration register */ - - struct { - __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ - __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - uint32_t : 2; - __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. - 1:trigger at posedge. 2:trigger at negedge. 3:trigger at - any edge. 4:valid at low level. 5:valid at high level */ - __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from - Light-sleep Mode) */ - __IOM uint32_t CONFIG : 2; /*!< reserved */ - __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not - shielded) interrupt. */ - uint32_t : 14; - } bit; - } PIN0; - __IM uint32_t RESERVED1[3]; - - union { - __IOM uint32_t reg; /*!< GPIO pin configuration register */ - - struct { - __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ - __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - uint32_t : 2; - __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. - 1:trigger at posedge. 2:trigger at negedge. 3:trigger at - any edge. 4:valid at low level. 5:valid at high level */ - __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from - Light-sleep Mode) */ - __IOM uint32_t CONFIG : 2; /*!< reserved */ - __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not - shielded) interrupt. */ - uint32_t : 14; - } bit; - } PIN1; - __IM uint32_t RESERVED2[3]; - - union { - __IOM uint32_t reg; /*!< GPIO pin configuration register */ - - struct { - __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ - __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - uint32_t : 2; - __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. - 1:trigger at posedge. 2:trigger at negedge. 3:trigger at - any edge. 4:valid at low level. 5:valid at high level */ - __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from - Light-sleep Mode) */ - __IOM uint32_t CONFIG : 2; /*!< reserved */ - __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not - shielded) interrupt. */ - uint32_t : 14; - } bit; - } PIN2; - __IM uint32_t RESERVED3[3]; - - union { - __IOM uint32_t reg; /*!< GPIO pin configuration register */ - - struct { - __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ - __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - uint32_t : 2; - __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. - 1:trigger at posedge. 2:trigger at negedge. 3:trigger at - any edge. 4:valid at low level. 5:valid at high level */ - __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from - Light-sleep Mode) */ - __IOM uint32_t CONFIG : 2; /*!< reserved */ - __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not - shielded) interrupt. */ - uint32_t : 14; - } bit; - } PIN3; - __IM uint32_t RESERVED4[3]; - - union { - __IOM uint32_t reg; /*!< GPIO pin configuration register */ - - struct { - __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ - __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - uint32_t : 2; - __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. - 1:trigger at posedge. 2:trigger at negedge. 3:trigger at - any edge. 4:valid at low level. 5:valid at high level */ - __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from - Light-sleep Mode) */ - __IOM uint32_t CONFIG : 2; /*!< reserved */ - __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not - shielded) interrupt. */ - uint32_t : 14; - } bit; - } PIN4; - __IM uint32_t RESERVED5[3]; - - union { - __IOM uint32_t reg; /*!< GPIO pin configuration register */ - - struct { - __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ - __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - uint32_t : 2; - __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. - 1:trigger at posedge. 2:trigger at negedge. 3:trigger at - any edge. 4:valid at low level. 5:valid at high level */ - __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from - Light-sleep Mode) */ - __IOM uint32_t CONFIG : 2; /*!< reserved */ - __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not - shielded) interrupt. */ - uint32_t : 14; - } bit; - } PIN5; - __IM uint32_t RESERVED6[3]; - - union { - __IOM uint32_t reg; /*!< GPIO pin configuration register */ - - struct { - __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ - __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - uint32_t : 2; - __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. - 1:trigger at posedge. 2:trigger at negedge. 3:trigger at - any edge. 4:valid at low level. 5:valid at high level */ - __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from - Light-sleep Mode) */ - __IOM uint32_t CONFIG : 2; /*!< reserved */ - __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not - shielded) interrupt. */ - uint32_t : 14; - } bit; - } PIN6; - __IM uint32_t RESERVED7[3]; - - union { - __IOM uint32_t reg; /*!< GPIO pin configuration register */ - - struct { - __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ - __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - uint32_t : 2; - __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. - 1:trigger at posedge. 2:trigger at negedge. 3:trigger at - any edge. 4:valid at low level. 5:valid at high level */ - __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from - Light-sleep Mode) */ - __IOM uint32_t CONFIG : 2; /*!< reserved */ - __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not - shielded) interrupt. */ - uint32_t : 14; - } bit; - } PIN7; - __IM uint32_t RESERVED8[3]; - - union { - __IOM uint32_t reg; /*!< GPIO pin configuration register */ - - struct { - __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ - __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - uint32_t : 2; - __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. - 1:trigger at posedge. 2:trigger at negedge. 3:trigger at - any edge. 4:valid at low level. 5:valid at high level */ - __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from - Light-sleep Mode) */ - __IOM uint32_t CONFIG : 2; /*!< reserved */ - __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not - shielded) interrupt. */ - uint32_t : 14; - } bit; - } PIN8; - __IM uint32_t RESERVED9[3]; - - union { - __IOM uint32_t reg; /*!< GPIO pin configuration register */ - - struct { - __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ - __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - uint32_t : 2; - __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. - 1:trigger at posedge. 2:trigger at negedge. 3:trigger at - any edge. 4:valid at low level. 5:valid at high level */ - __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from - Light-sleep Mode) */ - __IOM uint32_t CONFIG : 2; /*!< reserved */ - __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not - shielded) interrupt. */ - uint32_t : 14; - } bit; - } PIN9; - __IM uint32_t RESERVED10[3]; - - union { - __IOM uint32_t reg; /*!< GPIO pin configuration register */ - - struct { - __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ - __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - uint32_t : 2; - __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. - 1:trigger at posedge. 2:trigger at negedge. 3:trigger at - any edge. 4:valid at low level. 5:valid at high level */ - __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from - Light-sleep Mode) */ - __IOM uint32_t CONFIG : 2; /*!< reserved */ - __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not - shielded) interrupt. */ - uint32_t : 14; - } bit; - } PIN10; - __IM uint32_t RESERVED11[3]; - - union { - __IOM uint32_t reg; /*!< GPIO pin configuration register */ - - struct { - __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ - __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - uint32_t : 2; - __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. - 1:trigger at posedge. 2:trigger at negedge. 3:trigger at - any edge. 4:valid at low level. 5:valid at high level */ - __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from - Light-sleep Mode) */ - __IOM uint32_t CONFIG : 2; /*!< reserved */ - __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not - shielded) interrupt. */ - uint32_t : 14; - } bit; - } PIN11; - __IM uint32_t RESERVED12[3]; - - union { - __IOM uint32_t reg; /*!< GPIO pin configuration register */ - - struct { - __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ - __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - uint32_t : 2; - __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. - 1:trigger at posedge. 2:trigger at negedge. 3:trigger at - any edge. 4:valid at low level. 5:valid at high level */ - __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from - Light-sleep Mode) */ - __IOM uint32_t CONFIG : 2; /*!< reserved */ - __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not - shielded) interrupt. */ - uint32_t : 14; - } bit; - } PIN12; - __IM uint32_t RESERVED13[3]; - - union { - __IOM uint32_t reg; /*!< GPIO pin configuration register */ - - struct { - __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ - __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - uint32_t : 2; - __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. - 1:trigger at posedge. 2:trigger at negedge. 3:trigger at - any edge. 4:valid at low level. 5:valid at high level */ - __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from - Light-sleep Mode) */ - __IOM uint32_t CONFIG : 2; /*!< reserved */ - __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not - shielded) interrupt. */ - uint32_t : 14; - } bit; - } PIN13; - __IM uint32_t RESERVED14[3]; - - union { - __IOM uint32_t reg; /*!< GPIO pin configuration register */ - - struct { - __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ - __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - uint32_t : 2; - __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. - 1:trigger at posedge. 2:trigger at negedge. 3:trigger at - any edge. 4:valid at low level. 5:valid at high level */ - __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from - Light-sleep Mode) */ - __IOM uint32_t CONFIG : 2; /*!< reserved */ - __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not - shielded) interrupt. */ - uint32_t : 14; - } bit; - } PIN14; - __IM uint32_t RESERVED15; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC1_IN_SEL_CFG; - __IM uint32_t RESERVED16; - - union { - __IOM uint32_t reg; /*!< GPIO pin configuration register */ - - struct { - __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ - __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - uint32_t : 2; - __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. - 1:trigger at posedge. 2:trigger at negedge. 3:trigger at - any edge. 4:valid at low level. 5:valid at high level */ - __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from - Light-sleep Mode) */ - __IOM uint32_t CONFIG : 2; /*!< reserved */ - __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not - shielded) interrupt. */ - uint32_t : 14; - } bit; - } PIN15; - __IM uint32_t RESERVED17; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC2_IN_SEL_CFG; - __IM uint32_t RESERVED18; - - union { - __IOM uint32_t reg; /*!< GPIO pin configuration register */ - - struct { - __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ - __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - uint32_t : 2; - __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. - 1:trigger at posedge. 2:trigger at negedge. 3:trigger at - any edge. 4:valid at low level. 5:valid at high level */ - __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from - Light-sleep Mode) */ - __IOM uint32_t CONFIG : 2; /*!< reserved */ - __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not - shielded) interrupt. */ - uint32_t : 14; - } bit; - } PIN16; - __IM uint32_t RESERVED19; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC3_IN_SEL_CFG; - __IM uint32_t RESERVED20; - - union { - __IOM uint32_t reg; /*!< GPIO pin configuration register */ - - struct { - __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ - __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - uint32_t : 2; - __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. - 1:trigger at posedge. 2:trigger at negedge. 3:trigger at - any edge. 4:valid at low level. 5:valid at high level */ - __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from - Light-sleep Mode) */ - __IOM uint32_t CONFIG : 2; /*!< reserved */ - __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not - shielded) interrupt. */ - uint32_t : 14; - } bit; - } PIN17; - __IM uint32_t RESERVED21; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC4_IN_SEL_CFG; - __IM uint32_t RESERVED22; - - union { - __IOM uint32_t reg; /*!< GPIO pin configuration register */ - - struct { - __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ - __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - uint32_t : 2; - __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. - 1:trigger at posedge. 2:trigger at negedge. 3:trigger at - any edge. 4:valid at low level. 5:valid at high level */ - __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from - Light-sleep Mode) */ - __IOM uint32_t CONFIG : 2; /*!< reserved */ - __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not - shielded) interrupt. */ - uint32_t : 14; - } bit; - } PIN18; - __IM uint32_t RESERVED23; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC5_IN_SEL_CFG; - __IM uint32_t RESERVED24; - - union { - __IOM uint32_t reg; /*!< GPIO pin configuration register */ - - struct { - __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ - __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - uint32_t : 2; - __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. - 1:trigger at posedge. 2:trigger at negedge. 3:trigger at - any edge. 4:valid at low level. 5:valid at high level */ - __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from - Light-sleep Mode) */ - __IOM uint32_t CONFIG : 2; /*!< reserved */ - __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not - shielded) interrupt. */ - uint32_t : 14; - } bit; - } PIN19; - __IM uint32_t RESERVED25; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC6_IN_SEL_CFG; - __IM uint32_t RESERVED26; - - union { - __IOM uint32_t reg; /*!< GPIO pin configuration register */ - - struct { - __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ - __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - uint32_t : 2; - __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. - 1:trigger at posedge. 2:trigger at negedge. 3:trigger at - any edge. 4:valid at low level. 5:valid at high level */ - __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from - Light-sleep Mode) */ - __IOM uint32_t CONFIG : 2; /*!< reserved */ - __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not - shielded) interrupt. */ - uint32_t : 14; - } bit; - } PIN20; - __IM uint32_t RESERVED27; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC7_IN_SEL_CFG; - __IM uint32_t RESERVED28; - - union { - __IOM uint32_t reg; /*!< GPIO pin configuration register */ - - struct { - __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ - __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - uint32_t : 2; - __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. - 1:trigger at posedge. 2:trigger at negedge. 3:trigger at - any edge. 4:valid at low level. 5:valid at high level */ - __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from - Light-sleep Mode) */ - __IOM uint32_t CONFIG : 2; /*!< reserved */ - __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not - shielded) interrupt. */ - uint32_t : 14; - } bit; - } PIN21; - __IM uint32_t RESERVED29; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC8_IN_SEL_CFG; - __IM uint32_t RESERVED30; - - union { - __IOM uint32_t reg; /*!< GPIO pin configuration register */ - - struct { - __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ - __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - uint32_t : 2; - __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. - 1:trigger at posedge. 2:trigger at negedge. 3:trigger at - any edge. 4:valid at low level. 5:valid at high level */ - __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from - Light-sleep Mode) */ - __IOM uint32_t CONFIG : 2; /*!< reserved */ - __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not - shielded) interrupt. */ - uint32_t : 14; - } bit; - } PIN22; - __IM uint32_t RESERVED31; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC9_IN_SEL_CFG; - __IM uint32_t RESERVED32; - - union { - __IOM uint32_t reg; /*!< GPIO pin configuration register */ - - struct { - __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ - __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - uint32_t : 2; - __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. - 1:trigger at posedge. 2:trigger at negedge. 3:trigger at - any edge. 4:valid at low level. 5:valid at high level */ - __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from - Light-sleep Mode) */ - __IOM uint32_t CONFIG : 2; /*!< reserved */ - __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not - shielded) interrupt. */ - uint32_t : 14; - } bit; - } PIN23; - __IM uint32_t RESERVED33; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC10_IN_SEL_CFG; - __IM uint32_t RESERVED34; - - union { - __IOM uint32_t reg; /*!< GPIO pin configuration register */ - - struct { - __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ - __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - uint32_t : 2; - __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. - 1:trigger at posedge. 2:trigger at negedge. 3:trigger at - any edge. 4:valid at low level. 5:valid at high level */ - __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from - Light-sleep Mode) */ - __IOM uint32_t CONFIG : 2; /*!< reserved */ - __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not - shielded) interrupt. */ - uint32_t : 14; - } bit; - } PIN24; - __IM uint32_t RESERVED35; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC11_IN_SEL_CFG; - __IM uint32_t RESERVED36; - - union { - __IOM uint32_t reg; /*!< GPIO pin configuration register */ - - struct { - __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ - __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - uint32_t : 2; - __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. - 1:trigger at posedge. 2:trigger at negedge. 3:trigger at - any edge. 4:valid at low level. 5:valid at high level */ - __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from - Light-sleep Mode) */ - __IOM uint32_t CONFIG : 2; /*!< reserved */ - __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not - shielded) interrupt. */ - uint32_t : 14; - } bit; - } PIN25; - __IM uint32_t RESERVED37; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC12_IN_SEL_CFG; - __IM uint32_t RESERVED38; - - union { - __IOM uint32_t reg; /*!< GPIO pin configuration register */ - - struct { - __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ - __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - uint32_t : 2; - __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. - 1:trigger at posedge. 2:trigger at negedge. 3:trigger at - any edge. 4:valid at low level. 5:valid at high level */ - __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from - Light-sleep Mode) */ - __IOM uint32_t CONFIG : 2; /*!< reserved */ - __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not - shielded) interrupt. */ - uint32_t : 14; - } bit; - } PIN26; - __IM uint32_t RESERVED39; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC13_IN_SEL_CFG; - __IM uint32_t RESERVED40; - - union { - __IOM uint32_t reg; /*!< GPIO pin configuration register */ - - struct { - __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ - __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - uint32_t : 2; - __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. - 1:trigger at posedge. 2:trigger at negedge. 3:trigger at - any edge. 4:valid at low level. 5:valid at high level */ - __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from - Light-sleep Mode) */ - __IOM uint32_t CONFIG : 2; /*!< reserved */ - __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not - shielded) interrupt. */ - uint32_t : 14; - } bit; - } PIN27; - __IM uint32_t RESERVED41; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC14_IN_SEL_CFG; - __IM uint32_t RESERVED42; - - union { - __IOM uint32_t reg; /*!< GPIO pin configuration register */ - - struct { - __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ - __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - uint32_t : 2; - __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. - 1:trigger at posedge. 2:trigger at negedge. 3:trigger at - any edge. 4:valid at low level. 5:valid at high level */ - __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from - Light-sleep Mode) */ - __IOM uint32_t CONFIG : 2; /*!< reserved */ - __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not - shielded) interrupt. */ - uint32_t : 14; - } bit; - } PIN28; - __IM uint32_t RESERVED43; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC15_IN_SEL_CFG; - __IM uint32_t RESERVED44; - - union { - __IOM uint32_t reg; /*!< GPIO pin configuration register */ - - struct { - __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ - __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - uint32_t : 2; - __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. - 1:trigger at posedge. 2:trigger at negedge. 3:trigger at - any edge. 4:valid at low level. 5:valid at high level */ - __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from - Light-sleep Mode) */ - __IOM uint32_t CONFIG : 2; /*!< reserved */ - __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not - shielded) interrupt. */ - uint32_t : 14; - } bit; - } PIN29; - __IM uint32_t RESERVED45; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC16_IN_SEL_CFG; - __IM uint32_t RESERVED46; - - union { - __IOM uint32_t reg; /*!< GPIO pin configuration register */ - - struct { - __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ - __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - uint32_t : 2; - __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. - 1:trigger at posedge. 2:trigger at negedge. 3:trigger at - any edge. 4:valid at low level. 5:valid at high level */ - __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from - Light-sleep Mode) */ - __IOM uint32_t CONFIG : 2; /*!< reserved */ - __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not - shielded) interrupt. */ - uint32_t : 14; - } bit; - } PIN30; - __IM uint32_t RESERVED47; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC17_IN_SEL_CFG; - __IM uint32_t RESERVED48; - - union { - __IOM uint32_t reg; /*!< GPIO pin configuration register */ - - struct { - __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ - __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - uint32_t : 2; - __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. - 1:trigger at posedge. 2:trigger at negedge. 3:trigger at - any edge. 4:valid at low level. 5:valid at high level */ - __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from - Light-sleep Mode) */ - __IOM uint32_t CONFIG : 2; /*!< reserved */ - __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not - shielded) interrupt. */ - uint32_t : 14; - } bit; - } PIN31; - __IM uint32_t RESERVED49; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC18_IN_SEL_CFG; - __IM uint32_t RESERVED50; - - union { - __IOM uint32_t reg; /*!< GPIO pin configuration register */ - - struct { - __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ - __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - uint32_t : 2; - __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. - 1:trigger at posedge. 2:trigger at negedge. 3:trigger at - any edge. 4:valid at low level. 5:valid at high level */ - __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from - Light-sleep Mode) */ - __IOM uint32_t CONFIG : 2; /*!< reserved */ - __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not - shielded) interrupt. */ - uint32_t : 14; - } bit; - } PIN32; - __IM uint32_t RESERVED51; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC19_IN_SEL_CFG; - __IM uint32_t RESERVED52; - - union { - __IOM uint32_t reg; /*!< GPIO pin configuration register */ - - struct { - __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ - __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - uint32_t : 2; - __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. - 1:trigger at posedge. 2:trigger at negedge. 3:trigger at - any edge. 4:valid at low level. 5:valid at high level */ - __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from - Light-sleep Mode) */ - __IOM uint32_t CONFIG : 2; /*!< reserved */ - __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not - shielded) interrupt. */ - uint32_t : 14; - } bit; - } PIN33; - __IM uint32_t RESERVED53; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC20_IN_SEL_CFG; - __IM uint32_t RESERVED54; - - union { - __IOM uint32_t reg; /*!< GPIO pin configuration register */ - - struct { - __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ - __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - uint32_t : 2; - __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. - 1:trigger at posedge. 2:trigger at negedge. 3:trigger at - any edge. 4:valid at low level. 5:valid at high level */ - __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from - Light-sleep Mode) */ - __IOM uint32_t CONFIG : 2; /*!< reserved */ - __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not - shielded) interrupt. */ - uint32_t : 14; - } bit; - } PIN34; - __IM uint32_t RESERVED55; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC21_IN_SEL_CFG; - __IM uint32_t RESERVED56; - - union { - __IOM uint32_t reg; /*!< GPIO pin configuration register */ - - struct { - __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ - __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - uint32_t : 2; - __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. - 1:trigger at posedge. 2:trigger at negedge. 3:trigger at - any edge. 4:valid at low level. 5:valid at high level */ - __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from - Light-sleep Mode) */ - __IOM uint32_t CONFIG : 2; /*!< reserved */ - __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not - shielded) interrupt. */ - uint32_t : 14; - } bit; - } PIN35; - __IM uint32_t RESERVED57; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC22_IN_SEL_CFG; - __IM uint32_t RESERVED58; - - union { - __IOM uint32_t reg; /*!< GPIO pin configuration register */ - - struct { - __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ - __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - uint32_t : 2; - __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. - 1:trigger at posedge. 2:trigger at negedge. 3:trigger at - any edge. 4:valid at low level. 5:valid at high level */ - __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from - Light-sleep Mode) */ - __IOM uint32_t CONFIG : 2; /*!< reserved */ - __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not - shielded) interrupt. */ - uint32_t : 14; - } bit; - } PIN36; - __IM uint32_t RESERVED59; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC23_IN_SEL_CFG; - __IM uint32_t RESERVED60; - - union { - __IOM uint32_t reg; /*!< GPIO pin configuration register */ - - struct { - __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ - __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - uint32_t : 2; - __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. - 1:trigger at posedge. 2:trigger at negedge. 3:trigger at - any edge. 4:valid at low level. 5:valid at high level */ - __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from - Light-sleep Mode) */ - __IOM uint32_t CONFIG : 2; /*!< reserved */ - __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not - shielded) interrupt. */ - uint32_t : 14; - } bit; - } PIN37; - __IM uint32_t RESERVED61; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC24_IN_SEL_CFG; - __IM uint32_t RESERVED62; - - union { - __IOM uint32_t reg; /*!< GPIO pin configuration register */ - - struct { - __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ - __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - uint32_t : 2; - __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. - 1:trigger at posedge. 2:trigger at negedge. 3:trigger at - any edge. 4:valid at low level. 5:valid at high level */ - __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from - Light-sleep Mode) */ - __IOM uint32_t CONFIG : 2; /*!< reserved */ - __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not - shielded) interrupt. */ - uint32_t : 14; - } bit; - } PIN38; - __IM uint32_t RESERVED63; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC25_IN_SEL_CFG; - __IM uint32_t RESERVED64; - - union { - __IOM uint32_t reg; /*!< GPIO pin configuration register */ - - struct { - __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ - __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - uint32_t : 2; - __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. - 1:trigger at posedge. 2:trigger at negedge. 3:trigger at - any edge. 4:valid at low level. 5:valid at high level */ - __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from - Light-sleep Mode) */ - __IOM uint32_t CONFIG : 2; /*!< reserved */ - __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not - shielded) interrupt. */ - uint32_t : 14; - } bit; - } PIN39; - __IM uint32_t RESERVED65; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC26_IN_SEL_CFG; - __IM uint32_t RESERVED66; - - union { - __IOM uint32_t reg; /*!< GPIO pin configuration register */ - - struct { - __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ - __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - uint32_t : 2; - __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. - 1:trigger at posedge. 2:trigger at negedge. 3:trigger at - any edge. 4:valid at low level. 5:valid at high level */ - __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from - Light-sleep Mode) */ - __IOM uint32_t CONFIG : 2; /*!< reserved */ - __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not - shielded) interrupt. */ - uint32_t : 14; - } bit; - } PIN40; - __IM uint32_t RESERVED67; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC27_IN_SEL_CFG; - __IM uint32_t RESERVED68; - - union { - __IOM uint32_t reg; /*!< GPIO pin configuration register */ - - struct { - __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ - __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - uint32_t : 2; - __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. - 1:trigger at posedge. 2:trigger at negedge. 3:trigger at - any edge. 4:valid at low level. 5:valid at high level */ - __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from - Light-sleep Mode) */ - __IOM uint32_t CONFIG : 2; /*!< reserved */ - __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not - shielded) interrupt. */ - uint32_t : 14; - } bit; - } PIN41; - __IM uint32_t RESERVED69; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC28_IN_SEL_CFG; - __IM uint32_t RESERVED70; - - union { - __IOM uint32_t reg; /*!< GPIO pin configuration register */ - - struct { - __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ - __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - uint32_t : 2; - __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. - 1:trigger at posedge. 2:trigger at negedge. 3:trigger at - any edge. 4:valid at low level. 5:valid at high level */ - __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from - Light-sleep Mode) */ - __IOM uint32_t CONFIG : 2; /*!< reserved */ - __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not - shielded) interrupt. */ - uint32_t : 14; - } bit; - } PIN42; - __IM uint32_t RESERVED71; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC29_IN_SEL_CFG; - __IM uint32_t RESERVED72; - - union { - __IOM uint32_t reg; /*!< GPIO pin configuration register */ - - struct { - __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ - __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - uint32_t : 2; - __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. - 1:trigger at posedge. 2:trigger at negedge. 3:trigger at - any edge. 4:valid at low level. 5:valid at high level */ - __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from - Light-sleep Mode) */ - __IOM uint32_t CONFIG : 2; /*!< reserved */ - __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not - shielded) interrupt. */ - uint32_t : 14; - } bit; - } PIN43; - __IM uint32_t RESERVED73; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC30_IN_SEL_CFG; - __IM uint32_t RESERVED74; - - union { - __IOM uint32_t reg; /*!< GPIO pin configuration register */ - - struct { - __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ - __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - uint32_t : 2; - __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. - 1:trigger at posedge. 2:trigger at negedge. 3:trigger at - any edge. 4:valid at low level. 5:valid at high level */ - __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from - Light-sleep Mode) */ - __IOM uint32_t CONFIG : 2; /*!< reserved */ - __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not - shielded) interrupt. */ - uint32_t : 14; - } bit; - } PIN44; - __IM uint32_t RESERVED75; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC31_IN_SEL_CFG; - __IM uint32_t RESERVED76; - - union { - __IOM uint32_t reg; /*!< GPIO pin configuration register */ - - struct { - __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ - __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - uint32_t : 2; - __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. - 1:trigger at posedge. 2:trigger at negedge. 3:trigger at - any edge. 4:valid at low level. 5:valid at high level */ - __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from - Light-sleep Mode) */ - __IOM uint32_t CONFIG : 2; /*!< reserved */ - __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not - shielded) interrupt. */ - uint32_t : 14; - } bit; - } PIN45; - __IM uint32_t RESERVED77; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC32_IN_SEL_CFG; - __IM uint32_t RESERVED78; - - union { - __IOM uint32_t reg; /*!< GPIO pin configuration register */ - - struct { - __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ - __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - uint32_t : 2; - __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. - 1:trigger at posedge. 2:trigger at negedge. 3:trigger at - any edge. 4:valid at low level. 5:valid at high level */ - __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from - Light-sleep Mode) */ - __IOM uint32_t CONFIG : 2; /*!< reserved */ - __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not - shielded) interrupt. */ - uint32_t : 14; - } bit; - } PIN46; - __IM uint32_t RESERVED79; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC33_IN_SEL_CFG; - __IM uint32_t RESERVED80; - - union { - __IOM uint32_t reg; /*!< GPIO pin configuration register */ - - struct { - __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ - __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - uint32_t : 2; - __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. - 1:trigger at posedge. 2:trigger at negedge. 3:trigger at - any edge. 4:valid at low level. 5:valid at high level */ - __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from - Light-sleep Mode) */ - __IOM uint32_t CONFIG : 2; /*!< reserved */ - __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not - shielded) interrupt. */ - uint32_t : 14; - } bit; - } PIN47; - __IM uint32_t RESERVED81; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC34_IN_SEL_CFG; - __IM uint32_t RESERVED82; - - union { - __IOM uint32_t reg; /*!< GPIO pin configuration register */ - - struct { - __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ - __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - uint32_t : 2; - __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. - 1:trigger at posedge. 2:trigger at negedge. 3:trigger at - any edge. 4:valid at low level. 5:valid at high level */ - __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from - Light-sleep Mode) */ - __IOM uint32_t CONFIG : 2; /*!< reserved */ - __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not - shielded) interrupt. */ - uint32_t : 14; - } bit; - } PIN48; - __IM uint32_t RESERVED83; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC35_IN_SEL_CFG; - __IM uint32_t RESERVED84; - - union { - __IOM uint32_t reg; /*!< GPIO pin configuration register */ - - struct { - __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ - __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - uint32_t : 2; - __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. - 1:trigger at posedge. 2:trigger at negedge. 3:trigger at - any edge. 4:valid at low level. 5:valid at high level */ - __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from - Light-sleep Mode) */ - __IOM uint32_t CONFIG : 2; /*!< reserved */ - __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not - shielded) interrupt. */ - uint32_t : 14; - } bit; - } PIN49; - __IM uint32_t RESERVED85; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC36_IN_SEL_CFG; - __IM uint32_t RESERVED86; - - union { - __IOM uint32_t reg; /*!< GPIO pin configuration register */ - - struct { - __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ - __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - uint32_t : 2; - __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. - 1:trigger at posedge. 2:trigger at negedge. 3:trigger at - any edge. 4:valid at low level. 5:valid at high level */ - __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from - Light-sleep Mode) */ - __IOM uint32_t CONFIG : 2; /*!< reserved */ - __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not - shielded) interrupt. */ - uint32_t : 14; - } bit; - } PIN50; - __IM uint32_t RESERVED87; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC37_IN_SEL_CFG; - __IM uint32_t RESERVED88; - - union { - __IOM uint32_t reg; /*!< GPIO pin configuration register */ - - struct { - __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ - __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - uint32_t : 2; - __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. - 1:trigger at posedge. 2:trigger at negedge. 3:trigger at - any edge. 4:valid at low level. 5:valid at high level */ - __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from - Light-sleep Mode) */ - __IOM uint32_t CONFIG : 2; /*!< reserved */ - __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not - shielded) interrupt. */ - uint32_t : 14; - } bit; - } PIN51; - __IM uint32_t RESERVED89; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC38_IN_SEL_CFG; - __IM uint32_t RESERVED90; - - union { - __IOM uint32_t reg; /*!< GPIO pin configuration register */ - - struct { - __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ - __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - uint32_t : 2; - __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. - 1:trigger at posedge. 2:trigger at negedge. 3:trigger at - any edge. 4:valid at low level. 5:valid at high level */ - __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from - Light-sleep Mode) */ - __IOM uint32_t CONFIG : 2; /*!< reserved */ - __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not - shielded) interrupt. */ - uint32_t : 14; - } bit; - } PIN52; - __IM uint32_t RESERVED91; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC39_IN_SEL_CFG; - __IM uint32_t RESERVED92; - - union { - __IOM uint32_t reg; /*!< GPIO pin configuration register */ - - struct { - __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ - __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - uint32_t : 2; - __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. - 1:trigger at posedge. 2:trigger at negedge. 3:trigger at - any edge. 4:valid at low level. 5:valid at high level */ - __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from - Light-sleep Mode) */ - __IOM uint32_t CONFIG : 2; /*!< reserved */ - __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not - shielded) interrupt. */ - uint32_t : 14; - } bit; - } PIN53; - __IM uint32_t RESERVED93; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC40_IN_SEL_CFG; - __IM uint32_t RESERVED94; - - union { - __IOM uint32_t reg; /*!< GPIO pin configuration register */ - - struct { - __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ - __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - uint32_t : 2; - __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. - 1:trigger at posedge. 2:trigger at negedge. 3:trigger at - any edge. 4:valid at low level. 5:valid at high level */ - __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from - Light-sleep Mode) */ - __IOM uint32_t CONFIG : 2; /*!< reserved */ - __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not - shielded) interrupt. */ - uint32_t : 14; - } bit; - } PIN54; - __IM uint32_t RESERVED95; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC41_IN_SEL_CFG; - __IM uint32_t RESERVED96; - - union { - __IOM uint32_t reg; /*!< GPIO pin configuration register */ - - struct { - __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ - __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - uint32_t : 2; - __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. - 1:trigger at posedge. 2:trigger at negedge. 3:trigger at - any edge. 4:valid at low level. 5:valid at high level */ - __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from - Light-sleep Mode) */ - __IOM uint32_t CONFIG : 2; /*!< reserved */ - __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not - shielded) interrupt. */ - uint32_t : 14; - } bit; - } PIN55; - __IM uint32_t RESERVED97; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC42_IN_SEL_CFG; - __IM uint32_t RESERVED98; - - union { - __IOM uint32_t reg; /*!< GPIO pin configuration register */ - - struct { - __IOM uint32_t SYNC2_BYPASS : 2; /*!< set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - __IOM uint32_t PAD_DRIVER : 1; /*!< set this bit to select pad driver. 1:open-drain. 0:normal. */ - __IOM uint32_t SYNC1_BYPASS : 2; /*!< set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. - 2or3:trigger at posedge. */ - uint32_t : 2; - __IOM uint32_t INT_TYPE : 3; /*!< set this value to choose interrupt mode. 0:disable GPIO interrupt. - 1:trigger at posedge. 2:trigger at negedge. 3:trigger at - any edge. 4:valid at low level. 5:valid at high level */ - __IOM uint32_t WAKEUP_ENABLE : 1; /*!< set this bit to enable GPIO wakeup.(can only wakeup CPU from - Light-sleep Mode) */ - __IOM uint32_t CONFIG : 2; /*!< reserved */ - __IOM uint32_t INT_ENA : 5; /*!< set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not - shielded) interrupt. */ - uint32_t : 14; - } bit; - } PIN56; - __IM uint32_t RESERVED99; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC43_IN_SEL_CFG; - __IM uint32_t RESERVED100[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC44_IN_SEL_CFG; - __IM uint32_t RESERVED101[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC45_IN_SEL_CFG; - __IM uint32_t RESERVED102[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC46_IN_SEL_CFG; - __IM uint32_t RESERVED103[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC47_IN_SEL_CFG; - __IM uint32_t RESERVED104[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC48_IN_SEL_CFG; - __IM uint32_t RESERVED105[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC49_IN_SEL_CFG; - __IM uint32_t RESERVED106[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC50_IN_SEL_CFG; - __IM uint32_t RESERVED107[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC51_IN_SEL_CFG; - __IM uint32_t RESERVED108[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC52_IN_SEL_CFG; - __IM uint32_t RESERVED109[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC53_IN_SEL_CFG; - __IM uint32_t RESERVED110[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC54_IN_SEL_CFG; - __IM uint32_t RESERVED111[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC55_IN_SEL_CFG; - __IM uint32_t RESERVED112[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC56_IN_SEL_CFG; - __IM uint32_t RESERVED113[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC57_IN_SEL_CFG; - __IM uint32_t RESERVED114[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC58_IN_SEL_CFG; - __IM uint32_t RESERVED115[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC59_IN_SEL_CFG; - __IM uint32_t RESERVED116[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC60_IN_SEL_CFG; - __IM uint32_t RESERVED117[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC61_IN_SEL_CFG; - __IM uint32_t RESERVED118[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC62_IN_SEL_CFG; - __IM uint32_t RESERVED119[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC63_IN_SEL_CFG; - __IM uint32_t RESERVED120[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC64_IN_SEL_CFG; - __IM uint32_t RESERVED121[2]; - - union { - __IOM uint32_t reg; /*!< GPIO output function select register */ - - struct { - __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output - signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. - s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ - __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ - __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] - as output enable signal.0:use peripheral output enable - signal. */ - __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ - uint32_t : 20; - } bit; - } FUNC0_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC65_IN_SEL_CFG; - __IM uint32_t RESERVED122[2]; - - union { - __IOM uint32_t reg; /*!< GPIO output function select register */ - - struct { - __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output - signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. - s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ - __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ - __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] - as output enable signal.0:use peripheral output enable - signal. */ - __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ - uint32_t : 20; - } bit; - } FUNC1_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC66_IN_SEL_CFG; - __IM uint32_t RESERVED123[2]; - - union { - __IOM uint32_t reg; /*!< GPIO output function select register */ - - struct { - __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output - signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. - s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ - __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ - __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] - as output enable signal.0:use peripheral output enable - signal. */ - __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ - uint32_t : 20; - } bit; - } FUNC2_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC67_IN_SEL_CFG; - __IM uint32_t RESERVED124[2]; - - union { - __IOM uint32_t reg; /*!< GPIO output function select register */ - - struct { - __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output - signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. - s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ - __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ - __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] - as output enable signal.0:use peripheral output enable - signal. */ - __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ - uint32_t : 20; - } bit; - } FUNC3_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC68_IN_SEL_CFG; - __IM uint32_t RESERVED125[2]; - - union { - __IOM uint32_t reg; /*!< GPIO output function select register */ - - struct { - __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output - signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. - s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ - __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ - __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] - as output enable signal.0:use peripheral output enable - signal. */ - __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ - uint32_t : 20; - } bit; - } FUNC4_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC69_IN_SEL_CFG; - __IM uint32_t RESERVED126[2]; - - union { - __IOM uint32_t reg; /*!< GPIO output function select register */ - - struct { - __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output - signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. - s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ - __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ - __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] - as output enable signal.0:use peripheral output enable - signal. */ - __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ - uint32_t : 20; - } bit; - } FUNC5_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC70_IN_SEL_CFG; - __IM uint32_t RESERVED127[2]; - - union { - __IOM uint32_t reg; /*!< GPIO output function select register */ - - struct { - __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output - signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. - s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ - __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ - __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] - as output enable signal.0:use peripheral output enable - signal. */ - __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ - uint32_t : 20; - } bit; - } FUNC6_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC71_IN_SEL_CFG; - __IM uint32_t RESERVED128[2]; - - union { - __IOM uint32_t reg; /*!< GPIO output function select register */ - - struct { - __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output - signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. - s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ - __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ - __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] - as output enable signal.0:use peripheral output enable - signal. */ - __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ - uint32_t : 20; - } bit; - } FUNC7_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC72_IN_SEL_CFG; - __IM uint32_t RESERVED129[2]; - - union { - __IOM uint32_t reg; /*!< GPIO output function select register */ - - struct { - __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output - signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. - s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ - __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ - __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] - as output enable signal.0:use peripheral output enable - signal. */ - __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ - uint32_t : 20; - } bit; - } FUNC8_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC73_IN_SEL_CFG; - __IM uint32_t RESERVED130[2]; - - union { - __IOM uint32_t reg; /*!< GPIO output function select register */ - - struct { - __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output - signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. - s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ - __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ - __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] - as output enable signal.0:use peripheral output enable - signal. */ - __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ - uint32_t : 20; - } bit; - } FUNC9_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC74_IN_SEL_CFG; - __IM uint32_t RESERVED131[2]; - - union { - __IOM uint32_t reg; /*!< GPIO output function select register */ - - struct { - __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output - signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. - s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ - __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ - __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] - as output enable signal.0:use peripheral output enable - signal. */ - __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ - uint32_t : 20; - } bit; - } FUNC10_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC75_IN_SEL_CFG; - __IM uint32_t RESERVED132[2]; - - union { - __IOM uint32_t reg; /*!< GPIO output function select register */ - - struct { - __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output - signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. - s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ - __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ - __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] - as output enable signal.0:use peripheral output enable - signal. */ - __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ - uint32_t : 20; - } bit; - } FUNC11_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC76_IN_SEL_CFG; - __IM uint32_t RESERVED133[2]; - - union { - __IOM uint32_t reg; /*!< GPIO output function select register */ - - struct { - __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output - signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. - s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ - __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ - __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] - as output enable signal.0:use peripheral output enable - signal. */ - __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ - uint32_t : 20; - } bit; - } FUNC12_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC77_IN_SEL_CFG; - __IM uint32_t RESERVED134[2]; - - union { - __IOM uint32_t reg; /*!< GPIO output function select register */ - - struct { - __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output - signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. - s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ - __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ - __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] - as output enable signal.0:use peripheral output enable - signal. */ - __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ - uint32_t : 20; - } bit; - } FUNC13_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC78_IN_SEL_CFG; - __IM uint32_t RESERVED135[2]; - - union { - __IOM uint32_t reg; /*!< GPIO output function select register */ - - struct { - __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output - signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. - s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ - __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ - __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] - as output enable signal.0:use peripheral output enable - signal. */ - __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ - uint32_t : 20; - } bit; - } FUNC14_OUT_SEL_CFG; - - union { - union { - __IOM uint32_t reg; /*!< GPIO interrupt 2 status register for GPIO0-31 */ - - struct { - __IM uint32_t INT_2 : 32; /*!< GPIO interrupt 2 status register for GPIO0-31 */ - } bit; - } INTR_2; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC79_IN_SEL_CFG; - }; - - union { - __IOM uint32_t reg; /*!< GPIO interrupt 2 status register for GPIO32-56 */ - - struct { - __IM uint32_t INT1_2 : 25; /*!< GPIO interrupt 2 status register for GPIO32-56 */ - uint32_t : 7; - } bit; - } INTR1_2; - - union { - __IOM uint32_t reg; /*!< GPIO interrupt 3 status register for GPIO0-31 */ - - struct { - __IM uint32_t INT_3 : 32; /*!< GPIO interrupt 3 status register for GPIO0-31 */ - } bit; - } INTR_3; - - union { - union { - __IOM uint32_t reg; /*!< GPIO output function select register */ - - struct { - __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output - signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. - s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ - __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ - __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] - as output enable signal.0:use peripheral output enable - signal. */ - __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ - uint32_t : 20; - } bit; - } FUNC15_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< GPIO interrupt 3 status register for GPIO32-56 */ - - struct { - __IM uint32_t INT1_3 : 25; /*!< GPIO interrupt 3 status register for GPIO32-56 */ - uint32_t : 7; - } bit; - } INTR1_3; - }; - - union { - union { - __IOM uint32_t reg; /*!< GPIO clock gate register */ - - struct { - __IOM uint32_t CLK_EN : 1; /*!< set this bit to enable GPIO clock gate */ - uint32_t : 31; - } bit; - } CLOCK_GATE; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC80_IN_SEL_CFG; - }; - __IM uint32_t RESERVED136[2]; - - union { - __IOM uint32_t reg; /*!< GPIO output function select register */ - - struct { - __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output - signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. - s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ - __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ - __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] - as output enable signal.0:use peripheral output enable - signal. */ - __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ - uint32_t : 20; - } bit; - } FUNC16_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC81_IN_SEL_CFG; - __IM uint32_t RESERVED137[2]; - - union { - __IOM uint32_t reg; /*!< GPIO output function select register */ - - struct { - __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output - signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. - s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ - __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ - __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] - as output enable signal.0:use peripheral output enable - signal. */ - __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ - uint32_t : 20; - } bit; - } FUNC17_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC82_IN_SEL_CFG; - __IM uint32_t RESERVED138[2]; - - union { - __IOM uint32_t reg; /*!< GPIO output function select register */ - - struct { - __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output - signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. - s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ - __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ - __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] - as output enable signal.0:use peripheral output enable - signal. */ - __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ - uint32_t : 20; - } bit; - } FUNC18_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC83_IN_SEL_CFG; - __IM uint32_t RESERVED139[2]; - - union { - __IOM uint32_t reg; /*!< GPIO output function select register */ - - struct { - __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output - signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. - s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ - __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ - __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] - as output enable signal.0:use peripheral output enable - signal. */ - __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ - uint32_t : 20; - } bit; - } FUNC19_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC84_IN_SEL_CFG; - __IM uint32_t RESERVED140[2]; - - union { - __IOM uint32_t reg; /*!< GPIO output function select register */ - - struct { - __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output - signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. - s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ - __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ - __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] - as output enable signal.0:use peripheral output enable - signal. */ - __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ - uint32_t : 20; - } bit; - } FUNC20_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC85_IN_SEL_CFG; - __IM uint32_t RESERVED141[2]; - - union { - __IOM uint32_t reg; /*!< GPIO output function select register */ - - struct { - __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output - signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. - s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ - __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ - __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] - as output enable signal.0:use peripheral output enable - signal. */ - __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ - uint32_t : 20; - } bit; - } FUNC21_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC86_IN_SEL_CFG; - __IM uint32_t RESERVED142[2]; - - union { - __IOM uint32_t reg; /*!< GPIO output function select register */ - - struct { - __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output - signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. - s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ - __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ - __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] - as output enable signal.0:use peripheral output enable - signal. */ - __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ - uint32_t : 20; - } bit; - } FUNC22_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC87_IN_SEL_CFG; - __IM uint32_t RESERVED143[2]; - - union { - __IOM uint32_t reg; /*!< GPIO output function select register */ - - struct { - __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output - signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. - s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ - __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ - __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] - as output enable signal.0:use peripheral output enable - signal. */ - __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ - uint32_t : 20; - } bit; - } FUNC23_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC88_IN_SEL_CFG; - __IM uint32_t RESERVED144[2]; - - union { - __IOM uint32_t reg; /*!< GPIO output function select register */ - - struct { - __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output - signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. - s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ - __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ - __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] - as output enable signal.0:use peripheral output enable - signal. */ - __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ - uint32_t : 20; - } bit; - } FUNC24_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC89_IN_SEL_CFG; - __IM uint32_t RESERVED145[2]; - - union { - __IOM uint32_t reg; /*!< GPIO output function select register */ - - struct { - __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output - signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. - s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ - __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ - __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] - as output enable signal.0:use peripheral output enable - signal. */ - __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ - uint32_t : 20; - } bit; - } FUNC25_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC90_IN_SEL_CFG; - __IM uint32_t RESERVED146[2]; - - union { - __IOM uint32_t reg; /*!< GPIO output function select register */ - - struct { - __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output - signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. - s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ - __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ - __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] - as output enable signal.0:use peripheral output enable - signal. */ - __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ - uint32_t : 20; - } bit; - } FUNC26_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC91_IN_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< analog comparator interrupt raw */ - - struct { - __IOM uint32_t COMP0_NEG_INT_RAW : 1; /*!< analog comparator pos edge interrupt raw */ - __IOM uint32_t COMP0_POS_INT_RAW : 1; /*!< analog comparator neg edge interrupt raw */ - __IOM uint32_t COMP0_ALL_INT_RAW : 1; /*!< analog comparator neg or pos edge interrupt raw */ - __IOM uint32_t COMP1_NEG_INT_RAW : 1; /*!< analog comparator pos edge interrupt raw */ - __IOM uint32_t COMP1_POS_INT_RAW : 1; /*!< analog comparator neg edge interrupt raw */ - __IOM uint32_t COMP1_ALL_INT_RAW : 1; /*!< analog comparator neg or pos edge interrupt raw */ - __IOM uint32_t BISTOK_INT_RAW : 1; /*!< pad bistok interrupt raw */ - __IOM uint32_t BISTFAIL_INT_RAW : 1; /*!< pad bistfail interrupt raw */ - uint32_t : 24; - } bit; - } INT_RAW; - - union { - __IOM uint32_t reg; /*!< analog comparator interrupt status */ - - struct { - __IM uint32_t COMP0_NEG_INT_ST : 1; /*!< analog comparator pos edge interrupt status */ - __IM uint32_t COMP0_POS_INT_ST : 1; /*!< analog comparator neg edge interrupt status */ - __IM uint32_t COMP0_ALL_INT_ST : 1; /*!< analog comparator neg or pos edge interrupt status */ - __IM uint32_t COMP1_NEG_INT_ST : 1; /*!< analog comparator pos edge interrupt status */ - __IM uint32_t COMP1_POS_INT_ST : 1; /*!< analog comparator neg edge interrupt status */ - __IM uint32_t COMP1_ALL_INT_ST : 1; /*!< analog comparator neg or pos edge interrupt status */ - __IM uint32_t BISTOK_INT_ST : 1; /*!< pad bistok interrupt status */ - __IM uint32_t BISTFAIL_INT_ST : 1; /*!< pad bistfail interrupt status */ - uint32_t : 24; - } bit; - } INT_ST; - - union { - union { - __IOM uint32_t reg; /*!< GPIO output function select register */ - - struct { - __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output - signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. - s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ - __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ - __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] - as output enable signal.0:use peripheral output enable - signal. */ - __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ - uint32_t : 20; - } bit; - } FUNC27_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< analog comparator interrupt enable */ - - struct { - __IOM uint32_t COMP0_NEG_INT_ENA : 1; /*!< analog comparator pos edge interrupt enable */ - __IOM uint32_t COMP0_POS_INT_ENA : 1; /*!< analog comparator neg edge interrupt enable */ - __IOM uint32_t COMP0_ALL_INT_ENA : 1; /*!< analog comparator neg or pos edge interrupt enable */ - __IOM uint32_t COMP1_NEG_INT_ENA : 1; /*!< analog comparator pos edge interrupt enable */ - __IOM uint32_t COMP1_POS_INT_ENA : 1; /*!< analog comparator neg edge interrupt enable */ - __IOM uint32_t COMP1_ALL_INT_ENA : 1; /*!< analog comparator neg or pos edge interrupt enable */ - __IOM uint32_t BISTOK_INT_ENA : 1; /*!< pad bistok interrupt enable */ - __IOM uint32_t BISTFAIL_INT_ENA : 1; /*!< pad bistfail interrupt enable */ - uint32_t : 24; - } bit; - } INT_ENA; - }; - - union { - union { - __IOM uint32_t reg; /*!< analog comparator interrupt clear */ - - struct { - __OM uint32_t COMP0_NEG_INT_CLR : 1; /*!< analog comparator pos edge interrupt clear */ - __OM uint32_t COMP0_POS_INT_CLR : 1; /*!< analog comparator neg edge interrupt clear */ - __OM uint32_t COMP0_ALL_INT_CLR : 1; /*!< analog comparator neg or pos edge interrupt clear */ - __OM uint32_t COMP1_NEG_INT_CLR : 1; /*!< analog comparator pos edge interrupt clear */ - __OM uint32_t COMP1_POS_INT_CLR : 1; /*!< analog comparator neg edge interrupt clear */ - __OM uint32_t COMP1_ALL_INT_CLR : 1; /*!< analog comparator neg or pos edge interrupt clear */ - __OM uint32_t BISTOK_INT_CLR : 1; /*!< pad bistok interrupt enable */ - __OM uint32_t BISTFAIL_INT_CLR : 1; /*!< pad bistfail interrupt enable */ - uint32_t : 24; - } bit; - } INT_CLR; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC92_IN_SEL_CFG; - }; - - union { - __IOM uint32_t reg; /*!< GPIO analog comparator zero detect filter count */ - - struct { - __IOM uint32_t ZERO_DET0_FILTER_CNT : 32; /*!< GPIO analog comparator zero detect filter count */ - } bit; - } ZERO_DET0_FILTER_CNT; - - union { - __IOM uint32_t reg; /*!< GPIO analog comparator zero detect filter count */ - - struct { - __IOM uint32_t ZERO_DET1_FILTER_CNT : 32; /*!< GPIO analog comparator zero detect filter count */ - } bit; - } ZERO_DET1_FILTER_CNT; - - union { - union { - __IOM uint32_t reg; /*!< GPIO output function select register */ - - struct { - __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output - signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. - s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ - __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ - __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] - as output enable signal.0:use peripheral output enable - signal. */ - __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ - uint32_t : 20; - } bit; - } FUNC28_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< High speed sdio pad bist send sequence */ - - struct { - __IOM uint32_t SEND_SEQ : 32; /*!< High speed sdio pad bist send sequence */ - } bit; - } SEND_SEQ; - }; - - union { - union { - __IOM uint32_t reg; /*!< High speed sdio pad bist recive sequence */ - - struct { - __IM uint32_t RECIVE_SEQ : 32; /*!< High speed sdio pad bist recive sequence */ - } bit; - } RECIVE_SEQ; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC93_IN_SEL_CFG; - }; - - union { - __IOM uint32_t reg; /*!< High speed sdio pad bist in pad sel */ - - struct { - __IOM uint32_t BISTIN_SEL : 4; /*!< High speed sdio pad bist in pad sel 0:pad39, 1: pad40... */ - uint32_t : 28; - } bit; - } BISTIN_SEL; - - union { - __IOM uint32_t reg; /*!< High speed sdio pad bist control */ - - struct { - __IOM uint32_t BIST_PAD_OE : 1; /*!< High speed sdio pad bist out pad oe */ - __OM uint32_t BIST_START : 1; /*!< High speed sdio pad bist start */ - uint32_t : 30; - } bit; - } BIST_CTRL; - - union { - __IOM uint32_t reg; /*!< GPIO output function select register */ - - struct { - __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output - signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. - s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ - __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ - __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] - as output enable signal.0:use peripheral output enable - signal. */ - __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ - uint32_t : 20; - } bit; - } FUNC29_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC94_IN_SEL_CFG; - __IM uint32_t RESERVED147[2]; - - union { - __IOM uint32_t reg; /*!< GPIO output function select register */ - - struct { - __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output - signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. - s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ - __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ - __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] - as output enable signal.0:use peripheral output enable - signal. */ - __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ - uint32_t : 20; - } bit; - } FUNC30_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC95_IN_SEL_CFG; - __IM uint32_t RESERVED148[2]; - - union { - __IOM uint32_t reg; /*!< GPIO output function select register */ - - struct { - __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output - signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. - s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ - __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ - __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] - as output enable signal.0:use peripheral output enable - signal. */ - __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ - uint32_t : 20; - } bit; - } FUNC31_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC96_IN_SEL_CFG; - __IM uint32_t RESERVED149[2]; - - union { - __IOM uint32_t reg; /*!< GPIO output function select register */ - - struct { - __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output - signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. - s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ - __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ - __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] - as output enable signal.0:use peripheral output enable - signal. */ - __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ - uint32_t : 20; - } bit; - } FUNC32_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC97_IN_SEL_CFG; - __IM uint32_t RESERVED150[2]; - - union { - __IOM uint32_t reg; /*!< GPIO output function select register */ - - struct { - __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output - signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. - s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ - __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ - __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] - as output enable signal.0:use peripheral output enable - signal. */ - __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ - uint32_t : 20; - } bit; - } FUNC33_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC98_IN_SEL_CFG; - __IM uint32_t RESERVED151[2]; - - union { - __IOM uint32_t reg; /*!< GPIO output function select register */ - - struct { - __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output - signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. - s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ - __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ - __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] - as output enable signal.0:use peripheral output enable - signal. */ - __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ - uint32_t : 20; - } bit; - } FUNC34_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC99_IN_SEL_CFG; - __IM uint32_t RESERVED152[2]; - - union { - __IOM uint32_t reg; /*!< GPIO output function select register */ - - struct { - __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output - signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. - s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ - __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ - __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] - as output enable signal.0:use peripheral output enable - signal. */ - __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ - uint32_t : 20; - } bit; - } FUNC35_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC100_IN_SEL_CFG; - __IM uint32_t RESERVED153[2]; - - union { - __IOM uint32_t reg; /*!< GPIO output function select register */ - - struct { - __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output - signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. - s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ - __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ - __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] - as output enable signal.0:use peripheral output enable - signal. */ - __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ - uint32_t : 20; - } bit; - } FUNC36_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC101_IN_SEL_CFG; - __IM uint32_t RESERVED154[2]; - - union { - __IOM uint32_t reg; /*!< GPIO output function select register */ - - struct { - __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output - signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. - s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ - __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ - __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] - as output enable signal.0:use peripheral output enable - signal. */ - __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ - uint32_t : 20; - } bit; - } FUNC37_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC102_IN_SEL_CFG; - __IM uint32_t RESERVED155[2]; - - union { - __IOM uint32_t reg; /*!< GPIO output function select register */ - - struct { - __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output - signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. - s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ - __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ - __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] - as output enable signal.0:use peripheral output enable - signal. */ - __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ - uint32_t : 20; - } bit; - } FUNC38_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC103_IN_SEL_CFG; - __IM uint32_t RESERVED156[2]; - - union { - __IOM uint32_t reg; /*!< GPIO output function select register */ - - struct { - __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output - signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. - s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ - __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ - __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] - as output enable signal.0:use peripheral output enable - signal. */ - __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ - uint32_t : 20; - } bit; - } FUNC39_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC104_IN_SEL_CFG; - __IM uint32_t RESERVED157[2]; - - union { - __IOM uint32_t reg; /*!< GPIO output function select register */ - - struct { - __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output - signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. - s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ - __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ - __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] - as output enable signal.0:use peripheral output enable - signal. */ - __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ - uint32_t : 20; - } bit; - } FUNC40_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC105_IN_SEL_CFG; - __IM uint32_t RESERVED158[2]; - - union { - __IOM uint32_t reg; /*!< GPIO output function select register */ - - struct { - __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output - signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. - s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ - __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ - __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] - as output enable signal.0:use peripheral output enable - signal. */ - __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ - uint32_t : 20; - } bit; - } FUNC41_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC106_IN_SEL_CFG; - __IM uint32_t RESERVED159[2]; - - union { - __IOM uint32_t reg; /*!< GPIO output function select register */ - - struct { - __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output - signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. - s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ - __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ - __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] - as output enable signal.0:use peripheral output enable - signal. */ - __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ - uint32_t : 20; - } bit; - } FUNC42_OUT_SEL_CFG; - - union { - union { - __IOM uint32_t reg; /*!< GPIO version register */ - - struct { - __IOM uint32_t DATE : 28; /*!< version register */ - uint32_t : 4; - } bit; - } DATE; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC107_IN_SEL_CFG; - }; - __IM uint32_t RESERVED160[2]; - - union { - __IOM uint32_t reg; /*!< GPIO output function select register */ - - struct { - __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output - signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. - s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ - __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ - __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] - as output enable signal.0:use peripheral output enable - signal. */ - __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ - uint32_t : 20; - } bit; - } FUNC43_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC108_IN_SEL_CFG; - __IM uint32_t RESERVED161[2]; - - union { - __IOM uint32_t reg; /*!< GPIO output function select register */ - - struct { - __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output - signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. - s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ - __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ - __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] - as output enable signal.0:use peripheral output enable - signal. */ - __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ - uint32_t : 20; - } bit; - } FUNC44_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC109_IN_SEL_CFG; - __IM uint32_t RESERVED162[2]; - - union { - __IOM uint32_t reg; /*!< GPIO output function select register */ - - struct { - __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output - signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. - s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ - __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ - __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] - as output enable signal.0:use peripheral output enable - signal. */ - __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ - uint32_t : 20; - } bit; - } FUNC45_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC110_IN_SEL_CFG; - __IM uint32_t RESERVED163[2]; - - union { - __IOM uint32_t reg; /*!< GPIO output function select register */ - - struct { - __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output - signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. - s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ - __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ - __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] - as output enable signal.0:use peripheral output enable - signal. */ - __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ - uint32_t : 20; - } bit; - } FUNC46_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC111_IN_SEL_CFG; - __IM uint32_t RESERVED164[2]; - - union { - __IOM uint32_t reg; /*!< GPIO output function select register */ - - struct { - __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output - signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. - s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ - __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ - __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] - as output enable signal.0:use peripheral output enable - signal. */ - __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ - uint32_t : 20; - } bit; - } FUNC47_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC112_IN_SEL_CFG; - __IM uint32_t RESERVED165[2]; - - union { - __IOM uint32_t reg; /*!< GPIO output function select register */ - - struct { - __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output - signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. - s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ - __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ - __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] - as output enable signal.0:use peripheral output enable - signal. */ - __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ - uint32_t : 20; - } bit; - } FUNC48_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC113_IN_SEL_CFG; - __IM uint32_t RESERVED166[2]; - - union { - __IOM uint32_t reg; /*!< GPIO output function select register */ - - struct { - __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output - signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. - s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ - __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ - __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] - as output enable signal.0:use peripheral output enable - signal. */ - __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ - uint32_t : 20; - } bit; - } FUNC49_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC114_IN_SEL_CFG; - __IM uint32_t RESERVED167[2]; - - union { - __IOM uint32_t reg; /*!< GPIO output function select register */ - - struct { - __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output - signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. - s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ - __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ - __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] - as output enable signal.0:use peripheral output enable - signal. */ - __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ - uint32_t : 20; - } bit; - } FUNC50_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC115_IN_SEL_CFG; - __IM uint32_t RESERVED168[2]; - - union { - __IOM uint32_t reg; /*!< GPIO output function select register */ - - struct { - __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output - signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. - s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ - __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ - __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] - as output enable signal.0:use peripheral output enable - signal. */ - __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ - uint32_t : 20; - } bit; - } FUNC51_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC116_IN_SEL_CFG; - __IM uint32_t RESERVED169[2]; - - union { - __IOM uint32_t reg; /*!< GPIO output function select register */ - - struct { - __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output - signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. - s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ - __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ - __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] - as output enable signal.0:use peripheral output enable - signal. */ - __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ - uint32_t : 20; - } bit; - } FUNC52_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC117_IN_SEL_CFG; - __IM uint32_t RESERVED170[2]; - - union { - __IOM uint32_t reg; /*!< GPIO output function select register */ - - struct { - __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output - signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. - s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ - __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ - __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] - as output enable signal.0:use peripheral output enable - signal. */ - __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ - uint32_t : 20; - } bit; - } FUNC53_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC118_IN_SEL_CFG; - __IM uint32_t RESERVED171[2]; - - union { - __IOM uint32_t reg; /*!< GPIO output function select register */ - - struct { - __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output - signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. - s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ - __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ - __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] - as output enable signal.0:use peripheral output enable - signal. */ - __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ - uint32_t : 20; - } bit; - } FUNC54_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC119_IN_SEL_CFG; - __IM uint32_t RESERVED172[2]; - - union { - __IOM uint32_t reg; /*!< GPIO output function select register */ - - struct { - __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output - signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. - s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ - __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ - __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] - as output enable signal.0:use peripheral output enable - signal. */ - __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ - uint32_t : 20; - } bit; - } FUNC55_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC120_IN_SEL_CFG; - __IM uint32_t RESERVED173[2]; - - union { - __IOM uint32_t reg; /*!< GPIO output function select register */ - - struct { - __IOM uint32_t OUT_SEL : 9; /*!< The value of the bits: 0<=s<=256. Set the value to select output - signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. - s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. */ - __IOM uint32_t INV_SEL : 1; /*!< set this bit to invert output signal.1:invert.0:not invert. */ - __IOM uint32_t OEN_SEL : 1; /*!< set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] - as output enable signal.0:use peripheral output enable - signal. */ - __IOM uint32_t OEN_INV_SEL : 1; /*!< set this bit to invert output enable signal.1:invert.0:not invert. */ - uint32_t : 20; - } bit; - } FUNC56_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC121_IN_SEL_CFG; - __IM uint32_t RESERVED174[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC122_IN_SEL_CFG; - __IM uint32_t RESERVED175[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC123_IN_SEL_CFG; - __IM uint32_t RESERVED176[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC124_IN_SEL_CFG; - __IM uint32_t RESERVED177[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC125_IN_SEL_CFG; - __IM uint32_t RESERVED178[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC126_IN_SEL_CFG; - __IM uint32_t RESERVED179[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC127_IN_SEL_CFG; - __IM uint32_t RESERVED180[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC128_IN_SEL_CFG; - __IM uint32_t RESERVED181[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC129_IN_SEL_CFG; - __IM uint32_t RESERVED182[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC130_IN_SEL_CFG; - __IM uint32_t RESERVED183[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC131_IN_SEL_CFG; - __IM uint32_t RESERVED184[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC132_IN_SEL_CFG; - __IM uint32_t RESERVED185[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC133_IN_SEL_CFG; - __IM uint32_t RESERVED186[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC134_IN_SEL_CFG; - __IM uint32_t RESERVED187[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC135_IN_SEL_CFG; - __IM uint32_t RESERVED188[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC136_IN_SEL_CFG; - __IM uint32_t RESERVED189[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC137_IN_SEL_CFG; - __IM uint32_t RESERVED190[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC138_IN_SEL_CFG; - __IM uint32_t RESERVED191[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC139_IN_SEL_CFG; - __IM uint32_t RESERVED192[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC140_IN_SEL_CFG; - __IM uint32_t RESERVED193[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC141_IN_SEL_CFG; - __IM uint32_t RESERVED194[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC142_IN_SEL_CFG; - __IM uint32_t RESERVED195[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC143_IN_SEL_CFG; - __IM uint32_t RESERVED196[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC144_IN_SEL_CFG; - __IM uint32_t RESERVED197[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC145_IN_SEL_CFG; - __IM uint32_t RESERVED198[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC146_IN_SEL_CFG; - __IM uint32_t RESERVED199[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC147_IN_SEL_CFG; - __IM uint32_t RESERVED200[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC148_IN_SEL_CFG; - __IM uint32_t RESERVED201[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC149_IN_SEL_CFG; - __IM uint32_t RESERVED202[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC150_IN_SEL_CFG; - __IM uint32_t RESERVED203[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC151_IN_SEL_CFG; - __IM uint32_t RESERVED204[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC152_IN_SEL_CFG; - __IM uint32_t RESERVED205[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC153_IN_SEL_CFG; - __IM uint32_t RESERVED206[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC154_IN_SEL_CFG; - __IM uint32_t RESERVED207[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC155_IN_SEL_CFG; - __IM uint32_t RESERVED208[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC156_IN_SEL_CFG; - __IM uint32_t RESERVED209[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC157_IN_SEL_CFG; - __IM uint32_t RESERVED210[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC158_IN_SEL_CFG; - __IM uint32_t RESERVED211[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC159_IN_SEL_CFG; - __IM uint32_t RESERVED212[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC160_IN_SEL_CFG; - __IM uint32_t RESERVED213[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC161_IN_SEL_CFG; - __IM uint32_t RESERVED214[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC162_IN_SEL_CFG; - __IM uint32_t RESERVED215[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC163_IN_SEL_CFG; - __IM uint32_t RESERVED216[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC164_IN_SEL_CFG; - __IM uint32_t RESERVED217[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC165_IN_SEL_CFG; - __IM uint32_t RESERVED218[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC166_IN_SEL_CFG; - __IM uint32_t RESERVED219[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC167_IN_SEL_CFG; - __IM uint32_t RESERVED220[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC168_IN_SEL_CFG; - __IM uint32_t RESERVED221[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC169_IN_SEL_CFG; - __IM uint32_t RESERVED222[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC170_IN_SEL_CFG; - __IM uint32_t RESERVED223[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC171_IN_SEL_CFG; - __IM uint32_t RESERVED224[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC172_IN_SEL_CFG; - __IM uint32_t RESERVED225[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC173_IN_SEL_CFG; - __IM uint32_t RESERVED226[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC174_IN_SEL_CFG; - __IM uint32_t RESERVED227[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC175_IN_SEL_CFG; - __IM uint32_t RESERVED228[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC176_IN_SEL_CFG; - __IM uint32_t RESERVED229[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC177_IN_SEL_CFG; - __IM uint32_t RESERVED230[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC178_IN_SEL_CFG; - __IM uint32_t RESERVED231[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC179_IN_SEL_CFG; - __IM uint32_t RESERVED232[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC180_IN_SEL_CFG; - __IM uint32_t RESERVED233[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC181_IN_SEL_CFG; - __IM uint32_t RESERVED234[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC182_IN_SEL_CFG; - __IM uint32_t RESERVED235[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC183_IN_SEL_CFG; - __IM uint32_t RESERVED236[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC184_IN_SEL_CFG; - __IM uint32_t RESERVED237[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC185_IN_SEL_CFG; - __IM uint32_t RESERVED238[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC186_IN_SEL_CFG; - __IM uint32_t RESERVED239[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC187_IN_SEL_CFG; - __IM uint32_t RESERVED240[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC188_IN_SEL_CFG; - __IM uint32_t RESERVED241[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC189_IN_SEL_CFG; - __IM uint32_t RESERVED242[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC190_IN_SEL_CFG; - __IM uint32_t RESERVED243[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC191_IN_SEL_CFG; - __IM uint32_t RESERVED244[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC192_IN_SEL_CFG; - __IM uint32_t RESERVED245[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC193_IN_SEL_CFG; - __IM uint32_t RESERVED246[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC194_IN_SEL_CFG; - __IM uint32_t RESERVED247[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC195_IN_SEL_CFG; - __IM uint32_t RESERVED248[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC196_IN_SEL_CFG; - __IM uint32_t RESERVED249[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC197_IN_SEL_CFG; - __IM uint32_t RESERVED250[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC198_IN_SEL_CFG; - __IM uint32_t RESERVED251[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC199_IN_SEL_CFG; - __IM uint32_t RESERVED252[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC200_IN_SEL_CFG; - __IM uint32_t RESERVED253[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC201_IN_SEL_CFG; - __IM uint32_t RESERVED254[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC202_IN_SEL_CFG; - __IM uint32_t RESERVED255[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC203_IN_SEL_CFG; - __IM uint32_t RESERVED256[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC204_IN_SEL_CFG; - __IM uint32_t RESERVED257[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC205_IN_SEL_CFG; - __IM uint32_t RESERVED258[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC206_IN_SEL_CFG; - __IM uint32_t RESERVED259[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC207_IN_SEL_CFG; - __IM uint32_t RESERVED260[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC208_IN_SEL_CFG; - __IM uint32_t RESERVED261[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC209_IN_SEL_CFG; - __IM uint32_t RESERVED262[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC210_IN_SEL_CFG; - __IM uint32_t RESERVED263[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC211_IN_SEL_CFG; - __IM uint32_t RESERVED264[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC212_IN_SEL_CFG; - __IM uint32_t RESERVED265[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC213_IN_SEL_CFG; - __IM uint32_t RESERVED266[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC214_IN_SEL_CFG; - __IM uint32_t RESERVED267[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC215_IN_SEL_CFG; - __IM uint32_t RESERVED268[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC216_IN_SEL_CFG; - __IM uint32_t RESERVED269[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC217_IN_SEL_CFG; - __IM uint32_t RESERVED270[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC218_IN_SEL_CFG; - __IM uint32_t RESERVED271[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC219_IN_SEL_CFG; - __IM uint32_t RESERVED272[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC220_IN_SEL_CFG; - __IM uint32_t RESERVED273[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC221_IN_SEL_CFG; - __IM uint32_t RESERVED274[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC222_IN_SEL_CFG; - __IM uint32_t RESERVED275[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC223_IN_SEL_CFG; - __IM uint32_t RESERVED276[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC224_IN_SEL_CFG; - __IM uint32_t RESERVED277[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC225_IN_SEL_CFG; - __IM uint32_t RESERVED278[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC226_IN_SEL_CFG; - __IM uint32_t RESERVED279[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC227_IN_SEL_CFG; - __IM uint32_t RESERVED280[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC228_IN_SEL_CFG; - __IM uint32_t RESERVED281[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC229_IN_SEL_CFG; - __IM uint32_t RESERVED282[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC230_IN_SEL_CFG; - __IM uint32_t RESERVED283[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC231_IN_SEL_CFG; - __IM uint32_t RESERVED284[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC232_IN_SEL_CFG; - __IM uint32_t RESERVED285[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC233_IN_SEL_CFG; - __IM uint32_t RESERVED286[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC234_IN_SEL_CFG; - __IM uint32_t RESERVED287[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC235_IN_SEL_CFG; - __IM uint32_t RESERVED288[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC236_IN_SEL_CFG; - __IM uint32_t RESERVED289[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC237_IN_SEL_CFG; - __IM uint32_t RESERVED290[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC238_IN_SEL_CFG; - __IM uint32_t RESERVED291[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC239_IN_SEL_CFG; - __IM uint32_t RESERVED292[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC240_IN_SEL_CFG; - __IM uint32_t RESERVED293[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC241_IN_SEL_CFG; - __IM uint32_t RESERVED294[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC242_IN_SEL_CFG; - __IM uint32_t RESERVED295[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC243_IN_SEL_CFG; - __IM uint32_t RESERVED296[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC244_IN_SEL_CFG; - __IM uint32_t RESERVED297[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC245_IN_SEL_CFG; - __IM uint32_t RESERVED298[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC246_IN_SEL_CFG; - __IM uint32_t RESERVED299[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC247_IN_SEL_CFG; - __IM uint32_t RESERVED300[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC248_IN_SEL_CFG; - __IM uint32_t RESERVED301[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC249_IN_SEL_CFG; - __IM uint32_t RESERVED302[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC250_IN_SEL_CFG; - __IM uint32_t RESERVED303[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC251_IN_SEL_CFG; - __IM uint32_t RESERVED304[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC252_IN_SEL_CFG; - __IM uint32_t RESERVED305[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC253_IN_SEL_CFG; - __IM uint32_t RESERVED306[3]; - - union { - __IOM uint32_t reg; /*!< GPIO input function configuration register */ - - struct { - __IOM uint32_t IN_SEL : 6; /*!< set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: - set this port always high level. s=0x3E: set this port - always low level. */ - __IOM uint32_t IN_INV_SEL : 1; /*!< set this bit to invert input signal. 1:invert. 0:not invert. */ - __IOM uint32_t SEL : 1; /*!< set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass - GPIO. */ - uint32_t : 24; - } bit; - } FUNC254_IN_SEL_CFG; -} GPIO_Type; /*!< Size = 4400 (0x1130) */ - - - -/* =========================================================================================================================== */ -/* ================ GPIO_SD ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Sigma-Delta Modulation (GPIO_SD) - */ - -typedef struct { /*!< GPIO_SD Structure */ - - union { - __IOM uint32_t reg; /*!< Duty Cycle Configure Register of SDM0 */ - - struct { - __IOM uint32_t SD_IN : 8; /*!< This field is used to configure the duty cycle of sigma delta - modulation output. */ - __IOM uint32_t SD_PRESCALE : 8; /*!< This field is used to set a divider value to divide APB clock. */ - uint32_t : 16; - } bit; - } SIGMADELTA0; - __IM uint32_t RESERVED[3]; - - union { - __IOM uint32_t reg; /*!< Duty Cycle Configure Register of SDM1 */ - - struct { - __IOM uint32_t SD_IN : 8; /*!< This field is used to configure the duty cycle of sigma delta - modulation output. */ - __IOM uint32_t SD_PRESCALE : 8; /*!< This field is used to set a divider value to divide APB clock. */ - uint32_t : 16; - } bit; - } SIGMADELTA1; - __IM uint32_t RESERVED1[3]; - - union { - union { - __IOM uint32_t reg; /*!< Duty Cycle Configure Register of SDM2 */ - - struct { - __IOM uint32_t SD_IN : 8; /*!< This field is used to configure the duty cycle of sigma delta - modulation output. */ - __IOM uint32_t SD_PRESCALE : 8; /*!< This field is used to set a divider value to divide APB clock. */ - uint32_t : 16; - } bit; - } SIGMADELTA2; - - union { - __IOM uint32_t reg; /*!< Clock Gating Configure Register */ - - struct { - __IOM uint32_t CLK_EN : 1; /*!< Clock enable bit of configuration registers for sigma delta - modulation. */ - uint32_t : 31; - } bit; - } CLOCK_GATE; - }; - - union { - __IOM uint32_t reg; /*!< MISC Register */ - - struct { - uint32_t : 30; - __IOM uint32_t FUNCTION_CLK_EN : 1; /*!< Clock enable bit of sigma delta modulation. */ - __IOM uint32_t SPI_SWAP : 1; /*!< Reserved. */ - } bit; - } SIGMADELTA_MISC; - __IM uint32_t RESERVED2[2]; - - union { - union { - __IOM uint32_t reg; /*!< Duty Cycle Configure Register of SDM3 */ - - struct { - __IOM uint32_t SD_IN : 8; /*!< This field is used to configure the duty cycle of sigma delta - modulation output. */ - __IOM uint32_t SD_PRESCALE : 8; /*!< This field is used to set a divider value to divide APB clock. */ - uint32_t : 16; - } bit; - } SIGMADELTA3; - - union { - __IOM uint32_t reg; /*!< Glitch Filter Configure Register of Channel0 */ - - struct { - __IOM uint32_t FILTER_CH0_EN : 1; /*!< Glitch Filter channel enable bit. */ - __IOM uint32_t FILTER_CH0_INPUT_IO_NUM : 6;/*!< Glitch Filter input io number. */ - __IOM uint32_t FILTER_CH0_WINDOW_THRES : 6;/*!< Glitch Filter window threshold. */ - __IOM uint32_t FILTER_CH0_WINDOW_WIDTH : 6;/*!< Glitch Filter window width. */ - uint32_t : 13; - } bit; - } GLITCH_FILTER_CH0; - }; - __IM uint32_t RESERVED3[3]; - - union { - union { - __IOM uint32_t reg; /*!< Duty Cycle Configure Register of SDM4 */ - - struct { - __IOM uint32_t SD_IN : 8; /*!< This field is used to configure the duty cycle of sigma delta - modulation output. */ - __IOM uint32_t SD_PRESCALE : 8; /*!< This field is used to set a divider value to divide APB clock. */ - uint32_t : 16; - } bit; - } SIGMADELTA4; - - union { - __IOM uint32_t reg; /*!< Glitch Filter Configure Register of Channel1 */ - - struct { - __IOM uint32_t FILTER_CH0_EN : 1; /*!< Glitch Filter channel enable bit. */ - __IOM uint32_t FILTER_CH0_INPUT_IO_NUM : 6;/*!< Glitch Filter input io number. */ - __IOM uint32_t FILTER_CH0_WINDOW_THRES : 6;/*!< Glitch Filter window threshold. */ - __IOM uint32_t FILTER_CH0_WINDOW_WIDTH : 6;/*!< Glitch Filter window width. */ - uint32_t : 13; - } bit; - } GLITCH_FILTER_CH1; - }; - __IM uint32_t RESERVED4[3]; - - union { - union { - __IOM uint32_t reg; /*!< Duty Cycle Configure Register of SDM5 */ - - struct { - __IOM uint32_t SD_IN : 8; /*!< This field is used to configure the duty cycle of sigma delta - modulation output. */ - __IOM uint32_t SD_PRESCALE : 8; /*!< This field is used to set a divider value to divide APB clock. */ - uint32_t : 16; - } bit; - } SIGMADELTA5; - - union { - __IOM uint32_t reg; /*!< Glitch Filter Configure Register of Channel2 */ - - struct { - __IOM uint32_t FILTER_CH0_EN : 1; /*!< Glitch Filter channel enable bit. */ - __IOM uint32_t FILTER_CH0_INPUT_IO_NUM : 6;/*!< Glitch Filter input io number. */ - __IOM uint32_t FILTER_CH0_WINDOW_THRES : 6;/*!< Glitch Filter window threshold. */ - __IOM uint32_t FILTER_CH0_WINDOW_WIDTH : 6;/*!< Glitch Filter window width. */ - uint32_t : 13; - } bit; - } GLITCH_FILTER_CH2; - }; - __IM uint32_t RESERVED5[3]; - - union { - union { - __IOM uint32_t reg; /*!< Duty Cycle Configure Register of SDM6 */ - - struct { - __IOM uint32_t SD_IN : 8; /*!< This field is used to configure the duty cycle of sigma delta - modulation output. */ - __IOM uint32_t SD_PRESCALE : 8; /*!< This field is used to set a divider value to divide APB clock. */ - uint32_t : 16; - } bit; - } SIGMADELTA6; - - union { - __IOM uint32_t reg; /*!< Glitch Filter Configure Register of Channel3 */ - - struct { - __IOM uint32_t FILTER_CH0_EN : 1; /*!< Glitch Filter channel enable bit. */ - __IOM uint32_t FILTER_CH0_INPUT_IO_NUM : 6;/*!< Glitch Filter input io number. */ - __IOM uint32_t FILTER_CH0_WINDOW_THRES : 6;/*!< Glitch Filter window threshold. */ - __IOM uint32_t FILTER_CH0_WINDOW_WIDTH : 6;/*!< Glitch Filter window width. */ - uint32_t : 13; - } bit; - } GLITCH_FILTER_CH3; - - union { - __IOM uint32_t reg; /*!< Etm Config register of Channel0 */ - - struct { - __IOM uint32_t ETM_CH0_EVENT_SEL : 6; /*!< Etm event channel select gpio. */ - uint32_t : 1; - __IOM uint32_t ETM_CH0_EVENT_EN : 1; /*!< Etm event send enable bit. */ - uint32_t : 24; - } bit; - } ETM_EVENT_CH0_CFG; - }; - __IM uint32_t RESERVED6[3]; - - union { - union { - __IOM uint32_t reg; /*!< Duty Cycle Configure Register of SDM7 */ - - struct { - __IOM uint32_t SD_IN : 8; /*!< This field is used to configure the duty cycle of sigma delta - modulation output. */ - __IOM uint32_t SD_PRESCALE : 8; /*!< This field is used to set a divider value to divide APB clock. */ - uint32_t : 16; - } bit; - } SIGMADELTA7; - - union { - __IOM uint32_t reg; /*!< Glitch Filter Configure Register of Channel4 */ - - struct { - __IOM uint32_t FILTER_CH0_EN : 1; /*!< Glitch Filter channel enable bit. */ - __IOM uint32_t FILTER_CH0_INPUT_IO_NUM : 6;/*!< Glitch Filter input io number. */ - __IOM uint32_t FILTER_CH0_WINDOW_THRES : 6;/*!< Glitch Filter window threshold. */ - __IOM uint32_t FILTER_CH0_WINDOW_WIDTH : 6;/*!< Glitch Filter window width. */ - uint32_t : 13; - } bit; - } GLITCH_FILTER_CH4; - - union { - __IOM uint32_t reg; /*!< Etm Config register of Channel1 */ - - struct { - __IOM uint32_t ETM_CH0_EVENT_SEL : 6; /*!< Etm event channel select gpio. */ - uint32_t : 1; - __IOM uint32_t ETM_CH0_EVENT_EN : 1; /*!< Etm event send enable bit. */ - uint32_t : 24; - } bit; - } ETM_EVENT_CH1_CFG; - }; - __IM uint32_t RESERVED7[3]; - - union { - union { - __IOM uint32_t reg; /*!< Glitch Filter Configure Register of Channel5 */ - - struct { - __IOM uint32_t FILTER_CH0_EN : 1; /*!< Glitch Filter channel enable bit. */ - __IOM uint32_t FILTER_CH0_INPUT_IO_NUM : 6;/*!< Glitch Filter input io number. */ - __IOM uint32_t FILTER_CH0_WINDOW_THRES : 6;/*!< Glitch Filter window threshold. */ - __IOM uint32_t FILTER_CH0_WINDOW_WIDTH : 6;/*!< Glitch Filter window width. */ - uint32_t : 13; - } bit; - } GLITCH_FILTER_CH5; - - union { - __IOM uint32_t reg; /*!< Etm Config register of Channel2 */ - - struct { - __IOM uint32_t ETM_CH0_EVENT_SEL : 6; /*!< Etm event channel select gpio. */ - uint32_t : 1; - __IOM uint32_t ETM_CH0_EVENT_EN : 1; /*!< Etm event send enable bit. */ - uint32_t : 24; - } bit; - } ETM_EVENT_CH2_CFG; - }; - __IM uint32_t RESERVED8[3]; - - union { - union { - __IOM uint32_t reg; /*!< Glitch Filter Configure Register of Channel6 */ - - struct { - __IOM uint32_t FILTER_CH0_EN : 1; /*!< Glitch Filter channel enable bit. */ - __IOM uint32_t FILTER_CH0_INPUT_IO_NUM : 6;/*!< Glitch Filter input io number. */ - __IOM uint32_t FILTER_CH0_WINDOW_THRES : 6;/*!< Glitch Filter window threshold. */ - __IOM uint32_t FILTER_CH0_WINDOW_WIDTH : 6;/*!< Glitch Filter window width. */ - uint32_t : 13; - } bit; - } GLITCH_FILTER_CH6; - - union { - __IOM uint32_t reg; /*!< Etm Config register of Channel3 */ - - struct { - __IOM uint32_t ETM_CH0_EVENT_SEL : 6; /*!< Etm event channel select gpio. */ - uint32_t : 1; - __IOM uint32_t ETM_CH0_EVENT_EN : 1; /*!< Etm event send enable bit. */ - uint32_t : 24; - } bit; - } ETM_EVENT_CH3_CFG; - }; - __IM uint32_t RESERVED9[3]; - - union { - union { - __IOM uint32_t reg; /*!< Glitch Filter Configure Register of Channel7 */ - - struct { - __IOM uint32_t FILTER_CH0_EN : 1; /*!< Glitch Filter channel enable bit. */ - __IOM uint32_t FILTER_CH0_INPUT_IO_NUM : 6;/*!< Glitch Filter input io number. */ - __IOM uint32_t FILTER_CH0_WINDOW_THRES : 6;/*!< Glitch Filter window threshold. */ - __IOM uint32_t FILTER_CH0_WINDOW_WIDTH : 6;/*!< Glitch Filter window width. */ - uint32_t : 13; - } bit; - } GLITCH_FILTER_CH7; - - union { - __IOM uint32_t reg; /*!< Etm Config register of Channel4 */ - - struct { - __IOM uint32_t ETM_CH0_EVENT_SEL : 6; /*!< Etm event channel select gpio. */ - uint32_t : 1; - __IOM uint32_t ETM_CH0_EVENT_EN : 1; /*!< Etm event send enable bit. */ - uint32_t : 24; - } bit; - } ETM_EVENT_CH4_CFG; - - union { - __IOM uint32_t reg; /*!< Etm Configure Register to decide which GPIO been chosen */ - - struct { - __IOM uint32_t ETM_TASK_GPIO0_EN : 1; /*!< Enable bit of GPIO response etm task. */ - __IOM uint32_t ETM_TASK_GPIO0_SEL : 3; /*!< GPIO choose a etm task channel. */ - uint32_t : 4; - __IOM uint32_t ETM_TASK_GPIO1_EN : 1; /*!< Enable bit of GPIO response etm task. */ - __IOM uint32_t ETM_TASK_GPIO1_SEL : 3; /*!< GPIO choose a etm task channel. */ - uint32_t : 4; - __IOM uint32_t ETM_TASK_GPIO2_EN : 1; /*!< Enable bit of GPIO response etm task. */ - __IOM uint32_t ETM_TASK_GPIO2_SEL : 3; /*!< GPIO choose a etm task channel. */ - uint32_t : 4; - __IOM uint32_t ETM_TASK_GPIO3_EN : 1; /*!< Enable bit of GPIO response etm task. */ - __IOM uint32_t ETM_TASK_GPIO3_SEL : 3; /*!< GPIO choose a etm task channel. */ - uint32_t : 4; - } bit; - } ETM_TASK_P0_CFG; - }; - - union { - __IOM uint32_t reg; /*!< Etm Configure Register to decide which GPIO been chosen */ - - struct { - __IOM uint32_t ETM_TASK_GPIO4_EN : 1; /*!< Enable bit of GPIO response etm task. */ - __IOM uint32_t ETM_TASK_GPIO4_SEL : 3; /*!< GPIO choose a etm task channel. */ - uint32_t : 4; - __IOM uint32_t ETM_TASK_GPIO5_EN : 1; /*!< Enable bit of GPIO response etm task. */ - __IOM uint32_t ETM_TASK_GPIO5_SEL : 3; /*!< GPIO choose a etm task channel. */ - uint32_t : 4; - __IOM uint32_t ETM_TASK_GPIO6_EN : 1; /*!< Enable bit of GPIO response etm task. */ - __IOM uint32_t ETM_TASK_GPIO6_SEL : 3; /*!< GPIO choose a etm task channel. */ - uint32_t : 4; - __IOM uint32_t ETM_TASK_GPIO7_EN : 1; /*!< Enable bit of GPIO response etm task. */ - __IOM uint32_t ETM_TASK_GPIO7_SEL : 3; /*!< GPIO choose a etm task channel. */ - uint32_t : 4; - } bit; - } ETM_TASK_P1_CFG; - - union { - __IOM uint32_t reg; /*!< Etm Configure Register to decide which GPIO been chosen */ - - struct { - __IOM uint32_t ETM_TASK_GPIO8_EN : 1; /*!< Enable bit of GPIO response etm task. */ - __IOM uint32_t ETM_TASK_GPIO8_SEL : 3; /*!< GPIO choose a etm task channel. */ - uint32_t : 4; - __IOM uint32_t ETM_TASK_GPIO9_EN : 1; /*!< Enable bit of GPIO response etm task. */ - __IOM uint32_t ETM_TASK_GPIO9_SEL : 3; /*!< GPIO choose a etm task channel. */ - uint32_t : 4; - __IOM uint32_t ETM_TASK_GPIO10_EN : 1; /*!< Enable bit of GPIO response etm task. */ - __IOM uint32_t ETM_TASK_GPIO10_SEL : 3; /*!< GPIO choose a etm task channel. */ - uint32_t : 4; - __IOM uint32_t ETM_TASK_GPIO11_EN : 1; /*!< Enable bit of GPIO response etm task. */ - __IOM uint32_t ETM_TASK_GPIO11_SEL : 3; /*!< GPIO choose a etm task channel. */ - uint32_t : 4; - } bit; - } ETM_TASK_P2_CFG; - - union { - __IOM uint32_t reg; /*!< Etm Configure Register to decide which GPIO been chosen */ - - struct { - __IOM uint32_t ETM_TASK_GPIO12_EN : 1; /*!< Enable bit of GPIO response etm task. */ - __IOM uint32_t ETM_TASK_GPIO12_SEL : 3; /*!< GPIO choose a etm task channel. */ - uint32_t : 4; - __IOM uint32_t ETM_TASK_GPIO13_EN : 1; /*!< Enable bit of GPIO response etm task. */ - __IOM uint32_t ETM_TASK_GPIO13_SEL : 3; /*!< GPIO choose a etm task channel. */ - uint32_t : 4; - __IOM uint32_t ETM_TASK_GPIO14_EN : 1; /*!< Enable bit of GPIO response etm task. */ - __IOM uint32_t ETM_TASK_GPIO14_SEL : 3; /*!< GPIO choose a etm task channel. */ - uint32_t : 4; - __IOM uint32_t ETM_TASK_GPIO15_EN : 1; /*!< Enable bit of GPIO response etm task. */ - __IOM uint32_t ETM_TASK_GPIO15_SEL : 3; /*!< GPIO choose a etm task channel. */ - uint32_t : 4; - } bit; - } ETM_TASK_P3_CFG; - - union { - union { - __IOM uint32_t reg; /*!< Etm Config register of Channel5 */ - - struct { - __IOM uint32_t ETM_CH0_EVENT_SEL : 6; /*!< Etm event channel select gpio. */ - uint32_t : 1; - __IOM uint32_t ETM_CH0_EVENT_EN : 1; /*!< Etm event send enable bit. */ - uint32_t : 24; - } bit; - } ETM_EVENT_CH5_CFG; - - union { - __IOM uint32_t reg; /*!< Etm Configure Register to decide which GPIO been chosen */ - - struct { - __IOM uint32_t ETM_TASK_GPIO16_EN : 1; /*!< Enable bit of GPIO response etm task. */ - __IOM uint32_t ETM_TASK_GPIO16_SEL : 3; /*!< GPIO choose a etm task channel. */ - uint32_t : 4; - __IOM uint32_t ETM_TASK_GPIO17_EN : 1; /*!< Enable bit of GPIO response etm task. */ - __IOM uint32_t ETM_TASK_GPIO17_SEL : 3; /*!< GPIO choose a etm task channel. */ - uint32_t : 4; - __IOM uint32_t ETM_TASK_GPIO18_EN : 1; /*!< Enable bit of GPIO response etm task. */ - __IOM uint32_t ETM_TASK_GPIO18_SEL : 3; /*!< GPIO choose a etm task channel. */ - uint32_t : 4; - __IOM uint32_t ETM_TASK_GPIO19_EN : 1; /*!< Enable bit of GPIO response etm task. */ - __IOM uint32_t ETM_TASK_GPIO19_SEL : 3; /*!< GPIO choose a etm task channel. */ - uint32_t : 4; - } bit; - } ETM_TASK_P4_CFG; - }; - - union { - __IOM uint32_t reg; /*!< Etm Configure Register to decide which GPIO been chosen */ - - struct { - __IOM uint32_t ETM_TASK_GPIO20_EN : 1; /*!< Enable bit of GPIO response etm task. */ - __IOM uint32_t ETM_TASK_GPIO20_SEL : 3; /*!< GPIO choose a etm task channel. */ - uint32_t : 4; - __IOM uint32_t ETM_TASK_GPIO21_EN : 1; /*!< Enable bit of GPIO response etm task. */ - __IOM uint32_t ETM_TASK_GPIO21_SEL : 3; /*!< GPIO choose a etm task channel. */ - uint32_t : 4; - __IOM uint32_t ETM_TASK_GPIO22_EN : 1; /*!< Enable bit of GPIO response etm task. */ - __IOM uint32_t ETM_TASK_GPIO22_SEL : 3; /*!< GPIO choose a etm task channel. */ - uint32_t : 4; - __IOM uint32_t ETM_TASK_GPIO23_EN : 1; /*!< Enable bit of GPIO response etm task. */ - __IOM uint32_t ETM_TASK_GPIO23_SEL : 3; /*!< GPIO choose a etm task channel. */ - uint32_t : 4; - } bit; - } ETM_TASK_P5_CFG; - - union { - __IOM uint32_t reg; /*!< Etm Configure Register to decide which GPIO been chosen */ - - struct { - __IOM uint32_t ETM_TASK_GPIO24_EN : 1; /*!< Enable bit of GPIO response etm task. */ - __IOM uint32_t ETM_TASK_GPIO24_SEL : 3; /*!< GPIO choose a etm task channel. */ - uint32_t : 4; - __IOM uint32_t ETM_TASK_GPIO25_EN : 1; /*!< Enable bit of GPIO response etm task. */ - __IOM uint32_t ETM_TASK_GPIO25_SEL : 3; /*!< GPIO choose a etm task channel. */ - uint32_t : 4; - __IOM uint32_t ETM_TASK_GPIO26_EN : 1; /*!< Enable bit of GPIO response etm task. */ - __IOM uint32_t ETM_TASK_GPIO26_SEL : 3; /*!< GPIO choose a etm task channel. */ - uint32_t : 4; - __IOM uint32_t ETM_TASK_GPIO27_EN : 1; /*!< Enable bit of GPIO response etm task. */ - __IOM uint32_t ETM_TASK_GPIO27_SEL : 3; /*!< GPIO choose a etm task channel. */ - uint32_t : 4; - } bit; - } ETM_TASK_P6_CFG; - - union { - __IOM uint32_t reg; /*!< Etm Configure Register to decide which GPIO been chosen */ - - struct { - __IOM uint32_t ETM_TASK_GPIO28_EN : 1; /*!< Enable bit of GPIO response etm task. */ - __IOM uint32_t ETM_TASK_GPIO28_SEL : 3; /*!< GPIO choose a etm task channel. */ - uint32_t : 4; - __IOM uint32_t ETM_TASK_GPIO29_EN : 1; /*!< Enable bit of GPIO response etm task. */ - __IOM uint32_t ETM_TASK_GPIO29_SEL : 3; /*!< GPIO choose a etm task channel. */ - uint32_t : 4; - __IOM uint32_t ETM_TASK_GPIO30_EN : 1; /*!< Enable bit of GPIO response etm task. */ - __IOM uint32_t ETM_TASK_GPIO30_SEL : 3; /*!< GPIO choose a etm task channel. */ - uint32_t : 4; - __IOM uint32_t ETM_TASK_GPIO31_EN : 1; /*!< Enable bit of GPIO response etm task. */ - __IOM uint32_t ETM_TASK_GPIO31_SEL : 3; /*!< GPIO choose a etm task channel. */ - uint32_t : 4; - } bit; - } ETM_TASK_P7_CFG; - - union { - union { - __IOM uint32_t reg; /*!< Etm Config register of Channel6 */ - - struct { - __IOM uint32_t ETM_CH0_EVENT_SEL : 6; /*!< Etm event channel select gpio. */ - uint32_t : 1; - __IOM uint32_t ETM_CH0_EVENT_EN : 1; /*!< Etm event send enable bit. */ - uint32_t : 24; - } bit; - } ETM_EVENT_CH6_CFG; - - union { - __IOM uint32_t reg; /*!< Etm Configure Register to decide which GPIO been chosen */ - - struct { - __IOM uint32_t ETM_TASK_GPIO32_EN : 1; /*!< Enable bit of GPIO response etm task. */ - __IOM uint32_t ETM_TASK_GPIO32_SEL : 3; /*!< GPIO choose a etm task channel. */ - uint32_t : 4; - __IOM uint32_t ETM_TASK_GPIO33_EN : 1; /*!< Enable bit of GPIO response etm task. */ - __IOM uint32_t ETM_TASK_GPIO33_SEL : 3; /*!< GPIO choose a etm task channel. */ - uint32_t : 4; - __IOM uint32_t ETM_TASK_GPIO34_EN : 1; /*!< Enable bit of GPIO response etm task. */ - __IOM uint32_t ETM_TASK_GPIO34_SEL : 3; /*!< GPIO choose a etm task channel. */ - uint32_t : 4; - __IOM uint32_t ETM_TASK_GPIO35_EN : 1; /*!< Enable bit of GPIO response etm task. */ - __IOM uint32_t ETM_TASK_GPIO35_SEL : 3; /*!< GPIO choose a etm task channel. */ - uint32_t : 4; - } bit; - } ETM_TASK_P8_CFG; - }; - - union { - __IOM uint32_t reg; /*!< Etm Configure Register to decide which GPIO been chosen */ - - struct { - __IOM uint32_t ETM_TASK_GPIO36_EN : 1; /*!< Enable bit of GPIO response etm task. */ - __IOM uint32_t ETM_TASK_GPIO36_SEL : 3; /*!< GPIO choose a etm task channel. */ - uint32_t : 4; - __IOM uint32_t ETM_TASK_GPIO37_EN : 1; /*!< Enable bit of GPIO response etm task. */ - __IOM uint32_t ETM_TASK_GPIO37_SEL : 3; /*!< GPIO choose a etm task channel. */ - uint32_t : 4; - __IOM uint32_t ETM_TASK_GPIO38_EN : 1; /*!< Enable bit of GPIO response etm task. */ - __IOM uint32_t ETM_TASK_GPIO38_SEL : 3; /*!< GPIO choose a etm task channel. */ - uint32_t : 4; - __IOM uint32_t ETM_TASK_GPIO39_EN : 1; /*!< Enable bit of GPIO response etm task. */ - __IOM uint32_t ETM_TASK_GPIO39_SEL : 3; /*!< GPIO choose a etm task channel. */ - uint32_t : 4; - } bit; - } ETM_TASK_P9_CFG; - - union { - __IOM uint32_t reg; /*!< Etm Configure Register to decide which GPIO been chosen */ - - struct { - __IOM uint32_t ETM_TASK_GPIO40_EN : 1; /*!< Enable bit of GPIO response etm task. */ - __IOM uint32_t ETM_TASK_GPIO40_SEL : 3; /*!< GPIO choose a etm task channel. */ - uint32_t : 4; - __IOM uint32_t ETM_TASK_GPIO41_EN : 1; /*!< Enable bit of GPIO response etm task. */ - __IOM uint32_t ETM_TASK_GPIO41_SEL : 3; /*!< GPIO choose a etm task channel. */ - uint32_t : 4; - __IOM uint32_t ETM_TASK_GPIO42_EN : 1; /*!< Enable bit of GPIO response etm task. */ - __IOM uint32_t ETM_TASK_GPIO42_SEL : 3; /*!< GPIO choose a etm task channel. */ - uint32_t : 4; - __IOM uint32_t ETM_TASK_GPIO43_EN : 1; /*!< Enable bit of GPIO response etm task. */ - __IOM uint32_t ETM_TASK_GPIO43_SEL : 3; /*!< GPIO choose a etm task channel. */ - uint32_t : 4; - } bit; - } ETM_TASK_P10_CFG; - - union { - __IOM uint32_t reg; /*!< Etm Configure Register to decide which GPIO been chosen */ - - struct { - __IOM uint32_t ETM_TASK_GPIO44_EN : 1; /*!< Enable bit of GPIO response etm task. */ - __IOM uint32_t ETM_TASK_GPIO44_SEL : 3; /*!< GPIO choose a etm task channel. */ - uint32_t : 4; - __IOM uint32_t ETM_TASK_GPIO45_EN : 1; /*!< Enable bit of GPIO response etm task. */ - __IOM uint32_t ETM_TASK_GPIO45_SEL : 3; /*!< GPIO choose a etm task channel. */ - uint32_t : 4; - __IOM uint32_t ETM_TASK_GPIO46_EN : 1; /*!< Enable bit of GPIO response etm task. */ - __IOM uint32_t ETM_TASK_GPIO46_SEL : 3; /*!< GPIO choose a etm task channel. */ - uint32_t : 4; - __IOM uint32_t ETM_TASK_GPIO47_EN : 1; /*!< Enable bit of GPIO response etm task. */ - __IOM uint32_t ETM_TASK_GPIO47_SEL : 3; /*!< GPIO choose a etm task channel. */ - uint32_t : 4; - } bit; - } ETM_TASK_P11_CFG; - - union { - union { - __IOM uint32_t reg; /*!< Etm Config register of Channel7 */ - - struct { - __IOM uint32_t ETM_CH0_EVENT_SEL : 6; /*!< Etm event channel select gpio. */ - uint32_t : 1; - __IOM uint32_t ETM_CH0_EVENT_EN : 1; /*!< Etm event send enable bit. */ - uint32_t : 24; - } bit; - } ETM_EVENT_CH7_CFG; - - union { - __IOM uint32_t reg; /*!< Etm Configure Register to decide which GPIO been chosen */ - - struct { - __IOM uint32_t ETM_TASK_GPIO48_EN : 1; /*!< Enable bit of GPIO response etm task. */ - __IOM uint32_t ETM_TASK_GPIO48_SEL : 3; /*!< GPIO choose a etm task channel. */ - uint32_t : 4; - __IOM uint32_t ETM_TASK_GPIO49_EN : 1; /*!< Enable bit of GPIO response etm task. */ - __IOM uint32_t ETM_TASK_GPIO49_SEL : 3; /*!< GPIO choose a etm task channel. */ - uint32_t : 4; - __IOM uint32_t ETM_TASK_GPIO50_EN : 1; /*!< Enable bit of GPIO response etm task. */ - __IOM uint32_t ETM_TASK_GPIO50_SEL : 3; /*!< GPIO choose a etm task channel. */ - uint32_t : 4; - __IOM uint32_t ETM_TASK_GPIO51_EN : 1; /*!< Enable bit of GPIO response etm task. */ - __IOM uint32_t ETM_TASK_GPIO51_SEL : 3; /*!< GPIO choose a etm task channel. */ - uint32_t : 4; - } bit; - } ETM_TASK_P12_CFG; - }; - - union { - __IOM uint32_t reg; /*!< Etm Configure Register to decide which GPIO been chosen */ - - struct { - __IOM uint32_t ETM_TASK_GPIO52_EN : 1; /*!< Enable bit of GPIO response etm task. */ - __IOM uint32_t ETM_TASK_GPIO52_SEL : 3; /*!< GPIO choose a etm task channel. */ - uint32_t : 4; - __IOM uint32_t ETM_TASK_GPIO53_EN : 1; /*!< Enable bit of GPIO response etm task. */ - __IOM uint32_t ETM_TASK_GPIO53_SEL : 3; /*!< GPIO choose a etm task channel. */ - uint32_t : 4; - __IOM uint32_t ETM_TASK_GPIO54_EN : 1; /*!< Enable bit of GPIO response etm task. */ - __IOM uint32_t ETM_TASK_GPIO54_SEL : 3; /*!< GPIO choose a etm task channel. */ - uint32_t : 12; - } bit; - } ETM_TASK_P13_CFG; - __IM uint32_t RESERVED10[9]; - - union { - __IOM uint32_t reg; /*!< Version Control Register */ - - struct { - __IOM uint32_t GPIO_SD_DATE : 28; /*!< Version control register. */ - uint32_t : 4; - } bit; - } VERSION; -} GPIO_SD_Type; /*!< Size = 256 (0x100) */ - - - -/* =========================================================================================================================== */ -/* ================ H264 ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief H264 Encoder (Core) (H264) - */ - -typedef struct { /*!< H264 Structure */ - - union { - __IOM uint32_t reg; /*!< H264 system level control register. */ - - struct { - __OM uint32_t FRAME_START : 1; /*!< Configures whether or not to start encoding one frame.\\0: Invalid. - No effect\\1: Start encoding one frame */ - __OM uint32_t DMA_MOVE_START : 1; /*!< Configures whether or not to start moving reference data from - external mem.\\0: Invalid. No effect\\1: H264 start moving - two MB lines of reference frame from external mem to internal - mem */ - __IOM uint32_t FRAME_MODE : 1; /*!< Configures H264 running mode. When field H264_DUAL_STREAM_MODE - is set to 1, this field must be set to 1 too.\\0: GOP mode. - Before every GOP first frame start, need reconfig reference - frame DMA\\1: Frame mode. Before every frame start, need - reconfig reference frame DMA */ - __OM uint32_t SYS_RST_PULSE : 1; /*!< Configures whether or not to reset H264 ip.\\0: Invalid. No - effect\\1: Reset H264 ip */ - uint32_t : 28; - } bit; - } SYS_CTRL; - - union { - __IOM uint32_t reg; /*!< GOP related configuration register. */ - - struct { - __IOM uint32_t DUAL_STREAM_MODE : 1; /*!< Configures whether or not to enable dual stream mode. When this - field is set to 1, H264_FRAME_MODE field must be set to - 1 too.\\0: Normal mode\\1: Dual stream mode */ - __IOM uint32_t GOP_NUM : 8; /*!< Configures the frame number of one GOP.\\0: The frame number - of one GOP is infinite\\Others: Actual frame number of - one GOP */ - uint32_t : 23; - } bit; - } GOP_CONF; - - union { - __IOM uint32_t reg; /*!< Video A horizontal and vertical MB resolution register. */ - - struct { - __IOM uint32_t A_SYS_TOTAL_MB_Y : 7; /*!< Configures video A vertical MB resolution. */ - __IOM uint32_t A_SYS_TOTAL_MB_X : 7; /*!< Configures video A horizontal MB resolution. */ - uint32_t : 18; - } bit; - } A_SYS_MB_RES; - - union { - __IOM uint32_t reg; /*!< Video A system level configuration register. */ - - struct { - __IOM uint32_t A_DB_TMP_READY_TRIGGER_MB_NUM : 7;/*!< Configures when to trigger video A H264_DB_TMP_READY_INT. When - the (MB number of written db temp+1) is greater than this - filed in first MB line, trigger H264_DB_TMP_READY_INT. - Min is 3. */ - __IOM uint32_t A_REC_READY_TRIGGER_MB_LINES : 7;/*!< Configures when to trigger video A H264_REC_READY_INT. When - the MB line number of generated reconstruct pixel is greater - than this filed, trigger H264_REC_READY_INT. Min is 4. */ - __IOM uint32_t A_INTRA_COST_CMP_OFFSET : 16;/*!< Configures video A intra cost offset when I MB compared with - P MB. */ - uint32_t : 2; - } bit; - } A_SYS_CONF; - - union { - __IOM uint32_t reg; /*!< Video A luma and chroma MB decimate score Register. */ - - struct { - __IOM uint32_t A_C_DECI_SCORE : 10; /*!< Configures video A chroma MB decimate score. When chroma score - is smaller than it, chroma decimate will be enable. */ - __IOM uint32_t A_L_DECI_SCORE : 10; /*!< Configures video A luma MB decimate score. When luma score is - smaller than it, luma decimate will be enable. */ - uint32_t : 12; - } bit; - } A_DECI_SCORE; - - union { - __IOM uint32_t reg; /*!< Video A luma and chroma MB decimate score offset Register. */ - - struct { - __IOM uint32_t A_I16X16_DECI_SCORE_OFFSET : 6;/*!< Configures video A i16x16 MB decimate score offset. This offset - will be added to i16x16 MB score. */ - __IOM uint32_t A_I_CHROMA_DECI_SCORE_OFFSET : 6;/*!< Configures video A I chroma MB decimate score offset. This offset - will be added to I chroma MB score. */ - __IOM uint32_t A_P16X16_DECI_SCORE_OFFSET : 6;/*!< Configures video A p16x16 MB decimate score offset. This offset - will be added to p16x16 MB score. */ - __IOM uint32_t A_P_CHROMA_DECI_SCORE_OFFSET : 6;/*!< Configures video A p chroma MB decimate score offset. This offset - will be added to p chroma MB score. */ - uint32_t : 8; - } bit; - } A_DECI_SCORE_OFFSET; - - union { - __IOM uint32_t reg; /*!< Video A rate control configuration register0. */ - - struct { - __IOM uint32_t A_QP : 6; /*!< Configures video A frame level initial luma QP value. */ - __IOM uint32_t A_RATE_CTRL_U : 16; /*!< Configures video A parameter U value. U = int((float) u << 8). */ - __IOM uint32_t A_MB_RATE_CTRL_EN : 1; /*!< Configures video A whether or not to open macro block rate ctrl.\\1:Open - the macro block rate ctrl\\1:Close the macro block rate - ctrl. */ - uint32_t : 9; - } bit; - } A_RC_CONF0; - - union { - __IOM uint32_t reg; /*!< Video A rate control configuration register1. */ - - struct { - __IOM uint32_t A_CHROMA_DC_QP_DELTA : 3; /*!< Configures video A chroma DC QP offset based on Chroma QP. Chroma - DC QP = Chroma QP(after map) + reg_chroma_dc_qp_delta. */ - __IOM uint32_t A_CHROMA_QP_DELTA : 4; /*!< Configures video A chroma QP offset based on luma QP. Chroma - QP(before map) = Luma QP + reg_chroma_qp_delta. */ - __IOM uint32_t A_QP_MIN : 6; /*!< Configures video A allowed luma QP min value. */ - __IOM uint32_t A_QP_MAX : 6; /*!< Configures video A allowed luma QP max value. */ - __IOM uint32_t A_MAD_FRAME_PRED : 12; /*!< Configures vdieo A frame level predicted MB MAD value. */ - uint32_t : 1; - } bit; - } A_RC_CONF1; - - union { - __IOM uint32_t reg; /*!< Video A Deblocking bypass register */ - - struct { - __IOM uint32_t A_BYPASS_DB_FILTER : 1; /*!< Configures whether or not to bypass video A deblcoking filter. - \\0: Open the deblock filter\\1: Close the deblock filter */ - uint32_t : 31; - } bit; - } A_DB_BYPASS; - - union { - __IOM uint32_t reg; /*!< Video A H264 ROI region0 range configure register. */ - - struct { - __IOM uint32_t X : 7; /*!< Configures the horizontal start macroblocks of region 0 in Video - A. */ - __IOM uint32_t Y : 7; /*!< Configures the vertical start macroblocks of region 0 in Video - A. */ - __IOM uint32_t X_LEN : 7; /*!< Configures the number of macroblocks in horizontal direction - of the region 0 in Video A. */ - __IOM uint32_t Y_LEN : 7; /*!< Configures the number of macroblocks in vertical direction of - the region 0 in Video A. */ - __IOM uint32_t EN : 1; /*!< Configures whether or not to open Video A ROI of region 0 .\\0:Close - ROI\\1:Open ROI. */ - uint32_t : 3; - } bit; - } A_ROI_REGION0; - - union { - __IOM uint32_t reg; /*!< Video A H264 ROI region1 range configure register. */ - - struct { - __IOM uint32_t X : 7; /*!< Configures the horizontal start macroblocks of region 1 in Video - A. */ - __IOM uint32_t Y : 7; /*!< Configures the vertical start macroblocks of region 1 in Video - A. */ - __IOM uint32_t X_LEN : 7; /*!< Configures the number of macroblocks in horizontal direction - of the region 1 in Video A. */ - __IOM uint32_t Y_LEN : 7; /*!< Configures the number of macroblocks in vertical direction of - the region 1 in Video A. */ - __IOM uint32_t EN : 1; /*!< Configures whether or not to open Video A ROI of region 1 .\\0:Close - ROI\\1:Open ROI. */ - uint32_t : 3; - } bit; - } A_ROI_REGION1; - - union { - __IOM uint32_t reg; /*!< Video A H264 ROI region2 range configure register. */ - - struct { - __IOM uint32_t X : 7; /*!< Configures the horizontal start macroblocks of region 2 in Video - A. */ - __IOM uint32_t Y : 7; /*!< Configures the vertical start macroblocks of region 2 in Video - A. */ - __IOM uint32_t X_LEN : 7; /*!< Configures the number of macroblocks in horizontal direction - of the region 2 in Video A. */ - __IOM uint32_t Y_LEN : 7; /*!< Configures the number of macroblocks in vertical direction of - the region 2 in Video A. */ - __IOM uint32_t EN : 1; /*!< Configures whether or not to open Video A ROI of region 2 .\\0:Close - ROI\\1:Open ROI. */ - uint32_t : 3; - } bit; - } A_ROI_REGION2; - - union { - __IOM uint32_t reg; /*!< Video A H264 ROI region3 range configure register. */ - - struct { - __IOM uint32_t X : 7; /*!< Configures the horizontal start macroblocks of region 3 in Video - A. */ - __IOM uint32_t Y : 7; /*!< Configures the vertical start macroblocks of region 3 in Video - A. */ - __IOM uint32_t X_LEN : 7; /*!< Configures the number of macroblocks in horizontal direction - of the region 3 in video A. */ - __IOM uint32_t Y_LEN : 7; /*!< Configures the number of macroblocks in vertical direction of - the region 3 in video A. */ - __IOM uint32_t EN : 1; /*!< Configures whether or not to open Video A ROI of region 3 .\\0:Close - ROI\\1:Open ROI. */ - uint32_t : 3; - } bit; - } A_ROI_REGION3; - - union { - __IOM uint32_t reg; /*!< Video A H264 ROI region4 range configure register. */ - - struct { - __IOM uint32_t X : 7; /*!< Configures the horizontal start macroblocks of region 4 in Video - A. */ - __IOM uint32_t Y : 7; /*!< Configures the vertical start macroblocks of region 4 in Video - A. */ - __IOM uint32_t X_LEN : 7; /*!< Configures the number of macroblocks in horizontal direction - of the region 4 in video A. */ - __IOM uint32_t Y_LEN : 7; /*!< Configures the number of macroblocks in vertical direction of - the region 4 in video A. */ - __IOM uint32_t EN : 1; /*!< Configures whether or not to open Video A ROI of region 4 .\\0:Close - ROI\\1:Open ROI. */ - uint32_t : 3; - } bit; - } A_ROI_REGION4; - - union { - __IOM uint32_t reg; /*!< Video A H264 ROI region5 range configure register. */ - - struct { - __IOM uint32_t X : 7; /*!< Configures the horizontial start macroblocks of region 5 video - A. */ - __IOM uint32_t Y : 7; /*!< Configures the vertical start macroblocks of region 5 video - A. */ - __IOM uint32_t X_LEN : 7; /*!< Configures the number of macroblocks in horizontal direction - of the region 5 video A. */ - __IOM uint32_t Y_LEN : 7; /*!< Configures the number of macroblocks in vertical direction of - the region 5 in video A. */ - __IOM uint32_t EN : 1; /*!< Configures whether or not to open Video A ROI of region 5 .\\0:Close - ROI\\1:Open ROI. */ - uint32_t : 3; - } bit; - } A_ROI_REGION5; - - union { - __IOM uint32_t reg; /*!< Video A H264 ROI region6 range configure register. */ - - struct { - __IOM uint32_t X : 7; /*!< Configures the horizontial start macroblocks of region 6 video - A. */ - __IOM uint32_t Y : 7; /*!< Configures the vertical start macroblocks of region 6 in video - A. */ - __IOM uint32_t X_LEN : 7; /*!< Configures the number of macroblocks in horizontal direction - of the region 6 in video A. */ - __IOM uint32_t Y_LEN : 7; /*!< Configures the number of macroblocks in vertical direction of - the region 6 in video A. */ - __IOM uint32_t EN : 1; /*!< Configures whether or not to open Video A ROI of region 6 .\\0:Close - ROI\\1:Open ROI. */ - uint32_t : 3; - } bit; - } A_ROI_REGION6; - - union { - __IOM uint32_t reg; /*!< Video A H264 ROI region7 range configure register. */ - - struct { - __IOM uint32_t X : 7; /*!< Configures the horizontal start macroblocks of region 7 in video - A. */ - __IOM uint32_t Y : 7; /*!< Configures the vertical start macroblocks of region 7 in video - A. */ - __IOM uint32_t X_LEN : 7; /*!< Configures the number of macroblocks in horizontal direction - of the region 7 in video A. */ - __IOM uint32_t Y_LEN : 7; /*!< Configures the number of macroblocks in vertical direction of - the region 7 in video A. */ - __IOM uint32_t EN : 1; /*!< Configures whether or not to open Video A ROI of region 7 .\\0:Close - ROI\\1:Open ROI. */ - uint32_t : 3; - } bit; - } A_ROI_REGION7; - - union { - __IOM uint32_t reg; /*!< Video A H264 ROI region0, region1,region2,region3 QP register. */ - - struct { - __IOM uint32_t A_ROI_REGION0_QP : 7; /*!< Configure H264 ROI region0 qp in video A,fixed qp or delta qp. */ - __IOM uint32_t A_ROI_REGION1_QP : 7; /*!< Configure H264 ROI region1 qp in video A,fixed qp or delta qp. */ - __IOM uint32_t A_ROI_REGION2_QP : 7; /*!< Configure H264 ROI region2 qp in video A,fixed qp or delta qp. */ - __IOM uint32_t A_ROI_REGION3_QP : 7; /*!< Configure H264 ROI region3 qp in video A,fixed qp or delta qp. */ - uint32_t : 4; - } bit; - } A_ROI_REGION0_3_QP; - - union { - __IOM uint32_t reg; /*!< Video A H264 ROI region4, region5,region6,region7 QP register. */ - - struct { - __IOM uint32_t A_ROI_REGION4_QP : 7; /*!< Configure H264 ROI region4 qp in video A,fixed qp or delta qp. */ - __IOM uint32_t A_ROI_REGION5_QP : 7; /*!< Configure H264 ROI region5 qp in video A,fixed qp or delta qp. */ - __IOM uint32_t A_ROI_REGION6_QP : 7; /*!< Configure H264 ROI region6 qp in video A,fixed qp or delta qp. */ - __IOM uint32_t A_ROI_REGION7_QP : 7; /*!< Configure H264 ROI region7 qp in video A,fixed qp or delta qp. */ - uint32_t : 4; - } bit; - } A_ROI_REGION4_7_QP; - - union { - __IOM uint32_t reg; /*!< Video A H264 no roi region QP register. */ - - struct { - __IOM uint32_t A_NO_ROI_REGION_QP : 7; /*!< Configure H264 no region qp in video A, delta qp. */ - uint32_t : 25; - } bit; - } A_NO_ROI_REGION_QP_OFFSET; - - union { - __IOM uint32_t reg; /*!< Video A H264 ROI configure register. */ - - struct { - __IOM uint32_t A_ROI_EN : 1; /*!< Configure whether or not to enable ROI in video A.\\0:not enable - ROI\\1:enable ROI. */ - __IOM uint32_t A_ROI_MODE : 1; /*!< Configure the mode of ROI in video A.\\0:fixed qp\\1:delta qp. */ - uint32_t : 30; - } bit; - } A_ROI_CONFIG; - - union { - __IOM uint32_t reg; /*!< Video B horizontal and vertical MB resolution register. */ - - struct { - __IOM uint32_t B_SYS_TOTAL_MB_Y : 7; /*!< Configures video B vertical MB resolution. */ - __IOM uint32_t B_SYS_TOTAL_MB_X : 7; /*!< Configures video B horizontal MB resolution. */ - uint32_t : 18; - } bit; - } B_SYS_MB_RES; - - union { - __IOM uint32_t reg; /*!< Video B system level configuration register. */ - - struct { - __IOM uint32_t B_DB_TMP_READY_TRIGGER_MB_NUM : 7;/*!< Configures when to trigger video B H264_DB_TMP_READY_INT. When - the (MB number of written db temp+1) is greater than this - filed in first MB line, trigger H264_DB_TMP_READY_INT. - Min is 3. */ - __IOM uint32_t B_REC_READY_TRIGGER_MB_LINES : 7;/*!< Configures when to trigger video B H264_REC_READY_INT. When - the MB line number of generated reconstruct pixel is greater - than this filed, trigger H264_REC_READY_INT. Min is 4. */ - __IOM uint32_t B_INTRA_COST_CMP_OFFSET : 16;/*!< Configures video B intra cost offset when I MB compared with - P MB. */ - uint32_t : 2; - } bit; - } B_SYS_CONF; - - union { - __IOM uint32_t reg; /*!< Video B luma and chroma MB decimate score Register. */ - - struct { - __IOM uint32_t B_C_DECI_SCORE : 10; /*!< Configures video B chroma MB decimate score. When chroma score - is smaller than it, chroma decimate will be enable. */ - __IOM uint32_t B_L_DECI_SCORE : 10; /*!< Configures video B luma MB decimate score. When luma score is - smaller than it, luma decimate will be enable. */ - uint32_t : 12; - } bit; - } B_DECI_SCORE; - - union { - __IOM uint32_t reg; /*!< Video B luma and chroma MB decimate score offset Register. */ - - struct { - __IOM uint32_t B_I16X16_DECI_SCORE_OFFSET : 6;/*!< Configures video B i16x16 MB decimate score offset. This offset - will be added to i16x16 MB score. */ - __IOM uint32_t B_I_CHROMA_DECI_SCORE_OFFSET : 6;/*!< Configures video B I chroma MB decimate score offset. This offset - will be added to I chroma MB score. */ - __IOM uint32_t B_P16X16_DECI_SCORE_OFFSET : 6;/*!< Configures video B p16x16 MB decimate score offset. This offset - will be added to p16x16 MB score. */ - __IOM uint32_t B_P_CHROMA_DECI_SCORE_OFFSET : 6;/*!< Configures video B p chroma MB decimate score offset. This offset - will be added to p chroma MB score. */ - uint32_t : 8; - } bit; - } B_DECI_SCORE_OFFSET; - - union { - __IOM uint32_t reg; /*!< Video B rate control configuration register0. */ - - struct { - __IOM uint32_t B_QP : 6; /*!< Configures video B frame level initial luma QP value. */ - __IOM uint32_t B_RATE_CTRL_U : 16; /*!< Configures video B parameter U value. U = int((float) u << 8). */ - __IOM uint32_t B_MB_RATE_CTRL_EN : 1; /*!< Configures video A whether or not to open macro block rate ctrl.\\1:Open - the macro block rate ctrl\\1:Close the macro block rate - ctrl. */ - uint32_t : 9; - } bit; - } B_RC_CONF0; - - union { - __IOM uint32_t reg; /*!< Video B rate control configuration register1. */ - - struct { - __IOM uint32_t B_CHROMA_DC_QP_DELTA : 3; /*!< Configures video B chroma DC QP offset based on Chroma QP. Chroma - DC QP = Chroma QP(after map) + reg_chroma_dc_qp_delta. */ - __IOM uint32_t B_CHROMA_QP_DELTA : 4; /*!< Configures video B chroma QP offset based on luma QP. Chroma - QP(before map) = Luma QP + reg_chroma_qp_delta. */ - __IOM uint32_t B_QP_MIN : 6; /*!< Configures video B allowed luma QP min value. */ - __IOM uint32_t B_QP_MAX : 6; /*!< Configures video B allowed luma QP max value. */ - __IOM uint32_t B_MAD_FRAME_PRED : 12; /*!< Configures vdieo B frame level predicted MB MAD value. */ - uint32_t : 1; - } bit; - } B_RC_CONF1; - - union { - __IOM uint32_t reg; /*!< Video B Deblocking bypass register */ - - struct { - __IOM uint32_t B_BYPASS_DB_FILTER : 1; /*!< Configures whether or not to bypass video B deblcoking filter. - \\0: Open the deblock filter\\1: Close the deblock filter */ - uint32_t : 31; - } bit; - } B_DB_BYPASS; - - union { - __IOM uint32_t reg; /*!< Video B H264 ROI region0 range configure register. */ - - struct { - __IOM uint32_t X : 7; /*!< Configures the horizontal start macroblocks of region 0 in Video - B. */ - __IOM uint32_t Y : 7; /*!< Configures the vertical start macroblocks of region 0 in Video - B. */ - __IOM uint32_t X_LEN : 7; /*!< Configures the number of macroblocks in horizontal direction - of the region 0 in Video B. */ - __IOM uint32_t Y_LEN : 7; /*!< Configures the number of macroblocks in vertical direction of - the region 0 in Video B. */ - __IOM uint32_t EN : 1; /*!< Configures whether or not to open Video B ROI of region 0 .\\0:Close - ROI\\1:Open ROI. */ - uint32_t : 3; - } bit; - } B_ROI_REGION0; - - union { - __IOM uint32_t reg; /*!< Video B H264 ROI region1 range configure register. */ - - struct { - __IOM uint32_t X : 7; /*!< Configures the horizontal start macroblocks of region 1 in Video - B. */ - __IOM uint32_t Y : 7; /*!< Configures the vertical start macroblocks of region 1 in Video - B. */ - __IOM uint32_t X_LEN : 7; /*!< Configures the number of macroblocks in horizontal direction - of the region 1 in Video B. */ - __IOM uint32_t Y_LEN : 7; /*!< Configures the number of macroblocks in vertical direction of - the region 1 in Video B. */ - __IOM uint32_t EN : 1; /*!< Configures whether or not to open Video B ROI of region 1 .\\0:Close - ROI\\1:Open ROI. */ - uint32_t : 3; - } bit; - } B_ROI_REGION1; - - union { - __IOM uint32_t reg; /*!< Video B H264 ROI region2 range configure register. */ - - struct { - __IOM uint32_t X : 7; /*!< Configures the horizontal start macroblocks of region 2 in Video - B. */ - __IOM uint32_t Y : 7; /*!< Configures the vertical start macroblocks of region 2 in Video - B. */ - __IOM uint32_t X_LEN : 7; /*!< Configures the number of macroblocks in horizontal direction - of the region 2 in Video B. */ - __IOM uint32_t Y_LEN : 7; /*!< Configures the number of macroblocks in vertical direction of - the region 2 in Video B. */ - __IOM uint32_t EN : 1; /*!< Configures whether or not to open Video B ROI of region 2 .\\0:Close - ROI\\1:Open ROI. */ - uint32_t : 3; - } bit; - } B_ROI_REGION2; - - union { - __IOM uint32_t reg; /*!< Video B H264 ROI region3 range configure register. */ - - struct { - __IOM uint32_t X : 7; /*!< Configures the horizontal start macroblocks of region 3 in Video - B. */ - __IOM uint32_t Y : 7; /*!< Configures the vertical start macroblocks of region 3 in Video - B. */ - __IOM uint32_t X_LEN : 7; /*!< Configures the number of macroblocks in horizontal direction - of the region 3 in video B. */ - __IOM uint32_t Y_LEN : 7; /*!< Configures the number of macroblocks in vertical direction of - the region 3 in video B. */ - __IOM uint32_t EN : 1; /*!< Configures whether or not to open Video B ROI of region 3 .\\0:Close - ROI\\1:Open ROI. */ - uint32_t : 3; - } bit; - } B_ROI_REGION3; - - union { - __IOM uint32_t reg; /*!< Video B H264 ROI region4 range configure register. */ - - struct { - __IOM uint32_t X : 7; /*!< Configures the horizontal start macroblocks of region 4 in Video - B. */ - __IOM uint32_t Y : 7; /*!< Configures the vertical start macroblocks of region 4 in Video - B. */ - __IOM uint32_t X_LEN : 7; /*!< Configures the number of macroblocks in horizontal direction - of the region 4 in video B. */ - __IOM uint32_t Y_LEN : 7; /*!< Configures the number of macroblocks in vertical direction of - the region 4 in video B. */ - __IOM uint32_t EN : 1; /*!< Configures whether or not to open Video B ROI of region 4 .\\0:Close - ROI\\1:Open ROI. */ - uint32_t : 3; - } bit; - } B_ROI_REGION4; - - union { - __IOM uint32_t reg; /*!< Video B H264 ROI region5 range configure register. */ - - struct { - __IOM uint32_t X : 7; /*!< Configures the horizontial start macroblocks of region 5 video - B. */ - __IOM uint32_t Y : 7; /*!< Configures the vertical start macroblocks of region 5 video - B. */ - __IOM uint32_t X_LEN : 7; /*!< Configures the number of macroblocks in horizontal direction - of the region 5 video B. */ - __IOM uint32_t Y_LEN : 7; /*!< Configures the number of macroblocks in vertical direction of - the region 5 in video B. */ - __IOM uint32_t EN : 1; /*!< Configures whether or not to open Video B ROI of region 5 .\\0:Close - ROI\\1:Open ROI. */ - uint32_t : 3; - } bit; - } B_ROI_REGION5; - - union { - __IOM uint32_t reg; /*!< Video B H264 ROI region6 range configure register. */ - - struct { - __IOM uint32_t X : 7; /*!< Configures the horizontial start macroblocks of region 6 video - B. */ - __IOM uint32_t Y : 7; /*!< Configures the vertical start macroblocks of region 6 in video - B. */ - __IOM uint32_t X_LEN : 7; /*!< Configures the number of macroblocks in horizontal direction - of the region 6 in video B. */ - __IOM uint32_t Y_LEN : 7; /*!< Configures the number of macroblocks in vertical direction of - the region 6 in video B. */ - __IOM uint32_t EN : 1; /*!< Configures whether or not to open Video B ROI of region 6 .\\0:Close - ROI\\1:Open ROI. */ - uint32_t : 3; - } bit; - } B_ROI_REGION6; - - union { - __IOM uint32_t reg; /*!< Video B H264 ROI region7 range configure register. */ - - struct { - __IOM uint32_t X : 7; /*!< Configures the horizontal start macroblocks of region 7 in video - B. */ - __IOM uint32_t Y : 7; /*!< Configures the vertical start macroblocks of region 7 in video - B. */ - __IOM uint32_t X_LEN : 7; /*!< Configures the number of macroblocks in horizontal direction - of the region 7 in video B. */ - __IOM uint32_t Y_LEN : 7; /*!< Configures the number of macroblocks in vertical direction of - the region 7 in video B. */ - __IOM uint32_t EN : 1; /*!< Configures whether or not to open Video B ROI of region 7 .\\0:Close - ROI\\1:Open ROI. */ - uint32_t : 3; - } bit; - } B_ROI_REGION7; - - union { - __IOM uint32_t reg; /*!< Video B H264 ROI region0, region1,region2,region3 QP register. */ - - struct { - __IOM uint32_t B_ROI_REGION0_QP : 7; /*!< Configure H264 ROI region0 qp in video B,fixed qp or delta qp. */ - __IOM uint32_t B_ROI_REGION1_QP : 7; /*!< Configure H264 ROI region1 qp in video B,fixed qp or delta qp. */ - __IOM uint32_t B_ROI_REGION2_QP : 7; /*!< Configure H264 ROI region2 qp in video B,fixed qp or delta qp. */ - __IOM uint32_t B_ROI_REGION3_QP : 7; /*!< Configure H264 ROI region3 qp in video B,fixed qp or delta qp. */ - uint32_t : 4; - } bit; - } B_ROI_REGION0_3_QP; - - union { - __IOM uint32_t reg; /*!< Video B H264 ROI region4, region5,region6,region7 QP register. */ - - struct { - __IOM uint32_t B_ROI_REGION4_QP : 7; /*!< Configure H264 ROI region4 qp in video B,fixed qp or delta qp. */ - __IOM uint32_t B_ROI_REGION5_QP : 7; /*!< Configure H264 ROI region5 qp in video B,fixed qp or delta qp. */ - __IOM uint32_t B_ROI_REGION6_QP : 7; /*!< Configure H264 ROI region6 qp in video B,fixed qp or delta qp. */ - __IOM uint32_t B_ROI_REGION7_QP : 7; /*!< Configure H264 ROI region7 qp in video B,fixed qp or delta qp. */ - uint32_t : 4; - } bit; - } B_ROI_REGION4_7_QP; - - union { - __IOM uint32_t reg; /*!< Video B H264 no roi region QP register. */ - - struct { - __IOM uint32_t B_NO_ROI_REGION_QP : 7; /*!< Configure H264 no region qp in video B, delta qp. */ - uint32_t : 25; - } bit; - } B_NO_ROI_REGION_QP_OFFSET; - - union { - __IOM uint32_t reg; /*!< Video B H264 ROI configure register. */ - - struct { - __IOM uint32_t B_ROI_EN : 1; /*!< Configure whether or not to enable ROI in video B.\\0:not enable - ROI\\1:enable ROI. */ - __IOM uint32_t B_ROI_MODE : 1; /*!< Configure the mode of ROI in video B.\\0:fixed qp\\1:delta qp. */ - uint32_t : 30; - } bit; - } B_ROI_CONFIG; - - union { - __IOM uint32_t reg; /*!< Rate control status register0. */ - - struct { - __IM uint32_t FRAME_MAD_SUM : 21; /*!< Represents all MB actual MAD sum value of one frame. */ - uint32_t : 11; - } bit; - } RC_STATUS0; - - union { - __IOM uint32_t reg; /*!< Rate control status register1. */ - - struct { - __IM uint32_t FRAME_ENC_BITS : 27; /*!< Represents all MB actual encoding bits sum value of one frame. */ - uint32_t : 5; - } bit; - } RC_STATUS1; - - union { - __IOM uint32_t reg; /*!< Rate control status register2. */ - - struct { - __IM uint32_t FRAME_QP_SUM : 19; /*!< Represents all MB actual luma QP sum value of one frame. */ - uint32_t : 13; - } bit; - } RC_STATUS2; - - union { - __IOM uint32_t reg; /*!< Frame Slice Header remain bit register. */ - - struct { - __IOM uint32_t SLICE_REMAIN_BITLENGTH : 3;/*!< Configures Slice Header remain bit number */ - __IOM uint32_t SLICE_REMAIN_BIT : 8; /*!< Configures Slice Header remain bit */ - uint32_t : 21; - } bit; - } SLICE_HEADER_REMAIN; - - union { - __IOM uint32_t reg; /*!< Frame Slice Header byte length register. */ - - struct { - __IOM uint32_t SLICE_BYTE_LENGTH : 4; /*!< Configures Slice Header byte number */ - uint32_t : 28; - } bit; - } SLICE_HEADER_BYTE_LENGTH; - - union { - __IOM uint32_t reg; /*!< Bitstream buffer overflow threshold register */ - - struct { - __IOM uint32_t BS_BUFFER_THRESHOLD : 7; /*!< Configures bitstream buffer overflow threshold. This value should - be bigger than the encode bytes of one 4x4 submb. */ - uint32_t : 25; - } bit; - } BS_THRESHOLD; - - union { - __IOM uint32_t reg; /*!< Frame Slice Header byte low 32 bit register. */ - - struct { - __IOM uint32_t SLICE_BYTE_LSB : 32; /*!< Configures Slice Header low 32 bit */ - } bit; - } SLICE_HEADER_BYTE0; - - union { - __IOM uint32_t reg; /*!< Frame Slice Header byte high 32 bit register. */ - - struct { - __IOM uint32_t SLICE_BYTE_MSB : 32; /*!< Configures Slice Header high 32 bit */ - } bit; - } SLICE_HEADER_BYTE1; - - union { - __IOM uint32_t reg; /*!< Interrupt raw status register */ - - struct { - __IOM uint32_t DB_TMP_READY_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of H264_DB_TMP_READY_INT. - Triggered when H264 written enough db tmp pixel. */ - __IOM uint32_t REC_READY_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of H264_REC_READY_INT. - Triggered when H264 encoding enough reconstruct pixel. */ - __IOM uint32_t FRAME_DONE_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of H264_FRAME_DONE_INT. - Triggered when H264 encoding one frame done. */ - __IOM uint32_t DMA_MOVE_2MB_LINE_DONE_INT_RAW : 1;/*!< Raw status bit: The raw interrupt status of H264_DMA_MOVE_2MB_LINE_DONE_INT. - Triggered when H264 move two MB lines of reference frame - from external mem to internal mem done. */ - uint32_t : 28; - } bit; - } INT_RAW; - - union { - __IOM uint32_t reg; /*!< Interrupt masked status register */ - - struct { - __IM uint32_t DB_TMP_READY_INT_ST : 1; /*!< The masked interrupt status of H264_DB_TMP_READY_INT. Valid - only when the H264_DB_TMP_READY_INT_ENA is set to 1. */ - __IM uint32_t REC_READY_INT_ST : 1; /*!< The masked interrupt status of H264_REC_READY_INT. Valid only - when the H264_REC_READY_INT_ENA is set to 1. */ - __IM uint32_t FRAME_DONE_INT_ST : 1; /*!< The masked interrupt status of H264_FRAME_DONE_INT. Valid only - when the H264_FRAME_DONE_INT_ENA is set to 1. */ - __IM uint32_t DMA_MOVE_2MB_LINE_DONE_INT_ST : 1;/*!< Masked status bit: The masked interrupt status of H264_DMA_MOVE_2MB_LINE_DONE_ - NT. Valid only when the H264_DMA_MOVE_2MB_LINE_DONE_INT_ENA - is set to 1. */ - uint32_t : 28; - } bit; - } INT_ST; - - union { - __IOM uint32_t reg; /*!< Interrupt enable register */ - - struct { - __IOM uint32_t DB_TMP_READY_INT_ENA : 1; /*!< Write 1 to enable H264_DB_TMP_READY_INT. */ - __IOM uint32_t REC_READY_INT_ENA : 1; /*!< Write 1 to enable H264_REC_READY_INT. */ - __IOM uint32_t FRAME_DONE_INT_ENA : 1; /*!< Write 1 to enable H264_FRAME_DONE_INT. */ - __IOM uint32_t DMA_MOVE_2MB_LINE_DONE_INT_ENA : 1;/*!< Enable bit: Write 1 to enable H264_DMA_MOVE_2MB_LINE_DONE_INT. */ - uint32_t : 28; - } bit; - } INT_ENA; - - union { - __IOM uint32_t reg; /*!< Interrupt clear register */ - - struct { - __OM uint32_t DB_TMP_READY_INT_CLR : 1; /*!< Write 1 to clear H264_DB_TMP_READY_INT. */ - __OM uint32_t REC_READY_INT_CLR : 1; /*!< Write 1 to clear H264_REC_READY_INT. */ - __OM uint32_t FRAME_DONE_INT_CLR : 1; /*!< Write 1 to clear H264_FRAME_DONE_INT. */ - __OM uint32_t DMA_MOVE_2MB_LINE_DONE_INT_CLR : 1;/*!< Clear bit: Write 1 to clear H264_DMA_MOVE_2MB_LINE_DONE_INT. */ - uint32_t : 28; - } bit; - } INT_CLR; - - union { - __IOM uint32_t reg; /*!< General configuration register. */ - - struct { - __IOM uint32_t CLK_EN : 1; /*!< Configures whether or not to open register clock gate.\\0: Open - the clock gate only when application writes registers\\1: - Force open the clock gate for register */ - __IOM uint32_t REC_RAM_CLK_EN2 : 1; /*!< Configures whether or not to open the clock gate for rec ram2.\\0: - Open the clock gate only when application writes or reads - rec ram2\\1: Force open the clock gate for rec ram2 */ - __IOM uint32_t REC_RAM_CLK_EN1 : 1; /*!< Configures whether or not to open the clock gate for rec ram1.\\0: - Open the clock gate only when application writes or reads - rec ram1\\1: Force open the clock gate for rec ram1 */ - __IOM uint32_t QUANT_RAM_CLK_EN2 : 1; /*!< Configures whether or not to open the clock gate for quant ram2.\\0: - Open the clock gate only when application writes or reads - quant ram2\\1: Force open the clock gate for quant ram2 */ - __IOM uint32_t QUANT_RAM_CLK_EN1 : 1; /*!< Configures whether or not to open the clock gate for quant ram1.\\0: - Open the clock gate only when application writes or reads - quant ram1\\1: Force open the clock gate for quant ram1 */ - __IOM uint32_t PRE_RAM_CLK_EN : 1; /*!< Configures whether or not to open the clock gate for pre ram.\\0: - Open the clock gate only when application writes or reads - pre ram\\1: Force open the clock gate for pre ram */ - __IOM uint32_t MVD_RAM_CLK_EN : 1; /*!< Configures whether or not to open the clock gate for mvd ram.\\0: - Open the clock gate only when application writes or reads - mvd ram\\1: Force open the clock gate for mvd ram */ - __IOM uint32_t MC_RAM_CLK_EN : 1; /*!< Configures whether or not to open the clock gate for mc ram.\\0: - Open the clock gate only when application writes or reads - mc ram\\1: Force open the clock gate for mc ram */ - __IOM uint32_t REF_RAM_CLK_EN : 1; /*!< Configures whether or not to open the clock gate for ref ram.\\0: - Open the clock gate only when application writes or reads - ref ram\\1: Force open the clock gate for ref ram */ - __IOM uint32_t I4X4_REF_RAM_CLK_EN : 1; /*!< Configures whether or not to open the clock gate for i4x4_mode - ram.\\0: Open the clock gate only when application writes - or reads i4x4_mode ram\\1: Force open the clock gate for - i4x4_mode ram */ - __IOM uint32_t IME_RAM_CLK_EN : 1; /*!< Configures whether or not to open the clock gate for ime ram.\\0: - Open the clock gate only when application writes or reads - ime ram\\1: Force open the clock gate for ime ram */ - __IOM uint32_t FME_RAM_CLK_EN : 1; /*!< Configures whether or not to open the clock gate for fme ram.\\0: - Open the clock gate only when application writes or readsfme - ram\\1: Force open the clock gate for fme ram */ - __IOM uint32_t FETCH_RAM_CLK_EN : 1; /*!< Configures whether or not to open the clock gate for fetch ram.\\0: - Open the clock gate only when application writes or reads - fetch ram\\1: Force open the clock gate for fetch ram */ - __IOM uint32_t DB_RAM_CLK_EN : 1; /*!< Configures whether or not to open the clock gate for db ram.\\0: - Open the clock gate only when application writes or reads - db ram\\1: Force open the clock gate for db ram */ - __IOM uint32_t CUR_MB_RAM_CLK_EN : 1; /*!< Configures whether or not to open the clock gate for cur_mb - ram.\\0: Open the clock gate only when application writes - or reads cur_mb ram\\1: Force open the clock gate for cur_mb - ram */ - __IOM uint32_t CAVLC_RAM_CLK_EN : 1; /*!< Configures whether or not to open the clock gate for cavlc ram.\\0: - Open the clock gate only when application writes or reads - cavlc ram\\1: Force open the clock gate for cavlc ram */ - __IOM uint32_t IME_CLK_EN : 1; /*!< Configures whether or not to open the clock gate for ime.\\0: - Open the clock gate only when ime work\\1: Force open the - clock gate for ime */ - __IOM uint32_t FME_CLK_EN : 1; /*!< Configures whether or not to open the clock gate for fme.\\0: - Open the clock gate only when fme work\\1: Force open the - clock gate for fme */ - __IOM uint32_t MC_CLK_EN : 1; /*!< Configures whether or not to open the clock gate for mc.\\0: - Open the clock gate only when mc work\\1: Force open the - clock gate for mc */ - __IOM uint32_t INTERPOLATOR_CLK_EN : 1; /*!< Configures whether or not to open the clock gate for interpolator.\\0: - Open the clock gate only when interpolator work\\1: Force - open the clock gate for interpolator */ - __IOM uint32_t DB_CLK_EN : 1; /*!< Configures whether or not to open the clock gate for deblocking - filter.\\0: Open the clock gate only when deblocking filter - work\\1: Force open the clock gate for deblocking filter */ - __IOM uint32_t CLAVLC_CLK_EN : 1; /*!< Configures whether or not to open the clock gate for cavlc.\\0: - Open the clock gate only when cavlc work\\1: Force open - the clock gate for cavlc */ - __IOM uint32_t INTRA_CLK_EN : 1; /*!< Configures whether or not to open the clock gate for intra.\\0: - Open the clock gate only when intra work\\1: Force open - the clock gate for intra */ - __IOM uint32_t DECI_CLK_EN : 1; /*!< Configures whether or not to open the clock gate for decimate.\\0: - Open the clock gate only when decimate work\\1: Force open - the clock gate for decimate */ - __IOM uint32_t BS_CLK_EN : 1; /*!< Configures whether or not to open the clock gate for bs buffer.\\0: - Open the clock gate only when bs buffer work\\1: Force - open the clock gate for bs buffer */ - __IOM uint32_t MV_MERGE_CLK_EN : 1; /*!< Configures whether or not to open the clock gate for mv merge.\\0: - Open the clock gate only when mv merge work\\1: Force open - the clock gate for mv merge */ - uint32_t : 6; - } bit; - } CONF; - - union { - __IOM uint32_t reg; /*!< Mv merge configuration register. */ - - struct { - __IOM uint32_t MV_MERGE_TYPE : 2; /*!< Configure mv merge type.\\0: merge p16x16 mv\\1: merge min mv\\2: - merge max mv\\3: not valid. */ - __IOM uint32_t INT_MV_OUT_EN : 1; /*!< Configure mv merge output integer part not zero mv or all part - not zero mv.\\0: output all part not zero mv\\1: output - integer part not zero mv. */ - __IOM uint32_t A_MV_MERGE_EN : 1; /*!< Configure whether or not to enable video A mv merge.\\0: disable\\1: - enable. */ - __IOM uint32_t B_MV_MERGE_EN : 1; /*!< Configure whether or not to enable video B mv merge.\\0: disable\\1: - enable. */ - __IM uint32_t MB_VALID_NUM : 13; /*!< Represents the valid mb number of mv merge output. */ - uint32_t : 14; - } bit; - } MV_MERGE_CONFIG; - - union { - __IOM uint32_t reg; /*!< Debug H264 DMA select register */ - - struct { - __IOM uint32_t DBG_DMA_SEL : 8; /*!< Every bit represents a dma in h264 */ - uint32_t : 24; - } bit; - } DEBUG_DMA_SEL; - - union { - __IOM uint32_t reg; /*!< System status register. */ - - struct { - __IM uint32_t FRAME_NUM : 9; /*!< Represents current frame number. */ - __IM uint32_t DUAL_STREAM_SEL : 1; /*!< Represents which register group is used for cur frame.\\0: Register - group A is used\\1: Register group B is used. */ - __IM uint32_t INTRA_FLAG : 1; /*!< Represents the type of current encoding frame.\\0: P frame\\1: - I frame. */ - uint32_t : 21; - } bit; - } SYS_STATUS; - - union { - __IOM uint32_t reg; /*!< Frame code byte length register. */ - - struct { - __IM uint32_t FRAME_CODE_LENGTH : 24; /*!< Represents current frame code byte length. */ - uint32_t : 8; - } bit; - } FRAME_CODE_LENGTH; - - union { - __IOM uint32_t reg; /*!< Debug information register0. */ - - struct { - __IM uint32_t TOP_CTRL_INTER_DEBUG_STATE : 4;/*!< Represents top_ctrl_inter module FSM info. */ - __IM uint32_t TOP_CTRL_INTRA_DEBUG_STATE : 3;/*!< Represents top_ctrl_intra module FSM info. */ - __IM uint32_t P_I_CMP_DEBUG_STATE : 3; /*!< Represents p_i_cmp module FSM info. */ - __IM uint32_t MVD_DEBUG_STATE : 3; /*!< Represents mvd module FSM info. */ - __IM uint32_t MC_CHROMA_IP_DEBUG_STATE : 1;/*!< Represents mc_chroma_ip module FSM info. */ - __IM uint32_t INTRA_16X16_CHROMA_CTRL_DEBUG_STATE : 4;/*!< Represents intra_16x16_chroma_ctrl module FSM info. */ - __IM uint32_t INTRA_4X4_CTRL_DEBUG_STATE : 4;/*!< Represents intra_4x4_ctrl module FSM info. */ - __IM uint32_t INTRA_TOP_CTRL_DEBUG_STATE : 3;/*!< Represents intra_top_ctrl module FSM info. */ - __IM uint32_t IME_CTRL_DEBUG_STATE : 3; /*!< Represents ime_ctrl module FSM info. */ - uint32_t : 4; - } bit; - } DEBUG_INFO0; - - union { - __IOM uint32_t reg; /*!< Debug information register1. */ - - struct { - __IM uint32_t FME_CTRL_DEBUG_STATE : 3; /*!< Represents fme_ctrl module FSM info. */ - __IM uint32_t DECI_CALC_DEBUG_STATE : 2; /*!< Represents deci_calc module's FSM info. DEV use only. */ - __IM uint32_t DB_DEBUG_STATE : 3; /*!< Represents db module FSM info. */ - __IM uint32_t CAVLC_ENC_DEBUG_STATE : 4; /*!< Represents cavlc module enc FSM info. */ - __IM uint32_t CAVLC_SCAN_DEBUG_STATE : 4;/*!< Represents cavlc module scan FSM info. */ - __IM uint32_t CAVLC_CTRL_DEBUG_STATE : 2;/*!< Represents cavlc module ctrl FSM info. */ - __IM uint32_t BS_BUFFER_DEBUG_STATE : 1; /*!< Represents bs buffer overflow info. */ - uint32_t : 13; - } bit; - } DEBUG_INFO1; - - union { - __IOM uint32_t reg; /*!< Debug information register2. */ - - struct { - __IM uint32_t P_RC_DONE_DEBUG_FLAG : 1; /*!< Represents p rate ctrl done status.\\0: not done\\1: done. */ - __IM uint32_t P_P_I_CMP_DONE_DEBUG_FLAG : 1;/*!< Represents p p_i_cmp done status.\\0: not done\\1: done. */ - __IM uint32_t P_MV_MERGE_DONE_DEBUG_FLAG : 1;/*!< Represents p mv merge done status.\\0: not done\\1: done. */ - __IM uint32_t P_MOVE_ORI_DONE_DEBUG_FLAG : 1;/*!< Represents p move origin done status.\\0: not done\\1: done. */ - __IM uint32_t P_MC_DONE_DEBUG_FLAG : 1; /*!< Represents p mc done status.\\0: not done\\1: done. */ - __IM uint32_t P_IME_DONE_DEBUG_FLAG : 1; /*!< Represents p ime done status.\\0: not done\\1: done. */ - __IM uint32_t P_GET_ORI_DONE_DEBUG_FLAG : 1;/*!< Represents p get origin done status.\\0: not done\\1: done. */ - __IM uint32_t P_FME_DONE_DEBUG_FLAG : 1; /*!< Represents p fme done status.\\0: not done\\1: done. */ - __IM uint32_t P_FETCH_DONE_DEBUG_FLAG : 1;/*!< Represents p fetch done status.\\0: not done\\1: done. */ - __IM uint32_t P_DB_DONE_DEBUG_FLAG : 1; /*!< Represents p deblocking done status.\\0: not done\\1: done. */ - __IM uint32_t P_BS_BUF_DONE_DEBUG_FLAG : 1;/*!< Represents p bitstream buffer done status.\\0: not done\\1: - done. */ - __IM uint32_t REF_MOVE_2MB_LINE_DONE_DEBUG_FLAG : 1;/*!< Represents dma move 2 ref mb line done status.\\0: not done\\1: - done. */ - __IM uint32_t I_P_I_CMP_DONE_DEBUG_FLAG : 1;/*!< Represents I p_i_cmp done status.\\0: not done\\1: done. */ - __IM uint32_t I_MOVE_ORI_DONE_DEBUG_FLAG : 1;/*!< Represents I move origin done status.\\0: not done\\1: done. */ - __IM uint32_t I_GET_ORI_DONE_DEBUG_FLAG : 1;/*!< Represents I get origin done status.\\0: not done\\1: done. */ - __IM uint32_t I_EC_DONE_DEBUG_FLAG : 1; /*!< Represents I encoder done status.\\0: not done\\1: done. */ - __IM uint32_t I_DB_DONE_DEBUG_FLAG : 1; /*!< Represents I deblocking done status.\\0: not done\\1: done. */ - __IM uint32_t I_BS_BUF_DONE_DEBUG_FLAG : 1;/*!< Represents I bitstream buffer done status.\\0: not done\\1: - done. */ - uint32_t : 14; - } bit; - } DEBUG_INFO2; - - union { - __IOM uint32_t reg; /*!< Version control register */ - - struct { - __IOM uint32_t LEDC_DATE : 28; /*!< Configures the version. */ - uint32_t : 4; - } bit; - } DATE; -} H264_Type; /*!< Size = 244 (0xf4) */ - - - -/* =========================================================================================================================== */ -/* ================ H264_DMA ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief H264 Encoder (DMA) (H264_DMA) - */ - -typedef struct { /*!< H264_DMA Structure */ - - union { - __IOM uint32_t reg; /*!< TX CH0 config0 register */ - - struct { - __IOM uint32_t OUT_AUTO_WRBACK_CH0 : 1; /*!< Set this bit to enable automatic outlink-writeback when all - the data pointed by outlink descriptor has been received. */ - __IOM uint32_t OUT_EOF_MODE_CH0 : 1; /*!< EOF flag generation mode when receiving data. 1: EOF flag for - Tx channel 0 is generated when data need to read has been - popped from FIFO in DMA */ - __IOM uint32_t OUTDSCR_BURST_EN_CH0 : 1; /*!< Set this bit to 1 to enable INCR burst transfer for Tx channel - 0 reading link descriptor when accessing internal SRAM. */ - __IOM uint32_t OUT_ECC_AES_EN_CH0 : 1; /*!< When access address space is ecc/aes area, this bit should be - set to 1. In this case, the start address of square should - be 16-bit aligned. The width of square multiply byte number - of one pixel should be 16-bit aligned. */ - __IOM uint32_t OUT_CHECK_OWNER_CH0 : 1; /*!< Set this bit to enable checking the owner attribute of the link - descriptor. */ - uint32_t : 1; - __IOM uint32_t OUT_MEM_BURST_LENGTH_CH0 : 3;/*!< Block size of Tx channel 0. 0: single 1: 16 bytes 2: 32 bytes - 3: 64 bytes 4: 128 bytes */ - uint32_t : 3; - __IOM uint32_t OUT_PAGE_BOUND_EN_CH0 : 1; /*!< Set this bit to 1 to make sure AXI read data don't cross the - address boundary which define by mem_burst_length */ - uint32_t : 3; - __IOM uint32_t OUT_REORDER_EN_CH0 : 1; /*!< Enable TX channel 0 macro block reorder when set to 1, only - channel0 have this selection */ - uint32_t : 7; - __IOM uint32_t OUT_RST_CH0 : 1; /*!< Write 1 then write 0 to this bit to reset TX channel */ - __IOM uint32_t OUT_CMD_DISABLE_CH0 : 1; /*!< Write 1 before reset and write 0 after reset */ - __IOM uint32_t OUT_ARB_WEIGHT_OPT_DIS_CH0 : 1;/*!< Set this bit to 1 to disable arbiter optimum weight function. */ - uint32_t : 5; - } bit; - } OUT_CONF0_CH0; - - union { - __IOM uint32_t reg; /*!< TX CH0 interrupt raw register */ - - struct { - __IOM uint32_t OUT_DONE_CH0_INT_RAW : 1; /*!< The raw interrupt bit turns to high level when the last data - pointed by one outlink descriptor has been transmitted - to peripherals for Tx channel 0. */ - __IOM uint32_t OUT_EOF_CH0_INT_RAW : 1; /*!< The raw interrupt bit turns to high level when the last data - pointed by one outlink descriptor has been read from memory - for Tx channel 0. */ - __IOM uint32_t OUT_DSCR_ERR_CH0_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when detecting outlink - descriptor error, including owner error, the second and - third word error of outlink descriptor for Tx channel 0. */ - __IOM uint32_t OUT_TOTAL_EOF_CH0_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when data corresponding - a outlink (includes one link descriptor or few link descriptors) - is transmitted out for Tx channel 0. */ - __IOM uint32_t OUTFIFO_OVF_L1_CH0_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when fifo is overflow. */ - __IOM uint32_t OUTFIFO_UDF_L1_CH0_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when fifo is underflow. */ - __IOM uint32_t OUTFIFO_OVF_L2_CH0_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when fifo is overflow. */ - __IOM uint32_t OUTFIFO_UDF_L2_CH0_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when fifo is underflow. */ - __IOM uint32_t OUT_DSCR_TASK_OVF_CH0_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when dscr ready task - fifo is overflow. */ - uint32_t : 23; - } bit; - } OUT_INT_RAW_CH0; - - union { - __IOM uint32_t reg; /*!< TX CH0 interrupt ena register */ - - struct { - __IOM uint32_t OUT_DONE_CH0_INT_ENA : 1; /*!< The interrupt enable bit for the OUT_DONE_CH_INT interrupt. */ - __IOM uint32_t OUT_EOF_CH0_INT_ENA : 1; /*!< The interrupt enable bit for the OUT_EOF_CH_INT interrupt. */ - __IOM uint32_t OUT_DSCR_ERR_CH0_INT_ENA : 1;/*!< The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. */ - __IOM uint32_t OUT_TOTAL_EOF_CH0_INT_ENA : 1;/*!< The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. */ - __IOM uint32_t OUTFIFO_OVF_L1_CH0_INT_ENA : 1;/*!< The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. */ - __IOM uint32_t OUTFIFO_UDF_L1_CH0_INT_ENA : 1;/*!< The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. */ - __IOM uint32_t OUTFIFO_OVF_L2_CH0_INT_ENA : 1;/*!< The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. */ - __IOM uint32_t OUTFIFO_UDF_L2_CH0_INT_ENA : 1;/*!< The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. */ - __IOM uint32_t OUT_DSCR_TASK_OVF_CH0_INT_ENA : 1;/*!< The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. */ - uint32_t : 23; - } bit; - } OUT_INT_ENA_CH0; - - union { - __IOM uint32_t reg; /*!< TX CH0 interrupt st register */ - - struct { - __IM uint32_t OUT_DONE_CH0_INT_ST : 1; /*!< The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. */ - __IM uint32_t OUT_EOF_CH0_INT_ST : 1; /*!< The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. */ - __IM uint32_t OUT_DSCR_ERR_CH0_INT_ST : 1;/*!< The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. */ - __IM uint32_t OUT_TOTAL_EOF_CH0_INT_ST : 1;/*!< The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. */ - __IM uint32_t OUTFIFO_OVF_L1_CH0_INT_ST : 1;/*!< The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. */ - __IM uint32_t OUTFIFO_UDF_L1_CH0_INT_ST : 1;/*!< The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. */ - __IM uint32_t OUTFIFO_OVF_L2_CH0_INT_ST : 1;/*!< The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. */ - __IM uint32_t OUTFIFO_UDF_L2_CH0_INT_ST : 1;/*!< The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. */ - __IM uint32_t OUT_DSCR_TASK_OVF_CH0_INT_ST : 1;/*!< The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT - interrupt. */ - uint32_t : 23; - } bit; - } OUT_INT_ST_CH0; - - union { - __IOM uint32_t reg; /*!< TX CH0 interrupt clr register */ - - struct { - __OM uint32_t OUT_DONE_CH0_INT_CLR : 1; /*!< Set this bit to clear the OUT_DONE_CH_INT interrupt. */ - __OM uint32_t OUT_EOF_CH0_INT_CLR : 1; /*!< Set this bit to clear the OUT_EOF_CH_INT interrupt. */ - __OM uint32_t OUT_DSCR_ERR_CH0_INT_CLR : 1;/*!< Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. */ - __OM uint32_t OUT_TOTAL_EOF_CH0_INT_CLR : 1;/*!< Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. */ - __OM uint32_t OUTFIFO_OVF_L1_CH0_INT_CLR : 1;/*!< Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. */ - __OM uint32_t OUTFIFO_UDF_L1_CH0_INT_CLR : 1;/*!< Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. */ - __OM uint32_t OUTFIFO_OVF_L2_CH0_INT_CLR : 1;/*!< Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. */ - __OM uint32_t OUTFIFO_UDF_L2_CH0_INT_CLR : 1;/*!< Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. */ - __OM uint32_t OUT_DSCR_TASK_OVF_CH0_INT_CLR : 1;/*!< Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. */ - uint32_t : 23; - } bit; - } OUT_INT_CLR_CH0; - - union { - __IOM uint32_t reg; /*!< TX CH0 outfifo status register */ - - struct { - __IM uint32_t OUTFIFO_FULL_L2_CH0 : 1; /*!< Tx FIFO full signal for Tx channel 0. */ - __IM uint32_t OUTFIFO_EMPTY_L2_CH0 : 1; /*!< Tx FIFO empty signal for Tx channel 0. */ - __IM uint32_t OUTFIFO_CNT_L2_CH0 : 4; /*!< The register stores the byte number of the data in Tx FIFO for - Tx channel 0. */ - __IM uint32_t OUTFIFO_FULL_L1_CH0 : 1; /*!< Tx FIFO full signal for Tx channel 0. */ - __IM uint32_t OUTFIFO_EMPTY_L1_CH0 : 1; /*!< Tx FIFO empty signal for Tx channel 0. */ - __IM uint32_t OUTFIFO_CNT_L1_CH0 : 5; /*!< The register stores the byte number of the data in Tx FIFO for - Tx channel 0. */ - uint32_t : 3; - __IM uint32_t OUTFIFO_FULL_L3_CH0 : 1; /*!< Tx FIFO full signal for Tx channel 0. */ - __IM uint32_t OUTFIFO_EMPTY_L3_CH0 : 1; /*!< Tx FIFO empty signal for Tx channel 0. */ - __IM uint32_t OUTFIFO_CNT_L3_CH0 : 2; /*!< The register stores the 8byte number of the data in Tx FIFO - for Tx channel 0. */ - uint32_t : 12; - } bit; - } OUTFIFO_STATUS_CH0; - - union { - __IOM uint32_t reg; /*!< TX CH0 outfifo push register */ - - struct { - __IOM uint32_t OUTFIFO_WDATA_CH0 : 10; /*!< This register stores the data that need to be pushed into DMA - Tx FIFO. */ - __IOM uint32_t OUTFIFO_PUSH_CH0 : 1; /*!< Set this bit to push data into DMA Tx FIFO. */ - uint32_t : 21; - } bit; - } OUT_PUSH_CH0; - - union { - __IOM uint32_t reg; /*!< TX CH0 out_link dscr ctrl register */ - - struct { - uint32_t : 20; - __IOM uint32_t OUTLINK_STOP_CH0 : 1; /*!< Set this bit to stop dealing with the outlink descriptors. */ - __IOM uint32_t OUTLINK_START_CH0 : 1; /*!< Set this bit to start dealing with the outlink descriptors. */ - __IOM uint32_t OUTLINK_RESTART_CH0 : 1; /*!< Set this bit to restart a new outlink from the last address. */ - __IM uint32_t OUTLINK_PARK_CH0 : 1; /*!< 1: the outlink descriptor's FSM is in idle state. 0: the outlink - descriptor's FSM is working. */ - uint32_t : 8; - } bit; - } OUT_LINK_CONF_CH0; - - union { - __IOM uint32_t reg; /*!< TX CH0 out_link dscr addr register */ - - struct { - __IOM uint32_t OUTLINK_ADDR_CH0 : 32; /*!< This register stores the first outlink descriptor's address. */ - } bit; - } OUT_LINK_ADDR_CH0; - - union { - __IOM uint32_t reg; /*!< TX CH0 state register */ - - struct { - __IM uint32_t OUTLINK_DSCR_ADDR_CH0 : 18;/*!< This register stores the current outlink descriptor's address. */ - __IM uint32_t OUT_DSCR_STATE_CH0 : 2; /*!< This register stores the current descriptor state machine state. */ - __IM uint32_t OUT_STATE_CH0 : 4; /*!< This register stores the current control module state machine - state. */ - __IM uint32_t OUT_RESET_AVAIL_CH0 : 1; /*!< This register indicate that if the channel reset is safety. */ - uint32_t : 7; - } bit; - } OUT_STATE_CH0; - - union { - __IOM uint32_t reg; /*!< TX CH0 eof des addr register */ - - struct { - __IM uint32_t OUT_EOF_DES_ADDR_CH0 : 32; /*!< This register stores the address of the outlink descriptor when - the EOF bit in this descriptor is 1. */ - } bit; - } OUT_EOF_DES_ADDR_CH0; - - union { - __IOM uint32_t reg; /*!< TX CH0 next dscr addr register */ - - struct { - __IM uint32_t OUTLINK_DSCR_CH0 : 32; /*!< The address of the next outlink descriptor address y. */ - } bit; - } OUT_DSCR_CH0; - - union { - __IOM uint32_t reg; /*!< TX CH0 last dscr addr register */ - - struct { - __IM uint32_t OUTLINK_DSCR_BF0_CH0 : 32; /*!< The address of the last outlink descriptor's next address y-1. */ - } bit; - } OUT_DSCR_BF0_CH0; - - union { - __IOM uint32_t reg; /*!< TX CH0 second-to-last dscr addr register */ - - struct { - __IM uint32_t OUTLINK_DSCR_BF1_CH0 : 32; /*!< The address of the second-to-last outlink descriptor's next - address y-2. */ - } bit; - } OUT_DSCR_BF1_CH0; - __IM uint32_t RESERVED; - - union { - __IOM uint32_t reg; /*!< TX CH0 arb register */ - - struct { - __IOM uint32_t OUT_ARB_TOKEN_NUM_CH0 : 4; /*!< Set the max number of token count of arbiter */ - __IOM uint32_t EXTER_OUT_ARB_PRIORITY_CH0 : 2;/*!< Set the priority of channel */ - uint32_t : 26; - } bit; - } OUT_ARB_CH0; - - union { - __IOM uint32_t reg; /*!< TX CH0 reorder status register */ - - struct { - __IM uint32_t OUTFIFO_RO_CNT_CH0 : 2; /*!< The register stores the 8byte number of the data in reorder - Tx FIFO for channel 0. */ - uint32_t : 4; - __IM uint32_t OUT_RO_WR_STATE_CH0 : 2; /*!< The register stores the state of read ram of reorder */ - __IM uint32_t OUT_RO_RD_STATE_CH0 : 2; /*!< The register stores the state of write ram of reorder */ - __IM uint32_t OUT_PIXEL_BYTE_CH0 : 4; /*!< the number of bytes contained in a pixel at TX channel 0: 1byte - 1: 1.5bytes 2 : 2bytes 3: 2.5bytes 4: 3bytes 5: 4bytes */ - __IM uint32_t OUT_BURST_BLOCK_NUM_CH0 : 4;/*!< the number of macro blocks contained in a burst of data at TX - channel */ - uint32_t : 14; - } bit; - } OUT_RO_STATUS_CH0; - - union { - __IOM uint32_t reg; /*!< TX CH0 reorder power config register */ - - struct { - uint32_t : 4; - __IOM uint32_t OUT_RO_RAM_FORCE_PD_CH0 : 1;/*!< dma reorder ram power down */ - __IOM uint32_t OUT_RO_RAM_FORCE_PU_CH0 : 1;/*!< dma reorder ram power up */ - __IOM uint32_t OUT_RO_RAM_CLK_FO_CH0 : 1; /*!< 1: Force to open the clock and bypass the gate-clock when accessing - the RAM in DMA. 0: A gate-clock will be used when accessing - the RAM in DMA. */ - uint32_t : 25; - } bit; - } OUT_RO_PD_CONF_CH0; - __IM uint32_t RESERVED1[2]; - - union { - __IOM uint32_t reg; /*!< tx CH0 mode enable register */ - - struct { - __IOM uint32_t OUT_TEST_MODE_ENABLE_CH0 : 1;/*!< tx CH0 test mode enable.0 : H264_DMA work in normal mode.1 : - H264_DMA work in test mode */ - uint32_t : 31; - } bit; - } OUT_MODE_ENABLE_CH0; - - union { - __IOM uint32_t reg; /*!< tx CH0 test mode yuv value register */ - - struct { - __IOM uint32_t OUT_TEST_Y_VALUE_CH0 : 8; /*!< tx CH0 test mode y value */ - __IOM uint32_t OUT_TEST_U_VALUE_CH0 : 8; /*!< tx CH0 test mode u value */ - __IOM uint32_t OUT_TEST_V_VALUE_CH0 : 8; /*!< tx CH0 test mode v value */ - uint32_t : 8; - } bit; - } OUT_MODE_YUV_CH0; - __IM uint32_t RESERVED2[4]; - - union { - __IOM uint32_t reg; /*!< TX CH0 ETM config register */ - - struct { - __IOM uint32_t OUT_ETM_EN_CH0 : 1; /*!< Set this bit to 1 to enable ETM task function */ - __IOM uint32_t OUT_ETM_LOOP_EN_CH0 : 1; /*!< when this bit is 1, dscr can be processed after receiving a - task */ - __IOM uint32_t OUT_DSCR_TASK_MAK_CH0 : 2; /*!< ETM dscr_ready maximum cache numbers */ - uint32_t : 28; - } bit; - } OUT_ETM_CONF_CH0; - __IM uint32_t RESERVED3; - - union { - __IOM uint32_t reg; /*!< tx CH0 buf len register */ - - struct { - __IM uint32_t OUT_CMDFIFO_BUF_LEN_HB_CH0 : 13;/*!< only for debug */ - uint32_t : 19; - } bit; - } OUT_BUF_LEN_CH0; - - union { - __IOM uint32_t reg; /*!< tx CH0 fifo byte cnt register */ - - struct { - __IM uint32_t OUT_CMDFIFO_OUTFIFO_BCNT_CH0 : 10;/*!< only for debug */ - uint32_t : 22; - } bit; - } OUT_FIFO_BCNT_CH0; - - union { - __IOM uint32_t reg; /*!< tx CH0 push byte cnt register */ - - struct { - __IM uint32_t OUT_CMDFIFO_PUSH_BYTECNT_CH0 : 8;/*!< only for debug */ - uint32_t : 24; - } bit; - } OUT_PUSH_BYTECNT_CH0; - - union { - __IOM uint32_t reg; /*!< tx CH0 xaddr register */ - - struct { - __IM uint32_t OUT_CMDFIFO_XADDR_CH0 : 32;/*!< only for debug */ - } bit; - } OUT_XADDR_CH0; - __IM uint32_t RESERVED4[32]; - - union { - __IOM uint32_t reg; /*!< TX CH1 config0 register */ - - struct { - __IOM uint32_t OUT_AUTO_WRBACK_CH1 : 1; /*!< Set this bit to enable automatic outlink-writeback when all - the data pointed by outlink descriptor has been received. */ - __IOM uint32_t OUT_EOF_MODE_CH1 : 1; /*!< EOF flag generation mode when receiving data. 1: EOF flag for - Tx channel 0 is generated when data need to read has been - popped from FIFO in DMA */ - __IOM uint32_t OUTDSCR_BURST_EN_CH1 : 1; /*!< Set this bit to 1 to enable INCR burst transfer for Tx channel - 0 reading link descriptor when accessing internal SRAM. */ - __IOM uint32_t OUT_ECC_AES_EN_CH1 : 1; /*!< When access address space is ecc/aes area, this bit should be - set to 1. In this case, the start address of square should - be 16-bit aligned. The width of square multiply byte number - of one pixel should be 16-bit aligned. */ - __IOM uint32_t OUT_CHECK_OWNER_CH1 : 1; /*!< Set this bit to enable checking the owner attribute of the link - descriptor. */ - uint32_t : 1; - __IOM uint32_t OUT_MEM_BURST_LENGTH_CH1 : 3;/*!< Block size of Tx channel 1. 0: single 1: 16 bytes 2: 32 bytes - 3: 64 bytes 4: 128 64 bytes */ - uint32_t : 3; - __IOM uint32_t OUT_PAGE_BOUND_EN_CH1 : 1; /*!< Set this bit to 1 to make sure AXI read data don't cross the - address boundary which define by mem_burst_length */ - uint32_t : 11; - __IOM uint32_t OUT_RST_CH1 : 1; /*!< Write 1 then write 0 to this bit to reset TX channel */ - __IOM uint32_t OUT_CMD_DISABLE_CH1 : 1; /*!< Write 1 before reset and write 0 after reset */ - __IOM uint32_t OUT_ARB_WEIGHT_OPT_DIS_CH1 : 1;/*!< Set this bit to 1 to disable arbiter optimum weight function. */ - uint32_t : 5; - } bit; - } OUT_CONF0_CH1; - - union { - __IOM uint32_t reg; /*!< TX CH1 interrupt raw register */ - - struct { - __IOM uint32_t OUT_DONE_CH1_INT_RAW : 1; /*!< The raw interrupt bit turns to high level when the last data - pointed by one outlink descriptor has been transmitted - to peripherals for Tx channel 0. */ - __IOM uint32_t OUT_EOF_CH1_INT_RAW : 1; /*!< The raw interrupt bit turns to high level when the last data - pointed by one outlink descriptor has been read from memory - for Tx channel 0. */ - __IOM uint32_t OUT_DSCR_ERR_CH1_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when detecting outlink - descriptor error, including owner error, the second and - third word error of outlink descriptor for Tx channel 0. */ - __IOM uint32_t OUT_TOTAL_EOF_CH1_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when data corresponding - a outlink (includes one link descriptor or few link descriptors) - is transmitted out for Tx channel 0. */ - __IOM uint32_t OUTFIFO_OVF_L1_CH1_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when fifo is overflow. */ - __IOM uint32_t OUTFIFO_UDF_L1_CH1_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when fifo is underflow. */ - __IOM uint32_t OUTFIFO_OVF_L2_CH1_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when fifo is overflow. */ - __IOM uint32_t OUTFIFO_UDF_L2_CH1_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when fifo is underflow. */ - __IOM uint32_t OUT_DSCR_TASK_OVF_CH1_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when dscr ready task - fifo is overflow. */ - uint32_t : 23; - } bit; - } OUT_INT_RAW_CH1; - - union { - __IOM uint32_t reg; /*!< TX CH1 interrupt ena register */ - - struct { - __IOM uint32_t OUT_DONE_CH1_INT_ENA : 1; /*!< The interrupt enable bit for the OUT_DONE_CH_INT interrupt. */ - __IOM uint32_t OUT_EOF_CH1_INT_ENA : 1; /*!< The interrupt enable bit for the OUT_EOF_CH_INT interrupt. */ - __IOM uint32_t OUT_DSCR_ERR_CH1_INT_ENA : 1;/*!< The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. */ - __IOM uint32_t OUT_TOTAL_EOF_CH1_INT_ENA : 1;/*!< The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. */ - __IOM uint32_t OUTFIFO_OVF_L1_CH1_INT_ENA : 1;/*!< The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. */ - __IOM uint32_t OUTFIFO_UDF_L1_CH1_INT_ENA : 1;/*!< The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. */ - __IOM uint32_t OUTFIFO_OVF_L2_CH1_INT_ENA : 1;/*!< The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. */ - __IOM uint32_t OUTFIFO_UDF_L2_CH1_INT_ENA : 1;/*!< The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. */ - __IOM uint32_t OUT_DSCR_TASK_OVF_CH1_INT_ENA : 1;/*!< The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. */ - uint32_t : 23; - } bit; - } OUT_INT_ENA_CH1; - - union { - __IOM uint32_t reg; /*!< TX CH1 interrupt st register */ - - struct { - __IM uint32_t OUT_DONE_CH1_INT_ST : 1; /*!< The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. */ - __IM uint32_t OUT_EOF_CH1_INT_ST : 1; /*!< The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. */ - __IM uint32_t OUT_DSCR_ERR_CH1_INT_ST : 1;/*!< The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. */ - __IM uint32_t OUT_TOTAL_EOF_CH1_INT_ST : 1;/*!< The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. */ - __IM uint32_t OUTFIFO_OVF_L1_CH1_INT_ST : 1;/*!< The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. */ - __IM uint32_t OUTFIFO_UDF_L1_CH1_INT_ST : 1;/*!< The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. */ - __IM uint32_t OUTFIFO_OVF_L2_CH1_INT_ST : 1;/*!< The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. */ - __IM uint32_t OUTFIFO_UDF_L2_CH1_INT_ST : 1;/*!< The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. */ - __IM uint32_t OUT_DSCR_TASK_OVF_CH1_INT_ST : 1;/*!< The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT - interrupt. */ - uint32_t : 23; - } bit; - } OUT_INT_ST_CH1; - - union { - __IOM uint32_t reg; /*!< TX CH1 interrupt clr register */ - - struct { - __OM uint32_t OUT_DONE_CH1_INT_CLR : 1; /*!< Set this bit to clear the OUT_DONE_CH_INT interrupt. */ - __OM uint32_t OUT_EOF_CH1_INT_CLR : 1; /*!< Set this bit to clear the OUT_EOF_CH_INT interrupt. */ - __OM uint32_t OUT_DSCR_ERR_CH1_INT_CLR : 1;/*!< Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. */ - __OM uint32_t OUT_TOTAL_EOF_CH1_INT_CLR : 1;/*!< Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. */ - __OM uint32_t OUTFIFO_OVF_L1_CH1_INT_CLR : 1;/*!< Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. */ - __OM uint32_t OUTFIFO_UDF_L1_CH1_INT_CLR : 1;/*!< Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. */ - __OM uint32_t OUTFIFO_OVF_L2_CH1_INT_CLR : 1;/*!< Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. */ - __OM uint32_t OUTFIFO_UDF_L2_CH1_INT_CLR : 1;/*!< Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. */ - __OM uint32_t OUT_DSCR_TASK_OVF_CH1_INT_CLR : 1;/*!< Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. */ - uint32_t : 23; - } bit; - } OUT_INT_CLR_CH1; - - union { - __IOM uint32_t reg; /*!< TX CH1 outfifo status register */ - - struct { - __IM uint32_t OUTFIFO_FULL_L2_CH1 : 1; /*!< Tx FIFO full signal for Tx channel 1. */ - __IM uint32_t OUTFIFO_EMPTY_L2_CH1 : 1; /*!< Tx FIFO empty signal for Tx channel 1. */ - __IM uint32_t OUTFIFO_CNT_L2_CH1 : 4; /*!< The register stores the byte number of the data in Tx FIFO for - Tx channel 1. */ - __IM uint32_t OUTFIFO_FULL_L1_CH1 : 1; /*!< Tx FIFO full signal for Tx channel 1. */ - __IM uint32_t OUTFIFO_EMPTY_L1_CH1 : 1; /*!< Tx FIFO empty signal for Tx channel 1. */ - __IM uint32_t OUTFIFO_CNT_L1_CH1 : 5; /*!< The register stores the byte number of the data in Tx FIFO for - Tx channel 1. */ - uint32_t : 3; - __IM uint32_t OUTFIFO_FULL_L3_CH1 : 1; /*!< Tx FIFO full signal for Tx channel 1. */ - __IM uint32_t OUTFIFO_EMPTY_L3_CH1 : 1; /*!< Tx FIFO empty signal for Tx channel 1. */ - __IM uint32_t OUTFIFO_CNT_L3_CH1 : 2; /*!< The register stores the byte number of the data in Tx FIFO for - Tx channel 1. */ - uint32_t : 12; - } bit; - } OUTFIFO_STATUS_CH1; - - union { - __IOM uint32_t reg; /*!< TX CH1 outfifo push register */ - - struct { - __IOM uint32_t OUTFIFO_WDATA_CH1 : 10; /*!< This register stores the data that need to be pushed into DMA - Tx FIFO. */ - __IOM uint32_t OUTFIFO_PUSH_CH1 : 1; /*!< Set this bit to push data into DMA Tx FIFO. */ - uint32_t : 21; - } bit; - } OUT_PUSH_CH1; - - union { - __IOM uint32_t reg; /*!< TX CH1 out_link dscr ctrl register */ - - struct { - uint32_t : 20; - __IOM uint32_t OUTLINK_STOP_CH1 : 1; /*!< Set this bit to stop dealing with the outlink descriptors. */ - __IOM uint32_t OUTLINK_START_CH1 : 1; /*!< Set this bit to start dealing with the outlink descriptors. */ - __IOM uint32_t OUTLINK_RESTART_CH1 : 1; /*!< Set this bit to restart a new outlink from the last address. */ - __IM uint32_t OUTLINK_PARK_CH1 : 1; /*!< 1: the outlink descriptor's FSM is in idle state. 0: the outlink - descriptor's FSM is working. */ - uint32_t : 8; - } bit; - } OUT_LINK_CONF_CH1; - - union { - __IOM uint32_t reg; /*!< TX CH1 out_link dscr addr register */ - - struct { - __IOM uint32_t OUTLINK_ADDR_CH1 : 32; /*!< This register stores the first outlink descriptor's address. */ - } bit; - } OUT_LINK_ADDR_CH1; - - union { - __IOM uint32_t reg; /*!< TX CH1 state register */ - - struct { - __IM uint32_t OUTLINK_DSCR_ADDR_CH1 : 18;/*!< This register stores the current outlink descriptor's address. */ - __IM uint32_t OUT_DSCR_STATE_CH1 : 2; /*!< This register stores the current descriptor state machine state. */ - __IM uint32_t OUT_STATE_CH1 : 4; /*!< This register stores the current control module state machine - state. */ - __IM uint32_t OUT_RESET_AVAIL_CH1 : 1; /*!< This register indicate that if the channel reset is safety. */ - uint32_t : 7; - } bit; - } OUT_STATE_CH1; - - union { - __IOM uint32_t reg; /*!< TX CH1 eof des addr register */ - - struct { - __IM uint32_t OUT_EOF_DES_ADDR_CH1 : 32; /*!< This register stores the address of the outlink descriptor when - the EOF bit in this descriptor is 1. */ - } bit; - } OUT_EOF_DES_ADDR_CH1; - - union { - __IOM uint32_t reg; /*!< TX CH1 next dscr addr register */ - - struct { - __IM uint32_t OUTLINK_DSCR_CH1 : 32; /*!< The address of the next outlink descriptor address y. */ - } bit; - } OUT_DSCR_CH1; - - union { - __IOM uint32_t reg; /*!< TX CH1 last dscr addr register */ - - struct { - __IM uint32_t OUTLINK_DSCR_BF0_CH1 : 32; /*!< The address of the last outlink descriptor's next address y-1. */ - } bit; - } OUT_DSCR_BF0_CH1; - - union { - __IOM uint32_t reg; /*!< TX CH1 second-to-last dscr addr register */ - - struct { - __IM uint32_t OUTLINK_DSCR_BF1_CH1 : 32; /*!< The address of the second-to-last outlink descriptor's next - address y-2. */ - } bit; - } OUT_DSCR_BF1_CH1; - __IM uint32_t RESERVED5; - - union { - __IOM uint32_t reg; /*!< TX CH1 arb register */ - - struct { - __IOM uint32_t OUT_ARB_TOKEN_NUM_CH1 : 4; /*!< Set the max number of token count of arbiter */ - uint32_t : 2; - __IOM uint32_t INTER_OUT_ARB_PRIORITY_CH1 : 1;/*!< Set the priority of channel */ - uint32_t : 25; - } bit; - } OUT_ARB_CH1; - __IM uint32_t RESERVED6[10]; - - union { - __IOM uint32_t reg; /*!< TX CH1 ETM config register */ - - struct { - __IOM uint32_t OUT_ETM_EN_CH1 : 1; /*!< Set this bit to 1 to enable ETM task function */ - __IOM uint32_t OUT_ETM_LOOP_EN_CH1 : 1; /*!< when this bit is 1, dscr can be processed after receiving a - task */ - __IOM uint32_t OUT_DSCR_TASK_MAK_CH1 : 2; /*!< ETM dscr_ready maximum cache numbers */ - uint32_t : 28; - } bit; - } OUT_ETM_CONF_CH1; - __IM uint32_t RESERVED7; - - union { - __IOM uint32_t reg; /*!< tx CH1 buf len register */ - - struct { - __IM uint32_t OUT_CMDFIFO_BUF_LEN_HB_CH1 : 13;/*!< only for debug */ - uint32_t : 19; - } bit; - } OUT_BUF_LEN_CH1; - - union { - __IOM uint32_t reg; /*!< tx CH1 fifo byte cnt register */ - - struct { - __IM uint32_t OUT_CMDFIFO_OUTFIFO_BCNT_CH1 : 10;/*!< only for debug */ - uint32_t : 22; - } bit; - } OUT_FIFO_BCNT_CH1; - - union { - __IOM uint32_t reg; /*!< tx CH1 push byte cnt register */ - - struct { - __IM uint32_t OUT_CMDFIFO_PUSH_BYTECNT_CH1 : 8;/*!< only for debug */ - uint32_t : 24; - } bit; - } OUT_PUSH_BYTECNT_CH1; - - union { - __IOM uint32_t reg; /*!< tx CH1 xaddr register */ - - struct { - __IM uint32_t OUT_CMDFIFO_XADDR_CH1 : 32;/*!< only for debug */ - } bit; - } OUT_XADDR_CH1; - __IM uint32_t RESERVED8[32]; - - union { - __IOM uint32_t reg; /*!< TX CH2 config0 register */ - - struct { - __IOM uint32_t OUT_AUTO_WRBACK_CH2 : 1; /*!< Set this bit to enable automatic outlink-writeback when all - the data pointed by outlink descriptor has been received. */ - __IOM uint32_t OUT_EOF_MODE_CH2 : 1; /*!< EOF flag generation mode when receiving data. 1: EOF flag for - Tx channel 0 is generated when data need to read has been - popped from FIFO in DMA */ - __IOM uint32_t OUTDSCR_BURST_EN_CH2 : 1; /*!< Set this bit to 1 to enable INCR burst transfer for Tx channel - 0 reading link descriptor when accessing internal SRAM. */ - __IOM uint32_t OUT_ECC_AES_EN_CH2 : 1; /*!< When access address space is ecc/aes area, this bit should be - set to 1. In this case, the start address of square should - be 16-bit aligned. The width of square multiply byte number - of one pixel should be 16-bit aligned. */ - __IOM uint32_t OUT_CHECK_OWNER_CH2 : 1; /*!< Set this bit to enable checking the owner attribute of the link - descriptor. */ - uint32_t : 1; - __IOM uint32_t OUT_MEM_BURST_LENGTH_CH2 : 3;/*!< Block size of Tx channel 2. 0: single 1: 16 bytes 2: 32 bytes - 3: 64 bytes 4: 128 bytes */ - uint32_t : 3; - __IOM uint32_t OUT_PAGE_BOUND_EN_CH2 : 1; /*!< Set this bit to 1 to make sure AXI read data don't cross the - address boundary which define by mem_burst_length */ - uint32_t : 11; - __IOM uint32_t OUT_RST_CH2 : 1; /*!< Write 1 then write 0 to this bit to reset TX channel */ - __IOM uint32_t OUT_CMD_DISABLE_CH2 : 1; /*!< Write 1 before reset and write 0 after reset */ - __IOM uint32_t OUT_ARB_WEIGHT_OPT_DIS_CH2 : 1;/*!< Set this bit to 1 to disable arbiter optimum weight function. */ - uint32_t : 5; - } bit; - } OUT_CONF0_CH2; - - union { - __IOM uint32_t reg; /*!< TX CH2 interrupt raw register */ - - struct { - __IOM uint32_t OUT_DONE_CH2_INT_RAW : 1; /*!< The raw interrupt bit turns to high level when the last data - pointed by one outlink descriptor has been transmitted - to peripherals for Tx channel 0. */ - __IOM uint32_t OUT_EOF_CH2_INT_RAW : 1; /*!< The raw interrupt bit turns to high level when the last data - pointed by one outlink descriptor has been read from memory - for Tx channel 0. */ - __IOM uint32_t OUT_DSCR_ERR_CH2_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when detecting outlink - descriptor error, including owner error, the second and - third word error of outlink descriptor for Tx channel 0. */ - __IOM uint32_t OUT_TOTAL_EOF_CH2_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when data corresponding - a outlink (includes one link descriptor or few link descriptors) - is transmitted out for Tx channel 0. */ - __IOM uint32_t OUTFIFO_OVF_L1_CH2_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when fifo is overflow. */ - __IOM uint32_t OUTFIFO_UDF_L1_CH2_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when fifo is underflow. */ - __IOM uint32_t OUTFIFO_OVF_L2_CH2_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when fifo is overflow. */ - __IOM uint32_t OUTFIFO_UDF_L2_CH2_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when fifo is underflow. */ - __IOM uint32_t OUT_DSCR_TASK_OVF_CH2_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when dscr ready task - fifo is overflow. */ - uint32_t : 23; - } bit; - } OUT_INT_RAW_CH2; - - union { - __IOM uint32_t reg; /*!< TX CH2 interrupt ena register */ - - struct { - __IOM uint32_t OUT_DONE_CH2_INT_ENA : 1; /*!< The interrupt enable bit for the OUT_DONE_CH_INT interrupt. */ - __IOM uint32_t OUT_EOF_CH2_INT_ENA : 1; /*!< The interrupt enable bit for the OUT_EOF_CH_INT interrupt. */ - __IOM uint32_t OUT_DSCR_ERR_CH2_INT_ENA : 1;/*!< The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. */ - __IOM uint32_t OUT_TOTAL_EOF_CH2_INT_ENA : 1;/*!< The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. */ - __IOM uint32_t OUTFIFO_OVF_L1_CH2_INT_ENA : 1;/*!< The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. */ - __IOM uint32_t OUTFIFO_UDF_L1_CH2_INT_ENA : 1;/*!< The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. */ - __IOM uint32_t OUTFIFO_OVF_L2_CH2_INT_ENA : 1;/*!< The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. */ - __IOM uint32_t OUTFIFO_UDF_L2_CH2_INT_ENA : 1;/*!< The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. */ - __IOM uint32_t OUT_DSCR_TASK_OVF_CH2_INT_ENA : 1;/*!< The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. */ - uint32_t : 23; - } bit; - } OUT_INT_ENA_CH2; - - union { - __IOM uint32_t reg; /*!< TX CH2 interrupt st register */ - - struct { - __IM uint32_t OUT_DONE_CH2_INT_ST : 1; /*!< The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. */ - __IM uint32_t OUT_EOF_CH2_INT_ST : 1; /*!< The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. */ - __IM uint32_t OUT_DSCR_ERR_CH2_INT_ST : 1;/*!< The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. */ - __IM uint32_t OUT_TOTAL_EOF_CH2_INT_ST : 1;/*!< The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. */ - __IM uint32_t OUTFIFO_OVF_L1_CH2_INT_ST : 1;/*!< The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. */ - __IM uint32_t OUTFIFO_UDF_L1_CH2_INT_ST : 1;/*!< The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. */ - __IM uint32_t OUTFIFO_OVF_L2_CH2_INT_ST : 1;/*!< The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. */ - __IM uint32_t OUTFIFO_UDF_L2_CH2_INT_ST : 1;/*!< The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. */ - __IM uint32_t OUT_DSCR_TASK_OVF_CH2_INT_ST : 1;/*!< The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT - interrupt. */ - uint32_t : 23; - } bit; - } OUT_INT_ST_CH2; - - union { - __IOM uint32_t reg; /*!< TX CH2 interrupt clr register */ - - struct { - __OM uint32_t OUT_DONE_CH2_INT_CLR : 1; /*!< Set this bit to clear the OUT_DONE_CH_INT interrupt. */ - __OM uint32_t OUT_EOF_CH2_INT_CLR : 1; /*!< Set this bit to clear the OUT_EOF_CH_INT interrupt. */ - __OM uint32_t OUT_DSCR_ERR_CH2_INT_CLR : 1;/*!< Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. */ - __OM uint32_t OUT_TOTAL_EOF_CH2_INT_CLR : 1;/*!< Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. */ - __OM uint32_t OUTFIFO_OVF_L1_CH2_INT_CLR : 1;/*!< Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. */ - __OM uint32_t OUTFIFO_UDF_L1_CH2_INT_CLR : 1;/*!< Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. */ - __OM uint32_t OUTFIFO_OVF_L2_CH2_INT_CLR : 1;/*!< Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. */ - __OM uint32_t OUTFIFO_UDF_L2_CH2_INT_CLR : 1;/*!< Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. */ - __OM uint32_t OUT_DSCR_TASK_OVF_CH2_INT_CLR : 1;/*!< Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. */ - uint32_t : 23; - } bit; - } OUT_INT_CLR_CH2; - - union { - __IOM uint32_t reg; /*!< TX CH2 outfifo status register */ - - struct { - __IM uint32_t OUTFIFO_FULL_L2_CH2 : 1; /*!< Tx FIFO full signal for Tx channel 2. */ - __IM uint32_t OUTFIFO_EMPTY_L2_CH2 : 1; /*!< Tx FIFO empty signal for Tx channel 2. */ - __IM uint32_t OUTFIFO_CNT_L2_CH2 : 4; /*!< The register stores the byte number of the data in Tx FIFO for - Tx channel 2. */ - __IM uint32_t OUTFIFO_FULL_L1_CH2 : 1; /*!< Tx FIFO full signal for Tx channel 2. */ - __IM uint32_t OUTFIFO_EMPTY_L1_CH2 : 1; /*!< Tx FIFO empty signal for Tx channel 2. */ - __IM uint32_t OUTFIFO_CNT_L1_CH2 : 5; /*!< The register stores the byte number of the data in Tx FIFO for - Tx channel 2. */ - uint32_t : 3; - __IM uint32_t OUTFIFO_FULL_L3_CH2 : 1; /*!< Tx FIFO full signal for Tx channel 2. */ - __IM uint32_t OUTFIFO_EMPTY_L3_CH2 : 1; /*!< Tx FIFO empty signal for Tx channel 2. */ - __IM uint32_t OUTFIFO_CNT_L3_CH2 : 2; /*!< The register stores the byte number of the data in Tx FIFO for - Tx channel 2. */ - uint32_t : 12; - } bit; - } OUTFIFO_STATUS_CH2; - - union { - __IOM uint32_t reg; /*!< TX CH2 outfifo push register */ - - struct { - __IOM uint32_t OUTFIFO_WDATA_CH2 : 10; /*!< This register stores the data that need to be pushed into DMA - Tx FIFO. */ - __IOM uint32_t OUTFIFO_PUSH_CH2 : 1; /*!< Set this bit to push data into DMA Tx FIFO. */ - uint32_t : 21; - } bit; - } OUT_PUSH_CH2; - - union { - __IOM uint32_t reg; /*!< TX CH2 out_link dscr ctrl register */ - - struct { - uint32_t : 20; - __IOM uint32_t OUTLINK_STOP_CH2 : 1; /*!< Set this bit to stop dealing with the outlink descriptors. */ - __IOM uint32_t OUTLINK_START_CH2 : 1; /*!< Set this bit to start dealing with the outlink descriptors. */ - __IOM uint32_t OUTLINK_RESTART_CH2 : 1; /*!< Set this bit to restart a new outlink from the last address. */ - __IM uint32_t OUTLINK_PARK_CH2 : 1; /*!< 1: the outlink descriptor's FSM is in idle state. 0: the outlink - descriptor's FSM is working. */ - uint32_t : 8; - } bit; - } OUT_LINK_CONF_CH2; - - union { - __IOM uint32_t reg; /*!< TX CH2 out_link dscr addr register */ - - struct { - __IOM uint32_t OUTLINK_ADDR_CH2 : 32; /*!< This register stores the first outlink descriptor's address. */ - } bit; - } OUT_LINK_ADDR_CH2; - - union { - __IOM uint32_t reg; /*!< TX CH2 state register */ - - struct { - __IM uint32_t OUTLINK_DSCR_ADDR_CH2 : 18;/*!< This register stores the current outlink descriptor's address. */ - __IM uint32_t OUT_DSCR_STATE_CH2 : 2; /*!< This register stores the current descriptor state machine state. */ - __IM uint32_t OUT_STATE_CH2 : 4; /*!< This register stores the current control module state machine - state. */ - __IM uint32_t OUT_RESET_AVAIL_CH2 : 1; /*!< This register indicate that if the channel reset is safety. */ - uint32_t : 7; - } bit; - } OUT_STATE_CH2; - - union { - __IOM uint32_t reg; /*!< TX CH2 eof des addr register */ - - struct { - __IM uint32_t OUT_EOF_DES_ADDR_CH2 : 32; /*!< This register stores the address of the inlink descriptor when - the EOF bit in this descriptor is 1. */ - } bit; - } OUT_EOF_DES_ADDR_CH2; - - union { - __IOM uint32_t reg; /*!< TX CH2 next dscr addr register */ - - struct { - __IM uint32_t OUTLINK_DSCR_CH2 : 32; /*!< The address of the next outlink descriptor address y. */ - } bit; - } OUT_DSCR_CH2; - - union { - __IOM uint32_t reg; /*!< TX CH2 last dscr addr register */ - - struct { - __IM uint32_t OUTLINK_DSCR_BF0_CH2 : 32; /*!< The address of the last outlink descriptor's next address y-1. */ - } bit; - } OUT_DSCR_BF0_CH2; - - union { - __IOM uint32_t reg; /*!< TX CH2 second-to-last dscr addr register */ - - struct { - __IM uint32_t OUTLINK_DSCR_BF1_CH2 : 32; /*!< The address of the second-to-last outlink descriptor's next - address y-2. */ - } bit; - } OUT_DSCR_BF1_CH2; - __IM uint32_t RESERVED9; - - union { - __IOM uint32_t reg; /*!< TX CH2 arb register */ - - struct { - __IOM uint32_t OUT_ARB_TOKEN_NUM_CH2 : 4; /*!< Set the max number of token count of arbiter */ - uint32_t : 2; - __IOM uint32_t INTER_OUT_ARB_PRIORITY_CH2 : 1;/*!< Set the priority of channel */ - uint32_t : 25; - } bit; - } OUT_ARB_CH2; - __IM uint32_t RESERVED10[10]; - - union { - __IOM uint32_t reg; /*!< TX CH2 ETM config register */ - - struct { - __IOM uint32_t OUT_ETM_EN_CH2 : 1; /*!< Set this bit to 1 to enable ETM task function */ - __IOM uint32_t OUT_ETM_LOOP_EN_CH2 : 1; /*!< when this bit is 1, dscr can be processed after receiving a - task */ - __IOM uint32_t OUT_DSCR_TASK_MAK_CH2 : 2; /*!< ETM dscr_ready maximum cache numbers */ - uint32_t : 28; - } bit; - } OUT_ETM_CONF_CH2; - __IM uint32_t RESERVED11; - - union { - __IOM uint32_t reg; /*!< tx CH2 buf len register */ - - struct { - __IM uint32_t OUT_CMDFIFO_BUF_LEN_HB_CH2 : 13;/*!< only for debug */ - uint32_t : 19; - } bit; - } OUT_BUF_LEN_CH2; - - union { - __IOM uint32_t reg; /*!< tx CH2 fifo byte cnt register */ - - struct { - __IM uint32_t OUT_CMDFIFO_OUTFIFO_BCNT_CH2 : 10;/*!< only for debug */ - uint32_t : 22; - } bit; - } OUT_FIFO_BCNT_CH2; - - union { - __IOM uint32_t reg; /*!< tx CH2 push byte cnt register */ - - struct { - __IM uint32_t OUT_CMDFIFO_PUSH_BYTECNT_CH2 : 8;/*!< only for debug */ - uint32_t : 24; - } bit; - } OUT_PUSH_BYTECNT_CH2; - - union { - __IOM uint32_t reg; /*!< tx CH2 xaddr register */ - - struct { - __IM uint32_t OUT_CMDFIFO_XADDR_CH2 : 32;/*!< only for debug */ - } bit; - } OUT_XADDR_CH2; - __IM uint32_t RESERVED12[32]; - - union { - __IOM uint32_t reg; /*!< TX CH3 config0 register */ - - struct { - __IOM uint32_t OUT_AUTO_WRBACK_CH3 : 1; /*!< Set this bit to enable automatic outlink-writeback when all - the data pointed by outlink descriptor has been received. */ - __IOM uint32_t OUT_EOF_MODE_CH3 : 1; /*!< EOF flag generation mode when receiving data. 1: EOF flag for - Tx channel 0 is generated when data need to read has been - popped from FIFO in DMA */ - __IOM uint32_t OUTDSCR_BURST_EN_CH3 : 1; /*!< Set this bit to 1 to enable INCR burst transfer for Tx channel - 0 reading link descriptor when accessing internal SRAM. */ - __IOM uint32_t OUT_ECC_AES_EN_CH3 : 1; /*!< When access address space is ecc/aes area, this bit should be - set to 1. In this case, the start address of square should - be 16-bit aligned. The width of square multiply byte number - of one pixel should be 16-bit aligned. */ - __IOM uint32_t OUT_CHECK_OWNER_CH3 : 1; /*!< Set this bit to enable checking the owner attribute of the link - descriptor. */ - uint32_t : 1; - __IOM uint32_t OUT_MEM_BURST_LENGTH_CH3 : 3;/*!< Block size of Tx channel 3. 0: single 1: 16 bytes 2: 32 bytes - 3: 64 bytes 4: 128 bytes */ - uint32_t : 3; - __IOM uint32_t OUT_PAGE_BOUND_EN_CH3 : 1; /*!< Set this bit to 1 to make sure AXI read data don't cross the - address boundary which define by mem_burst_length */ - uint32_t : 13; - __IOM uint32_t OUT_ARB_WEIGHT_OPT_DIS_CH3 : 1;/*!< Set this bit to 1 to disable arbiter optimum weight function. */ - uint32_t : 5; - } bit; - } OUT_CONF0_CH3; - - union { - __IOM uint32_t reg; /*!< TX CH3 interrupt raw register */ - - struct { - __IOM uint32_t OUT_DONE_CH3_INT_RAW : 1; /*!< The raw interrupt bit turns to high level when the last data - pointed by one outlink descriptor has been transmitted - to peripherals for Tx channel 0. */ - __IOM uint32_t OUT_EOF_CH3_INT_RAW : 1; /*!< The raw interrupt bit turns to high level when the last data - pointed by one outlink descriptor has been read from memory - for Tx channel 0. */ - __IOM uint32_t OUT_DSCR_ERR_CH3_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when detecting outlink - descriptor error, including owner error, the second and - third word error of outlink descriptor for Tx channel 0. */ - __IOM uint32_t OUT_TOTAL_EOF_CH3_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when data corresponding - a outlink (includes one link descriptor or few link descriptors) - is transmitted out for Tx channel 0. */ - __IOM uint32_t OUTFIFO_OVF_L1_CH3_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when fifo is overflow. */ - __IOM uint32_t OUTFIFO_UDF_L1_CH3_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when fifo is underflow. */ - __IOM uint32_t OUTFIFO_OVF_L2_CH3_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when fifo is overflow. */ - __IOM uint32_t OUTFIFO_UDF_L2_CH3_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when fifo is underflow. */ - __IOM uint32_t OUT_DSCR_TASK_OVF_CH3_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when dscr ready task - fifo is overflow. */ - uint32_t : 23; - } bit; - } OUT_INT_RAW_CH3; - - union { - __IOM uint32_t reg; /*!< TX CH3 interrupt ena register */ - - struct { - __IOM uint32_t OUT_DONE_CH3_INT_ENA : 1; /*!< The interrupt enable bit for the OUT_DONE_CH_INT interrupt. */ - __IOM uint32_t OUT_EOF_CH3_INT_ENA : 1; /*!< The interrupt enable bit for the OUT_EOF_CH_INT interrupt. */ - __IOM uint32_t OUT_DSCR_ERR_CH3_INT_ENA : 1;/*!< The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. */ - __IOM uint32_t OUT_TOTAL_EOF_CH3_INT_ENA : 1;/*!< The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. */ - __IOM uint32_t OUTFIFO_OVF_L1_CH3_INT_ENA : 1;/*!< The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. */ - __IOM uint32_t OUTFIFO_UDF_L1_CH3_INT_ENA : 1;/*!< The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. */ - __IOM uint32_t OUTFIFO_OVF_L2_CH3_INT_ENA : 1;/*!< The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. */ - __IOM uint32_t OUTFIFO_UDF_L2_CH3_INT_ENA : 1;/*!< The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. */ - __IOM uint32_t OUT_DSCR_TASK_OVF_CH3_INT_ENA : 1;/*!< The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. */ - uint32_t : 23; - } bit; - } OUT_INT_ENA_CH3; - - union { - __IOM uint32_t reg; /*!< TX CH3 interrupt st register */ - - struct { - __IM uint32_t OUT_DONE_CH3_INT_ST : 1; /*!< The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. */ - __IM uint32_t OUT_EOF_CH3_INT_ST : 1; /*!< The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. */ - __IM uint32_t OUT_DSCR_ERR_CH3_INT_ST : 1;/*!< The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. */ - __IM uint32_t OUT_TOTAL_EOF_CH3_INT_ST : 1;/*!< The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. */ - __IM uint32_t OUTFIFO_OVF_L1_CH3_INT_ST : 1;/*!< The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. */ - __IM uint32_t OUTFIFO_UDF_L1_CH3_INT_ST : 1;/*!< The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. */ - __IM uint32_t OUTFIFO_OVF_L2_CH3_INT_ST : 1;/*!< The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. */ - __IM uint32_t OUTFIFO_UDF_L2_CH3_INT_ST : 1;/*!< The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. */ - __IM uint32_t OUT_DSCR_TASK_OVF_CH3_INT_ST : 1;/*!< The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT - interrupt. */ - uint32_t : 23; - } bit; - } OUT_INT_ST_CH3; - - union { - __IOM uint32_t reg; /*!< TX CH3 interrupt clr register */ - - struct { - __OM uint32_t OUT_DONE_CH3_INT_CLR : 1; /*!< Set this bit to clear the OUT_DONE_CH_INT interrupt. */ - __OM uint32_t OUT_EOF_CH3_INT_CLR : 1; /*!< Set this bit to clear the OUT_EOF_CH_INT interrupt. */ - __OM uint32_t OUT_DSCR_ERR_CH3_INT_CLR : 1;/*!< Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. */ - __OM uint32_t OUT_TOTAL_EOF_CH3_INT_CLR : 1;/*!< Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. */ - __OM uint32_t OUTFIFO_OVF_L1_CH3_INT_CLR : 1;/*!< Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. */ - __OM uint32_t OUTFIFO_UDF_L1_CH3_INT_CLR : 1;/*!< Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. */ - __OM uint32_t OUTFIFO_OVF_L2_CH3_INT_CLR : 1;/*!< Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. */ - __OM uint32_t OUTFIFO_UDF_L2_CH3_INT_CLR : 1;/*!< Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. */ - __OM uint32_t OUT_DSCR_TASK_OVF_CH3_INT_CLR : 1;/*!< Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. */ - uint32_t : 23; - } bit; - } OUT_INT_CLR_CH3; - - union { - __IOM uint32_t reg; /*!< TX CH3 outfifo status register */ - - struct { - __IM uint32_t OUTFIFO_FULL_L2_CH3 : 1; /*!< Tx FIFO full signal for Tx channel 2. */ - __IM uint32_t OUTFIFO_EMPTY_L2_CH3 : 1; /*!< Tx FIFO empty signal for Tx channel 2. */ - __IM uint32_t OUTFIFO_CNT_L2_CH3 : 4; /*!< The register stores the byte number of the data in Tx FIFO for - Tx channel 2. */ - __IM uint32_t OUTFIFO_FULL_L1_CH3 : 1; /*!< Tx FIFO full signal for Tx channel 2. */ - __IM uint32_t OUTFIFO_EMPTY_L1_CH3 : 1; /*!< Tx FIFO empty signal for Tx channel 2. */ - __IM uint32_t OUTFIFO_CNT_L1_CH3 : 5; /*!< The register stores the byte number of the data in Tx FIFO for - Tx channel 2. */ - uint32_t : 3; - __IM uint32_t OUTFIFO_FULL_L3_CH3 : 1; /*!< Tx FIFO full signal for Tx channel 2. */ - __IM uint32_t OUTFIFO_EMPTY_L3_CH3 : 1; /*!< Tx FIFO empty signal for Tx channel 2. */ - __IM uint32_t OUTFIFO_CNT_L3_CH3 : 2; /*!< The register stores the byte number of the data in Tx FIFO for - Tx channel 2. */ - uint32_t : 12; - } bit; - } OUTFIFO_STATUS_CH3; - - union { - __IOM uint32_t reg; /*!< TX CH3 outfifo push register */ - - struct { - __IOM uint32_t OUTFIFO_WDATA_CH3 : 10; /*!< This register stores the data that need to be pushed into DMA - Tx FIFO. */ - __IOM uint32_t OUTFIFO_PUSH_CH3 : 1; /*!< Set this bit to push data into DMA Tx FIFO. */ - uint32_t : 21; - } bit; - } OUT_PUSH_CH3; - - union { - __IOM uint32_t reg; /*!< TX CH3 out_link dscr ctrl register */ - - struct { - uint32_t : 20; - __IOM uint32_t OUTLINK_STOP_CH3 : 1; /*!< Set this bit to stop dealing with the outlink descriptors. */ - __IOM uint32_t OUTLINK_START_CH3 : 1; /*!< Set this bit to start dealing with the outlink descriptors. */ - __IOM uint32_t OUTLINK_RESTART_CH3 : 1; /*!< Set this bit to restart a new outlink from the last address. */ - __IM uint32_t OUTLINK_PARK_CH3 : 1; /*!< 1: the outlink descriptor's FSM is in idle state. 0: the outlink - descriptor's FSM is working. */ - uint32_t : 8; - } bit; - } OUT_LINK_CONF_CH3; - - union { - __IOM uint32_t reg; /*!< TX CH3 out_link dscr addr register */ - - struct { - __IOM uint32_t OUTLINK_ADDR_CH3 : 32; /*!< This register stores the first outlink descriptor's address. */ - } bit; - } OUT_LINK_ADDR_CH3; - - union { - __IOM uint32_t reg; /*!< TX CH3 state register */ - - struct { - __IM uint32_t OUTLINK_DSCR_ADDR_CH3 : 18;/*!< This register stores the current outlink descriptor's address. */ - __IM uint32_t OUT_DSCR_STATE_CH3 : 2; /*!< This register stores the current descriptor state machine state. */ - __IM uint32_t OUT_STATE_CH3 : 4; /*!< This register stores the current control module state machine - state. */ - uint32_t : 8; - } bit; - } OUT_STATE_CH3; - - union { - __IOM uint32_t reg; /*!< TX CH3 eof des addr register */ - - struct { - __IM uint32_t OUT_EOF_DES_ADDR_CH3 : 32; /*!< This register stores the address of the inlink descriptor when - the EOF bit in this descriptor is 1. */ - } bit; - } OUT_EOF_DES_ADDR_CH3; - - union { - __IOM uint32_t reg; /*!< TX CH3 next dscr addr register */ - - struct { - __IM uint32_t OUTLINK_DSCR_CH3 : 32; /*!< The address of the next outlink descriptor address y. */ - } bit; - } OUT_DSCR_CH3; - - union { - __IOM uint32_t reg; /*!< TX CH3 last dscr addr register */ - - struct { - __IM uint32_t OUTLINK_DSCR_BF0_CH3 : 32; /*!< The address of the last outlink descriptor's next address y-1. */ - } bit; - } OUT_DSCR_BF0_CH3; - - union { - __IOM uint32_t reg; /*!< TX CH3 second-to-last dscr addr register */ - - struct { - __IM uint32_t OUTLINK_DSCR_BF1_CH3 : 32; /*!< The address of the second-to-last outlink descriptor's next - address y-2. */ - } bit; - } OUT_DSCR_BF1_CH3; - __IM uint32_t RESERVED13; - - union { - __IOM uint32_t reg; /*!< TX CH3 arb register */ - - struct { - __IOM uint32_t OUT_ARB_TOKEN_NUM_CH3 : 4; /*!< Set the max number of token count of arbiter */ - __IOM uint32_t EXTER_OUT_ARB_PRIORITY_CH3 : 2;/*!< Set the priority of channel */ - uint32_t : 26; - } bit; - } OUT_ARB_CH3; - __IM uint32_t RESERVED14[10]; - - union { - __IOM uint32_t reg; /*!< TX CH3 ETM config register */ - - struct { - __IOM uint32_t OUT_ETM_EN_CH3 : 1; /*!< Set this bit to 1 to enable ETM task function */ - __IOM uint32_t OUT_ETM_LOOP_EN_CH3 : 1; /*!< when this bit is 1, dscr can be processed after receiving a - task */ - __IOM uint32_t OUT_DSCR_TASK_MAK_CH3 : 2; /*!< ETM dscr_ready maximum cache numbers */ - uint32_t : 28; - } bit; - } OUT_ETM_CONF_CH3; - __IM uint32_t RESERVED15; - - union { - __IOM uint32_t reg; /*!< tx CH3 buf len register */ - - struct { - __IM uint32_t OUT_CMDFIFO_BUF_LEN_HB_CH3 : 13;/*!< only for debug */ - uint32_t : 19; - } bit; - } OUT_BUF_LEN_CH3; - - union { - __IOM uint32_t reg; /*!< tx CH3 fifo byte cnt register */ - - struct { - __IM uint32_t OUT_CMDFIFO_OUTFIFO_BCNT_CH3 : 10;/*!< only for debug */ - uint32_t : 22; - } bit; - } OUT_FIFO_BCNT_CH3; - - union { - __IOM uint32_t reg; /*!< tx CH3 push byte cnt register */ - - struct { - __IM uint32_t OUT_CMDFIFO_PUSH_BYTECNT_CH3 : 8;/*!< only for debug */ - uint32_t : 24; - } bit; - } OUT_PUSH_BYTECNT_CH3; - - union { - __IOM uint32_t reg; /*!< tx CH3 xaddr register */ - - struct { - __IM uint32_t OUT_CMDFIFO_XADDR_CH3 : 32;/*!< only for debug */ - } bit; - } OUT_XADDR_CH3; - - union { - __IOM uint32_t reg; /*!< tx CH3 block buf len register */ - - struct { - __IM uint32_t OUT_BLOCK_BUF_LEN_CH3 : 28;/*!< only for debug */ - uint32_t : 4; - } bit; - } OUT_BLOCK_BUF_LEN_CH3; - __IM uint32_t RESERVED16[31]; - - union { - __IOM uint32_t reg; /*!< TX CH4 config0 register */ - - struct { - __IOM uint32_t OUT_AUTO_WRBACK_CH4 : 1; /*!< Set this bit to enable automatic outlink-writeback when all - the data pointed by outlink descriptor has been received. */ - __IOM uint32_t OUT_EOF_MODE_CH4 : 1; /*!< EOF flag generation mode when receiving data. 1: EOF flag for - Tx channel 0 is generated when data need to read has been - popped from FIFO in DMA */ - __IOM uint32_t OUTDSCR_BURST_EN_CH4 : 1; /*!< Set this bit to 1 to enable INCR burst transfer for Tx channel - 0 reading link descriptor when accessing internal SRAM. */ - __IOM uint32_t OUT_ECC_AES_EN_CH4 : 1; /*!< When access address space is ecc/aes area, this bit should be - set to 1. In this case, the start address of square should - be 16-bit aligned. The width of square multiply byte number - of one pixel should be 16-bit aligned. */ - __IOM uint32_t OUT_CHECK_OWNER_CH4 : 1; /*!< Set this bit to enable checking the owner attribute of the link - descriptor. */ - uint32_t : 1; - __IOM uint32_t OUT_MEM_BURST_LENGTH_CH4 : 3;/*!< Block size of Tx channel 4. 0: single 1: 16 bytes 2: 32 bytes - 3: 64 bytes 4: 128 bytes */ - uint32_t : 3; - __IOM uint32_t OUT_PAGE_BOUND_EN_CH4 : 1; /*!< Set this bit to 1 to make sure AXI read data don't cross the - address boundary which define by mem_burst_length */ - uint32_t : 13; - __IOM uint32_t OUT_ARB_WEIGHT_OPT_DIS_CH4 : 1;/*!< Set this bit to 1 to disable arbiter optimum weight function. */ - uint32_t : 5; - } bit; - } OUT_CONF0_CH4; - - union { - __IOM uint32_t reg; /*!< TX CH4 interrupt raw register */ - - struct { - __IOM uint32_t OUT_DONE_CH4_INT_RAW : 1; /*!< The raw interrupt bit turns to high level when the last data - pointed by one outlink descriptor has been transmitted - to peripherals for Tx channel 0. */ - __IOM uint32_t OUT_EOF_CH4_INT_RAW : 1; /*!< The raw interrupt bit turns to high level when the last data - pointed by one outlink descriptor has been read from memory - for Tx channel 0. */ - __IOM uint32_t OUT_DSCR_ERR_CH4_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when detecting outlink - descriptor error, including owner error, the second and - third word error of outlink descriptor for Tx channel 0. */ - __IOM uint32_t OUT_TOTAL_EOF_CH4_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when data corresponding - a outlink (includes one link descriptor or few link descriptors) - is transmitted out for Tx channel 0. */ - __IOM uint32_t OUTFIFO_OVF_L1_CH4_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when fifo is overflow. */ - __IOM uint32_t OUTFIFO_UDF_L1_CH4_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when fifo is underflow. */ - __IOM uint32_t OUTFIFO_OVF_L2_CH4_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when fifo is overflow. */ - __IOM uint32_t OUTFIFO_UDF_L2_CH4_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when fifo is underflow. */ - __IOM uint32_t OUT_DSCR_TASK_OVF_CH4_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when dscr ready task - fifo is overflow. */ - uint32_t : 23; - } bit; - } OUT_INT_RAW_CH4; - - union { - __IOM uint32_t reg; /*!< TX CH4 interrupt ena register */ - - struct { - __IOM uint32_t OUT_DONE_CH4_INT_ENA : 1; /*!< The interrupt enable bit for the OUT_DONE_CH_INT interrupt. */ - __IOM uint32_t OUT_EOF_CH4_INT_ENA : 1; /*!< The interrupt enable bit for the OUT_EOF_CH_INT interrupt. */ - __IOM uint32_t OUT_DSCR_ERR_CH4_INT_ENA : 1;/*!< The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. */ - __IOM uint32_t OUT_TOTAL_EOF_CH4_INT_ENA : 1;/*!< The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. */ - __IOM uint32_t OUTFIFO_OVF_L1_CH4_INT_ENA : 1;/*!< The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. */ - __IOM uint32_t OUTFIFO_UDF_L1_CH4_INT_ENA : 1;/*!< The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. */ - __IOM uint32_t OUTFIFO_OVF_L2_CH4_INT_ENA : 1;/*!< The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. */ - __IOM uint32_t OUTFIFO_UDF_L2_CH4_INT_ENA : 1;/*!< The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. */ - __IOM uint32_t OUT_DSCR_TASK_OVF_CH4_INT_ENA : 1;/*!< The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. */ - uint32_t : 23; - } bit; - } OUT_INT_ENA_CH4; - - union { - __IOM uint32_t reg; /*!< TX CH4 interrupt st register */ - - struct { - __IM uint32_t OUT_DONE_CH4_INT_ST : 1; /*!< The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. */ - __IM uint32_t OUT_EOF_CH4_INT_ST : 1; /*!< The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. */ - __IM uint32_t OUT_DSCR_ERR_CH4_INT_ST : 1;/*!< The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. */ - __IM uint32_t OUT_TOTAL_EOF_CH4_INT_ST : 1;/*!< The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. */ - __IM uint32_t OUTFIFO_OVF_L1_CH4_INT_ST : 1;/*!< The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. */ - __IM uint32_t OUTFIFO_UDF_L1_CH4_INT_ST : 1;/*!< The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. */ - __IM uint32_t OUTFIFO_OVF_L2_CH4_INT_ST : 1;/*!< The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. */ - __IM uint32_t OUTFIFO_UDF_L2_CH4_INT_ST : 1;/*!< The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. */ - __IM uint32_t OUT_DSCR_TASK_OVF_CH4_INT_ST : 1;/*!< The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT - interrupt. */ - uint32_t : 23; - } bit; - } OUT_INT_ST_CH4; - - union { - __IOM uint32_t reg; /*!< TX CH4 interrupt clr register */ - - struct { - __OM uint32_t OUT_DONE_CH4_INT_CLR : 1; /*!< Set this bit to clear the OUT_DONE_CH_INT interrupt. */ - __OM uint32_t OUT_EOF_CH4_INT_CLR : 1; /*!< Set this bit to clear the OUT_EOF_CH_INT interrupt. */ - __OM uint32_t OUT_DSCR_ERR_CH4_INT_CLR : 1;/*!< Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. */ - __OM uint32_t OUT_TOTAL_EOF_CH4_INT_CLR : 1;/*!< Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. */ - __OM uint32_t OUTFIFO_OVF_L1_CH4_INT_CLR : 1;/*!< Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. */ - __OM uint32_t OUTFIFO_UDF_L1_CH4_INT_CLR : 1;/*!< Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. */ - __OM uint32_t OUTFIFO_OVF_L2_CH4_INT_CLR : 1;/*!< Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. */ - __OM uint32_t OUTFIFO_UDF_L2_CH4_INT_CLR : 1;/*!< Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. */ - __OM uint32_t OUT_DSCR_TASK_OVF_CH4_INT_CLR : 1;/*!< Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. */ - uint32_t : 23; - } bit; - } OUT_INT_CLR_CH4; - - union { - __IOM uint32_t reg; /*!< TX CH4 outfifo status register */ - - struct { - __IM uint32_t OUTFIFO_FULL_L2_CH4 : 1; /*!< Tx FIFO full signal for Tx channel 2. */ - __IM uint32_t OUTFIFO_EMPTY_L2_CH4 : 1; /*!< Tx FIFO empty signal for Tx channel 2. */ - __IM uint32_t OUTFIFO_CNT_L2_CH4 : 4; /*!< The register stores the byte number of the data in Tx FIFO for - Tx channel 2. */ - __IM uint32_t OUTFIFO_FULL_L1_CH4 : 1; /*!< Tx FIFO full signal for Tx channel 2. */ - __IM uint32_t OUTFIFO_EMPTY_L1_CH4 : 1; /*!< Tx FIFO empty signal for Tx channel 2. */ - __IM uint32_t OUTFIFO_CNT_L1_CH4 : 5; /*!< The register stores the byte number of the data in Tx FIFO for - Tx channel 2. */ - uint32_t : 3; - __IM uint32_t OUTFIFO_FULL_L3_CH4 : 1; /*!< Tx FIFO full signal for Tx channel 2. */ - __IM uint32_t OUTFIFO_EMPTY_L3_CH4 : 1; /*!< Tx FIFO empty signal for Tx channel 2. */ - __IM uint32_t OUTFIFO_CNT_L3_CH4 : 2; /*!< The register stores the byte number of the data in Tx FIFO for - Tx channel 2. */ - uint32_t : 12; - } bit; - } OUTFIFO_STATUS_CH4; - - union { - __IOM uint32_t reg; /*!< TX CH4 outfifo push register */ - - struct { - __IOM uint32_t OUTFIFO_WDATA_CH4 : 10; /*!< This register stores the data that need to be pushed into DMA - Tx FIFO. */ - __IOM uint32_t OUTFIFO_PUSH_CH4 : 1; /*!< Set this bit to push data into DMA Tx FIFO. */ - uint32_t : 21; - } bit; - } OUT_PUSH_CH4; - - union { - __IOM uint32_t reg; /*!< TX CH4 out_link dscr ctrl register */ - - struct { - uint32_t : 20; - __IOM uint32_t OUTLINK_STOP_CH4 : 1; /*!< Set this bit to stop dealing with the outlink descriptors. */ - __IOM uint32_t OUTLINK_START_CH4 : 1; /*!< Set this bit to start dealing with the outlink descriptors. */ - __IOM uint32_t OUTLINK_RESTART_CH4 : 1; /*!< Set this bit to restart a new outlink from the last address. */ - __IM uint32_t OUTLINK_PARK_CH4 : 1; /*!< 1: the outlink descriptor's FSM is in idle state. 0: the outlink - descriptor's FSM is working. */ - uint32_t : 8; - } bit; - } OUT_LINK_CONF_CH4; - - union { - __IOM uint32_t reg; /*!< TX CH4 out_link dscr addr register */ - - struct { - __IOM uint32_t OUTLINK_ADDR_CH4 : 32; /*!< This register stores the first outlink descriptor's address. */ - } bit; - } OUT_LINK_ADDR_CH4; - - union { - __IOM uint32_t reg; /*!< TX CH4 state register */ - - struct { - __IM uint32_t OUTLINK_DSCR_ADDR_CH4 : 18;/*!< This register stores the current outlink descriptor's address. */ - __IM uint32_t OUT_DSCR_STATE_CH4 : 2; /*!< This register stores the current descriptor state machine state. */ - __IM uint32_t OUT_STATE_CH4 : 4; /*!< This register stores the current control module state machine - state. */ - uint32_t : 8; - } bit; - } OUT_STATE_CH4; - - union { - __IOM uint32_t reg; /*!< TX CH4 eof des addr register */ - - struct { - __IM uint32_t OUT_EOF_DES_ADDR_CH4 : 32; /*!< This register stores the address of the inlink descriptor when - the EOF bit in this descriptor is 1. */ - } bit; - } OUT_EOF_DES_ADDR_CH4; - - union { - __IOM uint32_t reg; /*!< TX CH4 next dscr addr register */ - - struct { - __IM uint32_t OUTLINK_DSCR_CH4 : 32; /*!< The address of the next outlink descriptor address y. */ - } bit; - } OUT_DSCR_CH4; - - union { - __IOM uint32_t reg; /*!< TX CH4 last dscr addr register */ - - struct { - __IM uint32_t OUTLINK_DSCR_BF0_CH4 : 32; /*!< The address of the last outlink descriptor's next address y-1. */ - } bit; - } OUT_DSCR_BF0_CH4; - - union { - __IOM uint32_t reg; /*!< TX CH4 second-to-last dscr addr register */ - - struct { - __IM uint32_t OUTLINK_DSCR_BF1_CH4 : 32; /*!< The address of the second-to-last outlink descriptor's next - address y-2. */ - } bit; - } OUT_DSCR_BF1_CH4; - __IM uint32_t RESERVED17; - - union { - __IOM uint32_t reg; /*!< TX CH4 arb register */ - - struct { - __IOM uint32_t OUT_ARB_TOKEN_NUM_CH4 : 4; /*!< Set the max number of token count of arbiter */ - __IOM uint32_t EXTER_OUT_ARB_PRIORITY_CH4 : 2;/*!< Set the priority of channel */ - uint32_t : 26; - } bit; - } OUT_ARB_CH4; - __IM uint32_t RESERVED18[10]; - - union { - __IOM uint32_t reg; /*!< TX CH4 ETM config register */ - - struct { - __IOM uint32_t OUT_ETM_EN_CH4 : 1; /*!< Set this bit to 1 to enable ETM task function */ - __IOM uint32_t OUT_ETM_LOOP_EN_CH4 : 1; /*!< when this bit is 1, dscr can be processed after receiving a - task */ - __IOM uint32_t OUT_DSCR_TASK_MAK_CH4 : 2; /*!< ETM dscr_ready maximum cache numbers */ - uint32_t : 28; - } bit; - } OUT_ETM_CONF_CH4; - __IM uint32_t RESERVED19; - - union { - __IOM uint32_t reg; /*!< tx CH4 buf len register */ - - struct { - __IM uint32_t OUT_CMDFIFO_BUF_LEN_HB_CH4 : 13;/*!< only for debug */ - uint32_t : 19; - } bit; - } OUT_BUF_LEN_CH4; - - union { - __IOM uint32_t reg; /*!< tx CH4 fifo byte cnt register */ - - struct { - __IM uint32_t OUT_CMDFIFO_OUTFIFO_BCNT_CH4 : 10;/*!< only for debug */ - uint32_t : 22; - } bit; - } OUT_FIFO_BCNT_CH4; - - union { - __IOM uint32_t reg; /*!< tx CH4 push byte cnt register */ - - struct { - __IM uint32_t OUT_CMDFIFO_PUSH_BYTECNT_CH4 : 8;/*!< only for debug */ - uint32_t : 24; - } bit; - } OUT_PUSH_BYTECNT_CH4; - - union { - __IOM uint32_t reg; /*!< tx CH4 xaddr register */ - - struct { - __IM uint32_t OUT_CMDFIFO_XADDR_CH4 : 32;/*!< only for debug */ - } bit; - } OUT_XADDR_CH4; - - union { - __IOM uint32_t reg; /*!< tx CH4 block buf len register */ - - struct { - __IM uint32_t OUT_BLOCK_BUF_LEN_CH4 : 28;/*!< only for debug */ - uint32_t : 4; - } bit; - } OUT_BLOCK_BUF_LEN_CH4; - __IM uint32_t RESERVED20[31]; - - union { - __IOM uint32_t reg; /*!< RX CH0 config0 register */ - - struct { - uint32_t : 2; - __IOM uint32_t INDSCR_BURST_EN_CH0 : 1; /*!< Set this bit to 1 to enable INCR burst transfer for Rx transmitting - link descriptor when accessing SRAM. */ - __IOM uint32_t IN_ECC_AES_EN_CH0 : 1; /*!< When access address space is ecc/aes area, this bit should be - set to 1. In this case, the start address of square should - be 16-bit aligned. The width of square multiply byte number - of one pixel should be 16-bit aligned. */ - __IOM uint32_t IN_CHECK_OWNER_CH0 : 1; /*!< Set this bit to enable checking the owner attribute of the link - descriptor. */ - uint32_t : 1; - __IOM uint32_t IN_MEM_BURST_LENGTH_CH0 : 3;/*!< Block size of Rx channel 0. 0: single 1: 16 bytes 2: 32 bytes - 3: 64 bytes 4: 128 bytes */ - uint32_t : 3; - __IOM uint32_t IN_PAGE_BOUND_EN_CH0 : 1; /*!< Set this bit to 1 to make sure AXI write data don't cross the - address boundary which define by mem_burst_length */ - uint32_t : 11; - __IOM uint32_t IN_RST_CH0 : 1; /*!< Write 1 then write 0 to this bit to reset Rx channel */ - __IOM uint32_t IN_CMD_DISABLE_CH0 : 1; /*!< Write 1 before reset and write 0 after reset */ - __IOM uint32_t IN_ARB_WEIGHT_OPT_DIS_CH0 : 1;/*!< Set this bit to 1 to disable arbiter optimum weight function. */ - uint32_t : 5; - } bit; - } IN_CONF0_CH0; - - union { - __IOM uint32_t reg; /*!< RX CH0 interrupt raw register */ - - struct { - __IOM uint32_t IN_DONE_CH0_INT_RAW : 1; /*!< The raw interrupt bit turns to high level when the last data - pointed by one inlink descriptor has been transmitted to - peripherals for Rx channel 0. */ - __IOM uint32_t IN_SUC_EOF_CH0_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when the last data - pointed by one inlink descriptor has been received and - no data error is detected for Rx channel 0. */ - __IOM uint32_t IN_ERR_EOF_CH0_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when the last data - pointed by one inlink descriptor has been received and - data error is detected */ - __IOM uint32_t IN_DSCR_ERR_CH0_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when detecting inlink - descriptor error, including owner error, the second and - third word error of inlink descriptor for Rx channel 0. */ - __IOM uint32_t INFIFO_OVF_L1_CH0_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when fifo of Rx channel - is overflow. */ - __IOM uint32_t INFIFO_UDF_L1_CH0_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when fifo of Rx channel - is underflow. */ - __IOM uint32_t INFIFO_OVF_L2_CH0_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when fifo of Rx channel - is overflow. */ - __IOM uint32_t INFIFO_UDF_L2_CH0_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when fifo of Rx channel - is underflow. */ - __IOM uint32_t IN_DSCR_EMPTY_CH0_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when the last descriptor - is done but fifo also remain data. */ - __IOM uint32_t IN_DSCR_TASK_OVF_CH0_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when dscr ready task - fifo is overflow. */ - uint32_t : 22; - } bit; - } IN_INT_RAW_CH0; - - union { - __IOM uint32_t reg; /*!< RX CH0 interrupt ena register */ - - struct { - __IOM uint32_t IN_DONE_CH0_INT_ENA : 1; /*!< The interrupt enable bit for the IN_DONE_CH_INT interrupt. */ - __IOM uint32_t IN_SUC_EOF_CH0_INT_ENA : 1;/*!< The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. */ - __IOM uint32_t IN_ERR_EOF_CH0_INT_ENA : 1;/*!< The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. */ - __IOM uint32_t IN_DSCR_ERR_CH0_INT_ENA : 1;/*!< The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. */ - __IOM uint32_t INFIFO_OVF_L1_CH0_INT_ENA : 1;/*!< The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. */ - __IOM uint32_t INFIFO_UDF_L1_CH0_INT_ENA : 1;/*!< The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. */ - __IOM uint32_t INFIFO_OVF_L2_CH0_INT_ENA : 1;/*!< The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. */ - __IOM uint32_t INFIFO_UDF_L2_CH0_INT_ENA : 1;/*!< The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. */ - __IOM uint32_t IN_DSCR_EMPTY_CH0_INT_ENA : 1;/*!< The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. */ - __IOM uint32_t IN_DSCR_TASK_OVF_CH0_INT_ENA : 1;/*!< The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. */ - uint32_t : 22; - } bit; - } IN_INT_ENA_CH0; - - union { - __IOM uint32_t reg; /*!< RX CH0 interrupt st register */ - - struct { - __IM uint32_t IN_DONE_CH0_INT_ST : 1; /*!< The raw interrupt status bit for the IN_DONE_CH_INT interrupt. */ - __IM uint32_t IN_SUC_EOF_CH0_INT_ST : 1; /*!< The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. */ - __IM uint32_t IN_ERR_EOF_CH0_INT_ST : 1; /*!< The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. */ - __IM uint32_t IN_DSCR_ERR_CH0_INT_ST : 1;/*!< The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. */ - __IM uint32_t INFIFO_OVF_L1_CH0_INT_ST : 1;/*!< The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. */ - __IM uint32_t INFIFO_UDF_L1_CH0_INT_ST : 1;/*!< The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. */ - __IM uint32_t INFIFO_OVF_L2_CH0_INT_ST : 1;/*!< The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. */ - __IM uint32_t INFIFO_UDF_L2_CH0_INT_ST : 1;/*!< The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. */ - __IM uint32_t IN_DSCR_EMPTY_CH0_INT_ST : 1;/*!< The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. */ - __IM uint32_t IN_DSCR_TASK_OVF_CH0_INT_ST : 1;/*!< The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT - interrupt. */ - uint32_t : 22; - } bit; - } IN_INT_ST_CH0; - - union { - __IOM uint32_t reg; /*!< RX CH0 interrupt clr register */ - - struct { - __OM uint32_t IN_DONE_CH0_INT_CLR : 1; /*!< Set this bit to clear the IN_DONE_CH_INT interrupt. */ - __OM uint32_t IN_SUC_EOF_CH0_INT_CLR : 1;/*!< Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. */ - __OM uint32_t IN_ERR_EOF_CH0_INT_CLR : 1;/*!< Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. */ - __OM uint32_t IN_DSCR_ERR_CH0_INT_CLR : 1;/*!< Set this bit to clear the INDSCR_ERR_CH_INT interrupt. */ - __OM uint32_t INFIFO_OVF_L1_CH0_INT_CLR : 1;/*!< Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. */ - __OM uint32_t INFIFO_UDF_L1_CH0_INT_CLR : 1;/*!< Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. */ - __OM uint32_t INFIFO_OVF_L2_CH0_INT_CLR : 1;/*!< Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. */ - __OM uint32_t INFIFO_UDF_L2_CH0_INT_CLR : 1;/*!< Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. */ - __OM uint32_t IN_DSCR_EMPTY_CH0_INT_CLR : 1;/*!< Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. */ - __OM uint32_t IN_DSCR_TASK_OVF_CH0_INT_CLR : 1;/*!< Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. */ - uint32_t : 22; - } bit; - } IN_INT_CLR_CH0; - - union { - __IOM uint32_t reg; /*!< RX CH0 INFIFO status register */ - - struct { - __IM uint32_t INFIFO_FULL_L2_CH0 : 1; /*!< Rx FIFO full signal for Rx channel. */ - __IM uint32_t INFIFO_EMPTY_L2_CH0 : 1; /*!< Rx FIFO empty signal for Rx channel. */ - __IM uint32_t INFIFO_CNT_L2_CH0 : 4; /*!< The register stores the byte number of the data in Rx FIFO for - Rx channel. */ - __IM uint32_t INFIFO_FULL_L1_CH0 : 1; /*!< Tx FIFO full signal for Tx channel 0. */ - __IM uint32_t INFIFO_EMPTY_L1_CH0 : 1; /*!< Tx FIFO empty signal for Tx channel 0. */ - __IM uint32_t INFIFO_CNT_L1_CH0 : 5; /*!< The register stores the byte number of the data in Tx FIFO for - Tx channel 0. */ - uint32_t : 3; - __IM uint32_t INFIFO_FULL_L3_CH0 : 1; /*!< Tx FIFO full signal for Tx channel 0. */ - __IM uint32_t INFIFO_EMPTY_L3_CH0 : 1; /*!< Tx FIFO empty signal for Tx channel 0. */ - __IM uint32_t INFIFO_CNT_L3_CH0 : 2; /*!< The register stores the 8byte number of the data in Tx FIFO - for Tx channel 0. */ - uint32_t : 12; - } bit; - } INFIFO_STATUS_CH0; - - union { - __IOM uint32_t reg; /*!< RX CH0 INFIFO pop register */ - - struct { - __IM uint32_t INFIFO_RDATA_CH0 : 11; /*!< This register stores the data popping from DMA Rx FIFO. */ - __IOM uint32_t INFIFO_POP_CH0 : 1; /*!< Set this bit to pop data from DMA Rx FIFO. */ - uint32_t : 20; - } bit; - } IN_POP_CH0; - - union { - __IOM uint32_t reg; /*!< RX CH0 in_link dscr ctrl register */ - - struct { - uint32_t : 20; - __IOM uint32_t INLINK_AUTO_RET_CH0 : 1; /*!< Set this bit to return to current inlink descriptor's address, - when there are some errors in current receiving data. */ - __IOM uint32_t INLINK_STOP_CH0 : 1; /*!< Set this bit to stop dealing with the inlink descriptors. */ - __IOM uint32_t INLINK_START_CH0 : 1; /*!< Set this bit to start dealing with the inlink descriptors. */ - __IOM uint32_t INLINK_RESTART_CH0 : 1; /*!< Set this bit to mount a new inlink descriptor. */ - __IM uint32_t INLINK_PARK_CH0 : 1; /*!< 1: the inlink descriptor's FSM is in idle state. 0: the inlink - descriptor's FSM is working. */ - uint32_t : 7; - } bit; - } IN_LINK_CONF_CH0; - - union { - __IOM uint32_t reg; /*!< RX CH0 in_link dscr addr register */ - - struct { - __IOM uint32_t INLINK_ADDR_CH0 : 32; /*!< This register stores the first inlink descriptor's address. */ - } bit; - } IN_LINK_ADDR_CH0; - - union { - __IOM uint32_t reg; /*!< RX CH0 state register */ - - struct { - __IM uint32_t INLINK_DSCR_ADDR_CH0 : 18; /*!< This register stores the current inlink descriptor's address. */ - __IM uint32_t IN_DSCR_STATE_CH0 : 2; /*!< This register stores the current descriptor state machine state. */ - __IM uint32_t IN_STATE_CH0 : 3; /*!< This register stores the current control module state machine - state. */ - __IM uint32_t IN_RESET_AVAIL_CH0 : 1; /*!< This register indicate that if the channel reset is safety. */ - uint32_t : 8; - } bit; - } IN_STATE_CH0; - - union { - __IOM uint32_t reg; /*!< RX CH0 eof des addr register */ - - struct { - __IM uint32_t IN_SUC_EOF_DES_ADDR_CH0 : 32;/*!< This register stores the address of the inlink descriptor when - the EOF bit in this descriptor is 1. */ - } bit; - } IN_SUC_EOF_DES_ADDR_CH0; - - union { - __IOM uint32_t reg; /*!< RX CH0 err eof des addr register */ - - struct { - __IM uint32_t IN_ERR_EOF_DES_ADDR_CH0 : 32;/*!< This register stores the address of the inlink descriptor when - there are some errors in current receiving data. */ - } bit; - } IN_ERR_EOF_DES_ADDR_CH0; - - union { - __IOM uint32_t reg; /*!< RX CH0 next dscr addr register */ - - struct { - __IM uint32_t INLINK_DSCR_CH0 : 32; /*!< The address of the next inlink descriptor address x. */ - } bit; - } IN_DSCR_CH0; - - union { - __IOM uint32_t reg; /*!< RX CH0 last dscr addr register */ - - struct { - __IM uint32_t INLINK_DSCR_BF0_CH0 : 32; /*!< The address of the last inlink descriptor's next address x-1. */ - } bit; - } IN_DSCR_BF0_CH0; - - union { - __IOM uint32_t reg; /*!< RX CH0 second-to-last dscr addr register */ - - struct { - __IM uint32_t INLINK_DSCR_BF1_CH0 : 32; /*!< The address of the second-to-last inlink descriptor's next address - x-2. */ - } bit; - } IN_DSCR_BF1_CH0; - __IM uint32_t RESERVED21; - - union { - __IOM uint32_t reg; /*!< RX CH0 arb register */ - - struct { - __IOM uint32_t IN_ARB_TOKEN_NUM_CH0 : 4; /*!< Set the max number of token count of arbiter */ - __IOM uint32_t EXTER_IN_ARB_PRIORITY_CH0 : 2;/*!< Set the priority of channel */ - __IOM uint32_t INTER_IN_ARB_PRIORITY_CH0 : 3;/*!< Set the priority of channel */ - uint32_t : 23; - } bit; - } IN_ARB_CH0; - __IM uint32_t RESERVED22; - - union { - __IOM uint32_t reg; /*!< RX CH0 reorder power config register */ - - struct { - uint32_t : 6; - __IOM uint32_t IN_RO_RAM_CLK_FO_CH0 : 1; /*!< 1: Force to open the clock and bypass the gate-clock when accessing - the RAM in DMA. 0: A gate-clock will be used when accessing - the RAM in DMA. */ - uint32_t : 25; - } bit; - } IN_RO_PD_CONF_CH0; - __IM uint32_t RESERVED23[8]; - - union { - __IOM uint32_t reg; /*!< RX CH0 ETM config register */ - - struct { - __IOM uint32_t IN_ETM_EN_CH0 : 1; /*!< Set this bit to 1 to enable ETM task function */ - __IOM uint32_t IN_ETM_LOOP_EN_CH0 : 1; /*!< when this bit is 1, dscr can be processed after receiving a - task */ - __IOM uint32_t IN_DSCR_TASK_MAK_CH0 : 2; /*!< ETM dscr_ready maximum cache numbers */ - uint32_t : 28; - } bit; - } IN_ETM_CONF_CH0; - __IM uint32_t RESERVED24[4]; - - union { - __IOM uint32_t reg; /*!< rx CH0 fifo cnt register */ - - struct { - __IM uint32_t IN_CMDFIFO_INFIFO_CNT_CH0 : 10;/*!< only for debug */ - uint32_t : 22; - } bit; - } IN_FIFO_CNT_CH0; - - union { - __IOM uint32_t reg; /*!< rx CH0 pop data cnt register */ - - struct { - __IM uint32_t IN_CMDFIFO_POP_DATA_CNT_CH0 : 8;/*!< only for debug */ - uint32_t : 24; - } bit; - } IN_POP_DATA_CNT_CH0; - - union { - __IOM uint32_t reg; /*!< rx CH0 xaddr register */ - - struct { - __IM uint32_t IN_CMDFIFO_XADDR_CH0 : 32; /*!< only for debug */ - } bit; - } IN_XADDR_CH0; - - union { - __IOM uint32_t reg; /*!< rx CH0 buf len hb rcv register */ - - struct { - __IM uint32_t IN_CMDFIFO_BUF_HB_RCV_CH0 : 29;/*!< only for debug */ - uint32_t : 3; - } bit; - } IN_BUF_HB_RCV_CH0; - __IM uint32_t RESERVED25[28]; - - union { - __IOM uint32_t reg; /*!< RX CH1 config0 register */ - - struct { - uint32_t : 2; - __IOM uint32_t INDSCR_BURST_EN_CH1 : 1; /*!< Set this bit to 1 to enable INCR burst transfer for Rx transmitting - link descriptor when accessing SRAM. */ - __IOM uint32_t IN_ECC_AES_EN_CH1 : 1; /*!< When access address space is ecc/aes area, this bit should be - set to 1. In this case, the start address of square should - be 16-bit aligned. The width of square multiply byte number - of one pixel should be 16-bit aligned. */ - __IOM uint32_t IN_CHECK_OWNER_CH1 : 1; /*!< Set this bit to enable checking the owner attribute of the link - descriptor. */ - uint32_t : 1; - __IOM uint32_t IN_MEM_BURST_LENGTH_CH1 : 3;/*!< Block size of Rx channel 1. 0: single 1: 16 bytes 2: 32 bytes - 3: 64 bytes 4: 128 bytes */ - uint32_t : 3; - __IOM uint32_t IN_PAGE_BOUND_EN_CH1 : 1; /*!< Set this bit to 1 to make sure AXI write data don't cross the - address boundary which define by mem_burst_length */ - uint32_t : 11; - __IOM uint32_t IN_RST_CH1 : 1; /*!< Write 1 then write 0 to this bit to reset Rx channel */ - __IOM uint32_t IN_CMD_DISABLE_CH1 : 1; /*!< Write 1 before reset and write 0 after reset */ - __IOM uint32_t IN_ARB_WEIGHT_OPT_DIS_CH1 : 1;/*!< Set this bit to 1 to disable arbiter optimum weight function. */ - uint32_t : 5; - } bit; - } IN_CONF0_CH1; - - union { - __IOM uint32_t reg; /*!< RX CH1 interrupt raw register */ - - struct { - __IOM uint32_t IN_DONE_CH1_INT_RAW : 1; /*!< The raw interrupt bit turns to high level when the last data - pointed by one inlink descriptor has been transmitted to - peripherals for Rx channel 1. */ - __IOM uint32_t IN_SUC_EOF_CH1_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when the last data - pointed by one inlink descriptor has been received and - no data error is detected for Rx channel 1. */ - __IOM uint32_t IN_ERR_EOF_CH1_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when the last data - pointed by one inlink descriptor has been received and - data error is detected */ - __IOM uint32_t IN_DSCR_ERR_CH1_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when detecting inlink - descriptor error, including owner error, the second and - third word error of inlink descriptor for Rx channel 1. */ - __IOM uint32_t INFIFO_OVF_L1_CH1_INT_RAW : 1;/*!< This raw interrupt bit turns to high level when fifo of Rx channel - is overflow. */ - __IOM uint32_t INFIFO_UDF_L1_CH1_INT_RAW : 1;/*!< This raw interrupt bit turns to high level when fifo of Rx channel - is underflow. */ - __IOM uint32_t INFIFO_OVF_L2_CH1_INT_RAW : 1;/*!< This raw interrupt bit turns to high level when fifo of Rx channel - is overflow. */ - __IOM uint32_t INFIFO_UDF_L2_CH1_INT_RAW : 1;/*!< This raw interrupt bit turns to high level when fifo of Rx channel - is underflow. */ - __IOM uint32_t IN_DSCR_EMPTY_CH1_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when the last descriptor - is done but fifo also remain data. */ - __IOM uint32_t IN_DSCR_TASK_OVF_CH1_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when dscr ready task - fifo is overflow. */ - uint32_t : 22; - } bit; - } IN_INT_RAW_CH1; - - union { - __IOM uint32_t reg; /*!< RX CH1 interrupt ena register */ - - struct { - __IOM uint32_t IN_DONE_CH1_INT_ENA : 1; /*!< The interrupt enable bit for the IN_DONE_CH_INT interrupt. */ - __IOM uint32_t IN_SUC_EOF_CH1_INT_ENA : 1;/*!< The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. */ - __IOM uint32_t IN_ERR_EOF_CH1_INT_ENA : 1;/*!< The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. */ - __IOM uint32_t IN_DSCR_ERR_CH1_INT_ENA : 1;/*!< The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. */ - __IOM uint32_t INFIFO_OVF_L1_CH1_INT_ENA : 1;/*!< The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. */ - __IOM uint32_t INFIFO_UDF_L1_CH1_INT_ENA : 1;/*!< The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. */ - __IOM uint32_t INFIFO_OVF_L2_CH1_INT_ENA : 1;/*!< The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. */ - __IOM uint32_t INFIFO_UDF_L2_CH1_INT_ENA : 1;/*!< The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. */ - __IOM uint32_t IN_DSCR_EMPTY_CH1_INT_ENA : 1;/*!< The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. */ - __IOM uint32_t IN_DSCR_TASK_OVF_CH1_INT_ENA : 1;/*!< The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. */ - uint32_t : 22; - } bit; - } IN_INT_ENA_CH1; - - union { - __IOM uint32_t reg; /*!< RX CH1 interrupt st register */ - - struct { - __IM uint32_t IN_DONE_CH1_INT_ST : 1; /*!< The raw interrupt status bit for the IN_DONE_CH_INT interrupt. */ - __IM uint32_t IN_SUC_EOF_CH1_INT_ST : 1; /*!< The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. */ - __IM uint32_t IN_ERR_EOF_CH1_INT_ST : 1; /*!< The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. */ - __IM uint32_t IN_DSCR_ERR_CH1_INT_ST : 1;/*!< The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. */ - __IM uint32_t INFIFO_OVF_L1_CH1_INT_ST : 1;/*!< The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. */ - __IM uint32_t INFIFO_UDF_L1_CH1_INT_ST : 1;/*!< The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. */ - __IM uint32_t INFIFO_OVF_L2_CH1_INT_ST : 1;/*!< The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. */ - __IM uint32_t INFIFO_UDF_L2_CH1_INT_ST : 1;/*!< The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. */ - __IM uint32_t IN_DSCR_EMPTY_CH1_INT_ST : 1;/*!< The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. */ - __IM uint32_t IN_DSCR_TASK_OVF_CH1_INT_ST : 1;/*!< The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT - interrupt. */ - uint32_t : 22; - } bit; - } IN_INT_ST_CH1; - - union { - __IOM uint32_t reg; /*!< RX CH1 interrupt clr register */ - - struct { - __OM uint32_t IN_DONE_CH1_INT_CLR : 1; /*!< Set this bit to clear the IN_DONE_CH_INT interrupt. */ - __OM uint32_t IN_SUC_EOF_CH1_INT_CLR : 1;/*!< Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. */ - __OM uint32_t IN_ERR_EOF_CH1_INT_CLR : 1;/*!< Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. */ - __OM uint32_t IN_DSCR_ERR_CH1_INT_CLR : 1;/*!< Set this bit to clear the INDSCR_ERR_CH_INT interrupt. */ - __OM uint32_t INFIFO_OVF_L1_CH1_INT_CLR : 1;/*!< Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. */ - __OM uint32_t INFIFO_UDF_L1_CH1_INT_CLR : 1;/*!< Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. */ - __OM uint32_t INFIFO_OVF_L2_CH1_INT_CLR : 1;/*!< Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. */ - __OM uint32_t INFIFO_UDF_L2_CH1_INT_CLR : 1;/*!< Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. */ - __OM uint32_t IN_DSCR_EMPTY_CH1_INT_CLR : 1;/*!< Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. */ - __OM uint32_t IN_DSCR_TASK_OVF_CH1_INT_CLR : 1;/*!< Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. */ - uint32_t : 22; - } bit; - } IN_INT_CLR_CH1; - - union { - __IOM uint32_t reg; /*!< RX CH1 INFIFO status register */ - - struct { - __IM uint32_t INFIFO_FULL_L2_CH1 : 1; /*!< Rx FIFO full signal for Rx channel. */ - __IM uint32_t INFIFO_EMPTY_L2_CH1 : 1; /*!< Rx FIFO empty signal for Rx channel. */ - __IM uint32_t INFIFO_CNT_L2_CH1 : 4; /*!< The register stores the byte number of the data in Rx FIFO for - Rx channel. */ - __IM uint32_t INFIFO_FULL_L1_CH1 : 1; /*!< Tx FIFO full signal for Tx channel 1. */ - __IM uint32_t INFIFO_EMPTY_L1_CH1 : 1; /*!< Tx FIFO empty signal for Tx channel 1. */ - __IM uint32_t INFIFO_CNT_L1_CH1 : 5; /*!< The register stores the byte number of the data in Tx FIFO for - Tx channel 1. */ - uint32_t : 3; - __IM uint32_t INFIFO_FULL_L3_CH1 : 1; /*!< Tx FIFO full signal for Tx channel 1. */ - __IM uint32_t INFIFO_EMPTY_L3_CH1 : 1; /*!< Tx FIFO empty signal for Tx channel 1. */ - __IM uint32_t INFIFO_CNT_L3_CH1 : 2; /*!< The register stores the byte number of the data in Tx FIFO for - Tx channel 1. */ - uint32_t : 12; - } bit; - } INFIFO_STATUS_CH1; - - union { - __IOM uint32_t reg; /*!< RX CH1 INFIFO pop register */ - - struct { - __IM uint32_t INFIFO_RDATA_CH1 : 11; /*!< This register stores the data popping from DMA Rx FIFO. */ - __IOM uint32_t INFIFO_POP_CH1 : 1; /*!< Set this bit to pop data from DMA Rx FIFO. */ - uint32_t : 20; - } bit; - } IN_POP_CH1; - - union { - __IOM uint32_t reg; /*!< RX CH1 in_link dscr ctrl register */ - - struct { - uint32_t : 20; - __IOM uint32_t INLINK_AUTO_RET_CH1 : 1; /*!< Set this bit to return to current inlink descriptor's address, - when there are some errors in current receiving data. */ - __IOM uint32_t INLINK_STOP_CH1 : 1; /*!< Set this bit to stop dealing with the inlink descriptors. */ - __IOM uint32_t INLINK_START_CH1 : 1; /*!< Set this bit to start dealing with the inlink descriptors. */ - __IOM uint32_t INLINK_RESTART_CH1 : 1; /*!< Set this bit to mount a new inlink descriptor. */ - __IM uint32_t INLINK_PARK_CH1 : 1; /*!< 1: the inlink descriptor's FSM is in idle state. 0: the inlink - descriptor's FSM is working. */ - uint32_t : 7; - } bit; - } IN_LINK_CONF_CH1; - - union { - __IOM uint32_t reg; /*!< RX CH1 in_link dscr addr register */ - - struct { - __IOM uint32_t INLINK_ADDR_CH1 : 32; /*!< This register stores the first inlink descriptor's address. */ - } bit; - } IN_LINK_ADDR_CH1; - - union { - __IOM uint32_t reg; /*!< RX CH1 state register */ - - struct { - __IM uint32_t INLINK_DSCR_ADDR_CH1 : 18; /*!< This register stores the current inlink descriptor's address. */ - __IM uint32_t IN_DSCR_STATE_CH1 : 2; /*!< This register stores the current descriptor state machine state. */ - __IM uint32_t IN_STATE_CH1 : 3; /*!< This register stores the current control module state machine - state. */ - __IM uint32_t IN_RESET_AVAIL_CH1 : 1; /*!< This register indicate that if the channel reset is safety. */ - uint32_t : 8; - } bit; - } IN_STATE_CH1; - - union { - __IOM uint32_t reg; /*!< RX CH1 eof des addr register */ - - struct { - __IM uint32_t IN_SUC_EOF_DES_ADDR_CH1 : 32;/*!< This register stores the address of the inlink descriptor when - the EOF bit in this descriptor is 1. */ - } bit; - } IN_SUC_EOF_DES_ADDR_CH1; - - union { - __IOM uint32_t reg; /*!< RX CH1 err eof des addr register */ - - struct { - __IM uint32_t IN_ERR_EOF_DES_ADDR_CH1 : 32;/*!< This register stores the address of the inlink descriptor when - there are some errors in current receiving data. */ - } bit; - } IN_ERR_EOF_DES_ADDR_CH1; - - union { - __IOM uint32_t reg; /*!< RX CH1 next dscr addr register */ - - struct { - __IM uint32_t INLINK_DSCR_CH1 : 32; /*!< The address of the next inlink descriptor address x. */ - } bit; - } IN_DSCR_CH1; - - union { - __IOM uint32_t reg; /*!< RX CH1 last dscr addr register */ - - struct { - __IM uint32_t INLINK_DSCR_BF0_CH1 : 32; /*!< The address of the last inlink descriptor's next address x-1. */ - } bit; - } IN_DSCR_BF0_CH1; - - union { - __IOM uint32_t reg; /*!< RX CH1 second-to-last dscr addr register */ - - struct { - __IM uint32_t INLINK_DSCR_BF1_CH1 : 32; /*!< The address of the second-to-last inlink descriptor's next address - x-2. */ - } bit; - } IN_DSCR_BF1_CH1; - __IM uint32_t RESERVED26; - - union { - __IOM uint32_t reg; /*!< RX CH1 arb register */ - - struct { - __IOM uint32_t IN_ARB_TOKEN_NUM_CH1 : 4; /*!< Set the max number of token count of arbiter */ - __IOM uint32_t EXTER_IN_ARB_PRIORITY_CH1 : 2;/*!< Set the priority of channel */ - __IOM uint32_t INTER_IN_ARB_PRIORITY_CH1 : 3;/*!< Set the priority of channel */ - uint32_t : 23; - } bit; - } IN_ARB_CH1; - __IM uint32_t RESERVED27; - - union { - __IOM uint32_t reg; /*!< RX CH1 ETM config register */ - - struct { - __IOM uint32_t IN_ETM_EN_CH1 : 1; /*!< Set this bit to 1 to enable ETM task function */ - __IOM uint32_t IN_ETM_LOOP_EN_CH1 : 1; /*!< when this bit is 1, dscr can be processed after receiving a - task */ - __IOM uint32_t IN_DSCR_TASK_MAK_CH1 : 2; /*!< ETM dscr_ready maximum cache numbers */ - uint32_t : 28; - } bit; - } IN_ETM_CONF_CH1; - __IM uint32_t RESERVED28[13]; - - union { - __IOM uint32_t reg; /*!< rx CH1 fifo cnt register */ - - struct { - __IM uint32_t IN_CMDFIFO_INFIFO_CNT_CH1 : 10;/*!< only for debug */ - uint32_t : 22; - } bit; - } IN_FIFO_CNT_CH1; - - union { - __IOM uint32_t reg; /*!< rx CH1 pop data cnt register */ - - struct { - __IM uint32_t IN_CMDFIFO_POP_DATA_CNT_CH1 : 8;/*!< only for debug */ - uint32_t : 24; - } bit; - } IN_POP_DATA_CNT_CH1; - - union { - __IOM uint32_t reg; /*!< rx CH1 xaddr register */ - - struct { - __IM uint32_t IN_CMDFIFO_XADDR_CH1 : 32; /*!< only for debug */ - } bit; - } IN_XADDR_CH1; - - union { - __IOM uint32_t reg; /*!< rx CH1 buf len hb rcv register */ - - struct { - __IM uint32_t IN_CMDFIFO_BUF_HB_RCV_CH1 : 29;/*!< only for debug */ - uint32_t : 3; - } bit; - } IN_BUF_HB_RCV_CH1; - __IM uint32_t RESERVED29[28]; - - union { - __IOM uint32_t reg; /*!< RX CH2 config0 register */ - - struct { - uint32_t : 2; - __IOM uint32_t INDSCR_BURST_EN_CH2 : 1; /*!< Set this bit to 1 to enable INCR burst transfer for Rx transmitting - link descriptor when accessing SRAM. */ - __IOM uint32_t IN_ECC_AES_EN_CH2 : 1; /*!< When access address space is ecc/aes area, this bit should be - set to 1. In this case, the start address of square should - be 16-bit aligned. The width of square multiply byte number - of one pixel should be 16-bit aligned. */ - __IOM uint32_t IN_CHECK_OWNER_CH2 : 1; /*!< Set this bit to enable checking the owner attribute of the link - descriptor. */ - uint32_t : 1; - __IOM uint32_t IN_MEM_BURST_LENGTH_CH2 : 3;/*!< Block size of Rx channel 2. 0: single 1: 16 bytes 2: 32 bytes - 3: 64 bytes 4: 128 bytes */ - uint32_t : 3; - __IOM uint32_t IN_PAGE_BOUND_EN_CH2 : 1; /*!< Set this bit to 1 to make sure AXI write data don't cross the - address boundary which define by mem_burst_length */ - uint32_t : 11; - __IOM uint32_t IN_RST_CH2 : 1; /*!< Write 1 then write 0 to this bit to reset Rx channel */ - __IOM uint32_t IN_CMD_DISABLE_CH2 : 1; /*!< Write 1 before reset and write 0 after reset */ - __IOM uint32_t IN_ARB_WEIGHT_OPT_DIS_CH2 : 1;/*!< Set this bit to 1 to disable arbiter optimum weight function. */ - uint32_t : 5; - } bit; - } IN_CONF0_CH2; - - union { - __IOM uint32_t reg; /*!< RX CH2 interrupt raw register */ - - struct { - __IOM uint32_t IN_DONE_CH2_INT_RAW : 1; /*!< The raw interrupt bit turns to high level when the last data - pointed by one inlink descriptor has been transmitted to - peripherals for Rx channel 1. */ - __IOM uint32_t IN_SUC_EOF_CH2_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when the last data - pointed by one inlink descriptor has been received and - no data error is detected for Rx channel 1. */ - __IOM uint32_t IN_ERR_EOF_CH2_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when the last data - pointed by one inlink descriptor has been received and - data error is detected */ - __IOM uint32_t IN_DSCR_ERR_CH2_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when detecting inlink - descriptor error, including owner error, the second and - third word error of inlink descriptor for Rx channel 1. */ - __IOM uint32_t INFIFO_OVF_L1_CH2_INT_RAW : 1;/*!< This raw interrupt bit turns to high level when fifo of Rx channel - is overflow. */ - __IOM uint32_t INFIFO_UDF_L1_CH2_INT_RAW : 1;/*!< This raw interrupt bit turns to high level when fifo of Rx channel - is underflow. */ - __IOM uint32_t INFIFO_OVF_L2_CH2_INT_RAW : 1;/*!< This raw interrupt bit turns to high level when fifo of Rx channel - is overflow. */ - __IOM uint32_t INFIFO_UDF_L2_CH2_INT_RAW : 1;/*!< This raw interrupt bit turns to high level when fifo of Rx channel - is underflow. */ - __IOM uint32_t IN_DSCR_EMPTY_CH2_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when the last descriptor - is done but fifo also remain data. */ - __IOM uint32_t IN_DSCR_TASK_OVF_CH2_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when dscr ready task - fifo is overflow. */ - uint32_t : 22; - } bit; - } IN_INT_RAW_CH2; - - union { - __IOM uint32_t reg; /*!< RX CH2 interrupt ena register */ - - struct { - __IOM uint32_t IN_DONE_CH2_INT_ENA : 1; /*!< The interrupt enable bit for the IN_DONE_CH_INT interrupt. */ - __IOM uint32_t IN_SUC_EOF_CH2_INT_ENA : 1;/*!< The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. */ - __IOM uint32_t IN_ERR_EOF_CH2_INT_ENA : 1;/*!< The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. */ - __IOM uint32_t IN_DSCR_ERR_CH2_INT_ENA : 1;/*!< The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. */ - __IOM uint32_t INFIFO_OVF_L1_CH2_INT_ENA : 1;/*!< The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. */ - __IOM uint32_t INFIFO_UDF_L1_CH2_INT_ENA : 1;/*!< The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. */ - __IOM uint32_t INFIFO_OVF_L2_CH2_INT_ENA : 1;/*!< The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. */ - __IOM uint32_t INFIFO_UDF_L2_CH2_INT_ENA : 1;/*!< The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. */ - __IOM uint32_t IN_DSCR_EMPTY_CH2_INT_ENA : 1;/*!< The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. */ - __IOM uint32_t IN_DSCR_TASK_OVF_CH2_INT_ENA : 1;/*!< The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. */ - uint32_t : 22; - } bit; - } IN_INT_ENA_CH2; - - union { - __IOM uint32_t reg; /*!< RX CH2 interrupt st register */ - - struct { - __IM uint32_t IN_DONE_CH2_INT_ST : 1; /*!< The raw interrupt status bit for the IN_DONE_CH_INT interrupt. */ - __IM uint32_t IN_SUC_EOF_CH2_INT_ST : 1; /*!< The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. */ - __IM uint32_t IN_ERR_EOF_CH2_INT_ST : 1; /*!< The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. */ - __IM uint32_t IN_DSCR_ERR_CH2_INT_ST : 1;/*!< The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. */ - __IM uint32_t INFIFO_OVF_L1_CH2_INT_ST : 1;/*!< The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. */ - __IM uint32_t INFIFO_UDF_L1_CH2_INT_ST : 1;/*!< The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. */ - __IM uint32_t INFIFO_OVF_L2_CH2_INT_ST : 1;/*!< The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. */ - __IM uint32_t INFIFO_UDF_L2_CH2_INT_ST : 1;/*!< The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. */ - __IM uint32_t IN_DSCR_EMPTY_CH2_INT_ST : 1;/*!< The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. */ - __IM uint32_t IN_DSCR_TASK_OVF_CH2_INT_ST : 1;/*!< The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT - interrupt. */ - uint32_t : 22; - } bit; - } IN_INT_ST_CH2; - - union { - __IOM uint32_t reg; /*!< RX CH2 interrupt clr register */ - - struct { - __OM uint32_t IN_DONE_CH2_INT_CLR : 1; /*!< Set this bit to clear the IN_DONE_CH_INT interrupt. */ - __OM uint32_t IN_SUC_EOF_CH2_INT_CLR : 1;/*!< Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. */ - __OM uint32_t IN_ERR_EOF_CH2_INT_CLR : 1;/*!< Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. */ - __OM uint32_t IN_DSCR_ERR_CH2_INT_CLR : 1;/*!< Set this bit to clear the INDSCR_ERR_CH_INT interrupt. */ - __OM uint32_t INFIFO_OVF_L1_CH2_INT_CLR : 1;/*!< Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. */ - __OM uint32_t INFIFO_UDF_L1_CH2_INT_CLR : 1;/*!< Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. */ - __OM uint32_t INFIFO_OVF_L2_CH2_INT_CLR : 1;/*!< Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. */ - __OM uint32_t INFIFO_UDF_L2_CH2_INT_CLR : 1;/*!< Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. */ - __OM uint32_t IN_DSCR_EMPTY_CH2_INT_CLR : 1;/*!< Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. */ - __OM uint32_t IN_DSCR_TASK_OVF_CH2_INT_CLR : 1;/*!< Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. */ - uint32_t : 22; - } bit; - } IN_INT_CLR_CH2; - - union { - __IOM uint32_t reg; /*!< RX CH2 INFIFO status register */ - - struct { - __IM uint32_t INFIFO_FULL_L2_CH2 : 1; /*!< Rx FIFO full signal for Rx channel. */ - __IM uint32_t INFIFO_EMPTY_L2_CH2 : 1; /*!< Rx FIFO empty signal for Rx channel. */ - __IM uint32_t INFIFO_CNT_L2_CH2 : 4; /*!< The register stores the byte number of the data in Rx FIFO for - Rx channel. */ - __IM uint32_t INFIFO_FULL_L1_CH2 : 1; /*!< Tx FIFO full signal for Tx channel 1. */ - __IM uint32_t INFIFO_EMPTY_L1_CH2 : 1; /*!< Tx FIFO empty signal for Tx channel 1. */ - __IM uint32_t INFIFO_CNT_L1_CH2 : 5; /*!< The register stores the byte number of the data in Tx FIFO for - Tx channel 1. */ - uint32_t : 3; - __IM uint32_t INFIFO_FULL_L3_CH2 : 1; /*!< Tx FIFO full signal for Tx channel 1. */ - __IM uint32_t INFIFO_EMPTY_L3_CH2 : 1; /*!< Tx FIFO empty signal for Tx channel 1. */ - __IM uint32_t INFIFO_CNT_L3_CH2 : 2; /*!< The register stores the byte number of the data in Tx FIFO for - Tx channel 1. */ - uint32_t : 12; - } bit; - } INFIFO_STATUS_CH2; - - union { - __IOM uint32_t reg; /*!< RX CH2 INFIFO pop register */ - - struct { - __IM uint32_t INFIFO_RDATA_CH2 : 11; /*!< This register stores the data popping from DMA Rx FIFO. */ - __IOM uint32_t INFIFO_POP_CH2 : 1; /*!< Set this bit to pop data from DMA Rx FIFO. */ - uint32_t : 20; - } bit; - } IN_POP_CH2; - - union { - __IOM uint32_t reg; /*!< RX CH2 in_link dscr ctrl register */ - - struct { - uint32_t : 20; - __IOM uint32_t INLINK_AUTO_RET_CH2 : 1; /*!< Set this bit to return to current inlink descriptor's address, - when there are some errors in current receiving data. */ - __IOM uint32_t INLINK_STOP_CH2 : 1; /*!< Set this bit to stop dealing with the inlink descriptors. */ - __IOM uint32_t INLINK_START_CH2 : 1; /*!< Set this bit to start dealing with the inlink descriptors. */ - __IOM uint32_t INLINK_RESTART_CH2 : 1; /*!< Set this bit to mount a new inlink descriptor. */ - __IM uint32_t INLINK_PARK_CH2 : 1; /*!< 1: the inlink descriptor's FSM is in idle state. 0: the inlink - descriptor's FSM is working. */ - uint32_t : 7; - } bit; - } IN_LINK_CONF_CH2; - - union { - __IOM uint32_t reg; /*!< RX CH2 in_link dscr addr register */ - - struct { - __IOM uint32_t INLINK_ADDR_CH2 : 32; /*!< This register stores the first inlink descriptor's address. */ - } bit; - } IN_LINK_ADDR_CH2; - - union { - __IOM uint32_t reg; /*!< RX CH2 state register */ - - struct { - __IM uint32_t INLINK_DSCR_ADDR_CH2 : 18; /*!< This register stores the current inlink descriptor's address. */ - __IM uint32_t IN_DSCR_STATE_CH2 : 2; /*!< This register stores the current descriptor state machine state. */ - __IM uint32_t IN_STATE_CH2 : 3; /*!< This register stores the current control module state machine - state. */ - __IM uint32_t IN_RESET_AVAIL_CH2 : 1; /*!< This register indicate that if the channel reset is safety. */ - uint32_t : 8; - } bit; - } IN_STATE_CH2; - - union { - __IOM uint32_t reg; /*!< RX CH2 eof des addr register */ - - struct { - __IM uint32_t IN_SUC_EOF_DES_ADDR_CH2 : 32;/*!< This register stores the address of the inlink descriptor when - the EOF bit in this descriptor is 1. */ - } bit; - } IN_SUC_EOF_DES_ADDR_CH2; - - union { - __IOM uint32_t reg; /*!< RX CH2 err eof des addr register */ - - struct { - __IM uint32_t IN_ERR_EOF_DES_ADDR_CH2 : 32;/*!< This register stores the address of the inlink descriptor when - there are some errors in current receiving data. */ - } bit; - } IN_ERR_EOF_DES_ADDR_CH2; - - union { - __IOM uint32_t reg; /*!< RX CH2 next dscr addr register */ - - struct { - __IM uint32_t INLINK_DSCR_CH2 : 32; /*!< The address of the next inlink descriptor address x. */ - } bit; - } IN_DSCR_CH2; - - union { - __IOM uint32_t reg; /*!< RX CH2 last dscr addr register */ - - struct { - __IM uint32_t INLINK_DSCR_BF0_CH2 : 32; /*!< The address of the last inlink descriptor's next address x-1. */ - } bit; - } IN_DSCR_BF0_CH2; - - union { - __IOM uint32_t reg; /*!< RX CH2 second-to-last dscr addr register */ - - struct { - __IM uint32_t INLINK_DSCR_BF1_CH2 : 32; /*!< The address of the second-to-last inlink descriptor's next address - x-2. */ - } bit; - } IN_DSCR_BF1_CH2; - __IM uint32_t RESERVED30; - - union { - __IOM uint32_t reg; /*!< RX CH2 arb register */ - - struct { - __IOM uint32_t IN_ARB_TOKEN_NUM_CH2 : 4; /*!< Set the max number of token count of arbiter */ - uint32_t : 2; - __IOM uint32_t INTER_IN_ARB_PRIORITY_CH2 : 3;/*!< Set the priority of channel */ - uint32_t : 23; - } bit; - } IN_ARB_CH2; - __IM uint32_t RESERVED31; - - union { - __IOM uint32_t reg; /*!< RX CH2 ETM config register */ - - struct { - __IOM uint32_t IN_ETM_EN_CH2 : 1; /*!< Set this bit to 1 to enable ETM task function */ - __IOM uint32_t IN_ETM_LOOP_EN_CH2 : 1; /*!< when this bit is 1, dscr can be processed after receiving a - task */ - __IOM uint32_t IN_DSCR_TASK_MAK_CH2 : 2; /*!< ETM dscr_ready maximum cache numbers */ - uint32_t : 28; - } bit; - } IN_ETM_CONF_CH2; - __IM uint32_t RESERVED32[13]; - - union { - __IOM uint32_t reg; /*!< rx CH2 fifo cnt register */ - - struct { - __IM uint32_t IN_CMDFIFO_INFIFO_CNT_CH2 : 10;/*!< only for debug */ - uint32_t : 22; - } bit; - } IN_FIFO_CNT_CH2; - - union { - __IOM uint32_t reg; /*!< rx CH2 pop data cnt register */ - - struct { - __IM uint32_t IN_CMDFIFO_POP_DATA_CNT_CH2 : 8;/*!< only for debug */ - uint32_t : 24; - } bit; - } IN_POP_DATA_CNT_CH2; - - union { - __IOM uint32_t reg; /*!< rx CH2 xaddr register */ - - struct { - __IM uint32_t IN_CMDFIFO_XADDR_CH2 : 32; /*!< only for debug */ - } bit; - } IN_XADDR_CH2; - - union { - __IOM uint32_t reg; /*!< rx CH2 buf len hb rcv register */ - - struct { - __IM uint32_t IN_CMDFIFO_BUF_HB_RCV_CH2 : 29;/*!< only for debug */ - uint32_t : 3; - } bit; - } IN_BUF_HB_RCV_CH2; - __IM uint32_t RESERVED33[28]; - - union { - __IOM uint32_t reg; /*!< RX CH3 config0 register */ - - struct { - uint32_t : 2; - __IOM uint32_t INDSCR_BURST_EN_CH3 : 1; /*!< Set this bit to 1 to enable INCR burst transfer for Rx transmitting - link descriptor when accessing SRAM. */ - __IOM uint32_t IN_ECC_AES_EN_CH3 : 1; /*!< When access address space is ecc/aes area, this bit should be - set to 1. In this case, the start address of square should - be 16-bit aligned. The width of square multiply byte number - of one pixel should be 16-bit aligned. */ - __IOM uint32_t IN_CHECK_OWNER_CH3 : 1; /*!< Set this bit to enable checking the owner attribute of the link - descriptor. */ - uint32_t : 1; - __IOM uint32_t IN_MEM_BURST_LENGTH_CH3 : 3;/*!< Block size of Rx channel 1. 0: single 1: 16 bytes 2: 32 bytes - 3: 64 bytes 4: 128 bytes */ - uint32_t : 3; - __IOM uint32_t IN_PAGE_BOUND_EN_CH3 : 1; /*!< Set this bit to 1 to make sure AXI write data don't cross the - address boundary which define by mem_burst_length */ - uint32_t : 11; - __IOM uint32_t IN_RST_CH3 : 1; /*!< Write 1 then write 0 to this bit to reset Rx channel */ - __IOM uint32_t IN_CMD_DISABLE_CH3 : 1; /*!< Write 1 before reset and write 0 after reset */ - __IOM uint32_t IN_ARB_WEIGHT_OPT_DIS_CH3 : 1;/*!< Set this bit to 1 to disable arbiter optimum weight function. */ - uint32_t : 5; - } bit; - } IN_CONF0_CH3; - - union { - __IOM uint32_t reg; /*!< RX CH3 interrupt raw register */ - - struct { - __IOM uint32_t IN_DONE_CH3_INT_RAW : 1; /*!< The raw interrupt bit turns to high level when the last data - pointed by one inlink descriptor has been transmitted to - peripherals for Rx channel 1. */ - __IOM uint32_t IN_SUC_EOF_CH3_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when the last data - pointed by one inlink descriptor has been received and - no data error is detected for Rx channel 1. */ - __IOM uint32_t IN_ERR_EOF_CH3_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when the last data - pointed by one inlink descriptor has been received and - data error is detected */ - __IOM uint32_t IN_DSCR_ERR_CH3_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when detecting inlink - descriptor error, including owner error, the second and - third word error of inlink descriptor for Rx channel 1. */ - __IOM uint32_t INFIFO_OVF_L1_CH3_INT_RAW : 1;/*!< This raw interrupt bit turns to high level when fifo of Rx channel - is overflow. */ - __IOM uint32_t INFIFO_UDF_L1_CH3_INT_RAW : 1;/*!< This raw interrupt bit turns to high level when fifo of Rx channel - is underflow. */ - __IOM uint32_t INFIFO_OVF_L2_CH3_INT_RAW : 1;/*!< This raw interrupt bit turns to high level when fifo of Rx channel - is overflow. */ - __IOM uint32_t INFIFO_UDF_L2_CH3_INT_RAW : 1;/*!< This raw interrupt bit turns to high level when fifo of Rx channel - is underflow. */ - __IOM uint32_t IN_DSCR_EMPTY_CH3_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when the last descriptor - is done but fifo also remain data. */ - __IOM uint32_t IN_DSCR_TASK_OVF_CH3_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when dscr ready task - fifo is overflow. */ - uint32_t : 22; - } bit; - } IN_INT_RAW_CH3; - - union { - __IOM uint32_t reg; /*!< RX CH3 interrupt ena register */ - - struct { - __IOM uint32_t IN_DONE_CH3_INT_ENA : 1; /*!< The interrupt enable bit for the IN_DONE_CH_INT interrupt. */ - __IOM uint32_t IN_SUC_EOF_CH3_INT_ENA : 1;/*!< The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. */ - __IOM uint32_t IN_ERR_EOF_CH3_INT_ENA : 1;/*!< The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. */ - __IOM uint32_t IN_DSCR_ERR_CH3_INT_ENA : 1;/*!< The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. */ - __IOM uint32_t INFIFO_OVF_L1_CH3_INT_ENA : 1;/*!< The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. */ - __IOM uint32_t INFIFO_UDF_L1_CH3_INT_ENA : 1;/*!< The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. */ - __IOM uint32_t INFIFO_OVF_L2_CH3_INT_ENA : 1;/*!< The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. */ - __IOM uint32_t INFIFO_UDF_L2_CH3_INT_ENA : 1;/*!< The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. */ - __IOM uint32_t IN_DSCR_EMPTY_CH3_INT_ENA : 1;/*!< The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. */ - __IOM uint32_t IN_DSCR_TASK_OVF_CH3_INT_ENA : 1;/*!< The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. */ - uint32_t : 22; - } bit; - } IN_INT_ENA_CH3; - - union { - __IOM uint32_t reg; /*!< RX CH3 interrupt st register */ - - struct { - __IM uint32_t IN_DONE_CH3_INT_ST : 1; /*!< The raw interrupt status bit for the IN_DONE_CH_INT interrupt. */ - __IM uint32_t IN_SUC_EOF_CH3_INT_ST : 1; /*!< The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. */ - __IM uint32_t IN_ERR_EOF_CH3_INT_ST : 1; /*!< The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. */ - __IM uint32_t IN_DSCR_ERR_CH3_INT_ST : 1;/*!< The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. */ - __IM uint32_t INFIFO_OVF_L1_CH3_INT_ST : 1;/*!< The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. */ - __IM uint32_t INFIFO_UDF_L1_CH3_INT_ST : 1;/*!< The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. */ - __IM uint32_t INFIFO_OVF_L2_CH3_INT_ST : 1;/*!< The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. */ - __IM uint32_t INFIFO_UDF_L2_CH3_INT_ST : 1;/*!< The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. */ - __IM uint32_t IN_DSCR_EMPTY_CH3_INT_ST : 1;/*!< The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. */ - __IM uint32_t IN_DSCR_TASK_OVF_CH3_INT_ST : 1;/*!< The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT - interrupt. */ - uint32_t : 22; - } bit; - } IN_INT_ST_CH3; - - union { - __IOM uint32_t reg; /*!< RX CH3 interrupt clr register */ - - struct { - __OM uint32_t IN_DONE_CH3_INT_CLR : 1; /*!< Set this bit to clear the IN_DONE_CH_INT interrupt. */ - __OM uint32_t IN_SUC_EOF_CH3_INT_CLR : 1;/*!< Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. */ - __OM uint32_t IN_ERR_EOF_CH3_INT_CLR : 1;/*!< Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. */ - __OM uint32_t IN_DSCR_ERR_CH3_INT_CLR : 1;/*!< Set this bit to clear the INDSCR_ERR_CH_INT interrupt. */ - __OM uint32_t INFIFO_OVF_L1_CH3_INT_CLR : 1;/*!< Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. */ - __OM uint32_t INFIFO_UDF_L1_CH3_INT_CLR : 1;/*!< Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. */ - __OM uint32_t INFIFO_OVF_L2_CH3_INT_CLR : 1;/*!< Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. */ - __OM uint32_t INFIFO_UDF_L2_CH3_INT_CLR : 1;/*!< Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. */ - __OM uint32_t IN_DSCR_EMPTY_CH3_INT_CLR : 1;/*!< Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. */ - __OM uint32_t IN_DSCR_TASK_OVF_CH3_INT_CLR : 1;/*!< Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. */ - uint32_t : 22; - } bit; - } IN_INT_CLR_CH3; - - union { - __IOM uint32_t reg; /*!< RX CH3 INFIFO status register */ - - struct { - __IM uint32_t INFIFO_FULL_L2_CH3 : 1; /*!< Rx FIFO full signal for Rx channel. */ - __IM uint32_t INFIFO_EMPTY_L2_CH3 : 1; /*!< Rx FIFO empty signal for Rx channel. */ - __IM uint32_t INFIFO_CNT_L2_CH3 : 4; /*!< The register stores the byte number of the data in Rx FIFO for - Rx channel. */ - __IM uint32_t INFIFO_FULL_L1_CH3 : 1; /*!< Tx FIFO full signal for Tx channel 1. */ - __IM uint32_t INFIFO_EMPTY_L1_CH3 : 1; /*!< Tx FIFO empty signal for Tx channel 1. */ - __IM uint32_t INFIFO_CNT_L1_CH3 : 5; /*!< The register stores the byte number of the data in Tx FIFO for - Tx channel 1. */ - uint32_t : 3; - __IM uint32_t INFIFO_FULL_L3_CH3 : 1; /*!< Tx FIFO full signal for Tx channel 1. */ - __IM uint32_t INFIFO_EMPTY_L3_CH3 : 1; /*!< Tx FIFO empty signal for Tx channel 1. */ - __IM uint32_t INFIFO_CNT_L3_CH3 : 2; /*!< The register stores the byte number of the data in Tx FIFO for - Tx channel 1. */ - uint32_t : 12; - } bit; - } INFIFO_STATUS_CH3; - - union { - __IOM uint32_t reg; /*!< RX CH3 INFIFO pop register */ - - struct { - __IM uint32_t INFIFO_RDATA_CH3 : 11; /*!< This register stores the data popping from DMA Rx FIFO. */ - __IOM uint32_t INFIFO_POP_CH3 : 1; /*!< Set this bit to pop data from DMA Rx FIFO. */ - uint32_t : 20; - } bit; - } IN_POP_CH3; - - union { - __IOM uint32_t reg; /*!< RX CH3 in_link dscr ctrl register */ - - struct { - uint32_t : 20; - __IOM uint32_t INLINK_AUTO_RET_CH3 : 1; /*!< Set this bit to return to current inlink descriptor's address, - when there are some errors in current receiving data. */ - __IOM uint32_t INLINK_STOP_CH3 : 1; /*!< Set this bit to stop dealing with the inlink descriptors. */ - __IOM uint32_t INLINK_START_CH3 : 1; /*!< Set this bit to start dealing with the inlink descriptors. */ - __IOM uint32_t INLINK_RESTART_CH3 : 1; /*!< Set this bit to mount a new inlink descriptor. */ - __IM uint32_t INLINK_PARK_CH3 : 1; /*!< 1: the inlink descriptor's FSM is in idle state. 0: the inlink - descriptor's FSM is working. */ - uint32_t : 7; - } bit; - } IN_LINK_CONF_CH3; - - union { - __IOM uint32_t reg; /*!< RX CH3 in_link dscr addr register */ - - struct { - __IOM uint32_t INLINK_ADDR_CH3 : 32; /*!< This register stores the first inlink descriptor's address. */ - } bit; - } IN_LINK_ADDR_CH3; - - union { - __IOM uint32_t reg; /*!< RX CH3 state register */ - - struct { - __IM uint32_t INLINK_DSCR_ADDR_CH3 : 18; /*!< This register stores the current inlink descriptor's address. */ - __IM uint32_t IN_DSCR_STATE_CH3 : 2; /*!< This register stores the current descriptor state machine state. */ - __IM uint32_t IN_STATE_CH3 : 3; /*!< This register stores the current control module state machine - state. */ - __IM uint32_t IN_RESET_AVAIL_CH3 : 1; /*!< This register indicate that if the channel reset is safety. */ - uint32_t : 8; - } bit; - } IN_STATE_CH3; - - union { - __IOM uint32_t reg; /*!< RX CH3 eof des addr register */ - - struct { - __IM uint32_t IN_SUC_EOF_DES_ADDR_CH3 : 32;/*!< This register stores the address of the inlink descriptor when - the EOF bit in this descriptor is 1. */ - } bit; - } IN_SUC_EOF_DES_ADDR_CH3; - - union { - __IOM uint32_t reg; /*!< RX CH3 err eof des addr register */ - - struct { - __IM uint32_t IN_ERR_EOF_DES_ADDR_CH3 : 32;/*!< This register stores the address of the inlink descriptor when - there are some errors in current receiving data. */ - } bit; - } IN_ERR_EOF_DES_ADDR_CH3; - - union { - __IOM uint32_t reg; /*!< RX CH3 next dscr addr register */ - - struct { - __IM uint32_t INLINK_DSCR_CH3 : 32; /*!< The address of the next inlink descriptor address x. */ - } bit; - } IN_DSCR_CH3; - - union { - __IOM uint32_t reg; /*!< RX CH3 last dscr addr register */ - - struct { - __IM uint32_t INLINK_DSCR_BF0_CH3 : 32; /*!< The address of the last inlink descriptor's next address x-1. */ - } bit; - } IN_DSCR_BF0_CH3; - - union { - __IOM uint32_t reg; /*!< RX CH3 second-to-last dscr addr register */ - - struct { - __IM uint32_t INLINK_DSCR_BF1_CH3 : 32; /*!< The address of the second-to-last inlink descriptor's next address - x-2. */ - } bit; - } IN_DSCR_BF1_CH3; - __IM uint32_t RESERVED34; - - union { - __IOM uint32_t reg; /*!< RX CH3 arb register */ - - struct { - __IOM uint32_t IN_ARB_TOKEN_NUM_CH3 : 4; /*!< Set the max number of token count of arbiter */ - uint32_t : 2; - __IOM uint32_t INTER_IN_ARB_PRIORITY_CH3 : 3;/*!< Set the priority of channel */ - uint32_t : 23; - } bit; - } IN_ARB_CH3; - __IM uint32_t RESERVED35; - - union { - __IOM uint32_t reg; /*!< RX CH3 ETM config register */ - - struct { - __IOM uint32_t IN_ETM_EN_CH3 : 1; /*!< Set this bit to 1 to enable ETM task function */ - __IOM uint32_t IN_ETM_LOOP_EN_CH3 : 1; /*!< when this bit is 1, dscr can be processed after receiving a - task */ - __IOM uint32_t IN_DSCR_TASK_MAK_CH3 : 2; /*!< ETM dscr_ready maximum cache numbers */ - uint32_t : 28; - } bit; - } IN_ETM_CONF_CH3; - __IM uint32_t RESERVED36[13]; - - union { - __IOM uint32_t reg; /*!< rx CH3 fifo cnt register */ - - struct { - __IM uint32_t IN_CMDFIFO_INFIFO_CNT_CH3 : 10;/*!< only for debug */ - uint32_t : 22; - } bit; - } IN_FIFO_CNT_CH3; - - union { - __IOM uint32_t reg; /*!< rx CH3 pop data cnt register */ - - struct { - __IM uint32_t IN_CMDFIFO_POP_DATA_CNT_CH3 : 8;/*!< only for debug */ - uint32_t : 24; - } bit; - } IN_POP_DATA_CNT_CH3; - - union { - __IOM uint32_t reg; /*!< rx CH3 xaddr register */ - - struct { - __IM uint32_t IN_CMDFIFO_XADDR_CH3 : 32; /*!< only for debug */ - } bit; - } IN_XADDR_CH3; - - union { - __IOM uint32_t reg; /*!< rx CH3 buf len hb rcv register */ - - struct { - __IM uint32_t IN_CMDFIFO_BUF_HB_RCV_CH3 : 29;/*!< only for debug */ - uint32_t : 3; - } bit; - } IN_BUF_HB_RCV_CH3; - __IM uint32_t RESERVED37[28]; - - union { - __IOM uint32_t reg; /*!< RX CH4 config0 register */ - - struct { - uint32_t : 2; - __IOM uint32_t INDSCR_BURST_EN_CH4 : 1; /*!< Set this bit to 1 to enable INCR burst transfer for Rx transmitting - link descriptor when accessing SRAM. */ - __IOM uint32_t IN_ECC_AES_EN_CH4 : 1; /*!< When access address space is ecc/aes area, this bit should be - set to 1. In this case, the start address of square should - be 16-bit aligned. The width of square multiply byte number - of one pixel should be 16-bit aligned. */ - __IOM uint32_t IN_CHECK_OWNER_CH4 : 1; /*!< Set this bit to enable checking the owner attribute of the link - descriptor. */ - uint32_t : 1; - __IOM uint32_t IN_MEM_BURST_LENGTH_CH4 : 3;/*!< Block size of Rx channel 1. 0: single 1: 16 bytes 2: 32 bytes - 3: 64 bytes 4: 128 bytes */ - uint32_t : 3; - __IOM uint32_t IN_PAGE_BOUND_EN_CH4 : 1; /*!< Set this bit to 1 to make sure AXI write data don't cross the - address boundary which define by mem_burst_length */ - uint32_t : 11; - __IOM uint32_t IN_RST_CH4 : 1; /*!< Write 1 then write 0 to this bit to reset Rx channel */ - __IOM uint32_t IN_CMD_DISABLE_CH4 : 1; /*!< Write 1 before reset and write 0 after reset */ - __IOM uint32_t IN_ARB_WEIGHT_OPT_DIS_CH4 : 1;/*!< Set this bit to 1 to disable arbiter optimum weight function. */ - uint32_t : 5; - } bit; - } IN_CONF0_CH4; - - union { - __IOM uint32_t reg; /*!< RX CH4 interrupt raw register */ - - struct { - __IOM uint32_t IN_DONE_CH4_INT_RAW : 1; /*!< The raw interrupt bit turns to high level when the last data - pointed by one inlink descriptor has been transmitted to - peripherals for Rx channel 1. */ - __IOM uint32_t IN_SUC_EOF_CH4_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when the last data - pointed by one inlink descriptor has been received and - no data error is detected for Rx channel 1. */ - __IOM uint32_t IN_ERR_EOF_CH4_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when the last data - pointed by one inlink descriptor has been received and - data error is detected */ - __IOM uint32_t IN_DSCR_ERR_CH4_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when detecting inlink - descriptor error, including owner error, the second and - third word error of inlink descriptor for Rx channel 1. */ - __IOM uint32_t INFIFO_OVF_L1_CH4_INT_RAW : 1;/*!< This raw interrupt bit turns to high level when fifo of Rx channel - is overflow. */ - __IOM uint32_t INFIFO_UDF_L1_CH4_INT_RAW : 1;/*!< This raw interrupt bit turns to high level when fifo of Rx channel - is underflow. */ - __IOM uint32_t INFIFO_OVF_L2_CH4_INT_RAW : 1;/*!< This raw interrupt bit turns to high level when fifo of Rx channel - is overflow. */ - __IOM uint32_t INFIFO_UDF_L2_CH4_INT_RAW : 1;/*!< This raw interrupt bit turns to high level when fifo of Rx channel - is underflow. */ - __IOM uint32_t IN_DSCR_EMPTY_CH4_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when the last descriptor - is done but fifo also remain data. */ - __IOM uint32_t IN_DSCR_TASK_OVF_CH4_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when dscr ready task - fifo is overflow. */ - uint32_t : 22; - } bit; - } IN_INT_RAW_CH4; - - union { - __IOM uint32_t reg; /*!< RX CH4 interrupt ena register */ - - struct { - __IOM uint32_t IN_DONE_CH4_INT_ENA : 1; /*!< The interrupt enable bit for the IN_DONE_CH_INT interrupt. */ - __IOM uint32_t IN_SUC_EOF_CH4_INT_ENA : 1;/*!< The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. */ - __IOM uint32_t IN_ERR_EOF_CH4_INT_ENA : 1;/*!< The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. */ - __IOM uint32_t IN_DSCR_ERR_CH4_INT_ENA : 1;/*!< The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. */ - __IOM uint32_t INFIFO_OVF_L1_CH4_INT_ENA : 1;/*!< The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. */ - __IOM uint32_t INFIFO_UDF_L1_CH4_INT_ENA : 1;/*!< The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. */ - __IOM uint32_t INFIFO_OVF_L2_CH4_INT_ENA : 1;/*!< The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. */ - __IOM uint32_t INFIFO_UDF_L2_CH4_INT_ENA : 1;/*!< The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. */ - __IOM uint32_t IN_DSCR_EMPTY_CH4_INT_ENA : 1;/*!< The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. */ - __IOM uint32_t IN_DSCR_TASK_OVF_CH4_INT_ENA : 1;/*!< The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. */ - uint32_t : 22; - } bit; - } IN_INT_ENA_CH4; - - union { - __IOM uint32_t reg; /*!< RX CH4 interrupt st register */ - - struct { - __IM uint32_t IN_DONE_CH4_INT_ST : 1; /*!< The raw interrupt status bit for the IN_DONE_CH_INT interrupt. */ - __IM uint32_t IN_SUC_EOF_CH4_INT_ST : 1; /*!< The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. */ - __IM uint32_t IN_ERR_EOF_CH4_INT_ST : 1; /*!< The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. */ - __IM uint32_t IN_DSCR_ERR_CH4_INT_ST : 1;/*!< The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. */ - __IM uint32_t INFIFO_OVF_L1_CH4_INT_ST : 1;/*!< The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. */ - __IM uint32_t INFIFO_UDF_L1_CH4_INT_ST : 1;/*!< The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. */ - __IM uint32_t INFIFO_OVF_L2_CH4_INT_ST : 1;/*!< The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. */ - __IM uint32_t INFIFO_UDF_L2_CH4_INT_ST : 1;/*!< The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. */ - __IM uint32_t IN_DSCR_EMPTY_CH4_INT_ST : 1;/*!< The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. */ - __IM uint32_t IN_DSCR_TASK_OVF_CH4_INT_ST : 1;/*!< The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT - interrupt. */ - uint32_t : 22; - } bit; - } IN_INT_ST_CH4; - - union { - __IOM uint32_t reg; /*!< RX CH4 interrupt clr register */ - - struct { - __OM uint32_t IN_DONE_CH4_INT_CLR : 1; /*!< Set this bit to clear the IN_DONE_CH_INT interrupt. */ - __OM uint32_t IN_SUC_EOF_CH4_INT_CLR : 1;/*!< Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. */ - __OM uint32_t IN_ERR_EOF_CH4_INT_CLR : 1;/*!< Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. */ - __OM uint32_t IN_DSCR_ERR_CH4_INT_CLR : 1;/*!< Set this bit to clear the INDSCR_ERR_CH_INT interrupt. */ - __OM uint32_t INFIFO_OVF_L1_CH4_INT_CLR : 1;/*!< Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. */ - __OM uint32_t INFIFO_UDF_L1_CH4_INT_CLR : 1;/*!< Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. */ - __OM uint32_t INFIFO_OVF_L2_CH4_INT_CLR : 1;/*!< Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. */ - __OM uint32_t INFIFO_UDF_L2_CH4_INT_CLR : 1;/*!< Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. */ - __OM uint32_t IN_DSCR_EMPTY_CH4_INT_CLR : 1;/*!< Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. */ - __OM uint32_t IN_DSCR_TASK_OVF_CH4_INT_CLR : 1;/*!< Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. */ - uint32_t : 22; - } bit; - } IN_INT_CLR_CH4; - - union { - __IOM uint32_t reg; /*!< RX CH4 INFIFO status register */ - - struct { - __IM uint32_t INFIFO_FULL_L2_CH4 : 1; /*!< Rx FIFO full signal for Rx channel. */ - __IM uint32_t INFIFO_EMPTY_L2_CH4 : 1; /*!< Rx FIFO empty signal for Rx channel. */ - __IM uint32_t INFIFO_CNT_L2_CH4 : 4; /*!< The register stores the byte number of the data in Rx FIFO for - Rx channel. */ - __IM uint32_t INFIFO_FULL_L1_CH4 : 1; /*!< Tx FIFO full signal for Tx channel 1. */ - __IM uint32_t INFIFO_EMPTY_L1_CH4 : 1; /*!< Tx FIFO empty signal for Tx channel 1. */ - __IM uint32_t INFIFO_CNT_L1_CH4 : 5; /*!< The register stores the byte number of the data in Tx FIFO for - Tx channel 1. */ - uint32_t : 3; - __IM uint32_t INFIFO_FULL_L3_CH4 : 1; /*!< Tx FIFO full signal for Tx channel 1. */ - __IM uint32_t INFIFO_EMPTY_L3_CH4 : 1; /*!< Tx FIFO empty signal for Tx channel 1. */ - __IM uint32_t INFIFO_CNT_L3_CH4 : 2; /*!< The register stores the byte number of the data in Tx FIFO for - Tx channel 1. */ - uint32_t : 12; - } bit; - } INFIFO_STATUS_CH4; - - union { - __IOM uint32_t reg; /*!< RX CH4 INFIFO pop register */ - - struct { - __IM uint32_t INFIFO_RDATA_CH4 : 11; /*!< This register stores the data popping from DMA Rx FIFO. */ - __IOM uint32_t INFIFO_POP_CH4 : 1; /*!< Set this bit to pop data from DMA Rx FIFO. */ - uint32_t : 20; - } bit; - } IN_POP_CH4; - - union { - __IOM uint32_t reg; /*!< RX CH4 in_link dscr ctrl register */ - - struct { - uint32_t : 20; - __IOM uint32_t INLINK_AUTO_RET_CH4 : 1; /*!< Set this bit to return to current inlink descriptor's address, - when there are some errors in current receiving data. */ - __IOM uint32_t INLINK_STOP_CH4 : 1; /*!< Set this bit to stop dealing with the inlink descriptors. */ - __IOM uint32_t INLINK_START_CH4 : 1; /*!< Set this bit to start dealing with the inlink descriptors. */ - __IOM uint32_t INLINK_RESTART_CH4 : 1; /*!< Set this bit to mount a new inlink descriptor. */ - __IM uint32_t INLINK_PARK_CH4 : 1; /*!< 1: the inlink descriptor's FSM is in idle state. 0: the inlink - descriptor's FSM is working. */ - uint32_t : 7; - } bit; - } IN_LINK_CONF_CH4; - - union { - __IOM uint32_t reg; /*!< RX CH4 in_link dscr addr register */ - - struct { - __IOM uint32_t INLINK_ADDR_CH4 : 32; /*!< This register stores the first inlink descriptor's address. */ - } bit; - } IN_LINK_ADDR_CH4; - - union { - __IOM uint32_t reg; /*!< RX CH4 state register */ - - struct { - __IM uint32_t INLINK_DSCR_ADDR_CH4 : 18; /*!< This register stores the current inlink descriptor's address. */ - __IM uint32_t IN_DSCR_STATE_CH4 : 2; /*!< This register stores the current descriptor state machine state. */ - __IM uint32_t IN_STATE_CH4 : 3; /*!< This register stores the current control module state machine - state. */ - __IM uint32_t IN_RESET_AVAIL_CH4 : 1; /*!< This register indicate that if the channel reset is safety. */ - uint32_t : 8; - } bit; - } IN_STATE_CH4; - - union { - __IOM uint32_t reg; /*!< RX CH4 eof des addr register */ - - struct { - __IM uint32_t IN_SUC_EOF_DES_ADDR_CH4 : 32;/*!< This register stores the address of the inlink descriptor when - the EOF bit in this descriptor is 1. */ - } bit; - } IN_SUC_EOF_DES_ADDR_CH4; - - union { - __IOM uint32_t reg; /*!< RX CH4 err eof des addr register */ - - struct { - __IM uint32_t IN_ERR_EOF_DES_ADDR_CH4 : 32;/*!< This register stores the address of the inlink descriptor when - there are some errors in current receiving data. */ - } bit; - } IN_ERR_EOF_DES_ADDR_CH4; - - union { - __IOM uint32_t reg; /*!< RX CH4 next dscr addr register */ - - struct { - __IM uint32_t INLINK_DSCR_CH4 : 32; /*!< The address of the next inlink descriptor address x. */ - } bit; - } IN_DSCR_CH4; - - union { - __IOM uint32_t reg; /*!< RX CH4 last dscr addr register */ - - struct { - __IM uint32_t INLINK_DSCR_BF0_CH4 : 32; /*!< The address of the last inlink descriptor's next address x-1. */ - } bit; - } IN_DSCR_BF0_CH4; - - union { - __IOM uint32_t reg; /*!< RX CH4 second-to-last dscr addr register */ - - struct { - __IM uint32_t INLINK_DSCR_BF1_CH4 : 32; /*!< The address of the second-to-last inlink descriptor's next address - x-2. */ - } bit; - } IN_DSCR_BF1_CH4; - __IM uint32_t RESERVED38; - - union { - __IOM uint32_t reg; /*!< RX CH4 arb register */ - - struct { - __IOM uint32_t IN_ARB_TOKEN_NUM_CH4 : 4; /*!< Set the max number of token count of arbiter */ - __IOM uint32_t EXTER_IN_ARB_PRIORITY_CH4 : 2;/*!< Set the priority of channel */ - __IOM uint32_t INTER_IN_ARB_PRIORITY_CH4 : 3;/*!< Set the priority of channel */ - uint32_t : 23; - } bit; - } IN_ARB_CH4; - __IM uint32_t RESERVED39; - - union { - __IOM uint32_t reg; /*!< RX CH4 ETM config register */ - - struct { - __IOM uint32_t IN_ETM_EN_CH4 : 1; /*!< Set this bit to 1 to enable ETM task function */ - __IOM uint32_t IN_ETM_LOOP_EN_CH4 : 1; /*!< when this bit is 1, dscr can be processed after receiving a - task */ - __IOM uint32_t IN_DSCR_TASK_MAK_CH4 : 2; /*!< ETM dscr_ready maximum cache numbers */ - uint32_t : 28; - } bit; - } IN_ETM_CONF_CH4; - __IM uint32_t RESERVED40[13]; - - union { - __IOM uint32_t reg; /*!< rx CH4 fifo cnt register */ - - struct { - __IM uint32_t IN_CMDFIFO_INFIFO_CNT_CH4 : 10;/*!< only for debug */ - uint32_t : 22; - } bit; - } IN_FIFO_CNT_CH4; - - union { - __IOM uint32_t reg; /*!< rx CH4 pop data cnt register */ - - struct { - __IM uint32_t IN_CMDFIFO_POP_DATA_CNT_CH4 : 8;/*!< only for debug */ - uint32_t : 24; - } bit; - } IN_POP_DATA_CNT_CH4; - - union { - __IOM uint32_t reg; /*!< rx CH4 xaddr register */ - - struct { - __IM uint32_t IN_CMDFIFO_XADDR_CH4 : 32; /*!< only for debug */ - } bit; - } IN_XADDR_CH4; - - union { - __IOM uint32_t reg; /*!< rx CH4 buf len hb rcv register */ - - struct { - __IM uint32_t IN_CMDFIFO_BUF_HB_RCV_CH4 : 29;/*!< only for debug */ - uint32_t : 3; - } bit; - } IN_BUF_HB_RCV_CH4; - __IM uint32_t RESERVED41[28]; - - union { - __IOM uint32_t reg; /*!< RX CH5 config0 register */ - - struct { - uint32_t : 3; - __IOM uint32_t IN_ECC_AES_EN_CH5 : 1; /*!< When access address space is ecc/aes area, this bit should be - set to 1. In this case, the start address of square should - be 16-bit aligned. The width of square multiply byte number - of one pixel should be 16-bit aligned. */ - uint32_t : 2; - __IOM uint32_t IN_MEM_BURST_LENGTH_CH5 : 3;/*!< Block size of Rx channel 1. 0: single 1: 16 bytes 2: 32 bytes - 3: 64 bytes 4: 128 bytes */ - uint32_t : 3; - __IOM uint32_t IN_PAGE_BOUND_EN_CH5 : 1; /*!< Set this bit to 1 to make sure AXI write data don't cross the - address boundary which define by mem_burst_length */ - uint32_t : 11; - __IOM uint32_t IN_RST_CH5 : 1; /*!< Write 1 then write 0 to this bit to reset Rx channel */ - __IOM uint32_t IN_CMD_DISABLE_CH5 : 1; /*!< Write 1 before reset and write 0 after reset */ - uint32_t : 6; - } bit; - } IN_CONF0_CH5; - - union { - __IOM uint32_t reg; /*!< RX CH5 config1 register */ - - struct { - __IOM uint32_t BLOCK_START_ADDR_CH5 : 32; /*!< RX Channel 5 destination start address */ - } bit; - } IN_CONF1_CH5; - - union { - __IOM uint32_t reg; /*!< RX CH5 config2 register */ - - struct { - __IOM uint32_t BLOCK_ROW_LENGTH_12LINE_CH5 : 16;/*!< The number of bytes contained in a row block 12line in RX channel - 5 */ - __IOM uint32_t BLOCK_ROW_LENGTH_4LINE_CH5 : 16;/*!< The number of bytes contained in a row block 4line in RX channel - 5 */ - } bit; - } IN_CONF2_CH5; - - union { - __IOM uint32_t reg; /*!< RX CH5 config3 register */ - - struct { - __IOM uint32_t BLOCK_LENGTH_12LINE_CH5 : 14;/*!< The number of bytes contained in a block 12line */ - __IOM uint32_t BLOCK_LENGTH_4LINE_CH5 : 14;/*!< The number of bytes contained in a block 4line */ - uint32_t : 4; - } bit; - } IN_CONF3_CH5; - - union { - __IOM uint32_t reg; /*!< RX CH5 interrupt raw register */ - - struct { - __IOM uint32_t IN_DONE_CH5_INT_RAW : 1; /*!< The raw interrupt bit turns to high level when the last data - pointed by one inlink descriptor has been transmitted to - peripherals for Rx channel 1. */ - __IOM uint32_t IN_SUC_EOF_CH5_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when the last data - pointed by one inlink descriptor has been received and - no data error is detected for Rx channel 1. */ - __IOM uint32_t INFIFO_OVF_L1_CH5_INT_RAW : 1;/*!< This raw interrupt bit turns to high level when fifo of Rx channel - is overflow. */ - __IOM uint32_t INFIFO_UDF_L1_CH5_INT_RAW : 1;/*!< This raw interrupt bit turns to high level when fifo of Rx channel - is underflow. */ - __IOM uint32_t FETCH_MB_COL_CNT_OVF_CH5_INT_RAW : 1;/*!< This raw interrupt bit turns to high level when fifo of Rx channel - is underflow. */ - uint32_t : 27; - } bit; - } IN_INT_RAW_CH5; - - union { - __IOM uint32_t reg; /*!< RX CH5 interrupt ena register */ - - struct { - __IOM uint32_t IN_DONE_CH5_INT_ENA : 1; /*!< The interrupt enable bit for the IN_DONE_CH_INT interrupt. */ - __IOM uint32_t IN_SUC_EOF_CH5_INT_ENA : 1;/*!< The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. */ - __IOM uint32_t INFIFO_OVF_L1_CH5_INT_ENA : 1;/*!< The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. */ - __IOM uint32_t INFIFO_UDF_L1_CH5_INT_ENA : 1;/*!< The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. */ - __IOM uint32_t FETCH_MB_COL_CNT_OVF_CH5_INT_ENA : 1;/*!< The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. */ - uint32_t : 27; - } bit; - } IN_INT_ENA_CH5; - - union { - __IOM uint32_t reg; /*!< RX CH5 interrupt st register */ - - struct { - __IM uint32_t IN_DONE_CH5_INT_ST : 1; /*!< The raw interrupt status bit for the IN_DONE_CH_INT interrupt. */ - __IM uint32_t IN_SUC_EOF_CH5_INT_ST : 1; /*!< The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. */ - __IM uint32_t INFIFO_OVF_L1_CH5_INT_ST : 1;/*!< The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. */ - __IM uint32_t INFIFO_UDF_L1_CH5_INT_ST : 1;/*!< The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. */ - __IM uint32_t FETCH_MB_COL_CNT_OVF_CH5_INT_ST : 1;/*!< The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. */ - uint32_t : 27; - } bit; - } IN_INT_ST_CH5; - - union { - __IOM uint32_t reg; /*!< RX CH5 interrupt clr register */ - - struct { - __OM uint32_t IN_DONE_CH5_INT_CLR : 1; /*!< Set this bit to clear the IN_DONE_CH_INT interrupt. */ - __OM uint32_t IN_SUC_EOF_CH5_INT_CLR : 1;/*!< Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. */ - __OM uint32_t INFIFO_OVF_L1_CH5_INT_CLR : 1;/*!< Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. */ - __OM uint32_t INFIFO_UDF_L1_CH5_INT_CLR : 1;/*!< Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. */ - __OM uint32_t FETCH_MB_COL_CNT_OVF_CH5_INT_CLR : 1;/*!< Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. */ - uint32_t : 27; - } bit; - } IN_INT_CLR_CH5; - - union { - __IOM uint32_t reg; /*!< RX CH5 INFIFO status register */ - - struct { - __IM uint32_t INFIFO_FULL_L1_CH5 : 1; /*!< Tx FIFO full signal for Tx channel 1. */ - __IM uint32_t INFIFO_EMPTY_L1_CH5 : 1; /*!< Tx FIFO empty signal for Tx channel 1. */ - __IM uint32_t INFIFO_CNT_L1_CH5 : 5; /*!< The register stores the byte number of the data in Tx FIFO for - Tx channel 1. */ - uint32_t : 25; - } bit; - } INFIFO_STATUS_CH5; - - union { - __IOM uint32_t reg; /*!< RX CH5 INFIFO pop register */ - - struct { - __IM uint32_t INFIFO_RDATA_CH5 : 11; /*!< This register stores the data popping from DMA Rx FIFO. */ - __IOM uint32_t INFIFO_POP_CH5 : 1; /*!< Set this bit to pop data from DMA Rx FIFO. */ - uint32_t : 20; - } bit; - } IN_POP_CH5; - - union { - __IOM uint32_t reg; /*!< RX CH5 state register */ - - struct { - __IM uint32_t IN_STATE_CH5 : 3; /*!< This register stores the current control module state machine - state. */ - __IM uint32_t IN_RESET_AVAIL_CH5 : 1; /*!< This register indicate that if the channel reset is safety. */ - uint32_t : 28; - } bit; - } IN_STATE_CH5; - __IM uint32_t RESERVED42[5]; - - union { - __IOM uint32_t reg; /*!< RX CH5 arb register */ - - struct { - __IOM uint32_t IN_ARB_TOKEN_NUM_CH5 : 4; /*!< Set the max number of token count of arbiter */ - uint32_t : 2; - __IOM uint32_t INTER_IN_ARB_PRIORITY_CH5 : 3;/*!< Set the priority of channel */ - uint32_t : 23; - } bit; - } IN_ARB_CH5; - __IM uint32_t RESERVED43[15]; - - union { - __IOM uint32_t reg; /*!< rx CH5 fifo cnt register */ - - struct { - __IM uint32_t IN_CMDFIFO_INFIFO_CNT_CH5 : 10;/*!< only for debug */ - uint32_t : 22; - } bit; - } IN_FIFO_CNT_CH5; - - union { - __IOM uint32_t reg; /*!< rx CH5 pop data cnt register */ - - struct { - __IM uint32_t IN_CMDFIFO_POP_DATA_CNT_CH5 : 8;/*!< only for debug */ - uint32_t : 24; - } bit; - } IN_POP_DATA_CNT_CH5; - - union { - __IOM uint32_t reg; /*!< rx CH5 xaddr register */ - - struct { - __IM uint32_t IN_CMDFIFO_XADDR_CH5 : 32; /*!< only for debug */ - } bit; - } IN_XADDR_CH5; - - union { - __IOM uint32_t reg; /*!< rx CH5 buf len hb rcv register */ - - struct { - __IM uint32_t IN_CMDFIFO_BUF_HB_RCV_CH5 : 29;/*!< only for debug */ - uint32_t : 3; - } bit; - } IN_BUF_HB_RCV_CH5; - __IM uint32_t RESERVED44[28]; - - union { - __IOM uint32_t reg; /*!< inter memory axi err register */ - - struct { - __IM uint32_t INTER_RID_ERR_CNT : 4; /*!< AXI read id err cnt */ - __IM uint32_t INTER_RRESP_ERR_CNT : 4; /*!< AXI read resp err cnt */ - __IM uint32_t INTER_WRESP_ERR_CNT : 4; /*!< AXI write resp err cnt */ - __IM uint32_t INTER_RD_FIFO_CNT : 3; /*!< AXI read cmd fifo remain cmd count */ - __IM uint32_t INTER_RD_BAK_FIFO_CNT : 4; /*!< AXI read backup cmd fifo remain cmd count */ - __IM uint32_t INTER_WR_FIFO_CNT : 3; /*!< AXI write cmd fifo remain cmd count */ - __IM uint32_t INTER_WR_BAK_FIFO_CNT : 4; /*!< AXI write backup cmd fifo remain cmd count */ - uint32_t : 6; - } bit; - } INTER_AXI_ERR; - - union { - __IOM uint32_t reg; /*!< exter memory axi err register */ - - struct { - __IM uint32_t EXTER_RID_ERR_CNT : 4; /*!< AXI read id err cnt */ - __IM uint32_t EXTER_RRESP_ERR_CNT : 4; /*!< AXI read resp err cnt */ - __IM uint32_t EXTER_WRESP_ERR_CNT : 4; /*!< AXI write resp err cnt */ - __IM uint32_t EXTER_RD_FIFO_CNT : 3; /*!< AXI read cmd fifo remain cmd count */ - __IM uint32_t EXTER_RD_BAK_FIFO_CNT : 4; /*!< AXI read backup cmd fifo remain cmd count */ - __IM uint32_t EXTER_WR_FIFO_CNT : 3; /*!< AXI write cmd fifo remain cmd count */ - __IM uint32_t EXTER_WR_BAK_FIFO_CNT : 4; /*!< AXI write backup cmd fifo remain cmd count */ - uint32_t : 6; - } bit; - } EXTER_AXI_ERR; - - union { - __IOM uint32_t reg; /*!< axi reset config register */ - - struct { - __IOM uint32_t INTER_AXIM_RD_RST : 1; /*!< Write 1 then write 0 to this bit to reset axi master read data - FIFO. */ - __IOM uint32_t INTER_AXIM_WR_RST : 1; /*!< Write 1 then write 0 to this bit to reset axi master write data - FIFO. */ - __IOM uint32_t EXTER_AXIM_RD_RST : 1; /*!< Write 1 then write 0 to this bit to reset axi master read data - FIFO. */ - __IOM uint32_t EXTER_AXIM_WR_RST : 1; /*!< Write 1 then write 0 to this bit to reset axi master write data - FIFO. */ - __IOM uint32_t CLK_EN : 1; /*!< 1'h1: Force clock on for register. 1'h0: Support clock only - when application writes registers. */ - uint32_t : 27; - } bit; - } RST_CONF; - - union { - __IOM uint32_t reg; /*!< Start address of inter memory range0 register */ - - struct { - __IOM uint32_t ACCESS_INTER_MEM_START_ADDR0 : 32;/*!< The start address of accessible address space. */ - } bit; - } INTER_MEM_START_ADDR0; - - union { - __IOM uint32_t reg; /*!< end address of inter memory range0 register */ - - struct { - __IOM uint32_t ACCESS_INTER_MEM_END_ADDR0 : 32;/*!< The end address of accessible address space. The access address - beyond this range would lead to descriptor error. */ - } bit; - } INTER_MEM_END_ADDR0; - - union { - __IOM uint32_t reg; /*!< Start address of inter memory range1 register */ - - struct { - __IOM uint32_t ACCESS_INTER_MEM_START_ADDR1 : 32;/*!< The start address of accessible address space. */ - } bit; - } INTER_MEM_START_ADDR1; - - union { - __IOM uint32_t reg; /*!< end address of inter memory range1 register */ - - struct { - __IOM uint32_t ACCESS_INTER_MEM_END_ADDR1 : 32;/*!< The end address of accessible address space. The access address - beyond this range would lead to descriptor error. */ - } bit; - } INTER_MEM_END_ADDR1; - __IM uint32_t RESERVED45; - - union { - __IOM uint32_t reg; /*!< Start address of exter memory range0 register */ - - struct { - __IOM uint32_t ACCESS_EXTER_MEM_START_ADDR0 : 32;/*!< The start address of accessible address space. */ - } bit; - } EXTER_MEM_START_ADDR0; - - union { - __IOM uint32_t reg; /*!< end address of exter memory range0 register */ - - struct { - __IOM uint32_t ACCESS_EXTER_MEM_END_ADDR0 : 32;/*!< The end address of accessible address space. The access address - beyond this range would lead to descriptor error. */ - } bit; - } EXTER_MEM_END_ADDR0; - - union { - __IOM uint32_t reg; /*!< Start address of exter memory range1 register */ - - struct { - __IOM uint32_t ACCESS_EXTER_MEM_START_ADDR1 : 32;/*!< The start address of accessible address space. */ - } bit; - } EXTER_MEM_START_ADDR1; - - union { - __IOM uint32_t reg; /*!< end address of exter memory range1 register */ - - struct { - __IOM uint32_t ACCESS_EXTER_MEM_END_ADDR1 : 32;/*!< The end address of accessible address space. The access address - beyond this range would lead to descriptor error. */ - } bit; - } EXTER_MEM_END_ADDR1; - - union { - __IOM uint32_t reg; /*!< reserved */ - - struct { - __IOM uint32_t OUT_ARB_TIMEOUT_NUM : 16; /*!< Set the max number of timeout count of arbiter */ - __IOM uint32_t OUT_WEIGHT_EN : 1; /*!< reserved */ - uint32_t : 15; - } bit; - } OUT_ARB_CONFIG; - - union { - __IOM uint32_t reg; /*!< reserved */ - - struct { - __IOM uint32_t IN_ARB_TIMEOUT_NUM : 16; /*!< Set the max number of timeout count of arbiter */ - __IOM uint32_t IN_WEIGHT_EN : 1; /*!< reserved */ - uint32_t : 15; - } bit; - } IN_ARB_CONFIG; - __IM uint32_t RESERVED46; - - union { - __IOM uint32_t reg; /*!< reserved */ - - struct { - __IOM uint32_t DATE : 32; /*!< register version. */ - } bit; - } DATE; - __IM uint32_t RESERVED47[4]; - - union { - __IOM uint32_t reg; /*!< counter reset register */ - - struct { - __IOM uint32_t RX_CH0_EXTER_COUNTER_RST : 1;/*!< Write 1 then write 0 to this bit to reset rx ch0 counter. */ - __IOM uint32_t RX_CH1_EXTER_COUNTER_RST : 1;/*!< Write 1 then write 0 to this bit to reset rx ch1 counter. */ - __IOM uint32_t RX_CH2_INTER_COUNTER_RST : 1;/*!< Write 1 then write 0 to this bit to reset rx ch2 counter. */ - __IOM uint32_t RX_CH5_INTER_COUNTER_RST : 1;/*!< Write 1 then write 0 to this bit to reset rx ch5 counter. */ - uint32_t : 28; - } bit; - } COUNTER_RST; - - union { - __IOM uint32_t reg; /*!< rx ch0 counter register */ - - struct { - __IM uint32_t RX_CH0_CNT : 23; /*!< rx ch0 counter register */ - uint32_t : 9; - } bit; - } RX_CH0_COUNTER; - - union { - __IOM uint32_t reg; /*!< rx ch1 counter register */ - - struct { - __IM uint32_t RX_CH1_CNT : 21; /*!< rx ch1 counter register */ - uint32_t : 11; - } bit; - } RX_CH1_COUNTER; - - union { - __IOM uint32_t reg; /*!< rx ch2 counter register */ - - struct { - __IM uint32_t RX_CH2_CNT : 11; /*!< rx ch2 counter register */ - uint32_t : 21; - } bit; - } RX_CH2_COUNTER; - - union { - __IOM uint32_t reg; /*!< rx ch5 counter register */ - - struct { - __IM uint32_t RX_CH5_CNT : 17; /*!< rx ch5 counter register */ - uint32_t : 15; - } bit; - } RX_CH5_COUNTER; -} H264_DMA_Type; /*!< Size = 2916 (0xb64) */ - - - -/* =========================================================================================================================== */ -/* ================ HMAC ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief HMAC (Hash-based Message Authentication Code) Accelerator (HMAC) - */ - -typedef struct { /*!< HMAC Structure */ - __IM uint32_t RESERVED[16]; - - union { - __IOM uint32_t reg; /*!< Process control register 0. */ - - struct { - __OM uint32_t SET_START : 1; /*!< Start hmac operation. */ - uint32_t : 31; - } bit; - } SET_START; - - union { - __IOM uint32_t reg; /*!< Configure purpose. */ - - struct { - __OM uint32_t PURPOSE_SET : 4; /*!< Set hmac parameter purpose. */ - uint32_t : 28; - } bit; - } SET_PARA_PURPOSE; - - union { - __IOM uint32_t reg; /*!< Configure key. */ - - struct { - __OM uint32_t KEY_SET : 3; /*!< Set hmac parameter key. */ - uint32_t : 29; - } bit; - } SET_PARA_KEY; - - union { - __IOM uint32_t reg; /*!< Finish initial configuration. */ - - struct { - __OM uint32_t SET_PARA_END : 1; /*!< Finish hmac configuration. */ - uint32_t : 31; - } bit; - } SET_PARA_FINISH; - - union { - __IOM uint32_t reg; /*!< Process control register 1. */ - - struct { - __OM uint32_t SET_TEXT_ONE : 1; /*!< Call SHA to calculate one message block. */ - uint32_t : 31; - } bit; - } SET_MESSAGE_ONE; - - union { - __IOM uint32_t reg; /*!< Process control register 2. */ - - struct { - __OM uint32_t SET_TEXT_ING : 1; /*!< Continue typical hmac. */ - uint32_t : 31; - } bit; - } SET_MESSAGE_ING; - - union { - __IOM uint32_t reg; /*!< Process control register 3. */ - - struct { - __OM uint32_t SET_TEXT_END : 1; /*!< Start hardware padding. */ - uint32_t : 31; - } bit; - } SET_MESSAGE_END; - - union { - __IOM uint32_t reg; /*!< Process control register 4. */ - - struct { - __OM uint32_t SET_RESULT_END : 1; /*!< After read result from upstream, then let hmac back to idle. */ - uint32_t : 31; - } bit; - } SET_RESULT_FINISH; - - union { - __IOM uint32_t reg; /*!< Invalidate register 0. */ - - struct { - __OM uint32_t SET_INVALIDATE_JTAG : 1; /*!< Clear result from hmac downstream JTAG. */ - uint32_t : 31; - } bit; - } SET_INVALIDATE_JTAG; - - union { - __IOM uint32_t reg; /*!< Invalidate register 1. */ - - struct { - __OM uint32_t SET_INVALIDATE_DS : 1; /*!< Clear result from hmac downstream DS. */ - uint32_t : 31; - } bit; - } SET_INVALIDATE_DS; - - union { - __IOM uint32_t reg; /*!< Error register. */ - - struct { - __IM uint32_t QUERY_CHECK : 1; /*!< Hmac configuration state. 0: key are agree with purpose. 1: - error */ - uint32_t : 31; - } bit; - } QUERY_ERROR; - - union { - __IOM uint32_t reg; /*!< Busy register. */ - - struct { - __IM uint32_t BUSY_STATE : 1; /*!< Hmac state. 1'b0: idle. 1'b1: busy */ - uint32_t : 31; - } bit; - } QUERY_BUSY; - __IM uint32_t RESERVED1[4]; - __IOM uint32_t WR_MESSAGE_MEM[16]; /*!< Message block memory. */ - __IOM uint32_t RD_RESULT_MEM[8]; /*!< Result from upstream. */ - __IM uint32_t RESERVED2[4]; - - union { - __IOM uint32_t reg; /*!< Process control register 5. */ - - struct { - __OM uint32_t SET_TEXT_PAD : 1; /*!< Start software padding. */ - uint32_t : 31; - } bit; - } SET_MESSAGE_PAD; - - union { - __IOM uint32_t reg; /*!< Process control register 6. */ - - struct { - __OM uint32_t SET_ONE_BLOCK : 1; /*!< Don't have to do padding. */ - uint32_t : 31; - } bit; - } ONE_BLOCK; - - union { - __IOM uint32_t reg; /*!< Jtag register 0. */ - - struct { - __OM uint32_t SOFT_JTAG_CTRL : 1; /*!< Turn on JTAG verification. */ - uint32_t : 31; - } bit; - } SOFT_JTAG_CTRL; - - union { - __IOM uint32_t reg; /*!< Jtag register 1. */ - - struct { - __OM uint32_t WR_JTAG : 32; /*!< 32-bit of key to be compared. */ - } bit; - } WR_JTAG; - __IM uint32_t RESERVED3[63]; - - union { - __IOM uint32_t reg; /*!< Date register. */ - - struct { - __IOM uint32_t DATE : 30; /*!< Hmac date information/ hmac version information. */ - uint32_t : 2; - } bit; - } DATE; -} HMAC_Type; /*!< Size = 512 (0x200) */ - - - -/* =========================================================================================================================== */ -/* ================ HP_SYS ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief High-Power System (HP_SYS) - */ - -typedef struct { /*!< HP_SYS Structure */ - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_VER_DATE : 32; /*!< NA */ - } bit; - } VER_DATE; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_CLK_EN : 1; /*!< NA */ - uint32_t : 31; - } bit; - } CLK_EN; - __IM uint32_t RESERVED[2]; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t CPU_INTR_FROM_CPU_0 : 1; /*!< set 1 will triger a interrupt */ - uint32_t : 31; - } bit; - } CPU_INTR_FROM_CPU_0; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t CPU_INTR_FROM_CPU_1 : 1; /*!< set 1 will triger a interrupt */ - uint32_t : 31; - } bit; - } CPU_INTR_FROM_CPU_1; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t CPU_INTR_FROM_CPU_2 : 1; /*!< set 1 will triger a interrupt */ - uint32_t : 31; - } bit; - } CPU_INTR_FROM_CPU_2; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t CPU_INTR_FROM_CPU_3 : 1; /*!< set 1 will triger a interrupt */ - uint32_t : 31; - } bit; - } CPU_INTR_FROM_CPU_3; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_L2_CACHE_CLK_ON : 1; /*!< l2 cahce clk enable */ - __IOM uint32_t REG_L1_D_CACHE_CLK_ON : 1; /*!< l1 dcahce clk enable */ - uint32_t : 2; - __IOM uint32_t REG_L1_I1_CACHE_CLK_ON : 1;/*!< l1 icahce1 clk enable */ - __IOM uint32_t REG_L1_I0_CACHE_CLK_ON : 1;/*!< l1 icahce0 clk enable */ - uint32_t : 26; - } bit; - } CACHE_CLK_CONFIG; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - uint32_t : 1; - __IOM uint32_t REG_L1_D_CACHE_RESET : 1; /*!< set 1 to reset l1 dcahce */ - uint32_t : 2; - __IOM uint32_t REG_L1_I1_CACHE_RESET : 1; /*!< set 1 to reset l1 icahce1 */ - __IOM uint32_t REG_L1_I0_CACHE_RESET : 1; /*!< set 1 to reset l1 icahce0 */ - uint32_t : 26; - } bit; - } CACHE_RESET_CONFIG; - __IM uint32_t RESERVED1; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_SYS_DMA_ADDR_SEL : 1; /*!< 0 means dma access extmem use 8xxx_xxxx else use 4xxx_xxxx */ - uint32_t : 31; - } bit; - } DMA_ADDR_CTRL; - __IM uint32_t RESERVED2; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_TCM_RAM_IBUS0_WT : 3; /*!< weight value of ibus0 */ - __IOM uint32_t REG_TCM_RAM_IBUS1_WT : 3; /*!< weight value of ibus1 */ - __IOM uint32_t REG_TCM_RAM_IBUS2_WT : 3; /*!< weight value of ibus2 */ - __IOM uint32_t REG_TCM_RAM_IBUS3_WT : 3; /*!< weight value of ibus3 */ - __IOM uint32_t REG_TCM_RAM_DBUS0_WT : 3; /*!< weight value of dbus0 */ - __IOM uint32_t REG_TCM_RAM_DBUS1_WT : 3; /*!< weight value of dbus1 */ - __IOM uint32_t REG_TCM_RAM_DBUS2_WT : 3; /*!< weight value of dbus2 */ - __IOM uint32_t REG_TCM_RAM_DBUS3_WT : 3; /*!< weight value of dbus3 */ - __IOM uint32_t REG_TCM_RAM_DMA_WT : 3; /*!< weight value of dma */ - uint32_t : 4; - __IOM uint32_t REG_TCM_RAM_WRR_HIGH : 1; /*!< enable weighted round robin arbitration */ - } bit; - } TCM_RAM_WRR_CONFIG; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_TCM_SW_PARITY_BWE_MASK_CTRL : 1;/*!< Set 1 to mask tcm bwe parity code bit */ - uint32_t : 31; - } bit; - } TCM_SW_PARITY_BWE_MASK; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_HP_TCM_CLK_FORCE_ON : 1;/*!< hp_tcm clk gatig force on */ - uint32_t : 31; - } bit; - } TCM_RAM_PWR_CTRL0; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_L2_ROM_CLK_FORCE_ON : 1;/*!< l2_rom clk gating force on */ - uint32_t : 31; - } bit; - } L2_ROM_PWR_CTRL0; - __IM uint32_t RESERVED3[3]; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_PROBE_A_MOD_SEL : 16; /*!< Tihs field is used to selec probe_group from probe_group0 to - probe_group15 for module's probe_out[31:0] in a mode */ - __IOM uint32_t REG_PROBE_A_TOP_SEL : 8; /*!< Tihs field is used to selec module's probe_out[31:0] as probe - out in a mode */ - __IOM uint32_t REG_PROBE_L_SEL : 2; /*!< Tihs field is used to selec probe_out[31:16] */ - __IOM uint32_t REG_PROBE_H_SEL : 2; /*!< Tihs field is used to selec probe_out[31:16] */ - __IOM uint32_t REG_PROBE_GLOBAL_EN : 1; /*!< Set this bit to enable global debug probe in hp system. */ - uint32_t : 3; - } bit; - } PROBEA_CTRL; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_PROBE_B_MOD_SEL : 16; /*!< Tihs field is used to selec probe_group from probe_group0 to - probe_group15 for module's probe_out[31:0] in b mode. */ - __IOM uint32_t REG_PROBE_B_TOP_SEL : 8; /*!< Tihs field is used to select module's probe_out[31:0] as probe_out - in b mode */ - __IOM uint32_t REG_PROBE_B_EN : 1; /*!< Set this bit to enable b mode for debug probe. 1: b mode, 0: - a mode. */ - uint32_t : 7; - } bit; - } PROBEB_CTRL; - __IM uint32_t RESERVED4; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t REG_PROBE_TOP_OUT : 32; /*!< NA */ - } bit; - } PROBE_OUT; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_L2_MEM_CLK_FORCE_ON : 1;/*!< l2ram clk_gating force on */ - uint32_t : 31; - } bit; - } L2_MEM_RAM_PWR_CTRL0; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t REG_CORE0_CORESTALLED_ST : 1;/*!< hp core0 corestalled status */ - __IM uint32_t REG_CORE1_CORESTALLED_ST : 1;/*!< hp core1 corestalled status */ - uint32_t : 30; - } bit; - } CPU_CORESTALLED_ST; - __IM uint32_t RESERVED5[2]; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_ENABLE_SPI_MANUAL_ENCRYPT : 1;/*!< NA */ - __IOM uint32_t REG_ENABLE_DOWNLOAD_DB_ENCRYPT : 1;/*!< NA */ - __IOM uint32_t REG_ENABLE_DOWNLOAD_G0CB_DECRYPT : 1;/*!< NA */ - __IOM uint32_t REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : 1;/*!< NA */ - uint32_t : 28; - } bit; - } CRYPTO_CTRL; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_GPIO_0_HOLD_LOW : 32; /*!< hold control for gpio47~16 */ - } bit; - } GPIO_O_HOLD_CTRL0; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_GPIO_0_HOLD_HIGH : 9; /*!< hold control for gpio56~48 */ - uint32_t : 23; - } bit; - } GPIO_O_HOLD_CTRL1; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_HP_SYS_RDN_ECO_EN : 1; /*!< NA */ - __IM uint32_t REG_HP_SYS_RDN_ECO_RESULT : 1;/*!< NA */ - uint32_t : 30; - } bit; - } RDN_ECO_CS; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_CACHE_APB_POSTW_EN : 1;/*!< cache apb register interface post write enable, 1 will speed - up write, but will take some time to update value to register */ - uint32_t : 31; - } bit; - } CACHE_APB_POSTW_EN; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_L2_MEM_SUB_BLKSIZE : 2;/*!< l2mem sub block size 00=>32 01=>64 10=>128 11=>256 */ - uint32_t : 30; - } bit; - } L2_MEM_SUBSIZE; - __IM uint32_t RESERVED6[5]; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_L2_MEM_ECC_ERR_INT_RAW : 1;/*!< intr triggered when two bit error detected and corrected from - ecc */ - __IOM uint32_t REG_L2_MEM_EXCEED_ADDR_INT_RAW : 1;/*!< intr triggered when access addr exceeds 0xff9ffff at bypass - mode or exceeds 0xff80000 at l2cache 128kb mode or exceeds - 0xff60000 at l2cache 256kb mode */ - __IOM uint32_t REG_L2_MEM_ERR_RESP_INT_RAW : 1;/*!< intr triggered when err response occurs */ - uint32_t : 29; - } bit; - } L2_MEM_INT_RAW; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t REG_L2_MEM_ECC_ERR_INT_ST : 1;/*!< NA */ - __IM uint32_t REG_L2_MEM_EXCEED_ADDR_INT_ST : 1;/*!< NA */ - __IM uint32_t REG_L2_MEM_ERR_RESP_INT_ST : 1;/*!< NA */ - uint32_t : 29; - } bit; - } L2_MEM_INT_ST; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_L2_MEM_ECC_ERR_INT_ENA : 1;/*!< NA */ - __IOM uint32_t REG_L2_MEM_EXCEED_ADDR_INT_ENA : 1;/*!< NA */ - __IOM uint32_t REG_L2_MEM_ERR_RESP_INT_ENA : 1;/*!< NA */ - uint32_t : 29; - } bit; - } L2_MEM_INT_ENA; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __OM uint32_t REG_L2_MEM_ECC_ERR_INT_CLR : 1;/*!< NA */ - __OM uint32_t REG_L2_MEM_EXCEED_ADDR_INT_CLR : 1;/*!< NA */ - __OM uint32_t REG_L2_MEM_ERR_RESP_INT_CLR : 1;/*!< NA */ - uint32_t : 29; - } bit; - } L2_MEM_INT_CLR; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_L2_RAM_UNIT0_ECC_EN : 1;/*!< NA */ - __IOM uint32_t REG_L2_RAM_UNIT1_ECC_EN : 1;/*!< NA */ - __IOM uint32_t REG_L2_RAM_UNIT2_ECC_EN : 1;/*!< NA */ - __IOM uint32_t REG_L2_RAM_UNIT3_ECC_EN : 1;/*!< NA */ - __IOM uint32_t REG_L2_RAM_UNIT4_ECC_EN : 1;/*!< NA */ - __IOM uint32_t REG_L2_RAM_UNIT5_ECC_EN : 1;/*!< NA */ - uint32_t : 26; - } bit; - } L2_MEM_L2_RAM_ECC; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t REG_L2_MEM_EXCEED_ADDR_INT_ADDR : 21;/*!< NA */ - __IM uint32_t REG_L2_MEM_EXCEED_ADDR_INT_WE : 1;/*!< NA */ - __IM uint32_t REG_L2_MEM_EXCEED_ADDR_INT_MASTER : 3;/*!< NA */ - uint32_t : 7; - } bit; - } L2_MEM_INT_RECORD0; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t REG_L2_MEM_ECC_ERR_INT_ADDR : 15;/*!< NA */ - __IM uint32_t REG_L2_MEM_ECC_ONE_BIT_ERR : 1;/*!< NA */ - __IM uint32_t REG_L2_MEM_ECC_TWO_BIT_ERR : 1;/*!< NA */ - __IM uint32_t REG_L2_MEM_ECC_ERR_BIT : 9;/*!< NA */ - __IM uint32_t REG_L2_CACHE_ERR_BANK : 1; /*!< NA */ - uint32_t : 5; - } bit; - } L2_MEM_INT_RECORD1; - __IM uint32_t RESERVED7[3]; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_L2_CACHE_ECC_EN : 1; /*!< NA */ - uint32_t : 31; - } bit; - } L2_MEM_L2_CACHE_ECC; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_L1_CACHE_BUS0_ID : 4; /*!< NA */ - uint32_t : 28; - } bit; - } L1CACHE_BUS0_ID; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_L1_CACHE_BUS1_ID : 4; /*!< NA */ - uint32_t : 28; - } bit; - } L1CACHE_BUS1_ID; - __IM uint32_t RESERVED8[2]; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_L2_MEM_RDN_ECO_EN : 1; /*!< NA */ - __IM uint32_t REG_L2_MEM_RDN_ECO_RESULT : 1;/*!< NA */ - uint32_t : 30; - } bit; - } L2_MEM_RDN_ECO_CS; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_L2_MEM_RDN_ECO_LOW : 32;/*!< NA */ - } bit; - } L2_MEM_RDN_ECO_LOW; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_L2_MEM_RDN_ECO_HIGH : 32;/*!< NA */ - } bit; - } L2_MEM_RDN_ECO_HIGH; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_HP_TCM_RDN_ECO_EN : 1; /*!< NA */ - __IM uint32_t REG_HP_TCM_RDN_ECO_RESULT : 1;/*!< NA */ - uint32_t : 30; - } bit; - } TCM_RDN_ECO_CS; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_HP_TCM_RDN_ECO_LOW : 32;/*!< NA */ - } bit; - } TCM_RDN_ECO_LOW; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_HP_TCM_RDN_ECO_HIGH : 32;/*!< NA */ - } bit; - } TCM_RDN_ECO_HIGH; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_GPIO_DED_HOLD : 26; /*!< hold control for gpio63~56 */ - uint32_t : 6; - } bit; - } GPIO_DED_HOLD_CTRL; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_L2_MEM_SW_ECC_BWE_MASK_CTRL : 1;/*!< Set 1 to mask bwe hamming code bit */ - uint32_t : 31; - } bit; - } L2_MEM_SW_ECC_BWE_MASK; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_USB20_MEM_CLK_FORCE_ON : 1;/*!< NA */ - uint32_t : 31; - } bit; - } USB20OTG_MEM_CTRL; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 31; - __IOM uint32_t TCM_PARITY_ERR_INT_RAW : 1;/*!< need_des */ - } bit; - } TCM_INT_RAW; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 31; - __IM uint32_t TCM_PARITY_ERR_INT_ST : 1; /*!< need_des */ - } bit; - } TCM_INT_ST; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 31; - __IOM uint32_t TCM_PARITY_ERR_INT_ENA : 1;/*!< need_des */ - } bit; - } TCM_INT_ENA; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 31; - __OM uint32_t TCM_PARITY_ERR_INT_CLR : 1;/*!< need_des */ - } bit; - } TCM_INT_CLR; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IM uint32_t TCM_PARITY_ERR_INT_ADDR : 13;/*!< hp tcm_parity_err_addr */ - uint32_t : 19; - } bit; - } TCM_PARITY_INT_RECORD; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_L1_CACHE_MEM_FO : 6; /*!< need_des */ - uint32_t : 26; - } bit; - } L1_CACHE_PWR_CTRL; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_L2_CACHE_MEM_FO : 2; /*!< need_des */ - uint32_t : 30; - } bit; - } L2_CACHE_PWR_CTRL; - - union { - __IOM uint32_t reg; /*!< CPU_WAITI configuration register */ - - struct { - __IOM uint32_t CPU_WAIT_MODE_FORCE_ON : 1;/*!< Set 1 to force cpu_waiti_clk enable. */ - __IOM uint32_t CPU_WAITI_DELAY_NUM : 4; /*!< This field used to set delay cycle when cpu enter waiti mode, - after delay waiti_clk will close */ - uint32_t : 27; - } bit; - } CPU_WAITI_CONF; - - union { - __IOM uint32_t reg; /*!< Core Debug runstall configure register */ - - struct { - __IOM uint32_t CORE_DEBUG_RUNSTALL_ENABLE : 1;/*!< Set this field to 1 to enable debug runstall feature between - HP-core and LP-core. */ - uint32_t : 31; - } bit; - } CORE_DEBUG_RUNSTALL_CONF; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t EN : 1; /*!< set this field to 1 to enable hp core0&1 ahb timeout handle */ - __IOM uint32_t THRES : 16; /*!< This field used to set hp core0&1 ahb bus timeout threshold */ - uint32_t : 15; - } bit; - } CORE_AHB_TIMEOUT; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t EN : 1; /*!< set this field to 1 to enable hp core0&1 ibus timeout handle */ - __IOM uint32_t THRES : 16; /*!< This field used to set hp core0&1 ibus timeout threshold */ - uint32_t : 15; - } bit; - } CORE_IBUS_TIMEOUT; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t EN : 1; /*!< set this field to 1 to enable hp core0&1 dbus timeout handle */ - __IOM uint32_t THRES : 16; /*!< This field used to set hp core0&1 dbus timeout threshold */ - uint32_t : 15; - } bit; - } CORE_DBUS_TIMEOUT; - __IM uint32_t RESERVED9[3]; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t CPU_ICM_H2X_POST_WR_EN : 1;/*!< need_des */ - __IOM uint32_t CPU_ICM_H2X_CUT_THROUGH_EN : 1;/*!< need_des */ - __IM uint32_t CPU_ICM_H2X_BRIDGE_BUSY : 1;/*!< need_des */ - uint32_t : 29; - } bit; - } ICM_CPU_H2X_CFG; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t PERI1_APB_POSTW_EN : 1; /*!< hp_peri1 apb register interface post write enable, 1 will speed - up write, but will take some time to update value to register */ - uint32_t : 31; - } bit; - } PERI1_APB_POSTW_EN; - - union { - __IOM uint32_t reg; /*!< Bitscrambler Peri Sel */ - - struct { - __IOM uint32_t BITSCRAMBLER_PERI_RX_SEL : 4;/*!< Set this field to sel peri with DMA RX interface to connec with - bitscrambler: 4'h0 : lcd_cam, 4'h1: gpspi2, 4'h2: gpspi3, - 4'h3: parl_io, 4'h4: aes, 4'h5: sha, 4'h6: adc, 4'h7: i2s0, - 4'h8: i2s1, 4'h9: i2s2, 4'ha: i3c_mst, 4'hb: uhci0, 4'hc: - RMT, else : none */ - __IOM uint32_t BITSCRAMBLER_PERI_TX_SEL : 4;/*!< Set this field to sel peri with DMA TX interface to connec with - bitscrambler: 4'h0 : lcd_cam, 4'h1: gpspi2, 4'h2: gpspi3, - 4'h3: parl_io, 4'h4: aes, 4'h5: sha, 4'h6: adc, 4'h7: i2s0, - 4'h8: i2s1, 4'h9: i2s2, 4'ha: i3c_mst, 4'hb: uhci0, 4'hc: - RMT, else : none */ - uint32_t : 24; - } bit; - } BITSCRAMBLER_PERI_SEL; - - union { - __IOM uint32_t reg; /*!< N/A */ - - struct { - __IOM uint32_t GMAC_APB_POSTW_EN : 1; /*!< N/A */ - __IOM uint32_t DSI_HOST_APB_POSTW_EN : 1; /*!< N/A */ - __IOM uint32_t CSI_HOST_APB_SYNC_POSTW_EN : 1;/*!< N/A */ - __IOM uint32_t CSI_HOST_APB_ASYNC_POSTW_EN : 1;/*!< N/A */ - uint32_t : 28; - } bit; - } APB_SYNC_POSTW_EN; - - union { - __IOM uint32_t reg; /*!< N/A */ - - struct { - __IOM uint32_t DEBUG_CH_NUM : 2; /*!< N/A */ - uint32_t : 30; - } bit; - } GDMA_CTRL; - - union { - __IOM uint32_t reg; /*!< N/A */ - - struct { - __IM uint32_t PTP_PPS : 1; /*!< N/A */ - __IOM uint32_t SBD_FLOWCTRL : 1; /*!< N/A */ - __IOM uint32_t PHY_INTF_SEL : 3; /*!< N/A */ - __IOM uint32_t GMAC_MEM_CLK_FORCE_ON : 1; /*!< N/A */ - __IM uint32_t GMAC_RST_CLK_TX_N : 1; /*!< N/A */ - __IM uint32_t GMAC_RST_CLK_RX_N : 1; /*!< N/A */ - uint32_t : 24; - } bit; - } GMAC_CTRL0; - - union { - __IOM uint32_t reg; /*!< N/A */ - - struct { - __IM uint32_t PTP_TIMESTAMP_L : 32; /*!< N/A */ - } bit; - } GMAC_CTRL1; - - union { - __IOM uint32_t reg; /*!< N/A */ - - struct { - __IM uint32_t PTP_TIMESTAMP_H : 32; /*!< N/A */ - } bit; - } GMAC_CTRL2; - - union { - __IOM uint32_t reg; /*!< N/A */ - - struct { - __IOM uint32_t PPA_LSLP_MEM_PD : 1; /*!< N/A */ - __IOM uint32_t JPEG_SDSLP_MEM_PD : 1; /*!< N/A */ - __IOM uint32_t JPEG_LSLP_MEM_PD : 1; /*!< N/A */ - __IOM uint32_t JPEG_DSLP_MEM_PD : 1; /*!< N/A */ - __IOM uint32_t DMA2D_LSLP_MEM_PD : 1; /*!< N/A */ - uint32_t : 27; - } bit; - } VPU_CTRL; - - union { - __IOM uint32_t reg; /*!< N/A */ - - struct { - __IM uint32_t OTG_PHY_TEST_DONE : 1; /*!< N/A */ - __IOM uint32_t USB_MEM_AUX_CTRL : 14; /*!< N/A */ - __IOM uint32_t PHY_SUSPENDM : 1; /*!< N/A */ - __IOM uint32_t PHY_SUSPEND_FORCE_EN : 1; /*!< N/A */ - __IOM uint32_t PHY_RSTN : 1; /*!< N/A */ - __IOM uint32_t PHY_RESET_FORCE_EN : 1; /*!< N/A */ - __IOM uint32_t PHY_PLL_FORCE_EN : 1; /*!< N/A */ - __IOM uint32_t PHY_PLL_EN : 1; /*!< N/A */ - __IOM uint32_t OTG_SUSPENDM : 1; /*!< N/A */ - __IOM uint32_t OTG_PHY_TXBITSTUFF_EN : 1; /*!< N/A */ - __IOM uint32_t OTG_PHY_REFCLK_MODE : 1; /*!< N/A */ - __IOM uint32_t OTG_PHY_BISTEN : 1; /*!< N/A */ - uint32_t : 7; - } bit; - } USBOTG20_CTRL; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t TCM_ERR_RESP_EN : 1; /*!< Set 1 to turn on tcm error response */ - uint32_t : 31; - } bit; - } TCM_ERR_RESP_CTRL; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_L2_MEM_UNIT0_REFERSH_EN : 1;/*!< NA */ - __IOM uint32_t REG_L2_MEM_UNIT1_REFERSH_EN : 1;/*!< NA */ - __IOM uint32_t REG_L2_MEM_UNIT2_REFERSH_EN : 1;/*!< NA */ - __IOM uint32_t REG_L2_MEM_UNIT3_REFERSH_EN : 1;/*!< NA */ - __IOM uint32_t REG_L2_MEM_UNIT4_REFERSH_EN : 1;/*!< NA */ - __IOM uint32_t REG_L2_MEM_UNIT5_REFERSH_EN : 1;/*!< NA */ - __IOM uint32_t REG_L2_MEM_REFERSH_CNT_RESET : 1;/*!< Set 1 to reset l2mem_refresh_cnt */ - __IM uint32_t REG_L2_MEM_UNIT0_REFRESH_DONE : 1;/*!< NA */ - __IM uint32_t REG_L2_MEM_UNIT1_REFRESH_DONE : 1;/*!< NA */ - __IM uint32_t REG_L2_MEM_UNIT2_REFRESH_DONE : 1;/*!< NA */ - __IM uint32_t REG_L2_MEM_UNIT3_REFRESH_DONE : 1;/*!< NA */ - __IM uint32_t REG_L2_MEM_UNIT4_REFRESH_DONE : 1;/*!< NA */ - __IM uint32_t REG_L2_MEM_UNIT5_REFRESH_DONE : 1;/*!< NA */ - uint32_t : 19; - } bit; - } L2_MEM_REFRESH; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_TCM_INIT_EN : 1; /*!< NA */ - __IOM uint32_t REG_TCM_INIT_CNT_RESET : 1;/*!< Set 1 to reset tcm init cnt */ - __IM uint32_t REG_TCM_INIT_DONE : 1; /*!< NA */ - uint32_t : 29; - } bit; - } TCM_INIT; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t TCM_PARITY_CHECK_EN : 1; /*!< Set 1 to turn on tcm parity check */ - uint32_t : 31; - } bit; - } TCM_PARITY_CHECK_CTRL; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t DFV0 : 32; /*!< register for DV */ - } bit; - } DESIGN_FOR_VERIFICATION0; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t DFV1 : 32; /*!< register for DV */ - } bit; - } DESIGN_FOR_VERIFICATION1; - __IM uint32_t RESERVED10[2]; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t CPU : 1; /*!< Set 1 to enable addr interchange between psram and flash in - axi matrix when hp cpu access through cache */ - __IOM uint32_t DMA : 1; /*!< Set 1 to enable addr interchange between psram and flash in - axi matrix when dma device access, lp core access and hp - core access through ahb */ - uint32_t : 30; - } bit; - } PSRAM_FLASH_ADDR_INTERCHANGE; - __IM uint32_t RESERVED11; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t CPU_ICM_H2X_BRESP_ERR_INT_RAW : 1;/*!< the raw interrupt status of bresp error, triggered when if bresp - err occurs in post write mode in ahb2axi. */ - uint32_t : 31; - } bit; - } AHB2AXI_BRESP_ERR_INT_RAW; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 31; - __IM uint32_t CPU_ICM_H2X_BRESP_ERR_INT_ST : 1;/*!< the masked interrupt status of cpu_icm_h2x_bresp_err */ - } bit; - } AHB2AXI_BRESP_ERR_INT_ST; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 31; - __IOM uint32_t CPU_ICM_H2X_BRESP_ERR_INT_ENA : 1;/*!< Write 1 to enable cpu_icm_h2x_bresp_err int */ - } bit; - } AHB2AXI_BRESP_ERR_INT_ENA; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 31; - __OM uint32_t CPU_ICM_H2X_BRESP_ERR_INT_CLR : 1;/*!< Write 1 to clear cpu_icm_h2x_bresp_err int */ - } bit; - } AHB2AXI_BRESP_ERR_INT_CLR; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t L2_MEM_ERR_RESP_EN : 1; /*!< Set 1 to turn on l2mem error response */ - uint32_t : 31; - } bit; - } L2_MEM_ERR_RESP_CTRL; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t L2_MEM_AHB_WRBUFFER_EN : 1;/*!< Set 1 to turn on l2mem ahb wr buffer */ - __IOM uint32_t L2_MEM_AHB_RDBUFFER_EN : 1;/*!< Set 1 to turn on l2mem ahb rd buffer */ - uint32_t : 30; - } bit; - } L2_MEM_AHB_BUFFER_CTRL; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IM uint32_t CORE_DMACTIVE_LPCORE : 1; /*!< hp core dmactive_lpcore value */ - uint32_t : 31; - } bit; - } CORE_DMACTIVE_LPCORE; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t CORE_ERR_RESP_DIS : 3; /*!< Set bit0 to disable ibus err resp. Set bit1 to disable dbus - err resp. Set bit 2 to disable ahb err resp. */ - uint32_t : 29; - } bit; - } CORE_ERR_RESP_DIS; - - union { - __IOM uint32_t reg; /*!< Hp core bus timeout interrupt raw register */ - - struct { - __IOM uint32_t CORE0_AHB_TIMEOUT_INT_RAW : 1;/*!< the raw interrupt status of hp core0 ahb timeout */ - __IOM uint32_t CORE1_AHB_TIMEOUT_INT_RAW : 1;/*!< the raw interrupt status of hp core1 ahb timeout */ - __IOM uint32_t CORE0_IBUS_TIMEOUT_INT_RAW : 1;/*!< the raw interrupt status of hp core0 ibus timeout */ - __IOM uint32_t CORE1_IBUS_TIMEOUT_INT_RAW : 1;/*!< the raw interrupt status of hp core1 ibus timeout */ - __IOM uint32_t CORE0_DBUS_TIMEOUT_INT_RAW : 1;/*!< the raw interrupt status of hp core0 dbus timeout */ - __IOM uint32_t CORE1_DBUS_TIMEOUT_INT_RAW : 1;/*!< the raw interrupt status of hp core1 dbus timeout */ - uint32_t : 26; - } bit; - } CORE_TIMEOUT_INT_RAW; - - union { - __IOM uint32_t reg; /*!< masked interrupt register */ - - struct { - __IM uint32_t CORE0_AHB_TIMEOUT_INT_ST : 1;/*!< the masked interrupt status of hp core0 ahb timeout */ - __IM uint32_t CORE1_AHB_TIMEOUT_INT_ST : 1;/*!< the masked interrupt status of hp core1 ahb timeout */ - __IM uint32_t CORE0_IBUS_TIMEOUT_INT_ST : 1;/*!< the masked interrupt status of hp core0 ibus timeout */ - __IM uint32_t CORE1_IBUS_TIMEOUT_INT_ST : 1;/*!< the masked interrupt status of hp core1 ibus timeout */ - __IM uint32_t CORE0_DBUS_TIMEOUT_INT_ST : 1;/*!< the masked interrupt status of hp core0 dbus timeout */ - __IM uint32_t CORE1_DBUS_TIMEOUT_INT_ST : 1;/*!< the masked interrupt status of hp core1 dbus timeout */ - uint32_t : 26; - } bit; - } CORE_TIMEOUT_INT_ST; - - union { - __IOM uint32_t reg; /*!< masked interrupt register */ - - struct { - __IOM uint32_t CORE0_AHB_TIMEOUT_INT_ENA : 1;/*!< Write 1 to enable hp_core0_ahb_timeout int */ - __IOM uint32_t CORE1_AHB_TIMEOUT_INT_ENA : 1;/*!< Write 1 to enable hp_core1_ahb_timeout int */ - __IOM uint32_t CORE0_IBUS_TIMEOUT_INT_ENA : 1;/*!< Write 1 to enable hp_core0_ibus_timeout int */ - __IOM uint32_t CORE1_IBUS_TIMEOUT_INT_ENA : 1;/*!< Write 1 to enable hp_core1_ibus_timeout int */ - __IOM uint32_t CORE0_DBUS_TIMEOUT_INT_ENA : 1;/*!< Write 1 to enable hp_core0_dbus_timeout int */ - __IOM uint32_t CORE1_DBUS_TIMEOUT_INT_ENA : 1;/*!< Write 1 to enable hp_core1_dbus_timeout int */ - uint32_t : 26; - } bit; - } CORE_TIMEOUT_INT_ENA; - - union { - __IOM uint32_t reg; /*!< interrupt clear register */ - - struct { - __OM uint32_t CORE0_AHB_TIMEOUT_INT_CLR : 1;/*!< Write 1 to clear hp_core0_ahb_timeout int */ - __OM uint32_t CORE1_AHB_TIMEOUT_INT_CLR : 1;/*!< Write 1 to clear hp_core1_ahb_timeout int */ - __OM uint32_t CORE0_IBUS_TIMEOUT_INT_CLR : 1;/*!< Write 1 to clear hp_core0_ibus_timeout int */ - __OM uint32_t CORE1_IBUS_TIMEOUT_INT_CLR : 1;/*!< Write 1 to clear hp_core1_ibus_timeout int */ - __OM uint32_t CORE0_DBUS_TIMEOUT_INT_CLR : 1;/*!< Write 1 to clear hp_core0_dbus_timeout int */ - __OM uint32_t CORE1_DBUS_TIMEOUT_INT_CLR : 1;/*!< Write 1 to clear hp_core1_dbus_timeout int */ - uint32_t : 26; - } bit; - } CORE_TIMEOUT_INT_CLR; - __IM uint32_t RESERVED12[2]; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_GPIO_0_HYS_LOW : 32; /*!< hys control for gpio47~16 */ - } bit; - } GPIO_O_HYS_CTRL0; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_GPIO_0_HYS_HIGH : 9; /*!< hys control for gpio56~48 */ - uint32_t : 23; - } bit; - } GPIO_O_HYS_CTRL1; - __IM uint32_t RESERVED13[2]; - - union { - __IOM uint32_t reg; /*!< rsa pd ctrl register */ - - struct { - __IOM uint32_t RSA_MEM_FORCE_PD : 1; /*!< Set this bit to power down rsa internal memory. */ - __IOM uint32_t RSA_MEM_FORCE_PU : 1; /*!< Set this bit to force power up rsa internal memory */ - __IOM uint32_t RSA_MEM_PD : 1; /*!< Set this bit to force power down rsa internal memory. */ - uint32_t : 29; - } bit; - } RSA_PD_CTRL; - - union { - __IOM uint32_t reg; /*!< ecc pd ctrl register */ - - struct { - __IOM uint32_t ECC_MEM_FORCE_PD : 1; /*!< Set this bit to power down ecc internal memory. */ - __IOM uint32_t ECC_MEM_FORCE_PU : 1; /*!< Set this bit to force power up ecc internal memory */ - __IOM uint32_t ECC_MEM_PD : 1; /*!< Set this bit to force power down ecc internal memory. */ - uint32_t : 29; - } bit; - } ECC_PD_CTRL; - - union { - __IOM uint32_t reg; /*!< rng cfg register */ - - struct { - __IOM uint32_t RNG_SAMPLE_ENABLE : 1; /*!< enable rng sample chain */ - uint32_t : 15; - __IOM uint32_t RNG_CHAIN_CLK_DIV_NUM : 8; /*!< chain clk div num to pad for debug */ - __IM uint32_t RNG_SAMPLE_CNT : 8; /*!< debug rng sample cnt */ - } bit; - } RNG_CFG; - - union { - __IOM uint32_t reg; /*!< ecc pd ctrl register */ - - struct { - __IOM uint32_t UART_MEM_FORCE_PD : 1; /*!< Set this bit to power down hp uart internal memory. */ - __IOM uint32_t UART_MEM_FORCE_PU : 1; /*!< Set this bit to force power up hp uart internal memory */ - uint32_t : 30; - } bit; - } UART_PD_CTRL; - - union { - __IOM uint32_t reg; /*!< hp peri mem clk force on regpster */ - - struct { - __IOM uint32_t RMT_MEM_CLK_FORCE_ON : 1; /*!< Set this bit to force on mem clk in rmt */ - __IOM uint32_t BITSCRAMBLER_TX_MEM_CLK_FORCE_ON : 1;/*!< Set this bit to force on tx mem clk in bitscrambler */ - __IOM uint32_t BITSCRAMBLER_RX_MEM_CLK_FORCE_ON : 1;/*!< Set this bit to force on rx mem clk in bitscrambler */ - __IOM uint32_t GDMA_MEM_CLK_FORCE_ON : 1; /*!< Set this bit to force on mem clk in gdma */ - uint32_t : 28; - } bit; - } PERI_MEM_CLK_FORCE_ON; -} HP_SYS_Type; /*!< Size = 484 (0x1e4) */ - - - -/* =========================================================================================================================== */ -/* ================ HP_SYS_CLKRST ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief HP_SYS_CLKRST Peripheral (HP_SYS_CLKRST) - */ - -typedef struct { /*!< HP_SYS_CLKRST Structure */ - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_CLK_EN : 1; /*!< Reserved */ - uint32_t : 31; - } bit; - } CLK_EN0; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_CPUICM_DELAY_NUM : 4; /*!< Reserved */ - __OM uint32_t REG_SOC_CLK_DIV_UPDATE : 1;/*!< Reserved */ - __IOM uint32_t REG_CPU_CLK_DIV_NUM : 8; /*!< Reserved */ - __IOM uint32_t REG_CPU_CLK_DIV_NUMERATOR : 8;/*!< Reserved */ - __IOM uint32_t REG_CPU_CLK_DIV_DENOMINATOR : 8;/*!< Reserved */ - uint32_t : 3; - } bit; - } ROOT_CLK_CTRL0; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_MEM_CLK_DIV_NUM : 8; /*!< Reserved */ - __IOM uint32_t REG_MEM_CLK_DIV_NUMERATOR : 8;/*!< Reserved */ - __IOM uint32_t REG_MEM_CLK_DIV_DENOMINATOR : 8;/*!< Reserved */ - __IOM uint32_t REG_SYS_CLK_DIV_NUM : 8; /*!< Reserved */ - } bit; - } ROOT_CLK_CTRL1; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_SYS_CLK_DIV_NUMERATOR : 8;/*!< Reserved */ - __IOM uint32_t REG_SYS_CLK_DIV_DENOMINATOR : 8;/*!< Reserved */ - __IOM uint32_t REG_APB_CLK_DIV_NUM : 8; /*!< Reserved */ - __IOM uint32_t REG_APB_CLK_DIV_NUMERATOR : 8;/*!< Reserved */ - } bit; - } ROOT_CLK_CTRL2; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_APB_CLK_DIV_DENOMINATOR : 8;/*!< Reserved */ - uint32_t : 24; - } bit; - } ROOT_CLK_CTRL3; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_CORE0_CLIC_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_CORE1_CLIC_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_MISC_CPU_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_CORE0_CPU_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_CORE1_CPU_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_TCM_CPU_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_BUSMON_CPU_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_L1CACHE_CPU_CLK_EN : 1;/*!< Reserved */ - __IOM uint32_t REG_L1CACHE_D_CPU_CLK_EN : 1;/*!< Reserved */ - __IOM uint32_t REG_L1CACHE_I0_CPU_CLK_EN : 1;/*!< Reserved */ - __IOM uint32_t REG_L1CACHE_I1_CPU_CLK_EN : 1;/*!< Reserved */ - __IOM uint32_t REG_TRACE_CPU_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_ICM_CPU_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_GDMA_CPU_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_VPU_CPU_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_L1CACHE_MEM_CLK_EN : 1;/*!< Reserved */ - __IOM uint32_t REG_L1CACHE_D_MEM_CLK_EN : 1;/*!< Reserved */ - __IOM uint32_t REG_L1CACHE_I0_MEM_CLK_EN : 1;/*!< Reserved */ - __IOM uint32_t REG_L1CACHE_I1_MEM_CLK_EN : 1;/*!< Reserved */ - __IOM uint32_t REG_L2CACHE_MEM_CLK_EN : 1;/*!< Reserved */ - __IOM uint32_t REG_L2MEM_MEM_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_L2MEMMON_MEM_CLK_EN : 1;/*!< Reserved */ - __IOM uint32_t REG_ICM_MEM_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_MISC_SYS_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_TRACE_SYS_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_L2CACHE_SYS_CLK_EN : 1;/*!< Reserved */ - __IOM uint32_t REG_L2MEM_SYS_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_L2MEMMON_SYS_CLK_EN : 1;/*!< Reserved */ - __IOM uint32_t REG_TCMMON_SYS_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_ICM_SYS_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_FLASH_SYS_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_PSRAM_SYS_CLK_EN : 1; /*!< Reserved */ - } bit; - } SOC_CLK_CTRL0; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_GPSPI2_SYS_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_GPSPI3_SYS_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_REGDMA_SYS_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_AHB_PDMA_SYS_CLK_EN : 1;/*!< Reserved */ - __IOM uint32_t REG_AXI_PDMA_SYS_CLK_EN : 1;/*!< Reserved */ - __IOM uint32_t REG_GDMA_SYS_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_DMA2D_SYS_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_VPU_SYS_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_JPEG_SYS_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_PPA_SYS_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_CSI_BRG_SYS_CLK_EN : 1;/*!< Reserved */ - __IOM uint32_t REG_CSI_HOST_SYS_CLK_EN : 1;/*!< Reserved */ - __IOM uint32_t REG_DSI_SYS_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_EMAC_SYS_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_SDMMC_SYS_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_USB_OTG11_SYS_CLK_EN : 1;/*!< Reserved */ - __IOM uint32_t REG_USB_OTG20_SYS_CLK_EN : 1;/*!< Reserved */ - __IOM uint32_t REG_UHCI_SYS_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_UART0_SYS_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_UART1_SYS_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_UART2_SYS_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_UART3_SYS_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_UART4_SYS_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_PARLIO_SYS_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_ETM_SYS_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_PVT_SYS_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_CRYPTO_SYS_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_KEY_MANAGER_SYS_CLK_EN : 1;/*!< Reserved */ - __IOM uint32_t REG_BITSRAMBLER_SYS_CLK_EN : 1;/*!< Reserved */ - __IOM uint32_t REG_BITSRAMBLER_RX_SYS_CLK_EN : 1;/*!< Reserved */ - __IOM uint32_t REG_BITSRAMBLER_TX_SYS_CLK_EN : 1;/*!< Reserved */ - __IOM uint32_t REG_H264_SYS_CLK_EN : 1; /*!< Reserved */ - } bit; - } SOC_CLK_CTRL1; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_RMT_SYS_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_HP_CLKRST_APB_CLK_EN : 1;/*!< Reserved */ - __IOM uint32_t REG_SYSREG_APB_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_ICM_APB_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_INTRMTX_APB_CLK_EN : 1;/*!< Reserved */ - __IOM uint32_t REG_ADC_APB_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_UHCI_APB_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_UART0_APB_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_UART1_APB_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_UART2_APB_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_UART3_APB_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_UART4_APB_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_I2C0_APB_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_I2C1_APB_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_I2S0_APB_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_I2S1_APB_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_I2S2_APB_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_I3C_MST_APB_CLK_EN : 1;/*!< Reserved */ - __IOM uint32_t REG_I3C_SLV_APB_CLK_EN : 1;/*!< Reserved */ - __IOM uint32_t REG_GPSPI2_APB_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_GPSPI3_APB_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_TIMERGRP0_APB_CLK_EN : 1;/*!< Reserved */ - __IOM uint32_t REG_TIMERGRP1_APB_CLK_EN : 1;/*!< Reserved */ - __IOM uint32_t REG_SYSTIMER_APB_CLK_EN : 1;/*!< Reserved */ - __IOM uint32_t REG_TWAI0_APB_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_TWAI1_APB_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_TWAI2_APB_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_MCPWM0_APB_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_MCPWM1_APB_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_USB_DEVICE_APB_CLK_EN : 1;/*!< Reserved */ - __IOM uint32_t REG_PCNT_APB_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_PARLIO_APB_CLK_EN : 1; /*!< Reserved */ - } bit; - } SOC_CLK_CTRL2; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_LEDC_APB_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_LCDCAM_APB_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_ETM_APB_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_IOMUX_APB_CLK_EN : 1; /*!< Reserved */ - uint32_t : 28; - } bit; - } SOC_CLK_CTRL3; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_REF_50M_CLK_DIV_NUM : 8;/*!< Reserved */ - __IOM uint32_t REG_REF_25M_CLK_DIV_NUM : 8;/*!< Reserved */ - __IOM uint32_t REG_REF_240M_CLK_DIV_NUM : 8;/*!< Reserved */ - __IOM uint32_t REG_REF_160M_CLK_DIV_NUM : 8;/*!< Reserved */ - } bit; - } REF_CLK_CTRL0; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_REF_120M_CLK_DIV_NUM : 8;/*!< Reserved */ - __IOM uint32_t REG_REF_80M_CLK_DIV_NUM : 8;/*!< Reserved */ - __IOM uint32_t REG_REF_20M_CLK_DIV_NUM : 8;/*!< Reserved */ - __IOM uint32_t REG_TM_400M_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_TM_200M_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_TM_100M_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_REF_50M_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_REF_25M_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_TM_480M_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_REF_240M_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_TM_240M_CLK_EN : 1; /*!< Reserved */ - } bit; - } REF_CLK_CTRL1; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_REF_160M_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_TM_160M_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_REF_120M_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_TM_120M_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_REF_80M_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_TM_80M_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_TM_60M_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_TM_48M_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_REF_20M_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_TM_20M_CLK_EN : 1; /*!< Reserved */ - uint32_t : 22; - } bit; - } REF_CLK_CTRL2; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_FLASH_CLK_SRC_SEL : 2; /*!< Reserved */ - __IOM uint32_t REG_FLASH_PLL_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_FLASH_CORE_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_FLASH_CORE_CLK_DIV_NUM : 8;/*!< Reserved */ - __IOM uint32_t REG_PSRAM_CLK_SRC_SEL : 2; /*!< Reserved */ - __IOM uint32_t REG_PSRAM_PLL_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_PSRAM_CORE_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_PSRAM_CORE_CLK_DIV_NUM : 8;/*!< Reserved */ - __IOM uint32_t REG_PAD_EMAC_REF_CLK_EN : 1;/*!< Reserved */ - __IOM uint32_t REG_EMAC_RMII_CLK_SRC_SEL : 2;/*!< Reserved */ - __IOM uint32_t REG_EMAC_RMII_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_EMAC_RX_CLK_SRC_SEL : 1;/*!< Reserved */ - __IOM uint32_t REG_EMAC_RX_CLK_EN : 1; /*!< Reserved */ - uint32_t : 2; - } bit; - } PERI_CLK_CTRL00; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_EMAC_RX_CLK_DIV_NUM : 8;/*!< Reserved */ - __IOM uint32_t REG_EMAC_TX_CLK_SRC_SEL : 1;/*!< Reserved */ - __IOM uint32_t REG_EMAC_TX_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_EMAC_TX_CLK_DIV_NUM : 8;/*!< Reserved */ - __IOM uint32_t REG_EMAC_PTP_REF_CLK_SRC_SEL : 1;/*!< Reserved */ - __IOM uint32_t REG_EMAC_PTP_REF_CLK_EN : 1;/*!< Reserved */ - __IOM uint32_t REG_EMAC_UNUSED0_CLK_EN : 1;/*!< Reserved */ - __IOM uint32_t REG_EMAC_UNUSED1_CLK_EN : 1;/*!< Reserved */ - __IOM uint32_t REG_SDIO_HS_MODE : 1; /*!< Reserved */ - __IOM uint32_t REG_SDIO_LS_CLK_SRC_SEL : 1;/*!< Reserved */ - __IOM uint32_t REG_SDIO_LS_CLK_EN : 1; /*!< Reserved */ - uint32_t : 7; - } bit; - } PERI_CLK_CTRL01; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_SDIO_LS_CLK_DIV_NUM : 8;/*!< Reserved */ - __OM uint32_t REG_SDIO_LS_CLK_EDGE_CFG_UPDATE : 1;/*!< Reserved */ - __IOM uint32_t REG_SDIO_LS_CLK_EDGE_L : 4;/*!< Reserved */ - __IOM uint32_t REG_SDIO_LS_CLK_EDGE_H : 4;/*!< Reserved */ - __IOM uint32_t REG_SDIO_LS_CLK_EDGE_N : 4;/*!< Reserved */ - __IOM uint32_t REG_SDIO_LS_SLF_CLK_EDGE_SEL : 2;/*!< Reserved */ - __IOM uint32_t REG_SDIO_LS_DRV_CLK_EDGE_SEL : 2;/*!< Reserved */ - __IOM uint32_t REG_SDIO_LS_SAM_CLK_EDGE_SEL : 2;/*!< Reserved */ - __IOM uint32_t REG_SDIO_LS_SLF_CLK_EN : 1;/*!< Reserved */ - __IOM uint32_t REG_SDIO_LS_DRV_CLK_EN : 1;/*!< Reserved */ - __IOM uint32_t REG_SDIO_LS_SAM_CLK_EN : 1;/*!< Reserved */ - __IOM uint32_t REG_MIPI_DSI_DPHY_CLK_SRC_SEL : 2;/*!< Reserved */ - } bit; - } PERI_CLK_CTRL02; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_MIPI_DSI_DPHY_CFG_CLK_EN : 1;/*!< Reserved */ - __IOM uint32_t REG_MIPI_DSI_DPHY_PLL_REFCLK_EN : 1;/*!< Reserved */ - __IOM uint32_t REG_MIPI_CSI_DPHY_CLK_SRC_SEL : 2;/*!< Reserved */ - __IOM uint32_t REG_MIPI_CSI_DPHY_CFG_CLK_EN : 1;/*!< Reserved */ - __IOM uint32_t REG_MIPI_DSI_DPICLK_SRC_SEL : 2;/*!< Reserved */ - __IOM uint32_t REG_MIPI_DSI_DPICLK_EN : 1;/*!< Reserved */ - __IOM uint32_t REG_MIPI_DSI_DPICLK_DIV_NUM : 8;/*!< Reserved */ - uint32_t : 16; - } bit; - } PERI_CLK_CTRL03; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_I2C0_CLK_SRC_SEL : 1; /*!< Reserved */ - __IOM uint32_t REG_I2C0_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_I2C0_CLK_DIV_NUM : 8; /*!< Reserved */ - __IOM uint32_t REG_I2C0_CLK_DIV_NUMERATOR : 8;/*!< Reserved */ - __IOM uint32_t REG_I2C0_CLK_DIV_DENOMINATOR : 8;/*!< Reserved */ - __IOM uint32_t REG_I2C1_CLK_SRC_SEL : 1; /*!< Reserved */ - __IOM uint32_t REG_I2C1_CLK_EN : 1; /*!< Reserved */ - uint32_t : 4; - } bit; - } PERI_CLK_CTRL10; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_I2C1_CLK_DIV_NUM : 8; /*!< Reserved */ - __IOM uint32_t REG_I2C1_CLK_DIV_NUMERATOR : 8;/*!< Reserved */ - __IOM uint32_t REG_I2C1_CLK_DIV_DENOMINATOR : 8;/*!< Reserved */ - __IOM uint32_t REG_I2S0_RX_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_I2S0_RX_CLK_SRC_SEL : 2;/*!< Reserved */ - uint32_t : 5; - } bit; - } PERI_CLK_CTRL11; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_I2S0_RX_DIV_N : 8; /*!< Reserved */ - __IOM uint32_t REG_I2S0_RX_DIV_X : 9; /*!< Reserved */ - __IOM uint32_t REG_I2S0_RX_DIV_Y : 9; /*!< Reserved */ - uint32_t : 6; - } bit; - } PERI_CLK_CTRL12; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_I2S0_RX_DIV_Z : 9; /*!< Reserved */ - __IOM uint32_t REG_I2S0_RX_DIV_YN1 : 1; /*!< Reserved */ - __IOM uint32_t REG_I2S0_TX_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_I2S0_TX_CLK_SRC_SEL : 2;/*!< Reserved */ - __IOM uint32_t REG_I2S0_TX_DIV_N : 8; /*!< Reserved */ - __IOM uint32_t REG_I2S0_TX_DIV_X : 9; /*!< Reserved */ - uint32_t : 2; - } bit; - } PERI_CLK_CTRL13; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_I2S0_TX_DIV_Y : 9; /*!< Reserved */ - __IOM uint32_t REG_I2S0_TX_DIV_Z : 9; /*!< Reserved */ - __IOM uint32_t REG_I2S0_TX_DIV_YN1 : 1; /*!< Reserved */ - __IOM uint32_t REG_I2S0_MST_CLK_SEL : 1; /*!< Reserved */ - __IOM uint32_t REG_I2S1_RX_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_I2S1_RX_CLK_SRC_SEL : 2;/*!< Reserved */ - __IOM uint32_t REG_I2S1_RX_DIV_N : 8; /*!< Reserved */ - uint32_t : 1; - } bit; - } PERI_CLK_CTRL14; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_I2S1_RX_DIV_X : 9; /*!< Reserved */ - __IOM uint32_t REG_I2S1_RX_DIV_Y : 9; /*!< Reserved */ - __IOM uint32_t REG_I2S1_RX_DIV_Z : 9; /*!< Reserved */ - __IOM uint32_t REG_I2S1_RX_DIV_YN1 : 1; /*!< Reserved */ - __IOM uint32_t REG_I2S1_TX_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_I2S1_TX_CLK_SRC_SEL : 2;/*!< Reserved */ - uint32_t : 1; - } bit; - } PERI_CLK_CTRL15; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_I2S1_TX_DIV_N : 8; /*!< Reserved */ - __IOM uint32_t REG_I2S1_TX_DIV_X : 9; /*!< Reserved */ - __IOM uint32_t REG_I2S1_TX_DIV_Y : 9; /*!< Reserved */ - uint32_t : 6; - } bit; - } PERI_CLK_CTRL16; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_I2S1_TX_DIV_Z : 9; /*!< Reserved */ - __IOM uint32_t REG_I2S1_TX_DIV_YN1 : 1; /*!< Reserved */ - __IOM uint32_t REG_I2S1_MST_CLK_SEL : 1; /*!< Reserved */ - __IOM uint32_t REG_I2S2_RX_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_I2S2_RX_CLK_SRC_SEL : 2;/*!< Reserved */ - __IOM uint32_t REG_I2S2_RX_DIV_N : 8; /*!< Reserved */ - __IOM uint32_t REG_I2S2_RX_DIV_X : 9; /*!< Reserved */ - uint32_t : 1; - } bit; - } PERI_CLK_CTRL17; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_I2S2_RX_DIV_Y : 9; /*!< Reserved */ - __IOM uint32_t REG_I2S2_RX_DIV_Z : 9; /*!< Reserved */ - __IOM uint32_t REG_I2S2_RX_DIV_YN1 : 1; /*!< Reserved */ - __IOM uint32_t REG_I2S2_TX_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_I2S2_TX_CLK_SRC_SEL : 2;/*!< Reserved */ - __IOM uint32_t REG_I2S2_TX_DIV_N : 8; /*!< Reserved */ - uint32_t : 2; - } bit; - } PERI_CLK_CTRL18; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_I2S2_TX_DIV_X : 9; /*!< Reserved */ - __IOM uint32_t REG_I2S2_TX_DIV_Y : 9; /*!< Reserved */ - __IOM uint32_t REG_I2S2_TX_DIV_Z : 9; /*!< Reserved */ - __IOM uint32_t REG_I2S2_TX_DIV_YN1 : 1; /*!< Reserved */ - __IOM uint32_t REG_I2S2_MST_CLK_SEL : 1; /*!< Reserved */ - __IOM uint32_t REG_LCD_CLK_SRC_SEL : 2; /*!< Reserved */ - __IOM uint32_t REG_LCD_CLK_EN : 1; /*!< Reserved */ - } bit; - } PERI_CLK_CTRL19; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_LCD_CLK_DIV_NUM : 8; /*!< Reserved */ - __IOM uint32_t REG_LCD_CLK_DIV_NUMERATOR : 8;/*!< Reserved */ - __IOM uint32_t REG_LCD_CLK_DIV_DENOMINATOR : 8;/*!< Reserved */ - __IOM uint32_t REG_UART0_CLK_SRC_SEL : 2; /*!< Reserved */ - __IOM uint32_t REG_UART0_CLK_EN : 1; /*!< Reserved */ - uint32_t : 5; - } bit; - } PERI_CLK_CTRL110; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_UART0_SCLK_DIV_NUM : 8;/*!< Reserved */ - __IOM uint32_t REG_UART0_SCLK_DIV_NUMERATOR : 8;/*!< Reserved */ - __IOM uint32_t REG_UART0_SCLK_DIV_DENOMINATOR : 8;/*!< Reserved */ - __IOM uint32_t REG_UART1_CLK_SRC_SEL : 2; /*!< Reserved */ - __IOM uint32_t REG_UART1_CLK_EN : 1; /*!< Reserved */ - uint32_t : 5; - } bit; - } PERI_CLK_CTRL111; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_UART1_SCLK_DIV_NUM : 8;/*!< Reserved */ - __IOM uint32_t REG_UART1_SCLK_DIV_NUMERATOR : 8;/*!< Reserved */ - __IOM uint32_t REG_UART1_SCLK_DIV_DENOMINATOR : 8;/*!< Reserved */ - __IOM uint32_t REG_UART2_CLK_SRC_SEL : 2; /*!< Reserved */ - __IOM uint32_t REG_UART2_CLK_EN : 1; /*!< Reserved */ - uint32_t : 5; - } bit; - } PERI_CLK_CTRL112; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_UART2_SCLK_DIV_NUM : 8;/*!< Reserved */ - __IOM uint32_t REG_UART2_SCLK_DIV_NUMERATOR : 8;/*!< Reserved */ - __IOM uint32_t REG_UART2_SCLK_DIV_DENOMINATOR : 8;/*!< Reserved */ - __IOM uint32_t REG_UART3_CLK_SRC_SEL : 2; /*!< Reserved */ - __IOM uint32_t REG_UART3_CLK_EN : 1; /*!< Reserved */ - uint32_t : 5; - } bit; - } PERI_CLK_CTRL113; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_UART3_SCLK_DIV_NUM : 8;/*!< Reserved */ - __IOM uint32_t REG_UART3_SCLK_DIV_NUMERATOR : 8;/*!< Reserved */ - __IOM uint32_t REG_UART3_SCLK_DIV_DENOMINATOR : 8;/*!< Reserved */ - __IOM uint32_t REG_UART4_CLK_SRC_SEL : 2; /*!< Reserved */ - __IOM uint32_t REG_UART4_CLK_EN : 1; /*!< Reserved */ - uint32_t : 5; - } bit; - } PERI_CLK_CTRL114; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_UART4_SCLK_DIV_NUM : 8;/*!< Reserved */ - __IOM uint32_t REG_UART4_SCLK_DIV_NUMERATOR : 8;/*!< Reserved */ - __IOM uint32_t REG_UART4_SCLK_DIV_DENOMINATOR : 8;/*!< Reserved */ - __IOM uint32_t REG_TWAI0_CLK_SRC_SEL : 1; /*!< Reserved */ - __IOM uint32_t REG_TWAI0_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_TWAI1_CLK_SRC_SEL : 1; /*!< Reserved */ - __IOM uint32_t REG_TWAI1_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_TWAI2_CLK_SRC_SEL : 1; /*!< Reserved */ - __IOM uint32_t REG_TWAI2_CLK_EN : 1; /*!< Reserved */ - uint32_t : 2; - } bit; - } PERI_CLK_CTRL115; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_GPSPI2_CLK_SRC_SEL : 3;/*!< Reserved */ - __IOM uint32_t REG_GPSPI2_HS_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_GPSPI2_HS_CLK_DIV_NUM : 8;/*!< Reserved */ - __IOM uint32_t REG_GPSPI2_MST_CLK_DIV_NUM : 8;/*!< Reserved */ - __IOM uint32_t REG_GPSPI2_MST_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_GPSPI3_CLK_SRC_SEL : 3;/*!< Reserved */ - __IOM uint32_t REG_GPSPI3_HS_CLK_EN : 1; /*!< Reserved */ - uint32_t : 7; - } bit; - } PERI_CLK_CTRL116; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_GPSPI3_HS_CLK_DIV_NUM : 8;/*!< Reserved */ - __IOM uint32_t REG_GPSPI3_MST_CLK_DIV_NUM : 8;/*!< Reserved */ - __IOM uint32_t REG_GPSPI3_MST_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_PARLIO_RX_CLK_SRC_SEL : 2;/*!< Reserved */ - __IOM uint32_t REG_PARLIO_RX_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_PARLIO_RX_CLK_DIV_NUM : 8;/*!< Reserved */ - uint32_t : 4; - } bit; - } PERI_CLK_CTRL117; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_PARLIO_RX_CLK_DIV_NUMERATOR : 8;/*!< Reserved */ - __IOM uint32_t REG_PARLIO_RX_CLK_DIV_DENOMINATOR : 8;/*!< Reserved */ - __IOM uint32_t REG_PARLIO_TX_CLK_SRC_SEL : 2;/*!< Reserved */ - __IOM uint32_t REG_PARLIO_TX_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_PARLIO_TX_CLK_DIV_NUM : 8;/*!< Reserved */ - uint32_t : 5; - } bit; - } PERI_CLK_CTRL118; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_PARLIO_TX_CLK_DIV_NUMERATOR : 8;/*!< Reserved */ - __IOM uint32_t REG_PARLIO_TX_CLK_DIV_DENOMINATOR : 8;/*!< Reserved */ - __IOM uint32_t REG_I3C_MST_CLK_SRC_SEL : 2;/*!< Reserved */ - __IOM uint32_t REG_I3C_MST_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_I3C_MST_CLK_DIV_NUM : 8;/*!< Reserved */ - __IOM uint32_t REG_CAM_CLK_SRC_SEL : 2; /*!< Reserved */ - __IOM uint32_t REG_CAM_CLK_EN : 1; /*!< Reserved */ - uint32_t : 2; - } bit; - } PERI_CLK_CTRL119; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_CAM_CLK_DIV_NUM : 8; /*!< Reserved */ - __IOM uint32_t REG_CAM_CLK_DIV_NUMERATOR : 8;/*!< Reserved */ - __IOM uint32_t REG_CAM_CLK_DIV_DENOMINATOR : 8;/*!< Reserved */ - uint32_t : 8; - } bit; - } PERI_CLK_CTRL120; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_MCPWM0_CLK_SRC_SEL : 2;/*!< Reserved */ - __IOM uint32_t REG_MCPWM0_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_MCPWM0_CLK_DIV_NUM : 8;/*!< Reserved */ - __IOM uint32_t REG_MCPWM1_CLK_SRC_SEL : 2;/*!< Reserved */ - __IOM uint32_t REG_MCPWM1_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_MCPWM1_CLK_DIV_NUM : 8;/*!< Reserved */ - __IOM uint32_t REG_TIMERGRP0_T0_SRC_SEL : 2;/*!< Reserved */ - __IOM uint32_t REG_TIMERGRP0_T0_CLK_EN : 1;/*!< Reserved */ - __IOM uint32_t REG_TIMERGRP0_T1_SRC_SEL : 2;/*!< Reserved */ - __IOM uint32_t REG_TIMERGRP0_T1_CLK_EN : 1;/*!< Reserved */ - __IOM uint32_t REG_TIMERGRP0_WDT_SRC_SEL : 2;/*!< Reserved */ - __IOM uint32_t REG_TIMERGRP0_WDT_CLK_EN : 1;/*!< Reserved */ - __IOM uint32_t REG_TIMERGRP0_TGRT_CLK_EN : 1;/*!< Reserved */ - } bit; - } PERI_CLK_CTRL20; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_TIMERGRP0_TGRT_CLK_SRC_SEL : 4;/*!< Reserved */ - __IOM uint32_t REG_TIMERGRP0_TGRT_CLK_DIV_NUM : 16;/*!< Reserved */ - __IOM uint32_t REG_TIMERGRP1_T0_SRC_SEL : 2;/*!< Reserved */ - __IOM uint32_t REG_TIMERGRP1_T0_CLK_EN : 1;/*!< Reserved */ - __IOM uint32_t REG_TIMERGRP1_T1_SRC_SEL : 2;/*!< Reserved */ - __IOM uint32_t REG_TIMERGRP1_T1_CLK_EN : 1;/*!< Reserved */ - __IOM uint32_t REG_TIMERGRP1_WDT_SRC_SEL : 2;/*!< Reserved */ - __IOM uint32_t REG_TIMERGRP1_WDT_CLK_EN : 1;/*!< Reserved */ - __IOM uint32_t REG_SYSTIMER_CLK_SRC_SEL : 1;/*!< Reserved */ - __IOM uint32_t REG_SYSTIMER_CLK_EN : 1; /*!< Reserved */ - uint32_t : 1; - } bit; - } PERI_CLK_CTRL21; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_LEDC_CLK_SRC_SEL : 2; /*!< Reserved */ - __IOM uint32_t REG_LEDC_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_RMT_CLK_SRC_SEL : 2; /*!< Reserved */ - __IOM uint32_t REG_RMT_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_RMT_CLK_DIV_NUM : 8; /*!< Reserved */ - __IOM uint32_t REG_RMT_CLK_DIV_NUMERATOR : 8;/*!< Reserved */ - __IOM uint32_t REG_RMT_CLK_DIV_DENOMINATOR : 8;/*!< Reserved */ - __IOM uint32_t REG_ADC_CLK_SRC_SEL : 2; /*!< Reserved */ - } bit; - } PERI_CLK_CTRL22; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_ADC_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_ADC_CLK_DIV_NUM : 8; /*!< Reserved */ - __IOM uint32_t REG_ADC_CLK_DIV_NUMERATOR : 8;/*!< Reserved */ - __IOM uint32_t REG_ADC_CLK_DIV_DENOMINATOR : 8;/*!< Reserved */ - uint32_t : 7; - } bit; - } PERI_CLK_CTRL23; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_ADC_SAR1_CLK_DIV_NUM : 8;/*!< Reserved */ - __IOM uint32_t REG_ADC_SAR2_CLK_DIV_NUM : 8;/*!< Reserved */ - __IOM uint32_t REG_PVT_CLK_DIV_NUM : 8; /*!< Reserved */ - __IOM uint32_t REG_PVT_CLK_EN : 1; /*!< Reserved */ - uint32_t : 7; - } bit; - } PERI_CLK_CTRL24; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_PVT_PERI_GROUP_CLK_DIV_NUM : 8;/*!< Reserved */ - __IOM uint32_t REG_PVT_PERI_GROUP1_CLK_EN : 1;/*!< Reserved */ - __IOM uint32_t REG_PVT_PERI_GROUP2_CLK_EN : 1;/*!< Reserved */ - __IOM uint32_t REG_PVT_PERI_GROUP3_CLK_EN : 1;/*!< Reserved */ - __IOM uint32_t REG_PVT_PERI_GROUP4_CLK_EN : 1;/*!< Reserved */ - __IOM uint32_t REG_CRYPTO_CLK_SRC_SEL : 2;/*!< Reserved */ - __IOM uint32_t REG_CRYPTO_AES_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_CRYPTO_DS_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_CRYPTO_ECC_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_CRYPTO_HMAC_CLK_EN : 1;/*!< Reserved */ - __IOM uint32_t REG_CRYPTO_RSA_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_CRYPTO_SEC_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_CRYPTO_SHA_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_CRYPTO_ECDSA_CLK_EN : 1;/*!< Reserved */ - __IOM uint32_t REG_CRYPTO_KM_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_ISP_CLK_SRC_SEL : 2; /*!< Reserved */ - __IOM uint32_t REG_ISP_CLK_EN : 1; /*!< Reserved */ - uint32_t : 6; - } bit; - } PERI_CLK_CTRL25; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_ISP_CLK_DIV_NUM : 8; /*!< Reserved */ - __IOM uint32_t REG_IOMUX_CLK_SRC_SEL : 1; /*!< Reserved */ - __IOM uint32_t REG_IOMUX_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_IOMUX_CLK_DIV_NUM : 8; /*!< Reserved */ - __IOM uint32_t REG_H264_CLK_SRC_SEL : 1; /*!< Reserved */ - __IOM uint32_t REG_H264_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_H264_CLK_DIV_NUM : 8; /*!< Reserved */ - __IOM uint32_t REG_PADBIST_RX_CLK_SRC_SEL : 1;/*!< Reserved */ - __IOM uint32_t REG_PADBIST_RX_CLK_EN : 1; /*!< Reserved */ - uint32_t : 2; - } bit; - } PERI_CLK_CTRL26; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_PADBIST_RX_CLK_DIV_NUM : 8;/*!< Reserved */ - __IOM uint32_t REG_PADBIST_TX_CLK_SRC_SEL : 1;/*!< Reserved */ - __IOM uint32_t REG_PADBIST_TX_CLK_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_PADBIST_TX_CLK_DIV_NUM : 8;/*!< Reserved */ - uint32_t : 14; - } bit; - } PERI_CLK_CTRL27; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_CPUICM_GATED_CLK_FORCE_ON : 1;/*!< Reserved */ - __IOM uint32_t REG_TCM_CPU_CLK_FORCE_ON : 1;/*!< Reserved */ - __IOM uint32_t REG_BUSMON_CPU_CLK_FORCE_ON : 1;/*!< Reserved */ - __IOM uint32_t REG_L1CACHE_CPU_CLK_FORCE_ON : 1;/*!< Reserved */ - __IOM uint32_t REG_L1CACHE_D_CPU_CLK_FORCE_ON : 1;/*!< Reserved */ - __IOM uint32_t REG_L1CACHE_I0_CPU_CLK_FORCE_ON : 1;/*!< Reserved */ - __IOM uint32_t REG_L1CACHE_I1_CPU_CLK_FORCE_ON : 1;/*!< Reserved */ - __IOM uint32_t REG_TRACE_CPU_CLK_FORCE_ON : 1;/*!< Reserved */ - __IOM uint32_t REG_TRACE_SYS_CLK_FORCE_ON : 1;/*!< Reserved */ - __IOM uint32_t REG_L1CACHE_MEM_CLK_FORCE_ON : 1;/*!< Reserved */ - __IOM uint32_t REG_L1CACHE_D_MEM_CLK_FORCE_ON : 1;/*!< Reserved */ - __IOM uint32_t REG_L1CACHE_I0_MEM_CLK_FORCE_ON : 1;/*!< Reserved */ - __IOM uint32_t REG_L1CACHE_I1_MEM_CLK_FORCE_ON : 1;/*!< Reserved */ - __IOM uint32_t REG_L2CACHE_MEM_CLK_FORCE_ON : 1;/*!< Reserved */ - __IOM uint32_t REG_L2MEM_MEM_CLK_FORCE_ON : 1;/*!< Reserved */ - __IOM uint32_t REG_SAR1_CLK_FORCE_ON : 1; /*!< Reserved */ - __IOM uint32_t REG_SAR2_CLK_FORCE_ON : 1; /*!< Reserved */ - __IOM uint32_t REG_GMAC_TX_CLK_FORCE_ON : 1;/*!< Reserved */ - uint32_t : 14; - } bit; - } CLK_FORCE_ON_CTRL0; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_SEC_DPA_LEVEL : 2; /*!< Reserved */ - __IOM uint32_t REG_SEC_DPA_CFG_SEL : 1; /*!< Reserved */ - uint32_t : 29; - } bit; - } DPA_CTRL0; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IM uint32_t REG_PLLA_CAL_END : 1; /*!< Reserved */ - __IOM uint32_t REG_PLLA_CAL_STOP : 1; /*!< Reserved */ - __IM uint32_t REG_CPU_PLL_CAL_END : 1; /*!< Reserved */ - __IOM uint32_t REG_CPU_PLL_CAL_STOP : 1; /*!< Reserved */ - __IM uint32_t REG_SDIO_PLL_CAL_END : 1; /*!< Reserved */ - __IOM uint32_t REG_SDIO_PLL_CAL_STOP : 1; /*!< Reserved */ - __IM uint32_t REG_SYS_PLL_CAL_END : 1; /*!< Reserved */ - __IOM uint32_t REG_SYS_PLL_CAL_STOP : 1; /*!< Reserved */ - __IM uint32_t REG_MSPI_CAL_END : 1; /*!< Reserved */ - __IOM uint32_t REG_MSPI_CAL_STOP : 1; /*!< Reserved */ - uint32_t : 22; - } bit; - } ANA_PLL_CTRL0; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_RST_EN_CORECTRL : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_PVT_TOP : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_PVT_PERI_GROUP1 : 1;/*!< Reserved */ - __IOM uint32_t REG_RST_EN_PVT_PERI_GROUP2 : 1;/*!< Reserved */ - __IOM uint32_t REG_RST_EN_PVT_PERI_GROUP3 : 1;/*!< Reserved */ - __IOM uint32_t REG_RST_EN_PVT_PERI_GROUP4 : 1;/*!< Reserved */ - __IOM uint32_t REG_RST_EN_REGDMA : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_CORE0_GLOBAL : 1;/*!< Reserved */ - __IOM uint32_t REG_RST_EN_CORE1_GLOBAL : 1;/*!< Reserved */ - __IOM uint32_t REG_RST_EN_CORETRACE0 : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_CORETRACE1 : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_HP_TCM : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_HP_CACHE : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_L1_I0_CACHE : 1;/*!< Reserved */ - __IOM uint32_t REG_RST_EN_L1_I1_CACHE : 1;/*!< Reserved */ - __IOM uint32_t REG_RST_EN_L1_D_CACHE : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_L2_CACHE : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_L2_MEM : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_L2MEMMON : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_TCMMON : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_PVT_APB : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_GDMA : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_MSPI_AXI : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_DUAL_MSPI_AXI : 1;/*!< Reserved */ - __IOM uint32_t REG_RST_EN_MSPI_APB : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_DUAL_MSPI_APB : 1;/*!< Reserved */ - __IOM uint32_t REG_RST_EN_DSI_BRG : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_CSI_HOST : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_CSI_BRG : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_ISP : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_JPEG : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_DMA2D : 1; /*!< Reserved */ - } bit; - } HP_RST_EN0; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_RST_EN_PPA : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_AHB_PDMA : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_AXI_PDMA : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_IOMUX : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_PADBIST : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_STIMER : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_TIMERGRP0 : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_TIMERGRP1 : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_UART0_CORE : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_UART1_CORE : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_UART2_CORE : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_UART3_CORE : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_UART4_CORE : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_UART0_APB : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_UART1_APB : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_UART2_APB : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_UART3_APB : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_UART4_APB : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_UHCI : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_I3CMST : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_I3CSLV : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_I2C1 : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_I2C0 : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_RMT : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_PWM0 : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_PWM1 : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_CAN0 : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_CAN1 : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_CAN2 : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_LEDC : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_PCNT : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_ETM : 1; /*!< Reserved */ - } bit; - } HP_RST_EN1; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_RST_EN_INTRMTX : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_PARLIO : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_PARLIO_RX : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_PARLIO_TX : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_I2S0_APB : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_I2S1_APB : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_I2S2_APB : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_SPI2 : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_SPI3 : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_LCDCAM : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_ADC : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_BITSRAMBLER : 1;/*!< Reserved */ - __IOM uint32_t REG_RST_EN_BITSRAMBLER_RX : 1;/*!< Reserved */ - __IOM uint32_t REG_RST_EN_BITSRAMBLER_TX : 1;/*!< Reserved */ - __IOM uint32_t REG_RST_EN_CRYPTO : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_SEC : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_AES : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_DS : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_SHA : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_HMAC : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_ECDSA : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_RSA : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_ECC : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_KM : 1; /*!< Reserved */ - __IOM uint32_t REG_RST_EN_H264 : 1; /*!< Reserved */ - uint32_t : 7; - } bit; - } HP_RST_EN2; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_FORCE_NORST_CORE0 : 1; /*!< Reserved */ - __IOM uint32_t REG_FORCE_NORST_CORE1 : 1; /*!< Reserved */ - __IOM uint32_t REG_FORCE_NORST_CORETRACE0 : 1;/*!< Reserved */ - __IOM uint32_t REG_FORCE_NORST_CORETRACE1 : 1;/*!< Reserved */ - __IOM uint32_t REG_FORCE_NORST_L2MEMMON : 1;/*!< Reserved */ - __IOM uint32_t REG_FORCE_NORST_TCMMON : 1;/*!< Reserved */ - __IOM uint32_t REG_FORCE_NORST_GDMA : 1; /*!< Reserved */ - __IOM uint32_t REG_FORCE_NORST_MSPI_AXI : 1;/*!< Reserved */ - __IOM uint32_t REG_FORCE_NORST_DUAL_MSPI_AXI : 1;/*!< Reserved */ - __IOM uint32_t REG_FORCE_NORST_MSPI_APB : 1;/*!< Reserved */ - __IOM uint32_t REG_FORCE_NORST_DUAL_MSPI_APB : 1;/*!< Reserved */ - __IOM uint32_t REG_FORCE_NORST_DSI_BRG : 1;/*!< Reserved */ - __IOM uint32_t REG_FORCE_NORST_CSI_HOST : 1;/*!< Reserved */ - __IOM uint32_t REG_FORCE_NORST_CSI_BRG : 1;/*!< Reserved */ - __IOM uint32_t REG_FORCE_NORST_ISP : 1; /*!< Reserved */ - __IOM uint32_t REG_FORCE_NORST_JPEG : 1; /*!< Reserved */ - __IOM uint32_t REG_FORCE_NORST_DMA2D : 1; /*!< Reserved */ - __IOM uint32_t REG_FORCE_NORST_PPA : 1; /*!< Reserved */ - __IOM uint32_t REG_FORCE_NORST_AHB_PDMA : 1;/*!< Reserved */ - __IOM uint32_t REG_FORCE_NORST_AXI_PDMA : 1;/*!< Reserved */ - __IOM uint32_t REG_FORCE_NORST_IOMUX : 1; /*!< Reserved */ - __IOM uint32_t REG_FORCE_NORST_PADBIST : 1;/*!< Reserved */ - __IOM uint32_t REG_FORCE_NORST_STIMER : 1;/*!< Reserved */ - __IOM uint32_t REG_FORCE_NORST_TIMERGRP0 : 1;/*!< Reserved */ - __IOM uint32_t REG_FORCE_NORST_TIMERGRP1 : 1;/*!< Reserved */ - __IOM uint32_t REG_FORCE_NORST_UART0 : 1; /*!< Reserved */ - __IOM uint32_t REG_FORCE_NORST_UART1 : 1; /*!< Reserved */ - __IOM uint32_t REG_FORCE_NORST_UART2 : 1; /*!< Reserved */ - __IOM uint32_t REG_FORCE_NORST_UART3 : 1; /*!< Reserved */ - __IOM uint32_t REG_FORCE_NORST_UART4 : 1; /*!< Reserved */ - __IOM uint32_t REG_FORCE_NORST_UHCI : 1; /*!< Reserved */ - __IOM uint32_t REG_FORCE_NORST_I3CMST : 1;/*!< Reserved */ - } bit; - } HP_FORCE_NORST0; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_FORCE_NORST_I3CSLV : 1;/*!< Reserved */ - __IOM uint32_t REG_FORCE_NORST_I2C1 : 1; /*!< Reserved */ - __IOM uint32_t REG_FORCE_NORST_I2C0 : 1; /*!< Reserved */ - __IOM uint32_t REG_FORCE_NORST_RMT : 1; /*!< Reserved */ - __IOM uint32_t REG_FORCE_NORST_PWM0 : 1; /*!< Reserved */ - __IOM uint32_t REG_FORCE_NORST_PWM1 : 1; /*!< Reserved */ - __IOM uint32_t REG_FORCE_NORST_CAN0 : 1; /*!< Reserved */ - __IOM uint32_t REG_FORCE_NORST_CAN1 : 1; /*!< Reserved */ - __IOM uint32_t REG_FORCE_NORST_CAN2 : 1; /*!< Reserved */ - __IOM uint32_t REG_FORCE_NORST_LEDC : 1; /*!< Reserved */ - __IOM uint32_t REG_FORCE_NORST_PCNT : 1; /*!< Reserved */ - __IOM uint32_t REG_FORCE_NORST_ETM : 1; /*!< Reserved */ - __IOM uint32_t REG_FORCE_NORST_INTRMTX : 1;/*!< Reserved */ - __IOM uint32_t REG_FORCE_NORST_PARLIO : 1;/*!< Reserved */ - __IOM uint32_t REG_FORCE_NORST_PARLIO_RX : 1;/*!< Reserved */ - __IOM uint32_t REG_FORCE_NORST_PARLIO_TX : 1;/*!< Reserved */ - __IOM uint32_t REG_FORCE_NORST_I2S0 : 1; /*!< Reserved */ - __IOM uint32_t REG_FORCE_NORST_I2S1 : 1; /*!< Reserved */ - __IOM uint32_t REG_FORCE_NORST_I2S2 : 1; /*!< Reserved */ - __IOM uint32_t REG_FORCE_NORST_SPI2 : 1; /*!< Reserved */ - __IOM uint32_t REG_FORCE_NORST_SPI3 : 1; /*!< Reserved */ - __IOM uint32_t REG_FORCE_NORST_LCDCAM : 1;/*!< Reserved */ - __IOM uint32_t REG_FORCE_NORST_ADC : 1; /*!< Reserved */ - __IOM uint32_t REG_FORCE_NORST_BITSRAMBLER : 1;/*!< Reserved */ - __IOM uint32_t REG_FORCE_NORST_BITSRAMBLER_RX : 1;/*!< Reserved */ - __IOM uint32_t REG_FORCE_NORST_BITSRAMBLER_TX : 1;/*!< Reserved */ - __IOM uint32_t REG_FORCE_NORST_H264 : 1; /*!< Reserved */ - uint32_t : 5; - } bit; - } HP_FORCE_NORST1; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_HPCORE0_STALL_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_HPCORE0_STALL_WAIT_NUM : 8;/*!< Reserved */ - __IOM uint32_t REG_WDT_HPCORE0_RST_LEN : 8;/*!< Reserved */ - uint32_t : 15; - } bit; - } HPWDT_CORE0_RST_CTRL0; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_HPCORE1_STALL_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_HPCORE1_STALL_WAIT_NUM : 8;/*!< Reserved */ - __IOM uint32_t REG_WDT_HPCORE1_RST_LEN : 8;/*!< Reserved */ - uint32_t : 15; - } bit; - } HPWDT_CORE1_RST_CTRL0; - - union { - __IOM uint32_t reg; /*!< CPU Source Frequency */ - - struct { - __IM uint32_t REG_CPU_SRC_FREQ : 32; /*!< cpu source clock frequency, step by 0.25MHz */ - } bit; - } CPU_SRC_FREQ0; - - union { - __IOM uint32_t reg; /*!< CPU Clock Status */ - - struct { - __IM uint32_t REG_ASIC_OR_FPGA : 1; /*!< 0: ASIC mode, 1: FPGA mode */ - __IM uint32_t REG_CPU_DIV_EFFECT : 1; /*!< 0: Divider bypass, 1: Divider takes effect */ - __IM uint32_t REG_CPU_SRC_IS_CPLL : 1; /*!< 0: CPU source isn't cpll_400m, 1: CPU Source is cll_400m */ - __IM uint32_t REG_CPU_DIV_NUM_CUR : 8; /*!< cpu current div number */ - __IM uint32_t REG_CPU_DIV_NUMERATOR_CUR : 8;/*!< cpu current div numerator */ - __IM uint32_t REG_CPU_DIV_DENOMINATOR_CUR : 8;/*!< cpu current div denominator */ - uint32_t : 5; - } bit; - } CPU_CLK_STATUS0; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_DBG_CH0_SEL : 8; /*!< Reserved */ - __IOM uint32_t REG_DBG_CH1_SEL : 8; /*!< Reserved */ - __IOM uint32_t REG_DBG_CH2_SEL : 8; /*!< Reserved */ - __IOM uint32_t REG_DBG_CH0_DIV_NUM : 8; /*!< Reserved */ - } bit; - } DBG_CLK_CTRL0; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_DBG_CH1_DIV_NUM : 8; /*!< Reserved */ - __IOM uint32_t REG_DBG_CH2_DIV_NUM : 8; /*!< Reserved */ - __IOM uint32_t REG_DBG_CH0_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_DBG_CH1_EN : 1; /*!< Reserved */ - __IOM uint32_t REG_DBG_CH2_EN : 1; /*!< Reserved */ - uint32_t : 13; - } bit; - } DBG_CLK_CTRL1; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_HPCORE0_WDT_RESET_SOURCE_SEL : 1;/*!< 1'b0: use wdt0 to reset hpcore0, 1'b1: use wdt1 to reset hpcore0 */ - __IOM uint32_t REG_HPCORE1_WDT_RESET_SOURCE_SEL : 1;/*!< 1'b0: use wdt0 to reset hpcore1, 1'b1: use wdt1 to reset hpcore1 */ - uint32_t : 30; - } bit; - } HPCORE_WDT_RESET_SOURCE0; -} HP_SYS_CLKRST_Type; /*!< Size = 240 (0xf0) */ - - - -/* =========================================================================================================================== */ -/* ================ LP_HUK ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief LP_HUK Peripheral (LP_HUK) - */ - -typedef struct { /*!< LP_HUK Structure */ - __IM uint32_t RESERVED; - - union { - __IOM uint32_t reg; /*!< HUK Generator clock gate control register */ - - struct { - __IOM uint32_t EN : 1; /*!< Write 1 to force on register clock gate. */ - __IOM uint32_t MEM_CG_FORCE_ON : 1; /*!< Write 1 to force on memory clock gate. */ - uint32_t : 30; - } bit; - } CLK; - - union { - __IOM uint32_t reg; /*!< HUK Generator interrupt raw register, valid in level. */ - - struct { - __IM uint32_t PREP_DONE_INT_RAW : 1; /*!< The raw interrupt status bit for the huk_prep_done_int interrupt */ - __IM uint32_t PROC_DONE_INT_RAW : 1; /*!< The raw interrupt status bit for the huk_proc_done_int interrupt */ - __IM uint32_t POST_DONE_INT_RAW : 1; /*!< The raw interrupt status bit for the huk_post_done_int interrupt */ - uint32_t : 29; - } bit; - } INT_RAW; - - union { - __IOM uint32_t reg; /*!< HUK Generator interrupt status register. */ - - struct { - __IM uint32_t PREP_DONE_INT_ST : 1; /*!< The masked interrupt status bit for the huk_prep_done_int interrupt */ - __IM uint32_t PROC_DONE_INT_ST : 1; /*!< The masked interrupt status bit for the huk_proc_done_int interrupt */ - __IM uint32_t POST_DONE_INT_ST : 1; /*!< The masked interrupt status bit for the huk_post_done_int interrupt */ - uint32_t : 29; - } bit; - } INT_ST; - - union { - __IOM uint32_t reg; /*!< HUK Generator interrupt enable register. */ - - struct { - __IOM uint32_t PREP_DONE_INT_ENA : 1; /*!< The interrupt enable bit for the huk_prep_done_int interrupt */ - __IOM uint32_t PROC_DONE_INT_ENA : 1; /*!< The interrupt enable bit for the huk_proc_done_int interrupt */ - __IOM uint32_t POST_DONE_INT_ENA : 1; /*!< The interrupt enable bit for the huk_post_done_int interrupt */ - uint32_t : 29; - } bit; - } INT_ENA; - - union { - __IOM uint32_t reg; /*!< HUK Generator interrupt clear register. */ - - struct { - __OM uint32_t PREP_DONE_INT_CLR : 1; /*!< Set this bit to clear the huk_prep_done_int interrupt */ - __OM uint32_t PROC_DONE_INT_CLR : 1; /*!< Set this bit to clear the huk_proc_done_int interrupt */ - __OM uint32_t POST_DONE_INT_CLR : 1; /*!< Set this bit to clear the huk_post_done_int interrupt */ - uint32_t : 29; - } bit; - } INT_CLR; - __IM uint32_t RESERVED1[2]; - - union { - __IOM uint32_t reg; /*!< HUK Generator configuration register */ - - struct { - __IOM uint32_t MODE : 1; /*!< Set this field to choose the huk process. 1: process huk generate - mode. 0: process huk recovery mode. */ - uint32_t : 31; - } bit; - } CONF; - - union { - __IOM uint32_t reg; /*!< HUK Generator control register */ - - struct { - __OM uint32_t START : 1; /*!< Write 1 to continue HUK Generator operation at LOAD/GAIN state. */ - __OM uint32_t CONTINUE : 1; /*!< Write 1 to start HUK Generator at IDLE state. */ - uint32_t : 30; - } bit; - } START; - - union { - __IOM uint32_t reg; /*!< HUK Generator state register */ - - struct { - __IM uint32_t STATE : 2; /*!< The state of HUK Generator. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY. */ - uint32_t : 30; - } bit; - } STATE; - __IM uint32_t RESERVED2[2]; - - union { - __IOM uint32_t reg; /*!< HUK Generator HUK status register */ - - struct { - __IM uint32_t STATUS : 2; /*!< The HUK generation status. 0: HUK is not generated. 1: HUK is - generated and valid. 2: HUK is generated but invalid. 3: - reserved. */ - __IM uint32_t RISK_LEVEL : 3; /*!< The risk level of HUK. 0-6: the higher the risk level is, the - more error bits there are in the PUF SRAM. 7: Error Level, - HUK is invalid. */ - uint32_t : 27; - } bit; - } STATUS; - __IM uint32_t RESERVED3[49]; - - union { - __IOM uint32_t reg; /*!< Version control register */ - - struct { - __IOM uint32_t DATE : 28; /*!< HUK Generator version control register. */ - uint32_t : 4; - } bit; - } DATE; - __IOM uint32_t INFO_MEM[96]; /*!< The memory that stores HUK info. */ -} LP_HUK_Type; /*!< Size = 640 (0x280) */ - - - -/* =========================================================================================================================== */ -/* ================ I2C0 ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief I2C (Inter-Integrated Circuit) Controller 0 (I2C0) - */ - -typedef struct { /*!< I2C0 Structure */ - - union { - __IOM uint32_t reg; /*!< Configures the low level width of the SCL Clock. */ - - struct { - __IOM uint32_t SCL_LOW_PERIOD : 9; /*!< Configures the low level width of the SCL Clock. Measurement - unit: i2c_sclk. */ - uint32_t : 23; - } bit; - } SCL_LOW_PERIOD; - - union { - __IOM uint32_t reg; /*!< Transmission setting */ - - struct { - __IOM uint32_t SDA_FORCE_OUT : 1; /*!< Configures the SDA output mode1: Direct output,0: Open drain - output. */ - __IOM uint32_t SCL_FORCE_OUT : 1; /*!< Configures the SCL output mode1: Direct output,0: Open drain - output. */ - __IOM uint32_t SAMPLE_SCL_LEVEL : 1; /*!< Configures the sample mode for SDA.1: Sample SDA data on the - SCL low level.0: Sample SDA data on the SCL high level. */ - __IOM uint32_t RX_FULL_ACK_LEVEL : 1; /*!< Configures the ACK value that needs to be sent by master when - the rx_fifo_cnt has reached the threshold. */ - __IOM uint32_t MS_MODE : 1; /*!< Configures the module as an I2C Master or Slave. 0: Slave1: - Master */ - __OM uint32_t TRANS_START : 1; /*!< Configures to start sending the data in txfifo for slave. 0: - No effect1: Start */ - __IOM uint32_t TX_LSB_FIRST : 1; /*!< Configures to control the sending order for data needing to - be sent. 1: send data from the least significant bit,0: - send data from the most significant bit. */ - __IOM uint32_t RX_LSB_FIRST : 1; /*!< Configures to control the storage order for received data.1: - receive data from the least significant bit0: receive data - from the most significant bit. */ - __IOM uint32_t CLK_EN : 1; /*!< Configures whether to gate clock signal for registers.0: Force - clock on for registers 1: Support clock only when registers - are read or written to by software. */ - __IOM uint32_t ARBITRATION_EN : 1; /*!< Configures to enable I2C bus arbitration detection.0: No effect1: - Enable */ - __OM uint32_t FSM_RST : 1; /*!< Configures to reset the SCL_FSM.0: No effect1: Reset */ - __OM uint32_t CONF_UPGATE : 1; /*!< Configures this bit for synchronization0: No effect1: Synchronize */ - __IOM uint32_t SLV_TX_AUTO_START_EN : 1; /*!< Configures to enable slave to send data automatically0: Disable1: - Enable */ - __IOM uint32_t ADDR_10BIT_RW_CHECK_EN : 1;/*!< Configures to check if the r/w bit of 10bit addressing consists - with I2C protocol.0: Not check1: Check */ - __IOM uint32_t ADDR_BROADCASTING_EN : 1; /*!< Configures to support the 7bit general call function. 0: Not - support1: Support */ - uint32_t : 17; - } bit; - } CTR; - - union { - __IOM uint32_t reg; /*!< Describe I2C work status. */ - - struct { - __IM uint32_t RESP_REC : 1; /*!< Represents the received ACK value in master mode or slave mode.0: - ACK,1: NACK. */ - __IM uint32_t SLAVE_RW : 1; /*!< Represents the transfer direction in slave mode,.1: Master reads - from slave,0: Master writes to slave. */ - uint32_t : 1; - __IM uint32_t ARB_LOST : 1; /*!< Represents whether the I2C controller loses control of SCL line.0: - No arbitration lost1: Arbitration lost */ - __IM uint32_t BUS_BUSY : 1; /*!< Represents the I2C bus state.1: The I2C bus is busy transferring - data, 0: The I2C bus is in idle state. */ - __IM uint32_t SLAVE_ADDRESSED : 1; /*!< Represents whether the address sent by the master is equal to - the address of the slave.Valid only when the module is - configured as an I2C Slave.0: Not equal1: Equal */ - uint32_t : 2; - __IM uint32_t RXFIFO_CNT : 6; /*!< Represents the number of data bytes to be sent. */ - __IM uint32_t STRETCH_CAUSE : 2; /*!< Represents the cause of SCL clocking stretching in slave mode.0: - Stretching SCL low when the master starts to read data.1: - Stretching SCL low when I2C TX FIFO is empty in slave mode.2: - Stretching SCL low when I2C RX FIFO is full in slave mode. */ - uint32_t : 2; - __IM uint32_t TXFIFO_CNT : 6; /*!< Represents the number of data bytes received in RAM. */ - __IM uint32_t SCL_MAIN_STATE_LAST : 3; /*!< Represents the states of the I2C module state machine. 0: Idle,1: - Address shift,2: ACK address,3: Rx data,4: Tx data,5: Send - ACK,6: Wait ACK */ - uint32_t : 1; - __IM uint32_t SCL_STATE_LAST : 3; /*!< Represents the states of the state machine used to produce SCL.0: - Idle,1: Start,2: Negative edge,3: Low,4: Positive edge,5: - High,6: Stop */ - uint32_t : 1; - } bit; - } SR; - - union { - __IOM uint32_t reg; /*!< Setting time out control for receiving data. */ - - struct { - __IOM uint32_t TIME_OUT_VALUE : 5; /*!< Configures the timeout threshold period for SCL stucking at - high or low level. The actual period is 2^(reg_time_out_value).Measuremen - unit: i2c_sclk. */ - __IOM uint32_t TIME_OUT_EN : 1; /*!< Configures to enable time out control.0: No effect1: Enable */ - uint32_t : 26; - } bit; - } TO; - - union { - __IOM uint32_t reg; /*!< Local slave address setting */ - - struct { - __IOM uint32_t SLAVE_ADDR : 15; /*!< Configure the slave address of I2C Slave. */ - uint32_t : 16; - __IOM uint32_t ADDR_10BIT_EN : 1; /*!< Configures to enable the slave 10-bit addressing mode in master - mode. 0: No effect1: Enable */ - } bit; - } SLAVE_ADDR; - - union { - __IOM uint32_t reg; /*!< FIFO status register. */ - - struct { - __IM uint32_t RXFIFO_RADDR : 5; /*!< Represents the offset address of the APB reading from RXFIFO */ - __IM uint32_t RXFIFO_WADDR : 5; /*!< Represents the offset address of i2c module receiving data and - writing to RXFIFO. */ - __IM uint32_t TXFIFO_RADDR : 5; /*!< Represents the offset address of i2c module reading from TXFIFO. */ - __IM uint32_t TXFIFO_WADDR : 5; /*!< Represents the offset address of APB bus writing to TXFIFO. */ - uint32_t : 2; - __IM uint32_t SLAVE_RW_POINT : 8; /*!< Represents the offset address in the I2C Slave RAM addressed - by I2C Master when in I2C slave mode. */ - uint32_t : 2; - } bit; - } FIFO_ST; - - union { - __IOM uint32_t reg; /*!< FIFO configuration register. */ - - struct { - __IOM uint32_t RXFIFO_WM_THRHD : 5; /*!< Configures the water mark threshold of RXFIFO in nonfifo access - mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter - is bigger than reg_rxfifo_wm_thrhd[4:0], reg_rxfifo_wm_int_raw - bit will be valid. */ - __IOM uint32_t TXFIFO_WM_THRHD : 5; /*!< Configures the water mark threshold of TXFIFO in nonfifo access - mode. When reg_reg_fifo_prt_en is 1 and tx FIFO counter - is smaller than reg_txfifo_wm_thrhd[4:0], reg_txfifo_wm_int_raw - bit will be valid. */ - __IOM uint32_t NONFIFO_EN : 1; /*!< Configures to enable APB nonfifo access. */ - __IOM uint32_t FIFO_ADDR_CFG_EN : 1; /*!< Configures to enable double addressing mode. When this mode - is enabled, the byte received after the I2C address byte - represents the offset address in the I2C Slave RAM. 0: - Disable1: Enable */ - __IOM uint32_t RX_FIFO_RST : 1; /*!< Configures to reset RXFIFO.0: No effect1: Reset */ - __IOM uint32_t TX_FIFO_RST : 1; /*!< Configures to reset TXFIFO.0: No effect1: Reset */ - __IOM uint32_t FIFO_PRT_EN : 1; /*!< Configures to enable FIFO pointer in non-fifo access mode. This - bit controls the valid bits and the TX/RX FIFO overflow, - underflow, full and empty interrupts.0: No effect1: Enable */ - uint32_t : 17; - } bit; - } FIFO_CONF; - - union { - __IOM uint32_t reg; /*!< Rx FIFO read data. */ - - struct { - __IM uint32_t FIFO_RDATA : 8; /*!< Represents the value of RXFIFO read data. */ - uint32_t : 24; - } bit; - } DATA; - - union { - __IOM uint32_t reg; /*!< Raw interrupt status */ - - struct { - __IM uint32_t RXFIFO_WM_INT_RAW : 1; /*!< The raw interrupt status of I2C_RXFIFO_WM_INT interrupt. */ - __IM uint32_t TXFIFO_WM_INT_RAW : 1; /*!< The raw interrupt status of I2C_TXFIFO_WM_INT interrupt. */ - __IM uint32_t RXFIFO_OVF_INT_RAW : 1; /*!< The raw interrupt status of I2C_RXFIFO_OVF_INT interrupt. */ - __IM uint32_t END_DETECT_INT_RAW : 1; /*!< The raw interrupt status of the I2C_END_DETECT_INT interrupt. */ - __IM uint32_t BYTE_TRANS_DONE_INT_RAW : 1;/*!< The raw interrupt status of the I2C_END_DETECT_INT interrupt. */ - __IM uint32_t ARBITRATION_LOST_INT_RAW : 1;/*!< The raw interrupt status of the I2C_ARBITRATION_LOST_INT interrupt. */ - __IM uint32_t MST_TXFIFO_UDF_INT_RAW : 1;/*!< The raw interrupt status of I2C_TRANS_COMPLETE_INT interrupt. */ - __IM uint32_t TRANS_COMPLETE_INT_RAW : 1;/*!< The raw interrupt status of the I2C_TRANS_COMPLETE_INT interrupt. */ - __IM uint32_t TIME_OUT_INT_RAW : 1; /*!< The raw interrupt status of the I2C_TIME_OUT_INT interrupt. */ - __IM uint32_t TRANS_START_INT_RAW : 1; /*!< The raw interrupt status of the I2C_TRANS_START_INT interrupt. */ - __IM uint32_t NACK_INT_RAW : 1; /*!< The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt. */ - __IM uint32_t TXFIFO_OVF_INT_RAW : 1; /*!< The raw interrupt status of I2C_TXFIFO_OVF_INT interrupt. */ - __IM uint32_t RXFIFO_UDF_INT_RAW : 1; /*!< The raw interrupt status of I2C_RXFIFO_UDF_INT interrupt. */ - __IM uint32_t SCL_ST_TO_INT_RAW : 1; /*!< The raw interrupt status of I2C_SCL_ST_TO_INT interrupt. */ - __IM uint32_t SCL_MAIN_ST_TO_INT_RAW : 1;/*!< The raw interrupt status of I2C_SCL_MAIN_ST_TO_INT interrupt. */ - __IM uint32_t DET_START_INT_RAW : 1; /*!< The raw interrupt status of I2C_DET_START_INT interrupt. */ - __IM uint32_t SLAVE_STRETCH_INT_RAW : 1; /*!< The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt. */ - __IM uint32_t GENERAL_CALL_INT_RAW : 1; /*!< The raw interrupt status of I2C_GENARAL_CALL_INT interrupt. */ - __IM uint32_t SLAVE_ADDR_UNMATCH_INT_RAW : 1;/*!< The raw interrupt status of I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt. */ - uint32_t : 13; - } bit; - } INT_RAW; - - union { - __IOM uint32_t reg; /*!< Interrupt clear bits */ - - struct { - __OM uint32_t RXFIFO_WM_INT_CLR : 1; /*!< Write 1 to clear I2C_RXFIFO_WM_INT interrupt. */ - __OM uint32_t TXFIFO_WM_INT_CLR : 1; /*!< Write 1 to clear I2C_TXFIFO_WM_INT interrupt. */ - __OM uint32_t RXFIFO_OVF_INT_CLR : 1; /*!< Write 1 to clear I2C_RXFIFO_OVF_INT interrupt. */ - __OM uint32_t END_DETECT_INT_CLR : 1; /*!< Write 1 to clear the I2C_END_DETECT_INT interrupt. */ - __OM uint32_t BYTE_TRANS_DONE_INT_CLR : 1;/*!< Write 1 to clear the I2C_END_DETECT_INT interrupt. */ - __OM uint32_t ARBITRATION_LOST_INT_CLR : 1;/*!< Write 1 to clear the I2C_ARBITRATION_LOST_INT interrupt. */ - __OM uint32_t MST_TXFIFO_UDF_INT_CLR : 1;/*!< Write 1 to clear I2C_TRANS_COMPLETE_INT interrupt. */ - __OM uint32_t TRANS_COMPLETE_INT_CLR : 1;/*!< Write 1 to clear the I2C_TRANS_COMPLETE_INT interrupt. */ - __OM uint32_t TIME_OUT_INT_CLR : 1; /*!< Write 1 to clear the I2C_TIME_OUT_INT interrupt. */ - __OM uint32_t TRANS_START_INT_CLR : 1; /*!< Write 1 to clear the I2C_TRANS_START_INT interrupt. */ - __OM uint32_t NACK_INT_CLR : 1; /*!< Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt. */ - __OM uint32_t TXFIFO_OVF_INT_CLR : 1; /*!< Write 1 to clear I2C_TXFIFO_OVF_INT interrupt. */ - __OM uint32_t RXFIFO_UDF_INT_CLR : 1; /*!< Write 1 to clear I2C_RXFIFO_UDF_INT interrupt. */ - __OM uint32_t SCL_ST_TO_INT_CLR : 1; /*!< Write 1 to clear I2C_SCL_ST_TO_INT interrupt. */ - __OM uint32_t SCL_MAIN_ST_TO_INT_CLR : 1;/*!< Write 1 to clear I2C_SCL_MAIN_ST_TO_INT interrupt. */ - __OM uint32_t DET_START_INT_CLR : 1; /*!< Write 1 to clear I2C_DET_START_INT interrupt. */ - __OM uint32_t SLAVE_STRETCH_INT_CLR : 1; /*!< Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt. */ - __OM uint32_t GENERAL_CALL_INT_CLR : 1; /*!< Write 1 to clear I2C_GENARAL_CALL_INT interrupt. */ - __OM uint32_t SLAVE_ADDR_UNMATCH_INT_CLR : 1;/*!< Write 1 to clear I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt. */ - uint32_t : 13; - } bit; - } INT_CLR; - - union { - __IOM uint32_t reg; /*!< Interrupt enable bits */ - - struct { - __IOM uint32_t RXFIFO_WM_INT_ENA : 1; /*!< Write 1 to enable I2C_RXFIFO_WM_INT interrupt. */ - __IOM uint32_t TXFIFO_WM_INT_ENA : 1; /*!< Write 1 to enable I2C_TXFIFO_WM_INT interrupt. */ - __IOM uint32_t RXFIFO_OVF_INT_ENA : 1; /*!< Write 1 to enable I2C_RXFIFO_OVF_INT interrupt. */ - __IOM uint32_t END_DETECT_INT_ENA : 1; /*!< Write 1 to enable the I2C_END_DETECT_INT interrupt. */ - __IOM uint32_t BYTE_TRANS_DONE_INT_ENA : 1;/*!< Write 1 to enable the I2C_END_DETECT_INT interrupt. */ - __IOM uint32_t ARBITRATION_LOST_INT_ENA : 1;/*!< Write 1 to enable the I2C_ARBITRATION_LOST_INT interrupt. */ - __IOM uint32_t MST_TXFIFO_UDF_INT_ENA : 1;/*!< Write 1 to enable I2C_TRANS_COMPLETE_INT interrupt. */ - __IOM uint32_t TRANS_COMPLETE_INT_ENA : 1;/*!< Write 1 to enable the I2C_TRANS_COMPLETE_INT interrupt. */ - __IOM uint32_t TIME_OUT_INT_ENA : 1; /*!< Write 1 to enable the I2C_TIME_OUT_INT interrupt. */ - __IOM uint32_t TRANS_START_INT_ENA : 1; /*!< Write 1 to enable the I2C_TRANS_START_INT interrupt. */ - __IOM uint32_t NACK_INT_ENA : 1; /*!< Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt. */ - __IOM uint32_t TXFIFO_OVF_INT_ENA : 1; /*!< Write 1 to enable I2C_TXFIFO_OVF_INT interrupt. */ - __IOM uint32_t RXFIFO_UDF_INT_ENA : 1; /*!< Write 1 to enable I2C_RXFIFO_UDF_INT interrupt. */ - __IOM uint32_t SCL_ST_TO_INT_ENA : 1; /*!< Write 1 to enable I2C_SCL_ST_TO_INT interrupt. */ - __IOM uint32_t SCL_MAIN_ST_TO_INT_ENA : 1;/*!< Write 1 to enable I2C_SCL_MAIN_ST_TO_INT interrupt. */ - __IOM uint32_t DET_START_INT_ENA : 1; /*!< Write 1 to enable I2C_DET_START_INT interrupt. */ - __IOM uint32_t SLAVE_STRETCH_INT_ENA : 1; /*!< Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt. */ - __IOM uint32_t GENERAL_CALL_INT_ENA : 1; /*!< Write 1 to enable I2C_GENARAL_CALL_INT interrupt. */ - __IOM uint32_t SLAVE_ADDR_UNMATCH_INT_ENA : 1;/*!< Write 1 to enable I2C_SLAVE_ADDR_UNMATCH_INT interrupt. */ - uint32_t : 13; - } bit; - } INT_ENA; - - union { - __IOM uint32_t reg; /*!< Status of captured I2C communication events */ - - struct { - __IM uint32_t RXFIFO_WM_INT_ST : 1; /*!< The masked interrupt status status of I2C_RXFIFO_WM_INT interrupt. */ - __IM uint32_t TXFIFO_WM_INT_ST : 1; /*!< The masked interrupt status status of I2C_TXFIFO_WM_INT interrupt. */ - __IM uint32_t RXFIFO_OVF_INT_ST : 1; /*!< The masked interrupt status status of I2C_RXFIFO_OVF_INT interrupt. */ - __IM uint32_t END_DETECT_INT_ST : 1; /*!< The masked interrupt status status of the I2C_END_DETECT_INT - interrupt. */ - __IM uint32_t BYTE_TRANS_DONE_INT_ST : 1;/*!< The masked interrupt status status of the I2C_END_DETECT_INT - interrupt. */ - __IM uint32_t ARBITRATION_LOST_INT_ST : 1;/*!< The masked interrupt status status of the I2C_ARBITRATION_LOST_INT - interrupt. */ - __IM uint32_t MST_TXFIFO_UDF_INT_ST : 1; /*!< The masked interrupt status status of I2C_TRANS_COMPLETE_INT - interrupt. */ - __IM uint32_t TRANS_COMPLETE_INT_ST : 1; /*!< The masked interrupt status status of the I2C_TRANS_COMPLETE_INT - interrupt. */ - __IM uint32_t TIME_OUT_INT_ST : 1; /*!< The masked interrupt status status of the I2C_TIME_OUT_INT interrupt. */ - __IM uint32_t TRANS_START_INT_ST : 1; /*!< The masked interrupt status status of the I2C_TRANS_START_INT - interrupt. */ - __IM uint32_t NACK_INT_ST : 1; /*!< The masked interrupt status status of I2C_SLAVE_STRETCH_INT - interrupt. */ - __IM uint32_t TXFIFO_OVF_INT_ST : 1; /*!< The masked interrupt status status of I2C_TXFIFO_OVF_INT interrupt. */ - __IM uint32_t RXFIFO_UDF_INT_ST : 1; /*!< The masked interrupt status status of I2C_RXFIFO_UDF_INT interrupt. */ - __IM uint32_t SCL_ST_TO_INT_ST : 1; /*!< The masked interrupt status status of I2C_SCL_ST_TO_INT interrupt. */ - __IM uint32_t SCL_MAIN_ST_TO_INT_ST : 1; /*!< The masked interrupt status status of I2C_SCL_MAIN_ST_TO_INT - interrupt. */ - __IM uint32_t DET_START_INT_ST : 1; /*!< The masked interrupt status status of I2C_DET_START_INT interrupt. */ - __IM uint32_t SLAVE_STRETCH_INT_ST : 1; /*!< The masked interrupt status status of I2C_SLAVE_STRETCH_INT - interrupt. */ - __IM uint32_t GENERAL_CALL_INT_ST : 1; /*!< The masked interrupt status status of I2C_GENARAL_CALL_INT interrupt. */ - __IM uint32_t SLAVE_ADDR_UNMATCH_INT_ST : 1;/*!< The masked interrupt status status of I2C_SLAVE_ADDR_UNMATCH_INT - interrupt. */ - uint32_t : 13; - } bit; - } INT_STATUS; - - union { - __IOM uint32_t reg; /*!< Configures the hold time after a negative SCL edge. */ - - struct { - __IOM uint32_t TIME : 9; /*!< Configures the time to hold the data after the falling edge - of SCL.Measurement unit: i2c_sclk */ - uint32_t : 23; - } bit; - } SDA_HOLD; - - union { - __IOM uint32_t reg; /*!< Configures the sample time after a positive SCL edge. */ - - struct { - __IOM uint32_t TIME : 9; /*!< Configures the sample time after a positive SCL edge.Measurement - unit: i2c_sclk */ - uint32_t : 23; - } bit; - } SDA_SAMPLE; - - union { - __IOM uint32_t reg; /*!< Configures the high level width of SCL */ - - struct { - __IOM uint32_t SCL_HIGH_PERIOD : 9; /*!< Configures for how long SCL remains high in master mode.Measurement - unit: i2c_sclk */ - __IOM uint32_t SCL_WAIT_HIGH_PERIOD : 7; /*!< Configures the SCL_FSM's waiting period for SCL high level in - master mode.Measurement unit: i2c_sclk */ - uint32_t : 16; - } bit; - } SCL_HIGH_PERIOD; - __IM uint32_t RESERVED; - - union { - __IOM uint32_t reg; /*!< Configures the delay between the SDA and SCL negative edge for - a start condition */ - - struct { - __IOM uint32_t TIME : 9; /*!< Configures the time between the falling edge of SDA and the - falling edge of SCL for a START condition.Measurement unit: - i2c_sclk. */ - uint32_t : 23; - } bit; - } SCL_START_HOLD; - - union { - __IOM uint32_t reg; /*!< Configures the delay between the positive edge of SCL and the - negative edge of SDA */ - - struct { - __IOM uint32_t TIME : 9; /*!< Configures the time between the positive edge of SCL and the - negative edge of SDA for a RESTART condition.Measurement - unit: i2c_sclk */ - uint32_t : 23; - } bit; - } SCL_RSTART_SETUP; - - union { - __IOM uint32_t reg; /*!< Configures the delay after the SCL clock edge for a stop condition */ - - struct { - __IOM uint32_t TIME : 9; /*!< Configures the delay after the STOP condition.Measurement unit: - i2c_sclk */ - uint32_t : 23; - } bit; - } SCL_STOP_HOLD; - - union { - __IOM uint32_t reg; /*!< Configures the delay between the SDA and SCL rising edge for - a stop condition.Measurement unit: i2c_sclk */ - - struct { - __IOM uint32_t TIME : 9; /*!< Configures the time between the rising edge of SCL and the rising - edge of SDA.Measurement unit: i2c_sclk */ - uint32_t : 23; - } bit; - } SCL_STOP_SETUP; - - union { - __IOM uint32_t reg; /*!< SCL and SDA filter configuration register */ - - struct { - __IOM uint32_t SCL_FILTER_THRES : 4; /*!< Configures the threshold pulse width to be filtered on SCL. - When a pulse on the SCL input has smaller width than this - register value, the I2C controller will ignore that pulse. - Measurement unit: i2c_sclk */ - __IOM uint32_t SDA_FILTER_THRES : 4; /*!< Configures the threshold pulse width to be filtered on SDA. - When a pulse on the SDA input has smaller width than this - register value, the I2C controller will ignore that pulse. - Measurement unit: i2c_sclk */ - __IOM uint32_t SCL_FILTER_EN : 1; /*!< Configures to enable the filter function for SCL. */ - __IOM uint32_t SDA_FILTER_EN : 1; /*!< Configures to enable the filter function for SDA. */ - uint32_t : 22; - } bit; - } FILTER_CFG; - - union { - __IOM uint32_t reg; /*!< I2C CLK configuration register */ - - struct { - __IOM uint32_t SCLK_DIV_NUM : 8; /*!< the integral part of the fractional divisor for i2c module */ - __IOM uint32_t SCLK_DIV_A : 6; /*!< the numerator of the fractional part of the fractional divisor - for i2c module */ - __IOM uint32_t SCLK_DIV_B : 6; /*!< the denominator of the fractional part of the fractional divisor - for i2c module */ - __IOM uint32_t SCLK_SEL : 1; /*!< The clock selection for i2c module:0-XTAL,1-CLK_8MHz. */ - __IOM uint32_t SCLK_ACTIVE : 1; /*!< The clock switch for i2c module */ - uint32_t : 10; - } bit; - } CLK_CONF; - - union { - __IOM uint32_t reg; /*!< I2C command register 0 */ - - struct { - __IOM uint32_t COMMAND0 : 14; /*!< Configures command 0. It consists of three parts: op_code is - the command,0: RSTART, 1: WRITE,2: READ,3: STOP,4: END.Byte_num - represents the number of bytes that need to be sent or - received.ack_check_en, ack_exp and ack are used to control - the ACK bit. See I2C cmd structure for more information. */ - uint32_t : 17; - __IOM uint32_t COMMAND0_DONE : 1; /*!< Represents whether command 0 is done in I2C Master mode.0: Not - done1: Done */ - } bit; - } COMD0; - - union { - __IOM uint32_t reg; /*!< I2C command register 1 */ - - struct { - __IOM uint32_t COMMAND1 : 14; /*!< Configures command 1. See details in I2C_CMD0_REG[13:0]. */ - uint32_t : 17; - __IOM uint32_t COMMAND1_DONE : 1; /*!< Represents whether command 1 is done in I2C Master mode.0: Not - done1: Done */ - } bit; - } COMD1; - - union { - __IOM uint32_t reg; /*!< I2C command register 2 */ - - struct { - __IOM uint32_t COMMAND2 : 14; /*!< Configures command 2. See details in I2C_CMD0_REG[13:0]. */ - uint32_t : 17; - __IOM uint32_t COMMAND2_DONE : 1; /*!< Represents whether command 2 is done in I2C Master mode.0: Not - done1: Done */ - } bit; - } COMD2; - - union { - __IOM uint32_t reg; /*!< I2C command register 3 */ - - struct { - __IOM uint32_t COMMAND3 : 14; /*!< Configures command 3. See details in I2C_CMD0_REG[13:0]. */ - uint32_t : 17; - __IOM uint32_t COMMAND3_DONE : 1; /*!< Represents whether command 3 is done in I2C Master mode.0: Not - done1: Done */ - } bit; - } COMD3; - - union { - __IOM uint32_t reg; /*!< I2C command register 4 */ - - struct { - __IOM uint32_t COMMAND4 : 14; /*!< Configures command 4. See details in I2C_CMD0_REG[13:0]. */ - uint32_t : 17; - __IOM uint32_t COMMAND4_DONE : 1; /*!< Represents whether command 4 is done in I2C Master mode.0: Not - done1: Done */ - } bit; - } COMD4; - - union { - __IOM uint32_t reg; /*!< I2C command register 5 */ - - struct { - __IOM uint32_t COMMAND5 : 14; /*!< Configures command 5. See details in I2C_CMD0_REG[13:0]. */ - uint32_t : 17; - __IOM uint32_t COMMAND5_DONE : 1; /*!< Represents whether command 5 is done in I2C Master mode.0: Not - done1: Done */ - } bit; - } COMD5; - - union { - __IOM uint32_t reg; /*!< I2C command register 6 */ - - struct { - __IOM uint32_t COMMAND6 : 14; /*!< Configures command 6. See details in I2C_CMD0_REG[13:0]. */ - uint32_t : 17; - __IOM uint32_t COMMAND6_DONE : 1; /*!< Represents whether command 6 is done in I2C Master mode.0: Not - done1: Done */ - } bit; - } COMD6; - - union { - __IOM uint32_t reg; /*!< I2C command register 7 */ - - struct { - __IOM uint32_t COMMAND7 : 14; /*!< Configures command 7. See details in I2C_CMD0_REG[13:0]. */ - uint32_t : 17; - __IOM uint32_t COMMAND7_DONE : 1; /*!< Represents whether command 7 is done in I2C Master mode.0: Not - done1: Done */ - } bit; - } COMD7; - - union { - __IOM uint32_t reg; /*!< SCL status time out register */ - - struct { - __IOM uint32_t SCL_ST_TO_I2C : 5; /*!< Configures the threshold value of SCL_FSM state unchanged period. - It should be no more than 23.Measurement unit: i2c_sclk */ - uint32_t : 27; - } bit; - } SCL_ST_TIME_OUT; - - union { - __IOM uint32_t reg; /*!< SCL main status time out register */ - - struct { - __IOM uint32_t SCL_MAIN_ST_TO_I2C : 5; /*!< Configures the threshold value of SCL_MAIN_FSM state unchanged - period.nIt should be no more than 23.Measurement unit: - i2c_sclk */ - uint32_t : 27; - } bit; - } SCL_MAIN_ST_TIME_OUT; - - union { - __IOM uint32_t reg; /*!< Power configuration register */ - - struct { - __IOM uint32_t SCL_RST_SLV_EN : 1; /*!< Configures to send out SCL pulses when I2C master is IDLE. The - number of pulses equals to reg_scl_rst_slv_num[4:0]. */ - __IOM uint32_t SCL_RST_SLV_NUM : 5; /*!< Configure the pulses of SCL generated in I2C master mode. Valid - when reg_scl_rst_slv_en is 1.Measurement unit: i2c_sclk */ - __IOM uint32_t SCL_PD_EN : 1; /*!< Configures to power down the I2C output SCL line. 0: Not power - down.1: Power down.Valid only when reg_scl_force_out is - 1. */ - __IOM uint32_t SDA_PD_EN : 1; /*!< Configures to power down the I2C output SDA line. 0: Not power - down.1: Power down.Valid only when reg_sda_force_out is - 1. */ - uint32_t : 24; - } bit; - } SCL_SP_CONF; - - union { - __IOM uint32_t reg; /*!< Set SCL stretch of I2C slave */ - - struct { - __IOM uint32_t STRETCH_PROTECT_NUM : 10; /*!< Configures the time period to release the SCL line from stretching - to avoid timing violation. Usually it should be larger - than the SDA setup time.Measurement unit: i2c_sclk */ - __IOM uint32_t SLAVE_SCL_STRETCH_EN : 1; /*!< Configures to enable slave SCL stretch function.0: Disable1: - EnableThe SCL output line will be stretched low when reg_slave_scl_stretc - _en is 1 and stretch event happens. The stretch cause can - be seen in reg_stretch_cause. */ - __OM uint32_t SLAVE_SCL_STRETCH_CLR : 1; /*!< Configures to clear the I2C slave SCL stretch function.0: No - effect1: Clear */ - __IOM uint32_t SLAVE_BYTE_ACK_CTL_EN : 1; /*!< Configures to enable the function for slave to control ACK level.0: - Disable1: Enable */ - __IOM uint32_t SLAVE_BYTE_ACK_LVL : 1; /*!< Set the ACK level when slave controlling ACK level function - enables.0: Low level1: High level */ - uint32_t : 18; - } bit; - } SCL_STRETCH_CONF; - __IM uint32_t RESERVED1[28]; - - union { - __IOM uint32_t reg; /*!< Version register */ - - struct { - __IOM uint32_t DATE : 32; /*!< Version control register. */ - } bit; - } DATE; - __IM uint32_t RESERVED2; - - union { - __IOM uint32_t reg; /*!< I2C TXFIFO base address register */ - - struct { - __IM uint32_t TXFIFO_START_ADDR : 32; /*!< Represents the I2C txfifo first address. */ - } bit; - } TXFIFO_START_ADDR; - __IM uint32_t RESERVED3[31]; - - union { - __IOM uint32_t reg; /*!< I2C RXFIFO base address register */ - - struct { - __IM uint32_t RXFIFO_START_ADDR : 32; /*!< Represents the I2C rxfifo first address. */ - } bit; - } RXFIFO_START_ADDR; -} I2C0_Type; /*!< Size = 388 (0x184) */ - - - -/* =========================================================================================================================== */ -/* ================ I2S0 ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief I2S (Inter-IC Sound) Controller 0 (I2S0) - */ - -typedef struct { /*!< I2S0 Structure */ - __IM uint32_t RESERVED[3]; - - union { - __IOM uint32_t reg; /*!< I2S interrupt raw register, valid in level. */ - - struct { - __IM uint32_t RX_DONE_INT_RAW : 1; /*!< The raw interrupt status bit for the i2s_rx_done_int interrupt */ - __IM uint32_t TX_DONE_INT_RAW : 1; /*!< The raw interrupt status bit for the i2s_tx_done_int interrupt */ - __IM uint32_t RX_HUNG_INT_RAW : 1; /*!< The raw interrupt status bit for the i2s_rx_hung_int interrupt */ - __IM uint32_t TX_HUNG_INT_RAW : 1; /*!< The raw interrupt status bit for the i2s_tx_hung_int interrupt */ - uint32_t : 28; - } bit; - } INT_RAW; - - union { - __IOM uint32_t reg; /*!< I2S interrupt status register. */ - - struct { - __IM uint32_t RX_DONE_INT_ST : 1; /*!< The masked interrupt status bit for the i2s_rx_done_int interrupt */ - __IM uint32_t TX_DONE_INT_ST : 1; /*!< The masked interrupt status bit for the i2s_tx_done_int interrupt */ - __IM uint32_t RX_HUNG_INT_ST : 1; /*!< The masked interrupt status bit for the i2s_rx_hung_int interrupt */ - __IM uint32_t TX_HUNG_INT_ST : 1; /*!< The masked interrupt status bit for the i2s_tx_hung_int interrupt */ - uint32_t : 28; - } bit; - } INT_ST; - - union { - __IOM uint32_t reg; /*!< I2S interrupt enable register. */ - - struct { - __IOM uint32_t RX_DONE_INT_ENA : 1; /*!< The interrupt enable bit for the i2s_rx_done_int interrupt */ - __IOM uint32_t TX_DONE_INT_ENA : 1; /*!< The interrupt enable bit for the i2s_tx_done_int interrupt */ - __IOM uint32_t RX_HUNG_INT_ENA : 1; /*!< The interrupt enable bit for the i2s_rx_hung_int interrupt */ - __IOM uint32_t TX_HUNG_INT_ENA : 1; /*!< The interrupt enable bit for the i2s_tx_hung_int interrupt */ - uint32_t : 28; - } bit; - } INT_ENA; - - union { - __IOM uint32_t reg; /*!< I2S interrupt clear register. */ - - struct { - __OM uint32_t RX_DONE_INT_CLR : 1; /*!< Set this bit to clear the i2s_rx_done_int interrupt */ - __OM uint32_t TX_DONE_INT_CLR : 1; /*!< Set this bit to clear the i2s_tx_done_int interrupt */ - __OM uint32_t RX_HUNG_INT_CLR : 1; /*!< Set this bit to clear the i2s_rx_hung_int interrupt */ - __OM uint32_t TX_HUNG_INT_CLR : 1; /*!< Set this bit to clear the i2s_tx_hung_int interrupt */ - uint32_t : 28; - } bit; - } INT_CLR; - __IM uint32_t RESERVED1; - - union { - __IOM uint32_t reg; /*!< I2S RX configure register */ - - struct { - __OM uint32_t RX_RESET : 1; /*!< Set this bit to reset receiver */ - __OM uint32_t RX_FIFO_RESET : 1; /*!< Set this bit to reset Rx AFIFO */ - __IOM uint32_t RX_START : 1; /*!< Set this bit to start receiving data */ - __IOM uint32_t RX_SLAVE_MOD : 1; /*!< Set this bit to enable slave receiver mode */ - __IOM uint32_t RX_STOP_MODE : 2; /*!< 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when - reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when - reg_rx_start is 0 or RX FIFO is full. */ - __IOM uint32_t RX_MONO : 1; /*!< Set this bit to enable receiver in mono mode */ - __IOM uint32_t RX_BIG_ENDIAN : 1; /*!< I2S Rx byte endian, 1: low addr value to high addr. 0: low addr - with low addr value. */ - __IOM uint32_t RX_UPDATE : 1; /*!< Set 1 to update I2S RX registers from APB clock domain to I2S - RX clock domain. This bit will be cleared by hardware after - update register done. */ - __IOM uint32_t RX_MONO_FST_VLD : 1; /*!< 1: The first channel data value is valid in I2S RX mono mode. - 0: The second channel data value is valid in I2S RX mono - mode. */ - __IOM uint32_t RX_PCM_CONF : 2; /*!< I2S RX compress/decompress configuration bit. & 0 (atol): A-Law - decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law - decompress, 3 (ltou) : u-Law compress. & */ - __IOM uint32_t RX_PCM_BYPASS : 1; /*!< Set this bit to bypass Compress/Decompress module for received - data. */ - __IOM uint32_t RX_MSB_SHIFT : 1; /*!< Set this bit to enable receiver in Phillips standard mode */ - uint32_t : 1; - __IOM uint32_t RX_LEFT_ALIGN : 1; /*!< 1: I2S RX left alignment mode. 0: I2S RX right alignment mode. */ - __IOM uint32_t RX_24_FILL_EN : 1; /*!< 1: store 24 channel bits to 32 bits. 0:store 24 channel bits - to 24 bits. */ - __IOM uint32_t RX_WS_IDLE_POL : 1; /*!< 0: WS should be 0 when receiving left channel data, and WS is - 1in right channel. 1: WS should be 1 when receiving left - channel data, and WS is 0in right channel. */ - __IOM uint32_t RX_BIT_ORDER : 1; /*!< I2S Rx bit endian. 1:small endian, the LSB is received first. - 0:big endian, the MSB is received first. */ - __IOM uint32_t RX_TDM_EN : 1; /*!< 1: Enable I2S TDM Rx mode . 0: Disable. */ - __IOM uint32_t RX_PDM_EN : 1; /*!< 1: Enable I2S PDM Rx mode . 0: Disable. */ - __IOM uint32_t RX_BCK_DIV_NUM : 6; /*!< Bit clock configuration bits in receiver mode. */ - uint32_t : 5; - } bit; - } RX_CONF; - - union { - __IOM uint32_t reg; /*!< I2S TX configure register */ - - struct { - __OM uint32_t TX_RESET : 1; /*!< Set this bit to reset transmitter */ - __OM uint32_t TX_FIFO_RESET : 1; /*!< Set this bit to reset Tx AFIFO */ - __IOM uint32_t TX_START : 1; /*!< Set this bit to start transmitting data */ - __IOM uint32_t TX_SLAVE_MOD : 1; /*!< Set this bit to enable slave transmitter mode */ - __IOM uint32_t TX_STOP_EN : 1; /*!< Set this bit to stop disable output BCK signal and WS signal - when tx FIFO is emtpy */ - __IOM uint32_t TX_CHAN_EQUAL : 1; /*!< 1: The value of Left channel data is equal to the value of right - channel data in I2S TX mono mode or TDM channel select - mode. 0: The invalid channel data is reg_i2s_single_data - in I2S TX mono mode or TDM channel select mode. */ - __IOM uint32_t TX_MONO : 1; /*!< Set this bit to enable transmitter in mono mode */ - __IOM uint32_t TX_BIG_ENDIAN : 1; /*!< I2S Tx byte endian, 1: low addr value to high addr. 0: low addr - with low addr value. */ - __IOM uint32_t TX_UPDATE : 1; /*!< Set 1 to update I2S TX registers from APB clock domain to I2S - TX clock domain. This bit will be cleared by hardware after - update register done. */ - __IOM uint32_t TX_MONO_FST_VLD : 1; /*!< 1: The first channel data value is valid in I2S TX mono mode. - 0: The second channel data value is valid in I2S TX mono - mode. */ - __IOM uint32_t TX_PCM_CONF : 2; /*!< I2S TX compress/decompress configuration bit. & 0 (atol): A-Law - decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law - decompress, 3 (ltou) : u-Law compress. & */ - __IOM uint32_t TX_PCM_BYPASS : 1; /*!< Set this bit to bypass Compress/Decompress module for transmitted - data. */ - __IOM uint32_t TX_MSB_SHIFT : 1; /*!< Set this bit to enable transmitter in Phillips standard mode */ - __IOM uint32_t TX_BCK_NO_DLY : 1; /*!< 1: BCK is not delayed to generate pos/neg edge in master mode. - 0: BCK is delayed to generate pos/neg edge in master mode. */ - __IOM uint32_t TX_LEFT_ALIGN : 1; /*!< 1: I2S TX left alignment mode. 0: I2S TX right alignment mode. */ - __IOM uint32_t TX_24_FILL_EN : 1; /*!< 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in - 24 channel bits mode */ - __IOM uint32_t TX_WS_IDLE_POL : 1; /*!< 0: WS should be 0 when sending left channel data, and WS is - 1in right channel. 1: WS should be 1 when sending left - channel data, and WS is 0in right channel. */ - __IOM uint32_t TX_BIT_ORDER : 1; /*!< I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big - endian, the MSB is sent first. */ - __IOM uint32_t TX_TDM_EN : 1; /*!< 1: Enable I2S TDM Tx mode . 0: Disable. */ - __IOM uint32_t TX_PDM_EN : 1; /*!< 1: Enable I2S PDM Tx mode . 0: Disable. */ - __IOM uint32_t TX_BCK_DIV_NUM : 6; /*!< Bit clock configuration bits in transmitter mode. */ - __IOM uint32_t TX_CHAN_MOD : 3; /*!< I2S transmitter channel mode configuration bits. */ - __IOM uint32_t SIG_LOOPBACK : 1; /*!< Enable signal loop back mode with transmitter module and receiver - module sharing the same WS and BCK signals. */ - uint32_t : 1; - } bit; - } TX_CONF; - - union { - __IOM uint32_t reg; /*!< I2S RX configure register 1 */ - - struct { - __IOM uint32_t RX_TDM_WS_WIDTH : 9; /*!< The width of rx_ws_out at idle level in TDM mode is (I2S_RX_TDM_WS_WIDTH[8:0] - +1) * T_bck */ - uint32_t : 5; - __IOM uint32_t RX_BITS_MOD : 5; /*!< Set the bits to configure the valid data bit length of I2S receiver - channel. 7: all the valid channel data is in 8-bit-mode. - 15: all the valid channel data is in 16-bit-mode. 23: all - the valid channel data is in 24-bit-mode. 31:all the valid - channel data is in 32-bit-mode. */ - __IOM uint32_t RX_HALF_SAMPLE_BITS : 8; /*!< I2S Rx half sample bits -1. */ - __IOM uint32_t RX_TDM_CHAN_BITS : 5; /*!< The Rx bit number for each channel minus 1in TDM mode. */ - } bit; - } RX_CONF1; - - union { - __IOM uint32_t reg; /*!< I2S TX configure register 1 */ - - struct { - __IOM uint32_t TX_TDM_WS_WIDTH : 9; /*!< The width of tx_ws_out at idle level in TDM mode is (I2S_TX_TDM_WS_WIDTH[8:0] - +1) * T_bck */ - uint32_t : 5; - __IOM uint32_t TX_BITS_MOD : 5; /*!< Set the bits to configure the valid data bit length of I2S transmitter - channel. 7: all the valid channel data is in 8-bit-mode. - 15: all the valid channel data is in 16-bit-mode. 23: all - the valid channel data is in 24-bit-mode. 31:all the valid - channel data is in 32-bit-mode. */ - __IOM uint32_t TX_HALF_SAMPLE_BITS : 8; /*!< I2S Tx half sample bits -1. */ - __IOM uint32_t TX_TDM_CHAN_BITS : 5; /*!< The Tx bit number for each channel minus 1in TDM mode. */ - } bit; - } TX_CONF1; - __IM uint32_t RESERVED2[4]; - - union { - __IOM uint32_t reg; /*!< I2S TX PCM2PDM configuration register */ - - struct { - __IOM uint32_t TX_PDM_HP_BYPASS : 1; /*!< I2S TX PDM bypass hp filter or not. The option has been removed. */ - __IOM uint32_t TX_PDM_SINC_OSR2 : 4; /*!< I2S TX PDM OSR2 value */ - __IOM uint32_t TX_PDM_PRESCALE : 8; /*!< I2S TX PDM prescale for sigmadelta */ - __IOM uint32_t TX_PDM_HP_IN_SHIFT : 2; /*!< I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 - , 3: x4 */ - __IOM uint32_t TX_PDM_LP_IN_SHIFT : 2; /*!< I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 - , 3: x4 */ - __IOM uint32_t TX_PDM_SINC_IN_SHIFT : 2; /*!< I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 - , 3: x4 */ - __IOM uint32_t TX_PDM_SIGMADELTA_IN_SHIFT : 2;/*!< I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 - , 3: x4 */ - __IOM uint32_t TX_PDM_SIGMADELTA_DITHER2 : 1;/*!< I2S TX PDM sigmadelta dither2 value */ - __IOM uint32_t TX_PDM_SIGMADELTA_DITHER : 1;/*!< I2S TX PDM sigmadelta dither value */ - __IOM uint32_t TX_PDM_DAC_2OUT_EN : 1; /*!< I2S TX PDM dac mode enable */ - __IOM uint32_t TX_PDM_DAC_MODE_EN : 1; /*!< I2S TX PDM dac 2channel enable */ - __IOM uint32_t PCM2PDM_CONV_EN : 1; /*!< I2S TX PDM Converter enable */ - uint32_t : 6; - } bit; - } TX_PCM2PDM_CONF; - - union { - __IOM uint32_t reg; /*!< I2S TX PCM2PDM configuration register */ - - struct { - __IOM uint32_t TX_PDM_FP : 10; /*!< I2S TX PDM Fp */ - __IOM uint32_t TX_PDM_FS : 10; /*!< I2S TX PDM Fs */ - __IOM uint32_t TX_IIR_HP_MULT12_5 : 3; /*!< The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 - + I2S_TX_IIR_HP_MULT12_5[2:0]) */ - __IOM uint32_t TX_IIR_HP_MULT12_0 : 3; /*!< The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 - + I2S_TX_IIR_HP_MULT12_0[2:0]) */ - uint32_t : 6; - } bit; - } TX_PCM2PDM_CONF1; - - union { - __IOM uint32_t reg; /*!< I2S RX configure register */ - - struct { - uint32_t : 19; - __IOM uint32_t RX_PDM2PCM_EN : 1; /*!< 1: Enable PDM2PCM RX mode. 0: DIsable. */ - __IOM uint32_t RX_PDM_SINC_DSR_16_EN : 1; /*!< Configure the down sampling rate of PDM RX filter group1 module. - 1: The down sampling rate is 128. 0: down sampling rate - is 64. */ - __IOM uint32_t RX_PDM2PCM_AMPLIFY_NUM : 4;/*!< Configure PDM RX amplify number. */ - __IOM uint32_t RX_PDM_HP_BYPASS : 1; /*!< I2S PDM RX bypass hp filter or not. */ - __IOM uint32_t RX_IIR_HP_MULT12_5 : 3; /*!< The fourth parameter of PDM RX IIR_HP filter stage 2 is (504 - + LP_I2S_RX_IIR_HP_MULT12_5[2:0]) */ - __IOM uint32_t RX_IIR_HP_MULT12_0 : 3; /*!< The fourth parameter of PDM RX IIR_HP filter stage 1 is (504 - + LP_I2S_RX_IIR_HP_MULT12_0[2:0]) */ - } bit; - } RX_PDM2PCM_CONF; - __IM uint32_t RESERVED3; - - union { - __IOM uint32_t reg; /*!< I2S TX TDM mode control register */ - - struct { - __IOM uint32_t RX_TDM_PDM_CHAN0_EN : 1; /*!< 1: Enable the valid data input of I2S RX TDM or PDM channel - 0. 0: Disable, just input 0 in this channel. */ - __IOM uint32_t RX_TDM_PDM_CHAN1_EN : 1; /*!< 1: Enable the valid data input of I2S RX TDM or PDM channel - 1. 0: Disable, just input 0 in this channel. */ - __IOM uint32_t RX_TDM_PDM_CHAN2_EN : 1; /*!< 1: Enable the valid data input of I2S RX TDM or PDM channel - 2. 0: Disable, just input 0 in this channel. */ - __IOM uint32_t RX_TDM_PDM_CHAN3_EN : 1; /*!< 1: Enable the valid data input of I2S RX TDM or PDM channel - 3. 0: Disable, just input 0 in this channel. */ - __IOM uint32_t RX_TDM_PDM_CHAN4_EN : 1; /*!< 1: Enable the valid data input of I2S RX TDM or PDM channel - 4. 0: Disable, just input 0 in this channel. */ - __IOM uint32_t RX_TDM_PDM_CHAN5_EN : 1; /*!< 1: Enable the valid data input of I2S RX TDM or PDM channel - 5. 0: Disable, just input 0 in this channel. */ - __IOM uint32_t RX_TDM_PDM_CHAN6_EN : 1; /*!< 1: Enable the valid data input of I2S RX TDM or PDM channel - 6. 0: Disable, just input 0 in this channel. */ - __IOM uint32_t RX_TDM_PDM_CHAN7_EN : 1; /*!< 1: Enable the valid data input of I2S RX TDM or PDM channel - 7. 0: Disable, just input 0 in this channel. */ - __IOM uint32_t RX_TDM_CHAN8_EN : 1; /*!< 1: Enable the valid data input of I2S RX TDM channel 8. 0: Disable, - just input 0 in this channel. */ - __IOM uint32_t RX_TDM_CHAN9_EN : 1; /*!< 1: Enable the valid data input of I2S RX TDM channel 9. 0: Disable, - just input 0 in this channel. */ - __IOM uint32_t RX_TDM_CHAN10_EN : 1; /*!< 1: Enable the valid data input of I2S RX TDM channel 10. 0: - Disable, just input 0 in this channel. */ - __IOM uint32_t RX_TDM_CHAN11_EN : 1; /*!< 1: Enable the valid data input of I2S RX TDM channel 11. 0: - Disable, just input 0 in this channel. */ - __IOM uint32_t RX_TDM_CHAN12_EN : 1; /*!< 1: Enable the valid data input of I2S RX TDM channel 12. 0: - Disable, just input 0 in this channel. */ - __IOM uint32_t RX_TDM_CHAN13_EN : 1; /*!< 1: Enable the valid data input of I2S RX TDM channel 13. 0: - Disable, just input 0 in this channel. */ - __IOM uint32_t RX_TDM_CHAN14_EN : 1; /*!< 1: Enable the valid data input of I2S RX TDM channel 14. 0: - Disable, just input 0 in this channel. */ - __IOM uint32_t RX_TDM_CHAN15_EN : 1; /*!< 1: Enable the valid data input of I2S RX TDM channel 15. 0: - Disable, just input 0 in this channel. */ - __IOM uint32_t RX_TDM_TOT_CHAN_NUM : 4; /*!< The total channel number of I2S TX TDM mode. */ - uint32_t : 12; - } bit; - } RX_TDM_CTRL; - - union { - __IOM uint32_t reg; /*!< I2S TX TDM mode control register */ - - struct { - __IOM uint32_t TX_TDM_CHAN0_EN : 1; /*!< 1: Enable the valid data output of I2S TX TDM channel 0. 0: - Disable, just output 0 in this channel. */ - __IOM uint32_t TX_TDM_CHAN1_EN : 1; /*!< 1: Enable the valid data output of I2S TX TDM channel 1. 0: - Disable, just output 0 in this channel. */ - __IOM uint32_t TX_TDM_CHAN2_EN : 1; /*!< 1: Enable the valid data output of I2S TX TDM channel 2. 0: - Disable, just output 0 in this channel. */ - __IOM uint32_t TX_TDM_CHAN3_EN : 1; /*!< 1: Enable the valid data output of I2S TX TDM channel 3. 0: - Disable, just output 0 in this channel. */ - __IOM uint32_t TX_TDM_CHAN4_EN : 1; /*!< 1: Enable the valid data output of I2S TX TDM channel 4. 0: - Disable, just output 0 in this channel. */ - __IOM uint32_t TX_TDM_CHAN5_EN : 1; /*!< 1: Enable the valid data output of I2S TX TDM channel 5. 0: - Disable, just output 0 in this channel. */ - __IOM uint32_t TX_TDM_CHAN6_EN : 1; /*!< 1: Enable the valid data output of I2S TX TDM channel 6. 0: - Disable, just output 0 in this channel. */ - __IOM uint32_t TX_TDM_CHAN7_EN : 1; /*!< 1: Enable the valid data output of I2S TX TDM channel 7. 0: - Disable, just output 0 in this channel. */ - __IOM uint32_t TX_TDM_CHAN8_EN : 1; /*!< 1: Enable the valid data output of I2S TX TDM channel 8. 0: - Disable, just output 0 in this channel. */ - __IOM uint32_t TX_TDM_CHAN9_EN : 1; /*!< 1: Enable the valid data output of I2S TX TDM channel 9. 0: - Disable, just output 0 in this channel. */ - __IOM uint32_t TX_TDM_CHAN10_EN : 1; /*!< 1: Enable the valid data output of I2S TX TDM channel 10. 0: - Disable, just output 0 in this channel. */ - __IOM uint32_t TX_TDM_CHAN11_EN : 1; /*!< 1: Enable the valid data output of I2S TX TDM channel 11. 0: - Disable, just output 0 in this channel. */ - __IOM uint32_t TX_TDM_CHAN12_EN : 1; /*!< 1: Enable the valid data output of I2S TX TDM channel 12. 0: - Disable, just output 0 in this channel. */ - __IOM uint32_t TX_TDM_CHAN13_EN : 1; /*!< 1: Enable the valid data output of I2S TX TDM channel 13. 0: - Disable, just output 0 in this channel. */ - __IOM uint32_t TX_TDM_CHAN14_EN : 1; /*!< 1: Enable the valid data output of I2S TX TDM channel 14. 0: - Disable, just output 0 in this channel. */ - __IOM uint32_t TX_TDM_CHAN15_EN : 1; /*!< 1: Enable the valid data output of I2S TX TDM channel 15. 0: - Disable, just output 0 in this channel. */ - __IOM uint32_t TX_TDM_TOT_CHAN_NUM : 4; /*!< The total channel number of I2S TX TDM mode. */ - __IOM uint32_t TX_TDM_SKIP_MSK_EN : 1; /*!< When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM - + 1) channels, and only the data of the enabled channels - is sent, then this bit should be set. Clear it when all - the data stored in DMA TX buffer is for enabled channels. */ - uint32_t : 11; - } bit; - } TX_TDM_CTRL; - - union { - __IOM uint32_t reg; /*!< I2S RX timing control register */ - - struct { - __IOM uint32_t RX_SD_IN_DM : 2; /*!< The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay - by pos edge. 2: delay by neg edge. 3: not used. */ - uint32_t : 2; - __IOM uint32_t RX_SD1_IN_DM : 2; /*!< The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay - by pos edge. 2: delay by neg edge. 3: not used. */ - uint32_t : 2; - __IOM uint32_t RX_SD2_IN_DM : 2; /*!< The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay - by pos edge. 2: delay by neg edge. 3: not used. */ - uint32_t : 2; - __IOM uint32_t RX_SD3_IN_DM : 2; /*!< The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay - by pos edge. 2: delay by neg edge. 3: not used. */ - uint32_t : 2; - __IOM uint32_t RX_WS_OUT_DM : 2; /*!< The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay - by pos edge. 2: delay by neg edge. 3: not used. */ - uint32_t : 2; - __IOM uint32_t RX_BCK_OUT_DM : 2; /*!< The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay - by pos edge. 2: delay by neg edge. 3: not used. */ - uint32_t : 2; - __IOM uint32_t RX_WS_IN_DM : 2; /*!< The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay - by pos edge. 2: delay by neg edge. 3: not used. */ - uint32_t : 2; - __IOM uint32_t RX_BCK_IN_DM : 2; /*!< The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay - by pos edge. 2: delay by neg edge. 3: not used. */ - uint32_t : 2; - } bit; - } RX_TIMING; - - union { - __IOM uint32_t reg; /*!< I2S TX timing control register */ - - struct { - __IOM uint32_t TX_SD_OUT_DM : 2; /*!< The delay mode of I2S TX SD output signal. 0: bypass. 1: delay - by pos edge. 2: delay by neg edge. 3: not used. */ - uint32_t : 2; - __IOM uint32_t TX_SD1_OUT_DM : 2; /*!< The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay - by pos edge. 2: delay by neg edge. 3: not used. */ - uint32_t : 10; - __IOM uint32_t TX_WS_OUT_DM : 2; /*!< The delay mode of I2S TX WS output signal. 0: bypass. 1: delay - by pos edge. 2: delay by neg edge. 3: not used. */ - uint32_t : 2; - __IOM uint32_t TX_BCK_OUT_DM : 2; /*!< The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay - by pos edge. 2: delay by neg edge. 3: not used. */ - uint32_t : 2; - __IOM uint32_t TX_WS_IN_DM : 2; /*!< The delay mode of I2S TX WS input signal. 0: bypass. 1: delay - by pos edge. 2: delay by neg edge. 3: not used. */ - uint32_t : 2; - __IOM uint32_t TX_BCK_IN_DM : 2; /*!< The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay - by pos edge. 2: delay by neg edge. 3: not used. */ - uint32_t : 2; - } bit; - } TX_TIMING; - - union { - __IOM uint32_t reg; /*!< I2S HUNG configure register. */ - - struct { - __IOM uint32_t LC_FIFO_TIMEOUT : 8; /*!< the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt - will be triggered when fifo hung counter is equal to this - value */ - __IOM uint32_t LC_FIFO_TIMEOUT_SHIFT : 3; /*!< The bits are used to scale tick counter threshold. The tick - counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift */ - __IOM uint32_t LC_FIFO_TIMEOUT_ENA : 1; /*!< The enable bit for FIFO timeout */ - uint32_t : 20; - } bit; - } LC_HUNG_CONF; - - union { - __IOM uint32_t reg; /*!< I2S RX data number control register. */ - - struct { - __IOM uint32_t RX_EOF_NUM : 12; /*!< The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * - (REG_RX_EOF_NUM[11:0] + 1) . It will trigger in_suc_eof - interrupt in the configured DMA RX channel. */ - uint32_t : 20; - } bit; - } RXEOF_NUM; - - union { - __IOM uint32_t reg; /*!< I2S signal data register */ - - struct { - __IOM uint32_t SINGLE_DATA : 32; /*!< The configured constant channel data to be sent out. */ - } bit; - } CONF_SIGLE_DATA; - - union { - __IOM uint32_t reg; /*!< I2S TX status register */ - - struct { - __IM uint32_t TX_IDLE : 1; /*!< 1: i2s_tx is idle state. 0: i2s_tx is working. */ - uint32_t : 31; - } bit; - } STATE; - - union { - __IOM uint32_t reg; /*!< I2S ETM configure register */ - - struct { - __IOM uint32_t ETM_TX_SEND_WORD_NUM : 10; /*!< I2S ETM send x words event. When sending word number of reg_etm_tx_send_word_n - m[9:0], i2s will trigger an etm event. */ - __IOM uint32_t ETM_RX_RECEIVE_WORD_NUM : 10;/*!< I2S ETM receive x words event. When receiving word number of - reg_etm_rx_receive_word_num[9:0], i2s will trigger an etm - event. */ - uint32_t : 12; - } bit; - } ETM_CONF; - - union { - __IOM uint32_t reg; /*!< I2S sync counter register */ - - struct { - __IM uint32_t TX_FIFO_CNT : 31; /*!< tx fifo counter value. */ - __OM uint32_t TX_FIFO_CNT_RST : 1; /*!< Set this bit to reset tx fifo counter. */ - } bit; - } FIFO_CNT; - - union { - __IOM uint32_t reg; /*!< I2S sync counter register */ - - struct { - __IM uint32_t TX_BCK_CNT : 31; /*!< tx bck counter value. */ - __OM uint32_t TX_BCK_CNT_RST : 1; /*!< Set this bit to reset tx bck counter. */ - } bit; - } BCK_CNT; - - union { - __IOM uint32_t reg; /*!< Clock gate register */ - - struct { - __IOM uint32_t CLK_EN : 1; /*!< set this bit to enable clock gate */ - uint32_t : 31; - } bit; - } CLK_GATE; - - union { - __IOM uint32_t reg; /*!< Version control register */ - - struct { - __IOM uint32_t DATE : 28; /*!< I2S version control register */ - uint32_t : 4; - } bit; - } DATE; -} I2S0_Type; /*!< Size = 132 (0x84) */ - - - -/* =========================================================================================================================== */ -/* ================ I3C_MST ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief I3C Controller (Master) (I3C_MST) - */ - -typedef struct { /*!< I3C_MST Structure */ - - union { - __IOM uint32_t reg; /*!< DEVICE_CTRL register controls the transfer properties and disposition - of controllers capabilities. */ - - struct { - uint32_t : 1; - __IOM uint32_t REG_BA_INCLUDE : 1; /*!< This bit is used to include I3C broadcast address(0x7E) for - private transfer.(If I3C broadcast address is not include - for the private transfer, In-Band Interrupts driven from - Slaves may not win address arbitration. Hence IBIs will - get delayed) */ - __IOM uint32_t REG_TRANS_START : 1; /*!< Transfer Start */ - __IOM uint32_t REG_CLK_EN : 1; /*!< NA */ - __IOM uint32_t REG_IBI_RSTART_TRANS_EN : 1;/*!< NA */ - __IOM uint32_t REG_AUTO_DIS_IBI_EN : 1; /*!< NA */ - __IOM uint32_t REG_DMA_RX_EN : 1; /*!< NA */ - __IOM uint32_t REG_DMA_TX_EN : 1; /*!< NA */ - __IOM uint32_t REG_MULTI_SLV_SINGLE_CCC_EN : 1;/*!< 0: rx high bit first, 1: rx low bit first */ - __IOM uint32_t REG_RX_BIT_ORDER : 1; /*!< 0: rx low byte fist, 1: rx high byte first */ - __IOM uint32_t REG_RX_BYTE_ORDER : 1; /*!< NA */ - __IOM uint32_t REG_SCL_PULLUP_FORCE_EN : 1;/*!< This bit is used to force scl_pullup_en */ - __IOM uint32_t REG_SCL_OE_FORCE_EN : 1; /*!< This bit is used to force scl_oe */ - __IOM uint32_t REG_SDA_PP_RD_PULLUP_EN : 1;/*!< NA */ - __IOM uint32_t REG_SDA_RD_TBIT_HLVL_PULLUP_EN : 1;/*!< NA */ - __IOM uint32_t REG_SDA_PP_WR_PULLUP_EN : 1;/*!< NA */ - __IOM uint32_t REG_DATA_BYTE_CNT_UNLATCH : 1;/*!< 1: read current real-time updated value 0: read latch data byte - cnt value */ - __IOM uint32_t REG_MEM_CLK_FORCE_ON : 1; /*!< 1: dev characteristic and address table memory clk date force - on . 0 : clock gating by rd/wr. */ - uint32_t : 14; - } bit; - } DEVICE_CTRL; - __IM uint32_t RESERVED[6]; - - union { - __IOM uint32_t reg; /*!< In-Band Interrupt Status Threshold Value . Every In Band Interrupt - received by I3C controller generates an IBI status. This - field controls the number of IBI status entries in the - IBI buffer that trigger the IBI_STATUS_THLD_STAT interrupt. */ - - struct { - __IOM uint32_t REG_CMD_BUF_EMPTY_THLD : 4;/*!< Command Buffer Empty Threshold Value is used to control the - number of empty locations(or greater) in the Command Buffer - that trigger CMD_BUFFER_READY_STAT interrupt. */ - uint32_t : 2; - __IOM uint32_t REG_RESP_BUF_THLD : 3; /*!< Response Buffer Threshold Value is used to control the number - of entries in the Response Buffer that trigger the RESP_READY_STAT_INTR. */ - uint32_t : 3; - __IOM uint32_t REG_IBI_DATA_BUF_THLD : 3; /*!< In-Band Interrupt Data Threshold Value . Every In Band Interrupt - received by I3C controller generates an IBI status. This - field controls the number of IBI data entries in the IBI - buffer that trigger the IBI_DATA_THLD_STAT interrupt. */ - uint32_t : 3; - __IOM uint32_t REG_IBI_STATUS_BUF_THLD : 3;/*!< NA */ - uint32_t : 11; - } bit; - } BUFFER_THLD_CTRL; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_TX_DATA_BUF_THLD : 3; /*!< Transmit Buffer Threshold Value. This field controls the number - of empty locations in the Transmit FIFO that trigger the - TX_THLD_STAT interrupt. Supports values: 000:2 001:4 010:8 - 011:16 100:31, else:31 */ - __IOM uint32_t REG_RX_DATA_BUF_THLD : 3; /*!< Receive Buffer Threshold Value. This field controls the number - of empty locations in the Receive FIFO that trigger the - RX_THLD_STAT interrupt. Supports: 000:2 001:4 010:8 011:16 - 100:31, else:31 */ - uint32_t : 26; - } bit; - } DATA_BUFFER_THLD_CTRL; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - uint32_t : 2; - __IOM uint32_t REG_NOTIFY_SIR_REJECTED : 1;/*!< Notify Rejected Slave Interrupt Request Control. This bit is - used to suppress reporting to the application about Slave - Interrupt Request. 0:Suppress passing the IBI Status to - the IBI FIFO(hence not notifying the application) when - a SIR request is NACKed and auto-disabled base on the IBI_SIR_REQ_REJECT - register. 1: Writes IBI Status to the IBI FIFO(hence notifying - the application) when SIR request is NACKed and auto-disabled - based on the IBI_SIR_REQ_REJECT registerl. */ - uint32_t : 29; - } bit; - } IBI_NOTIFY_CTRL; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_SIR_REQ_PAYLOAD : 32; /*!< NA */ - } bit; - } IBI_SIR_REQ_PAYLOAD; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_SIR_REQ_REJECT : 32; /*!< The application of controller can decide whether to send ACK - or NACK for Slave request received from any I3C device. - A device specific response control bit is provided to select - the response option, Master will ACK/NACK the Master Request - based on programming of control bit, corresponding to the - interrupting device. 0:ACK the SIR Request 1:NACK and send - direct auto disable CCC */ - } bit; - } IBI_SIR_REQ_REJECT; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __OM uint32_t TX_DATA_BUF_THLD_INT_CLR : 1;/*!< NA */ - __OM uint32_t RX_DATA_BUF_THLD_INT_CLR : 1;/*!< NA */ - __OM uint32_t IBI_STATUS_THLD_INT_CLR : 1;/*!< NA */ - __OM uint32_t CMD_BUF_EMPTY_THLD_INT_CLR : 1;/*!< NA */ - __OM uint32_t RESP_READY_INT_CLR : 1; /*!< NA */ - __OM uint32_t NXT_CMD_REQ_ERR_INT_CLR : 1;/*!< NA */ - __OM uint32_t TRANSFER_ERR_INT_CLR : 1; /*!< NA */ - __OM uint32_t TRANSFER_COMPLETE_INT_CLR : 1;/*!< NA */ - __OM uint32_t COMMAND_DONE_INT_CLR : 1; /*!< NA */ - __OM uint32_t DETECT_START_INT_CLR : 1; /*!< NA */ - __OM uint32_t RESP_BUF_OVF_INT_CLR : 1; /*!< NA */ - __OM uint32_t IBI_DATA_BUF_OVF_INT_CLR : 1;/*!< NA */ - __OM uint32_t IBI_STATUS_BUF_OVF_INT_CLR : 1;/*!< NA */ - __OM uint32_t IBI_HANDLE_DONE_INT_CLR : 1;/*!< NA */ - __OM uint32_t IBI_DETECT_INT_CLR : 1; /*!< NA */ - __OM uint32_t CMD_CCC_MISMATCH_INT_CLR : 1;/*!< NA */ - uint32_t : 16; - } bit; - } INT_CLR; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t TX_DATA_BUF_THLD_INT_RAW : 1;/*!< NA */ - __IOM uint32_t RX_DATA_BUF_THLD_INT_RAW : 1;/*!< NA */ - __IOM uint32_t IBI_STATUS_THLD_INT_RAW : 1;/*!< NA */ - __IOM uint32_t CMD_BUF_EMPTY_THLD_INT_RAW : 1;/*!< NA */ - __IOM uint32_t RESP_READY_INT_RAW : 1; /*!< NA */ - __IOM uint32_t NXT_CMD_REQ_ERR_INT_RAW : 1;/*!< NA */ - __IOM uint32_t TRANSFER_ERR_INT_RAW : 1; /*!< NA */ - __IOM uint32_t TRANSFER_COMPLETE_INT_RAW : 1;/*!< NA */ - __IOM uint32_t COMMAND_DONE_INT_RAW : 1; /*!< NA */ - __IOM uint32_t DETECT_START_INT_RAW : 1; /*!< NA */ - __IOM uint32_t RESP_BUF_OVF_INT_RAW : 1; /*!< NA */ - __IOM uint32_t IBI_DATA_BUF_OVF_INT_RAW : 1;/*!< NA */ - __IOM uint32_t IBI_STATUS_BUF_OVF_INT_RAW : 1;/*!< NA */ - __IOM uint32_t IBI_HANDLE_DONE_INT_RAW : 1;/*!< NA */ - __IOM uint32_t IBI_DETECT_INT_RAW : 1; /*!< NA */ - __IOM uint32_t CMD_CCC_MISMATCH_INT_RAW : 1;/*!< NA */ - uint32_t : 16; - } bit; - } INT_RAW; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t TX_DATA_BUF_THLD_INT_ST : 1;/*!< This interrupt is generated when number of empty locations in - transmit buffer is greater than or equal to threshold value - specified by TX_EMPTY_BUS_THLD field in DATA_BUFFER_THLD_CTRL - register. This interrupt will be cleared automatically - when number of empty locations in transmit buffer is less - than threshold value. */ - __IM uint32_t RX_DATA_BUF_THLD_INT_ST : 1;/*!< This interrupt is generated when number of entries in receive - buffer is greater than or equal to threshold value specified - by RX_BUF_THLD field in DATA_BUFFER_THLD_CTRL register. - This interrupt will be cleared automatically when number - of entries in receive buffer is less than threshold value. */ - __IM uint32_t IBI_STATUS_THLD_INT_ST : 1;/*!< Only used in master mode. This interrupt is generated when number - of entries in IBI buffer is greater than or equal to threshold - value specified by IBI_BUF_THLD field in BUFFER_THLD_CTRL - register. This interrupt will be cleared automatically - when number of entries in IBI buffer is less than threshold - value. */ - __IM uint32_t CMD_BUF_EMPTY_THLD_INT_ST : 1;/*!< This interrupt is generated when number of empty locations in - command buffer is greater than or equal to threshold value - specified by CMD_EMPTY_BUF_THLD field in BUFFER_THLD_CTRL - register. This interrupt will be cleared automatically - when number of empty locations in command buffer is less - than threshold value. */ - __IM uint32_t RESP_READY_INT_ST : 1; /*!< This interrupt is generated when number of entries in response - buffer is greater than or equal to threshold value specified - by RESP_BUF_THLD field in BUFFER_THLD_CTRL register. This - interrupt will be cleared automatically when number of - entries in response buffer is less than threshold value. */ - __IM uint32_t NXT_CMD_REQ_ERR_INT_ST : 1;/*!< This interrupt is generated if toc is 0(master will restart - next command), but command buf is empty. */ - __IM uint32_t TRANSFER_ERR_INT_ST : 1; /*!< This interrupt is generated if any error occurs during transfer. - The error type will be specified in the response packet - associated with the command (in ERR_STATUS field of RESPONSE_BUFFER_PORT - register). This bit can be cleared by writing 1'h1. */ - __IM uint32_t TRANSFER_COMPLETE_INT_ST : 1;/*!< NA */ - __IM uint32_t COMMAND_DONE_INT_ST : 1; /*!< NA */ - __IM uint32_t DETECT_START_INT_ST : 1; /*!< NA */ - __IM uint32_t RESP_BUF_OVF_INT_ST : 1; /*!< NA */ - __IM uint32_t IBI_DATA_BUF_OVF_INT_ST : 1;/*!< NA */ - __IM uint32_t IBI_STATUS_BUF_OVF_INT_ST : 1;/*!< NA */ - __IM uint32_t IBI_HANDLE_DONE_INT_ST : 1;/*!< NA */ - __IM uint32_t IBI_DETECT_INT_ST : 1; /*!< NA */ - __IM uint32_t CMD_CCC_MISMATCH_INT_ST : 1;/*!< NA */ - uint32_t : 16; - } bit; - } INT_ST; - - union { - __IOM uint32_t reg; /*!< The Interrupt status will be updated in INTR_STATUS register - if corresponding Status Enable bit set. */ - - struct { - __IOM uint32_t TX_DATA_BUF_THLD_INT_ENA : 1;/*!< Transmit Buffer threshold status enable. */ - __IOM uint32_t RX_DATA_BUF_THLD_INT_ENA : 1;/*!< Receive Buffer threshold status enable. */ - __IOM uint32_t IBI_STATUS_THLD_INT_ENA : 1;/*!< Only used in master mode. IBI Buffer threshold status enable. */ - __IOM uint32_t CMD_BUF_EMPTY_THLD_INT_ENA : 1;/*!< Command buffer ready status enable. */ - __IOM uint32_t RESP_READY_INT_ENA : 1; /*!< Response buffer ready status enable. */ - __IOM uint32_t NXT_CMD_REQ_ERR_INT_ENA : 1;/*!< next command request error status enable */ - __IOM uint32_t TRANSFER_ERR_INT_ENA : 1; /*!< Transfer error status enable */ - __IOM uint32_t TRANSFER_COMPLETE_INT_ENA : 1;/*!< NA */ - __IOM uint32_t COMMAND_DONE_INT_ENA : 1; /*!< NA */ - __IOM uint32_t DETECT_START_INT_ENA : 1; /*!< NA */ - __IOM uint32_t RESP_BUF_OVF_INT_ENA : 1; /*!< NA */ - __IOM uint32_t IBI_DATA_BUF_OVF_INT_ENA : 1;/*!< NA */ - __IOM uint32_t IBI_STATUS_BUF_OVF_INT_ENA : 1;/*!< NA */ - __IOM uint32_t IBI_HANDLE_DONE_INT_ENA : 1;/*!< NA */ - __IOM uint32_t IBI_DETECT_INT_ENA : 1; /*!< NA */ - __IOM uint32_t CMD_CCC_MISMATCH_INT_ENA : 1;/*!< NA */ - uint32_t : 16; - } bit; - } INT_ST_ENA; - __IM uint32_t RESERVED1; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __OM uint32_t REG_CORE_SOFT_RST : 1; /*!< NA */ - __IOM uint32_t REG_CMD_BUF_RST : 1; /*!< NA */ - __IOM uint32_t REG_RESP_BUF_RST : 1; /*!< NA */ - __IOM uint32_t REG_TX_DATA_BUF_BUF_RST : 1;/*!< NA */ - __IOM uint32_t REG_RX_DATA_BUF_RST : 1; /*!< NA */ - __IOM uint32_t REG_IBI_DATA_BUF_RST : 1; /*!< NA */ - __IOM uint32_t REG_IBI_STATUS_BUF_RST : 1;/*!< NA */ - uint32_t : 25; - } bit; - } RESET_CTRL; - - union { - __IOM uint32_t reg; /*!< BUFFER_STATUS_LEVEL reflects the status level of Buffers in - the controller. */ - - struct { - __IM uint32_t CMD_BUF_EMPTY_CNT : 5; /*!< Command Buffer Empty Locations contains the number of empty - locations in the command buffer. */ - uint32_t : 3; - __IM uint32_t RESP_BUF_CNT : 4; /*!< Response Buffer Level Value contains the number of valid data - entries in the response buffer. */ - uint32_t : 4; - __IM uint32_t IBI_DATA_BUF_CNT : 4; /*!< IBI Buffer Level Value contains the number of valid entries - in the IBI Buffer. This is field is used in master mode. */ - uint32_t : 4; - __IM uint32_t IBI_STATUS_BUF_CNT : 4; /*!< IBI Buffer Status Count contains the number of IBI status entries - in the IBI Buffer. This field is used in master mode. */ - uint32_t : 4; - } bit; - } BUFFER_STATUS_LEVEL; - - union { - __IOM uint32_t reg; /*!< DATA_BUFFER_STATUS_LEVEL reflects the status level of the Buffers - in the controller. */ - - struct { - __IM uint32_t TX_DATA_BUF_EMPTY_CNT : 6; /*!< Transmit Buffer Empty Level Value contains the number of empty - locations in the transmit Buffer. */ - uint32_t : 10; - __IM uint32_t RX_DATA_BUF_CNT : 6; /*!< Receive Buffer Level value contains the number of valid data - entries in the receive buffer. */ - uint32_t : 10; - } bit; - } DATA_BUFFER_STATUS_LEVEL; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t SDA_LVL : 1; /*!< This bit is used to check the SCL line level to recover from - error and for debugging. This bit reflects the value of - synchronized scl_in_a. */ - __IM uint32_t SCL_LVL : 1; /*!< This bit is used to check the SDA line level to recover from - error and for debugging. This bit reflects the value of - synchronized sda_in_a. */ - __IM uint32_t BUS_BUSY : 1; /*!< NA */ - __IM uint32_t BUS_FREE : 1; /*!< NA */ - uint32_t : 5; - __IM uint32_t CMD_TID : 4; /*!< NA */ - __IM uint32_t SCL_GEN_FSM_STATE : 3; /*!< NA */ - __IM uint32_t IBI_EV_HANDLE_FSM_STATE : 3;/*!< NA */ - __IM uint32_t I2C_MODE_FSM_STATE : 3; /*!< NA */ - __IM uint32_t SDR_MODE_FSM_STATE : 4; /*!< NA */ - __IM uint32_t DAA_MODE_FSM_STATE : 3; /*!< Reflects whether the Master Controller is in IDLE or not. This - bit will be set when all the buffer(Command, Response, - IBI, Transmit, Receive) are empty along with the Master - State machine is in idle state. 0X0: not in idle 0x1: in - idle */ - __IM uint32_t MAIN_FSM_STATE : 3; /*!< NA */ - } bit; - } PRESENT_STATE0; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t DATA_BYTE_CNT : 16; /*!< Present transfer data byte cnt: tx data byte cnt if write rx - data byte cnt if read ibi data byte cnt if IBI handle. */ - uint32_t : 16; - } bit; - } PRESENT_STATE1; - - union { - __IOM uint32_t reg; /*!< Pointer for Device Address Table */ - - struct { - __IOM uint32_t REG_DCT_DAA_INIT_INDEX : 4;/*!< Reserved */ - __IOM uint32_t REG_DAT_DAA_INIT_INDEX : 4;/*!< NA */ - __IM uint32_t PRESENT_DCT_INDEX : 4; /*!< NA */ - __IM uint32_t PRESENT_DAT_INDEX : 4; /*!< NA */ - uint32_t : 16; - } bit; - } DEVICE_TABLE; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_RESP_BUF_TO_VALUE : 5; /*!< NA */ - __IOM uint32_t REG_RESP_BUF_TO_EN : 1; /*!< NA */ - __IOM uint32_t REG_IBI_DATA_BUF_TO_VALUE : 5;/*!< NA */ - __IOM uint32_t REG_IBI_DATA_BUF_TO_EN : 1;/*!< NA */ - __IOM uint32_t REG_IBI_STATUS_BUF_TO_VALUE : 5;/*!< NA */ - __IOM uint32_t REG_IBI_STATUS_BUF_TO_EN : 1;/*!< NA */ - __IOM uint32_t REG_RX_DATA_BUF_TO_VALUE : 5;/*!< NA */ - __IOM uint32_t REG_RX_DATA_BUF_TO_EN : 1; /*!< NA */ - uint32_t : 8; - } bit; - } TIME_OUT_VALUE; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_I3C_MST_OD_LOW_PERIOD : 16;/*!< SCL Open-Drain low count for I3C transfers targeted to I3C devices. */ - __IOM uint32_t REG_I3C_MST_OD_HIGH_PERIOD : 16;/*!< SCL Open-Drain High count for I3C transfers targeted to I3C - devices. */ - } bit; - } SCL_I3C_MST_OD_TIME; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_I3C_MST_PP_LOW_PERIOD : 8;/*!< NA */ - uint32_t : 8; - __IOM uint32_t REG_I3C_MST_PP_HIGH_PERIOD : 8;/*!< NA */ - uint32_t : 8; - } bit; - } SCL_I3C_MST_PP_TIME; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_I2C_FM_LOW_PERIOD : 16;/*!< NA */ - __IOM uint32_t REG_I2C_FM_HIGH_PERIOD : 16;/*!< The SCL open-drain low count timing for I2C Fast Mode transfers. */ - } bit; - } SCL_I2C_FM_TIME; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_I2C_FMP_LOW_PERIOD : 16;/*!< NA */ - __IOM uint32_t REG_I2C_FMP_HIGH_PERIOD : 8;/*!< NA */ - uint32_t : 8; - } bit; - } SCL_I2C_FMP_TIME; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_I3C_MST_EXT_LOW_PERIOD1 : 8;/*!< NA */ - __IOM uint32_t REG_I3C_MST_EXT_LOW_PERIOD2 : 8;/*!< NA */ - __IOM uint32_t REG_I3C_MST_EXT_LOW_PERIOD3 : 8;/*!< NA */ - __IOM uint32_t REG_I3C_MST_EXT_LOW_PERIOD4 : 8;/*!< NA */ - } bit; - } SCL_EXT_LOW_TIME; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_SDA_OD_SAMPLE_TIME : 9;/*!< It is used to adjust sda sample point when scl high under open - drain speed */ - __IOM uint32_t REG_SDA_PP_SAMPLE_TIME : 5;/*!< It is used to adjust sda sample point when scl high under push - pull speed */ - uint32_t : 18; - } bit; - } SDA_SAMPLE_TIME; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_SDA_OD_TX_HOLD_TIME : 9;/*!< It is used to adjust sda drive point after scl neg under open - drain speed */ - __IOM uint32_t REG_SDA_PP_TX_HOLD_TIME : 5;/*!< It is used to adjust sda dirve point after scl neg under push - pull speed */ - uint32_t : 18; - } bit; - } SDA_HOLD_TIME; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_SCL_START_HOLD_TIME : 9;/*!< I2C_SCL_START_HOLD_TIME */ - __IOM uint32_t REG_START_DET_HOLD_TIME : 2;/*!< NA */ - uint32_t : 21; - } bit; - } SCL_START_HOLD; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_SCL_RSTART_SETUP_TIME : 9;/*!< I2C_SCL_RSTART_SETUP_TIME */ - uint32_t : 23; - } bit; - } SCL_RSTART_SETUP; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_SCL_STOP_HOLD_TIME : 9;/*!< I2C_SCL_STOP_HOLD_TIME */ - uint32_t : 23; - } bit; - } SCL_STOP_HOLD; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_SCL_STOP_SETUP_TIME : 9;/*!< I2C_SCL_STOP_SETUP_TIME */ - uint32_t : 23; - } bit; - } SCL_STOP_SETUP; - __IM uint32_t RESERVED2; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_BUS_FREE_TIME : 16; /*!< I3C Bus Free Count Value. This field is used only in Master - mode. In pure Bus System, this field represents tCAS. In - Mixed Bus System, this field is expected to be programmed - to tLOW of I2C Timing. */ - uint32_t : 16; - } bit; - } BUS_FREE_TIME; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_I3C_MST_TERMN_T_EXT_LOW_TIME : 8;/*!< NA */ - uint32_t : 24; - } bit; - } SCL_TERMN_T_EXT_LOW_TIME; - __IM uint32_t RESERVED3[2]; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_I3C_MST_VER_ID : 32; /*!< This field indicates the controller current release number that - is read by an application. */ - } bit; - } VER_ID; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_I3C_MST_VER_TYPE : 32; /*!< This field indicates the controller current release type that - is read by an application. */ - } bit; - } VER_TYPE; - __IM uint32_t RESERVED4; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_I3C_MST_FPGA_DEBUG_PROBE : 32;/*!< For Debug Probe Test on FPGA */ - } bit; - } FPGA_DEBUG_PROBE; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_RND_ECO_EN : 1; /*!< NA */ - __IM uint32_t RND_ECO_RESULT : 1; /*!< NA */ - uint32_t : 30; - } bit; - } RND_ECO_CS; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_RND_ECO_LOW : 32; /*!< NA */ - } bit; - } RND_ECO_LOW; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_RND_ECO_HIGH : 32; /*!< NA */ - } bit; - } RND_ECO_HIGH; -} I3C_MST_Type; /*!< Size = 188 (0xbc) */ - - - -/* =========================================================================================================================== */ -/* ================ I3C_MST_MEM ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief I3C_MST_MEM Peripheral (I3C_MST_MEM) - */ - -typedef struct { /*!< I3C_MST_MEM Structure */ - __IM uint32_t RESERVED[2]; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_COMMAND : 32; /*!< Contains a Command Descriptor structure that depends on the - requested transfer type. Command Descriptor structure is - used to schedule the transfers to devices on I3C bus. */ - } bit; - } COMMAND_BUF_PORT; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t RESPONSE : 32; /*!< The Response Buffer can be read through this register. The response - status for each Command is written into the Response Buffer - by the controller if ROC (Response On Completion) bit is - set or if transfer error has occurred. The response buffer - can be read through this register. */ - } bit; - } RESPONSE_BUF_PORT; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t RX_DATA_PORT : 32; /*!< Receive Data Port. Receive data is mapped to the Rx-data buffer - and receive data is always packed in 4-byte aligned data - words. If the length of data transfer is not aligned to - 4-bytes boundary, then there will be extra(unused) bytes(the - additional data bytes have to be ignored) at the end of - the transferred data. The valid data must be identified - using the DATA_LENGTH filed in the Response Descriptor. */ - } bit; - } RX_DATA_PORT; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_TX_DATA_PORT : 32; /*!< Transmit Data Port. Transmit data is mapped to the Tx-data buffer - and transmit data is always packed in 4-byte aligned data - words. If the length of data transfer is not aligned to - 4-bytes boundary, then there will be extra(unused) bytes(the - additional data bytes have to be ignored) at the end of - the transferred data. The valid data must be identified - using the DATA_LENGTH filed in the Response Descriptor. */ - } bit; - } TX_DATA_PORT; - - union { - __IOM uint32_t reg; /*!< In-Band Interrupt Buffer Status/Data Register. When receiving - an IBI, IBI_PORT is used to both: Read the IBI Status Read - the IBI Data(which is raw/opaque data) */ - - struct { - __IM uint32_t DATA_LENGTH : 8; /*!< This field represents the length of data received along with - IBI, in bytes. */ - __IM uint32_t IBI_ID : 8; /*!< IBI Identifier. The byte received after START which includes - the address the R/W bit: Device address and R/W bit in - case of Slave Interrupt or Master Request. */ - uint32_t : 12; - __IM uint32_t IBI_STS : 1; /*!< IBI received data/status. IBI Data register is mapped to the - IBI Buffer. The IBI Data is always packed in4-byte aligned - and put to the IBI Buffer. This register When read from, - reads the data from the IBI buffer. IBI Status register - when read from, returns the data from the IBI Buffer and - indicates how the controller responded to incoming IBI(SIR, - MR and HJ). */ - uint32_t : 3; - } bit; - } IBI_STATUS_BUF; - __IM uint32_t RESERVED1[9]; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t IBI_DATA : 32; /*!< NA */ - } bit; - } IBI_DATA_BUF; - __IM uint32_t RESERVED2[31]; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_DAT_DEV1_STATIC_ADDR : 7;/*!< NA */ - uint32_t : 9; - __IOM uint32_t REG_DAT_DEV1_DYNAMIC_ADDR : 8;/*!< Device Dynamic Address with parity, The MSB,bit[23], should - be programmed with parity of dynamic address. */ - uint32_t : 5; - __IOM uint32_t REG_DAT_DEV1_NACK_RETRY_CNT : 2;/*!< This field is used to set the Device NACK Retry count for the - particular device. If the Device NACK's for the device - address, the controller automatically retries the same - device until this count expires. If the Slave does not - ACK for the mentioned number of retries, then controller - generates an error response and move to the Halt state. */ - __IOM uint32_t REG_DAT_DEV1_I2C : 1; /*!< Legacy I2C device or not. This bit should be set to 1 if the - device is a legacy I2C device. */ - } bit; - } DEV_ADDR_TABLE1_LOC; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_DAT_DEV2_STATIC_ADDR : 7;/*!< NA */ - uint32_t : 9; - __IOM uint32_t REG_DAT_DEV2_DYNAMIC_ADDR : 8;/*!< Device Dynamic Address with parity, The MSB,bit[23], should - be programmed with parity of dynamic address. */ - uint32_t : 5; - __IOM uint32_t REG_DAT_DEV2_NACK_RETRY_CNT : 2;/*!< This field is used to set the Device NACK Retry count for the - particular device. If the Device NACK's for the device - address, the controller automatically retries the same - device until this count expires. If the Slave does not - ACK for the mentioned number of retries, then controller - generates an error response and move to the Halt state. */ - __IOM uint32_t REG_DAT_DEV2_I2C : 1; /*!< Legacy I2C device or not. This bit should be set to 1 if the - device is a legacy I2C device. */ - } bit; - } DEV_ADDR_TABLE2_LOC; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_DAT_DEV3_STATIC_ADDR : 7;/*!< NA */ - uint32_t : 9; - __IOM uint32_t REG_DAT_DEV3_DYNAMIC_ADDR : 8;/*!< Device Dynamic Address with parity, The MSB,bit[23], should - be programmed with parity of dynamic address. */ - uint32_t : 5; - __IOM uint32_t REG_DAT_DEV3_NACK_RETRY_CNT : 2;/*!< This field is used to set the Device NACK Retry count for the - particular device. If the Device NACK's for the device - address, the controller automatically retries the same - device until this count expires. If the Slave does not - ACK for the mentioned number of retries, then controller - generates an error response and move to the Halt state. */ - __IOM uint32_t REG_DAT_DEV3_I2C : 1; /*!< Legacy I2C device or not. This bit should be set to 1 if the - device is a legacy I2C device. */ - } bit; - } DEV_ADDR_TABLE3_LOC; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_DAT_DEV4_STATIC_ADDR : 7;/*!< NA */ - uint32_t : 9; - __IOM uint32_t REG_DAT_DEV4_DYNAMIC_ADDR : 8;/*!< Device Dynamic Address with parity, The MSB,bit[23], should - be programmed with parity of dynamic address. */ - uint32_t : 5; - __IOM uint32_t REG_DAT_DEV4_NACK_RETRY_CNT : 2;/*!< This field is used to set the Device NACK Retry count for the - particular device. If the Device NACK's for the device - address, the controller automatically retries the same - device until this count expires. If the Slave does not - ACK for the mentioned number of retries, then controller - generates an error response and move to the Halt state. */ - __IOM uint32_t REG_DAT_DEV4_I2C : 1; /*!< Legacy I2C device or not. This bit should be set to 1 if the - device is a legacy I2C device. */ - } bit; - } DEV_ADDR_TABLE4_LOC; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_DAT_DEV5_STATIC_ADDR : 7;/*!< NA */ - uint32_t : 9; - __IOM uint32_t REG_DAT_DEV5_DYNAMIC_ADDR : 8;/*!< Device Dynamic Address with parity, The MSB,bit[23], should - be programmed with parity of dynamic address. */ - uint32_t : 5; - __IOM uint32_t REG_DAT_DEV5_NACK_RETRY_CNT : 2;/*!< This field is used to set the Device NACK Retry count for the - particular device. If the Device NACK's for the device - address, the controller automatically retries the same - device until this count expires. If the Slave does not - ACK for the mentioned number of retries, then controller - generates an error response and move to the Halt state. */ - __IOM uint32_t REG_DAT_DEV5_I2C : 1; /*!< Legacy I2C device or not. This bit should be set to 1 if the - device is a legacy I2C device. */ - } bit; - } DEV_ADDR_TABLE5_LOC; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_DAT_DEV6_STATIC_ADDR : 7;/*!< NA */ - uint32_t : 9; - __IOM uint32_t REG_DAT_DEV6_DYNAMIC_ADDR : 8;/*!< Device Dynamic Address with parity, The MSB,bit[23], should - be programmed with parity of dynamic address. */ - uint32_t : 5; - __IOM uint32_t REG_DAT_DEV6_NACK_RETRY_CNT : 2;/*!< This field is used to set the Device NACK Retry count for the - particular device. If the Device NACK's for the device - address, the controller automatically retries the same - device until this count expires. If the Slave does not - ACK for the mentioned number of retries, then controller - generates an error response and move to the Halt state. */ - __IOM uint32_t REG_DAT_DEV6_I2C : 1; /*!< Legacy I2C device or not. This bit should be set to 1 if the - device is a legacy I2C device. */ - } bit; - } DEV_ADDR_TABLE6_LOC; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_DAT_DEV7_STATIC_ADDR : 7;/*!< NA */ - uint32_t : 9; - __IOM uint32_t REG_DAT_DEV7_DYNAMIC_ADDR : 8;/*!< Device Dynamic Address with parity, The MSB,bit[23], should - be programmed with parity of dynamic address. */ - uint32_t : 5; - __IOM uint32_t REG_DAT_DEV7_NACK_RETRY_CNT : 2;/*!< This field is used to set the Device NACK Retry count for the - particular device. If the Device NACK's for the device - address, the controller automatically retries the same - device until this count expires. If the Slave does not - ACK for the mentioned number of retries, then controller - generates an error response and move to the Halt state. */ - __IOM uint32_t REG_DAT_DEV7_I2C : 1; /*!< Legacy I2C device or not. This bit should be set to 1 if the - device is a legacy I2C device. */ - } bit; - } DEV_ADDR_TABLE7_LOC; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_DAT_DEV8_STATIC_ADDR : 7;/*!< NA */ - uint32_t : 9; - __IOM uint32_t REG_DAT_DEV8_DYNAMIC_ADDR : 8;/*!< Device Dynamic Address with parity, The MSB,bit[23], should - be programmed with parity of dynamic address. */ - uint32_t : 5; - __IOM uint32_t REG_DAT_DEV8_NACK_RETRY_CNT : 2;/*!< This field is used to set the Device NACK Retry count for the - particular device. If the Device NACK's for the device - address, the controller automatically retries the same - device until this count expires. If the Slave does not - ACK for the mentioned number of retries, then controller - generates an error response and move to the Halt state. */ - __IOM uint32_t REG_DAT_DEV8_I2C : 1; /*!< Legacy I2C device or not. This bit should be set to 1 if the - device is a legacy I2C device. */ - } bit; - } DEV_ADDR_TABLE8_LOC; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_DAT_DEV9_STATIC_ADDR : 7;/*!< NA */ - uint32_t : 9; - __IOM uint32_t REG_DAT_DEV9_DYNAMIC_ADDR : 8;/*!< Device Dynamic Address with parity, The MSB,bit[23], should - be programmed with parity of dynamic address. */ - uint32_t : 5; - __IOM uint32_t REG_DAT_DEV9_NACK_RETRY_CNT : 2;/*!< This field is used to set the Device NACK Retry count for the - particular device. If the Device NACK's for the device - address, the controller automatically retries the same - device until this count expires. If the Slave does not - ACK for the mentioned number of retries, then controller - generates an error response and move to the Halt state. */ - __IOM uint32_t REG_DAT_DEV9_I2C : 1; /*!< Legacy I2C device or not. This bit should be set to 1 if the - device is a legacy I2C device. */ - } bit; - } DEV_ADDR_TABLE9_LOC; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_DAT_DEV10_STATIC_ADDR : 7;/*!< NA */ - uint32_t : 9; - __IOM uint32_t REG_DAT_DEV10_DYNAMIC_ADDR : 8;/*!< Device Dynamic Address with parity, The MSB,bit[23], should - be programmed with parity of dynamic address. */ - uint32_t : 5; - __IOM uint32_t REG_DAT_DEV10_NACK_RETRY_CNT : 2;/*!< This field is used to set the Device NACK Retry count for the - particular device. If the Device NACK's for the device - address, the controller automatically retries the same - device until this count expires. If the Slave does not - ACK for the mentioned number of retries, then controller - generates an error response and move to the Halt state. */ - __IOM uint32_t REG_DAT_DEV10_I2C : 1; /*!< Legacy I2C device or not. This bit should be set to 1 if the - device is a legacy I2C device. */ - } bit; - } DEV_ADDR_TABLE10_LOC; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_DAT_DEV11_STATIC_ADDR : 7;/*!< NA */ - uint32_t : 9; - __IOM uint32_t REG_DAT_DEV11_DYNAMIC_ADDR : 8;/*!< Device Dynamic Address with parity, The MSB,bit[23], should - be programmed with parity of dynamic address. */ - uint32_t : 5; - __IOM uint32_t REG_DAT_DEV11_NACK_RETRY_CNT : 2;/*!< This field is used to set the Device NACK Retry count for the - particular device. If the Device NACK's for the device - address, the controller automatically retries the same - device until this count expires. If the Slave does not - ACK for the mentioned number of retries, then controller - generates an error response and move to the Halt state. */ - __IOM uint32_t REG_DAT_DEV11_I2C : 1; /*!< Legacy I2C device or not. This bit should be set to 1 if the - device is a legacy I2C device. */ - } bit; - } DEV_ADDR_TABLE11_LOC; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t REG_DAT_DEV12_STATIC_ADDR : 7;/*!< NA */ - uint32_t : 9; - __IOM uint32_t REG_DAT_DEV12_DYNAMIC_ADDR : 8;/*!< Device Dynamic Address with parity, The MSB,bit[23], should - be programmed with parity of dynamic address. */ - uint32_t : 5; - __IOM uint32_t REG_DAT_DEV12_NACK_RETRY_CNT : 2;/*!< This field is used to set the Device NACK Retry count for the - particular device. If the Device NACK's for the device - address, the controller automatically retries the same - device until this count expires. If the Slave does not - ACK for the mentioned number of retries, then controller - generates an error response and move to the Halt state. */ - __IOM uint32_t REG_DAT_DEV12_I2C : 1; /*!< Legacy I2C device or not. This bit should be set to 1 if the - device is a legacy I2C device. */ - } bit; - } DEV_ADDR_TABLE12_LOC; - __IM uint32_t RESERVED3[4]; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t DCT_DEV1_LOC1 : 32; /*!< NA */ - } bit; - } DEV_CHAR_TABLE1_LOC1; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t DCT_DEV1_LOC2 : 32; /*!< NA */ - } bit; - } DEV_CHAR_TABLE1_LOC2; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t DCT_DEV1_LOC3 : 32; /*!< NA */ - } bit; - } DEV_CHAR_TABLE1_LOC3; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t DCT_DEV1_LOC4 : 32; /*!< NA */ - } bit; - } DEV_CHAR_TABLE1_LOC4; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t DCT_DEV2_LOC1 : 32; /*!< NA */ - } bit; - } DEV_CHAR_TABLE2_LOC1; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t DCT_DEV2_LOC2 : 32; /*!< NA */ - } bit; - } DEV_CHAR_TABLE2_LOC2; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t DCT_DEV2_LOC3 : 32; /*!< NA */ - } bit; - } DEV_CHAR_TABLE2_LOC3; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t DCT_DEV2_LOC4 : 32; /*!< NA */ - } bit; - } DEV_CHAR_TABLE2_LOC4; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t DCT_DEV3_LOC1 : 32; /*!< NA */ - } bit; - } DEV_CHAR_TABLE3_LOC1; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t DCT_DEV3_LOC2 : 32; /*!< NA */ - } bit; - } DEV_CHAR_TABLE3_LOC2; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t DCT_DEV3_LOC3 : 32; /*!< NA */ - } bit; - } DEV_CHAR_TABLE3_LOC3; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t DCT_DEV3_LOC4 : 32; /*!< NA */ - } bit; - } DEV_CHAR_TABLE3_LOC4; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t DCT_DEV4_LOC1 : 32; /*!< NA */ - } bit; - } DEV_CHAR_TABLE4_LOC1; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t DCT_DEV4_LOC2 : 32; /*!< NA */ - } bit; - } DEV_CHAR_TABLE4_LOC2; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t DCT_DEV4_LOC3 : 32; /*!< NA */ - } bit; - } DEV_CHAR_TABLE4_LOC3; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t DCT_DEV4_LOC4 : 32; /*!< NA */ - } bit; - } DEV_CHAR_TABLE4_LOC4; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t DCT_DEV5_LOC1 : 32; /*!< NA */ - } bit; - } DEV_CHAR_TABLE5_LOC1; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t DCT_DEV5_LOC2 : 32; /*!< NA */ - } bit; - } DEV_CHAR_TABLE5_LOC2; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t DCT_DEV5_LOC3 : 32; /*!< NA */ - } bit; - } DEV_CHAR_TABLE5_LOC3; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t DCT_DEV5_LOC4 : 32; /*!< NA */ - } bit; - } DEV_CHAR_TABLE5_LOC4; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t DCT_DEV6_LOC1 : 32; /*!< NA */ - } bit; - } DEV_CHAR_TABLE6_LOC1; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t DCT_DEV6_LOC2 : 32; /*!< NA */ - } bit; - } DEV_CHAR_TABLE6_LOC2; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t DCT_DEV6_LOC3 : 32; /*!< NA */ - } bit; - } DEV_CHAR_TABLE6_LOC3; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t DCT_DEV6_LOC4 : 32; /*!< NA */ - } bit; - } DEV_CHAR_TABLE6_LOC4; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t DCT_DEV7_LOC1 : 32; /*!< NA */ - } bit; - } DEV_CHAR_TABLE7_LOC1; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t DCT_DEV7_LOC2 : 32; /*!< NA */ - } bit; - } DEV_CHAR_TABLE7_LOC2; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t DCT_DEV7_LOC3 : 32; /*!< NA */ - } bit; - } DEV_CHAR_TABLE7_LOC3; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t DCT_DEV7_LOC4 : 32; /*!< NA */ - } bit; - } DEV_CHAR_TABLE7_LOC4; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t DCT_DEV8_LOC1 : 32; /*!< NA */ - } bit; - } DEV_CHAR_TABLE8_LOC1; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t DCT_DEV8_LOC2 : 32; /*!< NA */ - } bit; - } DEV_CHAR_TABLE8_LOC2; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t DCT_DEV8_LOC3 : 32; /*!< NA */ - } bit; - } DEV_CHAR_TABLE8_LOC3; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t DCT_DEV8_LOC4 : 32; /*!< NA */ - } bit; - } DEV_CHAR_TABLE8_LOC4; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t DCT_DEV9_LOC1 : 32; /*!< NA */ - } bit; - } DEV_CHAR_TABLE9_LOC1; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t DCT_DEV9_LOC2 : 32; /*!< NA */ - } bit; - } DEV_CHAR_TABLE9_LOC2; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t DCT_DEV9_LOC3 : 32; /*!< NA */ - } bit; - } DEV_CHAR_TABLE9_LOC3; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t DCT_DEV9_LOC4 : 32; /*!< NA */ - } bit; - } DEV_CHAR_TABLE9_LOC4; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t DCT_DEV10_LOC1 : 32; /*!< NA */ - } bit; - } DEV_CHAR_TABLE10_LOC1; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t DCT_DEV10_LOC2 : 32; /*!< NA */ - } bit; - } DEV_CHAR_TABLE10_LOC2; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t DCT_DEV10_LOC3 : 32; /*!< NA */ - } bit; - } DEV_CHAR_TABLE10_LOC3; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t DCT_DEV10_LOC4 : 32; /*!< NA */ - } bit; - } DEV_CHAR_TABLE10_LOC4; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t DCT_DEV11_LOC1 : 32; /*!< NA */ - } bit; - } DEV_CHAR_TABLE11_LOC1; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t DCT_DEV11_LOC2 : 32; /*!< NA */ - } bit; - } DEV_CHAR_TABLE11_LOC2; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t DCT_DEV11_LOC3 : 32; /*!< NA */ - } bit; - } DEV_CHAR_TABLE11_LOC3; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t DCT_DEV11_LOC4 : 32; /*!< NA */ - } bit; - } DEV_CHAR_TABLE11_LOC4; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t DCT_DEV12_LOC1 : 32; /*!< NA */ - } bit; - } DEV_CHAR_TABLE12_LOC1; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t DCT_DEV12_LOC2 : 32; /*!< NA */ - } bit; - } DEV_CHAR_TABLE12_LOC2; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t DCT_DEV12_LOC3 : 32; /*!< NA */ - } bit; - } DEV_CHAR_TABLE12_LOC3; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t DCT_DEV12_LOC4 : 32; /*!< NA */ - } bit; - } DEV_CHAR_TABLE12_LOC4; -} I3C_MST_MEM_Type; /*!< Size = 448 (0x1c0) */ - - - -/* =========================================================================================================================== */ -/* ================ I3C_SLV ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief I3C Controller (Slave) (I3C_SLV) - */ - -typedef struct { /*!< I3C_SLV Structure */ - __IM uint32_t RESERVED; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t SLVENA : 1; /*!< 1: allow the slave to operate on i2c or i3c bus. 0: the slave - will ignore the bus. This should be not set until registers - such as PARTNO, IDEXT and the like are set 1st -if used- - since they impact data to the master */ - __IOM uint32_t NACK : 1; /*!< 1:the slave will NACK all requests to it except CCC broadcast. - This should be used with caution as the Master may determine - the slave is missing if overused. */ - __IOM uint32_t MATCHSS : 1; /*!< 1: the START and STOP sticky STATUS bits will only be set if - MATCHED is set..This allows START and STOP to be used to - detect end of a message to /from this slave. */ - __IOM uint32_t S0IGNORE : 1; /*!< If 1, the Slave will not detect S0 or S1 errors and so not lock - up waiting on an Exit Pattern. This should only be used - when the bus will not use HDR. */ - __IOM uint32_t DDROK : 1; /*!< NA */ - uint32_t : 3; - __IOM uint32_t IDRAND : 1; /*!< NA */ - __IOM uint32_t OFFLINE : 1; /*!< NA */ - uint32_t : 6; - __IOM uint32_t BAMATCH : 8; /*!< Bus Available condition match value for current ???Slow clock???. - This provides the count of the slow clock to count out - 1us (or more) to allow an IBI to drive SDA Low when the - Master is not doing so. The max width , and so max value, - is controlled by the block. Only if enabled for events - such IBI or MR or HJ, and if enabled to provide this as - a register. With is limited to CLK_SLOW_BITS */ - uint32_t : 1; - __IOM uint32_t SADDR : 7; /*!< If allowed by the block:sets i2c 7 bits static address,else - should be 0. If enabled to use one and to be provided by - SW. Block may provide in HW as well. */ - } bit; - } CONFIG; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t STNOTSTOP : 1; /*!< Is 1 if bus is busy(activity) and 0 when in a STOP condition. - Other bits may also set when busy. Note that this can also - be true from an S0 or S1 error, which waits for an Exit - Pattern. */ - __IM uint32_t STMSG : 1; /*!< Is 1 if this bus Slave is listening to the bus traffic or repsonding, - If STNOSTOP=1, then this will be 0 when a non-matching - address seen until next respeated START it STOP. */ - __IM uint32_t STCCCH : 1; /*!< Is 1 if a CCC message is being handled automatically. */ - __IM uint32_t STREQRD : 1; /*!< 1 if the req in process is an sdr read from this slave or an - IBI is being pushed out, */ - __IM uint32_t STREQWR : 1; /*!< NA */ - __IM uint32_t STDAA : 1; /*!< NA */ - __IM uint32_t STHDR : 1; /*!< NA */ - uint32_t : 1; - __IOM uint32_t START : 1; /*!< NA */ - __IOM uint32_t MATCHED : 1; /*!< NA */ - __IOM uint32_t STOP : 1; /*!< NA */ - __IM uint32_t RXPEND : 1; /*!< Receiving a message from master,which is not being handled by - block(not a CCC internally processed). For all but External - FIFO, this uses DATACTRL RXTRIG, which defaults to not-empty. - If DMA is enabled for RX, DMA will be signaled as well. - Will self-clear if data is read(FIFO and non-FIFO) */ - __IM uint32_t TXNOTFULL : 1; /*!< Is 1 when the To-bus buffer/FIFO can accept more data to go - out. Defau:1. For all but External FIFO, this uses DATACTRL - TXTRIG,which defaults to not-full. If DMA is enabled for - TX, it will also be signaled to provide more. */ - __IOM uint32_t DACHG : 1; /*!< The Slv Dynamic Address has been assigned, reassigned, or reset(lost) - and is now in that state of being valid or none. Actual - DA can be seen in the DYNADDR register. Note that this - will also be used when MAP Auto feature is configured. - This will be changing one or more MAP items. See DYNADDR - and/or MAPCTRLn. DYNAADDR for the main DA(0) will indicate - if last change was due to Auto MAP. */ - __IOM uint32_t CCC : 1; /*!< A common -command-code(CCC), not handled by block, has been - received. This acts differently between: *Broadcasted ones, - which will then also correspond with RXPEND and the 1st - byte will be the CCC(command) . *Direct ones, which may - never be directed to this device. If it is, then the TXSEND - or RXPEND will be triggered with this end the RXPEND will - contain the command. */ - __IM uint32_t ERRWARN : 1; /*!< NA */ - __IOM uint32_t HDRMATCH : 1; /*!< NA */ - uint32_t : 15; - } bit; - } STATUS; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t SLV_EVENT : 2; /*!< If set to non-0, will request an event. Once requested, STATUS.EVENT - and EVDET will show the status as it progresses. Once completed, - the field will automatically return to 0. Once non-0, only - 0 can be written(to cancel) until done. 0: Normal mode. - If set to 0 after was a non-0 value, will cancel if not - already in flight. 1: start an IBI. This will try to push - through an IBI on the bus. If data associate with the IBI, - it will be drawn from the IBIDATA field. Note that if Time - control is enabled, this will include anytime control related - bytes further, the IBIDATA byte will have bit7 set to 1. */ - uint32_t : 1; - __IOM uint32_t EXTDATA : 1; /*!< reserved */ - __IOM uint32_t MAPIDX : 4; /*!< Index of Dynamic Address that IBI is for. This is 0 for the - main or base Dynamic Address, or can be any valid index. */ - __IOM uint32_t IBIDATA : 8; /*!< Data byte to go with an IBI, if enabled for it. If enabled (was - in BCR), then it is required. */ - __IOM uint32_t PENDINT : 4; /*!< Should be set to the pending interrupt that GETSTATUS CCC will - return. This should be maintained by the application if - used and configured, as the Master will read this. If not - configured, the GETSTATUS field will return 1 if an IBI - is pending, and 0 otherwise. */ - __IOM uint32_t ACTSTATE : 2; /*!< NA */ - uint32_t : 2; - __IOM uint32_t VENDINFO : 8; /*!< NA */ - } bit; - } CTRL; - - union { - __IOM uint32_t reg; /*!< INSET allows setting enables for interrupts(connecting the corresponding - STATUS source to causing an IRQ to the processor) */ - - struct { - uint32_t : 10; - __IOM uint32_t STOP_ENA : 1; /*!< Interrupt on STOP state on the bus. See Start as the preferred - interrupt when needed. This interrupt may not trigger for - quick STOP/START combination, as it relates to the state - of being stopped. */ - __IOM uint32_t RXPEND_ENA : 1; /*!< Interrupt when receiving a message from Master, which is not - being handled by the block (excludes CCCs being handled - automatically). If FIFO, then RX fullness trigger. If DMA, - then message end. */ - __IOM uint32_t TXSEND_ENA : 1; /*!< NA */ - uint32_t : 19; - } bit; - } INTSET; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - uint32_t : 10; - __OM uint32_t STOP_CLR : 1; /*!< Interrupt on STOP state on the bus. See Start as the preferred - interrupt when needed. This interrupt may not trigger for - quick STOP/START combination, as it relates to the state - of being stopped. */ - __OM uint32_t RXPEND_CLR : 1; /*!< Interrupt when receiving a message from Master, which is not - being handled by the block (excludes CCCs being handled - automatically). If FIFO, then RX fullness trigger. If DMA, - then message end. */ - __OM uint32_t TXSEND_CLR : 1; /*!< NA */ - uint32_t : 19; - } bit; - } INTCLR; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - uint32_t : 10; - __IM uint32_t STOP_MASK : 1; /*!< Interrupt on STOP state on the bus. See Start as the preferred - interrupt when needed. This interrupt may not trigger for - quick STOP/START combination, as it relates to the state - of being stopped. */ - __IM uint32_t RXPEND_MASK : 1; /*!< Interrupt when receiving a message from Master, which is not - being handled by the block (excludes CCCs being handled - automatically). If FIFO, then RX fullness trigger. If DMA, - then message end. */ - __IM uint32_t TXSEND_MASK : 1; /*!< NA */ - uint32_t : 19; - } bit; - } INTMASKED; - __IM uint32_t RESERVED1[4]; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __OM uint32_t FLUSHTB : 1; /*!< Flushes the from-bus buffer/FIFO. Not normally used */ - __OM uint32_t FLUSHFB : 1; /*!< Flushes the to-bus buffer/FIFO. Used when Master terminates - a to-bus (read) message prematurely */ - uint32_t : 1; - __OM uint32_t UNLOCK : 1; /*!< If this bit is not written 1, the register bits from 7 to 4 - are not changed on write. */ - __IOM uint32_t TXTRIG : 2; /*!< Trigger level for tx emptiness when FIFOed, Affects interrupt - and DMA(if enabled). The defaults is 3 */ - __IOM uint32_t RXTRIG : 2; /*!< Trigger level for rx fulless when FIFOed, Affects interrupt - and DMA(if enabled). The defaults is 3 */ - uint32_t : 8; - __IM uint32_t TXCOUNT : 5; /*!< NA */ - uint32_t : 3; - __IM uint32_t RXCOUNT : 5; /*!< NA */ - uint32_t : 1; - __IM uint32_t TXFULL : 1; /*!< NA */ - __IM uint32_t RXEMPTY : 1; /*!< NA */ - } bit; - } DATACTRL; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __OM uint32_t WDATAB : 8; /*!< NA */ - __OM uint32_t WDATA_END : 1; /*!< NA */ - uint32_t : 23; - } bit; - } WDATAB; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __OM uint32_t WDATABE : 8; /*!< NA */ - uint32_t : 24; - } bit; - } WDATABE; - __IM uint32_t RESERVED2[2]; - - union { - __IOM uint32_t reg; /*!< Read Byte Data (from-bus) register */ - - struct { - __IM uint32_t DATA0 : 8; /*!< This register allows reading a byte from the bus unless external - FIFO is used. A byte should not be read unless there is - data waiting, as indicated by the RXPEND bit being set - in the STATUS register */ - uint32_t : 24; - } bit; - } RDARAB; - __IM uint32_t RESERVED3; - - union { - __IOM uint32_t reg; /*!< Read Half-word Data (from-bus) register */ - - struct { - __IM uint32_t DATA_LSB : 8; /*!< NA */ - __IM uint32_t DATA_MSB : 8; /*!< This register allows reading a Half-word (byte pair) from the - bus unless external FIFO is used. A Half-word should not - be read unless there is at least 2 bytes of data waiting, - as indicated by the RX FIFO level trigger or RXCOUNT available - space in the DATACTRL register */ - uint32_t : 16; - } bit; - } RDATAH; - __IM uint32_t RESERVED4[4]; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t CAPABLITIES2 : 32; /*!< NA */ - } bit; - } CAPABILITIES2; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t CAPABLITIES : 32; /*!< NA */ - } bit; - } CAPABILITIES; - __IM uint32_t RESERVED5[2]; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t PARTNO : 32; /*!< NA */ - } bit; - } IDPARTNO; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t IDEXT : 32; /*!< NA */ - } bit; - } IDEXT; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t VID : 15; /*!< NA */ - uint32_t : 17; - } bit; - } VENDORID; -} I3C_SLV_Type; /*!< Size = 120 (0x78) */ - - - -/* =========================================================================================================================== */ -/* ================ AXI_ICM ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief AXI_ICM Peripheral (AXI_ICM) - */ - -typedef struct { /*!< AXI_ICM Structure */ - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t ICM_REG_VERID : 32; /*!< NA */ - } bit; - } VERID_FILEDS; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IM uint32_t ICM_REG_AXI_HWCFG_QOS_SUPPORT : 1;/*!< NA */ - __IM uint32_t ICM_REG_AXI_HWCFG_APB3_SUPPORT : 1;/*!< NA */ - __IM uint32_t ICM_REG_AXI_HWCFG_AXI4_SUPPORT : 1;/*!< NA */ - __IM uint32_t ICM_REG_AXI_HWCFG_LOCK_EN : 1;/*!< NA */ - __IM uint32_t ICM_REG_AXI_HWCFG_TRUST_ZONE_EN : 1;/*!< NA */ - __IM uint32_t ICM_REG_AXI_HWCFG_DECODER_TYPE : 1;/*!< NA */ - __IM uint32_t ICM_REG_AXI_HWCFG_REMAP_EN : 1;/*!< NA */ - __IM uint32_t ICM_REG_AXI_HWCFG_BI_DIR_CMD_EN : 1;/*!< NA */ - __IM uint32_t ICM_REG_AXI_HWCFG_LOW_POWER_INF_EN : 1;/*!< NA */ - uint32_t : 3; - __IM uint32_t ICM_REG_AXI_HWCFG_AXI_NUM_MASTERS : 5;/*!< NA */ - uint32_t : 3; - __IM uint32_t ICM_REG_AXI_HWCFG_AXI_NUM_SLAVES : 5;/*!< NA */ - uint32_t : 7; - } bit; - } HW_CFG; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t ICM_REG_AXI_CMD : 3; /*!< NA */ - uint32_t : 4; - __IOM uint32_t ICM_REG_RD_WR_CHAN : 1; /*!< NA */ - __IOM uint32_t ICM_REG_AXI_MASTER_PORT : 4;/*!< NA */ - uint32_t : 16; - __IM uint32_t ICM_REG_AXI_ERR_BIT : 1; /*!< NA */ - __IOM uint32_t ICM_REG_AXI_SOFT_RESET_BIT : 1;/*!< NA */ - __IOM uint32_t ICM_REG_AXI_RD_WR_CMD : 1; /*!< NA */ - __IOM uint32_t ICM_REG_AXI_CMD_EN : 1; /*!< NA */ - } bit; - } CMD; - - union { - __IOM uint32_t reg; /*!< NA */ - - struct { - __IOM uint32_t ICM_REG_DATA : 32; /*!< NA */ - } bit; - } DATA; -} AXI_ICM_Type; /*!< Size = 16 (0x10) */ - - - -/* =========================================================================================================================== */ -/* ================ IO_MUX ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Input/Output Multiplexer (IO_MUX) - */ - -typedef struct { /*!< IO_MUX Structure */ - __IM uint32_t RESERVED; - - union { - __IOM uint32_t reg; /*!< IO_MUX Control Register */ - - struct { - __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep - mode. 0: Disable 1: Enable */ - __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: - Not enter 1: Enter */ - __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during - sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: - ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ - __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable - 1: Enable */ - __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: - ~20 mA 3: ~40 mA */ - __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select - Function 0 1: Select Function 1 ...... */ - __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. - 0: Disable 1: Enable */ - uint32_t : 16; - } bit; - } GPIO0; - __IM uint32_t RESERVED1[3]; - - union { - __IOM uint32_t reg; /*!< IO_MUX Control Register */ - - struct { - __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep - mode. 0: Disable 1: Enable */ - __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: - Not enter 1: Enter */ - __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during - sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: - ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ - __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable - 1: Enable */ - __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: - ~20 mA 3: ~40 mA */ - __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select - Function 0 1: Select Function 1 ...... */ - __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. - 0: Disable 1: Enable */ - uint32_t : 16; - } bit; - } GPIO1; - __IM uint32_t RESERVED2[3]; - - union { - __IOM uint32_t reg; /*!< IO_MUX Control Register */ - - struct { - __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep - mode. 0: Disable 1: Enable */ - __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: - Not enter 1: Enter */ - __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during - sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: - ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ - __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable - 1: Enable */ - __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: - ~20 mA 3: ~40 mA */ - __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select - Function 0 1: Select Function 1 ...... */ - __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. - 0: Disable 1: Enable */ - uint32_t : 16; - } bit; - } GPIO2; - __IM uint32_t RESERVED3[3]; - - union { - __IOM uint32_t reg; /*!< IO_MUX Control Register */ - - struct { - __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep - mode. 0: Disable 1: Enable */ - __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: - Not enter 1: Enter */ - __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during - sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: - ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ - __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable - 1: Enable */ - __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: - ~20 mA 3: ~40 mA */ - __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select - Function 0 1: Select Function 1 ...... */ - __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. - 0: Disable 1: Enable */ - uint32_t : 16; - } bit; - } GPIO3; - __IM uint32_t RESERVED4[3]; - - union { - __IOM uint32_t reg; /*!< IO_MUX Control Register */ - - struct { - __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep - mode. 0: Disable 1: Enable */ - __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: - Not enter 1: Enter */ - __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during - sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: - ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ - __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable - 1: Enable */ - __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: - ~20 mA 3: ~40 mA */ - __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select - Function 0 1: Select Function 1 ...... */ - __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. - 0: Disable 1: Enable */ - uint32_t : 16; - } bit; - } GPIO4; - __IM uint32_t RESERVED5[3]; - - union { - __IOM uint32_t reg; /*!< IO_MUX Control Register */ - - struct { - __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep - mode. 0: Disable 1: Enable */ - __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: - Not enter 1: Enter */ - __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during - sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: - ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ - __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable - 1: Enable */ - __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: - ~20 mA 3: ~40 mA */ - __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select - Function 0 1: Select Function 1 ...... */ - __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. - 0: Disable 1: Enable */ - uint32_t : 16; - } bit; - } GPIO5; - __IM uint32_t RESERVED6[3]; - - union { - __IOM uint32_t reg; /*!< IO_MUX Control Register */ - - struct { - __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep - mode. 0: Disable 1: Enable */ - __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: - Not enter 1: Enter */ - __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during - sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: - ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ - __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable - 1: Enable */ - __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: - ~20 mA 3: ~40 mA */ - __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select - Function 0 1: Select Function 1 ...... */ - __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. - 0: Disable 1: Enable */ - uint32_t : 16; - } bit; - } GPIO6; - __IM uint32_t RESERVED7[3]; - - union { - __IOM uint32_t reg; /*!< IO_MUX Control Register */ - - struct { - __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep - mode. 0: Disable 1: Enable */ - __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: - Not enter 1: Enter */ - __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during - sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: - ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ - __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable - 1: Enable */ - __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: - ~20 mA 3: ~40 mA */ - __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select - Function 0 1: Select Function 1 ...... */ - __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. - 0: Disable 1: Enable */ - uint32_t : 16; - } bit; - } GPIO7; - __IM uint32_t RESERVED8[3]; - - union { - __IOM uint32_t reg; /*!< IO_MUX Control Register */ - - struct { - __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep - mode. 0: Disable 1: Enable */ - __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: - Not enter 1: Enter */ - __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during - sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: - ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ - __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable - 1: Enable */ - __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: - ~20 mA 3: ~40 mA */ - __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select - Function 0 1: Select Function 1 ...... */ - __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. - 0: Disable 1: Enable */ - uint32_t : 16; - } bit; - } GPIO8; - __IM uint32_t RESERVED9[3]; - - union { - __IOM uint32_t reg; /*!< IO_MUX Control Register */ - - struct { - __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep - mode. 0: Disable 1: Enable */ - __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: - Not enter 1: Enter */ - __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during - sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: - ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ - __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable - 1: Enable */ - __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: - ~20 mA 3: ~40 mA */ - __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select - Function 0 1: Select Function 1 ...... */ - __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. - 0: Disable 1: Enable */ - uint32_t : 16; - } bit; - } GPIO9; - __IM uint32_t RESERVED10[3]; - - union { - __IOM uint32_t reg; /*!< IO_MUX Control Register */ - - struct { - __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep - mode. 0: Disable 1: Enable */ - __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: - Not enter 1: Enter */ - __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during - sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: - ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ - __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable - 1: Enable */ - __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: - ~20 mA 3: ~40 mA */ - __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select - Function 0 1: Select Function 1 ...... */ - __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. - 0: Disable 1: Enable */ - uint32_t : 16; - } bit; - } GPIO10; - __IM uint32_t RESERVED11[3]; - - union { - __IOM uint32_t reg; /*!< IO_MUX Control Register */ - - struct { - __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep - mode. 0: Disable 1: Enable */ - __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: - Not enter 1: Enter */ - __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during - sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: - ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ - __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable - 1: Enable */ - __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: - ~20 mA 3: ~40 mA */ - __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select - Function 0 1: Select Function 1 ...... */ - __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. - 0: Disable 1: Enable */ - uint32_t : 16; - } bit; - } GPIO11; - __IM uint32_t RESERVED12[3]; - - union { - __IOM uint32_t reg; /*!< IO_MUX Control Register */ - - struct { - __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep - mode. 0: Disable 1: Enable */ - __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: - Not enter 1: Enter */ - __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during - sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: - ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ - __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable - 1: Enable */ - __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: - ~20 mA 3: ~40 mA */ - __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select - Function 0 1: Select Function 1 ...... */ - __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. - 0: Disable 1: Enable */ - uint32_t : 16; - } bit; - } GPIO12; - __IM uint32_t RESERVED13[3]; - - union { - __IOM uint32_t reg; /*!< IO_MUX Control Register */ - - struct { - __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep - mode. 0: Disable 1: Enable */ - __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: - Not enter 1: Enter */ - __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during - sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: - ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ - __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable - 1: Enable */ - __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: - ~20 mA 3: ~40 mA */ - __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select - Function 0 1: Select Function 1 ...... */ - __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. - 0: Disable 1: Enable */ - uint32_t : 16; - } bit; - } GPIO13; - __IM uint32_t RESERVED14[3]; - - union { - __IOM uint32_t reg; /*!< IO_MUX Control Register */ - - struct { - __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep - mode. 0: Disable 1: Enable */ - __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: - Not enter 1: Enter */ - __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during - sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: - ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ - __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable - 1: Enable */ - __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: - ~20 mA 3: ~40 mA */ - __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select - Function 0 1: Select Function 1 ...... */ - __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. - 0: Disable 1: Enable */ - uint32_t : 16; - } bit; - } GPIO14; - __IM uint32_t RESERVED15[3]; - - union { - __IOM uint32_t reg; /*!< IO_MUX Control Register */ - - struct { - __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep - mode. 0: Disable 1: Enable */ - __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: - Not enter 1: Enter */ - __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during - sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: - ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ - __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable - 1: Enable */ - __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: - ~20 mA 3: ~40 mA */ - __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select - Function 0 1: Select Function 1 ...... */ - __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. - 0: Disable 1: Enable */ - uint32_t : 16; - } bit; - } GPIO15; - __IM uint32_t RESERVED16[3]; - - union { - union { - __IOM uint32_t reg; /*!< iomux version */ - - struct { - __IOM uint32_t DATE : 28; /*!< csv date */ - uint32_t : 4; - } bit; - } DATE; - - union { - __IOM uint32_t reg; /*!< IO_MUX Control Register */ - - struct { - __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep - mode. 0: Disable 1: Enable */ - __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: - Not enter 1: Enter */ - __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during - sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: - ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ - __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable - 1: Enable */ - __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: - ~20 mA 3: ~40 mA */ - __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select - Function 0 1: Select Function 1 ...... */ - __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. - 0: Disable 1: Enable */ - uint32_t : 16; - } bit; - } GPIO16; - }; - __IM uint32_t RESERVED17[3]; - - union { - __IOM uint32_t reg; /*!< IO_MUX Control Register */ - - struct { - __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep - mode. 0: Disable 1: Enable */ - __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: - Not enter 1: Enter */ - __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during - sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: - ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ - __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable - 1: Enable */ - __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: - ~20 mA 3: ~40 mA */ - __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select - Function 0 1: Select Function 1 ...... */ - __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. - 0: Disable 1: Enable */ - uint32_t : 16; - } bit; - } GPIO17; - __IM uint32_t RESERVED18[3]; - - union { - __IOM uint32_t reg; /*!< IO_MUX Control Register */ - - struct { - __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep - mode. 0: Disable 1: Enable */ - __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: - Not enter 1: Enter */ - __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during - sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: - ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ - __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable - 1: Enable */ - __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: - ~20 mA 3: ~40 mA */ - __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select - Function 0 1: Select Function 1 ...... */ - __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. - 0: Disable 1: Enable */ - uint32_t : 16; - } bit; - } GPIO18; - __IM uint32_t RESERVED19[3]; - - union { - __IOM uint32_t reg; /*!< IO_MUX Control Register */ - - struct { - __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep - mode. 0: Disable 1: Enable */ - __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: - Not enter 1: Enter */ - __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during - sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: - ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ - __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable - 1: Enable */ - __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: - ~20 mA 3: ~40 mA */ - __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select - Function 0 1: Select Function 1 ...... */ - __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. - 0: Disable 1: Enable */ - uint32_t : 16; - } bit; - } GPIO19; - __IM uint32_t RESERVED20[3]; - - union { - __IOM uint32_t reg; /*!< IO_MUX Control Register */ - - struct { - __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep - mode. 0: Disable 1: Enable */ - __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: - Not enter 1: Enter */ - __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during - sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: - ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ - __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable - 1: Enable */ - __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: - ~20 mA 3: ~40 mA */ - __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select - Function 0 1: Select Function 1 ...... */ - __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. - 0: Disable 1: Enable */ - uint32_t : 16; - } bit; - } GPIO20; - __IM uint32_t RESERVED21[3]; - - union { - __IOM uint32_t reg; /*!< IO_MUX Control Register */ - - struct { - __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep - mode. 0: Disable 1: Enable */ - __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: - Not enter 1: Enter */ - __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during - sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: - ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ - __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable - 1: Enable */ - __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: - ~20 mA 3: ~40 mA */ - __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select - Function 0 1: Select Function 1 ...... */ - __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. - 0: Disable 1: Enable */ - uint32_t : 16; - } bit; - } GPIO21; - __IM uint32_t RESERVED22[3]; - - union { - __IOM uint32_t reg; /*!< IO_MUX Control Register */ - - struct { - __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep - mode. 0: Disable 1: Enable */ - __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: - Not enter 1: Enter */ - __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during - sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: - ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ - __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable - 1: Enable */ - __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: - ~20 mA 3: ~40 mA */ - __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select - Function 0 1: Select Function 1 ...... */ - __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. - 0: Disable 1: Enable */ - uint32_t : 16; - } bit; - } GPIO22; - __IM uint32_t RESERVED23[3]; - - union { - __IOM uint32_t reg; /*!< IO_MUX Control Register */ - - struct { - __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep - mode. 0: Disable 1: Enable */ - __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: - Not enter 1: Enter */ - __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during - sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: - ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ - __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable - 1: Enable */ - __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: - ~20 mA 3: ~40 mA */ - __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select - Function 0 1: Select Function 1 ...... */ - __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. - 0: Disable 1: Enable */ - uint32_t : 16; - } bit; - } GPIO23; - __IM uint32_t RESERVED24[3]; - - union { - __IOM uint32_t reg; /*!< IO_MUX Control Register */ - - struct { - __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep - mode. 0: Disable 1: Enable */ - __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: - Not enter 1: Enter */ - __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during - sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: - ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ - __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable - 1: Enable */ - __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: - ~20 mA 3: ~40 mA */ - __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select - Function 0 1: Select Function 1 ...... */ - __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. - 0: Disable 1: Enable */ - uint32_t : 16; - } bit; - } GPIO24; - __IM uint32_t RESERVED25[3]; - - union { - __IOM uint32_t reg; /*!< IO_MUX Control Register */ - - struct { - __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep - mode. 0: Disable 1: Enable */ - __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: - Not enter 1: Enter */ - __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during - sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: - ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ - __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable - 1: Enable */ - __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: - ~20 mA 3: ~40 mA */ - __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select - Function 0 1: Select Function 1 ...... */ - __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. - 0: Disable 1: Enable */ - uint32_t : 16; - } bit; - } GPIO25; - __IM uint32_t RESERVED26[3]; - - union { - __IOM uint32_t reg; /*!< IO_MUX Control Register */ - - struct { - __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep - mode. 0: Disable 1: Enable */ - __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: - Not enter 1: Enter */ - __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during - sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: - ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ - __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable - 1: Enable */ - __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: - ~20 mA 3: ~40 mA */ - __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select - Function 0 1: Select Function 1 ...... */ - __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. - 0: Disable 1: Enable */ - uint32_t : 16; - } bit; - } GPIO26; - __IM uint32_t RESERVED27[3]; - - union { - __IOM uint32_t reg; /*!< IO_MUX Control Register */ - - struct { - __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep - mode. 0: Disable 1: Enable */ - __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: - Not enter 1: Enter */ - __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during - sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: - ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ - __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable - 1: Enable */ - __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: - ~20 mA 3: ~40 mA */ - __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select - Function 0 1: Select Function 1 ...... */ - __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. - 0: Disable 1: Enable */ - uint32_t : 16; - } bit; - } GPIO27; - __IM uint32_t RESERVED28[3]; - - union { - __IOM uint32_t reg; /*!< IO_MUX Control Register */ - - struct { - __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep - mode. 0: Disable 1: Enable */ - __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: - Not enter 1: Enter */ - __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during - sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: - ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ - __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable - 1: Enable */ - __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: - ~20 mA 3: ~40 mA */ - __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select - Function 0 1: Select Function 1 ...... */ - __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. - 0: Disable 1: Enable */ - uint32_t : 16; - } bit; - } GPIO28; - __IM uint32_t RESERVED29[3]; - - union { - __IOM uint32_t reg; /*!< IO_MUX Control Register */ - - struct { - __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep - mode. 0: Disable 1: Enable */ - __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: - Not enter 1: Enter */ - __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during - sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: - ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ - __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable - 1: Enable */ - __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: - ~20 mA 3: ~40 mA */ - __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select - Function 0 1: Select Function 1 ...... */ - __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. - 0: Disable 1: Enable */ - uint32_t : 16; - } bit; - } GPIO29; - __IM uint32_t RESERVED30[3]; - - union { - __IOM uint32_t reg; /*!< IO_MUX Control Register */ - - struct { - __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep - mode. 0: Disable 1: Enable */ - __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: - Not enter 1: Enter */ - __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during - sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: - ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ - __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable - 1: Enable */ - __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: - ~20 mA 3: ~40 mA */ - __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select - Function 0 1: Select Function 1 ...... */ - __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. - 0: Disable 1: Enable */ - uint32_t : 16; - } bit; - } GPIO30; - __IM uint32_t RESERVED31[3]; - - union { - __IOM uint32_t reg; /*!< IO_MUX Control Register */ - - struct { - __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep - mode. 0: Disable 1: Enable */ - __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: - Not enter 1: Enter */ - __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during - sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: - ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ - __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable - 1: Enable */ - __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: - ~20 mA 3: ~40 mA */ - __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select - Function 0 1: Select Function 1 ...... */ - __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. - 0: Disable 1: Enable */ - uint32_t : 16; - } bit; - } GPIO31; - __IM uint32_t RESERVED32[3]; - - union { - __IOM uint32_t reg; /*!< IO_MUX Control Register */ - - struct { - __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep - mode. 0: Disable 1: Enable */ - __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: - Not enter 1: Enter */ - __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during - sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: - ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ - __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable - 1: Enable */ - __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: - ~20 mA 3: ~40 mA */ - __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select - Function 0 1: Select Function 1 ...... */ - __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. - 0: Disable 1: Enable */ - uint32_t : 16; - } bit; - } GPIO32; - __IM uint32_t RESERVED33[3]; - - union { - __IOM uint32_t reg; /*!< IO_MUX Control Register */ - - struct { - __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep - mode. 0: Disable 1: Enable */ - __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: - Not enter 1: Enter */ - __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during - sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: - ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ - __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable - 1: Enable */ - __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: - ~20 mA 3: ~40 mA */ - __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select - Function 0 1: Select Function 1 ...... */ - __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. - 0: Disable 1: Enable */ - uint32_t : 16; - } bit; - } GPIO33; - __IM uint32_t RESERVED34[3]; - - union { - __IOM uint32_t reg; /*!< IO_MUX Control Register */ - - struct { - __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep - mode. 0: Disable 1: Enable */ - __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: - Not enter 1: Enter */ - __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during - sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: - ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ - __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable - 1: Enable */ - __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: - ~20 mA 3: ~40 mA */ - __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select - Function 0 1: Select Function 1 ...... */ - __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. - 0: Disable 1: Enable */ - uint32_t : 16; - } bit; - } GPIO34; - __IM uint32_t RESERVED35[3]; - - union { - __IOM uint32_t reg; /*!< IO_MUX Control Register */ - - struct { - __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep - mode. 0: Disable 1: Enable */ - __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: - Not enter 1: Enter */ - __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during - sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: - ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ - __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable - 1: Enable */ - __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: - ~20 mA 3: ~40 mA */ - __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select - Function 0 1: Select Function 1 ...... */ - __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. - 0: Disable 1: Enable */ - uint32_t : 16; - } bit; - } GPIO35; - __IM uint32_t RESERVED36[3]; - - union { - __IOM uint32_t reg; /*!< IO_MUX Control Register */ - - struct { - __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep - mode. 0: Disable 1: Enable */ - __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: - Not enter 1: Enter */ - __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during - sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: - ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ - __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable - 1: Enable */ - __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: - ~20 mA 3: ~40 mA */ - __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select - Function 0 1: Select Function 1 ...... */ - __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. - 0: Disable 1: Enable */ - uint32_t : 16; - } bit; - } GPIO36; - __IM uint32_t RESERVED37[3]; - - union { - __IOM uint32_t reg; /*!< IO_MUX Control Register */ - - struct { - __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep - mode. 0: Disable 1: Enable */ - __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: - Not enter 1: Enter */ - __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during - sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: - ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ - __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable - 1: Enable */ - __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: - ~20 mA 3: ~40 mA */ - __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select - Function 0 1: Select Function 1 ...... */ - __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. - 0: Disable 1: Enable */ - uint32_t : 16; - } bit; - } GPIO37; - __IM uint32_t RESERVED38[3]; - - union { - __IOM uint32_t reg; /*!< IO_MUX Control Register */ - - struct { - __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep - mode. 0: Disable 1: Enable */ - __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: - Not enter 1: Enter */ - __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during - sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: - ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ - __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable - 1: Enable */ - __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: - ~20 mA 3: ~40 mA */ - __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select - Function 0 1: Select Function 1 ...... */ - __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. - 0: Disable 1: Enable */ - uint32_t : 16; - } bit; - } GPIO38; - __IM uint32_t RESERVED39[3]; - - union { - __IOM uint32_t reg; /*!< IO_MUX Control Register */ - - struct { - __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep - mode. 0: Disable 1: Enable */ - __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: - Not enter 1: Enter */ - __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during - sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: - ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ - __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable - 1: Enable */ - __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: - ~20 mA 3: ~40 mA */ - __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select - Function 0 1: Select Function 1 ...... */ - __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. - 0: Disable 1: Enable */ - uint32_t : 16; - } bit; - } GPIO39; - __IM uint32_t RESERVED40[3]; - - union { - __IOM uint32_t reg; /*!< IO_MUX Control Register */ - - struct { - __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep - mode. 0: Disable 1: Enable */ - __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: - Not enter 1: Enter */ - __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during - sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: - ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ - __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable - 1: Enable */ - __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: - ~20 mA 3: ~40 mA */ - __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select - Function 0 1: Select Function 1 ...... */ - __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. - 0: Disable 1: Enable */ - uint32_t : 16; - } bit; - } GPIO40; - __IM uint32_t RESERVED41[3]; - - union { - __IOM uint32_t reg; /*!< IO_MUX Control Register */ - - struct { - __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep - mode. 0: Disable 1: Enable */ - __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: - Not enter 1: Enter */ - __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during - sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: - ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ - __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable - 1: Enable */ - __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: - ~20 mA 3: ~40 mA */ - __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select - Function 0 1: Select Function 1 ...... */ - __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. - 0: Disable 1: Enable */ - uint32_t : 16; - } bit; - } GPIO41; - __IM uint32_t RESERVED42[3]; - - union { - __IOM uint32_t reg; /*!< IO_MUX Control Register */ - - struct { - __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep - mode. 0: Disable 1: Enable */ - __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: - Not enter 1: Enter */ - __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during - sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: - ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ - __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable - 1: Enable */ - __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: - ~20 mA 3: ~40 mA */ - __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select - Function 0 1: Select Function 1 ...... */ - __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. - 0: Disable 1: Enable */ - uint32_t : 16; - } bit; - } GPIO42; - __IM uint32_t RESERVED43[3]; - - union { - __IOM uint32_t reg; /*!< IO_MUX Control Register */ - - struct { - __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep - mode. 0: Disable 1: Enable */ - __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: - Not enter 1: Enter */ - __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during - sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: - ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ - __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable - 1: Enable */ - __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: - ~20 mA 3: ~40 mA */ - __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select - Function 0 1: Select Function 1 ...... */ - __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. - 0: Disable 1: Enable */ - uint32_t : 16; - } bit; - } GPIO43; - __IM uint32_t RESERVED44[3]; - - union { - __IOM uint32_t reg; /*!< IO_MUX Control Register */ - - struct { - __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep - mode. 0: Disable 1: Enable */ - __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: - Not enter 1: Enter */ - __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during - sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: - ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ - __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable - 1: Enable */ - __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: - ~20 mA 3: ~40 mA */ - __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select - Function 0 1: Select Function 1 ...... */ - __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. - 0: Disable 1: Enable */ - uint32_t : 16; - } bit; - } GPIO44; - __IM uint32_t RESERVED45[3]; - - union { - __IOM uint32_t reg; /*!< IO_MUX Control Register */ - - struct { - __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep - mode. 0: Disable 1: Enable */ - __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: - Not enter 1: Enter */ - __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during - sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: - ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ - __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable - 1: Enable */ - __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: - ~20 mA 3: ~40 mA */ - __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select - Function 0 1: Select Function 1 ...... */ - __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. - 0: Disable 1: Enable */ - uint32_t : 16; - } bit; - } GPIO45; - __IM uint32_t RESERVED46[3]; - - union { - __IOM uint32_t reg; /*!< IO_MUX Control Register */ - - struct { - __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep - mode. 0: Disable 1: Enable */ - __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: - Not enter 1: Enter */ - __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during - sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: - ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ - __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable - 1: Enable */ - __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: - ~20 mA 3: ~40 mA */ - __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select - Function 0 1: Select Function 1 ...... */ - __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. - 0: Disable 1: Enable */ - uint32_t : 16; - } bit; - } GPIO46; - __IM uint32_t RESERVED47[3]; - - union { - __IOM uint32_t reg; /*!< IO_MUX Control Register */ - - struct { - __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep - mode. 0: Disable 1: Enable */ - __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: - Not enter 1: Enter */ - __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during - sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: - ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ - __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable - 1: Enable */ - __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: - ~20 mA 3: ~40 mA */ - __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select - Function 0 1: Select Function 1 ...... */ - __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. - 0: Disable 1: Enable */ - uint32_t : 16; - } bit; - } GPIO47; - __IM uint32_t RESERVED48[3]; - - union { - __IOM uint32_t reg; /*!< IO_MUX Control Register */ - - struct { - __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep - mode. 0: Disable 1: Enable */ - __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: - Not enter 1: Enter */ - __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during - sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: - ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ - __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable - 1: Enable */ - __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: - ~20 mA 3: ~40 mA */ - __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select - Function 0 1: Select Function 1 ...... */ - __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. - 0: Disable 1: Enable */ - uint32_t : 16; - } bit; - } GPIO48; - __IM uint32_t RESERVED49[3]; - - union { - __IOM uint32_t reg; /*!< IO_MUX Control Register */ - - struct { - __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep - mode. 0: Disable 1: Enable */ - __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: - Not enter 1: Enter */ - __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during - sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: - ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ - __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable - 1: Enable */ - __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: - ~20 mA 3: ~40 mA */ - __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select - Function 0 1: Select Function 1 ...... */ - __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. - 0: Disable 1: Enable */ - uint32_t : 16; - } bit; - } GPIO49; - __IM uint32_t RESERVED50[3]; - - union { - __IOM uint32_t reg; /*!< IO_MUX Control Register */ - - struct { - __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep - mode. 0: Disable 1: Enable */ - __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: - Not enter 1: Enter */ - __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during - sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: - ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ - __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable - 1: Enable */ - __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: - ~20 mA 3: ~40 mA */ - __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select - Function 0 1: Select Function 1 ...... */ - __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. - 0: Disable 1: Enable */ - uint32_t : 16; - } bit; - } GPIO50; - __IM uint32_t RESERVED51[3]; - - union { - __IOM uint32_t reg; /*!< IO_MUX Control Register */ - - struct { - __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep - mode. 0: Disable 1: Enable */ - __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: - Not enter 1: Enter */ - __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during - sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: - ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ - __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable - 1: Enable */ - __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: - ~20 mA 3: ~40 mA */ - __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select - Function 0 1: Select Function 1 ...... */ - __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. - 0: Disable 1: Enable */ - uint32_t : 16; - } bit; - } GPIO51; - __IM uint32_t RESERVED52[3]; - - union { - __IOM uint32_t reg; /*!< IO_MUX Control Register */ - - struct { - __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep - mode. 0: Disable 1: Enable */ - __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: - Not enter 1: Enter */ - __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during - sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: - ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ - __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable - 1: Enable */ - __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: - ~20 mA 3: ~40 mA */ - __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select - Function 0 1: Select Function 1 ...... */ - __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. - 0: Disable 1: Enable */ - uint32_t : 16; - } bit; - } GPIO52; - __IM uint32_t RESERVED53[3]; - - union { - __IOM uint32_t reg; /*!< IO_MUX Control Register */ - - struct { - __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep - mode. 0: Disable 1: Enable */ - __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: - Not enter 1: Enter */ - __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during - sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: - ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ - __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable - 1: Enable */ - __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: - ~20 mA 3: ~40 mA */ - __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select - Function 0 1: Select Function 1 ...... */ - __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. - 0: Disable 1: Enable */ - uint32_t : 16; - } bit; - } GPIO53; - union { - __IOM uint32_t reg; /*!< IO_MUX Control Register */ - - struct { - __IOM uint32_t MCU_OE : 1; /*!< Configures whether or not to enable the output of GPIOn in sleep - mode. 0: Disable 1: Enable */ - __IOM uint32_t SLP_SEL : 1; /*!< Configures whether or not to enter sleep mode for GPIOn. 0: - Not enter 1: Enter */ - __IOM uint32_t MCU_WPD : 1; /*!< Configure whether or not to enable pull-down resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_WPU : 1; /*!< Configures whether or not to enable pull-up resistor of GPIOn - during sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_IE : 1; /*!< Configures whether or not to enable the input of GPIOn during - sleep mode. 0: Disable 1: Enable */ - __IOM uint32_t MCU_DRV : 2; /*!< Configures the drive strength of GPIOn during sleep mode. 0: - ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA */ - __IOM uint32_t FUN_WPD : 1; /*!< Configures whether or not to enable pull-down resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_WPU : 1; /*!< Configures whether or not enable pull-up resistor of GPIOn. - 0: Disable 1: Enable */ - __IOM uint32_t FUN_IE : 1; /*!< Configures whether or not to enable input of GPIOn. 0: Disable - 1: Enable */ - __IOM uint32_t FUN_DRV : 2; /*!< Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: - ~20 mA 3: ~40 mA */ - __IOM uint32_t MCU_SEL : 3; /*!< Configures to select IO MUX function for this pin. 0: Select - Function 0 1: Select Function 1 ...... */ - __IOM uint32_t FILTER_EN : 1; /*!< Configures whether or not to enable filter for pin input signals. - 0: Disable 1: Enable */ - uint32_t : 16; - } bit; - } GPIO54; -} IO_MUX_Type; /*!< Size = 856 (0x358) */ - - - -/* =========================================================================================================================== */ -/* ================ ISP ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief ISP Peripheral (ISP) - */ - -typedef struct { /*!< ISP Structure */ - - union { - __IOM uint32_t reg; /*!< version control register */ - - struct { - __IOM uint32_t VER_DATA : 32; /*!< csv version */ - } bit; - } VER_DATE; - - union { - __IOM uint32_t reg; /*!< isp clk control register */ - - struct { - __IOM uint32_t CLK_EN : 1; /*!< this bit configures the clk force on of isp reg. 0: disable, - 1: enable */ - __IOM uint32_t CLK_BLC_FORCE_ON : 1; /*!< this bit configures the clk force on of blc. 0: disable, 1: - enable */ - __IOM uint32_t CLK_DPC_FORCE_ON : 1; /*!< this bit configures the clk force on of dpc. 0: disable, 1: - enable */ - __IOM uint32_t CLK_BF_FORCE_ON : 1; /*!< this bit configures the clk force on of bf. 0: disable, 1: enable */ - __IOM uint32_t CLK_LSC_FORCE_ON : 1; /*!< this bit configures the clk force on of lsc. 0: disable, 1: - enable */ - __IOM uint32_t CLK_DEMOSAIC_FORCE_ON : 1; /*!< this bit configures the clk force on of demosaic. 0: disable, - 1: enable */ - __IOM uint32_t CLK_MEDIAN_FORCE_ON : 1; /*!< this bit configures the clk force on of median. 0: disable, - 1: enable */ - __IOM uint32_t CLK_CCM_FORCE_ON : 1; /*!< this bit configures the clk force on of ccm. 0: disable, 1: - enable */ - __IOM uint32_t CLK_GAMMA_FORCE_ON : 1; /*!< this bit configures the clk force on of gamma. 0: disable, 1: - enable */ - __IOM uint32_t CLK_RGB2YUV_FORCE_ON : 1; /*!< this bit configures the clk force on of rgb2yuv. 0: disable, - 1: enable */ - __IOM uint32_t CLK_SHARP_FORCE_ON : 1; /*!< this bit configures the clk force on of sharp. 0: disable, 1: - enable */ - __IOM uint32_t CLK_COLOR_FORCE_ON : 1; /*!< this bit configures the clk force on of color. 0: disable, 1: - enable */ - __IOM uint32_t CLK_YUV2RGB_FORCE_ON : 1; /*!< this bit configures the clk force on of yuv2rgb. 0: disable, - 1: enable */ - __IOM uint32_t CLK_AE_FORCE_ON : 1; /*!< this bit configures the clk force on of ae. 0: disable, 1: enable */ - __IOM uint32_t CLK_AF_FORCE_ON : 1; /*!< this bit configures the clk force on of af. 0: disable, 1: enable */ - __IOM uint32_t CLK_AWB_FORCE_ON : 1; /*!< this bit configures the clk force on of awb. 0: disable, 1: - enable */ - __IOM uint32_t CLK_HIST_FORCE_ON : 1; /*!< this bit configures the clk force on of hist. 0: disable, 1: - enable */ - __IOM uint32_t CLK_MIPI_IDI_FORCE_ON : 1; /*!< this bit configures the clk force on of mipi idi input. 0: disable, - 1: enable */ - __IOM uint32_t ISP_MEM_CLK_FORCE_ON : 1; /*!< this bit configures the clk force on of all isp memory. 0: disable, - 1: enable */ - uint32_t : 13; - } bit; - } CLK_EN; - - union { - __IOM uint32_t reg; /*!< isp module enable control register */ - - struct { - __IOM uint32_t MIPI_DATA_EN : 1; /*!< this bit configures mipi input data enable. 0: disable, 1: enable */ - __IOM uint32_t ISP_EN : 1; /*!< this bit configures isp global enable. 0: disable, 1: enable */ - __IOM uint32_t BLC_EN : 1; /*!< this bit configures blc enable. 0: disable, 1: enable */ - __IOM uint32_t DPC_EN : 1; /*!< this bit configures dpc enable. 0: disable, 1: enable */ - __IOM uint32_t BF_EN : 1; /*!< this bit configures bf enable. 0: disable, 1: enable */ - __IOM uint32_t LSC_EN : 1; /*!< this bit configures lsc enable. 0: disable, 1: enable */ - __IOM uint32_t DEMOSAIC_EN : 1; /*!< this bit configures demosaic enable. 0: disable, 1: enable */ - __IOM uint32_t MEDIAN_EN : 1; /*!< this bit configures median enable. 0: disable, 1: enable */ - __IOM uint32_t CCM_EN : 1; /*!< this bit configures ccm enable. 0: disable, 1: enable */ - __IOM uint32_t GAMMA_EN : 1; /*!< this bit configures gamma enable. 0: disable, 1: enable */ - __IOM uint32_t RGB2YUV_EN : 1; /*!< this bit configures rgb2yuv enable. 0: disable, 1: enable */ - __IOM uint32_t SHARP_EN : 1; /*!< this bit configures sharp enable. 0: disable, 1: enable */ - __IOM uint32_t COLOR_EN : 1; /*!< this bit configures color enable. 0: disable, 1: enable */ - __IOM uint32_t YUV2RGB_EN : 1; /*!< this bit configures yuv2rgb enable. 0: disable, 1: enable */ - __IOM uint32_t AE_EN : 1; /*!< this bit configures ae enable. 0: disable, 1: enable */ - __IOM uint32_t AF_EN : 1; /*!< this bit configures af enable. 0: disable, 1: enable */ - __IOM uint32_t AWB_EN : 1; /*!< this bit configures awb enable. 0: disable, 1: enable */ - __IOM uint32_t HIST_EN : 1; /*!< this bit configures hist enable. 0: disable, 1: enable */ - uint32_t : 6; - __IOM uint32_t BYTE_ENDIAN_ORDER : 1; /*!< select input idi data byte_endian_order when isp is bypass, - 0: csi_data[31:0], 1: {[7:0], [15:8], [23:16], [31:24]} */ - __IOM uint32_t ISP_DATA_TYPE : 2; /*!< this field configures input data type, 0:RAW8 1:RAW10 2:RAW12 */ - __IOM uint32_t ISP_IN_SRC : 2; /*!< this field configures input data source, 0:CSI HOST 1:CAM 2:DMA */ - __IOM uint32_t ISP_OUT_TYPE : 3; /*!< this field configures pixel output type, 0: RAW8 1: YUV422 2: - RGB888 3: YUV420 4: RGB565 */ - } bit; - } CNTL; - - union { - __IOM uint32_t reg; /*!< header hsync interval control register */ - - struct { - __IOM uint32_t HSYNC_CNT : 8; /*!< this field configures the number of clock before hsync and after - vsync and line_end when decodes pix data from idi to isp */ - uint32_t : 24; - } bit; - } HSYNC_CNT; - - union { - __IOM uint32_t reg; /*!< frame control parameter register */ - - struct { - __IOM uint32_t VADR_NUM : 12; /*!< this field configures input image size in y-direction, image - row number - 1 */ - __IOM uint32_t HADR_NUM : 12; /*!< this field configures input image size in x-direction, image - line number - 1 */ - uint32_t : 3; - __IOM uint32_t BAYER_MODE : 2; /*!< this field configures the bayer mode of input pixel. 00 : BG/GR - 01 : GB/RG 10 : GR/BG 11 : RG/GB */ - __IOM uint32_t HSYNC_START_EXIST : 1; /*!< this bit configures the line end packet exist or not. 0: not - exist, 1: exist */ - __IOM uint32_t HSYNC_END_EXIST : 1; /*!< this bit configures the line start packet exist or not. 0: not - exist, 1: exist */ - uint32_t : 1; - } bit; - } FRAME_CFG; - - union { - __IOM uint32_t reg; /*!< ccm coef register 0 */ - - struct { - __IOM uint32_t CCM_RR : 13; /*!< this field configures the color correction matrix coefficient */ - __IOM uint32_t CCM_RG : 13; /*!< this field configures the color correction matrix coefficient */ - uint32_t : 6; - } bit; - } CCM_COEF0; - - union { - __IOM uint32_t reg; /*!< ccm coef register 1 */ - - struct { - __IOM uint32_t CCM_RB : 13; /*!< this field configures the color correction matrix coefficient */ - __IOM uint32_t CCM_GR : 13; /*!< this field configures the color correction matrix coefficient */ - uint32_t : 6; - } bit; - } CCM_COEF1; - - union { - __IOM uint32_t reg; /*!< ccm coef register 3 */ - - struct { - __IOM uint32_t CCM_GG : 13; /*!< this field configures the color correction matrix coefficient */ - __IOM uint32_t CCM_GB : 13; /*!< this field configures the color correction matrix coefficient */ - uint32_t : 6; - } bit; - } CCM_COEF3; - - union { - __IOM uint32_t reg; /*!< ccm coef register 4 */ - - struct { - __IOM uint32_t CCM_BR : 13; /*!< this field configures the color correction matrix coefficient */ - __IOM uint32_t CCM_BG : 13; /*!< this field configures the color correction matrix coefficient */ - uint32_t : 6; - } bit; - } CCM_COEF4; - - union { - __IOM uint32_t reg; /*!< ccm coef register 5 */ - - struct { - __IOM uint32_t CCM_BB : 13; /*!< this field configures the color correction matrix coefficient */ - uint32_t : 19; - } bit; - } CCM_COEF5; - - union { - __IOM uint32_t reg; /*!< bf pix2matrix ctrl */ - - struct { - __IOM uint32_t BF_TAIL_PIXEN_PULSE_TL : 8;/*!< matrix tail pixen low level threshold, should not to large to - prevent expanding to next frame, only reg_bf_tail_pixen_pulse_th!=0 - and reg_bf_tail_pixen_pulse_tl!=0 and reg_bf_tail_pixen_pulse_th - < reg_bf_tail_pixen_pulse_tl will enable tail pulse function */ - __IOM uint32_t BF_TAIL_PIXEN_PULSE_TH : 8;/*!< matrix tail pixen high level threshold, must < hnum-1, only - reg_bf_tail_pixen_pulse_th!=0 and reg_bf_tail_pixen_pulse_tl!=0 - and reg_bf_tail_pixen_pulse_th < reg_bf_tail_pixen_pulse_tl - will enable tail pulse function */ - __IOM uint32_t BF_PADDING_DATA : 8; /*!< this field configures bf matrix padding data */ - __IOM uint32_t BF_PADDING_MODE : 1; /*!< this bit configures the padding mode of bf matrix. 0: use pixel - in image to do padding 1: use reg_padding_data to do padding */ - uint32_t : 7; - } bit; - } BF_MATRIX_CTRL; - - union { - __IOM uint32_t reg; /*!< bf denoising level control register */ - - struct { - __IOM uint32_t SIGMA : 6; /*!< this field configures the bayer denoising level, valid data - from 2 to 20 */ - uint32_t : 26; - } bit; - } BF_SIGMA; - - union { - __IOM uint32_t reg; /*!< bf gau template register 0 */ - - struct { - __IOM uint32_t GAU_TEMPLATE21 : 4; /*!< this field configures index 21 of gausian template */ - __IOM uint32_t GAU_TEMPLATE20 : 4; /*!< this field configures index 20 of gausian template */ - __IOM uint32_t GAU_TEMPLATE12 : 4; /*!< this field configures index 12 of gausian template */ - __IOM uint32_t GAU_TEMPLATE11 : 4; /*!< this field configures index 11 of gausian template */ - __IOM uint32_t GAU_TEMPLATE10 : 4; /*!< this field configures index 10 of gausian template */ - __IOM uint32_t GAU_TEMPLATE02 : 4; /*!< this field configures index 02 of gausian template */ - __IOM uint32_t GAU_TEMPLATE01 : 4; /*!< this field configures index 01 of gausian template */ - __IOM uint32_t GAU_TEMPLATE00 : 4; /*!< this field configures index 00 of gausian template */ - } bit; - } BF_GAU0; - - union { - __IOM uint32_t reg; /*!< bf gau template register 1 */ - - struct { - __IOM uint32_t GAU_TEMPLATE22 : 4; /*!< this field configures index 22 of gausian template */ - uint32_t : 28; - } bit; - } BF_GAU1; - - union { - __IOM uint32_t reg; /*!< DPC mode control register */ - - struct { - __IOM uint32_t DPC_CHECK_EN : 1; /*!< this bit configures the check mode enable. 0: disable, 1: enable */ - __IOM uint32_t STA_EN : 1; /*!< this bit configures the sta dpc enable. 0: disable, 1: enable */ - __IOM uint32_t DYN_EN : 1; /*!< this bit configures the dyn dpc enable. 0: disable, 1: enable */ - __IOM uint32_t DPC_BLACK_EN : 1; /*!< this bit configures input image type select when in check mode, - 0: white img, 1: black img */ - __IOM uint32_t DPC_METHOD_SEL : 1; /*!< this bit configures dyn dpc method select. 0: simple method, - 1: hard method */ - __IOM uint32_t DPC_CHECK_OD_EN : 1; /*!< this bit configures output pixel data when in check mode or - not. 0: no data output, 1: data output */ - uint32_t : 26; - } bit; - } DPC_CTRL; - - union { - __IOM uint32_t reg; /*!< DPC parameter config register */ - - struct { - __IOM uint32_t DPC_THRESHOLD_L : 8; /*!< this bit configures the threshold to detect black img in check - mode, or the low threshold(use 8 bit 0~255) in dyn method - 0, or the low threshold factor (use 5 bit 10000-> 16/16, - 00001->1/16, 0/16~16/16) in dyn method 1 */ - __IOM uint32_t DPC_THRESHOLD_H : 8; /*!< this bit configures the threshold to detect white img in check - mode, or the high threshold(use 8 bit 0~255) in dyn method - 0, or the high threshold factor (use 5 bit 10000-> 16/16, - 00001->1/16, 0/16~16/16) in dyn method 1 */ - __IOM uint32_t DPC_FACTOR_DARK : 6; /*!< this field configures the dynamic correction method 1 dark factor */ - __IOM uint32_t DPC_FACTOR_BRIG : 6; /*!< this field configures the dynamic correction method 1 bright - factor */ - uint32_t : 4; - } bit; - } DPC_CONF; - - union { - __IOM uint32_t reg; /*!< dpc pix2matrix ctrl */ - - struct { - __IOM uint32_t DPC_TAIL_PIXEN_PULSE_TL : 8;/*!< matrix tail pixen low level threshold, should not to large to - prevent expanding to next frame, only reg_dpc_tail_pixen_pulse_th!=0 - and reg_dpc_tail_pixen_pulse_tl!=0 and reg_dpc_tail_pixen_pulse_th - < reg_dpc_tail_pixen_pulse_tl will enable tail pulse function */ - __IOM uint32_t DPC_TAIL_PIXEN_PULSE_TH : 8;/*!< matrix tail pixen high level threshold, must < hnum-1, only - reg_dpc_tail_pixen_pulse_th!=0 and reg_dpc_tail_pixen_pulse_tl!=0 - and reg_dpc_tail_pixen_pulse_th < reg_dpc_tail_pixen_pulse_tl - will enable tail pulse function */ - __IOM uint32_t DPC_PADDING_DATA : 8; /*!< this field configures dpc matrix padding data */ - __IOM uint32_t DPC_PADDING_MODE : 1; /*!< this bit configures the padding mode of dpc matrix. 0: use pixel - in image to do padding 1: use reg_padding_data to do padding */ - uint32_t : 7; - } bit; - } DPC_MATRIX_CTRL; - - union { - __IOM uint32_t reg; /*!< DPC dead-pix number register */ - - struct { - __IM uint32_t DPC_DEADPIX_CNT : 10; /*!< this field represents the dead pixel count */ - uint32_t : 22; - } bit; - } DPC_DEADPIX_CNT; - - union { - __IOM uint32_t reg; /*!< LUT command register */ - - struct { - __OM uint32_t LUT_ADDR : 12; /*!< this field configures the lut access addr, when select lsc lut, - [11:10]:00 sel gb_b lut, 01 sel r_gr lut */ - __OM uint32_t LUT_NUM : 4; /*!< this field configures the lut selection. 0000:LSC LUT 0001:DPC - LUT */ - __OM uint32_t LUT_CMD : 1; /*!< this bit configures the access event of lut. 0:rd 1: wr */ - uint32_t : 15; - } bit; - } LUT_CMD; - - union { - __IOM uint32_t reg; /*!< LUT write data register */ - - struct { - __IOM uint32_t LUT_WDATA : 32; /*!< this field configures the write data of lut. please initial - ISP_LUT_WDATA before write ISP_LUT_CMD register */ - } bit; - } LUT_WDATA; - - union { - __IOM uint32_t reg; /*!< LUT read data register */ - - struct { - __IM uint32_t LUT_RDATA : 32; /*!< this field represents the read data of lut. read ISP_LUT_RDATA - after write ISP_LUT_CMD register */ - } bit; - } LUT_RDATA; - - union { - __IOM uint32_t reg; /*!< LSC point in x-direction */ - - struct { - __IOM uint32_t LSC_XTABLESIZE : 5; /*!< this field configures lsc table size in x-direction */ - uint32_t : 27; - } bit; - } LSC_TABLESIZE; - - union { - __IOM uint32_t reg; /*!< demosaic pix2matrix ctrl */ - - struct { - __IOM uint32_t DEMOSAIC_TAIL_PIXEN_PULSE_TL : 8;/*!< matrix tail pixen low level threshold, should not to large to - prevent expanding to next frame, only reg_demosaic_tail_pixen_pulse_th!=0 - and reg_demosaic_tail_pixen_pulse_tl!=0 and reg_demosaic_tail_pixen_pulse - th < reg_demosaic_tail_pixen_pulse_tl will enable tail - pulse function */ - __IOM uint32_t DEMOSAIC_TAIL_PIXEN_PULSE_TH : 8;/*!< matrix tail pixen high level threshold, must < hnum-1, only - reg_demosaic_tail_pixen_pulse_th!=0 and reg_demosaic_tail_pixen_pulse_tl! - 0 and reg_demosaic_tail_pixen_pulse_th < reg_demosaic_tail_pixen_pulse_tl - will enable tail pulse function */ - __IOM uint32_t DEMOSAIC_PADDING_DATA : 8; /*!< this field configures demosaic matrix padding data */ - __IOM uint32_t DEMOSAIC_PADDING_MODE : 1; /*!< this bit configures the padding mode of demosaic matrix. 0: - use pixel in image to do padding 1: use reg_padding_data - to do padding */ - uint32_t : 7; - } bit; - } DEMOSAIC_MATRIX_CTRL; - - union { - __IOM uint32_t reg; /*!< demosaic gradient select ratio */ - - struct { - __IOM uint32_t DEMOSAIC_GRAD_RATIO : 6; /*!< this field configures demosaic gradient select ratio */ - uint32_t : 26; - } bit; - } DEMOSAIC_GRAD_RATIO; - - union { - __IOM uint32_t reg; /*!< median pix2matrix ctrl */ - - struct { - __IOM uint32_t MEDIAN_PADDING_DATA : 8; /*!< this field configures median matrix padding data */ - __IOM uint32_t MEDIAN_PADDING_MODE : 1; /*!< this bit configures the padding mode of median matrix. 0: use - pixel in image to do padding 1: use reg_padding_data to - do padding */ - uint32_t : 23; - } bit; - } MEDIAN_MATRIX_CTRL; - - union { - __IOM uint32_t reg; /*!< raw interrupt register */ - - struct { - __IM uint32_t ISP_DATA_TYPE_ERR_INT_RAW : 1;/*!< the raw interrupt status of input data type error. isp only - support RGB bayer data type, other type will report type_err_int */ - __IM uint32_t ISP_ASYNC_FIFO_OVF_INT_RAW : 1;/*!< the raw interrupt status of isp input fifo overflow */ - __IM uint32_t ISP_BUF_FULL_INT_RAW : 1; /*!< the raw interrupt status of isp input buffer full */ - __IM uint32_t ISP_HVNUM_SETTING_ERR_INT_RAW : 1;/*!< the raw interrupt status of hnum and vnum setting format error */ - __IM uint32_t ISP_DATA_TYPE_SETTING_ERR_INT_RAW : 1;/*!< the raw interrupt status of setting invalid reg_data_type */ - __IM uint32_t ISP_MIPI_HNUM_UNMATCH_INT_RAW : 1;/*!< the raw interrupt status of hnum setting unmatch with mipi input */ - __IM uint32_t DPC_CHECK_DONE_INT_RAW : 1;/*!< the raw interrupt status of dpc check done */ - __IM uint32_t GAMMA_XCOORD_ERR_INT_RAW : 1;/*!< the raw interrupt status of gamma setting error. it report the - sum of the lengths represented by reg_gamma_x00~x0F isn't - equal to 256 */ - __IM uint32_t AE_MONITOR_INT_RAW : 1; /*!< the raw interrupt status of ae monitor */ - __IM uint32_t AE_FRAME_DONE_INT_RAW : 1; /*!< the raw interrupt status of ae. */ - __IM uint32_t AF_FDONE_INT_RAW : 1; /*!< the raw interrupt status of af statistic. when auto_update enable, - each frame done will send one int pulse when manual_update, - each time when write 1 to reg_manual_update will send a - int pulse when next frame done */ - __IM uint32_t AF_ENV_INT_RAW : 1; /*!< the raw interrupt status of af monitor. send a int pulse when - env_det function enabled and environment changes detected */ - __IM uint32_t AWB_FDONE_INT_RAW : 1; /*!< the raw interrupt status of awb. send a int pulse when statistic - of one awb frame done */ - __IM uint32_t HIST_FDONE_INT_RAW : 1; /*!< the raw interrupt status of histogram. send a int pulse when - statistic of one frame histogram done */ - __IM uint32_t FRAME_INT_RAW : 1; /*!< the raw interrupt status of isp frame end */ - __IM uint32_t BLC_FRAME_INT_RAW : 1; /*!< the raw interrupt status of blc frame done */ - __IM uint32_t LSC_FRAME_INT_RAW : 1; /*!< the raw interrupt status of lsc frame done */ - __IM uint32_t DPC_FRAME_INT_RAW : 1; /*!< the raw interrupt status of dpc frame done */ - __IM uint32_t BF_FRAME_INT_RAW : 1; /*!< the raw interrupt status of bf frame done */ - __IM uint32_t DEMOSAIC_FRAME_INT_RAW : 1;/*!< the raw interrupt status of demosaic frame done */ - __IM uint32_t MEDIAN_FRAME_INT_RAW : 1; /*!< the raw interrupt status of median frame done */ - __IM uint32_t CCM_FRAME_INT_RAW : 1; /*!< the raw interrupt status of ccm frame done */ - __IM uint32_t GAMMA_FRAME_INT_RAW : 1; /*!< the raw interrupt status of gamma frame done */ - __IM uint32_t RGB2YUV_FRAME_INT_RAW : 1; /*!< the raw interrupt status of rgb2yuv frame done */ - __IM uint32_t SHARP_FRAME_INT_RAW : 1; /*!< the raw interrupt status of sharp frame done */ - __IM uint32_t COLOR_FRAME_INT_RAW : 1; /*!< the raw interrupt status of color frame done */ - __IM uint32_t YUV2RGB_FRAME_INT_RAW : 1; /*!< the raw interrupt status of yuv2rgb frame done */ - __IM uint32_t TAIL_IDI_FRAME_INT_RAW : 1;/*!< the raw interrupt status of isp_tail idi frame_end */ - __IM uint32_t HEADER_IDI_FRAME_INT_RAW : 1;/*!< the raw interrupt status of real input frame end of isp_input */ - uint32_t : 3; - } bit; - } INT_RAW; - - union { - __IOM uint32_t reg; /*!< masked interrupt register */ - - struct { - __IM uint32_t ISP_DATA_TYPE_ERR_INT_ST : 1;/*!< the masked interrupt status of input data type error */ - __IM uint32_t ISP_ASYNC_FIFO_OVF_INT_ST : 1;/*!< the masked interrupt status of isp input fifo overflow */ - __IM uint32_t ISP_BUF_FULL_INT_ST : 1; /*!< the masked interrupt status of isp input buffer full */ - __IM uint32_t ISP_HVNUM_SETTING_ERR_INT_ST : 1;/*!< the masked interrupt status of hnum and vnum setting format - error */ - __IM uint32_t ISP_DATA_TYPE_SETTING_ERR_INT_ST : 1;/*!< the masked interrupt status of setting invalid reg_data_type */ - __IM uint32_t ISP_MIPI_HNUM_UNMATCH_INT_ST : 1;/*!< the masked interrupt status of hnum setting unmatch with mipi - input */ - __IM uint32_t DPC_CHECK_DONE_INT_ST : 1; /*!< the masked interrupt status of dpc check done */ - __IM uint32_t GAMMA_XCOORD_ERR_INT_ST : 1;/*!< the masked interrupt status of gamma setting error */ - __IM uint32_t AE_MONITOR_INT_ST : 1; /*!< the masked interrupt status of ae monitor */ - __IM uint32_t AE_FRAME_DONE_INT_ST : 1; /*!< the masked interrupt status of ae */ - __IM uint32_t AF_FDONE_INT_ST : 1; /*!< the masked interrupt status of af statistic */ - __IM uint32_t AF_ENV_INT_ST : 1; /*!< the masked interrupt status of af monitor */ - __IM uint32_t AWB_FDONE_INT_ST : 1; /*!< the masked interrupt status of awb */ - __IM uint32_t HIST_FDONE_INT_ST : 1; /*!< the masked interrupt status of histogram */ - __IM uint32_t FRAME_INT_ST : 1; /*!< the masked interrupt status of isp frame end */ - __IM uint32_t BLC_FRAME_INT_ST : 1; /*!< the masked interrupt status of blc frame done */ - __IM uint32_t LSC_FRAME_INT_ST : 1; /*!< the masked interrupt status of lsc frame done */ - __IM uint32_t DPC_FRAME_INT_ST : 1; /*!< the masked interrupt status of dpc frame done */ - __IM uint32_t BF_FRAME_INT_ST : 1; /*!< the masked interrupt status of bf frame done */ - __IM uint32_t DEMOSAIC_FRAME_INT_ST : 1; /*!< the masked interrupt status of demosaic frame done */ - __IM uint32_t MEDIAN_FRAME_INT_ST : 1; /*!< the masked interrupt status of median frame done */ - __IM uint32_t CCM_FRAME_INT_ST : 1; /*!< the masked interrupt status of ccm frame done */ - __IM uint32_t GAMMA_FRAME_INT_ST : 1; /*!< the masked interrupt status of gamma frame done */ - __IM uint32_t RGB2YUV_FRAME_INT_ST : 1; /*!< the masked interrupt status of rgb2yuv frame done */ - __IM uint32_t SHARP_FRAME_INT_ST : 1; /*!< the masked interrupt status of sharp frame done */ - __IM uint32_t COLOR_FRAME_INT_ST : 1; /*!< the masked interrupt status of color frame done */ - __IM uint32_t YUV2RGB_FRAME_INT_ST : 1; /*!< the masked interrupt status of yuv2rgb frame done */ - __IM uint32_t TAIL_IDI_FRAME_INT_ST : 1; /*!< the masked interrupt status of isp_tail idi frame_end */ - __IM uint32_t HEADER_IDI_FRAME_INT_ST : 1;/*!< the masked interrupt status of real input frame end of isp_input */ - uint32_t : 3; - } bit; - } INT_ST; - - union { - __IOM uint32_t reg; /*!< interrupt enable register */ - - struct { - __IOM uint32_t ISP_DATA_TYPE_ERR_INT_ENA : 1;/*!< write 1 to enable input data type error */ - __IOM uint32_t ISP_ASYNC_FIFO_OVF_INT_ENA : 1;/*!< write 1 to enable isp input fifo overflow */ - __IOM uint32_t ISP_BUF_FULL_INT_ENA : 1; /*!< write 1 to enable isp input buffer full */ - __IOM uint32_t ISP_HVNUM_SETTING_ERR_INT_ENA : 1;/*!< write 1 to enable hnum and vnum setting format error */ - __IOM uint32_t ISP_DATA_TYPE_SETTING_ERR_INT_ENA : 1;/*!< write 1 to enable setting invalid reg_data_type */ - __IOM uint32_t ISP_MIPI_HNUM_UNMATCH_INT_ENA : 1;/*!< write 1 to enable hnum setting unmatch with mipi input */ - __IOM uint32_t DPC_CHECK_DONE_INT_ENA : 1;/*!< write 1 to enable dpc check done */ - __IOM uint32_t GAMMA_XCOORD_ERR_INT_ENA : 1;/*!< write 1 to enable gamma setting error */ - __IOM uint32_t AE_MONITOR_INT_ENA : 1; /*!< write 1 to enable ae monitor */ - __IOM uint32_t AE_FRAME_DONE_INT_ENA : 1; /*!< write 1 to enable ae */ - __IOM uint32_t AF_FDONE_INT_ENA : 1; /*!< write 1 to enable af statistic */ - __IOM uint32_t AF_ENV_INT_ENA : 1; /*!< write 1 to enable af monitor */ - __IOM uint32_t AWB_FDONE_INT_ENA : 1; /*!< write 1 to enable awb */ - __IOM uint32_t HIST_FDONE_INT_ENA : 1; /*!< write 1 to enable histogram */ - __IOM uint32_t FRAME_INT_ENA : 1; /*!< write 1 to enable isp frame end */ - __IOM uint32_t BLC_FRAME_INT_ENA : 1; /*!< write 1 to enable blc frame done */ - __IOM uint32_t LSC_FRAME_INT_ENA : 1; /*!< write 1 to enable lsc frame done */ - __IOM uint32_t DPC_FRAME_INT_ENA : 1; /*!< write 1 to enable dpc frame done */ - __IOM uint32_t BF_FRAME_INT_ENA : 1; /*!< write 1 to enable bf frame done */ - __IOM uint32_t DEMOSAIC_FRAME_INT_ENA : 1;/*!< write 1 to enable demosaic frame done */ - __IOM uint32_t MEDIAN_FRAME_INT_ENA : 1; /*!< write 1 to enable median frame done */ - __IOM uint32_t CCM_FRAME_INT_ENA : 1; /*!< write 1 to enable ccm frame done */ - __IOM uint32_t GAMMA_FRAME_INT_ENA : 1; /*!< write 1 to enable gamma frame done */ - __IOM uint32_t RGB2YUV_FRAME_INT_ENA : 1; /*!< write 1 to enable rgb2yuv frame done */ - __IOM uint32_t SHARP_FRAME_INT_ENA : 1; /*!< write 1 to enable sharp frame done */ - __IOM uint32_t COLOR_FRAME_INT_ENA : 1; /*!< write 1 to enable color frame done */ - __IOM uint32_t YUV2RGB_FRAME_INT_ENA : 1; /*!< write 1 to enable yuv2rgb frame done */ - __IOM uint32_t TAIL_IDI_FRAME_INT_ENA : 1;/*!< write 1 to enable isp_tail idi frame_end */ - __IOM uint32_t HEADER_IDI_FRAME_INT_ENA : 1;/*!< write 1 to enable real input frame end of isp_input */ - uint32_t : 3; - } bit; - } INT_ENA; - - union { - __IOM uint32_t reg; /*!< interrupt clear register */ - - struct { - __OM uint32_t ISP_DATA_TYPE_ERR_INT_CLR : 1;/*!< write 1 to clear input data type error */ - __OM uint32_t ISP_ASYNC_FIFO_OVF_INT_CLR : 1;/*!< write 1 to clear isp input fifo overflow */ - __OM uint32_t ISP_BUF_FULL_INT_CLR : 1; /*!< write 1 to clear isp input buffer full */ - __OM uint32_t ISP_HVNUM_SETTING_ERR_INT_CLR : 1;/*!< write 1 to clear hnum and vnum setting format error */ - __OM uint32_t ISP_DATA_TYPE_SETTING_ERR_INT_CLR : 1;/*!< write 1 to clear setting invalid reg_data_type */ - __OM uint32_t ISP_MIPI_HNUM_UNMATCH_INT_CLR : 1;/*!< write 1 to clear hnum setting unmatch with mipi input */ - __OM uint32_t DPC_CHECK_DONE_INT_CLR : 1;/*!< write 1 to clear dpc check done */ - __OM uint32_t GAMMA_XCOORD_ERR_INT_CLR : 1;/*!< write 1 to clear gamma setting error */ - __OM uint32_t AE_MONITOR_INT_CLR : 1; /*!< write 1 to clear ae monitor */ - __OM uint32_t AE_FRAME_DONE_INT_CLR : 1; /*!< write 1 to clear ae */ - __OM uint32_t AF_FDONE_INT_CLR : 1; /*!< write 1 to clear af statistic */ - __OM uint32_t AF_ENV_INT_CLR : 1; /*!< write 1 to clear af monitor */ - __OM uint32_t AWB_FDONE_INT_CLR : 1; /*!< write 1 to clear awb */ - __OM uint32_t HIST_FDONE_INT_CLR : 1; /*!< write 1 to clear histogram */ - __OM uint32_t FRAME_INT_CLR : 1; /*!< write 1 to clear isp frame end */ - __OM uint32_t BLC_FRAME_INT_CLR : 1; /*!< write 1 to clear blc frame done */ - __OM uint32_t LSC_FRAME_INT_CLR : 1; /*!< write 1 to clear lsc frame done */ - __OM uint32_t DPC_FRAME_INT_CLR : 1; /*!< write 1 to clear dpc frame done */ - __OM uint32_t BF_FRAME_INT_CLR : 1; /*!< write 1 to clear bf frame done */ - __OM uint32_t DEMOSAIC_FRAME_INT_CLR : 1;/*!< write 1 to clear demosaic frame done */ - __OM uint32_t MEDIAN_FRAME_INT_CLR : 1; /*!< write 1 to clear median frame done */ - __OM uint32_t CCM_FRAME_INT_CLR : 1; /*!< write 1 to clear ccm frame done */ - __OM uint32_t GAMMA_FRAME_INT_CLR : 1; /*!< write 1 to clear gamma frame done */ - __OM uint32_t RGB2YUV_FRAME_INT_CLR : 1; /*!< write 1 to clear rgb2yuv frame done */ - __OM uint32_t SHARP_FRAME_INT_CLR : 1; /*!< write 1 to clear sharp frame done */ - __OM uint32_t COLOR_FRAME_INT_CLR : 1; /*!< write 1 to clear color frame done */ - __OM uint32_t YUV2RGB_FRAME_INT_CLR : 1; /*!< write 1 to clear yuv2rgb frame done */ - __OM uint32_t TAIL_IDI_FRAME_INT_CLR : 1;/*!< write 1 to clear isp_tail idi frame_end */ - __OM uint32_t HEADER_IDI_FRAME_INT_CLR : 1;/*!< write 1 to clear real input frame end of isp_input */ - uint32_t : 3; - } bit; - } INT_CLR; - - union { - __IOM uint32_t reg; /*!< gamma control register */ - - struct { - __IOM uint32_t GAMMA_UPDATE : 1; /*!< Indicates that gamma register configuration is complete */ - __IOM uint32_t GAMMA_B_LAST_CORRECT : 1; /*!< this bit configures enable of last b segment correcction. 0: - disable, 1: enable */ - __IOM uint32_t GAMMA_G_LAST_CORRECT : 1; /*!< this bit configures enable of last g segment correcction. 0: - disable, 1: enable */ - __IOM uint32_t GAMMA_R_LAST_CORRECT : 1; /*!< this bit configures enable of last r segment correcction. 0: - disable, 1: enable */ - uint32_t : 28; - } bit; - } GAMMA_CTRL; - - union { - __IOM uint32_t reg; /*!< point of Y-axis of r channel gamma curve register 1 */ - - struct { - __IOM uint32_t GAMMA_R_Y03 : 8; /*!< this field configures the point 3 of Y-axis of r channel gamma - curve */ - __IOM uint32_t GAMMA_R_Y02 : 8; /*!< this field configures the point 2 of Y-axis of r channel gamma - curve */ - __IOM uint32_t GAMMA_R_Y01 : 8; /*!< this field configures the point 1 of Y-axis of r channel gamma - curve */ - __IOM uint32_t GAMMA_R_Y00 : 8; /*!< this field configures the point 0 of Y-axis of r channel gamma - curve */ - } bit; - } GAMMA_RY1; - - union { - __IOM uint32_t reg; /*!< point of Y-axis of r channel gamma curve register 2 */ - - struct { - __IOM uint32_t GAMMA_R_Y07 : 8; /*!< this field configures the point 7 of Y-axis of r channel gamma - curve */ - __IOM uint32_t GAMMA_R_Y06 : 8; /*!< this field configures the point 6 of Y-axis of r channel gamma - curve */ - __IOM uint32_t GAMMA_R_Y05 : 8; /*!< this field configures the point 5 of Y-axis of r channel gamma - curve */ - __IOM uint32_t GAMMA_R_Y04 : 8; /*!< this field configures the point 4 of Y-axis of r channel gamma - curve */ - } bit; - } GAMMA_RY2; - - union { - __IOM uint32_t reg; /*!< point of Y-axis of r channel gamma curve register 3 */ - - struct { - __IOM uint32_t GAMMA_R_Y0B : 8; /*!< this field configures the point 11 of Y-axis of r channel gamma - curve */ - __IOM uint32_t GAMMA_R_Y0A : 8; /*!< this field configures the point 10 of Y-axis of r channel gamma - curve */ - __IOM uint32_t GAMMA_R_Y09 : 8; /*!< this field configures the point 9 of Y-axis of r channel gamma - curve */ - __IOM uint32_t GAMMA_R_Y08 : 8; /*!< this field configures the point 8 of Y-axis of r channel gamma - curve */ - } bit; - } GAMMA_RY3; - - union { - __IOM uint32_t reg; /*!< point of Y-axis of r channel gamma curve register 4 */ - - struct { - __IOM uint32_t GAMMA_R_Y0F : 8; /*!< this field configures the point 15 of Y-axis of r channel gamma - curve */ - __IOM uint32_t GAMMA_R_Y0E : 8; /*!< this field configures the point 14 of Y-axis of r channel gamma - curve */ - __IOM uint32_t GAMMA_R_Y0D : 8; /*!< this field configures the point 13 of Y-axis of r channel gamma - curve */ - __IOM uint32_t GAMMA_R_Y0C : 8; /*!< this field configures the point 12 of Y-axis of r channel gamma - curve */ - } bit; - } GAMMA_RY4; - - union { - __IOM uint32_t reg; /*!< point of Y-axis of g channel gamma curve register 1 */ - - struct { - __IOM uint32_t GAMMA_G_Y03 : 8; /*!< this field configures the point 3 of Y-axis of g channel gamma - curve */ - __IOM uint32_t GAMMA_G_Y02 : 8; /*!< this field configures the point 2 of Y-axis of g channel gamma - curve */ - __IOM uint32_t GAMMA_G_Y01 : 8; /*!< this field configures the point 1 of Y-axis of g channel gamma - curve */ - __IOM uint32_t GAMMA_G_Y00 : 8; /*!< this field configures the point 0 of Y-axis of g channel gamma - curve */ - } bit; - } GAMMA_GY1; - - union { - __IOM uint32_t reg; /*!< point of Y-axis of g channel gamma curve register 2 */ - - struct { - __IOM uint32_t GAMMA_G_Y07 : 8; /*!< this field configures the point 7 of Y-axis of g channel gamma - curve */ - __IOM uint32_t GAMMA_G_Y06 : 8; /*!< this field configures the point 6 of Y-axis of g channel gamma - curve */ - __IOM uint32_t GAMMA_G_Y05 : 8; /*!< this field configures the point 5 of Y-axis of g channel gamma - curve */ - __IOM uint32_t GAMMA_G_Y04 : 8; /*!< this field configures the point 4 of Y-axis of g channel gamma - curve */ - } bit; - } GAMMA_GY2; - - union { - __IOM uint32_t reg; /*!< point of Y-axis of g channel gamma curve register 3 */ - - struct { - __IOM uint32_t GAMMA_G_Y0B : 8; /*!< this field configures the point 11 of Y-axis of g channel gamma - curve */ - __IOM uint32_t GAMMA_G_Y0A : 8; /*!< this field configures the point 10 of Y-axis of g channel gamma - curve */ - __IOM uint32_t GAMMA_G_Y09 : 8; /*!< this field configures the point 9 of Y-axis of g channel gamma - curve */ - __IOM uint32_t GAMMA_G_Y08 : 8; /*!< this field configures the point 8 of Y-axis of g channel gamma - curve */ - } bit; - } GAMMA_GY3; - - union { - __IOM uint32_t reg; /*!< point of Y-axis of g channel gamma curve register 4 */ - - struct { - __IOM uint32_t GAMMA_G_Y0F : 8; /*!< this field configures the point 15 of Y-axis of g channel gamma - curve */ - __IOM uint32_t GAMMA_G_Y0E : 8; /*!< this field configures the point 14 of Y-axis of g channel gamma - curve */ - __IOM uint32_t GAMMA_G_Y0D : 8; /*!< this field configures the point 13 of Y-axis of g channel gamma - curve */ - __IOM uint32_t GAMMA_G_Y0C : 8; /*!< this field configures the point 12 of Y-axis of g channel gamma - curve */ - } bit; - } GAMMA_GY4; - - union { - __IOM uint32_t reg; /*!< point of Y-axis of b channel gamma curve register 1 */ - - struct { - __IOM uint32_t GAMMA_B_Y03 : 8; /*!< this field configures the point 3 of Y-axis of b channel gamma - curve */ - __IOM uint32_t GAMMA_B_Y02 : 8; /*!< this field configures the point 2 of Y-axis of b channel gamma - curve */ - __IOM uint32_t GAMMA_B_Y01 : 8; /*!< this field configures the point 1 of Y-axis of b channel gamma - curve */ - __IOM uint32_t GAMMA_B_Y00 : 8; /*!< this field configures the point 0 of Y-axis of b channel gamma - curve */ - } bit; - } GAMMA_BY1; - - union { - __IOM uint32_t reg; /*!< point of Y-axis of b channel gamma curve register 2 */ - - struct { - __IOM uint32_t GAMMA_B_Y07 : 8; /*!< this field configures the point 7 of Y-axis of b channel gamma - curve */ - __IOM uint32_t GAMMA_B_Y06 : 8; /*!< this field configures the point 6 of Y-axis of b channel gamma - curve */ - __IOM uint32_t GAMMA_B_Y05 : 8; /*!< this field configures the point 5 of Y-axis of b channel gamma - curve */ - __IOM uint32_t GAMMA_B_Y04 : 8; /*!< this field configures the point 4 of Y-axis of b channel gamma - curve */ - } bit; - } GAMMA_BY2; - - union { - __IOM uint32_t reg; /*!< point of Y-axis of b channel gamma curve register 3 */ - - struct { - __IOM uint32_t GAMMA_B_Y0B : 8; /*!< this field configures the point 11 of Y-axis of b channel gamma - curve */ - __IOM uint32_t GAMMA_B_Y0A : 8; /*!< this field configures the point 10 of Y-axis of b channel gamma - curve */ - __IOM uint32_t GAMMA_B_Y09 : 8; /*!< this field configures the point 9 of Y-axis of b channel gamma - curve */ - __IOM uint32_t GAMMA_B_Y08 : 8; /*!< this field configures the point 8 of Y-axis of b channel gamma - curve */ - } bit; - } GAMMA_BY3; - - union { - __IOM uint32_t reg; /*!< point of Y-axis of b channel gamma curve register 4 */ - - struct { - __IOM uint32_t GAMMA_B_Y0F : 8; /*!< this field configures the point 15 of Y-axis of b channel gamma - curve */ - __IOM uint32_t GAMMA_B_Y0E : 8; /*!< this field configures the point 14 of Y-axis of b channel gamma - curve */ - __IOM uint32_t GAMMA_B_Y0D : 8; /*!< this field configures the point 13 of Y-axis of b channel gamma - curve */ - __IOM uint32_t GAMMA_B_Y0C : 8; /*!< this field configures the point 12 of Y-axis of b channel gamma - curve */ - } bit; - } GAMMA_BY4; - - union { - __IOM uint32_t reg; /*!< point of X-axis of r channel gamma curve register 1 */ - - struct { - __IOM uint32_t GAMMA_R_X07 : 3; /*!< this field configures the point 7 of X-axis of r channel gamma - curve, it represents the power of the distance from the - previous point */ - __IOM uint32_t GAMMA_R_X06 : 3; /*!< this field configures the point 6 of X-axis of r channel gamma - curve, it represents the power of the distance from the - previous point */ - __IOM uint32_t GAMMA_R_X05 : 3; /*!< this field configures the point 5 of X-axis of r channel gamma - curve, it represents the power of the distance from the - previous point */ - __IOM uint32_t GAMMA_R_X04 : 3; /*!< this field configures the point 4 of X-axis of r channel gamma - curve, it represents the power of the distance from the - previous point */ - __IOM uint32_t GAMMA_R_X03 : 3; /*!< this field configures the point 3 of X-axis of r channel gamma - curve, it represents the power of the distance from the - previous point */ - __IOM uint32_t GAMMA_R_X02 : 3; /*!< this field configures the point 2 of X-axis of r channel gamma - curve, it represents the power of the distance from the - previous point */ - __IOM uint32_t GAMMA_R_X01 : 3; /*!< this field configures the point 1 of X-axis of r channel gamma - curve, it represents the power of the distance from the - previous point */ - __IOM uint32_t GAMMA_R_X00 : 3; /*!< this field configures the point 0 of X-axis of r channel gamma - curve, it represents the power of the distance from the - previous point */ - uint32_t : 8; - } bit; - } GAMMA_RX1; - - union { - __IOM uint32_t reg; /*!< point of X-axis of r channel gamma curve register 2 */ - - struct { - __IOM uint32_t GAMMA_R_X0F : 3; /*!< this field configures the point 15 of X-axis of r channel gamma - curve, it represents the power of the distance from the - previous point */ - __IOM uint32_t GAMMA_R_X0E : 3; /*!< this field configures the point 14 of X-axis of r channel gamma - curve, it represents the power of the distance from the - previous point */ - __IOM uint32_t GAMMA_R_X0D : 3; /*!< this field configures the point 13 of X-axis of r channel gamma - curve, it represents the power of the distance from the - previous point */ - __IOM uint32_t GAMMA_R_X0C : 3; /*!< this field configures the point 12 of X-axis of r channel gamma - curve, it represents the power of the distance from the - previous point */ - __IOM uint32_t GAMMA_R_X0B : 3; /*!< this field configures the point 11 of X-axis of r channel gamma - curve, it represents the power of the distance from the - previous point */ - __IOM uint32_t GAMMA_R_X0A : 3; /*!< this field configures the point 10 of X-axis of r channel gamma - curve, it represents the power of the distance from the - previous point */ - __IOM uint32_t GAMMA_R_X09 : 3; /*!< this field configures the point 9 of X-axis of r channel gamma - curve, it represents the power of the distance from the - previous point */ - __IOM uint32_t GAMMA_R_X08 : 3; /*!< this field configures the point 8 of X-axis of r channel gamma - curve, it represents the power of the distance from the - previous point */ - uint32_t : 8; - } bit; - } GAMMA_RX2; - - union { - __IOM uint32_t reg; /*!< point of X-axis of g channel gamma curve register 1 */ - - struct { - __IOM uint32_t GAMMA_G_X07 : 3; /*!< this field configures the point 7 of X-axis of g channel gamma - curve, it represents the power of the distance from the - previous point */ - __IOM uint32_t GAMMA_G_X06 : 3; /*!< this field configures the point 6 of X-axis of g channel gamma - curve, it represents the power of the distance from the - previous point */ - __IOM uint32_t GAMMA_G_X05 : 3; /*!< this field configures the point 5 of X-axis of g channel gamma - curve, it represents the power of the distance from the - previous point */ - __IOM uint32_t GAMMA_G_X04 : 3; /*!< this field configures the point 4 of X-axis of g channel gamma - curve, it represents the power of the distance from the - previous point */ - __IOM uint32_t GAMMA_G_X03 : 3; /*!< this field configures the point 3 of X-axis of g channel gamma - curve, it represents the power of the distance from the - previous point */ - __IOM uint32_t GAMMA_G_X02 : 3; /*!< this field configures the point 2 of X-axis of g channel gamma - curve, it represents the power of the distance from the - previous point */ - __IOM uint32_t GAMMA_G_X01 : 3; /*!< this field configures the point 1 of X-axis of g channel gamma - curve, it represents the power of the distance from the - previous point */ - __IOM uint32_t GAMMA_G_X00 : 3; /*!< this field configures the point 0 of X-axis of g channel gamma - curve, it represents the power of the distance from the - previous point */ - uint32_t : 8; - } bit; - } GAMMA_GX1; - - union { - __IOM uint32_t reg; /*!< point of X-axis of g channel gamma curve register 2 */ - - struct { - __IOM uint32_t GAMMA_G_X0F : 3; /*!< this field configures the point 15 of X-axis of g channel gamma - curve, it represents the power of the distance from the - previous point */ - __IOM uint32_t GAMMA_G_X0E : 3; /*!< this field configures the point 14 of X-axis of g channel gamma - curve, it represents the power of the distance from the - previous point */ - __IOM uint32_t GAMMA_G_X0D : 3; /*!< this field configures the point 13 of X-axis of g channel gamma - curve, it represents the power of the distance from the - previous point */ - __IOM uint32_t GAMMA_G_X0C : 3; /*!< this field configures the point 12 of X-axis of g channel gamma - curve, it represents the power of the distance from the - previous point */ - __IOM uint32_t GAMMA_G_X0B : 3; /*!< this field configures the point 11 of X-axis of g channel gamma - curve, it represents the power of the distance from the - previous point */ - __IOM uint32_t GAMMA_G_X0A : 3; /*!< this field configures the point 10 of X-axis of g channel gamma - curve, it represents the power of the distance from the - previous point */ - __IOM uint32_t GAMMA_G_X09 : 3; /*!< this field configures the point 9 of X-axis of g channel gamma - curve, it represents the power of the distance from the - previous point */ - __IOM uint32_t GAMMA_G_X08 : 3; /*!< this field configures the point 8 of X-axis of g channel gamma - curve, it represents the power of the distance from the - previous point */ - uint32_t : 8; - } bit; - } GAMMA_GX2; - - union { - __IOM uint32_t reg; /*!< point of X-axis of b channel gamma curve register 1 */ - - struct { - __IOM uint32_t GAMMA_B_X07 : 3; /*!< this field configures the point 7 of X-axis of b channel gamma - curve, it represents the power of the distance from the - previous point */ - __IOM uint32_t GAMMA_B_X06 : 3; /*!< this field configures the point 6 of X-axis of b channel gamma - curve, it represents the power of the distance from the - previous point */ - __IOM uint32_t GAMMA_B_X05 : 3; /*!< this field configures the point 5 of X-axis of b channel gamma - curve, it represents the power of the distance from the - previous point */ - __IOM uint32_t GAMMA_B_X04 : 3; /*!< this field configures the point 4 of X-axis of b channel gamma - curve, it represents the power of the distance from the - previous point */ - __IOM uint32_t GAMMA_B_X03 : 3; /*!< this field configures the point 3 of X-axis of b channel gamma - curve, it represents the power of the distance from the - previous point */ - __IOM uint32_t GAMMA_B_X02 : 3; /*!< this field configures the point 2 of X-axis of b channel gamma - curve, it represents the power of the distance from the - previous point */ - __IOM uint32_t GAMMA_B_X01 : 3; /*!< this field configures the point 1 of X-axis of b channel gamma - curve, it represents the power of the distance from the - previous point */ - __IOM uint32_t GAMMA_B_X00 : 3; /*!< this field configures the point 0 of X-axis of b channel gamma - curve, it represents the power of the distance from the - previous point */ - uint32_t : 8; - } bit; - } GAMMA_BX1; - - union { - __IOM uint32_t reg; /*!< point of X-axis of b channel gamma curve register 2 */ - - struct { - __IOM uint32_t GAMMA_B_X0F : 3; /*!< this field configures the point 15 of X-axis of b channel gamma - curve, it represents the power of the distance from the - previous point */ - __IOM uint32_t GAMMA_B_X0E : 3; /*!< this field configures the point 14 of X-axis of b channel gamma - curve, it represents the power of the distance from the - previous point */ - __IOM uint32_t GAMMA_B_X0D : 3; /*!< this field configures the point 13 of X-axis of b channel gamma - curve, it represents the power of the distance from the - previous point */ - __IOM uint32_t GAMMA_B_X0C : 3; /*!< this field configures the point 12 of X-axis of b channel gamma - curve, it represents the power of the distance from the - previous point */ - __IOM uint32_t GAMMA_B_X0B : 3; /*!< this field configures the point 11 of X-axis of b channel gamma - curve, it represents the power of the distance from the - previous point */ - __IOM uint32_t GAMMA_B_X0A : 3; /*!< this field configures the point 10 of X-axis of b channel gamma - curve, it represents the power of the distance from the - previous point */ - __IOM uint32_t GAMMA_B_X09 : 3; /*!< this field configures the point 9 of X-axis of b channel gamma - curve, it represents the power of the distance from the - previous point */ - __IOM uint32_t GAMMA_B_X08 : 3; /*!< this field configures the point 8 of X-axis of b channel gamma - curve, it represents the power of the distance from the - previous point */ - uint32_t : 8; - } bit; - } GAMMA_BX2; - - union { - __IOM uint32_t reg; /*!< ae control register */ - - struct { - __OM uint32_t AE_UPDATE : 1; /*!< write 1 to this bit triggers one statistic event */ - __IOM uint32_t AE_SELECT : 1; /*!< this field configures ae input data source, 0: data from median, - 1: data from gama */ - uint32_t : 30; - } bit; - } AE_CTRL; - - union { - __IOM uint32_t reg; /*!< ae monitor control register */ - - struct { - __IOM uint32_t TL : 8; /*!< this field configures the lower lum threshold of ae monitor */ - __IOM uint32_t TH : 8; /*!< this field configures the higher lum threshold of ae monitor */ - __IOM uint32_t PERIOD : 6; /*!< this field cnfigures ae monitor frame period */ - uint32_t : 10; - } bit; - } AE_MONITOR; - - union { - __IOM uint32_t reg; /*!< ae window register in x-direction */ - - struct { - __IOM uint32_t AE_X_BSIZE : 11; /*!< this field configures every block x size */ - __IOM uint32_t AE_X_START : 11; /*!< this field configures first block start x address */ - uint32_t : 10; - } bit; - } AE_BX; - - union { - __IOM uint32_t reg; /*!< ae window register in y-direction */ - - struct { - __IOM uint32_t AE_Y_BSIZE : 11; /*!< this field configures every block y size */ - __IOM uint32_t AE_Y_START : 11; /*!< this field configures first block start y address */ - uint32_t : 10; - } bit; - } AE_BY; - - union { - __IOM uint32_t reg; /*!< ae sub-window pix num register */ - - struct { - __IOM uint32_t AE_SUBWIN_PIXNUM : 17; /*!< this field configures the pixel number of each sub win */ - uint32_t : 15; - } bit; - } AE_WINPIXNUM; - - union { - __IOM uint32_t reg; /*!< reciprocal of ae sub-window pixel number */ - - struct { - __IOM uint32_t AE_SUBWIN_RECIP : 20; /*!< this field configures the reciprocal of each subwin_pixnum, - 20bit fraction */ - uint32_t : 12; - } bit; - } AE_WIN_RECIPROCAL; - - union { - __IOM uint32_t reg; /*!< ae statistic result register 0 */ - - struct { - __IM uint32_t AE_B03_MEAN : 8; /*!< this field configures block03 Y mean data */ - __IM uint32_t AE_B02_MEAN : 8; /*!< this field configures block02 Y mean data */ - __IM uint32_t AE_B01_MEAN : 8; /*!< this field configures block01 Y mean data */ - __IM uint32_t AE_B00_MEAN : 8; /*!< this field configures block00 Y mean data */ - } bit; - } AE_BLOCK_MEAN_0; - - union { - __IOM uint32_t reg; /*!< ae statistic result register 1 */ - - struct { - __IM uint32_t AE_B12_MEAN : 8; /*!< this field configures block12 Y mean data */ - __IM uint32_t AE_B11_MEAN : 8; /*!< this field configures block11 Y mean data */ - __IM uint32_t AE_B10_MEAN : 8; /*!< this field configures block10 Y mean data */ - __IM uint32_t AE_B04_MEAN : 8; /*!< this field configures block04 Y mean data */ - } bit; - } AE_BLOCK_MEAN_1; - - union { - __IOM uint32_t reg; /*!< ae statistic result register 2 */ - - struct { - __IM uint32_t AE_B21_MEAN : 8; /*!< this field configures block21 Y mean data */ - __IM uint32_t AE_B20_MEAN : 8; /*!< this field configures block20 Y mean data */ - __IM uint32_t AE_B14_MEAN : 8; /*!< this field configures block14 Y mean data */ - __IM uint32_t AE_B13_MEAN : 8; /*!< this field configures block13 Y mean data */ - } bit; - } AE_BLOCK_MEAN_2; - - union { - __IOM uint32_t reg; /*!< ae statistic result register 3 */ - - struct { - __IM uint32_t AE_B30_MEAN : 8; /*!< this field configures block30 Y mean data */ - __IM uint32_t AE_B24_MEAN : 8; /*!< this field configures block24 Y mean data */ - __IM uint32_t AE_B23_MEAN : 8; /*!< this field configures block23 Y mean data */ - __IM uint32_t AE_B22_MEAN : 8; /*!< this field configures block22 Y mean data */ - } bit; - } AE_BLOCK_MEAN_3; - - union { - __IOM uint32_t reg; /*!< ae statistic result register 4 */ - - struct { - __IM uint32_t AE_B34_MEAN : 8; /*!< this field configures block34 Y mean data */ - __IM uint32_t AE_B33_MEAN : 8; /*!< this field configures block33 Y mean data */ - __IM uint32_t AE_B32_MEAN : 8; /*!< this field configures block32 Y mean data */ - __IM uint32_t AE_B31_MEAN : 8; /*!< this field configures block31 Y mean data */ - } bit; - } AE_BLOCK_MEAN_4; - - union { - __IOM uint32_t reg; /*!< ae statistic result register 5 */ - - struct { - __IM uint32_t AE_B43_MEAN : 8; /*!< this field configures block43 Y mean data */ - __IM uint32_t AE_B42_MEAN : 8; /*!< this field configures block42 Y mean data */ - __IM uint32_t AE_B41_MEAN : 8; /*!< this field configures block41 Y mean data */ - __IM uint32_t AE_B40_MEAN : 8; /*!< this field configures block40 Y mean data */ - } bit; - } AE_BLOCK_MEAN_5; - - union { - __IOM uint32_t reg; /*!< ae statistic result register 6 */ - - struct { - uint32_t : 24; - __IM uint32_t AE_B44_MEAN : 8; /*!< this field configures block44 Y mean data */ - } bit; - } AE_BLOCK_MEAN_6; - - union { - __IOM uint32_t reg; /*!< sharp control register 0 */ - - struct { - __IOM uint32_t SHARP_THRESHOLD_LOW : 8; /*!< this field configures sharpen threshold for detail */ - __IOM uint32_t SHARP_THRESHOLD_HIGH : 8; /*!< this field configures sharpen threshold for edge */ - __IOM uint32_t SHARP_AMOUNT_LOW : 8; /*!< this field configures sharpen amount for detail */ - __IOM uint32_t SHARP_AMOUNT_HIGH : 8; /*!< this field configures sharpen amount for edge */ - } bit; - } SHARP_CTRL0; - - union { - __IOM uint32_t reg; /*!< sharp usm config register 0 */ - - struct { - __IOM uint32_t SHARP_FILTER_COE00 : 5; /*!< this field configures unsharp masking(usm) filter coefficient */ - __IOM uint32_t SHARP_FILTER_COE01 : 5; /*!< this field configures usm filter coefficient */ - __IOM uint32_t SHARP_FILTER_COE02 : 5; /*!< this field configures usm filter coefficient */ - uint32_t : 17; - } bit; - } SHARP_FILTER0; - - union { - __IOM uint32_t reg; /*!< sharp usm config register 1 */ - - struct { - __IOM uint32_t SHARP_FILTER_COE10 : 5; /*!< this field configures usm filter coefficient */ - __IOM uint32_t SHARP_FILTER_COE11 : 5; /*!< this field configures usm filter coefficient */ - __IOM uint32_t SHARP_FILTER_COE12 : 5; /*!< this field configures usm filter coefficient */ - uint32_t : 17; - } bit; - } SHARP_FILTER1; - - union { - __IOM uint32_t reg; /*!< sharp usm config register 2 */ - - struct { - __IOM uint32_t SHARP_FILTER_COE20 : 5; /*!< this field configures usm filter coefficient */ - __IOM uint32_t SHARP_FILTER_COE21 : 5; /*!< this field configures usm filter coefficient */ - __IOM uint32_t SHARP_FILTER_COE22 : 5; /*!< this field configures usm filter coefficient */ - uint32_t : 17; - } bit; - } SHARP_FILTER2; - - union { - __IOM uint32_t reg; /*!< sharp pix2matrix ctrl */ - - struct { - __IOM uint32_t SHARP_TAIL_PIXEN_PULSE_TL : 8;/*!< matrix tail pixen low level threshold, should not to large to - prevent expanding to next frame, only reg_demosaic_tail_pixen_pulse_th!=0 - and reg_demosaic_tail_pixen_pulse_tl!=0 and reg_demosaic_tail_pixen_pulse - th < reg_demosaic_tail_pixen_pulse_tl will enable tail - pulse function */ - __IOM uint32_t SHARP_TAIL_PIXEN_PULSE_TH : 8;/*!< matrix tail pixen high level threshold, must < hnum-1, only - reg_sharp_tail_pixen_pulse_th!=0 and reg_sharp_tail_pixen_pulse_tl!=0 - and reg_sharp_tail_pixen_pulse_th < reg_sharp_tail_pixen_pulse_tl - will enable tail pulse function */ - __IOM uint32_t SHARP_PADDING_DATA : 8; /*!< this field configures sharp padding data */ - __IOM uint32_t SHARP_PADDING_MODE : 1; /*!< this field configures sharp padding mode */ - uint32_t : 7; - } bit; - } SHARP_MATRIX_CTRL; - - union { - __IOM uint32_t reg; /*!< sharp control register 1 */ - - struct { - __IM uint32_t SHARP_GRADIENT_MAX : 8; /*!< this field configures sharp max gradient, refresh at the end - of each frame end */ - uint32_t : 24; - } bit; - } SHARP_CTRL1; - - union { - __IOM uint32_t reg; /*!< isp dma source trans control register */ - - struct { - __OM uint32_t DMA_EN : 1; /*!< write 1 to triger dma to get 1 frame */ - __IOM uint32_t DMA_UPDATE : 1; /*!< write 1 to update reg_dma_burst_len & reg_dma_data_type */ - __IOM uint32_t DMA_DATA_TYPE : 6; /*!< this field configures the idi data type for image data */ - __IOM uint32_t DMA_BURST_LEN : 12; /*!< this field configures dma burst len when data source is dma. - set according to dma_msize, it is the number of 64bits - in a dma transfer */ - __IOM uint32_t DMA_INTERVAL : 12; /*!< this field configures dma req interval, 12'b1: 1 cycle, 12'b11 - 2 cycle ... */ - } bit; - } DMA_CNTL; - - union { - __IOM uint32_t reg; /*!< isp dma source total raw number set register */ - - struct { - __IOM uint32_t DMA_RAW_NUM_TOTAL : 22; /*!< this field configures the the number of 64bits in a frame */ - uint32_t : 9; - __OM uint32_t DMA_RAW_NUM_TOTAL_SET : 1; /*!< write 1 to update reg_dma_raw_num_total */ - } bit; - } DMA_RAW_DATA; - - union { - __IOM uint32_t reg; /*!< isp cam source control register */ - - struct { - __IOM uint32_t CAM_EN : 1; /*!< write 1 to start recive camera data, write 0 to disable */ - __IOM uint32_t CAM_UPDATE : 1; /*!< write 1 to update ISP_CAM_CONF */ - __IOM uint32_t CAM_RESET : 1; /*!< this bit configures cam clk domain reset, 1: reset cam input - logic, 0: release reset */ - __IOM uint32_t CAM_CLK_INV : 1; /*!< this bit configures the invertion of cam clk from pad. 0: not - invert cam clk, 1: invert cam clk */ - uint32_t : 28; - } bit; - } CAM_CNTL; - - union { - __IOM uint32_t reg; /*!< isp cam source config register */ - - struct { - __IOM uint32_t CAM_DATA_ORDER : 1; /*!< this field configures data order of cam port, 0: cam_data_in, - 1:{cam_data_in[7:0], cam_data_in[15:8]} */ - __IOM uint32_t CAM_2BYTE_MODE : 1; /*!< this field configures enable of cam 2 byte mode(input 2 bytes - each clock). 0: disable, 1: enable */ - __IOM uint32_t CAM_DATA_TYPE : 6; /*!< this field configures idi data type for image data, 0x2a: RAW8, - 0x2b: RAW10, 0x2c: RAW12 */ - __IOM uint32_t CAM_DE_INV : 1; /*!< this bit configures cam data enable invert. 0: not invert, 1: - invert */ - __IOM uint32_t CAM_HSYNC_INV : 1; /*!< this bit configures cam hsync invert. 0: not invert, 1: invert */ - __IOM uint32_t CAM_VSYNC_INV : 1; /*!< this bit configures cam vsync invert. 0: not invert, 1: invert */ - __IOM uint32_t CAM_VSYNC_FILTER_THRES : 3;/*!< this bit configures the number of clock of vsync filter length */ - __IOM uint32_t CAM_VSYNC_FILTER_EN : 1; /*!< this bit configures vsync filter en */ - uint32_t : 17; - } bit; - } CAM_CONF; - - union { - __IOM uint32_t reg; /*!< af control register 0 */ - - struct { - __IOM uint32_t AF_AUTO_UPDATE : 1; /*!< this bit configures auto_update enable. when set to 1, will - update sum and lum each frame */ - uint32_t : 3; - __OM uint32_t AF_MANUAL_UPDATE : 1; /*!< write 1 to this bit will update the sum and lum once */ - uint32_t : 3; - __IOM uint32_t AF_ENV_THRESHOLD : 4; /*!< this field configures env threshold. when both sum and lum changes - larger than this value, consider environment changes and - need to trigger a new autofocus. 4Bit fractional */ - uint32_t : 4; - __IOM uint32_t AF_ENV_PERIOD : 8; /*!< this field configures environment changes detection period (frame). - When set to 0, disable this function */ - uint32_t : 8; - } bit; - } AF_CTRL0; - - union { - __IOM uint32_t reg; /*!< af control register 1 */ - - struct { - __IOM uint32_t AF_THPIXNUM : 22; /*!< this field configures pixnum used when calculating the autofocus - threshold. Set to 0 to disable threshold calculation */ - uint32_t : 10; - } bit; - } AF_CTRL1; - - union { - __IOM uint32_t reg; /*!< af gen threshold control register */ - - struct { - __IOM uint32_t AF_GEN_THRESHOLD_MIN : 16; /*!< this field configures min threshold when use auto_threshold */ - __IOM uint32_t AF_GEN_THRESHOLD_MAX : 16; /*!< this field configures max threshold when use auto_threshold */ - } bit; - } AF_GEN_TH_CTRL; - - union { - __IOM uint32_t reg; /*!< af monitor user sum threshold register */ - - struct { - __IOM uint32_t AF_ENV_USER_THRESHOLD_SUM : 32;/*!< this field configures user setup env detect sum threshold */ - } bit; - } AF_ENV_USER_TH_SUM; - - union { - __IOM uint32_t reg; /*!< af monitor user lum threshold register */ - - struct { - __IOM uint32_t AF_ENV_USER_THRESHOLD_LUM : 30;/*!< this field configures user setup env detect lum threshold */ - uint32_t : 2; - } bit; - } AF_ENV_USER_TH_LUM; - - union { - __IOM uint32_t reg; /*!< af threshold register */ - - struct { - __IOM uint32_t AF_THRESHOLD : 16; /*!< this field configures user threshold. When set to non-zero, - autofocus will use this threshold */ - __IM uint32_t AF_GEN_THRESHOLD : 16; /*!< this field represents the last calculated threshold */ - } bit; - } AF_THRESHOLD; - - union { - __IOM uint32_t reg; /*!< h-scale of af window a register */ - - struct { - __IOM uint32_t AF_RPOINT_A : 12; /*!< this field configures left coordinate of focus window a, must - >= 2 */ - uint32_t : 4; - __IOM uint32_t AF_LPOINT_A : 12; /*!< this field configures top coordinate of focus window a, must - >= 2 */ - uint32_t : 4; - } bit; - } AF_HSCALE_A; - - union { - __IOM uint32_t reg; /*!< v-scale of af window a register */ - - struct { - __IOM uint32_t AF_BPOINT_A : 12; /*!< this field configures right coordinate of focus window a, must - <= hnum-2 */ - uint32_t : 4; - __IOM uint32_t AF_TPOINT_A : 12; /*!< this field configures bottom coordinate of focus window a, must - <= hnum-2 */ - uint32_t : 4; - } bit; - } AF_VSCALE_A; - - union { - __IOM uint32_t reg; /*!< h-scale of af window b register */ - - struct { - __IOM uint32_t AF_RPOINT_B : 12; /*!< this field configures left coordinate of focus window b, must - >= 2 */ - uint32_t : 4; - __IOM uint32_t AF_LPOINT_B : 12; /*!< this field configures top coordinate of focus window b, must - >= 2 */ - uint32_t : 4; - } bit; - } AF_HSCALE_B; - - union { - __IOM uint32_t reg; /*!< v-scale of af window b register */ - - struct { - __IOM uint32_t AF_BPOINT_B : 12; /*!< this field configures right coordinate of focus window b, must - <= hnum-2 */ - uint32_t : 4; - __IOM uint32_t AF_TPOINT_B : 12; /*!< this field configures bottom coordinate of focus window b, must - <= hnum-2 */ - uint32_t : 4; - } bit; - } AF_VSCALE_B; - - union { - __IOM uint32_t reg; /*!< v-scale of af window c register */ - - struct { - __IOM uint32_t AF_RPOINT_C : 12; /*!< this field configures left coordinate of focus window c, must - >= 2 */ - uint32_t : 4; - __IOM uint32_t AF_LPOINT_C : 12; /*!< this field configures top coordinate of focus window c, must - >= 2 */ - uint32_t : 4; - } bit; - } AF_HSCALE_C; - - union { - __IOM uint32_t reg; /*!< v-scale of af window c register */ - - struct { - __IOM uint32_t AF_BPOINT_C : 12; /*!< this field configures right coordinate of focus window c, must - <= hnum-2 */ - uint32_t : 4; - __IOM uint32_t AF_TPOINT_C : 12; /*!< this field configures bottom coordinate of focus window c, must - <= hnum-2 */ - uint32_t : 4; - } bit; - } AF_VSCALE_C; - - union { - __IOM uint32_t reg; /*!< result of sum of af window a */ - - struct { - __IM uint32_t AF_SUMA : 30; /*!< this field represents the result of accumulation of pix grad - of focus window a */ - uint32_t : 2; - } bit; - } AF_SUM_A; - - union { - __IOM uint32_t reg; /*!< result of sum of af window b */ - - struct { - __IM uint32_t AF_SUMB : 30; /*!< this field represents the result of accumulation of pix grad - of focus window b */ - uint32_t : 2; - } bit; - } AF_SUM_B; - - union { - __IOM uint32_t reg; /*!< result of sum of af window c */ - - struct { - __IM uint32_t AF_SUMC : 30; /*!< this field represents the result of accumulation of pix grad - of focus window c */ - uint32_t : 2; - } bit; - } AF_SUM_C; - - union { - __IOM uint32_t reg; /*!< result of lum of af window a */ - - struct { - __IM uint32_t AF_LUMA : 28; /*!< this field represents the result of accumulation of pix light - of focus window a */ - uint32_t : 4; - } bit; - } AF_LUM_A; - - union { - __IOM uint32_t reg; /*!< result of lum of af window b */ - - struct { - __IM uint32_t AF_LUMB : 28; /*!< this field represents the result of accumulation of pix light - of focus window b */ - uint32_t : 4; - } bit; - } AF_LUM_B; - - union { - __IOM uint32_t reg; /*!< result of lum of af window c */ - - struct { - __IM uint32_t AF_LUMC : 28; /*!< this field represents the result of accumulation of pix light - of focus window c */ - uint32_t : 4; - } bit; - } AF_LUM_C; - - union { - __IOM uint32_t reg; /*!< awb mode control register */ - - struct { - __IOM uint32_t AWB_MODE : 2; /*!< this field configures awb algo sel. 00: none sellected. 01: - sel algo0. 10: sel algo1. 11: sel both algo0 and algo1 */ - uint32_t : 2; - __IOM uint32_t AWB_SAMPLE : 1; /*!< this bit configures awb sample location, 0:before ccm, 1:after - ccm */ - uint32_t : 27; - } bit; - } AWB_MODE; - - union { - __IOM uint32_t reg; /*!< h-scale of awb window */ - - struct { - __IOM uint32_t AWB_RPOINT : 12; /*!< this field configures awb window right coordinate */ - uint32_t : 4; - __IOM uint32_t AWB_LPOINT : 12; /*!< this field configures awb window left coordinate */ - uint32_t : 4; - } bit; - } AWB_HSCALE; - - union { - __IOM uint32_t reg; /*!< v-scale of awb window */ - - struct { - __IOM uint32_t AWB_BPOINT : 12; /*!< this field configures awb window bottom coordinate */ - uint32_t : 4; - __IOM uint32_t AWB_TPOINT : 12; /*!< this field configures awb window top coordinate */ - uint32_t : 4; - } bit; - } AWB_VSCALE; - - union { - __IOM uint32_t reg; /*!< awb lum threshold register */ - - struct { - __IOM uint32_t AWB_MIN_LUM : 10; /*!< this field configures lower threshold of r+g+b */ - uint32_t : 6; - __IOM uint32_t AWB_MAX_LUM : 10; /*!< this field configures upper threshold of r+g+b */ - uint32_t : 6; - } bit; - } AWB_TH_LUM; - - union { - __IOM uint32_t reg; /*!< awb r/g threshold register */ - - struct { - __IOM uint32_t AWB_MIN_RG : 10; /*!< this field configures lower threshold of r/g, 2bit integer and - 8bit fraction */ - uint32_t : 6; - __IOM uint32_t AWB_MAX_RG : 10; /*!< this field configures upper threshold of r/g, 2bit integer and - 8bit fraction */ - uint32_t : 6; - } bit; - } AWB_TH_RG; - - union { - __IOM uint32_t reg; /*!< awb b/g threshold register */ - - struct { - __IOM uint32_t AWB_MIN_BG : 10; /*!< this field configures lower threshold of b/g, 2bit integer and - 8bit fraction */ - uint32_t : 6; - __IOM uint32_t AWB_MAX_BG : 10; /*!< this field configures upper threshold of b/g, 2bit integer and - 8bit fraction */ - uint32_t : 6; - } bit; - } AWB_TH_BG; - - union { - __IOM uint32_t reg; /*!< result of awb white point number */ - - struct { - __IM uint32_t AWB0_WHITE_CNT : 24; /*!< this field configures number of white point detected of algo0 */ - uint32_t : 8; - } bit; - } AWB0_WHITE_CNT; - - union { - __IOM uint32_t reg; /*!< result of accumulate of r channel of all white points */ - - struct { - __IM uint32_t AWB0_ACC_R : 32; /*!< this field represents accumulate of channel r of all white point - of algo0 */ - } bit; - } AWB0_ACC_R; - - union { - __IOM uint32_t reg; /*!< result of accumulate of g channel of all white points */ - - struct { - __IM uint32_t AWB0_ACC_G : 32; /*!< this field represents accumulate of channel g of all white point - of algo0 */ - } bit; - } AWB0_ACC_G; - - union { - __IOM uint32_t reg; /*!< result of accumulate of b channel of all white points */ - - struct { - __IM uint32_t AWB0_ACC_B : 32; /*!< this field represents accumulate of channel b of all white point - of algo0 */ - } bit; - } AWB0_ACC_B; - - union { - __IOM uint32_t reg; /*!< color control register */ - - struct { - __IOM uint32_t COLOR_SATURATION : 8; /*!< this field configures the color saturation value */ - __IOM uint32_t COLOR_HUE : 8; /*!< this field configures the color hue angle */ - __IOM uint32_t COLOR_CONTRAST : 8; /*!< this field configures the color contrast value */ - __IOM uint32_t COLOR_BRIGHTNESS : 8; /*!< this field configures the color brightness value, signed 2's - complement */ - } bit; - } COLOR_CTRL; - - union { - __IOM uint32_t reg; /*!< blc black level register */ - - struct { - __IOM uint32_t BLC_R3_VALUE : 8; /*!< this field configures the black level of bottom right channel - of bayer img */ - __IOM uint32_t BLC_R2_VALUE : 8; /*!< this field configures the black level of bottom left channel - of bayer img */ - __IOM uint32_t BLC_R1_VALUE : 8; /*!< this field configures the black level of top right channel of - bayer img */ - __IOM uint32_t BLC_R0_VALUE : 8; /*!< this field configures the black level of top left channel of - bayer img */ - } bit; - } BLC_VALUE; - - union { - __IOM uint32_t reg; /*!< blc stretch control register */ - - struct { - __IOM uint32_t BLC_R3_STRETCH : 1; /*!< this bit configures the stretch feature of bottom right channel. - 0: stretch disable, 1: stretch enable */ - __IOM uint32_t BLC_R2_STRETCH : 1; /*!< this bit configures the stretch feature of bottom left channel. - 0: stretch disable, 1: stretch enable */ - __IOM uint32_t BLC_R1_STRETCH : 1; /*!< this bit configures the stretch feature of top right channel. - 0: stretch disable, 1: stretch enable */ - __IOM uint32_t BLC_R0_STRETCH : 1; /*!< this bit configures the stretch feature of top left channel. - 0: stretch disable, 1: stretch enable */ - uint32_t : 28; - } bit; - } BLC_CTRL0; - - union { - __IOM uint32_t reg; /*!< blc window control register */ - - struct { - __IOM uint32_t BLC_WINDOW_TOP : 11; /*!< this field configures blc average calculation window top */ - __IOM uint32_t BLC_WINDOW_LEFT : 11; /*!< this field configures blc average calculation window left */ - __IOM uint32_t BLC_WINDOW_VNUM : 4; /*!< this field configures blc average calculation window vnum */ - __IOM uint32_t BLC_WINDOW_HNUM : 4; /*!< this field configures blc average calculation window hnum */ - __IOM uint32_t BLC_FILTER_EN : 1; /*!< this bit configures enable blc average input filter. 0: disable, - 1: enable */ - uint32_t : 1; - } bit; - } BLC_CTRL1; - - union { - __IOM uint32_t reg; /*!< blc black threshold control register */ - - struct { - __IOM uint32_t BLC_R3_TH : 8; /*!< this field configures black threshold when get blc average of - bottom right channel */ - __IOM uint32_t BLC_R2_TH : 8; /*!< this field configures black threshold when get blc average of - bottom left channel */ - __IOM uint32_t BLC_R1_TH : 8; /*!< this field configures black threshold when get blc average of - top right channel */ - __IOM uint32_t BLC_R0_TH : 8; /*!< this field configures black threshold when get blc average of - top left channel */ - } bit; - } BLC_CTRL2; - - union { - __IOM uint32_t reg; /*!< results of the average of black window */ - - struct { - __IM uint32_t BLC_R3_MEAN : 8; /*!< this field represents the average black value of bottom right - channel */ - __IM uint32_t BLC_R2_MEAN : 8; /*!< this field represents the average black value of bottom left - channel */ - __IM uint32_t BLC_R1_MEAN : 8; /*!< this field represents the average black value of top right channel */ - __IM uint32_t BLC_R0_MEAN : 8; /*!< this field represents the average black value of top left channel */ - } bit; - } BLC_MEAN; - - union { - __IOM uint32_t reg; /*!< histogram mode control register */ - - struct { - __IOM uint32_t HIST_MODE : 3; /*!< this field configures statistic mode. 0: RAW_B, 1: RAW_GB, 2: - RAW_GR 3: RAW_R, 4: RGB, 5:YUV_Y, 6:YUV_U, 7:YUV_V */ - uint32_t : 29; - } bit; - } HIST_MODE; - - union { - __IOM uint32_t reg; /*!< histogram rgb to gray coefficients register */ - - struct { - __IOM uint32_t B : 8; /*!< this field configures coefficient of B when set hist_mode to - RGB, sum of coeff_r and coeff_g and coeff_b should be 256 */ - __IOM uint32_t G : 8; /*!< this field configures coefficient of G when set hist_mode to - RGB, sum of coeff_r and coeff_g and coeff_b should be 256 */ - __IOM uint32_t R : 8; /*!< this field configures coefficient of R when set hist_mode to - RGB, sum of coeff_r and coeff_g and coeff_b should be 256 */ - uint32_t : 8; - } bit; - } HIST_COEFF; - - union { - __IOM uint32_t reg; /*!< histogram window offsets register */ - - struct { - __IOM uint32_t HIST_Y_OFFS : 12; /*!< this field configures y coordinate of first window */ - uint32_t : 4; - __IOM uint32_t HIST_X_OFFS : 12; /*!< this field configures x coordinate of first window */ - uint32_t : 4; - } bit; - } HIST_OFFS; - - union { - __IOM uint32_t reg; /*!< histogram sub-window size register */ - - struct { - __IOM uint32_t HIST_Y_SIZE : 9; /*!< this field configures y direction size of subwindow */ - uint32_t : 7; - __IOM uint32_t HIST_X_SIZE : 9; /*!< this field configures x direction size of subwindow */ - uint32_t : 7; - } bit; - } HIST_SIZE; - - union { - __IOM uint32_t reg; /*!< histogram bin control register 0 */ - - struct { - __IOM uint32_t HIST_SEG_3_4 : 8; /*!< this field configures threshold of histogram bin 3 and bin 4 */ - __IOM uint32_t HIST_SEG_2_3 : 8; /*!< this field configures threshold of histogram bin 2 and bin 3 */ - __IOM uint32_t HIST_SEG_1_2 : 8; /*!< this field configures threshold of histogram bin 1 and bin 2 */ - __IOM uint32_t HIST_SEG_0_1 : 8; /*!< this field configures threshold of histogram bin 0 and bin 1 */ - } bit; - } HIST_SEG0; - - union { - __IOM uint32_t reg; /*!< histogram bin control register 1 */ - - struct { - __IOM uint32_t HIST_SEG_7_8 : 8; /*!< this field configures threshold of histogram bin 7 and bin 8 */ - __IOM uint32_t HIST_SEG_6_7 : 8; /*!< this field configures threshold of histogram bin 6 and bin 7 */ - __IOM uint32_t HIST_SEG_5_6 : 8; /*!< this field configures threshold of histogram bin 5 and bin 6 */ - __IOM uint32_t HIST_SEG_4_5 : 8; /*!< this field configures threshold of histogram bin 4 and bin 5 */ - } bit; - } HIST_SEG1; - - union { - __IOM uint32_t reg; /*!< histogram bin control register 2 */ - - struct { - __IOM uint32_t HIST_SEG_11_12 : 8; /*!< this field configures threshold of histogram bin 11 and bin - 12 */ - __IOM uint32_t HIST_SEG_10_11 : 8; /*!< this field configures threshold of histogram bin 10 and bin - 11 */ - __IOM uint32_t HIST_SEG_9_10 : 8; /*!< this field configures threshold of histogram bin 9 and bin 10 */ - __IOM uint32_t HIST_SEG_8_9 : 8; /*!< this field configures threshold of histogram bin 8 and bin 9 */ - } bit; - } HIST_SEG2; - - union { - __IOM uint32_t reg; /*!< histogram bin control register 3 */ - - struct { - __IOM uint32_t HIST_SEG_14_15 : 8; /*!< this field configures threshold of histogram bin 14 and bin - 15 */ - __IOM uint32_t HIST_SEG_13_14 : 8; /*!< this field configures threshold of histogram bin 13 and bin - 14 */ - __IOM uint32_t HIST_SEG_12_13 : 8; /*!< this field configures threshold of histogram bin 12 and bin - 13 */ - uint32_t : 8; - } bit; - } HIST_SEG3; - - union { - __IOM uint32_t reg; /*!< histogram sub-window weight register 0 */ - - struct { - __IOM uint32_t HIST_WEIGHT_03 : 8; /*!< this field configures weight of subwindow 03 */ - __IOM uint32_t HIST_WEIGHT_02 : 8; /*!< this field configures weight of subwindow 02 */ - __IOM uint32_t HIST_WEIGHT_01 : 8; /*!< this field configures weight of subwindow 01 */ - __IOM uint32_t HIST_WEIGHT_00 : 8; /*!< this field configures weight of subwindow 00 and sum of all - weight should be 256 */ - } bit; - } HIST_WEIGHT0; - - union { - __IOM uint32_t reg; /*!< histogram sub-window weight register 1 */ - - struct { - __IOM uint32_t HIST_WEIGHT_12 : 8; /*!< this field configures weight of subwindow 12 */ - __IOM uint32_t HIST_WEIGHT_11 : 8; /*!< this field configures weight of subwindow 11 */ - __IOM uint32_t HIST_WEIGHT_10 : 8; /*!< this field configures weight of subwindow 10 */ - __IOM uint32_t HIST_WEIGHT_04 : 8; /*!< this field configures weight of subwindow 04 */ - } bit; - } HIST_WEIGHT1; - - union { - __IOM uint32_t reg; /*!< histogram sub-window weight register 2 */ - - struct { - __IOM uint32_t HIST_WEIGHT_21 : 8; /*!< this field configures weight of subwindow 21 */ - __IOM uint32_t HIST_WEIGHT_20 : 8; /*!< this field configures weight of subwindow 20 */ - __IOM uint32_t HIST_WEIGHT_14 : 8; /*!< this field configures weight of subwindow 04 */ - __IOM uint32_t HIST_WEIGHT_13 : 8; /*!< this field configures weight of subwindow 13 */ - } bit; - } HIST_WEIGHT2; - - union { - __IOM uint32_t reg; /*!< histogram sub-window weight register 3 */ - - struct { - __IOM uint32_t HIST_WEIGHT_30 : 8; /*!< this field configures weight of subwindow 30 */ - __IOM uint32_t HIST_WEIGHT_24 : 8; /*!< this field configures weight of subwindow 24 */ - __IOM uint32_t HIST_WEIGHT_23 : 8; /*!< this field configures weight of subwindow 23 */ - __IOM uint32_t HIST_WEIGHT_22 : 8; /*!< this field configures weight of subwindow 22 */ - } bit; - } HIST_WEIGHT3; - - union { - __IOM uint32_t reg; /*!< histogram sub-window weight register 4 */ - - struct { - __IOM uint32_t HIST_WEIGHT_34 : 8; /*!< this field configures weight of subwindow 34 */ - __IOM uint32_t HIST_WEIGHT_33 : 8; /*!< this field configures weight of subwindow 33 */ - __IOM uint32_t HIST_WEIGHT_32 : 8; /*!< this field configures weight of subwindow 32 */ - __IOM uint32_t HIST_WEIGHT_31 : 8; /*!< this field configures weight of subwindow 31 */ - } bit; - } HIST_WEIGHT4; - - union { - __IOM uint32_t reg; /*!< histogram sub-window weight register 5 */ - - struct { - __IOM uint32_t HIST_WEIGHT_43 : 8; /*!< this field configures weight of subwindow 43 */ - __IOM uint32_t HIST_WEIGHT_42 : 8; /*!< this field configures weight of subwindow 42 */ - __IOM uint32_t HIST_WEIGHT_41 : 8; /*!< this field configures weight of subwindow 41 */ - __IOM uint32_t HIST_WEIGHT_40 : 8; /*!< this field configures weight of subwindow 40 */ - } bit; - } HIST_WEIGHT5; - - union { - __IOM uint32_t reg; /*!< histogram sub-window weight register 6 */ - - struct { - __IOM uint32_t HIST_WEIGHT_44 : 8; /*!< this field configures weight of subwindow 44 */ - uint32_t : 24; - } bit; - } HIST_WEIGHT6; - - union { - __IOM uint32_t reg; /*!< result of histogram bin 0 */ - - struct { - __IM uint32_t HIST_BIN_0 : 17; /*!< this field represents result of histogram bin 0 */ - uint32_t : 15; - } bit; - } HIST_BIN0; - - union { - __IOM uint32_t reg; /*!< result of histogram bin 1 */ - - struct { - __IM uint32_t HIST_BIN_1 : 17; /*!< this field represents result of histogram bin 1 */ - uint32_t : 15; - } bit; - } HIST_BIN1; - - union { - __IOM uint32_t reg; /*!< result of histogram bin 2 */ - - struct { - __IM uint32_t HIST_BIN_2 : 17; /*!< this field represents result of histogram bin 2 */ - uint32_t : 15; - } bit; - } HIST_BIN2; - - union { - __IOM uint32_t reg; /*!< result of histogram bin 3 */ - - struct { - __IM uint32_t HIST_BIN_3 : 17; /*!< this field represents result of histogram bin 3 */ - uint32_t : 15; - } bit; - } HIST_BIN3; - - union { - __IOM uint32_t reg; /*!< result of histogram bin 4 */ - - struct { - __IM uint32_t HIST_BIN_4 : 17; /*!< this field represents result of histogram bin 4 */ - uint32_t : 15; - } bit; - } HIST_BIN4; - - union { - __IOM uint32_t reg; /*!< result of histogram bin 5 */ - - struct { - __IM uint32_t HIST_BIN_5 : 17; /*!< this field represents result of histogram bin 5 */ - uint32_t : 15; - } bit; - } HIST_BIN5; - - union { - __IOM uint32_t reg; /*!< result of histogram bin 6 */ - - struct { - __IM uint32_t HIST_BIN_6 : 17; /*!< this field represents result of histogram bin 6 */ - uint32_t : 15; - } bit; - } HIST_BIN6; - - union { - __IOM uint32_t reg; /*!< result of histogram bin 7 */ - - struct { - __IM uint32_t HIST_BIN_7 : 17; /*!< this field represents result of histogram bin 7 */ - uint32_t : 15; - } bit; - } HIST_BIN7; - - union { - __IOM uint32_t reg; /*!< result of histogram bin 8 */ - - struct { - __IM uint32_t HIST_BIN_8 : 17; /*!< this field represents result of histogram bin 8 */ - uint32_t : 15; - } bit; - } HIST_BIN8; - - union { - __IOM uint32_t reg; /*!< result of histogram bin 9 */ - - struct { - __IM uint32_t HIST_BIN_9 : 17; /*!< this field represents result of histogram bin 9 */ - uint32_t : 15; - } bit; - } HIST_BIN9; - - union { - __IOM uint32_t reg; /*!< result of histogram bin 10 */ - - struct { - __IM uint32_t HIST_BIN_10 : 17; /*!< this field represents result of histogram bin 10 */ - uint32_t : 15; - } bit; - } HIST_BIN10; - - union { - __IOM uint32_t reg; /*!< result of histogram bin 11 */ - - struct { - __IM uint32_t HIST_BIN_11 : 17; /*!< this field represents result of histogram bin 11 */ - uint32_t : 15; - } bit; - } HIST_BIN11; - - union { - __IOM uint32_t reg; /*!< result of histogram bin 12 */ - - struct { - __IM uint32_t HIST_BIN_12 : 17; /*!< this field represents result of histogram bin 12 */ - uint32_t : 15; - } bit; - } HIST_BIN12; - - union { - __IOM uint32_t reg; /*!< result of histogram bin 13 */ - - struct { - __IM uint32_t HIST_BIN_13 : 17; /*!< this field represents result of histogram bin 13 */ - uint32_t : 15; - } bit; - } HIST_BIN13; - - union { - __IOM uint32_t reg; /*!< result of histogram bin 14 */ - - struct { - __IM uint32_t HIST_BIN_14 : 17; /*!< this field represents result of histogram bin 14 */ - uint32_t : 15; - } bit; - } HIST_BIN14; - - union { - __IOM uint32_t reg; /*!< result of histogram bin 15 */ - - struct { - __IM uint32_t HIST_BIN_15 : 17; /*!< this field represents result of histogram bin 15 */ - uint32_t : 15; - } bit; - } HIST_BIN15; - - union { - __IOM uint32_t reg; /*!< mem aux control register 0 */ - - struct { - __IOM uint32_t HEADER_MEM_AUX_CTRL : 14; /*!< this field configures the mem_aux of isp input buffer memory */ - uint32_t : 2; - __IOM uint32_t DPC_LUT_MEM_AUX_CTRL : 14; /*!< this field represents this field configures the mem_aux of dpc - lut memory */ - uint32_t : 2; - } bit; - } MEM_AUX_CTRL_0; - - union { - __IOM uint32_t reg; /*!< mem aux control register 1 */ - - struct { - __IOM uint32_t LSC_LUT_R_GR_MEM_AUX_CTRL : 14;/*!< this field configures the mem_aux of lsc r gr lut memory */ - uint32_t : 2; - __IOM uint32_t LSC_LUT_GB_B_MEM_AUX_CTRL : 14;/*!< this field configures the mem_aux of lsc gb b lut memory */ - uint32_t : 2; - } bit; - } MEM_AUX_CTRL_1; - - union { - __IOM uint32_t reg; /*!< mem aux control register 2 */ - - struct { - __IOM uint32_t BF_MATRIX_MEM_AUX_CTRL : 14;/*!< this field configures the mem_aux of bf line buffer memory */ - uint32_t : 2; - __IOM uint32_t DPC_MATRIX_MEM_AUX_CTRL : 14;/*!< this field configures the mem_aux of dpc line buffer memory */ - uint32_t : 2; - } bit; - } MEM_AUX_CTRL_2; - - union { - __IOM uint32_t reg; /*!< mem aux control register 3 */ - - struct { - __IOM uint32_t SHARP_MATRIX_Y_MEM_AUX_CTRL : 14;/*!< this field configures the mem_aux of sharp y line buffer memory */ - uint32_t : 2; - __IOM uint32_t DEMOSAIC_MATRIX_MEM_AUX_CTRL : 14;/*!< this field configures the mem_aux of demosaic line buffer memory */ - uint32_t : 2; - } bit; - } MEM_AUX_CTRL_3; - - union { - __IOM uint32_t reg; /*!< mem aux control register 4 */ - - struct { - __IOM uint32_t SHARP_MATRIX_UV_MEM_AUX_CTRL : 14;/*!< this field configures the mem_aux of sharp uv line buffer memory */ - uint32_t : 18; - } bit; - } MEM_AUX_CTRL_4; - - union { - __IOM uint32_t reg; /*!< yuv format control register */ - - struct { - __IOM uint32_t YUV_MODE : 1; /*!< this bit configures the yuv mode. 0: ITU-R BT.601, 1: ITU-R - BT.709 */ - __IOM uint32_t YUV_RANGE : 1; /*!< this bit configures the yuv range. 0: full range, 1: limit range */ - uint32_t : 30; - } bit; - } YUV_FORMAT; - - union { - __IOM uint32_t reg; /*!< rdn eco cs register */ - - struct { - __IOM uint32_t RDN_ECO_EN : 1; /*!< rdn_eco_en */ - __IM uint32_t RDN_ECO_RESULT : 1; /*!< rdn_eco_result */ - uint32_t : 30; - } bit; - } RDN_ECO_CS; - - union { - __IOM uint32_t reg; /*!< rdn eco all low register */ - - struct { - __IOM uint32_t RDN_ECO_LOW : 32; /*!< rdn_eco_low */ - } bit; - } RDN_ECO_LOW; - - union { - __IOM uint32_t reg; /*!< rdn eco all high register */ - - struct { - __IOM uint32_t RDN_ECO_HIGH : 32; /*!< rdn_eco_high */ - } bit; - } RDN_ECO_HIGH; -} ISP_Type; /*!< Size = 580 (0x244) */ - - - -/* =========================================================================================================================== */ -/* ================ JPEG ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief JPEG Codec (JPEG) - */ - -typedef struct { /*!< JPEG Structure */ - - union { - __IOM uint32_t reg; /*!< Control and configuration registers */ - - struct { - __OM uint32_t FSM_RST : 1; /*!< fsm reset */ - __OM uint32_t JPEG_START : 1; /*!< start to compress a new pic(in dma reg mode) */ - __IOM uint32_t QNR_PRESITION : 1; /*!< 0:8bit qnr,1:12bit qnr(TBD) */ - __IOM uint32_t FF_CHECK_EN : 1; /*!< enable whether to add "00" after "ff" */ - __IOM uint32_t SAMPLE_SEL : 2; /*!< 0:yuv444,1:yuv422, 2:yuv420 */ - __IM uint32_t DMA_LINKLIST_MODE : 1; /*!< 1:use linklist to configure dma */ - __IOM uint32_t DEBUG_DIRECT_OUT_EN : 1; /*!< 0:normal mode,1:debug mode for direct output from input */ - __IOM uint32_t GRAY_SEL : 1; /*!< 0:use non-fifo way to access qnr ram,1:use fifo way to access - qnr ram */ - __IOM uint32_t LQNR_TBL_SEL : 2; /*!< choose luminance quntization table id(TBD) */ - __IOM uint32_t CQNR_TBL_SEL : 2; /*!< choose chrominance quntization table id (TBD) */ - __IOM uint32_t COLOR_SPACE : 2; /*!< configure picture's color space:0-rb888,1-yuv422,2-rgb565, 3-gray */ - __IOM uint32_t DHT_FIFO_EN : 1; /*!< 0:use non-fifo way to write dht len_total/codemin/value table,1:use - fifo way to write dht len_total/codemin/value table. Reading - dht len_total/codemin/value table only has nonfifo way */ - __IOM uint32_t MEM_CLK_FORCE_ON : 1; /*!< force memory's clock enabled */ - __IOM uint32_t JFIF_VER : 6; /*!< decode pause period to trigger decode_timeout int, the timeout - periods =2 power (reg_decode_timeout_thres) -1 */ - __IOM uint32_t DECODE_TIMEOUT_TASK_SEL : 1;/*!< 0: software use reset to abort decode process ,1: decoder abort - decode process by itself */ - __IOM uint32_t SOFT_RST : 1; /*!< when set to 1, soft reset JPEG module except jpeg_reg module */ - __IOM uint32_t FIFO_RST : 1; /*!< fifo reset */ - __IOM uint32_t PIXEL_REV : 1; /*!< reverse the source color pixel */ - __IOM uint32_t TAILER_EN : 1; /*!< set this bit to add EOI of "0xffd9" at the end of bitstream */ - __IOM uint32_t PAUSE_EN : 1; /*!< set this bit to pause jpeg encoding */ - __IOM uint32_t MEM_FORCE_PD : 1; /*!< 0: no operation,1:force jpeg memory to power down */ - __IOM uint32_t MEM_FORCE_PU : 1; /*!< 0: no operation,1:force jpeg memory to power up */ - __IOM uint32_t MODE : 1; /*!< 0:encoder mode, 1: decoder mode */ - } bit; - } CONFIG; - - union { - __IOM uint32_t reg; /*!< Control and configuration registers */ - - struct { - __IOM uint32_t T0_DQT_INFO : 8; /*!< Configure dqt table0's quantization coefficient precision in - bit[7:4], configure dqt table0's table id in bit[3:0] */ - __IOM uint32_t T1_DQT_INFO : 8; /*!< Configure dqt table1's quantization coefficient precision in - bit[7:4], configure dqt table1's table id in bit[3:0] */ - __IOM uint32_t T2_DQT_INFO : 8; /*!< Configure dqt table2's quantization coefficient precision in - bit[7:4], configure dqt table2's table id in bit[3:0] */ - __IOM uint32_t T3_DQT_INFO : 8; /*!< Configure dqt table3's quantization coefficient precision in - bit[7:4], configure dqt table3's table id in bit[3:0] */ - } bit; - } DQT_INFO; - - union { - __IOM uint32_t reg; /*!< Control and configuration registers */ - - struct { - __IOM uint32_t VA : 16; /*!< configure picture's height. when encode, the max configurable - bits is 14, when decode, the max configurable bits is 16 */ - __IOM uint32_t HA : 16; /*!< configure picture's width. when encode, the max configurable - bits is 14, when decode, the max configurable bits is 16 */ - } bit; - } PIC_SIZE; - __IM uint32_t RESERVED; - - union { - __IOM uint32_t reg; /*!< Control and configuration registers */ - - struct { - __IM uint32_t T0_QNR_VAL : 32; /*!< write this reg to configure 64 quantization coefficient in t0 - table */ - } bit; - } T0QNR; - - union { - __IOM uint32_t reg; /*!< Control and configuration registers */ - - struct { - __IM uint32_t CHROMINANCE_QNR_VAL : 32; /*!< write this reg to configure 64 quantization coefficient in t1 - table */ - } bit; - } T1QNR; - - union { - __IOM uint32_t reg; /*!< Control and configuration registers */ - - struct { - __IM uint32_t T2_QNR_VAL : 32; /*!< write this reg to configure 64 quantization coefficient in t2 - table */ - } bit; - } T2QNR; - - union { - __IOM uint32_t reg; /*!< Control and configuration registers */ - - struct { - __IM uint32_t T3_QNR_VAL : 32; /*!< write this reg to configure 64 quantization coefficient in t3 - table */ - } bit; - } T3QNR; - - union { - __IOM uint32_t reg; /*!< Control and configuration registers */ - - struct { - __IOM uint32_t RESTART_INTERVAL : 16; /*!< configure restart interval in DRI marker when decode */ - __IOM uint32_t COMPONENT_NUM : 8; /*!< configure number of components in frame when decode */ - __IM uint32_t SW_DHT_EN : 1; /*!< software decode dht table enable */ - __IOM uint32_t SOS_CHECK_BYTE_NUM : 2; /*!< Configure the byte number to check next sos marker in the multi-scan - picture after one scan is decoded down. The real check - number is reg_sos_check_byte_num+1 */ - __IOM uint32_t RST_CHECK_BYTE_NUM : 2; /*!< Configure the byte number to check next rst marker after one - rst interval is decoded down. The real check number is - reg_rst_check_byte_num+1 */ - __IOM uint32_t MULTI_SCAN_ERR_CHECK : 1; /*!< reserved for decoder */ - __IOM uint32_t DEZIGZAG_READY_CTL : 1; /*!< reserved for decoder */ - uint32_t : 1; - } bit; - } DECODE_CONF; - - union { - __IOM uint32_t reg; /*!< Control and configuration registers */ - - struct { - __IOM uint32_t DQT_TBL_SEL : 8; /*!< choose c0 quntization table id (TBD) */ - __IOM uint32_t Y_FACTOR : 4; /*!< vertical sampling factor of c0 */ - __IOM uint32_t X_FACTOR : 4; /*!< horizontal sampling factor of c0 */ - __IOM uint32_t ID : 8; /*!< the identifier of c0 */ - uint32_t : 8; - } bit; - } C0; - - union { - __IOM uint32_t reg; /*!< Control and configuration registers */ - - struct { - __IOM uint32_t DQT_TBL_SEL : 8; /*!< choose c1 quntization table id (TBD) */ - __IOM uint32_t Y_FACTOR : 4; /*!< vertical sampling factor of c1 */ - __IOM uint32_t X_FACTOR : 4; /*!< horizontal sampling factor of c1 */ - __IOM uint32_t ID : 8; /*!< the identifier of c1 */ - uint32_t : 8; - } bit; - } C1; - - union { - __IOM uint32_t reg; /*!< Control and configuration registers */ - - struct { - __IOM uint32_t DQT_TBL_SEL : 8; /*!< choose c2 quntization table id (TBD) */ - __IOM uint32_t Y_FACTOR : 4; /*!< vertical sampling factor of c2 */ - __IOM uint32_t X_FACTOR : 4; /*!< horizontal sampling factor of c2 */ - __IOM uint32_t ID : 8; /*!< the identifier of c2 */ - uint32_t : 8; - } bit; - } C2; - - union { - __IOM uint32_t reg; /*!< Control and configuration registers */ - - struct { - __IOM uint32_t DQT_TBL_SEL : 8; /*!< choose c3 quntization table id (TBD) */ - __IOM uint32_t Y_FACTOR : 4; /*!< vertical sampling factor of c3 */ - __IOM uint32_t X_FACTOR : 4; /*!< horizontal sampling factor of c3 */ - __IOM uint32_t ID : 8; /*!< the identifier of c3 */ - uint32_t : 8; - } bit; - } C3; - - union { - __IOM uint32_t reg; /*!< Control and configuration registers */ - - struct { - __IOM uint32_t DC0_DHT_ID : 4; /*!< configure dht dc table 0 id */ - __IOM uint32_t DC1_DHT_ID : 4; /*!< configure dht dc table 1 id */ - __IOM uint32_t AC0_DHT_ID : 4; /*!< configure dht ac table 0 id */ - __IOM uint32_t AC1_DHT_ID : 4; /*!< configure dht ac table 1 id */ - uint32_t : 16; - } bit; - } DHT_INFO; - - union { - __IOM uint32_t reg; /*!< Interrupt raw registers */ - - struct { - __IOM uint32_t DONE_INT_RAW : 1; /*!< This raw interrupt bit turns to high level when JPEG finishes - encoding a picture.. */ - __IOM uint32_t RLE_PARALLEL_ERR_INT_RAW : 1;/*!< The raw interrupt bit to sign that rle parallel error when decoding. */ - __IOM uint32_t CID_ERR_INT_RAW : 1; /*!< The raw interrupt bit to sign that scan id check with component - fails when decoding. */ - __IOM uint32_t C_DHT_DC_ID_ERR_INT_RAW : 1;/*!< The raw interrupt bit to sign that scan component's dc dht id - check with dc dht table's id fails when decoding. */ - __IOM uint32_t C_DHT_AC_ID_ERR_INT_RAW : 1;/*!< The raw interrupt bit to sign that scan component's ac dht id - check with ac dht table's id fails when decoding. */ - __IOM uint32_t C_DQT_ID_ERR_INT_RAW : 1; /*!< The raw interrupt bit to sign that scan component's dqt id check - with dqt table's id fails when decoding. */ - __IOM uint32_t RST_UXP_ERR_INT_RAW : 1; /*!< The raw interrupt bit to sign that RST header marker is detected - but restart interval is 0 when decoding. */ - __IOM uint32_t RST_CHECK_NONE_ERR_INT_RAW : 1;/*!< The raw interrupt bit to sign that RST header marker is not - detected but restart interval is not 0 when decoding. */ - __IOM uint32_t RST_CHECK_POS_ERR_INT_RAW : 1;/*!< The raw interrupt bit to sign that RST header marker position - mismatches with restart interval when decoding. */ - __IOM uint32_t OUT_EOF_INT_RAW : 1; /*!< The raw interrupt bit turns to high level when the last pixel - of one square has been transmitted for Tx channel. */ - __IOM uint32_t SR_COLOR_MODE_ERR_INT_RAW : 1;/*!< The raw interrupt bit to sign that the selected source color - mode is not supported. */ - __IOM uint32_t DCT_DONE_INT_RAW : 1; /*!< The raw interrupt bit to sign that one dct calculation is finished. */ - __IOM uint32_t BS_LAST_BLOCK_EOF_INT_RAW : 1;/*!< The raw interrupt bit to sign that the coding process for last - block is finished. */ - __IOM uint32_t SCAN_CHECK_NONE_ERR_INT_RAW : 1;/*!< The raw interrupt bit to sign that SOS header marker is not - detected but there are still components left to be decoded. */ - __IOM uint32_t SCAN_CHECK_POS_ERR_INT_RAW : 1;/*!< The raw interrupt bit to sign that SOS header marker position - wrong when decoding. */ - __IOM uint32_t UXP_DET_INT_RAW : 1; /*!< The raw interrupt bit to sign that unsupported header marker - is detected when decoding. */ - __IOM uint32_t EN_FRAME_EOF_ERR_INT_RAW : 1;/*!< The raw interrupt bit to sign that received pixel blocks are - smaller than expected when encoding. */ - __IOM uint32_t EN_FRAME_EOF_LACK_INT_RAW : 1;/*!< The raw interrupt bit to sign that the frame eof sign bit from - dma input is missing when encoding. But the number of pixel - blocks is enough. */ - __IOM uint32_t DE_FRAME_EOF_ERR_INT_RAW : 1;/*!< The raw interrupt bit to sign that decoded blocks are smaller - than expected when decoding. */ - __IOM uint32_t DE_FRAME_EOF_LACK_INT_RAW : 1;/*!< The raw interrupt bit to sign that the either frame eof from - dma input or eoi marker is missing when encoding. But the - number of decoded blocks is enough. */ - __IOM uint32_t SOS_UNMATCH_ERR_INT_RAW : 1;/*!< The raw interrupt bit to sign that the component number of a - scan is 0 or does not match the sos marker's length when - decoding. */ - __IOM uint32_t MARKER_ERR_FST_SCAN_INT_RAW : 1;/*!< The raw interrupt bit to sign that the first scan has header - marker error when decoding. */ - __IOM uint32_t MARKER_ERR_OTHER_SCAN_INT_RAW : 1;/*!< The raw interrupt bit to sign that the following scans but not - the first scan have header marker error when decoding. */ - __IOM uint32_t UNDET_INT_RAW : 1; /*!< The raw interrupt bit to sign that JPEG format is not detected - at the eof data of a packet when decoding. */ - __IOM uint32_t DECODE_TIMEOUT_INT_RAW : 1;/*!< The raw interrupt bit to sign that decode pause time is longer - than the setting decode timeout time when decoding. */ - uint32_t : 7; - } bit; - } INT_RAW; - - union { - __IOM uint32_t reg; /*!< Interrupt enable registers */ - - struct { - __IOM uint32_t DONE_INT_ENA : 1; /*!< This enable interrupt bit turns to high level when JPEG finishes - encoding a picture.. */ - __IOM uint32_t RLE_PARALLEL_ERR_INT_ENA : 1;/*!< The enable interrupt bit to sign that rle parallel error when - decoding. */ - __IOM uint32_t CID_ERR_INT_ENA : 1; /*!< The enable interrupt bit to sign that scan id check with component - fails when decoding. */ - __IOM uint32_t C_DHT_DC_ID_ERR_INT_ENA : 1;/*!< The enable interrupt bit to sign that scan component's dc dht - id check with dc dht table's id fails when decoding. */ - __IOM uint32_t C_DHT_AC_ID_ERR_INT_ENA : 1;/*!< The enable interrupt bit to sign that scan component's ac dht - id check with ac dht table's id fails when decoding. */ - __IOM uint32_t C_DQT_ID_ERR_INT_ENA : 1; /*!< The enable interrupt bit to sign that scan component's dqt id - check with dqt table's id fails when decoding. */ - __IOM uint32_t RST_UXP_ERR_INT_ENA : 1; /*!< The enable interrupt bit to sign that RST header marker is detected - but restart interval is 0 when decoding. */ - __IOM uint32_t RST_CHECK_NONE_ERR_INT_ENA : 1;/*!< The enable interrupt bit to sign that RST header marker is not - detected but restart interval is not 0 when decoding. */ - __IOM uint32_t RST_CHECK_POS_ERR_INT_ENA : 1;/*!< The enable interrupt bit to sign that RST header marker position - mismatches with restart interval when decoding. */ - __IOM uint32_t OUT_EOF_INT_ENA : 1; /*!< The enable interrupt bit turns to high level when the last pixel - of one square has been transmitted for Tx channel. */ - __IOM uint32_t SR_COLOR_MODE_ERR_INT_ENA : 1;/*!< The enable interrupt bit to sign that the selected source color - mode is not supported. */ - __IOM uint32_t DCT_DONE_INT_ENA : 1; /*!< The enable interrupt bit to sign that one dct calculation is - finished. */ - __IOM uint32_t BS_LAST_BLOCK_EOF_INT_ENA : 1;/*!< The enable interrupt bit to sign that the coding process for - last block is finished. */ - __IOM uint32_t SCAN_CHECK_NONE_ERR_INT_ENA : 1;/*!< The enable interrupt bit to sign that SOS header marker is not - detected but there are still components left to be decoded. */ - __IOM uint32_t SCAN_CHECK_POS_ERR_INT_ENA : 1;/*!< The enable interrupt bit to sign that SOS header marker position - wrong when decoding. */ - __IOM uint32_t UXP_DET_INT_ENA : 1; /*!< The enable interrupt bit to sign that unsupported header marker - is detected when decoding. */ - __IOM uint32_t EN_FRAME_EOF_ERR_INT_ENA : 1;/*!< The enable interrupt bit to sign that received pixel blocks - are smaller than expected when encoding. */ - __IOM uint32_t EN_FRAME_EOF_LACK_INT_ENA : 1;/*!< The enable interrupt bit to sign that the frame eof sign bit - from dma input is missing when encoding. But the number - of pixel blocks is enough. */ - __IOM uint32_t DE_FRAME_EOF_ERR_INT_ENA : 1;/*!< The enable interrupt bit to sign that decoded blocks are smaller - than expected when decoding. */ - __IOM uint32_t DE_FRAME_EOF_LACK_INT_ENA : 1;/*!< The enable interrupt bit to sign that the either frame eof from - dma input or eoi marker is missing when encoding. But the - number of decoded blocks is enough. */ - __IOM uint32_t SOS_UNMATCH_ERR_INT_ENA : 1;/*!< The enable interrupt bit to sign that the component number of - a scan is 0 or does not match the sos marker's length when - decoding. */ - __IOM uint32_t MARKER_ERR_FST_SCAN_INT_ENA : 1;/*!< The enable interrupt bit to sign that the first scan has header - marker error when decoding. */ - __IOM uint32_t MARKER_ERR_OTHER_SCAN_INT_ENA : 1;/*!< The enable interrupt bit to sign that the following scans but - not the first scan have header marker error when decoding. */ - __IOM uint32_t UNDET_INT_ENA : 1; /*!< The enable interrupt bit to sign that JPEG format is not detected - at the eof data of a packet when decoding. */ - __IOM uint32_t DECODE_TIMEOUT_INT_ENA : 1;/*!< The enable interrupt bit to sign that decode pause time is longer - than the setting decode timeout time when decoding. */ - uint32_t : 7; - } bit; - } INT_ENA; - - union { - __IOM uint32_t reg; /*!< Interrupt status registers */ - - struct { - __IM uint32_t DONE_INT_ST : 1; /*!< This status interrupt bit turns to high level when JPEG finishes - encoding a picture.. */ - __IM uint32_t RLE_PARALLEL_ERR_INT_ST : 1;/*!< The status interrupt bit to sign that rle parallel error when - decoding. */ - __IM uint32_t CID_ERR_INT_ST : 1; /*!< The status interrupt bit to sign that scan id check with component - fails when decoding. */ - __IM uint32_t C_DHT_DC_ID_ERR_INT_ST : 1;/*!< The status interrupt bit to sign that scan component's dc dht - id check with dc dht table's id fails when decoding. */ - __IM uint32_t C_DHT_AC_ID_ERR_INT_ST : 1;/*!< The status interrupt bit to sign that scan component's ac dht - id check with ac dht table's id fails when decoding. */ - __IM uint32_t C_DQT_ID_ERR_INT_ST : 1; /*!< The status interrupt bit to sign that scan component's dqt id - check with dqt table's id fails when decoding. */ - __IM uint32_t RST_UXP_ERR_INT_ST : 1; /*!< The status interrupt bit to sign that RST header marker is detected - but restart interval is 0 when decoding. */ - __IM uint32_t RST_CHECK_NONE_ERR_INT_ST : 1;/*!< The status interrupt bit to sign that RST header marker is not - detected but restart interval is not 0 when decoding. */ - __IM uint32_t RST_CHECK_POS_ERR_INT_ST : 1;/*!< The status interrupt bit to sign that RST header marker position - mismatches with restart interval when decoding. */ - __IM uint32_t OUT_EOF_INT_ST : 1; /*!< The status interrupt bit turns to high level when the last pixel - of one square has been transmitted for Tx channel. */ - __IM uint32_t SR_COLOR_MODE_ERR_INT_ST : 1;/*!< The status interrupt bit to sign that the selected source color - mode is not supported. */ - __IM uint32_t DCT_DONE_INT_ST : 1; /*!< The status interrupt bit to sign that one dct calculation is - finished. */ - __IM uint32_t BS_LAST_BLOCK_EOF_INT_ST : 1;/*!< The status interrupt bit to sign that the coding process for - last block is finished. */ - __IM uint32_t SCAN_CHECK_NONE_ERR_INT_ST : 1;/*!< The status interrupt bit to sign that SOS header marker is not - detected but there are still components left to be decoded. */ - __IM uint32_t SCAN_CHECK_POS_ERR_INT_ST : 1;/*!< The status interrupt bit to sign that SOS header marker position - wrong when decoding. */ - __IM uint32_t UXP_DET_INT_ST : 1; /*!< The status interrupt bit to sign that unsupported header marker - is detected when decoding. */ - __IM uint32_t EN_FRAME_EOF_ERR_INT_ST : 1;/*!< The status interrupt bit to sign that received pixel blocks - are smaller than expected when encoding. */ - __IM uint32_t EN_FRAME_EOF_LACK_INT_ST : 1;/*!< The status interrupt bit to sign that the frame eof sign bit - from dma input is missing when encoding. But the number - of pixel blocks is enough. */ - __IM uint32_t DE_FRAME_EOF_ERR_INT_ST : 1;/*!< The status interrupt bit to sign that decoded blocks are smaller - than expected when decoding. */ - __IM uint32_t DE_FRAME_EOF_LACK_INT_ST : 1;/*!< The status interrupt bit to sign that the either frame eof from - dma input or eoi marker is missing when encoding. But the - number of decoded blocks is enough. */ - __IM uint32_t SOS_UNMATCH_ERR_INT_ST : 1;/*!< The status interrupt bit to sign that the component number of - a scan is 0 or does not match the sos marker's length when - decoding. */ - __IM uint32_t MARKER_ERR_FST_SCAN_INT_ST : 1;/*!< The status interrupt bit to sign that the first scan has header - marker error when decoding. */ - __IM uint32_t MARKER_ERR_OTHER_SCAN_INT_ST : 1;/*!< The status interrupt bit to sign that the following scans but - not the first scan have header marker error when decoding. */ - __IM uint32_t UNDET_INT_ST : 1; /*!< The status interrupt bit to sign that JPEG format is not detected - at the eof data of a packet when decoding. */ - __IM uint32_t DECODE_TIMEOUT_INT_ST : 1; /*!< The status interrupt bit to sign that decode pause time is longer - than the setting decode timeout time when decoding. */ - uint32_t : 7; - } bit; - } INT_ST; - - union { - __IOM uint32_t reg; /*!< Interrupt clear registers */ - - struct { - __OM uint32_t DONE_INT_CLR : 1; /*!< This clear interrupt bit turns to high level when JPEG finishes - encoding a picture.. */ - __OM uint32_t RLE_PARALLEL_ERR_INT_CLR : 1;/*!< The clear interrupt bit to sign that rle parallel error when - decoding. */ - __OM uint32_t CID_ERR_INT_CLR : 1; /*!< The clear interrupt bit to sign that scan id check with component - fails when decoding. */ - __OM uint32_t C_DHT_DC_ID_ERR_INT_CLR : 1;/*!< The clear interrupt bit to sign that scan component's dc dht - id check with dc dht table's id fails when decoding. */ - __OM uint32_t C_DHT_AC_ID_ERR_INT_CLR : 1;/*!< The clear interrupt bit to sign that scan component's ac dht - id check with ac dht table's id fails when decoding. */ - __OM uint32_t C_DQT_ID_ERR_INT_CLR : 1; /*!< The clear interrupt bit to sign that scan component's dqt id - check with dqt table's id fails when decoding. */ - __OM uint32_t RST_UXP_ERR_INT_CLR : 1; /*!< The clear interrupt bit to sign that RST header marker is detected - but restart interval is 0 when decoding. */ - __OM uint32_t RST_CHECK_NONE_ERR_INT_CLR : 1;/*!< The clear interrupt bit to sign that RST header marker is not - detected but restart interval is not 0 when decoding. */ - __OM uint32_t RST_CHECK_POS_ERR_INT_CLR : 1;/*!< The clear interrupt bit to sign that RST header marker position - mismatches with restart interval when decoding. */ - __OM uint32_t OUT_EOF_INT_CLR : 1; /*!< The clear interrupt bit turns to high level when the last pixel - of one square has been transmitted for Tx channel. */ - __OM uint32_t SR_COLOR_MODE_ERR_INT_CLR : 1;/*!< The clear interrupt bit to sign that the selected source color - mode is not supported. */ - __OM uint32_t DCT_DONE_INT_CLR : 1; /*!< The clear interrupt bit to sign that one dct calculation is - finished. */ - __OM uint32_t BS_LAST_BLOCK_EOF_INT_CLR : 1;/*!< The clear interrupt bit to sign that the coding process for - last block is finished. */ - __OM uint32_t SCAN_CHECK_NONE_ERR_INT_CLR : 1;/*!< The clear interrupt bit to sign that SOS header marker is not - detected but there are still components left to be decoded. */ - __OM uint32_t SCAN_CHECK_POS_ERR_INT_CLR : 1;/*!< The clear interrupt bit to sign that SOS header marker position - wrong when decoding. */ - __OM uint32_t UXP_DET_INT_CLR : 1; /*!< The clear interrupt bit to sign that unsupported header marker - is detected when decoding. */ - __OM uint32_t EN_FRAME_EOF_ERR_INT_CLR : 1;/*!< The clear interrupt bit to sign that received pixel blocks are - smaller than expected when encoding. */ - __OM uint32_t EN_FRAME_EOF_LACK_INT_CLR : 1;/*!< The clear interrupt bit to sign that the frame eof sign bit - from dma input is missing when encoding. But the number - of pixel blocks is enough. */ - __OM uint32_t DE_FRAME_EOF_ERR_INT_CLR : 1;/*!< The clear interrupt bit to sign that decoded blocks are smaller - than expected when decoding. */ - __OM uint32_t DE_FRAME_EOF_LACK_INT_CLR : 1;/*!< The clear interrupt bit to sign that the either frame eof from - dma input or eoi marker is missing when encoding. But the - number of decoded blocks is enough. */ - __OM uint32_t SOS_UNMATCH_ERR_INT_CLR : 1;/*!< The clear interrupt bit to sign that the component number of - a scan is 0 or does not match the sos marker's length when - decoding. */ - __OM uint32_t MARKER_ERR_FST_SCAN_INT_CLR : 1;/*!< The clear interrupt bit to sign that the first scan has header - marker error when decoding. */ - __OM uint32_t MARKER_ERR_OTHER_SCAN_INT_CLR : 1;/*!< The clear interrupt bit to sign that the following scans but - not the first scan have header marker error when decoding. */ - __OM uint32_t UNDET_INT_CLR : 1; /*!< The clear interrupt bit to sign that JPEG format is not detected - at the eof data of a packet when decoding. */ - __OM uint32_t DECODE_TIMEOUT_INT_CLR : 1;/*!< The clear interrupt bit to sign that decode pause time is longer - than the setting decode timeout time when decoding. */ - uint32_t : 7; - } bit; - } INT_CLR; - - union { - __IOM uint32_t reg; /*!< Trace and Debug registers */ - - struct { - uint32_t : 11; - __IM uint32_t BITSTREAM_EOF_VLD_CNT : 6; /*!< the valid bit count for last bitstream */ - __IM uint32_t DCTOUT_ZZSCAN_ADDR : 6; /*!< the zig-zag read addr from dctout_ram */ - __IM uint32_t QNRVAL_ZZSCAN_ADDR : 6; /*!< the zig-zag read addr from qnrval_ram */ - __IM uint32_t REG_STATE_YUV : 3; /*!< the state of jpeg fsm */ - } bit; - } STATUS0; - - union { - __IOM uint32_t reg; /*!< Trace and Debug registers */ - - struct { - __IM uint32_t SOURCE_PIXEL : 24; /*!< source pixels fetched from dma */ - __IM uint32_t LAST_BLOCK : 1; /*!< indicate the encoding process for the last mcu of the picture */ - __IM uint32_t LAST_MCU : 1; /*!< indicate the encoding process for the last block of the picture */ - __IM uint32_t LAST_DC : 1; /*!< indicate the encoding process is at the header of the last block - of the picture */ - __IM uint32_t PACKFIFO_READY : 1; /*!< the jpeg pack_fifo ready signal, high active */ - uint32_t : 4; - } bit; - } STATUS2; - - union { - __IOM uint32_t reg; /*!< Trace and Debug registers */ - - struct { - __IM uint32_t YO : 9; /*!< component y transferred from rgb input */ - __IM uint32_t Y_READY : 1; /*!< component y valid signal, high active */ - __IM uint32_t CBO : 9; /*!< component cb transferred from rgb input */ - __IM uint32_t CB_READY : 1; /*!< component cb valid signal, high active */ - __IM uint32_t CRO : 9; /*!< component cr transferred from rgb input */ - __IM uint32_t CR_READY : 1; /*!< component cr valid signal, high active */ - uint32_t : 2; - } bit; - } STATUS3; - - union { - __IOM uint32_t reg; /*!< Trace and Debug registers */ - - struct { - __IM uint32_t HFM_BITSTREAM : 32; /*!< the hufman bitstream during encoding process */ - } bit; - } STATUS4; - - union { - __IOM uint32_t reg; /*!< Trace and Debug registers */ - - struct { - __IM uint32_t DHT_TOTLEN_DC0 : 32; /*!< write the numbers of 1~n codeword length sum from 1~16 of dc0 - table */ - } bit; - } DHT_TOTLEN_DC0; - - union { - __IOM uint32_t reg; /*!< Trace and Debug registers */ - - struct { - __IM uint32_t DHT_VAL_DC0 : 32; /*!< write codeword corresponding huffman values of dc0 table */ - } bit; - } DHT_VAl_DC0; - - union { - __IOM uint32_t reg; /*!< Trace and Debug registers */ - - struct { - __IM uint32_t DHT_TOTLEN_AC0 : 32; /*!< write the numbers of 1~n codeword length sum from 1~16 of ac0 - table */ - } bit; - } DHT_TOTLEN_AC0; - - union { - __IOM uint32_t reg; /*!< Trace and Debug registers */ - - struct { - __IM uint32_t DHT_VAL_AC0 : 32; /*!< write codeword corresponding huffman values of ac0 table */ - } bit; - } DHT_VAl_AC0; - - union { - __IOM uint32_t reg; /*!< Trace and Debug registers */ - - struct { - __IM uint32_t DHT_TOTLEN_DC1 : 32; /*!< write the numbers of 1~n codeword length sum from 1~16 of dc1 - table */ - } bit; - } DHT_TOTLEN_DC1; - - union { - __IOM uint32_t reg; /*!< Trace and Debug registers */ - - struct { - __IM uint32_t DHT_VAL_DC1 : 32; /*!< write codeword corresponding huffman values of dc1 table */ - } bit; - } DHT_VAl_DC1; - - union { - __IOM uint32_t reg; /*!< Trace and Debug registers */ - - struct { - __IM uint32_t DHT_TOTLEN_AC1 : 32; /*!< write the numbers of 1~n codeword length sum from 1~16 of ac1 - table */ - } bit; - } DHT_TOTLEN_AC1; - - union { - __IOM uint32_t reg; /*!< Trace and Debug registers */ - - struct { - __IM uint32_t DHT_VAL_AC1 : 32; /*!< write codeword corresponding huffman values of ac1 table */ - } bit; - } DHT_VAl_AC1; - - union { - __IOM uint32_t reg; /*!< Trace and Debug registers */ - - struct { - __IM uint32_t DHT_CODEMIN_DC0 : 32; /*!< write the minimum codeword of code length from 1~16 of dc0 table. - The codeword is left shifted to the MSB position of a 16bit - word */ - } bit; - } DHT_CODEMIN_DC0; - - union { - __IOM uint32_t reg; /*!< Trace and Debug registers */ - - struct { - __IM uint32_t DHT_CODEMIN_AC0 : 32; /*!< write the minimum codeword of code length from 1~16 of ac0 table. - The codeword is left shifted to the MSB position of a 16bit - word */ - } bit; - } DHT_CODEMIN_AC0; - - union { - __IOM uint32_t reg; /*!< Trace and Debug registers */ - - struct { - __IM uint32_t DHT_CODEMIN_DC1 : 32; /*!< write the minimum codeword of code length from 1~16 of dc1 table. - The codeword is left shifted to the MSB position of a 16bit - word */ - } bit; - } DHT_CODEMIN_DC1; - - union { - __IOM uint32_t reg; /*!< Trace and Debug registers */ - - struct { - __IM uint32_t DHT_CODEMIN_AC1 : 32; /*!< write the minimum codeword of code length from 1~16 of ac1 table. - The codeword is left shifted to the MSB position of a 16bit - word */ - } bit; - } DHT_CODEMIN_AC1; - - union { - __IOM uint32_t reg; /*!< Trace and Debug registers */ - - struct { - __IM uint32_t DECODE_BYTE_CNT : 26; /*!< Reserved */ - __IM uint32_t HEADER_DEC_ST : 4; /*!< Reserved */ - __IM uint32_t DECODE_SAMPLE_SEL : 2; /*!< Reserved */ - } bit; - } DECODER_STATUS0; - - union { - __IOM uint32_t reg; /*!< Trace and Debug registers */ - - struct { - __IM uint32_t ENCODE_DATA : 16; /*!< Reserved */ - __IM uint32_t COUNT_Q : 7; /*!< Reserved */ - __IM uint32_t MCU_FSM_READY : 1; /*!< Reserved */ - __IM uint32_t DECODE_DATA : 8; /*!< Reserved */ - } bit; - } DECODER_STATUS1; - - union { - __IOM uint32_t reg; /*!< Trace and Debug registers */ - - struct { - __IM uint32_t COMP_BLOCK_NUM : 26; /*!< Reserved */ - __IM uint32_t SCAN_NUM : 3; /*!< Reserved */ - __IM uint32_t RST_CHECK_WAIT : 1; /*!< Reserved */ - __IM uint32_t SCAN_CHECK_WAIT : 1; /*!< Reserved */ - __IM uint32_t MCU_IN_PROC : 1; /*!< Reserved */ - } bit; - } DECODER_STATUS2; - - union { - __IOM uint32_t reg; /*!< Trace and Debug registers */ - - struct { - __IM uint32_t LOOKUP_DATA : 32; /*!< Reserved */ - } bit; - } DECODER_STATUS3; - - union { - __IOM uint32_t reg; /*!< Trace and Debug registers */ - - struct { - __IM uint32_t BLOCK_EOF_CNT : 26; /*!< Reserved */ - __IM uint32_t DEZIGZAG_READY : 1; /*!< Reserved */ - __IM uint32_t DE_FRAME_EOF_CHECK : 1; /*!< Reserved */ - __IM uint32_t DE_DMA2D_IN_PUSH : 1; /*!< Reserved */ - uint32_t : 3; - } bit; - } DECODER_STATUS4; - - union { - __IOM uint32_t reg; /*!< Trace and Debug registers */ - - struct { - __IM uint32_t IDCT_HFM_DATA : 16; /*!< Reserved */ - __IM uint32_t NS0 : 3; /*!< Reserved */ - __IM uint32_t NS1 : 3; /*!< Reserved */ - __IM uint32_t NS2 : 3; /*!< Reserved */ - __IM uint32_t NS3 : 3; /*!< Reserved */ - __IM uint32_t DATA_LAST_O : 1; /*!< Reserved */ - __IM uint32_t RDN_RESULT : 1; /*!< redundant registers for jpeg */ - __IOM uint32_t RDN_ENA : 1; /*!< redundant control registers for jpeg */ - uint32_t : 1; - } bit; - } DECODER_STATUS5; - - union { - __IOM uint32_t reg; /*!< Trace and Debug registers */ - - struct { - __IM uint32_t PIC_BLOCK_NUM : 24; /*!< Reserved */ - uint32_t : 8; - } bit; - } STATUS5; - - union { - __IOM uint32_t reg; /*!< Trace and Debug registers */ - - struct { - __IOM uint32_t RDN_ECO_LOW : 32; /*!< redundant registers for jpeg */ - } bit; - } ECO_LOW; - - union { - __IOM uint32_t reg; /*!< Trace and Debug registers */ - - struct { - __IOM uint32_t RDN_ECO_HIGH : 32; /*!< redundant registers for jpeg */ - } bit; - } ECO_HIGH; - __IM uint32_t RESERVED1[19]; - - union { - __IOM uint32_t reg; /*!< Trace and Debug registers */ - - struct { - uint32_t : 31; - __IOM uint32_t CLK_EN : 1; /*!< Reserved */ - } bit; - } SYS; - - union { - __IOM uint32_t reg; /*!< Trace and Debug registers */ - - struct { - __IOM uint32_t JPEG_VER : 28; /*!< Reserved */ - uint32_t : 4; - } bit; - } VERSION; -} JPEG_Type; /*!< Size = 256 (0x100) */ - - - -/* =========================================================================================================================== */ -/* ================ LCD_CAM ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Camera/LCD Controller (LCD_CAM) - */ - -typedef struct { /*!< LCD_CAM Structure */ - - union { - __IOM uint32_t reg; /*!< LCD clock config register. */ - - struct { - __IOM uint32_t LCD_CLKCNT_N : 6; /*!< f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk - is 0. */ - __IOM uint32_t LCD_CLK_EQU_SYSCLK : 1; /*!< 1: f_LCD_PCLK = f_LCD_CLK. 0: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N - + 1). */ - __IOM uint32_t LCD_CK_IDLE_EDGE : 1; /*!< 1: LCD_PCLK line is high when idle 0: LCD_PCLK line is low when - idle. */ - __IOM uint32_t LCD_CK_OUT_EDGE : 1; /*!< 1: LCD_PCLK line is high in the first half data cycle. 0: LCD_PCLK - line is low in the second half data cycle. */ - __IOM uint32_t LCD_CLKM_DIV_NUM : 8; /*!< Integral LCD clock divider value */ - __IOM uint32_t LCD_CLKM_DIV_B : 6; /*!< Fractional clock divider numerator value */ - __IOM uint32_t LCD_CLKM_DIV_A : 6; /*!< Fractional clock divider denominator value */ - __IOM uint32_t LCD_CLK_SEL : 2; /*!< Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. - 3: no clock. */ - __IOM uint32_t CLK_EN : 1; /*!< Set this bit to enable clk gate */ - } bit; - } LCD_CLOCK; - - union { - __IOM uint32_t reg; /*!< CAM config register. */ - - struct { - __IOM uint32_t CAM_STOP_EN : 1; /*!< Camera stop enable signal, 1: camera stops when DMA Rx FIFO - is full. 0: Not stop. */ - __IOM uint32_t CAM_VSYNC_FILTER_THRES : 3;/*!< Filter threshold value for CAM_VSYNC signal. */ - __IOM uint32_t CAM_UPDATE : 1; /*!< 1: Update Camera registers, will be cleared by hardware. 0 : - Not care. */ - __IOM uint32_t CAM_BYTE_ORDER : 1; /*!< 1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] - in one byte mode, and bits[15:0] to bits[0:15] in two byte - mode. 0: Not change. */ - __IOM uint32_t CAM_BIT_ORDER : 1; /*!< 1: invert data byte order, only valid in 2 byte mode. 0: Not - change. */ - __IOM uint32_t CAM_LINE_INT_EN : 1; /*!< 1: Enable to generate CAM_HS_INT. 0: Disable. */ - __IOM uint32_t CAM_VS_EOF_EN : 1; /*!< 1: CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled - by reg_cam_rec_data_cyclelen. */ - __IOM uint32_t CAM_CLKM_DIV_NUM : 8; /*!< Integral Camera clock divider value */ - __IOM uint32_t CAM_CLKM_DIV_B : 6; /*!< Fractional clock divider numerator value */ - __IOM uint32_t CAM_CLKM_DIV_A : 6; /*!< Fractional clock divider denominator value */ - __IOM uint32_t CAM_CLK_SEL : 2; /*!< Select Camera module source clock. 0: no clock. 1: APLL. 2: - CLK160. 3: no clock. */ - uint32_t : 1; - } bit; - } CAM_CTRL; - - union { - __IOM uint32_t reg; /*!< CAM config register. */ - - struct { - __IOM uint32_t CAM_REC_DATA_BYTELEN : 16; /*!< Camera receive data byte length minus 1 to set DMA in_suc_eof_int. */ - __IOM uint32_t CAM_LINE_INT_NUM : 6; /*!< The line number minus 1 to generate cam_hs_int. */ - __IOM uint32_t CAM_CLK_INV : 1; /*!< 1: Invert the input signal CAM_PCLK. 0: Not invert. */ - __IOM uint32_t CAM_VSYNC_FILTER_EN : 1; /*!< 1: Enable CAM_VSYNC filter function. 0: bypass. */ - __IOM uint32_t CAM_2BYTE_EN : 1; /*!< 1: The bit number of input data is 9~16. 0: The bit number of - input data is 0~8. */ - __IOM uint32_t CAM_DE_INV : 1; /*!< CAM_DE invert enable signal, valid in high level. */ - __IOM uint32_t CAM_HSYNC_INV : 1; /*!< CAM_HSYNC invert enable signal, valid in high level. */ - __IOM uint32_t CAM_VSYNC_INV : 1; /*!< CAM_VSYNC invert enable signal, valid in high level. */ - __IOM uint32_t CAM_VH_DE_MODE_EN : 1; /*!< 1: Input control signals are CAM_DE CAM_HSYNC and CAM_VSYNC. - 0: Input control signals are CAM_DE and CAM_VSYNC. */ - __IOM uint32_t CAM_START : 1; /*!< Camera module start signal. */ - __OM uint32_t CAM_RESET : 1; /*!< Camera module reset signal. */ - __OM uint32_t CAM_AFIFO_RESET : 1; /*!< Camera AFIFO reset signal. */ - } bit; - } CAM_CTRL1; - - union { - __IOM uint32_t reg; /*!< CAM YUV/RGB converter configuration register. */ - - struct { - uint32_t : 21; - __IOM uint32_t CAM_CONV_8BITS_DATA_INV : 1;/*!< 1:invert every two 8bits input data. 2. disabled. */ - __IOM uint32_t CAM_CONV_YUV2YUV_MODE : 2; /*!< 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable - yuv2yuv mode, trans_mode must be set to 1. */ - __IOM uint32_t CAM_CONV_YUV_MODE : 2; /*!< 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode - decides the yuv mode of Data_in */ - __IOM uint32_t CAM_CONV_PROTOCOL_MODE : 1;/*!< 0:BT601. 1:BT709. */ - __IOM uint32_t CAM_CONV_DATA_OUT_MODE : 1;/*!< LIMIT or FULL mode of Data out. 0: limit. 1: full */ - __IOM uint32_t CAM_CONV_DATA_IN_MODE : 1; /*!< LIMIT or FULL mode of Data in. 0: limit. 1: full */ - __IOM uint32_t CAM_CONV_MODE_8BITS_ON : 1;/*!< 0: 16bits mode. 1: 8bits mode. */ - __IOM uint32_t CAM_CONV_TRANS_MODE : 1; /*!< 0: YUV to RGB. 1: RGB to YUV. */ - __IOM uint32_t CAM_CONV_ENABLE : 1; /*!< 0: Bypass converter. 1: Enable converter. */ - } bit; - } CAM_RGB_YUV; - - union { - __IOM uint32_t reg; /*!< LCD YUV/RGB converter configuration register. */ - - struct { - uint32_t : 20; - __IOM uint32_t LCD_CONV_8BITS_DATA_INV : 1;/*!< 1:invert every two 8bits input data. 2. disabled. */ - __IOM uint32_t LCD_CONV_TXTORX : 1; /*!< 0: txtorx mode off. 1: txtorx mode on. */ - __IOM uint32_t LCD_CONV_YUV2YUV_MODE : 2; /*!< 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable - yuv2yuv mode, trans_mode must be set to 1. */ - __IOM uint32_t LCD_CONV_YUV_MODE : 2; /*!< 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode - decides the yuv mode of Data_in */ - __IOM uint32_t LCD_CONV_PROTOCOL_MODE : 1;/*!< 0:BT601. 1:BT709. */ - __IOM uint32_t LCD_CONV_DATA_OUT_MODE : 1;/*!< LIMIT or FULL mode of Data out. 0: limit. 1: full */ - __IOM uint32_t LCD_CONV_DATA_IN_MODE : 1; /*!< LIMIT or FULL mode of Data in. 0: limit. 1: full */ - __IOM uint32_t LCD_CONV_MODE_8BITS_ON : 1;/*!< 0: 16bits mode. 1: 8bits mode. */ - __IOM uint32_t LCD_CONV_TRANS_MODE : 1; /*!< 0: YUV to RGB. 1: RGB to YUV. */ - __IOM uint32_t LCD_CONV_ENABLE : 1; /*!< 0: Bypass converter. 1: Enable converter. */ - } bit; - } LCD_RGB_YUV; - - union { - __IOM uint32_t reg; /*!< LCD config register. */ - - struct { - __IOM uint32_t LCD_DOUT_CYCLELEN : 13; /*!< The output data cycles minus 1 of LCD module. */ - __IOM uint32_t LCD_ALWAYS_OUT_EN : 1; /*!< LCD always output when LCD is in LCD_DOUT state, unless reg_lcd_start - is cleared or reg_lcd_reset is set. */ - __IOM uint32_t LCD_DOUT_BYTE_SWIZZLE_MODE : 3;/*!< 0: ABAB->BABA. 1: ABC->ACB. 2: ABC->BAC. 3: ABC->BCA. 4:ABC->CAB. - 5:ABC->CBA */ - __IOM uint32_t LCD_DOUT_BYTE_SWIZZLE_ENABLE : 1;/*!< 1: enable byte swizzle 0: disable */ - __IOM uint32_t LCD_DOUT_BIT_ORDER : 1; /*!< 1: change bit order in every byte. 0: Not change. */ - __IOM uint32_t LCD_BYTE_MODE : 2; /*!< 2: 24bit mode. 1: 16bit mode. 0: 8bit mode */ - __IOM uint32_t LCD_UPDATE : 1; /*!< 1: Update LCD registers, will be cleared by hardware. 0 : Not - care. */ - __IOM uint32_t LCD_BIT_ORDER : 1; /*!< 1: Change data bit order, change LCD_DATA_out[7:0] to LCD_DATA_out[0:7] - in one byte mode, and bits[15:0] to bits[0:15] in two byte - mode. 0: Not change. */ - __IOM uint32_t LCD_BYTE_ORDER : 1; /*!< 1: invert data byte order, only valid in 2 byte mode. 0: Not - change. */ - __IOM uint32_t LCD_DOUT : 1; /*!< 1: Be able to send data out in LCD sequence when LCD starts. - 0: Disable. */ - __IOM uint32_t LCD_DUMMY : 1; /*!< 1: Enable DUMMY phase in LCD sequence when LCD starts. 0: Disable. */ - __IOM uint32_t LCD_CMD : 1; /*!< 1: Be able to send command in LCD sequence when LCD starts. - 0: Disable. */ - __IOM uint32_t LCD_START : 1; /*!< LCD start sending data enable signal, valid in high level. */ - __OM uint32_t LCD_RESET : 1; /*!< The value of command. */ - __IOM uint32_t LCD_DUMMY_CYCLELEN : 2; /*!< The dummy cycle length minus 1. */ - __IOM uint32_t LCD_CMD_2_CYCLE_EN : 1; /*!< The cycle length of command phase. 1: 2 cycles. 0: 1 cycle. */ - } bit; - } LCD_USER; - - union { - __IOM uint32_t reg; /*!< LCD config register. */ - - struct { - uint32_t : 4; - __IOM uint32_t LCD_WIRE_MODE : 2; /*!< The wire width of LCD output. 0: 8bit. 1: 16bit 2: 24bit */ - __IOM uint32_t LCD_VFK_CYCLELEN : 6; /*!< The setup cycle length minus 1 in LCD non-RGB mode. */ - __IOM uint32_t LCD_VBK_CYCLELEN : 13; /*!< The vertical back blank region cycle length minus 1 in LCD RGB - mode, or the hold time cycle length in LCD non-RGB mode. */ - __IOM uint32_t LCD_NEXT_FRAME_EN : 1; /*!< 1: Send the next frame data when the current frame is sent out. - 0: LCD stops when the current frame is sent out. */ - __IOM uint32_t LCD_BK_EN : 1; /*!< 1: Enable blank region when LCD sends data out. 0: No blank - region. */ - __OM uint32_t LCD_AFIFO_RESET : 1; /*!< LCD AFIFO reset signal. */ - __IOM uint32_t LCD_CD_DATA_SET : 1; /*!< 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DOUT - state. 0: LCD_CD = reg_cd_idle_edge. */ - __IOM uint32_t LCD_CD_DUMMY_SET : 1; /*!< 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DUMMY - state. 0: LCD_CD = reg_cd_idle_edge. */ - __IOM uint32_t LCD_CD_CMD_SET : 1; /*!< 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_CMD - state. 0: LCD_CD = reg_cd_idle_edge. */ - __IOM uint32_t LCD_CD_IDLE_EDGE : 1; /*!< The default value of LCD_CD. */ - } bit; - } LCD_MISC; - - union { - __IOM uint32_t reg; /*!< LCD config register. */ - - struct { - __IOM uint32_t LCD_HB_FRONT : 11; /*!< It is the horizontal blank front porch of a frame. */ - __IOM uint32_t LCD_VA_HEIGHT : 10; /*!< It is the vertical active height of a frame. */ - __IOM uint32_t LCD_VT_HEIGHT : 10; /*!< It is the vertical total height of a frame. */ - __IOM uint32_t LCD_RGB_MODE_EN : 1; /*!< 1: Enable LCD RGB mode. 0: Disable LCD RGB mode. */ - } bit; - } LCD_CTRL; - - union { - __IOM uint32_t reg; /*!< LCD config register. */ - - struct { - __IOM uint32_t LCD_VB_FRONT : 8; /*!< It is the vertical blank front porch of a frame. */ - __IOM uint32_t LCD_HA_WIDTH : 12; /*!< It is the horizontal active width of a frame. */ - __IOM uint32_t LCD_HT_WIDTH : 12; /*!< It is the horizontal total width of a frame. */ - } bit; - } LCD_CTRL1; - - union { - __IOM uint32_t reg; /*!< LCD config register. */ - - struct { - __IOM uint32_t LCD_VSYNC_WIDTH : 7; /*!< It is the position of LCD_VSYNC active pulse in a line. */ - __IOM uint32_t LCD_VSYNC_IDLE_POL : 1; /*!< It is the idle value of LCD_VSYNC. */ - __IOM uint32_t LCD_DE_IDLE_POL : 1; /*!< It is the idle value of LCD_DE. */ - __IOM uint32_t LCD_HS_BLANK_EN : 1; /*!< 1: The pulse of LCD_HSYNC is out in vertical blanking lines - RGB mode. 0: LCD_HSYNC pulse is valid only in active region - lines in RGB mode. */ - uint32_t : 6; - __IOM uint32_t LCD_HSYNC_WIDTH : 7; /*!< It is the position of LCD_HSYNC active pulse in a line. */ - __IOM uint32_t LCD_HSYNC_IDLE_POL : 1; /*!< It is the idle value of LCD_HSYNC. */ - __IOM uint32_t LCD_HSYNC_POSITION : 8; /*!< It is the position of LCD_HSYNC active pulse in a line. */ - } bit; - } LCD_CTRL2; - - union { - __IOM uint32_t reg; /*!< LCD config register. */ - - struct { - __IOM uint32_t LCD_FIRST_CMD_VALUE : 32; /*!< The LCD write command value of first cmd cycle. */ - } bit; - } LCD_FIRST_CMD_VAL; - - union { - __IOM uint32_t reg; /*!< LCD config register. */ - - struct { - __IOM uint32_t LCD_LATTER_CMD_VALUE : 32; /*!< The LCD write command value of latter cmd cycle. */ - } bit; - } LCD_LATTER_CMD_VAL; - - union { - __IOM uint32_t reg; /*!< LCD config register. */ - - struct { - __IOM uint32_t DOUT16_MODE : 2; /*!< The output data bit 0 is delayed by module clock LCD_CLK. 0: - output without delayed. 1: delay by the positive edge of - LCD_CLK. 2: delay by the negative edge of LCD_CLK. */ - __IOM uint32_t DOUT17_MODE : 2; /*!< The output data bit 2 is delayed by module clock LCD_CLK. 0: - output without delayed. 1: delay by the positive edge of - LCD_CLK. 2: delay by the negative edge of LCD_CLK. */ - __IOM uint32_t DOUT18_MODE : 2; /*!< The output data bit 4 is delayed by module clock LCD_CLK. 0: - output without delayed. 1: delay by the positive edge of - LCD_CLK. 2: delay by the negative edge of LCD_CLK. */ - __IOM uint32_t DOUT19_MODE : 2; /*!< The output data bit 6 is delayed by module clock LCD_CLK. 0: - output without delayed. 1: delay by the positive edge of - LCD_CLK. 2: delay by the negative edge of LCD_CLK. */ - __IOM uint32_t DOUT20_MODE : 2; /*!< The output data bit 8 is delayed by module clock LCD_CLK. 0: - output without delayed. 1: delay by the positive edge of - LCD_CLK. 2: delay by the negative edge of LCD_CLK. */ - __IOM uint32_t DOUT21_MODE : 2; /*!< The output data bit 10 is delayed by module clock LCD_CLK. 0: - output without delayed. 1: delay by the positive edge of - LCD_CLK. 2: delay by the negative edge of LCD_CLK. */ - __IOM uint32_t DOUT22_MODE : 2; /*!< The output data bit 12 is delayed by module clock LCD_CLK. 0: - output without delayed. 1: delay by the positive edge of - LCD_CLK. 2: delay by the negative edge of LCD_CLK. */ - __IOM uint32_t DOUT23_MODE : 2; /*!< The output data bit 14 is delayed by module clock LCD_CLK. 0: - output without delayed. 1: delay by the positive edge of - LCD_CLK. 2: delay by the negative edge of LCD_CLK. */ - __IOM uint32_t LCD_CD_MODE : 2; /*!< The output LCD_CD is delayed by module clock LCD_CLK. 0: output - without delayed. 1: delay by the positive edge of LCD_CLK. - 2: delay by the negative edge of LCD_CLK. */ - __IOM uint32_t LCD_DE_MODE : 2; /*!< The output LCD_DE is delayed by module clock LCD_CLK. 0: output - without delayed. 1: delay by the positive edge of LCD_CLK. - 2: delay by the negative edge of LCD_CLK. */ - __IOM uint32_t LCD_HSYNC_MODE : 2; /*!< The output LCD_HSYNC is delayed by module clock LCD_CLK. 0: - output without delayed. 1: delay by the positive edge of - LCD_CLK. 2: delay by the negative edge of LCD_CLK. */ - __IOM uint32_t LCD_VSYNC_MODE : 2; /*!< The output LCD_VSYNC is delayed by module clock LCD_CLK. 0: - output without delayed. 1: delay by the positive edge of - LCD_CLK. 2: delay by the negative edge of LCD_CLK. */ - uint32_t : 8; - } bit; - } LCD_DLY_MODE_CFG1; - __IM uint32_t RESERVED; - - union { - __IOM uint32_t reg; /*!< LCD config register. */ - - struct { - __IOM uint32_t DOUT0_MODE : 2; /*!< The output data bit 0 is delayed by module clock LCD_CLK. 0: - output without delayed. 1: delay by the positive edge of - LCD_CLK. 2: delay by the negative edge of LCD_CLK. */ - __IOM uint32_t DOUT1_MODE : 2; /*!< The output data bit 2 is delayed by module clock LCD_CLK. 0: - output without delayed. 1: delay by the positive edge of - LCD_CLK. 2: delay by the negative edge of LCD_CLK. */ - __IOM uint32_t DOUT2_MODE : 2; /*!< The output data bit 4 is delayed by module clock LCD_CLK. 0: - output without delayed. 1: delay by the positive edge of - LCD_CLK. 2: delay by the negative edge of LCD_CLK. */ - __IOM uint32_t DOUT3_MODE : 2; /*!< The output data bit 6 is delayed by module clock LCD_CLK. 0: - output without delayed. 1: delay by the positive edge of - LCD_CLK. 2: delay by the negative edge of LCD_CLK. */ - __IOM uint32_t DOUT4_MODE : 2; /*!< The output data bit 8 is delayed by module clock LCD_CLK. 0: - output without delayed. 1: delay by the positive edge of - LCD_CLK. 2: delay by the negative edge of LCD_CLK. */ - __IOM uint32_t DOUT5_MODE : 2; /*!< The output data bit 10 is delayed by module clock LCD_CLK. 0: - output without delayed. 1: delay by the positive edge of - LCD_CLK. 2: delay by the negative edge of LCD_CLK. */ - __IOM uint32_t DOUT6_MODE : 2; /*!< The output data bit 12 is delayed by module clock LCD_CLK. 0: - output without delayed. 1: delay by the positive edge of - LCD_CLK. 2: delay by the negative edge of LCD_CLK. */ - __IOM uint32_t DOUT7_MODE : 2; /*!< The output data bit 14 is delayed by module clock LCD_CLK. 0: - output without delayed. 1: delay by the positive edge of - LCD_CLK. 2: delay by the negative edge of LCD_CLK. */ - __IOM uint32_t DOUT8_MODE : 2; /*!< The output data bit 16 is delayed by module clock LCD_CLK. 0: - output without delayed. 1: delay by the positive edge of - LCD_CLK. 2: delay by the negative edge of LCD_CLK. */ - __IOM uint32_t DOUT9_MODE : 2; /*!< The output data bit 18 is delayed by module clock LCD_CLK. 0: - output without delayed. 1: delay by the positive edge of - LCD_CLK. 2: delay by the negative edge of LCD_CLK. */ - __IOM uint32_t DOUT10_MODE : 2; /*!< The output data bit 20 is delayed by module clock LCD_CLK. 0: - output without delayed. 1: delay by the positive edge of - LCD_CLK. 2: delay by the negative edge of LCD_CLK. */ - __IOM uint32_t DOUT11_MODE : 2; /*!< The output data bit 22 is delayed by module clock LCD_CLK. 0: - output without delayed. 1: delay by the positive edge of - LCD_CLK. 2: delay by the negative edge of LCD_CLK. */ - __IOM uint32_t DOUT12_MODE : 2; /*!< The output data bit 24 is delayed by module clock LCD_CLK. 0: - output without delayed. 1: delay by the positive edge of - LCD_CLK. 2: delay by the negative edge of LCD_CLK. */ - __IOM uint32_t DOUT13_MODE : 2; /*!< The output data bit 26 is delayed by module clock LCD_CLK. 0: - output without delayed. 1: delay by the positive edge of - LCD_CLK. 2: delay by the negative edge of LCD_CLK. */ - __IOM uint32_t DOUT14_MODE : 2; /*!< The output data bit 28 is delayed by module clock LCD_CLK. 0: - output without delayed. 1: delay by the positive edge of - LCD_CLK. 2: delay by the negative edge of LCD_CLK. */ - __IOM uint32_t DOUT15_MODE : 2; /*!< The output data bit 30 is delayed by module clock LCD_CLK. 0: - output without delayed. 1: delay by the positive edge of - LCD_CLK. 2: delay by the negative edge of LCD_CLK. */ - } bit; - } LCD_DLY_MODE_CFG2; - __IM uint32_t RESERVED1[10]; - - union { - __IOM uint32_t reg; /*!< LCDCAM interrupt enable register. */ - - struct { - __IOM uint32_t LCD_VSYNC_INT_ENA : 1; /*!< The enable bit for LCD frame end interrupt. */ - __IOM uint32_t LCD_TRANS_DONE_INT_ENA : 1;/*!< The enable bit for lcd transfer end interrupt. */ - __IOM uint32_t CAM_VSYNC_INT_ENA : 1; /*!< The enable bit for Camera frame end interrupt. */ - __IOM uint32_t CAM_HS_INT_ENA : 1; /*!< The enable bit for Camera line interrupt. */ - uint32_t : 28; - } bit; - } LC_DMA_INT_ENA; - - union { - __IOM uint32_t reg; /*!< LCDCAM interrupt raw register, valid in level. */ - - struct { - __IM uint32_t LCD_VSYNC_INT_RAW : 1; /*!< The raw bit for LCD frame end interrupt. */ - __IM uint32_t LCD_TRANS_DONE_INT_RAW : 1;/*!< The raw bit for lcd transfer end interrupt. */ - __IM uint32_t CAM_VSYNC_INT_RAW : 1; /*!< The raw bit for Camera frame end interrupt. */ - __IM uint32_t CAM_HS_INT_RAW : 1; /*!< The raw bit for Camera line interrupt. */ - uint32_t : 28; - } bit; - } LC_DMA_INT_RAW; - - union { - __IOM uint32_t reg; /*!< LCDCAM interrupt status register. */ - - struct { - __IM uint32_t LCD_VSYNC_INT_ST : 1; /*!< The status bit for LCD frame end interrupt. */ - __IM uint32_t LCD_TRANS_DONE_INT_ST : 1; /*!< The status bit for lcd transfer end interrupt. */ - __IM uint32_t CAM_VSYNC_INT_ST : 1; /*!< The status bit for Camera frame end interrupt. */ - __IM uint32_t CAM_HS_INT_ST : 1; /*!< The status bit for Camera transfer end interrupt. */ - uint32_t : 28; - } bit; - } LC_DMA_INT_ST; - - union { - __IOM uint32_t reg; /*!< LCDCAM interrupt clear register. */ - - struct { - __OM uint32_t LCD_VSYNC_INT_CLR : 1; /*!< The clear bit for LCD frame end interrupt. */ - __OM uint32_t LCD_TRANS_DONE_INT_CLR : 1;/*!< The clear bit for lcd transfer end interrupt. */ - __OM uint32_t CAM_VSYNC_INT_CLR : 1; /*!< The clear bit for Camera frame end interrupt. */ - __OM uint32_t CAM_HS_INT_CLR : 1; /*!< The clear bit for Camera line interrupt. */ - uint32_t : 28; - } bit; - } LC_DMA_INT_CLR; - __IM uint32_t RESERVED2[34]; - - union { - __IOM uint32_t reg; /*!< Version register */ - - struct { - __IOM uint32_t LC_DATE : 28; /*!< LCD_CAM version control register */ - uint32_t : 4; - } bit; - } LC_REG_DATE; -} LCD_CAM_Type; /*!< Size = 256 (0x100) */ - - - -/* =========================================================================================================================== */ -/* ================ LEDC ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief LED Control PWM (Pulse Width Modulation) (LEDC) - */ - -typedef struct { /*!< LEDC Structure */ - __IOM uint32_t CH0_CONF0; /*!< Configuration register 0 for channel 0 */ - __IOM uint32_t CH0_HPOINT; /*!< High point register for channel 0 */ - __IOM uint32_t CH0_DUTY; /*!< Initial duty cycle register for channel 0 */ - - union { - __IOM uint32_t reg; /*!< Configuration register 1 for channel 0 */ - - struct { - uint32_t : 31; - __IOM uint32_t DUTY_START_CH : 1; /*!< Configures whether the duty cycle fading configurations take - effect.\\0: Not take effect\\1: Take effect */ - } bit; - } CH0_CONF1; - __IOM uint32_t CH0_DUTY_R; /*!< Current duty cycle register for channel 0 */ - __IM uint32_t RESERVED[15]; - __IOM uint32_t CH1_CONF0; /*!< Configuration register 0 for channel 1 */ - __IOM uint32_t CH1_HPOINT; /*!< High point register for channel 1 */ - __IOM uint32_t CH1_DUTY; /*!< Initial duty cycle register for channel 1 */ - - union { - __IOM uint32_t reg; /*!< Configuration register 1 for channel 1 */ - - struct { - uint32_t : 31; - __IOM uint32_t DUTY_START_CH : 1; /*!< Configures whether the duty cycle fading configurations take - effect.\\0: Not take effect\\1: Take effect */ - } bit; - } CH1_CONF1; - __IOM uint32_t CH1_DUTY_R; /*!< Current duty cycle register for channel 1 */ - __IM uint32_t RESERVED1[15]; - - union { - __IOM uint32_t CH2_CONF0; /*!< Configuration register 0 for channel 2 */ - __IOM uint32_t TIMER0_CONF; /*!< Timer 0 configuration register */ - }; - - union { - __IOM uint32_t CH2_HPOINT; /*!< High point register for channel 2 */ - __IOM uint32_t TIMER0_VALUE; /*!< Timer 0 current counter value register */ - }; - __IOM uint32_t CH2_DUTY; /*!< Initial duty cycle register for channel 2 */ - - union { - __IOM uint32_t reg; /*!< Configuration register 1 for channel 2 */ - - struct { - uint32_t : 31; - __IOM uint32_t DUTY_START_CH : 1; /*!< Configures whether the duty cycle fading configurations take - effect.\\0: Not take effect\\1: Take effect */ - } bit; - } CH2_CONF1; - __IOM uint32_t CH2_DUTY_R; /*!< Current duty cycle register for channel 2 */ - __IM uint32_t RESERVED2[3]; - - union { - __IOM uint32_t TIMER1_CONF; /*!< Timer 1 configuration register */ - - union { - __IOM uint32_t reg; /*!< Interrupt raw status register */ - - struct { - __IOM uint32_t TIMER0_OVF_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of LEDC_TIMER0_OVF_INT. - Triggered when the timer0 has reached its maximum counter - value. */ - __IOM uint32_t TIMER1_OVF_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of LEDC_TIMER1_OVF_INT. - Triggered when the timer1 has reached its maximum counter - value. */ - __IOM uint32_t TIMER2_OVF_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of LEDC_TIMER2_OVF_INT. - Triggered when the timer2 has reached its maximum counter - value. */ - __IOM uint32_t TIMER3_OVF_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of LEDC_TIMER3_OVF_INT. - Triggered when the timer3 has reached its maximum counter - value. */ - __IOM uint32_t DUTY_CHNG_END_CH0_INT_RAW : 1;/*!< Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. - Triggered when the fading of duty has finished. */ - __IOM uint32_t DUTY_CHNG_END_CH1_INT_RAW : 1;/*!< Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. - Triggered when the fading of duty has finished. */ - __IOM uint32_t DUTY_CHNG_END_CH2_INT_RAW : 1;/*!< Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. - Triggered when the fading of duty has finished. */ - __IOM uint32_t DUTY_CHNG_END_CH3_INT_RAW : 1;/*!< Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. - Triggered when the fading of duty has finished. */ - __IOM uint32_t DUTY_CHNG_END_CH4_INT_RAW : 1;/*!< Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. - Triggered when the fading of duty has finished. */ - __IOM uint32_t DUTY_CHNG_END_CH5_INT_RAW : 1;/*!< Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. - Triggered when the fading of duty has finished. */ - __IOM uint32_t DUTY_CHNG_END_CH6_INT_RAW : 1;/*!< Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH6_INT. - Triggered when the fading of duty has finished. */ - __IOM uint32_t DUTY_CHNG_END_CH7_INT_RAW : 1;/*!< Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH7_INT. - Triggered when the fading of duty has finished. */ - __IOM uint32_t OVF_CNT_CH0_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH0_INT. - Triggered when the ovf_cnt has reached the value specified - by LEDC_OVF_NUM_CH0. */ - __IOM uint32_t OVF_CNT_CH1_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH1_INT. - Triggered when the ovf_cnt has reached the value specified - by LEDC_OVF_NUM_CH1. */ - __IOM uint32_t OVF_CNT_CH2_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH2_INT. - Triggered when the ovf_cnt has reached the value specified - by LEDC_OVF_NUM_CH2. */ - __IOM uint32_t OVF_CNT_CH3_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH3_INT. - Triggered when the ovf_cnt has reached the value specified - by LEDC_OVF_NUM_CH3. */ - __IOM uint32_t OVF_CNT_CH4_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH4_INT. - Triggered when the ovf_cnt has reached the value specified - by LEDC_OVF_NUM_CH4. */ - __IOM uint32_t OVF_CNT_CH5_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH5_INT. - Triggered when the ovf_cnt has reached the value specified - by LEDC_OVF_NUM_CH5. */ - __IOM uint32_t OVF_CNT_CH6_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH6_INT. - Triggered when the ovf_cnt has reached the value specified - by LEDC_OVF_NUM_CH6. */ - __IOM uint32_t OVF_CNT_CH7_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH7_INT. - Triggered when the ovf_cnt has reached the value specified - by LEDC_OVF_NUM_CH7. */ - uint32_t : 12; - } bit; - } INT_RAW; - }; - - union { - __IOM uint32_t TIMER1_VALUE; /*!< Timer 1 current counter value register */ - - union { - __IOM uint32_t reg; /*!< Interrupt masked status register */ - - struct { - __IM uint32_t TIMER0_OVF_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of LEDC_TIMER0_OVF_INT. - Valid only when LEDC_TIMER0_OVF_INT_ENA is set to 1. */ - __IM uint32_t TIMER1_OVF_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of LEDC_TIMER1_OVF_INT. - Valid only when LEDC_TIMER1_OVF_INT_ENA is set to 1. */ - __IM uint32_t TIMER2_OVF_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of LEDC_TIMER2_OVF_INT. - Valid only when LEDC_TIMER2_OVF_INT_ENA is set to 1. */ - __IM uint32_t TIMER3_OVF_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of LEDC_TIMER3_OVF_INT. - Valid only when LEDC_TIMER3_OVF_INT_ENA is set to 1. */ - __IM uint32_t DUTY_CHNG_END_CH0_INT_ST : 1;/*!< Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. - Valid only when LEDC_DUTY_CHNG_END_CH0_INT_ENA is set to - 1. */ - __IM uint32_t DUTY_CHNG_END_CH1_INT_ST : 1;/*!< Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. - Valid only when LEDC_DUTY_CHNG_END_CH1_INT_ENA is set to - 1. */ - __IM uint32_t DUTY_CHNG_END_CH2_INT_ST : 1;/*!< Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. - Valid only when LEDC_DUTY_CHNG_END_CH2_INT_ENA is set to - 1. */ - __IM uint32_t DUTY_CHNG_END_CH3_INT_ST : 1;/*!< Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. - Valid only when LEDC_DUTY_CHNG_END_CH3_INT_ENA is set to - 1. */ - __IM uint32_t DUTY_CHNG_END_CH4_INT_ST : 1;/*!< Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. - Valid only when LEDC_DUTY_CHNG_END_CH4_INT_ENA is set to - 1. */ - __IM uint32_t DUTY_CHNG_END_CH5_INT_ST : 1;/*!< Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. - Valid only when LEDC_DUTY_CHNG_END_CH5_INT_ENA is set to - 1. */ - __IM uint32_t DUTY_CHNG_END_CH6_INT_ST : 1;/*!< Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH6_INT. - Valid only when LEDC_DUTY_CHNG_END_CH6_INT_ENA is set to - 1. */ - __IM uint32_t DUTY_CHNG_END_CH7_INT_ST : 1;/*!< Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH7_INT. - Valid only when LEDC_DUTY_CHNG_END_CH7_INT_ENA is set to - 1. */ - __IM uint32_t OVF_CNT_CH0_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH0_INT. - Valid only when LEDC_OVF_CNT_CH0_INT_ENA is set to 1. */ - __IM uint32_t OVF_CNT_CH1_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH1_INT. - Valid only when LEDC_OVF_CNT_CH1_INT_ENA is set to 1. */ - __IM uint32_t OVF_CNT_CH2_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH2_INT. - Valid only when LEDC_OVF_CNT_CH2_INT_ENA is set to 1. */ - __IM uint32_t OVF_CNT_CH3_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH3_INT. - Valid only when LEDC_OVF_CNT_CH3_INT_ENA is set to 1. */ - __IM uint32_t OVF_CNT_CH4_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH4_INT. - Valid only when LEDC_OVF_CNT_CH4_INT_ENA is set to 1. */ - __IM uint32_t OVF_CNT_CH5_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH5_INT. - Valid only when LEDC_OVF_CNT_CH5_INT_ENA is set to 1. */ - __IM uint32_t OVF_CNT_CH6_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH6_INT. - Valid only when LEDC_OVF_CNT_CH6_INT_ENA is set to 1. */ - __IM uint32_t OVF_CNT_CH7_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH7_INT. - Valid only when LEDC_OVF_CNT_CH7_INT_ENA is set to 1. */ - uint32_t : 12; - } bit; - } INT_ST; - }; - - union { - __IOM uint32_t reg; /*!< Interrupt enable register */ - - struct { - __IOM uint32_t TIMER0_OVF_INT_ENA : 1; /*!< Enable bit: Write 1 to enable LEDC_TIMER0_OVF_INT. */ - __IOM uint32_t TIMER1_OVF_INT_ENA : 1; /*!< Enable bit: Write 1 to enable LEDC_TIMER1_OVF_INT. */ - __IOM uint32_t TIMER2_OVF_INT_ENA : 1; /*!< Enable bit: Write 1 to enable LEDC_TIMER2_OVF_INT. */ - __IOM uint32_t TIMER3_OVF_INT_ENA : 1; /*!< Enable bit: Write 1 to enable LEDC_TIMER3_OVF_INT. */ - __IOM uint32_t DUTY_CHNG_END_CH0_INT_ENA : 1;/*!< Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH0_INT. */ - __IOM uint32_t DUTY_CHNG_END_CH1_INT_ENA : 1;/*!< Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH1_INT. */ - __IOM uint32_t DUTY_CHNG_END_CH2_INT_ENA : 1;/*!< Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH2_INT. */ - __IOM uint32_t DUTY_CHNG_END_CH3_INT_ENA : 1;/*!< Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH3_INT. */ - __IOM uint32_t DUTY_CHNG_END_CH4_INT_ENA : 1;/*!< Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH4_INT. */ - __IOM uint32_t DUTY_CHNG_END_CH5_INT_ENA : 1;/*!< Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH5_INT. */ - __IOM uint32_t DUTY_CHNG_END_CH6_INT_ENA : 1;/*!< Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH6_INT. */ - __IOM uint32_t DUTY_CHNG_END_CH7_INT_ENA : 1;/*!< Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH7_INT. */ - __IOM uint32_t OVF_CNT_CH0_INT_ENA : 1; /*!< Enable bit: Write 1 to enable LEDC_OVF_CNT_CH0_INT. */ - __IOM uint32_t OVF_CNT_CH1_INT_ENA : 1; /*!< Enable bit: Write 1 to enable LEDC_OVF_CNT_CH1_INT. */ - __IOM uint32_t OVF_CNT_CH2_INT_ENA : 1; /*!< Enable bit: Write 1 to enable LEDC_OVF_CNT_CH2_INT. */ - __IOM uint32_t OVF_CNT_CH3_INT_ENA : 1; /*!< Enable bit: Write 1 to enable LEDC_OVF_CNT_CH3_INT. */ - __IOM uint32_t OVF_CNT_CH4_INT_ENA : 1; /*!< Enable bit: Write 1 to enable LEDC_OVF_CNT_CH4_INT. */ - __IOM uint32_t OVF_CNT_CH5_INT_ENA : 1; /*!< Enable bit: Write 1 to enable LEDC_OVF_CNT_CH5_INT. */ - __IOM uint32_t OVF_CNT_CH6_INT_ENA : 1; /*!< Enable bit: Write 1 to enable LEDC_OVF_CNT_CH6_INT. */ - __IOM uint32_t OVF_CNT_CH7_INT_ENA : 1; /*!< Enable bit: Write 1 to enable LEDC_OVF_CNT_CH7_INT. */ - uint32_t : 12; - } bit; - } INT_ENA; - - union { - __IOM uint32_t reg; /*!< Interrupt clear register */ - - struct { - __OM uint32_t TIMER0_OVF_INT_CLR : 1; /*!< Clear bit: Write 1 to clear LEDC_TIMER0_OVF_INT. */ - __OM uint32_t TIMER1_OVF_INT_CLR : 1; /*!< Clear bit: Write 1 to clear LEDC_TIMER1_OVF_INT. */ - __OM uint32_t TIMER2_OVF_INT_CLR : 1; /*!< Clear bit: Write 1 to clear LEDC_TIMER2_OVF_INT. */ - __OM uint32_t TIMER3_OVF_INT_CLR : 1; /*!< Clear bit: Write 1 to clear LEDC_TIMER3_OVF_INT. */ - __OM uint32_t DUTY_CHNG_END_CH0_INT_CLR : 1;/*!< Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH0_INT. */ - __OM uint32_t DUTY_CHNG_END_CH1_INT_CLR : 1;/*!< Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH1_INT. */ - __OM uint32_t DUTY_CHNG_END_CH2_INT_CLR : 1;/*!< Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH2_INT. */ - __OM uint32_t DUTY_CHNG_END_CH3_INT_CLR : 1;/*!< Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH3_INT. */ - __OM uint32_t DUTY_CHNG_END_CH4_INT_CLR : 1;/*!< Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH4_INT. */ - __OM uint32_t DUTY_CHNG_END_CH5_INT_CLR : 1;/*!< Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH5_INT. */ - __OM uint32_t DUTY_CHNG_END_CH6_INT_CLR : 1;/*!< Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH6_INT. */ - __OM uint32_t DUTY_CHNG_END_CH7_INT_CLR : 1;/*!< Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH7_INT. */ - __OM uint32_t OVF_CNT_CH0_INT_CLR : 1; /*!< Clear bit: Write 1 to clear LEDC_OVF_CNT_CH0_INT. */ - __OM uint32_t OVF_CNT_CH1_INT_CLR : 1; /*!< Clear bit: Write 1 to clear LEDC_OVF_CNT_CH1_INT. */ - __OM uint32_t OVF_CNT_CH2_INT_CLR : 1; /*!< Clear bit: Write 1 to clear LEDC_OVF_CNT_CH2_INT. */ - __OM uint32_t OVF_CNT_CH3_INT_CLR : 1; /*!< Clear bit: Write 1 to clear LEDC_OVF_CNT_CH3_INT. */ - __OM uint32_t OVF_CNT_CH4_INT_CLR : 1; /*!< Clear bit: Write 1 to clear LEDC_OVF_CNT_CH4_INT. */ - __OM uint32_t OVF_CNT_CH5_INT_CLR : 1; /*!< Clear bit: Write 1 to clear LEDC_OVF_CNT_CH5_INT. */ - __OM uint32_t OVF_CNT_CH6_INT_CLR : 1; /*!< Clear bit: Write 1 to clear LEDC_OVF_CNT_CH6_INT. */ - __OM uint32_t OVF_CNT_CH7_INT_CLR : 1; /*!< Clear bit: Write 1 to clear LEDC_OVF_CNT_CH7_INT. */ - uint32_t : 12; - } bit; - } INT_CLR; - __IM uint32_t RESERVED3[4]; - __IOM uint32_t TIMER2_CONF; /*!< Timer 2 configuration register */ - __IOM uint32_t TIMER2_VALUE; /*!< Timer 2 current counter value register */ - __IM uint32_t RESERVED4[2]; - __IOM uint32_t CH3_CONF0; /*!< Configuration register 0 for channel 3 */ - __IOM uint32_t CH3_HPOINT; /*!< High point register for channel 3 */ - __IOM uint32_t CH3_DUTY; /*!< Initial duty cycle register for channel 3 */ - - union { - __IOM uint32_t reg; /*!< Configuration register 1 for channel 3 */ - - struct { - uint32_t : 31; - __IOM uint32_t DUTY_START_CH : 1; /*!< Configures whether the duty cycle fading configurations take - effect.\\0: Not take effect\\1: Take effect */ - } bit; - } CH3_CONF1; - - union { - __IOM uint32_t CH3_DUTY_R; /*!< Current duty cycle register for channel 3 */ - __IOM uint32_t TIMER3_CONF; /*!< Timer 3 configuration register */ - __IOM uint32_t CH0_GAMMA_CONF; /*!< Ledc ch0 gamma config register. */ - }; - __IOM uint32_t TIMER3_VALUE; /*!< Timer 3 current counter value register */ - __IM uint32_t RESERVED5[2]; - __IOM uint32_t CH1_GAMMA_CONF; /*!< Ledc ch1 gamma config register. */ - __IM uint32_t RESERVED6[3]; - - union { - __IOM uint32_t CH2_GAMMA_CONF; /*!< Ledc ch2 gamma config register. */ - - union { - __IOM uint32_t reg; /*!< Ledc event task enable bit register0. */ - - struct { - __IOM uint32_t EVT_DUTY_CHNG_END_CH0_EN : 1;/*!< Configures whether or not to enable the ledc_ch0_duty_chng_end - event.\\0: Disable\\1: Enable */ - __IOM uint32_t EVT_DUTY_CHNG_END_CH1_EN : 1;/*!< Configures whether or not to enable the ledc_ch1_duty_chng_end - event.\\0: Disable\\1: Enable */ - __IOM uint32_t EVT_DUTY_CHNG_END_CH2_EN : 1;/*!< Configures whether or not to enable the ledc_ch2_duty_chng_end - event.\\0: Disable\\1: Enable */ - __IOM uint32_t EVT_DUTY_CHNG_END_CH3_EN : 1;/*!< Configures whether or not to enable the ledc_ch3_duty_chng_end - event.\\0: Disable\\1: Enable */ - __IOM uint32_t EVT_DUTY_CHNG_END_CH4_EN : 1;/*!< Configures whether or not to enable the ledc_ch4_duty_chng_end - event.\\0: Disable\\1: Enable */ - __IOM uint32_t EVT_DUTY_CHNG_END_CH5_EN : 1;/*!< Configures whether or not to enable the ledc_ch5_duty_chng_end - event.\\0: Disable\\1: Enable */ - __IOM uint32_t EVT_DUTY_CHNG_END_CH6_EN : 1;/*!< Configures whether or not to enable the ledc_ch6_duty_chng_end - event.\\0: Disable\\1: Enable */ - __IOM uint32_t EVT_DUTY_CHNG_END_CH7_EN : 1;/*!< Configures whether or not to enable the ledc_ch7_duty_chng_end - event.\\0: Disable\\1: Enable */ - __IOM uint32_t EVT_OVF_CNT_PLS_CH0_EN : 1;/*!< Configures whether or not to enable the ledc_ch0_ovf_cnt_pls - event.\\0: Disable\\1: Enable */ - __IOM uint32_t EVT_OVF_CNT_PLS_CH1_EN : 1;/*!< Configures whether or not to enable the ledc_ch1_ovf_cnt_pls - event.\\0: Disable\\1: Enable */ - __IOM uint32_t EVT_OVF_CNT_PLS_CH2_EN : 1;/*!< Configures whether or not to enable the ledc_ch2_ovf_cnt_pls - event.\\0: Disable\\1: Enable */ - __IOM uint32_t EVT_OVF_CNT_PLS_CH3_EN : 1;/*!< Configures whether or not to enable the ledc_ch3_ovf_cnt_pls - event.\\0: Disable\\1: Enable */ - __IOM uint32_t EVT_OVF_CNT_PLS_CH4_EN : 1;/*!< Configures whether or not to enable the ledc_ch4_ovf_cnt_pls - event.\\0: Disable\\1: Enable */ - __IOM uint32_t EVT_OVF_CNT_PLS_CH5_EN : 1;/*!< Configures whether or not to enable the ledc_ch5_ovf_cnt_pls - event.\\0: Disable\\1: Enable */ - __IOM uint32_t EVT_OVF_CNT_PLS_CH6_EN : 1;/*!< Configures whether or not to enable the ledc_ch6_ovf_cnt_pls - event.\\0: Disable\\1: Enable */ - __IOM uint32_t EVT_OVF_CNT_PLS_CH7_EN : 1;/*!< Configures whether or not to enable the ledc_ch7_ovf_cnt_pls - event.\\0: Disable\\1: Enable */ - __IOM uint32_t EVT_TIME_OVF_TIMER0_EN : 1;/*!< Configures whether or not to enable the ledc_timer0_ovf event.\\0: - Disable\\1: Enable */ - __IOM uint32_t EVT_TIME_OVF_TIMER1_EN : 1;/*!< Configures whether or not to enable the ledc_timer1_ovf event.\\0: - Disable\\1: Enable */ - __IOM uint32_t EVT_TIME_OVF_TIMER2_EN : 1;/*!< Configures whether or not to enable the ledc_timer2_ovf event.\\0: - Disable\\1: Enable */ - __IOM uint32_t EVT_TIME_OVF_TIMER3_EN : 1;/*!< Configures whether or not to enable the ledc_timer3_ovf event.\\0: - Disable\\1: Enable */ - __IOM uint32_t EVT_TIME0_CMP_EN : 1; /*!< Configures whether or not to enable the ledc_timer0_cmp event.\\0: - Disable\\1: Enable */ - __IOM uint32_t EVT_TIME1_CMP_EN : 1; /*!< Configures whether or not to enable the ledc_timer1_cmp event.\\0: - Disable\\1: Enable */ - __IOM uint32_t EVT_TIME2_CMP_EN : 1; /*!< Configures whether or not to enable the ledc_timer2_cmp event.\\0: - Disable\\1: Enable */ - __IOM uint32_t EVT_TIME3_CMP_EN : 1; /*!< Configures whether or not to enable the ledc_timer3_cmp event.\\0: - Disable\\1: Enable */ - __IOM uint32_t TASK_DUTY_SCALE_UPDATE_CH0_EN : 1;/*!< Configures whether or not to enable the ledc_ch0_duty_scale_update - task.\\0: Disable\\1: Enable */ - __IOM uint32_t TASK_DUTY_SCALE_UPDATE_CH1_EN : 1;/*!< Configures whether or not to enable the ledc_ch1_duty_scale_update - task.\\0: Disable\\1: Enable */ - __IOM uint32_t TASK_DUTY_SCALE_UPDATE_CH2_EN : 1;/*!< Configures whether or not to enable the ledc_ch2_duty_scale_update - task.\\0: Disable\\1: Enable */ - __IOM uint32_t TASK_DUTY_SCALE_UPDATE_CH3_EN : 1;/*!< Configures whether or not to enable the ledc_ch3_duty_scale_update - task.\\0: Disable\\1: Enable */ - __IOM uint32_t TASK_DUTY_SCALE_UPDATE_CH4_EN : 1;/*!< Configures whether or not to enable the ledc_ch4_duty_scale_update - task.\\0: Disable\\1: Enable */ - __IOM uint32_t TASK_DUTY_SCALE_UPDATE_CH5_EN : 1;/*!< Configures whether or not to enable the ledc_ch5_duty_scale_update - task.\\0: Disable\\1: Enable */ - __IOM uint32_t TASK_DUTY_SCALE_UPDATE_CH6_EN : 1;/*!< Configures whether or not to enable the ledc_ch6_duty_scale_update - task.\\0: Disable\\1: Enable */ - __IOM uint32_t TASK_DUTY_SCALE_UPDATE_CH7_EN : 1;/*!< Configures whether or not to enable the ledc_ch7_duty_scale_update - task.\\0: Disable\\1: Enable */ - } bit; - } EVT_TASK_EN0; - }; - - union { - __IOM uint32_t reg; /*!< Ledc event task enable bit register1. */ - - struct { - __IOM uint32_t TASK_TIMER0_RES_UPDATE_EN : 1;/*!< Configures whether or not to enable ledc_timer0_res_update task.\\0: - Disable\\1: Enable */ - __IOM uint32_t TASK_TIMER1_RES_UPDATE_EN : 1;/*!< Configures whether or not to enable ledc_timer1_res_update task.\\0: - Disable\\1: Enable */ - __IOM uint32_t TASK_TIMER2_RES_UPDATE_EN : 1;/*!< Configures whether or not to enable ledc_timer2_res_update task.\\0: - Disable\\1: Enable */ - __IOM uint32_t TASK_TIMER3_RES_UPDATE_EN : 1;/*!< Configures whether or not to enable ledc_timer3_res_update task.\\0: - Disable\\1: Enable */ - __IOM uint32_t TASK_TIMER0_CAP_EN : 1; /*!< Configures whether or not to enable ledc_timer0_cap task.\\0: - Disable\\1: Enable */ - __IOM uint32_t TASK_TIMER1_CAP_EN : 1; /*!< Configures whether or not to enable ledc_timer1_cap task.\\0: - Disable\\1: Enable */ - __IOM uint32_t TASK_TIMER2_CAP_EN : 1; /*!< Configures whether or not to enable ledc_timer2_cap task.\\0: - Disable\\1: Enable */ - __IOM uint32_t TASK_TIMER3_CAP_EN : 1; /*!< Configures whether or not to enable ledc_timer3_cap task.\\0: - Disable\\1: Enable */ - __IOM uint32_t TASK_SIG_OUT_DIS_CH0_EN : 1;/*!< Configures whether or not to enable ledc_ch0_sig_out_dis task.\\0: - Disable\\1: Enable */ - __IOM uint32_t TASK_SIG_OUT_DIS_CH1_EN : 1;/*!< Configures whether or not to enable ledc_ch1_sig_out_dis task.\\0: - Disable\\1: Enable */ - __IOM uint32_t TASK_SIG_OUT_DIS_CH2_EN : 1;/*!< Configures whether or not to enable ledc_ch2_sig_out_dis task.\\0: - Disable\\1: Enable */ - __IOM uint32_t TASK_SIG_OUT_DIS_CH3_EN : 1;/*!< Configures whether or not to enable ledc_ch3_sig_out_dis task.\\0: - Disable\\1: Enable */ - __IOM uint32_t TASK_SIG_OUT_DIS_CH4_EN : 1;/*!< Configures whether or not to enable ledc_ch4_sig_out_dis task.\\0: - Disable\\1: Enable */ - __IOM uint32_t TASK_SIG_OUT_DIS_CH5_EN : 1;/*!< Configures whether or not to enable ledc_ch5_sig_out_dis task.\\0: - Disable\\1: Enable */ - __IOM uint32_t TASK_SIG_OUT_DIS_CH6_EN : 1;/*!< Configures whether or not to enable ledc_ch6_sig_out_dis task.\\0: - Disable\\1: Enable */ - __IOM uint32_t TASK_SIG_OUT_DIS_CH7_EN : 1;/*!< Configures whether or not to enable ledc_ch7_sig_out_dis task.\\0: - Disable\\1: Enable */ - __IOM uint32_t TASK_OVF_CNT_RST_CH0_EN : 1;/*!< Configures whether or not to enable ledc_ch0_ovf_cnt_rst task.\\0: - Disable\\1: Enable */ - __IOM uint32_t TASK_OVF_CNT_RST_CH1_EN : 1;/*!< Configures whether or not to enable ledc_ch1_ovf_cnt_rst task.\\0: - Disable\\1: Enable */ - __IOM uint32_t TASK_OVF_CNT_RST_CH2_EN : 1;/*!< Configures whether or not to enable ledc_ch2_ovf_cnt_rst task.\\0: - Disable\\1: Enable */ - __IOM uint32_t TASK_OVF_CNT_RST_CH3_EN : 1;/*!< Configures whether or not to enable ledc_ch3_ovf_cnt_rst task.\\0: - Disable\\1: Enable */ - __IOM uint32_t TASK_OVF_CNT_RST_CH4_EN : 1;/*!< Configures whether or not to enable ledc_ch4_ovf_cnt_rst task.\\0: - Disable\\1: Enable */ - __IOM uint32_t TASK_OVF_CNT_RST_CH5_EN : 1;/*!< Configures whether or not to enable ledc_ch5_ovf_cnt_rst task.\\0: - Disable\\1: Enable */ - __IOM uint32_t TASK_OVF_CNT_RST_CH6_EN : 1;/*!< Configures whether or not to enable ledc_ch6_ovf_cnt_rst task.\\0: - Disable\\1: Enable */ - __IOM uint32_t TASK_OVF_CNT_RST_CH7_EN : 1;/*!< Configures whether or not to enable ledc_ch7_ovf_cnt_rst task.\\0: - Disable\\1: Enable */ - __IOM uint32_t TASK_TIMER0_RST_EN : 1; /*!< Configures whether or not to enable ledc_timer0_rst task.\\0: - Disable\\1: Enable */ - __IOM uint32_t TASK_TIMER1_RST_EN : 1; /*!< Configures whether or not to enable ledc_timer1_rst task.\\0: - Disable\\1: Enable */ - __IOM uint32_t TASK_TIMER2_RST_EN : 1; /*!< Configures whether or not to enable ledc_timer2_rst task.\\0: - Disable\\1: Enable */ - __IOM uint32_t TASK_TIMER3_RST_EN : 1; /*!< Configures whether or not to enable ledc_timer3_rst task.\\0: - Disable\\1: Enable */ - __IOM uint32_t TASK_TIMER0_PAUSE_RESUME_EN : 1;/*!< Configures whether or not to enable ledc_timer0_pause_resume - task.\\0: Disable\\1: Enable */ - __IOM uint32_t TASK_TIMER1_PAUSE_RESUME_EN : 1;/*!< Configures whether or not to enable ledc_timer1_pause_resume - task.\\0: Disable\\1: Enable */ - __IOM uint32_t TASK_TIMER2_PAUSE_RESUME_EN : 1;/*!< Configures whether or not to enable ledc_timer2_pause_resume - task.\\0: Disable\\1: Enable */ - __IOM uint32_t TASK_TIMER3_PAUSE_RESUME_EN : 1;/*!< Configures whether or not to enable ledc_timer3_pause_resume - task.\\0: Disable\\1: Enable */ - } bit; - } EVT_TASK_EN1; - - union { - __IOM uint32_t reg; /*!< Ledc event task enable bit register2. */ - - struct { - __IOM uint32_t TASK_GAMMA_RESTART_CH0_EN : 1;/*!< Configures whether or not to enable ledc_ch0_gamma_restart task.\\0: - Disable\\1: Enable */ - __IOM uint32_t TASK_GAMMA_RESTART_CH1_EN : 1;/*!< Configures whether or not to enable ledc_ch1_gamma_restart task.\\0: - Disable\\1: Enable */ - __IOM uint32_t TASK_GAMMA_RESTART_CH2_EN : 1;/*!< Configures whether or not to enable ledc_ch2_gamma_restart task.\\0: - Disable\\1: Enable */ - __IOM uint32_t TASK_GAMMA_RESTART_CH3_EN : 1;/*!< Configures whether or not to enable ledc_ch3_gamma_restart task.\\0: - Disable\\1: Enable */ - __IOM uint32_t TASK_GAMMA_RESTART_CH4_EN : 1;/*!< Configures whether or not to enable ledc_ch4_gamma_restart task.\\0: - Disable\\1: Enable */ - __IOM uint32_t TASK_GAMMA_RESTART_CH5_EN : 1;/*!< Configures whether or not to enable ledc_ch5_gamma_restart task.\\0: - Disable\\1: Enable */ - __IOM uint32_t TASK_GAMMA_RESTART_CH6_EN : 1;/*!< Configures whether or not to enable ledc_ch6_gamma_restart task.\\0: - Disable\\1: Enable */ - __IOM uint32_t TASK_GAMMA_RESTART_CH7_EN : 1;/*!< Configures whether or not to enable ledc_ch7_gamma_restart task.\\0: - Disable\\1: Enable */ - __IOM uint32_t TASK_GAMMA_PAUSE_CH0_EN : 1;/*!< Configures whether or not to enable ledc_ch0_gamma_pause task.\\0: - Disable\\1: Enable */ - __IOM uint32_t TASK_GAMMA_PAUSE_CH1_EN : 1;/*!< Configures whether or not to enable ledc_ch1_gamma_pause task.\\0: - Disable\\1: Enable */ - __IOM uint32_t TASK_GAMMA_PAUSE_CH2_EN : 1;/*!< Configures whether or not to enable ledc_ch2_gamma_pause task.\\0: - Disable\\1: Enable */ - __IOM uint32_t TASK_GAMMA_PAUSE_CH3_EN : 1;/*!< Configures whether or not to enable ledc_ch3_gamma_pause task.\\0: - Disable\\1: Enable */ - __IOM uint32_t TASK_GAMMA_PAUSE_CH4_EN : 1;/*!< Configures whether or not to enable ledc_ch4_gamma_pause task.\\0: - Disable\\1: Enable */ - __IOM uint32_t TASK_GAMMA_PAUSE_CH5_EN : 1;/*!< Configures whether or not to enable ledc_ch5_gamma_pause task.\\0: - Disable\\1: Enable */ - __IOM uint32_t TASK_GAMMA_PAUSE_CH6_EN : 1;/*!< Configures whether or not to enable ledc_ch6_gamma_pause task.\\0: - Disable\\1: Enable */ - __IOM uint32_t TASK_GAMMA_PAUSE_CH7_EN : 1;/*!< Configures whether or not to enable ledc_ch7_gamma_pause task.\\0: - Disable\\1: Enable */ - __IOM uint32_t TASK_GAMMA_RESUME_CH0_EN : 1;/*!< Configures whether or not to enable ledc_ch0_gamma_resume task.\\0: - Disable\\1: Enable */ - __IOM uint32_t TASK_GAMMA_RESUME_CH1_EN : 1;/*!< Configures whether or not to enable ledc_ch1_gamma_resume task.\\0: - Disable\\1: Enable */ - __IOM uint32_t TASK_GAMMA_RESUME_CH2_EN : 1;/*!< Configures whether or not to enable ledc_ch2_gamma_resume task.\\0: - Disable\\1: Enable */ - __IOM uint32_t TASK_GAMMA_RESUME_CH3_EN : 1;/*!< Configures whether or not to enable ledc_ch3_gamma_resume task.\\0: - Disable\\1: Enable */ - __IOM uint32_t TASK_GAMMA_RESUME_CH4_EN : 1;/*!< Configures whether or not to enable ledc_ch4_gamma_resume task.\\0: - Disable\\1: Enable */ - __IOM uint32_t TASK_GAMMA_RESUME_CH5_EN : 1;/*!< Configures whether or not to enable ledc_ch5_gamma_resume task.\\0: - Disable\\1: Enable */ - __IOM uint32_t TASK_GAMMA_RESUME_CH6_EN : 1;/*!< Configures whether or not to enable ledc_ch6_gamma_resume task.\\0: - Disable\\1: Enable */ - __IOM uint32_t TASK_GAMMA_RESUME_CH7_EN : 1;/*!< Configures whether or not to enable ledc_ch7_gamma_resume task.\\0: - Disable\\1: Enable */ - uint32_t : 8; - } bit; - } EVT_TASK_EN2; - __IM uint32_t RESERVED7; - __IOM uint32_t CH3_GAMMA_CONF; /*!< Ledc ch3 gamma config register. */ - __IM uint32_t RESERVED8[3]; - - union { - __IOM uint32_t CH4_CONF0; /*!< Configuration register 0 for channel 4 */ - __IOM uint32_t CH4_GAMMA_CONF; /*!< Ledc ch4 gamma config register. */ - __IOM uint32_t TIMER0_CMP; /*!< Ledc timer0 compare value register. */ - }; - __IOM uint32_t CH4_HPOINT; /*!< High point register for channel 4 */ - __IOM uint32_t CH4_DUTY; /*!< Initial duty cycle register for channel 4 */ - - union { - __IOM uint32_t reg; /*!< Configuration register 1 for channel 4 */ - - struct { - uint32_t : 31; - __IOM uint32_t DUTY_START_CH : 1; /*!< Configures whether the duty cycle fading configurations take - effect.\\0: Not take effect\\1: Take effect */ - } bit; - } CH4_CONF1; - - union { - __IOM uint32_t CH4_DUTY_R; /*!< Current duty cycle register for channel 4 */ - __IOM uint32_t CH5_GAMMA_CONF; /*!< Ledc ch5 gamma config register. */ - __IOM uint32_t TIMER1_CMP; /*!< Ledc timer1 compare value register. */ - __IOM uint32_t TIMER0_CNT_CAP; /*!< Ledc timer0 captured count value register. */ - }; - __IM uint32_t RESERVED9[3]; - - union { - __IOM uint32_t CH6_GAMMA_CONF; /*!< Ledc ch6 gamma config register. */ - __IOM uint32_t TIMER2_CMP; /*!< Ledc timer2 compare value register. */ - __IOM uint32_t TIMER1_CNT_CAP; /*!< Ledc timer1 captured count value register. */ - }; - __IM uint32_t RESERVED10[3]; - - union { - __IOM uint32_t CH7_GAMMA_CONF; /*!< Ledc ch7 gamma config register. */ - __IOM uint32_t TIMER3_CMP; /*!< Ledc timer3 compare value register. */ - __IOM uint32_t TIMER2_CNT_CAP; /*!< Ledc timer2 captured count value register. */ - - union { - __IOM uint32_t reg; /*!< LEDC global configuration register */ - - struct { - __IOM uint32_t APB_CLK_SEL : 2; /*!< Configures the clock source for the four timers.\\0: APB_CLK\\1: - RC_FAST_CLK\\2: XTAL_CLK\\3: Invalid. No clock */ - __IOM uint32_t GAMMA_RAM_CLK_EN_CH0 : 1;/*!< Configures whether or not to open LEDC ch0 gamma ram clock gate.\\0: - Open the clock gate only when application writes or reads - LEDC ch0 gamma ram\\1: Force open the clock gate for LEDC - ch0 gamma ram */ - __IOM uint32_t GAMMA_RAM_CLK_EN_CH1 : 1;/*!< Configures whether or not to open LEDC ch1 gamma ram clock gate.\\0: - Open the clock gate only when application writes or reads - LEDC ch1 gamma ram\\1: Force open the clock gate for LEDC - ch1 gamma ram */ - __IOM uint32_t GAMMA_RAM_CLK_EN_CH2 : 1;/*!< Configures whether or not to open LEDC ch2 gamma ram clock gate.\\0: - Open the clock gate only when application writes or reads - LEDC ch2 gamma ram\\1: Force open the clock gate for LEDC - ch2 gamma ram */ - __IOM uint32_t GAMMA_RAM_CLK_EN_CH3 : 1;/*!< Configures whether or not to open LEDC ch3 gamma ram clock gate.\\0: - Open the clock gate only when application writes or reads - LEDC ch3 gamma ram\\1: Force open the clock gate for LEDC - ch3 gamma ram */ - __IOM uint32_t GAMMA_RAM_CLK_EN_CH4 : 1;/*!< Configures whether or not to open LEDC ch4 gamma ram clock gate.\\0: - Open the clock gate only when application writes or reads - LEDC ch4 gamma ram\\1: Force open the clock gate for LEDC - ch4 gamma ram */ - __IOM uint32_t GAMMA_RAM_CLK_EN_CH5 : 1;/*!< Configures whether or not to open LEDC ch5 gamma ram clock gate.\\0: - Open the clock gate only when application writes or reads - LEDC ch5 gamma ram\\1: Force open the clock gate for LEDC - ch5 gamma ram */ - __IOM uint32_t GAMMA_RAM_CLK_EN_CH6 : 1;/*!< Configures whether or not to open LEDC ch6 gamma ram clock gate.\\0: - Open the clock gate only when application writes or reads - LEDC ch6 gamma ram\\1: Force open the clock gate for LEDC - ch6 gamma ram */ - __IOM uint32_t GAMMA_RAM_CLK_EN_CH7 : 1;/*!< Configures whether or not to open LEDC ch7 gamma ram clock gate.\\0: - Open the clock gate only when application writes or reads - LEDC ch7 gamma ram\\1: Force open the clock gate for LEDC - ch7 gamma ram */ - uint32_t : 21; - __IOM uint32_t CLK_EN : 1; /*!< Configures whether or not to open register clock gate.\\0: Open - the clock gate only when application writes registers\\1: - Force open the clock gate for register */ - } bit; - } CONF; - }; - - union { - __IOM uint32_t reg; /*!< Version control register */ - - struct { - __IOM uint32_t LEDC_DATE : 28; /*!< Configures the version. */ - uint32_t : 4; - } bit; - } DATE; - __IM uint32_t RESERVED11[2]; - __IOM uint32_t TIMER3_CNT_CAP; /*!< Ledc timer3 captured count value register. */ - __IM uint32_t RESERVED12[3]; - __IOM uint32_t CH5_CONF0; /*!< Configuration register 0 for channel 5 */ - __IOM uint32_t CH5_HPOINT; /*!< High point register for channel 5 */ - __IOM uint32_t CH5_DUTY; /*!< Initial duty cycle register for channel 5 */ - - union { - __IOM uint32_t reg; /*!< Configuration register 1 for channel 5 */ - - struct { - uint32_t : 31; - __IOM uint32_t DUTY_START_CH : 1; /*!< Configures whether the duty cycle fading configurations take - effect.\\0: Not take effect\\1: Take effect */ - } bit; - } CH5_CONF1; - __IOM uint32_t CH5_DUTY_R; /*!< Current duty cycle register for channel 5 */ - __IM uint32_t RESERVED13[15]; - __IOM uint32_t CH6_CONF0; /*!< Configuration register 0 for channel 6 */ - __IOM uint32_t CH6_HPOINT; /*!< High point register for channel 6 */ - __IOM uint32_t CH6_DUTY; /*!< Initial duty cycle register for channel 6 */ - - union { - __IOM uint32_t reg; /*!< Configuration register 1 for channel 6 */ - - struct { - uint32_t : 31; - __IOM uint32_t DUTY_START_CH : 1; /*!< Configures whether the duty cycle fading configurations take - effect.\\0: Not take effect\\1: Take effect */ - } bit; - } CH6_CONF1; - __IOM uint32_t CH6_DUTY_R; /*!< Current duty cycle register for channel 6 */ - __IM uint32_t RESERVED14[15]; - __IOM uint32_t CH7_CONF0; /*!< Configuration register 0 for channel 7 */ - __IOM uint32_t CH7_HPOINT; /*!< High point register for channel 7 */ - __IOM uint32_t CH7_DUTY; /*!< Initial duty cycle register for channel 7 */ - - union { - __IOM uint32_t reg; /*!< Configuration register 1 for channel 7 */ - - struct { - uint32_t : 31; - __IOM uint32_t DUTY_START_CH : 1; /*!< Configures whether the duty cycle fading configurations take - effect.\\0: Not take effect\\1: Take effect */ - } bit; - } CH7_CONF1; - __IOM uint32_t CH7_DUTY_R; /*!< Current duty cycle register for channel 7 */ -} LEDC_Type; /*!< Size = 580 (0x244) */ - - - -/* =========================================================================================================================== */ -/* ================ LP_INTR ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Low-power Interrupt Controller (LP_INTR) - */ - -typedef struct { /*!< LP_INTR Structure */ - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 31; - __IOM uint32_t LP_SW_INT_RAW : 1; /*!< need_des */ - } bit; - } SW_INT_RAW; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 31; - __IM uint32_t LP_SW_INT_ST : 1; /*!< need_des */ - } bit; - } SW_INT_ST; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 31; - __IOM uint32_t LP_SW_INT_ENA : 1; /*!< need_des */ - } bit; - } SW_INT_ENA; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 31; - __OM uint32_t LP_SW_INT_CLR : 1; /*!< need_des */ - } bit; - } SW_INT_CLR; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 10; - __IM uint32_t LP_HUK_INTR_ST : 1; /*!< need_des */ - __IM uint32_t SYSREG_INTR_ST : 1; /*!< need_des */ - __IM uint32_t LP_SW_INTR_ST : 1; /*!< need_des */ - __IM uint32_t LP_EFUSE_INTR_ST : 1; /*!< need_des */ - __IM uint32_t LP_UART_INTR_ST : 1; /*!< need_des */ - __IM uint32_t LP_TSENS_INTR_ST : 1; /*!< need_des */ - __IM uint32_t LP_TOUCH_INTR_ST : 1; /*!< need_des */ - __IM uint32_t LP_SPI_INTR_ST : 1; /*!< need_des */ - __IM uint32_t LP_I2S_INTR_ST : 1; /*!< need_des */ - __IM uint32_t LP_I2C_INTR_ST : 1; /*!< need_des */ - __IM uint32_t LP_GPIO_INTR_ST : 1; /*!< need_des */ - __IM uint32_t LP_ADC_INTR_ST : 1; /*!< need_des */ - __IM uint32_t ANAPERI_INTR_ST : 1; /*!< need_des */ - __IM uint32_t PMU_REG_1_INTR_ST : 1; /*!< need_des */ - __IM uint32_t PMU_REG_0_INTR_ST : 1; /*!< need_des */ - __IM uint32_t MB_LP_INTR_ST : 1; /*!< need_des */ - __IM uint32_t MB_HP_INTR_ST : 1; /*!< need_des */ - __IM uint32_t LP_TIMER_REG_1_INTR_ST : 1;/*!< need_des */ - __IM uint32_t LP_TIMER_REG_0_INTR_ST : 1;/*!< need_des */ - __IM uint32_t LP_WDT_INTR_ST : 1; /*!< need_des */ - __IM uint32_t LP_RTC_INTR_ST : 1; /*!< need_des */ - __IM uint32_t HP_INTR_ST : 1; /*!< need_des */ - } bit; - } STATUS; - __IM uint32_t RESERVED[250]; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 31; - __IOM uint32_t CLK_EN : 1; /*!< need_des */ - } bit; - } DATE; -} LP_INTR_Type; /*!< Size = 1024 (0x400) */ - - - -/* =========================================================================================================================== */ -/* ================ LP_PERI ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief LP_PERI Peripheral (LP_PERI) - */ - -typedef struct { /*!< LP_PERI Structure */ - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 16; - __IOM uint32_t CK_EN_RNG : 1; /*!< need_des */ - __IOM uint32_t CK_EN_LP_TSENS : 1; /*!< need_des */ - __IOM uint32_t CK_EN_LP_PMS : 1; /*!< need_des */ - __IOM uint32_t CK_EN_LP_EFUSE : 1; /*!< need_des */ - __IOM uint32_t CK_EN_LP_IOMUX : 1; /*!< need_des */ - __IOM uint32_t CK_EN_LP_TOUCH : 1; /*!< need_des */ - __IOM uint32_t CK_EN_LP_SPI : 1; /*!< need_des */ - __IOM uint32_t CK_EN_LP_ADC : 1; /*!< need_des */ - __IOM uint32_t CK_EN_LP_I2S_TX : 1; /*!< need_des */ - __IOM uint32_t CK_EN_LP_I2S_RX : 1; /*!< need_des */ - __IOM uint32_t CK_EN_LP_I2S : 1; /*!< need_des */ - __IOM uint32_t CK_EN_LP_I2CMST : 1; /*!< need_des */ - __IOM uint32_t CK_EN_LP_I2C : 1; /*!< need_des */ - __IOM uint32_t CK_EN_LP_UART : 1; /*!< need_des */ - __IOM uint32_t CK_EN_LP_INTR : 1; /*!< need_des */ - __IOM uint32_t CK_EN_LP_CORE : 1; /*!< write 1 to force on lp_core clk */ - } bit; - } CLK_EN; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 24; - __IOM uint32_t LP_I2S_TX_CLK_SEL : 2; /*!< need_des */ - __IOM uint32_t LP_I2S_RX_CLK_SEL : 2; /*!< need_des */ - __IOM uint32_t LP_I2C_CLK_SEL : 2; /*!< need_des */ - __IOM uint32_t LP_UART_CLK_SEL : 2; /*!< need_des */ - } bit; - } CORE_CLK_SEL; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 18; - __IOM uint32_t RST_EN_LP_TSENS : 1; /*!< need_des */ - __IOM uint32_t RST_EN_LP_PMS : 1; /*!< need_des */ - __IOM uint32_t RST_EN_LP_EFUSE : 1; /*!< need_des */ - __IOM uint32_t RST_EN_LP_IOMUX : 1; /*!< need_des */ - __IOM uint32_t RST_EN_LP_TOUCH : 1; /*!< need_des */ - __IOM uint32_t RST_EN_LP_SPI : 1; /*!< need_des */ - __IOM uint32_t RST_EN_LP_ADC : 1; /*!< need_des */ - __IOM uint32_t RST_EN_LP_I2S : 1; /*!< need_des */ - __IOM uint32_t RST_EN_LP_I2CMST : 1; /*!< need_des */ - __IOM uint32_t RST_EN_LP_I2C : 1; /*!< need_des */ - __IOM uint32_t RST_EN_LP_UART : 1; /*!< need_des */ - __IOM uint32_t RST_EN_LP_INTR : 1; /*!< need_des */ - __IOM uint32_t RST_EN_LP_ROM : 1; /*!< need_des */ - __OM uint32_t RST_EN_LP_CORE : 1; /*!< need_des */ - } bit; - } RESET_EN; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 31; - __IOM uint32_t LPCORE_DBGM_UNAVAILABLE : 1;/*!< need_des */ - } bit; - } CPU; - __IM uint32_t RESERVED[6]; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __OM uint32_t LP_UART_WAKEUP_FLAG_CLR : 1;/*!< need_des */ - __IOM uint32_t LP_UART_WAKEUP_FLAG : 1; /*!< need_des */ - uint32_t : 27; - __IOM uint32_t LP_UART_WAKEUP_EN : 1; /*!< need_des */ - __IOM uint32_t LP_UART_MEM_FORCE_PD : 1; /*!< need_des */ - __IOM uint32_t LP_UART_MEM_FORCE_PU : 1; /*!< need_des */ - } bit; - } MEM_CTRL; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 6; - __IOM uint32_t SAR2_CLK_FORCE_ON : 1; /*!< need_des */ - __IOM uint32_t SAR1_CLK_FORCE_ON : 1; /*!< need_des */ - __IOM uint32_t LPADC_FUNC_DIV_NUM : 8; /*!< need_des */ - __IOM uint32_t LPADC_SAR2_DIV_NUM : 8; /*!< need_des */ - __IOM uint32_t LPADC_SAR1_DIV_NUM : 8; /*!< need_des */ - } bit; - } ADC_CTRL; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 24; - __IOM uint32_t LP_I2S_RX_CLKM_DIV_NUM : 8;/*!< need_des */ - } bit; - } LP_I2S_RXCLK_DIV_NUM; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 4; - __IOM uint32_t LP_I2S_RX_CLKM_DIV_YN1 : 1;/*!< need_des */ - __IOM uint32_t LP_I2S_RX_CLKM_DIV_Z : 9; /*!< need_des */ - __IOM uint32_t LP_I2S_RX_CLKM_DIV_Y : 9; /*!< need_des */ - __IOM uint32_t LP_I2S_RX_CLKM_DIV_X : 9; /*!< need_des */ - } bit; - } LP_I2S_RXCLK_DIV_XYZ; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 24; - __IOM uint32_t LP_I2S_TX_CLKM_DIV_NUM : 8;/*!< need_des */ - } bit; - } LP_I2S_TXCLK_DIV_NUM; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 4; - __IOM uint32_t LP_I2S_TX_CLKM_DIV_YN1 : 1;/*!< need_des */ - __IOM uint32_t LP_I2S_TX_CLKM_DIV_Z : 9; /*!< need_des */ - __IOM uint32_t LP_I2S_TX_CLKM_DIV_Y : 9; /*!< need_des */ - __IOM uint32_t LP_I2S_TX_CLKM_DIV_X : 9; /*!< need_des */ - } bit; - } LP_I2S_TXCLK_DIV_XYZ; - __IM uint32_t RESERVED1[239]; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 31; - __IOM uint32_t CLK_EN : 1; /*!< need_des */ - } bit; - } DATE; -} LP_PERI_Type; /*!< Size = 1024 (0x400) */ - - - -/* =========================================================================================================================== */ -/* ================ LP_SYS ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief LP_SYS Peripheral (LP_SYS) - */ - -typedef struct { /*!< LP_SYS Structure */ - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t VER_DATE : 32; /*!< need_des */ - } bit; - } LP_SYS_VER_DATE; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 16; - __IOM uint32_t ENA_SW_SEL_SYS_CLK : 1; /*!< reserved */ - __IOM uint32_t SW_SYS_CLK_SRC_SEL : 1; /*!< reserved */ - uint32_t : 14; - } bit; - } CLK_SEL_CTRL; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t LP_CORE_DISABLE : 1; /*!< lp cpu disable */ - __OM uint32_t SYS_SW_RST : 1; /*!< digital system software reset bit */ - __IOM uint32_t FORCE_DOWNLOAD_BOOT : 1; /*!< need_des */ - __IOM uint32_t DIG_FIB : 8; /*!< need_des */ - __IOM uint32_t IO_MUX_RESET_DISABLE : 1; /*!< reset disable bit for LP IOMUX */ - uint32_t : 2; - __IM uint32_t ANA_FIB : 7; /*!< need_des */ - __IOM uint32_t LP_FIB_SEL : 8; /*!< need_des */ - __OM uint32_t LP_CORE_ETM_WAKEUP_FLAG_CLR : 1;/*!< need_des */ - __IOM uint32_t LP_CORE_ETM_WAKEUP_FLAG : 1;/*!< need_des */ - __IOM uint32_t SYSTIMER_STALL_SEL : 1; /*!< 0: use systimer_stall signal from hp_core0, 1: use systimer_stall - signal from hp_core1 */ - } bit; - } SYS_CTRL; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t CLK_EN : 1; /*!< need_des */ - uint32_t : 13; - __IOM uint32_t LP_FOSC_HP_CKEN : 1; /*!< reserved */ - uint32_t : 17; - } bit; - } LP_CLK_CTRL; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t ANA_RST_BYPASS : 1; /*!< analog source reset bypass : wdt,brown out,super wdt,glitch */ - __IOM uint32_t SYS_RST_BYPASS : 1; /*!< system source reset bypass : software reset,hp wdt,lp wdt,efuse */ - __IOM uint32_t EFUSE_FORCE_NORST : 1; /*!< efuse force no reset control */ - uint32_t : 29; - } bit; - } LP_RST_CTRL; - __IM uint32_t RESERVED; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t LP_CPU_BOOT_ADDR : 32; /*!< need_des */ - } bit; - } LP_CORE_BOOT_ADDR; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t SEL : 16; /*!< Bitmap to select RTC pads for ext wakeup1 */ - __OM uint32_t STATUS_CLR : 1; /*!< clear ext wakeup1 status */ - uint32_t : 15; - } bit; - } EXT_WAKEUP1; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IM uint32_t EXT_WAKEUP1_STATUS : 16; /*!< ext wakeup1 status */ - uint32_t : 16; - } bit; - } EXT_WAKEUP1_STATUS; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 5; - __IOM uint32_t LP_TCM_ROM_CLK_FORCE_ON : 1;/*!< need_des */ - uint32_t : 1; - __IOM uint32_t LP_TCM_RAM_CLK_FORCE_ON : 1;/*!< need_des */ - uint32_t : 24; - } bit; - } LP_TCM_PWR_CTRL; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t BOOT_ADDR_HP_LP : 32; /*!< need_des */ - } bit; - } BOOT_ADDR_HP_LP; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t LP_SCRATCH0 : 32; /*!< need_des */ - } bit; - } LP_STORE0; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t LP_SCRATCH1 : 32; /*!< need_des */ - } bit; - } LP_STORE1; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t LP_SCRATCH2 : 32; /*!< need_des */ - } bit; - } LP_STORE2; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t LP_SCRATCH3 : 32; /*!< need_des */ - } bit; - } LP_STORE3; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t LP_SCRATCH4 : 32; /*!< need_des */ - } bit; - } LP_STORE4; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t LP_SCRATCH5 : 32; /*!< need_des */ - } bit; - } LP_STORE5; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t LP_SCRATCH6 : 32; /*!< need_des */ - } bit; - } LP_STORE6; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t LP_SCRATCH7 : 32; /*!< need_des */ - } bit; - } LP_STORE7; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t LP_SCRATCH8 : 32; /*!< need_des */ - } bit; - } LP_STORE8; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t LP_SCRATCH9 : 32; /*!< need_des */ - } bit; - } LP_STORE9; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t LP_SCRATCH10 : 32; /*!< need_des */ - } bit; - } LP_STORE10; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t LP_SCRATCH11 : 32; /*!< need_des */ - } bit; - } LP_STORE11; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t LP_SCRATCH12 : 32; /*!< need_des */ - } bit; - } LP_STORE12; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t LP_SCRATCH13 : 32; /*!< need_des */ - } bit; - } LP_STORE13; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t LP_SCRATCH14 : 32; /*!< need_des */ - } bit; - } LP_STORE14; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t LP_SCRATCH15 : 32; /*!< need_des */ - } bit; - } LP_STORE15; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t PROBE_A_MOD_SEL : 16; /*!< need_des */ - __IOM uint32_t PROBE_A_TOP_SEL : 8; /*!< need_des */ - __IOM uint32_t PROBE_L_SEL : 2; /*!< need_des */ - __IOM uint32_t PROBE_H_SEL : 2; /*!< need_des */ - __IOM uint32_t PROBE_GLOBAL_EN : 1; /*!< need_des */ - uint32_t : 3; - } bit; - } LP_PROBEA_CTRL; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t PROBE_B_MOD_SEL : 16; /*!< need_des */ - __IOM uint32_t PROBE_B_TOP_SEL : 8; /*!< need_des */ - __IOM uint32_t PROBE_B_EN : 1; /*!< need_des */ - uint32_t : 7; - } bit; - } LP_PROBEB_CTRL; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IM uint32_t PROBE_TOP_OUT : 32; /*!< need_des */ - } bit; - } LP_PROBE_OUT; - __IM uint32_t RESERVED1[9]; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t F2S_APB_POSTW_EN : 1; /*!< reserved */ - uint32_t : 31; - } bit; - } F2S_APB_BRG_CNTL; - __IM uint32_t RESERVED2[24]; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t SW_HW_USB_PHY_SEL : 1; /*!< need_des */ - __IOM uint32_t SW_USB_PHY_SEL : 1; /*!< need_des */ - __OM uint32_t USBOTG20_WAKEUP_CLR : 1; /*!< clear usb wakeup to PMU. */ - __IOM uint32_t USBOTG20_IN_SUSPEND : 1; /*!< indicate usb otg2.0 is in suspend state. */ - uint32_t : 28; - } bit; - } USB_CTRL; - __IM uint32_t RESERVED3[2]; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t ANA_REG_XPD_PAD_GROUP : 8; /*!< Set 1 to power up pad group */ - uint32_t : 24; - } bit; - } ANA_XPD_PAD_GROUP; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t LP_TCM_RAM_RDN_ECO_EN : 1; /*!< need_des */ - __IM uint32_t LP_TCM_RAM_RDN_ECO_RESULT : 1;/*!< need_des */ - uint32_t : 30; - } bit; - } LP_TCM_RAM_RDN_ECO_CS; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t LP_TCM_RAM_RDN_ECO_LOW : 32;/*!< need_des */ - } bit; - } LP_TCM_RAM_RDN_ECO_LOW; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t LP_TCM_RAM_RDN_ECO_HIGH : 32;/*!< need_des */ - } bit; - } LP_TCM_RAM_RDN_ECO_HIGH; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t LP_TCM_ROM_RDN_ECO_EN : 1; /*!< need_des */ - __IM uint32_t LP_TCM_ROM_RDN_ECO_RESULT : 1;/*!< need_des */ - uint32_t : 30; - } bit; - } LP_TCM_ROM_RDN_ECO_CS; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t LP_TCM_ROM_RDN_ECO_LOW : 32;/*!< need_des */ - } bit; - } LP_TCM_ROM_RDN_ECO_LOW; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t LP_TCM_ROM_RDN_ECO_HIGH : 32;/*!< need_des */ - } bit; - } LP_TCM_ROM_RDN_ECO_HIGH; - __IM uint32_t RESERVED4[2]; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t CPU_CLK_EN : 1; /*!< clock gate enable for hp cpu root 400M clk */ - __IOM uint32_t SYS_CLK_EN : 1; /*!< clock gate enable for hp sys root 480M clk */ - uint32_t : 30; - } bit; - } HP_ROOT_CLK_CTRL; - __IM uint32_t RESERVED5; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t PMU_RDN_ECO_LOW : 32; /*!< need_des */ - } bit; - } LP_PMU_RDN_ECO_LOW; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t PMU_RDN_ECO_HIGH : 32; /*!< need_des */ - } bit; - } LP_PMU_RDN_ECO_HIGH; - __IM uint32_t RESERVED6[2]; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t DREF_COMP0 : 3; /*!< pad comp dref */ - __IOM uint32_t MODE_COMP0 : 1; /*!< pad comp mode */ - __IOM uint32_t XPD_COMP0 : 1; /*!< pad comp xpd */ - uint32_t : 27; - } bit; - } PAD_COMP0; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t DREF_COMP1 : 3; /*!< pad comp dref */ - __IOM uint32_t MODE_COMP1 : 1; /*!< pad comp mode */ - __IOM uint32_t XPD_COMP1 : 1; /*!< pad comp xpd */ - uint32_t : 27; - } bit; - } PAD_COMP1; - __IM uint32_t RESERVED7; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t BURST_LIMIT_AON : 5; /*!< need_des */ - __IOM uint32_t READ_INTERVAL_AON : 7; /*!< need_des */ - __IOM uint32_t LINK_BACKUP_TOUT_THRES_AON : 10;/*!< need_des */ - __IOM uint32_t LINK_TOUT_THRES_AON : 10; /*!< need_des */ - } bit; - } BACKUP_DMA_CFG0; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 31; - __IOM uint32_t AON_BYPASS : 1; /*!< need_des */ - } bit; - } BACKUP_DMA_CFG1; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t LINK_ADDR_AON : 32; /*!< need_des */ - } bit; - } BACKUP_DMA_CFG2; - __IM uint32_t RESERVED8; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t BOOT_ADDR_HP_CORE1 : 32; /*!< need_des */ - } bit; - } BOOT_ADDR_HP_CORE1; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IM uint32_t LP_ADDRHOLE_ADDR : 32; /*!< need_des */ - } bit; - } LP_ADDRHOLE_ADDR; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IM uint32_t LP_ADDRHOLE_ID : 5; /*!< master id: 5'h0: hp core0, 5'h1:hp core1, 5'h2:lp core, 5'h3:usb - otg11, 5'h4: regdma, 5'h5: gmac, 5'h5 sdmmc, 5'h7: usbotg20, - 5'h8: trace0, 5'h9: trace1, 5'ha tcm monitor, 5'hb: l2mem - monitor. 5'h10~5'h1f: ahb pdma. */ - __IM uint32_t LP_ADDRHOLE_WR : 1; /*!< 1:write trans, 0: read trans. */ - __IM uint32_t LP_ADDRHOLE_SECURE : 1; /*!< 1: illegal address access, 0: access without permission */ - uint32_t : 25; - } bit; - } LP_ADDRHOLE_INFO; - - union { - __IOM uint32_t reg; /*!< raw interrupt register */ - - struct { - __IM uint32_t LP_ADDRHOLE_INT_RAW : 1; /*!< the raw interrupt status of lp addrhole(for lp peri and lp ram - tee apm, and lp matrix default slave) */ - __IM uint32_t IDBUS_ADDRHOLE_INT_RAW : 1;/*!< the raw interrupt status of idbus addrhole(only for lp cpu ibus - and dbus) */ - __IM uint32_t LP_CORE_AHB_TIMEOUT_INT_RAW : 1;/*!< the raw interrupt status of lp core ahb bus timeout */ - __IM uint32_t LP_CORE_IBUS_TIMEOUT_INT_RAW : 1;/*!< the raw interrupt status of lp core ibus timeout */ - __IM uint32_t LP_CORE_DBUS_TIMEOUT_INT_RAW : 1;/*!< the raw interrupt status of lp core dbus timeout */ - __IM uint32_t ETM_TASK_ULP_INT_RAW : 1; /*!< the raw interrupt status of etm task ulp */ - __IM uint32_t SLOW_CLK_TICK_INT_RAW : 1; /*!< the raw interrupt status of slow_clk_tick */ - uint32_t : 25; - } bit; - } INT_RAW; - - union { - __IOM uint32_t reg; /*!< masked interrupt register */ - - struct { - __IM uint32_t LP_ADDRHOLE_INT_ST : 1; /*!< the masked interrupt status of lp addrhole (for lp peri and - lp ram tee apm, and lp matrix default slave) */ - __IM uint32_t IDBUS_ADDRHOLE_INT_ST : 1; /*!< the masked interrupt status of idbus addrhole(only for lp cpu - ibus and dbus) */ - __IM uint32_t LP_CORE_AHB_TIMEOUT_INT_ST : 1;/*!< the masked interrupt status of lp core ahb bus timeout */ - __IM uint32_t LP_CORE_IBUS_TIMEOUT_INT_ST : 1;/*!< the masked interrupt status of lp core ibus timeout */ - __IM uint32_t LP_CORE_DBUS_TIMEOUT_INT_ST : 1;/*!< the masked interrupt status of lp core dbus timeout */ - __IM uint32_t ETM_TASK_ULP_INT_ST : 1; /*!< the masked interrupt status of etm task ulp */ - __IM uint32_t SLOW_CLK_TICK_INT_ST : 1; /*!< the masked interrupt status of slow_clk_tick */ - uint32_t : 25; - } bit; - } INT_ST; - - union { - __IOM uint32_t reg; /*!< masked interrupt register */ - - struct { - __IOM uint32_t LP_ADDRHOLE_INT_ENA : 1; /*!< Write 1 to enable lp addrhole int */ - __IOM uint32_t IDBUS_ADDRHOLE_INT_ENA : 1;/*!< Write 1 to enable idbus addrhole int */ - __IOM uint32_t LP_CORE_AHB_TIMEOUT_INT_ENA : 1;/*!< Write 1 to enable lp_core_ahb_timeout int */ - __IOM uint32_t LP_CORE_IBUS_TIMEOUT_INT_ENA : 1;/*!< Write 1 to enable lp_core_ibus_timeout int */ - __IOM uint32_t LP_CORE_DBUS_TIMEOUT_INT_ENA : 1;/*!< Write 1 to enable lp_core_dbus_timeout int */ - __IOM uint32_t ETM_TASK_ULP_INT_ENA : 1; /*!< Write 1 to enable etm task ulp int */ - __IOM uint32_t SLOW_CLK_TICK_INT_ENA : 1; /*!< Write 1 to enable slow_clk_tick int */ - uint32_t : 25; - } bit; - } INT_ENA; - - union { - __IOM uint32_t reg; /*!< interrupt clear register */ - - struct { - __OM uint32_t LP_ADDRHOLE_INT_CLR : 1; /*!< write 1 to clear lp addrhole int */ - __OM uint32_t IDBUS_ADDRHOLE_INT_CLR : 1;/*!< write 1 to clear idbus addrhole int */ - __OM uint32_t LP_CORE_AHB_TIMEOUT_INT_CLR : 1;/*!< Write 1 to clear lp_core_ahb_timeout int */ - __OM uint32_t LP_CORE_IBUS_TIMEOUT_INT_CLR : 1;/*!< Write 1 to clear lp_core_ibus_timeout int */ - __OM uint32_t LP_CORE_DBUS_TIMEOUT_INT_CLR : 1;/*!< Write 1 to clear lp_core_dbus_timeout int */ - __OM uint32_t ETM_TASK_ULP_INT_CLR : 1; /*!< Write 1 to clear etm tasl ulp int */ - __OM uint32_t SLOW_CLK_TICK_INT_CLR : 1; /*!< Write 1 to clear slow_clk_tick int */ - uint32_t : 25; - } bit; - } INT_CLR; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t HP_MEM_AUX_CTRL : 32; /*!< need_des */ - } bit; - } HP_MEM_AUX_CTRL; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t LP_MEM_AUX_CTRL : 32; /*!< need_des */ - } bit; - } LP_MEM_AUX_CTRL; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t HP_ROM_AUX_CTRL : 32; /*!< need_des */ - } bit; - } HP_ROM_AUX_CTRL; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t LP_ROM_AUX_CTRL : 32; /*!< need_des */ - } bit; - } LP_ROM_AUX_CTRL; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IM uint32_t LP_CPU_DBG_PC : 32; /*!< need_des */ - } bit; - } LP_CPU_DBG_PC; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IM uint32_t LP_CPU_EXC_PC : 32; /*!< need_des */ - } bit; - } LP_CPU_EXC_PC; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IM uint32_t IDBUS_ADDRHOLE_ADDR : 32; /*!< need_des */ - } bit; - } IDBUS_ADDRHOLE_ADDR; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IM uint32_t IDBUS_ADDRHOLE_ID : 5; /*!< need_des */ - __IM uint32_t IDBUS_ADDRHOLE_WR : 1; /*!< need_des */ - __IM uint32_t IDBUS_ADDRHOLE_SECURE : 1; /*!< need_des */ - uint32_t : 25; - } bit; - } IDBUS_ADDRHOLE_INFO; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 8; - __IOM uint32_t HP_PO_CNNT_RSTN_BYPASS_CTRL : 8;/*!< [15] 1'b1: po_cnnt_rstn bypass sys_sw_rstn[14] 1'b1: po_cnnt_rstn - bypass hp_wdt_sys_rstn[13] 1'b1: po_cnnt_rstn bypass hp_cpu_intrusion_rst - [12] 1'b1: po_cnnt_rstn bypass hp_sdio_sys_rstn[11] 1'b1: - po_cnnt_rstn bypass usb_jtag_chip_rst[10] 1'b1: po_cnnt_rstn - bypass usb_uart_chip_rst[9] 1'b1: po_cnnt_rstn bypass lp_wdt_hp_sys_rstn[ - ] 1'b1: po_cnnt_rstn bypass efuse_err_rstn */ - uint32_t : 8; - __IOM uint32_t HP_PO_RSTN_BYPASS_CTRL : 8;/*!< [31] 1'b1: po_rstn bypass sys_sw_rstn[30] 1'b1: po_rstn bypass - hp_wdt_sys_rstn[29] 1'b1: po_rstn bypass hp_cpu_intrusion_rstn[28] - 1'b1: po_rstn bypass hp_sdio_sys_rstn[27] 1'b1: po_rstn - bypass usb_jtag_chip_rst[26] 1'b1: po_rstn bypass usb_uart_chip_rst[25] - 1'b1: po_rstn bypass lp_wdt_hp_sys_rstn[24] 1'b1: po_rstn - bypass efuse_err_rstn */ - } bit; - } HP_POR_RST_BYPASS_CTRL; - - union { - __IOM uint32_t reg; /*!< rng data register */ - - struct { - __IM uint32_t RND_DATA : 32; /*!< result of rng output */ - } bit; - } RNG_DATA; - __IM uint32_t RESERVED9[2]; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t EN : 1; /*!< set this field to 1 to enable lp core ahb timeout handle */ - __IOM uint32_t THRES : 16; /*!< This field used to set lp core ahb bus timeout threshold */ - __IOM uint32_t LP2HP_AHB_TIMEOUT_EN : 1; /*!< set this field to 1 to enable lp2hp ahb timeout handle */ - __IOM uint32_t LP2HP_AHB_TIMEOUT_THRES : 5;/*!< This field used to set lp2hp ahb bus timeout threshold */ - uint32_t : 9; - } bit; - } LP_CORE_AHB_TIMEOUT; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t EN : 1; /*!< set this field to 1 to enable lp core ibus timeout handle */ - __IOM uint32_t THRES : 16; /*!< This field used to set lp core ibus timeout threshold */ - uint32_t : 15; - } bit; - } LP_CORE_IBUS_TIMEOUT; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t EN : 1; /*!< set this field to 1 to enable lp core dbus timeout handle */ - __IOM uint32_t THRES : 16; /*!< This field used to set lp core dbus timeout threshold */ - uint32_t : 15; - } bit; - } LP_CORE_DBUS_TIMEOUT; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t LP_CORE_ERR_RESP_DIS : 3; /*!< Set bit0 to disable ibus err resp;Set bit1 to disable dbus err - resp; Set bit 2 to disable ahb err resp. */ - uint32_t : 29; - } bit; - } LP_CORE_ERR_RESP_DIS; - - union { - __IOM uint32_t reg; /*!< rng cfg register */ - - struct { - __IOM uint32_t RNG_TIMER_EN : 1; /*!< enable rng timer */ - __IOM uint32_t RNG_TIMER_PSCALE : 8; /*!< configure ng timer pscale */ - __IOM uint32_t RNG_SAR_ENABLE : 1; /*!< enable rng_saradc */ - uint32_t : 6; - __IM uint32_t RNG_SAR_DATA : 13; /*!< debug rng sar sample cnt */ - uint32_t : 3; - } bit; - } RNG_CFG; -} LP_SYS_Type; /*!< Size = 452 (0x1c4) */ - - - -/* =========================================================================================================================== */ -/* ================ LP_ANA_PERI ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief LP_ANA_PERI Peripheral (LP_ANA_PERI) - */ - -typedef struct { /*!< LP_ANA_PERI Structure */ - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 6; - __IOM uint32_t LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA : 1;/*!< need_des */ - __IOM uint32_t LP_ANA_BOD_MODE0_PD_RF_ENA : 1;/*!< need_des */ - __IOM uint32_t LP_ANA_BOD_MODE0_INTR_WAIT : 10;/*!< need_des */ - __IOM uint32_t LP_ANA_BOD_MODE0_RESET_WAIT : 10;/*!< need_des */ - __IOM uint32_t LP_ANA_BOD_MODE0_CNT_CLR : 1;/*!< need_des */ - __IOM uint32_t LP_ANA_BOD_MODE0_INTR_ENA : 1;/*!< need_des */ - __IOM uint32_t LP_ANA_BOD_MODE0_RESET_SEL : 1;/*!< need_des */ - __IOM uint32_t LP_ANA_BOD_MODE0_RESET_ENA : 1;/*!< need_des */ - } bit; - } LP_ANA_BOD_MODE0_CNTL; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 31; - __IOM uint32_t LP_ANA_BOD_MODE1_RESET_ENA : 1;/*!< need_des */ - } bit; - } LP_ANA_BOD_MODE1_CNTL; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t LP_ANA_DETMODE_SEL : 8; /*!< need_des */ - __IM uint32_t LP_ANA_VGOOD_EVENT_RECORD : 8;/*!< need_des */ - __OM uint32_t LP_ANA_VBAT_EVENT_RECORD_CLR : 8;/*!< need_des */ - __IOM uint32_t LP_ANA_BOD_SOURCE_ENA : 8; /*!< need_des */ - } bit; - } LP_ANA_VDD_SOURCE_CNTL; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IM uint32_t LP_ANA_VDDBAT_UNDERVOLTAGE_FLAG : 1;/*!< need_des */ - uint32_t : 9; - __IOM uint32_t LP_ANA_VDDBAT_CHARGER : 1; /*!< need_des */ - __IOM uint32_t LP_ANA_VDDBAT_CNT_CLR : 1; /*!< need_des */ - __IOM uint32_t LP_ANA_VDDBAT_UPVOLTAGE_TARGET : 10;/*!< need_des */ - __IOM uint32_t LP_ANA_VDDBAT_UNDERVOLTAGE_TARGET : 10;/*!< need_des */ - } bit; - } LP_ANA_VDDBAT_BOD_CNTL; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IM uint32_t LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG : 1;/*!< need_des */ - uint32_t : 9; - __IOM uint32_t LP_ANA_VDDBAT_CHARGE_CHARGER : 1;/*!< need_des */ - __IOM uint32_t LP_ANA_VDDBAT_CHARGE_CNT_CLR : 1;/*!< need_des */ - __IOM uint32_t LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_TARGET : 10;/*!< need_des */ - __IOM uint32_t LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET : 10;/*!< need_des */ - } bit; - } LP_ANA_VDDBAT_CHARGE_CNTL; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 31; - __IOM uint32_t LP_ANA_CK_GLITCH_RESET_ENA : 1;/*!< need_des */ - } bit; - } LP_ANA_CK_GLITCH_CNTL; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 31; - __IOM uint32_t LP_ANA_POWER_GLITCH_RESET_ENA : 1;/*!< need_des */ - } bit; - } LP_ANA_PG_GLITCH_CNTL; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t LP_ANA_ANA_FIB_ENA : 32; /*!< need_des */ - } bit; - } LP_ANA_FIB_ENABLE; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 27; - __IOM uint32_t LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW : 1;/*!< need_des */ - __IOM uint32_t LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW : 1;/*!< need_des */ - __IOM uint32_t LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW : 1;/*!< need_des */ - __IOM uint32_t LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW : 1;/*!< need_des */ - __IOM uint32_t LP_ANA_BOD_MODE0_INT_RAW : 1;/*!< need_des */ - } bit; - } LP_ANA_INT_RAW; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 27; - __IM uint32_t LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ST : 1;/*!< need_des */ - __IM uint32_t LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST : 1;/*!< need_des */ - __IM uint32_t LP_ANA_VDDBAT_UPVOLTAGE_INT_ST : 1;/*!< need_des */ - __IM uint32_t LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ST : 1;/*!< need_des */ - __IM uint32_t LP_ANA_BOD_MODE0_INT_ST : 1;/*!< need_des */ - } bit; - } LP_ANA_INT_ST; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 27; - __IOM uint32_t LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA : 1;/*!< need_des */ - __IOM uint32_t LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA : 1;/*!< need_des */ - __IOM uint32_t LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA : 1;/*!< need_des */ - __IOM uint32_t LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA : 1;/*!< need_des */ - __IOM uint32_t LP_ANA_BOD_MODE0_INT_ENA : 1;/*!< need_des */ - } bit; - } LP_ANA_INT_ENA; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 27; - __OM uint32_t LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR : 1;/*!< need_des */ - __OM uint32_t LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR : 1;/*!< need_des */ - __OM uint32_t LP_ANA_VDDBAT_UPVOLTAGE_INT_CLR : 1;/*!< need_des */ - __OM uint32_t LP_ANA_VDDBAT_UNDERVOLTAGE_INT_CLR : 1;/*!< need_des */ - __OM uint32_t LP_ANA_BOD_MODE0_INT_CLR : 1;/*!< need_des */ - } bit; - } LP_ANA_INT_CLR; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 31; - __IOM uint32_t LP_ANA_BOD_MODE0_LP_INT_RAW : 1;/*!< need_des */ - } bit; - } LP_ANA_LP_INT_RAW; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 31; - __IM uint32_t LP_ANA_BOD_MODE0_LP_INT_ST : 1;/*!< need_des */ - } bit; - } LP_ANA_LP_INT_ST; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 31; - __IOM uint32_t LP_ANA_BOD_MODE0_LP_INT_ENA : 1;/*!< need_des */ - } bit; - } LP_ANA_LP_INT_ENA; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 31; - __OM uint32_t LP_ANA_BOD_MODE0_LP_INT_CLR : 1;/*!< need_des */ - } bit; - } LP_ANA_LP_INT_CLR; - __IM uint32_t RESERVED[47]; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t LP_ANA_TOUCH_APPROACH_MEAS_NUM2 : 10;/*!< need_des */ - __IOM uint32_t LP_ANA_TOUCH_APPROACH_MEAS_NUM1 : 10;/*!< need_des */ - __IOM uint32_t LP_ANA_TOUCH_APPROACH_MEAS_NUM0 : 10;/*!< need_des */ - uint32_t : 2; - } bit; - } LP_ANA_TOUCH_APPROACH_WORK_MEAS_NUM; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t LP_ANA_TOUCH_SHIELD_PAD_EN : 1;/*!< need_des */ - __IOM uint32_t LP_ANA_TOUCH_INACTIVE_CONNECTION : 1;/*!< need_des */ - __IOM uint32_t LP_ANA_TOUCH_SCAN_PAD_MAP : 15;/*!< need_des */ - __IOM uint32_t LP_ANA_TOUCH_XPD_WAIT : 15;/*!< need_des */ - } bit; - } LP_ANA_TOUCH_SCAN_CTRL1; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 6; - __IOM uint32_t LP_ANA_TOUCH_TIMEOUT_NUM : 16;/*!< need_des */ - __IOM uint32_t LP_ANA_TOUCH_TIMEOUT_EN : 1;/*!< need_des */ - __IOM uint32_t LP_ANA_TOUCH_OUT_RING : 4; /*!< need_des */ - __IOM uint32_t LP_ANA_FREQ_SCAN_EN : 1; /*!< need_des */ - __IOM uint32_t LP_ANA_FREQ_SCAN_CNT_LIMIT : 2;/*!< need_des */ - uint32_t : 2; - } bit; - } LP_ANA_TOUCH_SCAN_CTRL2; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 16; - __IOM uint32_t LP_ANA_DIV_NUM2 : 3; /*!< need_des */ - __IOM uint32_t LP_ANA_DIV_NUM1 : 3; /*!< need_des */ - __IOM uint32_t LP_ANA_DIV_NUM0 : 3; /*!< need_des */ - __IOM uint32_t LP_ANA_TOUCH_OUT_SEL : 1; /*!< need_des */ - __OM uint32_t LP_ANA_TOUCH_OUT_RESET : 1;/*!< need_des */ - __IOM uint32_t LP_ANA_TOUCH_OUT_GATE : 1; /*!< need_des */ - uint32_t : 4; - } bit; - } LP_ANA_TOUCH_WORK; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t LP_ANA_TOUCH_MEAS_NUM2 : 10;/*!< need_des */ - __IOM uint32_t LP_ANA_TOUCH_MEAS_NUM1 : 10;/*!< need_des */ - __IOM uint32_t LP_ANA_TOUCH_MEAS_NUM0 : 10;/*!< need_des */ - uint32_t : 2; - } bit; - } LP_ANA_TOUCH_WORK_MEAS_NUM; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t LP_ANA_TOUCH_NEG_NOISE_DISUPDATE_BASELINE_EN : 1;/*!< Reserved */ - __IOM uint32_t LP_ANA_TOUCH_HYSTERESIS : 2;/*!< need_des */ - __IOM uint32_t LP_ANA_TOUCH_NEG_NOISE_THRES : 2;/*!< need_des */ - __IOM uint32_t LP_ANA_TOUCH_NOISE_THRES : 2;/*!< need_des */ - __IOM uint32_t LP_ANA_TOUCH_SMOOTH_LVL : 2;/*!< need_des */ - __IOM uint32_t LP_ANA_TOUCH_JITTER_STEP : 4;/*!< need_des */ - __IOM uint32_t LP_ANA_TOUCH_FILTER_MODE : 3;/*!< need_des */ - __IOM uint32_t LP_ANA_TOUCH_FILTER_EN : 1;/*!< need_des */ - __IOM uint32_t LP_ANA_TOUCH_NEG_NOISE_LIMIT : 4;/*!< need_des */ - __IOM uint32_t LP_ANA_TOUCH_APPROACH_LIMIT : 8;/*!< need_des */ - __IOM uint32_t LP_ANA_TOUCH_DEBOUNCE_LIMIT : 3;/*!< need_des */ - } bit; - } LP_ANA_TOUCH_FILTER1; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 15; - __IOM uint32_t LP_ANA_TOUCH_OUTEN : 15; /*!< need_des */ - __IOM uint32_t LP_ANA_TOUCH_BYPASS_NOISE_THRES : 1;/*!< need_des */ - __IOM uint32_t LP_ANA_TOUCH_BYPASS_NEG_NOISE_THRES : 1;/*!< need_des */ - } bit; - } LP_ANA_TOUCH_FILTER2; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t LP_ANA_TOUCH_BASELINE_SW : 16;/*!< need_des */ - __OM uint32_t LP_ANA_TOUCH_UPDATE_BASELINE_SW : 1;/*!< need_des */ - uint32_t : 15; - } bit; - } LP_ANA_TOUCH_FILTER3; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t LP_ANA_TOUCH_SLP_TH0 : 16; /*!< need_des */ - __OM uint32_t LP_ANA_TOUCH_SLP_CHANNEL_CLR : 1;/*!< need_des */ - __IOM uint32_t LP_ANA_TOUCH_SLP_PAD : 4; /*!< need_des */ - uint32_t : 11; - } bit; - } LP_ANA_TOUCH_SLP0; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t LP_ANA_TOUCH_SLP_TH2 : 16; /*!< need_des */ - __IOM uint32_t LP_ANA_TOUCH_SLP_TH1 : 16; /*!< need_des */ - } bit; - } LP_ANA_TOUCH_SLP1; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __OM uint32_t LP_ANA_TOUCH_CHANNEL_CLR : 15;/*!< need_des */ - __OM uint32_t LP_ANA_TOUCH_STATUS_CLR : 1;/*!< need_des */ - uint32_t : 16; - } bit; - } LP_ANA_TOUCH_CLR; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t PAD0 : 4; /*!< need_des */ - __IOM uint32_t PAD1 : 4; /*!< need_des */ - __IOM uint32_t PAD2 : 4; /*!< need_des */ - __IOM uint32_t LP_ANA_TOUCH_SLP_APPROACH_EN : 1;/*!< need_des */ - uint32_t : 19; - } bit; - } LP_ANA_TOUCH_APPROACH; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t LP_ANA_TOUCH_FREQ0_DCAP_LPF : 7;/*!< need_des */ - __IOM uint32_t LP_ANA_TOUCH_FREQ0_DRES_LPF : 2;/*!< need_des */ - __IOM uint32_t LP_ANA_TOUCH_FREQ0_DRV_LS : 4;/*!< need_des */ - __IOM uint32_t LP_ANA_TOUCH_FREQ0_DRV_HS : 5;/*!< need_des */ - __IOM uint32_t LP_ANA_TOUCH_FREQ0_DBIAS : 5;/*!< need_des */ - uint32_t : 9; - } bit; - } LP_ANA_TOUCH_FREQ0_SCAN_PARA; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t LP_ANA_TOUCH_FREQ1_DCAP_LPF : 7;/*!< need_des */ - __IOM uint32_t LP_ANA_TOUCH_FREQ1_DRES_LPF : 2;/*!< need_des */ - __IOM uint32_t LP_ANA_TOUCH_FREQ1_DRV_LS : 4;/*!< need_des */ - __IOM uint32_t LP_ANA_TOUCH_FREQ1_DRV_HS : 5;/*!< need_des */ - __IOM uint32_t LP_ANA_TOUCH_FREQ1_DBIAS : 5;/*!< need_des */ - uint32_t : 9; - } bit; - } LP_ANA_TOUCH_FREQ1_SCAN_PARA; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t LP_ANA_TOUCH_FREQ2_DCAP_LPF : 7;/*!< need_des */ - __IOM uint32_t LP_ANA_TOUCH_FREQ2_DRES_LPF : 2;/*!< need_des */ - __IOM uint32_t LP_ANA_TOUCH_FREQ2_DRV_LS : 4;/*!< need_des */ - __IOM uint32_t LP_ANA_TOUCH_FREQ2_DRV_HS : 5;/*!< need_des */ - __IOM uint32_t LP_ANA_TOUCH_FREQ2_DBIAS : 5;/*!< need_des */ - uint32_t : 9; - } bit; - } LP_ANA_TOUCH_FREQ2_SCAN_PARA; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t LP_ANA_TOUCH_TOUCH_BUF_DRV : 3;/*!< need_des */ - __IOM uint32_t LP_ANA_TOUCH_TOUCH_EN_CAL : 1;/*!< need_des */ - __IOM uint32_t LP_ANA_TOUCH_TOUCH_DCAP_CAL : 7;/*!< need_des */ - uint32_t : 21; - } bit; - } LP_ANA_TOUCH_ANA_PARA; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 8; - __IOM uint32_t LP_ANA_TOUCH_DATA_SEL : 2; /*!< need_des */ - __IOM uint32_t LP_ANA_TOUCH_FREQ_SEL : 2; /*!< need_des */ - __IOM uint32_t LP_ANA_TOUCH_BUFSEL : 15; /*!< need_des */ - __IOM uint32_t LP_ANA_TOUCH_DONE_EN : 1; /*!< need_des */ - __IOM uint32_t LP_ANA_TOUCH_DONE_FORCE : 1;/*!< need_des */ - __IOM uint32_t LP_ANA_TOUCH_FSM_EN : 1; /*!< need_des */ - __IOM uint32_t LP_ANA_TOUCH_START_EN : 1; /*!< need_des */ - __IOM uint32_t LP_ANA_TOUCH_START_FORCE : 1;/*!< need_des */ - } bit; - } LP_ANA_TOUCH_MUX0; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t LP_ANA_TOUCH_START : 15; /*!< need_des */ - __IOM uint32_t LP_ANA_TOUCH_XPD : 15; /*!< need_des */ - uint32_t : 2; - } bit; - } LP_ANA_TOUCH_MUX1; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 16; - __IOM uint32_t LP_ANA_TOUCH_PAD0_TH0 : 16;/*!< Reserved */ - } bit; - } LP_ANA_TOUCH_PAD0_TH0; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 16; - __IOM uint32_t LP_ANA_TOUCH_PAD0_TH1 : 16;/*!< Reserved */ - } bit; - } LP_ANA_TOUCH_PAD0_TH1; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 16; - __IOM uint32_t LP_ANA_TOUCH_PAD0_TH2 : 16;/*!< Reserved */ - } bit; - } LP_ANA_TOUCH_PAD0_TH2; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 16; - __IOM uint32_t LP_ANA_TOUCH_PAD1_TH0 : 16;/*!< Reserved */ - } bit; - } LP_ANA_TOUCH_PAD1_TH0; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 16; - __IOM uint32_t LP_ANA_TOUCH_PAD1_TH1 : 16;/*!< Reserved */ - } bit; - } LP_ANA_TOUCH_PAD1_TH1; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 16; - __IOM uint32_t LP_ANA_TOUCH_PAD1_TH2 : 16;/*!< Reserved */ - } bit; - } LP_ANA_TOUCH_PAD1_TH2; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 16; - __IOM uint32_t LP_ANA_TOUCH_PAD2_TH0 : 16;/*!< Reserved */ - } bit; - } LP_ANA_TOUCH_PAD2_TH0; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 16; - __IOM uint32_t LP_ANA_TOUCH_PAD2_TH1 : 16;/*!< Reserved */ - } bit; - } LP_ANA_TOUCH_PAD2_TH1; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 16; - __IOM uint32_t LP_ANA_TOUCH_PAD2_TH2 : 16;/*!< Reserved */ - } bit; - } LP_ANA_TOUCH_PAD2_TH2; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 16; - __IOM uint32_t LP_ANA_TOUCH_PAD3_TH0 : 16;/*!< Reserved */ - } bit; - } LP_ANA_TOUCH_PAD3_TH0; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 16; - __IOM uint32_t LP_ANA_TOUCH_PAD3_TH1 : 16;/*!< Reserved */ - } bit; - } LP_ANA_TOUCH_PAD3_TH1; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 16; - __IOM uint32_t LP_ANA_TOUCH_PAD3_TH2 : 16;/*!< Reserved */ - } bit; - } LP_ANA_TOUCH_PAD3_TH2; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 16; - __IOM uint32_t LP_ANA_TOUCH_PAD4_TH0 : 16;/*!< Reserved */ - } bit; - } LP_ANA_TOUCH_PAD4_TH0; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 16; - __IOM uint32_t LP_ANA_TOUCH_PAD4_TH1 : 16;/*!< Reserved */ - } bit; - } LP_ANA_TOUCH_PAD4_TH1; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 16; - __IOM uint32_t LP_ANA_TOUCH_PAD4_TH2 : 16;/*!< Reserved */ - } bit; - } LP_ANA_TOUCH_PAD4_TH2; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 16; - __IOM uint32_t LP_ANA_TOUCH_PAD5_TH0 : 16;/*!< Reserved */ - } bit; - } LP_ANA_TOUCH_PAD5_TH0; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 16; - __IOM uint32_t LP_ANA_TOUCH_PAD5_TH1 : 16;/*!< Reserved */ - } bit; - } LP_ANA_TOUCH_PAD5_TH1; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 16; - __IOM uint32_t LP_ANA_TOUCH_PAD5_TH2 : 16;/*!< Reserved */ - } bit; - } LP_ANA_TOUCH_PAD5_TH2; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 16; - __IOM uint32_t LP_ANA_TOUCH_PAD6_TH0 : 16;/*!< Reserved */ - } bit; - } LP_ANA_TOUCH_PAD6_TH0; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 16; - __IOM uint32_t LP_ANA_TOUCH_PAD6_TH1 : 16;/*!< Reserved */ - } bit; - } LP_ANA_TOUCH_PAD6_TH1; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 16; - __IOM uint32_t LP_ANA_TOUCH_PAD6_TH2 : 16;/*!< Reserved */ - } bit; - } LP_ANA_TOUCH_PAD6_TH2; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 16; - __IOM uint32_t LP_ANA_TOUCH_PAD7_TH0 : 16;/*!< Reserved */ - } bit; - } LP_ANA_TOUCH_PAD7_TH0; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 16; - __IOM uint32_t LP_ANA_TOUCH_PAD7_TH1 : 16;/*!< Reserved */ - } bit; - } LP_ANA_TOUCH_PAD7_TH1; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 16; - __IOM uint32_t LP_ANA_TOUCH_PAD7_TH2 : 16;/*!< Reserved */ - } bit; - } LP_ANA_TOUCH_PAD7_TH2; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 16; - __IOM uint32_t LP_ANA_TOUCH_PAD8_TH0 : 16;/*!< Reserved */ - } bit; - } LP_ANA_TOUCH_PAD8_TH0; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 16; - __IOM uint32_t LP_ANA_TOUCH_PAD8_TH1 : 16;/*!< Reserved */ - } bit; - } LP_ANA_TOUCH_PAD8_TH1; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 16; - __IOM uint32_t LP_ANA_TOUCH_PAD8_TH2 : 16;/*!< Reserved */ - } bit; - } LP_ANA_TOUCH_PAD8_TH2; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 16; - __IOM uint32_t LP_ANA_TOUCH_PAD9_TH0 : 16;/*!< Reserved */ - } bit; - } LP_ANA_TOUCH_PAD9_TH0; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 16; - __IOM uint32_t LP_ANA_TOUCH_PAD9_TH1 : 16;/*!< Reserved */ - } bit; - } LP_ANA_TOUCH_PAD9_TH1; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 16; - __IOM uint32_t LP_ANA_TOUCH_PAD9_TH2 : 16;/*!< Reserved */ - } bit; - } LP_ANA_TOUCH_PAD9_TH2; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 16; - __IOM uint32_t LP_ANA_TOUCH_PAD10_TH0 : 16;/*!< Reserved */ - } bit; - } LP_ANA_TOUCH_PAD10_TH0; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 16; - __IOM uint32_t LP_ANA_TOUCH_PAD10_TH1 : 16;/*!< Reserved */ - } bit; - } LP_ANA_TOUCH_PAD10_TH1; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 16; - __IOM uint32_t LP_ANA_TOUCH_PAD10_TH2 : 16;/*!< Reserved */ - } bit; - } LP_ANA_TOUCH_PAD10_TH2; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 16; - __IOM uint32_t LP_ANA_TOUCH_PAD11_TH0 : 16;/*!< Reserved */ - } bit; - } LP_ANA_TOUCH_PAD11_TH0; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 16; - __IOM uint32_t LP_ANA_TOUCH_PAD11_TH1 : 16;/*!< Reserved */ - } bit; - } LP_ANA_TOUCH_PAD11_TH1; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 16; - __IOM uint32_t LP_ANA_TOUCH_PAD11_TH2 : 16;/*!< Reserved */ - } bit; - } LP_ANA_TOUCH_PAD11_TH2; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 16; - __IOM uint32_t LP_ANA_TOUCH_PAD12_TH0 : 16;/*!< Reserved */ - } bit; - } LP_ANA_TOUCH_PAD12_TH0; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 16; - __IOM uint32_t LP_ANA_TOUCH_PAD12_TH1 : 16;/*!< Reserved */ - } bit; - } LP_ANA_TOUCH_PAD12_TH1; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 16; - __IOM uint32_t LP_ANA_TOUCH_PAD12_TH2 : 16;/*!< Reserved */ - } bit; - } LP_ANA_TOUCH_PAD12_TH2; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 16; - __IOM uint32_t LP_ANA_TOUCH_PAD13_TH0 : 16;/*!< Reserved */ - } bit; - } LP_ANA_TOUCH_PAD13_TH0; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 16; - __IOM uint32_t LP_ANA_TOUCH_PAD13_TH1 : 16;/*!< Reserved */ - } bit; - } LP_ANA_TOUCH_PAD13_TH1; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 16; - __IOM uint32_t LP_ANA_TOUCH_PAD13_TH2 : 16;/*!< Reserved */ - } bit; - } LP_ANA_TOUCH_PAD13_TH2; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 16; - __IOM uint32_t LP_ANA_TOUCH_PAD14_TH0 : 16;/*!< Reserved */ - } bit; - } LP_ANA_TOUCH_PAD14_TH0; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 16; - __IOM uint32_t LP_ANA_TOUCH_PAD14_TH1 : 16;/*!< Reserved */ - } bit; - } LP_ANA_TOUCH_PAD14_TH1; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 16; - __IOM uint32_t LP_ANA_TOUCH_PAD14_TH2 : 16;/*!< Reserved */ - } bit; - } LP_ANA_TOUCH_PAD14_TH2; - __IM uint32_t RESERVED1[129]; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t LP_ANA_LP_ANA_DATE : 31; /*!< need_des */ - __IOM uint32_t LP_ANA_CLK_EN : 1; /*!< need_des */ - } bit; - } LP_ANA_DATE; -} LP_ANA_PERI_Type; /*!< Size = 1024 (0x400) */ - - - -/* =========================================================================================================================== */ -/* ================ LP_AON_CLKRST ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief LP_AON_CLKRST Peripheral (LP_AON_CLKRST) - */ - -typedef struct { /*!< LP_AON_CLKRST Structure */ - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t LP_AONCLKRST_SLOW_CLK_SEL : 2;/*!< need_des */ - __IOM uint32_t LP_AONCLKRST_FAST_CLK_SEL : 2;/*!< need_des */ - __IOM uint32_t LP_AONCLKRST_LP_PERI_DIV_NUM : 6;/*!< need_des */ - __IOM uint32_t LP_AONCLKRST_ANA_SEL_REF_PLL8M : 1;/*!< need_des */ - uint32_t : 21; - } bit; - } LP_AONCLKRST_LP_CLK_CONF; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t LP_AONCLKRST_CLK_CORE_EFUSE_OEN : 1;/*!< need_des */ - __IOM uint32_t LP_AONCLKRST_CLK_LP_BUS_OEN : 1;/*!< need_des */ - __IOM uint32_t LP_AONCLKRST_CLK_AON_SLOW_OEN : 1;/*!< need_des */ - __IOM uint32_t LP_AONCLKRST_CLK_AON_FAST_OEN : 1;/*!< need_des */ - __IOM uint32_t LP_AONCLKRST_CLK_SLOW_OEN : 1;/*!< need_des */ - __IOM uint32_t LP_AONCLKRST_CLK_FAST_OEN : 1;/*!< need_des */ - __IOM uint32_t LP_AONCLKRST_CLK_FOSC_OEN : 1;/*!< need_des */ - __IOM uint32_t LP_AONCLKRST_CLK_RC32K_OEN : 1;/*!< need_des */ - __IOM uint32_t LP_AONCLKRST_CLK_SXTAL_OEN : 1;/*!< need_des */ - __IOM uint32_t LP_AONCLKRST_CLK_SOSC_OEN : 1;/*!< 1'b1: probe sosc clk on1'b0: probe sosc clk off */ - uint32_t : 22; - } bit; - } LP_AONCLKRST_LP_CLK_PO_EN; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 26; - __IOM uint32_t LP_AONCLKRST_LP_RTC_XTAL_FORCE_ON : 1;/*!< need_des */ - __IOM uint32_t LP_AONCLKRST_CK_EN_LP_RAM : 1;/*!< need_des */ - __IOM uint32_t LP_AONCLKRST_ETM_EVENT_TICK_EN : 1;/*!< need_des */ - __IOM uint32_t LP_AONCLKRST_PLL8M_CLK_FORCE_ON : 1;/*!< need_des */ - __IOM uint32_t LP_AONCLKRST_XTAL_CLK_FORCE_ON : 1;/*!< need_des */ - __IOM uint32_t LP_AONCLKRST_FOSC_CLK_FORCE_ON : 1;/*!< need_des */ - } bit; - } LP_AONCLKRST_LP_CLK_EN; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 24; - __IOM uint32_t LP_AONCLKRST_RST_EN_LP_HUK : 1;/*!< need_des */ - __IOM uint32_t LP_AONCLKRST_RST_EN_LP_ANAPERI : 1;/*!< need_des */ - __IOM uint32_t LP_AONCLKRST_RST_EN_LP_WDT : 1;/*!< need_des */ - __IOM uint32_t LP_AONCLKRST_RST_EN_LP_TIMER : 1;/*!< need_des */ - __IOM uint32_t LP_AONCLKRST_RST_EN_LP_RTC : 1;/*!< need_des */ - __IOM uint32_t LP_AONCLKRST_RST_EN_LP_MAILBOX : 1;/*!< need_des */ - __IOM uint32_t LP_AONCLKRST_RST_EN_LP_AONEFUSEREG : 1;/*!< need_des */ - __IOM uint32_t LP_AONCLKRST_RST_EN_LP_RAM : 1;/*!< need_des */ - } bit; - } LP_AONCLKRST_LP_RST_EN; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IM uint32_t LP_AONCLKRST_LPCORE_RESET_CAUSE : 6;/*!< 6'h1: POR reset6'h9: PMU LP PERI power down reset6'ha: PMU LP - CPU reset6'hf: brown out reset6'h10: LP watchdog chip reset6'h12: - super watch dog reset6'h13: glitch reset6'h14: software - reset */ - __IM uint32_t LP_AONCLKRST_LPCORE_RESET_FLAG : 1;/*!< need_des */ - __IM uint32_t LP_AONCLKRST_HPCORE0_RESET_CAUSE : 6;/*!< 6'h1: POR reset6'h3: digital system software reset6'h5: PMU - HP system power down reset6'h7: HP system reset from HP - watchdog6'h9: HP system reset from LP watchdog6'hb: HP - core reset from HP watchdog6'hc: HP core software reset6'hd: - HP core reset from LP watchdog6'hf: brown out reset6'h10: - LP watchdog chip reset6'h12: super watch dog reset6'h13: - glitch reset6'h14: efuse crc error reset6'h16: HP usb jtag - chip reset6'h17: HP usb uart chip reset6'h18: HP jtag reset6'h1a: - HP core lockup */ - __IM uint32_t LP_AONCLKRST_HPCORE0_RESET_FLAG : 1;/*!< need_des */ - __IM uint32_t LP_AONCLKRST_HPCORE1_RESET_CAUSE : 6;/*!< 6'h1: POR reset6'h3: digital system software reset6'h5: PMU - HP system power down reset6'h7: HP system reset from HP - watchdog6'h9: HP system reset from LP watchdog6'hb: HP - core reset from HP watchdog6'hc: HP core software reset6'hd: - HP core reset from LP watchdog6'hf: brown out reset6'h10: - LP watchdog chip reset6'h12: super watch dog reset6'h13: - glitch reset6'h14: efuse crc error reset6'h16: HP usb jtag - chip reset6'h17: HP usb uart chip reset6'h18: HP jtag reset6'h1a: - HP core lockup */ - __IM uint32_t LP_AONCLKRST_HPCORE1_RESET_FLAG : 1;/*!< need_des */ - uint32_t : 4; - __IOM uint32_t LP_AONCLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK : 1;/*!< 1'b0: enable lpcore pmu_lp_cpu_reset reset_cause, 1'b1: disable - lpcore pmu_lp_cpu_reset reset_cause */ - __OM uint32_t LP_AONCLKRST_LPCORE_RESET_CAUSE_CLR : 1;/*!< need_des */ - __OM uint32_t LP_AONCLKRST_LPCORE_RESET_FLAG_CLR : 1;/*!< need_des */ - __OM uint32_t LP_AONCLKRST_HPCORE0_RESET_CAUSE_CLR : 1;/*!< need_des */ - __OM uint32_t LP_AONCLKRST_HPCORE0_RESET_FLAG_CLR : 1;/*!< need_des */ - __OM uint32_t LP_AONCLKRST_HPCORE1_RESET_CAUSE_CLR : 1;/*!< need_des */ - __OM uint32_t LP_AONCLKRST_HPCORE1_RESET_FLAG_CLR : 1;/*!< need_des */ - } bit; - } LP_AONCLKRST_RESET_CAUSE; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t LP_AONCLKRST_HPCORE0_LOCKUP_RESET_EN : 1;/*!< write 1 to enable hpcore0 lockup reset feature, write 0 to disable - hpcore0 lockup reset feature */ - __IOM uint32_t LP_AONCLKRST_LP_WDT_HPCORE0_RESET_LENGTH : 3;/*!< need_des */ - __IOM uint32_t LP_AONCLKRST_LP_WDT_HPCORE0_RESET_EN : 1;/*!< write 1 to enable lp_wdt reset hpcore0 feature, write 0 to disable - lp_wdt reset hpcore0 feature */ - __IOM uint32_t LP_AONCLKRST_HPCORE0_STALL_WAIT : 7;/*!< need_des */ - __IOM uint32_t LP_AONCLKRST_HPCORE0_STALL_EN : 1;/*!< need_des */ - __OM uint32_t LP_AONCLKRST_HPCORE0_SW_RESET : 1;/*!< need_des */ - __IOM uint32_t LP_AONCLKRST_HPCORE0_OCD_HALT_ON_RESET : 1;/*!< need_des */ - __IOM uint32_t LP_AONCLKRST_HPCORE0_STAT_VECTOR_SEL : 1;/*!< 1'b1: boot from HP TCM ROM: 0x4FC000001'b0: boot from LP TCM - RAM: 0x50108000 */ - __IOM uint32_t LP_AONCLKRST_HPCORE1_LOCKUP_RESET_EN : 1;/*!< write 1 to enable hpcore1 lockup reset feature, write 0 to disable - hpcore1 lockup reset feature */ - __IOM uint32_t LP_AONCLKRST_LP_WDT_HPCORE1_RESET_LENGTH : 3;/*!< need_des */ - __IOM uint32_t LP_AONCLKRST_LP_WDT_HPCORE1_RESET_EN : 1;/*!< write 1 to enable lp_wdt reset hpcore1 feature, write 0 to disable - lp_wdt reset hpcore1 feature */ - __IOM uint32_t LP_AONCLKRST_HPCORE1_STALL_WAIT : 7;/*!< need_des */ - __IOM uint32_t LP_AONCLKRST_HPCORE1_STALL_EN : 1;/*!< need_des */ - __OM uint32_t LP_AONCLKRST_HPCORE1_SW_RESET : 1;/*!< need_des */ - __IOM uint32_t LP_AONCLKRST_HPCORE1_OCD_HALT_ON_RESET : 1;/*!< need_des */ - __IOM uint32_t LP_AONCLKRST_HPCORE1_STAT_VECTOR_SEL : 1;/*!< 1'b1: boot from HP TCM ROM: 0x4FC000001'b0: boot from LP TCM - RAM: 0x50108000 */ - } bit; - } LP_AONCLKRST_HPCPU_RESET_CTRL0; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 16; - __IOM uint32_t LP_AONCLKRST_HPCORE0_SW_STALL_CODE : 8;/*!< HP core0 software stall when set to 8'h86 */ - __IOM uint32_t LP_AONCLKRST_HPCORE1_SW_STALL_CODE : 8;/*!< HP core1 software stall when set to 8'h86 */ - } bit; - } LP_AONCLKRST_HPCPU_RESET_CTRL1; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 22; - __IOM uint32_t LP_AONCLKRST_FOSC_DFREQ : 10;/*!< need_des */ - } bit; - } LP_AONCLKRST_FOSC_CNTL; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t LP_AONCLKRST_RC32K_DFREQ : 32;/*!< need_des */ - } bit; - } LP_AONCLKRST_RC32K_CNTL; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 22; - __IOM uint32_t LP_AONCLKRST_SOSC_DFREQ : 10;/*!< need_des */ - } bit; - } LP_AONCLKRST_SOSC_CNTL; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 28; - __IOM uint32_t LP_AONCLKRST_ICG_HP_XTAL32K : 1;/*!< reserved */ - __IOM uint32_t LP_AONCLKRST_ICG_HP_SOSC : 1;/*!< reserved */ - __IOM uint32_t LP_AONCLKRST_ICG_HP_OSC32K : 1;/*!< reserved */ - __IOM uint32_t LP_AONCLKRST_ICG_HP_FOSC : 1;/*!< reserved */ - } bit; - } LP_AONCLKRST_CLK_TO_HP; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 31; - __IOM uint32_t LP_AONCLKRST_LPMEM_CLK_FORCE_ON : 1;/*!< reserved */ - } bit; - } LP_AONCLKRST_LPMEM_FORCE; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 22; - __IOM uint32_t LP_AONCLKRST_DRES_XTAL32K : 3;/*!< need_des */ - __IOM uint32_t LP_AONCLKRST_DGM_XTAL32K : 3;/*!< need_des */ - __IOM uint32_t LP_AONCLKRST_DBUF_XTAL32K : 1;/*!< need_des */ - __IOM uint32_t LP_AONCLKRST_DAC_XTAL32K : 3;/*!< need_des */ - } bit; - } LP_AONCLKRST_XTAL32K; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS : 32;/*!< reserved */ - } bit; - } LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t LP_AONCLKRST_HPSYS_0_RESET_BYPASS : 32;/*!< reserved */ - } bit; - } LP_AONCLKRST_HPSYS_0_RESET_BYPASS; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t LP_AONCLKRST_HPSYS_APM_RESET_BYPASS : 32;/*!< reserved */ - } bit; - } LP_AONCLKRST_HPSYS_APM_RESET_BYPASS; - - union { - __IOM uint32_t reg; /*!< HP Clock Control Register. */ - - struct { - __IOM uint32_t LP_AONCLKRST_HP_ROOT_CLK_SRC_SEL : 2;/*!< HP SoC Root Clock Source Select. 2'd0: xtal_40m, 2'd1: cpll_400m, - 2'd2: fosc_20m. */ - __IOM uint32_t LP_AONCLKRST_HP_ROOT_CLK_EN : 1;/*!< HP SoC Root Clock Enable. */ - __IOM uint32_t LP_AONCLKRST_HP_PAD_PARLIO_TX_CLK_EN : 1;/*!< PARLIO TX Clock From Pad Enable. */ - __IOM uint32_t LP_AONCLKRST_HP_PAD_PARLIO_RX_CLK_EN : 1;/*!< PARLIO RX Clock From Pad Enable. */ - __IOM uint32_t LP_AONCLKRST_HP_PAD_UART4_SLP_CLK_EN : 1;/*!< UART4 SLP Clock From Pad Enable. */ - __IOM uint32_t LP_AONCLKRST_HP_PAD_UART3_SLP_CLK_EN : 1;/*!< UART3 SLP Clock From Pad Enable. */ - __IOM uint32_t LP_AONCLKRST_HP_PAD_UART2_SLP_CLK_EN : 1;/*!< UART2 SLP Clock From Pad Enable. */ - __IOM uint32_t LP_AONCLKRST_HP_PAD_UART1_SLP_CLK_EN : 1;/*!< UART1 SLP Clock From Pad Enable. */ - __IOM uint32_t LP_AONCLKRST_HP_PAD_UART0_SLP_CLK_EN : 1;/*!< UART0 SLP Clock From Pad Enable. */ - __IOM uint32_t LP_AONCLKRST_HP_PAD_I2S2_MCLK_EN : 1;/*!< I2S2 MCLK Clock From Pad Enable. */ - __IOM uint32_t LP_AONCLKRST_HP_PAD_I2S1_MCLK_EN : 1;/*!< I2S1 MCLK Clock From Pad Enable. */ - __IOM uint32_t LP_AONCLKRST_HP_PAD_I2S0_MCLK_EN : 1;/*!< I2S0 MCLK Clock From Pad Enable. */ - __IOM uint32_t LP_AONCLKRST_HP_PAD_EMAC_TX_CLK_EN : 1;/*!< EMAC RX Clock From Pad Enable. */ - __IOM uint32_t LP_AONCLKRST_HP_PAD_EMAC_RX_CLK_EN : 1;/*!< EMAC TX Clock From Pad Enable. */ - __IOM uint32_t LP_AONCLKRST_HP_PAD_EMAC_TXRX_CLK_EN : 1;/*!< EMAC TXRX Clock From Pad Enable. */ - __IOM uint32_t LP_AONCLKRST_HP_XTAL_32K_CLK_EN : 1;/*!< XTAL 32K Clock Enable. */ - __IOM uint32_t LP_AONCLKRST_HP_RC_32K_CLK_EN : 1;/*!< RC 32K Clock Enable. */ - __IOM uint32_t LP_AONCLKRST_HP_SOSC_150K_CLK_EN : 1;/*!< SOSC 150K Clock Enable. */ - __IOM uint32_t LP_AONCLKRST_HP_PLL_8M_CLK_EN : 1;/*!< PLL 8M Clock Enable. */ - __IOM uint32_t LP_AONCLKRST_HP_AUDIO_PLL_CLK_EN : 1;/*!< AUDIO PLL Clock Enable. */ - __IOM uint32_t LP_AONCLKRST_HP_SDIO_PLL2_CLK_EN : 1;/*!< SDIO PLL2 Clock Enable. */ - __IOM uint32_t LP_AONCLKRST_HP_SDIO_PLL1_CLK_EN : 1;/*!< SDIO PLL1 Clock Enable. */ - __IOM uint32_t LP_AONCLKRST_HP_SDIO_PLL0_CLK_EN : 1;/*!< SDIO PLL0 Clock Enable. */ - __IOM uint32_t LP_AONCLKRST_HP_FOSC_20M_CLK_EN : 1;/*!< FOSC 20M Clock Enable. */ - __IOM uint32_t LP_AONCLKRST_HP_XTAL_40M_CLK_EN : 1;/*!< XTAL 40M Clock Enalbe. */ - __IOM uint32_t LP_AONCLKRST_HP_CPLL_400M_CLK_EN : 1;/*!< CPLL 400M Clock Enable. */ - __IOM uint32_t LP_AONCLKRST_HP_SPLL_480M_CLK_EN : 1;/*!< SPLL 480M Clock Enable. */ - __IOM uint32_t LP_AONCLKRST_HP_MPLL_500M_CLK_EN : 1;/*!< MPLL 500M Clock Enable. */ - uint32_t : 3; - } bit; - } LP_AONCLKRST_HP_CLK_CTRL; - - union { - __IOM uint32_t reg; /*!< HP USB Clock Reset Control Register. */ - - struct { - __IOM uint32_t LP_AONCLKRST_USB_OTG20_SLEEP_MODE : 1;/*!< unused. */ - __IOM uint32_t LP_AONCLKRST_USB_OTG20_BK_SYS_CLK_EN : 1;/*!< unused. */ - __IOM uint32_t LP_AONCLKRST_USB_OTG11_SLEEP_MODE : 1;/*!< unused. */ - __IOM uint32_t LP_AONCLKRST_USB_OTG11_BK_SYS_CLK_EN : 1;/*!< unused. */ - __IOM uint32_t LP_AONCLKRST_USB_OTG11_48M_CLK_EN : 1;/*!< usb otg11 fs phy clock enable. */ - __IOM uint32_t LP_AONCLKRST_USB_DEVICE_48M_CLK_EN : 1;/*!< usb device fs phy clock enable. */ - __IOM uint32_t LP_AONCLKRST_USB_48M_DIV_NUM : 8;/*!< usb 480m to 25m divide number. */ - __IOM uint32_t LP_AONCLKRST_USB_25M_DIV_NUM : 8;/*!< usb 500m to 25m divide number. */ - __IOM uint32_t LP_AONCLKRST_USB_12M_DIV_NUM : 8;/*!< usb 480m to 12m divide number. */ - uint32_t : 2; - } bit; - } LP_AONCLKRST_HP_USB_CLKRST_CTRL0; - - union { - __IOM uint32_t reg; /*!< HP USB Clock Reset Control Register. */ - - struct { - __IOM uint32_t LP_AONCLKRST_RST_EN_USB_OTG20_ADP : 1;/*!< usb otg20 adp reset en */ - __IOM uint32_t LP_AONCLKRST_RST_EN_USB_OTG20_PHY : 1;/*!< usb otg20 phy reset en */ - __IOM uint32_t LP_AONCLKRST_RST_EN_USB_OTG20 : 1;/*!< usb otg20 reset en */ - __IOM uint32_t LP_AONCLKRST_RST_EN_USB_OTG11 : 1;/*!< usb org11 reset en */ - __IOM uint32_t LP_AONCLKRST_RST_EN_USB_DEVICE : 1;/*!< usb device reset en */ - uint32_t : 23; - __IOM uint32_t LP_AONCLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL : 2;/*!< usb otg20 hs phy src sel. 2'd0: 12m, 2'd1: 25m, 2'd2: pad_hsphy_refclk. */ - __IOM uint32_t LP_AONCLKRST_USB_OTG20_PHYREF_CLK_EN : 1;/*!< usb otg20 hs phy refclk enable. */ - __IOM uint32_t LP_AONCLKRST_USB_OTG20_ULPI_CLK_EN : 1;/*!< usb otg20 ulpi clock enable. */ - } bit; - } LP_AONCLKRST_HP_USB_CLKRST_CTRL1; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 28; - __IOM uint32_t LP_AONCLKRST_RST_EN_SDMMC : 1;/*!< hp sdmmc reset en */ - __IOM uint32_t LP_AONCLKRST_FORCE_NORST_SDMMC : 1;/*!< hp sdmmc force norst */ - __IOM uint32_t LP_AONCLKRST_RST_EN_EMAC : 1;/*!< hp emac reset en */ - __IOM uint32_t LP_AONCLKRST_FORCE_NORST_EMAC : 1;/*!< hp emac force norst */ - } bit; - } LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL; - __IM uint32_t RESERVED[235]; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 31; - __IOM uint32_t LP_AONCLKRST_CLK_EN : 1; /*!< need_des */ - } bit; - } LP_AONCLKRST_DATE; -} LP_AON_CLKRST_Type; /*!< Size = 1024 (0x400) */ - - - -/* =========================================================================================================================== */ -/* ================ LP_GPIO ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Low-power General Purpose Input/Output (LP_GPIO) - */ - -typedef struct { /*!< LP_GPIO Structure */ - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_CLK_EN : 1; /*!< Reserved */ - uint32_t : 31; - } bit; - } CLK_EN; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_VER_DATE : 28; /*!< Reserved */ - uint32_t : 4; - } bit; - } VER_DATE; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_GPIO_OUT_DATA : 16; /*!< Reserved */ - uint32_t : 16; - } bit; - } OUT; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __OM uint32_t REG_GPIO_OUT_DATA_W1TS : 16;/*!< Reserved */ - uint32_t : 16; - } bit; - } OUT_W1TS; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __OM uint32_t REG_GPIO_OUT_DATA_W1TC : 16;/*!< Reserved */ - uint32_t : 16; - } bit; - } OUT_W1TC; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_GPIO_ENABLE_DATA : 16; /*!< Reserved */ - uint32_t : 16; - } bit; - } ENABLE; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __OM uint32_t REG_GPIO_ENABLE_DATA_W1TS : 16;/*!< Reserved */ - uint32_t : 16; - } bit; - } ENABLE_W1TS; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __OM uint32_t REG_GPIO_ENABLE_DATA_W1TC : 16;/*!< Reserved */ - uint32_t : 16; - } bit; - } ENABLE_W1TC; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_GPIO_STATUS_DATA : 16; /*!< Reserved */ - uint32_t : 16; - } bit; - } STATUS; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __OM uint32_t REG_GPIO_STATUS_DATA_W1TS : 16;/*!< Reserved */ - uint32_t : 16; - } bit; - } STATUS_W1TS; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __OM uint32_t REG_GPIO_STATUS_DATA_W1TC : 16;/*!< Reserved */ - uint32_t : 16; - } bit; - } STATUS_W1TC; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IM uint32_t REG_GPIO_STATUS_INTERRUPT_NEXT : 16;/*!< Reserved */ - uint32_t : 16; - } bit; - } STATUS_NEXT; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IM uint32_t REG_GPIO_IN_DATA_NEXT : 16;/*!< Reserved */ - uint32_t : 16; - } bit; - } IN; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_GPIO_PIN0_WAKEUP_ENABLE : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_PIN0_INT_TYPE : 3;/*!< Reserved */ - __IOM uint32_t REG_GPIO_PIN0_PAD_DRIVER : 1;/*!< Reserved */ - __OM uint32_t REG_GPIO_PIN0_EDGE_WAKEUP_CLR : 1;/*!< need des */ - uint32_t : 26; - } bit; - } PIN0; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_GPIO_PIN1_WAKEUP_ENABLE : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_PIN1_INT_TYPE : 3;/*!< Reserved */ - __IOM uint32_t REG_GPIO_PIN1_PAD_DRIVER : 1;/*!< Reserved */ - __OM uint32_t REG_GPI1_PIN0_EDGE_WAKEUP_CLR : 1;/*!< need des */ - uint32_t : 26; - } bit; - } PIN1; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_GPIO_PIN2_WAKEUP_ENABLE : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_PIN2_INT_TYPE : 3;/*!< Reserved */ - __IOM uint32_t REG_GPIO_PIN2_PAD_DRIVER : 1;/*!< Reserved */ - __OM uint32_t REG_GPI2_PIN0_EDGE_WAKEUP_CLR : 1;/*!< need des */ - uint32_t : 26; - } bit; - } PIN2; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_GPIO_PIN3_WAKEUP_ENABLE : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_PIN3_INT_TYPE : 3;/*!< Reserved */ - __IOM uint32_t REG_GPIO_PIN3_PAD_DRIVER : 1;/*!< Reserved */ - __OM uint32_t REG_GPI3_PIN0_EDGE_WAKEUP_CLR : 1;/*!< need des */ - uint32_t : 26; - } bit; - } PIN3; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_GPIO_PIN4_WAKEUP_ENABLE : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_PIN4_INT_TYPE : 3;/*!< Reserved */ - __IOM uint32_t REG_GPIO_PIN4_PAD_DRIVER : 1;/*!< Reserved */ - __OM uint32_t REG_GPI4_PIN0_EDGE_WAKEUP_CLR : 1;/*!< need des */ - uint32_t : 26; - } bit; - } PIN4; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_GPIO_PIN5_WAKEUP_ENABLE : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_PIN5_INT_TYPE : 3;/*!< Reserved */ - __IOM uint32_t REG_GPIO_PIN5_PAD_DRIVER : 1;/*!< Reserved */ - __OM uint32_t REG_GPI5_PIN0_EDGE_WAKEUP_CLR : 1;/*!< need des */ - uint32_t : 26; - } bit; - } PIN5; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_GPIO_PIN6_WAKEUP_ENABLE : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_PIN6_INT_TYPE : 3;/*!< Reserved */ - __IOM uint32_t REG_GPIO_PIN6_PAD_DRIVER : 1;/*!< Reserved */ - __OM uint32_t REG_GPI6_PIN0_EDGE_WAKEUP_CLR : 1;/*!< need des */ - uint32_t : 26; - } bit; - } PIN6; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_GPIO_PIN7_WAKEUP_ENABLE : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_PIN7_INT_TYPE : 3;/*!< Reserved */ - __IOM uint32_t REG_GPIO_PIN7_PAD_DRIVER : 1;/*!< Reserved */ - __OM uint32_t REG_GPI7_PIN0_EDGE_WAKEUP_CLR : 1;/*!< need des */ - uint32_t : 26; - } bit; - } PIN7; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_GPIO_PIN8_WAKEUP_ENABLE : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_PIN8_INT_TYPE : 3;/*!< Reserved */ - __IOM uint32_t REG_GPIO_PIN8_PAD_DRIVER : 1;/*!< Reserved */ - __OM uint32_t REG_GPI8_PIN0_EDGE_WAKEUP_CLR : 1;/*!< need des */ - uint32_t : 26; - } bit; - } PIN8; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_GPIO_PIN9_WAKEUP_ENABLE : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_PIN9_INT_TYPE : 3;/*!< Reserved */ - __IOM uint32_t REG_GPIO_PIN9_PAD_DRIVER : 1;/*!< Reserved */ - __OM uint32_t REG_GPI9_PIN0_EDGE_WAKEUP_CLR : 1;/*!< need des */ - uint32_t : 26; - } bit; - } PIN9; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_GPIO_PIN10_WAKEUP_ENABLE : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_PIN10_INT_TYPE : 3;/*!< Reserved */ - __IOM uint32_t REG_GPIO_PIN10_PAD_DRIVER : 1;/*!< Reserved */ - __OM uint32_t REG_GPI10_PIN0_EDGE_WAKEUP_CLR : 1;/*!< need des */ - uint32_t : 26; - } bit; - } PIN10; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_GPIO_PIN11_WAKEUP_ENABLE : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_PIN11_INT_TYPE : 3;/*!< Reserved */ - __IOM uint32_t REG_GPIO_PIN11_PAD_DRIVER : 1;/*!< Reserved */ - __OM uint32_t REG_GPI11_PIN0_EDGE_WAKEUP_CLR : 1;/*!< need des */ - uint32_t : 26; - } bit; - } PIN11; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_GPIO_PIN12_WAKEUP_ENABLE : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_PIN12_INT_TYPE : 3;/*!< Reserved */ - __IOM uint32_t REG_GPIO_PIN12_PAD_DRIVER : 1;/*!< Reserved */ - __OM uint32_t REG_GPI12_PIN0_EDGE_WAKEUP_CLR : 1;/*!< need des */ - uint32_t : 26; - } bit; - } PIN12; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_GPIO_PIN13_WAKEUP_ENABLE : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_PIN13_INT_TYPE : 3;/*!< Reserved */ - __IOM uint32_t REG_GPIO_PIN13_PAD_DRIVER : 1;/*!< Reserved */ - __OM uint32_t REG_GPI13_PIN0_EDGE_WAKEUP_CLR : 1;/*!< need des */ - uint32_t : 26; - } bit; - } PIN13; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_GPIO_PIN14_WAKEUP_ENABLE : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_PIN14_INT_TYPE : 3;/*!< Reserved */ - __IOM uint32_t REG_GPIO_PIN14_PAD_DRIVER : 1;/*!< Reserved */ - __OM uint32_t REG_GPI14_PIN0_EDGE_WAKEUP_CLR : 1;/*!< need des */ - uint32_t : 26; - } bit; - } PIN14; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_GPIO_PIN15_WAKEUP_ENABLE : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_PIN15_INT_TYPE : 3;/*!< Reserved */ - __IOM uint32_t REG_GPIO_PIN15_PAD_DRIVER : 1;/*!< Reserved */ - __OM uint32_t REG_GPI15_PIN0_EDGE_WAKEUP_CLR : 1;/*!< need des */ - uint32_t : 26; - } bit; - } PIN15; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_GPIO_FUNC0_IN_INV_SEL : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_SIG0_IN_SEL : 1; /*!< Reserved */ - __IOM uint32_t REG_GPIO_FUNC0_IN_SEL : 6; /*!< reg_gpio_func0_in_sel[5:4]==2'b11->constant 1,reg_gpio_func0_in_sel[5:4]==2'b1 - ->constant 0 */ - uint32_t : 24; - } bit; - } FUNC0_IN_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_GPIO_FUNC1_IN_INV_SEL : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_SIG1_IN_SEL : 1; /*!< Reserved */ - __IOM uint32_t REG_GPIO_FUNC1_IN_SEL : 6; /*!< Reserved */ - uint32_t : 24; - } bit; - } FUNC1_IN_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_GPIO_FUNC2_IN_INV_SEL : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_SIG2_IN_SEL : 1; /*!< Reserved */ - __IOM uint32_t REG_GPIO_FUNC2_IN_SEL : 6; /*!< Reserved */ - uint32_t : 24; - } bit; - } FUNC2_IN_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_GPIO_FUNC3_IN_INV_SEL : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_SIG3_IN_SEL : 1; /*!< Reserved */ - __IOM uint32_t REG_GPIO_FUNC3_IN_SEL : 6; /*!< Reserved */ - uint32_t : 24; - } bit; - } FUNC3_IN_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_GPIO_FUNC4_IN_INV_SEL : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_SIG4_IN_SEL : 1; /*!< Reserved */ - __IOM uint32_t REG_GPIO_FUNC4_IN_SEL : 6; /*!< Reserved */ - uint32_t : 24; - } bit; - } FUNC4_IN_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_GPIO_FUNC5_IN_INV_SEL : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_SIG5_IN_SEL : 1; /*!< Reserved */ - __IOM uint32_t REG_GPIO_FUNC5_IN_SEL : 6; /*!< Reserved */ - uint32_t : 24; - } bit; - } FUNC5_IN_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_GPIO_FUNC6_IN_INV_SEL : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_SIG6_IN_SEL : 1; /*!< Reserved */ - __IOM uint32_t REG_GPIO_FUNC6_IN_SEL : 6; /*!< Reserved */ - uint32_t : 24; - } bit; - } FUNC6_IN_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_GPIO_FUNC7_IN_INV_SEL : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_SIG7_IN_SEL : 1; /*!< Reserved */ - __IOM uint32_t REG_GPIO_FUNC7_IN_SEL : 6; /*!< Reserved */ - uint32_t : 24; - } bit; - } FUNC7_IN_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_GPIO_FUNC8_IN_INV_SEL : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_SIG8_IN_SEL : 1; /*!< Reserved */ - __IOM uint32_t REG_GPIO_FUNC8_IN_SEL : 6; /*!< Reserved */ - uint32_t : 24; - } bit; - } FUNC8_IN_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_GPIO_FUNC9_IN_INV_SEL : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_SIG9_IN_SEL : 1; /*!< Reserved */ - __IOM uint32_t REG_GPIO_FUNC9_IN_SEL : 6; /*!< Reserved */ - uint32_t : 24; - } bit; - } FUNC9_IN_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_GPIO_FUNC10_IN_INV_SEL : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_SIG10_IN_SEL : 1; /*!< Reserved */ - __IOM uint32_t REG_GPIO_FUNC10_IN_SEL : 6;/*!< Reserved */ - uint32_t : 24; - } bit; - } FUNC10_IN_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_GPIO_FUNC11_IN_INV_SEL : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_SIG11_IN_SEL : 1; /*!< Reserved */ - __IOM uint32_t REG_GPIO_FUNC11_IN_SEL : 6;/*!< Reserved */ - uint32_t : 24; - } bit; - } FUNC11_IN_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_GPIO_FUNC12_IN_INV_SEL : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_SIG12_IN_SEL : 1; /*!< Reserved */ - __IOM uint32_t REG_GPIO_FUNC12_IN_SEL : 6;/*!< Reserved */ - uint32_t : 24; - } bit; - } FUNC12_IN_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_GPIO_FUNC13_IN_INV_SEL : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_SIG13_IN_SEL : 1; /*!< Reserved */ - __IOM uint32_t REG_GPIO_FUNC13_IN_SEL : 6;/*!< Reserved */ - uint32_t : 24; - } bit; - } FUNC13_IN_SEL_CFG; - __IM uint32_t RESERVED[18]; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_GPIO_FUNC0_OE_INV_SEL : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_FUNC0_OE_SEL : 1; /*!< Reserved */ - __IOM uint32_t REG_GPIO_FUNC0_OUT_INV_SEL : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_FUNC0_OUT_SEL : 6;/*!< reg_gpio_func0_out_sel[5:1]==16 -> output gpio register value - to pad */ - uint32_t : 23; - } bit; - } FUNC0_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_GPIO_FUNC1_OE_INV_SEL : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_FUNC1_OE_SEL : 1; /*!< Reserved */ - __IOM uint32_t REG_GPIO_FUNC1_OUT_INV_SEL : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_FUNC1_OUT_SEL : 6;/*!< Reserved */ - uint32_t : 23; - } bit; - } FUNC1_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_GPIO_FUNC2_OE_INV_SEL : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_FUNC2_OE_SEL : 1; /*!< Reserved */ - __IOM uint32_t REG_GPIO_FUNC2_OUT_INV_SEL : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_FUNC2_OUT_SEL : 6;/*!< Reserved */ - uint32_t : 23; - } bit; - } FUNC2_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_GPIO_FUNC3_OE_INV_SEL : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_FUNC3_OE_SEL : 1; /*!< Reserved */ - __IOM uint32_t REG_GPIO_FUNC3_OUT_INV_SEL : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_FUNC3_OUT_SEL : 6;/*!< Reserved */ - uint32_t : 23; - } bit; - } FUNC3_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_GPIO_FUNC4_OE_INV_SEL : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_FUNC4_OE_SEL : 1; /*!< Reserved */ - __IOM uint32_t REG_GPIO_FUNC4_OUT_INV_SEL : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_FUNC4_OUT_SEL : 6;/*!< Reserved */ - uint32_t : 23; - } bit; - } FUNC4_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_GPIO_FUNC5_OE_INV_SEL : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_FUNC5_OE_SEL : 1; /*!< Reserved */ - __IOM uint32_t REG_GPIO_FUNC5_OUT_INV_SEL : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_FUNC5_OUT_SEL : 6;/*!< Reserved */ - uint32_t : 23; - } bit; - } FUNC5_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_GPIO_FUNC6_OE_INV_SEL : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_FUNC6_OE_SEL : 1; /*!< Reserved */ - __IOM uint32_t REG_GPIO_FUNC6_OUT_INV_SEL : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_FUNC6_OUT_SEL : 6;/*!< Reserved */ - uint32_t : 23; - } bit; - } FUNC6_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_GPIO_FUNC7_OE_INV_SEL : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_FUNC7_OE_SEL : 1; /*!< Reserved */ - __IOM uint32_t REG_GPIO_FUNC7_OUT_INV_SEL : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_FUNC7_OUT_SEL : 6;/*!< Reserved */ - uint32_t : 23; - } bit; - } FUNC7_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_GPIO_FUNC8_OE_INV_SEL : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_FUNC8_OE_SEL : 1; /*!< Reserved */ - __IOM uint32_t REG_GPIO_FUNC8_OUT_INV_SEL : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_FUNC8_OUT_SEL : 6;/*!< Reserved */ - uint32_t : 23; - } bit; - } FUNC8_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_GPIO_FUNC9_OE_INV_SEL : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_FUNC9_OE_SEL : 1; /*!< Reserved */ - __IOM uint32_t REG_GPIO_FUNC9_OUT_INV_SEL : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_FUNC9_OUT_SEL : 6;/*!< Reserved */ - uint32_t : 23; - } bit; - } FUNC9_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_GPIO_FUNC10_OE_INV_SEL : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_FUNC10_OE_SEL : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_FUNC10_OUT_INV_SEL : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_FUNC10_OUT_SEL : 6;/*!< Reserved */ - uint32_t : 23; - } bit; - } FUNC10_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_GPIO_FUNC11_OE_INV_SEL : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_FUNC11_OE_SEL : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_FUNC11_OUT_INV_SEL : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_FUNC11_OUT_SEL : 6;/*!< Reserved */ - uint32_t : 23; - } bit; - } FUNC11_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_GPIO_FUNC12_OE_INV_SEL : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_FUNC12_OE_SEL : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_FUNC12_OUT_INV_SEL : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_FUNC12_OUT_SEL : 6;/*!< Reserved */ - uint32_t : 23; - } bit; - } FUNC12_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_GPIO_FUNC13_OE_INV_SEL : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_FUNC13_OE_SEL : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_FUNC13_OUT_INV_SEL : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_FUNC13_OUT_SEL : 6;/*!< Reserved */ - uint32_t : 23; - } bit; - } FUNC13_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_GPIO_FUNC14_OE_INV_SEL : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_FUNC14_OE_SEL : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_FUNC14_OUT_INV_SEL : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_FUNC14_OUT_SEL : 6;/*!< Reserved */ - uint32_t : 23; - } bit; - } FUNC14_OUT_SEL_CFG; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_GPIO_FUNC15_OE_INV_SEL : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_FUNC15_OE_SEL : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_FUNC15_OUT_INV_SEL : 1;/*!< Reserved */ - __IOM uint32_t REG_GPIO_FUNC15_OUT_SEL : 6;/*!< Reserved */ - uint32_t : 23; - } bit; - } FUNC15_OUT_SEL_CFG; -} LP_GPIO_Type; /*!< Size = 308 (0x134) */ - - - -/* =========================================================================================================================== */ -/* ================ LP_I2C0 ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Low-power I2C (Inter-Integrated Circuit) Controller 0 (LP_I2C0) - */ - -typedef struct { /*!< LP_I2C0 Structure */ - - union { - __IOM uint32_t reg; /*!< Configures the low level width of the SCLClock */ - - struct { - __IOM uint32_t SCL_LOW_PERIOD : 9; /*!< Configures the low level width of the SCL Clock. Measurement - unit: i2c_sclk. */ - uint32_t : 23; - } bit; - } SCL_LOW_PERIOD; - - union { - __IOM uint32_t reg; /*!< Transmission setting */ - - struct { - __IOM uint32_t SDA_FORCE_OUT : 1; /*!< Configures the SDA output mode1: Direct output,0: Open drain - output. */ - __IOM uint32_t SCL_FORCE_OUT : 1; /*!< Configures the SCL output mode1: Direct output,0: Open drain - output. */ - __IOM uint32_t SAMPLE_SCL_LEVEL : 1; /*!< Configures the sample mode for SDA.1: Sample SDA data on the - SCL low level.0: Sample SDA data on the SCL high level. */ - __IOM uint32_t RX_FULL_ACK_LEVEL : 1; /*!< Configures the ACK value that needs to be sent by master when - the rx_fifo_cnt has reached the threshold. */ - uint32_t : 1; - __OM uint32_t TRANS_START : 1; /*!< Configures to start sending the data in txfifo for slave. 0: - No effect1: Start */ - __IOM uint32_t TX_LSB_FIRST : 1; /*!< Configures to control the sending order for data needing to - be sent. 1: send data from the least significant bit,0: - send data from the most significant bit. */ - __IOM uint32_t RX_LSB_FIRST : 1; /*!< Configures to control the storage order for received data.1: - receive data from the least significant bit0: receive data - from the most significant bit. */ - __IOM uint32_t CLK_EN : 1; /*!< Configures whether to gate clock signal for registers.0: Force - clock on for registers 1: Support clock only when registers - are read or written to by software. */ - __IOM uint32_t ARBITRATION_EN : 1; /*!< Configures to enable I2C bus arbitration detection.0: No effect1: - Enable */ - __OM uint32_t FSM_RST : 1; /*!< Configures to reset the SCL_FSM.0: No effect1: Reset */ - __OM uint32_t CONF_UPGATE : 1; /*!< Configures this bit for synchronization0: No effect1: Synchronize */ - uint32_t : 20; - } bit; - } CTR; - - union { - __IOM uint32_t reg; /*!< Describe I2C work status. */ - - struct { - __IM uint32_t RESP_REC : 1; /*!< Represents the received ACK value in master mode or slave mode.0: - ACK,1: NACK. */ - uint32_t : 2; - __IM uint32_t ARB_LOST : 1; /*!< Represents whether the I2C controller loses control of SCL line.0: - No arbitration lost1: Arbitration lost */ - __IM uint32_t BUS_BUSY : 1; /*!< Represents the I2C bus state.1: The I2C bus is busy transferring - data, 0: The I2C bus is in idle state. */ - uint32_t : 3; - __IM uint32_t RXFIFO_CNT : 5; /*!< Represents the number of data bytes to be sent. */ - uint32_t : 5; - __IM uint32_t TXFIFO_CNT : 5; /*!< Represents the number of data bytes received in RAM. */ - uint32_t : 1; - __IM uint32_t SCL_MAIN_STATE_LAST : 3; /*!< Represents the states of the I2C module state machine. 0: Idle,1: - Address shift,2: ACK address,3: Rx data,4: Tx data,5: Send - ACK,6: Wait ACK */ - uint32_t : 1; - __IM uint32_t SCL_STATE_LAST : 3; /*!< Represents the states of the state machine used to produce SCL.0: - Idle,1: Start,2: Negative edge,3: Low,4: Positive edge,5: - High,6: Stop */ - uint32_t : 1; - } bit; - } SR; - - union { - __IOM uint32_t reg; /*!< Setting time out control for receiving data. */ - - struct { - __IOM uint32_t TIME_OUT_VALUE : 5; /*!< Configures the timeout threshold period for SCL stucking at - high or low level. The actual period is 2^(reg_time_out_value).Measuremen - unit: i2c_sclk. */ - __IOM uint32_t TIME_OUT_EN : 1; /*!< Configures to enable time out control.0: No effect1: Enable */ - uint32_t : 26; - } bit; - } TO; - __IM uint32_t RESERVED; - - union { - __IOM uint32_t reg; /*!< FIFO status register. */ - - struct { - __IM uint32_t RXFIFO_RADDR : 4; /*!< Represents the offset address of the APB reading from RXFIFO */ - uint32_t : 1; - __IM uint32_t RXFIFO_WADDR : 4; /*!< Represents the offset address of i2c module receiving data and - writing to RXFIFO. */ - uint32_t : 1; - __IM uint32_t TXFIFO_RADDR : 4; /*!< Represents the offset address of i2c module reading from TXFIFO. */ - uint32_t : 1; - __IM uint32_t TXFIFO_WADDR : 4; /*!< Represents the offset address of APB bus writing to TXFIFO. */ - uint32_t : 13; - } bit; - } FIFO_ST; - - union { - __IOM uint32_t reg; /*!< FIFO configuration register. */ - - struct { - __IOM uint32_t RXFIFO_WM_THRHD : 4; /*!< Configures the water mark threshold of RXFIFO in nonfifo access - mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter - is bigger than reg_rxfifo_wm_thrhd[3:0], reg_rxfifo_wm_int_raw - bit will be valid. */ - uint32_t : 1; - __IOM uint32_t TXFIFO_WM_THRHD : 4; /*!< Configures the water mark threshold of TXFIFO in nonfifo access - mode. When reg_reg_fifo_prt_en is 1 and tx FIFO counter - is smaller than reg_txfifo_wm_thrhd[3:0], reg_txfifo_wm_int_raw - bit will be valid. */ - uint32_t : 1; - __IOM uint32_t NONFIFO_EN : 1; /*!< Configures to enable APB nonfifo access. */ - uint32_t : 1; - __IOM uint32_t RX_FIFO_RST : 1; /*!< Configures to reset RXFIFO.0: No effect1: Reset */ - __IOM uint32_t TX_FIFO_RST : 1; /*!< Configures to reset TXFIFO.0: No effect1: Reset */ - __IOM uint32_t FIFO_PRT_EN : 1; /*!< Configures to enable FIFO pointer in non-fifo access mode. This - bit controls the valid bits and the TX/RX FIFO overflow, - underflow, full and empty interrupts.0: No effect1: Enable */ - uint32_t : 17; - } bit; - } FIFO_CONF; - - union { - __IOM uint32_t reg; /*!< Rx FIFO read data. */ - - struct { - __IM uint32_t FIFO_RDATA : 8; /*!< Represents the value of RXFIFO read data. */ - uint32_t : 24; - } bit; - } DATA; - - union { - __IOM uint32_t reg; /*!< Raw interrupt status */ - - struct { - __IM uint32_t RXFIFO_WM_INT_RAW : 1; /*!< The raw interrupt status of I2C_RXFIFO_WM_INT interrupt. */ - __IM uint32_t TXFIFO_WM_INT_RAW : 1; /*!< The raw interrupt status of I2C_TXFIFO_WM_INT interrupt. */ - __IM uint32_t RXFIFO_OVF_INT_RAW : 1; /*!< The raw interrupt status of I2C_RXFIFO_OVF_INT interrupt. */ - __IM uint32_t END_DETECT_INT_RAW : 1; /*!< The raw interrupt status of the I2C_END_DETECT_INT interrupt. */ - __IM uint32_t BYTE_TRANS_DONE_INT_RAW : 1;/*!< The raw interrupt status of the I2C_END_DETECT_INT interrupt. */ - __IM uint32_t ARBITRATION_LOST_INT_RAW : 1;/*!< The raw interrupt status of the I2C_ARBITRATION_LOST_INT interrupt. */ - __IM uint32_t MST_TXFIFO_UDF_INT_RAW : 1;/*!< The raw interrupt status of I2C_TRANS_COMPLETE_INT interrupt. */ - __IM uint32_t TRANS_COMPLETE_INT_RAW : 1;/*!< The raw interrupt status of the I2C_TRANS_COMPLETE_INT interrupt. */ - __IM uint32_t TIME_OUT_INT_RAW : 1; /*!< The raw interrupt status of the I2C_TIME_OUT_INT interrupt. */ - __IM uint32_t TRANS_START_INT_RAW : 1; /*!< The raw interrupt status of the I2C_TRANS_START_INT interrupt. */ - __IM uint32_t NACK_INT_RAW : 1; /*!< The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt. */ - __IM uint32_t TXFIFO_OVF_INT_RAW : 1; /*!< The raw interrupt status of I2C_TXFIFO_OVF_INT interrupt. */ - __IM uint32_t RXFIFO_UDF_INT_RAW : 1; /*!< The raw interrupt status of I2C_RXFIFO_UDF_INT interrupt. */ - __IM uint32_t SCL_ST_TO_INT_RAW : 1; /*!< The raw interrupt status of I2C_SCL_ST_TO_INT interrupt. */ - __IM uint32_t SCL_MAIN_ST_TO_INT_RAW : 1;/*!< The raw interrupt status of I2C_SCL_MAIN_ST_TO_INT interrupt. */ - __IM uint32_t DET_START_INT_RAW : 1; /*!< The raw interrupt status of I2C_DET_START_INT interrupt. */ - uint32_t : 16; - } bit; - } INT_RAW; - - union { - __IOM uint32_t reg; /*!< Interrupt clear bits */ - - struct { - __OM uint32_t RXFIFO_WM_INT_CLR : 1; /*!< Write 1 to clear I2C_RXFIFO_WM_INT interrupt. */ - __OM uint32_t TXFIFO_WM_INT_CLR : 1; /*!< Write 1 to clear I2C_TXFIFO_WM_INT interrupt. */ - __OM uint32_t RXFIFO_OVF_INT_CLR : 1; /*!< Write 1 to clear I2C_RXFIFO_OVF_INT interrupt. */ - __OM uint32_t END_DETECT_INT_CLR : 1; /*!< Write 1 to clear the I2C_END_DETECT_INT interrupt. */ - __OM uint32_t BYTE_TRANS_DONE_INT_CLR : 1;/*!< Write 1 to clear the I2C_END_DETECT_INT interrupt. */ - __OM uint32_t ARBITRATION_LOST_INT_CLR : 1;/*!< Write 1 to clear the I2C_ARBITRATION_LOST_INT interrupt. */ - __OM uint32_t MST_TXFIFO_UDF_INT_CLR : 1;/*!< Write 1 to clear I2C_TRANS_COMPLETE_INT interrupt. */ - __OM uint32_t TRANS_COMPLETE_INT_CLR : 1;/*!< Write 1 to clear the I2C_TRANS_COMPLETE_INT interrupt. */ - __OM uint32_t TIME_OUT_INT_CLR : 1; /*!< Write 1 to clear the I2C_TIME_OUT_INT interrupt. */ - __OM uint32_t TRANS_START_INT_CLR : 1; /*!< Write 1 to clear the I2C_TRANS_START_INT interrupt. */ - __OM uint32_t NACK_INT_CLR : 1; /*!< Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt. */ - __OM uint32_t TXFIFO_OVF_INT_CLR : 1; /*!< Write 1 to clear I2C_TXFIFO_OVF_INT interrupt. */ - __OM uint32_t RXFIFO_UDF_INT_CLR : 1; /*!< Write 1 to clear I2C_RXFIFO_UDF_INT interrupt. */ - __OM uint32_t SCL_ST_TO_INT_CLR : 1; /*!< Write 1 to clear I2C_SCL_ST_TO_INT interrupt. */ - __OM uint32_t SCL_MAIN_ST_TO_INT_CLR : 1;/*!< Write 1 to clear I2C_SCL_MAIN_ST_TO_INT interrupt. */ - __OM uint32_t DET_START_INT_CLR : 1; /*!< Write 1 to clear I2C_DET_START_INT interrupt. */ - uint32_t : 16; - } bit; - } INT_CLR; - - union { - __IOM uint32_t reg; /*!< Interrupt enable bits */ - - struct { - __IOM uint32_t RXFIFO_WM_INT_ENA : 1; /*!< Write 1 to anable I2C_RXFIFO_WM_INT interrupt. */ - __IOM uint32_t TXFIFO_WM_INT_ENA : 1; /*!< Write 1 to anable I2C_TXFIFO_WM_INT interrupt. */ - __IOM uint32_t RXFIFO_OVF_INT_ENA : 1; /*!< Write 1 to anable I2C_RXFIFO_OVF_INT interrupt. */ - __IOM uint32_t END_DETECT_INT_ENA : 1; /*!< Write 1 to anable the I2C_END_DETECT_INT interrupt. */ - __IOM uint32_t BYTE_TRANS_DONE_INT_ENA : 1;/*!< Write 1 to anable the I2C_END_DETECT_INT interrupt. */ - __IOM uint32_t ARBITRATION_LOST_INT_ENA : 1;/*!< Write 1 to anable the I2C_ARBITRATION_LOST_INT interrupt. */ - __IOM uint32_t MST_TXFIFO_UDF_INT_ENA : 1;/*!< Write 1 to anable I2C_TRANS_COMPLETE_INT interrupt. */ - __IOM uint32_t TRANS_COMPLETE_INT_ENA : 1;/*!< Write 1 to anable the I2C_TRANS_COMPLETE_INT interrupt. */ - __IOM uint32_t TIME_OUT_INT_ENA : 1; /*!< Write 1 to anable the I2C_TIME_OUT_INT interrupt. */ - __IOM uint32_t TRANS_START_INT_ENA : 1; /*!< Write 1 to anable the I2C_TRANS_START_INT interrupt. */ - __IOM uint32_t NACK_INT_ENA : 1; /*!< Write 1 to anable I2C_SLAVE_STRETCH_INT interrupt. */ - __IOM uint32_t TXFIFO_OVF_INT_ENA : 1; /*!< Write 1 to anable I2C_TXFIFO_OVF_INT interrupt. */ - __IOM uint32_t RXFIFO_UDF_INT_ENA : 1; /*!< Write 1 to anable I2C_RXFIFO_UDF_INT interrupt. */ - __IOM uint32_t SCL_ST_TO_INT_ENA : 1; /*!< Write 1 to anable I2C_SCL_ST_TO_INT interrupt. */ - __IOM uint32_t SCL_MAIN_ST_TO_INT_ENA : 1;/*!< Write 1 to anable I2C_SCL_MAIN_ST_TO_INT interrupt. */ - __IOM uint32_t DET_START_INT_ENA : 1; /*!< Write 1 to anable I2C_DET_START_INT interrupt. */ - uint32_t : 16; - } bit; - } INT_ENA; - - union { - __IOM uint32_t reg; /*!< Status of captured I2C communication events */ - - struct { - __IM uint32_t RXFIFO_WM_INT_ST : 1; /*!< The masked interrupt status status of I2C_RXFIFO_WM_INT interrupt. */ - __IM uint32_t TXFIFO_WM_INT_ST : 1; /*!< The masked interrupt status status of I2C_TXFIFO_WM_INT interrupt. */ - __IM uint32_t RXFIFO_OVF_INT_ST : 1; /*!< The masked interrupt status status of I2C_RXFIFO_OVF_INT interrupt. */ - __IM uint32_t END_DETECT_INT_ST : 1; /*!< The masked interrupt status status of the I2C_END_DETECT_INT - interrupt. */ - __IM uint32_t BYTE_TRANS_DONE_INT_ST : 1;/*!< The masked interrupt status status of the I2C_END_DETECT_INT - interrupt. */ - __IM uint32_t ARBITRATION_LOST_INT_ST : 1;/*!< The masked interrupt status status of the I2C_ARBITRATION_LOST_INT - interrupt. */ - __IM uint32_t MST_TXFIFO_UDF_INT_ST : 1; /*!< The masked interrupt status status of I2C_TRANS_COMPLETE_INT - interrupt. */ - __IM uint32_t TRANS_COMPLETE_INT_ST : 1; /*!< The masked interrupt status status of the I2C_TRANS_COMPLETE_INT - interrupt. */ - __IM uint32_t TIME_OUT_INT_ST : 1; /*!< The masked interrupt status status of the I2C_TIME_OUT_INT interrupt. */ - __IM uint32_t TRANS_START_INT_ST : 1; /*!< The masked interrupt status status of the I2C_TRANS_START_INT - interrupt. */ - __IM uint32_t NACK_INT_ST : 1; /*!< The masked interrupt status status of I2C_SLAVE_STRETCH_INT - interrupt. */ - __IM uint32_t TXFIFO_OVF_INT_ST : 1; /*!< The masked interrupt status status of I2C_TXFIFO_OVF_INT interrupt. */ - __IM uint32_t RXFIFO_UDF_INT_ST : 1; /*!< The masked interrupt status status of I2C_RXFIFO_UDF_INT interrupt. */ - __IM uint32_t SCL_ST_TO_INT_ST : 1; /*!< The masked interrupt status status of I2C_SCL_ST_TO_INT interrupt. */ - __IM uint32_t SCL_MAIN_ST_TO_INT_ST : 1; /*!< The masked interrupt status status of I2C_SCL_MAIN_ST_TO_INT - interrupt. */ - __IM uint32_t DET_START_INT_ST : 1; /*!< The masked interrupt status status of I2C_DET_START_INT interrupt. */ - uint32_t : 16; - } bit; - } INT_STATUS; - - union { - __IOM uint32_t reg; /*!< Configures the hold time after a negative SCL edge. */ - - struct { - __IOM uint32_t TIME : 9; /*!< Configures the time to hold the data after the falling edge - of SCL.Measurement unit: i2c_sclk */ - uint32_t : 23; - } bit; - } SDA_HOLD; - - union { - __IOM uint32_t reg; /*!< Configures the sample time after a positive SCL edge. */ - - struct { - __IOM uint32_t TIME : 9; /*!< Configures the sample time after a positive SCL edge.Measurement - unit: i2c_sclk */ - uint32_t : 23; - } bit; - } SDA_SAMPLE; - - union { - __IOM uint32_t reg; /*!< Configures the high level width of SCL */ - - struct { - __IOM uint32_t SCL_HIGH_PERIOD : 9; /*!< Configures for how long SCL remains high in master mode.Measurement - unit: i2c_sclk */ - __IOM uint32_t SCL_WAIT_HIGH_PERIOD : 7; /*!< Configures the SCL_FSM's waiting period for SCL high level in - master mode.Measurement unit: i2c_sclk */ - uint32_t : 16; - } bit; - } SCL_HIGH_PERIOD; - __IM uint32_t RESERVED1; - - union { - __IOM uint32_t reg; /*!< Configures the delay between the SDA and SCL negative edge for - a start condition */ - - struct { - __IOM uint32_t TIME : 9; /*!< Configures the time between the falling edge of SDA and the - falling edge of SCL for a START condition.Measurement unit: - i2c_sclk. */ - uint32_t : 23; - } bit; - } SCL_START_HOLD; - - union { - __IOM uint32_t reg; /*!< Configures the delay between the positiveedge of SCL and the - negative edge of SDA */ - - struct { - __IOM uint32_t TIME : 9; /*!< Configures the time between the positive edge of SCL and the - negative edge of SDA for a RESTART condition.Measurement - unit: i2c_sclk */ - uint32_t : 23; - } bit; - } SCL_RSTART_SETUP; - - union { - __IOM uint32_t reg; /*!< Configures the delay after the SCL clockedge for a stop condition */ - - struct { - __IOM uint32_t TIME : 9; /*!< Configures the delay after the STOP condition.Measurement unit: - i2c_sclk */ - uint32_t : 23; - } bit; - } SCL_STOP_HOLD; - - union { - __IOM uint32_t reg; /*!< Configures the delay between the SDA andSCL positive edge for - a stop condition */ - - struct { - __IOM uint32_t TIME : 9; /*!< Configures the time between the rising edge of SCL and the rising - edge of SDA.Measurement unit: i2c_sclk */ - uint32_t : 23; - } bit; - } SCL_STOP_SETUP; - - union { - __IOM uint32_t reg; /*!< SCL and SDA filter configuration register */ - - struct { - __IOM uint32_t SCL_FILTER_THRES : 4; /*!< Configures the threshold pulse width to be filtered on SCL. - When a pulse on the SCL input has smaller width than this - register value, the I2C controller will ignore that pulse. - Measurement unit: i2c_sclk */ - __IOM uint32_t SDA_FILTER_THRES : 4; /*!< Configures the threshold pulse width to be filtered on SDA. - When a pulse on the SDA input has smaller width than this - register value, the I2C controller will ignore that pulse. - Measurement unit: i2c_sclk */ - __IOM uint32_t SCL_FILTER_EN : 1; /*!< Configures to enable the filter function for SCL. */ - __IOM uint32_t SDA_FILTER_EN : 1; /*!< Configures to enable the filter function for SDA. */ - uint32_t : 22; - } bit; - } FILTER_CFG; - - union { - __IOM uint32_t reg; /*!< I2C CLK configuration register */ - - struct { - __IOM uint32_t SCLK_DIV_NUM : 8; /*!< the integral part of the fractional divisor for i2c module */ - __IOM uint32_t SCLK_DIV_A : 6; /*!< the numerator of the fractional part of the fractional divisor - for i2c module */ - __IOM uint32_t SCLK_DIV_B : 6; /*!< the denominator of the fractional part of the fractional divisor - for i2c module */ - __IOM uint32_t SCLK_SEL : 1; /*!< The clock selection for i2c module:0-XTAL,1-CLK_8MHz. */ - __IOM uint32_t SCLK_ACTIVE : 1; /*!< The clock switch for i2c module */ - uint32_t : 10; - } bit; - } CLK_CONF; - - union { - __IOM uint32_t reg; /*!< I2C command register 0 */ - - struct { - __IOM uint32_t COMMAND0 : 14; /*!< Configures command 0. It consists of three parts: op_code is - the command,0: RSTART, 1: WRITE,2: READ,3: STOP,4: END.Byte_num - represents the number of bytes that need to be sent or - received.ack_check_en, ack_exp and ack are used to control - the ACK bit. See I2C cmd structure for more information. */ - uint32_t : 17; - __IOM uint32_t COMMAND0_DONE : 1; /*!< Represents whether command 0 is done in I2C Master mode.0: Not - done1: Done */ - } bit; - } COMD0; - - union { - __IOM uint32_t reg; /*!< I2C command register 1 */ - - struct { - __IOM uint32_t COMMAND1 : 14; /*!< Configures command 1. See details in I2C_CMD0_REG[13:0]. */ - uint32_t : 17; - __IOM uint32_t COMMAND1_DONE : 1; /*!< Represents whether command 1 is done in I2C Master mode.0: Not - done1: Done */ - } bit; - } COMD1; - - union { - __IOM uint32_t reg; /*!< I2C command register 2 */ - - struct { - __IOM uint32_t COMMAND2 : 14; /*!< Configures command 2. See details in I2C_CMD0_REG[13:0]. */ - uint32_t : 17; - __IOM uint32_t COMMAND2_DONE : 1; /*!< Represents whether command 2 is done in I2C Master mode.0: Not - done1: Done */ - } bit; - } COMD2; - - union { - __IOM uint32_t reg; /*!< I2C command register 3 */ - - struct { - __IOM uint32_t COMMAND3 : 14; /*!< Configures command 3. See details in I2C_CMD0_REG[13:0]. */ - uint32_t : 17; - __IOM uint32_t COMMAND3_DONE : 1; /*!< Represents whether command 3 is done in I2C Master mode.0: Not - done1: Done */ - } bit; - } COMD3; - - union { - __IOM uint32_t reg; /*!< I2C command register 4 */ - - struct { - __IOM uint32_t COMMAND4 : 14; /*!< Configures command 4. See details in I2C_CMD0_REG[13:0]. */ - uint32_t : 17; - __IOM uint32_t COMMAND4_DONE : 1; /*!< Represents whether command 4 is done in I2C Master mode.0: Not - done1: Done */ - } bit; - } COMD4; - - union { - __IOM uint32_t reg; /*!< I2C command register 5 */ - - struct { - __IOM uint32_t COMMAND5 : 14; /*!< Configures command 5. See details in I2C_CMD0_REG[13:0]. */ - uint32_t : 17; - __IOM uint32_t COMMAND5_DONE : 1; /*!< Represents whether command 5 is done in I2C Master mode.0: Not - done1: Done */ - } bit; - } COMD5; - - union { - __IOM uint32_t reg; /*!< I2C command register 6 */ - - struct { - __IOM uint32_t COMMAND6 : 14; /*!< Configures command 6. See details in I2C_CMD0_REG[13:0]. */ - uint32_t : 17; - __IOM uint32_t COMMAND6_DONE : 1; /*!< Represents whether command 6 is done in I2C Master mode.0: Not - done1: Done */ - } bit; - } COMD6; - - union { - __IOM uint32_t reg; /*!< I2C command register 7 */ - - struct { - __IOM uint32_t COMMAND7 : 14; /*!< Configures command 7. See details in I2C_CMD0_REG[13:0]. */ - uint32_t : 17; - __IOM uint32_t COMMAND7_DONE : 1; /*!< Represents whether command 7 is done in I2C Master mode.0: Not - done1: Done */ - } bit; - } COMD7; - - union { - __IOM uint32_t reg; /*!< SCL status time out register */ - - struct { - __IOM uint32_t SCL_ST_TO_I2C : 5; /*!< Configures the threshold value of SCL_FSM state unchanged period. - It should be no more than 23.Measurement unit: i2c_sclk */ - uint32_t : 27; - } bit; - } SCL_ST_TIME_OUT; - - union { - __IOM uint32_t reg; /*!< SCL main status time out register */ - - struct { - __IOM uint32_t SCL_MAIN_ST_TO_I2C : 5; /*!< Configures the threshold value of SCL_MAIN_FSM state unchanged - period.nIt should be no more than 23.Measurement unit: - i2c_sclk */ - uint32_t : 27; - } bit; - } SCL_MAIN_ST_TIME_OUT; - - union { - __IOM uint32_t reg; /*!< Power configuration register */ - - struct { - __IOM uint32_t SCL_RST_SLV_EN : 1; /*!< When I2C master is IDLE, set this bit to send out SCL pulses. - The number of pulses equals to reg_scl_rst_slv_num[4:0]. */ - __IOM uint32_t SCL_RST_SLV_NUM : 5; /*!< Configures to send out SCL pulses when I2C master is IDLE. The - number of pulses equals to reg_scl_rst_slv_num[4:0]. */ - __IOM uint32_t SCL_PD_EN : 1; /*!< Configure the pulses of SCL generated in I2C master mode. Valid - when reg_scl_rst_slv_en is 1.Measurement unit: i2c_sclk */ - __IOM uint32_t SDA_PD_EN : 1; /*!< Configures to power down the I2C output SCL line. 0: Not power - down.1: Power down.Valid only when reg_scl_force_out is - 1. */ - uint32_t : 24; - } bit; - } SCL_SP_CONF; - __IM uint32_t RESERVED2[29]; - - union { - __IOM uint32_t reg; /*!< Version register */ - - struct { - __IOM uint32_t DATE : 32; /*!< Version control register. */ - } bit; - } DATE; - __IM uint32_t RESERVED3; - - union { - __IOM uint32_t reg; /*!< I2C TXFIFO base address register */ - - struct { - __IM uint32_t TXFIFO_START_ADDR : 32; /*!< Represents the I2C txfifo first address. */ - } bit; - } TXFIFO_START_ADDR; - __IM uint32_t RESERVED4[31]; - - union { - __IOM uint32_t reg; /*!< I2C RXFIFO base address register */ - - struct { - __IM uint32_t RXFIFO_START_ADDR : 32; /*!< Represents the I2C rxfifo first address. */ - } bit; - } RXFIFO_START_ADDR; -} LP_I2C0_Type; /*!< Size = 388 (0x184) */ - - - -/* =========================================================================================================================== */ -/* ================ LP_I2S0 ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Low-power I2S (Inter-IC Sound) Controller 0 (LP_I2S0) - */ - -typedef struct { /*!< LP_I2S0 Structure */ - - union { - __IOM uint32_t reg; /*!< I2S VAD Configure register */ - - struct { - __IOM uint32_t VAD_EN : 1; /*!< VAD enable register */ - __OM uint32_t VAD_RESET : 1; /*!< VAD reset register */ - __OM uint32_t VAD_FORCE_START : 1; /*!< VAD force start register. */ - uint32_t : 29; - } bit; - } VAD_CONF; - - union { - __IOM uint32_t reg; /*!< I2S VAD Result register */ - - struct { - __IM uint32_t VAD_FLAG : 1; /*!< Reg vad flag observe signal */ - __IM uint32_t ENERGY_ENOUGH : 1; /*!< Reg energy enough observe signal */ - uint32_t : 30; - } bit; - } VAD_RESULT; - - union { - __IOM uint32_t reg; /*!< I2S VAD Observe register */ - - struct { - __IM uint32_t RX_MEM_FIFO_CNT : 9; /*!< The number of data in the rx mem */ - __IOM uint32_t RX_MEM_THRESHOLD : 8; /*!< I2S rx mem will trigger an interrupt when the data in the mem - is over(not including equal) reg_rx_mem_threshold */ - uint32_t : 15; - } bit; - } RX_MEM_CONF; - - union { - __IOM uint32_t reg; /*!< I2S interrupt raw register, valid in level. */ - - struct { - __IM uint32_t RX_DONE_INT_RAW : 1; /*!< The raw interrupt status bit for the i2s_rx_done_int interrupt */ - __IM uint32_t RX_HUNG_INT_RAW : 1; /*!< The raw interrupt status bit for the i2s_rx_hung_int interrupt */ - __IM uint32_t RX_FIFOMEM_UDF_INT_RAW : 1;/*!< The raw interrupt status bit for the i2s_rx_fifomem_udf_int - interrupt */ - __IM uint32_t VAD_DONE_INT_RAW : 1; /*!< The raw interrupt status bit for the vad_done_int interrupt */ - __IM uint32_t VAD_RESET_DONE_INT_RAW : 1;/*!< The raw interrupt status bit for the vad_reset_done_int interrupt */ - __IM uint32_t RX_MEM_THRESHOLD_INT_RAW : 1;/*!< The raw interrupt status bit for the rx_mem_threshold_int interrupt */ - uint32_t : 26; - } bit; - } INT_RAW; - - union { - __IOM uint32_t reg; /*!< I2S interrupt status register. */ - - struct { - __IM uint32_t RX_DONE_INT_ST : 1; /*!< The masked interrupt status bit for the i2s_rx_done_int interrupt */ - __IM uint32_t RX_HUNG_INT_ST : 1; /*!< The masked interrupt status bit for the i2s_rx_hung_int interrupt */ - __IM uint32_t RX_FIFOMEM_UDF_INT_ST : 1; /*!< The masked interrupt status bit for the i2s_rx_fifomem_udf_int - interrupt */ - __IM uint32_t LP_VAD_DONE_INT_ST : 1; /*!< The masked interrupt status bit for the vad_done_int interrupt */ - __IM uint32_t LP_VAD_RESET_DONE_INT_ST : 1;/*!< The masked interrupt status bit for the vad_reset_done_int interrupt */ - __IM uint32_t RX_MEM_THRESHOLD_INT_ST : 1;/*!< The masked interrupt status bit for the rx_mem_threshold_int - interrupt */ - uint32_t : 26; - } bit; - } INT_ST; - - union { - __IOM uint32_t reg; /*!< I2S interrupt enable register. */ - - struct { - __IOM uint32_t RX_DONE_INT_ENA : 1; /*!< The interrupt enable bit for the i2s_rx_done_int interrupt */ - __IOM uint32_t RX_HUNG_INT_ENA : 1; /*!< The interrupt enable bit for the i2s_rx_hung_int interrupt */ - __IOM uint32_t RX_FIFOMEM_UDF_INT_ENA : 1;/*!< The interrupt enable bit for the i2s_rx_fifomem_udf_int interrupt */ - __IOM uint32_t LP_VAD_DONE_INT_ENA : 1; /*!< The interrupt enable bit for the vad_done_int interrupt */ - __IOM uint32_t LP_VAD_RESET_DONE_INT_ENA : 1;/*!< The interrupt enable bit for the vad_reset_done_int interrupt */ - __IOM uint32_t RX_MEM_THRESHOLD_INT_ENA : 1;/*!< The interrupt enable bit for the rx_mem_threshold_int interrupt */ - uint32_t : 26; - } bit; - } INT_ENA; - - union { - __IOM uint32_t reg; /*!< I2S interrupt clear register. */ - - struct { - __OM uint32_t RX_DONE_INT_CLR : 1; /*!< Set this bit to clear the i2s_rx_done_int interrupt */ - __OM uint32_t RX_HUNG_INT_CLR : 1; /*!< Set this bit to clear the i2s_rx_hung_int interrupt */ - __OM uint32_t RX_FIFOMEM_UDF_INT_CLR : 1;/*!< Set this bit to clear the i2s_rx_fifomem_udf_int interrupt */ - __OM uint32_t LP_VAD_DONE_INT_CLR : 1; /*!< Set this bit to clear the vad_done_int interrupt */ - __OM uint32_t LP_VAD_RESET_DONE_INT_CLR : 1;/*!< Set this bit to clear the vad_reset_done_int interrupt */ - __OM uint32_t RX_MEM_THRESHOLD_INT_CLR : 1;/*!< Set this bit to clear the rx_mem_threshold_int interrupt */ - uint32_t : 26; - } bit; - } INT_CLR; - __IM uint32_t RESERVED; - - union { - __IOM uint32_t reg; /*!< I2S RX configure register */ - - struct { - __OM uint32_t RX_RESET : 1; /*!< Set this bit to reset receiver */ - __OM uint32_t RX_FIFO_RESET : 1; /*!< Set this bit to reset Rx AFIFO */ - __IOM uint32_t RX_START : 1; /*!< Set this bit to start receiving data */ - __IOM uint32_t RX_SLAVE_MOD : 1; /*!< Set this bit to enable slave receiver mode */ - __OM uint32_t RX_FIFOMEM_RESET : 1; /*!< Set this bit to reset Rx Syncfifomem */ - __IOM uint32_t RX_MONO : 1; /*!< Set this bit to enable receiver in mono mode */ - uint32_t : 1; - __IOM uint32_t RX_BIG_ENDIAN : 1; /*!< I2S Rx byte endian, 1: low addr value to high addr. 0: low addr - with low addr value. */ - __IOM uint32_t RX_UPDATE : 1; /*!< Set 1 to update I2S RX registers from APB clock domain to I2S - RX clock domain. This bit will be cleared by hardware after - update register done. */ - __IOM uint32_t RX_MONO_FST_VLD : 1; /*!< 1: The first channel data value is valid in I2S RX mono mode. - 0: The second channel data value is valid in I2S RX mono - mode. */ - __IOM uint32_t RX_PCM_CONF : 2; /*!< I2S RX compress/decompress configuration bit. & 0 (atol): A-Law - decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law - decompress, 3 (ltou) : u-Law compress. & */ - __IOM uint32_t RX_PCM_BYPASS : 1; /*!< Set this bit to bypass Compress/Decompress module for received - data. */ - __IOM uint32_t RX_STOP_MODE : 2; /*!< 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when - reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when - reg_rx_start is 0 or RX FIFO is full. */ - __IOM uint32_t RX_LEFT_ALIGN : 1; /*!< 1: I2S RX left alignment mode. 0: I2S RX right alignment mode. */ - __IOM uint32_t RX_24_FILL_EN : 1; /*!< 1: store 24 channel bits to 32 bits. 0:store 24 channel bits - to 24 bits. */ - __IOM uint32_t RX_WS_IDLE_POL : 1; /*!< 0: WS should be 0 when receiving left channel data, and WS is - 1in right channel. 1: WS should be 1 when receiving left - channel data, and WS is 0in right channel. */ - __IOM uint32_t RX_BIT_ORDER : 1; /*!< I2S Rx bit endian. 1:small endian, the LSB is received first. - 0:big endian, the MSB is received first. */ - __IOM uint32_t RX_TDM_EN : 1; /*!< 1: Enable I2S TDM Rx mode . 0: Disable. */ - __IOM uint32_t RX_PDM_EN : 1; /*!< 1: Enable I2S PDM Rx mode . 0: Disable. */ - uint32_t : 11; - } bit; - } RX_CONF; - __IM uint32_t RESERVED1; - - union { - __IOM uint32_t reg; /*!< I2S RX configure register 1 */ - - struct { - __IOM uint32_t RX_TDM_WS_WIDTH : 7; /*!< The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH[6:0] - +1) * T_bck */ - __IOM uint32_t RX_BCK_DIV_NUM : 6; /*!< Bit clock configuration bits in receiver mode. */ - __IOM uint32_t RX_BITS_MOD : 5; /*!< Set the bits to configure the valid data bit length of I2S receiver - channel. 7: all the valid channel data is in 8-bit-mode. - 15: all the valid channel data is in 16-bit-mode. 23: all - the valid channel data is in 24-bit-mode. 31:all the valid - channel data is in 32-bit-mode. */ - __IOM uint32_t RX_HALF_SAMPLE_BITS : 6; /*!< I2S Rx half sample bits -1. */ - __IOM uint32_t RX_TDM_CHAN_BITS : 5; /*!< The Rx bit number for each channel minus 1in TDM mode. */ - __IOM uint32_t RX_MSB_SHIFT : 1; /*!< Set this bit to enable receiver in Phillips standard mode */ - uint32_t : 2; - } bit; - } RX_CONF1; - __IM uint32_t RESERVED2[9]; - - union { - __IOM uint32_t reg; /*!< I2S TX TDM mode control register */ - - struct { - __IOM uint32_t RX_TDM_PDM_CHAN0_EN : 1; /*!< 1: Enable the valid data input of I2S RX TDM or PDM channel - 0. 0: Disable, just input 0 in this channel. */ - __IOM uint32_t RX_TDM_PDM_CHAN1_EN : 1; /*!< 1: Enable the valid data input of I2S RX TDM or PDM channel - 1. 0: Disable, just input 0 in this channel. */ - uint32_t : 14; - __IOM uint32_t RX_TDM_TOT_CHAN_NUM : 4; /*!< The total channel number of I2S TX TDM mode. */ - uint32_t : 12; - } bit; - } RX_TDM_CTRL; - __IM uint32_t RESERVED3; - - union { - __IOM uint32_t reg; /*!< I2S RX timing control register */ - - struct { - __IOM uint32_t RX_SD_IN_DM : 2; /*!< The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay - by pos edge. 2: delay by neg edge. 3: not used. */ - uint32_t : 14; - __IOM uint32_t RX_WS_OUT_DM : 2; /*!< The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay - by pos edge. 2: delay by neg edge. 3: not used. */ - uint32_t : 2; - __IOM uint32_t RX_BCK_OUT_DM : 2; /*!< The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay - by pos edge. 2: delay by neg edge. 3: not used. */ - uint32_t : 2; - __IOM uint32_t RX_WS_IN_DM : 2; /*!< The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay - by pos edge. 2: delay by neg edge. 3: not used. */ - uint32_t : 2; - __IOM uint32_t RX_BCK_IN_DM : 2; /*!< The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay - by pos edge. 2: delay by neg edge. 3: not used. */ - uint32_t : 2; - } bit; - } RX_TIMING; - __IM uint32_t RESERVED4; - - union { - __IOM uint32_t reg; /*!< I2S HUNG configure register. */ - - struct { - __IOM uint32_t LC_FIFO_TIMEOUT : 8; /*!< the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt - will be triggered when fifo hung counter is equal to this - value */ - __IOM uint32_t LC_FIFO_TIMEOUT_SHIFT : 3; /*!< The bits are used to scale tick counter threshold. The tick - counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift */ - __IOM uint32_t LC_FIFO_TIMEOUT_ENA : 1; /*!< The enable bit for FIFO timeout */ - uint32_t : 20; - } bit; - } LC_HUNG_CONF; - - union { - __IOM uint32_t reg; /*!< I2S RX data number control register. */ - - struct { - __IOM uint32_t RX_EOF_NUM : 12; /*!< The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * - (REG_RX_EOF_NUM[11:0] + 1) . It will trigger in_suc_eof - interrupt in the configured DMA RX channel. */ - uint32_t : 20; - } bit; - } RXEOF_NUM; - - union { - __IOM uint32_t reg; /*!< I2S signal data register */ - - struct { - __IOM uint32_t SINGLE_DATA : 32; /*!< The configured constant channel data to be sent out. */ - } bit; - } CONF_SIGLE_DATA; - __IM uint32_t RESERVED5; - - union { - __IOM uint32_t reg; /*!< I2S RX configure register */ - - struct { - uint32_t : 19; - __IOM uint32_t RX_PDM2PCM_EN : 1; /*!< 1: Enable PDM2PCM RX mode. 0: DIsable. */ - __IOM uint32_t RX_PDM_SINC_DSR_16_EN : 1; /*!< Configure the down sampling rate of PDM RX filter group1 module. - 1: The down sampling rate is 128. 0: down sampling rate - is 64. */ - __IOM uint32_t RX_PDM2PCM_AMPLIFY_NUM : 4;/*!< Configure PDM RX amplify number. */ - __IOM uint32_t RX_PDM_HP_BYPASS : 1; /*!< I2S PDM RX bypass hp filter or not. */ - __IOM uint32_t RX_IIR_HP_MULT12_5 : 3; /*!< The fourth parameter of PDM RX IIR_HP filter stage 2 is (504 - + LP_I2S_RX_IIR_HP_MULT12_5[2:0]) */ - __IOM uint32_t RX_IIR_HP_MULT12_0 : 3; /*!< The fourth parameter of PDM RX IIR_HP filter stage 1 is (504 - + LP_I2S_RX_IIR_HP_MULT12_0[2:0]) */ - } bit; - } RX_PDM_CONF; - - union { - __IOM uint32_t reg; /*!< I2S ECO register */ - - struct { - __IOM uint32_t RDN_ECO_LOW : 32; /*!< logic low eco registers */ - } bit; - } ECO_LOW; - - union { - __IOM uint32_t reg; /*!< I2S ECO register */ - - struct { - __IOM uint32_t RDN_ECO_HIGH : 32; /*!< logic high eco registers */ - } bit; - } ECO_HIGH; - - union { - __IOM uint32_t reg; /*!< I2S ECO register */ - - struct { - __IOM uint32_t RDN_ENA : 1; /*!< enable rdn counter bit */ - __IM uint32_t RDN_RESULT : 1; /*!< rdn result */ - uint32_t : 30; - } bit; - } ECO_CONF; - - union { - __IOM uint32_t reg; /*!< I2S VAD Parameter register */ - - struct { - __IOM uint32_t PARAM_MIN_ENERGY : 16; /*!< VAD parameter */ - __IOM uint32_t PARAM_INIT_FRAME_NUM : 9; /*!< VAD parameter */ - uint32_t : 7; - } bit; - } VAD_PARAM0; - - union { - __IOM uint32_t reg; /*!< I2S VAD Parameter register */ - - struct { - __IOM uint32_t PARAM_MIN_SPEECH_COUNT : 4;/*!< VAD parameter */ - __IOM uint32_t PARAM_MAX_SPEECH_COUNT : 7;/*!< VAD parameter */ - __IOM uint32_t PARAM_HANGOVER_SPEECH : 5; /*!< VAD parameter */ - __IOM uint32_t PARAM_HANGOVER_SILENT : 8; /*!< VAD parameter */ - __IOM uint32_t PARAM_MAX_OFFSET : 7; /*!< VAD parameter */ - __IOM uint32_t PARAM_SKIP_BAND_ENERGY : 1;/*!< Set 1 to skip band energy check. */ - } bit; - } VAD_PARAM1; - - union { - __IOM uint32_t reg; /*!< I2S VAD Parameter register */ - - struct { - __IOM uint32_t PARAM_NOISE_AMP_DOWN : 16; /*!< VAD parameter */ - __IOM uint32_t PARAM_NOISE_AMP_UP : 16; /*!< VAD parameter */ - } bit; - } VAD_PARAM2; - - union { - __IOM uint32_t reg; /*!< I2S VAD Parameter register */ - - struct { - __IOM uint32_t PARAM_NOISE_SPE_UP0 : 16; /*!< VAD parameter */ - __IOM uint32_t PARAM_NOISE_SPE_UP1 : 16; /*!< VAD parameter */ - } bit; - } VAD_PARAM3; - - union { - __IOM uint32_t reg; /*!< I2S VAD Parameter register */ - - struct { - __IOM uint32_t PARAM_NOISE_SPE_DOWN : 16; /*!< VAD parameter */ - __IOM uint32_t PARAM_NOISE_MEAN_DOWN : 16;/*!< VAD parameter */ - } bit; - } VAD_PARAM4; - - union { - __IOM uint32_t reg; /*!< I2S VAD Parameter register */ - - struct { - __IOM uint32_t PARAM_NOISE_MEAN_UP0 : 16; /*!< VAD parameter */ - __IOM uint32_t PARAM_NOISE_MEAN_UP1 : 16; /*!< VAD parameter */ - } bit; - } VAD_PARAM5; - - union { - __IOM uint32_t reg; /*!< I2S VAD Parameter register */ - - struct { - __IOM uint32_t PARAM_NOISE_STD_FS_THSL : 16;/*!< Feature_sum threshold to determine noise_std max value when - vad_tag=1, equal to ((noise_std_max)>>11)^2*5 */ - __IOM uint32_t PARAM_NOISE_STD_FS_THSH : 16;/*!< Feature_sum threshold to determine noise_std max value when - vad_tag=0, equal to ((noise_std_max)>>11)^2*5 */ - } bit; - } VAD_PARAM6; - - union { - __IOM uint32_t reg; /*!< I2S VAD Parameter register */ - - struct { - __IOM uint32_t PARAM_THRES_UPD_BASE : 16; /*!< VAD parameter */ - __IOM uint32_t PARAM_THRES_UPD_VARY : 16; /*!< VAD parameter */ - } bit; - } VAD_PARAM7; - - union { - __IOM uint32_t reg; /*!< I2S VAD Parameter register */ - - struct { - __IOM uint32_t PARAM_THRES_UPD_BDL : 8; /*!< Noise_std boundary low when updating threshold. */ - __IOM uint32_t PARAM_THRES_UPD_BDH : 8; /*!< Noise_std boundary high when updating threshold. */ - __IOM uint32_t PARAM_FEATURE_BURST : 16; /*!< VAD parameter */ - } bit; - } VAD_PARAM8; - __IM uint32_t RESERVED6[3]; - - union { - __IOM uint32_t reg; /*!< I2S VAD Observe register */ - - struct { - __IM uint32_t SPEECH_COUNT_OB : 8; /*!< Reg silent count observe */ - __IM uint32_t SILENT_COUNT_OB : 8; /*!< Reg speech count observe */ - __IM uint32_t MAX_SIGNAL0_OB : 16; /*!< Reg max signal0 observe */ - } bit; - } VAD_OB0; - - union { - __IOM uint32_t reg; /*!< I2S VAD Observe register */ - - struct { - __IM uint32_t MAX_SIGNAL1_OB : 16; /*!< Reg max signal1 observe */ - __IM uint32_t MAX_SIGNAL2_OB : 16; /*!< Reg max signal2 observe */ - } bit; - } VAD_OB1; - - union { - __IOM uint32_t reg; /*!< I2S VAD Observe register */ - - struct { - __IM uint32_t NOISE_AMP_OB : 32; /*!< Reg noise_amp observe signal */ - } bit; - } VAD_OB2; - - union { - __IOM uint32_t reg; /*!< I2S VAD Observe register */ - - struct { - __IM uint32_t NOISE_MEAN_OB : 32; /*!< Reg noise_mean observe signal */ - } bit; - } VAD_OB3; - - union { - __IOM uint32_t reg; /*!< I2S VAD Observe register */ - - struct { - __IM uint32_t NOISE_STD_OB : 32; /*!< Reg noise_std observe signal */ - } bit; - } VAD_OB4; - - union { - __IOM uint32_t reg; /*!< I2S VAD Observe register */ - - struct { - __IM uint32_t OFFSET_OB : 32; /*!< Reg offset observe signal */ - } bit; - } VAD_OB5; - - union { - __IOM uint32_t reg; /*!< I2S VAD Observe register */ - - struct { - __IM uint32_t THRESHOLD_OB : 32; /*!< Reg threshold observe signal */ - } bit; - } VAD_OB6; - - union { - __IOM uint32_t reg; /*!< I2S VAD Observe register */ - - struct { - __IM uint32_t ENERGY_LOW_OB : 32; /*!< Reg energy bit 31~0 observe signal */ - } bit; - } VAD_OB7; - - union { - __IOM uint32_t reg; /*!< I2S VAD Observe register */ - - struct { - __IM uint32_t ENERGY_HIGH_OB : 32; /*!< Reg energy bit 63~32 observe signal */ - } bit; - } VAD_OB8; - __IM uint32_t RESERVED7[9]; - - union { - __IOM uint32_t reg; /*!< Clock gate register */ - - struct { - __IOM uint32_t CLK_EN : 1; /*!< set this bit to enable clock gate */ - __IOM uint32_t VAD_CG_FORCE_ON : 1; /*!< VAD clock gate force on register */ - __IOM uint32_t RX_MEM_CG_FORCE_ON : 1; /*!< I2S rx mem clock gate force on register */ - __IOM uint32_t RX_REG_CG_FORCE_ON : 1; /*!< I2S rx reg clock gate force on register */ - uint32_t : 28; - } bit; - } CLK_GATE; - - union { - __IOM uint32_t reg; /*!< Version control register */ - - struct { - __IOM uint32_t DATE : 28; /*!< I2S version control register */ - uint32_t : 4; - } bit; - } DATE; -} LP_I2S0_Type; /*!< Size = 256 (0x100) */ - - - -/* =========================================================================================================================== */ -/* ================ LP_IO_MUX ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Low-power Input/Output Multiplexer (LP_IO_MUX) - */ - -typedef struct { /*!< LP_IO_MUX Structure */ - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_CLK_EN : 1; /*!< Reserved */ - uint32_t : 31; - } bit; - } CLK_EN; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_VER_DATE : 28; /*!< Reserved */ - uint32_t : 4; - } bit; - } VER_DATE; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_PAD0_DRV : 2; /*!< Reserved */ - __IOM uint32_t REG_PAD0_RDE : 1; /*!< Reserved */ - __IOM uint32_t REG_PAD0_RUE : 1; /*!< Reserved */ - __IOM uint32_t REG_PAD0_MUX_SEL : 1; /*!< 1:use LP GPIO,0: use digital GPIO */ - __IOM uint32_t REG_PAD0_FUN_SEL : 2; /*!< function sel */ - __IOM uint32_t REG_PAD0_SLP_SEL : 1; /*!< 1: enable sleep mode during sleep,0: no sleep mode */ - __IOM uint32_t REG_PAD0_SLP_IE : 1; /*!< input enable in sleep mode */ - __IOM uint32_t REG_PAD0_SLP_OE : 1; /*!< output enable in sleep mode */ - __IOM uint32_t REG_PAD0_FUN_IE : 1; /*!< input enable in work mode */ - __IOM uint32_t REG_PAD0_FILTER_EN : 1; /*!< need des */ - uint32_t : 20; - } bit; - } PAD0; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_PAD1_DRV : 2; /*!< Reserved */ - __IOM uint32_t REG_PAD1_RDE : 1; /*!< Reserved */ - __IOM uint32_t REG_PAD1_RUE : 1; /*!< Reserved */ - __IOM uint32_t REG_PAD1_MUX_SEL : 1; /*!< 1:use LP GPIO,0: use digital GPIO */ - __IOM uint32_t REG_PAD1_FUN_SEL : 2; /*!< function sel */ - __IOM uint32_t REG_PAD1_SLP_SEL : 1; /*!< 1: enable sleep mode during sleep,0: no sleep mode */ - __IOM uint32_t REG_PAD1_SLP_IE : 1; /*!< input enable in sleep mode */ - __IOM uint32_t REG_PAD1_SLP_OE : 1; /*!< output enable in sleep mode */ - __IOM uint32_t REG_PAD1_FUN_IE : 1; /*!< input enable in work mode */ - __IOM uint32_t REG_PAD1_FILTER_EN : 1; /*!< need des */ - uint32_t : 20; - } bit; - } PAD1; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_PAD2_DRV : 2; /*!< Reserved */ - __IOM uint32_t REG_PAD2_RDE : 1; /*!< Reserved */ - __IOM uint32_t REG_PAD2_RUE : 1; /*!< Reserved */ - __IOM uint32_t REG_PAD2_MUX_SEL : 1; /*!< 1:use LP GPIO,0: use digital GPIO */ - __IOM uint32_t REG_PAD2_FUN_SEL : 2; /*!< function sel */ - __IOM uint32_t REG_PAD2_SLP_SEL : 1; /*!< 1: enable sleep mode during sleep,0: no sleep mode */ - __IOM uint32_t REG_PAD2_SLP_IE : 1; /*!< input enable in sleep mode */ - __IOM uint32_t REG_PAD2_SLP_OE : 1; /*!< output enable in sleep mode */ - __IOM uint32_t REG_PAD2_FUN_IE : 1; /*!< input enable in work mode */ - __IOM uint32_t REG_PAD2_FILTER_EN : 1; /*!< need des */ - uint32_t : 20; - } bit; - } PAD2; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_PAD3_DRV : 2; /*!< Reserved */ - __IOM uint32_t REG_PAD3_RDE : 1; /*!< Reserved */ - __IOM uint32_t REG_PAD3_RUE : 1; /*!< Reserved */ - __IOM uint32_t REG_PAD3_MUX_SEL : 1; /*!< 1:use LP GPIO,0: use digital GPIO */ - __IOM uint32_t REG_PAD3_FUN_SEL : 2; /*!< function sel */ - __IOM uint32_t REG_PAD3_SLP_SEL : 1; /*!< 1: enable sleep mode during sleep,0: no sleep mode */ - __IOM uint32_t REG_PAD3_SLP_IE : 1; /*!< input enable in sleep mode */ - __IOM uint32_t REG_PAD3_SLP_OE : 1; /*!< output enable in sleep mode */ - __IOM uint32_t REG_PAD3_FUN_IE : 1; /*!< input enable in work mode */ - __IOM uint32_t REG_PAD3_FILTER_EN : 1; /*!< need des */ - uint32_t : 20; - } bit; - } PAD3; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_PAD4_DRV : 2; /*!< Reserved */ - __IOM uint32_t REG_PAD4_RDE : 1; /*!< Reserved */ - __IOM uint32_t REG_PAD4_RUE : 1; /*!< Reserved */ - __IOM uint32_t REG_PAD4_MUX_SEL : 1; /*!< 1:use LP GPIO,0: use digital GPIO */ - __IOM uint32_t REG_PAD4_FUN_SEL : 2; /*!< function sel */ - __IOM uint32_t REG_PAD4_SLP_SEL : 1; /*!< 1: enable sleep mode during sleep,0: no sleep mode */ - __IOM uint32_t REG_PAD4_SLP_IE : 1; /*!< input enable in sleep mode */ - __IOM uint32_t REG_PAD4_SLP_OE : 1; /*!< output enable in sleep mode */ - __IOM uint32_t REG_PAD4_FUN_IE : 1; /*!< input enable in work mode */ - __IOM uint32_t REG_PAD4_FILTER_EN : 1; /*!< need des */ - uint32_t : 20; - } bit; - } PAD4; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_PAD5_DRV : 2; /*!< Reserved */ - __IOM uint32_t REG_PAD5_RDE : 1; /*!< Reserved */ - __IOM uint32_t REG_PAD5_RUE : 1; /*!< Reserved */ - __IOM uint32_t REG_PAD5_MUX_SEL : 1; /*!< 1:use LP GPIO,0: use digital GPIO */ - __IOM uint32_t REG_PAD5_FUN_SEL : 2; /*!< function sel */ - __IOM uint32_t REG_PAD5_SLP_SEL : 1; /*!< 1: enable sleep mode during sleep,0: no sleep mode */ - __IOM uint32_t REG_PAD5_SLP_IE : 1; /*!< input enable in sleep mode */ - __IOM uint32_t REG_PAD5_SLP_OE : 1; /*!< output enable in sleep mode */ - __IOM uint32_t REG_PAD5_FUN_IE : 1; /*!< input enable in work mode */ - __IOM uint32_t REG_PAD5_FILTER_EN : 1; /*!< need des */ - uint32_t : 20; - } bit; - } PAD5; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_PAD6_DRV : 2; /*!< Reserved */ - __IOM uint32_t REG_PAD6_RDE : 1; /*!< Reserved */ - __IOM uint32_t REG_PAD6_RUE : 1; /*!< Reserved */ - __IOM uint32_t REG_PAD6_MUX_SEL : 1; /*!< 1:use LP GPIO,0: use digital GPIO */ - __IOM uint32_t REG_PAD6_FUN_SEL : 2; /*!< function sel */ - __IOM uint32_t REG_PAD6_SLP_SEL : 1; /*!< 1: enable sleep mode during sleep,0: no sleep mode */ - __IOM uint32_t REG_PAD6_SLP_IE : 1; /*!< input enable in sleep mode */ - __IOM uint32_t REG_PAD6_SLP_OE : 1; /*!< output enable in sleep mode */ - __IOM uint32_t REG_PAD6_FUN_IE : 1; /*!< input enable in work mode */ - __IOM uint32_t REG_PAD6_FILTER_EN : 1; /*!< need des */ - uint32_t : 20; - } bit; - } PAD6; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_PAD7_DRV : 2; /*!< Reserved */ - __IOM uint32_t REG_PAD7_RDE : 1; /*!< Reserved */ - __IOM uint32_t REG_PAD7_RUE : 1; /*!< Reserved */ - __IOM uint32_t REG_PAD7_MUX_SEL : 1; /*!< 1:use LP GPIO,0: use digital GPIO */ - __IOM uint32_t REG_PAD7_FUN_SEL : 2; /*!< function sel */ - __IOM uint32_t REG_PAD7_SLP_SEL : 1; /*!< 1: enable sleep mode during sleep,0: no sleep mode */ - __IOM uint32_t REG_PAD7_SLP_IE : 1; /*!< input enable in sleep mode */ - __IOM uint32_t REG_PAD7_SLP_OE : 1; /*!< output enable in sleep mode */ - __IOM uint32_t REG_PAD7_FUN_IE : 1; /*!< input enable in work mode */ - __IOM uint32_t REG_PAD7_FILTER_EN : 1; /*!< need des */ - uint32_t : 20; - } bit; - } PAD7; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_PAD8_DRV : 2; /*!< Reserved */ - __IOM uint32_t REG_PAD8_RDE : 1; /*!< Reserved */ - __IOM uint32_t REG_PAD8_RUE : 1; /*!< Reserved */ - __IOM uint32_t REG_PAD8_MUX_SEL : 1; /*!< 1:use LP GPIO,0: use digital GPIO */ - __IOM uint32_t REG_PAD8_FUN_SEL : 2; /*!< function sel */ - __IOM uint32_t REG_PAD8_SLP_SEL : 1; /*!< 1: enable sleep mode during sleep,0: no sleep mode */ - __IOM uint32_t REG_PAD8_SLP_IE : 1; /*!< input enable in sleep mode */ - __IOM uint32_t REG_PAD8_SLP_OE : 1; /*!< output enable in sleep mode */ - __IOM uint32_t REG_PAD8_FUN_IE : 1; /*!< input enable in work mode */ - __IOM uint32_t REG_PAD8_FILTER_EN : 1; /*!< need des */ - uint32_t : 20; - } bit; - } PAD8; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_PAD9_DRV : 2; /*!< Reserved */ - __IOM uint32_t REG_PAD9_RDE : 1; /*!< Reserved */ - __IOM uint32_t REG_PAD9_RUE : 1; /*!< Reserved */ - __IOM uint32_t REG_PAD9_MUX_SEL : 1; /*!< 1:use LP GPIO,0: use digital GPIO */ - __IOM uint32_t REG_PAD9_FUN_SEL : 2; /*!< function sel */ - __IOM uint32_t REG_PAD9_SLP_SEL : 1; /*!< 1: enable sleep mode during sleep,0: no sleep mode */ - __IOM uint32_t REG_PAD9_SLP_IE : 1; /*!< input enable in sleep mode */ - __IOM uint32_t REG_PAD9_SLP_OE : 1; /*!< output enable in sleep mode */ - __IOM uint32_t REG_PAD9_FUN_IE : 1; /*!< input enable in work mode */ - __IOM uint32_t REG_PAD9_FILTER_EN : 1; /*!< need des */ - uint32_t : 20; - } bit; - } PAD9; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_PAD10_DRV : 2; /*!< Reserved */ - __IOM uint32_t REG_PAD10_RDE : 1; /*!< Reserved */ - __IOM uint32_t REG_PAD10_RUE : 1; /*!< Reserved */ - __IOM uint32_t REG_PAD10_MUX_SEL : 1; /*!< 1:use LP GPIO,0: use digital GPIO */ - __IOM uint32_t REG_PAD10_FUN_SEL : 2; /*!< function sel */ - __IOM uint32_t REG_PAD10_SLP_SEL : 1; /*!< 1: enable sleep mode during sleep,0: no sleep mode */ - __IOM uint32_t REG_PAD10_SLP_IE : 1; /*!< input enable in sleep mode */ - __IOM uint32_t REG_PAD10_SLP_OE : 1; /*!< output enable in sleep mode */ - __IOM uint32_t REG_PAD10_FUN_IE : 1; /*!< input enable in work mode */ - __IOM uint32_t REG_PAD10_FILTER_EN : 1; /*!< need des */ - uint32_t : 20; - } bit; - } PAD10; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_PAD11_DRV : 2; /*!< Reserved */ - __IOM uint32_t REG_PAD11_RDE : 1; /*!< Reserved */ - __IOM uint32_t REG_PAD11_RUE : 1; /*!< Reserved */ - __IOM uint32_t REG_PAD11_MUX_SEL : 1; /*!< 1:use LP GPIO,0: use digital GPIO */ - __IOM uint32_t REG_PAD11_FUN_SEL : 2; /*!< function sel */ - __IOM uint32_t REG_PAD11_SLP_SEL : 1; /*!< 1: enable sleep mode during sleep,0: no sleep mode */ - __IOM uint32_t REG_PAD11_SLP_IE : 1; /*!< input enable in sleep mode */ - __IOM uint32_t REG_PAD11_SLP_OE : 1; /*!< output enable in sleep mode */ - __IOM uint32_t REG_PAD11_FUN_IE : 1; /*!< input enable in work mode */ - __IOM uint32_t REG_PAD11_FILTER_EN : 1; /*!< need des */ - uint32_t : 20; - } bit; - } PAD11; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_PAD12_DRV : 2; /*!< Reserved */ - __IOM uint32_t REG_PAD12_RDE : 1; /*!< Reserved */ - __IOM uint32_t REG_PAD12_RUE : 1; /*!< Reserved */ - __IOM uint32_t REG_PAD12_MUX_SEL : 1; /*!< 1:use LP GPIO,0: use digital GPIO */ - __IOM uint32_t REG_PAD12_FUN_SEL : 2; /*!< function sel */ - __IOM uint32_t REG_PAD12_SLP_SEL : 1; /*!< 1: enable sleep mode during sleep,0: no sleep mode */ - __IOM uint32_t REG_PAD12_SLP_IE : 1; /*!< input enable in sleep mode */ - __IOM uint32_t REG_PAD12_SLP_OE : 1; /*!< output enable in sleep mode */ - __IOM uint32_t REG_PAD12_FUN_IE : 1; /*!< input enable in work mode */ - __IOM uint32_t REG_PAD12_FILTER_EN : 1; /*!< need des */ - uint32_t : 20; - } bit; - } PAD120; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_PAD13_DRV : 2; /*!< Reserved */ - __IOM uint32_t REG_PAD13_RDE : 1; /*!< Reserved */ - __IOM uint32_t REG_PAD13_RUE : 1; /*!< Reserved */ - __IOM uint32_t REG_PAD13_MUX_SEL : 1; /*!< 1:use LP GPIO,0: use digital GPIO */ - __IOM uint32_t REG_PAD13_FUN_SEL : 2; /*!< function sel */ - __IOM uint32_t REG_PAD13_SLP_SEL : 1; /*!< 1: enable sleep mode during sleep,0: no sleep mode */ - __IOM uint32_t REG_PAD13_SLP_IE : 1; /*!< input enable in sleep mode */ - __IOM uint32_t REG_PAD13_SLP_OE : 1; /*!< output enable in sleep mode */ - __IOM uint32_t REG_PAD13_FUN_IE : 1; /*!< input enable in work mode */ - __IOM uint32_t REG_PAD13_FILTER_EN : 1; /*!< need des */ - uint32_t : 20; - } bit; - } PAD13; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_PAD14_DRV : 2; /*!< Reserved */ - __IOM uint32_t REG_PAD14_RDE : 1; /*!< Reserved */ - __IOM uint32_t REG_PAD14_RUE : 1; /*!< Reserved */ - __IOM uint32_t REG_PAD14_MUX_SEL : 1; /*!< 1:use LP GPIO,0: use digital GPIO */ - __IOM uint32_t REG_PAD14_FUN_SEL : 2; /*!< function sel */ - __IOM uint32_t REG_PAD14_SLP_SEL : 1; /*!< 1: enable sleep mode during sleep,0: no sleep mode */ - __IOM uint32_t REG_PAD14_SLP_IE : 1; /*!< input enable in sleep mode */ - __IOM uint32_t REG_PAD14_SLP_OE : 1; /*!< output enable in sleep mode */ - __IOM uint32_t REG_PAD14_FUN_IE : 1; /*!< input enable in work mode */ - __IOM uint32_t REG_PAD14_FILTER_EN : 1; /*!< need des */ - uint32_t : 20; - } bit; - } PAD14; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_PAD15_DRV : 2; /*!< Reserved */ - __IOM uint32_t REG_PAD15_RDE : 1; /*!< Reserved */ - __IOM uint32_t REG_PAD15_RUE : 1; /*!< Reserved */ - __IOM uint32_t REG_PAD15_MUX_SEL : 1; /*!< 1:use LP GPIO,0: use digital GPIO */ - __IOM uint32_t REG_PAD15_FUN_SEL : 2; /*!< function sel */ - __IOM uint32_t REG_PAD15_SLP_SEL : 1; /*!< 1: enable sleep mode during sleep,0: no sleep mode */ - __IOM uint32_t REG_PAD15_SLP_IE : 1; /*!< input enable in sleep mode */ - __IOM uint32_t REG_PAD15_SLP_OE : 1; /*!< output enable in sleep mode */ - __IOM uint32_t REG_PAD15_FUN_IE : 1; /*!< input enable in work mode */ - __IOM uint32_t REG_PAD15_FILTER_EN : 1; /*!< need des */ - uint32_t : 20; - } bit; - } PAD15; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_XTL_EXT_CTR_SEL : 5; /*!< select LP GPIO 0 ~ 15 to control XTAL */ - __IOM uint32_t REG_EXT_WAKEUP0_SEL : 5; /*!< Reserved */ - uint32_t : 22; - } bit; - } EXT_WAKEUP0_SEL; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_LP_GPIO_HOLD : 16; /*!< Reserved */ - uint32_t : 16; - } bit; - } LP_PAD_HOLD; - - union { - __IOM uint32_t reg; /*!< Reserved */ - - struct { - __IOM uint32_t REG_LP_GPIO_HYS : 16; /*!< Reserved */ - uint32_t : 16; - } bit; - } LP_PAD_HYS; -} LP_IO_MUX_Type; /*!< Size = 84 (0x54) */ - - - -/* =========================================================================================================================== */ -/* ================ LP_UART ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Low-power UART (Universal Asynchronous Receiver-Transmitter) Controller (LP_UART) - */ - -typedef struct { /*!< LP_UART Structure */ - - union { - __IOM uint32_t reg; /*!< FIFO data register */ - - struct { - __IM uint32_t RXFIFO_RD_BYTE : 8; /*!< UART 0 accesses FIFO via this register. */ - uint32_t : 24; - } bit; - } FIFO; - - union { - __IOM uint32_t reg; /*!< Raw interrupt status */ - - struct { - __IOM uint32_t RXFIFO_FULL_INT_RAW : 1; /*!< This interrupt raw bit turns to high level when receiver receives - more data than what rxfifo_full_thrhd specifies. */ - __IOM uint32_t TXFIFO_EMPTY_INT_RAW : 1; /*!< This interrupt raw bit turns to high level when the amount of - data in Tx-FIFO is less than what txfifo_empty_thrhd specifies - . */ - __IOM uint32_t PARITY_ERR_INT_RAW : 1; /*!< This interrupt raw bit turns to high level when receiver detects - a parity error in the data. */ - __IOM uint32_t FRM_ERR_INT_RAW : 1; /*!< This interrupt raw bit turns to high level when receiver detects - a data frame error . */ - __IOM uint32_t RXFIFO_OVF_INT_RAW : 1; /*!< This interrupt raw bit turns to high level when receiver receives - more data than the FIFO can store. */ - __IOM uint32_t DSR_CHG_INT_RAW : 1; /*!< This interrupt raw bit turns to high level when receiver detects - the edge change of DSRn signal. */ - __IOM uint32_t CTS_CHG_INT_RAW : 1; /*!< This interrupt raw bit turns to high level when receiver detects - the edge change of CTSn signal. */ - __IOM uint32_t BRK_DET_INT_RAW : 1; /*!< This interrupt raw bit turns to high level when receiver detects - a 0 after the stop bit. */ - __IOM uint32_t RXFIFO_TOUT_INT_RAW : 1; /*!< This interrupt raw bit turns to high level when receiver takes - more time than rx_tout_thrhd to receive a byte. */ - __IOM uint32_t SW_XON_INT_RAW : 1; /*!< This interrupt raw bit turns to high level when receiver recevies - Xon char when uart_sw_flow_con_en is set to 1. */ - __IOM uint32_t SW_XOFF_INT_RAW : 1; /*!< This interrupt raw bit turns to high level when receiver receives - Xoff char when uart_sw_flow_con_en is set to 1. */ - __IOM uint32_t GLITCH_DET_INT_RAW : 1; /*!< This interrupt raw bit turns to high level when receiver detects - a glitch in the middle of a start bit. */ - __IOM uint32_t TX_BRK_DONE_INT_RAW : 1; /*!< This interrupt raw bit turns to high level when transmitter - completes sending NULL characters after all data in Tx-FIFO - are sent. */ - __IOM uint32_t TX_BRK_IDLE_DONE_INT_RAW : 1;/*!< This interrupt raw bit turns to high level when transmitter - has kept the shortest duration after sending the last data. */ - __IOM uint32_t TX_DONE_INT_RAW : 1; /*!< This interrupt raw bit turns to high level when transmitter - has send out all data in FIFO. */ - uint32_t : 3; - __IOM uint32_t AT_CMD_CHAR_DET_INT_RAW : 1;/*!< This interrupt raw bit turns to high level when receiver detects - the configured at_cmd char. */ - __IOM uint32_t WAKEUP_INT_RAW : 1; /*!< This interrupt raw bit turns to high level when input rxd edge - changes more times than what reg_active_threshold specifies - in light sleeping mode. */ - uint32_t : 12; - } bit; - } INT_RAW; - - union { - __IOM uint32_t reg; /*!< Masked interrupt status */ - - struct { - __IM uint32_t RXFIFO_FULL_INT_ST : 1; /*!< This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena - is set to 1. */ - __IM uint32_t TXFIFO_EMPTY_INT_ST : 1; /*!< This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena - is set to 1. */ - __IM uint32_t PARITY_ERR_INT_ST : 1; /*!< This is the status bit for parity_err_int_raw when parity_err_int_ena - is set to 1. */ - __IM uint32_t FRM_ERR_INT_ST : 1; /*!< This is the status bit for frm_err_int_raw when frm_err_int_ena - is set to 1. */ - __IM uint32_t RXFIFO_OVF_INT_ST : 1; /*!< This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena - is set to 1. */ - __IM uint32_t DSR_CHG_INT_ST : 1; /*!< This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena - is set to 1. */ - __IM uint32_t CTS_CHG_INT_ST : 1; /*!< This is the status bit for cts_chg_int_raw when cts_chg_int_ena - is set to 1. */ - __IM uint32_t BRK_DET_INT_ST : 1; /*!< This is the status bit for brk_det_int_raw when brk_det_int_ena - is set to 1. */ - __IM uint32_t RXFIFO_TOUT_INT_ST : 1; /*!< This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena - is set to 1. */ - __IM uint32_t SW_XON_INT_ST : 1; /*!< This is the status bit for sw_xon_int_raw when sw_xon_int_ena - is set to 1. */ - __IM uint32_t SW_XOFF_INT_ST : 1; /*!< This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena - is set to 1. */ - __IM uint32_t GLITCH_DET_INT_ST : 1; /*!< This is the status bit for glitch_det_int_raw when glitch_det_int_ena - is set to 1. */ - __IM uint32_t TX_BRK_DONE_INT_ST : 1; /*!< This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena - is set to 1. */ - __IM uint32_t TX_BRK_IDLE_DONE_INT_ST : 1;/*!< This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ - na is set to 1. */ - __IM uint32_t TX_DONE_INT_ST : 1; /*!< This is the status bit for tx_done_int_raw when tx_done_int_ena - is set to 1. */ - uint32_t : 3; - __IM uint32_t AT_CMD_CHAR_DET_INT_ST : 1;/*!< This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena - is set to 1. */ - __IM uint32_t WAKEUP_INT_ST : 1; /*!< This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena - is set to 1. */ - uint32_t : 12; - } bit; - } INT_ST; - - union { - __IOM uint32_t reg; /*!< Interrupt enable bits */ - - struct { - __IOM uint32_t RXFIFO_FULL_INT_ENA : 1; /*!< This is the enable bit for rxfifo_full_int_st register. */ - __IOM uint32_t TXFIFO_EMPTY_INT_ENA : 1; /*!< This is the enable bit for txfifo_empty_int_st register. */ - __IOM uint32_t PARITY_ERR_INT_ENA : 1; /*!< This is the enable bit for parity_err_int_st register. */ - __IOM uint32_t FRM_ERR_INT_ENA : 1; /*!< This is the enable bit for frm_err_int_st register. */ - __IOM uint32_t RXFIFO_OVF_INT_ENA : 1; /*!< This is the enable bit for rxfifo_ovf_int_st register. */ - __IOM uint32_t DSR_CHG_INT_ENA : 1; /*!< This is the enable bit for dsr_chg_int_st register. */ - __IOM uint32_t CTS_CHG_INT_ENA : 1; /*!< This is the enable bit for cts_chg_int_st register. */ - __IOM uint32_t BRK_DET_INT_ENA : 1; /*!< This is the enable bit for brk_det_int_st register. */ - __IOM uint32_t RXFIFO_TOUT_INT_ENA : 1; /*!< This is the enable bit for rxfifo_tout_int_st register. */ - __IOM uint32_t SW_XON_INT_ENA : 1; /*!< This is the enable bit for sw_xon_int_st register. */ - __IOM uint32_t SW_XOFF_INT_ENA : 1; /*!< This is the enable bit for sw_xoff_int_st register. */ - __IOM uint32_t GLITCH_DET_INT_ENA : 1; /*!< This is the enable bit for glitch_det_int_st register. */ - __IOM uint32_t TX_BRK_DONE_INT_ENA : 1; /*!< This is the enable bit for tx_brk_done_int_st register. */ - __IOM uint32_t TX_BRK_IDLE_DONE_INT_ENA : 1;/*!< This is the enable bit for tx_brk_idle_done_int_st register. */ - __IOM uint32_t TX_DONE_INT_ENA : 1; /*!< This is the enable bit for tx_done_int_st register. */ - uint32_t : 3; - __IOM uint32_t AT_CMD_CHAR_DET_INT_ENA : 1;/*!< This is the enable bit for at_cmd_char_det_int_st register. */ - __IOM uint32_t WAKEUP_INT_ENA : 1; /*!< This is the enable bit for uart_wakeup_int_st register. */ - uint32_t : 12; - } bit; - } INT_ENA; - - union { - __IOM uint32_t reg; /*!< Interrupt clear bits */ - - struct { - __OM uint32_t RXFIFO_FULL_INT_CLR : 1; /*!< Set this bit to clear the rxfifo_full_int_raw interrupt. */ - __OM uint32_t TXFIFO_EMPTY_INT_CLR : 1; /*!< Set this bit to clear txfifo_empty_int_raw interrupt. */ - __OM uint32_t PARITY_ERR_INT_CLR : 1; /*!< Set this bit to clear parity_err_int_raw interrupt. */ - __OM uint32_t FRM_ERR_INT_CLR : 1; /*!< Set this bit to clear frm_err_int_raw interrupt. */ - __OM uint32_t RXFIFO_OVF_INT_CLR : 1; /*!< Set this bit to clear rxfifo_ovf_int_raw interrupt. */ - __OM uint32_t DSR_CHG_INT_CLR : 1; /*!< Set this bit to clear the dsr_chg_int_raw interrupt. */ - __OM uint32_t CTS_CHG_INT_CLR : 1; /*!< Set this bit to clear the cts_chg_int_raw interrupt. */ - __OM uint32_t BRK_DET_INT_CLR : 1; /*!< Set this bit to clear the brk_det_int_raw interrupt. */ - __OM uint32_t RXFIFO_TOUT_INT_CLR : 1; /*!< Set this bit to clear the rxfifo_tout_int_raw interrupt. */ - __OM uint32_t SW_XON_INT_CLR : 1; /*!< Set this bit to clear the sw_xon_int_raw interrupt. */ - __OM uint32_t SW_XOFF_INT_CLR : 1; /*!< Set this bit to clear the sw_xoff_int_raw interrupt. */ - __OM uint32_t GLITCH_DET_INT_CLR : 1; /*!< Set this bit to clear the glitch_det_int_raw interrupt. */ - __OM uint32_t TX_BRK_DONE_INT_CLR : 1; /*!< Set this bit to clear the tx_brk_done_int_raw interrupt.. */ - __OM uint32_t TX_BRK_IDLE_DONE_INT_CLR : 1;/*!< Set this bit to clear the tx_brk_idle_done_int_raw interrupt. */ - __OM uint32_t TX_DONE_INT_CLR : 1; /*!< Set this bit to clear the tx_done_int_raw interrupt. */ - uint32_t : 3; - __OM uint32_t AT_CMD_CHAR_DET_INT_CLR : 1;/*!< Set this bit to clear the at_cmd_char_det_int_raw interrupt. */ - __OM uint32_t WAKEUP_INT_CLR : 1; /*!< Set this bit to clear the uart_wakeup_int_raw interrupt. */ - uint32_t : 12; - } bit; - } INT_CLR; - - union { - __IOM uint32_t reg; /*!< Clock divider configuration */ - - struct { - __IOM uint32_t CLKDIV : 12; /*!< The integral part of the frequency divider factor. */ - uint32_t : 8; - __IOM uint32_t CLKDIV_FRAG : 4; /*!< The decimal part of the frequency divider factor. */ - uint32_t : 8; - } bit; - } CLKDIV_SYNC; - - union { - __IOM uint32_t reg; /*!< Rx Filter configuration */ - - struct { - __IOM uint32_t GLITCH_FILT : 8; /*!< when input pulse width is lower than this value the pulse is - ignored. */ - __IOM uint32_t GLITCH_FILT_EN : 1; /*!< Set this bit to enable Rx signal filter. */ - uint32_t : 23; - } bit; - } RX_FILT; - - union { - __IOM uint32_t reg; /*!< UART status register */ - - struct { - uint32_t : 3; - __IM uint32_t RXFIFO_CNT : 5; /*!< Stores the byte number of valid data in Rx-FIFO. */ - uint32_t : 5; - __IM uint32_t DSRN : 1; /*!< The register represent the level value of the internal uart - dsr signal. */ - __IM uint32_t CTSN : 1; /*!< This register represent the level value of the internal uart - cts signal. */ - __IM uint32_t RXD : 1; /*!< This register represent the level value of the internal uart - rxd signal. */ - uint32_t : 3; - __IM uint32_t TXFIFO_CNT : 5; /*!< Stores the byte number of data in Tx-FIFO. */ - uint32_t : 5; - __IM uint32_t DTRN : 1; /*!< This bit represents the level of the internal uart dtr signal. */ - __IM uint32_t RTSN : 1; /*!< This bit represents the level of the internal uart rts signal. */ - __IM uint32_t TXD : 1; /*!< This bit represents the level of the internal uart txd signal. */ - } bit; - } STATUS; - - union { - __IOM uint32_t reg; /*!< Configuration register 0 */ - - struct { - __IOM uint32_t PARITY : 1; /*!< This register is used to configure the parity check mode. */ - __IOM uint32_t PARITY_EN : 1; /*!< Set this bit to enable uart parity check. */ - __IOM uint32_t BIT_NUM : 2; /*!< This register is used to set the length of data. */ - __IOM uint32_t STOP_BIT_NUM : 2; /*!< This register is used to set the length of stop bit. */ - __IOM uint32_t TXD_BRK : 1; /*!< Set this bit to enbale transmitter to send NULL when the process - of sending data is done. */ - uint32_t : 5; - __IOM uint32_t LOOPBACK : 1; /*!< Set this bit to enable uart loopback test mode. */ - __IOM uint32_t TX_FLOW_EN : 1; /*!< Set this bit to enable flow control function for transmitter. */ - uint32_t : 1; - __IOM uint32_t RXD_INV : 1; /*!< Set this bit to inverse the level value of uart rxd signal. */ - __IOM uint32_t TXD_INV : 1; /*!< Set this bit to inverse the level value of uart txd signal. */ - __IOM uint32_t DIS_RX_DAT_OVF : 1; /*!< Disable UART Rx data overflow detect. */ - __IOM uint32_t ERR_WR_MASK : 1; /*!< 1'h1: Receiver stops storing data into FIFO when data is wrong. - 1'h0: Receiver stores the data even if the received data - is wrong. */ - uint32_t : 1; - __IOM uint32_t MEM_CLK_EN : 1; /*!< UART memory clock gate enable signal. */ - __IOM uint32_t SW_RTS : 1; /*!< This register is used to configure the software rts signal which - is used in software flow control. */ - __IOM uint32_t RXFIFO_RST : 1; /*!< Set this bit to reset the uart receive-FIFO. */ - __IOM uint32_t TXFIFO_RST : 1; /*!< Set this bit to reset the uart transmit-FIFO. */ - uint32_t : 8; - } bit; - } CONF0_SYNC; - - union { - __IOM uint32_t reg; /*!< Configuration register 1 */ - - struct { - uint32_t : 3; - __IOM uint32_t RXFIFO_FULL_THRHD : 5; /*!< It will produce rxfifo_full_int interrupt when receiver receives - more data than this register value. */ - uint32_t : 3; - __IOM uint32_t TXFIFO_EMPTY_THRHD : 5; /*!< It will produce txfifo_empty_int interrupt when the data amount - in Tx-FIFO is less than this register value. */ - __IOM uint32_t CTS_INV : 1; /*!< Set this bit to inverse the level value of uart cts signal. */ - __IOM uint32_t DSR_INV : 1; /*!< Set this bit to inverse the level value of uart dsr signal. */ - __IOM uint32_t RTS_INV : 1; /*!< Set this bit to inverse the level value of uart rts signal. */ - __IOM uint32_t DTR_INV : 1; /*!< Set this bit to inverse the level value of uart dtr signal. */ - __IOM uint32_t SW_DTR : 1; /*!< This register is used to configure the software dtr signal which - is used in software flow control. */ - __IOM uint32_t CLK_EN : 1; /*!< 1'h1: Force clock on for register. 1'h0: Support clock only - when application writes registers. */ - uint32_t : 10; - } bit; - } CONF1; - __IM uint32_t RESERVED; - - union { - __IOM uint32_t reg; /*!< Hardware flow-control configuration */ - - struct { - uint32_t : 3; - __IOM uint32_t RX_FLOW_THRHD : 5; /*!< This register is used to configure the maximum amount of data - that can be received when hardware flow control works. */ - __IOM uint32_t RX_FLOW_EN : 1; /*!< This is the flow enable bit for UART receiver. */ - uint32_t : 23; - } bit; - } HWFC_CONF_SYNC; - - union { - __IOM uint32_t reg; /*!< UART sleep configure register 0 */ - - struct { - __IOM uint32_t WK_CHAR1 : 8; /*!< This register restores the specified wake up char1 to wake up */ - __IOM uint32_t WK_CHAR2 : 8; /*!< This register restores the specified wake up char2 to wake up */ - __IOM uint32_t WK_CHAR3 : 8; /*!< This register restores the specified wake up char3 to wake up */ - __IOM uint32_t WK_CHAR4 : 8; /*!< This register restores the specified wake up char4 to wake up */ - } bit; - } SLEEP_CONF0; - - union { - __IOM uint32_t reg; /*!< UART sleep configure register 1 */ - - struct { - __IOM uint32_t WK_CHAR0 : 8; /*!< This register restores the specified char0 to wake up */ - uint32_t : 24; - } bit; - } SLEEP_CONF1; - - union { - __IOM uint32_t reg; /*!< UART sleep configure register 2 */ - - struct { - __IOM uint32_t ACTIVE_THRESHOLD : 10; /*!< The uart is activated from light sleeping mode when the input - rxd edge changes more times than this register value. */ - uint32_t : 3; - __IOM uint32_t RX_WAKE_UP_THRHD : 5; /*!< In wake up mode 1 this field is used to set the received data - number threshold to wake up chip. */ - __IOM uint32_t WK_CHAR_NUM : 3; /*!< This register is used to select number of wake up char. */ - __IOM uint32_t WK_CHAR_MASK : 5; /*!< This register is used to mask wake up char. */ - __IOM uint32_t WK_MODE_SEL : 2; /*!< This register is used to select wake up mode. 0: RXD toggling - to wake up. 1: received data number larger than */ - uint32_t : 4; - } bit; - } SLEEP_CONF2; - - union { - __IOM uint32_t reg; /*!< Software flow-control character configuration */ - - struct { - __IOM uint32_t XON_CHAR : 8; /*!< This register stores the Xon flow control char. */ - __IOM uint32_t XOFF_CHAR : 8; /*!< This register stores the Xoff flow control char. */ - __IOM uint32_t XON_XOFF_STILL_SEND : 1; /*!< In software flow control mode, UART Tx is disabled once UART - Rx receives XOFF. In this status, UART Tx can not transmit - XOFF even the received data number is larger than UART_XOFF_THRESHOLD. - Set this bit to enable UART Tx can transmit XON/XOFF when - UART Tx is disabled. */ - __IOM uint32_t SW_FLOW_CON_EN : 1; /*!< Set this bit to enable software flow control. It is used with - register sw_xon or sw_xoff. */ - __IOM uint32_t XONOFF_DEL : 1; /*!< Set this bit to remove flow control char from the received data. */ - __IOM uint32_t FORCE_XON : 1; /*!< Set this bit to enable the transmitter to go on sending data. */ - __IOM uint32_t FORCE_XOFF : 1; /*!< Set this bit to stop the transmitter from sending data. */ - __IOM uint32_t SEND_XON : 1; /*!< Set this bit to send Xon char. It is cleared by hardware automatically. */ - __IOM uint32_t SEND_XOFF : 1; /*!< Set this bit to send Xoff char. It is cleared by hardware automatically. */ - uint32_t : 9; - } bit; - } SWFC_CONF0_SYNC; - - union { - __IOM uint32_t reg; /*!< Software flow-control character configuration */ - - struct { - uint32_t : 3; - __IOM uint32_t XON_THRESHOLD : 5; /*!< When the data amount in Rx-FIFO is less than this register value - with uart_sw_flow_con_en set to 1 it will send a Xon char. */ - uint32_t : 3; - __IOM uint32_t XOFF_THRESHOLD : 5; /*!< When the data amount in Rx-FIFO is more than this register value - with uart_sw_flow_con_en set to 1 it will send a Xoff char. */ - uint32_t : 16; - } bit; - } SWFC_CONF1; - - union { - __IOM uint32_t reg; /*!< Tx Break character configuration */ - - struct { - __IOM uint32_t TX_BRK_NUM : 8; /*!< This register is used to configure the number of 0 to be sent - after the process of sending data is done. It is active - when txd_brk is set to 1. */ - uint32_t : 24; - } bit; - } TXBRK_CONF_SYNC; - - union { - __IOM uint32_t reg; /*!< Frame-end idle configuration */ - - struct { - __IOM uint32_t RX_IDLE_THRHD : 10; /*!< It will produce frame end signal when receiver takes more time - to receive one byte data than this register value. */ - __IOM uint32_t TX_IDLE_NUM : 10; /*!< This register is used to configure the duration time between - transfers. */ - uint32_t : 12; - } bit; - } IDLE_CONF_SYNC; - - union { - __IOM uint32_t reg; /*!< RS485 mode configuration */ - - struct { - uint32_t : 1; - __IOM uint32_t DL0_EN : 1; /*!< Set this bit to delay the stop bit by 1 bit. */ - __IOM uint32_t DL1_EN : 1; /*!< Set this bit to delay the stop bit by 1 bit. */ - uint32_t : 29; - } bit; - } RS485_CONF_SYNC; - - union { - __IOM uint32_t reg; /*!< Pre-sequence timing configuration */ - - struct { - __IOM uint32_t PRE_IDLE_NUM : 16; /*!< This register is used to configure the idle duration time before - the first at_cmd is received by receiver. */ - uint32_t : 16; - } bit; - } AT_CMD_PRECNT_SYNC; - - union { - __IOM uint32_t reg; /*!< Post-sequence timing configuration */ - - struct { - __IOM uint32_t POST_IDLE_NUM : 16; /*!< This register is used to configure the duration time between - the last at_cmd and the next data. */ - uint32_t : 16; - } bit; - } AT_CMD_POSTCNT_SYNC; - - union { - __IOM uint32_t reg; /*!< Timeout configuration */ - - struct { - __IOM uint32_t RX_GAP_TOUT : 16; /*!< This register is used to configure the duration time between - the at_cmd chars. */ - uint32_t : 16; - } bit; - } AT_CMD_GAPTOUT_SYNC; - - union { - __IOM uint32_t reg; /*!< AT escape sequence detection configuration */ - - struct { - __IOM uint32_t AT_CMD_CHAR : 8; /*!< This register is used to configure the content of at_cmd char. */ - __IOM uint32_t CHAR_NUM : 8; /*!< This register is used to configure the num of continuous at_cmd - chars received by receiver. */ - uint32_t : 16; - } bit; - } AT_CMD_CHAR_SYNC; - - union { - __IOM uint32_t reg; /*!< UART memory power configuration */ - - struct { - uint32_t : 25; - __IOM uint32_t MEM_FORCE_PD : 1; /*!< Set this bit to force power down UART memory. */ - __IOM uint32_t MEM_FORCE_PU : 1; /*!< Set this bit to force power up UART memory. */ - uint32_t : 5; - } bit; - } MEM_CONF; - - union { - __IOM uint32_t reg; /*!< UART threshold and allocation configuration */ - - struct { - __IOM uint32_t RX_TOUT_EN : 1; /*!< This is the enble bit for uart receiver's timeout function. */ - __IOM uint32_t RX_TOUT_FLOW_DIS : 1; /*!< Set this bit to stop accumulating idle_cnt when hardware flow - control works. */ - __IOM uint32_t RX_TOUT_THRHD : 10; /*!< This register is used to configure the threshold time that receiver - takes to receive one byte. The rxfifo_tout_int interrupt - will be trigger when the receiver takes more time to receive - one byte with rx_tout_en set to 1. */ - uint32_t : 20; - } bit; - } TOUT_CONF_SYNC; - - union { - __IOM uint32_t reg; /*!< Tx-SRAM write and read offset address. */ - - struct { - uint32_t : 3; - __IM uint32_t TX_SRAM_WADDR : 5; /*!< This register stores the offset write address in Tx-SRAM. */ - uint32_t : 4; - __IM uint32_t TX_SRAM_RADDR : 5; /*!< This register stores the offset read address in Tx-SRAM. */ - uint32_t : 15; - } bit; - } MEM_TX_STATUS; - - union { - __IOM uint32_t reg; /*!< Rx-SRAM write and read offset address. */ - - struct { - uint32_t : 3; - __IM uint32_t RX_SRAM_RADDR : 5; /*!< This register stores the offset read address in RX-SRAM. */ - uint32_t : 4; - __IM uint32_t RX_SRAM_WADDR : 5; /*!< This register stores the offset write address in Rx-SRAM. */ - uint32_t : 15; - } bit; - } MEM_RX_STATUS; - - union { - __IOM uint32_t reg; /*!< UART transmit and receive status. */ - - struct { - __IM uint32_t ST_URX_OUT : 4; /*!< This is the status register of receiver. */ - __IM uint32_t ST_UTX_OUT : 4; /*!< This is the status register of transmitter. */ - uint32_t : 24; - } bit; - } FSM_STATUS; - __IM uint32_t RESERVED1[5]; - - union { - __IOM uint32_t reg; /*!< UART core clock configuration */ - - struct { - uint32_t : 24; - __IOM uint32_t TX_SCLK_EN : 1; /*!< Set this bit to enable UART Tx clock. */ - __IOM uint32_t RX_SCLK_EN : 1; /*!< Set this bit to enable UART Rx clock. */ - __IOM uint32_t TX_RST_CORE : 1; /*!< Write 1 then write 0 to this bit to reset UART Tx. */ - __IOM uint32_t RX_RST_CORE : 1; /*!< Write 1 then write 0 to this bit to reset UART Rx. */ - uint32_t : 4; - } bit; - } CLK_CONF; - - union { - __IOM uint32_t reg; /*!< UART Version register */ - - struct { - __IOM uint32_t DATE : 32; /*!< This is the version register. */ - } bit; - } DATE; - - union { - __IOM uint32_t reg; /*!< UART AFIFO Status */ - - struct { - __IM uint32_t TX_AFIFO_FULL : 1; /*!< Full signal of APB TX AFIFO. */ - __IM uint32_t TX_AFIFO_EMPTY : 1; /*!< Empty signal of APB TX AFIFO. */ - __IM uint32_t RX_AFIFO_FULL : 1; /*!< Full signal of APB RX AFIFO. */ - __IM uint32_t RX_AFIFO_EMPTY : 1; /*!< Empty signal of APB RX AFIFO. */ - uint32_t : 28; - } bit; - } AFIFO_STATUS; - __IM uint32_t RESERVED2; - - union { - __IOM uint32_t reg; /*!< UART Registers Configuration Update register */ - - struct { - __IOM uint32_t REG_UPDATE : 1; /*!< Software write 1 would synchronize registers into UART Core - clock domain and would be cleared by hardware after synchronization - is done. */ - uint32_t : 31; - } bit; - } REG_UPDATE; - - union { - __IOM uint32_t reg; /*!< UART ID register */ - - struct { - __IOM uint32_t ID : 32; /*!< This register is used to configure the uart_id. */ - } bit; - } ID; -} LP_UART_Type; /*!< Size = 160 (0xa0) */ - - - -/* =========================================================================================================================== */ -/* ================ MCPWM0 ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Motor Control Pulse-Width Modulation 0 (MCPWM0) - */ - -typedef struct { /*!< MCPWM0 Structure */ - - union { - __IOM uint32_t reg; /*!< PWM clock prescaler register. */ - - struct { - __IOM uint32_t CLK_PRESCALE : 8; /*!< Configures the prescaler value of clock, so that the period - of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1). */ - uint32_t : 24; - } bit; - } CLK_CFG; - __IOM uint32_t TIMER0_CFG0; /*!< PWM timer0 period and update method configuration register. */ - __IOM uint32_t TIMER0_CFG1; /*!< PWM timer0 working mode and start/stop control register. */ - - union { - __IOM uint32_t reg; /*!< PWM timer0 sync function configuration register. */ - - struct { - uint32_t : 1; - __IOM uint32_t SW : 1; /*!< Configures the generation of software sync. Toggling this bit - will trigger a software sync. */ - uint32_t : 30; - } bit; - } TIMER0_SYNC; - __IOM uint32_t TIMER0_STATUS; /*!< PWM timer0 status register. */ - __IM uint32_t RESERVED[8]; - - union { - __IOM uint32_t reg; /*!< Synchronization input selection register for PWM timers. */ - - struct { - __IOM uint32_t TIMER0_SYNCISEL : 3; /*!< Configures the selection of sync input for PWM timer0.\\1: PWM - timer0 sync_out\\2: PWM timer1 sync_out\\3: PWM timer2 - sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1 from GPIO - matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync - input selected */ - __IOM uint32_t TIMER1_SYNCISEL : 3; /*!< Configures the selection of sync input for PWM timer1.\\1: PWM - timer0 sync_out\\2: PWM timer1 sync_out\\3: PWM timer2 - sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1 from GPIO - matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync - input selected */ - __IOM uint32_t TIMER2_SYNCISEL : 3; /*!< Configures the selection of sync input for PWM timer2.\\1: PWM - timer0 sync_out\\2: PWM timer1 sync_out\\3: PWM timer2 - sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1 from GPIO - matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync - input selected */ - __IOM uint32_t EXTERNAL_SYNCI0_INVERT : 1;/*!< Configures whether or not to invert SYNC0 from GPIO matrix.\\0: - Not invert\\1: Invert */ - __IOM uint32_t EXTERNAL_SYNCI1_INVERT : 1;/*!< Configures whether or not to invert SYNC1 from GPIO matrix.\\0: - Not invert\\1: Invert */ - __IOM uint32_t EXTERNAL_SYNCI2_INVERT : 1;/*!< Configures whether or not to invert SYNC2 from GPIO matrix.\\0: - Not invert\\1: Invert */ - uint32_t : 20; - } bit; - } TIMER_SYNCI_CFG; - - union { - __IOM uint32_t reg; /*!< PWM operator's timer select register */ - - struct { - __IOM uint32_t OPERATOR0_TIMERSEL : 2; /*!< Configures which PWM timer will be the timing reference for - PWM operator0.\\0: Timer0\\1: Timer1\\2: Timer2\\3: Invalid, - will select timer2 */ - __IOM uint32_t OPERATOR1_TIMERSEL : 2; /*!< Configures which PWM timer will be the timing reference for - PWM operator1.\\0: Timer0\\1: Timer1\\2: Timer2\\3: Invalid, - will select timer2 */ - __IOM uint32_t OPERATOR2_TIMERSEL : 2; /*!< Configures which PWM timer will be the timing reference for - PWM operator2.\\0: Timer0\\1: Timer1\\2: Timer2\\3: Invalid, - will select timer2 */ - uint32_t : 26; - } bit; - } OPERATOR_TIMERSEL; - __IOM uint32_t GEN0_STMP_CFG; /*!< Generator0 time stamp registers A and B transfer status and - update method register */ - __IOM uint32_t GEN0_TSTMP_A; /*!< Generator0 time stamp A's shadow register */ - - union { - __IOM uint32_t TIMER1_CFG0; /*!< PWM timer1 period and update method configuration register. */ - __IOM uint32_t GEN0_TSTMP_B; /*!< Generator0 time stamp B's shadow register */ - }; - - union { - __IOM uint32_t TIMER1_CFG1; /*!< PWM timer1 working mode and start/stop control register. */ - __IOM uint32_t GEN0_CFG0; /*!< Generator0 fault event T0 and T1 configuration register */ - }; - - union { - union { - __IOM uint32_t reg; /*!< PWM timer1 sync function configuration register. */ - - struct { - uint32_t : 1; - __IOM uint32_t SW : 1; /*!< Configures the generation of software sync. Toggling this bit - will trigger a software sync. */ - uint32_t : 30; - } bit; - } TIMER1_SYNC; - __IOM uint32_t GEN0_FORCE; /*!< Generator0 output signal force mode register. */ - }; - - union { - __IOM uint32_t TIMER1_STATUS; /*!< PWM timer1 status register. */ - __IOM uint32_t GEN0_A; /*!< PWM0 output signal A actions configuration register */ - }; - __IOM uint32_t GEN0_B; /*!< PWM0 output signal B actions configuration register */ - - union { - __IOM uint32_t reg; /*!< Dead time configuration register */ - - struct { - __IOM uint32_t DB_FED_UPMETHOD : 4; /*!< Configures update method for FED (Falling edge delay) active - register.\\0: Immediate\\Bit0 is set to 1: TEZ\\Bit1 is - set to 1: TEP\\Bit2 is set to 1: Sync\\Bit3 is set to 1: - Disable the update */ - __IOM uint32_t DB_RED_UPMETHOD : 4; /*!< Configures update method for RED (rising edge delay) active - register.\\0: Immediate\\Bit0 is set to 1: TEZ\\Bit1 is - set to 1: TEP\\Bit2 is set to 1: Sync\\Bit3 is set to 1: - Disable the update */ - __IOM uint32_t DB_DEB_MODE : 1; /*!< Configures S8 in table, dual-edge B mode.\\0: fed/red take effect - on different path separately\\1: fed/red take effect on - B path, A out is in bypass or dulpB mode */ - __IOM uint32_t DB_A_OUTSWAP : 1; /*!< Configures S6 in table. */ - __IOM uint32_t DB_B_OUTSWAP : 1; /*!< Configures S7 in table. */ - __IOM uint32_t DB_RED_INSEL : 1; /*!< Configures S4 in table. */ - __IOM uint32_t DB_FED_INSEL : 1; /*!< Configures S5 in table. */ - __IOM uint32_t DB_RED_OUTINVERT : 1; /*!< Configures S2 in table. */ - __IOM uint32_t DB_FED_OUTINVERT : 1; /*!< Configures S3 in table. */ - __IOM uint32_t DB_A_OUTBYPASS : 1; /*!< Configures S1 in table. */ - __IOM uint32_t DB_B_OUTBYPASS : 1; /*!< Configures S0 in table. */ - uint32_t : 15; - } bit; - } DT0_CFG; - - union { - __IOM uint32_t reg; /*!< Falling edge delay (FED) shadow register */ - - struct { - __IOM uint32_t DB_FED : 16; /*!< Configures shadow register for FED. */ - uint32_t : 16; - } bit; - } DT0_FED_CFG; - - union { - __IOM uint32_t reg; /*!< Rising edge delay (RED) shadow register */ - - struct { - __IOM uint32_t DB_RED : 16; /*!< Configures shadow register for RED. */ - uint32_t : 16; - } bit; - } DT0_RED_CFG; - - union { - __IOM uint32_t reg; /*!< Carrier0 configuration register */ - - struct { - uint32_t : 8; - __IOM uint32_t CHOPPER_OSHTWTH : 4; /*!< Configures width of the first pulse. Measurement unit: Periods - of the carrier. */ - uint32_t : 20; - } bit; - } CARRIER0_CFG; - __IM uint32_t RESERVED1; - - union { - __IOM uint32_t reg; /*!< Software triggers for fault handler actions configuration register */ - - struct { - __IOM uint32_t TZ_CLR_OST : 1; /*!< Configures the generation of software one-shot mode action clear. - A toggle (software negate its value) triggers a clear for - on going one-shot mode action. */ - __IOM uint32_t TZ_CBCPULSE : 2; /*!< Configures the refresh moment selection of cycle-by-cycle mode - action.\\0: Select nothing, will not refresh\\Bit0 is set - to 1: TEZ\\Bit1 is set to 1: TEP */ - __IOM uint32_t TZ_FORCE_CBC : 1; /*!< Configures the generation of software cycle-by-cycle mode action. - A toggle (software negate its value) triggers a cycle-by-cycle - mode action. */ - __IOM uint32_t TZ_FORCE_OST : 1; /*!< Configures the generation of software one-shot mode action. - A toggle (software negate its value) triggers a one-shot - mode action. */ - uint32_t : 27; - } bit; - } FH0_CFG1; - - union { - __IOM uint32_t reg; /*!< Fault events status register */ - - struct { - __IM uint32_t TZ_CBC_ON : 1; /*!< Represents whether or not an cycle-by-cycle mode action is on - going.\\0:No action\\1: On going */ - __IM uint32_t TZ_OST_ON : 1; /*!< Represents whether or not an one-shot mode action is on going.\\0:No - action\\1: On going */ - uint32_t : 30; - } bit; - } FH0_STATUS; - __IM uint32_t RESERVED2[4]; - __IOM uint32_t TIMER2_CFG0; /*!< PWM timer2 period and update method configuration register. */ - __IOM uint32_t TIMER2_CFG1; /*!< PWM timer2 working mode and start/stop control register. */ - - union { - __IOM uint32_t reg; /*!< PWM timer2 sync function configuration register. */ - - struct { - uint32_t : 1; - __IOM uint32_t SW : 1; /*!< Configures the generation of software sync. Toggling this bit - will trigger a software sync. */ - uint32_t : 30; - } bit; - } TIMER2_SYNC; - __IOM uint32_t TIMER2_STATUS; /*!< PWM timer2 status register. */ - __IM uint32_t RESERVED3[20]; - - union { - __IOM uint32_t reg; /*!< Fault detection configuration and status register */ - - struct { - __IOM uint32_t F0_EN : 1; /*!< Configures whether or not to enable event_f0 generation.\\0: - Disable\\1: Enable */ - __IOM uint32_t F1_EN : 1; /*!< Configures whether or not to enable event_f1 generation.\\0: - Disable\\1: Enable */ - __IOM uint32_t F2_EN : 1; /*!< Configures whether or not to enable event_f2 generation.\\0: - Disable\\1: Enable */ - __IOM uint32_t F0_POLE : 1; /*!< Configures event_f0 trigger polarity on FAULT0 source from GPIO - matrix.\\0: Level low\\1: Level high */ - __IOM uint32_t F1_POLE : 1; /*!< Configures event_f1 trigger polarity on FAULT1 source from GPIO - matrix.\\0: Level low\\1: Level high */ - __IOM uint32_t F2_POLE : 1; /*!< Configures event_f2 trigger polarity on FAULT2 source from GPIO - matrix.\\0: Level low\\1: Level high */ - __IM uint32_t EVENT_F0 : 1; /*!< Represents whether or not an event_f0 is on going.\\0: No action\\1: - On going */ - __IM uint32_t EVENT_F1 : 1; /*!< Represents whether or not an event_f1 is on going.\\0: No action\\1: - On going */ - __IM uint32_t EVENT_F2 : 1; /*!< Represents whether or not an event_f2 is on going.\\0: No action\\1: - On going */ - uint32_t : 23; - } bit; - } FAULT_DETECT; - - union { - __IOM uint32_t reg; /*!< Capture timer configuration register */ - - struct { - __IOM uint32_t CAP_TIMER_EN : 1; /*!< Configures whether or not to enable capture timer increment.\\0: - Disable\\1: Enable */ - __IOM uint32_t CAP_SYNCI_EN : 1; /*!< Configures whether or not to enable capture timer sync.\\0: - Disable\\1: Enable */ - __IOM uint32_t CAP_SYNCI_SEL : 3; /*!< Configures the selection of capture module sync input.\\0: None\\1: - Timer0 sync_out\\2: Timer1 sync_out\\3: Timer2 sync_out\\4: - SYNC0 from GPIO matrix\\5: SYNC1 from GPIO matrix\\6: SYNC2 - from GPIO matrix\\7: None */ - __OM uint32_t CAP_SYNC_SW : 1; /*!< Configures the generation of a capture timer sync when reg_cap_synci_en - is 1.\\0: Invalid, No effect\\1: Trigger a capture timer - sync, capture timer is loaded with value in phase register */ - uint32_t : 26; - } bit; - } CAP_TIMER_CFG; - - union { - __IOM uint32_t reg; /*!< Capture timer sync phase register */ - - struct { - __IOM uint32_t CAP_PHASE : 32; /*!< Configures phase value for capture timer sync operation. */ - } bit; - } CAP_TIMER_PHASE; - __IOM uint32_t CAP_CH0_CFG; /*!< Capture channel 0 configuration register */ - __IM uint32_t RESERVED4[2]; - __IOM uint32_t CAP_CH0; /*!< CAP0 capture value register */ - __IOM uint32_t CAP_CH1_CFG; /*!< Capture channel 1 configuration register */ - __IM uint32_t RESERVED5; - - union { - __IOM uint32_t reg; /*!< Last capture trigger edge information register */ - - struct { - __IM uint32_t CAP0_EDGE : 1; /*!< Represents edge of last capture trigger on channel0.\\0: Posedge\\1: - Negedge */ - __IM uint32_t CAP1_EDGE : 1; /*!< Represents edge of last capture trigger on channel1.\\0: Posedge\\1: - Negedge */ - __IM uint32_t CAP2_EDGE : 1; /*!< Represents edge of last capture trigger on channel2.\\0: Posedge\\1: - Negedge */ - uint32_t : 29; - } bit; - } CAP_STATUS; - - union { - __IOM uint32_t CAP_CH1; /*!< CAP1 capture value register */ - - union { - __IOM uint32_t reg; /*!< Generator Update configuration register */ - - struct { - __IOM uint32_t GLOBAL_UP_EN : 1; /*!< Configures whether or not to enable global update for all active - registers in MCPWM module.\\0: Disable\\1: Enable */ - __IOM uint32_t GLOBAL_FORCE_UP : 1; /*!< Configures the generation of global forced update for all active - registers in MCPWM module. A toggle (software invert its - value) will trigger a global forced update. Valid only - when MCPWM_GLOBAL_UP_EN and MCPWM_OP0/1/2_UP_EN are both - set to 1. */ - __IOM uint32_t OP0_UP_EN : 1; /*!< Configures whether or not to enable update of active registers - in PWM operator0. Valid only when PWM_GLOBAL_UP_EN is set - to 1.\\0: Disable\\1: Enable */ - __IOM uint32_t OP0_FORCE_UP : 1; /*!< Configures the generation of forced update for active registers - in PWM operator0. A toggle (software invert its value) - will trigger a forced update. Valid only when MCPWM_GLOBAL_UP_EN - and MCPWM_OP0_UP_EN are both set to 1. */ - __IOM uint32_t OP1_UP_EN : 1; /*!< Configures whether or not to enable update of active registers - in PWM operator1. Valid only when PWM_GLOBAL_UP_EN is set - to 1.\\0: Disable\\1: Enable */ - __IOM uint32_t OP1_FORCE_UP : 1; /*!< Configures the generation of forced update for active registers - in PWM operator1. A toggle (software invert its value) - will trigger a forced update. Valid only when MCPWM_GLOBAL_UP_EN - and MCPWM_OP1_UP_EN are both set to 1. */ - __IOM uint32_t OP2_UP_EN : 1; /*!< Configures whether or not to enable update of active registers - in PWM operator2. Valid only when PWM_GLOBAL_UP_EN is set - to 1.\\0: Disable\\1: Enable */ - __IOM uint32_t OP2_FORCE_UP : 1; /*!< Configures the generation of forced update for active registers - in PWM operator2. A toggle (software invert its value) - will trigger a forced update. Valid only when MCPWM_GLOBAL_UP_EN - and MCPWM_OP2_UP_EN are both set to 1. */ - uint32_t : 24; - } bit; - } UPDATE_CFG; - }; - - union { - __IOM uint32_t CAP_CH2_CFG; /*!< Capture channel 2 configuration register */ - - union { - __IOM uint32_t reg; /*!< Interrupt enable register */ - - struct { - __IOM uint32_t TIMER0_STOP_INT_ENA : 1; /*!< Enable bit: Write 1 to enable the interrupt triggered when the - timer 0 stops. */ - __IOM uint32_t TIMER1_STOP_INT_ENA : 1; /*!< Enable bit: Write 1 to enable the interrupt triggered when the - timer 1 stops. */ - __IOM uint32_t TIMER2_STOP_INT_ENA : 1; /*!< Enable bit: Write 1 to enable the interrupt triggered when the - timer 2 stops. */ - __IOM uint32_t TIMER0_TEZ_INT_ENA : 1; /*!< Enable bit: Write 1 to enable the interrupt triggered by a PWM - timer 0 TEZ event. */ - __IOM uint32_t TIMER1_TEZ_INT_ENA : 1; /*!< Enable bit: Write 1 to enable the interrupt triggered by a PWM - timer 1 TEZ event. */ - __IOM uint32_t TIMER2_TEZ_INT_ENA : 1; /*!< Enable bit: Write 1 to enable the interrupt triggered by a PWM - timer 2 TEZ event. */ - __IOM uint32_t TIMER0_TEP_INT_ENA : 1; /*!< Enable bit: Write 1 to enable the interrupt triggered by a PWM - timer 0 TEP event. */ - __IOM uint32_t TIMER1_TEP_INT_ENA : 1; /*!< Enable bit: Write 1 to enable the interrupt triggered by a PWM - timer 1 TEP event. */ - __IOM uint32_t TIMER2_TEP_INT_ENA : 1; /*!< Enable bit: Write 1 to enable the interrupt triggered by a PWM - timer 2 TEP event. */ - __IOM uint32_t FAULT0_INT_ENA : 1; /*!< Enable bit: Write 1 to enable the interrupt triggered when event_f0 - starts. */ - __IOM uint32_t FAULT1_INT_ENA : 1; /*!< Enable bit: Write 1 to enable the interrupt triggered when event_f1 - starts. */ - __IOM uint32_t FAULT2_INT_ENA : 1; /*!< Enable bit: Write 1 to enable the interrupt triggered when event_f2 - starts. */ - __IOM uint32_t FAULT0_CLR_INT_ENA : 1; /*!< Enable bit: Write 1 to enable the interrupt triggered when event_f0 - clears. */ - __IOM uint32_t FAULT1_CLR_INT_ENA : 1; /*!< Enable bit: Write 1 to enable the interrupt triggered when event_f1 - clears. */ - __IOM uint32_t FAULT2_CLR_INT_ENA : 1; /*!< Enable bit: Write 1 to enable the interrupt triggered when event_f2 - clears. */ - __IOM uint32_t CMPR0_TEA_INT_ENA : 1; /*!< Enable bit: Write 1 to enable the interrupt triggered by a PWM - operator 0 TEA event. */ - __IOM uint32_t CMPR1_TEA_INT_ENA : 1; /*!< Enable bit: Write 1 to enable the interrupt triggered by a PWM - operator 1 TEA event. */ - __IOM uint32_t CMPR2_TEA_INT_ENA : 1; /*!< Enable bit: Write 1 to enable the interrupt triggered by a PWM - operator 2 TEA event. */ - __IOM uint32_t CMPR0_TEB_INT_ENA : 1; /*!< Enable bit: Write 1 to enable the interrupt triggered by a PWM - operator 0 TEB event. */ - __IOM uint32_t CMPR1_TEB_INT_ENA : 1; /*!< Enable bit: Write 1 to enable the interrupt triggered by a PWM - operator 1 TEB event. */ - __IOM uint32_t CMPR2_TEB_INT_ENA : 1; /*!< Enable bit: Write 1 to enable the interrupt triggered by a PWM - operator 2 TEB event. */ - __IOM uint32_t TZ0_CBC_INT_ENA : 1; /*!< Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle - mode action on PWM0. */ - __IOM uint32_t TZ1_CBC_INT_ENA : 1; /*!< Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle - mode action on PWM1. */ - __IOM uint32_t TZ2_CBC_INT_ENA : 1; /*!< Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle - mode action on PWM2. */ - __IOM uint32_t TZ0_OST_INT_ENA : 1; /*!< Enable bit: Write 1 to enable the interrupt triggered by a one-shot - mode action on PWM0. */ - __IOM uint32_t TZ1_OST_INT_ENA : 1; /*!< Enable bit: Write 1 to enable the interrupt triggered by a one-shot - mode action on PWM1. */ - __IOM uint32_t TZ2_OST_INT_ENA : 1; /*!< Enable bit: Write 1 to enable the interrupt triggered by a one-shot - mode action on PWM2. */ - __IOM uint32_t CAP0_INT_ENA : 1; /*!< Enable bit: Write 1 to enable the interrupt triggered by capture - on CAP0. */ - __IOM uint32_t CAP1_INT_ENA : 1; /*!< Enable bit: Write 1 to enable the interrupt triggered by capture - on CAP1. */ - __IOM uint32_t CAP2_INT_ENA : 1; /*!< Enable bit: Write 1 to enable the interrupt triggered by capture - on CAP2. */ - uint32_t : 2; - } bit; - } INT_ENA; - }; - - union { - __IOM uint32_t reg; /*!< Interrupt raw status register */ - - struct { - __IOM uint32_t TIMER0_STOP_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of the interrupt triggered - when the timer 0 stops. */ - __IOM uint32_t TIMER1_STOP_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of the interrupt triggered - when the timer 1 stops. */ - __IOM uint32_t TIMER2_STOP_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of the interrupt triggered - when the timer 2 stops. */ - __IOM uint32_t TIMER0_TEZ_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of the interrupt triggered - by a PWM timer 0 TEZ event. */ - __IOM uint32_t TIMER1_TEZ_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of the interrupt triggered - by a PWM timer 1 TEZ event. */ - __IOM uint32_t TIMER2_TEZ_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of the interrupt triggered - by a PWM timer 2 TEZ event. */ - __IOM uint32_t TIMER0_TEP_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of the interrupt triggered - by a PWM timer 0 TEP event. */ - __IOM uint32_t TIMER1_TEP_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of the interrupt triggered - by a PWM timer 1 TEP event. */ - __IOM uint32_t TIMER2_TEP_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of the interrupt triggered - by a PWM timer 2 TEP event. */ - __IOM uint32_t FAULT0_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of the interrupt triggered - when event_f0 starts. */ - __IOM uint32_t FAULT1_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of the interrupt triggered - when event_f1 starts. */ - __IOM uint32_t FAULT2_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of the interrupt triggered - when event_f2 starts. */ - __IOM uint32_t FAULT0_CLR_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of the interrupt triggered - when event_f0 clears. */ - __IOM uint32_t FAULT1_CLR_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of the interrupt triggered - when event_f1 clears. */ - __IOM uint32_t FAULT2_CLR_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of the interrupt triggered - when event_f2 clears. */ - __IOM uint32_t CMPR0_TEA_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of the interrupt triggered - by a PWM operator 0 TEA event */ - __IOM uint32_t CMPR1_TEA_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of the interrupt triggered - by a PWM operator 1 TEA event */ - __IOM uint32_t CMPR2_TEA_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of the interrupt triggered - by a PWM operator 2 TEA event */ - __IOM uint32_t CMPR0_TEB_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of the interrupt triggered - by a PWM operator 0 TEB event */ - __IOM uint32_t CMPR1_TEB_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of the interrupt triggered - by a PWM operator 1 TEB event */ - __IOM uint32_t CMPR2_TEB_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of the interrupt triggered - by a PWM operator 2 TEB event */ - __IOM uint32_t TZ0_CBC_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of the interrupt triggered - by a cycle-by-cycle mode action on PWM0. */ - __IOM uint32_t TZ1_CBC_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of the interrupt triggered - by a cycle-by-cycle mode action on PWM1. */ - __IOM uint32_t TZ2_CBC_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of the interrupt triggered - by a cycle-by-cycle mode action on PWM2. */ - __IOM uint32_t TZ0_OST_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of the interrupt triggered - by a one-shot mode action on PWM0. */ - __IOM uint32_t TZ1_OST_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of the interrupt triggered - by a one-shot mode action on PWM1. */ - __IOM uint32_t TZ2_OST_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of the interrupt triggered - by a one-shot mode action on PWM2. */ - __IOM uint32_t CAP0_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of the interrupt triggered - by capture on CAP0. */ - __IOM uint32_t CAP1_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of the interrupt triggered - by capture on CAP1. */ - __IOM uint32_t CAP2_INT_RAW : 1; /*!< Raw status bit: The raw interrupt status of the interrupt triggered - by capture on CAP2. */ - uint32_t : 2; - } bit; - } INT_RAW; - - union { - __IOM uint32_t reg; /*!< Interrupt masked status register */ - - struct { - __IM uint32_t TIMER0_STOP_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of the interrupt - triggered when the timer 0 stops. */ - __IM uint32_t TIMER1_STOP_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of the interrupt - triggered when the timer 1 stops. */ - __IM uint32_t TIMER2_STOP_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of the interrupt - triggered when the timer 2 stops. */ - __IM uint32_t TIMER0_TEZ_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of the interrupt - triggered by a PWM timer 0 TEZ event. */ - __IM uint32_t TIMER1_TEZ_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of the interrupt - triggered by a PWM timer 1 TEZ event. */ - __IM uint32_t TIMER2_TEZ_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of the interrupt - triggered by a PWM timer 2 TEZ event. */ - __IM uint32_t TIMER0_TEP_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of the interrupt - triggered by a PWM timer 0 TEP event. */ - __IM uint32_t TIMER1_TEP_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of the interrupt - triggered by a PWM timer 1 TEP event. */ - __IM uint32_t TIMER2_TEP_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of the interrupt - triggered by a PWM timer 2 TEP event. */ - __IM uint32_t FAULT0_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of the interrupt - triggered when event_f0 starts. */ - __IM uint32_t FAULT1_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of the interrupt - triggered when event_f1 starts. */ - __IM uint32_t FAULT2_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of the interrupt - triggered when event_f2 starts. */ - __IM uint32_t FAULT0_CLR_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of the interrupt - triggered when event_f0 clears. */ - __IM uint32_t FAULT1_CLR_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of the interrupt - triggered when event_f1 clears. */ - __IM uint32_t FAULT2_CLR_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of the interrupt - triggered when event_f2 clears. */ - __IM uint32_t CMPR0_TEA_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of the interrupt - triggered by a PWM operator 0 TEA event */ - __IM uint32_t CMPR1_TEA_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of the interrupt - triggered by a PWM operator 1 TEA event */ - __IM uint32_t CMPR2_TEA_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of the interrupt - triggered by a PWM operator 2 TEA event */ - __IM uint32_t CMPR0_TEB_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of the interrupt - triggered by a PWM operator 0 TEB event */ - __IM uint32_t CMPR1_TEB_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of the interrupt - triggered by a PWM operator 1 TEB event */ - __IM uint32_t CMPR2_TEB_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of the interrupt - triggered by a PWM operator 2 TEB event */ - __IM uint32_t TZ0_CBC_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of the interrupt - triggered by a cycle-by-cycle mode action on PWM0. */ - __IM uint32_t TZ1_CBC_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of the interrupt - triggered by a cycle-by-cycle mode action on PWM1. */ - __IM uint32_t TZ2_CBC_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of the interrupt - triggered by a cycle-by-cycle mode action on PWM2. */ - __IM uint32_t TZ0_OST_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of the interrupt - triggered by a one-shot mode action on PWM0. */ - __IM uint32_t TZ1_OST_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of the interrupt - triggered by a one-shot mode action on PWM1. */ - __IM uint32_t TZ2_OST_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of the interrupt - triggered by a one-shot mode action on PWM2. */ - __IM uint32_t CAP0_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of the interrupt - triggered by capture on CAP0. */ - __IM uint32_t CAP1_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of the interrupt - triggered by capture on CAP1. */ - __IM uint32_t CAP2_INT_ST : 1; /*!< Masked status bit: The masked interrupt status of the interrupt - triggered by capture on CAP2. */ - uint32_t : 2; - } bit; - } INT_ST; - - union { - __IOM uint32_t GEN1_STMP_CFG; /*!< Generator1 time stamp registers A and B transfer status and - update method register */ - __IOM uint32_t CAP_CH2; /*!< CAP2 capture value register */ - - union { - __IOM uint32_t reg; /*!< Interrupt clear register */ - - struct { - __OM uint32_t TIMER0_STOP_INT_CLR : 1; /*!< Clear bit: Write 1 to clear the interrupt triggered when the - timer 0 stops. */ - __OM uint32_t TIMER1_STOP_INT_CLR : 1; /*!< Clear bit: Write 1 to clear the interrupt triggered when the - timer 1 stops. */ - __OM uint32_t TIMER2_STOP_INT_CLR : 1; /*!< Clear bit: Write 1 to clear the interrupt triggered when the - timer 2 stops. */ - __OM uint32_t TIMER0_TEZ_INT_CLR : 1; /*!< Clear bit: Write 1 to clear the interrupt triggered by a PWM - timer 0 TEZ event. */ - __OM uint32_t TIMER1_TEZ_INT_CLR : 1; /*!< Clear bit: Write 1 to clear the interrupt triggered by a PWM - timer 1 TEZ event. */ - __OM uint32_t TIMER2_TEZ_INT_CLR : 1; /*!< Clear bit: Write 1 to clear the interrupt triggered by a PWM - timer 2 TEZ event. */ - __OM uint32_t TIMER0_TEP_INT_CLR : 1; /*!< Clear bit: Write 1 to clear the interrupt triggered by a PWM - timer 0 TEP event. */ - __OM uint32_t TIMER1_TEP_INT_CLR : 1; /*!< Clear bit: Write 1 to clear the interrupt triggered by a PWM - timer 1 TEP event. */ - __OM uint32_t TIMER2_TEP_INT_CLR : 1; /*!< Clear bit: Write 1 to clear the interrupt triggered by a PWM - timer 2 TEP event. */ - __OM uint32_t FAULT0_INT_CLR : 1; /*!< Clear bit: Write 1 to clear the interrupt triggered when event_f0 - starts. */ - __OM uint32_t FAULT1_INT_CLR : 1; /*!< Clear bit: Write 1 to clear the interrupt triggered when event_f1 - starts. */ - __OM uint32_t FAULT2_INT_CLR : 1; /*!< Clear bit: Write 1 to clear the interrupt triggered when event_f2 - starts. */ - __OM uint32_t FAULT0_CLR_INT_CLR : 1; /*!< Clear bit: Write 1 to clear the interrupt triggered when event_f0 - clears. */ - __OM uint32_t FAULT1_CLR_INT_CLR : 1; /*!< Clear bit: Write 1 to clear the interrupt triggered when event_f1 - clears. */ - __OM uint32_t FAULT2_CLR_INT_CLR : 1; /*!< Clear bit: Write 1 to clear the interrupt triggered when event_f2 - clears. */ - __OM uint32_t CMPR0_TEA_INT_CLR : 1; /*!< Clear bit: Write 1 to clear the interrupt triggered by a PWM - operator 0 TEA event */ - __OM uint32_t CMPR1_TEA_INT_CLR : 1; /*!< Clear bit: Write 1 to clear the interrupt triggered by a PWM - operator 1 TEA event */ - __OM uint32_t CMPR2_TEA_INT_CLR : 1; /*!< Clear bit: Write 1 to clear the interrupt triggered by a PWM - operator 2 TEA event */ - __OM uint32_t CMPR0_TEB_INT_CLR : 1; /*!< Clear bit: Write 1 to clear the interrupt triggered by a PWM - operator 0 TEB event */ - __OM uint32_t CMPR1_TEB_INT_CLR : 1; /*!< Clear bit: Write 1 to clear the interrupt triggered by a PWM - operator 1 TEB event */ - __OM uint32_t CMPR2_TEB_INT_CLR : 1; /*!< Clear bit: Write 1 to clear the interrupt triggered by a PWM - operator 2 TEB event */ - __OM uint32_t TZ0_CBC_INT_CLR : 1; /*!< Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle - mode action on PWM0. */ - __OM uint32_t TZ1_CBC_INT_CLR : 1; /*!< Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle - mode action on PWM1. */ - __OM uint32_t TZ2_CBC_INT_CLR : 1; /*!< Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle - mode action on PWM2. */ - __OM uint32_t TZ0_OST_INT_CLR : 1; /*!< Clear bit: Write 1 to clear the interrupt triggered by a one-shot - mode action on PWM0. */ - __OM uint32_t TZ1_OST_INT_CLR : 1; /*!< Clear bit: Write 1 to clear the interrupt triggered by a one-shot - mode action on PWM1. */ - __OM uint32_t TZ2_OST_INT_CLR : 1; /*!< Clear bit: Write 1 to clear the interrupt triggered by a one-shot - mode action on PWM2. */ - __OM uint32_t CAP0_INT_CLR : 1; /*!< Clear bit: Write 1 to clear the interrupt triggered by capture - on CAP0. */ - __OM uint32_t CAP1_INT_CLR : 1; /*!< Clear bit: Write 1 to clear the interrupt triggered by capture - on CAP1. */ - __OM uint32_t CAP2_INT_CLR : 1; /*!< Clear bit: Write 1 to clear the interrupt triggered by capture - on CAP2. */ - uint32_t : 2; - } bit; - } INT_CLR; - }; - - union { - __IOM uint32_t GEN1_TSTMP_A; /*!< Generator1 time stamp A's shadow register */ - - union { - __IOM uint32_t reg; /*!< Event enable register */ - - struct { - __IOM uint32_t EVT_TIMER0_STOP_EN : 1; /*!< Configures whether or not to enable timer0 stop event generate.\\0: - Disable\\1: Enable */ - __IOM uint32_t EVT_TIMER1_STOP_EN : 1; /*!< Configures whether or not to enable timer1 stop event generate.\\0: - Disable\\1: Enable */ - __IOM uint32_t EVT_TIMER2_STOP_EN : 1; /*!< Configures whether or not to enable timer2 stop event generate.\\0: - Disable\\1: Enable */ - __IOM uint32_t EVT_TIMER0_TEZ_EN : 1; /*!< Configures whether or not to enable timer0 equal zero event - generate.\\0: Disable\\1: Enable */ - __IOM uint32_t EVT_TIMER1_TEZ_EN : 1; /*!< Configures whether or not to enable timer1 equal zero event - generate.\\0: Disable\\1: Enable */ - __IOM uint32_t EVT_TIMER2_TEZ_EN : 1; /*!< Configures whether or not to enable timer2 equal zero event - generate.\\0: Disable\\1: Enable */ - __IOM uint32_t EVT_TIMER0_TEP_EN : 1; /*!< Configures whether or not to enable timer0 equal period event - generate.\\0: Disable\\1: Enable */ - __IOM uint32_t EVT_TIMER1_TEP_EN : 1; /*!< Configures whether or not to enable timer1 equal period event - generate.\\0: Disable\\1: Enable */ - __IOM uint32_t EVT_TIMER2_TEP_EN : 1; /*!< Configures whether or not to enable timer2 equal period event - generate.\\0: Disable\\1: Enable */ - __IOM uint32_t EVT_OP0_TEA_EN : 1; /*!< Configures whether or not to enable PWM generator0 timer equal - a event generate.\\0: Disable\\1: Enable */ - __IOM uint32_t EVT_OP1_TEA_EN : 1; /*!< Configures whether or not to enable PWM generator1 timer equal - a event generate.\\0: Disable\\1: Enable */ - __IOM uint32_t EVT_OP2_TEA_EN : 1; /*!< Configures whether or not to enable PWM generator2 timer equal - a event generate.\\0: Disable\\1: Enable */ - __IOM uint32_t EVT_OP0_TEB_EN : 1; /*!< Configures whether or not to enable PWM generator0 timer equal - b event generate.\\0: Disable\\1: Enable */ - __IOM uint32_t EVT_OP1_TEB_EN : 1; /*!< Configures whether or not to enable PWM generator1 timer equal - b event generate.\\0: Disable\\1: Enable */ - __IOM uint32_t EVT_OP2_TEB_EN : 1; /*!< Configures whether or not to enable PWM generator2 timer equal - b event generate.\\0: Disable\\1: Enable */ - __IOM uint32_t EVT_F0_EN : 1; /*!< Configures whether or not to enable fault0 event generate.\\0: - Disable\\1: Enable */ - __IOM uint32_t EVT_F1_EN : 1; /*!< Configures whether or not to enable fault1 event generate.\\0: - Disable\\1: Enable */ - __IOM uint32_t EVT_F2_EN : 1; /*!< Configures whether or not to enable fault2 event generate.\\0: - Disable\\1: Enable */ - __IOM uint32_t EVT_F0_CLR_EN : 1; /*!< Configures whether or not to enable fault0 clear event generate.\\0: - Disable\\1: Enable */ - __IOM uint32_t EVT_F1_CLR_EN : 1; /*!< Configures whether or not to enable fault1 clear event generate.\\0: - Disable\\1: Enable */ - __IOM uint32_t EVT_F2_CLR_EN : 1; /*!< Configures whether or not to enable fault2 clear event generate.\\0: - Disable\\1: Enable */ - __IOM uint32_t EVT_TZ0_CBC_EN : 1; /*!< Configures whether or not to enable cycle-by-cycle trip0 event - generate.\\0: Disable\\1: Enable */ - __IOM uint32_t EVT_TZ1_CBC_EN : 1; /*!< Configures whether or not to enable cycle-by-cycle trip1 event - generate.\\0: Disable\\1: Enable */ - __IOM uint32_t EVT_TZ2_CBC_EN : 1; /*!< Configures whether or not to enable cycle-by-cycle trip2 event - generate.\\0: Disable\\1: Enable */ - __IOM uint32_t EVT_TZ0_OST_EN : 1; /*!< Configures whether or not to enable one-shot trip0 event generate.\\0: - Disable\\1: Enable */ - __IOM uint32_t EVT_TZ1_OST_EN : 1; /*!< Configures whether or not to enable one-shot trip1 event generate.\\0: - Disable\\1: Enable */ - __IOM uint32_t EVT_TZ2_OST_EN : 1; /*!< Configures whether or not to enable one-shot trip2 event generate.\\0: - Disable\\1: Enable */ - __IOM uint32_t EVT_CAP0_EN : 1; /*!< Configures whether or not to enable capture0 event generate.\\0: - Disable\\1: Enable */ - __IOM uint32_t EVT_CAP1_EN : 1; /*!< Configures whether or not to enable capture1 event generate.\\0: - Disable\\1: Enable */ - __IOM uint32_t EVT_CAP2_EN : 1; /*!< Configures whether or not to enable capture2 event generate.\\0: - Disable\\1: Enable */ - uint32_t : 2; - } bit; - } EVT_EN; - }; - - union { - __IOM uint32_t GEN1_TSTMP_B; /*!< Generator1 time stamp B's shadow register */ - - union { - __IOM uint32_t reg; /*!< Task enable register */ - - struct { - __IOM uint32_t TASK_CMPR0_A_UP_EN : 1; /*!< Configures whether or not to enable PWM generator0 timer stamp - A's shadow register update task receive.\\0: Disable\\1: - Enable */ - __IOM uint32_t TASK_CMPR1_A_UP_EN : 1; /*!< Configures whether or not to enable PWM generator1 timer stamp - A's shadow register update task receive.\\0: Disable\\1: - Enable */ - __IOM uint32_t TASK_CMPR2_A_UP_EN : 1; /*!< Configures whether or not to enable PWM generator2 timer stamp - A's shadow register update task receive.\\0: Disable\\1: - Enable */ - __IOM uint32_t TASK_CMPR0_B_UP_EN : 1; /*!< Configures whether or not to enable PWM generator0 timer stamp - B's shadow register update task receive.\\0: Disable\\1: - Enable */ - __IOM uint32_t TASK_CMPR1_B_UP_EN : 1; /*!< Configures whether or not to enable PWM generator1 timer stamp - B's shadow register update task receive.\\0: Disable\\1: - Enable */ - __IOM uint32_t TASK_CMPR2_B_UP_EN : 1; /*!< Configures whether or not to enable PWM generator2 timer stamp - B's shadow register update task receive.\\0: Disable\\1: - Enable */ - __IOM uint32_t TASK_GEN_STOP_EN : 1; /*!< Configures whether or not to enable all PWM generate stop task - receive.\\0: Disable\\1: Enable */ - __IOM uint32_t TASK_TIMER0_SYNC_EN : 1; /*!< Configures whether or not to enable timer0 sync task receive.\\0: - Disable\\1: Enable */ - __IOM uint32_t TASK_TIMER1_SYNC_EN : 1; /*!< Configures whether or not to enable timer1 sync task receive.\\0: - Disable\\1: Enable */ - __IOM uint32_t TASK_TIMER2_SYNC_EN : 1; /*!< Configures whether or not to enable timer2 sync task receive.\\0: - Disable\\1: Enable */ - __IOM uint32_t TASK_TIMER0_PERIOD_UP_EN : 1;/*!< Configures whether or not to enable timer0 period update task - receive.\\0: Disable\\1: Enable */ - __IOM uint32_t TASK_TIMER1_PERIOD_UP_EN : 1;/*!< Configures whether or not to enable timer1 period update task - receive.\\0: Disable\\1: Enable */ - __IOM uint32_t TASK_TIMER2_PERIOD_UP_EN : 1;/*!< Configures whether or not to enable timer2 period update task - receive.\\0: Disable\\1: Enable */ - __IOM uint32_t TASK_TZ0_OST_EN : 1; /*!< Configures whether or not to enable one shot trip0 task receive.\\0: - Disable\\1: Enable */ - __IOM uint32_t TASK_TZ1_OST_EN : 1; /*!< Configures whether or not to enable one shot trip1 task receive.\\0: - Disable\\1: Enable */ - __IOM uint32_t TASK_TZ2_OST_EN : 1; /*!< Configures whether or not to enable one shot trip2 task receive.\\0: - Disable\\1: Enable */ - __IOM uint32_t TASK_CLR0_OST_EN : 1; /*!< Configures whether or not to enable one shot trip0 clear task - receive.\\0: Disable\\1: Enable */ - __IOM uint32_t TASK_CLR1_OST_EN : 1; /*!< Configures whether or not to enable one shot trip1 clear task - receive.\\0: Disable\\1: Enable */ - __IOM uint32_t TASK_CLR2_OST_EN : 1; /*!< Configures whether or not to enable one shot trip2 clear task - receive.\\0: Disable\\1: Enable */ - __IOM uint32_t TASK_CAP0_EN : 1; /*!< Configures whether or not to enable capture0 task receive.\\0: - Disable\\1: Enable */ - __IOM uint32_t TASK_CAP1_EN : 1; /*!< Configures whether or not to enable capture1 task receive.\\0: - Disable\\1: Enable */ - __IOM uint32_t TASK_CAP2_EN : 1; /*!< Configures whether or not to enable capture2 task receive.\\0: - Disable\\1: Enable */ - uint32_t : 10; - } bit; - } TASK_EN; - }; - - union { - __IOM uint32_t GEN1_CFG0; /*!< Generator1 fault event T0 and T1 configuration register */ - - union { - __IOM uint32_t reg; /*!< Event enable register2 */ - - struct { - __IOM uint32_t EVT_OP0_TEE1_EN : 1; /*!< Configures whether or not to enable PWM generator0 timer equal - OP0_TSTMP_E1_REG event generate.\\0: Disable\\1: Enable */ - __IOM uint32_t EVT_OP1_TEE1_EN : 1; /*!< Configures whether or not to enable PWM generator1 timer equal - OP1_TSTMP_E1_REG event generate.\\0: Disable\\1: Enable */ - __IOM uint32_t EVT_OP2_TEE1_EN : 1; /*!< Configures whether or not to enable PWM generator2 timer equal - OP2_TSTMP_E1_REG event generate.\\0: Disable\\1: Enable */ - __IOM uint32_t EVT_OP0_TEE2_EN : 1; /*!< Configures whether or not to enable PWM generator0 timer equal - OP0_TSTMP_E2_REG event generate.\\0: Disable\\1: Enable */ - __IOM uint32_t EVT_OP1_TEE2_EN : 1; /*!< Configures whether or not to enable PWM generator1 timer equal - OP1_TSTMP_E2_REG event generate.\\0: Disable\\1: Enable */ - __IOM uint32_t EVT_OP2_TEE2_EN : 1; /*!< Configures whether or not to enable PWM generator2 timer equal - OP2_TSTMP_E2_REG event generate.\\0: Disable\\1: Enable */ - uint32_t : 26; - } bit; - } EVT_EN2; - }; - - union { - __IOM uint32_t GEN1_FORCE; /*!< Generator1 output signal force mode register. */ - __IOM uint32_t OP0_TSTMP_E1; /*!< Generator0 timer stamp E1 value register */ - }; - - union { - __IOM uint32_t GEN1_A; /*!< PWM1 output signal A actions configuration register */ - __IOM uint32_t OP0_TSTMP_E2; /*!< Generator0 timer stamp E2 value register */ - }; - __IOM uint32_t GEN1_B; /*!< PWM1 output signal B actions configuration register */ - - union { - __IOM uint32_t reg; /*!< Dead time configuration register */ - - struct { - __IOM uint32_t DB_FED_UPMETHOD : 4; /*!< Configures update method for FED (Falling edge delay) active - register.\\0: Immediate\\Bit0 is set to 1: TEZ\\Bit1 is - set to 1: TEP\\Bit2 is set to 1: Sync\\Bit3 is set to 1: - Disable the update */ - __IOM uint32_t DB_RED_UPMETHOD : 4; /*!< Configures update method for RED (rising edge delay) active - register.\\0: Immediate\\Bit0 is set to 1: TEZ\\Bit1 is - set to 1: TEP\\Bit2 is set to 1: Sync\\Bit3 is set to 1: - Disable the update */ - __IOM uint32_t DB_DEB_MODE : 1; /*!< Configures S8 in table, dual-edge B mode.\\0: fed/red take effect - on different path separately\\1: fed/red take effect on - B path, A out is in bypass or dulpB mode */ - __IOM uint32_t DB_A_OUTSWAP : 1; /*!< Configures S6 in table. */ - __IOM uint32_t DB_B_OUTSWAP : 1; /*!< Configures S7 in table. */ - __IOM uint32_t DB_RED_INSEL : 1; /*!< Configures S4 in table. */ - __IOM uint32_t DB_FED_INSEL : 1; /*!< Configures S5 in table. */ - __IOM uint32_t DB_RED_OUTINVERT : 1; /*!< Configures S2 in table. */ - __IOM uint32_t DB_FED_OUTINVERT : 1; /*!< Configures S3 in table. */ - __IOM uint32_t DB_A_OUTBYPASS : 1; /*!< Configures S1 in table. */ - __IOM uint32_t DB_B_OUTBYPASS : 1; /*!< Configures S0 in table. */ - uint32_t : 15; - } bit; - } DT1_CFG; - - union { - __IOM uint32_t reg; /*!< Falling edge delay (FED) shadow register */ - - struct { - __IOM uint32_t DB_FED : 16; /*!< Configures shadow register for FED. */ - uint32_t : 16; - } bit; - } DT1_FED_CFG; - - union { - __IOM uint32_t reg; /*!< Rising edge delay (RED) shadow register */ - - struct { - __IOM uint32_t DB_RED : 16; /*!< Configures shadow register for RED. */ - uint32_t : 16; - } bit; - } DT1_RED_CFG; - - union { - union { - __IOM uint32_t reg; /*!< Carrier1 configuration register */ - - struct { - uint32_t : 8; - __IOM uint32_t CHOPPER_OSHTWTH : 4; /*!< Configures width of the first pulse. Measurement unit: Periods - of the carrier. */ - uint32_t : 20; - } bit; - } CARRIER1_CFG; - - union { - __IOM uint32_t reg; /*!< Global configuration register */ - - struct { - __IOM uint32_t EN : 1; /*!< Configures whether or not to open register clock gate.\\0: Open - the clock gate only when application writes registers\\1: - Force open the clock gate for register */ - uint32_t : 31; - } bit; - } CLK; - }; - - union { - __IOM uint32_t reg; /*!< Version register. */ - - struct { - __IOM uint32_t DATE : 28; /*!< Configures the version. */ - uint32_t : 4; - } bit; - } VERSION; - - union { - union { - __IOM uint32_t reg; /*!< Software triggers for fault handler actions configuration register */ - - struct { - __IOM uint32_t TZ_CLR_OST : 1; /*!< Configures the generation of software one-shot mode action clear. - A toggle (software negate its value) triggers a clear for - on going one-shot mode action. */ - __IOM uint32_t TZ_CBCPULSE : 2; /*!< Configures the refresh moment selection of cycle-by-cycle mode - action.\\0: Select nothing, will not refresh\\Bit0 is set - to 1: TEZ\\Bit1 is set to 1: TEP */ - __IOM uint32_t TZ_FORCE_CBC : 1; /*!< Configures the generation of software cycle-by-cycle mode action. - A toggle (software negate its value) triggers a cycle-by-cycle - mode action. */ - __IOM uint32_t TZ_FORCE_OST : 1; /*!< Configures the generation of software one-shot mode action. - A toggle (software negate its value) triggers a one-shot - mode action. */ - uint32_t : 27; - } bit; - } FH1_CFG1; - __IOM uint32_t OP1_TSTMP_E1; /*!< Generator1 timer stamp E1 value register */ - }; - - union { - union { - __IOM uint32_t reg; /*!< Fault events status register */ - - struct { - __IM uint32_t TZ_CBC_ON : 1; /*!< Represents whether or not an cycle-by-cycle mode action is on - going.\\0:No action\\1: On going */ - __IM uint32_t TZ_OST_ON : 1; /*!< Represents whether or not an one-shot mode action is on going.\\0:No - action\\1: On going */ - uint32_t : 30; - } bit; - } FH1_STATUS; - __IOM uint32_t OP1_TSTMP_E2; /*!< Generator1 timer stamp E2 value register */ - }; - __IM uint32_t RESERVED6[6]; - __IOM uint32_t OP2_TSTMP_E1; /*!< Generator2 timer stamp E1 value register */ - __IOM uint32_t OP2_TSTMP_E2; /*!< Generator2 timer stamp E2 value register */ - __IM uint32_t RESERVED7[34]; - __IOM uint32_t GEN2_STMP_CFG; /*!< Generator2 time stamp registers A and B transfer status and - update method register */ - __IOM uint32_t GEN2_TSTMP_A; /*!< Generator2 time stamp A's shadow register */ - __IOM uint32_t GEN2_TSTMP_B; /*!< Generator2 time stamp B's shadow register */ - __IOM uint32_t GEN2_CFG0; /*!< Generator2 fault event T0 and T1 configuration register */ - __IOM uint32_t GEN2_FORCE; /*!< Generator2 output signal force mode register. */ - __IOM uint32_t GEN2_A; /*!< PWM2 output signal A actions configuration register */ - __IOM uint32_t GEN2_B; /*!< PWM2 output signal B actions configuration register */ - - union { - __IOM uint32_t reg; /*!< Dead time configuration register */ - - struct { - __IOM uint32_t DB_FED_UPMETHOD : 4; /*!< Configures update method for FED (Falling edge delay) active - register.\\0: Immediate\\Bit0 is set to 1: TEZ\\Bit1 is - set to 1: TEP\\Bit2 is set to 1: Sync\\Bit3 is set to 1: - Disable the update */ - __IOM uint32_t DB_RED_UPMETHOD : 4; /*!< Configures update method for RED (rising edge delay) active - register.\\0: Immediate\\Bit0 is set to 1: TEZ\\Bit1 is - set to 1: TEP\\Bit2 is set to 1: Sync\\Bit3 is set to 1: - Disable the update */ - __IOM uint32_t DB_DEB_MODE : 1; /*!< Configures S8 in table, dual-edge B mode.\\0: fed/red take effect - on different path separately\\1: fed/red take effect on - B path, A out is in bypass or dulpB mode */ - __IOM uint32_t DB_A_OUTSWAP : 1; /*!< Configures S6 in table. */ - __IOM uint32_t DB_B_OUTSWAP : 1; /*!< Configures S7 in table. */ - __IOM uint32_t DB_RED_INSEL : 1; /*!< Configures S4 in table. */ - __IOM uint32_t DB_FED_INSEL : 1; /*!< Configures S5 in table. */ - __IOM uint32_t DB_RED_OUTINVERT : 1; /*!< Configures S2 in table. */ - __IOM uint32_t DB_FED_OUTINVERT : 1; /*!< Configures S3 in table. */ - __IOM uint32_t DB_A_OUTBYPASS : 1; /*!< Configures S1 in table. */ - __IOM uint32_t DB_B_OUTBYPASS : 1; /*!< Configures S0 in table. */ - uint32_t : 15; - } bit; - } DT2_CFG; - - union { - __IOM uint32_t reg; /*!< Falling edge delay (FED) shadow register */ - - struct { - __IOM uint32_t DB_FED : 16; /*!< Configures shadow register for FED. */ - uint32_t : 16; - } bit; - } DT2_FED_CFG; - - union { - __IOM uint32_t reg; /*!< Rising edge delay (RED) shadow register */ - - struct { - __IOM uint32_t DB_RED : 16; /*!< Configures shadow register for RED. */ - uint32_t : 16; - } bit; - } DT2_RED_CFG; - - union { - __IOM uint32_t reg; /*!< Carrier2 configuration register */ - - struct { - uint32_t : 8; - __IOM uint32_t CHOPPER_OSHTWTH : 4; /*!< Configures width of the first pulse. Measurement unit: Periods - of the carrier. */ - uint32_t : 20; - } bit; - } CARRIER2_CFG; - __IM uint32_t RESERVED8; - - union { - __IOM uint32_t reg; /*!< Software triggers for fault handler actions configuration register */ - - struct { - __IOM uint32_t TZ_CLR_OST : 1; /*!< Configures the generation of software one-shot mode action clear. - A toggle (software negate its value) triggers a clear for - on going one-shot mode action. */ - __IOM uint32_t TZ_CBCPULSE : 2; /*!< Configures the refresh moment selection of cycle-by-cycle mode - action.\\0: Select nothing, will not refresh\\Bit0 is set - to 1: TEZ\\Bit1 is set to 1: TEP */ - __IOM uint32_t TZ_FORCE_CBC : 1; /*!< Configures the generation of software cycle-by-cycle mode action. - A toggle (software negate its value) triggers a cycle-by-cycle - mode action. */ - __IOM uint32_t TZ_FORCE_OST : 1; /*!< Configures the generation of software one-shot mode action. - A toggle (software negate its value) triggers a one-shot - mode action. */ - uint32_t : 27; - } bit; - } FH2_CFG1; - - union { - __IOM uint32_t reg; /*!< Fault events status register */ - - struct { - __IM uint32_t TZ_CBC_ON : 1; /*!< Represents whether or not an cycle-by-cycle mode action is on - going.\\0:No action\\1: On going */ - __IM uint32_t TZ_OST_ON : 1; /*!< Represents whether or not an one-shot mode action is on going.\\0:No - action\\1: On going */ - uint32_t : 30; - } bit; - } FH2_STATUS; -} MCPWM0_Type; /*!< Size = 564 (0x234) */ - - - -/* =========================================================================================================================== */ -/* ================ PARL_IO ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Parallel IO Controller (PARL_IO) - */ - -typedef struct { /*!< PARL_IO Structure */ - - union { - __IOM uint32_t reg; /*!< Parallel RX Sampling mode configuration register. */ - - struct { - uint32_t : 21; - __IOM uint32_t RX_EXT_EN_SEL : 4; /*!< Configures rx external enable signal selection from IO PAD. */ - __IOM uint32_t RX_SW_EN : 1; /*!< Set this bit to enable data sampling by software. */ - __IOM uint32_t RX_EXT_EN_INV : 1; /*!< Set this bit to invert the external enable signal. */ - __IOM uint32_t RX_PULSE_SUBMODE_SEL : 3; /*!< Configures the rxd pulse sampling submode. 4'd0: positive pulse - start(data bit included) && positive pulse end(data bit - included)4'd1: positive pulse start(data bit included) - && positive pulse end (data bit excluded)4'd2: positive - pulse start(data bit excluded) && positive pulse end (data - bit included)4'd3: positive pulse start(data bit excluded) - && positive pulse end (data bit excluded)4'd4: positive - pulse start(data bit included) && length end4'd5: positive - pulse start(data bit excluded) && length end */ - __IOM uint32_t RX_SMP_MODE_SEL : 2; /*!< Configures the rxd sampling mode. 2'b00: external level enable - mode2'b01: external pulse enable mode 2'b10: internal software - enable mode */ - } bit; - } RX_MODE_CFG; - - union { - __IOM uint32_t reg; /*!< Parallel RX data configuration register. */ - - struct { - uint32_t : 9; - __IOM uint32_t RX_BITLEN : 19; /*!< Configures expected byte number of received data. */ - __IOM uint32_t RX_DATA_ORDER_INV : 1; /*!< Set this bit to invert bit order of one byte sent from RX_FIFO - to DMA. */ - __IOM uint32_t RX_BUS_WID_SEL : 3; /*!< Configures the rxd bus width. 3'd0: bus width is 1.3'd1: bus - width is 2.3'd2: bus width is 4.3'd3: bus width is 8. */ - } bit; - } RX_DATA_CFG; - - union { - __IOM uint32_t reg; /*!< Parallel RX general configuration register. */ - - struct { - uint32_t : 12; - __IOM uint32_t RX_GATING_EN : 1; /*!< Set this bit to enable the clock gating of output rx clock. */ - __IOM uint32_t RX_TIMEOUT_THRES : 16; /*!< Configures threshold of timeout counter. */ - __IOM uint32_t RX_TIMEOUT_EN : 1; /*!< Set this bit to enable timeout function to generate error eof. */ - __IOM uint32_t RX_EOF_GEN_SEL : 1; /*!< Configures the DMA eof generated mechanism. 1'b0: eof generated - by data bit length. 1'b1: eof generated by external enable - signal. */ - uint32_t : 1; - } bit; - } RX_GENRL_CFG; - - union { - __IOM uint32_t reg; /*!< Parallel RX Start configuration register. */ - - struct { - uint32_t : 31; - __IOM uint32_t RX_START : 1; /*!< Set this bit to start rx data sampling. */ - } bit; - } RX_START_CFG; - - union { - __IOM uint32_t reg; /*!< Parallel TX data configuration register. */ - - struct { - uint32_t : 9; - __IOM uint32_t TX_BITLEN : 19; /*!< Configures expected byte number of sent data. */ - __IOM uint32_t TX_DATA_ORDER_INV : 1; /*!< Set this bit to invert bit order of one byte sent from TX_FIFO - to IO data. */ - __IOM uint32_t TX_BUS_WID_SEL : 3; /*!< Configures the txd bus width. 3'd0: bus width is 1.3'd1: bus - width is 2.3'd2: bus width is 4.3'd3: bus width is 8. */ - } bit; - } TX_DATA_CFG; - - union { - __IOM uint32_t reg; /*!< Parallel TX Start configuration register. */ - - struct { - uint32_t : 31; - __IOM uint32_t TX_START : 1; /*!< Set this bit to start tx data transmit. */ - } bit; - } TX_START_CFG; - - union { - __IOM uint32_t reg; /*!< Parallel TX general configuration register. */ - - struct { - uint32_t : 13; - __IOM uint32_t TX_EOF_GEN_SEL : 1; /*!< Configures the tx eof generated mechanism. 1'b0: eof generated - by data bit length. 1'b1: eof generated by DMA eof. */ - __IOM uint32_t TX_IDLE_VALUE : 16; /*!< Configures bus value of transmitter in IDLE state. */ - __IOM uint32_t TX_GATING_EN : 1; /*!< Set this bit to enable the clock gating of output tx clock. */ - __IOM uint32_t TX_VALID_OUTPUT_EN : 1; /*!< Set this bit to enable the output of tx data valid signal. */ - } bit; - } TX_GENRL_CFG; - - union { - __IOM uint32_t reg; /*!< Parallel IO FIFO configuration register. */ - - struct { - uint32_t : 30; - __IOM uint32_t TX_FIFO_SRST : 1; /*!< Set this bit to reset async fifo in tx module. */ - __IOM uint32_t RX_FIFO_SRST : 1; /*!< Set this bit to reset async fifo in rx module. */ - } bit; - } FIFO_CFG; - - union { - __IOM uint32_t reg; /*!< Parallel IO FIFO configuration register. */ - - struct { - uint32_t : 31; - __OM uint32_t RX_REG_UPDATE : 1; /*!< Set this bit to update rx register configuration. */ - } bit; - } REG_UPDATE; - - union { - __IOM uint32_t reg; /*!< Parallel IO module status register0. */ - - struct { - uint32_t : 31; - __IM uint32_t TX_READY : 1; /*!< Represents the status that tx is ready to transmit. */ - } bit; - } ST; - - union { - __IOM uint32_t reg; /*!< Parallel IO interrupt enable singal configuration register. */ - - struct { - __IOM uint32_t TX_FIFO_REMPTY_INT_ENA : 1;/*!< Set this bit to enable TX_FIFO_REMPTY_INT. */ - __IOM uint32_t RX_FIFO_WOVF_INT_ENA : 1; /*!< Set this bit to enable RX_FIFO_WOVF_INT. */ - __IOM uint32_t TX_EOF_INT_ENA : 1; /*!< Set this bit to enable TX_EOF_INT. */ - uint32_t : 29; - } bit; - } INT_ENA; - - union { - __IOM uint32_t reg; /*!< Parallel IO interrupt raw singal status register. */ - - struct { - __IOM uint32_t TX_FIFO_REMPTY_INT_RAW : 1;/*!< The raw interrupt status of TX_FIFO_REMPTY_INT. */ - __IOM uint32_t RX_FIFO_WOVF_INT_RAW : 1; /*!< The raw interrupt status of RX_FIFO_WOVF_INT. */ - __IOM uint32_t TX_EOF_INT_RAW : 1; /*!< The raw interrupt status of TX_EOF_INT. */ - uint32_t : 29; - } bit; - } INT_RAW; - - union { - __IOM uint32_t reg; /*!< Parallel IO interrupt singal status register. */ - - struct { - __IM uint32_t TX_FIFO_REMPTY_INT_ST : 1; /*!< The masked interrupt status of TX_FIFO_REMPTY_INT. */ - __IM uint32_t RX_FIFO_WOVF_INT_ST : 1; /*!< The masked interrupt status of RX_FIFO_WOVF_INT. */ - __IM uint32_t TX_EOF_INT_ST : 1; /*!< The masked interrupt status of TX_EOF_INT. */ - uint32_t : 29; - } bit; - } INT_ST; - - union { - __IOM uint32_t reg; /*!< Parallel IO interrupt clear singal configuration register. */ - - struct { - __OM uint32_t TX_FIFO_REMPTY_INT_CLR : 1;/*!< Set this bit to clear TX_FIFO_REMPTY_INT. */ - __OM uint32_t RX_FIFO_WOVF_INT_CLR : 1; /*!< Set this bit to clear RX_FIFO_WOVF_INT. */ - __OM uint32_t TX_EOF_INT_CLR : 1; /*!< Set this bit to clear TX_EOF_INT. */ - uint32_t : 29; - } bit; - } INT_CLR; - - union { - __IOM uint32_t reg; /*!< Parallel IO RX status register0 */ - - struct { - uint32_t : 8; - __IM uint32_t RX_CNT : 5; /*!< Indicates the cycle number of reading Rx FIFO. */ - __IM uint32_t RX_FIFO_WR_BIT_CNT : 19; /*!< Indicates the current written bit number into Rx FIFO. */ - } bit; - } RX_ST0; - - union { - __IOM uint32_t reg; /*!< Parallel IO RX status register1 */ - - struct { - uint32_t : 13; - __IM uint32_t RX_FIFO_RD_BIT_CNT : 19; /*!< Indicates the current read bit number from Rx FIFO. */ - } bit; - } RX_ST1; - - union { - __IOM uint32_t reg; /*!< Parallel IO TX status register0 */ - - struct { - uint32_t : 6; - __IM uint32_t TX_CNT : 7; /*!< Indicates the cycle number of reading Tx FIFO. */ - __IM uint32_t TX_FIFO_RD_BIT_CNT : 19; /*!< Indicates the current read bit number from Tx FIFO. */ - } bit; - } TX_ST0; - - union { - __IOM uint32_t reg; /*!< Parallel IO RX clk configuration register */ - - struct { - uint32_t : 30; - __IOM uint32_t RX_CLK_I_INV : 1; /*!< Set this bit to invert the input Rx core clock. */ - __IOM uint32_t RX_CLK_O_INV : 1; /*!< Set this bit to invert the output Rx core clock. */ - } bit; - } RX_CLK_CFG; - - union { - __IOM uint32_t reg; /*!< Parallel IO TX clk configuration register */ - - struct { - uint32_t : 30; - __IOM uint32_t TX_CLK_I_INV : 1; /*!< Set this bit to invert the input Tx core clock. */ - __IOM uint32_t TX_CLK_O_INV : 1; /*!< Set this bit to invert the output Tx core clock. */ - } bit; - } TX_CLK_CFG; - __IM uint32_t RESERVED[53]; - - union { - __IOM uint32_t reg; /*!< Parallel IO clk configuration register */ - - struct { - uint32_t : 31; - __IOM uint32_t EN : 1; /*!< Force clock on for this register file */ - } bit; - } CLK; - __IM uint32_t RESERVED1[182]; - - union { - __IOM uint32_t reg; /*!< Version register. */ - - struct { - __IOM uint32_t DATE : 28; /*!< Version of this register file */ - uint32_t : 4; - } bit; - } VERSION; -} PARL_IO_Type; /*!< Size = 1024 (0x400) */ - - - -/* =========================================================================================================================== */ -/* ================ PAU ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief PAU Peripheral (PAU) - */ - -typedef struct { /*!< PAU Structure */ - - union { - __IOM uint32_t reg; /*!< Peri backup control register */ - - struct { - __IM uint32_t FLOW_ERR : 3; /*!< backup error type */ - __OM uint32_t START : 1; /*!< backup start signal */ - __IOM uint32_t TO_MEM : 1; /*!< backup direction(reg to mem / mem to reg) */ - __IOM uint32_t LINK_SEL : 2; /*!< Link select */ - __OM uint32_t START_MAC : 1; /*!< mac sw backup start signal */ - __IOM uint32_t TO_MEM_MAC : 1; /*!< mac sw backup direction(reg to mem / mem to reg) */ - __IOM uint32_t SEL_MAC : 1; /*!< mac hw/sw select */ - uint32_t : 22; - } bit; - } REGDMA_CONF; - - union { - __IOM uint32_t reg; /*!< Clock control register */ - - struct { - __IOM uint32_t CLK_EN : 1; /*!< clock enable */ - uint32_t : 31; - } bit; - } REGDMA_CLK_CONF; - - union { - __IOM uint32_t reg; /*!< ETM start ctrl reg */ - - struct { - __OM uint32_t ETM_START_0 : 1; /*!< etm_start_0 reg */ - __OM uint32_t ETM_START_1 : 1; /*!< etm_start_1 reg */ - __OM uint32_t ETM_START_2 : 1; /*!< etm_start_2 reg */ - __OM uint32_t ETM_START_3 : 1; /*!< etm_start_3 reg */ - uint32_t : 28; - } bit; - } REGDMA_ETM_CTRL; - - union { - __IOM uint32_t reg; /*!< link_0_addr */ - - struct { - __IOM uint32_t LINK_ADDR_0 : 32; /*!< link_0_addr reg */ - } bit; - } REGDMA_LINK_0_ADDR; - - union { - __IOM uint32_t reg; /*!< Link_1_addr */ - - struct { - __IOM uint32_t LINK_ADDR_1 : 32; /*!< Link_1_addr reg */ - } bit; - } REGDMA_LINK_1_ADDR; - - union { - __IOM uint32_t reg; /*!< Link_2_addr */ - - struct { - __IOM uint32_t LINK_ADDR_2 : 32; /*!< Link_2_addr reg */ - } bit; - } REGDMA_LINK_2_ADDR; - - union { - __IOM uint32_t reg; /*!< Link_3_addr */ - - struct { - __IOM uint32_t LINK_ADDR_3 : 32; /*!< Link_3_addr reg */ - } bit; - } REGDMA_LINK_3_ADDR; - - union { - __IOM uint32_t reg; /*!< Link_mac_addr */ - - struct { - __IOM uint32_t LINK_ADDR_MAC : 32; /*!< Link_mac_addr reg */ - } bit; - } REGDMA_LINK_MAC_ADDR; - - union { - __IOM uint32_t reg; /*!< current link addr */ - - struct { - __IM uint32_t CURRENT_LINK_ADDR : 32; /*!< current link addr reg */ - } bit; - } REGDMA_CURRENT_LINK_ADDR; - - union { - __IOM uint32_t reg; /*!< Backup addr */ - - struct { - __IM uint32_t BACKUP_ADDR : 32; /*!< backup addr reg */ - } bit; - } REGDMA_BACKUP_ADDR; - - union { - __IOM uint32_t reg; /*!< mem addr */ - - struct { - __IM uint32_t MEM_ADDR : 32; /*!< mem addr reg */ - } bit; - } REGDMA_MEM_ADDR; - - union { - __IOM uint32_t reg; /*!< backup config */ - - struct { - __IOM uint32_t READ_INTERVAL : 7; /*!< Link read_interval */ - __IOM uint32_t LINK_TOUT_THRES : 10; /*!< link wait timeout threshold */ - __IOM uint32_t BURST_LIMIT : 5; /*!< burst limit */ - __IOM uint32_t BACKUP_TOUT_THRES : 10; /*!< Backup timeout threshold */ - } bit; - } REGDMA_BKP_CONF; - - union { - __IOM uint32_t reg; /*!< Read only register for error and done */ - - struct { - __IOM uint32_t DONE_INT_ENA : 1; /*!< backup done flag */ - __IOM uint32_t ERROR_INT_ENA : 1; /*!< error flag */ - uint32_t : 30; - } bit; - } INT_ENA; - - union { - __IOM uint32_t reg; /*!< Read only register for error and done */ - - struct { - __IOM uint32_t DONE_INT_RAW : 1; /*!< backup done flag */ - __IOM uint32_t ERROR_INT_RAW : 1; /*!< error flag */ - uint32_t : 30; - } bit; - } INT_RAW; - - union { - __IOM uint32_t reg; /*!< Read only register for error and done */ - - struct { - __OM uint32_t DONE_INT_CLR : 1; /*!< backup done flag */ - __OM uint32_t ERROR_INT_CLR : 1; /*!< error flag */ - uint32_t : 30; - } bit; - } INT_CLR; - - union { - __IOM uint32_t reg; /*!< Read only register for error and done */ - - struct { - __IM uint32_t DONE_INT_ST : 1; /*!< backup done flag */ - __IM uint32_t ERROR_INT_ST : 1; /*!< error flag */ - uint32_t : 30; - } bit; - } INT_ST; - __IM uint32_t RESERVED[239]; - - union { - __IOM uint32_t reg; /*!< Date register. */ - - struct { - __IOM uint32_t DATE : 28; /*!< REGDMA date information/ REGDMA version information. */ - uint32_t : 4; - } bit; - } DATE; -} PAU_Type; /*!< Size = 1024 (0x400) */ - - - -/* =========================================================================================================================== */ -/* ================ PCNT ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Pulse Count Controller (PCNT) - */ - -typedef struct { /*!< PCNT Structure */ - - union { - __IOM uint32_t reg; /*!< Configuration register 0 for unit 0 */ - - struct { - __IOM uint32_t FILTER_THRES_U : 10; /*!< This sets the maximum threshold, in APB_CLK cycles, for the - filter.Any pulses with width less than this will be ignored - when the filter is enabled. */ - uint32_t : 6; - __IOM uint32_t CH0_NEG_MODE_U : 2; /*!< This register sets the behavior when the signal input of channel - 0 detects a negative edge.1: Increase the counter.2: Decrease - the counter.0, 3: No effect on counter */ - __IOM uint32_t CH0_POS_MODE_U : 2; /*!< This register sets the behavior when the signal input of channel - 0 detects a positive edge.1: Increase the counter.2: Decrease - the counter.0, 3: No effect on counter */ - uint32_t : 4; - __IOM uint32_t CH1_NEG_MODE_U : 2; /*!< This register sets the behavior when the signal input of channel - 1 detects a negative edge.1: Increment the counter.2: Decrement - the counter.0, 3: No effect on counter */ - __IOM uint32_t CH1_POS_MODE_U : 2; /*!< This register sets the behavior when the signal input of channel - 1 detects a positive edge.1: Increment the counter.2: Decrement - the counter.0, 3: No effect on counter */ - uint32_t : 4; - } bit; - } U0_CONF0; - __IOM uint32_t U0_CONF1; /*!< Configuration register 1 for unit 0 */ - __IOM uint32_t U0_CONF2; /*!< Configuration register 2 for unit 0 */ - __IM uint32_t RESERVED[9]; - - union { - union { - __IOM uint32_t reg; /*!< Configuration register 0 for unit 1 */ - - struct { - __IOM uint32_t FILTER_THRES_U : 10; /*!< This sets the maximum threshold, in APB_CLK cycles, for the - filter.Any pulses with width less than this will be ignored - when the filter is enabled. */ - uint32_t : 6; - __IOM uint32_t CH0_NEG_MODE_U : 2; /*!< This register sets the behavior when the signal input of channel - 0 detects a negative edge.1: Increase the counter.2: Decrease - the counter.0, 3: No effect on counter */ - __IOM uint32_t CH0_POS_MODE_U : 2; /*!< This register sets the behavior when the signal input of channel - 0 detects a positive edge.1: Increase the counter.2: Decrease - the counter.0, 3: No effect on counter */ - uint32_t : 4; - __IOM uint32_t CH1_NEG_MODE_U : 2; /*!< This register sets the behavior when the signal input of channel - 1 detects a negative edge.1: Increment the counter.2: Decrement - the counter.0, 3: No effect on counter */ - __IOM uint32_t CH1_POS_MODE_U : 2; /*!< This register sets the behavior when the signal input of channel - 1 detects a positive edge.1: Increment the counter.2: Decrement - the counter.0, 3: No effect on counter */ - uint32_t : 4; - } bit; - } U1_CONF0; - __IOM uint32_t U0_CNT; /*!< Counter value for unit 0 */ - }; - __IOM uint32_t U1_CONF1; /*!< Configuration register 1 for unit 1 */ - __IOM uint32_t U1_CONF2; /*!< Configuration register 2 for unit 1 */ - __IM uint32_t RESERVED1; - - union { - __IOM uint32_t U1_CNT; /*!< Counter value for unit 1 */ - - union { - __IOM uint32_t reg; /*!< Interrupt raw status register */ - - struct { - __IOM uint32_t CNT_THR_EVENT_U0_INT_RAW : 1;/*!< The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT - interrupt. */ - __IOM uint32_t CNT_THR_EVENT_U1_INT_RAW : 1;/*!< The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT - interrupt. */ - __IOM uint32_t CNT_THR_EVENT_U2_INT_RAW : 1;/*!< The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT - interrupt. */ - __IOM uint32_t CNT_THR_EVENT_U3_INT_RAW : 1;/*!< The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT - interrupt. */ - uint32_t : 28; - } bit; - } INT_RAW; - }; - - union { - __IOM uint32_t reg; /*!< Interrupt status register */ - - struct { - __IM uint32_t CNT_THR_EVENT_U0_INT_ST : 1;/*!< The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT - interrupt. */ - __IM uint32_t CNT_THR_EVENT_U1_INT_ST : 1;/*!< The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT - interrupt. */ - __IM uint32_t CNT_THR_EVENT_U2_INT_ST : 1;/*!< The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT - interrupt. */ - __IM uint32_t CNT_THR_EVENT_U3_INT_ST : 1;/*!< The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT - interrupt. */ - uint32_t : 28; - } bit; - } INT_ST; - - union { - __IOM uint32_t reg; /*!< Interrupt enable register */ - - struct { - __IOM uint32_t CNT_THR_EVENT_U0_INT_ENA : 1;/*!< The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. */ - __IOM uint32_t CNT_THR_EVENT_U1_INT_ENA : 1;/*!< The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. */ - __IOM uint32_t CNT_THR_EVENT_U2_INT_ENA : 1;/*!< The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. */ - __IOM uint32_t CNT_THR_EVENT_U3_INT_ENA : 1;/*!< The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. */ - uint32_t : 28; - } bit; - } INT_ENA; - - union { - __IOM uint32_t reg; /*!< Interrupt clear register */ - - struct { - __OM uint32_t CNT_THR_EVENT_U0_INT_CLR : 1;/*!< Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt. */ - __OM uint32_t CNT_THR_EVENT_U1_INT_CLR : 1;/*!< Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt. */ - __OM uint32_t CNT_THR_EVENT_U2_INT_CLR : 1;/*!< Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt. */ - __OM uint32_t CNT_THR_EVENT_U3_INT_CLR : 1;/*!< Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt. */ - uint32_t : 28; - } bit; - } INT_CLR; - - union { - __IOM uint32_t U2_CNT; /*!< Counter value for unit 2 */ - __IOM uint32_t U0_STATUS; /*!< PNCT UNIT0 status register */ - }; - __IM uint32_t RESERVED2[3]; - - union { - union { - __IOM uint32_t reg; /*!< Configuration register 0 for unit 2 */ - - struct { - __IOM uint32_t FILTER_THRES_U : 10; /*!< This sets the maximum threshold, in APB_CLK cycles, for the - filter.Any pulses with width less than this will be ignored - when the filter is enabled. */ - uint32_t : 6; - __IOM uint32_t CH0_NEG_MODE_U : 2; /*!< This register sets the behavior when the signal input of channel - 0 detects a negative edge.1: Increase the counter.2: Decrease - the counter.0, 3: No effect on counter */ - __IOM uint32_t CH0_POS_MODE_U : 2; /*!< This register sets the behavior when the signal input of channel - 0 detects a positive edge.1: Increase the counter.2: Decrease - the counter.0, 3: No effect on counter */ - uint32_t : 4; - __IOM uint32_t CH1_NEG_MODE_U : 2; /*!< This register sets the behavior when the signal input of channel - 1 detects a negative edge.1: Increment the counter.2: Decrement - the counter.0, 3: No effect on counter */ - __IOM uint32_t CH1_POS_MODE_U : 2; /*!< This register sets the behavior when the signal input of channel - 1 detects a positive edge.1: Increment the counter.2: Decrement - the counter.0, 3: No effect on counter */ - uint32_t : 4; - } bit; - } U2_CONF0; - __IOM uint32_t U3_CNT; /*!< Counter value for unit 3 */ - __IOM uint32_t U1_STATUS; /*!< PNCT UNIT1 status register */ - - union { - __IOM uint32_t reg; /*!< Control register for all counters */ - - struct { - __IOM uint32_t PULSE_CNT_RST_U0 : 1; /*!< Set this bit to clear unit 0's counter. */ - __IOM uint32_t CNT_PAUSE_U0 : 1; /*!< Set this bit to freeze unit 0's counter. */ - __IOM uint32_t PULSE_CNT_RST_U1 : 1; /*!< Set this bit to clear unit 1's counter. */ - __IOM uint32_t CNT_PAUSE_U1 : 1; /*!< Set this bit to freeze unit 1's counter. */ - __IOM uint32_t PULSE_CNT_RST_U2 : 1; /*!< Set this bit to clear unit 2's counter. */ - __IOM uint32_t CNT_PAUSE_U2 : 1; /*!< Set this bit to freeze unit 2's counter. */ - __IOM uint32_t PULSE_CNT_RST_U3 : 1; /*!< Set this bit to clear unit 3's counter. */ - __IOM uint32_t CNT_PAUSE_U3 : 1; /*!< Set this bit to freeze unit 3's counter. */ - __IOM uint32_t DALTA_CHANGE_EN_U0 : 1; /*!< Configures this bit to enable unit 0's step comparator. */ - __IOM uint32_t DALTA_CHANGE_EN_U1 : 1; /*!< Configures this bit to enable unit 1's step comparator. */ - __IOM uint32_t DALTA_CHANGE_EN_U2 : 1; /*!< Configures this bit to enable unit 2's step comparator. */ - __IOM uint32_t DALTA_CHANGE_EN_U3 : 1; /*!< Configures this bit to enable unit 3's step comparator. */ - uint32_t : 4; - __IOM uint32_t CLK_EN : 1; /*!< The registers clock gate enable signal of PCNT module. 1: the - registers can be read and written by application. 0: the - registers can not be read or written by application */ - uint32_t : 15; - } bit; - } CTRL; - }; - - union { - __IOM uint32_t U2_CONF1; /*!< Configuration register 1 for unit 2 */ - - union { - __IOM uint32_t reg; /*!< Configuration register for unit $n's step value. */ - - struct { - __IOM uint32_t CNT_STEP_U3 : 16; /*!< Configures the step value for unit 3. */ - __IOM uint32_t CNT_STEP_LIM_U3 : 16; /*!< Configures the step limit value for unit 3. */ - } bit; - } U3_CHANGE_CONF; - }; - - union { - __IOM uint32_t U2_CONF2; /*!< Configuration register 2 for unit 2 */ - - union { - __IOM uint32_t reg; /*!< Configuration register for unit $n's step value. */ - - struct { - __IOM uint32_t CNT_STEP_U2 : 16; /*!< Configures the step value for unit 2. */ - __IOM uint32_t CNT_STEP_LIM_U2 : 16; /*!< Configures the step limit value for unit 2. */ - } bit; - } U2_CHANGE_CONF; - }; - - union { - __IOM uint32_t reg; /*!< Configuration register for unit $n's step value. */ - - struct { - __IOM uint32_t CNT_STEP_U1 : 16; /*!< Configures the step value for unit 1. */ - __IOM uint32_t CNT_STEP_LIM_U1 : 16; /*!< Configures the step limit value for unit 1. */ - } bit; - } U1_CHANGE_CONF; - - union { - __IOM uint32_t U2_STATUS; /*!< PNCT UNIT2 status register */ - - union { - __IOM uint32_t reg; /*!< Configuration register for unit $n's step value. */ - - struct { - __IOM uint32_t CNT_STEP_U0 : 16; /*!< Configures the step value for unit 0. */ - __IOM uint32_t CNT_STEP_LIM_U0 : 16; /*!< Configures the step limit value for unit 0. */ - } bit; - } U0_CHANGE_CONF; - }; - __IM uint32_t RESERVED3[3]; - __IOM uint32_t U3_STATUS; /*!< PNCT UNIT3 status register */ - __IM uint32_t RESERVED4[3]; - - union { - __IOM uint32_t reg; /*!< Configuration register 0 for unit 3 */ - - struct { - __IOM uint32_t FILTER_THRES_U : 10; /*!< This sets the maximum threshold, in APB_CLK cycles, for the - filter.Any pulses with width less than this will be ignored - when the filter is enabled. */ - uint32_t : 6; - __IOM uint32_t CH0_NEG_MODE_U : 2; /*!< This register sets the behavior when the signal input of channel - 0 detects a negative edge.1: Increase the counter.2: Decrease - the counter.0, 3: No effect on counter */ - __IOM uint32_t CH0_POS_MODE_U : 2; /*!< This register sets the behavior when the signal input of channel - 0 detects a positive edge.1: Increase the counter.2: Decrease - the counter.0, 3: No effect on counter */ - uint32_t : 4; - __IOM uint32_t CH1_NEG_MODE_U : 2; /*!< This register sets the behavior when the signal input of channel - 1 detects a negative edge.1: Increment the counter.2: Decrement - the counter.0, 3: No effect on counter */ - __IOM uint32_t CH1_POS_MODE_U : 2; /*!< This register sets the behavior when the signal input of channel - 1 detects a positive edge.1: Increment the counter.2: Decrement - the counter.0, 3: No effect on counter */ - uint32_t : 4; - } bit; - } U3_CONF0; - __IOM uint32_t U3_CONF1; /*!< Configuration register 1 for unit 3 */ - __IOM uint32_t U3_CONF2; /*!< Configuration register 2 for unit 3 */ - __IM uint32_t RESERVED5[24]; - - union { - __IOM uint32_t reg; /*!< PCNT version control register */ - - struct { - __IOM uint32_t DATE : 32; /*!< This is the PCNT version control register. */ - } bit; - } DATE; -} PCNT_Type; /*!< Size = 256 (0x100) */ - - - -/* =========================================================================================================================== */ -/* ================ PMU ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief PMU Peripheral (PMU) - */ - -typedef struct { /*!< PMU Structure */ - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 21; - __IOM uint32_t HP_ACTIVE_DCDC_SWITCH_PD_EN : 1;/*!< need_des */ - __IOM uint32_t HP_ACTIVE_HP_MEM_DSLP : 1; /*!< need_des */ - __IOM uint32_t HP_ACTIVE_PD_HP_MEM_PD_EN : 1;/*!< need_des */ - uint32_t : 6; - __IOM uint32_t HP_ACTIVE_PD_CNNT_PD_EN : 1;/*!< need_des */ - __IOM uint32_t HP_ACTIVE_PD_TOP_PD_EN : 1;/*!< need_des */ - } bit; - } HP_ACTIVE_DIG_POWER; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t HP_ACTIVE_DIG_ICG_FUNC_EN : 32;/*!< need_des */ - } bit; - } HP_ACTIVE_ICG_HP_FUNC; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t HP_ACTIVE_DIG_ICG_APB_EN : 32;/*!< need_des */ - } bit; - } HP_ACTIVE_ICG_HP_APB; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 30; - __IOM uint32_t HP_ACTIVE_DIG_ICG_MODEM_CODE : 2;/*!< need_des */ - } bit; - } HP_ACTIVE_ICG_MODEM; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 23; - __IOM uint32_t HP_ACTIVE_HP_POWER_DET_BYPASS : 1;/*!< need_des */ - __IOM uint32_t HP_ACTIVE_UART_WAKEUP_EN : 1;/*!< need_des */ - __IOM uint32_t HP_ACTIVE_LP_PAD_HOLD_ALL : 1;/*!< need_des */ - __IOM uint32_t HP_ACTIVE_HP_PAD_HOLD_ALL : 1;/*!< need_des */ - __IOM uint32_t HP_ACTIVE_DIG_PAD_SLP_SEL : 1;/*!< need_des */ - __IOM uint32_t HP_ACTIVE_DIG_PAUSE_WDT : 1;/*!< need_des */ - __IOM uint32_t HP_ACTIVE_DIG_CPU_STALL : 1;/*!< need_des */ - uint32_t : 2; - } bit; - } HP_ACTIVE_HP_SYS_CNTL; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 21; - __IOM uint32_t HP_ACTIVE_I2C_ISO_EN : 1; /*!< need_des */ - __IOM uint32_t HP_ACTIVE_I2C_RETENTION : 1;/*!< need_des */ - __IOM uint32_t HP_ACTIVE_XPD_PLL_I2C : 4; /*!< need_des */ - __IOM uint32_t HP_ACTIVE_XPD_PLL : 4; /*!< need_des */ - uint32_t : 1; - } bit; - } HP_ACTIVE_HP_CK_POWER; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 18; - __IOM uint32_t HP_ACTIVE_DCM_VSET : 5; /*!< need_des */ - __IOM uint32_t HP_ACTIVE_DCM_MODE : 2; /*!< need_des */ - __IOM uint32_t HP_ACTIVE_XPD_BIAS : 1; /*!< need_des */ - __IOM uint32_t HP_ACTIVE_DBG_ATTEN : 4; /*!< need_des */ - __IOM uint32_t HP_ACTIVE_PD_CUR : 1; /*!< need_des */ - __IOM uint32_t SLEEP : 1; /*!< need_des */ - } bit; - } HP_ACTIVE_BIAS; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 4; - __IOM uint32_t HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE : 2;/*!< need_des */ - __IOM uint32_t HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE : 2;/*!< need_des */ - uint32_t : 2; - __IOM uint32_t HP_ACTIVE_RETENTION_MODE : 1;/*!< need_des */ - __IOM uint32_t HP_SLEEP2ACTIVE_RETENTION_EN : 1;/*!< need_des */ - __IOM uint32_t HP_MODEM2ACTIVE_RETENTION_EN : 1;/*!< need_des */ - uint32_t : 1; - __IOM uint32_t HP_SLEEP2ACTIVE_BACKUP_CLK_SEL : 2;/*!< need_des */ - __IOM uint32_t HP_MODEM2ACTIVE_BACKUP_CLK_SEL : 2;/*!< need_des */ - uint32_t : 2; - __IOM uint32_t HP_SLEEP2ACTIVE_BACKUP_MODE : 3;/*!< need_des */ - __IOM uint32_t HP_MODEM2ACTIVE_BACKUP_MODE : 3;/*!< need_des */ - uint32_t : 3; - __IOM uint32_t HP_SLEEP2ACTIVE_BACKUP_EN : 1;/*!< need_des */ - __IOM uint32_t HP_MODEM2ACTIVE_BACKUP_EN : 1;/*!< need_des */ - uint32_t : 1; - } bit; - } HP_ACTIVE_BACKUP; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t HP_ACTIVE_BACKUP_ICG_FUNC_EN : 32;/*!< need_des */ - } bit; - } HP_ACTIVE_BACKUP_CLK; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 26; - __IOM uint32_t HP_ACTIVE_DIG_SYS_CLK_NO_DIV : 1;/*!< need_des */ - __IOM uint32_t HP_ACTIVE_ICG_SYS_CLOCK_EN : 1;/*!< need_des */ - __IOM uint32_t HP_ACTIVE_SYS_CLK_SLP_SEL : 1;/*!< need_des */ - __IOM uint32_t HP_ACTIVE_ICG_SLP_SEL : 1; /*!< need_des */ - __IOM uint32_t HP_ACTIVE_DIG_SYS_CLK_SEL : 2;/*!< need_des */ - } bit; - } HP_ACTIVE_SYSCLK; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 4; - __IM uint32_t LP_DBIAS_VOL : 5; /*!< need_des */ - __IM uint32_t HP_DBIAS_VOL : 5; /*!< need_des */ - __IOM uint32_t DIG_REGULATOR0_DBIAS_SEL : 1;/*!< need_des */ - __OM uint32_t DIG_DBIAS_INIT : 1; /*!< need_des */ - __IOM uint32_t HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD : 1;/*!< need_des */ - __IOM uint32_t HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD : 1;/*!< need_des */ - __IOM uint32_t HP_ACTIVE_HP_REGULATOR_XPD : 1;/*!< need_des */ - __IOM uint32_t HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS : 4;/*!< need_des */ - __IOM uint32_t HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS : 4;/*!< need_des */ - __IOM uint32_t HP_ACTIVE_HP_REGULATOR_DBIAS : 5;/*!< need_des */ - } bit; - } HP_ACTIVE_HP_REGULATOR0; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 26; - __IOM uint32_t HP_ACTIVE_HP_REGULATOR_DRV_B : 6;/*!< need_des */ - } bit; - } HP_ACTIVE_HP_REGULATOR1; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 31; - __IOM uint32_t HP_ACTIVE_XPD_XTAL : 1; /*!< need_des */ - } bit; - } HP_ACTIVE_XTAL; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 21; - __IOM uint32_t HP_MODEM_DCDC_SWITCH_PD_EN : 1;/*!< need_des */ - __OM uint32_t HP_MODEM_HP_MEM_DSLP : 1; /*!< need_des */ - __OM uint32_t HP_MODEM_PD_HP_MEM_PD_EN : 4;/*!< need_des */ - __OM uint32_t HP_MODEM_PD_HP_WIFI_PD_EN : 1;/*!< need_des */ - uint32_t : 1; - __OM uint32_t HP_MODEM_PD_HP_CPU_PD_EN : 1;/*!< need_des */ - __OM uint32_t HP_MODEM_PD_CNNT_PD_EN : 1;/*!< need_des */ - __OM uint32_t HP_MODEM_PD_TOP_PD_EN : 1; /*!< need_des */ - } bit; - } HP_MODEM_DIG_POWER; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __OM uint32_t HP_MODEM_DIG_ICG_FUNC_EN : 32;/*!< need_des */ - } bit; - } HP_MODEM_ICG_HP_FUNC; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __OM uint32_t HP_MODEM_DIG_ICG_APB_EN : 32;/*!< need_des */ - } bit; - } HP_MODEM_ICG_HP_APB; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 30; - __OM uint32_t HP_MODEM_DIG_ICG_MODEM_CODE : 2;/*!< need_des */ - } bit; - } HP_MODEM_ICG_MODEM; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 23; - __OM uint32_t HP_MODEM_HP_POWER_DET_BYPASS : 1;/*!< need_des */ - __OM uint32_t HP_MODEM_UART_WAKEUP_EN : 1;/*!< need_des */ - __OM uint32_t HP_MODEM_LP_PAD_HOLD_ALL : 1;/*!< need_des */ - __OM uint32_t HP_MODEM_HP_PAD_HOLD_ALL : 1;/*!< need_des */ - __OM uint32_t HP_MODEM_DIG_PAD_SLP_SEL : 1;/*!< need_des */ - __OM uint32_t HP_MODEM_DIG_PAUSE_WDT : 1;/*!< need_des */ - __OM uint32_t HP_MODEM_DIG_CPU_STALL : 1;/*!< need_des */ - uint32_t : 2; - } bit; - } HP_MODEM_HP_SYS_CNTL; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 21; - __OM uint32_t HP_MODEM_I2C_ISO_EN : 1; /*!< need_des */ - __OM uint32_t HP_MODEM_I2C_RETENTION : 1;/*!< need_des */ - __OM uint32_t HP_MODEM_XPD_PLL_I2C : 4; /*!< need_des */ - __OM uint32_t HP_MODEM_XPD_PLL : 4; /*!< need_des */ - uint32_t : 1; - } bit; - } HP_MODEM_HP_CK_POWER; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 18; - __OM uint32_t HP_MODEM_DCM_VSET : 5; /*!< need_des */ - __OM uint32_t HP_MODEM_DCM_MODE : 2; /*!< need_des */ - __OM uint32_t HP_MODEM_XPD_BIAS : 1; /*!< need_des */ - __OM uint32_t HP_MODEM_DBG_ATTEN : 4; /*!< need_des */ - __OM uint32_t HP_MODEM_PD_CUR : 1; /*!< need_des */ - __OM uint32_t SLEEP : 1; /*!< need_des */ - } bit; - } HP_MODEM_BIAS; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 4; - __OM uint32_t HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE : 2;/*!< need_des */ - uint32_t : 4; - __OM uint32_t HP_MODEM_RETENTION_MODE : 1;/*!< need_des */ - __OM uint32_t HP_SLEEP2MODEM_RETENTION_EN : 1;/*!< need_des */ - uint32_t : 2; - __OM uint32_t HP_SLEEP2MODEM_BACKUP_CLK_SEL : 2;/*!< need_des */ - uint32_t : 4; - __OM uint32_t HP_SLEEP2MODEM_BACKUP_MODE : 3;/*!< need_des */ - uint32_t : 6; - __OM uint32_t HP_SLEEP2MODEM_BACKUP_EN : 1;/*!< need_des */ - uint32_t : 2; - } bit; - } HP_MODEM_BACKUP; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __OM uint32_t HP_MODEM_BACKUP_ICG_FUNC_EN : 32;/*!< need_des */ - } bit; - } HP_MODEM_BACKUP_CLK; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 26; - __OM uint32_t HP_MODEM_DIG_SYS_CLK_NO_DIV : 1;/*!< need_des */ - __OM uint32_t HP_MODEM_ICG_SYS_CLOCK_EN : 1;/*!< need_des */ - __OM uint32_t HP_MODEM_SYS_CLK_SLP_SEL : 1;/*!< need_des */ - __OM uint32_t HP_MODEM_ICG_SLP_SEL : 1; /*!< need_des */ - __OM uint32_t HP_MODEM_DIG_SYS_CLK_SEL : 2;/*!< need_des */ - } bit; - } HP_MODEM_SYSCLK; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 16; - __OM uint32_t HP_MODEM_HP_REGULATOR_SLP_MEM_XPD : 1;/*!< need_des */ - __OM uint32_t HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD : 1;/*!< need_des */ - __OM uint32_t HP_MODEM_HP_REGULATOR_XPD : 1;/*!< need_des */ - __OM uint32_t HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS : 4;/*!< need_des */ - __OM uint32_t HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS : 4;/*!< need_des */ - __OM uint32_t HP_MODEM_HP_REGULATOR_DBIAS : 5;/*!< need_des */ - } bit; - } HP_MODEM_HP_REGULATOR0; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 8; - __OM uint32_t HP_MODEM_HP_REGULATOR_DRV_B : 24;/*!< need_des */ - } bit; - } HP_MODEM_HP_REGULATOR1; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 31; - __OM uint32_t HP_MODEM_XPD_XTAL : 1; /*!< need_des */ - } bit; - } HP_MODEM_XTAL; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 21; - __IOM uint32_t HP_SLEEP_DCDC_SWITCH_PD_EN : 1;/*!< need_des */ - __IOM uint32_t HP_SLEEP_HP_MEM_DSLP : 1; /*!< need_des */ - __IOM uint32_t HP_SLEEP_PD_HP_MEM_PD_EN : 1;/*!< need_des */ - uint32_t : 6; - __IOM uint32_t HP_SLEEP_PD_CNNT_PD_EN : 1;/*!< need_des */ - __IOM uint32_t HP_SLEEP_PD_TOP_PD_EN : 1; /*!< need_des */ - } bit; - } HP_SLEEP_DIG_POWER; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t HP_SLEEP_DIG_ICG_FUNC_EN : 32;/*!< need_des */ - } bit; - } HP_SLEEP_ICG_HP_FUNC; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t HP_SLEEP_DIG_ICG_APB_EN : 32;/*!< need_des */ - } bit; - } HP_SLEEP_ICG_HP_APB; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 30; - __IOM uint32_t HP_SLEEP_DIG_ICG_MODEM_CODE : 2;/*!< need_des */ - } bit; - } HP_SLEEP_ICG_MODEM; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 23; - __IOM uint32_t HP_SLEEP_HP_POWER_DET_BYPASS : 1;/*!< need_des */ - __IOM uint32_t HP_SLEEP_UART_WAKEUP_EN : 1;/*!< need_des */ - __IOM uint32_t HP_SLEEP_LP_PAD_HOLD_ALL : 1;/*!< need_des */ - __IOM uint32_t HP_SLEEP_HP_PAD_HOLD_ALL : 1;/*!< need_des */ - __IOM uint32_t HP_SLEEP_DIG_PAD_SLP_SEL : 1;/*!< need_des */ - __IOM uint32_t HP_SLEEP_DIG_PAUSE_WDT : 1;/*!< need_des */ - __IOM uint32_t HP_SLEEP_DIG_CPU_STALL : 1;/*!< need_des */ - uint32_t : 2; - } bit; - } HP_SLEEP_HP_SYS_CNTL; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 21; - __IOM uint32_t HP_SLEEP_I2C_ISO_EN : 1; /*!< need_des */ - __IOM uint32_t HP_SLEEP_I2C_RETENTION : 1;/*!< need_des */ - __IOM uint32_t HP_SLEEP_XPD_PLL_I2C : 4; /*!< need_des */ - __IOM uint32_t HP_SLEEP_XPD_PLL : 4; /*!< need_des */ - uint32_t : 1; - } bit; - } HP_SLEEP_HP_CK_POWER; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 18; - __IOM uint32_t HP_SLEEP_DCM_VSET : 5; /*!< need_des */ - __IOM uint32_t HP_SLEEP_DCM_MODE : 2; /*!< need_des */ - __IOM uint32_t HP_SLEEP_XPD_BIAS : 1; /*!< need_des */ - __IOM uint32_t HP_SLEEP_DBG_ATTEN : 4; /*!< need_des */ - __IOM uint32_t HP_SLEEP_PD_CUR : 1; /*!< need_des */ - __IOM uint32_t SLEEP : 1; /*!< need_des */ - } bit; - } HP_SLEEP_BIAS; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 6; - __IOM uint32_t HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE : 2;/*!< need_des */ - __IOM uint32_t HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE : 2;/*!< need_des */ - __IOM uint32_t HP_SLEEP_RETENTION_MODE : 1;/*!< need_des */ - uint32_t : 1; - __IOM uint32_t HP_MODEM2SLEEP_RETENTION_EN : 1;/*!< need_des */ - __IOM uint32_t HP_ACTIVE2SLEEP_RETENTION_EN : 1;/*!< need_des */ - uint32_t : 2; - __IOM uint32_t HP_MODEM2SLEEP_BACKUP_CLK_SEL : 2;/*!< need_des */ - __IOM uint32_t HP_ACTIVE2SLEEP_BACKUP_CLK_SEL : 2;/*!< need_des */ - uint32_t : 3; - __IOM uint32_t HP_MODEM2SLEEP_BACKUP_MODE : 3;/*!< need_des */ - __IOM uint32_t HP_ACTIVE2SLEEP_BACKUP_MODE : 3;/*!< need_des */ - uint32_t : 1; - __IOM uint32_t HP_MODEM2SLEEP_BACKUP_EN : 1;/*!< need_des */ - __IOM uint32_t HP_ACTIVE2SLEEP_BACKUP_EN : 1;/*!< need_des */ - } bit; - } HP_SLEEP_BACKUP; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t HP_SLEEP_BACKUP_ICG_FUNC_EN : 32;/*!< need_des */ - } bit; - } HP_SLEEP_BACKUP_CLK; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 26; - __IOM uint32_t HP_SLEEP_DIG_SYS_CLK_NO_DIV : 1;/*!< need_des */ - __IOM uint32_t HP_SLEEP_ICG_SYS_CLOCK_EN : 1;/*!< need_des */ - __IOM uint32_t HP_SLEEP_SYS_CLK_SLP_SEL : 1;/*!< need_des */ - __IOM uint32_t HP_SLEEP_ICG_SLP_SEL : 1; /*!< need_des */ - __IOM uint32_t HP_SLEEP_DIG_SYS_CLK_SEL : 2;/*!< need_des */ - } bit; - } HP_SLEEP_SYSCLK; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 16; - __IOM uint32_t HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD : 1;/*!< need_des */ - __IOM uint32_t HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD : 1;/*!< need_des */ - __IOM uint32_t HP_SLEEP_HP_REGULATOR_XPD : 1;/*!< need_des */ - __IOM uint32_t HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS : 4;/*!< need_des */ - __IOM uint32_t HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS : 4;/*!< need_des */ - __IOM uint32_t HP_SLEEP_HP_REGULATOR_DBIAS : 5;/*!< need_des */ - } bit; - } HP_SLEEP_HP_REGULATOR0; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 26; - __IOM uint32_t HP_SLEEP_HP_REGULATOR_DRV_B : 6;/*!< need_des */ - } bit; - } HP_SLEEP_HP_REGULATOR1; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 31; - __IOM uint32_t HP_SLEEP_XPD_XTAL : 1; /*!< need_des */ - } bit; - } HP_SLEEP_XTAL; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 21; - __IOM uint32_t HP_SLEEP_LP_REGULATOR_SLP_XPD : 1;/*!< need_des */ - __IOM uint32_t HP_SLEEP_LP_REGULATOR_XPD : 1;/*!< need_des */ - __IOM uint32_t HP_SLEEP_LP_REGULATOR_SLP_DBIAS : 4;/*!< need_des */ - __IOM uint32_t HP_SLEEP_LP_REGULATOR_DBIAS : 5;/*!< need_des */ - } bit; - } HP_SLEEP_LP_REGULATOR0; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 26; - __IOM uint32_t HP_SLEEP_LP_REGULATOR_DRV_B : 6;/*!< need_des */ - } bit; - } HP_SLEEP_LP_REGULATOR1; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __OM uint32_t PMU_HP_SLEEP_LP_DCDC_RESERVE : 32;/*!< need_des */ - } bit; - } HP_SLEEP_LP_DCDC_RESERVE; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 26; - __IOM uint32_t HP_SLEEP_LP_PAD_SLP_SEL : 1;/*!< need_des */ - __IOM uint32_t HP_SLEEP_BOD_SOURCE_SEL : 1;/*!< need_des */ - __IOM uint32_t HP_SLEEP_VDDBAT_MODE : 2; /*!< need_des */ - __IOM uint32_t HP_SLEEP_LP_MEM_DSLP : 1; /*!< need_des */ - __IOM uint32_t HP_SLEEP_PD_LP_PERI_PD_EN : 1;/*!< need_des */ - } bit; - } HP_SLEEP_LP_DIG_POWER; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 27; - __IOM uint32_t HP_SLEEP_XPD_LPPLL : 1; /*!< need_des */ - __IOM uint32_t HP_SLEEP_XPD_XTAL32K : 1; /*!< need_des */ - __IOM uint32_t HP_SLEEP_XPD_RC32K : 1; /*!< need_des */ - __IOM uint32_t HP_SLEEP_XPD_FOSC_CLK : 1; /*!< need_des */ - __IOM uint32_t HP_SLEEP_PD_OSC_CLK : 1; /*!< need_des */ - } bit; - } HP_SLEEP_LP_CK_POWER; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __OM uint32_t PMU_LP_SLEEP_LP_BIAS_RESERVE : 32;/*!< need_des */ - } bit; - } LP_SLEEP_LP_BIAS_RESERVE; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 21; - __IOM uint32_t LP_SLEEP_LP_REGULATOR_SLP_XPD : 1;/*!< need_des */ - __IOM uint32_t LP_SLEEP_LP_REGULATOR_XPD : 1;/*!< need_des */ - __IOM uint32_t LP_SLEEP_LP_REGULATOR_SLP_DBIAS : 4;/*!< need_des */ - __IOM uint32_t LP_SLEEP_LP_REGULATOR_DBIAS : 5;/*!< need_des */ - } bit; - } LP_SLEEP_LP_REGULATOR0; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 26; - __IOM uint32_t LP_SLEEP_LP_REGULATOR_DRV_B : 6;/*!< need_des */ - } bit; - } LP_SLEEP_LP_REGULATOR1; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 31; - __IOM uint32_t LP_SLEEP_XPD_XTAL : 1; /*!< need_des */ - } bit; - } LP_SLEEP_XTAL; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 26; - __IOM uint32_t LP_SLEEP_LP_PAD_SLP_SEL : 1;/*!< need_des */ - __IOM uint32_t LP_SLEEP_BOD_SOURCE_SEL : 1;/*!< need_des */ - __IOM uint32_t LP_SLEEP_VDDBAT_MODE : 2; /*!< need_des */ - __IOM uint32_t LP_SLEEP_LP_MEM_DSLP : 1; /*!< need_des */ - __IOM uint32_t LP_SLEEP_PD_LP_PERI_PD_EN : 1;/*!< need_des */ - } bit; - } LP_SLEEP_LP_DIG_POWER; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 27; - __IOM uint32_t LP_SLEEP_XPD_LPPLL : 1; /*!< need_des */ - __IOM uint32_t LP_SLEEP_XPD_XTAL32K : 1; /*!< need_des */ - __IOM uint32_t LP_SLEEP_XPD_RC32K : 1; /*!< need_des */ - __IOM uint32_t LP_SLEEP_XPD_FOSC_CLK : 1; /*!< need_des */ - __IOM uint32_t LP_SLEEP_PD_OSC_CLK : 1; /*!< need_des */ - } bit; - } LP_SLEEP_LP_CK_POWER; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 25; - __IOM uint32_t LP_SLEEP_XPD_BIAS : 1; /*!< need_des */ - __IOM uint32_t LP_SLEEP_DBG_ATTEN : 4; /*!< need_des */ - __IOM uint32_t LP_SLEEP_PD_CUR : 1; /*!< need_des */ - __IOM uint32_t SLEEP : 1; /*!< need_des */ - } bit; - } LP_SLEEP_BIAS; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t TIE_LOW_CALI_XTAL_ICG : 1; /*!< need_des */ - __OM uint32_t TIE_LOW_GLOBAL_PLL_ICG : 4;/*!< need_des */ - __OM uint32_t TIE_LOW_GLOBAL_XTAL_ICG : 1;/*!< need_des */ - __OM uint32_t TIE_LOW_I2C_RETENTION : 1; /*!< need_des */ - __OM uint32_t TIE_LOW_XPD_PLL_I2C : 4; /*!< need_des */ - __OM uint32_t TIE_LOW_XPD_PLL : 4; /*!< need_des */ - __OM uint32_t TIE_LOW_XPD_XTAL : 1; /*!< need_des */ - __IOM uint32_t TIE_HIGH_CALI_XTAL_ICG : 1;/*!< need_des */ - __OM uint32_t TIE_HIGH_GLOBAL_PLL_ICG : 4;/*!< need_des */ - __OM uint32_t TIE_HIGH_GLOBAL_XTAL_ICG : 1;/*!< need_des */ - __OM uint32_t TIE_HIGH_I2C_RETENTION : 1;/*!< need_des */ - __OM uint32_t TIE_HIGH_XPD_PLL_I2C : 4; /*!< need_des */ - __OM uint32_t TIE_HIGH_XPD_PLL : 4; /*!< need_des */ - __OM uint32_t TIE_HIGH_XPD_XTAL : 1; /*!< need_des */ - } bit; - } IMM_HP_CK_POWER; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 28; - __OM uint32_t UPDATE_DIG_ICG_SWITCH : 1; /*!< need_des */ - __OM uint32_t TIE_LOW_ICG_SLP_SEL : 1; /*!< need_des */ - __OM uint32_t TIE_HIGH_ICG_SLP_SEL : 1; /*!< need_des */ - __OM uint32_t UPDATE_DIG_SYS_CLK_SEL : 1;/*!< need_des */ - } bit; - } IMM_SLEEP_SYSCLK; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 31; - __OM uint32_t UPDATE_DIG_ICG_FUNC_EN : 1;/*!< need_des */ - } bit; - } IMM_HP_FUNC_ICG; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 31; - __OM uint32_t UPDATE_DIG_ICG_APB_EN : 1; /*!< need_des */ - } bit; - } IMM_HP_APB_ICG; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 31; - __OM uint32_t UPDATE_DIG_ICG_MODEM_EN : 1;/*!< need_des */ - } bit; - } IMM_MODEM_ICG; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 30; - __OM uint32_t TIE_LOW_LP_ROOTCLK_SEL : 1;/*!< need_des */ - __OM uint32_t TIE_HIGH_LP_ROOTCLK_SEL : 1;/*!< need_des */ - } bit; - } IMM_LP_ICG; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IM uint32_t PAD_SLP_SEL : 1; /*!< need_des */ - __IM uint32_t LP_PAD_HOLD_ALL : 1; /*!< need_des */ - __IM uint32_t HP_PAD_HOLD_ALL : 1; /*!< need_des */ - uint32_t : 23; - __OM uint32_t TIE_HIGH_PAD_SLP_SEL : 1; /*!< need_des */ - __OM uint32_t TIE_LOW_PAD_SLP_SEL : 1; /*!< need_des */ - __OM uint32_t TIE_HIGH_LP_PAD_HOLD_ALL : 1;/*!< need_des */ - __OM uint32_t TIE_LOW_LP_PAD_HOLD_ALL : 1;/*!< need_des */ - __OM uint32_t TIE_HIGH_HP_PAD_HOLD_ALL : 1;/*!< need_des */ - __OM uint32_t TIE_LOW_HP_PAD_HOLD_ALL : 1;/*!< need_des */ - } bit; - } IMM_PAD_HOLD_ALL; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 30; - __OM uint32_t TIE_HIGH_I2C_ISO_EN : 1; /*!< need_des */ - __OM uint32_t TIE_LOW_I2C_ISO_EN : 1; /*!< need_des */ - } bit; - } IMM_I2C_ISO; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 5; - __IOM uint32_t DG_HP_POWERDOWN_TIMER : 9; /*!< need_des */ - __IOM uint32_t DG_HP_POWERUP_TIMER : 9; /*!< need_des */ - __IOM uint32_t DG_HP_WAIT_TIMER : 9; /*!< need_des */ - } bit; - } POWER_WAIT_TIMER0; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 5; - __IOM uint32_t DG_LP_POWERDOWN_TIMER : 9; /*!< need_des */ - __IOM uint32_t DG_LP_POWERUP_TIMER : 9; /*!< need_des */ - __IOM uint32_t DG_LP_WAIT_TIMER : 9; /*!< need_des */ - } bit; - } POWER_WAIT_TIMER1; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t FORCE_TOP_RESET : 1; /*!< need_des */ - __IOM uint32_t FORCE_TOP_ISO : 1; /*!< need_des */ - __IOM uint32_t FORCE_TOP_PU : 1; /*!< need_des */ - __IOM uint32_t FORCE_TOP_NO_RESET : 1; /*!< need_des */ - __IOM uint32_t FORCE_TOP_NO_ISO : 1; /*!< need_des */ - __IOM uint32_t FORCE_TOP_PD : 1; /*!< need_des */ - uint32_t : 26; - } bit; - } POWER_PD_TOP_CNTL; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t FORCE_CNNT_RESET : 1; /*!< need_des */ - __IOM uint32_t FORCE_CNNT_ISO : 1; /*!< need_des */ - __IOM uint32_t FORCE_CNNT_PU : 1; /*!< need_des */ - __IOM uint32_t FORCE_CNNT_NO_RESET : 1; /*!< need_des */ - __IOM uint32_t FORCE_CNNT_NO_ISO : 1; /*!< need_des */ - __IOM uint32_t FORCE_CNNT_PD : 1; /*!< need_des */ - uint32_t : 26; - } bit; - } POWER_PD_CNNT_CNTL; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t FORCE_HP_MEM_RESET : 1; /*!< need_des */ - __IOM uint32_t FORCE_HP_MEM_ISO : 1; /*!< need_des */ - __IOM uint32_t FORCE_HP_MEM_PU : 1; /*!< need_des */ - __IOM uint32_t FORCE_HP_MEM_NO_RESET : 1; /*!< need_des */ - __IOM uint32_t FORCE_HP_MEM_NO_ISO : 1; /*!< need_des */ - __IOM uint32_t FORCE_HP_MEM_PD : 1; /*!< need_des */ - uint32_t : 26; - } bit; - } POWER_PD_HPMEM_CNTL; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t XPD_TOP_MASK : 5; /*!< need_des */ - uint32_t : 22; - __IOM uint32_t PD_TOP_MASK : 5; /*!< need_des */ - } bit; - } POWER_PD_TOP_MASK; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t XPD_CNNT_MASK : 5; /*!< need_des */ - uint32_t : 22; - __IOM uint32_t PD_CNNT_MASK : 5; /*!< need_des */ - } bit; - } POWER_PD_CNNT_MASK; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t XPD_HP_MEM_MASK : 6; /*!< need_des */ - uint32_t : 20; - __IOM uint32_t PD_HP_MEM_MASK : 6; /*!< need_des */ - } bit; - } POWER_PD_HPMEM_MASK; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t FORCE_DCDC_SWITCH_PU : 1; /*!< need_des */ - __IOM uint32_t FORCE_DCDC_SWITCH_PD : 1; /*!< need_des */ - uint32_t : 30; - } bit; - } POWER_DCDC_SWITCH; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t FORCE_LP_PERI_RESET : 1; /*!< need_des */ - __IOM uint32_t FORCE_LP_PERI_ISO : 1; /*!< need_des */ - __IOM uint32_t FORCE_LP_PERI_PU : 1; /*!< need_des */ - __IOM uint32_t FORCE_LP_PERI_NO_RESET : 1;/*!< need_des */ - __IOM uint32_t FORCE_LP_PERI_NO_ISO : 1; /*!< need_des */ - __IOM uint32_t FORCE_LP_PERI_PD : 1; /*!< need_des */ - uint32_t : 26; - } bit; - } POWER_PD_LPPERI_CNTL; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t XPD_LP_PERI_MASK : 5; /*!< need_des */ - uint32_t : 22; - __IOM uint32_t PD_LP_PERI_MASK : 5; /*!< need_des */ - } bit; - } POWER_PD_LPPERI_MASK; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t FORCE_HP_PAD_NO_ISO_ALL : 1;/*!< need_des */ - __IOM uint32_t FORCE_HP_PAD_ISO_ALL : 1; /*!< need_des */ - uint32_t : 30; - } bit; - } POWER_HP_PAD; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t PMU_WAIT_XTL_STABLE : 16; /*!< need_des */ - __IOM uint32_t PMU_WAIT_PLL_STABLE : 16; /*!< need_des */ - } bit; - } POWER_CK_WAIT_CNTL; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 31; - __OM uint32_t SLEEP_REQ : 1; /*!< need_des */ - } bit; - } SLP_WAKEUP_CNTL0; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t SLEEP_REJECT_ENA : 31; /*!< need_des */ - __IOM uint32_t SLP_REJECT_EN : 1; /*!< need_des */ - } bit; - } SLP_WAKEUP_CNTL1; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t WAKEUP_ENA : 31; /*!< need_des */ - uint32_t : 1; - } bit; - } SLP_WAKEUP_CNTL2; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t LP_MIN_SLP_VAL : 8; /*!< need_des */ - __IOM uint32_t HP_MIN_SLP_VAL : 8; /*!< need_des */ - __IOM uint32_t SLEEP_PRT_SEL : 2; /*!< need_des */ - uint32_t : 14; - } bit; - } SLP_WAKEUP_CNTL3; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 31; - __OM uint32_t SLP_REJECT_CAUSE_CLR : 1; /*!< need_des */ - } bit; - } SLP_WAKEUP_CNTL4; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t MODEM_WAIT_TARGET : 20; /*!< need_des */ - uint32_t : 4; - __IOM uint32_t LP_ANA_WAIT_TARGET : 8; /*!< need_des */ - } bit; - } SLP_WAKEUP_CNTL5; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t SOC_WAKEUP_WAIT : 20; /*!< need_des */ - uint32_t : 10; - __IOM uint32_t SOC_WAKEUP_WAIT_CFG : 2; /*!< need_des */ - } bit; - } SLP_WAKEUP_CNTL6; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 16; - __IOM uint32_t ANA_WAIT_TARGET : 16; /*!< need_des */ - } bit; - } SLP_WAKEUP_CNTL7; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 31; - __IOM uint32_t LP_LITE_WAKEUP_ENA : 1; /*!< need_des */ - } bit; - } SLP_WAKEUP_CNTL8; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IM uint32_t WAKEUP_CAUSE : 31; /*!< need_des */ - uint32_t : 1; - } bit; - } SLP_WAKEUP_STATUS0; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IM uint32_t REJECT_CAUSE : 31; /*!< need_des */ - uint32_t : 1; - } bit; - } SLP_WAKEUP_STATUS1; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 31; - __IM uint32_t LP_LITE_WAKEUP_CAUSE : 1; /*!< need_des */ - } bit; - } SLP_WAKEUP_STATUS2; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t I2C_POR_WAIT_TARGET : 8; /*!< need_des */ - uint32_t : 24; - } bit; - } HP_CK_POWERON; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t MODIFY_ICG_CNTL_WAIT : 8; /*!< need_des */ - __IOM uint32_t SWITCH_ICG_CNTL_WAIT : 8; /*!< need_des */ - uint32_t : 16; - } bit; - } HP_CK_CNTL; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 31; - __IM uint32_t POR_DONE : 1; /*!< need_des */ - } bit; - } POR_STATUS; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 24; - __IOM uint32_t MSPI_PHY_XPD : 1; /*!< need_des */ - __IOM uint32_t SDIO_PLL_XPD : 1; /*!< need_des */ - __IOM uint32_t PERIF_I2C_RSTB : 1; /*!< need_des */ - __IOM uint32_t XPD_PERIF_I2C : 1; /*!< need_des */ - __IOM uint32_t XPD_TXRF_I2C : 1; /*!< need_des */ - __IOM uint32_t XPD_RFRX_PBUS : 1; /*!< need_des */ - __IOM uint32_t XPD_CKGEN_I2C : 1; /*!< need_des */ - uint32_t : 1; - } bit; - } RF_PWC; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 31; - __IOM uint32_t BACKUP_SYS_CLK_NO_DIV : 1; /*!< need_des */ - } bit; - } BACKUP_CFG; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 14; - __IOM uint32_t _0P1A_CNT_TARGET0_REACH_0_HP_INT_RAW : 1;/*!< reg_0p1a_0_counter after xpd reach target0 */ - __IOM uint32_t _0P1A_CNT_TARGET1_REACH_0_HP_INT_RAW : 1;/*!< reg_0p1a_1_counter after xpd reach target1 */ - __IOM uint32_t _0P1A_CNT_TARGET0_REACH_1_HP_INT_RAW : 1;/*!< reg_0p1a_0 counter after xpd reach target0 */ - __IOM uint32_t _0P1A_CNT_TARGET1_REACH_1_HP_INT_RAW : 1;/*!< reg_0p1a_1_counter after xpd reach target1 */ - __IOM uint32_t _0P2A_CNT_TARGET0_REACH_0_HP_INT_RAW : 1;/*!< reg_0p2a_0 counter after xpd reach target0 */ - __IOM uint32_t _0P2A_CNT_TARGET1_REACH_0_HP_INT_RAW : 1;/*!< reg_0p2a_1_counter after xpd reach target1 */ - __IOM uint32_t _0P2A_CNT_TARGET0_REACH_1_HP_INT_RAW : 1;/*!< reg_0p2a_0 counter after xpd reach target0 */ - __IOM uint32_t _0P2A_CNT_TARGET1_REACH_1_HP_INT_RAW : 1;/*!< reg_0p2a_1_counter after xpd reach target1 */ - __IOM uint32_t _0P3A_CNT_TARGET0_REACH_0_HP_INT_RAW : 1;/*!< reg_0p3a_0 counter after xpd reach target0 */ - __IOM uint32_t _0P3A_CNT_TARGET1_REACH_0_HP_INT_RAW : 1;/*!< reg_0p3a_1_counter after xpd reach target1 */ - __IOM uint32_t _0P3A_CNT_TARGET0_REACH_1_HP_INT_RAW : 1;/*!< reg_0p3a_0_counter after xpd reach target0 */ - __IOM uint32_t _0P3A_CNT_TARGET1_REACH_1_HP_INT_RAW : 1;/*!< reg_0p3a_1_counter after xpd reach target1 */ - uint32_t : 1; - __IOM uint32_t LP_CPU_EXC_INT_RAW : 1; /*!< need_des */ - __IOM uint32_t SDIO_IDLE_INT_RAW : 1; /*!< need_des */ - __IOM uint32_t SW_INT_RAW : 1; /*!< need_des */ - __IOM uint32_t SOC_SLEEP_REJECT_INT_RAW : 1;/*!< need_des */ - __IOM uint32_t SOC_WAKEUP_INT_RAW : 1; /*!< need_des */ - } bit; - } INT_RAW; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 14; - __IM uint32_t _0P1A_CNT_TARGET0_REACH_0_HP_INT_ST : 1;/*!< reg_0p1a_0_counter after xpd reach target0 */ - __IM uint32_t _0P1A_CNT_TARGET1_REACH_0_HP_INT_ST : 1;/*!< reg_0p1a_1_counter after xpd reach target1 */ - __IM uint32_t _0P1A_CNT_TARGET0_REACH_1_HP_INT_ST : 1;/*!< reg_0p1a_0 counter after xpd reach target0 */ - __IM uint32_t _0P1A_CNT_TARGET1_REACH_1_HP_INT_ST : 1;/*!< reg_0p1a_1_counter after xpd reach target1 */ - __IM uint32_t _0P2A_CNT_TARGET0_REACH_0_HP_INT_ST : 1;/*!< reg_0p2a_0 counter after xpd reach target0 */ - __IM uint32_t _0P2A_CNT_TARGET1_REACH_0_HP_INT_ST : 1;/*!< reg_0p2a_1_counter after xpd reach target1 */ - __IM uint32_t _0P2A_CNT_TARGET0_REACH_1_HP_INT_ST : 1;/*!< reg_0p2a_0 counter after xpd reach target0 */ - __IM uint32_t _0P2A_CNT_TARGET1_REACH_1_HP_INT_ST : 1;/*!< reg_0p2a_1_counter after xpd reach target1 */ - __IM uint32_t _0P3A_CNT_TARGET0_REACH_0_HP_INT_ST : 1;/*!< reg_0p3a_0 counter after xpd reach target0 */ - __IM uint32_t _0P3A_CNT_TARGET1_REACH_0_HP_INT_ST : 1;/*!< reg_0p3a_1_counter after xpd reach target1 */ - __IM uint32_t _0P3A_CNT_TARGET0_REACH_1_HP_INT_ST : 1;/*!< reg_0p3a_0_counter after xpd reach target0 */ - __IM uint32_t _0P3A_CNT_TARGET1_REACH_1_HP_INT_ST : 1;/*!< reg_0p3a_1_counter after xpd reach target1 */ - uint32_t : 1; - __IM uint32_t LP_CPU_EXC_INT_ST : 1; /*!< need_des */ - __IM uint32_t SDIO_IDLE_INT_ST : 1; /*!< need_des */ - __IM uint32_t SW_INT_ST : 1; /*!< need_des */ - __IM uint32_t SOC_SLEEP_REJECT_INT_ST : 1;/*!< need_des */ - __IM uint32_t SOC_WAKEUP_INT_ST : 1; /*!< need_des */ - } bit; - } HP_INT_ST; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 14; - __IOM uint32_t _0P1A_CNT_TARGET0_REACH_0_HP_INT_ENA : 1;/*!< reg_0p1a_0_counter after xpd reach target0 */ - __IOM uint32_t _0P1A_CNT_TARGET1_REACH_0_HP_INT_ENA : 1;/*!< reg_0p1a_1_counter after xpd reach target1 */ - __IOM uint32_t _0P1A_CNT_TARGET0_REACH_1_HP_INT_ENA : 1;/*!< reg_0p1a_0 counter after xpd reach target0 */ - __IOM uint32_t _0P1A_CNT_TARGET1_REACH_1_HP_INT_ENA : 1;/*!< reg_0p1a_1_counter after xpd reach target1 */ - __IOM uint32_t _0P2A_CNT_TARGET0_REACH_0_HP_INT_ENA : 1;/*!< reg_0p2a_0 counter after xpd reach target0 */ - __IOM uint32_t _0P2A_CNT_TARGET1_REACH_0_HP_INT_ENA : 1;/*!< reg_0p2a_1_counter after xpd reach target1 */ - __IOM uint32_t _0P2A_CNT_TARGET0_REACH_1_HP_INT_ENA : 1;/*!< reg_0p2a_0 counter after xpd reach target0 */ - __IOM uint32_t _0P2A_CNT_TARGET1_REACH_1_HP_INT_ENA : 1;/*!< reg_0p2a_1_counter after xpd reach target1 */ - __IOM uint32_t _0P3A_CNT_TARGET0_REACH_0_HP_INT_ENA : 1;/*!< reg_0p3a_0 counter after xpd reach target0 */ - __IOM uint32_t _0P3A_CNT_TARGET1_REACH_0_HP_INT_ENA : 1;/*!< reg_0p3a_1_counter after xpd reach target1 */ - __IOM uint32_t _0P3A_CNT_TARGET0_REACH_1_HP_INT_ENA : 1;/*!< reg_0p3a_0_counter after xpd reach target0 */ - __IOM uint32_t _0P3A_CNT_TARGET1_REACH_1_HP_INT_ENA : 1;/*!< reg_0p3a_1_counter after xpd reach target1 */ - uint32_t : 1; - __IOM uint32_t LP_CPU_EXC_INT_ENA : 1; /*!< need_des */ - __IOM uint32_t SDIO_IDLE_INT_ENA : 1; /*!< need_des */ - __IOM uint32_t SW_INT_ENA : 1; /*!< need_des */ - __IOM uint32_t SOC_SLEEP_REJECT_INT_ENA : 1;/*!< need_des */ - __IOM uint32_t SOC_WAKEUP_INT_ENA : 1; /*!< need_des */ - } bit; - } HP_INT_ENA; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 14; - __OM uint32_t _0P1A_CNT_TARGET0_REACH_0_HP_INT_CLR : 1;/*!< reg_0p1a_0_counter after xpd reach target0 */ - __OM uint32_t _0P1A_CNT_TARGET1_REACH_0_HP_INT_CLR : 1;/*!< reg_0p1a_1_counter after xpd reach target1 */ - __OM uint32_t _0P1A_CNT_TARGET0_REACH_1_HP_INT_CLR : 1;/*!< reg_0p1a_0 counter after xpd reach target0 */ - __OM uint32_t _0P1A_CNT_TARGET1_REACH_1_HP_INT_CLR : 1;/*!< reg_0p1a_1_counter after xpd reach target1 */ - __OM uint32_t _0P2A_CNT_TARGET0_REACH_0_HP_INT_CLR : 1;/*!< reg_0p2a_0 counter after xpd reach target0 */ - __OM uint32_t _0P2A_CNT_TARGET1_REACH_0_HP_INT_CLR : 1;/*!< reg_0p2a_1_counter after xpd reach target1 */ - __OM uint32_t _0P2A_CNT_TARGET0_REACH_1_HP_INT_CLR : 1;/*!< reg_0p2a_0 counter after xpd reach target0 */ - __OM uint32_t _0P2A_CNT_TARGET1_REACH_1_HP_INT_CLR : 1;/*!< reg_0p2a_1_counter after xpd reach target1 */ - __OM uint32_t _0P3A_CNT_TARGET0_REACH_0_HP_INT_CLR : 1;/*!< reg_0p3a_0 counter after xpd reach target0 */ - __OM uint32_t _0P3A_CNT_TARGET1_REACH_0_HP_INT_CLR : 1;/*!< reg_0p3a_1_counter after xpd reach target1 */ - __OM uint32_t _0P3A_CNT_TARGET0_REACH_1_HP_INT_CLR : 1;/*!< reg_0p3a_0_counter after xpd reach target0 */ - __OM uint32_t _0P3A_CNT_TARGET1_REACH_1_HP_INT_CLR : 1;/*!< reg_0p3a_1_counter after xpd reach target1 */ - uint32_t : 1; - __OM uint32_t LP_CPU_EXC_INT_CLR : 1; /*!< need_des */ - __OM uint32_t SDIO_IDLE_INT_CLR : 1; /*!< need_des */ - __OM uint32_t SW_INT_CLR : 1; /*!< need_des */ - __OM uint32_t SOC_SLEEP_REJECT_INT_CLR : 1;/*!< need_des */ - __OM uint32_t SOC_WAKEUP_INT_CLR : 1; /*!< need_des */ - } bit; - } HP_INT_CLR; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 13; - __IOM uint32_t LP_CPU_SLEEP_REJECT_INT_RAW : 1;/*!< need_des */ - __IOM uint32_t _0P1A_CNT_TARGET0_REACH_0_LP_INT_RAW : 1;/*!< reg_0p1a_0_counter after xpd reach target0 */ - __IOM uint32_t _0P1A_CNT_TARGET1_REACH_0_LP_INT_RAW : 1;/*!< reg_0p1a_1_counter after xpd reach target1 */ - __IOM uint32_t _0P1A_CNT_TARGET0_REACH_1_LP_INT_RAW : 1;/*!< reg_0p1a_0 counter after xpd reach target0 */ - __IOM uint32_t _0P1A_CNT_TARGET1_REACH_1_LP_INT_RAW : 1;/*!< reg_0p1a_1_counter after xpd reach target1 */ - __IOM uint32_t _0P2A_CNT_TARGET0_REACH_0_LP_INT_RAW : 1;/*!< reg_0p2a_0 counter after xpd reach target0 */ - __IOM uint32_t _0P2A_CNT_TARGET1_REACH_0_LP_INT_RAW : 1;/*!< reg_0p2a_1_counter after xpd reach target1 */ - __IOM uint32_t _0P2A_CNT_TARGET0_REACH_1_LP_INT_RAW : 1;/*!< reg_0p2a_0 counter after xpd reach target0 */ - __IOM uint32_t _0P2A_CNT_TARGET1_REACH_1_LP_INT_RAW : 1;/*!< reg_0p2a_1_counter after xpd reach target1 */ - __IOM uint32_t _0P3A_CNT_TARGET0_REACH_0_LP_INT_RAW : 1;/*!< reg_0p3a_0 counter after xpd reach target0 */ - __IOM uint32_t _0P3A_CNT_TARGET1_REACH_0_LP_INT_RAW : 1;/*!< reg_0p3a_1_counter after xpd reach target1 */ - __IOM uint32_t _0P3A_CNT_TARGET0_REACH_1_LP_INT_RAW : 1;/*!< reg_0p3a_0_counter after xpd reach target0 */ - __IOM uint32_t _0P3A_CNT_TARGET1_REACH_1_LP_INT_RAW : 1;/*!< reg_0p3a_1_counter after xpd reach target1 */ - __IOM uint32_t LP_CPU_WAKEUP_INT_RAW : 1; /*!< need_des */ - __IOM uint32_t SLEEP_SWITCH_ACTIVE_END_INT_RAW : 1;/*!< need_des */ - __IOM uint32_t ACTIVE_SWITCH_SLEEP_END_INT_RAW : 1;/*!< need_des */ - __IOM uint32_t SLEEP_SWITCH_ACTIVE_START_INT_RAW : 1;/*!< need_des */ - __IOM uint32_t ACTIVE_SWITCH_SLEEP_START_INT_RAW : 1;/*!< need_des */ - __IOM uint32_t HP_SW_TRIGGER_INT_RAW : 1; /*!< need_des */ - } bit; - } LP_INT_RAW; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 13; - __IM uint32_t LP_CPU_SLEEP_REJECT_INT_ST : 1;/*!< need_des */ - __IM uint32_t _0P1A_CNT_TARGET0_REACH_0_LP_INT_ST : 1;/*!< reg_0p1a_0_counter after xpd reach target0 */ - __IM uint32_t _0P1A_CNT_TARGET1_REACH_0_LP_INT_ST : 1;/*!< reg_0p1a_1_counter after xpd reach target1 */ - __IM uint32_t _0P1A_CNT_TARGET0_REACH_1_LP_INT_ST : 1;/*!< reg_0p1a_0 counter after xpd reach target0 */ - __IM uint32_t _0P1A_CNT_TARGET1_REACH_1_LP_INT_ST : 1;/*!< reg_0p1a_1_counter after xpd reach target1 */ - __IM uint32_t _0P2A_CNT_TARGET0_REACH_0_LP_INT_ST : 1;/*!< reg_0p2a_0 counter after xpd reach target0 */ - __IM uint32_t _0P2A_CNT_TARGET1_REACH_0_LP_INT_ST : 1;/*!< reg_0p2a_1_counter after xpd reach target1 */ - __IM uint32_t _0P2A_CNT_TARGET0_REACH_1_LP_INT_ST : 1;/*!< reg_0p2a_0 counter after xpd reach target0 */ - __IM uint32_t _0P2A_CNT_TARGET1_REACH_1_LP_INT_ST : 1;/*!< reg_0p2a_1_counter after xpd reach target1 */ - __IM uint32_t _0P3A_CNT_TARGET0_REACH_0_LP_INT_ST : 1;/*!< reg_0p3a_0 counter after xpd reach target0 */ - __IM uint32_t _0P3A_CNT_TARGET1_REACH_0_LP_INT_ST : 1;/*!< reg_0p3a_1_counter after xpd reach target1 */ - __IM uint32_t _0P3A_CNT_TARGET0_REACH_1_LP_INT_ST : 1;/*!< reg_0p3a_0_counter after xpd reach target0 */ - __IM uint32_t _0P3A_CNT_TARGET1_REACH_1_LP_INT_ST : 1;/*!< reg_0p3a_1_counter after xpd reach target1 */ - __IM uint32_t LP_CPU_WAKEUP_INT_ST : 1; /*!< need_des */ - __IM uint32_t SLEEP_SWITCH_ACTIVE_END_INT_ST : 1;/*!< need_des */ - __IM uint32_t ACTIVE_SWITCH_SLEEP_END_INT_ST : 1;/*!< need_des */ - __IM uint32_t SLEEP_SWITCH_ACTIVE_START_INT_ST : 1;/*!< need_des */ - __IM uint32_t ACTIVE_SWITCH_SLEEP_START_INT_ST : 1;/*!< need_des */ - __IM uint32_t HP_SW_TRIGGER_INT_ST : 1; /*!< need_des */ - } bit; - } LP_INT_ST; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 13; - __IOM uint32_t LP_CPU_SLEEP_REJECT_INT_ENA : 1;/*!< need_des */ - __IOM uint32_t _0P1A_CNT_TARGET0_REACH_0_LP_INT_ENA : 1;/*!< reg_0p1a_0_counter after xpd reach target0 */ - __IOM uint32_t _0P1A_CNT_TARGET1_REACH_0_LP_INT_ENA : 1;/*!< reg_0p1a_1_counter after xpd reach target1 */ - __IOM uint32_t _0P1A_CNT_TARGET0_REACH_1_LP_INT_ENA : 1;/*!< reg_0p1a_0 counter after xpd reach target0 */ - __IOM uint32_t _0P1A_CNT_TARGET1_REACH_1_LP_INT_ENA : 1;/*!< reg_0p1a_1_counter after xpd reach target1 */ - __IOM uint32_t _0P2A_CNT_TARGET0_REACH_0_LP_INT_ENA : 1;/*!< reg_0p2a_0 counter after xpd reach target0 */ - __IOM uint32_t _0P2A_CNT_TARGET1_REACH_0_LP_INT_ENA : 1;/*!< reg_0p2a_1_counter after xpd reach target1 */ - __IOM uint32_t _0P2A_CNT_TARGET0_REACH_1_LP_INT_ENA : 1;/*!< reg_0p2a_0 counter after xpd reach target0 */ - __IOM uint32_t _0P2A_CNT_TARGET1_REACH_1_LP_INT_ENA : 1;/*!< reg_0p2a_1_counter after xpd reach target1 */ - __IOM uint32_t _0P3A_CNT_TARGET0_REACH_0_LP_INT_ENA : 1;/*!< reg_0p3a_0 counter after xpd reach target0 */ - __IOM uint32_t _0P3A_CNT_TARGET1_REACH_0_LP_INT_ENA : 1;/*!< reg_0p3a_1_counter after xpd reach target1 */ - __IOM uint32_t _0P3A_CNT_TARGET0_REACH_1_LP_INT_ENA : 1;/*!< reg_0p3a_0_counter after xpd reach target0 */ - __IOM uint32_t _0P3A_CNT_TARGET1_REACH_1_LP_INT_ENA : 1;/*!< reg_0p3a_1_counter after xpd reach target1 */ - __IOM uint32_t LP_CPU_WAKEUP_INT_ENA : 1; /*!< need_des */ - __IOM uint32_t SLEEP_SWITCH_ACTIVE_END_INT_ENA : 1;/*!< need_des */ - __IOM uint32_t ACTIVE_SWITCH_SLEEP_END_INT_ENA : 1;/*!< need_des */ - __IOM uint32_t SLEEP_SWITCH_ACTIVE_START_INT_ENA : 1;/*!< need_des */ - __IOM uint32_t ACTIVE_SWITCH_SLEEP_START_INT_ENA : 1;/*!< need_des */ - __IOM uint32_t HP_SW_TRIGGER_INT_ENA : 1; /*!< need_des */ - } bit; - } LP_INT_ENA; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 13; - __OM uint32_t LP_CPU_SLEEP_REJECT_LP_INT_CLR : 1;/*!< need_des */ - __OM uint32_t _0P1A_CNT_TARGET0_REACH_0_LP_INT_CLR : 1;/*!< reg_0p1a_0_counter after xpd reach target0 */ - __OM uint32_t _0P1A_CNT_TARGET1_REACH_0_LP_INT_CLR : 1;/*!< reg_0p1a_1_counter after xpd reach target1 */ - __OM uint32_t _0P1A_CNT_TARGET0_REACH_1_LP_INT_CLR : 1;/*!< reg_0p1a_0 counter after xpd reach target0 */ - __OM uint32_t _0P1A_CNT_TARGET1_REACH_1_LP_INT_CLR : 1;/*!< reg_0p1a_1_counter after xpd reach target1 */ - __OM uint32_t _0P2A_CNT_TARGET0_REACH_0_LP_INT_CLR : 1;/*!< reg_0p2a_0 counter after xpd reach target0 */ - __OM uint32_t _0P2A_CNT_TARGET1_REACH_0_LP_INT_CLR : 1;/*!< reg_0p2a_1_counter after xpd reach target1 */ - __OM uint32_t _0P2A_CNT_TARGET0_REACH_1_LP_INT_CLR : 1;/*!< reg_0p2a_0 counter after xpd reach target0 */ - __OM uint32_t _0P2A_CNT_TARGET1_REACH_1_LP_INT_CLR : 1;/*!< reg_0p2a_1_counter after xpd reach target1 */ - __OM uint32_t _0P3A_CNT_TARGET0_REACH_0_LP_INT_CLR : 1;/*!< reg_0p3a_0 counter after xpd reach target0 */ - __OM uint32_t _0P3A_CNT_TARGET1_REACH_0_LP_INT_CLR : 1;/*!< reg_0p3a_1_counter after xpd reach target1 */ - __OM uint32_t _0P3A_CNT_TARGET0_REACH_1_LP_INT_CLR : 1;/*!< reg_0p3a_0_counter after xpd reach target0 */ - __OM uint32_t _0P3A_CNT_TARGET1_REACH_1_LP_INT_CLR : 1;/*!< reg_0p3a_1_counter after xpd reach target1 */ - __OM uint32_t LP_CPU_WAKEUP_INT_CLR : 1; /*!< need_des */ - __OM uint32_t SLEEP_SWITCH_ACTIVE_END_INT_CLR : 1;/*!< need_des */ - __OM uint32_t ACTIVE_SWITCH_SLEEP_END_INT_CLR : 1;/*!< need_des */ - __OM uint32_t SLEEP_SWITCH_ACTIVE_START_INT_CLR : 1;/*!< need_des */ - __OM uint32_t ACTIVE_SWITCH_SLEEP_START_INT_CLR : 1;/*!< need_des */ - __OM uint32_t HP_SW_TRIGGER_INT_CLR : 1; /*!< need_des */ - } bit; - } LP_INT_CLR; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IM uint32_t LP_CPU_WAITI_RDY : 1; /*!< need_des */ - __IM uint32_t LP_CPU_STALL_RDY : 1; /*!< need_des */ - uint32_t : 16; - __IOM uint32_t LP_CPU_FORCE_STALL : 1; /*!< need_des */ - __IOM uint32_t LP_CPU_SLP_WAITI_FLAG_EN : 1;/*!< need_des */ - __IOM uint32_t LP_CPU_SLP_STALL_FLAG_EN : 1;/*!< need_des */ - __IOM uint32_t LP_CPU_SLP_STALL_WAIT : 8; /*!< need_des */ - __IOM uint32_t LP_CPU_SLP_STALL_EN : 1; /*!< need_des */ - __IOM uint32_t LP_CPU_SLP_RESET_EN : 1; /*!< need_des */ - __IOM uint32_t LP_CPU_SLP_BYPASS_INTR_EN : 1;/*!< need_des */ - } bit; - } LP_CPU_PWR0; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 31; - __OM uint32_t LP_CPU_SLEEP_REQ : 1; /*!< need_des */ - } bit; - } LP_CPU_PWR1; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t LP_CPU_WAKEUP_EN : 31; /*!< need_des */ - uint32_t : 1; - } bit; - } LP_CPU_PWR2; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IM uint32_t LP_CPU_WAKEUP_CAUSE : 31; /*!< need_des */ - uint32_t : 1; - } bit; - } LP_CPU_PWR3; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t LP_CPU_REJECT_EN : 31; /*!< need_des */ - uint32_t : 1; - } bit; - } LP_CPU_PWR4; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IM uint32_t LP_CPU_REJECT_CAUSE : 31; /*!< need_des */ - uint32_t : 1; - } bit; - } LP_CPU_PWR5; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 30; - __OM uint32_t LP_TRIGGER_HP : 1; /*!< need_des */ - __OM uint32_t HP_TRIGGER_LP : 1; /*!< need_des */ - } bit; - } HP_LP_CPU_COMM; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 31; - __IOM uint32_t DIG_REGULATOR_EN_CAL : 1; /*!< need_des */ - } bit; - } HP_REGULATOR_CFG; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t ENABLE_CALI_PMU_CNTL : 1; /*!< need_des */ - uint32_t : 10; - __IM uint32_t PMU_MAIN_LAST_ST_STATE : 7;/*!< need_des */ - __IM uint32_t PMU_MAIN_TAR_ST_STATE : 7; /*!< need_des */ - __IM uint32_t PMU_MAIN_CUR_ST_STATE : 7; /*!< need_des */ - } bit; - } MAIN_STATE; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 13; - __IM uint32_t PMU_BACKUP_ST_STATE : 5; /*!< need_des */ - __IM uint32_t PMU_LP_PWR_ST_STATE : 5; /*!< need_des */ - __IM uint32_t PMU_HP_PWR_ST_STATE : 9; /*!< need_des */ - } bit; - } PWR_STATE; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IM uint32_t STABLE_XPD_PLL_STATE : 3; /*!< need_des */ - __IM uint32_t STABLE_XPD_XTAL_STATE : 1; /*!< need_des */ - __IM uint32_t PMU_ANA_XPD_PLL_I2C_STATE : 3;/*!< need_des */ - uint32_t : 3; - __IM uint32_t PMU_SYS_CLK_SLP_SEL_STATE : 1;/*!< need_des */ - __IM uint32_t PMU_SYS_CLK_SEL_STATE : 2; /*!< need_des */ - __IM uint32_t PMU_SYS_CLK_NO_DIV_STATE : 1;/*!< need_des */ - __IM uint32_t PMU_ICG_SYS_CLK_EN_STATE : 1;/*!< need_des */ - __IM uint32_t PMU_ICG_MODEM_SWITCH_STATE : 1;/*!< need_des */ - __IM uint32_t PMU_ICG_MODEM_CODE_STATE : 2;/*!< need_des */ - __IM uint32_t PMU_ICG_SLP_SEL_STATE : 1; /*!< need_des */ - __IM uint32_t PMU_ICG_GLOBAL_XTAL_STATE : 1;/*!< need_des */ - __IM uint32_t PMU_ICG_GLOBAL_PLL_STATE : 4;/*!< need_des */ - __IM uint32_t PMU_ANA_I2C_ISO_EN_STATE : 1;/*!< need_des */ - __IM uint32_t PMU_ANA_I2C_RETENTION_STATE : 1;/*!< need_des */ - uint32_t : 1; - __IM uint32_t PMU_ANA_XPD_PLL_STATE : 4; /*!< need_des */ - __IM uint32_t PMU_ANA_XPD_XTAL_STATE : 1;/*!< need_des */ - } bit; - } CLK_STATE0; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IM uint32_t PMU_ICG_FUNC_EN_STATE : 32;/*!< need_des */ - } bit; - } CLK_STATE1; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IM uint32_t PMU_ICG_APB_EN_STATE : 32; /*!< need_des */ - } bit; - } CLK_STATE2; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 7; - __IOM uint32_t _0P1A_FORCE_TIEH_SEL_0 : 1;/*!< need_des */ - __IOM uint32_t _0P1A_XPD_0 : 1; /*!< need_des */ - __IOM uint32_t _0P1A_TIEH_SEL_0 : 3; /*!< need_des */ - __IOM uint32_t _0P1A_TIEH_POS_EN_0 : 1; /*!< need_des */ - __IOM uint32_t _0P1A_TIEH_NEG_EN_0 : 1; /*!< need_des */ - __IOM uint32_t _0P1A_TIEH_0 : 1; /*!< need_des */ - __IOM uint32_t _0P1A_TARGET1_0 : 8; /*!< need_des */ - __IOM uint32_t _0P1A_TARGET0_0 : 8; /*!< need_des */ - __IOM uint32_t _0P1A_LDO_CNT_PRESCALER_SEL_0 : 1;/*!< need_des */ - } bit; - } EXT_LDO_P0_0P1A; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 23; - __IOM uint32_t ANA_0P1A_MUL_0 : 3; /*!< need_des */ - __IOM uint32_t ANA_0P1A_EN_VDET_0 : 1; /*!< need_des */ - __IOM uint32_t ANA_0P1A_EN_CUR_LIM_0 : 1; /*!< need_des */ - __IOM uint32_t ANA_0P1A_DREF_0 : 4; /*!< need_des */ - } bit; - } EXT_LDO_P0_0P1A_ANA; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 7; - __IOM uint32_t _0P2A_FORCE_TIEH_SEL_0 : 1;/*!< need_des */ - __IOM uint32_t _0P2A_XPD_0 : 1; /*!< need_des */ - __IOM uint32_t _0P2A_TIEH_SEL_0 : 3; /*!< need_des */ - __IOM uint32_t _0P2A_TIEH_POS_EN_0 : 1; /*!< need_des */ - __IOM uint32_t _0P2A_TIEH_NEG_EN_0 : 1; /*!< need_des */ - __IOM uint32_t _0P2A_TIEH_0 : 1; /*!< need_des */ - __IOM uint32_t _0P2A_TARGET1_0 : 8; /*!< need_des */ - __IOM uint32_t _0P2A_TARGET0_0 : 8; /*!< need_des */ - __IOM uint32_t _0P2A_LDO_CNT_PRESCALER_SEL_0 : 1;/*!< need_des */ - } bit; - } EXT_LDO_P0_0P2A; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 23; - __IOM uint32_t ANA_0P2A_MUL_0 : 3; /*!< need_des */ - __IOM uint32_t ANA_0P2A_EN_VDET_0 : 1; /*!< need_des */ - __IOM uint32_t ANA_0P2A_EN_CUR_LIM_0 : 1; /*!< need_des */ - __IOM uint32_t ANA_0P2A_DREF_0 : 4; /*!< need_des */ - } bit; - } EXT_LDO_P0_0P2A_ANA; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 7; - __IOM uint32_t _0P3A_FORCE_TIEH_SEL_0 : 1;/*!< need_des */ - __IOM uint32_t _0P3A_XPD_0 : 1; /*!< need_des */ - __IOM uint32_t _0P3A_TIEH_SEL_0 : 3; /*!< need_des */ - __IOM uint32_t _0P3A_TIEH_POS_EN_0 : 1; /*!< need_des */ - __IOM uint32_t _0P3A_TIEH_NEG_EN_0 : 1; /*!< need_des */ - __IOM uint32_t _0P3A_TIEH_0 : 1; /*!< need_des */ - __IOM uint32_t _0P3A_TARGET1_0 : 8; /*!< need_des */ - __IOM uint32_t _0P3A_TARGET0_0 : 8; /*!< need_des */ - __IOM uint32_t _0P3A_LDO_CNT_PRESCALER_SEL_0 : 1;/*!< need_des */ - } bit; - } EXT_LDO_P0_0P3A; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 23; - __IOM uint32_t ANA_0P3A_MUL_0 : 3; /*!< need_des */ - __IOM uint32_t ANA_0P3A_EN_VDET_0 : 1; /*!< need_des */ - __IOM uint32_t ANA_0P3A_EN_CUR_LIM_0 : 1; /*!< need_des */ - __IOM uint32_t ANA_0P3A_DREF_0 : 4; /*!< need_des */ - } bit; - } EXT_LDO_P0_0P3A_ANA; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 7; - __IOM uint32_t _0P1A_FORCE_TIEH_SEL_1 : 1;/*!< need_des */ - __IOM uint32_t _0P1A_XPD_1 : 1; /*!< need_des */ - __IOM uint32_t _0P1A_TIEH_SEL_1 : 3; /*!< need_des */ - __IOM uint32_t _0P1A_TIEH_POS_EN_1 : 1; /*!< need_des */ - __IOM uint32_t _0P1A_TIEH_NEG_EN_1 : 1; /*!< need_des */ - __IOM uint32_t _0P1A_TIEH_1 : 1; /*!< need_des */ - __IOM uint32_t _0P1A_TARGET1_1 : 8; /*!< need_des */ - __IOM uint32_t _0P1A_TARGET0_1 : 8; /*!< need_des */ - __IOM uint32_t _0P1A_LDO_CNT_PRESCALER_SEL_1 : 1;/*!< need_des */ - } bit; - } EXT_LDO_P1_0P1A; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 23; - __IOM uint32_t ANA_0P1A_MUL_1 : 3; /*!< need_des */ - __IOM uint32_t ANA_0P1A_EN_VDET_1 : 1; /*!< need_des */ - __IOM uint32_t ANA_0P1A_EN_CUR_LIM_1 : 1; /*!< need_des */ - __IOM uint32_t ANA_0P1A_DREF_1 : 4; /*!< need_des */ - } bit; - } EXT_LDO_P1_0P1A_ANA; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 7; - __IOM uint32_t _0P2A_FORCE_TIEH_SEL_1 : 1;/*!< need_des */ - __IOM uint32_t _0P2A_XPD_1 : 1; /*!< need_des */ - __IOM uint32_t _0P2A_TIEH_SEL_1 : 3; /*!< need_des */ - __IOM uint32_t _0P2A_TIEH_POS_EN_1 : 1; /*!< need_des */ - __IOM uint32_t _0P2A_TIEH_NEG_EN_1 : 1; /*!< need_des */ - __IOM uint32_t _0P2A_TIEH_1 : 1; /*!< need_des */ - __IOM uint32_t _0P2A_TARGET1_1 : 8; /*!< need_des */ - __IOM uint32_t _0P2A_TARGET0_1 : 8; /*!< need_des */ - __IOM uint32_t _0P2A_LDO_CNT_PRESCALER_SEL_1 : 1;/*!< need_des */ - } bit; - } EXT_LDO_P1_0P2A; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 23; - __IOM uint32_t ANA_0P2A_MUL_1 : 3; /*!< need_des */ - __IOM uint32_t ANA_0P2A_EN_VDET_1 : 1; /*!< need_des */ - __IOM uint32_t ANA_0P2A_EN_CUR_LIM_1 : 1; /*!< need_des */ - __IOM uint32_t ANA_0P2A_DREF_1 : 4; /*!< need_des */ - } bit; - } EXT_LDO_P1_0P2A_ANA; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 7; - __IOM uint32_t _0P3A_FORCE_TIEH_SEL_1 : 1;/*!< need_des */ - __IOM uint32_t _0P3A_XPD_1 : 1; /*!< need_des */ - __IOM uint32_t _0P3A_TIEH_SEL_1 : 3; /*!< need_des */ - __IOM uint32_t _0P3A_TIEH_POS_EN_1 : 1; /*!< need_des */ - __IOM uint32_t _0P3A_TIEH_NEG_EN_1 : 1; /*!< need_des */ - __IOM uint32_t _0P3A_TIEH_1 : 1; /*!< need_des */ - __IOM uint32_t _0P3A_TARGET1_1 : 8; /*!< need_des */ - __IOM uint32_t _0P3A_TARGET0_1 : 8; /*!< need_des */ - __IOM uint32_t _0P3A_LDO_CNT_PRESCALER_SEL_1 : 1;/*!< need_des */ - } bit; - } EXT_LDO_P1_0P3A; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 23; - __IOM uint32_t ANA_0P3A_MUL_1 : 3; /*!< need_des */ - __IOM uint32_t ANA_0P3A_EN_VDET_1 : 1; /*!< need_des */ - __IOM uint32_t ANA_0P3A_EN_CUR_LIM_1 : 1; /*!< need_des */ - __IOM uint32_t ANA_0P3A_DREF_1 : 4; /*!< need_des */ - } bit; - } EXT_LDO_P1_0P3A_ANA; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t EXT_WAKEUP_LV : 32; /*!< need_des */ - } bit; - } EXT_WAKEUP_LV; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t EXT_WAKEUP_SEL : 32; /*!< need_des */ - } bit; - } EXT_WAKEUP_SEL; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IM uint32_t EXT_WAKEUP_STATUS : 32; /*!< need_des */ - } bit; - } EXT_WAKEUP_ST; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 30; - __IOM uint32_t EXT_WAKEUP_STATUS_CLR : 1; /*!< need_des */ - __IOM uint32_t EXT_WAKEUP_FILTER : 1; /*!< need_des */ - } bit; - } EXT_WAKEUP_CNTL; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t SDIO_ACT_DNUM : 10; /*!< need_des */ - uint32_t : 22; - } bit; - } SDIO_WAKEUP_CNTL; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 16; - __IOM uint32_t CNT_TARGET : 16; /*!< need_des */ - } bit; - } XTAL_SLP; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 16; - __IOM uint32_t HPCORE1_SW_STALL_CODE : 8; /*!< need_des */ - __IOM uint32_t HPCORE0_SW_STALL_CODE : 8; /*!< need_des */ - } bit; - } CPU_SW_STALL; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __OM uint32_t DCDC_ON_REQ : 1; /*!< SW trigger dcdc on */ - __OM uint32_t DCDC_OFF_REQ : 1; /*!< SW trigger dcdc off */ - __OM uint32_t DCDC_LIGHTSLP_REQ : 1; /*!< SW trigger dcdc enter lightsleep */ - __OM uint32_t DCDC_DEEPSLP_REQ : 1; /*!< SW trigger dcdc enter deepsleep */ - uint32_t : 3; - __IOM uint32_t DCDC_DONE_FORCE : 1; /*!< need_des */ - __IOM uint32_t DCDC_ON_FORCE_PU : 1; /*!< need_des */ - __IOM uint32_t DCDC_ON_FORCE_PD : 1; /*!< need_des */ - __IOM uint32_t DCDC_FB_RES_FORCE_PU : 1; /*!< need_des */ - __IOM uint32_t DCDC_FB_RES_FORCE_PD : 1; /*!< need_des */ - __IOM uint32_t DCDC_LS_FORCE_PU : 1; /*!< need_des */ - __IOM uint32_t DCDC_LS_FORCE_PD : 1; /*!< need_des */ - __IOM uint32_t DCDC_DS_FORCE_PU : 1; /*!< need_des */ - __IOM uint32_t DCDC_DS_FORCE_PD : 1; /*!< need_des */ - __IM uint32_t DCM_CUR_ST : 8; /*!< need_des */ - uint32_t : 5; - __IOM uint32_t DCDC_EN_AMUX_TEST : 1; /*!< Enable analog mux to pull PAD TEST_DCDC voltage signal */ - uint32_t : 2; - } bit; - } DCM_CTRL; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t DCDC_PRE_DELAY : 8; /*!< DCDC pre-on/post off delay */ - __IOM uint32_t DCDC_RES_OFF_DELAY : 8; /*!< DCDC fb res off delay */ - __IOM uint32_t DCDC_STABLE_DELAY : 10; /*!< DCDC stable delay */ - uint32_t : 6; - } bit; - } DCM_WAIT_DELAY; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IM uint32_t ANA_VDDBAT_MODE : 2; /*!< need_des */ - uint32_t : 29; - __OM uint32_t VDDBAT_SW_UPDATE : 1; /*!< need_des */ - } bit; - } VDDBAT_CFG; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 5; - __IOM uint32_t TOUCH_WAIT_CYCLES : 9; /*!< need_des */ - __IOM uint32_t TOUCH_SLEEP_CYCLES : 16; /*!< need_des */ - __IOM uint32_t TOUCH_FORCE_DONE : 1; /*!< need_des */ - __IOM uint32_t TOUCH_SLEEP_TIMER_EN : 1; /*!< need_des */ - } bit; - } TOUCH_PWR_CNTL; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IM uint32_t PMU_RDN_ECO_RESULT : 1; /*!< need_des */ - uint32_t : 30; - __IOM uint32_t PMU_RDN_ECO_EN : 1; /*!< need_des */ - } bit; - } RDN_ECO; - __IM uint32_t RESERVED[121]; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t PMU_DATE : 31; /*!< need_des */ - __IOM uint32_t CLK_EN : 1; /*!< need_des */ - } bit; - } DATE; -} PMU_Type; /*!< Size = 1024 (0x400) */ - - - -/* =========================================================================================================================== */ -/* ================ PPA ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief PPA Peripheral (PPA) - */ - -typedef struct { /*!< PPA Structure */ - - union { - __IOM uint32_t reg; /*!< CLUT sram data read/write register in background plane of blender */ - - struct { - __IOM uint32_t RDWR_WORD_BLEND0_CLUT : 32;/*!< Write and read data to/from CLUT RAM in background plane of - blender engine through this field in fifo mode. */ - } bit; - } BLEND0_CLUT_DATA; - - union { - __IOM uint32_t reg; /*!< CLUT sram data read/write register in foreground plane of blender */ - - struct { - __IOM uint32_t RDWR_WORD_BLEND1_CLUT : 32;/*!< Write and read data to/from CLUT RAM in foreground plane of - blender engine through this field in fifo mode. */ - } bit; - } BLEND1_CLUT_DATA; - __IM uint32_t RESERVED; - - union { - __IOM uint32_t reg; /*!< CLUT configure register */ - - struct { - __IOM uint32_t APB_FIFO_MASK : 1; /*!< 1'b0: fifo mode to wr/rd clut0/clut1 RAM through register PPA_SR_CLUT_DATA_REG - PPA_BLEND0_CLUT_DATA_REG/PPA_BLEND1_CLUT_DATA_REG. 1'b1: - memory mode to wr/rd sr/blend0/blend1 clut RAM. The bit - 11 and 10 of the waddr should be 01 to access sr clut and - should be 10 to access blend0 clut and should be 11 to - access blend 1 clut in memory mode. */ - __IOM uint32_t BLEND0_CLUT_MEM_RST : 1; /*!< Write 1 then write 0 to this bit to reset BLEND0 CLUT. */ - __IOM uint32_t BLEND1_CLUT_MEM_RST : 1; /*!< Write 1 then write 0 to this bit to reset BLEND1 CLUT. */ - __IOM uint32_t BLEND0_CLUT_MEM_RDADDR_RST : 1;/*!< Write 1 then write 0 to reset the read address of BLEND0 CLUT - in fifo mode. */ - __IOM uint32_t BLEND1_CLUT_MEM_RDADDR_RST : 1;/*!< Write 1 then write 0 to reset the read address of BLEND1 CLUT - in fifo mode. */ - __IOM uint32_t BLEND0_CLUT_MEM_FORCE_PD : 1;/*!< 1: force power down BLEND CLUT memory. */ - __IOM uint32_t BLEND0_CLUT_MEM_FORCE_PU : 1;/*!< 1: force power up BLEND CLUT memory. */ - __IOM uint32_t BLEND0_CLUT_MEM_CLK_ENA : 1;/*!< 1: Force clock on for BLEND CLUT memory. */ - uint32_t : 24; - } bit; - } CLUT_CONF; - - union { - __IOM uint32_t reg; /*!< Raw status interrupt */ - - struct { - __IOM uint32_t SR_EOF_INT_RAW : 1; /*!< The raw interrupt bit turns to high level when scaling and rotating - engine calculate one frame image. */ - __IOM uint32_t BLEND_EOF_INT_RAW : 1; /*!< The raw interrupt bit turns to high level when blending engine - calculate one frame image. */ - __IOM uint32_t SR_PARAM_CFG_ERR_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when the configured - scaling and rotating coefficient is wrong. User can check - the reasons through register PPA_SR_PARAM_ERR_ST_REG. */ - uint32_t : 29; - } bit; - } INT_RAW; - - union { - __IOM uint32_t reg; /*!< Masked interrupt */ - - struct { - __IM uint32_t SR_EOF_INT_ST : 1; /*!< The raw interrupt status bit for the PPA_SR_EOF_INT interrupt. */ - __IM uint32_t BLEND_EOF_INT_ST : 1; /*!< The raw interrupt status bit for the PPA_BLEND_EOF_INT interrupt. */ - __IM uint32_t SR_PARAM_CFG_ERR_INT_ST : 1;/*!< The raw interrupt status bit for the PPA_SR_RX_YSCAL_ERR_INT - interrupt. */ - uint32_t : 29; - } bit; - } INT_ST; - - union { - __IOM uint32_t reg; /*!< Interrupt enable bits */ - - struct { - __IOM uint32_t SR_EOF_INT_ENA : 1; /*!< The interrupt enable bit for the PPA_SR_EOF_INT interrupt. */ - __IOM uint32_t BLEND_EOF_INT_ENA : 1; /*!< The interrupt enable bit for the PPA_BLEND_EOF_INT interrupt. */ - __IOM uint32_t SR_PARAM_CFG_ERR_INT_ENA : 1;/*!< The interrupt enable bit for the PPA_SR_RX_YSCAL_ERR_INT interrupt. */ - uint32_t : 29; - } bit; - } INT_ENA; - - union { - __IOM uint32_t reg; /*!< Interrupt clear bits */ - - struct { - __OM uint32_t SR_EOF_INT_CLR : 1; /*!< Set this bit to clear the PPA_SR_EOF_INT interrupt. */ - __OM uint32_t BLEND_EOF_INT_CLR : 1; /*!< Set this bit to clear the PPA_BLEND_EOF_INT interrupt. */ - __OM uint32_t SR_PARAM_CFG_ERR_INT_CLR : 1;/*!< Set this bit to clear the PPA_SR_RX_YSCAL_ERR_INT interrupt. */ - uint32_t : 29; - } bit; - } INT_CLR; - - union { - __IOM uint32_t reg; /*!< Scaling and rotating engine color mode register */ - - struct { - __IOM uint32_t SR_RX_CM : 4; /*!< The source image color mode for Scaling and Rotating engine - Rx. 0: ARGB8888. 1: RGB888. 2: RGB565. 8: YUV420. others: - Reserved. */ - __IOM uint32_t SR_TX_CM : 4; /*!< The destination image color mode for Scaling and Rotating engine - Tx. 0: ARGB8888. 1: RGB888. 2: RGB565. 8: YUV420. others: - Reserved. */ - __IOM uint32_t YUV_RX_RANGE : 1; /*!< YUV input range when reg_sr_rx_cm is 4'd8. 0: limit range. 1: - full range */ - __IOM uint32_t YUV_TX_RANGE : 1; /*!< YUV output range when reg_sr_tx_cm is 4'd8. 0: limit range. - 1: full range */ - __IOM uint32_t YUV2RGB_PROTOCAL : 1; /*!< YUV to RGB protocal when reg_sr_rx_cm is 4'd8. 0: BT601. 1: - BT709 */ - __IOM uint32_t RGB2YUV_PROTOCAL : 1; /*!< RGB to YUV protocal when reg_sr_tx_cm is 4'd8. 0: BT601. 1: - BT709 */ - uint32_t : 20; - } bit; - } SR_COLOR_MODE; - - union { - __IOM uint32_t reg; /*!< blending engine color mode register */ - - struct { - __IOM uint32_t BLEND0_RX_CM : 4; /*!< The source image color mode for background plane. 0: ARGB8888. - 1: RGB888. 2: RGB565. 3: Reserved. 4: L8. 5: L4. */ - __IOM uint32_t BLEND1_RX_CM : 4; /*!< The source image color mode for foreground plane. 0: ARGB8888. - 1: RGB888. 2: RGB565. 3: Reserved. 4: L8. 5: L4. 6: A8. - 7: A4. */ - __IOM uint32_t BLEND_TX_CM : 4; /*!< The destination image color mode for output of blender. 0: ARGB8888. - 1: RGB888. 2: RGB565. 3: Reserved.. */ - uint32_t : 20; - } bit; - } BLEND_COLOR_MODE; - - union { - __IOM uint32_t reg; /*!< Scaling and rotating engine byte order register */ - - struct { - __IOM uint32_t SR_RX_BYTE_SWAP_EN : 1; /*!< Set this bit to 1 the data into Rx channel 0 would be swapped - in byte. The Byte0 and Byte1 would be swapped while byte - 2 and byte 3 would be swappped. */ - __IOM uint32_t SR_RX_RGB_SWAP_EN : 1; /*!< Set this bit to 1 the data into Rx channel 0 would be swapped - in rgb. It means rgb would be swap to bgr. */ - __IOM uint32_t SR_MACRO_BK_RO_BYPASS : 1; /*!< Set this bit to 1 to bypass the macro block order function. - This function is used to improve efficient accessing external - memory. */ - uint32_t : 29; - } bit; - } SR_BYTE_ORDER; - - union { - __IOM uint32_t reg; /*!< Blending engine byte order register */ - - struct { - __IOM uint32_t BLEND0_RX_BYTE_SWAP_EN : 1;/*!< Set this bit to 1 the data into Rx channel 0 would be swapped - in byte. The Byte0 and Byte1 would be swapped while byte - 2 and byte 3 would be swappped. */ - __IOM uint32_t BLEND1_RX_BYTE_SWAP_EN : 1;/*!< Set this bit to 1 the data into Rx channel 0 would be swapped - in byte. The Byte0 and Byte1 would be swapped while byte - 2 and byte 3 would be swappped. */ - __IOM uint32_t BLEND0_RX_RGB_SWAP_EN : 1; /*!< Set this bit to 1 the data into Rx channel 0 would be swapped - in rgb. It means rgb would be swap to bgr. */ - __IOM uint32_t BLEND1_RX_RGB_SWAP_EN : 1; /*!< Set this bit to 1 the data into Rx channel 0 would be swapped - in rgb. It means rgb would be swap to bgr. */ - uint32_t : 28; - } bit; - } BLEND_BYTE_ORDER; - __IM uint32_t RESERVED1; - - union { - __IOM uint32_t reg; /*!< Blending engine mode configure register */ - - struct { - __IOM uint32_t BLEND_EN : 1; /*!< Set this bit to enable alpha blending. */ - __IOM uint32_t BLEND_BYPASS : 1; /*!< Set this bit to bypass blender. Then background date would be - output. */ - __IOM uint32_t BLEND_FIX_PIXEL_FILL_EN : 1;/*!< This bit is used to enable fix pixel filling. When this mode - is enable only Tx channel is work and the output pixel - is configured by PPA_OUT_FIX_PIXEL. */ - __OM uint32_t UPDATE : 1; /*!< Set this bit to update the transfer mode. Only the bit is set - the transfer mode is valid. */ - __IOM uint32_t BLEND_RST : 1; /*!< write 1 then write 0 to reset blending engine. */ - uint32_t : 27; - } bit; - } BLEND_TRANS_MODE; - - union { - __IOM uint32_t reg; /*!< Scaling and rotating engine alpha override register */ - - struct { - __IOM uint32_t SR_RX_FIX_ALPHA : 8; /*!< The value would replace the alpha value in received pixel for - Scaling and Rotating engine when PPA_SR_RX_ALPHA_CONF_EN - is enabled. */ - __IOM uint32_t SR_RX_ALPHA_MOD : 2; /*!< Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_SR_FIX_ALPHA. - 2: Original alpha multiply with PPA_SR_FIX_ALPHA/256. */ - __IOM uint32_t SR_RX_ALPHA_INV : 1; /*!< Set this bit to invert the original alpha value. When RX color - mode is RGB565/RGB88. The original alpha value is 255. */ - uint32_t : 21; - } bit; - } SR_FIX_ALPHA; - - union { - __IOM uint32_t reg; /*!< Fix pixel filling mode image size register */ - - struct { - __IOM uint32_t BLEND_HB : 14; /*!< The horizontal width of image block that would be filled in - fix pixel filling mode. The unit is pixel */ - __IOM uint32_t BLEND_VB : 14; /*!< The vertical width of image block that would be filled in fix - pixel filling mode. The unit is pixel */ - uint32_t : 4; - } bit; - } BLEND_TX_SIZE; - - union { - __IOM uint32_t reg; /*!< Blending engine alpha override register */ - - struct { - __IOM uint32_t BLEND0_RX_FIX_ALPHA : 8; /*!< The value would replace the alpha value in received pixel for - background plane of blender when PPA_BLEND0_RX_ALPHA_CONF_EN - is enabled. */ - __IOM uint32_t BLEND1_RX_FIX_ALPHA : 8; /*!< The value would replace the alpha value in received pixel for - foreground plane of blender when PPA_BLEND1_RX_ALPHA_CONF_EN - is enabled. */ - __IOM uint32_t BLEND0_RX_ALPHA_MOD : 2; /*!< Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_SR_FIX_ALPHA. - 2: Original alpha multiply with PPA_SR_FIX_ALPHA/256. */ - __IOM uint32_t BLEND1_RX_ALPHA_MOD : 2; /*!< Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_SR_FIX_ALPHA. - 2: Original alpha multiply with PPA_SR_FIX_ALPHA/256. */ - __IOM uint32_t BLEND0_RX_ALPHA_INV : 1; /*!< Set this bit to invert the original alpha value. When RX color - mode is RGB565/RGB88. The original alpha value is 255. */ - __IOM uint32_t BLEND1_RX_ALPHA_INV : 1; /*!< Set this bit to invert the original alpha value. When RX color - mode is RGB565/RGB88. The original alpha value is 255. */ - uint32_t : 10; - } bit; - } BLEND_FIX_ALPHA; - __IM uint32_t RESERVED2; - - union { - __IOM uint32_t reg; /*!< RGB color register */ - - struct { - __IOM uint32_t BLEND1_RX_B : 8; /*!< blue color for A4/A8 mode. */ - __IOM uint32_t BLEND1_RX_G : 8; /*!< green color for A4/A8 mode. */ - __IOM uint32_t BLEND1_RX_R : 8; /*!< red color for A4/A8 mode. */ - uint32_t : 8; - } bit; - } BLEND_RGB; - - union { - __IOM uint32_t reg; /*!< Blending engine fix pixel register */ - - struct { - __IOM uint32_t BLEND_TX_FIX_PIXEL : 32; /*!< The configure fix pixel in fix pixel filling mode for blender - engine. */ - } bit; - } BLEND_FIX_PIXEL; - - union { - __IOM uint32_t reg; /*!< foreground color key lower threshold */ - - struct { - __IOM uint32_t COLORKEY_FG_B_LOW : 8; /*!< color key lower threshold of foreground b channel */ - __IOM uint32_t COLORKEY_FG_G_LOW : 8; /*!< color key lower threshold of foreground g channel */ - __IOM uint32_t COLORKEY_FG_R_LOW : 8; /*!< color key lower threshold of foreground r channel */ - uint32_t : 8; - } bit; - } CK_FG_LOW; - - union { - __IOM uint32_t reg; /*!< foreground color key higher threshold */ - - struct { - __IOM uint32_t COLORKEY_FG_B_HIGH : 8; /*!< color key higher threshold of foreground b channel */ - __IOM uint32_t COLORKEY_FG_G_HIGH : 8; /*!< color key higher threshold of foreground g channel */ - __IOM uint32_t COLORKEY_FG_R_HIGH : 8; /*!< color key higher threshold of foreground r channel */ - uint32_t : 8; - } bit; - } CK_FG_HIGH; - - union { - __IOM uint32_t reg; /*!< background color key lower threshold */ - - struct { - __IOM uint32_t COLORKEY_BG_B_LOW : 8; /*!< color key lower threshold of background b channel */ - __IOM uint32_t COLORKEY_BG_G_LOW : 8; /*!< color key lower threshold of background g channel */ - __IOM uint32_t COLORKEY_BG_R_LOW : 8; /*!< color key lower threshold of background r channel */ - uint32_t : 8; - } bit; - } CK_BG_LOW; - - union { - __IOM uint32_t reg; /*!< background color key higher threshold */ - - struct { - __IOM uint32_t COLORKEY_BG_B_HIGH : 8; /*!< color key higher threshold of background b channel */ - __IOM uint32_t COLORKEY_BG_G_HIGH : 8; /*!< color key higher threshold of background g channel */ - __IOM uint32_t COLORKEY_BG_R_HIGH : 8; /*!< color key higher threshold of background r channel */ - uint32_t : 8; - } bit; - } CK_BG_HIGH; - - union { - __IOM uint32_t reg; /*!< default value when foreground and background both in color key - range */ - - struct { - __IOM uint32_t COLORKEY_DEFAULT_B : 8; /*!< default B channle value of color key */ - __IOM uint32_t COLORKEY_DEFAULT_G : 8; /*!< default G channle value of color key */ - __IOM uint32_t COLORKEY_DEFAULT_R : 8; /*!< default R channle value of color key */ - __IOM uint32_t COLORKEY_FG_BG_REVERSE : 1;/*!< when pixel in bg ck range but not in fg ck range, 0: the result - is bg, 1: the result is fg */ - uint32_t : 7; - } bit; - } CK_DEFAULT; - - union { - __IOM uint32_t reg; /*!< Scaling and rotating coefficient register */ - - struct { - __IOM uint32_t SR_SCAL_X_INT : 8; /*!< The integrated part of scaling coefficient in X direction. */ - __IOM uint32_t SR_SCAL_X_FRAG : 4; /*!< The fragment part of scaling coefficient in X direction. */ - __IOM uint32_t SR_SCAL_Y_INT : 8; /*!< The integrated part of scaling coefficient in Y direction. */ - __IOM uint32_t SR_SCAL_Y_FRAG : 4; /*!< The fragment part of scaling coefficient in Y direction. */ - __IOM uint32_t SR_ROTATE_ANGLE : 2; /*!< The rotate angle. 0: 0 degree. 1: 90 degree. 2: 180 degree. - 3: 270 degree. */ - __IOM uint32_t SCAL_ROTATE_RST : 1; /*!< Write 1 then write 0 to this bit to reset scaling and rotating - engine. */ - __OM uint32_t SCAL_ROTATE_START : 1; /*!< Write 1 to enable scaling and rotating engine after parameter - is configured. */ - __IOM uint32_t SR_MIRROR_X : 1; /*!< Image mirror in X direction. 0: disable, 1: enable */ - __IOM uint32_t SR_MIRROR_Y : 1; /*!< Image mirror in Y direction. 0: disable, 1: enable */ - uint32_t : 2; - } bit; - } SR_SCAL_ROTATE; - - union { - __IOM uint32_t reg; /*!< SR memory power done register */ - - struct { - __IOM uint32_t SR_MEM_CLK_ENA : 1; /*!< Set this bit to force clock enable of scaling and rotating engine's - data memory. */ - __IOM uint32_t SR_MEM_FORCE_PD : 1; /*!< Set this bit to force power down scaling and rotating engine's - data memory. */ - __IOM uint32_t SR_MEM_FORCE_PU : 1; /*!< Set this bit to force power up scaling and rotating engine's - data memory. */ - uint32_t : 29; - } bit; - } SR_MEM_PD; - - union { - __IOM uint32_t reg; /*!< Register clock enable register */ - - struct { - __IOM uint32_t CLK_EN : 1; /*!< PPA register clock gate enable signal. */ - uint32_t : 31; - } bit; - } REG_CONF; - - union { - __IOM uint32_t reg; /*!< BLEND CLUT write counter register */ - - struct { - __IM uint32_t BLEND0_CLUT_CNT : 9; /*!< The write data counter of BLEND0 CLUT in fifo mode. */ - __IM uint32_t BLEND1_CLUT_CNT : 9; /*!< The write data counter of BLEND1 CLUT in fifo mode. */ - uint32_t : 14; - } bit; - } CLUT_CNT; - - union { - __IOM uint32_t reg; /*!< Blending engine status register */ - - struct { - __IM uint32_t BLEND_SIZE_DIFF_ST : 1; /*!< 1: indicate the size of two image is different. */ - uint32_t : 31; - } bit; - } BLEND_ST; - - union { - __IOM uint32_t reg; /*!< Scaling and rotating coefficient error register */ - - struct { - __IM uint32_t TX_DSCR_VB_ERR_ST : 1; /*!< The error is that the scaled VB plus the offset of Y coordinate - in 2DDMA receive descriptor is larger than VA in 2DDMA - receive descriptor. */ - __IM uint32_t TX_DSCR_HB_ERR_ST : 1; /*!< The error is that the scaled HB plus the offset of X coordinate - in 2DDMA receive descriptor is larger than HA in 2DDMA - receive descriptor. */ - __IM uint32_t Y_RX_SCAL_EQUAL_0_ERR_ST : 1;/*!< The error is that the PPA_SR_SCAL_Y_INT and PPA_SR_CAL_Y_FRAG - both are 0. */ - __IM uint32_t RX_DSCR_VB_ERR_ST : 1; /*!< The error is that VB in 2DDMA receive descriptor plus the offset - of Y coordinate in 2DDMA transmit descriptor is larger - than VA in 2DDMA transmit descriptor */ - __IM uint32_t YDST_LEN_TOO_SAMLL_ERR_ST : 1;/*!< The error is that the scaled image width is 0. For example. - when source width is 14. scaled value is 1/16. and no rotate - operation. then scaled width would be 0 as the result would - be floored. */ - __IM uint32_t YDST_LEN_TOO_LARGE_ERR_ST : 1;/*!< The error is that the scaled width is larger than (2^13 - 1). */ - __IM uint32_t X_RX_SCAL_EQUAL_0_ERR_ST : 1;/*!< The error is that the scaled image height is 0. */ - __IM uint32_t RX_DSCR_HB_ERR_ST : 1; /*!< The error is that the HB in 2DDMA transmit descriptor plus the - offset of X coordinate in 2DDMA transmit descriptor is - larger than HA in 2DDMA transmit descriptor. */ - __IM uint32_t XDST_LEN_TOO_SAMLL_ERR_ST : 1;/*!< The error is that the scaled image height is 0. For example. - when source height is 14. scaled value is 1/16. and no - rotate operation. then scaled height would be 0 as the - result would be floored. */ - __IM uint32_t XDST_LEN_TOO_LARGE_ERR_ST : 1;/*!< The error is that the scaled image height is larger than (2^13 - - 1). */ - __IM uint32_t X_YUV420_RX_SCALE_ERR_ST : 1;/*!< The error is that the ha/hb/x param in dma2d descriptor is an - odd num when enable yuv420 rx */ - __IM uint32_t Y_YUV420_RX_SCALE_ERR_ST : 1;/*!< The error is that the va/vb/y param in dma2d descriptor is an - odd num when enable yuv420 rx */ - __IM uint32_t X_YUV420_TX_SCALE_ERR_ST : 1;/*!< The error is that the ha/hb/x param in dma2d descriptor is an - odd num when enable yuv420 tx */ - __IM uint32_t Y_YUV420_TX_SCALE_ERR_ST : 1;/*!< The error is that the va/vb/y param in dma2d descriptor is an - odd num when enable yuv420 tx */ - uint32_t : 18; - } bit; - } SR_PARAM_ERR_ST; - - union { - __IOM uint32_t reg; /*!< SR FSM register */ - - struct { - __IM uint32_t SR_RX_DSCR_SAMPLE_STATE : 2;/*!< Reserved. */ - __IM uint32_t SR_RX_SCAN_STATE : 2; /*!< Reserved. */ - __IM uint32_t SR_TX_DSCR_SAMPLE_STATE : 2;/*!< Reserved. */ - __IM uint32_t SR_TX_SCAN_STATE : 3; /*!< Reserved. */ - uint32_t : 23; - } bit; - } SR_STATUS; - - union { - __IOM uint32_t reg; /*!< Reserved. */ - - struct { - __IOM uint32_t RND_ECO_LOW : 32; /*!< Reserved. */ - } bit; - } ECO_LOW; - - union { - __IOM uint32_t reg; /*!< Reserved. */ - - struct { - __IOM uint32_t RND_ECO_HIGH : 32; /*!< Reserved. */ - } bit; - } ECO_HIGH; - - union { - __IOM uint32_t reg; /*!< Reserved. */ - - struct { - __IM uint32_t RDN_RESULT : 1; /*!< Reserved. */ - __IOM uint32_t RDN_ENA : 1; /*!< Reserved. */ - uint32_t : 30; - } bit; - } ECO_CELL_CTRL; - - union { - __IOM uint32_t reg; /*!< PPA SRAM Control Register */ - - struct { - __IOM uint32_t MEM_AUX_CTRL : 14; /*!< Control signals */ - uint32_t : 18; - } bit; - } SRAM_CTRL; - __IM uint32_t RESERVED3[28]; - - union { - __IOM uint32_t reg; /*!< PPA Version register */ - - struct { - __IOM uint32_t DATE : 32; /*!< register version. */ - } bit; - } DATE; -} PPA_Type; /*!< Size = 260 (0x104) */ - - - -/* =========================================================================================================================== */ -/* ================ PVT ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief PVT Peripheral (PVT) - */ - -typedef struct { /*!< PVT Structure */ - - union { - __IOM uint32_t reg; /*!< select valid pvt channel */ - - struct { - __IOM uint32_t PUMP_BITMAP_HIGH0 : 32; /*!< select valid high channel0 */ - } bit; - } PMUP_BITMAP_HIGH0; - - union { - __IOM uint32_t reg; /*!< select valid pvt channel */ - - struct { - __IOM uint32_t PUMP_BITMAP_HIGH1 : 32; /*!< select valid high channel1 */ - } bit; - } PMUP_BITMAP_HIGH1; - - union { - __IOM uint32_t reg; /*!< select valid pvt channel */ - - struct { - __IOM uint32_t PUMP_BITMAP_HIGH2 : 32; /*!< select valid high channel2 */ - } bit; - } PMUP_BITMAP_HIGH2; - - union { - __IOM uint32_t reg; /*!< select valid pvt channel */ - - struct { - __IOM uint32_t PUMP_BITMAP_HIGH3 : 32; /*!< select valid high channel3 */ - } bit; - } PMUP_BITMAP_HIGH3; - - union { - __IOM uint32_t reg; /*!< select valid pvt channel */ - - struct { - __IOM uint32_t PUMP_BITMAP_HIGH4 : 32; /*!< select valid high channel4 */ - } bit; - } PMUP_BITMAP_HIGH4; - - union { - __IOM uint32_t reg; /*!< select valid pvt channel */ - - struct { - __IOM uint32_t PUMP_BITMAP_LOW0 : 32; /*!< select valid low channel0 */ - } bit; - } PMUP_BITMAP_LOW0; - - union { - __IOM uint32_t reg; /*!< select valid pvt channel */ - - struct { - __IOM uint32_t PUMP_BITMAP_LOW1 : 32; /*!< select valid low channel1 */ - } bit; - } PMUP_BITMAP_LOW1; - - union { - __IOM uint32_t reg; /*!< select valid pvt channel */ - - struct { - __IOM uint32_t PUMP_BITMAP_LOW2 : 32; /*!< select valid low channel2 */ - } bit; - } PMUP_BITMAP_LOW2; - - union { - __IOM uint32_t reg; /*!< select valid pvt channel */ - - struct { - __IOM uint32_t PUMP_BITMAP_LOW3 : 32; /*!< select valid low channel3 */ - } bit; - } PMUP_BITMAP_LOW3; - - union { - __IOM uint32_t reg; /*!< select valid pvt channel */ - - struct { - __IOM uint32_t PUMP_BITMAP_LOW4 : 32; /*!< select valid low channel4 */ - } bit; - } PMUP_BITMAP_LOW4; - - union { - __IOM uint32_t reg; /*!< configure pump drv */ - - struct { - uint32_t : 9; - __IOM uint32_t PUMP_EN : 1; /*!< configure pvt charge xpd */ - __IOM uint32_t CLK_EN : 1; /*!< force register clken */ - __IOM uint32_t PUMP_DRV4 : 4; /*!< configure cmd4 drv */ - __IOM uint32_t PUMP_DRV3 : 4; /*!< configure cmd3 drv */ - __IOM uint32_t PUMP_DRV2 : 4; /*!< configure cmd2 drv */ - __IOM uint32_t PUMP_DRV1 : 4; /*!< configure cmd1 drv */ - __IOM uint32_t PUMP_DRV0 : 4; /*!< configure cmd0 drv */ - uint32_t : 1; - } bit; - } PMUP_DRV_CFG; - - union { - __IOM uint32_t reg; /*!< configure the code of valid pump channel code */ - - struct { - uint32_t : 7; - __IOM uint32_t PUMP_CHANNEL_CODE4 : 5; /*!< configure cmd4 code */ - __IOM uint32_t PUMP_CHANNEL_CODE3 : 5; /*!< configure cmd3 code */ - __IOM uint32_t PUMP_CHANNEL_CODE2 : 5; /*!< configure cmd2 code */ - __IOM uint32_t PUMP_CHANNEL_CODE1 : 5; /*!< configure cmd1 code */ - __IOM uint32_t PUMP_CHANNEL_CODE0 : 5; /*!< configure cmd0 code */ - } bit; - } PMUP_CHANNEL_CFG; - - union { - __IOM uint32_t reg; /*!< configure pvt clk */ - - struct { - __IOM uint32_t PUMP_CLK_DIV_NUM : 8; /*!< needs field desc */ - __IOM uint32_t MONITOR_CLK_PVT_EN : 1; /*!< needs field desc */ - uint32_t : 22; - __IOM uint32_t CLK_SEL : 1; /*!< select pvt clk */ - } bit; - } CLK_CFG; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - uint32_t : 4; - __IOM uint32_t DBIAS_CHANNEL3_SEL : 7; /*!< needs field desc */ - __IOM uint32_t DBIAS_CHANNEL2_SEL : 7; /*!< needs field desc */ - __IOM uint32_t DBIAS_CHANNEL1_SEL : 7; /*!< needs field desc */ - __IOM uint32_t DBIAS_CHANNEL0_SEL : 7; /*!< needs field desc */ - } bit; - } DBIAS_CHANNEL_SEL0; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - uint32_t : 25; - __IOM uint32_t DBIAS_CHANNEL4_SEL : 7; /*!< needs field desc */ - } bit; - } DBIAS_CHANNEL_SEL1; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t DBIAS_CHANNEL0_CFG : 17; /*!< needs field desc */ - uint32_t : 15; - } bit; - } DBIAS_CHANNEL0_SEL; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t DBIAS_CHANNEL1_CFG : 17; /*!< needs field desc */ - uint32_t : 15; - } bit; - } DBIAS_CHANNEL1_SEL; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t DBIAS_CHANNEL2_CFG : 17; /*!< needs field desc */ - uint32_t : 15; - } bit; - } DBIAS_CHANNEL2_SEL; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t DBIAS_CHANNEL3_CFG : 17; /*!< needs field desc */ - uint32_t : 15; - } bit; - } DBIAS_CHANNEL3_SEL; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t DBIAS_CHANNEL4_CFG : 17; /*!< needs field desc */ - uint32_t : 15; - } bit; - } DBIAS_CHANNEL4_SEL; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t DBIAS_CMD0 : 17; /*!< needs field desc */ - uint32_t : 15; - } bit; - } DBIAS_CMD0; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t DBIAS_CMD1 : 17; /*!< needs field desc */ - uint32_t : 15; - } bit; - } DBIAS_CMD1; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t DBIAS_CMD2 : 17; /*!< needs field desc */ - uint32_t : 15; - } bit; - } DBIAS_CMD2; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t DBIAS_CMD3 : 17; /*!< needs field desc */ - uint32_t : 15; - } bit; - } DBIAS_CMD3; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t DBIAS_CMD4 : 17; /*!< needs field desc */ - uint32_t : 15; - } bit; - } DBIAS_CMD4; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - uint32_t : 15; - __IOM uint32_t TIMER_TARGET : 16; /*!< needs field desc */ - __IOM uint32_t TIMER_EN : 1; /*!< needs field desc */ - } bit; - } DBIAS_TIMER; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EN_VT0_PD_SITE0_UNIT0 : 1;/*!< needs field desc */ - __OM uint32_t TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT0 : 1;/*!< needs field desc */ - __IOM uint32_t DELAY_LIMIT_VT0_PD_SITE0_UNIT0 : 8;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_NUM_O_VT0_PD_SITE0_UNIT0 : 8;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_VT0_PD_SITE0_UNIT0 : 1;/*!< needs field desc */ - } bit; - } COMB_PD_SITE0_UNIT0_VT0_CONF1; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EN_VT0_PD_SITE0_UNIT1 : 1;/*!< needs field desc */ - __OM uint32_t TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT1 : 1;/*!< needs field desc */ - __IOM uint32_t DELAY_LIMIT_VT0_PD_SITE0_UNIT1 : 8;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_NUM_O_VT0_PD_SITE0_UNIT1 : 8;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_VT0_PD_SITE0_UNIT1 : 1;/*!< needs field desc */ - } bit; - } COMB_PD_SITE0_UNIT1_VT0_CONF1; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EN_VT0_PD_SITE0_UNIT2 : 1;/*!< needs field desc */ - __OM uint32_t TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT2 : 1;/*!< needs field desc */ - __IOM uint32_t DELAY_LIMIT_VT0_PD_SITE0_UNIT2 : 8;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_NUM_O_VT0_PD_SITE0_UNIT2 : 8;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_VT0_PD_SITE0_UNIT2 : 1;/*!< needs field desc */ - } bit; - } COMB_PD_SITE0_UNIT2_VT0_CONF1; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EN_VT0_PD_SITE0_UNIT3 : 1;/*!< needs field desc */ - __OM uint32_t TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT3 : 1;/*!< needs field desc */ - __IOM uint32_t DELAY_LIMIT_VT0_PD_SITE0_UNIT3 : 8;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_NUM_O_VT0_PD_SITE0_UNIT3 : 8;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_VT0_PD_SITE0_UNIT3 : 1;/*!< needs field desc */ - } bit; - } COMB_PD_SITE0_UNIT3_VT0_CONF1; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EN_VT1_PD_SITE0_UNIT0 : 1;/*!< needs field desc */ - __OM uint32_t TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT0 : 1;/*!< needs field desc */ - __IOM uint32_t DELAY_LIMIT_VT1_PD_SITE0_UNIT0 : 8;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_NUM_O_VT1_PD_SITE0_UNIT0 : 8;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_VT1_PD_SITE0_UNIT0 : 1;/*!< needs field desc */ - } bit; - } COMB_PD_SITE0_UNIT0_VT1_CONF1; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EN_VT1_PD_SITE0_UNIT1 : 1;/*!< needs field desc */ - __OM uint32_t TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT1 : 1;/*!< needs field desc */ - __IOM uint32_t DELAY_LIMIT_VT1_PD_SITE0_UNIT1 : 8;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_NUM_O_VT1_PD_SITE0_UNIT1 : 8;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_VT1_PD_SITE0_UNIT1 : 1;/*!< needs field desc */ - } bit; - } COMB_PD_SITE0_UNIT1_VT1_CONF1; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EN_VT1_PD_SITE0_UNIT2 : 1;/*!< needs field desc */ - __OM uint32_t TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT2 : 1;/*!< needs field desc */ - __IOM uint32_t DELAY_LIMIT_VT1_PD_SITE0_UNIT2 : 8;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_NUM_O_VT1_PD_SITE0_UNIT2 : 8;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_VT1_PD_SITE0_UNIT2 : 1;/*!< needs field desc */ - } bit; - } COMB_PD_SITE0_UNIT2_VT1_CONF1; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EN_VT1_PD_SITE0_UNIT3 : 1;/*!< needs field desc */ - __OM uint32_t TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT3 : 1;/*!< needs field desc */ - __IOM uint32_t DELAY_LIMIT_VT1_PD_SITE0_UNIT3 : 8;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_NUM_O_VT1_PD_SITE0_UNIT3 : 8;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_VT1_PD_SITE0_UNIT3 : 1;/*!< needs field desc */ - } bit; - } COMB_PD_SITE0_UNIT3_VT1_CONF1; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EN_VT2_PD_SITE0_UNIT0 : 1;/*!< needs field desc */ - __OM uint32_t TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT0 : 1;/*!< needs field desc */ - __IOM uint32_t DELAY_LIMIT_VT2_PD_SITE0_UNIT0 : 8;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_NUM_O_VT2_PD_SITE0_UNIT0 : 8;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_VT2_PD_SITE0_UNIT0 : 1;/*!< needs field desc */ - } bit; - } COMB_PD_SITE0_UNIT0_VT2_CONF1; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EN_VT2_PD_SITE0_UNIT1 : 1;/*!< needs field desc */ - __OM uint32_t TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT1 : 1;/*!< needs field desc */ - __IOM uint32_t DELAY_LIMIT_VT2_PD_SITE0_UNIT1 : 8;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_NUM_O_VT2_PD_SITE0_UNIT1 : 8;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_VT2_PD_SITE0_UNIT1 : 1;/*!< needs field desc */ - } bit; - } COMB_PD_SITE0_UNIT1_VT2_CONF1; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EN_VT2_PD_SITE0_UNIT2 : 1;/*!< needs field desc */ - __OM uint32_t TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT2 : 1;/*!< needs field desc */ - __IOM uint32_t DELAY_LIMIT_VT2_PD_SITE0_UNIT2 : 8;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_NUM_O_VT2_PD_SITE0_UNIT2 : 8;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_VT2_PD_SITE0_UNIT2 : 1;/*!< needs field desc */ - } bit; - } COMB_PD_SITE0_UNIT2_VT2_CONF1; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EN_VT2_PD_SITE0_UNIT3 : 1;/*!< needs field desc */ - __OM uint32_t TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT3 : 1;/*!< needs field desc */ - __IOM uint32_t DELAY_LIMIT_VT2_PD_SITE0_UNIT3 : 8;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_NUM_O_VT2_PD_SITE0_UNIT3 : 8;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_VT2_PD_SITE0_UNIT3 : 1;/*!< needs field desc */ - } bit; - } COMB_PD_SITE0_UNIT3_VT2_CONF1; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EN_VT0_PD_SITE1_UNIT0 : 1;/*!< needs field desc */ - __OM uint32_t TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT0 : 1;/*!< needs field desc */ - __IOM uint32_t DELAY_LIMIT_VT0_PD_SITE1_UNIT0 : 8;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_NUM_O_VT0_PD_SITE1_UNIT0 : 8;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_VT0_PD_SITE1_UNIT0 : 1;/*!< needs field desc */ - } bit; - } COMB_PD_SITE1_UNIT0_VT0_CONF1; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EN_VT0_PD_SITE1_UNIT1 : 1;/*!< needs field desc */ - __OM uint32_t TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT1 : 1;/*!< needs field desc */ - __IOM uint32_t DELAY_LIMIT_VT0_PD_SITE1_UNIT1 : 8;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_NUM_O_VT0_PD_SITE1_UNIT1 : 8;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_VT0_PD_SITE1_UNIT1 : 1;/*!< needs field desc */ - } bit; - } COMB_PD_SITE1_UNIT1_VT0_CONF1; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EN_VT0_PD_SITE1_UNIT2 : 1;/*!< needs field desc */ - __OM uint32_t TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT2 : 1;/*!< needs field desc */ - __IOM uint32_t DELAY_LIMIT_VT0_PD_SITE1_UNIT2 : 8;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_NUM_O_VT0_PD_SITE1_UNIT2 : 8;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_VT0_PD_SITE1_UNIT2 : 1;/*!< needs field desc */ - } bit; - } COMB_PD_SITE1_UNIT2_VT0_CONF1; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EN_VT0_PD_SITE1_UNIT3 : 1;/*!< needs field desc */ - __OM uint32_t TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT3 : 1;/*!< needs field desc */ - __IOM uint32_t DELAY_LIMIT_VT0_PD_SITE1_UNIT3 : 8;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_NUM_O_VT0_PD_SITE1_UNIT3 : 8;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_VT0_PD_SITE1_UNIT3 : 1;/*!< needs field desc */ - } bit; - } COMB_PD_SITE1_UNIT3_VT0_CONF1; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EN_VT1_PD_SITE1_UNIT0 : 1;/*!< needs field desc */ - __OM uint32_t TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT0 : 1;/*!< needs field desc */ - __IOM uint32_t DELAY_LIMIT_VT1_PD_SITE1_UNIT0 : 8;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_NUM_O_VT1_PD_SITE1_UNIT0 : 8;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_VT1_PD_SITE1_UNIT0 : 1;/*!< needs field desc */ - } bit; - } COMB_PD_SITE1_UNIT0_VT1_CONF1; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EN_VT1_PD_SITE1_UNIT1 : 1;/*!< needs field desc */ - __OM uint32_t TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT1 : 1;/*!< needs field desc */ - __IOM uint32_t DELAY_LIMIT_VT1_PD_SITE1_UNIT1 : 8;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_NUM_O_VT1_PD_SITE1_UNIT1 : 8;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_VT1_PD_SITE1_UNIT1 : 1;/*!< needs field desc */ - } bit; - } COMB_PD_SITE1_UNIT1_VT1_CONF1; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EN_VT1_PD_SITE1_UNIT2 : 1;/*!< needs field desc */ - __OM uint32_t TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT2 : 1;/*!< needs field desc */ - __IOM uint32_t DELAY_LIMIT_VT1_PD_SITE1_UNIT2 : 8;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_NUM_O_VT1_PD_SITE1_UNIT2 : 8;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_VT1_PD_SITE1_UNIT2 : 1;/*!< needs field desc */ - } bit; - } COMB_PD_SITE1_UNIT2_VT1_CONF1; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EN_VT1_PD_SITE1_UNIT3 : 1;/*!< needs field desc */ - __OM uint32_t TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT3 : 1;/*!< needs field desc */ - __IOM uint32_t DELAY_LIMIT_VT1_PD_SITE1_UNIT3 : 8;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_NUM_O_VT1_PD_SITE1_UNIT3 : 8;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_VT1_PD_SITE1_UNIT3 : 1;/*!< needs field desc */ - } bit; - } COMB_PD_SITE1_UNIT3_VT1_CONF1; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EN_VT2_PD_SITE1_UNIT0 : 1;/*!< needs field desc */ - __OM uint32_t TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT0 : 1;/*!< needs field desc */ - __IOM uint32_t DELAY_LIMIT_VT2_PD_SITE1_UNIT0 : 8;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_NUM_O_VT2_PD_SITE1_UNIT0 : 8;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_VT2_PD_SITE1_UNIT0 : 1;/*!< needs field desc */ - } bit; - } COMB_PD_SITE1_UNIT0_VT2_CONF1; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EN_VT2_PD_SITE1_UNIT1 : 1;/*!< needs field desc */ - __OM uint32_t TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT1 : 1;/*!< needs field desc */ - __IOM uint32_t DELAY_LIMIT_VT2_PD_SITE1_UNIT1 : 8;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_NUM_O_VT2_PD_SITE1_UNIT1 : 8;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_VT2_PD_SITE1_UNIT1 : 1;/*!< needs field desc */ - } bit; - } COMB_PD_SITE1_UNIT1_VT2_CONF1; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EN_VT2_PD_SITE1_UNIT2 : 1;/*!< needs field desc */ - __OM uint32_t TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT2 : 1;/*!< needs field desc */ - __IOM uint32_t DELAY_LIMIT_VT2_PD_SITE1_UNIT2 : 8;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_NUM_O_VT2_PD_SITE1_UNIT2 : 8;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_VT2_PD_SITE1_UNIT2 : 1;/*!< needs field desc */ - } bit; - } COMB_PD_SITE1_UNIT2_VT2_CONF1; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EN_VT2_PD_SITE1_UNIT3 : 1;/*!< needs field desc */ - __OM uint32_t TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT3 : 1;/*!< needs field desc */ - __IOM uint32_t DELAY_LIMIT_VT2_PD_SITE1_UNIT3 : 8;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_NUM_O_VT2_PD_SITE1_UNIT3 : 8;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_VT2_PD_SITE1_UNIT3 : 1;/*!< needs field desc */ - } bit; - } COMB_PD_SITE1_UNIT3_VT2_CONF1; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EN_VT0_PD_SITE2_UNIT0 : 1;/*!< needs field desc */ - __OM uint32_t TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT0 : 1;/*!< needs field desc */ - __IOM uint32_t DELAY_LIMIT_VT0_PD_SITE2_UNIT0 : 8;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_NUM_O_VT0_PD_SITE2_UNIT0 : 8;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_VT0_PD_SITE2_UNIT0 : 1;/*!< needs field desc */ - } bit; - } COMB_PD_SITE2_UNIT0_VT0_CONF1; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EN_VT0_PD_SITE2_UNIT1 : 1;/*!< needs field desc */ - __OM uint32_t TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT1 : 1;/*!< needs field desc */ - __IOM uint32_t DELAY_LIMIT_VT0_PD_SITE2_UNIT1 : 8;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_NUM_O_VT0_PD_SITE2_UNIT1 : 8;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_VT0_PD_SITE2_UNIT1 : 1;/*!< needs field desc */ - } bit; - } COMB_PD_SITE2_UNIT1_VT0_CONF1; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EN_VT0_PD_SITE2_UNIT2 : 1;/*!< needs field desc */ - __OM uint32_t TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT2 : 1;/*!< needs field desc */ - __IOM uint32_t DELAY_LIMIT_VT0_PD_SITE2_UNIT2 : 8;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_NUM_O_VT0_PD_SITE2_UNIT2 : 8;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_VT0_PD_SITE2_UNIT2 : 1;/*!< needs field desc */ - } bit; - } COMB_PD_SITE2_UNIT2_VT0_CONF1; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EN_VT0_PD_SITE2_UNIT3 : 1;/*!< needs field desc */ - __OM uint32_t TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT3 : 1;/*!< needs field desc */ - __IOM uint32_t DELAY_LIMIT_VT0_PD_SITE2_UNIT3 : 8;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_NUM_O_VT0_PD_SITE2_UNIT3 : 8;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_VT0_PD_SITE2_UNIT3 : 1;/*!< needs field desc */ - } bit; - } COMB_PD_SITE2_UNIT3_VT0_CONF1; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EN_VT1_PD_SITE2_UNIT0 : 1;/*!< needs field desc */ - __OM uint32_t TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT0 : 1;/*!< needs field desc */ - __IOM uint32_t DELAY_LIMIT_VT1_PD_SITE2_UNIT0 : 8;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_NUM_O_VT1_PD_SITE2_UNIT0 : 8;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_VT1_PD_SITE2_UNIT0 : 1;/*!< needs field desc */ - } bit; - } COMB_PD_SITE2_UNIT0_VT1_CONF1; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EN_VT1_PD_SITE2_UNIT1 : 1;/*!< needs field desc */ - __OM uint32_t TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT1 : 1;/*!< needs field desc */ - __IOM uint32_t DELAY_LIMIT_VT1_PD_SITE2_UNIT1 : 8;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_NUM_O_VT1_PD_SITE2_UNIT1 : 8;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_VT1_PD_SITE2_UNIT1 : 1;/*!< needs field desc */ - } bit; - } COMB_PD_SITE2_UNIT1_VT1_CONF1; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EN_VT1_PD_SITE2_UNIT2 : 1;/*!< needs field desc */ - __OM uint32_t TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT2 : 1;/*!< needs field desc */ - __IOM uint32_t DELAY_LIMIT_VT1_PD_SITE2_UNIT2 : 8;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_NUM_O_VT1_PD_SITE2_UNIT2 : 8;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_VT1_PD_SITE2_UNIT2 : 1;/*!< needs field desc */ - } bit; - } COMB_PD_SITE2_UNIT2_VT1_CONF1; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EN_VT1_PD_SITE2_UNIT3 : 1;/*!< needs field desc */ - __OM uint32_t TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT3 : 1;/*!< needs field desc */ - __IOM uint32_t DELAY_LIMIT_VT1_PD_SITE2_UNIT3 : 8;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_NUM_O_VT1_PD_SITE2_UNIT3 : 8;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_VT1_PD_SITE2_UNIT3 : 1;/*!< needs field desc */ - } bit; - } COMB_PD_SITE2_UNIT3_VT1_CONF1; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EN_VT2_PD_SITE2_UNIT0 : 1;/*!< needs field desc */ - __OM uint32_t TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT0 : 1;/*!< needs field desc */ - __IOM uint32_t DELAY_LIMIT_VT2_PD_SITE2_UNIT0 : 8;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_NUM_O_VT2_PD_SITE2_UNIT0 : 8;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_VT2_PD_SITE2_UNIT0 : 1;/*!< needs field desc */ - } bit; - } COMB_PD_SITE2_UNIT0_VT2_CONF1; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EN_VT2_PD_SITE2_UNIT1 : 1;/*!< needs field desc */ - __OM uint32_t TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT1 : 1;/*!< needs field desc */ - __IOM uint32_t DELAY_LIMIT_VT2_PD_SITE2_UNIT1 : 8;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_NUM_O_VT2_PD_SITE2_UNIT1 : 8;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_VT2_PD_SITE2_UNIT1 : 1;/*!< needs field desc */ - } bit; - } COMB_PD_SITE2_UNIT1_VT2_CONF1; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EN_VT2_PD_SITE2_UNIT2 : 1;/*!< needs field desc */ - __OM uint32_t TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT2 : 1;/*!< needs field desc */ - __IOM uint32_t DELAY_LIMIT_VT2_PD_SITE2_UNIT2 : 8;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_NUM_O_VT2_PD_SITE2_UNIT2 : 8;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_VT2_PD_SITE2_UNIT2 : 1;/*!< needs field desc */ - } bit; - } COMB_PD_SITE2_UNIT2_VT2_CONF1; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EN_VT2_PD_SITE2_UNIT3 : 1;/*!< needs field desc */ - __OM uint32_t TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT3 : 1;/*!< needs field desc */ - __IOM uint32_t DELAY_LIMIT_VT2_PD_SITE2_UNIT3 : 8;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_NUM_O_VT2_PD_SITE2_UNIT3 : 8;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_VT2_PD_SITE2_UNIT3 : 1;/*!< needs field desc */ - } bit; - } COMB_PD_SITE2_UNIT3_VT2_CONF1; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EN_VT0_PD_SITE3_UNIT0 : 1;/*!< needs field desc */ - __OM uint32_t TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT0 : 1;/*!< needs field desc */ - __IOM uint32_t DELAY_LIMIT_VT0_PD_SITE3_UNIT0 : 8;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_NUM_O_VT0_PD_SITE3_UNIT0 : 8;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_VT0_PD_SITE3_UNIT0 : 1;/*!< needs field desc */ - } bit; - } COMB_PD_SITE3_UNIT0_VT0_CONF1; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EN_VT0_PD_SITE3_UNIT1 : 1;/*!< needs field desc */ - __OM uint32_t TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT1 : 1;/*!< needs field desc */ - __IOM uint32_t DELAY_LIMIT_VT0_PD_SITE3_UNIT1 : 8;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_NUM_O_VT0_PD_SITE3_UNIT1 : 8;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_VT0_PD_SITE3_UNIT1 : 1;/*!< needs field desc */ - } bit; - } COMB_PD_SITE3_UNIT1_VT0_CONF1; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EN_VT0_PD_SITE3_UNIT2 : 1;/*!< needs field desc */ - __OM uint32_t TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT2 : 1;/*!< needs field desc */ - __IOM uint32_t DELAY_LIMIT_VT0_PD_SITE3_UNIT2 : 8;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_NUM_O_VT0_PD_SITE3_UNIT2 : 8;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_VT0_PD_SITE3_UNIT2 : 1;/*!< needs field desc */ - } bit; - } COMB_PD_SITE3_UNIT2_VT0_CONF1; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EN_VT0_PD_SITE3_UNIT3 : 1;/*!< needs field desc */ - __OM uint32_t TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT3 : 1;/*!< needs field desc */ - __IOM uint32_t DELAY_LIMIT_VT0_PD_SITE3_UNIT3 : 8;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_NUM_O_VT0_PD_SITE3_UNIT3 : 8;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_VT0_PD_SITE3_UNIT3 : 1;/*!< needs field desc */ - } bit; - } COMB_PD_SITE3_UNIT3_VT0_CONF1; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EN_VT1_PD_SITE3_UNIT0 : 1;/*!< needs field desc */ - __OM uint32_t TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT0 : 1;/*!< needs field desc */ - __IOM uint32_t DELAY_LIMIT_VT1_PD_SITE3_UNIT0 : 8;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_NUM_O_VT1_PD_SITE3_UNIT0 : 8;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_VT1_PD_SITE3_UNIT0 : 1;/*!< needs field desc */ - } bit; - } COMB_PD_SITE3_UNIT0_VT1_CONF1; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EN_VT1_PD_SITE3_UNIT1 : 1;/*!< needs field desc */ - __OM uint32_t TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT1 : 1;/*!< needs field desc */ - __IOM uint32_t DELAY_LIMIT_VT1_PD_SITE3_UNIT1 : 8;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_NUM_O_VT1_PD_SITE3_UNIT1 : 8;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_VT1_PD_SITE3_UNIT1 : 1;/*!< needs field desc */ - } bit; - } COMB_PD_SITE3_UNIT1_VT1_CONF1; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EN_VT1_PD_SITE3_UNIT2 : 1;/*!< needs field desc */ - __OM uint32_t TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT2 : 1;/*!< needs field desc */ - __IOM uint32_t DELAY_LIMIT_VT1_PD_SITE3_UNIT2 : 8;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_NUM_O_VT1_PD_SITE3_UNIT2 : 8;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_VT1_PD_SITE3_UNIT2 : 1;/*!< needs field desc */ - } bit; - } COMB_PD_SITE3_UNIT2_VT1_CONF1; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EN_VT1_PD_SITE3_UNIT3 : 1;/*!< needs field desc */ - __OM uint32_t TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT3 : 1;/*!< needs field desc */ - __IOM uint32_t DELAY_LIMIT_VT1_PD_SITE3_UNIT3 : 8;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_NUM_O_VT1_PD_SITE3_UNIT3 : 8;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_VT1_PD_SITE3_UNIT3 : 1;/*!< needs field desc */ - } bit; - } COMB_PD_SITE3_UNIT3_VT1_CONF1; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EN_VT2_PD_SITE3_UNIT0 : 1;/*!< needs field desc */ - __OM uint32_t TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT0 : 1;/*!< needs field desc */ - __IOM uint32_t DELAY_LIMIT_VT2_PD_SITE3_UNIT0 : 8;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_NUM_O_VT2_PD_SITE3_UNIT0 : 8;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_VT2_PD_SITE3_UNIT0 : 1;/*!< needs field desc */ - } bit; - } COMB_PD_SITE3_UNIT0_VT2_CONF1; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EN_VT2_PD_SITE3_UNIT1 : 1;/*!< needs field desc */ - __OM uint32_t TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT1 : 1;/*!< needs field desc */ - __IOM uint32_t DELAY_LIMIT_VT2_PD_SITE3_UNIT1 : 8;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_NUM_O_VT2_PD_SITE3_UNIT1 : 8;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_VT2_PD_SITE3_UNIT1 : 1;/*!< needs field desc */ - } bit; - } COMB_PD_SITE3_UNIT1_VT2_CONF1; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EN_VT2_PD_SITE3_UNIT2 : 1;/*!< needs field desc */ - __OM uint32_t TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT2 : 1;/*!< needs field desc */ - __IOM uint32_t DELAY_LIMIT_VT2_PD_SITE3_UNIT2 : 8;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_NUM_O_VT2_PD_SITE3_UNIT2 : 8;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_VT2_PD_SITE3_UNIT2 : 1;/*!< needs field desc */ - } bit; - } COMB_PD_SITE3_UNIT2_VT2_CONF1; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EN_VT2_PD_SITE3_UNIT3 : 1;/*!< needs field desc */ - __OM uint32_t TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT3 : 1;/*!< needs field desc */ - __IOM uint32_t DELAY_LIMIT_VT2_PD_SITE3_UNIT3 : 8;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_NUM_O_VT2_PD_SITE3_UNIT3 : 8;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_VT2_PD_SITE3_UNIT3 : 1;/*!< needs field desc */ - } bit; - } COMB_PD_SITE3_UNIT3_VT2_CONF1; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT0 : 2;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_OVF_VT0_PD_SITE0_UNIT0 : 1;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT0 : 16;/*!< needs field desc */ - } bit; - } COMB_PD_SITE0_UNIT0_VT0_CONF2; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT1 : 2;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_OVF_VT0_PD_SITE0_UNIT1 : 1;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT1 : 16;/*!< needs field desc */ - } bit; - } COMB_PD_SITE0_UNIT1_VT0_CONF2; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT2 : 2;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_OVF_VT0_PD_SITE0_UNIT2 : 1;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT2 : 16;/*!< needs field desc */ - } bit; - } COMB_PD_SITE0_UNIT2_VT0_CONF2; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT3 : 2;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_OVF_VT0_PD_SITE0_UNIT3 : 1;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT3 : 16;/*!< needs field desc */ - } bit; - } COMB_PD_SITE0_UNIT3_VT0_CONF2; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT0 : 2;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_OVF_VT1_PD_SITE0_UNIT0 : 1;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT0 : 16;/*!< needs field desc */ - } bit; - } COMB_PD_SITE0_UNIT0_VT1_CONF2; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT1 : 2;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_OVF_VT1_PD_SITE0_UNIT1 : 1;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT1 : 16;/*!< needs field desc */ - } bit; - } COMB_PD_SITE0_UNIT1_VT1_CONF2; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT2 : 2;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_OVF_VT1_PD_SITE0_UNIT2 : 1;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT2 : 16;/*!< needs field desc */ - } bit; - } COMB_PD_SITE0_UNIT2_VT1_CONF2; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT3 : 2;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_OVF_VT1_PD_SITE0_UNIT3 : 1;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT3 : 16;/*!< needs field desc */ - } bit; - } COMB_PD_SITE0_UNIT3_VT1_CONF2; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT0 : 2;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_OVF_VT2_PD_SITE0_UNIT0 : 1;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT0 : 16;/*!< needs field desc */ - } bit; - } COMB_PD_SITE0_UNIT0_VT2_CONF2; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT1 : 2;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_OVF_VT2_PD_SITE0_UNIT1 : 1;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT1 : 16;/*!< needs field desc */ - } bit; - } COMB_PD_SITE0_UNIT1_VT2_CONF2; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT2 : 2;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_OVF_VT2_PD_SITE0_UNIT2 : 1;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT2 : 16;/*!< needs field desc */ - } bit; - } COMB_PD_SITE0_UNIT2_VT2_CONF2; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT3 : 2;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_OVF_VT2_PD_SITE0_UNIT3 : 1;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT3 : 16;/*!< needs field desc */ - } bit; - } COMB_PD_SITE0_UNIT3_VT2_CONF2; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT0 : 2;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_OVF_VT0_PD_SITE1_UNIT0 : 1;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT0 : 16;/*!< needs field desc */ - } bit; - } COMB_PD_SITE1_UNIT0_VT0_CONF2; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT1 : 2;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_OVF_VT0_PD_SITE1_UNIT1 : 1;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT1 : 16;/*!< needs field desc */ - } bit; - } COMB_PD_SITE1_UNIT1_VT0_CONF2; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT2 : 2;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_OVF_VT0_PD_SITE1_UNIT2 : 1;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT2 : 16;/*!< needs field desc */ - } bit; - } COMB_PD_SITE1_UNIT2_VT0_CONF2; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT3 : 2;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_OVF_VT0_PD_SITE1_UNIT3 : 1;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT3 : 16;/*!< needs field desc */ - } bit; - } COMB_PD_SITE1_UNIT3_VT0_CONF2; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT0 : 2;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_OVF_VT1_PD_SITE1_UNIT0 : 1;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT0 : 16;/*!< needs field desc */ - } bit; - } COMB_PD_SITE1_UNIT0_VT1_CONF2; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT1 : 2;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_OVF_VT1_PD_SITE1_UNIT1 : 1;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT1 : 16;/*!< needs field desc */ - } bit; - } COMB_PD_SITE1_UNIT1_VT1_CONF2; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT2 : 2;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_OVF_VT1_PD_SITE1_UNIT2 : 1;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT2 : 16;/*!< needs field desc */ - } bit; - } COMB_PD_SITE1_UNIT2_VT1_CONF2; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT3 : 2;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_OVF_VT1_PD_SITE1_UNIT3 : 1;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT3 : 16;/*!< needs field desc */ - } bit; - } COMB_PD_SITE1_UNIT3_VT1_CONF2; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT0 : 2;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_OVF_VT2_PD_SITE1_UNIT0 : 1;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT0 : 16;/*!< needs field desc */ - } bit; - } COMB_PD_SITE1_UNIT0_VT2_CONF2; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT1 : 2;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_OVF_VT2_PD_SITE1_UNIT1 : 1;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT1 : 16;/*!< needs field desc */ - } bit; - } COMB_PD_SITE1_UNIT1_VT2_CONF2; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT2 : 2;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_OVF_VT2_PD_SITE1_UNIT2 : 1;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT2 : 16;/*!< needs field desc */ - } bit; - } COMB_PD_SITE1_UNIT2_VT2_CONF2; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT3 : 2;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_OVF_VT2_PD_SITE1_UNIT3 : 1;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT3 : 16;/*!< needs field desc */ - } bit; - } COMB_PD_SITE1_UNIT3_VT2_CONF2; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT0 : 2;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_OVF_VT0_PD_SITE2_UNIT0 : 1;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT0 : 16;/*!< needs field desc */ - } bit; - } COMB_PD_SITE2_UNIT0_VT0_CONF2; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT1 : 2;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_OVF_VT0_PD_SITE2_UNIT1 : 1;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT1 : 16;/*!< needs field desc */ - } bit; - } COMB_PD_SITE2_UNIT1_VT0_CONF2; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT2 : 2;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_OVF_VT0_PD_SITE2_UNIT2 : 1;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT2 : 16;/*!< needs field desc */ - } bit; - } COMB_PD_SITE2_UNIT2_VT0_CONF2; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT3 : 2;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_OVF_VT0_PD_SITE2_UNIT3 : 1;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT3 : 16;/*!< needs field desc */ - } bit; - } COMB_PD_SITE2_UNIT3_VT0_CONF2; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT0 : 2;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_OVF_VT1_PD_SITE2_UNIT0 : 1;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT0 : 16;/*!< needs field desc */ - } bit; - } COMB_PD_SITE2_UNIT0_VT1_CONF2; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT1 : 2;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_OVF_VT1_PD_SITE2_UNIT1 : 1;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT1 : 16;/*!< needs field desc */ - } bit; - } COMB_PD_SITE2_UNIT1_VT1_CONF2; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT2 : 2;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_OVF_VT1_PD_SITE2_UNIT2 : 1;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT2 : 16;/*!< needs field desc */ - } bit; - } COMB_PD_SITE2_UNIT2_VT1_CONF2; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT3 : 2;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_OVF_VT1_PD_SITE2_UNIT3 : 1;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT3 : 16;/*!< needs field desc */ - } bit; - } COMB_PD_SITE2_UNIT3_VT1_CONF2; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0 : 2;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_OVF_VT2_PD_SITE2_UNIT0 : 1;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT0 : 16;/*!< needs field desc */ - } bit; - } COMB_PD_SITE2_UNIT0_VT2_CONF2; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT1 : 2;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_OVF_VT2_PD_SITE2_UNIT1 : 1;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT1 : 16;/*!< needs field desc */ - } bit; - } COMB_PD_SITE2_UNIT1_VT2_CONF2; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT2 : 2;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_OVF_VT2_PD_SITE2_UNIT2 : 1;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT2 : 16;/*!< needs field desc */ - } bit; - } COMB_PD_SITE2_UNIT2_VT2_CONF2; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT3 : 2;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_OVF_VT2_PD_SITE2_UNIT3 : 1;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT3 : 16;/*!< needs field desc */ - } bit; - } COMB_PD_SITE2_UNIT3_VT2_CONF2; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT0 : 2;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_OVF_VT0_PD_SITE3_UNIT0 : 1;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT0 : 16;/*!< needs field desc */ - } bit; - } COMB_PD_SITE3_UNIT0_VT0_CONF2; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT1 : 2;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_OVF_VT0_PD_SITE3_UNIT1 : 1;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT1 : 16;/*!< needs field desc */ - } bit; - } COMB_PD_SITE3_UNIT1_VT0_CONF2; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT2 : 2;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_OVF_VT0_PD_SITE3_UNIT2 : 1;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT2 : 16;/*!< needs field desc */ - } bit; - } COMB_PD_SITE3_UNIT2_VT0_CONF2; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT3 : 2;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_OVF_VT0_PD_SITE3_UNIT3 : 1;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT3 : 16;/*!< needs field desc */ - } bit; - } COMB_PD_SITE3_UNIT3_VT0_CONF2; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT0 : 2;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_OVF_VT1_PD_SITE3_UNIT0 : 1;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT0 : 16;/*!< needs field desc */ - } bit; - } COMB_PD_SITE3_UNIT0_VT1_CONF2; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT1 : 2;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_OVF_VT1_PD_SITE3_UNIT1 : 1;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT1 : 16;/*!< needs field desc */ - } bit; - } COMB_PD_SITE3_UNIT1_VT1_CONF2; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT2 : 2;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_OVF_VT1_PD_SITE3_UNIT2 : 1;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT2 : 16;/*!< needs field desc */ - } bit; - } COMB_PD_SITE3_UNIT2_VT1_CONF2; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT3 : 2;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_OVF_VT1_PD_SITE3_UNIT3 : 1;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT3 : 16;/*!< needs field desc */ - } bit; - } COMB_PD_SITE3_UNIT3_VT1_CONF2; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT0 : 2;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_OVF_VT2_PD_SITE3_UNIT0 : 1;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT0 : 16;/*!< needs field desc */ - } bit; - } COMB_PD_SITE3_UNIT0_VT2_CONF2; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT1 : 2;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_OVF_VT2_PD_SITE3_UNIT1 : 1;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT1 : 16;/*!< needs field desc */ - } bit; - } COMB_PD_SITE3_UNIT1_VT2_CONF2; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT2 : 2;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_OVF_VT2_PD_SITE3_UNIT2 : 1;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT2 : 16;/*!< needs field desc */ - } bit; - } COMB_PD_SITE3_UNIT2_VT2_CONF2; - - union { - __IOM uint32_t reg; /*!< needs desc */ - - struct { - __IOM uint32_t MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT3 : 2;/*!< needs field desc */ - uint32_t : 13; - __IM uint32_t DELAY_OVF_VT2_PD_SITE3_UNIT3 : 1;/*!< needs field desc */ - __IM uint32_t TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT3 : 16;/*!< needs field desc */ - } bit; - } COMB_PD_SITE3_UNIT3_VT2_CONF2; - - union { - __IOM uint32_t reg; /*!< needs field desc */ - - struct { - __OM uint32_t VALUE_UPDATE : 1; /*!< needs field desc */ - __IOM uint32_t BYPASS : 1; /*!< needs field desc */ - uint32_t : 30; - } bit; - } VALUE_UPDATE; - __IM uint32_t RESERVED[900]; - - union { - __IOM uint32_t reg; /*!< version register */ - - struct { - __IOM uint32_t DATE : 32; /*!< version register */ - } bit; - } DATE; -} PVT_Type; /*!< Size = 4096 (0x1000) */ - - - -/* =========================================================================================================================== */ -/* ================ RMT ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Remote Control (RMT) - */ - -typedef struct { /*!< RMT Structure */ - __IOM uint32_t TX_CH0DATA; /*!< The read and write data register for CHANNEL0 by apb fifo access. */ - __IM uint32_t RESERVED[3]; - - union { - __IOM uint32_t TX_CH1DATA; /*!< The read and write data register for CHANNEL1 by apb fifo access. */ - - union { - __IOM uint32_t reg; /*!< The read and write data register for CHANNEL$n by apb fifo access. */ - - struct { - __IM uint32_t CHDATA : 32; /*!< Read and write data for channel 0 via APB FIFO. */ - } bit; - } RX_CH0DATA; - }; - __IM uint32_t RESERVED1[3]; - - union { - __IOM uint32_t TX_CH2DATA; /*!< The read and write data register for CHANNEL2 by apb fifo access. */ - - union { - __IOM uint32_t reg; /*!< The read and write data register for CHANNEL$n by apb fifo access. */ - - struct { - __IM uint32_t CHDATA : 32; /*!< Read and write data for channel 0 via APB FIFO. */ - } bit; - } RX_CH1DATA; - - union { - __IOM uint32_t reg; /*!< Channel 0 configure register 0 */ - - struct { - uint32_t : 23; - __OM uint32_t AFIFO_RST_CH0 : 1; /*!< Reserved */ - uint32_t : 8; - } bit; - } TX_CH0CONF0; - }; - __IM uint32_t RESERVED2[3]; - - union { - __IOM uint32_t TX_CH3DATA; /*!< The read and write data register for CHANNEL3 by apb fifo access. */ - - union { - __IOM uint32_t reg; /*!< The read and write data register for CHANNEL$n by apb fifo access. */ - - struct { - __IM uint32_t CHDATA : 32; /*!< Read and write data for channel 0 via APB FIFO. */ - } bit; - } RX_CH2DATA; - - union { - __IOM uint32_t reg; /*!< Channel 1 configure register 0 */ - - struct { - uint32_t : 23; - __OM uint32_t AFIFO_RST_CH0 : 1; /*!< Reserved */ - uint32_t : 8; - } bit; - } TX_CH1CONF0; - - union { - __IOM uint32_t reg; /*!< Channel 0 configure register 0 */ - - struct { - uint32_t : 8; - __IOM uint32_t IDLE_THRES_CH4 : 15; /*!< When no edge is detected on the input signal and continuous - clock cycles is longer than this register value, received - process is finished. */ - uint32_t : 9; - } bit; - } RX_CH0CONF0; - }; - - union { - __IOM uint32_t reg; /*!< Channel 0 configure register 1 */ - - struct { - uint32_t : 5; - __IOM uint32_t RX_FILTER_THRES_CH4 : 8; /*!< Ignores the input pulse when its width is smaller than this - register value in APB clock periods (in receive mode). */ - uint32_t : 1; - __OM uint32_t AFIFO_RST_CH4 : 1; /*!< Reserved */ - uint32_t : 17; - } bit; - } RX_CH0CONF1; - __IM uint32_t RESERVED3[2]; - - union { - union { - __IOM uint32_t reg; /*!< The read and write data register for CHANNEL$n by apb fifo access. */ - - struct { - __IM uint32_t CHDATA : 32; /*!< Read and write data for channel 0 via APB FIFO. */ - } bit; - } RX_CH3DATA; - - union { - __IOM uint32_t reg; /*!< Channel 2 configure register 0 */ - - struct { - uint32_t : 23; - __OM uint32_t AFIFO_RST_CH0 : 1; /*!< Reserved */ - uint32_t : 8; - } bit; - } TX_CH2CONF0; - }; - __IM uint32_t RESERVED4[3]; - - union { - union { - __IOM uint32_t reg; /*!< Channel 3 configure register 0 */ - - struct { - uint32_t : 23; - __OM uint32_t AFIFO_RST_CH0 : 1; /*!< Reserved */ - uint32_t : 8; - } bit; - } TX_CH3CONF0; - - union { - __IOM uint32_t reg; /*!< Channel 1 configure register 0 */ - - struct { - uint32_t : 8; - __IOM uint32_t IDLE_THRES_CH4 : 15; /*!< When no edge is detected on the input signal and continuous - clock cycles is longer than this register value, received - process is finished. */ - uint32_t : 9; - } bit; - } RX_CH1CONF0; - - union { - __IOM uint32_t reg; /*!< Channel 0 status register */ - - struct { - uint32_t : 11; - __IM uint32_t APB_MEM_WADDR_CH0 : 10; /*!< This register records the memory address offset when writes - RAM over APB bus. */ - uint32_t : 4; - __IM uint32_t MEM_EMPTY_CH0 : 1; /*!< This status bit will be set when the data to be set is more - than memory size and the wraparound mode is disabled. */ - __IM uint32_t APB_MEM_WR_ERR_CH0 : 1; /*!< This status bit will be set if the offset address out of memory - size when writes via APB bus. */ - uint32_t : 5; - } bit; - } TX_CH0STATUS; - }; - - union { - __IOM uint32_t reg; /*!< Channel 1 configure register 1 */ - - struct { - uint32_t : 5; - __IOM uint32_t RX_FILTER_THRES_CH4 : 8; /*!< Ignores the input pulse when its width is smaller than this - register value in APB clock periods (in receive mode). */ - uint32_t : 1; - __OM uint32_t AFIFO_RST_CH4 : 1; /*!< Reserved */ - uint32_t : 17; - } bit; - } RX_CH1CONF1; - __IM uint32_t RESERVED5[2]; - - union { - union { - __IOM uint32_t reg; /*!< Channel 1 status register */ - - struct { - uint32_t : 11; - __IM uint32_t APB_MEM_WADDR_CH0 : 10; /*!< This register records the memory address offset when writes - RAM over APB bus. */ - uint32_t : 4; - __IM uint32_t MEM_EMPTY_CH0 : 1; /*!< This status bit will be set when the data to be set is more - than memory size and the wraparound mode is disabled. */ - __IM uint32_t APB_MEM_WR_ERR_CH0 : 1; /*!< This status bit will be set if the offset address out of memory - size when writes via APB bus. */ - uint32_t : 5; - } bit; - } TX_CH1STATUS; - - union { - __IOM uint32_t reg; /*!< Channel 0 status register */ - - struct { - uint32_t : 11; - __IM uint32_t APB_MEM_RADDR_CH4 : 10; /*!< This register records the memory address offset when reads RAM - over APB bus. */ - uint32_t : 4; - __IM uint32_t MEM_OWNER_ERR_CH4 : 1; /*!< This status bit will be set when the ownership of memory block - is wrong. */ - __IM uint32_t MEM_FULL_CH4 : 1; /*!< This status bit will be set if the receiver receives more data - than the memory size. */ - __IM uint32_t APB_MEM_RD_ERR_CH4 : 1; /*!< This status bit will be set if the offset address out of memory - size when reads via APB bus. */ - uint32_t : 4; - } bit; - } RX_CH0STATUS; - }; - __IM uint32_t RESERVED6[3]; - - union { - union { - __IOM uint32_t reg; /*!< Channel 2 configure register 0 */ - - struct { - uint32_t : 8; - __IOM uint32_t IDLE_THRES_CH4 : 15; /*!< When no edge is detected on the input signal and continuous - clock cycles is longer than this register value, received - process is finished. */ - uint32_t : 9; - } bit; - } RX_CH2CONF0; - - union { - __IOM uint32_t reg; /*!< Channel 2 status register */ - - struct { - uint32_t : 11; - __IM uint32_t APB_MEM_WADDR_CH0 : 10; /*!< This register records the memory address offset when writes - RAM over APB bus. */ - uint32_t : 4; - __IM uint32_t MEM_EMPTY_CH0 : 1; /*!< This status bit will be set when the data to be set is more - than memory size and the wraparound mode is disabled. */ - __IM uint32_t APB_MEM_WR_ERR_CH0 : 1; /*!< This status bit will be set if the offset address out of memory - size when writes via APB bus. */ - uint32_t : 5; - } bit; - } TX_CH2STATUS; - - union { - __IOM uint32_t reg; /*!< Channel 1 status register */ - - struct { - uint32_t : 11; - __IM uint32_t APB_MEM_RADDR_CH4 : 10; /*!< This register records the memory address offset when reads RAM - over APB bus. */ - uint32_t : 4; - __IM uint32_t MEM_OWNER_ERR_CH4 : 1; /*!< This status bit will be set when the ownership of memory block - is wrong. */ - __IM uint32_t MEM_FULL_CH4 : 1; /*!< This status bit will be set if the receiver receives more data - than the memory size. */ - __IM uint32_t APB_MEM_RD_ERR_CH4 : 1; /*!< This status bit will be set if the offset address out of memory - size when reads via APB bus. */ - uint32_t : 4; - } bit; - } RX_CH1STATUS; - - union { - __IOM uint32_t reg; /*!< Raw interrupt status */ - - struct { - __IOM uint32_t CH0_TX_END_INT_RAW : 1; /*!< The interrupt raw bit for CHANNEL0. Triggered when transmission - done. */ - __IOM uint32_t CH1_TX_END_INT_RAW : 1; /*!< The interrupt raw bit for CHANNEL1. Triggered when transmission - done. */ - __IOM uint32_t CH2_TX_END_INT_RAW : 1; /*!< The interrupt raw bit for CHANNEL2. Triggered when transmission - done. */ - __IOM uint32_t CH3_TX_END_INT_RAW : 1; /*!< The interrupt raw bit for CHANNEL3. Triggered when transmission - done. */ - __IOM uint32_t TX_CH0_ERR_INT_RAW : 1; /*!< The interrupt raw bit for CHANNEL0. Triggered when error occurs. */ - __IOM uint32_t TX_CH1_ERR_INT_RAW : 1; /*!< The interrupt raw bit for CHANNEL1. Triggered when error occurs. */ - __IOM uint32_t TX_CH2_ERR_INT_RAW : 1; /*!< The interrupt raw bit for CHANNEL2. Triggered when error occurs. */ - __IOM uint32_t TX_CH3_ERR_INT_RAW : 1; /*!< The interrupt raw bit for CHANNEL3. Triggered when error occurs. */ - __IOM uint32_t CH0_TX_THR_EVENT_INT_RAW : 1;/*!< The interrupt raw bit for CHANNEL0. Triggered when transmitter - sent more data than configured value. */ - __IOM uint32_t CH1_TX_THR_EVENT_INT_RAW : 1;/*!< The interrupt raw bit for CHANNEL1. Triggered when transmitter - sent more data than configured value. */ - __IOM uint32_t CH2_TX_THR_EVENT_INT_RAW : 1;/*!< The interrupt raw bit for CHANNEL2. Triggered when transmitter - sent more data than configured value. */ - __IOM uint32_t CH3_TX_THR_EVENT_INT_RAW : 1;/*!< The interrupt raw bit for CHANNEL3. Triggered when transmitter - sent more data than configured value. */ - __IOM uint32_t CH0_TX_LOOP_INT_RAW : 1; /*!< The interrupt raw bit for CHANNEL0. Triggered when the loop - count reaches the configured threshold value. */ - __IOM uint32_t CH1_TX_LOOP_INT_RAW : 1; /*!< The interrupt raw bit for CHANNEL1. Triggered when the loop - count reaches the configured threshold value. */ - __IOM uint32_t CH2_TX_LOOP_INT_RAW : 1; /*!< The interrupt raw bit for CHANNEL2. Triggered when the loop - count reaches the configured threshold value. */ - __IOM uint32_t CH3_TX_LOOP_INT_RAW : 1; /*!< The interrupt raw bit for CHANNEL3. Triggered when the loop - count reaches the configured threshold value. */ - __IOM uint32_t CH4_RX_END_INT_RAW : 1; /*!< The interrupt raw bit for CHANNEL4. Triggered when reception - done. */ - __IOM uint32_t CH5_RX_END_INT_RAW : 1; /*!< The interrupt raw bit for CHANNEL5. Triggered when reception - done. */ - __IOM uint32_t CH6_RX_END_INT_RAW : 1; /*!< The interrupt raw bit for CHANNEL6. Triggered when reception - done. */ - __IOM uint32_t CH7_RX_END_INT_RAW : 1; /*!< The interrupt raw bit for CHANNEL7. Triggered when reception - done. */ - __IOM uint32_t RX_CH4_ERR_INT_RAW : 1; /*!< The interrupt raw bit for CHANNEL4. Triggered when error occurs. */ - __IOM uint32_t RX_CH5_ERR_INT_RAW : 1; /*!< The interrupt raw bit for CHANNEL5. Triggered when error occurs. */ - __IOM uint32_t RX_CH6_ERR_INT_RAW : 1; /*!< The interrupt raw bit for CHANNEL6. Triggered when error occurs. */ - __IOM uint32_t RX_CH7_ERR_INT_RAW : 1; /*!< The interrupt raw bit for CHANNEL7. Triggered when error occurs. */ - __IOM uint32_t CH4_RX_THR_EVENT_INT_RAW : 1;/*!< The interrupt raw bit for CHANNEL4. Triggered when receiver - receive more data than configured value. */ - __IOM uint32_t CH5_RX_THR_EVENT_INT_RAW : 1;/*!< The interrupt raw bit for CHANNEL5. Triggered when receiver - receive more data than configured value. */ - __IOM uint32_t CH6_RX_THR_EVENT_INT_RAW : 1;/*!< The interrupt raw bit for CHANNEL6. Triggered when receiver - receive more data than configured value. */ - __IOM uint32_t CH7_RX_THR_EVENT_INT_RAW : 1;/*!< The interrupt raw bit for CHANNEL7. Triggered when receiver - receive more data than configured value. */ - __IOM uint32_t TX_CH3_DMA_ACCESS_FAIL_INT_RAW : 1;/*!< The interrupt raw bit for CHANNEL3. Triggered when dma accessing - CHANNEL3 fails. */ - __IOM uint32_t RX_CH7_DMA_ACCESS_FAIL_INT_RAW : 1;/*!< The interrupt raw bit for CHANNEL7. Triggered when dma accessing - CHANNEL7 fails. */ - uint32_t : 2; - } bit; - } INT_RAW; - }; - - union { - union { - __IOM uint32_t reg; /*!< Channel 2 configure register 1 */ - - struct { - uint32_t : 5; - __IOM uint32_t RX_FILTER_THRES_CH4 : 8; /*!< Ignores the input pulse when its width is smaller than this - register value in APB clock periods (in receive mode). */ - uint32_t : 1; - __OM uint32_t AFIFO_RST_CH4 : 1; /*!< Reserved */ - uint32_t : 17; - } bit; - } RX_CH2CONF1; - - union { - __IOM uint32_t reg; /*!< Masked interrupt status */ - - struct { - __IM uint32_t CH0_TX_END_INT_ST : 1; /*!< The masked interrupt status bit for CH0_TX_END_INT. */ - __IM uint32_t CH1_TX_END_INT_ST : 1; /*!< The masked interrupt status bit for CH1_TX_END_INT. */ - __IM uint32_t CH2_TX_END_INT_ST : 1; /*!< The masked interrupt status bit for CH2_TX_END_INT. */ - __IM uint32_t CH3_TX_END_INT_ST : 1; /*!< The masked interrupt status bit for CH3_TX_END_INT. */ - __IM uint32_t TX_CH0_ERR_INT_ST : 1; /*!< The masked interrupt status bit for CH0_ERR_INT. */ - __IM uint32_t TX_CH1_ERR_INT_ST : 1; /*!< The masked interrupt status bit for CH1_ERR_INT. */ - __IM uint32_t TX_CH2_ERR_INT_ST : 1; /*!< The masked interrupt status bit for CH2_ERR_INT. */ - __IM uint32_t TX_CH3_ERR_INT_ST : 1; /*!< The masked interrupt status bit for CH3_ERR_INT. */ - __IM uint32_t CH0_TX_THR_EVENT_INT_ST : 1;/*!< The masked interrupt status bit for CH0_TX_THR_EVENT_INT. */ - __IM uint32_t CH1_TX_THR_EVENT_INT_ST : 1;/*!< The masked interrupt status bit for CH1_TX_THR_EVENT_INT. */ - __IM uint32_t CH2_TX_THR_EVENT_INT_ST : 1;/*!< The masked interrupt status bit for CH2_TX_THR_EVENT_INT. */ - __IM uint32_t CH3_TX_THR_EVENT_INT_ST : 1;/*!< The masked interrupt status bit for CH3_TX_THR_EVENT_INT. */ - __IM uint32_t CH0_TX_LOOP_INT_ST : 1; /*!< The masked interrupt status bit for CH0_TX_LOOP_INT. */ - __IM uint32_t CH1_TX_LOOP_INT_ST : 1; /*!< The masked interrupt status bit for CH1_TX_LOOP_INT. */ - __IM uint32_t CH2_TX_LOOP_INT_ST : 1; /*!< The masked interrupt status bit for CH2_TX_LOOP_INT. */ - __IM uint32_t CH3_TX_LOOP_INT_ST : 1; /*!< The masked interrupt status bit for CH3_TX_LOOP_INT. */ - __IM uint32_t CH4_RX_END_INT_ST : 1; /*!< The masked interrupt status bit for CH4_RX_END_INT. */ - __IM uint32_t CH5_RX_END_INT_ST : 1; /*!< The masked interrupt status bit for CH5_RX_END_INT. */ - __IM uint32_t CH6_RX_END_INT_ST : 1; /*!< The masked interrupt status bit for CH6_RX_END_INT. */ - __IM uint32_t CH7_RX_END_INT_ST : 1; /*!< The masked interrupt status bit for CH7_RX_END_INT. */ - __IM uint32_t RX_CH4_ERR_INT_ST : 1; /*!< The masked interrupt status bit for CH4_ERR_INT. */ - __IM uint32_t RX_CH5_ERR_INT_ST : 1; /*!< The masked interrupt status bit for CH5_ERR_INT. */ - __IM uint32_t RX_CH6_ERR_INT_ST : 1; /*!< The masked interrupt status bit for CH6_ERR_INT. */ - __IM uint32_t RX_CH7_ERR_INT_ST : 1; /*!< The masked interrupt status bit for CH7_ERR_INT. */ - __IM uint32_t CH4_RX_THR_EVENT_INT_ST : 1;/*!< The masked interrupt status bit for CH4_RX_THR_EVENT_INT. */ - __IM uint32_t CH5_RX_THR_EVENT_INT_ST : 1;/*!< The masked interrupt status bit for CH5_RX_THR_EVENT_INT. */ - __IM uint32_t CH6_RX_THR_EVENT_INT_ST : 1;/*!< The masked interrupt status bit for CH6_RX_THR_EVENT_INT. */ - __IM uint32_t CH7_RX_THR_EVENT_INT_ST : 1;/*!< The masked interrupt status bit for CH7_RX_THR_EVENT_INT. */ - __IM uint32_t TX_CH3_DMA_ACCESS_FAIL_INT_ST : 1;/*!< The masked interrupt status bit for CH3_DMA_ACCESS_FAIL_INT. */ - __IM uint32_t RX_CH7_DMA_ACCESS_FAIL_INT_ST : 1;/*!< The masked interrupt status bit for CH7_DMA_ACCESS_FAIL_INT. */ - uint32_t : 2; - } bit; - } INT_ST; - }; - - union { - __IOM uint32_t reg; /*!< Interrupt enable bits */ - - struct { - __IOM uint32_t CH0_TX_END_INT_ENA : 1; /*!< The interrupt enable bit for CH0_TX_END_INT. */ - __IOM uint32_t CH1_TX_END_INT_ENA : 1; /*!< The interrupt enable bit for CH1_TX_END_INT. */ - __IOM uint32_t CH2_TX_END_INT_ENA : 1; /*!< The interrupt enable bit for CH2_TX_END_INT. */ - __IOM uint32_t CH3_TX_END_INT_ENA : 1; /*!< The interrupt enable bit for CH3_TX_END_INT. */ - __IOM uint32_t TX_CH0_ERR_INT_ENA : 1; /*!< The interrupt enable bit for CH0_ERR_INT. */ - __IOM uint32_t TX_CH1_ERR_INT_ENA : 1; /*!< The interrupt enable bit for CH1_ERR_INT. */ - __IOM uint32_t TX_CH2_ERR_INT_ENA : 1; /*!< The interrupt enable bit for CH2_ERR_INT. */ - __IOM uint32_t TX_CH3_ERR_INT_ENA : 1; /*!< The interrupt enable bit for CH3_ERR_INT. */ - __IOM uint32_t CH0_TX_THR_EVENT_INT_ENA : 1;/*!< The interrupt enable bit for CH0_TX_THR_EVENT_INT. */ - __IOM uint32_t CH1_TX_THR_EVENT_INT_ENA : 1;/*!< The interrupt enable bit for CH1_TX_THR_EVENT_INT. */ - __IOM uint32_t CH2_TX_THR_EVENT_INT_ENA : 1;/*!< The interrupt enable bit for CH2_TX_THR_EVENT_INT. */ - __IOM uint32_t CH3_TX_THR_EVENT_INT_ENA : 1;/*!< The interrupt enable bit for CH3_TX_THR_EVENT_INT. */ - __IOM uint32_t CH0_TX_LOOP_INT_ENA : 1; /*!< The interrupt enable bit for CH0_TX_LOOP_INT. */ - __IOM uint32_t CH1_TX_LOOP_INT_ENA : 1; /*!< The interrupt enable bit for CH1_TX_LOOP_INT. */ - __IOM uint32_t CH2_TX_LOOP_INT_ENA : 1; /*!< The interrupt enable bit for CH2_TX_LOOP_INT. */ - __IOM uint32_t CH3_TX_LOOP_INT_ENA : 1; /*!< The interrupt enable bit for CH3_TX_LOOP_INT. */ - __IOM uint32_t CH4_RX_END_INT_ENA : 1; /*!< The interrupt enable bit for CH4_RX_END_INT. */ - __IOM uint32_t CH5_RX_END_INT_ENA : 1; /*!< The interrupt enable bit for CH5_RX_END_INT. */ - __IOM uint32_t CH6_RX_END_INT_ENA : 1; /*!< The interrupt enable bit for CH6_RX_END_INT. */ - __IOM uint32_t CH7_RX_END_INT_ENA : 1; /*!< The interrupt enable bit for CH7_RX_END_INT. */ - __IOM uint32_t CH4_ERR_INT_ENA : 1; /*!< The interrupt enable bit for CH4_ERR_INT. */ - __IOM uint32_t CH5_ERR_INT_ENA : 1; /*!< The interrupt enable bit for CH5_ERR_INT. */ - __IOM uint32_t CH6_ERR_INT_ENA : 1; /*!< The interrupt enable bit for CH6_ERR_INT. */ - __IOM uint32_t CH7_ERR_INT_ENA : 1; /*!< The interrupt enable bit for CH7_ERR_INT. */ - __IOM uint32_t CH4_RX_THR_EVENT_INT_ENA : 1;/*!< The interrupt enable bit for CH4_RX_THR_EVENT_INT. */ - __IOM uint32_t CH5_RX_THR_EVENT_INT_ENA : 1;/*!< The interrupt enable bit for CH5_RX_THR_EVENT_INT. */ - __IOM uint32_t CH6_RX_THR_EVENT_INT_ENA : 1;/*!< The interrupt enable bit for CH6_RX_THR_EVENT_INT. */ - __IOM uint32_t CH7_RX_THR_EVENT_INT_ENA : 1;/*!< The interrupt enable bit for CH7_RX_THR_EVENT_INT. */ - __IOM uint32_t TX_CH3_DMA_ACCESS_FAIL_INT_ENA : 1;/*!< The interrupt enable bit for CH3_DMA_ACCESS_FAIL_INT. */ - __IOM uint32_t RX_CH7_DMA_ACCESS_FAIL_INT_ENA : 1;/*!< The interrupt enable bit for CH7_DMA_ACCESS_FAIL_INT. */ - uint32_t : 2; - } bit; - } INT_ENA; - - union { - __IOM uint32_t reg; /*!< Interrupt clear bits */ - - struct { - __OM uint32_t CH0_TX_END_INT_CLR : 1; /*!< Set this bit to clear theCH0_TX_END_INT interrupt. */ - __OM uint32_t CH1_TX_END_INT_CLR : 1; /*!< Set this bit to clear theCH1_TX_END_INT interrupt. */ - __OM uint32_t CH2_TX_END_INT_CLR : 1; /*!< Set this bit to clear theCH2_TX_END_INT interrupt. */ - __OM uint32_t CH3_TX_END_INT_CLR : 1; /*!< Set this bit to clear theCH3_TX_END_INT interrupt. */ - __OM uint32_t TX_CH0_ERR_INT_CLR : 1; /*!< Set this bit to clear theCH0_ERR_INT interrupt. */ - __OM uint32_t TX_CH1_ERR_INT_CLR : 1; /*!< Set this bit to clear theCH1_ERR_INT interrupt. */ - __OM uint32_t TX_CH2_ERR_INT_CLR : 1; /*!< Set this bit to clear theCH2_ERR_INT interrupt. */ - __OM uint32_t TX_CH3_ERR_INT_CLR : 1; /*!< Set this bit to clear theCH3_ERR_INT interrupt. */ - __OM uint32_t CH0_TX_THR_EVENT_INT_CLR : 1;/*!< Set this bit to clear theCH0_TX_THR_EVENT_INT interrupt. */ - __OM uint32_t CH1_TX_THR_EVENT_INT_CLR : 1;/*!< Set this bit to clear theCH1_TX_THR_EVENT_INT interrupt. */ - __OM uint32_t CH2_TX_THR_EVENT_INT_CLR : 1;/*!< Set this bit to clear theCH2_TX_THR_EVENT_INT interrupt. */ - __OM uint32_t CH3_TX_THR_EVENT_INT_CLR : 1;/*!< Set this bit to clear theCH3_TX_THR_EVENT_INT interrupt. */ - __OM uint32_t CH0_TX_LOOP_INT_CLR : 1; /*!< Set this bit to clear theCH0_TX_LOOP_INT interrupt. */ - __OM uint32_t CH1_TX_LOOP_INT_CLR : 1; /*!< Set this bit to clear theCH1_TX_LOOP_INT interrupt. */ - __OM uint32_t CH2_TX_LOOP_INT_CLR : 1; /*!< Set this bit to clear theCH2_TX_LOOP_INT interrupt. */ - __OM uint32_t CH3_TX_LOOP_INT_CLR : 1; /*!< Set this bit to clear theCH3_TX_LOOP_INT interrupt. */ - __OM uint32_t CH4_RX_END_INT_CLR : 1; /*!< Set this bit to clear theCH4_RX_END_INT interrupt. */ - __OM uint32_t CH5_RX_END_INT_CLR : 1; /*!< Set this bit to clear theCH5_RX_END_INT interrupt. */ - __OM uint32_t CH6_RX_END_INT_CLR : 1; /*!< Set this bit to clear theCH6_RX_END_INT interrupt. */ - __OM uint32_t CH7_RX_END_INT_CLR : 1; /*!< Set this bit to clear theCH7_RX_END_INT interrupt. */ - __OM uint32_t RX_CH4_ERR_INT_CLR : 1; /*!< Set this bit to clear theCH4_ERR_INT interrupt. */ - __OM uint32_t RX_CH5_ERR_INT_CLR : 1; /*!< Set this bit to clear theCH5_ERR_INT interrupt. */ - __OM uint32_t RX_CH6_ERR_INT_CLR : 1; /*!< Set this bit to clear theCH6_ERR_INT interrupt. */ - __OM uint32_t RX_CH7_ERR_INT_CLR : 1; /*!< Set this bit to clear theCH7_ERR_INT interrupt. */ - __OM uint32_t CH4_RX_THR_EVENT_INT_CLR : 1;/*!< Set this bit to clear theCH4_RX_THR_EVENT_INT interrupt. */ - __OM uint32_t CH5_RX_THR_EVENT_INT_CLR : 1;/*!< Set this bit to clear theCH5_RX_THR_EVENT_INT interrupt. */ - __OM uint32_t CH6_RX_THR_EVENT_INT_CLR : 1;/*!< Set this bit to clear theCH6_RX_THR_EVENT_INT interrupt. */ - __OM uint32_t CH7_RX_THR_EVENT_INT_CLR : 1;/*!< Set this bit to clear theCH7_RX_THR_EVENT_INT interrupt. */ - __OM uint32_t TX_CH3_DMA_ACCESS_FAIL_INT_CLR : 1;/*!< Set this bit to clear the CH3_DMA_ACCESS_FAIL_INT interrupt. */ - __OM uint32_t RX_CH7_DMA_ACCESS_FAIL_INT_CLR : 1;/*!< Set this bit to clear the CH7_DMA_ACCESS_FAIL_INT interrupt. */ - uint32_t : 2; - } bit; - } INT_CLR; - - union { - union { - __IOM uint32_t reg; /*!< Channel 3 status register */ - - struct { - uint32_t : 11; - __IM uint32_t APB_MEM_WADDR_CH0 : 10; /*!< This register records the memory address offset when writes - RAM over APB bus. */ - uint32_t : 4; - __IM uint32_t MEM_EMPTY_CH0 : 1; /*!< This status bit will be set when the data to be set is more - than memory size and the wraparound mode is disabled. */ - __IM uint32_t APB_MEM_WR_ERR_CH0 : 1; /*!< This status bit will be set if the offset address out of memory - size when writes via APB bus. */ - uint32_t : 5; - } bit; - } TX_CH3STATUS; - - union { - __IOM uint32_t reg; /*!< Channel 2 status register */ - - struct { - uint32_t : 11; - __IM uint32_t APB_MEM_RADDR_CH4 : 10; /*!< This register records the memory address offset when reads RAM - over APB bus. */ - uint32_t : 4; - __IM uint32_t MEM_OWNER_ERR_CH4 : 1; /*!< This status bit will be set when the ownership of memory block - is wrong. */ - __IM uint32_t MEM_FULL_CH4 : 1; /*!< This status bit will be set if the receiver receives more data - than the memory size. */ - __IM uint32_t APB_MEM_RD_ERR_CH4 : 1; /*!< This status bit will be set if the offset address out of memory - size when reads via APB bus. */ - uint32_t : 4; - } bit; - } RX_CH2STATUS; - __IOM uint32_t CH0CARRIER_DUTY; /*!< Channel 0 duty cycle configuration register */ - }; - __IM uint32_t RESERVED7[3]; - - union { - union { - __IOM uint32_t reg; /*!< Channel 3 configure register 0 */ - - struct { - uint32_t : 8; - __IOM uint32_t IDLE_THRES_CH4 : 15; /*!< When no edge is detected on the input signal and continuous - clock cycles is longer than this register value, received - process is finished. */ - uint32_t : 9; - } bit; - } RX_CH3CONF0; - - union { - __IOM uint32_t reg; /*!< Channel 3 status register */ - - struct { - uint32_t : 11; - __IM uint32_t APB_MEM_RADDR_CH4 : 10; /*!< This register records the memory address offset when reads RAM - over APB bus. */ - uint32_t : 4; - __IM uint32_t MEM_OWNER_ERR_CH4 : 1; /*!< This status bit will be set when the ownership of memory block - is wrong. */ - __IM uint32_t MEM_FULL_CH4 : 1; /*!< This status bit will be set if the receiver receives more data - than the memory size. */ - __IM uint32_t APB_MEM_RD_ERR_CH4 : 1; /*!< This status bit will be set if the offset address out of memory - size when reads via APB bus. */ - uint32_t : 4; - } bit; - } RX_CH3STATUS; - __IOM uint32_t CH1CARRIER_DUTY; /*!< Channel 1 duty cycle configuration register */ - __IOM uint32_t CH0_RX_CARRIER_RM; /*!< Channel 0 carrier remove register */ - }; - - union { - __IOM uint32_t reg; /*!< Channel 3 configure register 1 */ - - struct { - uint32_t : 5; - __IOM uint32_t RX_FILTER_THRES_CH4 : 8; /*!< Ignores the input pulse when its width is smaller than this - register value in APB clock periods (in receive mode). */ - uint32_t : 1; - __OM uint32_t AFIFO_RST_CH4 : 1; /*!< Reserved */ - uint32_t : 17; - } bit; - } RX_CH3CONF1; - __IM uint32_t RESERVED8[2]; - - union { - __IOM uint32_t CH2CARRIER_DUTY; /*!< Channel 2 duty cycle configuration register */ - __IOM uint32_t CH1_RX_CARRIER_RM; /*!< Channel 1 carrier remove register */ - - union { - __IOM uint32_t reg; /*!< Channel 0 Tx event configuration register */ - - struct { - uint32_t : 9; - __IOM uint32_t TX_LOOP_NUM_CH : 10; /*!< This register is used to configure the maximum loop count when - tx_conti_mode is valid. */ - __IOM uint32_t TX_LOOP_CNT_EN_CH : 1; /*!< This register is the enabled bit for loop count. */ - __OM uint32_t LOOP_COUNT_RESET_CH : 1; /*!< This register is used to reset the loop count when tx_conti_mode - is valid. */ - uint32_t : 11; - } bit; - } CH0_TX_LIM; - }; - __IM uint32_t RESERVED9[3]; - - union { - __IOM uint32_t CH3CARRIER_DUTY; /*!< Channel 3 duty cycle configuration register */ - __IOM uint32_t CH2_RX_CARRIER_RM; /*!< Channel 2 carrier remove register */ - - union { - __IOM uint32_t reg; /*!< Channel 1 Tx event configuration register */ - - struct { - uint32_t : 9; - __IOM uint32_t TX_LOOP_NUM_CH : 10; /*!< This register is used to configure the maximum loop count when - tx_conti_mode is valid. */ - __IOM uint32_t TX_LOOP_CNT_EN_CH : 1; /*!< This register is the enabled bit for loop count. */ - __OM uint32_t LOOP_COUNT_RESET_CH : 1; /*!< This register is used to reset the loop count when tx_conti_mode - is valid. */ - uint32_t : 11; - } bit; - } CH1_TX_LIM; - __IOM uint32_t CH0_RX_LIM; /*!< Channel 0 Rx event configuration register */ - }; - __IM uint32_t RESERVED10[3]; - - union { - __IOM uint32_t CH3_RX_CARRIER_RM; /*!< Channel 3 carrier remove register */ - - union { - __IOM uint32_t reg; /*!< Channel 2 Tx event configuration register */ - - struct { - uint32_t : 9; - __IOM uint32_t TX_LOOP_NUM_CH : 10; /*!< This register is used to configure the maximum loop count when - tx_conti_mode is valid. */ - __IOM uint32_t TX_LOOP_CNT_EN_CH : 1; /*!< This register is the enabled bit for loop count. */ - __OM uint32_t LOOP_COUNT_RESET_CH : 1; /*!< This register is used to reset the loop count when tx_conti_mode - is valid. */ - uint32_t : 11; - } bit; - } CH2_TX_LIM; - __IOM uint32_t CH1_RX_LIM; /*!< Channel 1 Rx event configuration register */ - - union { - __IOM uint32_t reg; /*!< RMT apb configuration register */ - - struct { - __IOM uint32_t APB_FIFO_MASK : 1; /*!< 1'h1: access memory directly. 1'h0: access memory by FIFO. */ - __IOM uint32_t MEM_CLK_FORCE_ON : 1; /*!< Set this bit to enable the clock for RMT memory. */ - __IOM uint32_t MEM_FORCE_PD : 1; /*!< Set this bit to power down RMT memory. */ - __IOM uint32_t MEM_FORCE_PU : 1; /*!< 1: Disable RMT memory light sleep power down function. 0: Power - down RMT memory when RMT is in light sleep mode. */ - __IOM uint32_t SCLK_DIV_NUM : 8; /*!< the integral part of the fractional divisor */ - __IOM uint32_t SCLK_DIV_A : 6; /*!< the numerator of the fractional part of the fractional divisor */ - __IOM uint32_t SCLK_DIV_B : 6; /*!< the denominator of the fractional part of the fractional divisor */ - __IOM uint32_t SCLK_SEL : 2; /*!< choose the clock source of rmt_sclk. 1:CLK_80Mhz.2:CLK_8MHz.3:XTAL */ - __IOM uint32_t SCLK_ACTIVE : 1; /*!< rmt_sclk switch */ - uint32_t : 4; - __IOM uint32_t CLK_EN : 1; /*!< RMT register clock gate enable signal. 1: Power up the drive - clock of registers. 0: Power down the drive clock of registers */ - } bit; - } SYS_CONF; - }; - - union { - __IOM uint32_t reg; /*!< RMT TX synchronous register */ - - struct { - __IOM uint32_t CH0 : 1; /*!< Set this bit to enable CHANNEL0 to start sending data synchronously - with other enabled channels. */ - __IOM uint32_t CH1 : 1; /*!< Set this bit to enable CHANNEL1 to start sending data synchronously - with other enabled channels. */ - __IOM uint32_t CH2 : 1; /*!< Set this bit to enable CHANNEL2 to start sending data synchronously - with other enabled channels. */ - __IOM uint32_t CH3 : 1; /*!< Set this bit to enable CHANNEL3 to start sending data synchronously - with other enabled channels. */ - __IOM uint32_t EN : 1; /*!< This register is used to enable multiple of channels to start - sending data synchronously. */ - uint32_t : 27; - } bit; - } TX_SIM; - - union { - __IOM uint32_t reg; /*!< RMT clock divider reset register */ - - struct { - __OM uint32_t TX_REF_CNT_RST_CH0 : 1; /*!< This register is used to reset the clock divider of CHANNEL0. */ - __OM uint32_t TX_REF_CNT_RST_CH1 : 1; /*!< This register is used to reset the clock divider of CHANNEL1. */ - __OM uint32_t TX_REF_CNT_RST_CH2 : 1; /*!< This register is used to reset the clock divider of CHANNEL2. */ - __OM uint32_t TX_REF_CNT_RST_CH3 : 1; /*!< This register is used to reset the clock divider of CHANNEL3. */ - __OM uint32_t RX_REF_CNT_RST_CH4 : 1; /*!< This register is used to reset the clock divider of CHANNEL4. */ - __OM uint32_t RX_REF_CNT_RST_CH5 : 1; /*!< This register is used to reset the clock divider of CHANNEL5. */ - __OM uint32_t RX_REF_CNT_RST_CH6 : 1; /*!< This register is used to reset the clock divider of CHANNEL6. */ - __OM uint32_t RX_REF_CNT_RST_CH7 : 1; /*!< This register is used to reset the clock divider of CHANNEL7. */ - uint32_t : 24; - } bit; - } REF_CNT_RST; - - union { - __IOM uint32_t reg; /*!< RMT version register */ - - struct { - __IOM uint32_t DATE : 28; /*!< This is the version register. */ - uint32_t : 4; - } bit; - } DATE; - - union { - union { - __IOM uint32_t reg; /*!< Channel 3 Tx event configuration register */ - - struct { - uint32_t : 9; - __IOM uint32_t TX_LOOP_NUM_CH : 10; /*!< This register is used to configure the maximum loop count when - tx_conti_mode is valid. */ - __IOM uint32_t TX_LOOP_CNT_EN_CH : 1; /*!< This register is the enabled bit for loop count. */ - __OM uint32_t LOOP_COUNT_RESET_CH : 1; /*!< This register is used to reset the loop count when tx_conti_mode - is valid. */ - uint32_t : 11; - } bit; - } CH3_TX_LIM; - __IOM uint32_t CH2_RX_LIM; /*!< Channel 2 Rx event configuration register */ - }; - __IM uint32_t RESERVED11[3]; - __IOM uint32_t CH3_RX_LIM; /*!< Channel 3 Rx event configuration register */ -} RMT_Type; /*!< Size = 228 (0xe4) */ - - - -/* =========================================================================================================================== */ -/* ================ RSA ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief RSA (Rivest Shamir Adleman) Accelerator (RSA) - */ - -typedef struct { /*!< RSA Structure */ - __IOM uint32_t M_MEM[4]; /*!< Represents M */ - __IM uint32_t RESERVED[124]; - __IOM uint32_t Z_MEM[4]; /*!< Represents Z */ - __IM uint32_t RESERVED1[124]; - __IOM uint32_t Y_MEM[4]; /*!< Represents Y */ - __IM uint32_t RESERVED2[124]; - __IOM uint32_t X_MEM[4]; /*!< Represents X */ - __IM uint32_t RESERVED3[124]; - - union { - __IOM uint32_t reg; /*!< Represents M’ */ - - struct { - __IOM uint32_t M_PRIME : 32; /*!< Represents M’ */ - } bit; - } M_PRIME; - - union { - __IOM uint32_t reg; /*!< Configures RSA length */ - - struct { - __IOM uint32_t MODE : 7; /*!< Configures the RSA length. */ - uint32_t : 25; - } bit; - } MODE; - - union { - __IOM uint32_t reg; /*!< RSA clean register */ - - struct { - __IM uint32_t QUERY_CLEAN : 1; /*!< Represents whether or not the RSA memory completes initialization.0: - Not complete1: Completed */ - uint32_t : 31; - } bit; - } QUERY_CLEAN; - - union { - __IOM uint32_t reg; /*!< Starts modular exponentiation */ - - struct { - __OM uint32_t SET_START_MODEXP : 1; /*!< Configure whether or not to start the modular exponentiation.0: - No effect1: Start */ - uint32_t : 31; - } bit; - } SET_START_MODEXP; - - union { - __IOM uint32_t reg; /*!< Starts modular multiplication */ - - struct { - __OM uint32_t SET_START_MODMULT : 1; /*!< Configure whether or not to start the modular multiplication.0: - No effect1: Start */ - uint32_t : 31; - } bit; - } SET_START_MODMULT; - - union { - __IOM uint32_t reg; /*!< Starts multiplication */ - - struct { - __OM uint32_t SET_START_MULT : 1; /*!< Configure whether or not to start the multiplication.0: No effect1: - Start */ - uint32_t : 31; - } bit; - } SET_START_MULT; - - union { - __IOM uint32_t reg; /*!< Represents the RSA status */ - - struct { - __IM uint32_t QUERY_IDLE : 1; /*!< Represents the RSA status.0: Busy1: Idle */ - uint32_t : 31; - } bit; - } QUERY_IDLE; - - union { - __IOM uint32_t reg; /*!< Clears RSA interrupt */ - - struct { - __OM uint32_t CLEAR_INTERRUPT : 1; /*!< Write 1 to clear the RSA interrupt. */ - uint32_t : 31; - } bit; - } INT_CLR; - - union { - __IOM uint32_t reg; /*!< Configures the constant_time option */ - - struct { - __IOM uint32_t CONSTANT_TIME : 1; /*!< Configures the constant_time option. 0: Acceleration1: No acceleration - (default) */ - uint32_t : 31; - } bit; - } CONSTANT_TIME; - - union { - __IOM uint32_t reg; /*!< Configures the search option */ - - struct { - __IOM uint32_t SEARCH_ENABLE : 1; /*!< Configure the search option. 0: No acceleration (default)1: - AccelerationThis option should be used together with RSA_SEARCH_POS. */ - uint32_t : 31; - } bit; - } SEARCH_ENABLE; - - union { - __IOM uint32_t reg; /*!< Configures the search position */ - - struct { - __IOM uint32_t SEARCH_POS : 12; /*!< Configures the starting address to start search. This field - should be used together with RSA_SEARCH_ENABLE. The field - is only valid when RSA_SEARCH_ENABLE is high. */ - uint32_t : 20; - } bit; - } SEARCH_POS; - - union { - __IOM uint32_t reg; /*!< Enables the RSA interrupt */ - - struct { - __IOM uint32_t INT_ENA : 1; /*!< Write 1 to enable the RSA interrupt. */ - uint32_t : 31; - } bit; - } INT_ENA; - - union { - __IOM uint32_t reg; /*!< Version control register */ - - struct { - __IOM uint32_t DATE : 30; /*!< Version control register. */ - uint32_t : 2; - } bit; - } DATE; -} RSA_Type; /*!< Size = 2100 (0x834) */ - - - -/* =========================================================================================================================== */ -/* ================ LP_ADC ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Low-power Analog to Digital Converter (LP_ADC) - */ - -typedef struct { /*!< LP_ADC Structure */ - - union { - __IOM uint32_t reg; /*!< Control the read operation of ADC1. */ - - struct { - __IOM uint32_t SAR1_CLK_DIV : 8; /*!< Clock divider. */ - uint32_t : 10; - __IOM uint32_t SAR1_CLK_GATED : 1; /*!< N/A */ - __IOM uint32_t SAR1_SAMPLE_NUM : 8; /*!< N/A */ - uint32_t : 1; - __IOM uint32_t SAR1_DATA_INV : 1; /*!< Invert SAR ADC1 data. */ - __IOM uint32_t SAR1_INT_EN : 1; /*!< Enable saradc1 to send out interrupt. */ - __IOM uint32_t SAR1_EN_PAD_FORCE_ENABLE : 2;/*!< Force enable adc en_pad to analog circuit 2'b11: force enable - . */ - } bit; - } READER1_CTRL; - - union { - __IOM uint32_t reg; /*!< N/A */ - - struct { - __IM uint32_t SAR1_READER_STATUS : 32; /*!< N/A */ - } bit; - } READER1_STATUS; - - union { - __IOM uint32_t reg; /*!< N/A */ - - struct { - uint32_t : 24; - __IOM uint32_t FORCE_XPD_AMP : 2; /*!< N/A */ - __IOM uint32_t AMP_RST_FB_FORCE : 2; /*!< N/A */ - __IOM uint32_t AMP_SHORT_REF_FORCE : 2; /*!< N/A */ - __IOM uint32_t AMP_SHORT_REF_GND_FORCE : 2;/*!< N/A */ - } bit; - } MEAS1_CTRL1; - - union { - __IOM uint32_t reg; /*!< ADC1 configuration registers. */ - - struct { - __IM uint32_t MEAS1_DATA_SAR : 16; /*!< SAR ADC1 data. */ - __IM uint32_t MEAS1_DONE_SAR : 1; /*!< SAR ADC1 conversion done indication. */ - __IOM uint32_t MEAS1_START_SAR : 1; /*!< SAR ADC1 controller (in RTC) starts conversion. */ - __IOM uint32_t MEAS1_START_FORCE : 1; /*!< 1: SAR ADC1 controller (in RTC) is started by SW. */ - __IOM uint32_t SAR1_EN_PAD : 12; /*!< SAR ADC1 pad enable bitmap. */ - __IOM uint32_t SAR1_EN_PAD_FORCE : 1; /*!< 1: SAR ADC1 pad enable bitmap is controlled by SW. */ - } bit; - } MEAS1_CTRL2; - - union { - __IOM uint32_t reg; /*!< SAR ADC1 MUX register. */ - - struct { - uint32_t : 31; - __IOM uint32_t SAR1_DIG_FORCE : 1; /*!< 1: SAR ADC1 controlled by DIG ADC1 CTRL. */ - } bit; - } MEAS1_MUX; - - union { - __IOM uint32_t reg; /*!< ADC1 attenuation registers. */ - - struct { - __IOM uint32_t SAR1_ATTEN : 32; /*!< 2-bit attenuation for each pad. */ - } bit; - } ATTEN1; - - union { - __IOM uint32_t reg; /*!< N/A */ - - struct { - __IOM uint32_t SAR_AMP_WAIT1 : 16; /*!< N/A */ - __IOM uint32_t SAR_AMP_WAIT2 : 16; /*!< N/A */ - } bit; - } AMP_CTRL1; - - union { - __IOM uint32_t reg; /*!< N/A */ - - struct { - __IOM uint32_t SAR1_DAC_XPD_FSM_IDLE : 1; /*!< N/A */ - __IOM uint32_t XPD_SAR_AMP_FSM_IDLE : 1; /*!< N/A */ - __IOM uint32_t AMP_RST_FB_FSM_IDLE : 1; /*!< N/A */ - __IOM uint32_t AMP_SHORT_REF_FSM_IDLE : 1;/*!< N/A */ - __IOM uint32_t AMP_SHORT_REF_GND_FSM_IDLE : 1;/*!< N/A */ - __IOM uint32_t XPD_SAR_FSM_IDLE : 1; /*!< N/A */ - __IOM uint32_t SAR_RSTB_FSM_IDLE : 1; /*!< N/A */ - uint32_t : 9; - __IOM uint32_t SAR_AMP_WAIT3 : 16; /*!< N/A */ - } bit; - } AMP_CTRL2; - - union { - __IOM uint32_t reg; /*!< N/A */ - - struct { - __IOM uint32_t SAR1_DAC_XPD_FSM : 4; /*!< N/A */ - __IOM uint32_t XPD_SAR_AMP_FSM : 4; /*!< N/A */ - __IOM uint32_t AMP_RST_FB_FSM : 4; /*!< N/A */ - __IOM uint32_t AMP_SHORT_REF_FSM : 4; /*!< N/A */ - __IOM uint32_t AMP_SHORT_REF_GND_FSM : 4; /*!< N/A */ - __IOM uint32_t XPD_SAR_FSM : 4; /*!< N/A */ - __IOM uint32_t SAR_RSTB_FSM : 4; /*!< N/A */ - uint32_t : 4; - } bit; - } AMP_CTRL3; - - union { - __IOM uint32_t reg; /*!< Control the read operation of ADC2. */ - - struct { - __IOM uint32_t SAR2_CLK_DIV : 8; /*!< Clock divider. */ - uint32_t : 8; - __IOM uint32_t SAR2_WAIT_ARB_CYCLE : 2; /*!< Wait arbit stable after sar_done. */ - __IOM uint32_t SAR2_CLK_GATED : 1; /*!< N/A */ - __IOM uint32_t SAR2_SAMPLE_NUM : 8; /*!< N/A */ - __IOM uint32_t SAR2_EN_PAD_FORCE_ENABLE : 2;/*!< Force enable adc en_pad to analog circuit 2'b11: force enable - . */ - __IOM uint32_t SAR2_DATA_INV : 1; /*!< Invert SAR ADC2 data. */ - __IOM uint32_t SAR2_INT_EN : 1; /*!< Enable saradc2 to send out interrupt. */ - uint32_t : 1; - } bit; - } READER2_CTRL; - - union { - __IOM uint32_t reg; /*!< N/A */ - - struct { - __IM uint32_t SAR2_READER_STATUS : 32; /*!< N/A */ - } bit; - } READER2_STATUS; - - union { - __IOM uint32_t reg; /*!< ADC2 configuration registers. */ - - struct { - __IM uint32_t SAR2_CNTL_STATE : 3; /*!< saradc2_cntl_fsm. */ - __IOM uint32_t SAR2_PWDET_CAL_EN : 1; /*!< RTC control pwdet enable. */ - __IOM uint32_t SAR2_PKDET_CAL_EN : 1; /*!< RTC control pkdet enable. */ - __IOM uint32_t SAR2_EN_TEST : 1; /*!< SAR2_EN_TEST. */ - __IOM uint32_t SAR2_RSTB_FORCE : 2; /*!< N/A */ - __IOM uint32_t SAR2_STANDBY_WAIT : 8; /*!< N/A */ - __IOM uint32_t SAR2_RSTB_WAIT : 8; /*!< N/A */ - __IOM uint32_t SAR2_XPD_WAIT : 8; /*!< N/A */ - } bit; - } MEAS2_CTRL1; - - union { - __IOM uint32_t reg; /*!< ADC2 configuration registers. */ - - struct { - __IM uint32_t MEAS2_DATA_SAR : 16; /*!< SAR ADC2 data. */ - __IM uint32_t MEAS2_DONE_SAR : 1; /*!< SAR ADC2 conversion done indication. */ - __IOM uint32_t MEAS2_START_SAR : 1; /*!< SAR ADC2 controller (in RTC) starts conversion. */ - __IOM uint32_t MEAS2_START_FORCE : 1; /*!< 1: SAR ADC2 controller (in RTC) is started by SW. */ - __IOM uint32_t SAR2_EN_PAD : 12; /*!< SAR ADC2 pad enable bitmap. */ - __IOM uint32_t SAR2_EN_PAD_FORCE : 1; /*!< 1: SAR ADC2 pad enable bitmap is controlled by SW. */ - } bit; - } MEAS2_CTRL2; - - union { - __IOM uint32_t reg; /*!< SAR ADC2 MUX register. */ - - struct { - uint32_t : 28; - __IOM uint32_t SAR2_PWDET_CCT : 3; /*!< SAR2_PWDET_CCT. */ - __IOM uint32_t SAR2_RTC_FORCE : 1; /*!< In sleep, force to use rtc to control ADC. */ - } bit; - } MEAS2_MUX; - - union { - __IOM uint32_t reg; /*!< ADC1 attenuation registers. */ - - struct { - __IOM uint32_t SAR2_ATTEN : 32; /*!< 2-bit attenuation for each pad. */ - } bit; - } ATTEN2; - - union { - __IOM uint32_t reg; /*!< In sleep, force to use rtc to control ADC */ - - struct { - __IOM uint32_t FORCE_XPD_SAR1 : 2; /*!< 2'b11:software control, force on. 2'b10:software control, force - off. 2'b0x:hardware control. */ - __IOM uint32_t FORCE_XPD_SAR2 : 2; /*!< 2'b11:software control, force on. 2'b10:software control, force - off. 2'b0x:hardware control. */ - uint32_t : 28; - } bit; - } FORCE_WPD_SAR; - - union { - __IOM uint32_t reg; /*!< N/A */ - - struct { - __IM uint32_t SARADC_MEAS_STATUS : 8; /*!< N/A */ - uint32_t : 24; - } bit; - } MEAS_STATUS; - - union { - __IOM uint32_t reg; /*!< N/A */ - - struct { - __IOM uint32_t CLK_EN : 1; /*!< N/A */ - uint32_t : 31; - } bit; - } REG_CLKEN; - - union { - __IOM uint32_t reg; /*!< Interrupt raw registers. */ - - struct { - __IOM uint32_t COCPU_SARADC1_INT_RAW : 1; /*!< ADC1 Conversion is done, int raw. */ - __IOM uint32_t COCPU_SARADC2_INT_RAW : 1; /*!< ADC2 Conversion is done, int raw. */ - __IOM uint32_t COCPU_SARADC1_ERROR_INT_RAW : 1;/*!< An errro occurs from ADC1, int raw. */ - __IOM uint32_t COCPU_SARADC2_ERROR_INT_RAW : 1;/*!< An errro occurs from ADC2, int raw. */ - __IOM uint32_t COCPU_SARADC1_WAKE_INT_RAW : 1;/*!< A wakeup event is triggered from ADC1, int raw. */ - __IOM uint32_t COCPU_SARADC2_WAKE_INT_RAW : 1;/*!< A wakeup event is triggered from ADC2, int raw. */ - uint32_t : 26; - } bit; - } COCPU_INT_RAW; - - union { - __IOM uint32_t reg; /*!< Interrupt enable registers. */ - - struct { - __IOM uint32_t COCPU_SARADC1_INT_ENA : 1; /*!< ADC1 Conversion is done, int enable. */ - __IOM uint32_t COCPU_SARADC2_INT_ENA : 1; /*!< ADC2 Conversion is done, int enable. */ - __IOM uint32_t COCPU_SARADC1_ERROR_INT_ENA : 1;/*!< An errro occurs from ADC1, int enable. */ - __IOM uint32_t COCPU_SARADC2_ERROR_INT_ENA : 1;/*!< An errro occurs from ADC2, int enable. */ - __IOM uint32_t COCPU_SARADC1_WAKE_INT_ENA : 1;/*!< A wakeup event is triggered from ADC1, int enable. */ - __IOM uint32_t COCPU_SARADC2_WAKE_INT_ENA : 1;/*!< A wakeup event is triggered from ADC2, int enable. */ - uint32_t : 26; - } bit; - } INT_ENA; - - union { - __IOM uint32_t reg; /*!< Interrupt status registers. */ - - struct { - __IM uint32_t COCPU_SARADC1_INT_ST : 1; /*!< ADC1 Conversion is done, int status. */ - __IM uint32_t COCPU_SARADC2_INT_ST : 1; /*!< ADC2 Conversion is done, int status. */ - __IM uint32_t COCPU_SARADC1_ERROR_INT_ST : 1;/*!< An errro occurs from ADC1, int status. */ - __IM uint32_t COCPU_SARADC2_ERROR_INT_ST : 1;/*!< An errro occurs from ADC2, int status. */ - __IM uint32_t COCPU_SARADC1_WAKE_INT_ST : 1;/*!< A wakeup event is triggered from ADC1, int status. */ - __IM uint32_t COCPU_SARADC2_WAKE_INT_ST : 1;/*!< A wakeup event is triggered from ADC2, int status. */ - uint32_t : 26; - } bit; - } INT_ST; - - union { - __IOM uint32_t reg; /*!< Interrupt clear registers. */ - - struct { - __OM uint32_t COCPU_SARADC1_INT_CLR : 1; /*!< ADC1 Conversion is done, int clear. */ - __OM uint32_t COCPU_SARADC2_INT_CLR : 1; /*!< ADC2 Conversion is done, int clear. */ - __OM uint32_t COCPU_SARADC1_ERROR_INT_CLR : 1;/*!< An errro occurs from ADC1, int clear. */ - __OM uint32_t COCPU_SARADC2_ERROR_INT_CLR : 1;/*!< An errro occurs from ADC2, int clear. */ - __OM uint32_t COCPU_SARADC1_WAKE_INT_CLR : 1;/*!< A wakeup event is triggered from ADC1, int clear. */ - __OM uint32_t COCPU_SARADC2_WAKE_INT_CLR : 1;/*!< A wakeup event is triggered from ADC2, int clear. */ - uint32_t : 26; - } bit; - } INT_CLR; - - union { - __IOM uint32_t reg; /*!< Interrupt enable assert registers. */ - - struct { - __OM uint32_t COCPU_SARADC1_INT_ENA_W1TS : 1;/*!< ADC1 Conversion is done, write 1 to assert int enable. */ - __OM uint32_t COCPU_SARADC2_INT_ENA_W1TS : 1;/*!< ADC2 Conversion is done, write 1 to assert int enable. */ - __OM uint32_t COCPU_SARADC1_ERROR_INT_ENA_W1TS : 1;/*!< An errro occurs from ADC1, write 1 to assert int enable. */ - __OM uint32_t COCPU_SARADC2_ERROR_INT_ENA_W1TS : 1;/*!< An errro occurs from ADC2, write 1 to assert int enable. */ - __OM uint32_t COCPU_SARADC1_WAKE_INT_ENA_W1TS : 1;/*!< A wakeup event is triggered from ADC1, write 1 to assert int - enable. */ - __OM uint32_t COCPU_SARADC2_WAKE_INT_ENA_W1TS : 1;/*!< A wakeup event is triggered from ADC2, write 1 to assert int - enable. */ - uint32_t : 26; - } bit; - } INT_ENA_W1TS; - - union { - __IOM uint32_t reg; /*!< Interrupt enable deassert registers. */ - - struct { - __OM uint32_t COCPU_SARADC1_INT_ENA_W1TC : 1;/*!< ADC1 Conversion is done, write 1 to deassert int enable. */ - __OM uint32_t COCPU_SARADC2_INT_ENA_W1TC : 1;/*!< ADC2 Conversion is done, write 1 to deassert int enable. */ - __OM uint32_t COCPU_SARADC1_ERROR_INT_ENA_W1TC : 1;/*!< An errro occurs from ADC1, write 1 to deassert int enable. */ - __OM uint32_t COCPU_SARADC2_ERROR_INT_ENA_W1TC : 1;/*!< An errro occurs from ADC2, write 1 to deassert int enable. */ - __OM uint32_t COCPU_SARADC1_WAKE_INT_ENA_W1TC : 1;/*!< A wakeup event is triggered from ADC1, write 1 to deassert int - enable. */ - __OM uint32_t COCPU_SARADC2_WAKE_INT_ENA_W1TC : 1;/*!< A wakeup event is triggered from ADC2, write 1 to deassert int - enable. */ - uint32_t : 26; - } bit; - } INT_ENA_W1TC; - - union { - __IOM uint32_t reg; /*!< ADC1 wakeup configuration registers. */ - - struct { - __IOM uint32_t SAR1_WAKEUP_TH_LOW : 12; /*!< Lower threshold. */ - uint32_t : 2; - __IOM uint32_t SAR1_WAKEUP_TH_HIGH : 12; /*!< Upper threshold. */ - uint32_t : 3; - __IM uint32_t SAR1_WAKEUP_OVER_UPPER_TH : 1;/*!< Indicates that this wakeup event arose from exceeding upper - threshold. */ - __IOM uint32_t SAR1_WAKEUP_EN : 1; /*!< Wakeup function enable. */ - __IOM uint32_t SAR1_WAKEUP_MODE : 1; /*!< 0:absolute value comparison mode. 1: relative value comparison - mode. */ - } bit; - } WAKEUP1; - - union { - __IOM uint32_t reg; /*!< ADC2 wakeup configuration registers. */ - - struct { - __IOM uint32_t SAR2_WAKEUP_TH_LOW : 12; /*!< Lower threshold. */ - uint32_t : 2; - __IOM uint32_t SAR2_WAKEUP_TH_HIGH : 12; /*!< Upper threshold. */ - uint32_t : 3; - __IM uint32_t SAR2_WAKEUP_OVER_UPPER_TH : 1;/*!< Indicates that this wakeup event arose from exceeding upper - threshold. */ - __IOM uint32_t SAR2_WAKEUP_EN : 1; /*!< Wakeup function enable. */ - __IOM uint32_t SAR2_WAKEUP_MODE : 1; /*!< 0:absolute value comparison mode. 1: relative value comparison - mode. */ - } bit; - } WAKEUP2; - - union { - __IOM uint32_t reg; /*!< Wakeup source select register. */ - - struct { - __IOM uint32_t SAR_WAKEUP_SEL : 1; /*!< 0: ADC1. 1: ADC2. */ - uint32_t : 31; - } bit; - } WAKEUP_SEL; - - union { - __IOM uint32_t reg; /*!< Hardware automatic sampling registers for wakeup function. */ - - struct { - __IOM uint32_t ADC1_HW_READ_EN_I : 1; /*!< Enable hardware automatic sampling. */ - __IOM uint32_t ADC1_HW_READ_RATE_I : 16; /*!< Hardware automatic sampling rate. */ - uint32_t : 15; - } bit; - } SAR1_HW_WAKEUP; - - union { - __IOM uint32_t reg; /*!< Hardware automatic sampling registers for wakeup function. */ - - struct { - __IOM uint32_t ADC2_HW_READ_EN_I : 1; /*!< Enable hardware automatic sampling. */ - __IOM uint32_t ADC2_HW_READ_RATE_I : 16; /*!< Hardware automatic sampling rate. */ - uint32_t : 15; - } bit; - } SAR2_HW_WAKEUP; - - union { - __IOM uint32_t reg; /*!< N/A */ - - struct { - __IOM uint32_t RND_ECO_LOW : 32; /*!< N/A */ - } bit; - } RND_ECO_LOW; - - union { - __IOM uint32_t reg; /*!< N/A */ - - struct { - __IOM uint32_t RND_ECO_HIGH : 32; /*!< N/A */ - } bit; - } RND_ECO_HIGH; - - union { - __IOM uint32_t reg; /*!< N/A */ - - struct { - __IOM uint32_t RND_ECO_EN : 1; /*!< N/A */ - __IM uint32_t RND_ECO_RESULT : 1; /*!< N/A */ - uint32_t : 30; - } bit; - } RND_ECO_CS; -} LP_ADC_Type; /*!< Size = 128 (0x80) */ - - - -/* =========================================================================================================================== */ -/* ================ LP_TIMER ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Low-power Timer (LP_TIMER) - */ - -typedef struct { /*!< LP_TIMER Structure */ - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t MAIN_TIMER_TAR_LOW0 : 32; /*!< need_des */ - } bit; - } TAR0_LOW; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t MAIN_TIMER_TAR_HIGH0 : 16; /*!< need_des */ - uint32_t : 15; - __OM uint32_t MAIN_TIMER_TAR_EN0 : 1; /*!< need_des */ - } bit; - } TAR0_HIGH; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t MAIN_TIMER_TAR_LOW1 : 32; /*!< need_des */ - } bit; - } TAR1_LOW; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t MAIN_TIMER_TAR_HIGH1 : 16; /*!< need_des */ - uint32_t : 15; - __OM uint32_t MAIN_TIMER_TAR_EN1 : 1; /*!< need_des */ - } bit; - } TAR1_HIGH; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 28; - __OM uint32_t MAIN_TIMER_UPDATE : 1; /*!< need_des */ - __IOM uint32_t MAIN_TIMER_XTAL_OFF : 1; /*!< need_des */ - __IOM uint32_t MAIN_TIMER_SYS_STALL : 1; /*!< need_des */ - __IOM uint32_t MAIN_TIMER_SYS_RST : 1; /*!< need_des */ - } bit; - } UPDATE; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IM uint32_t MAIN_TIMER_BUF0_LOW : 32; /*!< need_des */ - } bit; - } MAIN_BUF0_LOW; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IM uint32_t MAIN_TIMER_BUF0_HIGH : 16; /*!< need_des */ - uint32_t : 16; - } bit; - } MAIN_BUF0_HIGH; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IM uint32_t MAIN_TIMER_BUF1_LOW : 32; /*!< need_des */ - } bit; - } MAIN_BUF1_LOW; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IM uint32_t MAIN_TIMER_BUF1_HIGH : 16; /*!< need_des */ - uint32_t : 16; - } bit; - } MAIN_BUF1_HIGH; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 31; - __OM uint32_t MAIN_TIMER_ALARM_LOAD : 1; /*!< need_des */ - } bit; - } MAIN_OVERFLOW; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 30; - __IOM uint32_t OVERFLOW_RAW : 1; /*!< need_des */ - __IOM uint32_t SOC_WAKEUP_INT_RAW : 1; /*!< need_des */ - } bit; - } INT_RAW; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 30; - __IM uint32_t OVERFLOW_ST : 1; /*!< need_des */ - __IM uint32_t SOC_WAKEUP_INT_ST : 1; /*!< need_des */ - } bit; - } INT_ST; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 30; - __IOM uint32_t OVERFLOW_ENA : 1; /*!< need_des */ - __IOM uint32_t SOC_WAKEUP_INT_ENA : 1; /*!< need_des */ - } bit; - } INT_ENA; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 30; - __OM uint32_t OVERFLOW_CLR : 1; /*!< need_des */ - __OM uint32_t SOC_WAKEUP_INT_CLR : 1; /*!< need_des */ - } bit; - } INT_CLR; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 30; - __IOM uint32_t MAIN_TIMER_OVERFLOW_LP_INT_RAW : 1;/*!< need_des */ - __IOM uint32_t MAIN_TIMER_LP_INT_RAW : 1; /*!< need_des */ - } bit; - } LP_INT_RAW; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 30; - __IM uint32_t MAIN_TIMER_OVERFLOW_LP_INT_ST : 1;/*!< need_des */ - __IM uint32_t MAIN_TIMER_LP_INT_ST : 1; /*!< need_des */ - } bit; - } LP_INT_ST; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 30; - __IOM uint32_t MAIN_TIMER_OVERFLOW_LP_INT_ENA : 1;/*!< need_des */ - __IOM uint32_t MAIN_TIMER_LP_INT_ENA : 1; /*!< need_des */ - } bit; - } LP_INT_ENA; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 30; - __OM uint32_t MAIN_TIMER_OVERFLOW_LP_INT_CLR : 1;/*!< need_des */ - __OM uint32_t MAIN_TIMER_LP_INT_CLR : 1; /*!< need_des */ - } bit; - } LP_INT_CLR; - __IM uint32_t RESERVED[237]; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t DATE : 31; /*!< need_des */ - __IOM uint32_t CLK_EN : 1; /*!< need_des */ - } bit; - } DATE; -} LP_TIMER_Type; /*!< Size = 1024 (0x400) */ - - - -/* =========================================================================================================================== */ -/* ================ LP_TOUCH ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief LP_TOUCH Peripheral (LP_TOUCH) - */ - -typedef struct { /*!< LP_TOUCH Structure */ - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t SCAN_DONE_INT_RAW : 1; /*!< need_des */ - __IOM uint32_t DONE_INT_RAW : 1; /*!< need_des */ - __IOM uint32_t ACTIVE_INT_RAW : 1; /*!< need_des */ - __IOM uint32_t INACTIVE_INT_RAW : 1; /*!< need_des */ - __IOM uint32_t TIMEOUT_INT_RAW : 1; /*!< need_des */ - __IOM uint32_t APPROACH_LOOP_DONE_INT_RAW : 1;/*!< need_des */ - uint32_t : 26; - } bit; - } INT_RAW; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IM uint32_t SCAN_DONE_INT_ST : 1; /*!< need_des */ - __IM uint32_t DONE_INT_ST : 1; /*!< need_des */ - __IM uint32_t ACTIVE_INT_ST : 1; /*!< need_des */ - __IM uint32_t INACTIVE_INT_ST : 1; /*!< need_des */ - __IM uint32_t TIMEOUT_INT_ST : 1; /*!< need_des */ - __IM uint32_t APPROACH_LOOP_DONE_INT_ST : 1;/*!< need_des */ - uint32_t : 26; - } bit; - } INT_ST; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t SCAN_DONE_INT_ENA : 1; /*!< need_des */ - __IOM uint32_t DONE_INT_ENA : 1; /*!< need_des */ - __IOM uint32_t ACTIVE_INT_ENA : 1; /*!< need_des */ - __IOM uint32_t INACTIVE_INT_ENA : 1; /*!< need_des */ - __IOM uint32_t TIMEOUT_INT_ENA : 1; /*!< need_des */ - __IOM uint32_t APPROACH_LOOP_DONE_INT_ENA : 1;/*!< need_des */ - uint32_t : 26; - } bit; - } INT_ENA; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __OM uint32_t SCAN_DONE_INT_CLR : 1; /*!< need_des */ - __OM uint32_t DONE_INT_CLR : 1; /*!< need_des */ - __OM uint32_t ACTIVE_INT_CLR : 1; /*!< need_des */ - __OM uint32_t INACTIVE_INT_CLR : 1; /*!< need_des */ - __OM uint32_t TIMEOUT_INT_CLR : 1; /*!< need_des */ - __OM uint32_t APPROACH_LOOP_DONE_INT_CLR : 1;/*!< need_des */ - uint32_t : 26; - } bit; - } INT_CLR; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IM uint32_t PAD_ACTIVE : 15; /*!< need_des */ - __IM uint32_t MEAS_DONE : 1; /*!< need_des */ - __IM uint32_t SCAN_CURR : 4; /*!< need_des */ - uint32_t : 12; - } bit; - } CHN_STATUS; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IM uint32_t PAD0_DATA : 16; /*!< need_des */ - __IM uint32_t PAD0_DEBOUNCE_CNT : 3; /*!< need_des */ - __IM uint32_t PAD0_NEG_NOISE_CNT : 4; /*!< need_des */ - uint32_t : 9; - } bit; - } STATUS_0; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IM uint32_t PAD1_DATA : 16; /*!< need_des */ - __IM uint32_t PAD1_DEBOUNCE_CNT : 3; /*!< need_des */ - __IM uint32_t PAD1_NEG_NOISE_CNT : 4; /*!< need_des */ - uint32_t : 9; - } bit; - } STATUS_1; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IM uint32_t PAD2_DATA : 16; /*!< need_des */ - __IM uint32_t PAD2_DEBOUNCE_CNT : 3; /*!< need_des */ - __IM uint32_t PAD2_NEG_NOISE_CNT : 4; /*!< need_des */ - uint32_t : 9; - } bit; - } STATUS_2; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IM uint32_t PAD3_DATA : 16; /*!< need_des */ - __IM uint32_t PAD3_DEBOUNCE_CNT : 3; /*!< need_des */ - __IM uint32_t PAD3_NEG_NOISE_CNT : 4; /*!< need_des */ - uint32_t : 9; - } bit; - } STATUS_3; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IM uint32_t PAD4_DATA : 16; /*!< need_des */ - __IM uint32_t PAD4_DEBOUNCE_CNT : 3; /*!< need_des */ - __IM uint32_t PAD4_NEG_NOISE_CNT : 4; /*!< need_des */ - uint32_t : 9; - } bit; - } STATUS_4; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IM uint32_t PAD5_DATA : 16; /*!< need_des */ - __IM uint32_t PAD5_DEBOUNCE_CNT : 3; /*!< need_des */ - __IM uint32_t PAD5_NEG_NOISE_CNT : 4; /*!< need_des */ - uint32_t : 9; - } bit; - } STATUS_5; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IM uint32_t PAD6_DATA : 16; /*!< need_des */ - __IM uint32_t PAD6_DEBOUNCE_CNT : 3; /*!< need_des */ - __IM uint32_t PAD6_NEG_NOISE_CNT : 4; /*!< need_des */ - uint32_t : 9; - } bit; - } STATUS_6; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IM uint32_t PAD7_DATA : 16; /*!< need_des */ - __IM uint32_t PAD7_DEBOUNCE_CNT : 3; /*!< need_des */ - __IM uint32_t PAD7_NEG_NOISE_CNT : 4; /*!< need_des */ - uint32_t : 9; - } bit; - } STATUS_7; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IM uint32_t PAD8_DATA : 16; /*!< need_des */ - __IM uint32_t PAD8_DEBOUNCE_CNT : 3; /*!< need_des */ - __IM uint32_t PAD8_NEG_NOISE_CNT : 4; /*!< need_des */ - uint32_t : 9; - } bit; - } STATUS_8; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IM uint32_t PAD9_DATA : 16; /*!< need_des */ - __IM uint32_t PAD9_DEBOUNCE_CNT : 3; /*!< need_des */ - __IM uint32_t PAD9_NEG_NOISE_CNT : 4; /*!< need_des */ - uint32_t : 9; - } bit; - } STATUS_9; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IM uint32_t PAD10_DATA : 16; /*!< need_des */ - __IM uint32_t PAD10_DEBOUNCE_CNT : 3; /*!< need_des */ - __IM uint32_t PAD10_NEG_NOISE_CNT : 4; /*!< need_des */ - uint32_t : 9; - } bit; - } STATUS_10; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IM uint32_t PAD11_DATA : 16; /*!< need_des */ - __IM uint32_t PAD11_DEBOUNCE_CNT : 3; /*!< need_des */ - __IM uint32_t PAD11_NEG_NOISE_CNT : 4; /*!< need_des */ - uint32_t : 9; - } bit; - } STATUS_11; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IM uint32_t PAD12_DATA : 16; /*!< need_des */ - __IM uint32_t PAD12_DEBOUNCE_CNT : 3; /*!< need_des */ - __IM uint32_t PAD12_NEG_NOISE_CNT : 4; /*!< need_des */ - uint32_t : 9; - } bit; - } STATUS_12; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IM uint32_t PAD13_DATA : 16; /*!< need_des */ - __IM uint32_t PAD13_DEBOUNCE_CNT : 3; /*!< need_des */ - __IM uint32_t PAD13_NEG_NOISE_CNT : 4; /*!< need_des */ - uint32_t : 9; - } bit; - } STATUS_13; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IM uint32_t PAD14_DATA : 16; /*!< need_des */ - __IM uint32_t PAD14_DEBOUNCE_CNT : 3; /*!< need_des */ - __IM uint32_t PAD14_NEG_NOISE_CNT : 4; /*!< need_des */ - uint32_t : 9; - } bit; - } STATUS_14; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IM uint32_t SLP_DATA : 16; /*!< need_des */ - __IM uint32_t SLP_DEBOUNCE_CNT : 3; /*!< need_des */ - __IM uint32_t SLP_NEG_NOISE_CNT : 4; /*!< need_des */ - uint32_t : 9; - } bit; - } STATUS_15; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IM uint32_t APPROACH_PAD2_CNT : 8; /*!< need_des */ - __IM uint32_t APPROACH_PAD1_CNT : 8; /*!< need_des */ - __IM uint32_t APPROACH_PAD0_CNT : 8; /*!< need_des */ - __IM uint32_t SLP_APPROACH_CNT : 8; /*!< need_des */ - } bit; - } STATUS_16; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IM uint32_t DCAP_LPF : 7; /*!< Reserved */ - __IM uint32_t DRES_LPF : 2; /*!< need_des */ - __IM uint32_t DRV_LS : 4; /*!< need_des */ - __IM uint32_t DRV_HS : 5; /*!< need_des */ - __IM uint32_t DBIAS : 5; /*!< need_des */ - __IM uint32_t RTC_FREQ_SCAN_CNT : 2; /*!< need_des */ - uint32_t : 7; - } bit; - } STATUS_17; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IM uint32_t PAD_INACTIVE_STATUS : 15; /*!< need_des */ - __IM uint32_t PAD_ACTIVE_STATUS : 15; /*!< need_des */ - uint32_t : 2; - } bit; - } CHN_TMP_STATUS; - __IM uint32_t RESERVED[40]; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t RTC_DATE : 28; /*!< need_des */ - uint32_t : 3; - __IOM uint32_t RTC_CLK_EN : 1; /*!< need_des */ - } bit; - } DATE; -} LP_TOUCH_Type; /*!< Size = 260 (0x104) */ - - - -/* =========================================================================================================================== */ -/* ================ LP_WDT ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Low-power Watchdog Timer (LP_WDT) - */ - -typedef struct { /*!< LP_WDT Structure */ - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t WDT_CHIP_RESET_WIDTH : 8; /*!< need_des */ - __IOM uint32_t WDT_CHIP_RESET_EN : 1; /*!< need_des */ - __IOM uint32_t WDT_PAUSE_IN_SLP : 1; /*!< need_des */ - __IOM uint32_t WDT_APPCPU_RESET_EN : 1; /*!< need_des */ - __IOM uint32_t WDT_PROCPU_RESET_EN : 1; /*!< need_des */ - __IOM uint32_t WDT_FLASHBOOT_MOD_EN : 1; /*!< need_des */ - __IOM uint32_t WDT_SYS_RESET_LENGTH : 3; /*!< need_des */ - __IOM uint32_t WDT_CPU_RESET_LENGTH : 3; /*!< need_des */ - __IOM uint32_t WDT_STG3 : 3; /*!< need_des */ - __IOM uint32_t WDT_STG2 : 3; /*!< need_des */ - __IOM uint32_t WDT_STG1 : 3; /*!< need_des */ - __IOM uint32_t WDT_STG0 : 3; /*!< need_des */ - __IOM uint32_t WDT_EN : 1; /*!< need_des */ - } bit; - } CONFIG0; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t WDT_STG0_HOLD : 32; /*!< need_des */ - } bit; - } CONFIG1; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t WDT_STG1_HOLD : 32; /*!< need_des */ - } bit; - } CONFIG2; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t WDT_STG2_HOLD : 32; /*!< need_des */ - } bit; - } CONFIG3; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t WDT_STG3_HOLD : 32; /*!< need_des */ - } bit; - } CONFIG4; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 31; - __OM uint32_t FEED : 1; /*!< need_des */ - } bit; - } FEED; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t WDT_WKEY : 32; /*!< need_des */ - } bit; - } WPROTECT; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IM uint32_t SWD_RESET_FLAG : 1; /*!< need_des */ - uint32_t : 17; - __IOM uint32_t SWD_AUTO_FEED_EN : 1; /*!< need_des */ - __OM uint32_t SWD_RST_FLAG_CLR : 1; /*!< need_des */ - __IOM uint32_t SWD_SIGNAL_WIDTH : 10; /*!< need_des */ - __IOM uint32_t SWD_DISABLE : 1; /*!< need_des */ - __OM uint32_t SWD_FEED : 1; /*!< need_des */ - } bit; - } SWD_CONFIG; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t SWD_WKEY : 32; /*!< need_des */ - } bit; - } SWD_WPROTECT; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 30; - __IOM uint32_t SUPER_WDT_INT_RAW : 1; /*!< need_des */ - __IOM uint32_t LP_WDT_INT_RAW : 1; /*!< need_des */ - } bit; - } INT_RAW; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 30; - __IM uint32_t SUPER_WDT_INT_ST : 1; /*!< need_des */ - __IM uint32_t LP_WDT_INT_ST : 1; /*!< need_des */ - } bit; - } INT_ST; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 30; - __IOM uint32_t SUPER_WDT_INT_ENA : 1; /*!< need_des */ - __IOM uint32_t LP_WDT_INT_ENA : 1; /*!< need_des */ - } bit; - } INT_ENA; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - uint32_t : 30; - __OM uint32_t SUPER_WDT_INT_CLR : 1; /*!< need_des */ - __OM uint32_t LP_WDT_INT_CLR : 1; /*!< need_des */ - } bit; - } INT_CLR; - __IM uint32_t RESERVED[242]; - - union { - __IOM uint32_t reg; /*!< need_des */ - - struct { - __IOM uint32_t LP_WDT_DATE : 31; /*!< need_des */ - __IOM uint32_t CLK_EN : 1; /*!< need_des */ - } bit; - } DATE; -} LP_WDT_Type; /*!< Size = 1024 (0x400) */ - - - -/* =========================================================================================================================== */ -/* ================ SDHOST ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief SD/MMC Host Controller (SDHOST) - */ - -typedef struct { /*!< SDHOST Structure */ - - union { - __IOM uint32_t reg; /*!< Control register */ - - struct { - __IOM uint32_t CONTROLLER_RESET : 1; /*!< To reset controller, firmware should set this bit. This bit - is auto-cleared after two AHB and two sdhost_cclk_in clock - cycles. */ - __IOM uint32_t FIFO_RESET : 1; /*!< To reset FIFO, firmware should set bit to 1. This bit is auto-cleared - after completion of reset operation.Note: FIFO pointers - will be out of reset after 2 cycles of system clocks in - addition to synchronization delay (2 cycles of card clock), - after the fifo_reset is cleared. */ - __IOM uint32_t DMA_RESET : 1; /*!< To reset DMA interface, firmware should set bit to 1. This bit - is auto-cleared after two AHB clocks. */ - uint32_t : 1; - __IOM uint32_t INT_ENABLE : 1; /*!< Global interrupt enable/disable bit. 0: Disable; 1: Enable. */ - uint32_t : 1; - __IOM uint32_t READ_WAIT : 1; /*!< For sending read-wait to SDIO cards. */ - __IOM uint32_t SEND_IRQ_RESPONSE : 1; /*!< Bit automatically clears once response is sent. To wait for - MMC card interrupts, host issues CMD40 and waits for interrupt - response from MMC card(s). In the meantime, if host wants - SD/MMC to exit waiting for interrupt state, it can set - this bit, at which time SD/MMC command state-machine sends - CMD40 response on bus and returns to idle state. */ - __IOM uint32_t ABORT_READ_DATA : 1; /*!< After a suspend-command is issued during a read-operation, software - polls the card to find when the suspend-event occurred. - Once the suspend-event has occurred, software sets the - bit which will reset the data state machine that is waiting - for the next block of data. This bit is automatically cleared - once the data state machine is reset to idle. */ - __IOM uint32_t SEND_CCSD : 1; /*!< When set, SD/MMC sends CCSD to the CE-ATA device. Software sets - this bit only if the current command is expecting CCS (that - is, RW_BLK), and if interrupts are enabled for the CE-ATA - device. Once the CCSD pattern is sent to the device, SD/MMC - automatically clears the SDHOST_SEND_CCSD bit. It also - sets the Command Done (CD) bit in the SDHOST_RINTSTS_REG - register, and generates an interrupt for the host, in case - the Command Done interrupt is not masked. NOTE: Once the - SDHOST_SEND_CCSD bit is set, it takes two card clock cycles - to drive the CCSD on the CMD line. Due to this, within - the boundary conditions the CCSD may be sent to the CE-ATA - device, even if the device has signalled CCS. */ - __IOM uint32_t SEND_AUTO_STOP_CCSD : 1; /*!< Always Set SDHOST_SEND_AUTO_STOP_CCSD and SDHOST_SEND_CCSD bits - together; SDHOST_SEND_AUTO_STOP_CCSD should not be set - independently of send_ccsd. When set, SD/MMC automatically - sends an internally-generated STOP command (CMD12) to the - CE-ATA device. After sending this internally-generated - STOP command, the Auto Command Done (ACD) bit in SDHOST_RINTSTS_REG - is set and an interrupt is generated for the host, in case - the ACD interrupt is not masked. After sending the Command - Completion Signal Disable (CCSD), SD/MMC automatically - clears the SDHOST_SEND_AUTO_STOP_CCSD bit. */ - __IOM uint32_t CEATA_DEVICE_INTERRUPT_STATUS : 1;/*!< Software should appropriately write to this bit after the power-on - reset or any other reset to the CE-ATA device. After reset, - the CE-ATA device's interrupt is usually disabled (nIEN - = 1). If the host enables the CE-ATA device's interrupt, - then software should set this bit. */ - uint32_t : 20; - } bit; - } CTRL; - __IM uint32_t RESERVED; - - union { - __IOM uint32_t reg; /*!< Clock divider configuration register */ - - struct { - __IOM uint32_t CLK_DIVIDER0 : 8; /*!< Clock divider0 value. Clock divisor is 2*n, where n = 0 bypasses - the divider (divisor of 1). For example, a value of 1 means - divided by 2*1 = 2, a value of 0xFF means divided by 2*255 - = 510, and so on. */ - __IOM uint32_t CLK_DIVIDER1 : 8; /*!< Clock divider1 value. Clock divisor is 2*n, where n = 0 bypasses - the divider (divisor of 1). For example, a value of 1 means - divided by 2*1 = 2, a value of 0xFF means divided by 2*255 - = 510, and so on. */ - __IOM uint32_t CLK_DIVIDER2 : 8; /*!< Clock divider2 value. Clock divisor is 2*n, where n = 0 bypasses - the divider (divisor of 1). For example, a value of 1 means - divided by 2*1 = 2, a value of 0xFF means divided by 2*255 - = 510, and so on. */ - __IOM uint32_t CLK_DIVIDER3 : 8; /*!< Clock divider3 value. Clock divisor is 2*n, where n = 0 bypasses - the divider (divisor of 1). For example, a value of 1 means - divided by 2*1 = 2, a value of 0xFF means divided by 2*255 - = 510, and so on. */ - } bit; - } CLKDIV; - - union { - __IOM uint32_t reg; /*!< Clock source selection register */ - - struct { - __IOM uint32_t CLKSRC : 4; /*!< Clock divider source for two SD cards is supported. Each card - has two bits assigned to it. For example, bit[1:0] are - assigned for card 0, bit[3:2] are assigned for card 1. - Card 0 maps and internally routes clock divider[0:3] outputs - to cclk_out[1:0] pins, depending on bit value.00 : Clock - divider 0;01 : Clock divider 1;10 : Clock divider 2;11 - : Clock divider 3. */ - uint32_t : 28; - } bit; - } CLKSRC; - - union { - __IOM uint32_t reg; /*!< Clock enable register */ - - struct { - __IOM uint32_t CCLK_ENABLE : 2; /*!< Clock-enable control for two SD card clocks and one MMC card - clock is supported. One bit per card.0: Clock disabled;1: - Clock enabled. */ - uint32_t : 14; - __IOM uint32_t LP_ENABLE : 2; /*!< Disable clock when the card is in IDLE state. One bit per card.0: - clock disabled;1: clock enabled. */ - uint32_t : 14; - } bit; - } CLKENA; - - union { - __IOM uint32_t reg; /*!< Data and response timeout configuration register */ - - struct { - __IOM uint32_t RESPONSE_TIMEOUT : 8; /*!< Response timeout value. Value is specified in terms of number - of card output clocks, i.e., sdhost_cclk_out. */ - __IOM uint32_t DATA_TIMEOUT : 24; /*!< Value for card data read timeout. This value is also used for - data starvation by host timeout. The timeout counter is - started only after the card clock is stopped. This value - is specified in number of card output clocks, i.e. sdhost_cclk_out - of the selected card.NOTE: The software timer should be - used if the timeout value is in the order of 100 ms. In - this case, read data timeout interrupt needs to be disabled. */ - } bit; - } TMOUT; - - union { - __IOM uint32_t reg; /*!< Card bus width configuration register */ - - struct { - __IOM uint32_t CARD_WIDTH4 : 2; /*!< One bit per card indicates if card is 1-bit or 4-bit mode.0: - 1-bit mode;1: 4-bit mode.Bit[1:0] correspond to card[1:0] - respectively. */ - uint32_t : 14; - __IOM uint32_t CARD_WIDTH8 : 2; /*!< One bit per card indicates if card is in 8-bit mode.0: Non 8-bit - mode;1: 8-bit mode.Bit[17:16] correspond to card[1:0] respectively. */ - uint32_t : 14; - } bit; - } CTYPE; - - union { - __IOM uint32_t reg; /*!< Card data block size configuration register */ - - struct { - __IOM uint32_t BLOCK_SIZE : 16; /*!< Block size. */ - uint32_t : 16; - } bit; - } BLKSIZ; - - union { - __IOM uint32_t reg; /*!< Data transfer length configuration register */ - - struct { - __IOM uint32_t BYTE_COUNT : 32; /*!< Number of bytes to be transferred, should be an integral multiple - of Block Size for block transfers. For data transfers of - undefined byte lengths, byte count should be set to 0. - When byte count is set to 0, it is the responsibility of - host to explicitly send stop/abort command to terminate - data transfer. */ - } bit; - } BYTCNT; - - union { - __IOM uint32_t reg; /*!< SDIO interrupt mask register */ - - struct { - __IOM uint32_t INT_MASK : 16; /*!< These bits used to mask unwanted interrupts. A value of 0 masks - interrupt, and a value of 1 enables the interrupt.Bit 15 - (EBE): End-bit error/no CRC error;Bit 14 (ACD): Auto command - done;Bit 13 (SBE/BCI): Rx Start Bit Error;Bit 12 (HLE): - Hardware locked write error;Bit 11 (FRUN): FIFO underrun/overrun - error;Bit 10 (HTO): Data starvation-by-host timeout;Bit - 9 (DRTO): Data read timeout;Bit 8 (RTO): Response timeout; - Bit 7 (DCRC): Data CRC error; Bit 6 (RCRC): Response CRC - error; Bit 5 (RXDR): Receive FIFO data request; Bit 4 (TXDR): - Transmit FIFO data request; Bit 3 (DTO): Data transfer - over; Bit 2 (CD): Command done; Bit 1 (RE): Response error;Bit - 0 (CD): Card detect. */ - __IOM uint32_t SDIO_INT_MASK : 2; /*!< SDIO interrupt mask, one bit for each card. Bit[17:16] correspond - to card[15:0] respectively. When masked, SDIO interrupt - detection for that card is disabled. 0 masks an interrupt, - and 1 enables an interrupt. */ - uint32_t : 14; - } bit; - } INTMASK; - - union { - __IOM uint32_t reg; /*!< Command argument data register */ - - struct { - __IOM uint32_t CMDARG : 32; /*!< Value indicates command argument to be passed to the card. */ - } bit; - } CMDARG; - - union { - __IOM uint32_t reg; /*!< Command and boot configuration register */ - - struct { - __IOM uint32_t INDEX : 6; /*!< Command index. */ - __IOM uint32_t RESPONSE_EXPECT : 1; /*!< 0: No response expected from card; 1: Response expected from - card. */ - __IOM uint32_t RESPONSE_LENGTH : 1; /*!< 0: Short response expected from card; 1: Long response expected - from card. */ - __IOM uint32_t CHECK_RESPONSE_CRC : 1; /*!< 0: Do not check; 1: Check response CRC.Some of command responses - do not return valid CRC bits. Software should disable CRC - checks for those commands in order to disable CRC checking - by controller. */ - __IOM uint32_t DATA_EXPECTED : 1; /*!< 0: No data transfer expected; 1: Data transfer expected. */ - __IOM uint32_t READ_WRITE : 1; /*!< 0: Read from card; 1: Write to card.Don't care if no data is - expected from card. */ - __IOM uint32_t TRANSFER_MODE : 1; /*!< 0: Block data transfer command; 1: Stream data transfer command.Don't - care if no data expected. */ - __IOM uint32_t SEND_AUTO_STOP : 1; /*!< 0: No stop command is sent at the end of data transfer; 1: Send - stop command at the end of data transfer. */ - __IOM uint32_t WAIT_PRVDATA_COMPLETE : 1; /*!< 0: Send command at once, even if previous data transfer has - not completed; 1: Wait for previous data transfer to complete - before sending Command.The SDHOST_WAIT_PRVDATA_COMPLETE] - = 0 option is typically used to query status of card during - data transfer or to stop current data transfer. SDHOST_CARD_NUMBERr - should be same as in previous command. */ - __IOM uint32_t STOP_ABORT_CMD : 1; /*!< 0: Neither stop nor abort command can stop current data transfer. - If abort is sent to function-number currently selected - or not in data-transfer mode, then bit should be set to - 0; 1: Stop or abort command intended to stop current data - transfer in progress.When open-ended or predefined data - transfer is in progress, and host issues stop or abort - command to stop data transfer, bit should be set so that - command/data state-machines of CIU can return correctly - to idle state. */ - __IOM uint32_t SEND_INITIALIZATION : 1; /*!< 0: Do not send initialization sequence (80 clocks of 1) before - sending this command; 1: Send initialization sequence before - sending this command.After powered on, 80 clocks must be - sent to card for initialization before sending any commands - to card. Bit should be set while sending first command - to card so that controller will initialize clocks before - sending command to card. */ - __IOM uint32_t CARD_NUMBER : 5; /*!< Card number in use. Represents physical slot number of card - being accessed. In SD-only mode, up to two cards are supported. */ - __IOM uint32_t UPDATE_CLOCK_REGISTERS_ONLY : 1;/*!< 0: Normal command sequence; 1: Do not send commands, just update - clock register value into card clock domain.Following register - values are transferred into card clock domain: CLKDIV, - CLRSRC, and CLKENA.Changes card clocks (change frequency, - truncate off or on, and set low-frequency mode). This is - provided in order to change clock frequency or stop clock - without having to send command to cards. During normal - command sequence, when sdhost_update_clock_registers_only - = 0, following control registers are transferred from BIU - to CIU: CMD, CMDARG, TMOUT, CTYPE, BLKSIZ, and BYTCNT. - CIU uses new register values for new command sequence to - card(s). When bit is set, there are no Command Done interrupts - because no command is sent to SD_MMC_CEATA cards. */ - __IOM uint32_t READ_CEATA_DEVICE : 1; /*!< Read access flag.0: Host is not performing read access (RW_REG - or RW_BLK)towards CE-ATA device;1: Host is performing read - access (RW_REG or RW_BLK) towards CE-ATA device.Software - should set this bit to indicate that CE-ATA device is being - accessed for read transfer. This bit is used to disable - read data timeout indication while performing CE-ATA read - transfers. Maximum value of I/O transmission delay can - be no less than 10 seconds. SD/MMC should not indicate - read data timeout while waiting for data from CE-ATA device. */ - __IOM uint32_t CCS_EXPECTED : 1; /*!< Expected Command Completion Signal (CCS) configuration.0: Interrupts - are not enabled in CE-ATA device (nIEN = 1 in ATA control - register), or command does not expect CCS from device;1: - Interrupts are enabled in CE-ATA device (nIEN = 0), and - RW_BLK command expects command completion signal from CE-ATA - device. If the command expects Command Completion Signal - (CCS) from the CE-ATA device, the software should set this - control bit. SD/MMC sets Data Transfer Over (DTO) bit in - RINTSTS register and generates interrupt to host if Data - Transfer Over interrupt is not masked. */ - uint32_t : 5; - __IOM uint32_t USE_HOLE : 1; /*!< Use Hold Register.0: CMD and DATA sent to card bypassing HOLD - Register;1: CMD and DATA sent to card through the HOLD - Register. */ - uint32_t : 1; - __IOM uint32_t START_CMD : 1; /*!< Start command. Once command is served by the CIU, this bit is - automatically cleared. When this bit is set, host should - not attempt to write to any command registers. If a write - is attempted, hardware lock error is set in raw interrupt - register. Once command is sent and a response is received - from SD_MMC_CEATA cards, Command Done bit is set in the - raw interrupt Register. */ - } bit; - } CMD; - - union { - __IOM uint32_t reg; /*!< Response data register */ - - struct { - __IM uint32_t RESPONSE0 : 32; /*!< Bit[31:0] of response. */ - } bit; - } RESP0; - - union { - __IOM uint32_t reg; /*!< Long response data register */ - - struct { - __IM uint32_t RESPONSE1 : 32; /*!< Bit[63:32] of long response. */ - } bit; - } RESP1; - - union { - __IOM uint32_t reg; /*!< Long response data register */ - - struct { - __IM uint32_t RESPONSE2 : 32; /*!< Bit[95:64] of long response. */ - } bit; - } RESP2; - - union { - __IOM uint32_t reg; /*!< Long response data register */ - - struct { - __IM uint32_t RESPONSE3 : 32; /*!< Bit[127:96] of long response. */ - } bit; - } RESP3; - - union { - __IOM uint32_t reg; /*!< Masked interrupt status register */ - - struct { - __IM uint32_t INT_STATUS_MSK : 16; /*!< Interrupt enabled only if corresponding bit in interrupt mask - register is set.Bit 15 (EBE): End-bit error/no CRC error;Bit - 14 (ACD): Auto command done;Bit 13 (SBE/BCI): RX Start - Bit Error;Bit 12 (HLE): Hardware locked write error; Bit - 11 (FRUN): FIFO underrun/overrun error;Bit 10 (HTO): Data - starvation by host timeout (HTO);Bit 9 (DTRO): Data read - timeout; Bit 8 (RTO): Response timeout; Bit 7 (DCRC): Data - CRC error; Bit 6 (RCRC): Response CRC error; Bit 5 (RXDR): - Receive FIFO data request; Bit 4 (TXDR): Transmit FIFO - data request;Bit 3 (DTO): Data transfer over; Bit 2 (CD): - Command done; Bit 1 (RE): Response error;Bit 0 (CD): Card - detect. */ - __IM uint32_t SDIO_INTERRUPT_MSK : 2; /*!< Interrupt from SDIO card, one bit for each card. Bit[17:16] - correspond to card1 and card0, respectively. SDIO interrupt - for card is enabled only if corresponding sdhost_sdio_int_mask - bit is set in Interrupt mask register (Setting mask bit - enables interrupt). */ - uint32_t : 14; - } bit; - } MINTSTS; - - union { - __IOM uint32_t reg; /*!< Raw interrupt status register */ - - struct { - __IOM uint32_t INT_STATUS_RAW : 16; /*!< Setting a bit clears the corresponding interrupt and writing - 0 has no effect. Bits are logged regardless of interrupt - mask status.Bit 15 (EBE): End-bit error/no CRC error;Bit - 14 (ACD): Auto command done;Bit 13 (SBE/BCI): RX Start - Bit Error;Bit 12 (HLE): Hardware locked write error; Bit - 11 (FRUN): FIFO underrun/overrun error;Bit 10 (HTO): Data - starvation by host timeout (HTO);Bit 9 (DTRO): Data read - timeout; Bit 8 (RTO): Response timeout; Bit 7 (DCRC): Data - CRC error; Bit 6 (RCRC): Response CRC error; Bit 5 (RXDR): - Receive FIFO data request; Bit 4 (TXDR): Transmit FIFO - data request;Bit 3 (DTO): Data transfer over; Bit 2 (CD): - Command done; Bit 1 (RE): Response error;Bit 0 (CD): Card - detect. */ - __IOM uint32_t SDIO_INTERRUPT_RAW : 2; /*!< Interrupt from SDIO card, one bit for each card. Bit[17:16] - correspond to card1 and card0, respectively. Setting a - bit clears the corresponding interrupt bit and writing - 0 has no effect.0: No SDIO interrupt from card;1: SDIO - interrupt from card. */ - uint32_t : 14; - } bit; - } RINTSTS; - - union { - __IOM uint32_t reg; /*!< SD/MMC status register */ - - struct { - __IM uint32_t FIFO_RX_WATERMARK : 1; /*!< FIFO reached Receive watermark level, not qualified with data - transfer. */ - __IM uint32_t FIFO_TX_WATERMARK : 1; /*!< FIFO reached Transmit watermark level, not qualified with data - transfer. */ - __IM uint32_t FIFO_EMPTY : 1; /*!< FIFO is empty status. */ - __IM uint32_t FIFO_FULL : 1; /*!< FIFO is full status. */ - __IM uint32_t COMMAND_FSM_STATES : 4; /*!< Command FSM states.0: Idle;1: Send init sequence; 2: Send cmd - start bit; 3: Send cmd tx bit;4: Send cmd index + arg;5: - Send cmd crc7;6: Send cmd end bit;7: Receive resp start - bit;8: Receive resp IRQ response;9: Receive resp tx bit;10: - Receive resp cmd idx;11: Receive resp data;12: Receive - resp crc7;13: Receive resp end bit;14: Cmd path wait NCC;15: - Wait, cmd-to-response turnaround. */ - __IM uint32_t DATA_3_STATUS : 1; /*!< Raw selected sdhost_card_data[3], checks whether card is present.0: - card not present;1: card present. */ - __IM uint32_t DATA_BUSY : 1; /*!< Inverted version of raw selected sdhost_card_data[0].0: Card - data not busy;1: Card data busy. */ - __IM uint32_t DATA_STATE_MC_BUSY : 1; /*!< Data transmit or receive state-machine is busy. */ - __IM uint32_t RESPONSE_INDEX : 6; /*!< Index of previous response, including any auto-stop sent by - core. */ - __IM uint32_t FIFO_COUNT : 13; /*!< FIFO count, number of filled locations in FIFO. */ - uint32_t : 2; - } bit; - } STATUS; - - union { - __IOM uint32_t reg; /*!< FIFO configuration register */ - - struct { - __IOM uint32_t TX_WMARK : 12; /*!< FIFO threshold watermark level when transmitting data to card. - When FIFO data count is less than or equal to this number, - DMA/FIFO request is raised. If Interrupt is enabled, then - interrupt occurs. During end of packet, request or interrupt - is generated, regardless of threshold programming.In non-DMA - mode, when transmit FIFO threshold (TXDR) interrupt is - enabled, then interrupt is generated instead of DMA request. - During end of packet, on last interrupt, host is responsible - for filling FIFO with only required remaining bytes (not - before FIFO is full or after CIU completes data transfers, - because FIFO may not be empty). In DMA mode, at end of - packet, if last transfer is less than burst size, DMA controller - does single cycles until required bytes are transferred. */ - uint32_t : 4; - __IOM uint32_t RX_WMARK : 11; /*!< FIFO threshold watermark level when receiving data to card.When - FIFO data count reaches greater than this number , DMA/FIFO - request is raised. During end of packet, request is generated - regardless of threshold programming in order to complete - any remaining data.In non-DMA mode, when receiver FIFO - threshold (RXDR) interrupt is enabled, then interrupt is - generated instead of DMA request.During end of packet, - interrupt is not generated if threshold programming is - larger than any remaining data. It is responsibility of - host to read remaining bytes on seeing Data Transfer Done - interrupt.In DMA mode, at end of packet, even if remaining - bytes are less than threshold, DMA request does single - transfers to flush out any remaining bytes before Data - Transfer Done interrupt is set. */ - uint32_t : 1; - __IOM uint32_t DMA_MULTIPLE_TRANSACTION_SIZE : 3;/*!< Burst size of multiple transaction, should be programmed same - as DMA controller multiple-transaction-size SDHOST_SRC/DEST_MSIZE.000: - 1-byte transfer; 001: 4-byte transfer; 010: 8-byte transfer; - 011: 16-byte transfer; 100: 32-byte transfer; 101: 64-byte - transfer; 110: 128-byte transfer; 111: 256-byte transfer. */ - uint32_t : 1; - } bit; - } FIFOTH; - - union { - __IOM uint32_t reg; /*!< Card detect register */ - - struct { - __IM uint32_t CARD_DETECT_N : 2; /*!< Value on sdhost_card_detect_n input ports (1 bit per card), - read-only bits. 0 represents presence of card. Only NUM_CARDS - number of bits are implemented. */ - uint32_t : 30; - } bit; - } CDETECT; - - union { - __IOM uint32_t reg; /*!< Card write protection (WP) status register */ - - struct { - __IM uint32_t WRITE_PROTECT : 2; /*!< Value on sdhost_card_write_prt input ports (1 bit per card). - 1 represents write protection. Only NUM_CARDS number of - bits are implemented. */ - uint32_t : 30; - } bit; - } WRTPRT; - __IM uint32_t RESERVED1; - - union { - __IOM uint32_t reg; /*!< Transferred byte count register */ - - struct { - __IM uint32_t TCBCNT : 32; /*!< Number of bytes transferred by CIU unit to card. */ - } bit; - } TCBCNT; - - union { - __IOM uint32_t reg; /*!< Transferred byte count register */ - - struct { - __IM uint32_t TBBCNT : 32; /*!< Number of bytes transferred between Host/DMA memory and BIU - FIFO. */ - } bit; - } TBBCNT; - - union { - __IOM uint32_t reg; /*!< Debounce filter time configuration register */ - - struct { - __IOM uint32_t DEBOUNCE_COUNT : 24; /*!< Number of host clocks (clk) used by debounce filter logic. The - typical debounce time is 5 \verb+~+ 25 ms to prevent the - card instability when the card is inserted or removed. */ - uint32_t : 8; - } bit; - } DEBNCE; - - union { - __IOM uint32_t reg; /*!< User ID (scratchpad) register */ - - struct { - __IOM uint32_t USRID : 32; /*!< User identification register, value set by user. Can also be - used as a scratchpad register by user. */ - } bit; - } USRID; - - union { - __IOM uint32_t reg; /*!< Version ID (scratchpad) register */ - - struct { - __IM uint32_t VERSIONID : 32; /*!< Hardware version register. Can also be read by fireware. */ - } bit; - } VERID; - - union { - __IOM uint32_t reg; /*!< Hardware feature register */ - - struct { - __IM uint32_t CARD_TYPE : 1; /*!< Hardware support SDIO and MMC. */ - __IM uint32_t CARD_NUM : 5; /*!< Support card number is 2. */ - __IM uint32_t BUS_TYPE : 1; /*!< Register config is APB bus. */ - __IM uint32_t DATA_WIDTH : 3; /*!< Regisger data widht is 32. */ - __IM uint32_t ADDR_WIDTH : 6; /*!< Register address width is 32. */ - uint32_t : 2; - __IM uint32_t DMA_WIDTH : 3; /*!< DMA data witdth is 32. */ - __IM uint32_t RAM_INDISE : 1; /*!< Inside RAM in SDMMC module. */ - __IM uint32_t HOLD : 1; /*!< Have a hold regiser in data path . */ - uint32_t : 1; - __IM uint32_t NUM_CLK_DIV : 2; /*!< Have 4 clk divider in design . */ - uint32_t : 6; - } bit; - } HCON; - - union { - __IOM uint32_t reg; /*!< UHS-1 register */ - - struct { - uint32_t : 16; - __IOM uint32_t DDR : 2; /*!< DDR mode selecton,1 bit for each card.0-Non-DDR mdoe.1-DDR mdoe. */ - uint32_t : 14; - } bit; - } UHS; - - union { - __IOM uint32_t reg; /*!< Card reset register */ - - struct { - __IOM uint32_t CARD_RESET : 2; /*!< Hardware reset.1: Active mode; 0: Reset. These bits cause the - cards to enter pre-idle state, which requires them to be - re-initialized. SDHOST_RST_CARD_RESET[0] should be set - to 1'b0 to reset card0, SDHOST_RST_CARD_RESET[1] should - be set to 1'b0 to reset card1. */ - uint32_t : 30; - } bit; - } RST_N; - __IM uint32_t RESERVED2; - - union { - __IOM uint32_t reg; /*!< Burst mode transfer configuration register */ - - struct { - __IOM uint32_t SWR : 1; /*!< Software Reset. When set, the DMA Controller resets all its - internal registers. It is automatically cleared after one - clock cycle. */ - __IOM uint32_t FB : 1; /*!< Fixed Burst. Controls whether the AHB Master interface performs - fixed burst transfers or not. When set, the AHB will use - only SINGLE, INCR4, INCR8 or INCR16 during start of normal - burst transfers. When reset, the AHB will use SINGLE and - INCR burst transfer operations. */ - uint32_t : 5; - __IOM uint32_t DE : 1; /*!< IDMAC Enable. When set, the IDMAC is enabled. */ - __IOM uint32_t PBL : 3; /*!< Programmable Burst Length. These bits indicate the maximum number - of beats to be performed in one IDMAC???Internal DMA Control???transactio - . The IDMAC will always attempt to burst as specified in - PBL each time it starts a burst transfer on the host bus. - The permissible values are 1, 4, 8, 16, 32, 64, 128 and - 256. This value is the mirror of MSIZE of FIFOTH register. - In order to change this value, write the required value - to FIFOTH register. This is an encode value as follows:000: - 1-byte transfer; 001: 4-byte transfer; 010: 8-byte transfer; - 011: 16-byte transfer; 100: 32-byte transfer; 101: 64-byte - transfer; 110: 128-byte transfer; 111: 256-byte transfer.PBL - is a read-only value and is applicable only for data access, - it does not apply to descriptor access. */ - uint32_t : 21; - } bit; - } BMOD; - - union { - __IOM uint32_t reg; /*!< Poll demand configuration register */ - - struct { - __OM uint32_t PD : 32; /*!< Poll Demand. If the OWNER bit of a descriptor is not set, the - FSM goes to the Suspend state. The host needs to write - any value into this register for the IDMAC FSM to resume - normal descriptor fetch operation. This is a write only - . */ - } bit; - } PLDMND; - - union { - __IOM uint32_t reg; /*!< Descriptor base address register */ - - struct { - __IOM uint32_t DBADDR : 32; /*!< Start of Descriptor List. Contains the base address of the First - Descriptor. The LSB bits [1:0] are ignored and taken as - all-zero by the IDMAC internally. Hence these LSB bits - may be treated as read-only. */ - } bit; - } DBADDR; - - union { - __IOM uint32_t reg; /*!< IDMAC status register */ - - struct { - __IOM uint32_t TI : 1; /*!< Transmit Interrupt. Indicates that data transmission is finished - for a descriptor. Writing 1 clears this bit. */ - __IOM uint32_t RI : 1; /*!< Receive Interrupt. Indicates the completion of data reception - for a descriptor. Writing 1 clears this bit. */ - __IOM uint32_t FBE : 1; /*!< Fatal Bus Error Interrupt. Indicates that a Bus Error occurred - (IDSTS[12:10]) . When this bit is set, the DMA disables - all its bus accesses. Writing 1 clears this bit. */ - uint32_t : 1; - __IOM uint32_t DU : 1; /*!< Descriptor Unavailable Interrupt. This bit is set when the descriptor - is unavailable due to OWNER bit = 0 (DES0[31] = 0). Writing - 1 clears this bit. */ - __IOM uint32_t CES : 1; /*!< Card Error Summary. Indicates the status of the transaction - to/from the card, also present in RINTSTS. Indicates the - logical OR of the following bits:EBE : End Bit Error; RTO - : Response Timeout/Boot Ack Timeout; RCRC : Response CRC; - SBE : Start Bit Error; DRTO : Data Read Timeout/BDS timeout; - DCRC : Data CRC for Receive; RE : Response Error.Writing - 1 clears this bit. The abort condition of the IDMAC depends - on the setting of this CES bit. If the CES bit is enabled, - then the IDMAC aborts on a response error. */ - uint32_t : 2; - __IOM uint32_t NIS : 1; /*!< Normal Interrupt Summary. Logical OR of the following: IDSTS[0] - : Transmit Interrupt, IDSTS[1] : Receive Interrupt. Only - unmasked bits affect this bit. This is a sticky bit and - must be cleared each time a corresponding bit that causes - NIS to be set is cleared. Writing 1 clears this bit. */ - __IOM uint32_t AIS : 1; /*!< Abnormal Interrupt Summary. Logical OR of the following: IDSTS[2] - : Fatal Bus Interrupt, IDSTS[4] : DU bit Interrupt. Only - unmasked bits affect this bit. This is a sticky bit and - must be cleared each time a corresponding bit that causes - AIS to be set is cleared. Writing 1 clears this bit. */ - __IOM uint32_t FBE_CODE : 3; /*!< Fatal Bus Error Code. Indicates the type of error that caused - a Bus Error. Valid only when the Fatal Bus Error bit IDSTS[2] - is set. This field does not generate an interrupt.001: - Host Abort received during transmission;010: Host Abort - received during reception;Others: Reserved. */ - __IOM uint32_t FSM : 4; /*!< DMAC FSM present state.0: DMA_IDLE (idle state); 1: DMA_SUSPEND - (suspend state); 2: DESC_RD (descriptor reading state); - 3: DESC_CHK (descriptor checking state); 4: DMA_RD_REQ_WAIT - (read-data request waiting state);5: DMA_WR_REQ_WAIT (write-data - request waiting state); 6: DMA_RD (data-read state); 7: - DMA_WR (data-write state); 8: DESC_CLOSE (descriptor close - state). */ - uint32_t : 15; - } bit; - } IDSTS; - - union { - __IOM uint32_t reg; /*!< IDMAC interrupt enable register */ - - struct { - __IOM uint32_t TI : 1; /*!< Transmit Interrupt Enable. When set with Normal Interrupt Summary - Enable, Transmit Interrupt is enabled. When reset, Transmit - Interrupt is disabled. */ - __IOM uint32_t RI : 1; /*!< Receive Interrupt Enable. When set with Normal Interrupt Summary - Enable, Receive Interrupt is enabled. When reset, Receive - Interrupt is disabled. */ - __IOM uint32_t FBE : 1; /*!< Fatal Bus Error Enable. When set with Abnormal Interrupt Summary - Enable, the Fatal Bus Error Interrupt is enabled. When - reset, Fatal Bus Error Enable Interrupt is disabled. */ - uint32_t : 1; - __IOM uint32_t DU : 1; /*!< Descriptor Unavailable Interrupt. When set along with Abnormal - Interrupt Summary Enable, the DU interrupt is enabled. */ - __IOM uint32_t CES : 1; /*!< Card Error summary Interrupt Enable. When set, it enables the - Card Interrupt summary. */ - uint32_t : 2; - __IOM uint32_t NI : 1; /*!< Normal Interrupt Summary Enable. When set, a normal interrupt - is enabled. When reset, a normal interrupt is disabled. - This bit enables the following bits:IDINTEN[0]: Transmit - Interrupt;IDINTEN[1]: Receive Interrupt. */ - __IOM uint32_t AI : 1; /*!< Abnormal Interrupt Summary Enable. When set, an abnormal interrupt - is enabled. This bit enables the following bits:IDINTEN[2]: - Fatal Bus Error Interrupt;IDINTEN[4]: DU Interrupt. */ - uint32_t : 22; - } bit; - } IDINTEN; - - union { - __IOM uint32_t reg; /*!< Host descriptor address pointer */ - - struct { - __IM uint32_t DSCADDR : 32; /*!< Host Descriptor Address Pointer, updated by IDMAC during operation - and cleared on reset. This register points to the start - address of the current descriptor read by the IDMAC. */ - } bit; - } DSCADDR; - - union { - __IOM uint32_t reg; /*!< Host buffer address pointer register */ - - struct { - __IM uint32_t BUFADDR : 32; /*!< Host Buffer Address Pointer, updated by IDMAC during operation - and cleared on reset. This register points to the current - Data Buffer Address being accessed by the IDMAC. */ - } bit; - } BUFADDR; - __IM uint32_t RESERVED3[25]; - - union { - __IOM uint32_t reg; /*!< Card Threshold Control register */ - - struct { - __IOM uint32_t CARDRDTHREN : 1; /*!< Card read threshold enable.1'b0-Card read threshold disabled.1'b1-Card - read threshold enabled. */ - __IOM uint32_t CARDCLRINTEN : 1; /*!< Busy clear interrupt generation:1'b0-Busy clear interrypt disabled.1'b1-Busy - clear interrypt enabled. */ - __IOM uint32_t CARDWRTHREN : 1; /*!< Applicable when HS400 mode is enabled.1'b0-Card write Threshold - disabled.1'b1-Card write Threshold enabled. */ - uint32_t : 13; - __IOM uint32_t CARDTHRESHOLD : 16; /*!< The inside FIFO size is 512,This register is applicable when - SDHOST_CARDERTHREN_REG is set to 1 or SDHOST_CARDRDTHREN_REG - set to 1. */ - } bit; - } CARDTHRCTL; - __IM uint32_t RESERVED4[2]; - - union { - __IOM uint32_t reg; /*!< eMMC DDR register */ - - struct { - __IOM uint32_t HALFSTARTBIT : 2; /*!< Control for start bit detection mechanism duration of start - bit.Each bit refers to one slot.Set this bit to 1 for eMMC4.5 - and above,set to 0 for SD applications.For eMMC4.5,start - bit can be:1'b0-Full cycle.1'b1-less than one full cycle. */ - uint32_t : 29; - __IOM uint32_t HS400_MODE : 1; /*!< Set 1 to enable HS400 mode. */ - } bit; - } EMMCDDR; - - union { - __IOM uint32_t reg; /*!< Enable Phase Shift register */ - - struct { - __IOM uint32_t ENABLE_SHIFT : 4; /*!< Control for the amount of phase shift provided on the default - enables in the design.Two bits assigned for each card.2'b00-Default - phase shift.2'b01-Enables shifted to next immediate positive - edge.2'b10-Enables shifted to next immediate negative edge.2'b11-Reserved - */ - uint32_t : 28; - } bit; - } ENSHIFT; - __IM uint32_t RESERVED5[59]; - - union { - __IOM uint32_t reg; /*!< CPU write and read transmit data by FIFO */ - - struct { - __IOM uint32_t BUFFIFO : 32; /*!< CPU write and read transmit data by FIFO. This register points - to the current Data FIFO . */ - } bit; - } BUFFIFO; - __IM uint32_t RESERVED6[383]; - - union { - __IOM uint32_t reg; /*!< SDIO control register. */ - - struct { - __IOM uint32_t CCLKIN_EDGE_DRV_SEL : 3; /*!< It's used to select the clock phase of the output signal from - phase 0, phase 90, phase 180, phase 270. */ - __IOM uint32_t CCLKIN_EDGE_SAM_SEL : 3; /*!< It's used to select the clock phase of the input signal from - phase 0, phase 90, phase 180, phase 270. */ - __IOM uint32_t CCLKIN_EDGE_SLF_SEL : 3; /*!< It's used to select the clock phase of the internal signal from - phase 0, phase 90, phase 180, phase 270. */ - __IOM uint32_t CCLLKIN_EDGE_H : 4; /*!< The high level of the divider clock. The value should be smaller - than CCLKIN_EDGE_L. */ - __IOM uint32_t CCLLKIN_EDGE_L : 4; /*!< The low level of the divider clock. The value should be larger - than CCLKIN_EDGE_H. */ - __IOM uint32_t CCLLKIN_EDGE_N : 4; /*!< The clock division of cclk_in. */ - __IOM uint32_t ESDIO_MODE : 1; /*!< Enable esdio mode. */ - __IOM uint32_t ESD_MODE : 1; /*!< Enable esd mode. */ - __IOM uint32_t CCLK_EN : 1; /*!< Sdio clock enable. */ - __IOM uint32_t ULTRA_HIGH_SPEED_MODE : 1; /*!< Enable ultra high speed mode, use dll to generate clk. */ - uint32_t : 7; - } bit; - } CLK_EDGE_SEL; - - union { - __IOM uint32_t reg; /*!< SDIO raw ints register. */ - - struct { - __IM uint32_t RAW_INTS : 32; /*!< It indicates raw ints. */ - } bit; - } RAW_INTS; - - union { - __IOM uint32_t reg; /*!< SDIO DLL clock control register. */ - - struct { - __IOM uint32_t DLL_CCLK_IN_SLF_EN : 1; /*!< Clock enable of cclk_in_slf when ULTRA_HIGH_SPEED_MODE==1. */ - __IOM uint32_t DLL_CCLK_IN_DRV_EN : 1; /*!< Clock enable of cclk_in_drv when ULTRA_HIGH_SPEED_MODE==1. */ - __IOM uint32_t DLL_CCLK_IN_SAM_EN : 1; /*!< Clock enable of cclk_in_sam when ULTRA_HIGH_SPEED_MODE==1. */ - __IOM uint32_t DLL_CCLK_IN_SLF_PHASE : 6; /*!< It's used to control the phase of cclk_in_slf when ULTRA_HIGH_SPEED_MODE==1. */ - __IOM uint32_t DLL_CCLK_IN_DRV_PHASE : 6; /*!< It's used to control the phase of cclk_in_drv when ULTRA_HIGH_SPEED_MODE==1. */ - __IOM uint32_t DLL_CCLK_IN_SAM_PHASE : 6; /*!< It's used to control the phase of cclk_in_sam when ULTRA_HIGH_SPEED_MODE==1. */ - uint32_t : 11; - } bit; - } DLL_CLK_CONF; - - union { - __IOM uint32_t reg; /*!< SDIO DLL configuration register. */ - - struct { - __IOM uint32_t DLL_CAL_STOP : 1; /*!< Set 1 to stop calibration. */ - __IM uint32_t DLL_CAL_END : 1; /*!< 1 means calibration finished. */ - uint32_t : 30; - } bit; - } DLL_CONF; -} SDHOST_Type; /*!< Size = 2064 (0x810) */ - - - -/* =========================================================================================================================== */ -/* ================ SHA ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief SHA (Secure Hash Algorithm) Accelerator (SHA) - */ - -typedef struct { /*!< SHA Structure */ - - union { - __IOM uint32_t reg; /*!< Initial configuration register. */ - - struct { - __IOM uint32_t MODE : 3; /*!< Sha mode. */ - uint32_t : 29; - } bit; - } MODE; - - union { - __IOM uint32_t reg; /*!< SHA 512/t configuration register 0. */ - - struct { - __IOM uint32_t T_STRING : 32; /*!< Sha t_string (used if and only if mode == SHA_512/t). */ - } bit; - } T_STRING; - - union { - __IOM uint32_t reg; /*!< SHA 512/t configuration register 1. */ - - struct { - __IOM uint32_t T_LENGTH : 6; /*!< Sha t_length (used if and only if mode == SHA_512/t). */ - uint32_t : 26; - } bit; - } T_LENGTH; - - union { - __IOM uint32_t reg; /*!< DMA configuration register 0. */ - - struct { - __IOM uint32_t DMA_BLOCK_NUM : 6; /*!< Dma-sha block number. */ - uint32_t : 26; - } bit; - } DMA_BLOCK_NUM; - - union { - __IOM uint32_t reg; /*!< Typical SHA configuration register 0. */ - - struct { - uint32_t : 1; - __IM uint32_t START : 31; /*!< Reserved. */ - } bit; - } START; - - union { - __IOM uint32_t reg; /*!< Typical SHA configuration register 1. */ - - struct { - uint32_t : 1; - __IM uint32_t CONTINUE : 31; /*!< Reserved. */ - } bit; - } CONTINUE; - - union { - __IOM uint32_t reg; /*!< Busy register. */ - - struct { - __IM uint32_t STATE : 1; /*!< Sha busy state. 1'b0: idle. 1'b1: busy. */ - uint32_t : 31; - } bit; - } BUSY; - - union { - __IOM uint32_t reg; /*!< DMA configuration register 1. */ - - struct { - __OM uint32_t DMA_START : 1; /*!< Start dma-sha. */ - uint32_t : 31; - } bit; - } DMA_START; - - union { - __IOM uint32_t reg; /*!< DMA configuration register 2. */ - - struct { - __OM uint32_t DMA_CONTINUE : 1; /*!< Continue dma-sha. */ - uint32_t : 31; - } bit; - } DMA_CONTINUE; - - union { - __IOM uint32_t reg; /*!< Interrupt clear register. */ - - struct { - __OM uint32_t CLEAR_INTERRUPT : 1; /*!< Clear sha interrupt. */ - uint32_t : 31; - } bit; - } CLEAR_IRQ; - - union { - __IOM uint32_t reg; /*!< Interrupt enable register. */ - - struct { - __IOM uint32_t INTERRUPT_ENA : 1; /*!< Sha interrupt enable register. 1'b0: disable(default). 1'b1: - enable. */ - uint32_t : 31; - } bit; - } IRQ_ENA; - - union { - __IOM uint32_t reg; /*!< Date register. */ - - struct { - __IOM uint32_t DATE : 30; /*!< Sha date information/ sha version information. */ - uint32_t : 2; - } bit; - } DATE; - __IM uint32_t RESERVED[4]; - __IOM uint32_t H_MEM[16]; /*!< Sha H memory which contains intermediate hash or finial hash. */ - __IOM uint32_t M_MEM[16]; /*!< Sha M memory which contains message. */ -} SHA_Type; /*!< Size = 192 (0xc0) */ - - - -/* =========================================================================================================================== */ -/* ================ SOC_ETM ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Event Task Matrix (SOC_ETM) - */ - -typedef struct { /*!< SOC_ETM Structure */ - - union { - __IOM uint32_t reg; /*!< Channel enable status register */ - - struct { - __IOM uint32_t CH_ENA0 : 1; /*!< Represents ch0 enable status.\\0: Disable\\1: Enable */ - __IOM uint32_t CH_ENA1 : 1; /*!< Represents ch1 enable status.\\0: Disable\\1: Enable */ - __IOM uint32_t CH_ENA2 : 1; /*!< Represents ch2 enable status.\\0: Disable\\1: Enable */ - __IOM uint32_t CH_ENA3 : 1; /*!< Represents ch3 enable status.\\0: Disable\\1: Enable */ - __IOM uint32_t CH_ENA4 : 1; /*!< Represents ch4 enable status.\\0: Disable\\1: Enable */ - __IOM uint32_t CH_ENA5 : 1; /*!< Represents ch5 enable status.\\0: Disable\\1: Enable */ - __IOM uint32_t CH_ENA6 : 1; /*!< Represents ch6 enable status.\\0: Disable\\1: Enable */ - __IOM uint32_t CH_ENA7 : 1; /*!< Represents ch7 enable status.\\0: Disable\\1: Enable */ - __IOM uint32_t CH_ENA8 : 1; /*!< Represents ch8 enable status.\\0: Disable\\1: Enable */ - __IOM uint32_t CH_ENA9 : 1; /*!< Represents ch9 enable status.\\0: Disable\\1: Enable */ - __IOM uint32_t CH_ENA10 : 1; /*!< Represents ch10 enable status.\\0: Disable\\1: Enable */ - __IOM uint32_t CH_ENA11 : 1; /*!< Represents ch11 enable status.\\0: Disable\\1: Enable */ - __IOM uint32_t CH_ENA12 : 1; /*!< Represents ch12 enable status.\\0: Disable\\1: Enable */ - __IOM uint32_t CH_ENA13 : 1; /*!< Represents ch13 enable status.\\0: Disable\\1: Enable */ - __IOM uint32_t CH_ENA14 : 1; /*!< Represents ch14 enable status.\\0: Disable\\1: Enable */ - __IOM uint32_t CH_ENA15 : 1; /*!< Represents ch15 enable status.\\0: Disable\\1: Enable */ - __IOM uint32_t CH_ENA16 : 1; /*!< Represents ch16 enable status.\\0: Disable\\1: Enable */ - __IOM uint32_t CH_ENA17 : 1; /*!< Represents ch17 enable status.\\0: Disable\\1: Enable */ - __IOM uint32_t CH_ENA18 : 1; /*!< Represents ch18 enable status.\\0: Disable\\1: Enable */ - __IOM uint32_t CH_ENA19 : 1; /*!< Represents ch19 enable status.\\0: Disable\\1: Enable */ - __IOM uint32_t CH_ENA20 : 1; /*!< Represents ch20 enable status.\\0: Disable\\1: Enable */ - __IOM uint32_t CH_ENA21 : 1; /*!< Represents ch21 enable status.\\0: Disable\\1: Enable */ - __IOM uint32_t CH_ENA22 : 1; /*!< Represents ch22 enable status.\\0: Disable\\1: Enable */ - __IOM uint32_t CH_ENA23 : 1; /*!< Represents ch23 enable status.\\0: Disable\\1: Enable */ - __IOM uint32_t CH_ENA24 : 1; /*!< Represents ch24 enable status.\\0: Disable\\1: Enable */ - __IOM uint32_t CH_ENA25 : 1; /*!< Represents ch25 enable status.\\0: Disable\\1: Enable */ - __IOM uint32_t CH_ENA26 : 1; /*!< Represents ch26 enable status.\\0: Disable\\1: Enable */ - __IOM uint32_t CH_ENA27 : 1; /*!< Represents ch27 enable status.\\0: Disable\\1: Enable */ - __IOM uint32_t CH_ENA28 : 1; /*!< Represents ch28 enable status.\\0: Disable\\1: Enable */ - __IOM uint32_t CH_ENA29 : 1; /*!< Represents ch29 enable status.\\0: Disable\\1: Enable */ - __IOM uint32_t CH_ENA30 : 1; /*!< Represents ch30 enable status.\\0: Disable\\1: Enable */ - __IOM uint32_t CH_ENA31 : 1; /*!< Represents ch31 enable status.\\0: Disable\\1: Enable */ - } bit; - } CH_ENA_AD0; - - union { - __IOM uint32_t reg; /*!< Channel enable set register */ - - struct { - __OM uint32_t CH_SET0 : 1; /*!< Configures whether or not to enable ch0.\\0: Invalid, No effect\\1: - Enable */ - __OM uint32_t CH_SET1 : 1; /*!< Configures whether or not to enable ch1.\\0: Invalid, No effect\\1: - Enable */ - __OM uint32_t CH_SET2 : 1; /*!< Configures whether or not to enable ch2.\\0: Invalid, No effect\\1: - Enable */ - __OM uint32_t CH_SET3 : 1; /*!< Configures whether or not to enable ch3.\\0: Invalid, No effect\\1: - Enable */ - __OM uint32_t CH_SET4 : 1; /*!< Configures whether or not to enable ch4.\\0: Invalid, No effect\\1: - Enable */ - __OM uint32_t CH_SET5 : 1; /*!< Configures whether or not to enable ch5.\\0: Invalid, No effect\\1: - Enable */ - __OM uint32_t CH_SET6 : 1; /*!< Configures whether or not to enable ch6.\\0: Invalid, No effect\\1: - Enable */ - __OM uint32_t CH_SET7 : 1; /*!< Configures whether or not to enable ch7.\\0: Invalid, No effect\\1: - Enable */ - __OM uint32_t CH_SET8 : 1; /*!< Configures whether or not to enable ch8.\\0: Invalid, No effect\\1: - Enable */ - __OM uint32_t CH_SET9 : 1; /*!< Configures whether or not to enable ch9.\\0: Invalid, No effect\\1: - Enable */ - __OM uint32_t CH_SET10 : 1; /*!< Configures whether or not to enable ch10.\\0: Invalid, No effect\\1: - Enable */ - __OM uint32_t CH_SET11 : 1; /*!< Configures whether or not to enable ch11.\\0: Invalid, No effect\\1: - Enable */ - __OM uint32_t CH_SET12 : 1; /*!< Configures whether or not to enable ch12.\\0: Invalid, No effect\\1: - Enable */ - __OM uint32_t CH_SET13 : 1; /*!< Configures whether or not to enable ch13.\\0: Invalid, No effect\\1: - Enable */ - __OM uint32_t CH_SET14 : 1; /*!< Configures whether or not to enable ch14.\\0: Invalid, No effect\\1: - Enable */ - __OM uint32_t CH_SET15 : 1; /*!< Configures whether or not to enable ch15.\\0: Invalid, No effect\\1: - Enable */ - __OM uint32_t CH_SET16 : 1; /*!< Configures whether or not to enable ch16.\\0: Invalid, No effect\\1: - Enable */ - __OM uint32_t CH_SET17 : 1; /*!< Configures whether or not to enable ch17.\\0: Invalid, No effect\\1: - Enable */ - __OM uint32_t CH_SET18 : 1; /*!< Configures whether or not to enable ch18.\\0: Invalid, No effect\\1: - Enable */ - __OM uint32_t CH_SET19 : 1; /*!< Configures whether or not to enable ch19.\\0: Invalid, No effect\\1: - Enable */ - __OM uint32_t CH_SET20 : 1; /*!< Configures whether or not to enable ch20.\\0: Invalid, No effect\\1: - Enable */ - __OM uint32_t CH_SET21 : 1; /*!< Configures whether or not to enable ch21.\\0: Invalid, No effect\\1: - Enable */ - __OM uint32_t CH_SET22 : 1; /*!< Configures whether or not to enable ch22.\\0: Invalid, No effect\\1: - Enable */ - __OM uint32_t CH_SET23 : 1; /*!< Configures whether or not to enable ch23.\\0: Invalid, No effect\\1: - Enable */ - __OM uint32_t CH_SET24 : 1; /*!< Configures whether or not to enable ch24.\\0: Invalid, No effect\\1: - Enable */ - __OM uint32_t CH_SET25 : 1; /*!< Configures whether or not to enable ch25.\\0: Invalid, No effect\\1: - Enable */ - __OM uint32_t CH_SET26 : 1; /*!< Configures whether or not to enable ch26.\\0: Invalid, No effect\\1: - Enable */ - __OM uint32_t CH_SET27 : 1; /*!< Configures whether or not to enable ch27.\\0: Invalid, No effect\\1: - Enable */ - __OM uint32_t CH_SET28 : 1; /*!< Configures whether or not to enable ch28.\\0: Invalid, No effect\\1: - Enable */ - __OM uint32_t CH_SET29 : 1; /*!< Configures whether or not to enable ch29.\\0: Invalid, No effect\\1: - Enable */ - __OM uint32_t CH_SET30 : 1; /*!< Configures whether or not to enable ch30.\\0: Invalid, No effect\\1: - Enable */ - __OM uint32_t CH_SET31 : 1; /*!< Configures whether or not to enable ch31.\\0: Invalid, No effect\\1: - Enable */ - } bit; - } CH_ENA_AD0_SET; - - union { - __IOM uint32_t reg; /*!< Channel enable clear register */ - - struct { - __OM uint32_t CH_CLR0 : 1; /*!< Configures whether or not to clear ch0 enable.\\0: Invalid, - No effect\\1: Clear */ - __OM uint32_t CH_CLR1 : 1; /*!< Configures whether or not to clear ch1 enable.\\0: Invalid, - No effect\\1: Clear */ - __OM uint32_t CH_CLR2 : 1; /*!< Configures whether or not to clear ch2 enable.\\0: Invalid, - No effect\\1: Clear */ - __OM uint32_t CH_CLR3 : 1; /*!< Configures whether or not to clear ch3 enable.\\0: Invalid, - No effect\\1: Clear */ - __OM uint32_t CH_CLR4 : 1; /*!< Configures whether or not to clear ch4 enable.\\0: Invalid, - No effect\\1: Clear */ - __OM uint32_t CH_CLR5 : 1; /*!< Configures whether or not to clear ch5 enable.\\0: Invalid, - No effect\\1: Clear */ - __OM uint32_t CH_CLR6 : 1; /*!< Configures whether or not to clear ch6 enable.\\0: Invalid, - No effect\\1: Clear */ - __OM uint32_t CH_CLR7 : 1; /*!< Configures whether or not to clear ch7 enable.\\0: Invalid, - No effect\\1: Clear */ - __OM uint32_t CH_CLR8 : 1; /*!< Configures whether or not to clear ch8 enable.\\0: Invalid, - No effect\\1: Clear */ - __OM uint32_t CH_CLR9 : 1; /*!< Configures whether or not to clear ch9 enable.\\0: Invalid, - No effect\\1: Clear */ - __OM uint32_t CH_CLR10 : 1; /*!< Configures whether or not to clear ch10 enable.\\0: Invalid, - No effect\\1: Clear */ - __OM uint32_t CH_CLR11 : 1; /*!< Configures whether or not to clear ch11 enable.\\0: Invalid, - No effect\\1: Clear */ - __OM uint32_t CH_CLR12 : 1; /*!< Configures whether or not to clear ch12 enable.\\0: Invalid, - No effect\\1: Clear */ - __OM uint32_t CH_CLR13 : 1; /*!< Configures whether or not to clear ch13 enable.\\0: Invalid, - No effect\\1: Clear */ - __OM uint32_t CH_CLR14 : 1; /*!< Configures whether or not to clear ch14 enable.\\0: Invalid, - No effect\\1: Clear */ - __OM uint32_t CH_CLR15 : 1; /*!< Configures whether or not to clear ch15 enable.\\0: Invalid, - No effect\\1: Clear */ - __OM uint32_t CH_CLR16 : 1; /*!< Configures whether or not to clear ch16 enable.\\0: Invalid, - No effect\\1: Clear */ - __OM uint32_t CH_CLR17 : 1; /*!< Configures whether or not to clear ch17 enable.\\0: Invalid, - No effect\\1: Clear */ - __OM uint32_t CH_CLR18 : 1; /*!< Configures whether or not to clear ch18 enable.\\0: Invalid, - No effect\\1: Clear */ - __OM uint32_t CH_CLR19 : 1; /*!< Configures whether or not to clear ch19 enable.\\0: Invalid, - No effect\\1: Clear */ - __OM uint32_t CH_CLR20 : 1; /*!< Configures whether or not to clear ch20 enable.\\0: Invalid, - No effect\\1: Clear */ - __OM uint32_t CH_CLR21 : 1; /*!< Configures whether or not to clear ch21 enable.\\0: Invalid, - No effect\\1: Clear */ - __OM uint32_t CH_CLR22 : 1; /*!< Configures whether or not to clear ch22 enable.\\0: Invalid, - No effect\\1: Clear */ - __OM uint32_t CH_CLR23 : 1; /*!< Configures whether or not to clear ch23 enable.\\0: Invalid, - No effect\\1: Clear */ - __OM uint32_t CH_CLR24 : 1; /*!< Configures whether or not to clear ch24 enable.\\0: Invalid, - No effect\\1: Clear */ - __OM uint32_t CH_CLR25 : 1; /*!< Configures whether or not to clear ch25 enable.\\0: Invalid, - No effect\\1: Clear */ - __OM uint32_t CH_CLR26 : 1; /*!< Configures whether or not to clear ch26 enable.\\0: Invalid, - No effect\\1: Clear */ - __OM uint32_t CH_CLR27 : 1; /*!< Configures whether or not to clear ch27 enable.\\0: Invalid, - No effect\\1: Clear */ - __OM uint32_t CH_CLR28 : 1; /*!< Configures whether or not to clear ch28 enable.\\0: Invalid, - No effect\\1: Clear */ - __OM uint32_t CH_CLR29 : 1; /*!< Configures whether or not to clear ch29 enable.\\0: Invalid, - No effect\\1: Clear */ - __OM uint32_t CH_CLR30 : 1; /*!< Configures whether or not to clear ch30 enable.\\0: Invalid, - No effect\\1: Clear */ - __OM uint32_t CH_CLR31 : 1; /*!< Configures whether or not to clear ch31 enable.\\0: Invalid, - No effect\\1: Clear */ - } bit; - } CH_ENA_AD0_CLR; - - union { - __IOM uint32_t reg; /*!< Channel enable status register */ - - struct { - __IOM uint32_t CH_ENA32 : 1; /*!< Represents ch32 enable status.\\0: Disable\\1: Enable */ - __IOM uint32_t CH_ENA33 : 1; /*!< Represents ch33 enable status.\\0: Disable\\1: Enable */ - __IOM uint32_t CH_ENA34 : 1; /*!< Represents ch34 enable status.\\0: Disable\\1: Enable */ - __IOM uint32_t CH_ENA35 : 1; /*!< Represents ch35 enable status.\\0: Disable\\1: Enable */ - __IOM uint32_t CH_ENA36 : 1; /*!< Represents ch36 enable status.\\0: Disable\\1: Enable */ - __IOM uint32_t CH_ENA37 : 1; /*!< Represents ch37 enable status.\\0: Disable\\1: Enable */ - __IOM uint32_t CH_ENA38 : 1; /*!< Represents ch38 enable status.\\0: Disable\\1: Enable */ - __IOM uint32_t CH_ENA39 : 1; /*!< Represents ch39 enable status.\\0: Disable\\1: Enable */ - __IOM uint32_t CH_ENA40 : 1; /*!< Represents ch40 enable status.\\0: Disable\\1: Enable */ - __IOM uint32_t CH_ENA41 : 1; /*!< Represents ch41 enable status.\\0: Disable\\1: Enable */ - __IOM uint32_t CH_ENA42 : 1; /*!< Represents ch42 enable status.\\0: Disable\\1: Enable */ - __IOM uint32_t CH_ENA43 : 1; /*!< Represents ch43 enable status.\\0: Disable\\1: Enable */ - __IOM uint32_t CH_ENA44 : 1; /*!< Represents ch44 enable status.\\0: Disable\\1: Enable */ - __IOM uint32_t CH_ENA45 : 1; /*!< Represents ch45 enable status.\\0: Disable\\1: Enable */ - __IOM uint32_t CH_ENA46 : 1; /*!< Represents ch46 enable status.\\0: Disable\\1: Enable */ - __IOM uint32_t CH_ENA47 : 1; /*!< Represents ch47 enable status.\\0: Disable\\1: Enable */ - __IOM uint32_t CH_ENA48 : 1; /*!< Represents ch48 enable status.\\0: Disable\\1: Enable */ - __IOM uint32_t CH_ENA49 : 1; /*!< Represents ch49 enable status.\\0: Disable\\1: Enable */ - uint32_t : 14; - } bit; - } CH_ENA_AD1; - - union { - __IOM uint32_t reg; /*!< Channel enable set register */ - - struct { - __OM uint32_t CH_SET32 : 1; /*!< Configures whether or not to enable ch32.\\0: Invalid, No effect\\1: - Enable */ - __OM uint32_t CH_SET33 : 1; /*!< Configures whether or not to enable ch33.\\0: Invalid, No effect\\1: - Enable */ - __OM uint32_t CH_SET34 : 1; /*!< Configures whether or not to enable ch34.\\0: Invalid, No effect\\1: - Enable */ - __OM uint32_t CH_SET35 : 1; /*!< Configures whether or not to enable ch35.\\0: Invalid, No effect\\1: - Enable */ - __OM uint32_t CH_SET36 : 1; /*!< Configures whether or not to enable ch36.\\0: Invalid, No effect\\1: - Enable */ - __OM uint32_t CH_SET37 : 1; /*!< Configures whether or not to enable ch37.\\0: Invalid, No effect\\1: - Enable */ - __OM uint32_t CH_SET38 : 1; /*!< Configures whether or not to enable ch38.\\0: Invalid, No effect\\1: - Enable */ - __OM uint32_t CH_SET39 : 1; /*!< Configures whether or not to enable ch39.\\0: Invalid, No effect\\1: - Enable */ - __OM uint32_t CH_SET40 : 1; /*!< Configures whether or not to enable ch40.\\0: Invalid, No effect\\1: - Enable */ - __OM uint32_t CH_SET41 : 1; /*!< Configures whether or not to enable ch41.\\0: Invalid, No effect\\1: - Enable */ - __OM uint32_t CH_SET42 : 1; /*!< Configures whether or not to enable ch42.\\0: Invalid, No effect\\1: - Enable */ - __OM uint32_t CH_SET43 : 1; /*!< Configures whether or not to enable ch43.\\0: Invalid, No effect\\1: - Enable */ - __OM uint32_t CH_SET44 : 1; /*!< Configures whether or not to enable ch44.\\0: Invalid, No effect\\1: - Enable */ - __OM uint32_t CH_SET45 : 1; /*!< Configures whether or not to enable ch45.\\0: Invalid, No effect\\1: - Enable */ - __OM uint32_t CH_SET46 : 1; /*!< Configures whether or not to enable ch46.\\0: Invalid, No effect\\1: - Enable */ - __OM uint32_t CH_SET47 : 1; /*!< Configures whether or not to enable ch47.\\0: Invalid, No effect\\1: - Enable */ - __OM uint32_t CH_SET48 : 1; /*!< Configures whether or not to enable ch48.\\0: Invalid, No effect\\1: - Enable */ - __OM uint32_t CH_SET49 : 1; /*!< Configures whether or not to enable ch49.\\0: Invalid, No effect\\1: - Enable */ - uint32_t : 14; - } bit; - } CH_ENA_AD1_SET; - - union { - __IOM uint32_t reg; /*!< Channel enable clear register */ - - struct { - __OM uint32_t CH_CLR32 : 1; /*!< Configures whether or not to clear ch32 enable.\\0: Invalid, - No effect\\1: Clear */ - __OM uint32_t CH_CLR33 : 1; /*!< Configures whether or not to clear ch33 enable.\\0: Invalid, - No effect\\1: Clear */ - __OM uint32_t CH_CLR34 : 1; /*!< Configures whether or not to clear ch34 enable.\\0: Invalid, - No effect\\1: Clear */ - __OM uint32_t CH_CLR35 : 1; /*!< Configures whether or not to clear ch35 enable.\\0: Invalid, - No effect\\1: Clear */ - __OM uint32_t CH_CLR36 : 1; /*!< Configures whether or not to clear ch36 enable.\\0: Invalid, - No effect\\1: Clear */ - __OM uint32_t CH_CLR37 : 1; /*!< Configures whether or not to clear ch37 enable.\\0: Invalid, - No effect\\1: Clear */ - __OM uint32_t CH_CLR38 : 1; /*!< Configures whether or not to clear ch38 enable.\\0: Invalid, - No effect\\1: Clear */ - __OM uint32_t CH_CLR39 : 1; /*!< Configures whether or not to clear ch39 enable.\\0: Invalid, - No effect\\1: Clear */ - __OM uint32_t CH_CLR40 : 1; /*!< Configures whether or not to clear ch40 enable.\\0: Invalid, - No effect\\1: Clear */ - __OM uint32_t CH_CLR41 : 1; /*!< Configures whether or not to clear ch41 enable.\\0: Invalid, - No effect\\1: Clear */ - __OM uint32_t CH_CLR42 : 1; /*!< Configures whether or not to clear ch42 enable.\\0: Invalid, - No effect\\1: Clear */ - __OM uint32_t CH_CLR43 : 1; /*!< Configures whether or not to clear ch43 enable.\\0: Invalid, - No effect\\1: Clear */ - __OM uint32_t CH_CLR44 : 1; /*!< Configures whether or not to clear ch44 enable.\\0: Invalid, - No effect\\1: Clear */ - __OM uint32_t CH_CLR45 : 1; /*!< Configures whether or not to clear ch45 enable.\\0: Invalid, - No effect\\1: Clear */ - __OM uint32_t CH_CLR46 : 1; /*!< Configures whether or not to clear ch46 enable.\\0: Invalid, - No effect\\1: Clear */ - __OM uint32_t CH_CLR47 : 1; /*!< Configures whether or not to clear ch47 enable.\\0: Invalid, - No effect\\1: Clear */ - __OM uint32_t CH_CLR48 : 1; /*!< Configures whether or not to clear ch48 enable.\\0: Invalid, - No effect\\1: Clear */ - __OM uint32_t CH_CLR49 : 1; /*!< Configures whether or not to clear ch49 enable.\\0: Invalid, - No effect\\1: Clear */ - uint32_t : 14; - } bit; - } CH_ENA_AD1_CLR; - - union { - __IOM uint32_t reg; /*!< Channel0 event id register */ - - struct { - __IOM uint32_t CH0_EVT_ID : 8; /*!< Configures ch0_evt_id */ - uint32_t : 24; - } bit; - } CH0_EVT_ID; - - union { - __IOM uint32_t reg; /*!< Channel0 task id register */ - - struct { - __IOM uint32_t CH0_TASK_ID : 8; /*!< Configures ch0_task_id */ - uint32_t : 24; - } bit; - } CH0_TASK_ID; - - union { - __IOM uint32_t reg; /*!< Channel1 event id register */ - - struct { - __IOM uint32_t CH1_EVT_ID : 8; /*!< Configures ch1_evt_id */ - uint32_t : 24; - } bit; - } CH1_EVT_ID; - - union { - __IOM uint32_t reg; /*!< Channel1 task id register */ - - struct { - __IOM uint32_t CH1_TASK_ID : 8; /*!< Configures ch1_task_id */ - uint32_t : 24; - } bit; - } CH1_TASK_ID; - - union { - __IOM uint32_t reg; /*!< Channel2 event id register */ - - struct { - __IOM uint32_t CH2_EVT_ID : 8; /*!< Configures ch2_evt_id */ - uint32_t : 24; - } bit; - } CH2_EVT_ID; - - union { - __IOM uint32_t reg; /*!< Channel2 task id register */ - - struct { - __IOM uint32_t CH2_TASK_ID : 8; /*!< Configures ch2_task_id */ - uint32_t : 24; - } bit; - } CH2_TASK_ID; - - union { - __IOM uint32_t reg; /*!< Channel3 event id register */ - - struct { - __IOM uint32_t CH3_EVT_ID : 8; /*!< Configures ch3_evt_id */ - uint32_t : 24; - } bit; - } CH3_EVT_ID; - - union { - __IOM uint32_t reg; /*!< Channel3 task id register */ - - struct { - __IOM uint32_t CH3_TASK_ID : 8; /*!< Configures ch3_task_id */ - uint32_t : 24; - } bit; - } CH3_TASK_ID; - - union { - __IOM uint32_t reg; /*!< Channel4 event id register */ - - struct { - __IOM uint32_t CH4_EVT_ID : 8; /*!< Configures ch4_evt_id */ - uint32_t : 24; - } bit; - } CH4_EVT_ID; - - union { - __IOM uint32_t reg; /*!< Channel4 task id register */ - - struct { - __IOM uint32_t CH4_TASK_ID : 8; /*!< Configures ch4_task_id */ - uint32_t : 24; - } bit; - } CH4_TASK_ID; - - union { - __IOM uint32_t reg; /*!< Channel5 event id register */ - - struct { - __IOM uint32_t CH5_EVT_ID : 8; /*!< Configures ch5_evt_id */ - uint32_t : 24; - } bit; - } CH5_EVT_ID; - - union { - __IOM uint32_t reg; /*!< Channel5 task id register */ - - struct { - __IOM uint32_t CH5_TASK_ID : 8; /*!< Configures ch5_task_id */ - uint32_t : 24; - } bit; - } CH5_TASK_ID; - - union { - __IOM uint32_t reg; /*!< Channel6 event id register */ - - struct { - __IOM uint32_t CH6_EVT_ID : 8; /*!< Configures ch6_evt_id */ - uint32_t : 24; - } bit; - } CH6_EVT_ID; - - union { - __IOM uint32_t reg; /*!< Channel6 task id register */ - - struct { - __IOM uint32_t CH6_TASK_ID : 8; /*!< Configures ch6_task_id */ - uint32_t : 24; - } bit; - } CH6_TASK_ID; - - union { - __IOM uint32_t reg; /*!< Channel7 event id register */ - - struct { - __IOM uint32_t CH7_EVT_ID : 8; /*!< Configures ch7_evt_id */ - uint32_t : 24; - } bit; - } CH7_EVT_ID; - - union { - __IOM uint32_t reg; /*!< Channel7 task id register */ - - struct { - __IOM uint32_t CH7_TASK_ID : 8; /*!< Configures ch7_task_id */ - uint32_t : 24; - } bit; - } CH7_TASK_ID; - - union { - __IOM uint32_t reg; /*!< Channel8 event id register */ - - struct { - __IOM uint32_t CH8_EVT_ID : 8; /*!< Configures ch8_evt_id */ - uint32_t : 24; - } bit; - } CH8_EVT_ID; - - union { - __IOM uint32_t reg; /*!< Channel8 task id register */ - - struct { - __IOM uint32_t CH8_TASK_ID : 8; /*!< Configures ch8_task_id */ - uint32_t : 24; - } bit; - } CH8_TASK_ID; - - union { - __IOM uint32_t reg; /*!< Channel9 event id register */ - - struct { - __IOM uint32_t CH9_EVT_ID : 8; /*!< Configures ch9_evt_id */ - uint32_t : 24; - } bit; - } CH9_EVT_ID; - - union { - __IOM uint32_t reg; /*!< Channel9 task id register */ - - struct { - __IOM uint32_t CH9_TASK_ID : 8; /*!< Configures ch9_task_id */ - uint32_t : 24; - } bit; - } CH9_TASK_ID; - - union { - __IOM uint32_t reg; /*!< Channel10 event id register */ - - struct { - __IOM uint32_t CH10_EVT_ID : 8; /*!< Configures ch10_evt_id */ - uint32_t : 24; - } bit; - } CH10_EVT_ID; - - union { - __IOM uint32_t reg; /*!< Channel10 task id register */ - - struct { - __IOM uint32_t CH10_TASK_ID : 8; /*!< Configures ch10_task_id */ - uint32_t : 24; - } bit; - } CH10_TASK_ID; - - union { - __IOM uint32_t reg; /*!< Channel11 event id register */ - - struct { - __IOM uint32_t CH11_EVT_ID : 8; /*!< Configures ch11_evt_id */ - uint32_t : 24; - } bit; - } CH11_EVT_ID; - - union { - __IOM uint32_t reg; /*!< Channel11 task id register */ - - struct { - __IOM uint32_t CH11_TASK_ID : 8; /*!< Configures ch11_task_id */ - uint32_t : 24; - } bit; - } CH11_TASK_ID; - - union { - __IOM uint32_t reg; /*!< Channel12 event id register */ - - struct { - __IOM uint32_t CH12_EVT_ID : 8; /*!< Configures ch12_evt_id */ - uint32_t : 24; - } bit; - } CH12_EVT_ID; - - union { - __IOM uint32_t reg; /*!< Channel12 task id register */ - - struct { - __IOM uint32_t CH12_TASK_ID : 8; /*!< Configures ch12_task_id */ - uint32_t : 24; - } bit; - } CH12_TASK_ID; - - union { - __IOM uint32_t reg; /*!< Channel13 event id register */ - - struct { - __IOM uint32_t CH13_EVT_ID : 8; /*!< Configures ch13_evt_id */ - uint32_t : 24; - } bit; - } CH13_EVT_ID; - - union { - __IOM uint32_t reg; /*!< Channel13 task id register */ - - struct { - __IOM uint32_t CH13_TASK_ID : 8; /*!< Configures ch13_task_id */ - uint32_t : 24; - } bit; - } CH13_TASK_ID; - - union { - __IOM uint32_t reg; /*!< Channel14 event id register */ - - struct { - __IOM uint32_t CH14_EVT_ID : 8; /*!< Configures ch14_evt_id */ - uint32_t : 24; - } bit; - } CH14_EVT_ID; - - union { - __IOM uint32_t reg; /*!< Channel14 task id register */ - - struct { - __IOM uint32_t CH14_TASK_ID : 8; /*!< Configures ch14_task_id */ - uint32_t : 24; - } bit; - } CH14_TASK_ID; - - union { - __IOM uint32_t reg; /*!< Channel15 event id register */ - - struct { - __IOM uint32_t CH15_EVT_ID : 8; /*!< Configures ch15_evt_id */ - uint32_t : 24; - } bit; - } CH15_EVT_ID; - - union { - __IOM uint32_t reg; /*!< Channel15 task id register */ - - struct { - __IOM uint32_t CH15_TASK_ID : 8; /*!< Configures ch15_task_id */ - uint32_t : 24; - } bit; - } CH15_TASK_ID; - - union { - __IOM uint32_t reg; /*!< Channel16 event id register */ - - struct { - __IOM uint32_t CH16_EVT_ID : 8; /*!< Configures ch16_evt_id */ - uint32_t : 24; - } bit; - } CH16_EVT_ID; - - union { - __IOM uint32_t reg; /*!< Channel16 task id register */ - - struct { - __IOM uint32_t CH16_TASK_ID : 8; /*!< Configures ch16_task_id */ - uint32_t : 24; - } bit; - } CH16_TASK_ID; - - union { - __IOM uint32_t reg; /*!< Channel17 event id register */ - - struct { - __IOM uint32_t CH17_EVT_ID : 8; /*!< Configures ch17_evt_id */ - uint32_t : 24; - } bit; - } CH17_EVT_ID; - - union { - __IOM uint32_t reg; /*!< Channel17 task id register */ - - struct { - __IOM uint32_t CH17_TASK_ID : 8; /*!< Configures ch17_task_id */ - uint32_t : 24; - } bit; - } CH17_TASK_ID; - - union { - __IOM uint32_t reg; /*!< Channel18 event id register */ - - struct { - __IOM uint32_t CH18_EVT_ID : 8; /*!< Configures ch18_evt_id */ - uint32_t : 24; - } bit; - } CH18_EVT_ID; - - union { - __IOM uint32_t reg; /*!< Channel18 task id register */ - - struct { - __IOM uint32_t CH18_TASK_ID : 8; /*!< Configures ch18_task_id */ - uint32_t : 24; - } bit; - } CH18_TASK_ID; - - union { - __IOM uint32_t reg; /*!< Channel19 event id register */ - - struct { - __IOM uint32_t CH19_EVT_ID : 8; /*!< Configures ch19_evt_id */ - uint32_t : 24; - } bit; - } CH19_EVT_ID; - - union { - __IOM uint32_t reg; /*!< Channel19 task id register */ - - struct { - __IOM uint32_t CH19_TASK_ID : 8; /*!< Configures ch19_task_id */ - uint32_t : 24; - } bit; - } CH19_TASK_ID; - - union { - __IOM uint32_t reg; /*!< Channel20 event id register */ - - struct { - __IOM uint32_t CH20_EVT_ID : 8; /*!< Configures ch20_evt_id */ - uint32_t : 24; - } bit; - } CH20_EVT_ID; - - union { - __IOM uint32_t reg; /*!< Channel20 task id register */ - - struct { - __IOM uint32_t CH20_TASK_ID : 8; /*!< Configures ch20_task_id */ - uint32_t : 24; - } bit; - } CH20_TASK_ID; - - union { - __IOM uint32_t reg; /*!< Channel21 event id register */ - - struct { - __IOM uint32_t CH21_EVT_ID : 8; /*!< Configures ch21_evt_id */ - uint32_t : 24; - } bit; - } CH21_EVT_ID; - - union { - __IOM uint32_t reg; /*!< Channel21 task id register */ - - struct { - __IOM uint32_t CH21_TASK_ID : 8; /*!< Configures ch21_task_id */ - uint32_t : 24; - } bit; - } CH21_TASK_ID; - - union { - __IOM uint32_t reg; /*!< Channel22 event id register */ - - struct { - __IOM uint32_t CH22_EVT_ID : 8; /*!< Configures ch22_evt_id */ - uint32_t : 24; - } bit; - } CH22_EVT_ID; - - union { - __IOM uint32_t reg; /*!< Channel22 task id register */ - - struct { - __IOM uint32_t CH22_TASK_ID : 8; /*!< Configures ch22_task_id */ - uint32_t : 24; - } bit; - } CH22_TASK_ID; - - union { - __IOM uint32_t reg; /*!< Channel23 event id register */ - - struct { - __IOM uint32_t CH23_EVT_ID : 8; /*!< Configures ch23_evt_id */ - uint32_t : 24; - } bit; - } CH23_EVT_ID; - - union { - __IOM uint32_t reg; /*!< Channel23 task id register */ - - struct { - __IOM uint32_t CH23_TASK_ID : 8; /*!< Configures ch23_task_id */ - uint32_t : 24; - } bit; - } CH23_TASK_ID; - - union { - __IOM uint32_t reg; /*!< Channel24 event id register */ - - struct { - __IOM uint32_t CH24_EVT_ID : 8; /*!< Configures ch24_evt_id */ - uint32_t : 24; - } bit; - } CH24_EVT_ID; - - union { - __IOM uint32_t reg; /*!< Channel24 task id register */ - - struct { - __IOM uint32_t CH24_TASK_ID : 8; /*!< Configures ch24_task_id */ - uint32_t : 24; - } bit; - } CH24_TASK_ID; - - union { - __IOM uint32_t reg; /*!< Channel25 event id register */ - - struct { - __IOM uint32_t CH25_EVT_ID : 8; /*!< Configures ch25_evt_id */ - uint32_t : 24; - } bit; - } CH25_EVT_ID; - - union { - __IOM uint32_t reg; /*!< Channel25 task id register */ - - struct { - __IOM uint32_t CH25_TASK_ID : 8; /*!< Configures ch25_task_id */ - uint32_t : 24; - } bit; - } CH25_TASK_ID; - - union { - __IOM uint32_t reg; /*!< Channel26 event id register */ - - struct { - __IOM uint32_t CH26_EVT_ID : 8; /*!< Configures ch26_evt_id */ - uint32_t : 24; - } bit; - } CH26_EVT_ID; - - union { - __IOM uint32_t reg; /*!< Channel26 task id register */ - - struct { - __IOM uint32_t CH26_TASK_ID : 8; /*!< Configures ch26_task_id */ - uint32_t : 24; - } bit; - } CH26_TASK_ID; - - union { - __IOM uint32_t reg; /*!< Channel27 event id register */ - - struct { - __IOM uint32_t CH27_EVT_ID : 8; /*!< Configures ch27_evt_id */ - uint32_t : 24; - } bit; - } CH27_EVT_ID; - - union { - __IOM uint32_t reg; /*!< Channel27 task id register */ - - struct { - __IOM uint32_t CH27_TASK_ID : 8; /*!< Configures ch27_task_id */ - uint32_t : 24; - } bit; - } CH27_TASK_ID; - - union { - __IOM uint32_t reg; /*!< Channel28 event id register */ - - struct { - __IOM uint32_t CH28_EVT_ID : 8; /*!< Configures ch28_evt_id */ - uint32_t : 24; - } bit; - } CH28_EVT_ID; - - union { - __IOM uint32_t reg; /*!< Channel28 task id register */ - - struct { - __IOM uint32_t CH28_TASK_ID : 8; /*!< Configures ch28_task_id */ - uint32_t : 24; - } bit; - } CH28_TASK_ID; - - union { - __IOM uint32_t reg; /*!< Channel29 event id register */ - - struct { - __IOM uint32_t CH29_EVT_ID : 8; /*!< Configures ch29_evt_id */ - uint32_t : 24; - } bit; - } CH29_EVT_ID; - - union { - __IOM uint32_t reg; /*!< Channel29 task id register */ - - struct { - __IOM uint32_t CH29_TASK_ID : 8; /*!< Configures ch29_task_id */ - uint32_t : 24; - } bit; - } CH29_TASK_ID; - - union { - __IOM uint32_t reg; /*!< Channel30 event id register */ - - struct { - __IOM uint32_t CH30_EVT_ID : 8; /*!< Configures ch30_evt_id */ - uint32_t : 24; - } bit; - } CH30_EVT_ID; - - union { - __IOM uint32_t reg; /*!< Channel30 task id register */ - - struct { - __IOM uint32_t CH30_TASK_ID : 8; /*!< Configures ch30_task_id */ - uint32_t : 24; - } bit; - } CH30_TASK_ID; - - union { - __IOM uint32_t reg; /*!< Channel31 event id register */ - - struct { - __IOM uint32_t CH31_EVT_ID : 8; /*!< Configures ch31_evt_id */ - uint32_t : 24; - } bit; - } CH31_EVT_ID; - - union { - __IOM uint32_t reg; /*!< Channel31 task id register */ - - struct { - __IOM uint32_t CH31_TASK_ID : 8; /*!< Configures ch31_task_id */ - uint32_t : 24; - } bit; - } CH31_TASK_ID; - - union { - __IOM uint32_t reg; /*!< Channel32 event id register */ - - struct { - __IOM uint32_t CH32_EVT_ID : 8; /*!< Configures ch32_evt_id */ - uint32_t : 24; - } bit; - } CH32_EVT_ID; - - union { - __IOM uint32_t reg; /*!< Channel32 task id register */ - - struct { - __IOM uint32_t CH32_TASK_ID : 8; /*!< Configures ch32_task_id */ - uint32_t : 24; - } bit; - } CH32_TASK_ID; - - union { - __IOM uint32_t reg; /*!< Channel33 event id register */ - - struct { - __IOM uint32_t CH33_EVT_ID : 8; /*!< Configures ch33_evt_id */ - uint32_t : 24; - } bit; - } CH33_EVT_ID; - - union { - __IOM uint32_t reg; /*!< Channel33 task id register */ - - struct { - __IOM uint32_t CH33_TASK_ID : 8; /*!< Configures ch33_task_id */ - uint32_t : 24; - } bit; - } CH33_TASK_ID; - - union { - __IOM uint32_t reg; /*!< Channel34 event id register */ - - struct { - __IOM uint32_t CH34_EVT_ID : 8; /*!< Configures ch34_evt_id */ - uint32_t : 24; - } bit; - } CH34_EVT_ID; - - union { - __IOM uint32_t reg; /*!< Channel34 task id register */ - - struct { - __IOM uint32_t CH34_TASK_ID : 8; /*!< Configures ch34_task_id */ - uint32_t : 24; - } bit; - } CH34_TASK_ID; - - union { - __IOM uint32_t reg; /*!< Channel35 event id register */ - - struct { - __IOM uint32_t CH35_EVT_ID : 8; /*!< Configures ch35_evt_id */ - uint32_t : 24; - } bit; - } CH35_EVT_ID; - - union { - __IOM uint32_t reg; /*!< Channel35 task id register */ - - struct { - __IOM uint32_t CH35_TASK_ID : 8; /*!< Configures ch35_task_id */ - uint32_t : 24; - } bit; - } CH35_TASK_ID; - - union { - __IOM uint32_t reg; /*!< Channel36 event id register */ - - struct { - __IOM uint32_t CH36_EVT_ID : 8; /*!< Configures ch36_evt_id */ - uint32_t : 24; - } bit; - } CH36_EVT_ID; - - union { - __IOM uint32_t reg; /*!< Channel36 task id register */ - - struct { - __IOM uint32_t CH36_TASK_ID : 8; /*!< Configures ch36_task_id */ - uint32_t : 24; - } bit; - } CH36_TASK_ID; - - union { - __IOM uint32_t reg; /*!< Channel37 event id register */ - - struct { - __IOM uint32_t CH37_EVT_ID : 8; /*!< Configures ch37_evt_id */ - uint32_t : 24; - } bit; - } CH37_EVT_ID; - - union { - __IOM uint32_t reg; /*!< Channel37 task id register */ - - struct { - __IOM uint32_t CH37_TASK_ID : 8; /*!< Configures ch37_task_id */ - uint32_t : 24; - } bit; - } CH37_TASK_ID; - - union { - __IOM uint32_t reg; /*!< Channel38 event id register */ - - struct { - __IOM uint32_t CH38_EVT_ID : 8; /*!< Configures ch38_evt_id */ - uint32_t : 24; - } bit; - } CH38_EVT_ID; - - union { - __IOM uint32_t reg; /*!< Channel38 task id register */ - - struct { - __IOM uint32_t CH38_TASK_ID : 8; /*!< Configures ch38_task_id */ - uint32_t : 24; - } bit; - } CH38_TASK_ID; - - union { - __IOM uint32_t reg; /*!< Channel39 event id register */ - - struct { - __IOM uint32_t CH39_EVT_ID : 8; /*!< Configures ch39_evt_id */ - uint32_t : 24; - } bit; - } CH39_EVT_ID; - - union { - __IOM uint32_t reg; /*!< Channel39 task id register */ - - struct { - __IOM uint32_t CH39_TASK_ID : 8; /*!< Configures ch39_task_id */ - uint32_t : 24; - } bit; - } CH39_TASK_ID; - - union { - __IOM uint32_t reg; /*!< Channel40 event id register */ - - struct { - __IOM uint32_t CH40_EVT_ID : 8; /*!< Configures ch40_evt_id */ - uint32_t : 24; - } bit; - } CH40_EVT_ID; - - union { - __IOM uint32_t reg; /*!< Channel40 task id register */ - - struct { - __IOM uint32_t CH40_TASK_ID : 8; /*!< Configures ch40_task_id */ - uint32_t : 24; - } bit; - } CH40_TASK_ID; - - union { - __IOM uint32_t reg; /*!< Channel41 event id register */ - - struct { - __IOM uint32_t CH41_EVT_ID : 8; /*!< Configures ch41_evt_id */ - uint32_t : 24; - } bit; - } CH41_EVT_ID; - - union { - __IOM uint32_t reg; /*!< Channel41 task id register */ - - struct { - __IOM uint32_t CH41_TASK_ID : 8; /*!< Configures ch41_task_id */ - uint32_t : 24; - } bit; - } CH41_TASK_ID; - - union { - __IOM uint32_t reg; /*!< Channel42 event id register */ - - struct { - __IOM uint32_t CH42_EVT_ID : 8; /*!< Configures ch42_evt_id */ - uint32_t : 24; - } bit; - } CH42_EVT_ID; - - union { - __IOM uint32_t reg; /*!< Channel42 task id register */ - - struct { - __IOM uint32_t CH42_TASK_ID : 8; /*!< Configures ch42_task_id */ - uint32_t : 24; - } bit; - } CH42_TASK_ID; - - union { - __IOM uint32_t reg; /*!< Channel43 event id register */ - - struct { - __IOM uint32_t CH43_EVT_ID : 8; /*!< Configures ch43_evt_id */ - uint32_t : 24; - } bit; - } CH43_EVT_ID; - - union { - __IOM uint32_t reg; /*!< Channel43 task id register */ - - struct { - __IOM uint32_t CH43_TASK_ID : 8; /*!< Configures ch43_task_id */ - uint32_t : 24; - } bit; - } CH43_TASK_ID; - - union { - __IOM uint32_t reg; /*!< Channel44 event id register */ - - struct { - __IOM uint32_t CH44_EVT_ID : 8; /*!< Configures ch44_evt_id */ - uint32_t : 24; - } bit; - } CH44_EVT_ID; - - union { - __IOM uint32_t reg; /*!< Channel44 task id register */ - - struct { - __IOM uint32_t CH44_TASK_ID : 8; /*!< Configures ch44_task_id */ - uint32_t : 24; - } bit; - } CH44_TASK_ID; - - union { - __IOM uint32_t reg; /*!< Channel45 event id register */ - - struct { - __IOM uint32_t CH45_EVT_ID : 8; /*!< Configures ch45_evt_id */ - uint32_t : 24; - } bit; - } CH45_EVT_ID; - - union { - __IOM uint32_t reg; /*!< Channel45 task id register */ - - struct { - __IOM uint32_t CH45_TASK_ID : 8; /*!< Configures ch45_task_id */ - uint32_t : 24; - } bit; - } CH45_TASK_ID; - - union { - __IOM uint32_t reg; /*!< Channel46 event id register */ - - struct { - __IOM uint32_t CH46_EVT_ID : 8; /*!< Configures ch46_evt_id */ - uint32_t : 24; - } bit; - } CH46_EVT_ID; - - union { - __IOM uint32_t reg; /*!< Channel46 task id register */ - - struct { - __IOM uint32_t CH46_TASK_ID : 8; /*!< Configures ch46_task_id */ - uint32_t : 24; - } bit; - } CH46_TASK_ID; - - union { - __IOM uint32_t reg; /*!< Channel47 event id register */ - - struct { - __IOM uint32_t CH47_EVT_ID : 8; /*!< Configures ch47_evt_id */ - uint32_t : 24; - } bit; - } CH47_EVT_ID; - - union { - __IOM uint32_t reg; /*!< Channel47 task id register */ - - struct { - __IOM uint32_t CH47_TASK_ID : 8; /*!< Configures ch47_task_id */ - uint32_t : 24; - } bit; - } CH47_TASK_ID; - - union { - __IOM uint32_t reg; /*!< Channel48 event id register */ - - struct { - __IOM uint32_t CH48_EVT_ID : 8; /*!< Configures ch48_evt_id */ - uint32_t : 24; - } bit; - } CH48_EVT_ID; - - union { - __IOM uint32_t reg; /*!< Channel48 task id register */ - - struct { - __IOM uint32_t CH48_TASK_ID : 8; /*!< Configures ch48_task_id */ - uint32_t : 24; - } bit; - } CH48_TASK_ID; - - union { - __IOM uint32_t reg; /*!< Channel49 event id register */ - - struct { - __IOM uint32_t CH49_EVT_ID : 8; /*!< Configures ch49_evt_id */ - uint32_t : 24; - } bit; - } CH49_EVT_ID; - - union { - __IOM uint32_t reg; /*!< Channel49 task id register */ - - struct { - __IOM uint32_t CH49_TASK_ID : 8; /*!< Configures ch49_task_id */ - uint32_t : 24; - } bit; - } CH49_TASK_ID; - - union { - __IOM uint32_t reg; /*!< Events trigger status register */ - - struct { - __IOM uint32_t GPIO_EVT_CH0_RISE_EDGE_ST : 1;/*!< Represents GPIO_evt_ch0_rise_edge trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t GPIO_EVT_CH1_RISE_EDGE_ST : 1;/*!< Represents GPIO_evt_ch1_rise_edge trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t GPIO_EVT_CH2_RISE_EDGE_ST : 1;/*!< Represents GPIO_evt_ch2_rise_edge trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t GPIO_EVT_CH3_RISE_EDGE_ST : 1;/*!< Represents GPIO_evt_ch3_rise_edge trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t GPIO_EVT_CH4_RISE_EDGE_ST : 1;/*!< Represents GPIO_evt_ch4_rise_edge trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t GPIO_EVT_CH5_RISE_EDGE_ST : 1;/*!< Represents GPIO_evt_ch5_rise_edge trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t GPIO_EVT_CH6_RISE_EDGE_ST : 1;/*!< Represents GPIO_evt_ch6_rise_edge trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t GPIO_EVT_CH7_RISE_EDGE_ST : 1;/*!< Represents GPIO_evt_ch7_rise_edge trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t GPIO_EVT_CH0_FALL_EDGE_ST : 1;/*!< Represents GPIO_evt_ch0_fall_edge trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t GPIO_EVT_CH1_FALL_EDGE_ST : 1;/*!< Represents GPIO_evt_ch1_fall_edge trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t GPIO_EVT_CH2_FALL_EDGE_ST : 1;/*!< Represents GPIO_evt_ch2_fall_edge trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t GPIO_EVT_CH3_FALL_EDGE_ST : 1;/*!< Represents GPIO_evt_ch3_fall_edge trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t GPIO_EVT_CH4_FALL_EDGE_ST : 1;/*!< Represents GPIO_evt_ch4_fall_edge trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t GPIO_EVT_CH5_FALL_EDGE_ST : 1;/*!< Represents GPIO_evt_ch5_fall_edge trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t GPIO_EVT_CH6_FALL_EDGE_ST : 1;/*!< Represents GPIO_evt_ch6_fall_edge trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t GPIO_EVT_CH7_FALL_EDGE_ST : 1;/*!< Represents GPIO_evt_ch7_fall_edge trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t GPIO_EVT_CH0_ANY_EDGE_ST : 1;/*!< Represents GPIO_evt_ch0_any_edge trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t GPIO_EVT_CH1_ANY_EDGE_ST : 1;/*!< Represents GPIO_evt_ch1_any_edge trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t GPIO_EVT_CH2_ANY_EDGE_ST : 1;/*!< Represents GPIO_evt_ch2_any_edge trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t GPIO_EVT_CH3_ANY_EDGE_ST : 1;/*!< Represents GPIO_evt_ch3_any_edge trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t GPIO_EVT_CH4_ANY_EDGE_ST : 1;/*!< Represents GPIO_evt_ch4_any_edge trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t GPIO_EVT_CH5_ANY_EDGE_ST : 1;/*!< Represents GPIO_evt_ch5_any_edge trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t GPIO_EVT_CH6_ANY_EDGE_ST : 1;/*!< Represents GPIO_evt_ch6_any_edge trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t GPIO_EVT_CH7_ANY_EDGE_ST : 1;/*!< Represents GPIO_evt_ch7_any_edge trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t GPIO_EVT_ZERO_DET_POS0_ST : 1;/*!< Represents GPIO_evt_zero_det_pos0 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t GPIO_EVT_ZERO_DET_NEG0_ST : 1;/*!< Represents GPIO_evt_zero_det_neg0 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t GPIO_EVT_ZERO_DET_POS1_ST : 1;/*!< Represents GPIO_evt_zero_det_pos1 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t GPIO_EVT_ZERO_DET_NEG1_ST : 1;/*!< Represents GPIO_evt_zero_det_neg1 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t LEDC_EVT_DUTY_CHNG_END_CH0_ST : 1;/*!< Represents LEDC_evt_duty_chng_end_ch0 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t LEDC_EVT_DUTY_CHNG_END_CH1_ST : 1;/*!< Represents LEDC_evt_duty_chng_end_ch1 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t LEDC_EVT_DUTY_CHNG_END_CH2_ST : 1;/*!< Represents LEDC_evt_duty_chng_end_ch2 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t LEDC_EVT_DUTY_CHNG_END_CH3_ST : 1;/*!< Represents LEDC_evt_duty_chng_end_ch3 trigger status.\\0: Not - triggered\\1: Triggered */ - } bit; - } EVT_ST0; - - union { - __IOM uint32_t reg; /*!< Events trigger status clear register */ - - struct { - __OM uint32_t GPIO_EVT_CH0_RISE_EDGE_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_evt_ch0_rise_edge trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t GPIO_EVT_CH1_RISE_EDGE_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_evt_ch1_rise_edge trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t GPIO_EVT_CH2_RISE_EDGE_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_evt_ch2_rise_edge trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t GPIO_EVT_CH3_RISE_EDGE_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_evt_ch3_rise_edge trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t GPIO_EVT_CH4_RISE_EDGE_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_evt_ch4_rise_edge trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t GPIO_EVT_CH5_RISE_EDGE_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_evt_ch5_rise_edge trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t GPIO_EVT_CH6_RISE_EDGE_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_evt_ch6_rise_edge trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t GPIO_EVT_CH7_RISE_EDGE_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_evt_ch7_rise_edge trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t GPIO_EVT_CH0_FALL_EDGE_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_evt_ch0_fall_edge trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t GPIO_EVT_CH1_FALL_EDGE_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_evt_ch1_fall_edge trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t GPIO_EVT_CH2_FALL_EDGE_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_evt_ch2_fall_edge trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t GPIO_EVT_CH3_FALL_EDGE_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_evt_ch3_fall_edge trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t GPIO_EVT_CH4_FALL_EDGE_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_evt_ch4_fall_edge trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t GPIO_EVT_CH5_FALL_EDGE_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_evt_ch5_fall_edge trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t GPIO_EVT_CH6_FALL_EDGE_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_evt_ch6_fall_edge trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t GPIO_EVT_CH7_FALL_EDGE_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_evt_ch7_fall_edge trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t GPIO_EVT_CH0_ANY_EDGE_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_evt_ch0_any_edge trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t GPIO_EVT_CH1_ANY_EDGE_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_evt_ch1_any_edge trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t GPIO_EVT_CH2_ANY_EDGE_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_evt_ch2_any_edge trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t GPIO_EVT_CH3_ANY_EDGE_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_evt_ch3_any_edge trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t GPIO_EVT_CH4_ANY_EDGE_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_evt_ch4_any_edge trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t GPIO_EVT_CH5_ANY_EDGE_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_evt_ch5_any_edge trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t GPIO_EVT_CH6_ANY_EDGE_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_evt_ch6_any_edge trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t GPIO_EVT_CH7_ANY_EDGE_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_evt_ch7_any_edge trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t GPIO_EVT_ZERO_DET_POS0_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_evt_zero_det_pos0 trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t GPIO_EVT_ZERO_DET_NEG0_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_evt_zero_det_neg0 trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t GPIO_EVT_ZERO_DET_POS1_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_evt_zero_det_pos1 trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t GPIO_EVT_ZERO_DET_NEG1_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_evt_zero_det_neg1 trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_evt_duty_chng_end_ch0 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_evt_duty_chng_end_ch1 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_evt_duty_chng_end_ch2 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_evt_duty_chng_end_ch3 - trigger status.\\0: Invalid, No effect\\1: Clear */ - } bit; - } EVT_ST0_CLR; - - union { - __IOM uint32_t reg; /*!< Events trigger status register */ - - struct { - __IOM uint32_t LEDC_EVT_DUTY_CHNG_END_CH4_ST : 1;/*!< Represents LEDC_evt_duty_chng_end_ch4 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t LEDC_EVT_DUTY_CHNG_END_CH5_ST : 1;/*!< Represents LEDC_evt_duty_chng_end_ch5 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t LEDC_EVT_DUTY_CHNG_END_CH6_ST : 1;/*!< Represents LEDC_evt_duty_chng_end_ch6 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t LEDC_EVT_DUTY_CHNG_END_CH7_ST : 1;/*!< Represents LEDC_evt_duty_chng_end_ch7 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t LEDC_EVT_OVF_CNT_PLS_CH0_ST : 1;/*!< Represents LEDC_evt_ovf_cnt_pls_ch0 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t LEDC_EVT_OVF_CNT_PLS_CH1_ST : 1;/*!< Represents LEDC_evt_ovf_cnt_pls_ch1 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t LEDC_EVT_OVF_CNT_PLS_CH2_ST : 1;/*!< Represents LEDC_evt_ovf_cnt_pls_ch2 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t LEDC_EVT_OVF_CNT_PLS_CH3_ST : 1;/*!< Represents LEDC_evt_ovf_cnt_pls_ch3 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t LEDC_EVT_OVF_CNT_PLS_CH4_ST : 1;/*!< Represents LEDC_evt_ovf_cnt_pls_ch4 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t LEDC_EVT_OVF_CNT_PLS_CH5_ST : 1;/*!< Represents LEDC_evt_ovf_cnt_pls_ch5 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t LEDC_EVT_OVF_CNT_PLS_CH6_ST : 1;/*!< Represents LEDC_evt_ovf_cnt_pls_ch6 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t LEDC_EVT_OVF_CNT_PLS_CH7_ST : 1;/*!< Represents LEDC_evt_ovf_cnt_pls_ch7 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t LEDC_EVT_TIME_OVF_TIMER0_ST : 1;/*!< Represents LEDC_evt_time_ovf_timer0 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t LEDC_EVT_TIME_OVF_TIMER1_ST : 1;/*!< Represents LEDC_evt_time_ovf_timer1 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t LEDC_EVT_TIME_OVF_TIMER2_ST : 1;/*!< Represents LEDC_evt_time_ovf_timer2 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t LEDC_EVT_TIME_OVF_TIMER3_ST : 1;/*!< Represents LEDC_evt_time_ovf_timer3 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t LEDC_EVT_TIMER0_CMP_ST : 1;/*!< Represents LEDC_evt_timer0_cmp trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t LEDC_EVT_TIMER1_CMP_ST : 1;/*!< Represents LEDC_evt_timer1_cmp trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t LEDC_EVT_TIMER2_CMP_ST : 1;/*!< Represents LEDC_evt_timer2_cmp trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t LEDC_EVT_TIMER3_CMP_ST : 1;/*!< Represents LEDC_evt_timer3_cmp trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t TG0_EVT_CNT_CMP_TIMER0_ST : 1;/*!< Represents TG0_evt_cnt_cmp_timer0 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t TG0_EVT_CNT_CMP_TIMER1_ST : 1;/*!< Represents TG0_evt_cnt_cmp_timer1 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t TG1_EVT_CNT_CMP_TIMER0_ST : 1;/*!< Represents TG1_evt_cnt_cmp_timer0 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t TG1_EVT_CNT_CMP_TIMER1_ST : 1;/*!< Represents TG1_evt_cnt_cmp_timer1 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t SYSTIMER_EVT_CNT_CMP0_ST : 1;/*!< Represents SYSTIMER_evt_cnt_cmp0 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t SYSTIMER_EVT_CNT_CMP1_ST : 1;/*!< Represents SYSTIMER_evt_cnt_cmp1 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t SYSTIMER_EVT_CNT_CMP2_ST : 1;/*!< Represents SYSTIMER_evt_cnt_cmp2 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM0_EVT_TIMER0_STOP_ST : 1;/*!< Represents MCPWM0_evt_timer0_stop trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM0_EVT_TIMER1_STOP_ST : 1;/*!< Represents MCPWM0_evt_timer1_stop trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM0_EVT_TIMER2_STOP_ST : 1;/*!< Represents MCPWM0_evt_timer2_stop trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM0_EVT_TIMER0_TEZ_ST : 1;/*!< Represents MCPWM0_evt_timer0_tez trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM0_EVT_TIMER1_TEZ_ST : 1;/*!< Represents MCPWM0_evt_timer1_tez trigger status.\\0: Not triggered\\1: - Triggered */ - } bit; - } EVT_ST1; - - union { - __IOM uint32_t reg; /*!< Events trigger status clear register */ - - struct { - __OM uint32_t LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_evt_duty_chng_end_ch4 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_evt_duty_chng_end_ch5 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_EVT_DUTY_CHNG_END_CH6_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_evt_duty_chng_end_ch6 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_EVT_DUTY_CHNG_END_CH7_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_evt_duty_chng_end_ch7 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch0 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch1 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch2 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch3 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch4 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch5 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_EVT_OVF_CNT_PLS_CH6_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch6 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_EVT_OVF_CNT_PLS_CH7_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch7 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_EVT_TIME_OVF_TIMER0_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_evt_time_ovf_timer0 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_EVT_TIME_OVF_TIMER1_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_evt_time_ovf_timer1 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_EVT_TIME_OVF_TIMER2_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_evt_time_ovf_timer2 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_EVT_TIME_OVF_TIMER3_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_evt_time_ovf_timer3 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_EVT_TIMER0_CMP_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_evt_timer0_cmp trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_EVT_TIMER1_CMP_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_evt_timer1_cmp trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_EVT_TIMER2_CMP_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_evt_timer2_cmp trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_EVT_TIMER3_CMP_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_evt_timer3_cmp trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t TG0_EVT_CNT_CMP_TIMER0_ST_CLR : 1;/*!< Configures whether or not to clear TG0_evt_cnt_cmp_timer0 trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t TG0_EVT_CNT_CMP_TIMER1_ST_CLR : 1;/*!< Configures whether or not to clear TG0_evt_cnt_cmp_timer1 trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t TG1_EVT_CNT_CMP_TIMER0_ST_CLR : 1;/*!< Configures whether or not to clear TG1_evt_cnt_cmp_timer0 trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t TG1_EVT_CNT_CMP_TIMER1_ST_CLR : 1;/*!< Configures whether or not to clear TG1_evt_cnt_cmp_timer1 trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t SYSTIMER_EVT_CNT_CMP0_ST_CLR : 1;/*!< Configures whether or not to clear SYSTIMER_evt_cnt_cmp0 trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t SYSTIMER_EVT_CNT_CMP1_ST_CLR : 1;/*!< Configures whether or not to clear SYSTIMER_evt_cnt_cmp1 trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t SYSTIMER_EVT_CNT_CMP2_ST_CLR : 1;/*!< Configures whether or not to clear SYSTIMER_evt_cnt_cmp2 trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM0_EVT_TIMER0_STOP_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_timer0_stop trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM0_EVT_TIMER1_STOP_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_timer1_stop trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM0_EVT_TIMER2_STOP_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_timer2_stop trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM0_EVT_TIMER0_TEZ_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_timer0_tez trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM0_EVT_TIMER1_TEZ_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_timer1_tez trigger - status.\\0: Invalid, No effect\\1: Clear */ - } bit; - } EVT_ST1_CLR; - - union { - __IOM uint32_t reg; /*!< Events trigger status register */ - - struct { - __IOM uint32_t MCPWM0_EVT_TIMER2_TEZ_ST : 1;/*!< Represents MCPWM0_evt_timer2_tez trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM0_EVT_TIMER0_TEP_ST : 1;/*!< Represents MCPWM0_evt_timer0_tep trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM0_EVT_TIMER1_TEP_ST : 1;/*!< Represents MCPWM0_evt_timer1_tep trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM0_EVT_TIMER2_TEP_ST : 1;/*!< Represents MCPWM0_evt_timer2_tep trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM0_EVT_OP0_TEA_ST : 1; /*!< Represents MCPWM0_evt_op0_tea trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM0_EVT_OP1_TEA_ST : 1; /*!< Represents MCPWM0_evt_op1_tea trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM0_EVT_OP2_TEA_ST : 1; /*!< Represents MCPWM0_evt_op2_tea trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM0_EVT_OP0_TEB_ST : 1; /*!< Represents MCPWM0_evt_op0_teb trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM0_EVT_OP1_TEB_ST : 1; /*!< Represents MCPWM0_evt_op1_teb trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM0_EVT_OP2_TEB_ST : 1; /*!< Represents MCPWM0_evt_op2_teb trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM0_EVT_F0_ST : 1; /*!< Represents MCPWM0_evt_f0 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM0_EVT_F1_ST : 1; /*!< Represents MCPWM0_evt_f1 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM0_EVT_F2_ST : 1; /*!< Represents MCPWM0_evt_f2 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM0_EVT_F0_CLR_ST : 1; /*!< Represents MCPWM0_evt_f0_clr trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM0_EVT_F1_CLR_ST : 1; /*!< Represents MCPWM0_evt_f1_clr trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM0_EVT_F2_CLR_ST : 1; /*!< Represents MCPWM0_evt_f2_clr trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM0_EVT_TZ0_CBC_ST : 1; /*!< Represents MCPWM0_evt_tz0_cbc trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM0_EVT_TZ1_CBC_ST : 1; /*!< Represents MCPWM0_evt_tz1_cbc trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM0_EVT_TZ2_CBC_ST : 1; /*!< Represents MCPWM0_evt_tz2_cbc trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM0_EVT_TZ0_OST_ST : 1; /*!< Represents MCPWM0_evt_tz0_ost trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM0_EVT_TZ1_OST_ST : 1; /*!< Represents MCPWM0_evt_tz1_ost trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM0_EVT_TZ2_OST_ST : 1; /*!< Represents MCPWM0_evt_tz2_ost trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM0_EVT_CAP0_ST : 1; /*!< Represents MCPWM0_evt_cap0 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM0_EVT_CAP1_ST : 1; /*!< Represents MCPWM0_evt_cap1 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM0_EVT_CAP2_ST : 1; /*!< Represents MCPWM0_evt_cap2 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM0_EVT_OP0_TEE1_ST : 1;/*!< Represents MCPWM0_evt_op0_tee1 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM0_EVT_OP1_TEE1_ST : 1;/*!< Represents MCPWM0_evt_op1_tee1 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM0_EVT_OP2_TEE1_ST : 1;/*!< Represents MCPWM0_evt_op2_tee1 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM0_EVT_OP0_TEE2_ST : 1;/*!< Represents MCPWM0_evt_op0_tee2 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM0_EVT_OP1_TEE2_ST : 1;/*!< Represents MCPWM0_evt_op1_tee2 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM0_EVT_OP2_TEE2_ST : 1;/*!< Represents MCPWM0_evt_op2_tee2 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM1_EVT_TIMER0_STOP_ST : 1;/*!< Represents MCPWM1_evt_timer0_stop trigger status.\\0: Not triggered\\1: - Triggered */ - } bit; - } EVT_ST2; - - union { - __IOM uint32_t reg; /*!< Events trigger status clear register */ - - struct { - __OM uint32_t MCPWM0_EVT_TIMER2_TEZ_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_timer2_tez trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM0_EVT_TIMER0_TEP_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_timer0_tep trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM0_EVT_TIMER1_TEP_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_timer1_tep trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM0_EVT_TIMER2_TEP_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_timer2_tep trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM0_EVT_OP0_TEA_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_op0_tea trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM0_EVT_OP1_TEA_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_op1_tea trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM0_EVT_OP2_TEA_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_op2_tea trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM0_EVT_OP0_TEB_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_op0_teb trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM0_EVT_OP1_TEB_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_op1_teb trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM0_EVT_OP2_TEB_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_op2_teb trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM0_EVT_F0_ST_CLR : 1; /*!< Configures whether or not to clear MCPWM0_evt_f0 trigger status.\\0: - Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM0_EVT_F1_ST_CLR : 1; /*!< Configures whether or not to clear MCPWM0_evt_f1 trigger status.\\0: - Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM0_EVT_F2_ST_CLR : 1; /*!< Configures whether or not to clear MCPWM0_evt_f2 trigger status.\\0: - Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM0_EVT_F0_CLR_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_f0_clr trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM0_EVT_F1_CLR_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_f1_clr trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM0_EVT_F2_CLR_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_f2_clr trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM0_EVT_TZ0_CBC_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_tz0_cbc trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM0_EVT_TZ1_CBC_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_tz1_cbc trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM0_EVT_TZ2_CBC_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_tz2_cbc trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM0_EVT_TZ0_OST_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_tz0_ost trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM0_EVT_TZ1_OST_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_tz1_ost trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM0_EVT_TZ2_OST_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_tz2_ost trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM0_EVT_CAP0_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_cap0 trigger status.\\0: - Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM0_EVT_CAP1_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_cap1 trigger status.\\0: - Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM0_EVT_CAP2_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_cap2 trigger status.\\0: - Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM0_EVT_OP0_TEE1_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_op0_tee1 trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM0_EVT_OP1_TEE1_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_op1_tee1 trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM0_EVT_OP2_TEE1_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_op2_tee1 trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM0_EVT_OP0_TEE2_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_op0_tee2 trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM0_EVT_OP1_TEE2_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_op1_tee2 trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM0_EVT_OP2_TEE2_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_evt_op2_tee2 trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM1_EVT_TIMER0_STOP_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_timer0_stop trigger - status.\\0: Invalid, No effect\\1: Clear */ - } bit; - } EVT_ST2_CLR; - - union { - __IOM uint32_t reg; /*!< Events trigger status register */ - - struct { - __IOM uint32_t MCPWM1_EVT_TIMER1_STOP_ST : 1;/*!< Represents MCPWM1_evt_timer1_stop trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM1_EVT_TIMER2_STOP_ST : 1;/*!< Represents MCPWM1_evt_timer2_stop trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM1_EVT_TIMER0_TEZ_ST : 1;/*!< Represents MCPWM1_evt_timer0_tez trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM1_EVT_TIMER1_TEZ_ST : 1;/*!< Represents MCPWM1_evt_timer1_tez trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM1_EVT_TIMER2_TEZ_ST : 1;/*!< Represents MCPWM1_evt_timer2_tez trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM1_EVT_TIMER0_TEP_ST : 1;/*!< Represents MCPWM1_evt_timer0_tep trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM1_EVT_TIMER1_TEP_ST : 1;/*!< Represents MCPWM1_evt_timer1_tep trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM1_EVT_TIMER2_TEP_ST : 1;/*!< Represents MCPWM1_evt_timer2_tep trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM1_EVT_OP0_TEA_ST : 1; /*!< Represents MCPWM1_evt_op0_tea trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM1_EVT_OP1_TEA_ST : 1; /*!< Represents MCPWM1_evt_op1_tea trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM1_EVT_OP2_TEA_ST : 1; /*!< Represents MCPWM1_evt_op2_tea trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM1_EVT_OP0_TEB_ST : 1; /*!< Represents MCPWM1_evt_op0_teb trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM1_EVT_OP1_TEB_ST : 1; /*!< Represents MCPWM1_evt_op1_teb trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM1_EVT_OP2_TEB_ST : 1; /*!< Represents MCPWM1_evt_op2_teb trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM1_EVT_F0_ST : 1; /*!< Represents MCPWM1_evt_f0 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM1_EVT_F1_ST : 1; /*!< Represents MCPWM1_evt_f1 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM1_EVT_F2_ST : 1; /*!< Represents MCPWM1_evt_f2 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM1_EVT_F0_CLR_ST : 1; /*!< Represents MCPWM1_evt_f0_clr trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM1_EVT_F1_CLR_ST : 1; /*!< Represents MCPWM1_evt_f1_clr trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM1_EVT_F2_CLR_ST : 1; /*!< Represents MCPWM1_evt_f2_clr trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM1_EVT_TZ0_CBC_ST : 1; /*!< Represents MCPWM1_evt_tz0_cbc trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM1_EVT_TZ1_CBC_ST : 1; /*!< Represents MCPWM1_evt_tz1_cbc trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM1_EVT_TZ2_CBC_ST : 1; /*!< Represents MCPWM1_evt_tz2_cbc trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM1_EVT_TZ0_OST_ST : 1; /*!< Represents MCPWM1_evt_tz0_ost trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM1_EVT_TZ1_OST_ST : 1; /*!< Represents MCPWM1_evt_tz1_ost trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM1_EVT_TZ2_OST_ST : 1; /*!< Represents MCPWM1_evt_tz2_ost trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM1_EVT_CAP0_ST : 1; /*!< Represents MCPWM1_evt_cap0 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM1_EVT_CAP1_ST : 1; /*!< Represents MCPWM1_evt_cap1 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM1_EVT_CAP2_ST : 1; /*!< Represents MCPWM1_evt_cap2 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM1_EVT_OP0_TEE1_ST : 1;/*!< Represents MCPWM1_evt_op0_tee1 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM1_EVT_OP1_TEE1_ST : 1;/*!< Represents MCPWM1_evt_op1_tee1 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM1_EVT_OP2_TEE1_ST : 1;/*!< Represents MCPWM1_evt_op2_tee1 trigger status.\\0: Not triggered\\1: - Triggered */ - } bit; - } EVT_ST3; - - union { - __IOM uint32_t reg; /*!< Events trigger status clear register */ - - struct { - __OM uint32_t MCPWM1_EVT_TIMER1_STOP_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_timer1_stop trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM1_EVT_TIMER2_STOP_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_timer2_stop trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM1_EVT_TIMER0_TEZ_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_timer0_tez trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM1_EVT_TIMER1_TEZ_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_timer1_tez trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM1_EVT_TIMER2_TEZ_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_timer2_tez trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM1_EVT_TIMER0_TEP_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_timer0_tep trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM1_EVT_TIMER1_TEP_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_timer1_tep trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM1_EVT_TIMER2_TEP_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_timer2_tep trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM1_EVT_OP0_TEA_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_op0_tea trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM1_EVT_OP1_TEA_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_op1_tea trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM1_EVT_OP2_TEA_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_op2_tea trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM1_EVT_OP0_TEB_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_op0_teb trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM1_EVT_OP1_TEB_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_op1_teb trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM1_EVT_OP2_TEB_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_op2_teb trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM1_EVT_F0_ST_CLR : 1; /*!< Configures whether or not to clear MCPWM1_evt_f0 trigger status.\\0: - Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM1_EVT_F1_ST_CLR : 1; /*!< Configures whether or not to clear MCPWM1_evt_f1 trigger status.\\0: - Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM1_EVT_F2_ST_CLR : 1; /*!< Configures whether or not to clear MCPWM1_evt_f2 trigger status.\\0: - Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM1_EVT_F0_CLR_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_f0_clr trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM1_EVT_F1_CLR_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_f1_clr trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM1_EVT_F2_CLR_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_f2_clr trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM1_EVT_TZ0_CBC_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_tz0_cbc trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM1_EVT_TZ1_CBC_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_tz1_cbc trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM1_EVT_TZ2_CBC_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_tz2_cbc trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM1_EVT_TZ0_OST_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_tz0_ost trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM1_EVT_TZ1_OST_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_tz1_ost trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM1_EVT_TZ2_OST_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_tz2_ost trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM1_EVT_CAP0_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_cap0 trigger status.\\0: - Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM1_EVT_CAP1_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_cap1 trigger status.\\0: - Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM1_EVT_CAP2_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_cap2 trigger status.\\0: - Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM1_EVT_OP0_TEE1_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_op0_tee1 trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM1_EVT_OP1_TEE1_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_op1_tee1 trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM1_EVT_OP2_TEE1_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_op2_tee1 trigger - status.\\0: Invalid, No effect\\1: Clear */ - } bit; - } EVT_ST3_CLR; - - union { - __IOM uint32_t reg; /*!< Events trigger status register */ - - struct { - __IOM uint32_t MCPWM1_EVT_OP0_TEE2_ST : 1;/*!< Represents MCPWM1_evt_op0_tee2 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM1_EVT_OP1_TEE2_ST : 1;/*!< Represents MCPWM1_evt_op1_tee2 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM1_EVT_OP2_TEE2_ST : 1;/*!< Represents MCPWM1_evt_op2_tee2 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t ADC_EVT_CONV_CMPLT0_ST : 1;/*!< Represents ADC_evt_conv_cmplt0 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t ADC_EVT_EQ_ABOVE_THRESH0_ST : 1;/*!< Represents ADC_evt_eq_above_thresh0 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t ADC_EVT_EQ_ABOVE_THRESH1_ST : 1;/*!< Represents ADC_evt_eq_above_thresh1 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t ADC_EVT_EQ_BELOW_THRESH0_ST : 1;/*!< Represents ADC_evt_eq_below_thresh0 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t ADC_EVT_EQ_BELOW_THRESH1_ST : 1;/*!< Represents ADC_evt_eq_below_thresh1 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t ADC_EVT_RESULT_DONE0_ST : 1;/*!< Represents ADC_evt_result_done0 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t ADC_EVT_STOPPED0_ST : 1; /*!< Represents ADC_evt_stopped0 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t ADC_EVT_STARTED0_ST : 1; /*!< Represents ADC_evt_started0 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t REGDMA_EVT_DONE0_ST : 1; /*!< Represents REGDMA_evt_done0 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t REGDMA_EVT_DONE1_ST : 1; /*!< Represents REGDMA_evt_done1 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t REGDMA_EVT_DONE2_ST : 1; /*!< Represents REGDMA_evt_done2 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t REGDMA_EVT_DONE3_ST : 1; /*!< Represents REGDMA_evt_done3 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t REGDMA_EVT_ERR0_ST : 1; /*!< Represents REGDMA_evt_err0 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t REGDMA_EVT_ERR1_ST : 1; /*!< Represents REGDMA_evt_err1 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t REGDMA_EVT_ERR2_ST : 1; /*!< Represents REGDMA_evt_err2 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t REGDMA_EVT_ERR3_ST : 1; /*!< Represents REGDMA_evt_err3 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t TMPSNSR_EVT_OVER_LIMIT_ST : 1;/*!< Represents TMPSNSR_evt_over_limit trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t I2S0_EVT_RX_DONE_ST : 1; /*!< Represents I2S0_evt_rx_done trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t I2S0_EVT_TX_DONE_ST : 1; /*!< Represents I2S0_evt_tx_done trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t I2S0_EVT_X_WORDS_RECEIVED_ST : 1;/*!< Represents I2S0_evt_x_words_received trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t I2S0_EVT_X_WORDS_SENT_ST : 1;/*!< Represents I2S0_evt_x_words_sent trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t I2S1_EVT_RX_DONE_ST : 1; /*!< Represents I2S1_evt_rx_done trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t I2S1_EVT_TX_DONE_ST : 1; /*!< Represents I2S1_evt_tx_done trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t I2S1_EVT_X_WORDS_RECEIVED_ST : 1;/*!< Represents I2S1_evt_x_words_received trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t I2S1_EVT_X_WORDS_SENT_ST : 1;/*!< Represents I2S1_evt_x_words_sent trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t I2S2_EVT_RX_DONE_ST : 1; /*!< Represents I2S2_evt_rx_done trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t I2S2_EVT_TX_DONE_ST : 1; /*!< Represents I2S2_evt_tx_done trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t I2S2_EVT_X_WORDS_RECEIVED_ST : 1;/*!< Represents I2S2_evt_x_words_received trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t I2S2_EVT_X_WORDS_SENT_ST : 1;/*!< Represents I2S2_evt_x_words_sent trigger status.\\0: Not triggered\\1: - Triggered */ - } bit; - } EVT_ST4; - - union { - __IOM uint32_t reg; /*!< Events trigger status clear register */ - - struct { - __OM uint32_t MCPWM1_EVT_OP0_TEE2_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_op0_tee2 trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM1_EVT_OP1_TEE2_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_op1_tee2 trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM1_EVT_OP2_TEE2_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_evt_op2_tee2 trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t ADC_EVT_CONV_CMPLT0_ST_CLR : 1;/*!< Configures whether or not to clear ADC_evt_conv_cmplt0 trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR : 1;/*!< Configures whether or not to clear ADC_evt_eq_above_thresh0 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR : 1;/*!< Configures whether or not to clear ADC_evt_eq_above_thresh1 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t ADC_EVT_EQ_BELOW_THRESH0_ST_CLR : 1;/*!< Configures whether or not to clear ADC_evt_eq_below_thresh0 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t ADC_EVT_EQ_BELOW_THRESH1_ST_CLR : 1;/*!< Configures whether or not to clear ADC_evt_eq_below_thresh1 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t ADC_EVT_RESULT_DONE0_ST_CLR : 1;/*!< Configures whether or not to clear ADC_evt_result_done0 trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t ADC_EVT_STOPPED0_ST_CLR : 1;/*!< Configures whether or not to clear ADC_evt_stopped0 trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t ADC_EVT_STARTED0_ST_CLR : 1;/*!< Configures whether or not to clear ADC_evt_started0 trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t REGDMA_EVT_DONE0_ST_CLR : 1;/*!< Configures whether or not to clear REGDMA_evt_done0 trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t REGDMA_EVT_DONE1_ST_CLR : 1;/*!< Configures whether or not to clear REGDMA_evt_done1 trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t REGDMA_EVT_DONE2_ST_CLR : 1;/*!< Configures whether or not to clear REGDMA_evt_done2 trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t REGDMA_EVT_DONE3_ST_CLR : 1;/*!< Configures whether or not to clear REGDMA_evt_done3 trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t REGDMA_EVT_ERR0_ST_CLR : 1;/*!< Configures whether or not to clear REGDMA_evt_err0 trigger status.\\0: - Invalid, No effect\\1: Clear */ - __OM uint32_t REGDMA_EVT_ERR1_ST_CLR : 1;/*!< Configures whether or not to clear REGDMA_evt_err1 trigger status.\\0: - Invalid, No effect\\1: Clear */ - __OM uint32_t REGDMA_EVT_ERR2_ST_CLR : 1;/*!< Configures whether or not to clear REGDMA_evt_err2 trigger status.\\0: - Invalid, No effect\\1: Clear */ - __OM uint32_t REGDMA_EVT_ERR3_ST_CLR : 1;/*!< Configures whether or not to clear REGDMA_evt_err3 trigger status.\\0: - Invalid, No effect\\1: Clear */ - __OM uint32_t TMPSNSR_EVT_OVER_LIMIT_ST_CLR : 1;/*!< Configures whether or not to clear TMPSNSR_evt_over_limit trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t I2S0_EVT_RX_DONE_ST_CLR : 1;/*!< Configures whether or not to clear I2S0_evt_rx_done trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t I2S0_EVT_TX_DONE_ST_CLR : 1;/*!< Configures whether or not to clear I2S0_evt_tx_done trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t I2S0_EVT_X_WORDS_RECEIVED_ST_CLR : 1;/*!< Configures whether or not to clear I2S0_evt_x_words_received - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t I2S0_EVT_X_WORDS_SENT_ST_CLR : 1;/*!< Configures whether or not to clear I2S0_evt_x_words_sent trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t I2S1_EVT_RX_DONE_ST_CLR : 1;/*!< Configures whether or not to clear I2S1_evt_rx_done trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t I2S1_EVT_TX_DONE_ST_CLR : 1;/*!< Configures whether or not to clear I2S1_evt_tx_done trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t I2S1_EVT_X_WORDS_RECEIVED_ST_CLR : 1;/*!< Configures whether or not to clear I2S1_evt_x_words_received - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t I2S1_EVT_X_WORDS_SENT_ST_CLR : 1;/*!< Configures whether or not to clear I2S1_evt_x_words_sent trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t I2S2_EVT_RX_DONE_ST_CLR : 1;/*!< Configures whether or not to clear I2S2_evt_rx_done trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t I2S2_EVT_TX_DONE_ST_CLR : 1;/*!< Configures whether or not to clear I2S2_evt_tx_done trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t I2S2_EVT_X_WORDS_RECEIVED_ST_CLR : 1;/*!< Configures whether or not to clear I2S2_evt_x_words_received - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t I2S2_EVT_X_WORDS_SENT_ST_CLR : 1;/*!< Configures whether or not to clear I2S2_evt_x_words_sent trigger - status.\\0: Invalid, No effect\\1: Clear */ - } bit; - } EVT_ST4_CLR; - - union { - __IOM uint32_t reg; /*!< Events trigger status register */ - - struct { - __IOM uint32_t ULP_EVT_ERR_INTR_ST : 1; /*!< Represents ULP_evt_err_intr trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t ULP_EVT_HALT_ST : 1; /*!< Represents ULP_evt_halt trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t ULP_EVT_START_INTR_ST : 1; /*!< Represents ULP_evt_start_intr trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t RTC_EVT_TICK_ST : 1; /*!< Represents RTC_evt_tick trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t RTC_EVT_OVF_ST : 1; /*!< Represents RTC_evt_ovf trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t RTC_EVT_CMP_ST : 1; /*!< Represents RTC_evt_cmp trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t PDMA_AHB_EVT_IN_DONE_CH0_ST : 1;/*!< Represents PDMA_AHB_evt_in_done_ch0 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t PDMA_AHB_EVT_IN_DONE_CH1_ST : 1;/*!< Represents PDMA_AHB_evt_in_done_ch1 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t PDMA_AHB_EVT_IN_DONE_CH2_ST : 1;/*!< Represents PDMA_AHB_evt_in_done_ch2 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST : 1;/*!< Represents PDMA_AHB_evt_in_suc_eof_ch0 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST : 1;/*!< Represents PDMA_AHB_evt_in_suc_eof_ch1 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST : 1;/*!< Represents PDMA_AHB_evt_in_suc_eof_ch2 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST : 1;/*!< Represents PDMA_AHB_evt_in_fifo_empty_ch0 trigger status.\\0: - Not triggered\\1: Triggered */ - __IOM uint32_t PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST : 1;/*!< Represents PDMA_AHB_evt_in_fifo_empty_ch1 trigger status.\\0: - Not triggered\\1: Triggered */ - __IOM uint32_t PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST : 1;/*!< Represents PDMA_AHB_evt_in_fifo_empty_ch2 trigger status.\\0: - Not triggered\\1: Triggered */ - __IOM uint32_t PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST : 1;/*!< Represents PDMA_AHB_evt_in_fifo_full_ch0 trigger status.\\0: - Not triggered\\1: Triggered */ - __IOM uint32_t PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST : 1;/*!< Represents PDMA_AHB_evt_in_fifo_full_ch1 trigger status.\\0: - Not triggered\\1: Triggered */ - __IOM uint32_t PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST : 1;/*!< Represents PDMA_AHB_evt_in_fifo_full_ch2 trigger status.\\0: - Not triggered\\1: Triggered */ - __IOM uint32_t PDMA_AHB_EVT_OUT_DONE_CH0_ST : 1;/*!< Represents PDMA_AHB_evt_out_done_ch0 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t PDMA_AHB_EVT_OUT_DONE_CH1_ST : 1;/*!< Represents PDMA_AHB_evt_out_done_ch1 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t PDMA_AHB_EVT_OUT_DONE_CH2_ST : 1;/*!< Represents PDMA_AHB_evt_out_done_ch2 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t PDMA_AHB_EVT_OUT_EOF_CH0_ST : 1;/*!< Represents PDMA_AHB_evt_out_eof_ch0 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t PDMA_AHB_EVT_OUT_EOF_CH1_ST : 1;/*!< Represents PDMA_AHB_evt_out_eof_ch1 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t PDMA_AHB_EVT_OUT_EOF_CH2_ST : 1;/*!< Represents PDMA_AHB_evt_out_eof_ch2 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST : 1;/*!< Represents PDMA_AHB_evt_out_total_eof_ch0 trigger status.\\0: - Not triggered\\1: Triggered */ - __IOM uint32_t PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST : 1;/*!< Represents PDMA_AHB_evt_out_total_eof_ch1 trigger status.\\0: - Not triggered\\1: Triggered */ - __IOM uint32_t PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST : 1;/*!< Represents PDMA_AHB_evt_out_total_eof_ch2 trigger status.\\0: - Not triggered\\1: Triggered */ - __IOM uint32_t PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST : 1;/*!< Represents PDMA_AHB_evt_out_fifo_empty_ch0 trigger status.\\0: - Not triggered\\1: Triggered */ - __IOM uint32_t PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST : 1;/*!< Represents PDMA_AHB_evt_out_fifo_empty_ch1 trigger status.\\0: - Not triggered\\1: Triggered */ - __IOM uint32_t PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST : 1;/*!< Represents PDMA_AHB_evt_out_fifo_empty_ch2 trigger status.\\0: - Not triggered\\1: Triggered */ - __IOM uint32_t PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST : 1;/*!< Represents PDMA_AHB_evt_out_fifo_full_ch0 trigger status.\\0: - Not triggered\\1: Triggered */ - __IOM uint32_t PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST : 1;/*!< Represents PDMA_AHB_evt_out_fifo_full_ch1 trigger status.\\0: - Not triggered\\1: Triggered */ - } bit; - } EVT_ST5; - - union { - __IOM uint32_t reg; /*!< Events trigger status clear register */ - - struct { - __OM uint32_t ULP_EVT_ERR_INTR_ST_CLR : 1;/*!< Configures whether or not to clear ULP_evt_err_intr trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t ULP_EVT_HALT_ST_CLR : 1; /*!< Configures whether or not to clear ULP_evt_halt trigger status.\\0: - Invalid, No effect\\1: Clear */ - __OM uint32_t ULP_EVT_START_INTR_ST_CLR : 1;/*!< Configures whether or not to clear ULP_evt_start_intr trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t RTC_EVT_TICK_ST_CLR : 1; /*!< Configures whether or not to clear RTC_evt_tick trigger status.\\0: - Invalid, No effect\\1: Clear */ - __OM uint32_t RTC_EVT_OVF_ST_CLR : 1; /*!< Configures whether or not to clear RTC_evt_ovf trigger status.\\0: - Invalid, No effect\\1: Clear */ - __OM uint32_t RTC_EVT_CMP_ST_CLR : 1; /*!< Configures whether or not to clear RTC_evt_cmp trigger status.\\0: - Invalid, No effect\\1: Clear */ - __OM uint32_t PDMA_AHB_EVT_IN_DONE_CH0_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_evt_in_done_ch0 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t PDMA_AHB_EVT_IN_DONE_CH1_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_evt_in_done_ch1 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t PDMA_AHB_EVT_IN_DONE_CH2_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_evt_in_done_ch2 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_evt_in_suc_eof_ch0 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_evt_in_suc_eof_ch1 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_evt_in_suc_eof_ch2 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_evt_in_fifo_empty_ch0 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_evt_in_fifo_empty_ch1 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_evt_in_fifo_empty_ch2 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_evt_in_fifo_full_ch0 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_evt_in_fifo_full_ch1 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_evt_in_fifo_full_ch2 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t PDMA_AHB_EVT_OUT_DONE_CH0_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_evt_out_done_ch0 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t PDMA_AHB_EVT_OUT_DONE_CH1_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_evt_out_done_ch1 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t PDMA_AHB_EVT_OUT_DONE_CH2_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_evt_out_done_ch2 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t PDMA_AHB_EVT_OUT_EOF_CH0_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_evt_out_eof_ch0 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t PDMA_AHB_EVT_OUT_EOF_CH1_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_evt_out_eof_ch1 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t PDMA_AHB_EVT_OUT_EOF_CH2_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_evt_out_eof_ch2 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_evt_out_total_eof_ch0 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_evt_out_total_eof_ch1 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_evt_out_total_eof_ch2 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_evt_out_fifo_empty_ch0 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_evt_out_fifo_empty_ch1 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_evt_out_fifo_empty_ch2 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_evt_out_fifo_full_ch0 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_evt_out_fifo_full_ch1 - trigger status.\\0: Invalid, No effect\\1: Clear */ - } bit; - } EVT_ST5_CLR; - - union { - __IOM uint32_t reg; /*!< Events trigger status register */ - - struct { - __IOM uint32_t PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST : 1;/*!< Represents PDMA_AHB_evt_out_fifo_full_ch2 trigger status.\\0: - Not triggered\\1: Triggered */ - __IOM uint32_t PDMA_AXI_EVT_IN_DONE_CH0_ST : 1;/*!< Represents PDMA_AXI_evt_in_done_ch0 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t PDMA_AXI_EVT_IN_DONE_CH1_ST : 1;/*!< Represents PDMA_AXI_evt_in_done_ch1 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t PDMA_AXI_EVT_IN_DONE_CH2_ST : 1;/*!< Represents PDMA_AXI_evt_in_done_ch2 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST : 1;/*!< Represents PDMA_AXI_evt_in_suc_eof_ch0 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST : 1;/*!< Represents PDMA_AXI_evt_in_suc_eof_ch1 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST : 1;/*!< Represents PDMA_AXI_evt_in_suc_eof_ch2 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST : 1;/*!< Represents PDMA_AXI_evt_in_fifo_empty_ch0 trigger status.\\0: - Not triggered\\1: Triggered */ - __IOM uint32_t PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST : 1;/*!< Represents PDMA_AXI_evt_in_fifo_empty_ch1 trigger status.\\0: - Not triggered\\1: Triggered */ - __IOM uint32_t PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST : 1;/*!< Represents PDMA_AXI_evt_in_fifo_empty_ch2 trigger status.\\0: - Not triggered\\1: Triggered */ - __IOM uint32_t PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST : 1;/*!< Represents PDMA_AXI_evt_in_fifo_full_ch0 trigger status.\\0: - Not triggered\\1: Triggered */ - __IOM uint32_t PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST : 1;/*!< Represents PDMA_AXI_evt_in_fifo_full_ch1 trigger status.\\0: - Not triggered\\1: Triggered */ - __IOM uint32_t PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST : 1;/*!< Represents PDMA_AXI_evt_in_fifo_full_ch2 trigger status.\\0: - Not triggered\\1: Triggered */ - __IOM uint32_t PDMA_AXI_EVT_OUT_DONE_CH0_ST : 1;/*!< Represents PDMA_AXI_evt_out_done_ch0 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t PDMA_AXI_EVT_OUT_DONE_CH1_ST : 1;/*!< Represents PDMA_AXI_evt_out_done_ch1 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t PDMA_AXI_EVT_OUT_DONE_CH2_ST : 1;/*!< Represents PDMA_AXI_evt_out_done_ch2 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t PDMA_AXI_EVT_OUT_EOF_CH0_ST : 1;/*!< Represents PDMA_AXI_evt_out_eof_ch0 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t PDMA_AXI_EVT_OUT_EOF_CH1_ST : 1;/*!< Represents PDMA_AXI_evt_out_eof_ch1 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t PDMA_AXI_EVT_OUT_EOF_CH2_ST : 1;/*!< Represents PDMA_AXI_evt_out_eof_ch2 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST : 1;/*!< Represents PDMA_AXI_evt_out_total_eof_ch0 trigger status.\\0: - Not triggered\\1: Triggered */ - __IOM uint32_t PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST : 1;/*!< Represents PDMA_AXI_evt_out_total_eof_ch1 trigger status.\\0: - Not triggered\\1: Triggered */ - __IOM uint32_t PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST : 1;/*!< Represents PDMA_AXI_evt_out_total_eof_ch2 trigger status.\\0: - Not triggered\\1: Triggered */ - __IOM uint32_t PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST : 1;/*!< Represents PDMA_AXI_evt_out_fifo_empty_ch0 trigger status.\\0: - Not triggered\\1: Triggered */ - __IOM uint32_t PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST : 1;/*!< Represents PDMA_AXI_evt_out_fifo_empty_ch1 trigger status.\\0: - Not triggered\\1: Triggered */ - __IOM uint32_t PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST : 1;/*!< Represents PDMA_AXI_evt_out_fifo_empty_ch2 trigger status.\\0: - Not triggered\\1: Triggered */ - __IOM uint32_t PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST : 1;/*!< Represents PDMA_AXI_evt_out_fifo_full_ch0 trigger status.\\0: - Not triggered\\1: Triggered */ - __IOM uint32_t PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST : 1;/*!< Represents PDMA_AXI_evt_out_fifo_full_ch1 trigger status.\\0: - Not triggered\\1: Triggered */ - __IOM uint32_t PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST : 1;/*!< Represents PDMA_AXI_evt_out_fifo_full_ch2 trigger status.\\0: - Not triggered\\1: Triggered */ - __IOM uint32_t PMU_EVT_SLEEP_WEEKUP_ST : 1;/*!< Represents PMU_evt_sleep_weekup trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t DMA2D_EVT_IN_DONE_CH0_ST : 1;/*!< Represents DMA2D_evt_in_done_ch0 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t DMA2D_EVT_IN_DONE_CH1_ST : 1;/*!< Represents DMA2D_evt_in_done_ch1 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t DMA2D_EVT_IN_SUC_EOF_CH0_ST : 1;/*!< Represents DMA2D_evt_in_suc_eof_ch0 trigger status.\\0: Not - triggered\\1: Triggered */ - } bit; - } EVT_ST6; - - union { - __IOM uint32_t reg; /*!< Events trigger status clear register */ - - struct { - __OM uint32_t PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_evt_out_fifo_full_ch2 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t PDMA_AXI_EVT_IN_DONE_CH0_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_evt_in_done_ch0 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t PDMA_AXI_EVT_IN_DONE_CH1_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_evt_in_done_ch1 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t PDMA_AXI_EVT_IN_DONE_CH2_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_evt_in_done_ch2 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_evt_in_suc_eof_ch0 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_evt_in_suc_eof_ch1 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_evt_in_suc_eof_ch2 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_evt_in_fifo_empty_ch0 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_evt_in_fifo_empty_ch1 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_evt_in_fifo_empty_ch2 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_evt_in_fifo_full_ch0 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_evt_in_fifo_full_ch1 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_evt_in_fifo_full_ch2 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t PDMA_AXI_EVT_OUT_DONE_CH0_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_evt_out_done_ch0 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t PDMA_AXI_EVT_OUT_DONE_CH1_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_evt_out_done_ch1 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t PDMA_AXI_EVT_OUT_DONE_CH2_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_evt_out_done_ch2 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t PDMA_AXI_EVT_OUT_EOF_CH0_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_evt_out_eof_ch0 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t PDMA_AXI_EVT_OUT_EOF_CH1_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_evt_out_eof_ch1 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t PDMA_AXI_EVT_OUT_EOF_CH2_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_evt_out_eof_ch2 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_evt_out_total_eof_ch0 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_evt_out_total_eof_ch1 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_evt_out_total_eof_ch2 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_evt_out_fifo_empty_ch0 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_evt_out_fifo_empty_ch1 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_evt_out_fifo_empty_ch2 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_evt_out_fifo_full_ch0 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_evt_out_fifo_full_ch1 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_evt_out_fifo_full_ch2 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t PMU_EVT_SLEEP_WEEKUP_ST_CLR : 1;/*!< Configures whether or not to clear PMU_evt_sleep_weekup trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t DMA2D_EVT_IN_DONE_CH0_ST_CLR : 1;/*!< Configures whether or not to clear DMA2D_evt_in_done_ch0 trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t DMA2D_EVT_IN_DONE_CH1_ST_CLR : 1;/*!< Configures whether or not to clear DMA2D_evt_in_done_ch1 trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t DMA2D_EVT_IN_SUC_EOF_CH0_ST_CLR : 1;/*!< Configures whether or not to clear DMA2D_evt_in_suc_eof_ch0 - trigger status.\\0: Invalid, No effect\\1: Clear */ - } bit; - } EVT_ST6_CLR; - - union { - __IOM uint32_t reg; /*!< Events trigger status register */ - - struct { - __IOM uint32_t DMA2D_EVT_IN_SUC_EOF_CH1_ST : 1;/*!< Represents DMA2D_evt_in_suc_eof_ch1 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t DMA2D_EVT_OUT_DONE_CH0_ST : 1;/*!< Represents DMA2D_evt_out_done_ch0 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t DMA2D_EVT_OUT_DONE_CH1_ST : 1;/*!< Represents DMA2D_evt_out_done_ch1 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t DMA2D_EVT_OUT_DONE_CH2_ST : 1;/*!< Represents DMA2D_evt_out_done_ch2 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t DMA2D_EVT_OUT_EOF_CH0_ST : 1;/*!< Represents DMA2D_evt_out_eof_ch0 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t DMA2D_EVT_OUT_EOF_CH1_ST : 1;/*!< Represents DMA2D_evt_out_eof_ch1 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t DMA2D_EVT_OUT_EOF_CH2_ST : 1;/*!< Represents DMA2D_evt_out_eof_ch2 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST : 1;/*!< Represents DMA2D_evt_out_total_eof_ch0 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST : 1;/*!< Represents DMA2D_evt_out_total_eof_ch1 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST : 1;/*!< Represents DMA2D_evt_out_total_eof_ch2 trigger status.\\0: Not - triggered\\1: Triggered */ - uint32_t : 22; - } bit; - } EVT_ST7; - - union { - __IOM uint32_t reg; /*!< Events trigger status clear register */ - - struct { - __OM uint32_t DMA2D_EVT_IN_SUC_EOF_CH1_ST_CLR : 1;/*!< Configures whether or not to clear DMA2D_evt_in_suc_eof_ch1 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t DMA2D_EVT_OUT_DONE_CH0_ST_CLR : 1;/*!< Configures whether or not to clear DMA2D_evt_out_done_ch0 trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t DMA2D_EVT_OUT_DONE_CH1_ST_CLR : 1;/*!< Configures whether or not to clear DMA2D_evt_out_done_ch1 trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t DMA2D_EVT_OUT_DONE_CH2_ST_CLR : 1;/*!< Configures whether or not to clear DMA2D_evt_out_done_ch2 trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t DMA2D_EVT_OUT_EOF_CH0_ST_CLR : 1;/*!< Configures whether or not to clear DMA2D_evt_out_eof_ch0 trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t DMA2D_EVT_OUT_EOF_CH1_ST_CLR : 1;/*!< Configures whether or not to clear DMA2D_evt_out_eof_ch1 trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t DMA2D_EVT_OUT_EOF_CH2_ST_CLR : 1;/*!< Configures whether or not to clear DMA2D_evt_out_eof_ch2 trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST_CLR : 1;/*!< Configures whether or not to clear DMA2D_evt_out_total_eof_ch0 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST_CLR : 1;/*!< Configures whether or not to clear DMA2D_evt_out_total_eof_ch1 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST_CLR : 1;/*!< Configures whether or not to clear DMA2D_evt_out_total_eof_ch2 - trigger status.\\0: Invalid, No effect\\1: Clear */ - uint32_t : 22; - } bit; - } EVT_ST7_CLR; - - union { - __IOM uint32_t reg; /*!< Tasks trigger status register */ - - struct { - __IOM uint32_t GPIO_TASK_CH0_SET_ST : 1; /*!< Represents GPIO_task_ch0_set trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t GPIO_TASK_CH1_SET_ST : 1; /*!< Represents GPIO_task_ch1_set trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t GPIO_TASK_CH2_SET_ST : 1; /*!< Represents GPIO_task_ch2_set trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t GPIO_TASK_CH3_SET_ST : 1; /*!< Represents GPIO_task_ch3_set trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t GPIO_TASK_CH4_SET_ST : 1; /*!< Represents GPIO_task_ch4_set trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t GPIO_TASK_CH5_SET_ST : 1; /*!< Represents GPIO_task_ch5_set trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t GPIO_TASK_CH6_SET_ST : 1; /*!< Represents GPIO_task_ch6_set trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t GPIO_TASK_CH7_SET_ST : 1; /*!< Represents GPIO_task_ch7_set trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t GPIO_TASK_CH0_CLEAR_ST : 1;/*!< Represents GPIO_task_ch0_clear trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t GPIO_TASK_CH1_CLEAR_ST : 1;/*!< Represents GPIO_task_ch1_clear trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t GPIO_TASK_CH2_CLEAR_ST : 1;/*!< Represents GPIO_task_ch2_clear trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t GPIO_TASK_CH3_CLEAR_ST : 1;/*!< Represents GPIO_task_ch3_clear trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t GPIO_TASK_CH4_CLEAR_ST : 1;/*!< Represents GPIO_task_ch4_clear trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t GPIO_TASK_CH5_CLEAR_ST : 1;/*!< Represents GPIO_task_ch5_clear trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t GPIO_TASK_CH6_CLEAR_ST : 1;/*!< Represents GPIO_task_ch6_clear trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t GPIO_TASK_CH7_CLEAR_ST : 1;/*!< Represents GPIO_task_ch7_clear trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t GPIO_TASK_CH0_TOGGLE_ST : 1;/*!< Represents GPIO_task_ch0_toggle trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t GPIO_TASK_CH1_TOGGLE_ST : 1;/*!< Represents GPIO_task_ch1_toggle trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t GPIO_TASK_CH2_TOGGLE_ST : 1;/*!< Represents GPIO_task_ch2_toggle trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t GPIO_TASK_CH3_TOGGLE_ST : 1;/*!< Represents GPIO_task_ch3_toggle trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t GPIO_TASK_CH4_TOGGLE_ST : 1;/*!< Represents GPIO_task_ch4_toggle trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t GPIO_TASK_CH5_TOGGLE_ST : 1;/*!< Represents GPIO_task_ch5_toggle trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t GPIO_TASK_CH6_TOGGLE_ST : 1;/*!< Represents GPIO_task_ch6_toggle trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t GPIO_TASK_CH7_TOGGLE_ST : 1;/*!< Represents GPIO_task_ch7_toggle trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t LEDC_TASK_TIMER0_RES_UPDATE_ST : 1;/*!< Represents LEDC_task_timer0_res_update trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t LEDC_TASK_TIMER1_RES_UPDATE_ST : 1;/*!< Represents LEDC_task_timer1_res_update trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t LEDC_TASK_TIMER2_RES_UPDATE_ST : 1;/*!< Represents LEDC_task_timer2_res_update trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t LEDC_TASK_TIMER3_RES_UPDATE_ST : 1;/*!< Represents LEDC_task_timer3_res_update trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST : 1;/*!< Represents LEDC_task_duty_scale_update_ch0 trigger status.\\0: - Not triggered\\1: Triggered */ - __IOM uint32_t LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST : 1;/*!< Represents LEDC_task_duty_scale_update_ch1 trigger status.\\0: - Not triggered\\1: Triggered */ - __IOM uint32_t LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST : 1;/*!< Represents LEDC_task_duty_scale_update_ch2 trigger status.\\0: - Not triggered\\1: Triggered */ - __IOM uint32_t LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST : 1;/*!< Represents LEDC_task_duty_scale_update_ch3 trigger status.\\0: - Not triggered\\1: Triggered */ - } bit; - } TASK_ST0; - - union { - __IOM uint32_t reg; /*!< Tasks trigger status clear register */ - - struct { - __OM uint32_t GPIO_TASK_CH0_SET_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_task_ch0_set trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t GPIO_TASK_CH1_SET_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_task_ch1_set trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t GPIO_TASK_CH2_SET_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_task_ch2_set trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t GPIO_TASK_CH3_SET_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_task_ch3_set trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t GPIO_TASK_CH4_SET_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_task_ch4_set trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t GPIO_TASK_CH5_SET_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_task_ch5_set trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t GPIO_TASK_CH6_SET_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_task_ch6_set trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t GPIO_TASK_CH7_SET_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_task_ch7_set trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t GPIO_TASK_CH0_CLEAR_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_task_ch0_clear trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t GPIO_TASK_CH1_CLEAR_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_task_ch1_clear trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t GPIO_TASK_CH2_CLEAR_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_task_ch2_clear trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t GPIO_TASK_CH3_CLEAR_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_task_ch3_clear trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t GPIO_TASK_CH4_CLEAR_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_task_ch4_clear trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t GPIO_TASK_CH5_CLEAR_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_task_ch5_clear trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t GPIO_TASK_CH6_CLEAR_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_task_ch6_clear trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t GPIO_TASK_CH7_CLEAR_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_task_ch7_clear trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t GPIO_TASK_CH0_TOGGLE_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_task_ch0_toggle trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t GPIO_TASK_CH1_TOGGLE_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_task_ch1_toggle trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t GPIO_TASK_CH2_TOGGLE_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_task_ch2_toggle trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t GPIO_TASK_CH3_TOGGLE_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_task_ch3_toggle trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t GPIO_TASK_CH4_TOGGLE_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_task_ch4_toggle trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t GPIO_TASK_CH5_TOGGLE_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_task_ch5_toggle trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t GPIO_TASK_CH6_TOGGLE_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_task_ch6_toggle trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t GPIO_TASK_CH7_TOGGLE_ST_CLR : 1;/*!< Configures whether or not to clear GPIO_task_ch7_toggle trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_timer0_res_update - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_timer1_res_update - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_timer2_res_update - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_timer3_res_update - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_duty_scale_update_ch0 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_duty_scale_update_ch1 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_duty_scale_update_ch2 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_duty_scale_update_ch3 - trigger status.\\0: Invalid, No effect\\1: Clear */ - } bit; - } TASK_ST0_CLR; - - union { - __IOM uint32_t reg; /*!< Tasks trigger status register */ - - struct { - __IOM uint32_t LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST : 1;/*!< Represents LEDC_task_duty_scale_update_ch4 trigger status.\\0: - Not triggered\\1: Triggered */ - __IOM uint32_t LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST : 1;/*!< Represents LEDC_task_duty_scale_update_ch5 trigger status.\\0: - Not triggered\\1: Triggered */ - __IOM uint32_t LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST : 1;/*!< Represents LEDC_task_duty_scale_update_ch6 trigger status.\\0: - Not triggered\\1: Triggered */ - __IOM uint32_t LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST : 1;/*!< Represents LEDC_task_duty_scale_update_ch7 trigger status.\\0: - Not triggered\\1: Triggered */ - __IOM uint32_t LEDC_TASK_TIMER0_CAP_ST : 1;/*!< Represents LEDC_task_timer0_cap trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t LEDC_TASK_TIMER1_CAP_ST : 1;/*!< Represents LEDC_task_timer1_cap trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t LEDC_TASK_TIMER2_CAP_ST : 1;/*!< Represents LEDC_task_timer2_cap trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t LEDC_TASK_TIMER3_CAP_ST : 1;/*!< Represents LEDC_task_timer3_cap trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t LEDC_TASK_SIG_OUT_DIS_CH0_ST : 1;/*!< Represents LEDC_task_sig_out_dis_ch0 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t LEDC_TASK_SIG_OUT_DIS_CH1_ST : 1;/*!< Represents LEDC_task_sig_out_dis_ch1 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t LEDC_TASK_SIG_OUT_DIS_CH2_ST : 1;/*!< Represents LEDC_task_sig_out_dis_ch2 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t LEDC_TASK_SIG_OUT_DIS_CH3_ST : 1;/*!< Represents LEDC_task_sig_out_dis_ch3 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t LEDC_TASK_SIG_OUT_DIS_CH4_ST : 1;/*!< Represents LEDC_task_sig_out_dis_ch4 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t LEDC_TASK_SIG_OUT_DIS_CH5_ST : 1;/*!< Represents LEDC_task_sig_out_dis_ch5 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t LEDC_TASK_SIG_OUT_DIS_CH6_ST : 1;/*!< Represents LEDC_task_sig_out_dis_ch6 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t LEDC_TASK_SIG_OUT_DIS_CH7_ST : 1;/*!< Represents LEDC_task_sig_out_dis_ch7 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t LEDC_TASK_OVF_CNT_RST_CH0_ST : 1;/*!< Represents LEDC_task_ovf_cnt_rst_ch0 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t LEDC_TASK_OVF_CNT_RST_CH1_ST : 1;/*!< Represents LEDC_task_ovf_cnt_rst_ch1 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t LEDC_TASK_OVF_CNT_RST_CH2_ST : 1;/*!< Represents LEDC_task_ovf_cnt_rst_ch2 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t LEDC_TASK_OVF_CNT_RST_CH3_ST : 1;/*!< Represents LEDC_task_ovf_cnt_rst_ch3 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t LEDC_TASK_OVF_CNT_RST_CH4_ST : 1;/*!< Represents LEDC_task_ovf_cnt_rst_ch4 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t LEDC_TASK_OVF_CNT_RST_CH5_ST : 1;/*!< Represents LEDC_task_ovf_cnt_rst_ch5 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t LEDC_TASK_OVF_CNT_RST_CH6_ST : 1;/*!< Represents LEDC_task_ovf_cnt_rst_ch6 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t LEDC_TASK_OVF_CNT_RST_CH7_ST : 1;/*!< Represents LEDC_task_ovf_cnt_rst_ch7 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t LEDC_TASK_TIMER0_RST_ST : 1;/*!< Represents LEDC_task_timer0_rst trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t LEDC_TASK_TIMER1_RST_ST : 1;/*!< Represents LEDC_task_timer1_rst trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t LEDC_TASK_TIMER2_RST_ST : 1;/*!< Represents LEDC_task_timer2_rst trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t LEDC_TASK_TIMER3_RST_ST : 1;/*!< Represents LEDC_task_timer3_rst trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t LEDC_TASK_TIMER0_RESUME_ST : 1;/*!< Represents LEDC_task_timer0_resume trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t LEDC_TASK_TIMER1_RESUME_ST : 1;/*!< Represents LEDC_task_timer1_resume trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t LEDC_TASK_TIMER2_RESUME_ST : 1;/*!< Represents LEDC_task_timer2_resume trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t LEDC_TASK_TIMER3_RESUME_ST : 1;/*!< Represents LEDC_task_timer3_resume trigger status.\\0: Not triggered\\1: - Triggered */ - } bit; - } TASK_ST1; - - union { - __IOM uint32_t reg; /*!< Tasks trigger status clear register */ - - struct { - __OM uint32_t LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_duty_scale_update_ch4 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_duty_scale_update_ch5 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_duty_scale_update_ch6 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_duty_scale_update_ch7 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_TIMER0_CAP_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_timer0_cap trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_TIMER1_CAP_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_timer1_cap trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_TIMER2_CAP_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_timer2_cap trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_TIMER3_CAP_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_timer3_cap trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_sig_out_dis_ch0 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_sig_out_dis_ch1 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_sig_out_dis_ch2 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_sig_out_dis_ch3 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_sig_out_dis_ch4 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_sig_out_dis_ch5 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_SIG_OUT_DIS_CH6_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_sig_out_dis_ch6 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_SIG_OUT_DIS_CH7_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_sig_out_dis_ch7 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch0 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch1 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch2 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch3 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch4 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch5 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_OVF_CNT_RST_CH6_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch6 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_OVF_CNT_RST_CH7_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch7 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_TIMER0_RST_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_timer0_rst trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_TIMER1_RST_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_timer1_rst trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_TIMER2_RST_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_timer2_rst trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_TIMER3_RST_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_timer3_rst trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_TIMER0_RESUME_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_timer0_resume trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_TIMER1_RESUME_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_timer1_resume trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_TIMER2_RESUME_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_timer2_resume trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_TIMER3_RESUME_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_timer3_resume trigger - status.\\0: Invalid, No effect\\1: Clear */ - } bit; - } TASK_ST1_CLR; - - union { - __IOM uint32_t reg; /*!< Tasks trigger status register */ - - struct { - __IOM uint32_t LEDC_TASK_TIMER0_PAUSE_ST : 1;/*!< Represents LEDC_task_timer0_pause trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t LEDC_TASK_TIMER1_PAUSE_ST : 1;/*!< Represents LEDC_task_timer1_pause trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t LEDC_TASK_TIMER2_PAUSE_ST : 1;/*!< Represents LEDC_task_timer2_pause trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t LEDC_TASK_TIMER3_PAUSE_ST : 1;/*!< Represents LEDC_task_timer3_pause trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t LEDC_TASK_GAMMA_RESTART_CH0_ST : 1;/*!< Represents LEDC_task_gamma_restart_ch0 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t LEDC_TASK_GAMMA_RESTART_CH1_ST : 1;/*!< Represents LEDC_task_gamma_restart_ch1 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t LEDC_TASK_GAMMA_RESTART_CH2_ST : 1;/*!< Represents LEDC_task_gamma_restart_ch2 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t LEDC_TASK_GAMMA_RESTART_CH3_ST : 1;/*!< Represents LEDC_task_gamma_restart_ch3 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t LEDC_TASK_GAMMA_RESTART_CH4_ST : 1;/*!< Represents LEDC_task_gamma_restart_ch4 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t LEDC_TASK_GAMMA_RESTART_CH5_ST : 1;/*!< Represents LEDC_task_gamma_restart_ch5 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t LEDC_TASK_GAMMA_RESTART_CH6_ST : 1;/*!< Represents LEDC_task_gamma_restart_ch6 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t LEDC_TASK_GAMMA_RESTART_CH7_ST : 1;/*!< Represents LEDC_task_gamma_restart_ch7 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t LEDC_TASK_GAMMA_PAUSE_CH0_ST : 1;/*!< Represents LEDC_task_gamma_pause_ch0 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t LEDC_TASK_GAMMA_PAUSE_CH1_ST : 1;/*!< Represents LEDC_task_gamma_pause_ch1 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t LEDC_TASK_GAMMA_PAUSE_CH2_ST : 1;/*!< Represents LEDC_task_gamma_pause_ch2 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t LEDC_TASK_GAMMA_PAUSE_CH3_ST : 1;/*!< Represents LEDC_task_gamma_pause_ch3 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t LEDC_TASK_GAMMA_PAUSE_CH4_ST : 1;/*!< Represents LEDC_task_gamma_pause_ch4 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t LEDC_TASK_GAMMA_PAUSE_CH5_ST : 1;/*!< Represents LEDC_task_gamma_pause_ch5 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t LEDC_TASK_GAMMA_PAUSE_CH6_ST : 1;/*!< Represents LEDC_task_gamma_pause_ch6 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t LEDC_TASK_GAMMA_PAUSE_CH7_ST : 1;/*!< Represents LEDC_task_gamma_pause_ch7 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t LEDC_TASK_GAMMA_RESUME_CH0_ST : 1;/*!< Represents LEDC_task_gamma_resume_ch0 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t LEDC_TASK_GAMMA_RESUME_CH1_ST : 1;/*!< Represents LEDC_task_gamma_resume_ch1 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t LEDC_TASK_GAMMA_RESUME_CH2_ST : 1;/*!< Represents LEDC_task_gamma_resume_ch2 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t LEDC_TASK_GAMMA_RESUME_CH3_ST : 1;/*!< Represents LEDC_task_gamma_resume_ch3 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t LEDC_TASK_GAMMA_RESUME_CH4_ST : 1;/*!< Represents LEDC_task_gamma_resume_ch4 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t LEDC_TASK_GAMMA_RESUME_CH5_ST : 1;/*!< Represents LEDC_task_gamma_resume_ch5 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t LEDC_TASK_GAMMA_RESUME_CH6_ST : 1;/*!< Represents LEDC_task_gamma_resume_ch6 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t LEDC_TASK_GAMMA_RESUME_CH7_ST : 1;/*!< Represents LEDC_task_gamma_resume_ch7 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t TG0_TASK_CNT_START_TIMER0_ST : 1;/*!< Represents TG0_task_cnt_start_timer0 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t TG0_TASK_ALARM_START_TIMER0_ST : 1;/*!< Represents TG0_task_alarm_start_timer0 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t TG0_TASK_CNT_STOP_TIMER0_ST : 1;/*!< Represents TG0_task_cnt_stop_timer0 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t TG0_TASK_CNT_RELOAD_TIMER0_ST : 1;/*!< Represents TG0_task_cnt_reload_timer0 trigger status.\\0: Not - triggered\\1: Triggered */ - } bit; - } TASK_ST2; - - union { - __IOM uint32_t reg; /*!< Tasks trigger status clear register */ - - struct { - __OM uint32_t LEDC_TASK_TIMER0_PAUSE_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_timer0_pause trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_TIMER1_PAUSE_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_timer1_pause trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_TIMER2_PAUSE_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_timer2_pause trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_TIMER3_PAUSE_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_timer3_pause trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_gamma_restart_ch0 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_gamma_restart_ch1 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_gamma_restart_ch2 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_gamma_restart_ch3 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_gamma_restart_ch4 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_gamma_restart_ch5 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_GAMMA_RESTART_CH6_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_gamma_restart_ch6 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_GAMMA_RESTART_CH7_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_gamma_restart_ch7 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_gamma_pause_ch0 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_gamma_pause_ch1 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_gamma_pause_ch2 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_gamma_pause_ch3 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_gamma_pause_ch4 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_gamma_pause_ch5 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_GAMMA_PAUSE_CH6_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_gamma_pause_ch6 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_GAMMA_PAUSE_CH7_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_gamma_pause_ch7 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_gamma_resume_ch0 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_gamma_resume_ch1 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_gamma_resume_ch2 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_gamma_resume_ch3 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_gamma_resume_ch4 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_gamma_resume_ch5 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_GAMMA_RESUME_CH6_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_gamma_resume_ch6 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t LEDC_TASK_GAMMA_RESUME_CH7_ST_CLR : 1;/*!< Configures whether or not to clear LEDC_task_gamma_resume_ch7 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t TG0_TASK_CNT_START_TIMER0_ST_CLR : 1;/*!< Configures whether or not to clear TG0_task_cnt_start_timer0 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t TG0_TASK_ALARM_START_TIMER0_ST_CLR : 1;/*!< Configures whether or not to clear TG0_task_alarm_start_timer0 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t TG0_TASK_CNT_STOP_TIMER0_ST_CLR : 1;/*!< Configures whether or not to clear TG0_task_cnt_stop_timer0 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR : 1;/*!< Configures whether or not to clear TG0_task_cnt_reload_timer0 - trigger status.\\0: Invalid, No effect\\1: Clear */ - } bit; - } TASK_ST2_CLR; - - union { - __IOM uint32_t reg; /*!< Tasks trigger status register */ - - struct { - __IOM uint32_t TG0_TASK_CNT_CAP_TIMER0_ST : 1;/*!< Represents TG0_task_cnt_cap_timer0 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t TG0_TASK_CNT_START_TIMER1_ST : 1;/*!< Represents TG0_task_cnt_start_timer1 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t TG0_TASK_ALARM_START_TIMER1_ST : 1;/*!< Represents TG0_task_alarm_start_timer1 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t TG0_TASK_CNT_STOP_TIMER1_ST : 1;/*!< Represents TG0_task_cnt_stop_timer1 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t TG0_TASK_CNT_RELOAD_TIMER1_ST : 1;/*!< Represents TG0_task_cnt_reload_timer1 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t TG0_TASK_CNT_CAP_TIMER1_ST : 1;/*!< Represents TG0_task_cnt_cap_timer1 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t TG1_TASK_CNT_START_TIMER0_ST : 1;/*!< Represents TG1_task_cnt_start_timer0 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t TG1_TASK_ALARM_START_TIMER0_ST : 1;/*!< Represents TG1_task_alarm_start_timer0 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t TG1_TASK_CNT_STOP_TIMER0_ST : 1;/*!< Represents TG1_task_cnt_stop_timer0 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t TG1_TASK_CNT_RELOAD_TIMER0_ST : 1;/*!< Represents TG1_task_cnt_reload_timer0 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t TG1_TASK_CNT_CAP_TIMER0_ST : 1;/*!< Represents TG1_task_cnt_cap_timer0 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t TG1_TASK_CNT_START_TIMER1_ST : 1;/*!< Represents TG1_task_cnt_start_timer1 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t TG1_TASK_ALARM_START_TIMER1_ST : 1;/*!< Represents TG1_task_alarm_start_timer1 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t TG1_TASK_CNT_STOP_TIMER1_ST : 1;/*!< Represents TG1_task_cnt_stop_timer1 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t TG1_TASK_CNT_RELOAD_TIMER1_ST : 1;/*!< Represents TG1_task_cnt_reload_timer1 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t TG1_TASK_CNT_CAP_TIMER1_ST : 1;/*!< Represents TG1_task_cnt_cap_timer1 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM0_TASK_CMPR0_A_UP_ST : 1;/*!< Represents MCPWM0_task_cmpr0_a_up trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM0_TASK_CMPR1_A_UP_ST : 1;/*!< Represents MCPWM0_task_cmpr1_a_up trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM0_TASK_CMPR2_A_UP_ST : 1;/*!< Represents MCPWM0_task_cmpr2_a_up trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM0_TASK_CMPR0_B_UP_ST : 1;/*!< Represents MCPWM0_task_cmpr0_b_up trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM0_TASK_CMPR1_B_UP_ST : 1;/*!< Represents MCPWM0_task_cmpr1_b_up trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM0_TASK_CMPR2_B_UP_ST : 1;/*!< Represents MCPWM0_task_cmpr2_b_up trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM0_TASK_GEN_STOP_ST : 1;/*!< Represents MCPWM0_task_gen_stop trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM0_TASK_TIMER0_SYN_ST : 1;/*!< Represents MCPWM0_task_timer0_syn trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM0_TASK_TIMER1_SYN_ST : 1;/*!< Represents MCPWM0_task_timer1_syn trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM0_TASK_TIMER2_SYN_ST : 1;/*!< Represents MCPWM0_task_timer2_syn trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM0_TASK_TIMER0_PERIOD_UP_ST : 1;/*!< Represents MCPWM0_task_timer0_period_up trigger status.\\0: - Not triggered\\1: Triggered */ - __IOM uint32_t MCPWM0_TASK_TIMER1_PERIOD_UP_ST : 1;/*!< Represents MCPWM0_task_timer1_period_up trigger status.\\0: - Not triggered\\1: Triggered */ - __IOM uint32_t MCPWM0_TASK_TIMER2_PERIOD_UP_ST : 1;/*!< Represents MCPWM0_task_timer2_period_up trigger status.\\0: - Not triggered\\1: Triggered */ - __IOM uint32_t MCPWM0_TASK_TZ0_OST_ST : 1;/*!< Represents MCPWM0_task_tz0_ost trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM0_TASK_TZ1_OST_ST : 1;/*!< Represents MCPWM0_task_tz1_ost trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM0_TASK_TZ2_OST_ST : 1;/*!< Represents MCPWM0_task_tz2_ost trigger status.\\0: Not triggered\\1: - Triggered */ - } bit; - } TASK_ST3; - - union { - __IOM uint32_t reg; /*!< Tasks trigger status clear register */ - - struct { - __OM uint32_t TG0_TASK_CNT_CAP_TIMER0_ST_CLR : 1;/*!< Configures whether or not to clear TG0_task_cnt_cap_timer0 trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t TG0_TASK_CNT_START_TIMER1_ST_CLR : 1;/*!< Configures whether or not to clear TG0_task_cnt_start_timer1 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t TG0_TASK_ALARM_START_TIMER1_ST_CLR : 1;/*!< Configures whether or not to clear TG0_task_alarm_start_timer1 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t TG0_TASK_CNT_STOP_TIMER1_ST_CLR : 1;/*!< Configures whether or not to clear TG0_task_cnt_stop_timer1 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR : 1;/*!< Configures whether or not to clear TG0_task_cnt_reload_timer1 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t TG0_TASK_CNT_CAP_TIMER1_ST_CLR : 1;/*!< Configures whether or not to clear TG0_task_cnt_cap_timer1 trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t TG1_TASK_CNT_START_TIMER0_ST_CLR : 1;/*!< Configures whether or not to clear TG1_task_cnt_start_timer0 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t TG1_TASK_ALARM_START_TIMER0_ST_CLR : 1;/*!< Configures whether or not to clear TG1_task_alarm_start_timer0 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t TG1_TASK_CNT_STOP_TIMER0_ST_CLR : 1;/*!< Configures whether or not to clear TG1_task_cnt_stop_timer0 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR : 1;/*!< Configures whether or not to clear TG1_task_cnt_reload_timer0 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t TG1_TASK_CNT_CAP_TIMER0_ST_CLR : 1;/*!< Configures whether or not to clear TG1_task_cnt_cap_timer0 trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t TG1_TASK_CNT_START_TIMER1_ST_CLR : 1;/*!< Configures whether or not to clear TG1_task_cnt_start_timer1 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t TG1_TASK_ALARM_START_TIMER1_ST_CLR : 1;/*!< Configures whether or not to clear TG1_task_alarm_start_timer1 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t TG1_TASK_CNT_STOP_TIMER1_ST_CLR : 1;/*!< Configures whether or not to clear TG1_task_cnt_stop_timer1 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR : 1;/*!< Configures whether or not to clear TG1_task_cnt_reload_timer1 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t TG1_TASK_CNT_CAP_TIMER1_ST_CLR : 1;/*!< Configures whether or not to clear TG1_task_cnt_cap_timer1 trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM0_TASK_CMPR0_A_UP_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_task_cmpr0_a_up trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM0_TASK_CMPR1_A_UP_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_task_cmpr1_a_up trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM0_TASK_CMPR2_A_UP_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_task_cmpr2_a_up trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM0_TASK_CMPR0_B_UP_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_task_cmpr0_b_up trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM0_TASK_CMPR1_B_UP_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_task_cmpr1_b_up trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM0_TASK_CMPR2_B_UP_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_task_cmpr2_b_up trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM0_TASK_GEN_STOP_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_task_gen_stop trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM0_TASK_TIMER0_SYN_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_task_timer0_syn trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM0_TASK_TIMER1_SYN_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_task_timer1_syn trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM0_TASK_TIMER2_SYN_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_task_timer2_syn trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM0_TASK_TIMER0_PERIOD_UP_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_task_timer0_period_up - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM0_TASK_TIMER1_PERIOD_UP_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_task_timer1_period_up - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM0_TASK_TIMER2_PERIOD_UP_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_task_timer2_period_up - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM0_TASK_TZ0_OST_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_task_tz0_ost trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM0_TASK_TZ1_OST_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_task_tz1_ost trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM0_TASK_TZ2_OST_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_task_tz2_ost trigger - status.\\0: Invalid, No effect\\1: Clear */ - } bit; - } TASK_ST3_CLR; - - union { - __IOM uint32_t reg; /*!< Tasks trigger status register */ - - struct { - __IOM uint32_t MCPWM0_TASK_CLR0_OST_ST : 1;/*!< Represents MCPWM0_task_clr0_ost trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM0_TASK_CLR1_OST_ST : 1;/*!< Represents MCPWM0_task_clr1_ost trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM0_TASK_CLR2_OST_ST : 1;/*!< Represents MCPWM0_task_clr2_ost trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM0_TASK_CAP0_ST : 1; /*!< Represents MCPWM0_task_cap0 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM0_TASK_CAP1_ST : 1; /*!< Represents MCPWM0_task_cap1 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM0_TASK_CAP2_ST : 1; /*!< Represents MCPWM0_task_cap2 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM1_TASK_CMPR0_A_UP_ST : 1;/*!< Represents MCPWM1_task_cmpr0_a_up trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM1_TASK_CMPR1_A_UP_ST : 1;/*!< Represents MCPWM1_task_cmpr1_a_up trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM1_TASK_CMPR2_A_UP_ST : 1;/*!< Represents MCPWM1_task_cmpr2_a_up trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM1_TASK_CMPR0_B_UP_ST : 1;/*!< Represents MCPWM1_task_cmpr0_b_up trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM1_TASK_CMPR1_B_UP_ST : 1;/*!< Represents MCPWM1_task_cmpr1_b_up trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM1_TASK_CMPR2_B_UP_ST : 1;/*!< Represents MCPWM1_task_cmpr2_b_up trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM1_TASK_GEN_STOP_ST : 1;/*!< Represents MCPWM1_task_gen_stop trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM1_TASK_TIMER0_SYN_ST : 1;/*!< Represents MCPWM1_task_timer0_syn trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM1_TASK_TIMER1_SYN_ST : 1;/*!< Represents MCPWM1_task_timer1_syn trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM1_TASK_TIMER2_SYN_ST : 1;/*!< Represents MCPWM1_task_timer2_syn trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM1_TASK_TIMER0_PERIOD_UP_ST : 1;/*!< Represents MCPWM1_task_timer0_period_up trigger status.\\0: - Not triggered\\1: Triggered */ - __IOM uint32_t MCPWM1_TASK_TIMER1_PERIOD_UP_ST : 1;/*!< Represents MCPWM1_task_timer1_period_up trigger status.\\0: - Not triggered\\1: Triggered */ - __IOM uint32_t MCPWM1_TASK_TIMER2_PERIOD_UP_ST : 1;/*!< Represents MCPWM1_task_timer2_period_up trigger status.\\0: - Not triggered\\1: Triggered */ - __IOM uint32_t MCPWM1_TASK_TZ0_OST_ST : 1;/*!< Represents MCPWM1_task_tz0_ost trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM1_TASK_TZ1_OST_ST : 1;/*!< Represents MCPWM1_task_tz1_ost trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM1_TASK_TZ2_OST_ST : 1;/*!< Represents MCPWM1_task_tz2_ost trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM1_TASK_CLR0_OST_ST : 1;/*!< Represents MCPWM1_task_clr0_ost trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM1_TASK_CLR1_OST_ST : 1;/*!< Represents MCPWM1_task_clr1_ost trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM1_TASK_CLR2_OST_ST : 1;/*!< Represents MCPWM1_task_clr2_ost trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM1_TASK_CAP0_ST : 1; /*!< Represents MCPWM1_task_cap0 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM1_TASK_CAP1_ST : 1; /*!< Represents MCPWM1_task_cap1 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t MCPWM1_TASK_CAP2_ST : 1; /*!< Represents MCPWM1_task_cap2 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t ADC_TASK_SAMPLE0_ST : 1; /*!< Represents ADC_task_sample0 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t ADC_TASK_SAMPLE1_ST : 1; /*!< Represents ADC_task_sample1 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t ADC_TASK_START0_ST : 1; /*!< Represents ADC_task_start0 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t ADC_TASK_STOP0_ST : 1; /*!< Represents ADC_task_stop0 trigger status.\\0: Not triggered\\1: - Triggered */ - } bit; - } TASK_ST4; - - union { - __IOM uint32_t reg; /*!< Tasks trigger status clear register */ - - struct { - __OM uint32_t MCPWM0_TASK_CLR0_OST_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_task_clr0_ost trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM0_TASK_CLR1_OST_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_task_clr1_ost trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM0_TASK_CLR2_OST_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_task_clr2_ost trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM0_TASK_CAP0_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_task_cap0 trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM0_TASK_CAP1_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_task_cap1 trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM0_TASK_CAP2_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM0_task_cap2 trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM1_TASK_CMPR0_A_UP_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_task_cmpr0_a_up trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM1_TASK_CMPR1_A_UP_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_task_cmpr1_a_up trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM1_TASK_CMPR2_A_UP_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_task_cmpr2_a_up trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM1_TASK_CMPR0_B_UP_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_task_cmpr0_b_up trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM1_TASK_CMPR1_B_UP_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_task_cmpr1_b_up trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM1_TASK_CMPR2_B_UP_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_task_cmpr2_b_up trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM1_TASK_GEN_STOP_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_task_gen_stop trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM1_TASK_TIMER0_SYN_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_task_timer0_syn trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM1_TASK_TIMER1_SYN_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_task_timer1_syn trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM1_TASK_TIMER2_SYN_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_task_timer2_syn trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM1_TASK_TIMER0_PERIOD_UP_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_task_timer0_period_up - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM1_TASK_TIMER1_PERIOD_UP_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_task_timer1_period_up - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM1_TASK_TIMER2_PERIOD_UP_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_task_timer2_period_up - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM1_TASK_TZ0_OST_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_task_tz0_ost trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM1_TASK_TZ1_OST_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_task_tz1_ost trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM1_TASK_TZ2_OST_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_task_tz2_ost trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM1_TASK_CLR0_OST_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_task_clr0_ost trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM1_TASK_CLR1_OST_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_task_clr1_ost trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM1_TASK_CLR2_OST_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_task_clr2_ost trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM1_TASK_CAP0_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_task_cap0 trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM1_TASK_CAP1_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_task_cap1 trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t MCPWM1_TASK_CAP2_ST_CLR : 1;/*!< Configures whether or not to clear MCPWM1_task_cap2 trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t ADC_TASK_SAMPLE0_ST_CLR : 1;/*!< Configures whether or not to clear ADC_task_sample0 trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t ADC_TASK_SAMPLE1_ST_CLR : 1;/*!< Configures whether or not to clear ADC_task_sample1 trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t ADC_TASK_START0_ST_CLR : 1;/*!< Configures whether or not to clear ADC_task_start0 trigger status.\\0: - Invalid, No effect\\1: Clear */ - __OM uint32_t ADC_TASK_STOP0_ST_CLR : 1; /*!< Configures whether or not to clear ADC_task_stop0 trigger status.\\0: - Invalid, No effect\\1: Clear */ - } bit; - } TASK_ST4_CLR; - - union { - __IOM uint32_t reg; /*!< Tasks trigger status register */ - - struct { - __IOM uint32_t REGDMA_TASK_START0_ST : 1; /*!< Represents REGDMA_task_start0 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t REGDMA_TASK_START1_ST : 1; /*!< Represents REGDMA_task_start1 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t REGDMA_TASK_START2_ST : 1; /*!< Represents REGDMA_task_start2 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t REGDMA_TASK_START3_ST : 1; /*!< Represents REGDMA_task_start3 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t TMPSNSR_TASK_START_SAMPLE_ST : 1;/*!< Represents TMPSNSR_task_start_sample trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t TMPSNSR_TASK_STOP_SAMPLE_ST : 1;/*!< Represents TMPSNSR_task_stop_sample trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t I2S0_TASK_START_RX_ST : 1; /*!< Represents I2S0_task_start_rx trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t I2S0_TASK_START_TX_ST : 1; /*!< Represents I2S0_task_start_tx trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t I2S0_TASK_STOP_RX_ST : 1; /*!< Represents I2S0_task_stop_rx trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t I2S0_TASK_STOP_TX_ST : 1; /*!< Represents I2S0_task_stop_tx trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t I2S1_TASK_START_RX_ST : 1; /*!< Represents I2S1_task_start_rx trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t I2S1_TASK_START_TX_ST : 1; /*!< Represents I2S1_task_start_tx trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t I2S1_TASK_STOP_RX_ST : 1; /*!< Represents I2S1_task_stop_rx trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t I2S1_TASK_STOP_TX_ST : 1; /*!< Represents I2S1_task_stop_tx trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t I2S2_TASK_START_RX_ST : 1; /*!< Represents I2S2_task_start_rx trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t I2S2_TASK_START_TX_ST : 1; /*!< Represents I2S2_task_start_tx trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t I2S2_TASK_STOP_RX_ST : 1; /*!< Represents I2S2_task_stop_rx trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t I2S2_TASK_STOP_TX_ST : 1; /*!< Represents I2S2_task_stop_tx trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t ULP_TASK_WAKEUP_CPU_ST : 1;/*!< Represents ULP_task_wakeup_cpu trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t ULP_TASK_INT_CPU_ST : 1; /*!< Represents ULP_task_int_cpu trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t RTC_TASK_START_ST : 1; /*!< Represents RTC_task_start trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t RTC_TASK_STOP_ST : 1; /*!< Represents RTC_task_stop trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t RTC_TASK_CLR_ST : 1; /*!< Represents RTC_task_clr trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t RTC_TASK_TRIGGERFLW_ST : 1;/*!< Represents RTC_task_triggerflw trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t PDMA_AHB_TASK_IN_START_CH0_ST : 1;/*!< Represents PDMA_AHB_task_in_start_ch0 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t PDMA_AHB_TASK_IN_START_CH1_ST : 1;/*!< Represents PDMA_AHB_task_in_start_ch1 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t PDMA_AHB_TASK_IN_START_CH2_ST : 1;/*!< Represents PDMA_AHB_task_in_start_ch2 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t PDMA_AHB_TASK_OUT_START_CH0_ST : 1;/*!< Represents PDMA_AHB_task_out_start_ch0 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t PDMA_AHB_TASK_OUT_START_CH1_ST : 1;/*!< Represents PDMA_AHB_task_out_start_ch1 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t PDMA_AHB_TASK_OUT_START_CH2_ST : 1;/*!< Represents PDMA_AHB_task_out_start_ch2 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t PDMA_AXI_TASK_IN_START_CH0_ST : 1;/*!< Represents PDMA_AXI_task_in_start_ch0 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t PDMA_AXI_TASK_IN_START_CH1_ST : 1;/*!< Represents PDMA_AXI_task_in_start_ch1 trigger status.\\0: Not - triggered\\1: Triggered */ - } bit; - } TASK_ST5; - - union { - __IOM uint32_t reg; /*!< Tasks trigger status clear register */ - - struct { - __OM uint32_t REGDMA_TASK_START0_ST_CLR : 1;/*!< Configures whether or not to clear REGDMA_task_start0 trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t REGDMA_TASK_START1_ST_CLR : 1;/*!< Configures whether or not to clear REGDMA_task_start1 trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t REGDMA_TASK_START2_ST_CLR : 1;/*!< Configures whether or not to clear REGDMA_task_start2 trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t REGDMA_TASK_START3_ST_CLR : 1;/*!< Configures whether or not to clear REGDMA_task_start3 trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t TMPSNSR_TASK_START_SAMPLE_ST_CLR : 1;/*!< Configures whether or not to clear TMPSNSR_task_start_sample - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t TMPSNSR_TASK_STOP_SAMPLE_ST_CLR : 1;/*!< Configures whether or not to clear TMPSNSR_task_stop_sample - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t I2S0_TASK_START_RX_ST_CLR : 1;/*!< Configures whether or not to clear I2S0_task_start_rx trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t I2S0_TASK_START_TX_ST_CLR : 1;/*!< Configures whether or not to clear I2S0_task_start_tx trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t I2S0_TASK_STOP_RX_ST_CLR : 1;/*!< Configures whether or not to clear I2S0_task_stop_rx trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t I2S0_TASK_STOP_TX_ST_CLR : 1;/*!< Configures whether or not to clear I2S0_task_stop_tx trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t I2S1_TASK_START_RX_ST_CLR : 1;/*!< Configures whether or not to clear I2S1_task_start_rx trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t I2S1_TASK_START_TX_ST_CLR : 1;/*!< Configures whether or not to clear I2S1_task_start_tx trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t I2S1_TASK_STOP_RX_ST_CLR : 1;/*!< Configures whether or not to clear I2S1_task_stop_rx trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t I2S1_TASK_STOP_TX_ST_CLR : 1;/*!< Configures whether or not to clear I2S1_task_stop_tx trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t I2S2_TASK_START_RX_ST_CLR : 1;/*!< Configures whether or not to clear I2S2_task_start_rx trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t I2S2_TASK_START_TX_ST_CLR : 1;/*!< Configures whether or not to clear I2S2_task_start_tx trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t I2S2_TASK_STOP_RX_ST_CLR : 1;/*!< Configures whether or not to clear I2S2_task_stop_rx trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t I2S2_TASK_STOP_TX_ST_CLR : 1;/*!< Configures whether or not to clear I2S2_task_stop_tx trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t ULP_TASK_WAKEUP_CPU_ST_CLR : 1;/*!< Configures whether or not to clear ULP_task_wakeup_cpu trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t ULP_TASK_INT_CPU_ST_CLR : 1;/*!< Configures whether or not to clear ULP_task_int_cpu trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t RTC_TASK_START_ST_CLR : 1; /*!< Configures whether or not to clear RTC_task_start trigger status.\\0: - Invalid, No effect\\1: Clear */ - __OM uint32_t RTC_TASK_STOP_ST_CLR : 1; /*!< Configures whether or not to clear RTC_task_stop trigger status.\\0: - Invalid, No effect\\1: Clear */ - __OM uint32_t RTC_TASK_CLR_ST_CLR : 1; /*!< Configures whether or not to clear RTC_task_clr trigger status.\\0: - Invalid, No effect\\1: Clear */ - __OM uint32_t RTC_TASK_TRIGGERFLW_ST_CLR : 1;/*!< Configures whether or not to clear RTC_task_triggerflw trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t PDMA_AHB_TASK_IN_START_CH0_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_task_in_start_ch0 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t PDMA_AHB_TASK_IN_START_CH1_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_task_in_start_ch1 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t PDMA_AHB_TASK_IN_START_CH2_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_task_in_start_ch2 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t PDMA_AHB_TASK_OUT_START_CH0_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_task_out_start_ch0 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t PDMA_AHB_TASK_OUT_START_CH1_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_task_out_start_ch1 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t PDMA_AHB_TASK_OUT_START_CH2_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AHB_task_out_start_ch2 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t PDMA_AXI_TASK_IN_START_CH0_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_task_in_start_ch0 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t PDMA_AXI_TASK_IN_START_CH1_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_task_in_start_ch1 - trigger status.\\0: Invalid, No effect\\1: Clear */ - } bit; - } TASK_ST5_CLR; - - union { - __IOM uint32_t reg; /*!< Tasks trigger status register */ - - struct { - __IOM uint32_t PDMA_AXI_TASK_IN_START_CH2_ST : 1;/*!< Represents PDMA_AXI_task_in_start_ch2 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t PDMA_AXI_TASK_OUT_START_CH0_ST : 1;/*!< Represents PDMA_AXI_task_out_start_ch0 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t PDMA_AXI_TASK_OUT_START_CH1_ST : 1;/*!< Represents PDMA_AXI_task_out_start_ch1 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t PDMA_AXI_TASK_OUT_START_CH2_ST : 1;/*!< Represents PDMA_AXI_task_out_start_ch2 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t PMU_TASK_SLEEP_REQ_ST : 1; /*!< Represents PMU_task_sleep_req trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t DMA2D_TASK_IN_START_CH0_ST : 1;/*!< Represents DMA2D_task_in_start_ch0 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t DMA2D_TASK_IN_START_CH1_ST : 1;/*!< Represents DMA2D_task_in_start_ch1 trigger status.\\0: Not triggered\\1: - Triggered */ - __IOM uint32_t DMA2D_TASK_IN_DSCR_READY_CH0_ST : 1;/*!< Represents DMA2D_task_in_dscr_ready_ch0 trigger status.\\0: - Not triggered\\1: Triggered */ - __IOM uint32_t DMA2D_TASK_IN_DSCR_READY_CH1_ST : 1;/*!< Represents DMA2D_task_in_dscr_ready_ch1 trigger status.\\0: - Not triggered\\1: Triggered */ - __IOM uint32_t DMA2D_TASK_OUT_START_CH0_ST : 1;/*!< Represents DMA2D_task_out_start_ch0 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t DMA2D_TASK_OUT_START_CH1_ST : 1;/*!< Represents DMA2D_task_out_start_ch1 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t DMA2D_TASK_OUT_START_CH2_ST : 1;/*!< Represents DMA2D_task_out_start_ch2 trigger status.\\0: Not - triggered\\1: Triggered */ - __IOM uint32_t DMA2D_TASK_OUT_DSCR_READY_CH0_ST : 1;/*!< Represents DMA2D_task_out_dscr_ready_ch0 trigger status.\\0: - Not triggered\\1: Triggered */ - __IOM uint32_t DMA2D_TASK_OUT_DSCR_READY_CH1_ST : 1;/*!< Represents DMA2D_task_out_dscr_ready_ch1 trigger status.\\0: - Not triggered\\1: Triggered */ - __IOM uint32_t DMA2D_TASK_OUT_DSCR_READY_CH2_ST : 1;/*!< Represents DMA2D_task_out_dscr_ready_ch2 trigger status.\\0: - Not triggered\\1: Triggered */ - uint32_t : 17; - } bit; - } TASK_ST6; - - union { - __IOM uint32_t reg; /*!< Tasks trigger status clear register */ - - struct { - __OM uint32_t PDMA_AXI_TASK_IN_START_CH2_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_task_in_start_ch2 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t PDMA_AXI_TASK_OUT_START_CH0_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_task_out_start_ch0 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t PDMA_AXI_TASK_OUT_START_CH1_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_task_out_start_ch1 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t PDMA_AXI_TASK_OUT_START_CH2_ST_CLR : 1;/*!< Configures whether or not to clear PDMA_AXI_task_out_start_ch2 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t PMU_TASK_SLEEP_REQ_ST_CLR : 1;/*!< Configures whether or not to clear PMU_task_sleep_req trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t DMA2D_TASK_IN_START_CH0_ST_CLR : 1;/*!< Configures whether or not to clear DMA2D_task_in_start_ch0 trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t DMA2D_TASK_IN_START_CH1_ST_CLR : 1;/*!< Configures whether or not to clear DMA2D_task_in_start_ch1 trigger - status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t DMA2D_TASK_IN_DSCR_READY_CH0_ST_CLR : 1;/*!< Configures whether or not to clear DMA2D_task_in_dscr_ready_ch0 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t DMA2D_TASK_IN_DSCR_READY_CH1_ST_CLR : 1;/*!< Configures whether or not to clear DMA2D_task_in_dscr_ready_ch1 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t DMA2D_TASK_OUT_START_CH0_ST_CLR : 1;/*!< Configures whether or not to clear DMA2D_task_out_start_ch0 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t DMA2D_TASK_OUT_START_CH1_ST_CLR : 1;/*!< Configures whether or not to clear DMA2D_task_out_start_ch1 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t DMA2D_TASK_OUT_START_CH2_ST_CLR : 1;/*!< Configures whether or not to clear DMA2D_task_out_start_ch2 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t DMA2D_TASK_OUT_DSCR_READY_CH0_ST_CLR : 1;/*!< Configures whether or not to clear DMA2D_task_out_dscr_ready_ch0 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t DMA2D_TASK_OUT_DSCR_READY_CH1_ST_CLR : 1;/*!< Configures whether or not to clear DMA2D_task_out_dscr_ready_ch1 - trigger status.\\0: Invalid, No effect\\1: Clear */ - __OM uint32_t DMA2D_TASK_OUT_DSCR_READY_CH2_ST_CLR : 1;/*!< Configures whether or not to clear DMA2D_task_out_dscr_ready_ch2 - trigger status.\\0: Invalid, No effect\\1: Clear */ - uint32_t : 17; - } bit; - } TASK_ST6_CLR; - - union { - __IOM uint32_t reg; /*!< ETM clock enable register */ - - struct { - __IOM uint32_t CLK_EN : 1; /*!< Configures whether or not to open register clock gate.\\0: Open - the clock gate only when application writes registers\\1: - Force open the clock gate for register */ - uint32_t : 31; - } bit; - } CLK_EN; - - union { - __IOM uint32_t reg; /*!< ETM date register */ - - struct { - __IOM uint32_t DATE : 28; /*!< Configures the version. */ - uint32_t : 4; - } bit; - } DATE; -} SOC_ETM_Type; /*!< Size = 552 (0x228) */ - - - -/* =========================================================================================================================== */ -/* ================ SPI0 ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief SPI (Serial Peripheral Interface) Controller 0 (SPI0) - */ - -typedef struct { /*!< SPI0 Structure */ - - union { - __IOM uint32_t reg; /*!< SPI0 FSM status register */ - - struct { - __IM uint32_t SPI_MEM_MST_ST : 4; /*!< The current status of SPI0 master FSM: spi0_mst_st. 0: idle - state, 1:SPI0_GRANT , 2: program/erase suspend state, 3: - SPI0 read data state, 4: wait cache/EDMA sent data is stored - in SPI0 TX FIFO, 5: SPI0 write data state. */ - __IM uint32_t SPI_MEM_SLV_ST : 4; /*!< The current status of SPI0 slave FSM: mspi_st. 0: idle state, - 1: preparation state, 2: send command state, 3: send address - state, 4: wait state, 5: read data state, 6:write data - state, 7: done state, 8: read data end state. */ - uint32_t : 10; - __IM uint32_t SPI_MEM_USR : 1; /*!< SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is - cleared. An operation will be triggered when the bit is - set. The bit will be cleared once the operation done.1: - enable 0: disable. */ - uint32_t : 13; - } bit; - } SPI_MEM_CMD; - __IM uint32_t RESERVED; - - union { - __IOM uint32_t reg; /*!< SPI0 control register. */ - - struct { - __IOM uint32_t SPI_MEM_WDUMMY_DQS_ALWAYS_OUT : 1;/*!< In the dummy phase of an MSPI write data transfer when accesses - to flash, the level of SPI_DQS is output by the MSPI controller. */ - __IOM uint32_t SPI_MEM_WDUMMY_ALWAYS_OUT : 1;/*!< In the dummy phase of an MSPI write data transfer when accesses - to flash, the level of SPI_IO[7:0] is output by the MSPI - controller. */ - __IOM uint32_t SPI_MEM_FDUMMY_RIN : 1; /*!< In an MSPI read data transfer when accesses to flash, the level - of SPI_IO[7:0] is output by the MSPI controller in the - first half part of dummy phase. It is used to mask invalid - SPI_DQS in the half part of dummy phase. */ - __IOM uint32_t SPI_MEM_FDUMMY_WOUT : 1; /*!< In an MSPI write data transfer when accesses to flash, the level - of SPI_IO[7:0] is output by the MSPI controller in the - second half part of dummy phase. It is used to pre-drive - flash. */ - __IOM uint32_t SPI_MEM_FDOUT_OCT : 1; /*!< Apply 8 signals during write-data phase 1:enable 0: disable */ - __IOM uint32_t SPI_MEM_FDIN_OCT : 1; /*!< Apply 8 signals during read-data phase 1:enable 0: disable */ - __IOM uint32_t SPI_MEM_FADDR_OCT : 1; /*!< Apply 8 signals during address phase 1:enable 0: disable */ - uint32_t : 1; - __IOM uint32_t SPI_MEM_FCMD_QUAD : 1; /*!< Apply 4 signals during command phase 1:enable 0: disable */ - __IOM uint32_t SPI_MEM_FCMD_OCT : 1; /*!< Apply 8 signals during command phase 1:enable 0: disable */ - uint32_t : 3; - __IOM uint32_t SPI_MEM_FASTRD_MODE : 1; /*!< This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, - SPI_MEM_FREAD_QOUT and SPI_MEM_FREAD_DOUT. 1: enable 0: - disable. */ - __IOM uint32_t SPI_MEM_FREAD_DUAL : 1; /*!< In the read operations, read-data phase apply 2 signals. 1: - enable 0: disable. */ - uint32_t : 3; - __IOM uint32_t SPI_MEM_Q_POL : 1; /*!< The bit is used to set MISO line polarity, 1: high 0, low */ - __IOM uint32_t SPI_MEM_D_POL : 1; /*!< The bit is used to set MOSI line polarity, 1: high 0, low */ - __IOM uint32_t SPI_MEM_FREAD_QUAD : 1; /*!< In the read operations read-data phase apply 4 signals. 1: enable - 0: disable. */ - __IOM uint32_t SPI_MEM_WP : 1; /*!< Write protect signal output when SPI is idle. 1: output high, - 0: output low. */ - uint32_t : 1; - __IOM uint32_t SPI_MEM_FREAD_DIO : 1; /*!< In the read operations address phase and read-data phase apply - 2 signals. 1: enable 0: disable. */ - __IOM uint32_t SPI_MEM_FREAD_QIO : 1; /*!< In the read operations address phase and read-data phase apply - 4 signals. 1: enable 0: disable. */ - uint32_t : 5; - __IOM uint32_t SPI_MEM_DQS_IE_ALWAYS_ON : 1;/*!< When accesses to flash, 1: the IE signals of pads connected - to SPI_DQS are always 1. 0: Others. */ - __IOM uint32_t SPI_MEM_DATA_IE_ALWAYS_ON : 1;/*!< When accesses to flash, 1: the IE signals of pads connected - to SPI_IO[7:0] are always 1. 0: Others. */ - } bit; - } SPI_MEM_CTRL; - - union { - __IOM uint32_t reg; /*!< SPI0 control1 register. */ - - struct { - __IOM uint32_t SPI_MEM_CLK_MODE : 2; /*!< SPI clock mode bits. 0: SPI clock is off when CS inactive 1: - SPI clock is delayed one cycle after CS inactive 2: SPI - clock is delayed two cycles after CS inactive 3: SPI clock - is alwasy on. */ - uint32_t : 19; - __IOM uint32_t SPI_AR_SIZE0_1_SUPPORT_EN : 1;/*!< 1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address - is 4*n and reply the real AXI read data back. 0: When ARSIZE - 0~1, MSPI reply SLV_ERR. */ - __IOM uint32_t SPI_AW_SIZE0_1_SUPPORT_EN : 1;/*!< 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply - SLV_ERR. */ - __IOM uint32_t SPI_AXI_RDATA_BACK_FAST : 1;/*!< 1: Reply AXI read data to AXI bus when one AXI read beat data - is available. 0: Reply AXI read data to AXI bus when all - the read data is available. */ - __IOM uint32_t SPI_MEM_RRESP_ECC_ERR_EN : 1;/*!< 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. - 0: RRESP is OKAY when there is a ECC error in AXI read - data. The ECC error information is recorded in SPI_MEM_ECC_ERR_ADDR_REG. */ - __IOM uint32_t SPI_MEM_AR_SPLICE_EN : 1; /*!< Set this bit to enable AXI Read Splice-transfer. */ - __IOM uint32_t SPI_MEM_AW_SPLICE_EN : 1; /*!< Set this bit to enable AXI Write Splice-transfer. */ - __IM uint32_t SPI_MEM_RAM0_EN : 1; /*!< When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only - EXT_RAM0 will be accessed. When SPI_MEM_DUAL_RAM_EN is - 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 will be accessed. - When SPI_MEM_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will - be accessed at the same time. */ - __IM uint32_t SPI_MEM_DUAL_RAM_EN : 1; /*!< Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 - will be accessed at the same time. */ - __IOM uint32_t SPI_MEM_FAST_WRITE_EN : 1; /*!< Set this bit to write data faster, do not wait write data has - been stored in tx_bus_fifo_l2. It will wait 4*T_clk_ctrl - to insure the write data has been stored in tx_bus_fifo_l2. */ - __OM uint32_t SPI_MEM_RXFIFO_RST : 1; /*!< The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI - SYNC FIFO to receive signals from AXI. Set this bit to - reset these FIFO. */ - __OM uint32_t SPI_MEM_TXFIFO_RST : 1; /*!< The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI - SYNC FIFO to send signals to AXI. Set this bit to reset - these FIFO. */ - } bit; - } SPI_MEM_CTRL1; - - union { - __IOM uint32_t reg; /*!< SPI0 control2 register. */ - - struct { - __IOM uint32_t SPI_MEM_CS_SETUP_TIME : 5; /*!< (cycles-1) of prepare phase by SPI Bus clock, this bits are - combined with SPI_MEM_CS_SETUP bit. */ - __IOM uint32_t SPI_MEM_CS_HOLD_TIME : 5; /*!< SPI CS signal is delayed to inactive by SPI bus clock, this - bits are combined with SPI_MEM_CS_HOLD bit. */ - __IOM uint32_t SPI_MEM_ECC_CS_HOLD_TIME : 3;/*!< SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 - CS hold cycle in ECC mode when accessed flash. */ - __IOM uint32_t SPI_MEM_ECC_SKIP_PAGE_CORNER : 1;/*!< 1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not - skip page corner when accesses flash. */ - __IOM uint32_t SPI_MEM_ECC_16TO18_BYTE_EN : 1;/*!< Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with - 2 ECC bytes mode when accesses flash. */ - uint32_t : 9; - __IOM uint32_t SPI_MEM_SPLIT_TRANS_EN : 1;/*!< Set this bit to enable SPI0 split one AXI read flash transfer - into two SPI transfers when one transfer will cross flash - or EXT_RAM page corner, valid no matter whether there is - an ECC region or not. */ - __IOM uint32_t SPI_MEM_CS_HOLD_DELAY : 6; /*!< These bits are used to set the minimum CS high time tSHSL between - SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELA - [5:0] + 1) MSPI core clock cycles. */ - __OM uint32_t SPI_MEM_SYNC_RESET : 1; /*!< The spi0_mst_st and spi0_slv_st will be reset. */ - } bit; - } SPI_MEM_CTRL2; - - union { - __IOM uint32_t reg; /*!< SPI clock division control register. */ - - struct { - __IOM uint32_t SPI_MEM_CLKCNT_L : 8; /*!< In the master mode it must be equal to spi_mem_clkcnt_N. */ - __IOM uint32_t SPI_MEM_CLKCNT_H : 8; /*!< In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). */ - __IOM uint32_t SPI_MEM_CLKCNT_N : 8; /*!< In the master mode it is the divider of spi_mem_clk. So spi_mem_clk - frequency is system/(spi_mem_clkcnt_N+1) */ - uint32_t : 7; - __IOM uint32_t SPI_MEM_CLK_EQU_SYSCLK : 1;/*!< 1: 1-division mode, the frequency of SPI bus clock equals to - that of MSPI module clock. */ - } bit; - } SPI_MEM_CLOCK; - - union { - __IOM uint32_t reg; /*!< SPI0 user register. */ - - struct { - uint32_t : 6; - __IOM uint32_t SPI_MEM_CS_HOLD : 1; /*!< spi cs keep low when spi is in done phase. 1: enable 0: disable. */ - __IOM uint32_t SPI_MEM_CS_SETUP : 1; /*!< spi cs is enable when spi is in prepare phase. 1: enable 0: - disable. */ - uint32_t : 1; - __IOM uint32_t SPI_MEM_CK_OUT_EDGE : 1; /*!< The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI - clock mode 0~3. */ - uint32_t : 16; - __IOM uint32_t SPI_MEM_USR_DUMMY_IDLE : 1;/*!< spi clock is disable in dummy phase when the bit is enable. */ - uint32_t : 2; - __IOM uint32_t SPI_MEM_USR_DUMMY : 1; /*!< This bit enable the dummy phase of an operation. */ - uint32_t : 2; - } bit; - } SPI_MEM_USER; - - union { - __IOM uint32_t reg; /*!< SPI0 user1 register. */ - - struct { - __IOM uint32_t SPI_MEM_USR_DUMMY_CYCLELEN : 6;/*!< The length in spi_mem_clk cycles of dummy phase. The register - value shall be (cycle_num-1). */ - __IM uint32_t SPI_MEM_USR_DBYTELEN : 3; /*!< SPI0 USR_CMD read or write data byte length -1 */ - uint32_t : 17; - __IOM uint32_t SPI_MEM_USR_ADDR_BITLEN : 6;/*!< The length in bits of address phase. The register value shall - be (bit_num-1). */ - } bit; - } SPI_MEM_USER1; - - union { - __IOM uint32_t reg; /*!< SPI0 user2 register. */ - - struct { - __IOM uint32_t SPI_MEM_USR_COMMAND_VALUE : 16;/*!< The value of command. */ - uint32_t : 12; - __IOM uint32_t SPI_MEM_USR_COMMAND_BITLEN : 4;/*!< The length in bits of command phase. The register value shall - be (bit_num-1) */ - } bit; - } SPI_MEM_USER2; - __IM uint32_t RESERVED1[2]; - - union { - __IOM uint32_t reg; /*!< SPI0 read control register. */ - - struct { - uint32_t : 16; - __IOM uint32_t SPI_MEM_WB_MODE : 8; /*!< Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode - bit. */ - uint32_t : 8; - } bit; - } SPI_MEM_RD_STATUS; - __IM uint32_t RESERVED2; - - union { - __IOM uint32_t reg; /*!< SPI0 misc register */ - - struct { - uint32_t : 7; - __IOM uint32_t SPI_MEM_FSUB_PIN : 1; /*!< For SPI0, flash is connected to SUBPINs. */ - __IOM uint32_t SPI_MEM_SSUB_PIN : 1; /*!< For SPI0, sram is connected to SUBPINs. */ - __IOM uint32_t SPI_MEM_CK_IDLE_EDGE : 1; /*!< 1: SPI_CLK line is high when idle 0: spi clk line is low when - idle */ - __IOM uint32_t SPI_MEM_CS_KEEP_ACTIVE : 1;/*!< SPI_CS line keep low when the bit is set. */ - uint32_t : 21; - } bit; - } SPI_MEM_MISC; - __IM uint32_t RESERVED3; - - union { - __IOM uint32_t reg; /*!< SPI0 bit mode control register. */ - - struct { - __IOM uint32_t SPI_MEM_AXI_REQ_EN : 1; /*!< For SPI0, AXI master access enable, 1: enable, 0:disable. */ - __IOM uint32_t SPI_MEM_CACHE_USR_ADDR_4BYTE : 1;/*!< For SPI0, cache read flash with 4 bytes address, 1: enable, - 0:disable. */ - __IOM uint32_t SPI_MEM_CACHE_FLASH_USR_CMD : 1;/*!< For SPI0, cache read flash for user define command, 1: enable, - 0:disable. */ - __IOM uint32_t SPI_MEM_FDIN_DUAL : 1; /*!< For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. - The bit is the same with spi_mem_fread_dio. */ - __IOM uint32_t SPI_MEM_FDOUT_DUAL : 1; /*!< For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. - The bit is the same with spi_mem_fread_dio. */ - __IOM uint32_t SPI_MEM_FADDR_DUAL : 1; /*!< For SPI0 flash, address phase apply 2 signals. 1: enable 0: - disable. The bit is the same with spi_mem_fread_dio. */ - __IOM uint32_t SPI_MEM_FDIN_QUAD : 1; /*!< For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. - The bit is the same with spi_mem_fread_qio. */ - __IOM uint32_t SPI_MEM_FDOUT_QUAD : 1; /*!< For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. - The bit is the same with spi_mem_fread_qio. */ - __IOM uint32_t SPI_MEM_FADDR_QUAD : 1; /*!< For SPI0 flash, address phase apply 4 signals. 1: enable 0: - disable. The bit is the same with spi_mem_fread_qio. */ - uint32_t : 21; - __IOM uint32_t SPI_SAME_AW_AR_ADDR_CHK_EN : 1;/*!< Set this bit to check AXI read/write the same address region. */ - __IOM uint32_t SPI_CLOSE_AXI_INF_EN : 1; /*!< Set this bit to close AXI read/write transfer to MSPI, which - means that only SLV_ERR will be replied to BRESP/RRESP. */ - } bit; - } SPI_MEM_CACHE_FCTRL; - - union { - __IOM uint32_t reg; /*!< SPI0 external RAM control register */ - - struct { - __IOM uint32_t SPI_MEM_CACHE_USR_SADDR_4BYTE : 1;/*!< For SPI0, In the external RAM mode, cache read flash with 4 - bytes command, 1: enable, 0:disable. */ - __IOM uint32_t SPI_MEM_USR_SRAM_DIO : 1; /*!< For SPI0, In the external RAM mode, spi dual I/O mode enable, - 1: enable, 0:disable */ - __IOM uint32_t SPI_MEM_USR_SRAM_QIO : 1; /*!< For SPI0, In the external RAM mode, spi quad I/O mode enable, - 1: enable, 0:disable */ - __IOM uint32_t SPI_MEM_USR_WR_SRAM_DUMMY : 1;/*!< For SPI0, In the external RAM mode, it is the enable bit of - dummy phase for write operations. */ - __IOM uint32_t SPI_MEM_USR_RD_SRAM_DUMMY : 1;/*!< For SPI0, In the external RAM mode, it is the enable bit of - dummy phase for read operations. */ - __IOM uint32_t SPI_MEM_CACHE_SRAM_USR_RCMD : 1;/*!< For SPI0, In the external RAM mode cache read external RAM for - user define command. */ - __IOM uint32_t SPI_MEM_SRAM_RDUMMY_CYCLELEN : 6;/*!< For SPI0, In the external RAM mode, it is the length in bits - of read dummy phase. The register value shall be (bit_num-1). */ - uint32_t : 2; - __IOM uint32_t SPI_MEM_SRAM_ADDR_BITLEN : 6;/*!< For SPI0, In the external RAM mode, it is the length in bits - of address phase. The register value shall be (bit_num-1). */ - __IOM uint32_t SPI_MEM_CACHE_SRAM_USR_WCMD : 1;/*!< For SPI0, In the external RAM mode cache write sram for user - define command */ - __IOM uint32_t SPI_MEM_SRAM_OCT : 1; /*!< reserved */ - __IOM uint32_t SPI_MEM_SRAM_WDUMMY_CYCLELEN : 6;/*!< For SPI0, In the external RAM mode, it is the length in bits - of write dummy phase. The register value shall be (bit_num-1). */ - uint32_t : 4; - } bit; - } SPI_MEM_CACHE_SCTRL; - - union { - __IOM uint32_t reg; /*!< SPI0 external RAM mode control register */ - - struct { - __IOM uint32_t SPI_MEM_SCLK_MODE : 2; /*!< SPI clock mode bits. 0: SPI clock is off when CS inactive 1: - SPI clock is delayed one cycle after CS inactive 2: SPI - clock is delayed two cycles after CS inactive 3: SPI clock - is always on. */ - __IOM uint32_t SPI_MEM_SWB_MODE : 8; /*!< Mode bits in the external RAM fast read mode it is combined - with spi_mem_fastrd_mode bit. */ - __IOM uint32_t SPI_MEM_SDIN_DUAL : 1; /*!< For SPI0 external RAM , din phase apply 2 signals. 1: enable - 0: disable. The bit is the same with spi_mem_usr_sram_dio. */ - __IOM uint32_t SPI_MEM_SDOUT_DUAL : 1; /*!< For SPI0 external RAM , dout phase apply 2 signals. 1: enable - 0: disable. The bit is the same with spi_mem_usr_sram_dio. */ - __IOM uint32_t SPI_MEM_SADDR_DUAL : 1; /*!< For SPI0 external RAM , address phase apply 2 signals. 1: enable - 0: disable. The bit is the same with spi_mem_usr_sram_dio. */ - uint32_t : 1; - __IOM uint32_t SPI_MEM_SDIN_QUAD : 1; /*!< For SPI0 external RAM , din phase apply 4 signals. 1: enable - 0: disable. The bit is the same with spi_mem_usr_sram_qio. */ - __IOM uint32_t SPI_MEM_SDOUT_QUAD : 1; /*!< For SPI0 external RAM , dout phase apply 4 signals. 1: enable - 0: disable. The bit is the same with spi_mem_usr_sram_qio. */ - __IOM uint32_t SPI_MEM_SADDR_QUAD : 1; /*!< For SPI0 external RAM , address phase apply 4 signals. 1: enable - 0: disable. The bit is the same with spi_mem_usr_sram_qio. */ - __IOM uint32_t SPI_MEM_SCMD_QUAD : 1; /*!< For SPI0 external RAM , cmd phase apply 4 signals. 1: enable - 0: disable. The bit is the same with spi_mem_usr_sram_qio. */ - __IOM uint32_t SPI_MEM_SDIN_OCT : 1; /*!< For SPI0 external RAM , din phase apply 8 signals. 1: enable - 0: disable. */ - __IOM uint32_t SPI_MEM_SDOUT_OCT : 1; /*!< For SPI0 external RAM , dout phase apply 8 signals. 1: enable - 0: disable. */ - __IOM uint32_t SPI_MEM_SADDR_OCT : 1; /*!< For SPI0 external RAM , address phase apply 4 signals. 1: enable - 0: disable. */ - __IOM uint32_t SPI_MEM_SCMD_OCT : 1; /*!< For SPI0 external RAM , cmd phase apply 8 signals. 1: enable - 0: disable. */ - __IOM uint32_t SPI_MEM_SDUMMY_RIN : 1; /*!< In the dummy phase of a MSPI read data transfer when accesses - to external RAM, the signal level of SPI bus is output - by the MSPI controller. */ - __IOM uint32_t SPI_MEM_SDUMMY_WOUT : 1; /*!< In the dummy phase of a MSPI write data transfer when accesses - to external RAM, the signal level of SPI bus is output - by the MSPI controller. */ - __IOM uint32_t SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT : 1;/*!< In the dummy phase of an MSPI write data transfer when accesses - to external RAM, the level of SPI_DQS is output by the - MSPI controller. */ - __IOM uint32_t SPI_SMEM_WDUMMY_ALWAYS_OUT : 1;/*!< In the dummy phase of an MSPI write data transfer when accesses - to external RAM, the level of SPI_IO[7:0] is output by - the MSPI controller. */ - __IOM uint32_t SPI_MEM_SDIN_HEX : 1; /*!< For SPI0 external RAM , din phase apply 16 signals. 1: enable - 0: disable. */ - __IOM uint32_t SPI_MEM_SDOUT_HEX : 1; /*!< For SPI0 external RAM , dout phase apply 16 signals. 1: enable - 0: disable. */ - uint32_t : 2; - __IOM uint32_t SPI_SMEM_DQS_IE_ALWAYS_ON : 1;/*!< When accesses to external RAM, 1: the IE signals of pads connected - to SPI_DQS are always 1. 0: Others. */ - __IOM uint32_t SPI_SMEM_DATA_IE_ALWAYS_ON : 1;/*!< When accesses to external RAM, 1: the IE signals of pads connected - to SPI_IO[7:0] are always 1. 0: Others. */ - } bit; - } SPI_MEM_SRAM_CMD; - - union { - __IOM uint32_t reg; /*!< SPI0 external RAM DDR read command control register */ - - struct { - __IOM uint32_t SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE : 16;/*!< For SPI0,When cache mode is enable it is the read command value - of command phase for sram. */ - uint32_t : 12; - __IOM uint32_t SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN : 4;/*!< For SPI0,When cache mode is enable it is the length in bits - of command phase for sram. The register value shall be - (bit_num-1). */ - } bit; - } SPI_MEM_SRAM_DRD_CMD; - - union { - __IOM uint32_t reg; /*!< SPI0 external RAM DDR write command control register */ - - struct { - __IOM uint32_t SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE : 16;/*!< For SPI0,When cache mode is enable it is the write command value - of command phase for sram. */ - uint32_t : 12; - __IOM uint32_t SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN : 4;/*!< For SPI0,When cache mode is enable it is the in bits of command - phase for sram. The register value shall be (bit_num-1). */ - } bit; - } SPI_MEM_SRAM_DWR_CMD; - - union { - __IOM uint32_t reg; /*!< SPI0 external RAM clock control register */ - - struct { - __IOM uint32_t SPI_MEM_SCLKCNT_L : 8; /*!< For SPI0 external RAM interface, it must be equal to spi_mem_clkcnt_N. */ - __IOM uint32_t SPI_MEM_SCLKCNT_H : 8; /*!< For SPI0 external RAM interface, it must be floor((spi_mem_clkcnt_N+1)/2-1). */ - __IOM uint32_t SPI_MEM_SCLKCNT_N : 8; /*!< For SPI0 external RAM interface, it is the divider of spi_mem_clk. - So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1) */ - uint32_t : 7; - __IOM uint32_t SPI_MEM_SCLK_EQU_SYSCLK : 1;/*!< For SPI0 external RAM interface, 1: spi_mem_clk is eqaul to - system 0: spi_mem_clk is divided from system clock. */ - } bit; - } SPI_MEM_SRAM_CLK; - - union { - __IOM uint32_t reg; /*!< SPI0 FSM status register */ - - struct { - uint32_t : 7; - __IOM uint32_t SPI_MEM_LOCK_DELAY_TIME : 5;/*!< The lock delay time of SPI0/1 arbiter by spi0_slv_st, after - PER is sent by SPI1. */ - uint32_t : 20; - } bit; - } SPI_MEM_FSM; - __IM uint32_t RESERVED4[26]; - - union { - __IOM uint32_t reg; /*!< SPI0 interrupt enable register */ - - struct { - uint32_t : 3; - __IOM uint32_t SPI_MEM_SLV_ST_END_INT_ENA : 1;/*!< The enable bit for SPI_MEM_SLV_ST_END_INT interrupt. */ - __IOM uint32_t SPI_MEM_MST_ST_END_INT_ENA : 1;/*!< The enable bit for SPI_MEM_MST_ST_END_INT interrupt. */ - __IOM uint32_t SPI_MEM_ECC_ERR_INT_ENA : 1;/*!< The enable bit for SPI_MEM_ECC_ERR_INT interrupt. */ - __IOM uint32_t SPI_MEM_PMS_REJECT_INT_ENA : 1;/*!< The enable bit for SPI_MEM_PMS_REJECT_INT interrupt. */ - __IOM uint32_t SPI_MEM_AXI_RADDR_ERR_INT_ENA : 1;/*!< The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. */ - __IOM uint32_t SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA : 1;/*!< The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. */ - __IOM uint32_t SPI_MEM_AXI_WADDR_ERR_INT__ENA : 1;/*!< The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. */ - uint32_t : 18; - __IOM uint32_t SPI_MEM_DQS0_AFIFO_OVF_INT_ENA : 1;/*!< The enable bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. */ - __IOM uint32_t SPI_MEM_DQS1_AFIFO_OVF_INT_ENA : 1;/*!< The enable bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. */ - __IOM uint32_t SPI_MEM_BUS_FIFO1_UDF_INT_ENA : 1;/*!< The enable bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. */ - __IOM uint32_t SPI_MEM_BUS_FIFO0_UDF_INT_ENA : 1;/*!< The enable bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. */ - } bit; - } SPI_MEM_INT_ENA; - - union { - __IOM uint32_t reg; /*!< SPI0 interrupt clear register */ - - struct { - uint32_t : 3; - __OM uint32_t SPI_MEM_SLV_ST_END_INT_CLR : 1;/*!< The clear bit for SPI_MEM_SLV_ST_END_INT interrupt. */ - __OM uint32_t SPI_MEM_MST_ST_END_INT_CLR : 1;/*!< The clear bit for SPI_MEM_MST_ST_END_INT interrupt. */ - __OM uint32_t SPI_MEM_ECC_ERR_INT_CLR : 1;/*!< The clear bit for SPI_MEM_ECC_ERR_INT interrupt. */ - __OM uint32_t SPI_MEM_PMS_REJECT_INT_CLR : 1;/*!< The clear bit for SPI_MEM_PMS_REJECT_INT interrupt. */ - __OM uint32_t SPI_MEM_AXI_RADDR_ERR_INT_CLR : 1;/*!< The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. */ - __OM uint32_t SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR : 1;/*!< The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. */ - __OM uint32_t SPI_MEM_AXI_WADDR_ERR_INT_CLR : 1;/*!< The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. */ - uint32_t : 18; - __OM uint32_t SPI_MEM_DQS0_AFIFO_OVF_INT_CLR : 1;/*!< The clear bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. */ - __OM uint32_t SPI_MEM_DQS1_AFIFO_OVF_INT_CLR : 1;/*!< The clear bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. */ - __OM uint32_t SPI_MEM_BUS_FIFO1_UDF_INT_CLR : 1;/*!< The clear bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. */ - __OM uint32_t SPI_MEM_BUS_FIFO0_UDF_INT_CLR : 1;/*!< The clear bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. */ - } bit; - } SPI_MEM_INT_CLR; - - union { - __IOM uint32_t reg; /*!< SPI0 interrupt raw register */ - - struct { - uint32_t : 3; - __IOM uint32_t SPI_MEM_SLV_ST_END_INT_RAW : 1;/*!< The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered - when spi0_slv_st is changed from non idle state to idle - state. It means that SPI_CS raises high. 0: Others */ - __IOM uint32_t SPI_MEM_MST_ST_END_INT_RAW : 1;/*!< The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered - when spi0_mst_st is changed from non idle state to idle - state. 0: Others. */ - __IOM uint32_t SPI_MEM_ECC_ERR_INT_RAW : 1;/*!< The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN - is set and SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit - is triggered when the error times of SPI0/1 ECC read flash - are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When - SPI_FMEM_ECC_ERR_INT_EN is cleared and SPI_SMEM_ECC_ERR_INT_EN - is set, this bit is triggered when the error times of SPI0/1 - ECC read external RAM are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. - When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN - are set, this bit is triggered when the total error times - of SPI0/1 ECC read external RAM and flash are equal or - bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN - and SPI_SMEM_ECC_ERR_INT_EN are cleared, this bit will - not be triggered. */ - __IOM uint32_t SPI_MEM_PMS_REJECT_INT_RAW : 1;/*!< The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered - when SPI1 access is rejected. 0: Others. */ - __IOM uint32_t SPI_MEM_AXI_RADDR_ERR_INT_RAW : 1;/*!< The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered - when AXI read address is invalid by compared to MMU configuration. - 0: Others. */ - __IOM uint32_t SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW : 1;/*!< The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered - when AXI write flash request is received. 0: Others. */ - __IOM uint32_t SPI_MEM_AXI_WADDR_ERR_INT_RAW : 1;/*!< The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered - when AXI write address is invalid by compared to MMU configuration. - 0: Others. */ - uint32_t : 18; - __IOM uint32_t SPI_MEM_DQS0_AFIFO_OVF_INT_RAW : 1;/*!< The raw bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. 1: Triggered - when the AFIFO connected to SPI_DQS1 is overflow. */ - __IOM uint32_t SPI_MEM_DQS1_AFIFO_OVF_INT_RAW : 1;/*!< The raw bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. 1: Triggered - when the AFIFO connected to SPI_DQS is overflow. */ - __IOM uint32_t SPI_MEM_BUS_FIFO1_UDF_INT_RAW : 1;/*!< The raw bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. 1: Triggered - when BUS1 FIFO is underflow. */ - __IOM uint32_t SPI_MEM_BUS_FIFO0_UDF_INT_RAW : 1;/*!< The raw bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. 1: Triggered - when BUS0 FIFO is underflow. */ - } bit; - } SPI_MEM_INT_RAW; - - union { - __IOM uint32_t reg; /*!< SPI0 interrupt status register */ - - struct { - uint32_t : 3; - __IM uint32_t SPI_MEM_SLV_ST_END_INT_ST : 1;/*!< The status bit for SPI_MEM_SLV_ST_END_INT interrupt. */ - __IM uint32_t SPI_MEM_MST_ST_END_INT_ST : 1;/*!< The status bit for SPI_MEM_MST_ST_END_INT interrupt. */ - __IM uint32_t SPI_MEM_ECC_ERR_INT_ST : 1;/*!< The status bit for SPI_MEM_ECC_ERR_INT interrupt. */ - __IM uint32_t SPI_MEM_PMS_REJECT_INT_ST : 1;/*!< The status bit for SPI_MEM_PMS_REJECT_INT interrupt. */ - __IM uint32_t SPI_MEM_AXI_RADDR_ERR_INT_ST : 1;/*!< The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. */ - __IM uint32_t SPI_MEM_AXI_WR_FLASH_ERR_INT_ST : 1;/*!< The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. */ - __IM uint32_t SPI_MEM_AXI_WADDR_ERR_INT_ST : 1;/*!< The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. */ - uint32_t : 18; - __IM uint32_t SPI_MEM_DQS0_AFIFO_OVF_INT_ST : 1;/*!< The status bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. */ - __IM uint32_t SPI_MEM_DQS1_AFIFO_OVF_INT_ST : 1;/*!< The status bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. */ - __IM uint32_t SPI_MEM_BUS_FIFO1_UDF_INT_ST : 1;/*!< The status bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. */ - __IM uint32_t SPI_MEM_BUS_FIFO0_UDF_INT_ST : 1;/*!< The status bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. */ - } bit; - } SPI_MEM_INT_ST; - __IM uint32_t RESERVED5; - - union { - __IOM uint32_t reg; /*!< SPI0 flash DDR mode control register */ - - struct { - __IOM uint32_t SPI_FMEM_DDR_EN : 1; /*!< 1: in DDR mode, 0 in SDR mode */ - __IOM uint32_t SPI_FMEM_VAR_DUMMY : 1; /*!< Set the bit to enable variable dummy cycle in spi DDR mode. */ - __IOM uint32_t SPI_FMEM_DDR_RDAT_SWP : 1; /*!< Set the bit to reorder rx data of the word in spi DDR mode. */ - __IOM uint32_t SPI_FMEM_DDR_WDAT_SWP : 1; /*!< Set the bit to reorder tx data of the word in spi DDR mode. */ - __IOM uint32_t SPI_FMEM_DDR_CMD_DIS : 1; /*!< the bit is used to disable dual edge in command phase when DDR - mode. */ - __IOM uint32_t SPI_FMEM_OUTMINBYTELEN : 7;/*!< It is the minimum output data length in the panda device. */ - __IOM uint32_t SPI_FMEM_TX_DDR_MSK_EN : 1;/*!< Set this bit to mask the first or the last byte in SPI0 ECC - DDR write mode, when accesses to flash. */ - __IOM uint32_t SPI_FMEM_RX_DDR_MSK_EN : 1;/*!< Set this bit to mask the first or the last byte in SPI0 ECC - DDR read mode, when accesses to flash. */ - __IOM uint32_t SPI_FMEM_USR_DDR_DQS_THD : 7;/*!< The delay number of data strobe which from memory based on SPI - clock. */ - __IOM uint32_t SPI_FMEM_DDR_DQS_LOOP : 1; /*!< 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive - data when spi0_slv_st is in SPI_MEM_DIN state. It is used - when there is no SPI_DQS signal or SPI_DQS signal is not - stable. 0: SPI0 starts to store data at the positive and - negative edge of SPI_DQS. */ - uint32_t : 2; - __IOM uint32_t SPI_FMEM_CLK_DIFF_EN : 1; /*!< Set this bit to enable the differential SPI_CLK#. */ - uint32_t : 1; - __IOM uint32_t SPI_FMEM_DQS_CA_IN : 1; /*!< Set this bit to enable the input of SPI_DQS signal in SPI phases - of CMD and ADDR. */ - __IOM uint32_t SPI_FMEM_HYPERBUS_DUMMY_2X : 1;/*!< Set this bit to enable the vary dummy function in SPI HyperBus - mode, when SPI0 accesses flash or SPI1 accesses flash or - sram. */ - __IOM uint32_t SPI_FMEM_CLK_DIFF_INV : 1; /*!< Set this bit to invert SPI_DIFF when accesses to flash. . */ - __IOM uint32_t SPI_FMEM_OCTA_RAM_ADDR : 1;/*!< Set this bit to enable octa_ram address out when accesses to - flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], - 6'd0, spi_usr_addr_value[3:1], 1'b0}. */ - __IOM uint32_t SPI_FMEM_HYPERBUS_CA : 1; /*!< Set this bit to enable HyperRAM address out when accesses to - flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], - 13'd0, spi_usr_addr_value[3:1]}. */ - uint32_t : 1; - } bit; - } SPI_MEM_DDR; - - union { - __IOM uint32_t reg; /*!< SPI0 external RAM DDR mode control register */ - - struct { - __IOM uint32_t EN : 1; /*!< 1: in DDR mode, 0 in SDR mode */ - __IOM uint32_t SPI_SMEM_VAR_DUMMY : 1; /*!< Set the bit to enable variable dummy cycle in spi DDR mode. */ - __IOM uint32_t RDAT_SWP : 1; /*!< Set the bit to reorder rx data of the word in spi DDR mode. */ - __IOM uint32_t WDAT_SWP : 1; /*!< Set the bit to reorder tx data of the word in spi DDR mode. */ - __IOM uint32_t CMD_DIS : 1; /*!< the bit is used to disable dual edge in command phase when DDR - mode. */ - __IOM uint32_t SPI_SMEM_OUTMINBYTELEN : 7;/*!< It is the minimum output data length in the DDR psram. */ - __IOM uint32_t SPI_SMEM_TX_DDR_MSK_EN : 1;/*!< Set this bit to mask the first or the last byte in SPI0 ECC - DDR write mode, when accesses to external RAM. */ - __IOM uint32_t SPI_SMEM_RX_DDR_MSK_EN : 1;/*!< Set this bit to mask the first or the last byte in SPI0 ECC - DDR read mode, when accesses to external RAM. */ - __IOM uint32_t SPI_SMEM_USR_DDR_DQS_THD : 7;/*!< The delay number of data strobe which from memory based on SPI - clock. */ - __IOM uint32_t DQS_LOOP : 1; /*!< 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive - data when spi0_slv_st is in SPI_MEM_DIN state. It is used - when there is no SPI_DQS signal or SPI_DQS signal is not - stable. 0: SPI0 starts to store data at the positive and - negative edge of SPI_DQS. */ - uint32_t : 2; - __IOM uint32_t SPI_SMEM_CLK_DIFF_EN : 1; /*!< Set this bit to enable the differential SPI_CLK#. */ - uint32_t : 1; - __IOM uint32_t SPI_SMEM_DQS_CA_IN : 1; /*!< Set this bit to enable the input of SPI_DQS signal in SPI phases - of CMD and ADDR. */ - __IOM uint32_t SPI_SMEM_HYPERBUS_DUMMY_2X : 1;/*!< Set this bit to enable the vary dummy function in SPI HyperBus - mode, when SPI0 accesses flash or SPI1 accesses flash or - sram. */ - __IOM uint32_t SPI_SMEM_CLK_DIFF_INV : 1; /*!< Set this bit to invert SPI_DIFF when accesses to external RAM. - . */ - __IOM uint32_t SPI_SMEM_OCTA_RAM_ADDR : 1;/*!< Set this bit to enable octa_ram address out when accesses to - external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], - 6'd0, spi_usr_addr_value[3:1], 1'b0}. */ - __IOM uint32_t SPI_SMEM_HYPERBUS_CA : 1; /*!< Set this bit to enable HyperRAM address out when accesses to - external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], - 13'd0, spi_usr_addr_value[3:1]}. */ - uint32_t : 1; - } bit; - } SPI_SMEM_DDR; - __IM uint32_t RESERVED6[9]; - __IOM uint32_t SPI_FMEM_PMS0_ATTR; /*!< MSPI flash PMS section 0 attribute register */ - __IM uint32_t RESERVED7[3]; - - union { - __IOM uint32_t SPI_FMEM_PMS1_ATTR; /*!< MSPI flash PMS section 1 attribute register */ - __IOM uint32_t SPI_FMEM_PMS0_ADDR; /*!< SPI1 flash PMS section 0 start address register */ - }; - __IM uint32_t RESERVED8[3]; - - union { - __IOM uint32_t SPI_FMEM_PMS2_ATTR; /*!< MSPI flash PMS section 2 attribute register */ - __IOM uint32_t SPI_FMEM_PMS1_ADDR; /*!< SPI1 flash PMS section 1 start address register */ - __IOM uint32_t SPI_FMEM_PMS0_SIZE; /*!< SPI1 flash PMS section 0 start address register */ - }; - __IM uint32_t RESERVED9[3]; - - union { - __IOM uint32_t SPI_FMEM_PMS3_ATTR; /*!< MSPI flash PMS section 3 attribute register */ - __IOM uint32_t SPI_FMEM_PMS2_ADDR; /*!< SPI1 flash PMS section 2 start address register */ - __IOM uint32_t SPI_FMEM_PMS1_SIZE; /*!< SPI1 flash PMS section 1 start address register */ - __IOM uint32_t SPI_SMEM_PMS0_ATTR; /*!< SPI1 flash PMS section 0 start address register */ - }; - __IM uint32_t RESERVED10[3]; - - union { - __IOM uint32_t SPI_FMEM_PMS3_ADDR; /*!< SPI1 flash PMS section 3 start address register */ - __IOM uint32_t SPI_FMEM_PMS2_SIZE; /*!< SPI1 flash PMS section 2 start address register */ - __IOM uint32_t SPI_SMEM_PMS1_ATTR; /*!< SPI1 flash PMS section 1 start address register */ - __IOM uint32_t SPI_SMEM_PMS0_ADDR; /*!< SPI1 external RAM PMS section 0 start address register */ - }; - __IM uint32_t RESERVED11[3]; - - union { - __IOM uint32_t SPI_FMEM_PMS3_SIZE; /*!< SPI1 flash PMS section 3 start address register */ - __IOM uint32_t SPI_SMEM_PMS2_ATTR; /*!< SPI1 flash PMS section 2 start address register */ - __IOM uint32_t SPI_SMEM_PMS1_ADDR; /*!< SPI1 external RAM PMS section 1 start address register */ - __IOM uint32_t SPI_SMEM_PMS0_SIZE; /*!< SPI1 external RAM PMS section 0 start address register */ - }; - __IM uint32_t RESERVED12[3]; - - union { - __IOM uint32_t SPI_SMEM_PMS3_ATTR; /*!< SPI1 flash PMS section 3 start address register */ - __IOM uint32_t SPI_SMEM_PMS2_ADDR; /*!< SPI1 external RAM PMS section 2 start address register */ - __IOM uint32_t SPI_SMEM_PMS1_SIZE; /*!< SPI1 external RAM PMS section 1 start address register */ - }; - - union { - __IOM uint32_t reg; /*!< SPI1 access reject register */ - - struct { - __IM uint32_t SPI_MEM_REJECT_ADDR : 27; /*!< This bits show the first SPI1 access error address. It is cleared - by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. */ - __IOM uint32_t SPI_MEM_PM_EN : 1; /*!< Set this bit to enable SPI0/1 transfer permission control function. */ - __IM uint32_t SPI_MEM_PMS_LD : 1; /*!< 1: SPI1 write access error. 0: No write access error. It is - cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. */ - __IM uint32_t SPI_MEM_PMS_ST : 1; /*!< 1: SPI1 read access error. 0: No read access error. It is cleared - by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. */ - __IM uint32_t SPI_MEM_PMS_MULTI_HIT : 1; /*!< 1: SPI1 access is rejected because of address miss. 0: No address - miss error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR - bit is set. */ - __IM uint32_t SPI_MEM_PMS_IVD : 1; /*!< 1: SPI1 access is rejected because of address multi-hit. 0: - No address multi-hit error. It is cleared by when SPI_MEM_PMS_REJECT_INT_ - LR bit is set. */ - } bit; - } SPI_MEM_PMS_REJECT; - - union { - __IOM uint32_t reg; /*!< MSPI ECC control register */ - - struct { - uint32_t : 5; - __IM uint32_t SPI_MEM_ECC_ERR_CNT : 6; /*!< This bits show the error times of MSPI ECC read. It is cleared - by when SPI_MEM_ECC_ERR_INT_CLR bit is set. */ - __IOM uint32_t SPI_FMEM_ECC_ERR_INT_NUM : 6;/*!< Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT - interrupt. */ - __IOM uint32_t SPI_FMEM_ECC_ERR_INT_EN : 1;/*!< Set this bit to calculate the error times of MSPI ECC read when - accesses to flash. */ - __IOM uint32_t SPI_FMEM_PAGE_SIZE : 2; /*!< Set the page size of the flash accessed by MSPI. 0: 256 bytes. - 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes. */ - __IOM uint32_t SPI_FMEM_ECC_ADDR_EN : 1; /*!< Set this bit to enable MSPI ECC address conversion, no matter - MSPI accesses to the ECC region or non-ECC region of flash. - If there is no ECC region in flash, this bit should be - 0. Otherwise, this bit should be 1. */ - __IOM uint32_t SPI_MEM_USR_ECC_ADDR_EN : 1;/*!< Set this bit to enable ECC address convert in SPI0/1 USR_CMD - transfer. */ - uint32_t : 2; - __IOM uint32_t SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN : 1;/*!< 1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR - is updated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS - and SPI_MEM_ECC_ERR_ADDR record the first ECC error information. */ - __IM uint32_t SPI_MEM_ECC_ERR_BITS : 7; /*!< Records the first ECC error bit number in the 16 bytes(From - 0~127, corresponding to byte 0 bit 0 to byte 15 bit 7) */ - } bit; - } SPI_MEM_ECC_CTRL; - - union { - __IOM uint32_t reg; /*!< MSPI ECC error address register */ - - struct { - __IM uint32_t SPI_MEM_ECC_ERR_ADDR : 27; /*!< This bits show the first MSPI ECC error address. It is cleared - by when SPI_MEM_ECC_ERR_INT_CLR bit is set. */ - uint32_t : 5; - } bit; - } SPI_MEM_ECC_ERR_ADDR; - - union { - __IOM uint32_t SPI_SMEM_PMS3_ADDR; /*!< SPI1 external RAM PMS section 3 start address register */ - __IOM uint32_t SPI_SMEM_PMS2_SIZE; /*!< SPI1 external RAM PMS section 2 start address register */ - - union { - __IOM uint32_t reg; /*!< SPI0 AXI request error address. */ - - struct { - __IM uint32_t SPI_MEM_AXI_ERR_ADDR : 27;/*!< This bits show the first AXI write/read invalid error or AXI - write flash error address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_IN - _CLR, SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR - bit is set. */ - uint32_t : 5; - } bit; - } SPI_MEM_AXI_ERR_ADDR; - }; - - union { - __IOM uint32_t reg; /*!< MSPI ECC control register */ - - struct { - uint32_t : 17; - __IOM uint32_t SPI_SMEM_ECC_ERR_INT_EN : 1;/*!< Set this bit to calculate the error times of MSPI ECC read when - accesses to external RAM. */ - __IOM uint32_t SPI_SMEM_PAGE_SIZE : 2; /*!< Set the page size of the external RAM accessed by MSPI. 0: 256 - bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes. */ - __IOM uint32_t SPI_SMEM_ECC_ADDR_EN : 1; /*!< Set this bit to enable MSPI ECC address conversion, no matter - MSPI accesses to the ECC region or non-ECC region of external - RAM. If there is no ECC region in external RAM, this bit - should be 0. Otherwise, this bit should be 1. */ - uint32_t : 11; - } bit; - } SPI_SMEM_ECC_CTRL; - - union { - __IOM uint32_t reg; /*!< SPI0 AXI address control register */ - - struct { - uint32_t : 26; - __IM uint32_t SPI_MEM_ALL_FIFO_EMPTY : 1;/*!< The empty status of all AFIFO and SYNC_FIFO in MSPI module. - 1: All AXI transfers and SPI0 transfers are done. 0: Others. */ - __IM uint32_t SPI_RDATA_AFIFO_REMPTY : 1;/*!< 1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is - pending. */ - __IM uint32_t SPI_RADDR_AFIFO_REMPTY : 1;/*!< 1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer - is pending. */ - __IM uint32_t SPI_WDATA_AFIFO_REMPTY : 1;/*!< 1: WDATA_AFIFO is empty. 0: At least one AXI write transfer - is pending. */ - __IM uint32_t SPI_WBLEN_AFIFO_REMPTY : 1;/*!< 1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer - is pending. */ - __IM uint32_t SPI_ALL_AXI_TRANS_AFIFO_EMPTY : 1;/*!< This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, - AXI_RADDR_CTL_AFIFO and RDATA_AFIFO are empty and spi0_mst_st - is IDLE. */ - } bit; - } SPI_SMEM_AXI_ADDR_CTRL; - - union { - __IOM uint32_t reg; /*!< SPI0 AXI error response enable register */ - - struct { - __IOM uint32_t SPI_MEM_AW_RESP_EN_MMU_VLD : 1;/*!< Set this bit to enable AXI response function for mmu valid err - in axi write trans. */ - __IOM uint32_t SPI_MEM_AW_RESP_EN_MMU_GID : 1;/*!< Set this bit to enable AXI response function for mmu gid err - in axi write trans. */ - __IOM uint32_t SPI_MEM_AW_RESP_EN_AXI_SIZE : 1;/*!< Set this bit to enable AXI response function for axi size err - in axi write trans. */ - __IOM uint32_t SPI_MEM_AW_RESP_EN_AXI_FLASH : 1;/*!< Set this bit to enable AXI response function for axi flash err - in axi write trans. */ - __IOM uint32_t SPI_MEM_AW_RESP_EN_MMU_ECC : 1;/*!< Set this bit to enable AXI response function for mmu ecc err - in axi write trans. */ - __IOM uint32_t SPI_MEM_AW_RESP_EN_MMU_SENS : 1;/*!< Set this bit to enable AXI response function for mmu sens in - err axi write trans. */ - __IOM uint32_t SPI_MEM_AW_RESP_EN_AXI_WSTRB : 1;/*!< Set this bit to enable AXI response function for axi wstrb err - in axi write trans. */ - __IOM uint32_t SPI_MEM_AR_RESP_EN_MMU_VLD : 1;/*!< Set this bit to enable AXI response function for mmu valid err - in axi read trans. */ - __IOM uint32_t SPI_MEM_AR_RESP_EN_MMU_GID : 1;/*!< Set this bit to enable AXI response function for mmu gid err - in axi read trans. */ - __IOM uint32_t SPI_MEM_AR_RESP_EN_MMU_ECC : 1;/*!< Set this bit to enable AXI response function for mmu ecc err - in axi read trans. */ - __IOM uint32_t SPI_MEM_AR_RESP_EN_MMU_SENS : 1;/*!< Set this bit to enable AXI response function for mmu sensitive - err in axi read trans. */ - __IOM uint32_t SPI_MEM_AR_RESP_EN_AXI_SIZE : 1;/*!< Set this bit to enable AXI response function for axi size err - in axi read trans. */ - uint32_t : 20; - } bit; - } SPI_MEM_AXI_ERR_RESP_EN; - - union { - __IOM uint32_t SPI_SMEM_PMS3_SIZE; /*!< SPI1 external RAM PMS section 3 start address register */ - - union { - __IOM uint32_t reg; /*!< SPI0 flash timing calibration register */ - - struct { - __IOM uint32_t SPI_MEM_TIMING_CLK_ENA : 1;/*!< The bit is used to enable timing adjust clock for all reading - operations. */ - __IOM uint32_t SPI_MEM_TIMING_CALI : 1; /*!< The bit is used to enable timing auto-calibration for all reading - operations. */ - __IOM uint32_t SPI_MEM_EXTRA_DUMMY_CYCLELEN : 3;/*!< add extra dummy spi clock cycle length for spi clock calibration. */ - __IOM uint32_t SPI_MEM_DLL_TIMING_CALI : 1;/*!< Set this bit to enable DLL for timing calibration in DDR mode - when accessed to flash. */ - __OM uint32_t UPDATE : 1; /*!< Set this bit to update delay mode, delay num and extra dummy - in MSPI. */ - uint32_t : 25; - } bit; - } SPI_MEM_TIMING_CALI; - }; - - union { - __IOM uint32_t reg; /*!< MSPI flash input timing delay mode control register */ - - struct { - __IOM uint32_t SPI_MEM_DIN0_MODE : 3; /*!< the input signals are delayed by system clock cycles, 0: input - without delayed, 1: input with the posedge of clk_apb,2 - input with the negedge of clk_apb, 3: input with the posedge - of clk_160, 4 input with the negedge of clk_160, 5: input - with the spi_clk high edge, 6: input with the spi_clk low - edge */ - __IOM uint32_t SPI_MEM_DIN1_MODE : 3; /*!< the input signals are delayed by system clock cycles, 0: input - without delayed, 1: input with the posedge of clk_apb,2 - input with the negedge of clk_apb, 3: input with the posedge - of clk_160, 4 input with the negedge of clk_160, 5: input - with the spi_clk high edge, 6: input with the spi_clk low - edge */ - __IOM uint32_t SPI_MEM_DIN2_MODE : 3; /*!< the input signals are delayed by system clock cycles, 0: input - without delayed, 1: input with the posedge of clk_apb,2 - input with the negedge of clk_apb, 3: input with the posedge - of clk_160, 4 input with the negedge of clk_160, 5: input - with the spi_clk high edge, 6: input with the spi_clk low - edge */ - __IOM uint32_t SPI_MEM_DIN3_MODE : 3; /*!< the input signals are delayed by system clock cycles, 0: input - without delayed, 1: input with the posedge of clk_apb,2 - input with the negedge of clk_apb, 3: input with the posedge - of clk_160, 4 input with the negedge of clk_160, 5: input - with the spi_clk high edge, 6: input with the spi_clk low - edge */ - __IOM uint32_t SPI_MEM_DIN4_MODE : 3; /*!< the input signals are delayed by system clock cycles, 0: input - without delayed, 1: input with the posedge of clk_apb,2 - input with the negedge of clk_apb, 3: input with the spi_clk */ - __IOM uint32_t SPI_MEM_DIN5_MODE : 3; /*!< the input signals are delayed by system clock cycles, 0: input - without delayed, 1: input with the posedge of clk_apb,2 - input with the negedge of clk_apb, 3: input with the spi_clk */ - __IOM uint32_t SPI_MEM_DIN6_MODE : 3; /*!< the input signals are delayed by system clock cycles, 0: input - without delayed, 1: input with the posedge of clk_apb,2 - input with the negedge of clk_apb, 3: input with the spi_clk */ - __IOM uint32_t SPI_MEM_DIN7_MODE : 3; /*!< the input signals are delayed by system clock cycles, 0: input - without delayed, 1: input with the posedge of clk_apb,2 - input with the negedge of clk_apb, 3: input with the spi_clk */ - __IOM uint32_t SPI_MEM_DINS_MODE : 3; /*!< the input signals are delayed by system clock cycles, 0: input - without delayed, 1: input with the posedge of clk_apb,2 - input with the negedge of clk_apb, 3: input with the spi_clk */ - uint32_t : 5; - } bit; - } SPI_MEM_DIN_MODE; - - union { - __IOM uint32_t reg; /*!< MSPI flash input timing delay number control register */ - - struct { - __IOM uint32_t SPI_MEM_DIN0_NUM : 2; /*!< the input signals are delayed by system clock cycles, 0: delayed - by 1 cycle, 1: delayed by 2 cycles,... */ - __IOM uint32_t SPI_MEM_DIN1_NUM : 2; /*!< the input signals are delayed by system clock cycles, 0: delayed - by 1 cycle, 1: delayed by 2 cycles,... */ - __IOM uint32_t SPI_MEM_DIN2_NUM : 2; /*!< the input signals are delayed by system clock cycles, 0: delayed - by 1 cycle, 1: delayed by 2 cycles,... */ - __IOM uint32_t SPI_MEM_DIN3_NUM : 2; /*!< the input signals are delayed by system clock cycles, 0: delayed - by 1 cycle, 1: delayed by 2 cycles,... */ - __IOM uint32_t SPI_MEM_DIN4_NUM : 2; /*!< the input signals are delayed by system clock cycles, 0: delayed - by 1 cycle, 1: delayed by 2 cycles,... */ - __IOM uint32_t SPI_MEM_DIN5_NUM : 2; /*!< the input signals are delayed by system clock cycles, 0: delayed - by 1 cycle, 1: delayed by 2 cycles,... */ - __IOM uint32_t SPI_MEM_DIN6_NUM : 2; /*!< the input signals are delayed by system clock cycles, 0: delayed - by 1 cycle, 1: delayed by 2 cycles,... */ - __IOM uint32_t SPI_MEM_DIN7_NUM : 2; /*!< the input signals are delayed by system clock cycles, 0: delayed - by 1 cycle, 1: delayed by 2 cycles,... */ - __IOM uint32_t SPI_MEM_DINS_NUM : 2; /*!< the input signals are delayed by system clock cycles, 0: delayed - by 1 cycle, 1: delayed by 2 cycles,... */ - uint32_t : 14; - } bit; - } SPI_MEM_DIN_NUM; - - union { - __IOM uint32_t reg; /*!< MSPI flash output timing adjustment control register */ - - struct { - __IOM uint32_t SPI_MEM_DOUT0_MODE : 1; /*!< the output signals are delayed by system clock cycles, 0: output - without delayed, 1: output with the posedge of clk_apb,2 - output with the negedge of clk_apb, 3: output with the - posedge of clk_160,4 output with the negedge of clk_160,5: - output with the spi_clk high edge ,6: output with the spi_clk - low edge */ - __IOM uint32_t SPI_MEM_DOUT1_MODE : 1; /*!< the output signals are delayed by system clock cycles, 0: output - without delayed, 1: output with the posedge of clk_apb,2 - output with the negedge of clk_apb, 3: output with the - posedge of clk_160,4 output with the negedge of clk_160,5: - output with the spi_clk high edge ,6: output with the spi_clk - low edge */ - __IOM uint32_t SPI_MEM_DOUT2_MODE : 1; /*!< the output signals are delayed by system clock cycles, 0: output - without delayed, 1: output with the posedge of clk_apb,2 - output with the negedge of clk_apb, 3: output with the - posedge of clk_160,4 output with the negedge of clk_160,5: - output with the spi_clk high edge ,6: output with the spi_clk - low edge */ - __IOM uint32_t SPI_MEM_DOUT3_MODE : 1; /*!< the output signals are delayed by system clock cycles, 0: output - without delayed, 1: output with the posedge of clk_apb,2 - output with the negedge of clk_apb, 3: output with the - posedge of clk_160,4 output with the negedge of clk_160,5: - output with the spi_clk high edge ,6: output with the spi_clk - low edge */ - __IOM uint32_t SPI_MEM_DOUT4_MODE : 1; /*!< the output signals are delayed by system clock cycles, 0: output - without delayed, 1: output with the posedge of clk_apb,2 - output with the negedge of clk_apb, 3: output with the - spi_clk */ - __IOM uint32_t SPI_MEM_DOUT5_MODE : 1; /*!< the output signals are delayed by system clock cycles, 0: output - without delayed, 1: output with the posedge of clk_apb,2 - output with the negedge of clk_apb, 3: output with the - spi_clk */ - __IOM uint32_t SPI_MEM_DOUT6_MODE : 1; /*!< the output signals are delayed by system clock cycles, 0: output - without delayed, 1: output with the posedge of clk_apb,2 - output with the negedge of clk_apb, 3: output with the - spi_clk */ - __IOM uint32_t SPI_MEM_DOUT7_MODE : 1; /*!< the output signals are delayed by system clock cycles, 0: output - without delayed, 1: output with the posedge of clk_apb,2 - output with the negedge of clk_apb, 3: output with the - spi_clk */ - __IOM uint32_t SPI_MEM_DOUTS_MODE : 1; /*!< the output signals are delayed by system clock cycles, 0: output - without delayed, 1: output with the posedge of clk_apb,2 - output with the negedge of clk_apb, 3: output with the - spi_clk */ - uint32_t : 23; - } bit; - } SPI_MEM_DOUT_MODE; - - union { - __IOM uint32_t reg; /*!< MSPI external RAM timing calibration register */ - - struct { - __IOM uint32_t SPI_SMEM_TIMING_CLK_ENA : 1;/*!< For sram, the bit is used to enable timing adjust clock for - all reading operations. */ - __IOM uint32_t SPI_SMEM_TIMING_CALI : 1; /*!< For sram, the bit is used to enable timing auto-calibration - for all reading operations. */ - __IOM uint32_t SPI_SMEM_EXTRA_DUMMY_CYCLELEN : 3;/*!< For sram, add extra dummy spi clock cycle length for spi clock - calibration. */ - __IOM uint32_t SPI_SMEM_DLL_TIMING_CALI : 1;/*!< Set this bit to enable DLL for timing calibration in DDR mode - when accessed to EXT_RAM. */ - uint32_t : 26; - } bit; - } SPI_SMEM_TIMING_CALI; - - union { - __IOM uint32_t reg; /*!< MSPI external RAM input timing delay mode control register */ - - struct { - __IOM uint32_t SPI_SMEM_DIN0_MODE : 3; /*!< the input signals are delayed by system clock cycles, 0: input - without delayed, 1: input with the posedge of clk_apb,2 - input with the negedge of clk_apb, 3: input with the posedge - of clk_160, 4 input with the negedge of clk_160, 5: input - with the spi_clk high edge, 6: input with the spi_clk low - edge */ - __IOM uint32_t SPI_SMEM_DIN1_MODE : 3; /*!< the input signals are delayed by system clock cycles, 0: input - without delayed, 1: input with the posedge of clk_apb,2 - input with the negedge of clk_apb, 3: input with the posedge - of clk_160, 4 input with the negedge of clk_160, 5: input - with the spi_clk high edge, 6: input with the spi_clk low - edge */ - __IOM uint32_t SPI_SMEM_DIN2_MODE : 3; /*!< the input signals are delayed by system clock cycles, 0: input - without delayed, 1: input with the posedge of clk_apb,2 - input with the negedge of clk_apb, 3: input with the posedge - of clk_160, 4 input with the negedge of clk_160, 5: input - with the spi_clk high edge, 6: input with the spi_clk low - edge */ - __IOM uint32_t SPI_SMEM_DIN3_MODE : 3; /*!< the input signals are delayed by system clock cycles, 0: input - without delayed, 1: input with the posedge of clk_apb,2 - input with the negedge of clk_apb, 3: input with the posedge - of clk_160, 4 input with the negedge of clk_160, 5: input - with the spi_clk high edge, 6: input with the spi_clk low - edge */ - __IOM uint32_t SPI_SMEM_DIN4_MODE : 3; /*!< the input signals are delayed by system clock cycles, 0: input - without delayed, 1: input with the posedge of clk_apb,2 - input with the negedge of clk_apb, 3: input with the posedge - of clk_160, 4 input with the negedge of clk_160, 5: input - with the spi_clk high edge, 6: input with the spi_clk low - edge */ - __IOM uint32_t SPI_SMEM_DIN5_MODE : 3; /*!< the input signals are delayed by system clock cycles, 0: input - without delayed, 1: input with the posedge of clk_apb,2 - input with the negedge of clk_apb, 3: input with the posedge - of clk_160, 4 input with the negedge of clk_160, 5: input - with the spi_clk high edge, 6: input with the spi_clk low - edge */ - __IOM uint32_t SPI_SMEM_DIN6_MODE : 3; /*!< the input signals are delayed by system clock cycles, 0: input - without delayed, 1: input with the posedge of clk_apb,2 - input with the negedge of clk_apb, 3: input with the posedge - of clk_160, 4 input with the negedge of clk_160, 5: input - with the spi_clk high edge, 6: input with the spi_clk low - edge */ - __IOM uint32_t SPI_SMEM_DIN7_MODE : 3; /*!< the input signals are delayed by system clock cycles, 0: input - without delayed, 1: input with the posedge of clk_apb,2 - input with the negedge of clk_apb, 3: input with the posedge - of clk_160, 4 input with the negedge of clk_160, 5: input - with the spi_clk high edge, 6: input with the spi_clk low - edge */ - __IOM uint32_t SPI_SMEM_DINS_MODE : 3; /*!< the input signals are delayed by system clock cycles, 0: input - without delayed, 1: input with the posedge of clk_apb,2 - input with the negedge of clk_apb, 3: input with the posedge - of clk_160, 4 input with the negedge of clk_160, 5: input - with the spi_clk high edge, 6: input with the spi_clk low - edge */ - uint32_t : 5; - } bit; - } SPI_SMEM_DIN_MODE; - - union { - __IOM uint32_t reg; /*!< MSPI external RAM input timing delay number control register */ - - struct { - __IOM uint32_t SPI_SMEM_DIN0_NUM : 2; /*!< the input signals are delayed by system clock cycles, 0: delayed - by 1 cycle, 1: delayed by 2 cycles,... */ - __IOM uint32_t SPI_SMEM_DIN1_NUM : 2; /*!< the input signals are delayed by system clock cycles, 0: delayed - by 1 cycle, 1: delayed by 2 cycles,... */ - __IOM uint32_t SPI_SMEM_DIN2_NUM : 2; /*!< the input signals are delayed by system clock cycles, 0: delayed - by 1 cycle, 1: delayed by 2 cycles,... */ - __IOM uint32_t SPI_SMEM_DIN3_NUM : 2; /*!< the input signals are delayed by system clock cycles, 0: delayed - by 1 cycle, 1: delayed by 2 cycles,... */ - __IOM uint32_t SPI_SMEM_DIN4_NUM : 2; /*!< the input signals are delayed by system clock cycles, 0: delayed - by 1 cycle, 1: delayed by 2 cycles,... */ - __IOM uint32_t SPI_SMEM_DIN5_NUM : 2; /*!< the input signals are delayed by system clock cycles, 0: delayed - by 1 cycle, 1: delayed by 2 cycles,... */ - __IOM uint32_t SPI_SMEM_DIN6_NUM : 2; /*!< the input signals are delayed by system clock cycles, 0: delayed - by 1 cycle, 1: delayed by 2 cycles,... */ - __IOM uint32_t SPI_SMEM_DIN7_NUM : 2; /*!< the input signals are delayed by system clock cycles, 0: delayed - by 1 cycle, 1: delayed by 2 cycles,... */ - __IOM uint32_t SPI_SMEM_DINS_NUM : 2; /*!< the input signals are delayed by system clock cycles, 0: delayed - by 1 cycle, 1: delayed by 2 cycles,... */ - uint32_t : 14; - } bit; - } SPI_SMEM_DIN_NUM; - - union { - __IOM uint32_t reg; /*!< MSPI external RAM output timing adjustment control register */ - - struct { - __IOM uint32_t SPI_SMEM_DOUT0_MODE : 1; /*!< the output signals are delayed by system clock cycles, 0: output - without delayed, 1: output with the posedge of clk_apb,2 - output with the negedge of clk_apb, 3: output with the - posedge of clk_160,4 output with the negedge of clk_160,5: - output with the spi_clk high edge ,6: output with the spi_clk - low edge */ - __IOM uint32_t SPI_SMEM_DOUT1_MODE : 1; /*!< the output signals are delayed by system clock cycles, 0: output - without delayed, 1: output with the posedge of clk_apb,2 - output with the negedge of clk_apb, 3: output with the - posedge of clk_160,4 output with the negedge of clk_160,5: - output with the spi_clk high edge ,6: output with the spi_clk - low edge */ - __IOM uint32_t SPI_SMEM_DOUT2_MODE : 1; /*!< the output signals are delayed by system clock cycles, 0: output - without delayed, 1: output with the posedge of clk_apb,2 - output with the negedge of clk_apb, 3: output with the - posedge of clk_160,4 output with the negedge of clk_160,5: - output with the spi_clk high edge ,6: output with the spi_clk - low edge */ - __IOM uint32_t SPI_SMEM_DOUT3_MODE : 1; /*!< the output signals are delayed by system clock cycles, 0: output - without delayed, 1: output with the posedge of clk_apb,2 - output with the negedge of clk_apb, 3: output with the - posedge of clk_160,4 output with the negedge of clk_160,5: - output with the spi_clk high edge ,6: output with the spi_clk - low edge */ - __IOM uint32_t SPI_SMEM_DOUT4_MODE : 1; /*!< the output signals are delayed by system clock cycles, 0: output - without delayed, 1: output with the posedge of clk_apb,2 - output with the negedge of clk_apb, 3: output with the - posedge of clk_160,4 output with the negedge of clk_160,5: - output with the spi_clk high edge ,6: output with the spi_clk - low edge */ - __IOM uint32_t SPI_SMEM_DOUT5_MODE : 1; /*!< the output signals are delayed by system clock cycles, 0: output - without delayed, 1: output with the posedge of clk_apb,2 - output with the negedge of clk_apb, 3: output with the - posedge of clk_160,4 output with the negedge of clk_160,5: - output with the spi_clk high edge ,6: output with the spi_clk - low edge */ - __IOM uint32_t SPI_SMEM_DOUT6_MODE : 1; /*!< the output signals are delayed by system clock cycles, 0: output - without delayed, 1: output with the posedge of clk_apb,2 - output with the negedge of clk_apb, 3: output with the - posedge of clk_160,4 output with the negedge of clk_160,5: - output with the spi_clk high edge ,6: output with the spi_clk - low edge */ - __IOM uint32_t SPI_SMEM_DOUT7_MODE : 1; /*!< the output signals are delayed by system clock cycles, 0: output - without delayed, 1: output with the posedge of clk_apb,2 - output with the negedge of clk_apb, 3: output with the - posedge of clk_160,4 output with the negedge of clk_160,5: - output with the spi_clk high edge ,6: output with the spi_clk - low edge */ - __IOM uint32_t SPI_SMEM_DOUTS_MODE : 1; /*!< the output signals are delayed by system clock cycles, 0: output - without delayed, 1: output with the posedge of clk_apb,2 - output with the negedge of clk_apb, 3: output with the - posedge of clk_160,4 output with the negedge of clk_160,5: - output with the spi_clk high edge ,6: output with the spi_clk - low edge */ - uint32_t : 23; - } bit; - } SPI_SMEM_DOUT_MODE; - - union { - __IOM uint32_t reg; /*!< MSPI external RAM ECC and SPI CS timing control register */ - - struct { - __IOM uint32_t SPI_SMEM_CS_SETUP : 1; /*!< For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. - 1: enable 0: disable. */ - __IOM uint32_t SPI_SMEM_CS_HOLD : 1; /*!< For SPI0 and SPI1, spi cs keep low when spi is in done phase. - 1: enable 0: disable. */ - __IOM uint32_t SPI_SMEM_CS_SETUP_TIME : 5;/*!< For spi0, (cycles-1) of prepare phase by spi clock this bits - are combined with spi_mem_cs_setup bit. */ - __IOM uint32_t SPI_SMEM_CS_HOLD_TIME : 5; /*!< For SPI0 and SPI1, spi cs signal is delayed to inactive by spi - clock this bits are combined with spi_mem_cs_hold bit. */ - __IOM uint32_t SPI_SMEM_ECC_CS_HOLD_TIME : 3;/*!< SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 - and SPI1 CS hold cycles in ECC mode when accessed external - RAM. */ - __IOM uint32_t SPI_SMEM_ECC_SKIP_PAGE_CORNER : 1;/*!< 1: SPI0 skips page corner when accesses external RAM. 0: Not - skip page corner when accesses external RAM. */ - __IOM uint32_t SPI_SMEM_ECC_16TO18_BYTE_EN : 1;/*!< Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with - 2 ECC bytes mode when accesses external RAM. */ - uint32_t : 8; - __IOM uint32_t SPI_SMEM_CS_HOLD_DELAY : 6;/*!< These bits are used to set the minimum CS high time tSHSL between - SPI burst transfer when accesses to external RAM. tSHSL - is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles. */ - __IOM uint32_t SPI_SMEM_SPLIT_TRANS_EN : 1;/*!< Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer - into two SPI transfers when one transfer will cross flash/EXT_RAM - page corner, valid no matter whether there is an ECC region - or not. */ - } bit; - } SPI_SMEM_AC; - - union { - __IOM uint32_t reg; /*!< MSPI 16x external RAM input timing delay mode control register */ - - struct { - __IOM uint32_t SPI_SMEM_DIN08_MODE : 3; /*!< the input signals are delayed by system clock cycles, 0: input - without delayed, 1: input with the posedge of clk_apb,2 - input with the negedge of clk_apb, 3: input with the posedge - of clk_160, 4 input with the negedge of clk_160, 5: input - with the spi_clk high edge, 6: input with the spi_clk low - edge */ - __IOM uint32_t SPI_SMEM_DIN09_MODE : 3; /*!< the input signals are delayed by system clock cycles, 0: input - without delayed, 1: input with the posedge of clk_apb,2 - input with the negedge of clk_apb, 3: input with the posedge - of clk_160, 4 input with the negedge of clk_160, 5: input - with the spi_clk high edge, 6: input with the spi_clk low - edge */ - __IOM uint32_t SPI_SMEM_DIN10_MODE : 3; /*!< the input signals are delayed by system clock cycles, 0: input - without delayed, 1: input with the posedge of clk_apb,2 - input with the negedge of clk_apb, 3: input with the posedge - of clk_160, 4 input with the negedge of clk_160, 5: input - with the spi_clk high edge, 6: input with the spi_clk low - edge */ - __IOM uint32_t SPI_SMEM_DIN11_MODE : 3; /*!< the input signals are delayed by system clock cycles, 0: input - without delayed, 1: input with the posedge of clk_apb,2 - input with the negedge of clk_apb, 3: input with the posedge - of clk_160, 4 input with the negedge of clk_160, 5: input - with the spi_clk high edge, 6: input with the spi_clk low - edge */ - __IOM uint32_t SPI_SMEM_DIN12_MODE : 3; /*!< the input signals are delayed by system clock cycles, 0: input - without delayed, 1: input with the posedge of clk_apb,2 - input with the negedge of clk_apb, 3: input with the posedge - of clk_160, 4 input with the negedge of clk_160, 5: input - with the spi_clk high edge, 6: input with the spi_clk low - edge */ - __IOM uint32_t SPI_SMEM_DIN13_MODE : 3; /*!< the input signals are delayed by system clock cycles, 0: input - without delayed, 1: input with the posedge of clk_apb,2 - input with the negedge of clk_apb, 3: input with the posedge - of clk_160, 4 input with the negedge of clk_160, 5: input - with the spi_clk high edge, 6: input with the spi_clk low - edge */ - __IOM uint32_t SPI_SMEM_DIN14_MODE : 3; /*!< the input signals are delayed by system clock cycles, 0: input - without delayed, 1: input with the posedge of clk_apb,2 - input with the negedge of clk_apb, 3: input with the posedge - of clk_160, 4 input with the negedge of clk_160, 5: input - with the spi_clk high edge, 6: input with the spi_clk low - edge */ - __IOM uint32_t SPI_SMEM_DIN15_MODE : 3; /*!< the input signals are delayed by system clock cycles, 0: input - without delayed, 1: input with the posedge of clk_apb,2 - input with the negedge of clk_apb, 3: input with the posedge - of clk_160, 4 input with the negedge of clk_160, 5: input - with the spi_clk high edge, 6: input with the spi_clk low - edge */ - __IOM uint32_t SPI_SMEM_DINS_HEX_MODE : 3;/*!< the input signals are delayed by system clock cycles, 0: input - without delayed, 1: input with the posedge of clk_apb,2 - input with the negedge of clk_apb, 3: input with the posedge - of clk_160, 4 input with the negedge of clk_160, 5: input - with the spi_clk high edge, 6: input with the spi_clk low - edge */ - uint32_t : 5; - } bit; - } SPI_SMEM_DIN_HEX_MODE; - - union { - __IOM uint32_t reg; /*!< MSPI 16x external RAM input timing delay number control register */ - - struct { - __IOM uint32_t SPI_SMEM_DIN08_NUM : 2; /*!< the input signals are delayed by system clock cycles, 0: delayed - by 1 cycle, 1: delayed by 2 cycles,... */ - __IOM uint32_t SPI_SMEM_DIN09_NUM : 2; /*!< the input signals are delayed by system clock cycles, 0: delayed - by 1 cycle, 1: delayed by 2 cycles,... */ - __IOM uint32_t SPI_SMEM_DIN10_NUM : 2; /*!< the input signals are delayed by system clock cycles, 0: delayed - by 1 cycle, 1: delayed by 2 cycles,... */ - __IOM uint32_t SPI_SMEM_DIN11_NUM : 2; /*!< the input signals are delayed by system clock cycles, 0: delayed - by 1 cycle, 1: delayed by 2 cycles,... */ - __IOM uint32_t SPI_SMEM_DIN12_NUM : 2; /*!< the input signals are delayed by system clock cycles, 0: delayed - by 1 cycle, 1: delayed by 2 cycles,... */ - __IOM uint32_t SPI_SMEM_DIN13_NUM : 2; /*!< the input signals are delayed by system clock cycles, 0: delayed - by 1 cycle, 1: delayed by 2 cycles,... */ - __IOM uint32_t SPI_SMEM_DIN14_NUM : 2; /*!< the input signals are delayed by system clock cycles, 0: delayed - by 1 cycle, 1: delayed by 2 cycles,... */ - __IOM uint32_t SPI_SMEM_DIN15_NUM : 2; /*!< the input signals are delayed by system clock cycles, 0: delayed - by 1 cycle, 1: delayed by 2 cycles,... */ - __IOM uint32_t SPI_SMEM_DINS_HEX_NUM : 2; /*!< the input signals are delayed by system clock cycles, 0: delayed - by 1 cycle, 1: delayed by 2 cycles,... */ - uint32_t : 14; - } bit; - } SPI_SMEM_DIN_HEX_NUM; - - union { - __IOM uint32_t reg; /*!< MSPI 16x external RAM output timing adjustment control register */ - - struct { - __IOM uint32_t SPI_SMEM_DOUT08_MODE : 1; /*!< the output signals are delayed by system clock cycles, 0: output - without delayed, 1: output with the posedge of clk_apb,2 - output with the negedge of clk_apb, 3: output with the - posedge of clk_160,4 output with the negedge of clk_160,5: - output with the spi_clk high edge ,6: output with the spi_clk - low edge */ - __IOM uint32_t SPI_SMEM_DOUT09_MODE : 1; /*!< the output signals are delayed by system clock cycles, 0: output - without delayed, 1: output with the posedge of clk_apb,2 - output with the negedge of clk_apb, 3: output with the - posedge of clk_160,4 output with the negedge of clk_160,5: - output with the spi_clk high edge ,6: output with the spi_clk - low edge */ - __IOM uint32_t SPI_SMEM_DOUT10_MODE : 1; /*!< the output signals are delayed by system clock cycles, 0: output - without delayed, 1: output with the posedge of clk_apb,2 - output with the negedge of clk_apb, 3: output with the - posedge of clk_160,4 output with the negedge of clk_160,5: - output with the spi_clk high edge ,6: output with the spi_clk - low edge */ - __IOM uint32_t SPI_SMEM_DOUT11_MODE : 1; /*!< the output signals are delayed by system clock cycles, 0: output - without delayed, 1: output with the posedge of clk_apb,2 - output with the negedge of clk_apb, 3: output with the - posedge of clk_160,4 output with the negedge of clk_160,5: - output with the spi_clk high edge ,6: output with the spi_clk - low edge */ - __IOM uint32_t SPI_SMEM_DOUT12_MODE : 1; /*!< the output signals are delayed by system clock cycles, 0: output - without delayed, 1: output with the posedge of clk_apb,2 - output with the negedge of clk_apb, 3: output with the - posedge of clk_160,4 output with the negedge of clk_160,5: - output with the spi_clk high edge ,6: output with the spi_clk - low edge */ - __IOM uint32_t SPI_SMEM_DOUT13_MODE : 1; /*!< the output signals are delayed by system clock cycles, 0: output - without delayed, 1: output with the posedge of clk_apb,2 - output with the negedge of clk_apb, 3: output with the - posedge of clk_160,4 output with the negedge of clk_160,5: - output with the spi_clk high edge ,6: output with the spi_clk - low edge */ - __IOM uint32_t SPI_SMEM_DOUT14_MODE : 1; /*!< the output signals are delayed by system clock cycles, 0: output - without delayed, 1: output with the posedge of clk_apb,2 - output with the negedge of clk_apb, 3: output with the - posedge of clk_160,4 output with the negedge of clk_160,5: - output with the spi_clk high edge ,6: output with the spi_clk - low edge */ - __IOM uint32_t SPI_SMEM_DOUT15_MODE : 1; /*!< the output signals are delayed by system clock cycles, 0: output - without delayed, 1: output with the posedge of clk_apb,2 - output with the negedge of clk_apb, 3: output with the - posedge of clk_160,4 output with the negedge of clk_160,5: - output with the spi_clk high edge ,6: output with the spi_clk - low edge */ - __IOM uint32_t SPI_SMEM_DOUTS_HEX_MODE : 1;/*!< the output signals are delayed by system clock cycles, 0: output - without delayed, 1: output with the posedge of clk_apb,2 - output with the negedge of clk_apb, 3: output with the - posedge of clk_160,4 output with the negedge of clk_160,5: - output with the spi_clk high edge ,6: output with the spi_clk - low edge */ - uint32_t : 23; - } bit; - } SPI_SMEM_DOUT_HEX_MODE; - __IM uint32_t RESERVED13[20]; - - union { - __IOM uint32_t reg; /*!< SPI0 clock gate register */ - - struct { - __IOM uint32_t SPI_CLK_EN : 1; /*!< Register clock gate enable signal. 1: Enable. 0: Disable. */ - uint32_t : 31; - } bit; - } SPI_MEM_CLOCK_GATE; - __IM uint32_t RESERVED14[63]; - - union { - __IOM uint32_t reg; /*!< The base address of the memory that stores plaintext in Manual - Encryption */ - - struct { - __IOM uint32_t SPI_XTS_PLAIN : 32; /*!< This field is only used to generate include file in c case. - This field is useless. Please do not use this field. */ - } bit; - } SPI_MEM_XTS_PLAIN_BASE; - __IM uint32_t RESERVED15[15]; - - union { - __IOM uint32_t reg; /*!< Manual Encryption Line-Size register */ - - struct { - __IOM uint32_t SPI_XTS_LINESIZE : 2; /*!< This bits stores the line-size parameter which will be used - in manual encryption calculation. It decides how many bytes - will be encrypted one time. 0: 16-bytes, 1: 32-bytes, 2: - 64-bytes, 3:reserved. */ - uint32_t : 30; - } bit; - } SPI_MEM_XTS_LINESIZE; - - union { - __IOM uint32_t reg; /*!< Manual Encryption destination register */ - - struct { - __IOM uint32_t SPI_XTS_DESTINATION : 1; /*!< This bit stores the destination parameter which will be used - in manual encryption calculation. 0: flash(default), 1: - psram(reserved). Only default value can be used. */ - uint32_t : 31; - } bit; - } SPI_MEM_XTS_DESTINATION; - - union { - __IOM uint32_t reg; /*!< Manual Encryption physical address register */ - - struct { - __IOM uint32_t SPI_XTS_PHYSICAL_ADDRESS : 26;/*!< This bits stores the physical-address parameter which will be - used in manual encryption calculation. This value should - aligned with byte number decided by line-size parameter. */ - uint32_t : 6; - } bit; - } SPI_MEM_XTS_PHYSICAL_ADDRESS; - - union { - __IOM uint32_t reg; /*!< Manual Encryption physical address register */ - - struct { - __OM uint32_t SPI_XTS_TRIGGER : 1; /*!< Set this bit to trigger the process of manual encryption calculation. - This action should only be asserted when manual encryption - status is 0. After this action, manual encryption status - becomes 1. After calculation is done, manual encryption - status becomes 2. */ - uint32_t : 31; - } bit; - } SPI_MEM_XTS_TRIGGER; - - union { - __IOM uint32_t reg; /*!< Manual Encryption physical address register */ - - struct { - __OM uint32_t SPI_XTS_RELEASE : 1; /*!< Set this bit to release encrypted result to mspi. This action - should only be asserted when manual encryption status is - 2. After this action, manual encryption status will become - 3. */ - uint32_t : 31; - } bit; - } SPI_MEM_XTS_RELEASE; - - union { - __IOM uint32_t reg; /*!< Manual Encryption physical address register */ - - struct { - __OM uint32_t SPI_XTS_DESTROY : 1; /*!< Set this bit to destroy encrypted result. This action should - be asserted only when manual encryption status is 3. After - this action, manual encryption status will become 0. */ - uint32_t : 31; - } bit; - } SPI_MEM_XTS_DESTROY; - - union { - __IOM uint32_t reg; /*!< Manual Encryption physical address register */ - - struct { - __IM uint32_t SPI_XTS_STATE : 2; /*!< This bits stores the status of manual encryption. 0: idle, 1: - busy of encryption calculation, 2: encryption calculation - is done but the encrypted result is invisible to mspi, - 3: the encrypted result is visible to mspi. */ - uint32_t : 30; - } bit; - } SPI_MEM_XTS_STATE; - - union { - __IOM uint32_t reg; /*!< Manual Encryption version register */ - - struct { - __IOM uint32_t SPI_XTS_DATE : 30; /*!< This bits stores the last modified-time of manual encryption - feature. */ - uint32_t : 2; - } bit; - } SPI_MEM_XTS_DATE; - __IM uint32_t RESERVED16[7]; - - union { - __IOM uint32_t reg; /*!< MSPI-MMU item content register */ - - struct { - __IOM uint32_t SPI_MMU_ITEM_CONTENT : 32; /*!< MSPI-MMU item content */ - } bit; - } SPI_MEM_MMU_ITEM_CONTENT; - - union { - __IOM uint32_t reg; /*!< MSPI-MMU item index register */ - - struct { - __IOM uint32_t SPI_MMU_ITEM_INDEX : 32; /*!< MSPI-MMU item index */ - } bit; - } SPI_MEM_MMU_ITEM_INDEX; - - union { - __IOM uint32_t reg; /*!< MSPI MMU power control register */ - - struct { - __IOM uint32_t SPI_MMU_MEM_FORCE_ON : 1; /*!< Set this bit to enable mmu-memory clock force on */ - __IOM uint32_t SPI_MMU_MEM_FORCE_PD : 1; /*!< Set this bit to force mmu-memory powerdown */ - __IOM uint32_t SPI_MMU_MEM_FORCE_PU : 1; /*!< Set this bit to force mmu-memory powerup, in this case, the - power should also be controlled by rtc. */ - uint32_t : 13; - __IOM uint32_t SPI_MEM_AUX_CTRL : 14; /*!< MMU PSRAM aux control register */ - __IOM uint32_t SPI_MEM_RDN_ENA : 1; /*!< ECO register enable bit */ - __IM uint32_t SPI_MEM_RDN_RESULT : 1; /*!< MSPI module clock domain and AXI clock domain ECO register result - register */ - } bit; - } SPI_MEM_MMU_POWER_CTRL; - - union { - __IOM uint32_t reg; /*!< SPI memory cryption DPA register */ - - struct { - __IOM uint32_t SPI_CRYPT_SECURITY_LEVEL : 3;/*!< Set the security level of spi mem cryption. 0: Shut off cryption - DPA funtion. 1-7: The bigger the number is, the more secure - the cryption is. (Note that the performance of cryption - will decrease together with this number increasing) */ - __IOM uint32_t SPI_CRYPT_CALC_D_DPA_EN : 1;/*!< Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable - DPA in the calculation that using key 1 or key 2. 0: Enable - DPA only in the calculation that using key 1. */ - __IOM uint32_t SPI_CRYPT_DPA_SELECT_REGISTER : 1;/*!< 1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN - and SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits. */ - uint32_t : 27; - } bit; - } SPI_MEM_DPA_CTRL; - __IM uint32_t RESERVED17[25]; - - union { - __IOM uint32_t reg; /*!< MSPI ECO high register */ - - struct { - __IOM uint32_t SPI_MEM_REGISTERRND_ECO_HIGH : 32;/*!< ECO high register */ - } bit; - } SPI_MEM_REGISTERRND_ECO_HIGH; - - union { - __IOM uint32_t reg; /*!< MSPI ECO low register */ - - struct { - __IOM uint32_t SPI_MEM_REGISTERRND_ECO_LOW : 32;/*!< ECO low register */ - } bit; - } SPI_MEM_REGISTERRND_ECO_LOW; - __IM uint32_t RESERVED18; - - union { - __IOM uint32_t reg; /*!< SPI0 version control register */ - - struct { - __IOM uint32_t SPI_MEM_DATE : 28; /*!< SPI0 register version. */ - uint32_t : 4; - } bit; - } SPI_MEM_DATE; -} SPI0_Type; /*!< Size = 1024 (0x400) */ - - - -/* =========================================================================================================================== */ -/* ================ SPI1 ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief SPI (Serial Peripheral Interface) Controller 1 (SPI1) - */ - -typedef struct { /*!< SPI1 Structure */ - - union { - __IOM uint32_t reg; /*!< SPI1 memory command register */ - - struct { - __IM uint32_t SPI_MEM_MST_ST : 4; /*!< The current status of SPI1 master FSM. */ - __IM uint32_t SPI_MEM_SLV_ST : 4; /*!< The current status of SPI1 slave FSM: mspi_st. 0: idle state, - 1: preparation state, 2: send command state, 3: send address - state, 4: wait state, 5: read data state, 6:write data - state, 7: done state, 8: read data end state. */ - uint32_t : 9; - __IOM uint32_t SPI_MEM_FLASH_PE : 1; /*!< In user mode, it is set to indicate that program/erase operation - will be triggered. The bit is combined with spi_mem_usr - bit. The bit will be cleared once the operation done.1: - enable 0: disable. */ - __IOM uint32_t SPI_MEM_USR : 1; /*!< User define command enable. An operation will be triggered when - the bit is set. The bit will be cleared once the operation - done.1: enable 0: disable. */ - __IOM uint32_t SPI_MEM_FLASH_HPM : 1; /*!< Drive Flash into high performance mode. The bit will be cleared - once the operation done.1: enable 0: disable. */ - __IOM uint32_t SPI_MEM_FLASH_RES : 1; /*!< This bit combined with reg_resandres bit releases Flash from - the power-down state or high performance mode and obtains - the devices ID. The bit will be cleared once the operation - done.1: enable 0: disable. */ - __IOM uint32_t SPI_MEM_FLASH_DP : 1; /*!< Drive Flash into power down. An operation will be triggered - when the bit is set. The bit will be cleared once the operation - done.1: enable 0: disable. */ - __IOM uint32_t SPI_MEM_FLASH_CE : 1; /*!< Chip erase enable. Chip erase operation will be triggered when - the bit is set. The bit will be cleared once the operation - done.1: enable 0: disable. */ - __IOM uint32_t SPI_MEM_FLASH_BE : 1; /*!< Block erase enable(32KB) . Block erase operation will be triggered - when the bit is set. The bit will be cleared once the operation - done.1: enable 0: disable. */ - __IOM uint32_t SPI_MEM_FLASH_SE : 1; /*!< Sector erase enable(4KB). Sector erase operation will be triggered - when the bit is set. The bit will be cleared once the operation - done.1: enable 0: disable. */ - __IOM uint32_t SPI_MEM_FLASH_PP : 1; /*!< Page program enable(1 byte ~256 bytes data to be programmed). - Page program operation will be triggered when the bit is - set. The bit will be cleared once the operation done .1: - enable 0: disable. */ - __IOM uint32_t SPI_MEM_FLASH_WRSR : 1; /*!< Write status register enable. Write status operation will be - triggered when the bit is set. The bit will be cleared - once the operation done.1: enable 0: disable. */ - __IOM uint32_t SPI_MEM_FLASH_RDSR : 1; /*!< Read status register-1. Read status operation will be triggered - when the bit is set. The bit will be cleared once the operation - done.1: enable 0: disable. */ - __IOM uint32_t SPI_MEM_FLASH_RDID : 1; /*!< Read JEDEC ID . Read ID command will be sent when the bit is - set. The bit will be cleared once the operation done. 1: - enable 0: disable. */ - __IOM uint32_t SPI_MEM_FLASH_WRDI : 1; /*!< Write flash disable. Write disable command will be sent when - the bit is set. The bit will be cleared once the operation - done. 1: enable 0: disable. */ - __IOM uint32_t SPI_MEM_FLASH_WREN : 1; /*!< Write flash enable. Write enable command will be sent when the - bit is set. The bit will be cleared once the operation - done. 1: enable 0: disable. */ - __IOM uint32_t SPI_MEM_FLASH_READ : 1; /*!< Read flash enable. Read flash operation will be triggered when - the bit is set. The bit will be cleared once the operation - done. 1: enable 0: disable. */ - } bit; - } SPI_MEM_CMD; - - union { - __IOM uint32_t reg; /*!< SPI1 address register */ - - struct { - __IOM uint32_t SPI_MEM_USR_ADDR_VALUE : 32;/*!< In user mode, it is the memory address. other then the bit0-bit23 - is the memory address, the bit24-bit31 are the byte length - of a transfer. */ - } bit; - } SPI_MEM_ADDR; - - union { - __IOM uint32_t reg; /*!< SPI1 control register. */ - - struct { - uint32_t : 2; - __IOM uint32_t SPI_MEM_FDUMMY_RIN : 1; /*!< In the dummy phase of a MSPI read data transfer when accesses - to flash, the signal level of SPI bus is output by the - MSPI controller. */ - __IOM uint32_t SPI_MEM_FDUMMY_WOUT : 1; /*!< In the dummy phase of a MSPI write data transfer when accesses - to flash, the signal level of SPI bus is output by the - MSPI controller. */ - __IOM uint32_t SPI_MEM_FDOUT_OCT : 1; /*!< Apply 8 signals during write-data phase 1:enable 0: disable */ - __IOM uint32_t SPI_MEM_FDIN_OCT : 1; /*!< Apply 8 signals during read-data phase 1:enable 0: disable */ - __IOM uint32_t SPI_MEM_FADDR_OCT : 1; /*!< Apply 8 signals during address phase 1:enable 0: disable */ - uint32_t : 1; - __IOM uint32_t SPI_MEM_FCMD_QUAD : 1; /*!< Apply 4 signals during command phase 1:enable 0: disable */ - __IOM uint32_t SPI_MEM_FCMD_OCT : 1; /*!< Apply 8 signals during command phase 1:enable 0: disable */ - __IOM uint32_t SPI_MEM_FCS_CRC_EN : 1; /*!< For SPI1, initialize crc32 module before writing encrypted data - to flash. Active low. */ - __IOM uint32_t SPI_MEM_TX_CRC_EN : 1; /*!< For SPI1, enable crc32 when writing encrypted data to flash. - 1: enable 0:disable */ - uint32_t : 1; - __IOM uint32_t SPI_MEM_FASTRD_MODE : 1; /*!< This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, - spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: - disable. */ - __IOM uint32_t SPI_MEM_FREAD_DUAL : 1; /*!< In the read operations, read-data phase apply 2 signals. 1: - enable 0: disable. */ - __IOM uint32_t SPI_MEM_RESANDRES : 1; /*!< The Device ID is read out to SPI_MEM_RD_STATUS register, this - bit combine with spi_mem_flash_res bit. 1: enable 0: disable. */ - uint32_t : 2; - __IOM uint32_t SPI_MEM_Q_POL : 1; /*!< The bit is used to set MISO line polarity, 1: high 0, low */ - __IOM uint32_t SPI_MEM_D_POL : 1; /*!< The bit is used to set MOSI line polarity, 1: high 0, low */ - __IOM uint32_t SPI_MEM_FREAD_QUAD : 1; /*!< In the read operations read-data phase apply 4 signals. 1: enable - 0: disable. */ - __IOM uint32_t SPI_MEM_WP : 1; /*!< Write protect signal output when SPI is idle. 1: output high, - 0: output low. */ - __IOM uint32_t SPI_MEM_WRSR_2B : 1; /*!< two bytes data will be written to status register when it is - set. 1: enable 0: disable. */ - __IOM uint32_t SPI_MEM_FREAD_DIO : 1; /*!< In the read operations address phase and read-data phase apply - 2 signals. 1: enable 0: disable. */ - __IOM uint32_t SPI_MEM_FREAD_QIO : 1; /*!< In the read operations address phase and read-data phase apply - 4 signals. 1: enable 0: disable. */ - uint32_t : 7; - } bit; - } SPI_MEM_CTRL; - - union { - __IOM uint32_t reg; /*!< SPI1 control1 register. */ - - struct { - __IOM uint32_t SPI_MEM_CLK_MODE : 2; /*!< SPI clock mode bits. 0: SPI clock is off when CS inactive 1: - SPI clock is delayed one cycle after CS inactive 2: SPI - clock is delayed two cycles after CS inactive 3: SPI clock - is alwasy on. */ - __IOM uint32_t SPI_MEM_CS_HOLD_DLY_RES : 10;/*!< After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] - * 512) SPI_CLK cycles. */ - uint32_t : 20; - } bit; - } SPI_MEM_CTRL1; - - union { - __IOM uint32_t reg; /*!< SPI1 control2 register. */ - - struct { - uint32_t : 31; - __OM uint32_t SPI_MEM_SYNC_RESET : 1; /*!< The FSM will be reset. */ - } bit; - } SPI_MEM_CTRL2; - - union { - __IOM uint32_t reg; /*!< SPI1 clock division control register. */ - - struct { - __IOM uint32_t SPI_MEM_CLKCNT_L : 8; /*!< In the master mode it must be equal to spi_mem_clkcnt_N. */ - __IOM uint32_t SPI_MEM_CLKCNT_H : 8; /*!< In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). */ - __IOM uint32_t SPI_MEM_CLKCNT_N : 8; /*!< In the master mode it is the divider of spi_mem_clk. So spi_mem_clk - frequency is system/(spi_mem_clkcnt_N+1) */ - uint32_t : 7; - __IOM uint32_t SPI_MEM_CLK_EQU_SYSCLK : 1;/*!< reserved */ - } bit; - } SPI_MEM_CLOCK; - - union { - __IOM uint32_t reg; /*!< SPI1 user register. */ - - struct { - uint32_t : 9; - __IOM uint32_t SPI_MEM_CK_OUT_EDGE : 1; /*!< the bit combined with spi_mem_mosi_delay_mode bits to set mosi - signal delay mode. */ - uint32_t : 2; - __IOM uint32_t SPI_MEM_FWRITE_DUAL : 1; /*!< In the write operations read-data phase apply 2 signals */ - __IOM uint32_t SPI_MEM_FWRITE_QUAD : 1; /*!< In the write operations read-data phase apply 4 signals */ - __IOM uint32_t SPI_MEM_FWRITE_DIO : 1; /*!< In the write operations address phase and read-data phase apply - 2 signals. */ - __IOM uint32_t SPI_MEM_FWRITE_QIO : 1; /*!< In the write operations address phase and read-data phase apply - 4 signals. */ - uint32_t : 8; - __IOM uint32_t SPI_MEM_USR_MISO_HIGHPART : 1;/*!< read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. - 1: enable 0: disable. */ - __IOM uint32_t SPI_MEM_USR_MOSI_HIGHPART : 1;/*!< write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15 - 1: enable 0: disable. */ - __IOM uint32_t SPI_MEM_USR_DUMMY_IDLE : 1;/*!< SPI clock is disable in dummy phase when the bit is enable. */ - __IOM uint32_t SPI_MEM_USR_MOSI : 1; /*!< This bit enable the write-data phase of an operation. */ - __IOM uint32_t SPI_MEM_USR_MISO : 1; /*!< This bit enable the read-data phase of an operation. */ - __IOM uint32_t SPI_MEM_USR_DUMMY : 1; /*!< This bit enable the dummy phase of an operation. */ - __IOM uint32_t SPI_MEM_USR_ADDR : 1; /*!< This bit enable the address phase of an operation. */ - __IOM uint32_t SPI_MEM_USR_COMMAND : 1; /*!< This bit enable the command phase of an operation. */ - } bit; - } SPI_MEM_USER; - - union { - __IOM uint32_t reg; /*!< SPI1 user1 register. */ - - struct { - __IOM uint32_t SPI_MEM_USR_DUMMY_CYCLELEN : 6;/*!< The length in spi_mem_clk cycles of dummy phase. The register - value shall be (cycle_num-1). */ - uint32_t : 20; - __IOM uint32_t SPI_MEM_USR_ADDR_BITLEN : 6;/*!< The length in bits of address phase. The register value shall - be (bit_num-1). */ - } bit; - } SPI_MEM_USER1; - - union { - __IOM uint32_t reg; /*!< SPI1 user2 register. */ - - struct { - __IOM uint32_t SPI_MEM_USR_COMMAND_VALUE : 16;/*!< The value of command. */ - uint32_t : 12; - __IOM uint32_t SPI_MEM_USR_COMMAND_BITLEN : 4;/*!< The length in bits of command phase. The register value shall - be (bit_num-1) */ - } bit; - } SPI_MEM_USER2; - - union { - __IOM uint32_t reg; /*!< SPI1 send data bit length control register. */ - - struct { - __IOM uint32_t SPI_MEM_USR_MOSI_DBITLEN : 10;/*!< The length in bits of write-data. The register value shall be - (bit_num-1). */ - uint32_t : 22; - } bit; - } SPI_MEM_MOSI_DLEN; - - union { - __IOM uint32_t reg; /*!< SPI1 receive data bit length control register. */ - - struct { - __IOM uint32_t SPI_MEM_USR_MISO_DBITLEN : 10;/*!< The length in bits of read-data. The register value shall be - (bit_num-1). */ - uint32_t : 22; - } bit; - } SPI_MEM_MISO_DLEN; - - union { - __IOM uint32_t reg; /*!< SPI1 status register. */ - - struct { - __IOM uint32_t SPI_MEM_STATUS : 16; /*!< The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res - bit. */ - __IOM uint32_t SPI_MEM_WB_MODE : 8; /*!< Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode - bit. */ - uint32_t : 8; - } bit; - } SPI_MEM_RD_STATUS; - __IM uint32_t RESERVED; - - union { - __IOM uint32_t reg; /*!< SPI1 misc register */ - - struct { - __IOM uint32_t SPI_MEM_CS0_DIS : 1; /*!< SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active - to select SPI device, such as flash, external RAM and so - on. */ - __IOM uint32_t SPI_MEM_CS1_DIS : 1; /*!< SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active - to select SPI device, such as flash, external RAM and so - on. */ - uint32_t : 7; - __IOM uint32_t SPI_MEM_CK_IDLE_EDGE : 1; /*!< 1: spi clk line is high when idle 0: spi clk line is low when - idle */ - __IOM uint32_t SPI_MEM_CS_KEEP_ACTIVE : 1;/*!< spi cs line keep low when the bit is set. */ - uint32_t : 21; - } bit; - } SPI_MEM_MISC; - - union { - __IOM uint32_t reg; /*!< SPI1 TX CRC data register. */ - - struct { - __IM uint32_t DATA : 32; /*!< For SPI1, the value of crc32. */ - } bit; - } SPI_MEM_TX_CRC; - - union { - __IOM uint32_t reg; /*!< SPI1 bit mode control register. */ - - struct { - uint32_t : 1; - __IOM uint32_t SPI_MEM_CACHE_USR_ADDR_4BYTE : 1;/*!< For SPI1, cache read flash with 4 bytes address, 1: enable, - 0:disable. */ - uint32_t : 1; - __IOM uint32_t SPI_MEM_FDIN_DUAL : 1; /*!< For SPI1, din phase apply 2 signals. 1: enable 0: disable. The - bit is the same with spi_mem_fread_dio. */ - __IOM uint32_t SPI_MEM_FDOUT_DUAL : 1; /*!< For SPI1, dout phase apply 2 signals. 1: enable 0: disable. - The bit is the same with spi_mem_fread_dio. */ - __IOM uint32_t SPI_MEM_FADDR_DUAL : 1; /*!< For SPI1, address phase apply 2 signals. 1: enable 0: disable. - The bit is the same with spi_mem_fread_dio. */ - __IOM uint32_t SPI_MEM_FDIN_QUAD : 1; /*!< For SPI1, din phase apply 4 signals. 1: enable 0: disable. The - bit is the same with spi_mem_fread_qio. */ - __IOM uint32_t SPI_MEM_FDOUT_QUAD : 1; /*!< For SPI1, dout phase apply 4 signals. 1: enable 0: disable. - The bit is the same with spi_mem_fread_qio. */ - __IOM uint32_t SPI_MEM_FADDR_QUAD : 1; /*!< For SPI1, address phase apply 4 signals. 1: enable 0: disable. - The bit is the same with spi_mem_fread_qio. */ - uint32_t : 23; - } bit; - } SPI_MEM_CACHE_FCTRL; - __IM uint32_t RESERVED1[6]; - - union { - __IOM uint32_t reg; /*!< SPI1 memory data buffer0 */ - - struct { - __IOM uint32_t SPI_MEM_BUF0 : 32; /*!< data buffer */ - } bit; - } SPI_MEM_W0; - - union { - __IOM uint32_t reg; /*!< SPI1 memory data buffer1 */ - - struct { - __IOM uint32_t SPI_MEM_BUF1 : 32; /*!< data buffer */ - } bit; - } SPI_MEM_W1; - - union { - __IOM uint32_t reg; /*!< SPI1 memory data buffer2 */ - - struct { - __IOM uint32_t SPI_MEM_BUF2 : 32; /*!< data buffer */ - } bit; - } SPI_MEM_W2; - - union { - __IOM uint32_t reg; /*!< SPI1 memory data buffer3 */ - - struct { - __IOM uint32_t SPI_MEM_BUF3 : 32; /*!< data buffer */ - } bit; - } SPI_MEM_W3; - - union { - __IOM uint32_t reg; /*!< SPI1 memory data buffer4 */ - - struct { - __IOM uint32_t SPI_MEM_BUF4 : 32; /*!< data buffer */ - } bit; - } SPI_MEM_W4; - - union { - __IOM uint32_t reg; /*!< SPI1 memory data buffer5 */ - - struct { - __IOM uint32_t SPI_MEM_BUF5 : 32; /*!< data buffer */ - } bit; - } SPI_MEM_W5; - - union { - __IOM uint32_t reg; /*!< SPI1 memory data buffer6 */ - - struct { - __IOM uint32_t SPI_MEM_BUF6 : 32; /*!< data buffer */ - } bit; - } SPI_MEM_W6; - - union { - __IOM uint32_t reg; /*!< SPI1 memory data buffer7 */ - - struct { - __IOM uint32_t SPI_MEM_BUF7 : 32; /*!< data buffer */ - } bit; - } SPI_MEM_W7; - - union { - __IOM uint32_t reg; /*!< SPI1 memory data buffer8 */ - - struct { - __IOM uint32_t SPI_MEM_BUF8 : 32; /*!< data buffer */ - } bit; - } SPI_MEM_W8; - - union { - __IOM uint32_t reg; /*!< SPI1 memory data buffer9 */ - - struct { - __IOM uint32_t SPI_MEM_BUF9 : 32; /*!< data buffer */ - } bit; - } SPI_MEM_W9; - - union { - __IOM uint32_t reg; /*!< SPI1 memory data buffer10 */ - - struct { - __IOM uint32_t SPI_MEM_BUF10 : 32; /*!< data buffer */ - } bit; - } SPI_MEM_W10; - - union { - __IOM uint32_t reg; /*!< SPI1 memory data buffer11 */ - - struct { - __IOM uint32_t SPI_MEM_BUF11 : 32; /*!< data buffer */ - } bit; - } SPI_MEM_W11; - - union { - __IOM uint32_t reg; /*!< SPI1 memory data buffer12 */ - - struct { - __IOM uint32_t SPI_MEM_BUF12 : 32; /*!< data buffer */ - } bit; - } SPI_MEM_W12; - - union { - __IOM uint32_t reg; /*!< SPI1 memory data buffer13 */ - - struct { - __IOM uint32_t SPI_MEM_BUF13 : 32; /*!< data buffer */ - } bit; - } SPI_MEM_W13; - - union { - __IOM uint32_t reg; /*!< SPI1 memory data buffer14 */ - - struct { - __IOM uint32_t SPI_MEM_BUF14 : 32; /*!< data buffer */ - } bit; - } SPI_MEM_W14; - - union { - __IOM uint32_t reg; /*!< SPI1 memory data buffer15 */ - - struct { - __IOM uint32_t SPI_MEM_BUF15 : 32; /*!< data buffer */ - } bit; - } SPI_MEM_W15; - - union { - __IOM uint32_t reg; /*!< SPI1 wait idle control register */ - - struct { - __IOM uint32_t SPI_MEM_WAITI_EN : 1; /*!< 1: The hardware will wait idle after SE/PP/WRSR automatically, - and hardware auto Suspend/Resume can be enabled. 0: The - functions of hardware wait idle and auto Suspend/Resume - are not supported. */ - __IOM uint32_t SPI_MEM_WAITI_DUMMY : 1; /*!< The dummy phase enable when wait flash idle (RDSR) */ - __IOM uint32_t SPI_MEM_WAITI_ADDR_EN : 1; /*!< 1: Output address 0 in RDSR or read SUS command transfer. 0: - Do not send out address in RDSR or read SUS command transfer. */ - __IOM uint32_t SPI_MEM_WAITI_ADDR_CYCLELEN : 2;/*!< When SPI_MEM_WAITI_ADDR_EN is set, the cycle length of sent - out address is (SPI_MEM_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI - bus clock cycles. It is not active when SPI_MEM_WAITI_ADDR_EN - is cleared. */ - uint32_t : 4; - __IOM uint32_t SPI_MEM_WAITI_CMD_2B : 1; /*!< 1:The wait idle command bit length is 16. 0: The wait idle command - bit length is 8. */ - __IOM uint32_t SPI_MEM_WAITI_DUMMY_CYCLELEN : 6;/*!< The dummy cycle length when wait flash idle(RDSR). */ - __IOM uint32_t SPI_MEM_WAITI_CMD : 16; /*!< The command value to wait flash idle(RDSR). */ - } bit; - } SPI_MEM_FLASH_WAITI_CTRL; - - union { - __IOM uint32_t reg; /*!< SPI1 flash suspend control register */ - - struct { - __IOM uint32_t SPI_MEM_FLASH_PER : 1; /*!< program erase resume bit, program erase suspend operation will - be triggered when the bit is set. The bit will be cleared - once the operation done.1: enable 0: disable. */ - __IOM uint32_t SPI_MEM_FLASH_PES : 1; /*!< program erase suspend bit, program erase suspend operation will - be triggered when the bit is set. The bit will be cleared - once the operation done.1: enable 0: disable. */ - __IOM uint32_t SPI_MEM_FLASH_PER_WAIT_EN : 1;/*!< 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK - cycles after program erase resume command is sent. 0: SPI1 - does not wait after program erase resume command is sent. */ - __IOM uint32_t SPI_MEM_FLASH_PES_WAIT_EN : 1;/*!< 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK - cycles after program erase suspend command is sent. 0: - SPI1 does not wait after program erase suspend command - is sent. */ - __IOM uint32_t SPI_MEM_PES_PER_EN : 1; /*!< Set this bit to enable PES end triggers PER transfer option. - If this bit is 0, application should send PER after PES - is done. */ - __IOM uint32_t SPI_MEM_FLASH_PES_EN : 1; /*!< Set this bit to enable Auto-suspending function. */ - __IOM uint32_t SPI_MEM_PESR_END_MSK : 16; /*!< The mask value when check SUS/SUS1/SUS2 status bit. If the read - status value is status_in[15:0](only status_in[7:0] is - valid when only one byte of data is read out, status_in[15:0] - is valid when two bytes of data are read out), SUS/SUS1/SUS2 - = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0]. */ - __IOM uint32_t SPI_FMEM_RD_SUS_2B : 1; /*!< 1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. - 0: Read one byte when check flash SUS/SUS1/SUS2 status - bit */ - __IOM uint32_t SPI_MEM_PER_END_EN : 1; /*!< 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure - the resume status of flash. 0: Only need to check WIP is - 0. */ - __IOM uint32_t SPI_MEM_PES_END_EN : 1; /*!< 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure - the suspend status of flash. 0: Only need to check WIP - is 0. */ - __IOM uint32_t SPI_MEM_SUS_TIMEOUT_CNT : 7;/*!< When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] - times, it will be treated as check pass. */ - } bit; - } SPI_MEM_FLASH_SUS_CTRL; - - union { - __IOM uint32_t reg; /*!< SPI1 flash suspend command register */ - - struct { - __IOM uint32_t SPI_MEM_FLASH_PES_COMMAND : 16;/*!< Program/Erase suspend command. */ - __IOM uint32_t SPI_MEM_WAIT_PESR_COMMAND : 16;/*!< Flash SUS/SUS1/SUS2 status bit read command. The command should - be sent when SUS/SUS1/SUS2 bit should be checked to insure - the suspend or resume status of flash. */ - } bit; - } SPI_MEM_FLASH_SUS_CMD; - - union { - __IOM uint32_t reg; /*!< SPI1 flash suspend status register */ - - struct { - __IOM uint32_t SPI_MEM_FLASH_SUS : 1; /*!< The status of flash suspend, only used in SPI1. */ - __IOM uint32_t SPI_MEM_WAIT_PESR_CMD_2B : 1;/*!< 1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 - bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to - check SUS/SUS1/SUS2 bit. */ - __IOM uint32_t SPI_MEM_FLASH_HPM_DLY_128 : 1;/*!< 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK - cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RE - [9:0] * 4) SPI_CLK cycles after HPM command is sent. */ - __IOM uint32_t SPI_MEM_FLASH_RES_DLY_128 : 1;/*!< 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK - cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RE - [9:0] * 4) SPI_CLK cycles after RES command is sent. */ - __IOM uint32_t SPI_MEM_FLASH_DP_DLY_128 : 1;/*!< 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK - cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES - 9:0] * 4) SPI_CLK cycles after DP command is sent. */ - __IOM uint32_t SPI_MEM_FLASH_PER_DLY_128 : 1;/*!< Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELA - _RES[9:0] * 128) SPI_CLK cycles after PER command is sent. - 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK - cycles after PER command is sent. */ - __IOM uint32_t SPI_MEM_FLASH_PES_DLY_128 : 1;/*!< Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELA - _RES[9:0] * 128) SPI_CLK cycles after PES command is sent. - 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK - cycles after PES command is sent. */ - __IOM uint32_t SPI_MEM_SPI0_LOCK_EN : 1; /*!< 1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it. */ - uint32_t : 7; - __IOM uint32_t SPI_MEM_FLASH_PESR_CMD_2B : 1;/*!< 1: The bit length of Program/Erase Suspend/Resume command is - 16. 0: The bit length of Program/Erase Suspend/Resume command - is 8. */ - __IOM uint32_t SPI_MEM_FLASH_PER_COMMAND : 16;/*!< Program/Erase resume command. */ - } bit; - } SPI_MEM_SUS_STATUS; - __IM uint32_t RESERVED2[6]; - - union { - __IOM uint32_t reg; /*!< SPI1 interrupt enable register */ - - struct { - __IOM uint32_t SPI_MEM_PER_END_INT_ENA : 1;/*!< The enable bit for SPI_MEM_PER_END_INT interrupt. */ - __IOM uint32_t SPI_MEM_PES_END_INT_ENA : 1;/*!< The enable bit for SPI_MEM_PES_END_INT interrupt. */ - __IOM uint32_t SPI_MEM_WPE_END_INT_ENA : 1;/*!< The enable bit for SPI_MEM_WPE_END_INT interrupt. */ - __IOM uint32_t SPI_MEM_SLV_ST_END_INT_ENA : 1;/*!< The enable bit for SPI_MEM_SLV_ST_END_INT interrupt. */ - __IOM uint32_t SPI_MEM_MST_ST_END_INT_ENA : 1;/*!< The enable bit for SPI_MEM_MST_ST_END_INT interrupt. */ - uint32_t : 5; - __IOM uint32_t SPI_MEM_BROWN_OUT_INT_ENA : 1;/*!< The enable bit for SPI_MEM_BROWN_OUT_INT interrupt. */ - uint32_t : 21; - } bit; - } SPI_MEM_INT_ENA; - - union { - __IOM uint32_t reg; /*!< SPI1 interrupt clear register */ - - struct { - __OM uint32_t SPI_MEM_PER_END_INT_CLR : 1;/*!< The clear bit for SPI_MEM_PER_END_INT interrupt. */ - __OM uint32_t SPI_MEM_PES_END_INT_CLR : 1;/*!< The clear bit for SPI_MEM_PES_END_INT interrupt. */ - __OM uint32_t SPI_MEM_WPE_END_INT_CLR : 1;/*!< The clear bit for SPI_MEM_WPE_END_INT interrupt. */ - __OM uint32_t SPI_MEM_SLV_ST_END_INT_CLR : 1;/*!< The clear bit for SPI_MEM_SLV_ST_END_INT interrupt. */ - __OM uint32_t SPI_MEM_MST_ST_END_INT_CLR : 1;/*!< The clear bit for SPI_MEM_MST_ST_END_INT interrupt. */ - uint32_t : 5; - __OM uint32_t SPI_MEM_BROWN_OUT_INT_CLR : 1;/*!< The status bit for SPI_MEM_BROWN_OUT_INT interrupt. */ - uint32_t : 21; - } bit; - } SPI_MEM_INT_CLR; - - union { - __IOM uint32_t reg; /*!< SPI1 interrupt raw register */ - - struct { - __IOM uint32_t SPI_MEM_PER_END_INT_RAW : 1;/*!< The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered - when Auto Resume command (0x7A) is sent and flash is resumed - successfully. 0: Others. */ - __IOM uint32_t SPI_MEM_PES_END_INT_RAW : 1;/*!< The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when - Auto Suspend command (0x75) is sent and flash is suspended - successfully. 0: Others. */ - __IOM uint32_t SPI_MEM_WPE_END_INT_RAW : 1;/*!< The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered - when WRSR/PP/SE/BE/CE is sent and flash is already idle. - 0: Others. */ - __IOM uint32_t SPI_MEM_SLV_ST_END_INT_RAW : 1;/*!< The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered - when spi1_slv_st is changed from non idle state to idle - state. It means that SPI_CS raises high. 0: Others */ - __IOM uint32_t SPI_MEM_MST_ST_END_INT_RAW : 1;/*!< The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered - when spi1_mst_st is changed from non idle state to idle - state. 0: Others. */ - uint32_t : 5; - __IOM uint32_t SPI_MEM_BROWN_OUT_INT_RAW : 1;/*!< The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered - condition is that chip is loosing power and RTC module - sends out brown out close flash request to SPI1. After - SPI1 sends out suspend command to flash, this interrupt - is triggered and MSPI returns to idle state. 0: Others. */ - uint32_t : 21; - } bit; - } SPI_MEM_INT_RAW; - - union { - __IOM uint32_t reg; /*!< SPI1 interrupt status register */ - - struct { - __IM uint32_t SPI_MEM_PER_END_INT_ST : 1;/*!< The status bit for SPI_MEM_PER_END_INT interrupt. */ - __IM uint32_t SPI_MEM_PES_END_INT_ST : 1;/*!< The status bit for SPI_MEM_PES_END_INT interrupt. */ - __IM uint32_t SPI_MEM_WPE_END_INT_ST : 1;/*!< The status bit for SPI_MEM_WPE_END_INT interrupt. */ - __IM uint32_t SPI_MEM_SLV_ST_END_INT_ST : 1;/*!< The status bit for SPI_MEM_SLV_ST_END_INT interrupt. */ - __IM uint32_t SPI_MEM_MST_ST_END_INT_ST : 1;/*!< The status bit for SPI_MEM_MST_ST_END_INT interrupt. */ - uint32_t : 5; - __IM uint32_t SPI_MEM_BROWN_OUT_INT_ST : 1;/*!< The status bit for SPI_MEM_BROWN_OUT_INT interrupt. */ - uint32_t : 21; - } bit; - } SPI_MEM_INT_ST; - __IM uint32_t RESERVED3; - - union { - __IOM uint32_t reg; /*!< SPI1 DDR control register */ - - struct { - __IOM uint32_t SPI_FMEM_DDR_EN : 1; /*!< 1: in ddr mode, 0 in sdr mode */ - __IOM uint32_t SPI_FMEM_VAR_DUMMY : 1; /*!< Set the bit to enable variable dummy cycle in spi ddr mode. */ - __IOM uint32_t SPI_FMEM_DDR_RDAT_SWP : 1; /*!< Set the bit to reorder rx data of the word in spi ddr mode. */ - __IOM uint32_t SPI_FMEM_DDR_WDAT_SWP : 1; /*!< Set the bit to reorder tx data of the word in spi ddr mode. */ - __IOM uint32_t SPI_FMEM_DDR_CMD_DIS : 1; /*!< the bit is used to disable dual edge in command phase when ddr - mode. */ - __IOM uint32_t SPI_FMEM_OUTMINBYTELEN : 7;/*!< It is the minimum output data length in the panda device. */ - uint32_t : 2; - __IOM uint32_t SPI_FMEM_USR_DDR_DQS_THD : 7;/*!< The delay number of data strobe which from memory based on SPI - clock. */ - __IOM uint32_t SPI_FMEM_DDR_DQS_LOOP : 1; /*!< 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive - data when spi0_slv_st is in SPI_MEM_DIN state. It is used - when there is no SPI_DQS signal or SPI_DQS signal is not - stable. 0: SPI0 starts to store data at the positive and - negative edge of SPI_DQS. */ - uint32_t : 2; - __IOM uint32_t SPI_FMEM_CLK_DIFF_EN : 1; /*!< Set this bit to enable the differential SPI_CLK#. */ - uint32_t : 1; - __IOM uint32_t SPI_FMEM_DQS_CA_IN : 1; /*!< Set this bit to enable the input of SPI_DQS signal in SPI phases - of CMD and ADDR. */ - __IOM uint32_t SPI_FMEM_HYPERBUS_DUMMY_2X : 1;/*!< Set this bit to enable the vary dummy function in SPI HyperBus - mode, when SPI0 accesses flash or SPI1 accesses flash or - sram. */ - __IOM uint32_t SPI_FMEM_CLK_DIFF_INV : 1; /*!< Set this bit to invert SPI_DIFF when accesses to flash. . */ - __IOM uint32_t SPI_FMEM_OCTA_RAM_ADDR : 1;/*!< Set this bit to enable octa_ram address out when accesses to - flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], - 6'd0, spi_usr_addr_value[3:1], 1'b0}. */ - __IOM uint32_t SPI_FMEM_HYPERBUS_CA : 1; /*!< Set this bit to enable HyperRAM address out when accesses to - flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], - 13'd0, spi_usr_addr_value[3:1]}. */ - uint32_t : 1; - } bit; - } SPI_MEM_DDR; - __IM uint32_t RESERVED4[42]; - - union { - __IOM uint32_t reg; /*!< SPI1 timing control register */ - - struct { - uint32_t : 1; - __IOM uint32_t SPI_MEM_TIMING_CALI : 1; /*!< The bit is used to enable timing auto-calibration for all reading - operations. */ - __IOM uint32_t SPI_MEM_EXTRA_DUMMY_CYCLELEN : 3;/*!< add extra dummy spi clock cycle length for spi clock calibration. */ - uint32_t : 27; - } bit; - } SPI_MEM_TIMING_CALI; - __IM uint32_t RESERVED5[31]; - - union { - __IOM uint32_t reg; /*!< SPI1 clk_gate register */ - - struct { - __IOM uint32_t SPI_MEM_CLK_EN : 1; /*!< Register clock gate enable signal. 1: Enable. 0: Disable. */ - uint32_t : 31; - } bit; - } SPI_MEM_CLOCK_GATE; - __IM uint32_t RESERVED6[126]; - - union { - __IOM uint32_t reg; /*!< Version control register */ - - struct { - __IOM uint32_t SPI_MEM_DATE : 28; /*!< Version control register */ - uint32_t : 4; - } bit; - } SPI_MEM_DATE; -} SPI1_Type; /*!< Size = 1024 (0x400) */ - - - -/* =========================================================================================================================== */ -/* ================ SPI2 ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief SPI (Serial Peripheral Interface) Controller 2 (SPI2) - */ - -typedef struct { /*!< SPI2 Structure */ - - union { - __IOM uint32_t reg; /*!< Command control register */ - - struct { - __IOM uint32_t SPI_CONF_BITLEN : 18; /*!< Define the APB cycles of SPI_CONF state. Can be configured in - CONF state. */ - uint32_t : 5; - __OM uint32_t SPI_UPDATE : 1; /*!< Set this bit to synchronize SPI registers from APB clock domain - into SPI module clock domain, which is only used in SPI - master mode. */ - __IOM uint32_t SPI_USR : 1; /*!< User define command enable. An operation will be triggered when - the bit is set. The bit will be cleared once the operation - done.1: enable 0: disable. Can not be changed by CONF_buf. */ - uint32_t : 7; - } bit; - } SPI_CMD; - - union { - __IOM uint32_t reg; /*!< Address value register */ - - struct { - __IOM uint32_t SPI_USR_ADDR_VALUE : 32; /*!< Address to slave. Can be configured in CONF state. */ - } bit; - } SPI_ADDR; - - union { - __IOM uint32_t reg; /*!< SPI control register */ - - struct { - uint32_t : 3; - __IOM uint32_t SPI_DUMMY_OUT : 1; /*!< 0: In the dummy phase, the FSPI bus signals are not output. - 1: In the dummy phase, the FSPI bus signals are output. - Can be configured in CONF state. */ - uint32_t : 1; - __IOM uint32_t SPI_FADDR_DUAL : 1; /*!< Apply 2 signals during addr phase 1:enable 0: disable. Can be - configured in CONF state. */ - __IOM uint32_t SPI_FADDR_QUAD : 1; /*!< Apply 4 signals during addr phase 1:enable 0: disable. Can be - configured in CONF state. */ - __IOM uint32_t SPI_FADDR_OCT : 1; /*!< Apply 8 signals during addr phase 1:enable 0: disable. Can be - configured in CONF state. */ - __IOM uint32_t SPI_FCMD_DUAL : 1; /*!< Apply 2 signals during command phase 1:enable 0: disable. Can - be configured in CONF state. */ - __IOM uint32_t SPI_FCMD_QUAD : 1; /*!< Apply 4 signals during command phase 1:enable 0: disable. Can - be configured in CONF state. */ - __IOM uint32_t SPI_FCMD_OCT : 1; /*!< Apply 8 signals during command phase 1:enable 0: disable. Can - be configured in CONF state. */ - uint32_t : 3; - __IOM uint32_t SPI_FREAD_DUAL : 1; /*!< In the read operations, read-data phase apply 2 signals. 1: - enable 0: disable. Can be configured in CONF state. */ - __IOM uint32_t SPI_FREAD_QUAD : 1; /*!< In the read operations read-data phase apply 4 signals. 1: enable - 0: disable. Can be configured in CONF state. */ - __IOM uint32_t SPI_FREAD_OCT : 1; /*!< In the read operations read-data phase apply 8 signals. 1: enable - 0: disable. Can be configured in CONF state. */ - uint32_t : 1; - __IOM uint32_t SPI_Q_POL : 1; /*!< The bit is used to set MISO line polarity, 1: high 0, low. Can - be configured in CONF state. */ - __IOM uint32_t SPI_D_POL : 1; /*!< The bit is used to set MOSI line polarity, 1: high 0, low. Can - be configured in CONF state. */ - __IOM uint32_t SPI_HOLD_POL : 1; /*!< SPI_HOLD output value when SPI is idle. 1: output high, 0: output - low. Can be configured in CONF state. */ - __IOM uint32_t SPI_WP_POL : 1; /*!< Write protect signal output when SPI is idle. 1: output high, - 0: output low. Can be configured in CONF state. */ - uint32_t : 1; - __IOM uint32_t SPI_RD_BIT_ORDER : 2; /*!< In read-data (MISO) phase 1: LSB first 0: MSB first. Can be - configured in CONF state. */ - __IOM uint32_t SPI_WR_BIT_ORDER : 2; /*!< In command address write-data (MOSI) phases 1: LSB firs 0: MSB - first. Can be configured in CONF state. */ - uint32_t : 5; - } bit; - } SPI_CTRL; - - union { - __IOM uint32_t reg; /*!< SPI clock control register */ - - struct { - __IOM uint32_t SPI_CLKCNT_L : 6; /*!< In the master mode it must be equal to spi_clkcnt_N. In the - slave mode it must be 0. Can be configured in CONF state. */ - __IOM uint32_t SPI_CLKCNT_H : 6; /*!< In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In - the slave mode it must be 0. Can be configured in CONF - state. */ - __IOM uint32_t SPI_CLKCNT_N : 6; /*!< In the master mode it is the divider of spi_clk. So spi_clk - frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). - Can be configured in CONF state. */ - __IOM uint32_t SPI_CLKDIV_PRE : 4; /*!< In the master mode it is pre-divider of spi_clk. Can be configured - in CONF state. */ - uint32_t : 9; - __IOM uint32_t SPI_CLK_EQU_SYSCLK : 1; /*!< In the master mode 1: spi_clk is eqaul to system 0: spi_clk - is divided from system clock. Can be configured in CONF - state. */ - } bit; - } SPI_CLOCK; - - union { - __IOM uint32_t reg; /*!< SPI USER control register */ - - struct { - __IOM uint32_t SPI_DOUTDIN : 1; /*!< Set the bit to enable full duplex communication. 1: enable 0: - disable. Can be configured in CONF state. */ - uint32_t : 2; - __IOM uint32_t SPI_QPI_MODE : 1; /*!< Both for master mode and slave mode. 1: spi controller is in - QPI mode. 0: others. Can be configured in CONF state. */ - __IOM uint32_t SPI_OPI_MODE : 1; /*!< Just for master mode. 1: spi controller is in OPI mode (all - in 8-b-m). 0: others. Can be configured in CONF state. */ - __IOM uint32_t SPI_TSCK_I_EDGE : 1; /*!< In the slave mode, this bit can be used to change the polarity - of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i. */ - __IOM uint32_t SPI_CS_HOLD : 1; /*!< spi cs keep low when spi is in done phase. 1: enable 0: disable. - Can be configured in CONF state. */ - __IOM uint32_t SPI_CS_SETUP : 1; /*!< spi cs is enable when spi is in prepare phase. 1: enable 0: - disable. Can be configured in CONF state. */ - __IOM uint32_t SPI_RSCK_I_EDGE : 1; /*!< In the slave mode, this bit can be used to change the polarity - of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i. */ - __IOM uint32_t SPI_CK_OUT_EDGE : 1; /*!< the bit combined with spi_mosi_delay_mode bits to set mosi signal - delay mode. Can be configured in CONF state. */ - uint32_t : 2; - __IOM uint32_t SPI_FWRITE_DUAL : 1; /*!< In the write operations read-data phase apply 2 signals. Can - be configured in CONF state. */ - __IOM uint32_t SPI_FWRITE_QUAD : 1; /*!< In the write operations read-data phase apply 4 signals. Can - be configured in CONF state. */ - __IOM uint32_t SPI_FWRITE_OCT : 1; /*!< In the write operations read-data phase apply 8 signals. Can - be configured in CONF state. */ - __IOM uint32_t SPI_USR_CONF_NXT : 1; /*!< 1: Enable the DMA CONF phase of next seg-trans operation, which - means seg-trans will continue. 0: The seg-trans will end - after the current SPI seg-trans or this is not seg-trans - mode. Can be configured in CONF state. */ - uint32_t : 1; - __IOM uint32_t SPI_SIO : 1; /*!< Set the bit to enable 3-line half duplex communication mosi - and miso signals share the same pin. 1: enable 0: disable. - Can be configured in CONF state. */ - uint32_t : 6; - __IOM uint32_t SPI_USR_MISO_HIGHPART : 1; /*!< read-data phase only access to high-part of the buffer spi_w8~spi_w15. - 1: enable 0: disable. Can be configured in CONF state. */ - __IOM uint32_t SPI_USR_MOSI_HIGHPART : 1; /*!< write-data phase only access to high-part of the buffer spi_w8~spi_w15. - 1: enable 0: disable. Can be configured in CONF state. */ - __IOM uint32_t SPI_USR_DUMMY_IDLE : 1; /*!< spi clock is disable in dummy phase when the bit is enable. - Can be configured in CONF state. */ - __IOM uint32_t SPI_USR_MOSI : 1; /*!< This bit enable the write-data phase of an operation. Can be - configured in CONF state. */ - __IOM uint32_t SPI_USR_MISO : 1; /*!< This bit enable the read-data phase of an operation. Can be - configured in CONF state. */ - __IOM uint32_t SPI_USR_DUMMY : 1; /*!< This bit enable the dummy phase of an operation. Can be configured - in CONF state. */ - __IOM uint32_t SPI_USR_ADDR : 1; /*!< This bit enable the address phase of an operation. Can be configured - in CONF state. */ - __IOM uint32_t SPI_USR_COMMAND : 1; /*!< This bit enable the command phase of an operation. Can be configured - in CONF state. */ - } bit; - } SPI_USER; - - union { - __IOM uint32_t reg; /*!< SPI USER control register 1 */ - - struct { - __IOM uint32_t SPI_USR_DUMMY_CYCLELEN : 8;/*!< The length in spi_clk cycles of dummy phase. The register value - shall be (cycle_num-1). Can be configured in CONF state. */ - uint32_t : 8; - __IOM uint32_t SPI_MST_WFULL_ERR_END_EN : 1;/*!< 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid - in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended - when SPI RX AFIFO wfull error is valid in GP-SPI master - FD/HD-mode. */ - __IOM uint32_t SPI_CS_SETUP_TIME : 5; /*!< (cycles+1) of prepare phase by spi clock this bits are combined - with spi_cs_setup bit. Can be configured in CONF state. */ - __IOM uint32_t SPI_CS_HOLD_TIME : 5; /*!< delay cycles of cs pin by spi clock this bits are combined with - spi_cs_hold bit. Can be configured in CONF state. */ - __IOM uint32_t SPI_USR_ADDR_BITLEN : 5; /*!< The length in bits of address phase. The register value shall - be (bit_num-1). Can be configured in CONF state. */ - } bit; - } SPI_USER1; - - union { - __IOM uint32_t reg; /*!< SPI USER control register 2 */ - - struct { - __IOM uint32_t SPI_USR_COMMAND_VALUE : 16;/*!< The value of command. Can be configured in CONF state. */ - uint32_t : 11; - __IOM uint32_t SPI_MST_REMPTY_ERR_END_EN : 1;/*!< 1: SPI transfer is ended when SPI TX AFIFO read empty error - is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is - not ended when SPI TX AFIFO read empty error is valid in - GP-SPI master FD/HD-mode. */ - __IOM uint32_t SPI_USR_COMMAND_BITLEN : 4;/*!< The length in bits of command phase. The register value shall - be (bit_num-1). Can be configured in CONF state. */ - } bit; - } SPI_USER2; - - union { - __IOM uint32_t reg; /*!< SPI data bit length control register */ - - struct { - __IOM uint32_t SPI_MS_DATA_BITLEN : 18; /*!< The value of these bits is the configured SPI transmission data - bit length in master mode DMA controlled transfer or CPU - controlled transfer. The value is also the configured bit - length in slave mode DMA RX controlled transfer. The register - value shall be (bit_num-1). Can be configured in CONF state. */ - uint32_t : 14; - } bit; - } SPI_MS_DLEN; - - union { - __IOM uint32_t reg; /*!< SPI misc register */ - - struct { - __IOM uint32_t SPI_CS0_DIS : 1; /*!< SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to - CS0 pin. Can be configured in CONF state. */ - __IOM uint32_t SPI_CS1_DIS : 1; /*!< SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to - CS1 pin. Can be configured in CONF state. */ - __IOM uint32_t SPI_CS2_DIS : 1; /*!< SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to - CS2 pin. Can be configured in CONF state. */ - __IOM uint32_t SPI_CS3_DIS : 1; /*!< SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to - CS3 pin. Can be configured in CONF state. */ - __IOM uint32_t SPI_CS4_DIS : 1; /*!< SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to - CS4 pin. Can be configured in CONF state. */ - __IOM uint32_t SPI_CS5_DIS : 1; /*!< SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to - CS5 pin. Can be configured in CONF state. */ - __IOM uint32_t SPI_CK_DIS : 1; /*!< 1: spi clk out disable, 0: spi clk out enable. Can be configured - in CONF state. */ - __IOM uint32_t SPI_MASTER_CS_POL : 6; /*!< In the master mode the bits are the polarity of spi cs line, - the value is equivalent to spi_cs ^ spi_master_cs_pol. - Can be configured in CONF state. */ - uint32_t : 3; - __IOM uint32_t SPI_CLK_DATA_DTR_EN : 1; /*!< 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. - 0: SPI master DTR mode is only applied to spi_dqs. This - bit should be used with bit 17/18/19. */ - __IOM uint32_t SPI_DATA_DTR_EN : 1; /*!< 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR - mode, including master 1/2/4/8-bm. 0: SPI clk and data - of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured - in CONF state. */ - __IOM uint32_t SPI_ADDR_DTR_EN : 1; /*!< 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, - including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR - state are in STR mode. Can be configured in CONF state. */ - __IOM uint32_t SPI_CMD_DTR_EN : 1; /*!< 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including - master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD - state are in STR mode. Can be configured in CONF state. */ - uint32_t : 3; - __IOM uint32_t SPI_SLAVE_CS_POL : 1; /*!< spi slave input cs polarity select. 1: inv 0: not change. Can - be configured in CONF state. */ - __IOM uint32_t SPI_DQS_IDLE_EDGE : 1; /*!< The default value of spi_dqs. Can be configured in CONF state. */ - uint32_t : 4; - __IOM uint32_t SPI_CK_IDLE_EDGE : 1; /*!< 1: spi clk line is high when idle 0: spi clk line is low when - idle. Can be configured in CONF state. */ - __IOM uint32_t SPI_CS_KEEP_ACTIVE : 1; /*!< spi cs line keep low when the bit is set. Can be configured - in CONF state. */ - __IOM uint32_t SPI_QUAD_DIN_PIN_SWAP : 1; /*!< 1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP - with FSPIHD. 0: spi quad input swap disable. Can be configured - in CONF state. */ - } bit; - } SPI_MISC; - - union { - __IOM uint32_t reg; /*!< SPI input delay mode configuration */ - - struct { - __IOM uint32_t SPI_DIN0_MODE : 2; /*!< the input signals are delayed by SPI module clock cycles, 0: - input without delayed, 1: input with the posedge of clk_apb,2 - input with the negedge of clk_apb, 3: input with the spi_clk. - Can be configured in CONF state. */ - __IOM uint32_t SPI_DIN1_MODE : 2; /*!< the input signals are delayed by SPI module clock cycles, 0: - input without delayed, 1: input with the posedge of clk_apb,2 - input with the negedge of clk_apb, 3: input with the spi_clk. - Can be configured in CONF state. */ - __IOM uint32_t SPI_DIN2_MODE : 2; /*!< the input signals are delayed by SPI module clock cycles, 0: - input without delayed, 1: input with the posedge of clk_apb,2 - input with the negedge of clk_apb, 3: input with the spi_clk. - Can be configured in CONF state. */ - __IOM uint32_t SPI_DIN3_MODE : 2; /*!< the input signals are delayed by SPI module clock cycles, 0: - input without delayed, 1: input with the posedge of clk_apb,2 - input with the negedge of clk_apb, 3: input with the spi_clk. - Can be configured in CONF state. */ - __IOM uint32_t SPI_DIN4_MODE : 2; /*!< the input signals are delayed by SPI module clock cycles, 0: - input without delayed, 1: input with the posedge of clk_apb,2 - input with the negedge of clk_apb, 3: input with the spi_clk. - Can be configured in CONF state. */ - __IOM uint32_t SPI_DIN5_MODE : 2; /*!< the input signals are delayed by SPI module clock cycles, 0: - input without delayed, 1: input with the posedge of clk_apb,2 - input with the negedge of clk_apb, 3: input with the spi_clk. - Can be configured in CONF state. */ - __IOM uint32_t SPI_DIN6_MODE : 2; /*!< the input signals are delayed by SPI module clock cycles, 0: - input without delayed, 1: input with the posedge of clk_apb,2 - input with the negedge of clk_apb, 3: input with the spi_clk. - Can be configured in CONF state. */ - __IOM uint32_t SPI_DIN7_MODE : 2; /*!< the input signals are delayed by SPI module clock cycles, 0: - input without delayed, 1: input with the posedge of clk_apb,2 - input with the negedge of clk_apb, 3: input with the spi_clk. - Can be configured in CONF state. */ - __IOM uint32_t SPI_TIMING_HCLK_ACTIVE : 1;/*!< 1:enable hclk in SPI input timing module. 0: disable it. Can - be configured in CONF state. */ - uint32_t : 15; - } bit; - } SPI_DIN_MODE; - - union { - __IOM uint32_t reg; /*!< SPI input delay number configuration */ - - struct { - __IOM uint32_t SPI_DIN0_NUM : 2; /*!< the input signals are delayed by SPI module clock cycles, 0: - delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured - in CONF state. */ - __IOM uint32_t SPI_DIN1_NUM : 2; /*!< the input signals are delayed by SPI module clock cycles, 0: - delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured - in CONF state. */ - __IOM uint32_t SPI_DIN2_NUM : 2; /*!< the input signals are delayed by SPI module clock cycles, 0: - delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured - in CONF state. */ - __IOM uint32_t SPI_DIN3_NUM : 2; /*!< the input signals are delayed by SPI module clock cycles, 0: - delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured - in CONF state. */ - __IOM uint32_t SPI_DIN4_NUM : 2; /*!< the input signals are delayed by SPI module clock cycles, 0: - delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured - in CONF state. */ - __IOM uint32_t SPI_DIN5_NUM : 2; /*!< the input signals are delayed by SPI module clock cycles, 0: - delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured - in CONF state. */ - __IOM uint32_t SPI_DIN6_NUM : 2; /*!< the input signals are delayed by SPI module clock cycles, 0: - delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured - in CONF state. */ - __IOM uint32_t SPI_DIN7_NUM : 2; /*!< the input signals are delayed by SPI module clock cycles, 0: - delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured - in CONF state. */ - uint32_t : 16; - } bit; - } SPI_DIN_NUM; - - union { - __IOM uint32_t reg; /*!< SPI output delay mode configuration */ - - struct { - __IOM uint32_t SPI_DOUT0_MODE : 1; /*!< The output signal 0 is delayed by the SPI module clock, 0: output - without delayed, 1: output delay for a SPI module clock - cycle at its negative edge. Can be configured in CONF state. */ - __IOM uint32_t SPI_DOUT1_MODE : 1; /*!< The output signal 1 is delayed by the SPI module clock, 0: output - without delayed, 1: output delay for a SPI module clock - cycle at its negative edge. Can be configured in CONF state. */ - __IOM uint32_t SPI_DOUT2_MODE : 1; /*!< The output signal 2 is delayed by the SPI module clock, 0: output - without delayed, 1: output delay for a SPI module clock - cycle at its negative edge. Can be configured in CONF state. */ - __IOM uint32_t SPI_DOUT3_MODE : 1; /*!< The output signal 3 is delayed by the SPI module clock, 0: output - without delayed, 1: output delay for a SPI module clock - cycle at its negative edge. Can be configured in CONF state. */ - __IOM uint32_t SPI_DOUT4_MODE : 1; /*!< The output signal 4 is delayed by the SPI module clock, 0: output - without delayed, 1: output delay for a SPI module clock - cycle at its negative edge. Can be configured in CONF state. */ - __IOM uint32_t SPI_DOUT5_MODE : 1; /*!< The output signal 5 is delayed by the SPI module clock, 0: output - without delayed, 1: output delay for a SPI module clock - cycle at its negative edge. Can be configured in CONF state. */ - __IOM uint32_t SPI_DOUT6_MODE : 1; /*!< The output signal 6 is delayed by the SPI module clock, 0: output - without delayed, 1: output delay for a SPI module clock - cycle at its negative edge. Can be configured in CONF state. */ - __IOM uint32_t SPI_DOUT7_MODE : 1; /*!< The output signal 7 is delayed by the SPI module clock, 0: output - without delayed, 1: output delay for a SPI module clock - cycle at its negative edge. Can be configured in CONF state. */ - __IOM uint32_t SPI_D_DQS_MODE : 1; /*!< The output signal SPI_DQS is delayed by the SPI module clock, - 0: output without delayed, 1: output delay for a SPI module - clock cycle at its negative edge. Can be configured in - CONF state. */ - uint32_t : 23; - } bit; - } SPI_DOUT_MODE; - - union { - __IOM uint32_t reg; /*!< SPI DMA control register */ - - struct { - __IM uint32_t SPI_DMA_OUTFIFO_EMPTY : 1; /*!< Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready - for sending data. 0: DMA TX FIFO is ready for sending data. */ - __IM uint32_t SPI_DMA_INFIFO_FULL : 1; /*!< Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready - for receiving data. 0: DMA RX FIFO is ready for receiving - data. */ - uint32_t : 16; - __IOM uint32_t SPI_DMA_SLV_SEG_TRANS_EN : 1;/*!< Enable dma segment transfer in spi dma half slave mode. 1: enable. - 0: disable. */ - __IOM uint32_t SPI_SLV_RX_SEG_TRANS_CLR_EN : 1;/*!< 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: - spi_dma_infifo_full_vld is cleared by spi_trans_done. */ - __IOM uint32_t SPI_SLV_TX_SEG_TRANS_CLR_EN : 1;/*!< 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. - 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done. */ - __IOM uint32_t SPI_RX_EOF_EN : 1; /*!< 1: spi_dma_inlink_eof is set when the number of dma pushed data - bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] - in spi dma transition. 0: spi_dma_inlink_eof is set by - spi_trans_done in non-seg-trans or spi_dma_seg_trans_done - in seg-trans. */ - uint32_t : 5; - __IOM uint32_t SPI_DMA_RX_ENA : 1; /*!< Set this bit to enable SPI DMA controlled receive data mode. */ - __IOM uint32_t SPI_DMA_TX_ENA : 1; /*!< Set this bit to enable SPI DMA controlled send data mode. */ - __OM uint32_t SPI_RX_AFIFO_RST : 1; /*!< Set this bit to reset RX AFIFO, which is used to receive data - in SPI master and slave mode transfer. */ - __OM uint32_t SPI_BUF_AFIFO_RST : 1; /*!< Set this bit to reset BUF TX AFIFO, which is used send data - out in SPI slave CPU controlled mode transfer and master - mode transfer. */ - __OM uint32_t SPI_DMA_AFIFO_RST : 1; /*!< Set this bit to reset DMA TX AFIFO, which is used to send data - out in SPI slave DMA controlled mode transfer. */ - } bit; - } SPI_DMA_CONF; - - union { - __IOM uint32_t reg; /*!< SPI interrupt enable register */ - - struct { - __IOM uint32_t SPI_DMA_INFIFO_FULL_ERR_INT_ENA : 1;/*!< The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. */ - __IOM uint32_t SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA : 1;/*!< The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. */ - __IOM uint32_t SPI_SLV_EX_QPI_INT_ENA : 1;/*!< The enable bit for SPI slave Ex_QPI interrupt. */ - __IOM uint32_t SPI_SLV_EN_QPI_INT_ENA : 1;/*!< The enable bit for SPI slave En_QPI interrupt. */ - __IOM uint32_t SPI_SLV_CMD7_INT_ENA : 1; /*!< The enable bit for SPI slave CMD7 interrupt. */ - __IOM uint32_t SPI_SLV_CMD8_INT_ENA : 1; /*!< The enable bit for SPI slave CMD8 interrupt. */ - __IOM uint32_t SPI_SLV_CMD9_INT_ENA : 1; /*!< The enable bit for SPI slave CMD9 interrupt. */ - __IOM uint32_t SPI_SLV_CMDA_INT_ENA : 1; /*!< The enable bit for SPI slave CMDA interrupt. */ - __IOM uint32_t SPI_SLV_RD_DMA_DONE_INT_ENA : 1;/*!< The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt. */ - __IOM uint32_t SPI_SLV_WR_DMA_DONE_INT_ENA : 1;/*!< The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt. */ - __IOM uint32_t SPI_SLV_RD_BUF_DONE_INT_ENA : 1;/*!< The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt. */ - __IOM uint32_t SPI_SLV_WR_BUF_DONE_INT_ENA : 1;/*!< The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt. */ - __IOM uint32_t SPI_TRANS_DONE_INT_ENA : 1;/*!< The enable bit for SPI_TRANS_DONE_INT interrupt. */ - __IOM uint32_t SPI_DMA_SEG_TRANS_DONE_INT_ENA : 1;/*!< The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. */ - __IOM uint32_t SPI_SEG_MAGIC_ERR_INT_ENA : 1;/*!< The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt. */ - __IOM uint32_t SPI_SLV_BUF_ADDR_ERR_INT_ENA : 1;/*!< The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. */ - __IOM uint32_t SPI_SLV_CMD_ERR_INT_ENA : 1;/*!< The enable bit for SPI_SLV_CMD_ERR_INT interrupt. */ - __IOM uint32_t SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA : 1;/*!< The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. */ - __IOM uint32_t SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA : 1;/*!< The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. */ - __IOM uint32_t SPI_APP2_INT_ENA : 1; /*!< The enable bit for SPI_APP2_INT interrupt. */ - __IOM uint32_t SPI_APP1_INT_ENA : 1; /*!< The enable bit for SPI_APP1_INT interrupt. */ - uint32_t : 11; - } bit; - } SPI_DMA_INT_ENA; - - union { - __IOM uint32_t reg; /*!< SPI interrupt clear register */ - - struct { - __OM uint32_t SPI_DMA_INFIFO_FULL_ERR_INT_CLR : 1;/*!< The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. */ - __OM uint32_t SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR : 1;/*!< The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. */ - __OM uint32_t SPI_SLV_EX_QPI_INT_CLR : 1;/*!< The clear bit for SPI slave Ex_QPI interrupt. */ - __OM uint32_t SPI_SLV_EN_QPI_INT_CLR : 1;/*!< The clear bit for SPI slave En_QPI interrupt. */ - __OM uint32_t SPI_SLV_CMD7_INT_CLR : 1; /*!< The clear bit for SPI slave CMD7 interrupt. */ - __OM uint32_t SPI_SLV_CMD8_INT_CLR : 1; /*!< The clear bit for SPI slave CMD8 interrupt. */ - __OM uint32_t SPI_SLV_CMD9_INT_CLR : 1; /*!< The clear bit for SPI slave CMD9 interrupt. */ - __OM uint32_t SPI_SLV_CMDA_INT_CLR : 1; /*!< The clear bit for SPI slave CMDA interrupt. */ - __OM uint32_t SPI_SLV_RD_DMA_DONE_INT_CLR : 1;/*!< The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt. */ - __OM uint32_t SPI_SLV_WR_DMA_DONE_INT_CLR : 1;/*!< The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt. */ - __OM uint32_t SPI_SLV_RD_BUF_DONE_INT_CLR : 1;/*!< The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt. */ - __OM uint32_t SPI_SLV_WR_BUF_DONE_INT_CLR : 1;/*!< The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt. */ - __OM uint32_t SPI_TRANS_DONE_INT_CLR : 1;/*!< The clear bit for SPI_TRANS_DONE_INT interrupt. */ - __OM uint32_t SPI_DMA_SEG_TRANS_DONE_INT_CLR : 1;/*!< The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. */ - __OM uint32_t SPI_SEG_MAGIC_ERR_INT_CLR : 1;/*!< The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt. */ - __OM uint32_t SPI_SLV_BUF_ADDR_ERR_INT_CLR : 1;/*!< The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. */ - __OM uint32_t SPI_SLV_CMD_ERR_INT_CLR : 1;/*!< The clear bit for SPI_SLV_CMD_ERR_INT interrupt. */ - __OM uint32_t SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR : 1;/*!< The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. */ - __OM uint32_t SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR : 1;/*!< The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. */ - __OM uint32_t SPI_APP2_INT_CLR : 1; /*!< The clear bit for SPI_APP2_INT interrupt. */ - __OM uint32_t SPI_APP1_INT_CLR : 1; /*!< The clear bit for SPI_APP1_INT interrupt. */ - uint32_t : 11; - } bit; - } SPI_DMA_INT_CLR; - - union { - __IOM uint32_t reg; /*!< SPI interrupt raw register */ - - struct { - __IOM uint32_t SPI_DMA_INFIFO_FULL_ERR_INT_RAW : 1;/*!< 1: The current data rate of DMA Rx is smaller than that of SPI, - which will lose the receive data. 0: Others. */ - __IOM uint32_t SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW : 1;/*!< 1: The current data rate of DMA TX is smaller than that of SPI. - SPI will stop in master mode and send out all 0 in slave - mode. 0: Others. */ - __IOM uint32_t SPI_SLV_EX_QPI_INT_RAW : 1;/*!< The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode - Ex_QPI transmission is ended. 0: Others. */ - __IOM uint32_t SPI_SLV_EN_QPI_INT_RAW : 1;/*!< The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode - En_QPI transmission is ended. 0: Others. */ - __IOM uint32_t SPI_SLV_CMD7_INT_RAW : 1; /*!< The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode - CMD7 transmission is ended. 0: Others. */ - __IOM uint32_t SPI_SLV_CMD8_INT_RAW : 1; /*!< The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode - CMD8 transmission is ended. 0: Others. */ - __IOM uint32_t SPI_SLV_CMD9_INT_RAW : 1; /*!< The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode - CMD9 transmission is ended. 0: Others. */ - __IOM uint32_t SPI_SLV_CMDA_INT_RAW : 1; /*!< The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode - CMDA transmission is ended. 0: Others. */ - __IOM uint32_t SPI_SLV_RD_DMA_DONE_INT_RAW : 1;/*!< The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave - mode Rd_DMA transmission is ended. 0: Others. */ - __IOM uint32_t SPI_SLV_WR_DMA_DONE_INT_RAW : 1;/*!< The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave - mode Wr_DMA transmission is ended. 0: Others. */ - __IOM uint32_t SPI_SLV_RD_BUF_DONE_INT_RAW : 1;/*!< The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave - mode Rd_BUF transmission is ended. 0: Others. */ - __IOM uint32_t SPI_SLV_WR_BUF_DONE_INT_RAW : 1;/*!< The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave - mode Wr_BUF transmission is ended. 0: Others. */ - __IOM uint32_t SPI_TRANS_DONE_INT_RAW : 1;/*!< The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master - mode transmission is ended. 0: others. */ - __IOM uint32_t SPI_DMA_SEG_TRANS_DONE_INT_RAW : 1;/*!< The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi - master DMA full-duplex/half-duplex seg-conf-trans ends - or slave half-duplex seg-trans ends. And data has been - pushed to corresponding memory. 0: seg-conf-trans or seg-trans - is not ended or not occurred. */ - __IOM uint32_t SPI_SEG_MAGIC_ERR_INT_RAW : 1;/*!< The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic - value in CONF buffer is error in the DMA seg-conf-trans. - 0: others. */ - __IOM uint32_t SPI_SLV_BUF_ADDR_ERR_INT_RAW : 1;/*!< The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing - data address of the current SPI slave mode CPU controlled - FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: - Others. */ - __IOM uint32_t SPI_SLV_CMD_ERR_INT_RAW : 1;/*!< The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave - command value in the current SPI slave HD mode transmission - is not supported. 0: Others. */ - __IOM uint32_t SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW : 1;/*!< The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: - There is a RX AFIFO write-full error when SPI inputs data - in master mode. 0: Others. */ - __IOM uint32_t SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW : 1;/*!< The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: - There is a TX BUF AFIFO read-empty error when SPI outputs - data in master mode. 0: Others. */ - __IOM uint32_t SPI_APP2_INT_RAW : 1; /*!< The raw bit for SPI_APP2_INT interrupt. The value is only controlled - by software. */ - __IOM uint32_t SPI_APP1_INT_RAW : 1; /*!< The raw bit for SPI_APP1_INT interrupt. The value is only controlled - by software. */ - uint32_t : 11; - } bit; - } SPI_DMA_INT_RAW; - - union { - __IOM uint32_t reg; /*!< SPI interrupt status register */ - - struct { - __IM uint32_t SPI_DMA_INFIFO_FULL_ERR_INT_ST : 1;/*!< The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. */ - __IM uint32_t SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST : 1;/*!< The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. */ - __IM uint32_t SPI_SLV_EX_QPI_INT_ST : 1; /*!< The status bit for SPI slave Ex_QPI interrupt. */ - __IM uint32_t SPI_SLV_EN_QPI_INT_ST : 1; /*!< The status bit for SPI slave En_QPI interrupt. */ - __IM uint32_t SPI_SLV_CMD7_INT_ST : 1; /*!< The status bit for SPI slave CMD7 interrupt. */ - __IM uint32_t SPI_SLV_CMD8_INT_ST : 1; /*!< The status bit for SPI slave CMD8 interrupt. */ - __IM uint32_t SPI_SLV_CMD9_INT_ST : 1; /*!< The status bit for SPI slave CMD9 interrupt. */ - __IM uint32_t SPI_SLV_CMDA_INT_ST : 1; /*!< The status bit for SPI slave CMDA interrupt. */ - __IM uint32_t SPI_SLV_RD_DMA_DONE_INT_ST : 1;/*!< The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt. */ - __IM uint32_t SPI_SLV_WR_DMA_DONE_INT_ST : 1;/*!< The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt. */ - __IM uint32_t SPI_SLV_RD_BUF_DONE_INT_ST : 1;/*!< The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt. */ - __IM uint32_t SPI_SLV_WR_BUF_DONE_INT_ST : 1;/*!< The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt. */ - __IM uint32_t SPI_TRANS_DONE_INT_ST : 1; /*!< The status bit for SPI_TRANS_DONE_INT interrupt. */ - __IM uint32_t SPI_DMA_SEG_TRANS_DONE_INT_ST : 1;/*!< The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. */ - __IM uint32_t SPI_SEG_MAGIC_ERR_INT_ST : 1;/*!< The status bit for SPI_SEG_MAGIC_ERR_INT interrupt. */ - __IM uint32_t SPI_SLV_BUF_ADDR_ERR_INT_ST : 1;/*!< The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. */ - __IM uint32_t SPI_SLV_CMD_ERR_INT_ST : 1;/*!< The status bit for SPI_SLV_CMD_ERR_INT interrupt. */ - __IM uint32_t SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST : 1;/*!< The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. */ - __IM uint32_t SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST : 1;/*!< The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. */ - __IM uint32_t SPI_APP2_INT_ST : 1; /*!< The status bit for SPI_APP2_INT interrupt. */ - __IM uint32_t SPI_APP1_INT_ST : 1; /*!< The status bit for SPI_APP1_INT interrupt. */ - uint32_t : 11; - } bit; - } SPI_DMA_INT_ST; - - union { - __IOM uint32_t reg; /*!< SPI interrupt software set register */ - - struct { - __OM uint32_t SPI_DMA_INFIFO_FULL_ERR_INT_SET : 1;/*!< The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. */ - __OM uint32_t SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET : 1;/*!< The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. */ - __OM uint32_t SPI_SLV_EX_QPI_INT_SET : 1;/*!< The software set bit for SPI slave Ex_QPI interrupt. */ - __OM uint32_t SPI_SLV_EN_QPI_INT_SET : 1;/*!< The software set bit for SPI slave En_QPI interrupt. */ - __OM uint32_t SPI_SLV_CMD7_INT_SET : 1; /*!< The software set bit for SPI slave CMD7 interrupt. */ - __OM uint32_t SPI_SLV_CMD8_INT_SET : 1; /*!< The software set bit for SPI slave CMD8 interrupt. */ - __OM uint32_t SPI_SLV_CMD9_INT_SET : 1; /*!< The software set bit for SPI slave CMD9 interrupt. */ - __OM uint32_t SPI_SLV_CMDA_INT_SET : 1; /*!< The software set bit for SPI slave CMDA interrupt. */ - __OM uint32_t SPI_SLV_RD_DMA_DONE_INT_SET : 1;/*!< The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt. */ - __OM uint32_t SPI_SLV_WR_DMA_DONE_INT_SET : 1;/*!< The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt. */ - __OM uint32_t SPI_SLV_RD_BUF_DONE_INT_SET : 1;/*!< The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt. */ - __OM uint32_t SPI_SLV_WR_BUF_DONE_INT_SET : 1;/*!< The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt. */ - __OM uint32_t SPI_TRANS_DONE_INT_SET : 1;/*!< The software set bit for SPI_TRANS_DONE_INT interrupt. */ - __OM uint32_t SPI_DMA_SEG_TRANS_DONE_INT_SET : 1;/*!< The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. */ - __OM uint32_t SPI_SEG_MAGIC_ERR_INT_SET : 1;/*!< The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt. */ - __OM uint32_t SPI_SLV_BUF_ADDR_ERR_INT_SET : 1;/*!< The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. */ - __OM uint32_t SPI_SLV_CMD_ERR_INT_SET : 1;/*!< The software set bit for SPI_SLV_CMD_ERR_INT interrupt. */ - __OM uint32_t SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET : 1;/*!< The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. */ - __OM uint32_t SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET : 1;/*!< The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. */ - __OM uint32_t SPI_APP2_INT_SET : 1; /*!< The software set bit for SPI_APP2_INT interrupt. */ - __OM uint32_t SPI_APP1_INT_SET : 1; /*!< The software set bit for SPI_APP1_INT interrupt. */ - uint32_t : 11; - } bit; - } SPI_DMA_INT_SET; - __IM uint32_t RESERVED[20]; - - union { - __IOM uint32_t reg; /*!< SPI CPU-controlled buffer0 */ - - struct { - __IOM uint32_t SPI_BUF0 : 32; /*!< data buffer */ - } bit; - } SPI_W0; - - union { - __IOM uint32_t reg; /*!< SPI CPU-controlled buffer1 */ - - struct { - __IOM uint32_t SPI_BUF1 : 32; /*!< data buffer */ - } bit; - } SPI_W1; - - union { - __IOM uint32_t reg; /*!< SPI CPU-controlled buffer2 */ - - struct { - __IOM uint32_t SPI_BUF2 : 32; /*!< data buffer */ - } bit; - } SPI_W2; - - union { - __IOM uint32_t reg; /*!< SPI CPU-controlled buffer3 */ - - struct { - __IOM uint32_t SPI_BUF3 : 32; /*!< data buffer */ - } bit; - } SPI_W3; - - union { - __IOM uint32_t reg; /*!< SPI CPU-controlled buffer4 */ - - struct { - __IOM uint32_t SPI_BUF4 : 32; /*!< data buffer */ - } bit; - } SPI_W4; - - union { - __IOM uint32_t reg; /*!< SPI CPU-controlled buffer5 */ - - struct { - __IOM uint32_t SPI_BUF5 : 32; /*!< data buffer */ - } bit; - } SPI_W5; - - union { - __IOM uint32_t reg; /*!< SPI CPU-controlled buffer6 */ - - struct { - __IOM uint32_t SPI_BUF6 : 32; /*!< data buffer */ - } bit; - } SPI_W6; - - union { - __IOM uint32_t reg; /*!< SPI CPU-controlled buffer7 */ - - struct { - __IOM uint32_t SPI_BUF7 : 32; /*!< data buffer */ - } bit; - } SPI_W7; - - union { - __IOM uint32_t reg; /*!< SPI CPU-controlled buffer8 */ - - struct { - __IOM uint32_t SPI_BUF8 : 32; /*!< data buffer */ - } bit; - } SPI_W8; - - union { - __IOM uint32_t reg; /*!< SPI CPU-controlled buffer9 */ - - struct { - __IOM uint32_t SPI_BUF9 : 32; /*!< data buffer */ - } bit; - } SPI_W9; - - union { - __IOM uint32_t reg; /*!< SPI CPU-controlled buffer10 */ - - struct { - __IOM uint32_t SPI_BUF10 : 32; /*!< data buffer */ - } bit; - } SPI_W10; - - union { - __IOM uint32_t reg; /*!< SPI CPU-controlled buffer11 */ - - struct { - __IOM uint32_t SPI_BUF11 : 32; /*!< data buffer */ - } bit; - } SPI_W11; - - union { - __IOM uint32_t reg; /*!< SPI CPU-controlled buffer12 */ - - struct { - __IOM uint32_t SPI_BUF12 : 32; /*!< data buffer */ - } bit; - } SPI_W12; - - union { - __IOM uint32_t reg; /*!< SPI CPU-controlled buffer13 */ - - struct { - __IOM uint32_t SPI_BUF13 : 32; /*!< data buffer */ - } bit; - } SPI_W13; - - union { - __IOM uint32_t reg; /*!< SPI CPU-controlled buffer14 */ - - struct { - __IOM uint32_t SPI_BUF14 : 32; /*!< data buffer */ - } bit; - } SPI_W14; - - union { - __IOM uint32_t reg; /*!< SPI CPU-controlled buffer15 */ - - struct { - __IOM uint32_t SPI_BUF15 : 32; /*!< data buffer */ - } bit; - } SPI_W15; - __IM uint32_t RESERVED1[2]; - - union { - __IOM uint32_t reg; /*!< SPI slave control register */ - - struct { - __IOM uint32_t SPI_CLK_MODE : 2; /*!< SPI clock mode bits. 0: SPI clock is off when CS inactive 1: - SPI clock is delayed one cycle after CS inactive 2: SPI - clock is delayed two cycles after CS inactive 3: SPI clock - is alwasy on. Can be configured in CONF state. */ - __IOM uint32_t SPI_CLK_MODE_13 : 1; /*!< {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output - data B[0]/B[7]. 0: support spi clk mode 0 and 2, first - edge output data B[1]/B[6]. */ - __IOM uint32_t SPI_RSCK_DATA_OUT : 1; /*!< It saves half a cycle when tsck is the same as rsck. 1: output - data at rsck posedge 0: output data at tsck posedge */ - uint32_t : 4; - __IOM uint32_t SPI_SLV_RDDMA_BITLEN_EN : 1;/*!< 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave - data length in DMA controlled mode(Rd_DMA). 0: others */ - __IOM uint32_t SPI_SLV_WRDMA_BITLEN_EN : 1;/*!< 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave - data length in DMA controlled mode(Wr_DMA). 0: others */ - __IOM uint32_t SPI_SLV_RDBUF_BITLEN_EN : 1;/*!< 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave - data length in CPU controlled mode(Rd_BUF). 0: others */ - __IOM uint32_t SPI_SLV_WRBUF_BITLEN_EN : 1;/*!< 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave - data length in CPU controlled mode(Wr_BUF). 0: others */ - __IM uint32_t SPI_SLV_LAST_BYTE_STRB : 8;/*!< Represents the effective bit of the last received data byte - in SPI slave FD and HD mode. */ - uint32_t : 2; - __IOM uint32_t SPI_DMA_SEG_MAGIC_VALUE : 4;/*!< The magic value of BM table in master DMA seg-trans. */ - __IOM uint32_t MODE : 1; /*!< Set SPI work mode. 1: slave mode 0: master mode. */ - __OM uint32_t SPI_SOFT_RESET : 1; /*!< Software reset enable, reset the spi clock line cs line and - data lines. Can be configured in CONF state. */ - __IOM uint32_t SPI_USR_CONF : 1; /*!< 1: Enable the DMA CONF phase of current seg-trans operation, - which means seg-trans will start. 0: This is not seg-trans - mode. */ - __IOM uint32_t SPI_MST_FD_WAIT_DMA_TX_DATA : 1;/*!< In master full-duplex mode, 1: GP-SPI will wait DMA TX data - is ready before starting SPI transfer. 0: GP-SPI does not - wait DMA TX data before starting SPI transfer. */ - uint32_t : 2; - } bit; - } SPI_SLAVE; - - union { - __IOM uint32_t reg; /*!< SPI slave control register 1 */ - - struct { - __IOM uint32_t SPI_SLV_DATA_BITLEN : 18; /*!< The transferred data bit length in SPI slave FD and HD mode. */ - __IOM uint32_t SPI_SLV_LAST_COMMAND : 8; /*!< In the slave mode it is the value of command. */ - __IOM uint32_t SPI_SLV_LAST_ADDR : 6; /*!< In the slave mode it is the value of address. */ - } bit; - } SPI_SLAVE1; - - union { - __IOM uint32_t reg; /*!< SPI module clock and register clock control */ - - struct { - __IOM uint32_t SPI_CLK_EN : 1; /*!< Set this bit to enable clk gate */ - __IOM uint32_t SPI_MST_CLK_ACTIVE : 1; /*!< Set this bit to power on the SPI module clock. */ - __IOM uint32_t SPI_MST_CLK_SEL : 1; /*!< This bit is used to select SPI module clock source in master - mode. 1: PLL_CLK_80M. 0: XTAL CLK. */ - uint32_t : 29; - } bit; - } SPI_CLK_GATE; - __IM uint32_t RESERVED2; - - union { - __IOM uint32_t reg; /*!< Version control */ - - struct { - __IOM uint32_t SPI_DATE : 28; /*!< SPI register version. */ - uint32_t : 4; - } bit; - } SPI_DATE; -} SPI2_Type; /*!< Size = 244 (0xf4) */ - - - -/* =========================================================================================================================== */ -/* ================ SPI3 ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief SPI (Serial Peripheral Interface) Controller 3 (SPI3) - */ - -typedef struct { /*!< SPI3 Structure */ - - union { - __IOM uint32_t reg; /*!< Command control register */ - - struct { - uint32_t : 23; - __OM uint32_t SPI_UPDATE : 1; /*!< Set this bit to synchronize SPI registers from APB clock domain - into SPI module clock domain, which is only used in SPI - master mode. */ - __IOM uint32_t SPI_USR : 1; /*!< User define command enable. An operation will be triggered when - the bit is set. The bit will be cleared once the operation - done.1: enable 0: disable. Can not be changed by CONF_buf. */ - uint32_t : 7; - } bit; - } SPI_CMD; - - union { - __IOM uint32_t reg; /*!< Address value register */ - - struct { - __IOM uint32_t SPI_USR_ADDR_VALUE : 32; /*!< Address to slave. Can be configured in CONF state. */ - } bit; - } SPI_ADDR; - - union { - __IOM uint32_t reg; /*!< SPI control register */ - - struct { - uint32_t : 3; - __IOM uint32_t SPI_DUMMY_OUT : 1; /*!< 0: In the dummy phase, the FSPI bus signals are not output. - 1: In the dummy phase, the FSPI bus signals are output. - Can be configured in CONF state. */ - uint32_t : 1; - __IOM uint32_t SPI_FADDR_DUAL : 1; /*!< Apply 2 signals during addr phase 1:enable 0: disable. Can be - configured in CONF state. */ - __IOM uint32_t SPI_FADDR_QUAD : 1; /*!< Apply 4 signals during addr phase 1:enable 0: disable. Can be - configured in CONF state. */ - uint32_t : 1; - __IOM uint32_t SPI_FCMD_DUAL : 1; /*!< Apply 2 signals during command phase 1:enable 0: disable. Can - be configured in CONF state. */ - __IOM uint32_t SPI_FCMD_QUAD : 1; /*!< Apply 4 signals during command phase 1:enable 0: disable. Can - be configured in CONF state. */ - uint32_t : 4; - __IOM uint32_t SPI_FREAD_DUAL : 1; /*!< In the read operations, read-data phase apply 2 signals. 1: - enable 0: disable. Can be configured in CONF state. */ - __IOM uint32_t SPI_FREAD_QUAD : 1; /*!< In the read operations read-data phase apply 4 signals. 1: enable - 0: disable. Can be configured in CONF state. */ - uint32_t : 2; - __IOM uint32_t SPI_Q_POL : 1; /*!< The bit is used to set MISO line polarity, 1: high 0, low. Can - be configured in CONF state. */ - __IOM uint32_t SPI_D_POL : 1; /*!< The bit is used to set MOSI line polarity, 1: high 0, low. Can - be configured in CONF state. */ - __IOM uint32_t SPI_HOLD_POL : 1; /*!< SPI_HOLD output value when SPI is idle. 1: output high, 0: output - low. Can be configured in CONF state. */ - __IOM uint32_t SPI_WP_POL : 1; /*!< Write protect signal output when SPI is idle. 1: output high, - 0: output low. Can be configured in CONF state. */ - uint32_t : 1; - __IOM uint32_t SPI_RD_BIT_ORDER : 2; /*!< In read-data (MISO) phase 1: LSB first 0: MSB first. Can be - configured in CONF state. */ - __IOM uint32_t SPI_WR_BIT_ORDER : 2; /*!< In command address write-data (MOSI) phases 1: LSB firs 0: MSB - first. Can be configured in CONF state. */ - uint32_t : 5; - } bit; - } SPI_CTRL; - - union { - __IOM uint32_t reg; /*!< SPI clock control register */ - - struct { - __IOM uint32_t SPI_CLKCNT_L : 6; /*!< In the master mode it must be equal to spi_clkcnt_N. In the - slave mode it must be 0. Can be configured in CONF state. */ - __IOM uint32_t SPI_CLKCNT_H : 6; /*!< In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In - the slave mode it must be 0. Can be configured in CONF - state. */ - __IOM uint32_t SPI_CLKCNT_N : 6; /*!< In the master mode it is the divider of spi_clk. So spi_clk - frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). - Can be configured in CONF state. */ - __IOM uint32_t SPI_CLKDIV_PRE : 4; /*!< In the master mode it is pre-divider of spi_clk. Can be configured - in CONF state. */ - uint32_t : 9; - __IOM uint32_t SPI_CLK_EQU_SYSCLK : 1; /*!< In the master mode 1: spi_clk is eqaul to system 0: spi_clk - is divided from system clock. Can be configured in CONF - state. */ - } bit; - } SPI_CLOCK; - - union { - __IOM uint32_t reg; /*!< SPI USER control register */ - - struct { - __IOM uint32_t SPI_DOUTDIN : 1; /*!< Set the bit to enable full duplex communication. 1: enable 0: - disable. Can be configured in CONF state. */ - uint32_t : 2; - __IOM uint32_t SPI_QPI_MODE : 1; /*!< Both for master mode and slave mode. 1: spi controller is in - QPI mode. 0: others. Can be configured in CONF state. */ - uint32_t : 1; - __IOM uint32_t SPI_TSCK_I_EDGE : 1; /*!< In the slave mode, this bit can be used to change the polarity - of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i. */ - __IOM uint32_t SPI_CS_HOLD : 1; /*!< spi cs keep low when spi is in done phase. 1: enable 0: disable. - Can be configured in CONF state. */ - __IOM uint32_t SPI_CS_SETUP : 1; /*!< spi cs is enable when spi is in prepare phase. 1: enable 0: - disable. Can be configured in CONF state. */ - __IOM uint32_t SPI_RSCK_I_EDGE : 1; /*!< In the slave mode, this bit can be used to change the polarity - of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i. */ - __IOM uint32_t SPI_CK_OUT_EDGE : 1; /*!< the bit combined with spi_mosi_delay_mode bits to set mosi signal - delay mode. Can be configured in CONF state. */ - uint32_t : 2; - __IOM uint32_t SPI_FWRITE_DUAL : 1; /*!< In the write operations read-data phase apply 2 signals. Can - be configured in CONF state. */ - __IOM uint32_t SPI_FWRITE_QUAD : 1; /*!< In the write operations read-data phase apply 4 signals. Can - be configured in CONF state. */ - uint32_t : 3; - __IOM uint32_t SPI_SIO : 1; /*!< Set the bit to enable 3-line half duplex communication mosi - and miso signals share the same pin. 1: enable 0: disable. - Can be configured in CONF state. */ - uint32_t : 6; - __IOM uint32_t SPI_USR_MISO_HIGHPART : 1; /*!< read-data phase only access to high-part of the buffer spi_w8~spi_w15. - 1: enable 0: disable. Can be configured in CONF state. */ - __IOM uint32_t SPI_USR_MOSI_HIGHPART : 1; /*!< write-data phase only access to high-part of the buffer spi_w8~spi_w15. - 1: enable 0: disable. Can be configured in CONF state. */ - __IOM uint32_t SPI_USR_DUMMY_IDLE : 1; /*!< spi clock is disable in dummy phase when the bit is enable. - Can be configured in CONF state. */ - __IOM uint32_t SPI_USR_MOSI : 1; /*!< This bit enable the write-data phase of an operation. Can be - configured in CONF state. */ - __IOM uint32_t SPI_USR_MISO : 1; /*!< This bit enable the read-data phase of an operation. Can be - configured in CONF state. */ - __IOM uint32_t SPI_USR_DUMMY : 1; /*!< This bit enable the dummy phase of an operation. Can be configured - in CONF state. */ - __IOM uint32_t SPI_USR_ADDR : 1; /*!< This bit enable the address phase of an operation. Can be configured - in CONF state. */ - __IOM uint32_t SPI_USR_COMMAND : 1; /*!< This bit enable the command phase of an operation. Can be configured - in CONF state. */ - } bit; - } SPI_USER; - - union { - __IOM uint32_t reg; /*!< SPI USER control register 1 */ - - struct { - __IOM uint32_t SPI_USR_DUMMY_CYCLELEN : 8;/*!< The length in spi_clk cycles of dummy phase. The register value - shall be (cycle_num-1). Can be configured in CONF state. */ - uint32_t : 8; - __IOM uint32_t SPI_MST_WFULL_ERR_END_EN : 1;/*!< 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid - in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended - when SPI RX AFIFO wfull error is valid in GP-SPI master - FD/HD-mode. */ - __IOM uint32_t SPI_CS_SETUP_TIME : 5; /*!< (cycles+1) of prepare phase by spi clock this bits are combined - with spi_cs_setup bit. Can be configured in CONF state. */ - __IOM uint32_t SPI_CS_HOLD_TIME : 5; /*!< delay cycles of cs pin by spi clock this bits are combined with - spi_cs_hold bit. Can be configured in CONF state. */ - __IOM uint32_t SPI_USR_ADDR_BITLEN : 5; /*!< The length in bits of address phase. The register value shall - be (bit_num-1). Can be configured in CONF state. */ - } bit; - } SPI_USER1; - - union { - __IOM uint32_t reg; /*!< SPI USER control register 2 */ - - struct { - __IOM uint32_t SPI_USR_COMMAND_VALUE : 16;/*!< The value of command. Can be configured in CONF state. */ - uint32_t : 11; - __IOM uint32_t SPI_MST_REMPTY_ERR_END_EN : 1;/*!< 1: SPI transfer is ended when SPI TX AFIFO read empty error - is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is - not ended when SPI TX AFIFO read empty error is valid in - GP-SPI master FD/HD-mode. */ - __IOM uint32_t SPI_USR_COMMAND_BITLEN : 4;/*!< The length in bits of command phase. The register value shall - be (bit_num-1). Can be configured in CONF state. */ - } bit; - } SPI_USER2; - - union { - __IOM uint32_t reg; /*!< SPI data bit length control register */ - - struct { - __IOM uint32_t SPI_MS_DATA_BITLEN : 18; /*!< The value of these bits is the configured SPI transmission data - bit length in master mode DMA controlled transfer or CPU - controlled transfer. The value is also the configured bit - length in slave mode DMA RX controlled transfer. The register - value shall be (bit_num-1). Can be configured in CONF state. */ - uint32_t : 14; - } bit; - } SPI_MS_DLEN; - - union { - __IOM uint32_t reg; /*!< SPI misc register */ - - struct { - __IOM uint32_t SPI_CS0_DIS : 1; /*!< SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to - CS0 pin. Can be configured in CONF state. */ - __IOM uint32_t SPI_CS1_DIS : 1; /*!< SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to - CS1 pin. Can be configured in CONF state. */ - __IOM uint32_t SPI_CS2_DIS : 1; /*!< SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to - CS2 pin. Can be configured in CONF state. */ - uint32_t : 3; - __IOM uint32_t SPI_CK_DIS : 1; /*!< 1: spi clk out disable, 0: spi clk out enable. Can be configured - in CONF state. */ - __IOM uint32_t SPI_MASTER_CS_POL : 3; /*!< In the master mode the bits are the polarity of spi cs line, - the value is equivalent to spi_cs ^ spi_master_cs_pol. - Can be configured in CONF state. */ - uint32_t : 13; - __IOM uint32_t SPI_SLAVE_CS_POL : 1; /*!< spi slave input cs polarity select. 1: inv 0: not change. Can - be configured in CONF state. */ - uint32_t : 5; - __IOM uint32_t SPI_CK_IDLE_EDGE : 1; /*!< 1: spi clk line is high when idle 0: spi clk line is low when - idle. Can be configured in CONF state. */ - __IOM uint32_t SPI_CS_KEEP_ACTIVE : 1; /*!< spi cs line keep low when the bit is set. Can be configured - in CONF state. */ - __IOM uint32_t SPI_QUAD_DIN_PIN_SWAP : 1; /*!< 1: spi quad input swap enable 0: spi quad input swap disable. - Can be configured in CONF state. */ - } bit; - } SPI_MISC; - - union { - __IOM uint32_t reg; /*!< SPI input delay mode configuration */ - - struct { - __IOM uint32_t SPI_DIN0_MODE : 2; /*!< the input signals are delayed by SPI module clock cycles, 0: - input without delayed, 1: input with the posedge of clk_apb,2 - input with the negedge of clk_apb, 3: input with the spi_clk. - Can be configured in CONF state. */ - __IOM uint32_t SPI_DIN1_MODE : 2; /*!< the input signals are delayed by SPI module clock cycles, 0: - input without delayed, 1: input with the posedge of clk_apb,2 - input with the negedge of clk_apb, 3: input with the spi_clk. - Can be configured in CONF state. */ - __IOM uint32_t SPI_DIN2_MODE : 2; /*!< the input signals are delayed by SPI module clock cycles, 0: - input without delayed, 1: input with the posedge of clk_apb,2 - input with the negedge of clk_apb, 3: input with the spi_clk. - Can be configured in CONF state. */ - __IOM uint32_t SPI_DIN3_MODE : 2; /*!< the input signals are delayed by SPI module clock cycles, 0: - input without delayed, 1: input with the posedge of clk_apb,2 - input with the negedge of clk_apb, 3: input with the spi_clk. - Can be configured in CONF state. */ - uint32_t : 8; - __IOM uint32_t SPI_TIMING_HCLK_ACTIVE : 1;/*!< 1:enable hclk in SPI input timing module. 0: disable it. Can - be configured in CONF state. */ - uint32_t : 15; - } bit; - } SPI_DIN_MODE; - - union { - __IOM uint32_t reg; /*!< SPI input delay number configuration */ - - struct { - __IOM uint32_t SPI_DIN0_NUM : 2; /*!< the input signals are delayed by SPI module clock cycles, 0: - delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured - in CONF state. */ - __IOM uint32_t SPI_DIN1_NUM : 2; /*!< the input signals are delayed by SPI module clock cycles, 0: - delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured - in CONF state. */ - __IOM uint32_t SPI_DIN2_NUM : 2; /*!< the input signals are delayed by SPI module clock cycles, 0: - delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured - in CONF state. */ - __IOM uint32_t SPI_DIN3_NUM : 2; /*!< the input signals are delayed by SPI module clock cycles, 0: - delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured - in CONF state. */ - uint32_t : 24; - } bit; - } SPI_DIN_NUM; - - union { - __IOM uint32_t reg; /*!< SPI output delay mode configuration */ - - struct { - __IOM uint32_t SPI_DOUT0_MODE : 1; /*!< The output signal 0 is delayed by the SPI module clock, 0: output - without delayed, 1: output delay for a SPI module clock - cycle at its negative edge. Can be configured in CONF state. */ - __IOM uint32_t SPI_DOUT1_MODE : 1; /*!< The output signal 1 is delayed by the SPI module clock, 0: output - without delayed, 1: output delay for a SPI module clock - cycle at its negative edge. Can be configured in CONF state. */ - __IOM uint32_t SPI_DOUT2_MODE : 1; /*!< The output signal 2 is delayed by the SPI module clock, 0: output - without delayed, 1: output delay for a SPI module clock - cycle at its negative edge. Can be configured in CONF state. */ - __IOM uint32_t SPI_DOUT3_MODE : 1; /*!< The output signal 3 is delayed by the SPI module clock, 0: output - without delayed, 1: output delay for a SPI module clock - cycle at its negative edge. Can be configured in CONF state. */ - uint32_t : 28; - } bit; - } SPI_DOUT_MODE; - - union { - __IOM uint32_t reg; /*!< SPI DMA control register */ - - struct { - __IM uint32_t SPI_DMA_OUTFIFO_EMPTY : 1; /*!< Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready - for sending data. 0: DMA TX FIFO is ready for sending data. */ - __IM uint32_t SPI_DMA_INFIFO_FULL : 1; /*!< Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready - for receiving data. 0: DMA RX FIFO is ready for receiving - data. */ - uint32_t : 16; - __IOM uint32_t SPI_DMA_SLV_SEG_TRANS_EN : 1;/*!< Enable dma segment transfer in spi dma half slave mode. 1: enable. - 0: disable. */ - __IOM uint32_t SPI_SLV_RX_SEG_TRANS_CLR_EN : 1;/*!< 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: - spi_dma_infifo_full_vld is cleared by spi_trans_done. */ - __IOM uint32_t SPI_SLV_TX_SEG_TRANS_CLR_EN : 1;/*!< 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. - 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done. */ - __IOM uint32_t SPI_RX_EOF_EN : 1; /*!< 1: spi_dma_inlink_eof is set when the number of dma pushed data - bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] - in spi dma transition. 0: spi_dma_inlink_eof is set by - spi_trans_done in non-seg-trans or spi_dma_seg_trans_done - in seg-trans. */ - uint32_t : 5; - __IOM uint32_t SPI_DMA_RX_ENA : 1; /*!< Set this bit to enable SPI DMA controlled receive data mode. */ - __IOM uint32_t SPI_DMA_TX_ENA : 1; /*!< Set this bit to enable SPI DMA controlled send data mode. */ - __OM uint32_t SPI_RX_AFIFO_RST : 1; /*!< Set this bit to reset RX AFIFO, which is used to receive data - in SPI master and slave mode transfer. */ - __OM uint32_t SPI_BUF_AFIFO_RST : 1; /*!< Set this bit to reset BUF TX AFIFO, which is used send data - out in SPI slave CPU controlled mode transfer and master - mode transfer. */ - __OM uint32_t SPI_DMA_AFIFO_RST : 1; /*!< Set this bit to reset DMA TX AFIFO, which is used to send data - out in SPI slave DMA controlled mode transfer. */ - } bit; - } SPI_DMA_CONF; - - union { - __IOM uint32_t reg; /*!< SPI interrupt enable register */ - - struct { - __IOM uint32_t SPI_DMA_INFIFO_FULL_ERR_INT_ENA : 1;/*!< The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. */ - __IOM uint32_t SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA : 1;/*!< The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. */ - __IOM uint32_t SPI_SLV_EX_QPI_INT_ENA : 1;/*!< The enable bit for SPI slave Ex_QPI interrupt. */ - __IOM uint32_t SPI_SLV_EN_QPI_INT_ENA : 1;/*!< The enable bit for SPI slave En_QPI interrupt. */ - __IOM uint32_t SPI_SLV_CMD7_INT_ENA : 1; /*!< The enable bit for SPI slave CMD7 interrupt. */ - __IOM uint32_t SPI_SLV_CMD8_INT_ENA : 1; /*!< The enable bit for SPI slave CMD8 interrupt. */ - __IOM uint32_t SPI_SLV_CMD9_INT_ENA : 1; /*!< The enable bit for SPI slave CMD9 interrupt. */ - __IOM uint32_t SPI_SLV_CMDA_INT_ENA : 1; /*!< The enable bit for SPI slave CMDA interrupt. */ - __IOM uint32_t SPI_SLV_RD_DMA_DONE_INT_ENA : 1;/*!< The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt. */ - __IOM uint32_t SPI_SLV_WR_DMA_DONE_INT_ENA : 1;/*!< The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt. */ - __IOM uint32_t SPI_SLV_RD_BUF_DONE_INT_ENA : 1;/*!< The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt. */ - __IOM uint32_t SPI_SLV_WR_BUF_DONE_INT_ENA : 1;/*!< The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt. */ - __IOM uint32_t SPI_TRANS_DONE_INT_ENA : 1;/*!< The enable bit for SPI_TRANS_DONE_INT interrupt. */ - __IOM uint32_t SPI_DMA_SEG_TRANS_DONE_INT_ENA : 1;/*!< The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. */ - uint32_t : 1; - __IOM uint32_t SPI_SLV_BUF_ADDR_ERR_INT_ENA : 1;/*!< The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. */ - __IOM uint32_t SPI_SLV_CMD_ERR_INT_ENA : 1;/*!< The enable bit for SPI_SLV_CMD_ERR_INT interrupt. */ - __IOM uint32_t SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA : 1;/*!< The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. */ - __IOM uint32_t SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA : 1;/*!< The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. */ - __IOM uint32_t SPI_APP2_INT_ENA : 1; /*!< The enable bit for SPI_APP2_INT interrupt. */ - __IOM uint32_t SPI_APP1_INT_ENA : 1; /*!< The enable bit for SPI_APP1_INT interrupt. */ - uint32_t : 11; - } bit; - } SPI_DMA_INT_ENA; - - union { - __IOM uint32_t reg; /*!< SPI interrupt clear register */ - - struct { - __OM uint32_t SPI_DMA_INFIFO_FULL_ERR_INT_CLR : 1;/*!< The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. */ - __OM uint32_t SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR : 1;/*!< The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. */ - __OM uint32_t SPI_SLV_EX_QPI_INT_CLR : 1;/*!< The clear bit for SPI slave Ex_QPI interrupt. */ - __OM uint32_t SPI_SLV_EN_QPI_INT_CLR : 1;/*!< The clear bit for SPI slave En_QPI interrupt. */ - __OM uint32_t SPI_SLV_CMD7_INT_CLR : 1; /*!< The clear bit for SPI slave CMD7 interrupt. */ - __OM uint32_t SPI_SLV_CMD8_INT_CLR : 1; /*!< The clear bit for SPI slave CMD8 interrupt. */ - __OM uint32_t SPI_SLV_CMD9_INT_CLR : 1; /*!< The clear bit for SPI slave CMD9 interrupt. */ - __OM uint32_t SPI_SLV_CMDA_INT_CLR : 1; /*!< The clear bit for SPI slave CMDA interrupt. */ - __OM uint32_t SPI_SLV_RD_DMA_DONE_INT_CLR : 1;/*!< The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt. */ - __OM uint32_t SPI_SLV_WR_DMA_DONE_INT_CLR : 1;/*!< The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt. */ - __OM uint32_t SPI_SLV_RD_BUF_DONE_INT_CLR : 1;/*!< The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt. */ - __OM uint32_t SPI_SLV_WR_BUF_DONE_INT_CLR : 1;/*!< The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt. */ - __OM uint32_t SPI_TRANS_DONE_INT_CLR : 1;/*!< The clear bit for SPI_TRANS_DONE_INT interrupt. */ - __OM uint32_t SPI_DMA_SEG_TRANS_DONE_INT_CLR : 1;/*!< The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. */ - uint32_t : 1; - __OM uint32_t SPI_SLV_BUF_ADDR_ERR_INT_CLR : 1;/*!< The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. */ - __OM uint32_t SPI_SLV_CMD_ERR_INT_CLR : 1;/*!< The clear bit for SPI_SLV_CMD_ERR_INT interrupt. */ - __OM uint32_t SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR : 1;/*!< The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. */ - __OM uint32_t SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR : 1;/*!< The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. */ - __OM uint32_t SPI_APP2_INT_CLR : 1; /*!< The clear bit for SPI_APP2_INT interrupt. */ - __OM uint32_t SPI_APP1_INT_CLR : 1; /*!< The clear bit for SPI_APP1_INT interrupt. */ - uint32_t : 11; - } bit; - } SPI_DMA_INT_CLR; - - union { - __IOM uint32_t reg; /*!< SPI interrupt raw register */ - - struct { - __IOM uint32_t SPI_DMA_INFIFO_FULL_ERR_INT_RAW : 1;/*!< 1: The current data rate of DMA Rx is smaller than that of SPI, - which will lose the receive data. 0: Others. */ - __IOM uint32_t SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW : 1;/*!< 1: The current data rate of DMA TX is smaller than that of SPI. - SPI will stop in master mode and send out all 0 in slave - mode. 0: Others. */ - __IOM uint32_t SPI_SLV_EX_QPI_INT_RAW : 1;/*!< The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode - Ex_QPI transmission is ended. 0: Others. */ - __IOM uint32_t SPI_SLV_EN_QPI_INT_RAW : 1;/*!< The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode - En_QPI transmission is ended. 0: Others. */ - __IOM uint32_t SPI_SLV_CMD7_INT_RAW : 1; /*!< The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode - CMD7 transmission is ended. 0: Others. */ - __IOM uint32_t SPI_SLV_CMD8_INT_RAW : 1; /*!< The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode - CMD8 transmission is ended. 0: Others. */ - __IOM uint32_t SPI_SLV_CMD9_INT_RAW : 1; /*!< The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode - CMD9 transmission is ended. 0: Others. */ - __IOM uint32_t SPI_SLV_CMDA_INT_RAW : 1; /*!< The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode - CMDA transmission is ended. 0: Others. */ - __IOM uint32_t SPI_SLV_RD_DMA_DONE_INT_RAW : 1;/*!< The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave - mode Rd_DMA transmission is ended. 0: Others. */ - __IOM uint32_t SPI_SLV_WR_DMA_DONE_INT_RAW : 1;/*!< The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave - mode Wr_DMA transmission is ended. 0: Others. */ - __IOM uint32_t SPI_SLV_RD_BUF_DONE_INT_RAW : 1;/*!< The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave - mode Rd_BUF transmission is ended. 0: Others. */ - __IOM uint32_t SPI_SLV_WR_BUF_DONE_INT_RAW : 1;/*!< The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave - mode Wr_BUF transmission is ended. 0: Others. */ - __IOM uint32_t SPI_TRANS_DONE_INT_RAW : 1;/*!< The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master - mode transmission is ended. 0: others. */ - __IOM uint32_t SPI_DMA_SEG_TRANS_DONE_INT_RAW : 1;/*!< The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi - master DMA full-duplex/half-duplex seg-conf-trans ends - or slave half-duplex seg-trans ends. And data has been - pushed to corresponding memory. 0: seg-conf-trans or seg-trans - is not ended or not occurred. */ - uint32_t : 1; - __IOM uint32_t SPI_SLV_BUF_ADDR_ERR_INT_RAW : 1;/*!< The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing - data address of the current SPI slave mode CPU controlled - FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: - Others. */ - __IOM uint32_t SPI_SLV_CMD_ERR_INT_RAW : 1;/*!< The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave - command value in the current SPI slave HD mode transmission - is not supported. 0: Others. */ - __IOM uint32_t SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW : 1;/*!< The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: - There is a RX AFIFO write-full error when SPI inputs data - in master mode. 0: Others. */ - __IOM uint32_t SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW : 1;/*!< The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: - There is a TX BUF AFIFO read-empty error when SPI outputs - data in master mode. 0: Others. */ - __IOM uint32_t SPI_APP2_INT_RAW : 1; /*!< The raw bit for SPI_APP2_INT interrupt. The value is only controlled - by software. */ - __IOM uint32_t SPI_APP1_INT_RAW : 1; /*!< The raw bit for SPI_APP1_INT interrupt. The value is only controlled - by software. */ - uint32_t : 11; - } bit; - } SPI_DMA_INT_RAW; - - union { - __IOM uint32_t reg; /*!< SPI interrupt status register */ - - struct { - __IM uint32_t SPI_DMA_INFIFO_FULL_ERR_INT_ST : 1;/*!< The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. */ - __IM uint32_t SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST : 1;/*!< The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. */ - __IM uint32_t SPI_SLV_EX_QPI_INT_ST : 1; /*!< The status bit for SPI slave Ex_QPI interrupt. */ - __IM uint32_t SPI_SLV_EN_QPI_INT_ST : 1; /*!< The status bit for SPI slave En_QPI interrupt. */ - __IM uint32_t SPI_SLV_CMD7_INT_ST : 1; /*!< The status bit for SPI slave CMD7 interrupt. */ - __IM uint32_t SPI_SLV_CMD8_INT_ST : 1; /*!< The status bit for SPI slave CMD8 interrupt. */ - __IM uint32_t SPI_SLV_CMD9_INT_ST : 1; /*!< The status bit for SPI slave CMD9 interrupt. */ - __IM uint32_t SPI_SLV_CMDA_INT_ST : 1; /*!< The status bit for SPI slave CMDA interrupt. */ - __IM uint32_t SPI_SLV_RD_DMA_DONE_INT_ST : 1;/*!< The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt. */ - __IM uint32_t SPI_SLV_WR_DMA_DONE_INT_ST : 1;/*!< The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt. */ - __IM uint32_t SPI_SLV_RD_BUF_DONE_INT_ST : 1;/*!< The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt. */ - __IM uint32_t SPI_SLV_WR_BUF_DONE_INT_ST : 1;/*!< The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt. */ - __IM uint32_t SPI_TRANS_DONE_INT_ST : 1; /*!< The status bit for SPI_TRANS_DONE_INT interrupt. */ - __IM uint32_t SPI_DMA_SEG_TRANS_DONE_INT_ST : 1;/*!< The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. */ - uint32_t : 1; - __IM uint32_t SPI_SLV_BUF_ADDR_ERR_INT_ST : 1;/*!< The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. */ - __IM uint32_t SPI_SLV_CMD_ERR_INT_ST : 1;/*!< The status bit for SPI_SLV_CMD_ERR_INT interrupt. */ - __IM uint32_t SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST : 1;/*!< The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. */ - __IM uint32_t SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST : 1;/*!< The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. */ - __IM uint32_t SPI_APP2_INT_ST : 1; /*!< The status bit for SPI_APP2_INT interrupt. */ - __IM uint32_t SPI_APP1_INT_ST : 1; /*!< The status bit for SPI_APP1_INT interrupt. */ - uint32_t : 11; - } bit; - } SPI_DMA_INT_ST; - - union { - __IOM uint32_t reg; /*!< SPI interrupt software set register */ - - struct { - __OM uint32_t SPI_DMA_INFIFO_FULL_ERR_INT_SET : 1;/*!< The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. */ - __OM uint32_t SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET : 1;/*!< The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. */ - __OM uint32_t SPI_SLV_EX_QPI_INT_SET : 1;/*!< The software set bit for SPI slave Ex_QPI interrupt. */ - __OM uint32_t SPI_SLV_EN_QPI_INT_SET : 1;/*!< The software set bit for SPI slave En_QPI interrupt. */ - __OM uint32_t SPI_SLV_CMD7_INT_SET : 1; /*!< The software set bit for SPI slave CMD7 interrupt. */ - __OM uint32_t SPI_SLV_CMD8_INT_SET : 1; /*!< The software set bit for SPI slave CMD8 interrupt. */ - __OM uint32_t SPI_SLV_CMD9_INT_SET : 1; /*!< The software set bit for SPI slave CMD9 interrupt. */ - __OM uint32_t SPI_SLV_CMDA_INT_SET : 1; /*!< The software set bit for SPI slave CMDA interrupt. */ - __OM uint32_t SPI_SLV_RD_DMA_DONE_INT_SET : 1;/*!< The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt. */ - __OM uint32_t SPI_SLV_WR_DMA_DONE_INT_SET : 1;/*!< The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt. */ - __OM uint32_t SPI_SLV_RD_BUF_DONE_INT_SET : 1;/*!< The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt. */ - __OM uint32_t SPI_SLV_WR_BUF_DONE_INT_SET : 1;/*!< The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt. */ - __OM uint32_t SPI_TRANS_DONE_INT_SET : 1;/*!< The software set bit for SPI_TRANS_DONE_INT interrupt. */ - __OM uint32_t SPI_DMA_SEG_TRANS_DONE_INT_SET : 1;/*!< The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. */ - uint32_t : 1; - __OM uint32_t SPI_SLV_BUF_ADDR_ERR_INT_SET : 1;/*!< The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. */ - __OM uint32_t SPI_SLV_CMD_ERR_INT_SET : 1;/*!< The software set bit for SPI_SLV_CMD_ERR_INT interrupt. */ - __OM uint32_t SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET : 1;/*!< The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. */ - __OM uint32_t SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET : 1;/*!< The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. */ - __OM uint32_t SPI_APP2_INT_SET : 1; /*!< The software set bit for SPI_APP2_INT interrupt. */ - __OM uint32_t SPI_APP1_INT_SET : 1; /*!< The software set bit for SPI_APP1_INT interrupt. */ - uint32_t : 11; - } bit; - } SPI_DMA_INT_SET; - __IM uint32_t RESERVED[20]; - - union { - __IOM uint32_t reg; /*!< SPI CPU-controlled buffer0 */ - - struct { - __IOM uint32_t SPI_BUF0 : 32; /*!< data buffer */ - } bit; - } SPI_W0; - - union { - __IOM uint32_t reg; /*!< SPI CPU-controlled buffer1 */ - - struct { - __IOM uint32_t SPI_BUF1 : 32; /*!< data buffer */ - } bit; - } SPI_W1; - - union { - __IOM uint32_t reg; /*!< SPI CPU-controlled buffer2 */ - - struct { - __IOM uint32_t SPI_BUF2 : 32; /*!< data buffer */ - } bit; - } SPI_W2; - - union { - __IOM uint32_t reg; /*!< SPI CPU-controlled buffer3 */ - - struct { - __IOM uint32_t SPI_BUF3 : 32; /*!< data buffer */ - } bit; - } SPI_W3; - - union { - __IOM uint32_t reg; /*!< SPI CPU-controlled buffer4 */ - - struct { - __IOM uint32_t SPI_BUF4 : 32; /*!< data buffer */ - } bit; - } SPI_W4; - - union { - __IOM uint32_t reg; /*!< SPI CPU-controlled buffer5 */ - - struct { - __IOM uint32_t SPI_BUF5 : 32; /*!< data buffer */ - } bit; - } SPI_W5; - - union { - __IOM uint32_t reg; /*!< SPI CPU-controlled buffer6 */ - - struct { - __IOM uint32_t SPI_BUF6 : 32; /*!< data buffer */ - } bit; - } SPI_W6; - - union { - __IOM uint32_t reg; /*!< SPI CPU-controlled buffer7 */ - - struct { - __IOM uint32_t SPI_BUF7 : 32; /*!< data buffer */ - } bit; - } SPI_W7; - - union { - __IOM uint32_t reg; /*!< SPI CPU-controlled buffer8 */ - - struct { - __IOM uint32_t SPI_BUF8 : 32; /*!< data buffer */ - } bit; - } SPI_W8; - - union { - __IOM uint32_t reg; /*!< SPI CPU-controlled buffer9 */ - - struct { - __IOM uint32_t SPI_BUF9 : 32; /*!< data buffer */ - } bit; - } SPI_W9; - - union { - __IOM uint32_t reg; /*!< SPI CPU-controlled buffer10 */ - - struct { - __IOM uint32_t SPI_BUF10 : 32; /*!< data buffer */ - } bit; - } SPI_W10; - - union { - __IOM uint32_t reg; /*!< SPI CPU-controlled buffer11 */ - - struct { - __IOM uint32_t SPI_BUF11 : 32; /*!< data buffer */ - } bit; - } SPI_W11; - - union { - __IOM uint32_t reg; /*!< SPI CPU-controlled buffer12 */ - - struct { - __IOM uint32_t SPI_BUF12 : 32; /*!< data buffer */ - } bit; - } SPI_W12; - - union { - __IOM uint32_t reg; /*!< SPI CPU-controlled buffer13 */ - - struct { - __IOM uint32_t SPI_BUF13 : 32; /*!< data buffer */ - } bit; - } SPI_W13; - - union { - __IOM uint32_t reg; /*!< SPI CPU-controlled buffer14 */ - - struct { - __IOM uint32_t SPI_BUF14 : 32; /*!< data buffer */ - } bit; - } SPI_W14; - - union { - __IOM uint32_t reg; /*!< SPI CPU-controlled buffer15 */ - - struct { - __IOM uint32_t SPI_BUF15 : 32; /*!< data buffer */ - } bit; - } SPI_W15; - __IM uint32_t RESERVED1[2]; - - union { - __IOM uint32_t reg; /*!< SPI slave control register */ - - struct { - __IOM uint32_t SPI_CLK_MODE : 2; /*!< SPI clock mode bits. 0: SPI clock is off when CS inactive 1: - SPI clock is delayed one cycle after CS inactive 2: SPI - clock is delayed two cycles after CS inactive 3: SPI clock - is alwasy on. Can be configured in CONF state. */ - __IOM uint32_t SPI_CLK_MODE_13 : 1; /*!< {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output - data B[0]/B[7]. 0: support spi clk mode 0 and 2, first - edge output data B[1]/B[6]. */ - __IOM uint32_t SPI_RSCK_DATA_OUT : 1; /*!< It saves half a cycle when tsck is the same as rsck. 1: output - data at rsck posedge 0: output data at tsck posedge */ - uint32_t : 4; - __IOM uint32_t SPI_SLV_RDDMA_BITLEN_EN : 1;/*!< 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave - data length in DMA controlled mode(Rd_DMA). 0: others */ - __IOM uint32_t SPI_SLV_WRDMA_BITLEN_EN : 1;/*!< 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave - data length in DMA controlled mode(Wr_DMA). 0: others */ - __IOM uint32_t SPI_SLV_RDBUF_BITLEN_EN : 1;/*!< 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave - data length in CPU controlled mode(Rd_BUF). 0: others */ - __IOM uint32_t SPI_SLV_WRBUF_BITLEN_EN : 1;/*!< 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave - data length in CPU controlled mode(Wr_BUF). 0: others */ - __IM uint32_t SPI_SLV_LAST_BYTE_STRB : 8;/*!< Represents the effective bit of the last received data byte - in SPI slave FD and HD mode. */ - uint32_t : 6; - __IOM uint32_t MODE : 1; /*!< Set SPI work mode. 1: slave mode 0: master mode. */ - __OM uint32_t SPI_SOFT_RESET : 1; /*!< Software reset enable, reset the spi clock line cs line and - data lines. Can be configured in CONF state. */ - uint32_t : 1; - __IOM uint32_t SPI_MST_FD_WAIT_DMA_TX_DATA : 1;/*!< In master full-duplex mode, 1: GP-SPI will wait DMA TX data - is ready before starting SPI transfer. 0: GP-SPI does not - wait DMA TX data before starting SPI transfer. */ - uint32_t : 2; - } bit; - } SPI_SLAVE; - - union { - __IOM uint32_t reg; /*!< SPI slave control register 1 */ - - struct { - __IOM uint32_t SPI_SLV_DATA_BITLEN : 18; /*!< The transferred data bit length in SPI slave FD and HD mode. */ - __IOM uint32_t SPI_SLV_LAST_COMMAND : 8; /*!< In the slave mode it is the value of command. */ - __IOM uint32_t SPI_SLV_LAST_ADDR : 6; /*!< In the slave mode it is the value of address. */ - } bit; - } SPI_SLAVE1; - - union { - __IOM uint32_t reg; /*!< SPI module clock and register clock control */ - - struct { - __IOM uint32_t SPI_CLK_EN : 1; /*!< Set this bit to enable clk gate */ - __IOM uint32_t SPI_MST_CLK_ACTIVE : 1; /*!< Set this bit to power on the SPI module clock. */ - __IOM uint32_t SPI_MST_CLK_SEL : 1; /*!< This bit is used to select SPI module clock source in master - mode. 1: PLL_CLK_80M. 0: XTAL CLK. */ - uint32_t : 29; - } bit; - } SPI_CLK_GATE; - __IM uint32_t RESERVED2; - - union { - __IOM uint32_t reg; /*!< Version control */ - - struct { - __IOM uint32_t SPI_DATE : 28; /*!< SPI register version. */ - uint32_t : 4; - } bit; - } SPI_DATE; -} SPI3_Type; /*!< Size = 244 (0xf4) */ - - - -/* =========================================================================================================================== */ -/* ================ SYSTIMER ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief System Timer (SYSTIMER) - */ - -typedef struct { /*!< SYSTIMER Structure */ - - union { - __IOM uint32_t reg; /*!< Configure system timer clock */ - - struct { - __IOM uint32_t SYSTIMER_CLK_FO : 1; /*!< systimer clock force on */ - __IOM uint32_t ETM_EN : 1; /*!< enable systimer's etm task and event */ - uint32_t : 20; - __IOM uint32_t TARGET2_WORK_EN : 1; /*!< target2 work enable */ - __IOM uint32_t TARGET1_WORK_EN : 1; /*!< target1 work enable */ - __IOM uint32_t TARGET0_WORK_EN : 1; /*!< target0 work enable */ - __IOM uint32_t TIMER_UNIT1_CORE1_STALL_EN : 1;/*!< If timer unit1 is stalled when core1 stalled */ - __IOM uint32_t TIMER_UNIT1_CORE0_STALL_EN : 1;/*!< If timer unit1 is stalled when core0 stalled */ - __IOM uint32_t TIMER_UNIT0_CORE1_STALL_EN : 1;/*!< If timer unit0 is stalled when core1 stalled */ - __IOM uint32_t TIMER_UNIT0_CORE0_STALL_EN : 1;/*!< If timer unit0 is stalled when core0 stalled */ - __IOM uint32_t TIMER_UNIT1_WORK_EN : 1; /*!< timer unit1 work enable */ - __IOM uint32_t TIMER_UNIT0_WORK_EN : 1; /*!< timer unit0 work enable */ - __IOM uint32_t CLK_EN : 1; /*!< register file clk gating */ - } bit; - } CONF; - - union { - __IOM uint32_t reg; /*!< system timer unit0 value update register */ - - struct { - uint32_t : 29; - __IM uint32_t TIMER_UNIT0_VALUE_VALID : 1;/*!< timer value is sync and valid */ - __OM uint32_t TIMER_UNIT0_UPDATE : 1; /*!< update timer_unit0 */ - uint32_t : 1; - } bit; - } UNIT0_OP; - - union { - __IOM uint32_t reg; /*!< system timer unit1 value update register */ - - struct { - uint32_t : 29; - __IM uint32_t TIMER_UNIT1_VALUE_VALID : 1;/*!< timer value is sync and valid */ - __OM uint32_t TIMER_UNIT1_UPDATE : 1; /*!< update timer unit1 */ - uint32_t : 1; - } bit; - } UNIT1_OP; - - union { - __IOM uint32_t reg; /*!< system timer unit0 value high load register */ - - struct { - __IOM uint32_t TIMER_UNIT0_LOAD_HI : 20; /*!< timer unit0 load high 20 bits */ - uint32_t : 12; - } bit; - } UNIT0_LOAD_HI; - - union { - __IOM uint32_t reg; /*!< system timer unit0 value low load register */ - - struct { - __IOM uint32_t TIMER_UNIT0_LOAD_LO : 32; /*!< timer unit0 load low 32 bits */ - } bit; - } UNIT0_LOAD_LO; - - union { - __IOM uint32_t reg; /*!< system timer unit1 value high load register */ - - struct { - __IOM uint32_t TIMER_UNIT1_LOAD_HI : 20; /*!< timer unit1 load high 20 bits */ - uint32_t : 12; - } bit; - } UNIT1_LOAD_HI; - - union { - __IOM uint32_t reg; /*!< system timer unit1 value low load register */ - - struct { - __IOM uint32_t TIMER_UNIT1_LOAD_LO : 32; /*!< timer unit1 load low 32 bits */ - } bit; - } UNIT1_LOAD_LO; - - union { - __IOM uint32_t reg; /*!< system timer comp0 value high register */ - - struct { - __IOM uint32_t TIMER_TARGET0_HI : 20; /*!< timer taget0 high 20 bits */ - uint32_t : 12; - } bit; - } TARGET0_HI; - - union { - __IOM uint32_t reg; /*!< system timer comp0 value low register */ - - struct { - __IOM uint32_t TIMER_TARGET0_LO : 32; /*!< timer taget0 low 32 bits */ - } bit; - } TARGET0_LO; - - union { - __IOM uint32_t reg; /*!< system timer comp1 value high register */ - - struct { - __IOM uint32_t TIMER_TARGET1_HI : 20; /*!< timer taget1 high 20 bits */ - uint32_t : 12; - } bit; - } TARGET1_HI; - - union { - __IOM uint32_t reg; /*!< system timer comp1 value low register */ - - struct { - __IOM uint32_t TIMER_TARGET1_LO : 32; /*!< timer taget1 low 32 bits */ - } bit; - } TARGET1_LO; - - union { - __IOM uint32_t reg; /*!< system timer comp2 value high register */ - - struct { - __IOM uint32_t TIMER_TARGET2_HI : 20; /*!< timer taget2 high 20 bits */ - uint32_t : 12; - } bit; - } TARGET2_HI; - - union { - __IOM uint32_t reg; /*!< system timer comp2 value low register */ - - struct { - __IOM uint32_t TIMER_TARGET2_LO : 32; /*!< timer taget2 low 32 bits */ - } bit; - } TARGET2_LO; - - union { - __IOM uint32_t reg; /*!< system timer comp0 target mode register */ - - struct { - __IOM uint32_t TARGET0_PERIOD : 26; /*!< target0 period */ - uint32_t : 4; - __IOM uint32_t TARGET0_PERIOD_MODE : 1; /*!< Set target0 to period mode */ - __IOM uint32_t TARGET0_TIMER_UNIT_SEL : 1;/*!< select which unit to compare */ - } bit; - } TARGET0_CONF; - - union { - __IOM uint32_t reg; /*!< system timer comp1 target mode register */ - - struct { - __IOM uint32_t TARGET1_PERIOD : 26; /*!< target1 period */ - uint32_t : 4; - __IOM uint32_t TARGET1_PERIOD_MODE : 1; /*!< Set target1 to period mode */ - __IOM uint32_t TARGET1_TIMER_UNIT_SEL : 1;/*!< select which unit to compare */ - } bit; - } TARGET1_CONF; - - union { - __IOM uint32_t reg; /*!< system timer comp2 target mode register */ - - struct { - __IOM uint32_t TARGET2_PERIOD : 26; /*!< target2 period */ - uint32_t : 4; - __IOM uint32_t TARGET2_PERIOD_MODE : 1; /*!< Set target2 to period mode */ - __IOM uint32_t TARGET2_TIMER_UNIT_SEL : 1;/*!< select which unit to compare */ - } bit; - } TARGET2_CONF; - - union { - __IOM uint32_t reg; /*!< system timer unit0 value high register */ - - struct { - __IM uint32_t TIMER_UNIT0_VALUE_HI : 20; /*!< timer read value high 20bits */ - uint32_t : 12; - } bit; - } UNIT0_VALUE_HI; - - union { - __IOM uint32_t reg; /*!< system timer unit0 value low register */ - - struct { - __IM uint32_t TIMER_UNIT0_VALUE_LO : 32; /*!< timer read value low 32bits */ - } bit; - } UNIT0_VALUE_LO; - - union { - __IOM uint32_t reg; /*!< system timer unit1 value high register */ - - struct { - __IM uint32_t TIMER_UNIT1_VALUE_HI : 20; /*!< timer read value high 20bits */ - uint32_t : 12; - } bit; - } UNIT1_VALUE_HI; - - union { - __IOM uint32_t reg; /*!< system timer unit1 value low register */ - - struct { - __IM uint32_t TIMER_UNIT1_VALUE_LO : 32; /*!< timer read value low 32bits */ - } bit; - } UNIT1_VALUE_LO; - - union { - __IOM uint32_t reg; /*!< system timer comp0 conf sync register */ - - struct { - __OM uint32_t TIMER_COMP0_LOAD : 1; /*!< timer comp0 sync enable signal */ - uint32_t : 31; - } bit; - } COMP0_LOAD; - - union { - __IOM uint32_t reg; /*!< system timer comp1 conf sync register */ - - struct { - __OM uint32_t TIMER_COMP1_LOAD : 1; /*!< timer comp1 sync enable signal */ - uint32_t : 31; - } bit; - } COMP1_LOAD; - - union { - __IOM uint32_t reg; /*!< system timer comp2 conf sync register */ - - struct { - __OM uint32_t TIMER_COMP2_LOAD : 1; /*!< timer comp2 sync enable signal */ - uint32_t : 31; - } bit; - } COMP2_LOAD; - - union { - __IOM uint32_t reg; /*!< system timer unit0 conf sync register */ - - struct { - __OM uint32_t TIMER_UNIT0_LOAD : 1; /*!< timer unit0 sync enable signal */ - uint32_t : 31; - } bit; - } UNIT0_LOAD; - - union { - __IOM uint32_t reg; /*!< system timer unit1 conf sync register */ - - struct { - __OM uint32_t TIMER_UNIT1_LOAD : 1; /*!< timer unit1 sync enable signal */ - uint32_t : 31; - } bit; - } UNIT1_LOAD; - - union { - __IOM uint32_t reg; /*!< systimer interrupt enable register */ - - struct { - __IOM uint32_t TARGET0_INT_ENA : 1; /*!< interupt0 enable */ - __IOM uint32_t TARGET1_INT_ENA : 1; /*!< interupt1 enable */ - __IOM uint32_t TARGET2_INT_ENA : 1; /*!< interupt2 enable */ - uint32_t : 29; - } bit; - } INT_ENA; - - union { - __IOM uint32_t reg; /*!< systimer interrupt raw register */ - - struct { - __IOM uint32_t TARGET0_INT_RAW : 1; /*!< interupt0 raw */ - __IOM uint32_t TARGET1_INT_RAW : 1; /*!< interupt1 raw */ - __IOM uint32_t TARGET2_INT_RAW : 1; /*!< interupt2 raw */ - uint32_t : 29; - } bit; - } INT_RAW; - - union { - __IOM uint32_t reg; /*!< systimer interrupt clear register */ - - struct { - __OM uint32_t TARGET0_INT_CLR : 1; /*!< interupt0 clear */ - __OM uint32_t TARGET1_INT_CLR : 1; /*!< interupt1 clear */ - __OM uint32_t TARGET2_INT_CLR : 1; /*!< interupt2 clear */ - uint32_t : 29; - } bit; - } INT_CLR; - - union { - __IOM uint32_t reg; /*!< systimer interrupt status register */ - - struct { - __IM uint32_t TARGET0_INT_ST : 1; /*!< interupt0 status */ - __IM uint32_t TARGET1_INT_ST : 1; /*!< interupt1 status */ - __IM uint32_t TARGET2_INT_ST : 1; /*!< interupt2 status */ - uint32_t : 29; - } bit; - } INT_ST; - - union { - __IOM uint32_t reg; /*!< system timer comp0 actual target value low register */ - - struct { - __IM uint32_t TARGET0_LO_RO : 32; /*!< actual target value value low 32bits */ - } bit; - } REAL_TARGET0_LO; - - union { - __IOM uint32_t reg; /*!< system timer comp0 actual target value high register */ - - struct { - __IM uint32_t TARGET0_HI_RO : 20; /*!< actual target value value high 20bits */ - uint32_t : 12; - } bit; - } REAL_TARGET0_HI; - - union { - __IOM uint32_t reg; /*!< system timer comp1 actual target value low register */ - - struct { - __IM uint32_t TARGET1_LO_RO : 32; /*!< actual target value value low 32bits */ - } bit; - } REAL_TARGET1_LO; - - union { - __IOM uint32_t reg; /*!< system timer comp1 actual target value high register */ - - struct { - __IM uint32_t TARGET1_HI_RO : 20; /*!< actual target value value high 20bits */ - uint32_t : 12; - } bit; - } REAL_TARGET1_HI; - - union { - __IOM uint32_t reg; /*!< system timer comp2 actual target value low register */ - - struct { - __IM uint32_t TARGET2_LO_RO : 32; /*!< actual target value value low 32bits */ - } bit; - } REAL_TARGET2_LO; - - union { - __IOM uint32_t reg; /*!< system timer comp2 actual target value high register */ - - struct { - __IM uint32_t TARGET2_HI_RO : 20; /*!< actual target value value high 20bits */ - uint32_t : 12; - } bit; - } REAL_TARGET2_HI; - __IM uint32_t RESERVED[28]; - - union { - __IOM uint32_t reg; /*!< system timer version control register */ - - struct { - __IOM uint32_t DATE : 32; /*!< systimer register version */ - } bit; - } DATE; -} SYSTIMER_Type; /*!< Size = 256 (0x100) */ - - - -/* =========================================================================================================================== */ -/* ================ TIMG0 ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Timer Group 0 (TIMG0) - */ - -typedef struct { /*!< TIMG0 Structure */ - __IM uint32_t RESERVED[18]; - - union { - __IOM uint32_t reg; /*!< Watchdog timer configuration register */ - - struct { - uint32_t : 12; - __IOM uint32_t WDT_APPCPU_RESET_EN : 1; /*!< WDT reset CPU enable. */ - __IOM uint32_t WDT_PROCPU_RESET_EN : 1; /*!< WDT reset CPU enable. */ - __IOM uint32_t WDT_FLASHBOOT_MOD_EN : 1; /*!< When set, Flash boot protection is enabled. */ - __IOM uint32_t WDT_SYS_RESET_LENGTH : 3; /*!< System reset signal length selection. 0: 100 ns, 1: 200 ns,2: - 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: - 3.2 us. */ - __IOM uint32_t WDT_CPU_RESET_LENGTH : 3; /*!< CPU reset signal length selection. 0: 100 ns, 1: 200 ns,2: 300 - ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 - us. */ - __IOM uint32_t WDT_USE_XTAL : 1; /*!< choose WDT clock:0-apb_clk, 1-xtal_clk. */ - __OM uint32_t WDT_CONF_UPDATE_EN : 1; /*!< update the WDT configuration registers */ - __IOM uint32_t WDT_STG3 : 2; /*!< Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: - reset system. */ - __IOM uint32_t WDT_STG2 : 2; /*!< Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: - reset system. */ - __IOM uint32_t WDT_STG1 : 2; /*!< Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: - reset system. */ - __IOM uint32_t WDT_STG0 : 2; /*!< Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: - reset system. */ - __IOM uint32_t WDT_EN : 1; /*!< When set, MWDT is enabled. */ - } bit; - } WDTCONFIG0; - - union { - __IOM uint32_t reg; /*!< Watchdog timer prescaler register */ - - struct { - __OM uint32_t WDT_DIVCNT_RST : 1; /*!< When set, WDT 's clock divider counter will be reset. */ - uint32_t : 15; - __IOM uint32_t WDT_CLK_PRESCALE : 16; /*!< MWDT clock prescaler value. MWDT clock period = 12.5 ns *TIMG_WDT_CLK_PRESCALE - */ - } bit; - } WDTCONFIG1; - - union { - __IOM uint32_t reg; /*!< Watchdog timer stage 0 timeout value */ - - struct { - __IOM uint32_t WDT_STG0_HOLD : 32; /*!< Stage 0 timeout value, in MWDT clock cycles. */ - } bit; - } WDTCONFIG2; - - union { - __IOM uint32_t reg; /*!< Watchdog timer stage 1 timeout value */ - - struct { - __IOM uint32_t WDT_STG1_HOLD : 32; /*!< Stage 1 timeout value, in MWDT clock cycles. */ - } bit; - } WDTCONFIG3; - - union { - __IOM uint32_t reg; /*!< Watchdog timer stage 2 timeout value */ - - struct { - __IOM uint32_t WDT_STG2_HOLD : 32; /*!< Stage 2 timeout value, in MWDT clock cycles. */ - } bit; - } WDTCONFIG4; - - union { - __IOM uint32_t reg; /*!< Watchdog timer stage 3 timeout value */ - - struct { - __IOM uint32_t WDT_STG3_HOLD : 32; /*!< Stage 3 timeout value, in MWDT clock cycles. */ - } bit; - } WDTCONFIG5; - - union { - __IOM uint32_t reg; /*!< Write to feed the watchdog timer */ - - struct { - __OM uint32_t WDT_FEED : 32; /*!< Write any value to feed the MWDT. (WO) */ - } bit; - } WDTFEED; - - union { - __IOM uint32_t reg; /*!< Watchdog write protect register */ - - struct { - __IOM uint32_t WDT_WKEY : 32; /*!< If the register contains a different value than its reset value, - writeprotection is enabled. */ - } bit; - } WDTWPROTECT; - - union { - __IOM uint32_t reg; /*!< RTC calibration configure register */ - - struct { - uint32_t : 12; - __IOM uint32_t RTC_CALI_START_CYCLING : 1;/*!< 0: one-shot frequency calculation,1: periodic frequency calculation, */ - __IOM uint32_t RTC_CALI_CLK_SEL : 2; /*!< 0:rtc slow clock. 1:clk_8m, 2:xtal_32k. */ - __IM uint32_t RTC_CALI_RDY : 1; /*!< indicate one-shot frequency calculation is done. */ - __IOM uint32_t RTC_CALI_MAX : 15; /*!< Configure the time to calculate RTC slow clock's frequency. */ - __IOM uint32_t RTC_CALI_START : 1; /*!< Set this bit to start one-shot frequency calculation. */ - } bit; - } RTCCALICFG; - - union { - __IOM uint32_t reg; /*!< RTC calibration configure1 register */ - - struct { - __IM uint32_t RTC_CALI_CYCLING_DATA_VLD : 1;/*!< indicate periodic frequency calculation is done. */ - uint32_t : 6; - __IM uint32_t RTC_CALI_VALUE : 25; /*!< When one-shot or periodic frequency calculation is done, read - this value to calculate RTC slow clock's frequency. */ - } bit; - } RTCCALICFG1; - - union { - __IOM uint32_t reg; /*!< Interrupt enable bits */ - - struct { - __IOM uint32_t T0_INT_ENA : 1; /*!< The interrupt enable bit for the TIMG_T0_INT interrupt. */ - __IOM uint32_t T1_INT_ENA : 1; /*!< The interrupt enable bit for the TIMG_T1_INT interrupt. */ - __IOM uint32_t WDT_INT_ENA : 1; /*!< The interrupt enable bit for the TIMG_WDT_INT interrupt. */ - uint32_t : 29; - } bit; - } INT_ENA_TIMERS; - - union { - __IOM uint32_t reg; /*!< Raw interrupt status */ - - struct { - __IM uint32_t T0_INT_RAW : 1; /*!< The raw interrupt status bit for the TIMG_T0_INT interrupt. */ - __IM uint32_t T1_INT_RAW : 1; /*!< The raw interrupt status bit for the TIMG_T1_INT interrupt. */ - __IM uint32_t WDT_INT_RAW : 1; /*!< The raw interrupt status bit for the TIMG_WDT_INT interrupt. */ - uint32_t : 29; - } bit; - } INT_RAW_TIMERS; - - union { - __IOM uint32_t reg; /*!< Masked interrupt status */ - - struct { - __IM uint32_t T0_INT_ST : 1; /*!< The masked interrupt status bit for the TIMG_T0_INT interrupt. */ - __IM uint32_t T1_INT_ST : 1; /*!< The masked interrupt status bit for the TIMG_T1_INT interrupt. */ - __IM uint32_t WDT_INT_ST : 1; /*!< The masked interrupt status bit for the TIMG_WDT_INT interrupt. */ - uint32_t : 29; - } bit; - } INT_ST_TIMERS; - - union { - __IOM uint32_t reg; /*!< Interrupt clear bits */ - - struct { - __OM uint32_t T0_INT_CLR : 1; /*!< Set this bit to clear the TIMG_T0_INT interrupt. */ - __OM uint32_t T1_INT_CLR : 1; /*!< Set this bit to clear the TIMG_T1_INT interrupt. */ - __OM uint32_t WDT_INT_CLR : 1; /*!< Set this bit to clear the TIMG_WDT_INT interrupt. */ - uint32_t : 29; - } bit; - } INT_CLR_TIMERS; - - union { - __IOM uint32_t reg; /*!< Timer group calibration register */ - - struct { - __IM uint32_t RTC_CALI_TIMEOUT : 1; /*!< RTC calibration timeout indicator */ - uint32_t : 2; - __IOM uint32_t RTC_CALI_TIMEOUT_RST_CNT : 4;/*!< Cycles that release calibration timeout reset */ - __IOM uint32_t RTC_CALI_TIMEOUT_THRES : 25;/*!< Threshold value for the RTC calibration timer. If the calibration - timer's value exceeds this threshold, a timeout is triggered. */ - } bit; - } RTCCALICFG2; - __IM uint32_t RESERVED1[29]; - - union { - __IOM uint32_t reg; /*!< Timer version control register */ - - struct { - __IOM uint32_t NTIMGS_DATE : 28; /*!< Timer version control register */ - uint32_t : 4; - } bit; - } NTIMERS_DATE; - - union { - __IOM uint32_t reg; /*!< Timer group clock gate register */ - - struct { - uint32_t : 28; - __IOM uint32_t ETM_EN : 1; /*!< enable timer's etm task and event */ - __IOM uint32_t WDT_CLK_IS_ACTIVE : 1; /*!< enable WDT's clock */ - __IOM uint32_t TIMER_CLK_IS_ACTIVE : 1; /*!< enable Timer 30's clock */ - __IOM uint32_t CLK_EN : 1; /*!< Register clock gate signal. 1: Registers can be read and written - to by software. 0: Registers can not be read or written - to by software. */ - } bit; - } REGCLK; -} TIMG0_Type; /*!< Size = 256 (0x100) */ - - - -/* =========================================================================================================================== */ -/* ================ TRACE0 ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief TRACE0 Peripheral (TRACE0) - */ - -typedef struct { /*!< TRACE0 Structure */ - - union { - __IOM uint32_t reg; /*!< mem start addr */ - - struct { - __IOM uint32_t MEM_START_ADDR : 32; /*!< The start address of trace memory */ - } bit; - } MEM_START_ADDR; - - union { - __IOM uint32_t reg; /*!< mem end addr */ - - struct { - __IOM uint32_t MEM_END_ADDR : 32; /*!< The end address of trace memory */ - } bit; - } MEM_END_ADDR; - - union { - __IOM uint32_t reg; /*!< mem current addr */ - - struct { - __IM uint32_t MEM_CURRENT_ADDR : 32; /*!< current_mem_addr,indicate that next writing addr */ - } bit; - } MEM_CURRENT_ADDR; - - union { - __IOM uint32_t reg; /*!< mem addr update */ - - struct { - __OM uint32_t MEM_CURRENT_ADDR_UPDATE : 1;/*!< when set, the will \hyperref[fielddesc:TRACEMEMCURRENTADDR]{TRACE_MEM_CURRENT_ - DDR} update to \hyperref[fielddesc:TRACEMEMSTARTADDR]{TRACE_MEM_START_ADD - }. */ - uint32_t : 31; - } bit; - } MEM_ADDR_UPDATE; - - union { - __IOM uint32_t reg; /*!< fifo status register */ - - struct { - __IM uint32_t FIFO_EMPTY : 1; /*!< Represent whether the fifo is empty. \\1: empty \\0: not empty */ - __IM uint32_t WORK_STATUS : 2; /*!< Represent trace work status: \\0: idle state \\1: working state\\ - 2: wait state due to hart halted or havereset \\3: lost - state */ - uint32_t : 29; - } bit; - } FIFO_STATUS; - - union { - __IOM uint32_t reg; /*!< interrupt enable register */ - - struct { - __IOM uint32_t FIFO_OVERFLOW_INTR_ENA : 1;/*!< Set 1 enable fifo_overflow interrupt */ - __IOM uint32_t MEM_FULL_INTR_ENA : 1; /*!< Set 1 enable mem_full interrupt */ - uint32_t : 30; - } bit; - } INTR_ENA; - - union { - __IOM uint32_t reg; /*!< interrupt status register */ - - struct { - __IM uint32_t FIFO_OVERFLOW_INTR_RAW : 1;/*!< fifo_overflow interrupt status */ - __IM uint32_t MEM_FULL_INTR_RAW : 1; /*!< mem_full interrupt status */ - uint32_t : 30; - } bit; - } INTR_RAW; - - union { - __IOM uint32_t reg; /*!< interrupt clear register */ - - struct { - __OM uint32_t FIFO_OVERFLOW_INTR_CLR : 1;/*!< Set 1 clear fifo overflow interrupt */ - __OM uint32_t MEM_FULL_INTR_CLR : 1; /*!< Set 1 clear mem full interrupt */ - uint32_t : 30; - } bit; - } INTR_CLR; - - union { - __IOM uint32_t reg; /*!< trigger register */ - - struct { - __OM uint32_t ON : 1; /*!< Configure whether or not start trace.\\1: start trace \\0: invalid\\ */ - __OM uint32_t OFF : 1; /*!< Configure whether or not stop trace.\\1: stop trace \\0: invalid\\ */ - __IOM uint32_t MEM_LOOP : 1; /*!< Configure memory loop mode. \\1: trace will loop wrtie trace_mem. - \\0: when mem_current_addr at mem_end_addr, it will stop - at the mem_end_addr\\ */ - __IOM uint32_t RESTART_ENA : 1; /*!< Configure whether or not enable auto-restart.\\1: enable\\0: - disable\\ */ - uint32_t : 28; - } bit; - } TRIGGER; - - union { - __IOM uint32_t reg; /*!< trace configuration register */ - - struct { - __IOM uint32_t DM_TRIGGER_ENA : 1; /*!< Configure whether or not enable cpu trigger action.\\1: enable\\0:disable\\ */ - __IOM uint32_t RESET_ENA : 1; /*!< Configure whether or not enable trace cpu haverest, when enabeld, - if cpu have reset, the encoder will output a packet to - report the address of the last instruction, and upon reset - deassertion, the encoder start again.\\1: enabeld\\0: disabled\\ */ - __IOM uint32_t HALT_ENA : 1; /*!< Configure whether or not enable trace cpu is halted, when enabeld, - if the cpu halted, the encoder will output a packet to - report the address of the last instruction, and upon halted - deassertion, the encoder start again.When disabled, encoder - will not report the last address before halted and first - address after halted, cpu halted information will not be - tracked. \\1: enabeld\\0: disabled\\ */ - __IOM uint32_t STALL_ENA : 1; /*!< Configure whether or not enable stall cpu. When enabled, when - the fifo almost full, the cpu will be stalled until the - packets is able to write to fifo.\\1: enabled.\\0: disabled\\ */ - __IOM uint32_t FULL_ADDRESS : 1; /*!< Configure whether or not enable full-address mode.\\1: full - address mode.\\0: delta address mode\\ */ - __IOM uint32_t IMPLICIT_EXCEPT : 1; /*!< Configure whether or not enabel implicit exception mode. When - enabled,, do not sent exception address, only exception - cause in exception packets.\\1: enabled\\0: disabled\\ */ - uint32_t : 26; - } bit; - } CONFIG; - - union { - __IOM uint32_t reg; /*!< filter control register */ - - struct { - __IOM uint32_t FILTER_EN : 1; /*!< Configure whether or not enable filter unit. \\1: enable filter.\\ - 0: always match */ - __IOM uint32_t MATCH_COMP : 1; /*!< when set, the comparator must be high in order for the filter - to match */ - __IOM uint32_t MATCH_PRIVILEGE : 1; /*!< when set, match privilege levels specified by \hyperref[fielddesc:TRACEMATCHCH - ICEPRIVILEGE]{TRACE_MATCH_CHOICE_PRIVILEGE}. */ - __IOM uint32_t MATCH_ECAUSE : 1; /*!< when set, start matching from exception cause codes specified - by \hyperref[fielddesc:TRACEMATCHCHOICEECAUSE]{TRACE_MATCH_CHOICE_ECAUSE} - and stop matching upon return from the 1st matching exception. */ - __IOM uint32_t MATCH_INTERRUPT : 1; /*!< when set, start matching from a trap with the interrupt level - codes specified by \hyperref[fielddesc:TRACEMATCHVALUEINTERRUPT]{TRACE_MA - CH_VALUE_INTERRUPT}, and stop matching upon return from - the 1st matching trap. */ - uint32_t : 27; - } bit; - } FILTER_CONTROL; - - union { - __IOM uint32_t reg; /*!< filter match control register */ - - struct { - __IOM uint32_t MATCH_CHOICE_PRIVILEGE : 1;/*!< Select match which privilege level when \hyperref[fielddesc:TRACEMATCHPRIVILEG - ]{TRACE_MATCH_PRIVILEGE} is set. \\1: machine mode. \\0: - user mode */ - __IOM uint32_t MATCH_VALUE_INTERRUPT : 1; /*!< Select which match which itype when \hyperref[fielddesc:TRACEMATCHINTERRUPT]{T - ACE_MATCH_INTERRUP} is set. \\1: match itype of 2. \\0: - match itype or 1. */ - __IOM uint32_t MATCH_CHOICE_ECAUSE : 6; /*!< specified which ecause matched. */ - uint32_t : 24; - } bit; - } FILTER_MATCH_CONTROL; - - union { - __IOM uint32_t reg; /*!< filter comparator match control register */ - - struct { - __IOM uint32_t P_INPUT : 1; /*!< Determines which input to compare against the primary comparator, - \\0: iaddr, \\1: tval. */ - uint32_t : 1; - __IOM uint32_t P_FUNCTION : 3; /*!< Select the primary comparator function. \\0: equal, \\1: not - equal, \\2: less than, \\3: less than or equal, \\4: greater - than, \\5: greater than or equal, \\other: always match */ - __IOM uint32_t P_NOTIFY : 1; /*!< Generate a trace packet explicitly reporting the address that - cause the primary match */ - uint32_t : 2; - __IOM uint32_t S_INPUT : 1; /*!< Determines which input to compare against the secondary comparator, - \\0: iaddr, \\1: tval. */ - uint32_t : 1; - __IOM uint32_t S_FUNCTION : 3; /*!< Select the secondary comparator function. \\0: equal, \\1: not - equal, \\2: less than, \\3: less than or equal, \\4: greater - than, \\5: greater than or equal, \\other: always match */ - __IOM uint32_t S_NOTIFY : 1; /*!< Generate a trace packet explicitly reporting the address that - cause the secondary match */ - uint32_t : 2; - __IOM uint32_t MATCH_MODE : 2; /*!< 0: only primary matches, \\1: primary and secondary comparator - both matches(P\&\&S),\\ 2:either primary or secondary comparator - matches !(P\&\&S), \\3: set when primary matches and continue - to match until after secondary comparator matches */ - uint32_t : 14; - } bit; - } FILTER_COMPARATOR_CONTROL; - - union { - __IOM uint32_t reg; /*!< primary comparator match value */ - - struct { - __IOM uint32_t P_MATCH : 32; /*!< primary comparator match value */ - } bit; - } FILTER_P_COMPARATOR_MATCH; - - union { - __IOM uint32_t reg; /*!< secondary comparator match value */ - - struct { - __IOM uint32_t S_MATCH : 32; /*!< secondary comparator match value */ - } bit; - } FILTER_S_COMPARATOR_MATCH; - - union { - __IOM uint32_t reg; /*!< resync configuration register */ - - struct { - __IOM uint32_t RESYNC_PROLONGED : 24; /*!< count number, when count to this value, send a sync package */ - __IOM uint32_t RESYNC_MODE : 2; /*!< resyc mode sel: \\0: off, \\2: cycle count \\3: package num - count */ - uint32_t : 6; - } bit; - } RESYNC_PROLONGED; - - union { - __IOM uint32_t reg; /*!< AHB config register */ - - struct { - __IOM uint32_t HBURST : 3; /*!< set hburst */ - __IOM uint32_t MAX_INCR : 3; /*!< set max continuous access for incr mode */ - uint32_t : 26; - } bit; - } AHB_CONFIG; - - union { - __IOM uint32_t reg; /*!< Clock gate control register */ - - struct { - __IOM uint32_t CLK_EN : 1; /*!< The bit is used to enable clock gate when access all registers - in this module. */ - uint32_t : 31; - } bit; - } CLOCK_GATE; - __IM uint32_t RESERVED[237]; - - union { - __IOM uint32_t reg; /*!< Version control register */ - - struct { - __IOM uint32_t DATE : 28; /*!< version control register. Note that this default value stored - is the latest date when the hardware logic was updated. */ - uint32_t : 4; - } bit; - } DATE; -} TRACE0_Type; /*!< Size = 1024 (0x400) */ - - - -/* =========================================================================================================================== */ -/* ================ LP_TSENS ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Low-power Temperature Sensor (LP_TSENS) - */ - -typedef struct { /*!< LP_TSENS Structure */ - - union { - __IOM uint32_t reg; /*!< Tsens configuration. */ - - struct { - __IM uint32_t OUT : 8; /*!< Temperature sensor data out. */ - __IM uint32_t READY : 1; /*!< Indicate temperature sensor out ready. */ - __IOM uint32_t SAMPLE_EN : 1; /*!< Enable sample signal for wakeup module. */ - __IOM uint32_t WAKEUP_MASK : 1; /*!< Wake up signal mask. */ - uint32_t : 1; - __IOM uint32_t INT_EN : 1; /*!< Enable temperature sensor to send out interrupt. */ - __IOM uint32_t IN_INV : 1; /*!< Invert temperature sensor data. */ - __IOM uint32_t CLK_DIV : 8; /*!< Temperature sensor clock divider. */ - __IOM uint32_t POWER_UP : 1; /*!< Temperature sensor power up. */ - __IOM uint32_t POWER_UP_FORCE : 1; /*!< 1: dump out & power up controlled by SW, 0: by FSM. */ - uint32_t : 8; - } bit; - } CTRL; - - union { - __IOM uint32_t reg; /*!< Tsens configuration. */ - - struct { - __IOM uint32_t XPD_WAIT : 12; /*!< N/A */ - __IOM uint32_t XPD_FORCE : 2; /*!< N/A */ - __IOM uint32_t CLK_INV : 1; /*!< N/A */ - uint32_t : 17; - } bit; - } CTRL2; - - union { - __IOM uint32_t reg; /*!< Tsens interrupt raw registers. */ - - struct { - __IOM uint32_t COCPU_TSENS_WAKE_INT_RAW : 1;/*!< Tsens wakeup interrupt raw. */ - uint32_t : 31; - } bit; - } INT_RAW; - - union { - __IOM uint32_t reg; /*!< Tsens interrupt status registers. */ - - struct { - __IM uint32_t COCPU_TSENS_WAKE_INT_ST : 1;/*!< Tsens wakeup interrupt status. */ - uint32_t : 31; - } bit; - } INT_ST; - - union { - __IOM uint32_t reg; /*!< Tsens interrupt enable registers. */ - - struct { - __IOM uint32_t COCPU_TSENS_WAKE_INT_ENA : 1;/*!< Tsens wakeup interrupt enable. */ - uint32_t : 31; - } bit; - } INT_ENA; - - union { - __IOM uint32_t reg; /*!< Tsens interrupt clear registers. */ - - struct { - __OM uint32_t COCPU_TSENS_WAKE_INT_CLR : 1;/*!< Tsens wakeup interrupt clear. */ - uint32_t : 31; - } bit; - } INT_CLR; - - union { - __IOM uint32_t reg; /*!< Tsens regbank configuration registers. */ - - struct { - __IOM uint32_t CLK_EN : 1; /*!< Tsens regbank clock gating enable. */ - uint32_t : 31; - } bit; - } CLK_CONF; - - union { - __IOM uint32_t reg; /*!< Tsens wakeup interrupt enable assert. */ - - struct { - __OM uint32_t COCPU_TSENS_WAKE_INT_ENA_W1TS : 1;/*!< Write 1 to this field to assert interrupt enable. */ - uint32_t : 31; - } bit; - } INT_ENA_W1TS; - - union { - __IOM uint32_t reg; /*!< Tsens wakeup interrupt enable deassert. */ - - struct { - __OM uint32_t COCPU_TSENS_WAKE_INT_ENA_W1TC : 1;/*!< Write 1 to this field to deassert interrupt enable. */ - uint32_t : 31; - } bit; - } INT_ENA_W1TC; - - union { - __IOM uint32_t reg; /*!< Tsens wakeup control registers. */ - - struct { - __IOM uint32_t WAKEUP_TH_LOW : 8; /*!< Lower threshold. */ - uint32_t : 6; - __IOM uint32_t WAKEUP_TH_HIGH : 8; /*!< Upper threshold. */ - uint32_t : 7; - __IM uint32_t WAKEUP_OVER_UPPER_TH : 1; /*!< Indicates that this wakeup event arose from exceeding upper - threshold. */ - __IOM uint32_t WAKEUP_EN : 1; /*!< Tsens wakeup enable. */ - __IOM uint32_t WAKEUP_MODE : 1; /*!< 0:absolute value comparison mode. 1: relative value comparison - mode. */ - } bit; - } WAKEUP_CTRL; - - union { - __IOM uint32_t reg; /*!< Hardware automatic sampling control registers. */ - - struct { - __IOM uint32_t SAMPLE_RATE : 16; /*!< Hardware automatic sampling rate. */ - uint32_t : 16; - } bit; - } SAMPLE_RATE; - - union { - __IOM uint32_t reg; /*!< N/A */ - - struct { - __IOM uint32_t RND_ECO_LOW : 32; /*!< N/A */ - } bit; - } RND_ECO_LOW; - - union { - __IOM uint32_t reg; /*!< N/A */ - - struct { - __IOM uint32_t RND_ECO_HIGH : 32; /*!< N/A */ - } bit; - } RND_ECO_HIGH; - - union { - __IOM uint32_t reg; /*!< N/A */ - - struct { - __IOM uint32_t RND_ECO_EN : 1; /*!< N/A */ - __IM uint32_t RND_ECO_RESULT : 1; /*!< N/A */ - uint32_t : 30; - } bit; - } RND_ECO_CS; -} LP_TSENS_Type; /*!< Size = 56 (0x38) */ - - - -/* =========================================================================================================================== */ -/* ================ TWAI0 ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Two-Wire Automotive Interface (TWAI0) - */ - -typedef struct { /*!< TWAI0 Structure */ - - union { - __IOM uint32_t reg; /*!< TWAI mode register. */ - - struct { - __IOM uint32_t RESET_MODE : 1; /*!< 1: reset, detection of a set reset mode bit results in aborting - the current transmission/reception of a message and entering - the reset mode. 0: normal, on the '1-to-0' transition of - the reset mode bit, the TWAI controller returns to the - operating mode. */ - __IOM uint32_t LISTEN_ONLY_MODE : 1; /*!< 1: listen only, in this mode the TWAI controller would give - no acknowledge to the TWAI-bus, even if a message is received - successfully. The error counters are stopped at the current - value. 0: normal. */ - __IOM uint32_t SELF_TEST_MODE : 1; /*!< 1: self test, in this mode a full node test is possible without - any other active node on the bus using the self reception - request command. The TWAI controller will perform a successful - transmission, even if there is no acknowledge received. - 0: normal, an acknowledge is required for successful transmission. */ - __IOM uint32_t ACCEPTANCE_FILTER_MODE : 1;/*!< 1:single, the single acceptance filter option is enabled (one - filter with the length of 32 bit is active). 0:dual, the - dual acceptance filter option is enabled (two filters, - each with the length of 16 bit are active). */ - uint32_t : 28; - } bit; - } MODE; - - union { - __IOM uint32_t reg; /*!< TWAI command register. */ - - struct { - __OM uint32_t TX_REQUEST : 1; /*!< 1: present, a message shall be transmitted. 0: absent */ - __OM uint32_t ABORT_TX : 1; /*!< 1: present, if not already in progress, a pending transmission - request is cancelled. 0: absent */ - __OM uint32_t RELEASE_BUFFER : 1; /*!< 1: released, the receive buffer, representing the message memory - space in the RXFIFO is released. 0: no action */ - __OM uint32_t CLEAR_DATA_OVERRUN : 1; /*!< 1: clear, the data overrun status bit is cleared. 0: no action. */ - __OM uint32_t SELF_RX_REQUEST : 1; /*!< 1: present, a message shall be transmitted and received simultaneously. - 0: absent. */ - uint32_t : 27; - } bit; - } CMD; - - union { - __IOM uint32_t reg; /*!< TWAI status register. */ - - struct { - __IM uint32_t RECEIVE_BUFFER : 1; /*!< 1: full, one or more complete messages are available in the - RXFIFO. 0: empty, no message is available */ - __IM uint32_t OVERRUN : 1; /*!< 1: overrun, a message was lost because there was not enough - space for that message in the RXFIFO. 0: absent, no data - overrun has occurred since the last clear data overrun - command was given */ - __IM uint32_t TRANSMIT_BUFFER : 1; /*!< 1: released, the CPU may write a message into the transmit buffer. - 0: locked, the CPU cannot access the transmit buffer, a - message is either waiting for transmission or is in the - process of being transmitted */ - __IM uint32_t TRANSMISSION_COMPLETE : 1; /*!< 1: complete, last requested transmission has been successfully - completed. 0: incomplete, previously requested transmission - is not yet completed */ - __IM uint32_t RECEIVE : 1; /*!< 1: receive, the TWAI controller is receiving a message. 0: idle */ - __IM uint32_t TRANSMIT : 1; /*!< 1: transmit, the TWAI controller is transmitting a message. - 0: idle */ - __IM uint32_t ERR : 1; /*!< 1: error, at least one of the error counters has reached or - exceeded the CPU warning limit defined by the Error Warning - Limit Register (EWLR). 0: ok, both error counters are below - the warning limit */ - __IM uint32_t NODE_BUS_OFF : 1; /*!< 1: bus-off, the TWAI controller is not involved in bus activities. - 0: bus-on, the TWAI controller is involved in bus activities */ - __IM uint32_t MISS : 1; /*!< 1: current message is destroyed because of FIFO overflow. */ - uint32_t : 23; - } bit; - } STATUS; - - union { - __IOM uint32_t reg; /*!< Interrupt signals' register. */ - - struct { - __IM uint32_t RECEIVE_INT_ST : 1; /*!< 1: this bit is set while the receive FIFO is not empty and the - RIE bit is set within the interrupt enable register. 0: - reset */ - __IM uint32_t TRANSMIT_INT_ST : 1; /*!< 1: this bit is set whenever the transmit buffer status changes - from '0-to-1' (released) and the TIE bit is set within - the interrupt enable register. 0: reset */ - __IM uint32_t ERR_WARNING_INT_ST : 1; /*!< 1: this bit is set on every change (set and clear) of either - the error status or bus status bits and the EIE bit is - set within the interrupt enable register. 0: reset */ - __IM uint32_t DATA_OVERRUN_INT_ST : 1; /*!< 1: this bit is set on a '0-to-1' transition of the data overrun - status bit and the DOIE bit is set within the interrupt - enable register. 0: reset */ - __IM uint32_t TS_COUNTER_OVFL_INT_ST : 1;/*!< 1: this bit is set then the timestamp counter reaches the maximum - value and overflow. */ - __IM uint32_t ERR_PASSIVE_INT_ST : 1; /*!< 1: this bit is set whenever the TWAI controller has reached - the error passive status (at least one error counter exceeds - the protocol-defined level of 127) or if the TWAI controller - is in the error passive status and enters the error active - status again and the EPIE bit is set within the interrupt - enable register. 0: reset */ - __IM uint32_t ARBITRATION_LOST_INT_ST : 1;/*!< 1: this bit is set when the TWAI controller lost the arbitration - and becomes a receiver and the ALIE bit is set within the - interrupt enable register. 0: reset */ - __IM uint32_t BUS_ERR_INT_ST : 1; /*!< 1: this bit is set when the TWAI controller detects an error - on the TWAI-bus and the BEIE bit is set within the interrupt - enable register. 0: reset */ - __IM uint32_t IDLE_INT_ST : 1; /*!< 1: this bit is set when the TWAI controller detects state of - TWAI become IDLE and this interrupt enable bit is set within - the interrupt enable register. 0: reset */ - uint32_t : 23; - } bit; - } INTERRUPT; - - union { - __IOM uint32_t reg; /*!< Interrupt enable register. */ - - struct { - __IOM uint32_t EXT_RECEIVE_INT_ENA : 1; /*!< 1: enabled, when the receive buffer status is 'full' the TWAI - controller requests the respective interrupt. 0: disable */ - __IOM uint32_t EXT_TRANSMIT_INT_ENA : 1; /*!< 1: enabled, when a message has been successfully transmitted - or the transmit buffer is accessible again (e.g. after - an abort transmission command), the TWAI controller requests - the respective interrupt. 0: disable */ - __IOM uint32_t EXT_ERR_WARNING_INT_ENA : 1;/*!< 1: enabled, if the error or bus status change (see status register. - Table 14), the TWAI controllerrequests the respective interrupt. - 0: disable */ - __IOM uint32_t EXT_DATA_OVERRUN_INT_ENA : 1;/*!< 1: enabled, if the data overrun status bit is set (see status - register. Table 14), the TWAI controllerrequests the respective - interrupt. 0: disable */ - __IOM uint32_t TS_COUNTER_OVFL_INT_ENA : 1;/*!< enable the timestamp counter overflow interrupt request. */ - __IOM uint32_t ERR_PASSIVE_INT_ENA : 1; /*!< 1: enabled, if the error status of the TWAI controller changes - from error active to error passive or vice versa, the respective - interrupt is requested. 0: disable */ - __IOM uint32_t ARBITRATION_LOST_INT_ENA : 1;/*!< 1: enabled, if the TWAI controller has lost arbitration, the - respective interrupt is requested. 0: disable */ - __IOM uint32_t BUS_ERR_INT_ENA : 1; /*!< 1: enabled, if an bus error has been detected, the TWAI controller - requests the respective interrupt. 0: disable */ - __IM uint32_t IDLE_INT_ENA : 1; /*!< 1: enabled, if state of TWAI become IDLE, the TWAI controller - requests the respective interrupt. 0: disable */ - uint32_t : 23; - } bit; - } INTERRUPT_ENABLE; - __IM uint32_t RESERVED; - - union { - __IOM uint32_t reg; /*!< Bit timing configuration register 0. */ - - struct { - __IOM uint32_t BAUD_PRESC : 14; /*!< The period of the TWAI system clock is programmable and determines - the individual bit timing. Software has R/W permission - in reset mode and RO permission in operation mode. */ - __IOM uint32_t SYNC_JUMP_WIDTH : 2; /*!< The synchronization jump width defines the maximum number of - clock cycles a bit period may be shortened or lengthened. - Software has R/W permission in reset mode and RO in operation - mode. */ - uint32_t : 16; - } bit; - } BUS_TIMING_0; - - union { - __IOM uint32_t reg; /*!< Bit timing configuration register 1. */ - - struct { - __IOM uint32_t TIME_SEGMENT1 : 4; /*!< The number of clock cycles in TSEG1 per bit timing. Software - has R/W permission in reset mode and RO in operation mode. */ - __IOM uint32_t TIME_SEGMENT2 : 3; /*!< The number of clock cycles in TSEG2 per bit timing. Software - has R/W permission in reset mode and RO in operation mode. */ - __IOM uint32_t TIME_SAMPLING : 1; /*!< 1: triple, the bus is sampled three times. 0: single, the bus - is sampled once. Software has R/W permission in reset mode - and RO in operation mode. */ - uint32_t : 24; - } bit; - } BUS_TIMING_1; - __IM uint32_t RESERVED1[3]; - - union { - __IOM uint32_t reg; /*!< TWAI arbiter lost capture register. */ - - struct { - __IM uint32_t ARBITRATION_LOST_CAPTURE : 5;/*!< This register contains information about the bit position of - losing arbitration. */ - uint32_t : 27; - } bit; - } ARB_LOST_CAP; - - union { - __IOM uint32_t reg; /*!< TWAI error info capture register. */ - - struct { - __IM uint32_t ERR_CAPTURE_CODE_SEGMENT : 5;/*!< This register contains information about the location of errors - on the bus. */ - __IM uint32_t ERR_CAPTURE_CODE_DIRECTION : 1;/*!< 1: RX, error occurred during reception. 0: TX, error occurred - during transmission. */ - __IM uint32_t ERR_CAPTURE_CODE_TYPE : 2; /*!< 00: bit error. 01: form error. 10:stuff error. 11:other type - of error. */ - uint32_t : 24; - } bit; - } ERR_CODE_CAP; - - union { - __IOM uint32_t reg; /*!< TWAI error threshold configuration register. */ - - struct { - __IOM uint32_t ERR_WARNING_LIMIT : 8; /*!< The threshold that trigger error warning interrupt when this - interrupt is enabled. Software has R/W permission in reset - mode and RO in operation mode. */ - uint32_t : 24; - } bit; - } ERR_WARNING_LIMIT; - - union { - __IOM uint32_t reg; /*!< Rx error counter register. */ - - struct { - __IOM uint32_t RX_ERR_CNT : 8; /*!< The RX error counter register reflects the current value of - the transmit error counter. Software has R/W permission - in reset mode and RO in operation mode. */ - uint32_t : 24; - } bit; - } RX_ERR_CNT; - - union { - __IOM uint32_t reg; /*!< Tx error counter register. */ - - struct { - __IOM uint32_t TX_ERR_CNT : 8; /*!< The TX error counter register reflects the current value of - the transmit error counter. Software has R/W permission - in reset mode and RO in operation mode. */ - uint32_t : 24; - } bit; - } TX_ERR_CNT; - - union { - __IOM uint32_t reg; /*!< Data register 0. */ - - struct { - __IOM uint32_t DATA_0 : 8; /*!< In reset mode, it is acceptance code register 0 with R/W Permission. - In operation mode, when software initiate write operation, - it is tx data register 0 and when software initiate read - operation, it is rx data register 0. */ - uint32_t : 24; - } bit; - } DATA_0; - - union { - __IOM uint32_t reg; /*!< Data register 1. */ - - struct { - __IOM uint32_t DATA_1 : 8; /*!< In reset mode, it is acceptance code register 1 with R/W Permission. - In operation mode, when software initiate write operation, - it is tx data register 1 and when software initiate read - operation, it is rx data register 1. */ - uint32_t : 24; - } bit; - } DATA_1; - - union { - __IOM uint32_t reg; /*!< Data register 2. */ - - struct { - __IOM uint32_t DATA_2 : 8; /*!< In reset mode, it is acceptance code register 2 with R/W Permission. - In operation mode, when software initiate write operation, - it is tx data register 2 and when software initiate read - operation, it is rx data register 2. */ - uint32_t : 24; - } bit; - } DATA_2; - - union { - __IOM uint32_t reg; /*!< Data register 3. */ - - struct { - __IOM uint32_t DATA_3 : 8; /*!< In reset mode, it is acceptance code register 3 with R/W Permission. - In operation mode, when software initiate write operation, - it is tx data register 3 and when software initiate read - operation, it is rx data register 3. */ - uint32_t : 24; - } bit; - } DATA_3; - - union { - __IOM uint32_t reg; /*!< Data register 4. */ - - struct { - __IOM uint32_t DATA_4 : 8; /*!< In reset mode, it is acceptance mask register 0 with R/W Permission. - In operation mode, when software initiate write operation, - it is tx data register 4 and when software initiate read - operation, it is rx data register 4. */ - uint32_t : 24; - } bit; - } DATA_4; - - union { - __IOM uint32_t reg; /*!< Data register 5. */ - - struct { - __IOM uint32_t DATA_5 : 8; /*!< In reset mode, it is acceptance mask register 1 with R/W Permission. - In operation mode, when software initiate write operation, - it is tx data register 5 and when software initiate read - operation, it is rx data register 5. */ - uint32_t : 24; - } bit; - } DATA_5; - - union { - __IOM uint32_t reg; /*!< Data register 6. */ - - struct { - __IOM uint32_t DATA_6 : 8; /*!< In reset mode, it is acceptance mask register 2 with R/W Permission. - In operation mode, when software initiate write operation, - it is tx data register 6 and when software initiate read - operation, it is rx data register 6. */ - uint32_t : 24; - } bit; - } DATA_6; - - union { - __IOM uint32_t reg; /*!< Data register 7. */ - - struct { - __IOM uint32_t DATA_7 : 8; /*!< In reset mode, it is acceptance mask register 3 with R/W Permission. - In operation mode, when software initiate write operation, - it is tx data register 7 and when software initiate read - operation, it is rx data register 7. */ - uint32_t : 24; - } bit; - } DATA_7; - - union { - __IOM uint32_t reg; /*!< Data register 8. */ - - struct { - __IOM uint32_t DATA_8 : 8; /*!< In reset mode, reserved with RO. In operation mode, when software - initiate write operation, it is tx data register 8 and - when software initiate read operation, it is rx data register - 8. */ - uint32_t : 24; - } bit; - } DATA_8; - - union { - __IOM uint32_t reg; /*!< Data register 9. */ - - struct { - __IOM uint32_t DATA_9 : 8; /*!< In reset mode, reserved with RO. In operation mode, when software - initiate write operation, it is tx data register 9 and - when software initiate read operation, it is rx data register - 9. */ - uint32_t : 24; - } bit; - } DATA_9; - - union { - __IOM uint32_t reg; /*!< Data register 10. */ - - struct { - __IOM uint32_t DATA_10 : 8; /*!< In reset mode, reserved with RO. In operation mode, when software - initiate write operation, it is tx data register 10 and - when software initiate read operation, it is rx data register - 10. */ - uint32_t : 24; - } bit; - } DATA_10; - - union { - __IOM uint32_t reg; /*!< Data register 11. */ - - struct { - __IOM uint32_t DATA_11 : 8; /*!< In reset mode, reserved with RO. In operation mode, when software - initiate write operation, it is tx data register 11 and - when software initiate read operation, it is rx data register - 11. */ - uint32_t : 24; - } bit; - } DATA_11; - - union { - __IOM uint32_t reg; /*!< Data register 12. */ - - struct { - __IOM uint32_t DATA_12 : 8; /*!< In reset mode, reserved with RO. In operation mode, when software - initiate write operation, it is tx data register 12 and - when software initiate read operation, it is rx data register - 12. */ - uint32_t : 24; - } bit; - } DATA_12; - - union { - __IOM uint32_t reg; /*!< Received message counter register. */ - - struct { - __IM uint32_t RX_MESSAGE_COUNTER : 7; /*!< Reflects the number of messages available within the RXFIFO. - The value is incremented with each receive event and decremented - by the release receive buffer command. */ - uint32_t : 25; - } bit; - } RX_MESSAGE_COUNTER; - __IM uint32_t RESERVED2; - - union { - __IOM uint32_t reg; /*!< Clock divider register. */ - - struct { - __IOM uint32_t CD : 8; /*!< These bits are used to define the frequency at the external - CLKOUT pin. */ - __IOM uint32_t CLOCK_OFF : 1; /*!< 1: Disable the external CLKOUT pin. 0: Enable the external CLKOUT - pin. Software has R/W permission in reset mode and RO in - operation mode. */ - uint32_t : 23; - } bit; - } CLOCK_DIVIDER; - - union { - __IOM uint32_t reg; /*!< Software configure standby pin directly. */ - - struct { - __IOM uint32_t SW_STANDBY_EN : 1; /*!< Enable standby pin. */ - __IOM uint32_t SW_STANDBY_CLR : 1; /*!< Clear standby pin. */ - uint32_t : 30; - } bit; - } SW_STANDBY_CFG; - - union { - __IOM uint32_t reg; /*!< Hardware configure standby pin. */ - - struct { - __IOM uint32_t HW_STANDBY_EN : 1; /*!< Enable function that hardware control standby pin. */ - uint32_t : 31; - } bit; - } HW_CFG; - - union { - __IOM uint32_t reg; /*!< Configure standby counter. */ - - struct { - __IOM uint32_t STANDBY_WAIT_CNT : 32; /*!< Configure the number of cycles before standby becomes high when - TWAI_HW_STANDBY_EN is enabled. */ - } bit; - } HW_STANDBY_CNT; - - union { - __IOM uint32_t reg; /*!< Configure idle interrupt counter. */ - - struct { - __IOM uint32_t IDLE_INTR_CNT : 32; /*!< Configure the number of cycles before triggering idle interrupt. */ - } bit; - } IDLE_INTR_CNT; - - union { - __IOM uint32_t reg; /*!< ECO configuration register. */ - - struct { - __IOM uint32_t RDN_ENA : 1; /*!< Enable eco module. */ - __IM uint32_t RDN_RESULT : 1; /*!< Output of eco module. */ - uint32_t : 30; - } bit; - } ECO_CFG; - - union { - __IOM uint32_t reg; /*!< Timestamp data register */ - - struct { - __IM uint32_t TIMESTAMP_DATA : 32; /*!< Data of timestamp of a CAN frame. */ - } bit; - } TIMESTAMP_DATA; - - union { - __IOM uint32_t reg; /*!< Timestamp configuration register */ - - struct { - __IOM uint32_t TS_DIV_NUM : 16; /*!< Configures the clock division number of timestamp counter. */ - uint32_t : 16; - } bit; - } TIMESTAMP_PRESCALER; - - union { - __IOM uint32_t reg; /*!< Timestamp configuration register */ - - struct { - __IOM uint32_t TS_ENABLE : 1; /*!< enable the timestamp collection function. */ - uint32_t : 31; - } bit; - } TIMESTAMP_CFG; -} TWAI0_Type; /*!< Size = 160 (0xa0) */ - - - -/* =========================================================================================================================== */ -/* ================ UART0 ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief UART (Universal Asynchronous Receiver-Transmitter) Controller 0 (UART0) - */ - -typedef struct { /*!< UART0 Structure */ - - union { - __IOM uint32_t reg; /*!< FIFO data register */ - - struct { - __IM uint32_t RXFIFO_RD_BYTE : 8; /*!< UART 0 accesses FIFO via this register. */ - uint32_t : 24; - } bit; - } FIFO; - - union { - __IOM uint32_t reg; /*!< Raw interrupt status */ - - struct { - __IOM uint32_t RXFIFO_FULL_INT_RAW : 1; /*!< This interrupt raw bit turns to high level when receiver receives - more data than what rxfifo_full_thrhd specifies. */ - __IOM uint32_t TXFIFO_EMPTY_INT_RAW : 1; /*!< This interrupt raw bit turns to high level when the amount of - data in Tx-FIFO is less than what txfifo_empty_thrhd specifies - . */ - __IOM uint32_t PARITY_ERR_INT_RAW : 1; /*!< This interrupt raw bit turns to high level when receiver detects - a parity error in the data. */ - __IOM uint32_t FRM_ERR_INT_RAW : 1; /*!< This interrupt raw bit turns to high level when receiver detects - a data frame error . */ - __IOM uint32_t RXFIFO_OVF_INT_RAW : 1; /*!< This interrupt raw bit turns to high level when receiver receives - more data than the FIFO can store. */ - __IOM uint32_t DSR_CHG_INT_RAW : 1; /*!< This interrupt raw bit turns to high level when receiver detects - the edge change of DSRn signal. */ - __IOM uint32_t CTS_CHG_INT_RAW : 1; /*!< This interrupt raw bit turns to high level when receiver detects - the edge change of CTSn signal. */ - __IOM uint32_t BRK_DET_INT_RAW : 1; /*!< This interrupt raw bit turns to high level when receiver detects - a 0 after the stop bit. */ - __IOM uint32_t RXFIFO_TOUT_INT_RAW : 1; /*!< This interrupt raw bit turns to high level when receiver takes - more time than rx_tout_thrhd to receive a byte. */ - __IOM uint32_t SW_XON_INT_RAW : 1; /*!< This interrupt raw bit turns to high level when receiver recevies - Xon char when uart_sw_flow_con_en is set to 1. */ - __IOM uint32_t SW_XOFF_INT_RAW : 1; /*!< This interrupt raw bit turns to high level when receiver receives - Xoff char when uart_sw_flow_con_en is set to 1. */ - __IOM uint32_t GLITCH_DET_INT_RAW : 1; /*!< This interrupt raw bit turns to high level when receiver detects - a glitch in the middle of a start bit. */ - __IOM uint32_t TX_BRK_DONE_INT_RAW : 1; /*!< This interrupt raw bit turns to high level when transmitter - completes sending NULL characters after all data in Tx-FIFO - are sent. */ - __IOM uint32_t TX_BRK_IDLE_DONE_INT_RAW : 1;/*!< This interrupt raw bit turns to high level when transmitter - has kept the shortest duration after sending the last data. */ - __IOM uint32_t TX_DONE_INT_RAW : 1; /*!< This interrupt raw bit turns to high level when transmitter - has send out all data in FIFO. */ - __IOM uint32_t RS485_PARITY_ERR_INT_RAW : 1;/*!< This interrupt raw bit turns to high level when receiver detects - a parity error from the echo of transmitter in rs485 mode. */ - __IOM uint32_t RS485_FRM_ERR_INT_RAW : 1; /*!< This interrupt raw bit turns to high level when receiver detects - a data frame error from the echo of transmitter in rs485 - mode. */ - __IOM uint32_t RS485_CLASH_INT_RAW : 1; /*!< This interrupt raw bit turns to high level when detects a clash - between transmitter and receiver in rs485 mode. */ - __IOM uint32_t AT_CMD_CHAR_DET_INT_RAW : 1;/*!< This interrupt raw bit turns to high level when receiver detects - the configured at_cmd char. */ - __IOM uint32_t WAKEUP_INT_RAW : 1; /*!< This interrupt raw bit turns to high level when input rxd edge - changes more times than what reg_active_threshold specifies - in light sleeping mode. */ - uint32_t : 12; - } bit; - } INT_RAW; - - union { - __IOM uint32_t reg; /*!< Masked interrupt status */ - - struct { - __IM uint32_t RXFIFO_FULL_INT_ST : 1; /*!< This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena - is set to 1. */ - __IM uint32_t TXFIFO_EMPTY_INT_ST : 1; /*!< This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena - is set to 1. */ - __IM uint32_t PARITY_ERR_INT_ST : 1; /*!< This is the status bit for parity_err_int_raw when parity_err_int_ena - is set to 1. */ - __IM uint32_t FRM_ERR_INT_ST : 1; /*!< This is the status bit for frm_err_int_raw when frm_err_int_ena - is set to 1. */ - __IM uint32_t RXFIFO_OVF_INT_ST : 1; /*!< This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena - is set to 1. */ - __IM uint32_t DSR_CHG_INT_ST : 1; /*!< This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena - is set to 1. */ - __IM uint32_t CTS_CHG_INT_ST : 1; /*!< This is the status bit for cts_chg_int_raw when cts_chg_int_ena - is set to 1. */ - __IM uint32_t BRK_DET_INT_ST : 1; /*!< This is the status bit for brk_det_int_raw when brk_det_int_ena - is set to 1. */ - __IM uint32_t RXFIFO_TOUT_INT_ST : 1; /*!< This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena - is set to 1. */ - __IM uint32_t SW_XON_INT_ST : 1; /*!< This is the status bit for sw_xon_int_raw when sw_xon_int_ena - is set to 1. */ - __IM uint32_t SW_XOFF_INT_ST : 1; /*!< This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena - is set to 1. */ - __IM uint32_t GLITCH_DET_INT_ST : 1; /*!< This is the status bit for glitch_det_int_raw when glitch_det_int_ena - is set to 1. */ - __IM uint32_t TX_BRK_DONE_INT_ST : 1; /*!< This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena - is set to 1. */ - __IM uint32_t TX_BRK_IDLE_DONE_INT_ST : 1;/*!< This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ - na is set to 1. */ - __IM uint32_t TX_DONE_INT_ST : 1; /*!< This is the status bit for tx_done_int_raw when tx_done_int_ena - is set to 1. */ - __IM uint32_t RS485_PARITY_ERR_INT_ST : 1;/*!< This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena - is set to 1. */ - __IM uint32_t RS485_FRM_ERR_INT_ST : 1; /*!< This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena - is set to 1. */ - __IM uint32_t RS485_CLASH_INT_ST : 1; /*!< This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena - is set to 1. */ - __IM uint32_t AT_CMD_CHAR_DET_INT_ST : 1;/*!< This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena - is set to 1. */ - __IM uint32_t WAKEUP_INT_ST : 1; /*!< This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena - is set to 1. */ - uint32_t : 12; - } bit; - } INT_ST; - - union { - __IOM uint32_t reg; /*!< Interrupt enable bits */ - - struct { - __IOM uint32_t RXFIFO_FULL_INT_ENA : 1; /*!< This is the enable bit for rxfifo_full_int_st register. */ - __IOM uint32_t TXFIFO_EMPTY_INT_ENA : 1; /*!< This is the enable bit for txfifo_empty_int_st register. */ - __IOM uint32_t PARITY_ERR_INT_ENA : 1; /*!< This is the enable bit for parity_err_int_st register. */ - __IOM uint32_t FRM_ERR_INT_ENA : 1; /*!< This is the enable bit for frm_err_int_st register. */ - __IOM uint32_t RXFIFO_OVF_INT_ENA : 1; /*!< This is the enable bit for rxfifo_ovf_int_st register. */ - __IOM uint32_t DSR_CHG_INT_ENA : 1; /*!< This is the enable bit for dsr_chg_int_st register. */ - __IOM uint32_t CTS_CHG_INT_ENA : 1; /*!< This is the enable bit for cts_chg_int_st register. */ - __IOM uint32_t BRK_DET_INT_ENA : 1; /*!< This is the enable bit for brk_det_int_st register. */ - __IOM uint32_t RXFIFO_TOUT_INT_ENA : 1; /*!< This is the enable bit for rxfifo_tout_int_st register. */ - __IOM uint32_t SW_XON_INT_ENA : 1; /*!< This is the enable bit for sw_xon_int_st register. */ - __IOM uint32_t SW_XOFF_INT_ENA : 1; /*!< This is the enable bit for sw_xoff_int_st register. */ - __IOM uint32_t GLITCH_DET_INT_ENA : 1; /*!< This is the enable bit for glitch_det_int_st register. */ - __IOM uint32_t TX_BRK_DONE_INT_ENA : 1; /*!< This is the enable bit for tx_brk_done_int_st register. */ - __IOM uint32_t TX_BRK_IDLE_DONE_INT_ENA : 1;/*!< This is the enable bit for tx_brk_idle_done_int_st register. */ - __IOM uint32_t TX_DONE_INT_ENA : 1; /*!< This is the enable bit for tx_done_int_st register. */ - __IOM uint32_t RS485_PARITY_ERR_INT_ENA : 1;/*!< This is the enable bit for rs485_parity_err_int_st register. */ - __IOM uint32_t RS485_FRM_ERR_INT_ENA : 1; /*!< This is the enable bit for rs485_parity_err_int_st register. */ - __IOM uint32_t RS485_CLASH_INT_ENA : 1; /*!< This is the enable bit for rs485_clash_int_st register. */ - __IOM uint32_t AT_CMD_CHAR_DET_INT_ENA : 1;/*!< This is the enable bit for at_cmd_char_det_int_st register. */ - __IOM uint32_t WAKEUP_INT_ENA : 1; /*!< This is the enable bit for uart_wakeup_int_st register. */ - uint32_t : 12; - } bit; - } INT_ENA; - - union { - __IOM uint32_t reg; /*!< Interrupt clear bits */ - - struct { - __OM uint32_t RXFIFO_FULL_INT_CLR : 1; /*!< Set this bit to clear the rxfifo_full_int_raw interrupt. */ - __OM uint32_t TXFIFO_EMPTY_INT_CLR : 1; /*!< Set this bit to clear txfifo_empty_int_raw interrupt. */ - __OM uint32_t PARITY_ERR_INT_CLR : 1; /*!< Set this bit to clear parity_err_int_raw interrupt. */ - __OM uint32_t FRM_ERR_INT_CLR : 1; /*!< Set this bit to clear frm_err_int_raw interrupt. */ - __OM uint32_t RXFIFO_OVF_INT_CLR : 1; /*!< Set this bit to clear rxfifo_ovf_int_raw interrupt. */ - __OM uint32_t DSR_CHG_INT_CLR : 1; /*!< Set this bit to clear the dsr_chg_int_raw interrupt. */ - __OM uint32_t CTS_CHG_INT_CLR : 1; /*!< Set this bit to clear the cts_chg_int_raw interrupt. */ - __OM uint32_t BRK_DET_INT_CLR : 1; /*!< Set this bit to clear the brk_det_int_raw interrupt. */ - __OM uint32_t RXFIFO_TOUT_INT_CLR : 1; /*!< Set this bit to clear the rxfifo_tout_int_raw interrupt. */ - __OM uint32_t SW_XON_INT_CLR : 1; /*!< Set this bit to clear the sw_xon_int_raw interrupt. */ - __OM uint32_t SW_XOFF_INT_CLR : 1; /*!< Set this bit to clear the sw_xoff_int_raw interrupt. */ - __OM uint32_t GLITCH_DET_INT_CLR : 1; /*!< Set this bit to clear the glitch_det_int_raw interrupt. */ - __OM uint32_t TX_BRK_DONE_INT_CLR : 1; /*!< Set this bit to clear the tx_brk_done_int_raw interrupt.. */ - __OM uint32_t TX_BRK_IDLE_DONE_INT_CLR : 1;/*!< Set this bit to clear the tx_brk_idle_done_int_raw interrupt. */ - __OM uint32_t TX_DONE_INT_CLR : 1; /*!< Set this bit to clear the tx_done_int_raw interrupt. */ - __OM uint32_t RS485_PARITY_ERR_INT_CLR : 1;/*!< Set this bit to clear the rs485_parity_err_int_raw interrupt. */ - __OM uint32_t RS485_FRM_ERR_INT_CLR : 1; /*!< Set this bit to clear the rs485_frm_err_int_raw interrupt. */ - __OM uint32_t RS485_CLASH_INT_CLR : 1; /*!< Set this bit to clear the rs485_clash_int_raw interrupt. */ - __OM uint32_t AT_CMD_CHAR_DET_INT_CLR : 1;/*!< Set this bit to clear the at_cmd_char_det_int_raw interrupt. */ - __OM uint32_t WAKEUP_INT_CLR : 1; /*!< Set this bit to clear the uart_wakeup_int_raw interrupt. */ - uint32_t : 12; - } bit; - } INT_CLR; - - union { - __IOM uint32_t reg; /*!< Clock divider configuration */ - - struct { - __IOM uint32_t CLKDIV : 12; /*!< The integral part of the frequency divider factor. */ - uint32_t : 8; - __IOM uint32_t CLKDIV_FRAG : 4; /*!< The decimal part of the frequency divider factor. */ - uint32_t : 8; - } bit; - } CLKDIV_SYNC; - - union { - __IOM uint32_t reg; /*!< Rx Filter configuration */ - - struct { - __IOM uint32_t GLITCH_FILT : 8; /*!< when input pulse width is lower than this value the pulse is - ignored. */ - __IOM uint32_t GLITCH_FILT_EN : 1; /*!< Set this bit to enable Rx signal filter. */ - uint32_t : 23; - } bit; - } RX_FILT; - - union { - __IOM uint32_t reg; /*!< UART status register */ - - struct { - __IM uint32_t RXFIFO_CNT : 8; /*!< Stores the byte number of valid data in Rx-FIFO. */ - uint32_t : 5; - __IM uint32_t DSRN : 1; /*!< The register represent the level value of the internal uart - dsr signal. */ - __IM uint32_t CTSN : 1; /*!< This register represent the level value of the internal uart - cts signal. */ - __IM uint32_t RXD : 1; /*!< This register represent the level value of the internal uart - rxd signal. */ - __IM uint32_t TXFIFO_CNT : 8; /*!< Stores the byte number of data in Tx-FIFO. */ - uint32_t : 5; - __IM uint32_t DTRN : 1; /*!< This bit represents the level of the internal uart dtr signal. */ - __IM uint32_t RTSN : 1; /*!< This bit represents the level of the internal uart rts signal. */ - __IM uint32_t TXD : 1; /*!< This bit represents the level of the internal uart txd signal. */ - } bit; - } STATUS; - - union { - __IOM uint32_t reg; /*!< a */ - - struct { - __IOM uint32_t PARITY : 1; /*!< This register is used to configure the parity check mode. */ - __IOM uint32_t PARITY_EN : 1; /*!< Set this bit to enable uart parity check. */ - __IOM uint32_t BIT_NUM : 2; /*!< This register is used to set the length of data. */ - __IOM uint32_t STOP_BIT_NUM : 2; /*!< This register is used to set the length of stop bit. */ - __IOM uint32_t TXD_BRK : 1; /*!< Set this bit to enbale transmitter to send NULL when the process - of sending data is done. */ - __IOM uint32_t IRDA_DPLX : 1; /*!< Set this bit to enable IrDA loopback mode. */ - __IOM uint32_t IRDA_TX_EN : 1; /*!< This is the start enable bit for IrDA transmitter. */ - __IOM uint32_t IRDA_WCTL : 1; /*!< 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. - 1'h0: Set IrDA transmitter's 11th bit to 0. */ - __IOM uint32_t IRDA_TX_INV : 1; /*!< Set this bit to invert the level of IrDA transmitter. */ - __IOM uint32_t IRDA_RX_INV : 1; /*!< Set this bit to invert the level of IrDA receiver. */ - __IOM uint32_t LOOPBACK : 1; /*!< Set this bit to enable uart loopback test mode. */ - __IOM uint32_t TX_FLOW_EN : 1; /*!< Set this bit to enable flow control function for transmitter. */ - __IOM uint32_t IRDA_EN : 1; /*!< Set this bit to enable IrDA protocol. */ - __IOM uint32_t RXD_INV : 1; /*!< Set this bit to inverse the level value of uart rxd signal. */ - __IOM uint32_t TXD_INV : 1; /*!< Set this bit to inverse the level value of uart txd signal. */ - __IOM uint32_t DIS_RX_DAT_OVF : 1; /*!< Disable UART Rx data overflow detect. */ - __IOM uint32_t ERR_WR_MASK : 1; /*!< 1'h1: Receiver stops storing data into FIFO when data is wrong. - 1'h0: Receiver stores the data even if the received data - is wrong. */ - __IOM uint32_t AUTOBAUD_EN : 1; /*!< This is the enable bit for detecting baudrate. */ - __IOM uint32_t MEM_CLK_EN : 1; /*!< UART memory clock gate enable signal. */ - __IOM uint32_t SW_RTS : 1; /*!< This register is used to configure the software rts signal which - is used in software flow control. */ - __IOM uint32_t RXFIFO_RST : 1; /*!< Set this bit to reset the uart receive-FIFO. */ - __IOM uint32_t TXFIFO_RST : 1; /*!< Set this bit to reset the uart transmit-FIFO. */ - uint32_t : 8; - } bit; - } CONF0_SYNC; - - union { - __IOM uint32_t reg; /*!< Configuration register 1 */ - - struct { - __IOM uint32_t RXFIFO_FULL_THRHD : 8; /*!< It will produce rxfifo_full_int interrupt when receiver receives - more data than this register value. */ - __IOM uint32_t TXFIFO_EMPTY_THRHD : 8; /*!< It will produce txfifo_empty_int interrupt when the data amount - in Tx-FIFO is less than this register value. */ - __IOM uint32_t CTS_INV : 1; /*!< Set this bit to inverse the level value of uart cts signal. */ - __IOM uint32_t DSR_INV : 1; /*!< Set this bit to inverse the level value of uart dsr signal. */ - __IOM uint32_t RTS_INV : 1; /*!< Set this bit to inverse the level value of uart rts signal. */ - __IOM uint32_t DTR_INV : 1; /*!< Set this bit to inverse the level value of uart dtr signal. */ - __IOM uint32_t SW_DTR : 1; /*!< This register is used to configure the software dtr signal which - is used in software flow control. */ - __IOM uint32_t CLK_EN : 1; /*!< 1'h1: Force clock on for register. 1'h0: Support clock only - when application writes registers. */ - uint32_t : 10; - } bit; - } CONF1; - __IM uint32_t RESERVED; - - union { - __IOM uint32_t reg; /*!< Hardware flow-control configuration */ - - struct { - __IOM uint32_t RX_FLOW_THRHD : 8; /*!< This register is used to configure the maximum amount of data - that can be received when hardware flow control works. */ - __IOM uint32_t RX_FLOW_EN : 1; /*!< This is the flow enable bit for UART receiver. */ - uint32_t : 23; - } bit; - } HWFC_CONF_SYNC; - - union { - __IOM uint32_t reg; /*!< UART sleep configure register 0 */ - - struct { - __IOM uint32_t WK_CHAR1 : 8; /*!< This register restores the specified wake up char1 to wake up */ - __IOM uint32_t WK_CHAR2 : 8; /*!< This register restores the specified wake up char2 to wake up */ - __IOM uint32_t WK_CHAR3 : 8; /*!< This register restores the specified wake up char3 to wake up */ - __IOM uint32_t WK_CHAR4 : 8; /*!< This register restores the specified wake up char4 to wake up */ - } bit; - } SLEEP_CONF0; - - union { - __IOM uint32_t reg; /*!< UART sleep configure register 1 */ - - struct { - __IOM uint32_t WK_CHAR0 : 8; /*!< This register restores the specified char0 to wake up */ - uint32_t : 24; - } bit; - } SLEEP_CONF1; - - union { - __IOM uint32_t reg; /*!< UART sleep configure register 2 */ - - struct { - __IOM uint32_t ACTIVE_THRESHOLD : 10; /*!< The uart is activated from light sleeping mode when the input - rxd edge changes more times than this register value. */ - __IOM uint32_t RX_WAKE_UP_THRHD : 8; /*!< In wake up mode 1 this field is used to set the received data - number threshold to wake up chip. */ - __IOM uint32_t WK_CHAR_NUM : 3; /*!< This register is used to select number of wake up char. */ - __IOM uint32_t WK_CHAR_MASK : 5; /*!< This register is used to mask wake up char. */ - __IOM uint32_t WK_MODE_SEL : 2; /*!< This register is used to select wake up mode. 0: RXD toggling - to wake up. 1: received data number larger than */ - uint32_t : 4; - } bit; - } SLEEP_CONF2; - - union { - __IOM uint32_t reg; /*!< Software flow-control character configuration */ - - struct { - __IOM uint32_t XON_CHAR : 8; /*!< This register stores the Xon flow control char. */ - __IOM uint32_t XOFF_CHAR : 8; /*!< This register stores the Xoff flow control char. */ - __IOM uint32_t XON_XOFF_STILL_SEND : 1; /*!< In software flow control mode, UART Tx is disabled once UART - Rx receives XOFF. In this status, UART Tx can not transmit - XOFF even the received data number is larger than UART_XOFF_THRESHOLD. - Set this bit to enable UART Tx can transmit XON/XOFF when - UART Tx is disabled. */ - __IOM uint32_t SW_FLOW_CON_EN : 1; /*!< Set this bit to enable software flow control. It is used with - register sw_xon or sw_xoff. */ - __IOM uint32_t XONOFF_DEL : 1; /*!< Set this bit to remove flow control char from the received data. */ - __IOM uint32_t FORCE_XON : 1; /*!< Set this bit to enable the transmitter to go on sending data. */ - __IOM uint32_t FORCE_XOFF : 1; /*!< Set this bit to stop the transmitter from sending data. */ - __IOM uint32_t SEND_XON : 1; /*!< Set this bit to send Xon char. It is cleared by hardware automatically. */ - __IOM uint32_t SEND_XOFF : 1; /*!< Set this bit to send Xoff char. It is cleared by hardware automatically. */ - uint32_t : 9; - } bit; - } SWFC_CONF0_SYNC; - - union { - __IOM uint32_t reg; /*!< Software flow-control character configuration */ - - struct { - __IOM uint32_t XON_THRESHOLD : 8; /*!< When the data amount in Rx-FIFO is less than this register value - with uart_sw_flow_con_en set to 1 it will send a Xon char. */ - __IOM uint32_t XOFF_THRESHOLD : 8; /*!< When the data amount in Rx-FIFO is more than this register value - with uart_sw_flow_con_en set to 1 it will send a Xoff char. */ - uint32_t : 16; - } bit; - } SWFC_CONF1; - - union { - __IOM uint32_t reg; /*!< Tx Break character configuration */ - - struct { - __IOM uint32_t TX_BRK_NUM : 8; /*!< This register is used to configure the number of 0 to be sent - after the process of sending data is done. It is active - when txd_brk is set to 1. */ - uint32_t : 24; - } bit; - } TXBRK_CONF_SYNC; - - union { - __IOM uint32_t reg; /*!< Frame-end idle configuration */ - - struct { - __IOM uint32_t RX_IDLE_THRHD : 10; /*!< It will produce frame end signal when receiver takes more time - to receive one byte data than this register value. */ - __IOM uint32_t TX_IDLE_NUM : 10; /*!< This register is used to configure the duration time between - transfers. */ - uint32_t : 12; - } bit; - } IDLE_CONF_SYNC; - - union { - __IOM uint32_t reg; /*!< RS485 mode configuration */ - - struct { - __IOM uint32_t RS485_EN : 1; /*!< Set this bit to choose the rs485 mode. */ - __IOM uint32_t DL0_EN : 1; /*!< Set this bit to delay the stop bit by 1 bit. */ - __IOM uint32_t DL1_EN : 1; /*!< Set this bit to delay the stop bit by 1 bit. */ - __IOM uint32_t RS485TX_RX_EN : 1; /*!< Set this bit to enable receiver could receive data when the - transmitter is transmitting data in rs485 mode. */ - __IOM uint32_t RS485RXBY_TX_EN : 1; /*!< 1'h1: enable rs485 transmitter to send data when rs485 receiver - line is busy. */ - __IOM uint32_t RS485_RX_DLY_NUM : 1; /*!< This register is used to delay the receiver's internal data - signal. */ - __IOM uint32_t RS485_TX_DLY_NUM : 4; /*!< This register is used to delay the transmitter's internal data - signal. */ - uint32_t : 22; - } bit; - } RS485_CONF_SYNC; - - union { - __IOM uint32_t reg; /*!< Pre-sequence timing configuration */ - - struct { - __IOM uint32_t PRE_IDLE_NUM : 16; /*!< This register is used to configure the idle duration time before - the first at_cmd is received by receiver. */ - uint32_t : 16; - } bit; - } AT_CMD_PRECNT_SYNC; - - union { - __IOM uint32_t reg; /*!< Post-sequence timing configuration */ - - struct { - __IOM uint32_t POST_IDLE_NUM : 16; /*!< This register is used to configure the duration time between - the last at_cmd and the next data. */ - uint32_t : 16; - } bit; - } AT_CMD_POSTCNT_SYNC; - - union { - __IOM uint32_t reg; /*!< Timeout configuration */ - - struct { - __IOM uint32_t RX_GAP_TOUT : 16; /*!< This register is used to configure the duration time between - the at_cmd chars. */ - uint32_t : 16; - } bit; - } AT_CMD_GAPTOUT_SYNC; - - union { - __IOM uint32_t reg; /*!< AT escape sequence detection configuration */ - - struct { - __IOM uint32_t AT_CMD_CHAR : 8; /*!< This register is used to configure the content of at_cmd char. */ - __IOM uint32_t CHAR_NUM : 8; /*!< This register is used to configure the num of continuous at_cmd - chars received by receiver. */ - uint32_t : 16; - } bit; - } AT_CMD_CHAR_SYNC; - - union { - __IOM uint32_t reg; /*!< UART memory power configuration */ - - struct { - uint32_t : 25; - __IOM uint32_t MEM_FORCE_PD : 1; /*!< Set this bit to force power down UART memory. */ - __IOM uint32_t MEM_FORCE_PU : 1; /*!< Set this bit to force power up UART memory. */ - uint32_t : 5; - } bit; - } MEM_CONF; - - union { - __IOM uint32_t reg; /*!< UART threshold and allocation configuration */ - - struct { - __IOM uint32_t RX_TOUT_EN : 1; /*!< This is the enble bit for uart receiver's timeout function. */ - __IOM uint32_t RX_TOUT_FLOW_DIS : 1; /*!< Set this bit to stop accumulating idle_cnt when hardware flow - control works. */ - __IOM uint32_t RX_TOUT_THRHD : 10; /*!< This register is used to configure the threshold time that receiver - takes to receive one byte. The rxfifo_tout_int interrupt - will be trigger when the receiver takes more time to receive - one byte with rx_tout_en set to 1. */ - uint32_t : 20; - } bit; - } TOUT_CONF_SYNC; - - union { - __IOM uint32_t reg; /*!< Tx-SRAM write and read offset address. */ - - struct { - __IM uint32_t TX_SRAM_WADDR : 8; /*!< This register stores the offset write address in Tx-SRAM. */ - uint32_t : 1; - __IM uint32_t TX_SRAM_RADDR : 8; /*!< This register stores the offset read address in Tx-SRAM. */ - uint32_t : 15; - } bit; - } MEM_TX_STATUS; - - union { - __IOM uint32_t reg; /*!< Rx-SRAM write and read offset address. */ - - struct { - __IM uint32_t RX_SRAM_RADDR : 8; /*!< This register stores the offset read address in RX-SRAM. */ - uint32_t : 1; - __IM uint32_t RX_SRAM_WADDR : 8; /*!< This register stores the offset write address in Rx-SRAM. */ - uint32_t : 15; - } bit; - } MEM_RX_STATUS; - - union { - __IOM uint32_t reg; /*!< UART transmit and receive status. */ - - struct { - __IM uint32_t ST_URX_OUT : 4; /*!< This is the status register of receiver. */ - __IM uint32_t ST_UTX_OUT : 4; /*!< This is the status register of transmitter. */ - uint32_t : 24; - } bit; - } FSM_STATUS; - - union { - __IOM uint32_t reg; /*!< Autobaud high pulse register */ - - struct { - __IM uint32_t POSEDGE_MIN_CNT : 12; /*!< This register stores the minimal input clock count between two - positive edges. It is used in boudrate-detect process. */ - uint32_t : 20; - } bit; - } POSPULSE; - - union { - __IOM uint32_t reg; /*!< Autobaud low pulse register */ - - struct { - __IM uint32_t NEGEDGE_MIN_CNT : 12; /*!< This register stores the minimal input clock count between two - negative edges. It is used in boudrate-detect process. */ - uint32_t : 20; - } bit; - } NEGPULSE; - - union { - __IOM uint32_t reg; /*!< Autobaud minimum low pulse duration register */ - - struct { - __IM uint32_t MIN_CNT : 12; /*!< This register stores the value of the minimum duration time - of the low level pulse. It is used in baud rate-detect - process. */ - uint32_t : 20; - } bit; - } LOWPULSE; - - union { - __IOM uint32_t reg; /*!< Autobaud minimum high pulse duration register */ - - struct { - __IM uint32_t MIN_CNT : 12; /*!< This register stores the value of the maxinum duration time - for the high level pulse. It is used in baud rate-detect - process. */ - uint32_t : 20; - } bit; - } HIGHPULSE; - - union { - __IOM uint32_t reg; /*!< Autobaud edge change count register */ - - struct { - __IM uint32_t RXD_EDGE_CNT : 10; /*!< This register stores the count of rxd edge change. It is used - in baud rate-detect process. */ - uint32_t : 22; - } bit; - } RXD_CNT; - - union { - __IOM uint32_t reg; /*!< UART core clock configuration */ - - struct { - uint32_t : 24; - __IOM uint32_t TX_SCLK_EN : 1; /*!< Set this bit to enable UART Tx clock. */ - __IOM uint32_t RX_SCLK_EN : 1; /*!< Set this bit to enable UART Rx clock. */ - __IOM uint32_t TX_RST_CORE : 1; /*!< Write 1 then write 0 to this bit to reset UART Tx. */ - __IOM uint32_t RX_RST_CORE : 1; /*!< Write 1 then write 0 to this bit to reset UART Rx. */ - uint32_t : 4; - } bit; - } CLK_CONF; - - union { - __IOM uint32_t reg; /*!< UART Version register */ - - struct { - __IOM uint32_t DATE : 32; /*!< This is the version register. */ - } bit; - } DATE; - - union { - __IOM uint32_t reg; /*!< UART AFIFO Status */ - - struct { - __IM uint32_t TX_AFIFO_FULL : 1; /*!< Full signal of APB TX AFIFO. */ - __IM uint32_t TX_AFIFO_EMPTY : 1; /*!< Empty signal of APB TX AFIFO. */ - __IM uint32_t RX_AFIFO_FULL : 1; /*!< Full signal of APB RX AFIFO. */ - __IM uint32_t RX_AFIFO_EMPTY : 1; /*!< Empty signal of APB RX AFIFO. */ - uint32_t : 28; - } bit; - } AFIFO_STATUS; - __IM uint32_t RESERVED1; - - union { - __IOM uint32_t reg; /*!< UART Registers Configuration Update register */ - - struct { - __IOM uint32_t REG_UPDATE : 1; /*!< Software write 1 would synchronize registers into UART Core - clock domain and would be cleared by hardware after synchronization - is done. */ - uint32_t : 31; - } bit; - } REG_UPDATE; - - union { - __IOM uint32_t reg; /*!< UART ID register */ - - struct { - __IOM uint32_t ID : 32; /*!< This register is used to configure the uart_id. */ - } bit; - } ID; -} UART0_Type; /*!< Size = 160 (0xa0) */ - - - -/* =========================================================================================================================== */ -/* ================ UHCI0 ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Universal Host Controller Interface 0 (UHCI0) - */ - -typedef struct { /*!< UHCI0 Structure */ - - union { - __IOM uint32_t reg; /*!< UHCI Configuration Register0 */ - - struct { - __IOM uint32_t TX_RST : 1; /*!< Write 1 then write 0 to this bit to reset decode state machine. */ - __IOM uint32_t RX_RST : 1; /*!< Write 1 then write 0 to this bit to reset encode state machine. */ - __IOM uint32_t UART_SEL : 3; /*!< Select which uart to connect with GDMA. */ - __IOM uint32_t SEPER_EN : 1; /*!< Set this bit to separate the data frame using a special char. */ - __IOM uint32_t HEAD_EN : 1; /*!< Set this bit to encode the data packet with a formatting header. */ - __IOM uint32_t CRC_REC_EN : 1; /*!< Set this bit to enable UHCI to receive the 16 bit CRC. */ - __IOM uint32_t UART_IDLE_EOF_EN : 1; /*!< If this bit is set to 1 UHCI will end the payload receiving - process when UART has been in idle state. */ - __IOM uint32_t LEN_EOF_EN : 1; /*!< If this bit is set to 1 UHCI decoder receiving payload data - is end when the receiving byte count has reached the specified - value. The value is payload length indicated by UHCI packet - header when UHCI_HEAD_EN is 1 or the value is configuration - value when UHCI_HEAD_EN is 0. If this bit is set to 0 UHCI - decoder receiving payload data is end when 0xc0 is received. */ - __IOM uint32_t ENCODE_CRC_EN : 1; /*!< Set this bit to enable data integrity checking by appending - a 16 bit CCITT-CRC to end of the payload. */ - __IOM uint32_t CLK_EN : 1; /*!< 1'b1: Force clock on for register. 1'b0: Support clock only - when application writes registers. */ - __IOM uint32_t UART_RX_BRK_EOF_EN : 1; /*!< If this bit is set to 1 UHCI will end payload receive process - when NULL frame is received by UART. */ - uint32_t : 19; - } bit; - } CONF0; - - union { - __IOM uint32_t reg; /*!< UHCI Interrupt Raw Register */ - - struct { - __IOM uint32_t RX_START_INT_RAW : 1; /*!< Indicates the raw interrupt of UHCI_RX_START_INT. Interrupt - will be triggered when delimiter is sent successfully. */ - __IOM uint32_t TX_START_INT_RAW : 1; /*!< Indicates the raw interrupt of UHCI_TX_START_INT. Interrupt - will be triggered when DMA detects delimiter. */ - __IOM uint32_t RX_HUNG_INT_RAW : 1; /*!< Indicates the raw interrupt of UHCI_RX_HUNG_INT. Interrupt will - be triggered when the required time of DMA receiving data - exceeds the configuration value. */ - __IOM uint32_t TX_HUNG_INT_RAW : 1; /*!< Indicates the raw interrupt of UHCI_TX_HUNG_INT. Interrupt will - be triggered when the required time of DMA reading RAM - data exceeds the configuration value. */ - __IOM uint32_t SEND_S_REG_Q_INT_RAW : 1; /*!< Indicates the raw interrupt of UHCI_SEND_S_REG_Q_INT. Interrupt - will be triggered when UHCI sends short packet successfully - with single_send mode. */ - __IOM uint32_t SEND_A_REG_Q_INT_RAW : 1; /*!< Indicates the raw interrupt of UHCI_SEND_A_REG_Q_INT. Interrupt - will be triggered when UHCI sends short packet successfully - with always_send mode. */ - __IOM uint32_t OUT_EOF_INT_RAW : 1; /*!< Indicates the raw interrupt of UHCI_OUT_EOF_INT. Interrupt will - be triggered when there are errors in EOF. */ - __IOM uint32_t APP_CTRL0_INT_RAW : 1; /*!< Indicates the raw interrupt of UHCI_APP_CTRL0_INT. Interrupt - will be triggered when UHCI_APP_CTRL0_IN_SET is set to - 1. */ - __IOM uint32_t APP_CTRL1_INT_RAW : 1; /*!< Indicates the raw interrupt of UHCI_APP_CTRL1_INT. Interrupt - will be triggered when UHCI_APP_CTRL1_IN_SET is set to - 1. */ - uint32_t : 23; - } bit; - } INT_RAW; - - union { - __IOM uint32_t reg; /*!< UHCI Interrupt Status Register */ - - struct { - __IM uint32_t RX_START_INT_ST : 1; /*!< Indicates the interrupt status of UHCI_RX_START_INT. */ - __IM uint32_t TX_START_INT_ST : 1; /*!< Indicates the interrupt status of UHCI_TX_START_INT. */ - __IM uint32_t RX_HUNG_INT_ST : 1; /*!< Indicates the interrupt status of UHCI_RX_HUNG_INT. */ - __IM uint32_t TX_HUNG_INT_ST : 1; /*!< Indicates the interrupt status of UHCI_TX_HUNG_INT. */ - __IM uint32_t SEND_S_REG_Q_INT_ST : 1; /*!< Indicates the interrupt status of UHCI_SEND_S_REG_Q_INT. */ - __IM uint32_t SEND_A_REG_Q_INT_ST : 1; /*!< Indicates the interrupt status of UHCI_SEND_A_REG_Q_INT. */ - __IM uint32_t OUTLINK_EOF_ERR_INT_ST : 1;/*!< Indicates the interrupt status of UHCI_OUT_EOF_INT. */ - __IM uint32_t APP_CTRL0_INT_ST : 1; /*!< Indicates the interrupt status of UHCI_APP_CTRL0_INT. */ - __IM uint32_t APP_CTRL1_INT_ST : 1; /*!< Indicates the interrupt status of UHCI_APP_CTRL1_INT. */ - uint32_t : 23; - } bit; - } INT_ST; - - union { - __IOM uint32_t reg; /*!< UHCI Interrupt Enable Register */ - - struct { - __IOM uint32_t RX_START_INT_ENA : 1; /*!< Set this bit to enable the interrupt of UHCI_RX_START_INT. */ - __IOM uint32_t TX_START_INT_ENA : 1; /*!< Set this bit to enable the interrupt of UHCI_TX_START_INT. */ - __IOM uint32_t RX_HUNG_INT_ENA : 1; /*!< Set this bit to enable the interrupt of UHCI_RX_HUNG_INT. */ - __IOM uint32_t TX_HUNG_INT_ENA : 1; /*!< Set this bit to enable the interrupt of UHCI_TX_HUNG_INT. */ - __IOM uint32_t SEND_S_REG_Q_INT_ENA : 1; /*!< Set this bit to enable the interrupt of UHCI_SEND_S_REG_Q_INT. */ - __IOM uint32_t SEND_A_REG_Q_INT_ENA : 1; /*!< Set this bit to enable the interrupt of UHCI_SEND_A_REG_Q_INT. */ - __IOM uint32_t OUTLINK_EOF_ERR_INT_ENA : 1;/*!< Set this bit to enable the interrupt of UHCI_OUT_EOF_INT. */ - __IOM uint32_t APP_CTRL0_INT_ENA : 1; /*!< Set this bit to enable the interrupt of UHCI_APP_CTRL0_INT. */ - __IOM uint32_t APP_CTRL1_INT_ENA : 1; /*!< Set this bit to enable the interrupt of UHCI_APP_CTRL1_INT. */ - uint32_t : 23; - } bit; - } INT_ENA; - - union { - __IOM uint32_t reg; /*!< UHCI Interrupt Clear Register */ - - struct { - __OM uint32_t RX_START_INT_CLR : 1; /*!< Set this bit to clear the raw interrupt of UHCI_RX_START_INT. */ - __OM uint32_t TX_START_INT_CLR : 1; /*!< Set this bit to clear the raw interrupt of UHCI_TX_START_INT. */ - __OM uint32_t RX_HUNG_INT_CLR : 1; /*!< Set this bit to clear the raw interrupt of UHCI_RX_HUNG_INT. */ - __OM uint32_t TX_HUNG_INT_CLR : 1; /*!< Set this bit to clear the raw interrupt of UHCI_TX_HUNG_INT. */ - __OM uint32_t SEND_S_REG_Q_INT_CLR : 1; /*!< Set this bit to clear the raw interrupt of UHCI_SEND_S_REG_Q_INT. */ - __OM uint32_t SEND_A_REG_Q_INT_CLR : 1; /*!< Set this bit to clear the raw interrupt of UHCI_SEND_A_REG_Q_INT. */ - __OM uint32_t OUTLINK_EOF_ERR_INT_CLR : 1;/*!< Set this bit to clear the raw interrupt of UHCI_OUT_EOF_INT. */ - __OM uint32_t APP_CTRL0_INT_CLR : 1; /*!< Set this bit to clear the raw interrupt of UHCI_APP_CTRL0_INT. */ - __OM uint32_t APP_CTRL1_INT_CLR : 1; /*!< Set this bit to clear the raw interrupt of UHCI_APP_CTRL1_INT. */ - uint32_t : 23; - } bit; - } INT_CLR; - - union { - __IOM uint32_t reg; /*!< UHCI Configuration Register1 */ - - struct { - __IOM uint32_t CHECK_SUM_EN : 1; /*!< Set this bit to enable head checksum check when receiving. */ - __IOM uint32_t CHECK_SEQ_EN : 1; /*!< Set this bit to enable sequence number check when receiving. */ - __IOM uint32_t CRC_DISABLE : 1; /*!< Set this bit to support CRC calculation, and data integrity - check bit should 1. */ - __IOM uint32_t SAVE_HEAD : 1; /*!< Set this bit to save data packet head when UHCI receive data. */ - __IOM uint32_t TX_CHECK_SUM_RE : 1; /*!< Set this bit to encode data packet with checksum. */ - __IOM uint32_t TX_ACK_NUM_RE : 1; /*!< Set this bit to encode data packet with ACK when reliable data - packet is ready. */ - uint32_t : 1; - __IOM uint32_t WAIT_SW_START : 1; /*!< Set this bit to enable UHCI encoder transfer to ST_SW_WAIT status. */ - __OM uint32_t SW_START : 1; /*!< Set this bit to transmit data packet if UCHI_ENCODE_STATE is - ST_SW_WAIT. */ - uint32_t : 23; - } bit; - } CONF1; - - union { - __IOM uint32_t reg; /*!< UHCI Receive Status Register */ - - struct { - __IM uint32_t RX_ERR_CAUSE : 3; /*!< Indicates the error types when DMA receives the error frame. - 3'b001: UHCI packet checksum error. 3'b010: UHCI packet - sequence number error. 3'b011: UHCI packet CRC bit error. - 3'b100: find 0xC0, but received packet is uncompleted. - 3'b101: 0xC0 is not found, but received packet is completed. - 3'b110: CRC check error. */ - __IM uint32_t DECODE_STATE : 3; /*!< Indicates UHCI decoder status. */ - uint32_t : 26; - } bit; - } STATE0; - - union { - __IOM uint32_t reg; /*!< UHCI Transmit Status Register */ - - struct { - __IM uint32_t ENCODE_STATE : 3; /*!< Indicates UHCI encoder status. */ - uint32_t : 29; - } bit; - } STATE1; - - union { - __IOM uint32_t reg; /*!< UHCI Escapes Configuration Register0 */ - - struct { - __IOM uint32_t TX_C0_ESC_EN : 1; /*!< Set this bit to enable resolve char 0xC0 when DMA receiving - data. */ - __IOM uint32_t TX_DB_ESC_EN : 1; /*!< Set this bit to enable resolve char 0xDB when DMA receiving - data. */ - __IOM uint32_t TX_11_ESC_EN : 1; /*!< Set this bit to enable resolve flow control char 0x11 when DMA - receiving data. */ - __IOM uint32_t TX_13_ESC_EN : 1; /*!< Set this bit to enable resolve flow control char 0x13 when DMA - receiving data. */ - __IOM uint32_t RX_C0_ESC_EN : 1; /*!< Set this bit to enable replacing 0xC0 with special char when - DMA receiving data. */ - __IOM uint32_t RX_DB_ESC_EN : 1; /*!< Set this bit to enable replacing 0xDB with special char when - DMA receiving data. */ - __IOM uint32_t RX_11_ESC_EN : 1; /*!< Set this bit to enable replacing 0x11 with special char when - DMA receiving data. */ - __IOM uint32_t RX_13_ESC_EN : 1; /*!< Set this bit to enable replacing 0x13 with special char when - DMA receiving data. */ - uint32_t : 24; - } bit; - } ESCAPE_CONF; - - union { - __IOM uint32_t reg; /*!< UHCI Hung Configuration Register0 */ - - struct { - __IOM uint32_t TXFIFO_TIMEOUT : 8; /*!< Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for - timeout when receiving data. */ - __IOM uint32_t TXFIFO_TIMEOUT_SHIFT : 3; /*!< Configures the maximum counter value. */ - __IOM uint32_t TXFIFO_TIMEOUT_ENA : 1; /*!< Set this bit to enable TX FIFO timeout when receiving. */ - __IOM uint32_t RXFIFO_TIMEOUT : 8; /*!< Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for - timeout when reading RAM data. */ - __IOM uint32_t RXFIFO_TIMEOUT_SHIFT : 3; /*!< Configures the maximum counter value. */ - __IOM uint32_t RXFIFO_TIMEOUT_ENA : 1; /*!< Set this bit to enable TX FIFO timeout when DMA sending data. */ - uint32_t : 8; - } bit; - } HUNG_CONF; - - union { - __IOM uint32_t reg; /*!< UHCI Ack Value Configuration Register0 */ - - struct { - __IOM uint32_t ACK_NUM : 3; /*!< Indicates the ACK number during software flow control. */ - __OM uint32_t LOAD : 1; /*!< Set this bit to load the ACK value of UHCI_ACK_NUM. */ - uint32_t : 28; - } bit; - } ACK_NUM; - - union { - __IOM uint32_t reg; /*!< UHCI Head Register */ - - struct { - __IM uint32_t RX_HEAD : 32; /*!< Stores the head of received packet. */ - } bit; - } RX_HEAD; - - union { - __IOM uint32_t reg; /*!< UCHI Quick send Register */ - - struct { - __IOM uint32_t SINGLE_SEND_NUM : 3; /*!< Configures single_send mode. */ - __OM uint32_t SINGLE_SEND_EN : 1; /*!< Set this bit to enable sending short packet with single_send - mode. */ - __IOM uint32_t ALWAYS_SEND_NUM : 3; /*!< Configures always_send mode. */ - __IOM uint32_t ALWAYS_SEND_EN : 1; /*!< Set this bit to enable sending short packet with always_send - mode. */ - uint32_t : 24; - } bit; - } QUICK_SENT; - - union { - __IOM uint32_t reg; /*!< UHCI Q0_WORD0 Quick Send Register */ - - struct { - __IOM uint32_t SEND_Q0_WORD0 : 32; /*!< Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM - or UHCI_SINGLE_SEND_NUM. */ - } bit; - } REG_Q0_WORD0; - - union { - __IOM uint32_t reg; /*!< UHCI Q0_WORD1 Quick Send Register */ - - struct { - __IOM uint32_t SEND_Q0_WORD1 : 32; /*!< Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM - or UHCI_SINGLE_SEND_NUM. */ - } bit; - } REG_Q0_WORD1; - - union { - __IOM uint32_t reg; /*!< UHCI Q1_WORD0 Quick Send Register */ - - struct { - __IOM uint32_t SEND_Q1_WORD0 : 32; /*!< Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM - or UHCI_SINGLE_SEND_NUM. */ - } bit; - } REG_Q1_WORD0; - - union { - __IOM uint32_t reg; /*!< UHCI Q1_WORD1 Quick Send Register */ - - struct { - __IOM uint32_t SEND_Q1_WORD1 : 32; /*!< Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM - or UHCI_SINGLE_SEND_NUM. */ - } bit; - } REG_Q1_WORD1; - - union { - __IOM uint32_t reg; /*!< UHCI Q2_WORD0 Quick Send Register */ - - struct { - __IOM uint32_t SEND_Q2_WORD0 : 32; /*!< Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM - or UHCI_SINGLE_SEND_NUM. */ - } bit; - } REG_Q2_WORD0; - - union { - __IOM uint32_t reg; /*!< UHCI Q2_WORD1 Quick Send Register */ - - struct { - __IOM uint32_t SEND_Q2_WORD1 : 32; /*!< Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM - or UHCI_SINGLE_SEND_NUM. */ - } bit; - } REG_Q2_WORD1; - - union { - __IOM uint32_t reg; /*!< UHCI Q3_WORD0 Quick Send Register */ - - struct { - __IOM uint32_t SEND_Q3_WORD0 : 32; /*!< Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM - or UHCI_SINGLE_SEND_NUM. */ - } bit; - } REG_Q3_WORD0; - - union { - __IOM uint32_t reg; /*!< UHCI Q3_WORD1 Quick Send Register */ - - struct { - __IOM uint32_t SEND_Q3_WORD1 : 32; /*!< Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM - or UHCI_SINGLE_SEND_NUM. */ - } bit; - } REG_Q3_WORD1; - - union { - __IOM uint32_t reg; /*!< UHCI Q4_WORD0 Quick Send Register */ - - struct { - __IOM uint32_t SEND_Q4_WORD0 : 32; /*!< Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM - or UHCI_SINGLE_SEND_NUM. */ - } bit; - } REG_Q4_WORD0; - - union { - __IOM uint32_t reg; /*!< UHCI Q4_WORD1 Quick Send Register */ - - struct { - __IOM uint32_t SEND_Q4_WORD1 : 32; /*!< Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM - or UHCI_SINGLE_SEND_NUM. */ - } bit; - } REG_Q4_WORD1; - - union { - __IOM uint32_t reg; /*!< UHCI Q5_WORD0 Quick Send Register */ - - struct { - __IOM uint32_t SEND_Q5_WORD0 : 32; /*!< Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM - or UHCI_SINGLE_SEND_NUM. */ - } bit; - } REG_Q5_WORD0; - - union { - __IOM uint32_t reg; /*!< UHCI Q5_WORD1 Quick Send Register */ - - struct { - __IOM uint32_t SEND_Q5_WORD1 : 32; /*!< Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM - or UHCI_SINGLE_SEND_NUM. */ - } bit; - } REG_Q5_WORD1; - - union { - __IOM uint32_t reg; /*!< UHCI Q6_WORD0 Quick Send Register */ - - struct { - __IOM uint32_t SEND_Q6_WORD0 : 32; /*!< Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM - or UHCI_SINGLE_SEND_NUM. */ - } bit; - } REG_Q6_WORD0; - - union { - __IOM uint32_t reg; /*!< UHCI Q6_WORD1 Quick Send Register */ - - struct { - __IOM uint32_t SEND_Q6_WORD1 : 32; /*!< Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM - or UHCI_SINGLE_SEND_NUM. */ - } bit; - } REG_Q6_WORD1; - - union { - __IOM uint32_t reg; /*!< UHCI Escapes Sequence Configuration Register0 */ - - struct { - __IOM uint32_t SEPER_CHAR : 8; /*!< Configures the delimiter for encoding, default value is 0xC0. */ - __IOM uint32_t SEPER_ESC_CHAR0 : 8; /*!< Configures the first char of SLIP escape character, default - value is 0xDB. */ - __IOM uint32_t SEPER_ESC_CHAR1 : 8; /*!< Configures the second char of SLIP escape character, default - value is 0xDC. */ - uint32_t : 8; - } bit; - } ESC_CONF0; - - union { - __IOM uint32_t reg; /*!< UHCI Escapes Sequence Configuration Register1 */ - - struct { - __IOM uint32_t ESC_SEQ0 : 8; /*!< Configures the char needing encoding, which is 0xDB as flow - control char by default. */ - __IOM uint32_t ESC_SEQ0_CHAR0 : 8; /*!< Configures the first char of SLIP escape character, default - value is 0xDB. */ - __IOM uint32_t ESC_SEQ0_CHAR1 : 8; /*!< Configures the second char of SLIP escape character, default - value is 0xDD. */ - uint32_t : 8; - } bit; - } ESC_CONF1; - - union { - __IOM uint32_t reg; /*!< UHCI Escapes Sequence Configuration Register2 */ - - struct { - __IOM uint32_t ESC_SEQ1 : 8; /*!< Configures the char needing encoding, which is 0x11 as flow - control char by default. */ - __IOM uint32_t ESC_SEQ1_CHAR0 : 8; /*!< Configures the first char of SLIP escape character, default - value is 0xDB. */ - __IOM uint32_t ESC_SEQ1_CHAR1 : 8; /*!< Configures the second char of SLIP escape character, default - value is 0xDE. */ - uint32_t : 8; - } bit; - } ESC_CONF2; - - union { - __IOM uint32_t reg; /*!< UHCI Escapes Sequence Configuration Register3 */ - - struct { - __IOM uint32_t ESC_SEQ2 : 8; /*!< Configures the char needing encoding, which is 0x13 as flow - control char by default. */ - __IOM uint32_t ESC_SEQ2_CHAR0 : 8; /*!< Configures the first char of SLIP escape character, default - value is 0xDB. */ - __IOM uint32_t ESC_SEQ2_CHAR1 : 8; /*!< Configures the second char of SLIP escape character, default - value is 0xDF. */ - uint32_t : 8; - } bit; - } ESC_CONF3; - - union { - __IOM uint32_t reg; /*!< UCHI Packet Length Configuration Register */ - - struct { - __IOM uint32_t PKT_THRS : 13; /*!< Configures the data packet's maximum length when UHCI_HEAD_EN - is 0. */ - uint32_t : 19; - } bit; - } PKT_THRES; - - union { - __IOM uint32_t reg; /*!< UHCI Version Register */ - - struct { - __IOM uint32_t DATE : 32; /*!< Configures version. */ - } bit; - } DATE; -} UHCI0_Type; /*!< Size = 132 (0x84) */ - - - -/* =========================================================================================================================== */ -/* ================ USB_DEVICE ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Full-speed USB Serial/JTAG Controller (USB_DEVICE) - */ - -typedef struct { /*!< USB_DEVICE Structure */ - - union { - __IOM uint32_t reg; /*!< FIFO access for the CDC-ACM data IN and OUT endpoints. */ - - struct { - __IM uint32_t USB_SERIAL_JTAG_RDWR_BYTE : 8;/*!< Write and read byte data to/from UART Tx/Rx FIFO through this - field. When USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then - user can write data (up to 64 bytes) into UART Tx FIFO. - When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can - check USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR - to know how many data is received, then read data from - UART Rx FIFO. */ - uint32_t : 24; - } bit; - } EP1; - - union { - __IOM uint32_t reg; /*!< Configuration and control registers for the CDC-ACM FIFOs. */ - - struct { - __OM uint32_t USB_SERIAL_JTAG_WR_DONE : 1;/*!< Set this bit to indicate writing byte data to UART Tx FIFO is - done. */ - __IM uint32_t USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE : 1;/*!< 1'b1: Indicate UART Tx FIFO is not full and can write data into - in. After writing USB_DEVICE_WR_DONE, this bit would be - 0 until data in UART Tx FIFO is read by USB Host. */ - __IM uint32_t USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL : 1;/*!< 1'b1: Indicate there is data in UART Rx FIFO. */ - uint32_t : 29; - } bit; - } EP1_CONF; - - union { - __IOM uint32_t reg; /*!< Interrupt raw status register. */ - - struct { - __IOM uint32_t USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when flush cmd is - received for IN endpoint 2 of JTAG. */ - __IOM uint32_t USB_SERIAL_JTAG_SOF_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when SOF frame is - received. */ - __IOM uint32_t USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when Serial Port OUT - Endpoint received one packet. */ - __IOM uint32_t USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when Serial Port IN - Endpoint is empty. */ - __IOM uint32_t USB_SERIAL_JTAG_PID_ERR_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when pid error is - detected. */ - __IOM uint32_t USB_SERIAL_JTAG_CRC5_ERR_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when CRC5 error is - detected. */ - __IOM uint32_t USB_SERIAL_JTAG_CRC16_ERR_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when CRC16 error is - detected. */ - __IOM uint32_t USB_SERIAL_JTAG_STUFF_ERR_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when stuff error is - detected. */ - __IOM uint32_t USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when IN token for - IN endpoint 1 is received. */ - __IOM uint32_t USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when usb bus reset - is detected. */ - __IOM uint32_t USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when OUT endpoint - 1 received packet with zero palyload. */ - __IOM uint32_t USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when OUT endpoint - 2 received packet with zero palyload. */ - __IOM uint32_t USB_SERIAL_JTAG_RTS_CHG_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when level of RTS - from usb serial channel is changed. */ - __IOM uint32_t USB_SERIAL_JTAG_DTR_CHG_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when level of DTR - from usb serial channel is changed. */ - __IOM uint32_t USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when level of GET - LINE CODING request is received. */ - __IOM uint32_t USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW : 1;/*!< The raw interrupt bit turns to high level when level of SET - LINE CODING request is received. */ - uint32_t : 16; - } bit; - } INT_RAW; - - union { - __IOM uint32_t reg; /*!< Interrupt status register. */ - - struct { - __IM uint32_t USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST : 1;/*!< The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT - interrupt. */ - __IM uint32_t USB_SERIAL_JTAG_SOF_INT_ST : 1;/*!< The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt. */ - __IM uint32_t USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST : 1;/*!< The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT - interrupt. */ - __IM uint32_t USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST : 1;/*!< The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT - interrupt. */ - __IM uint32_t USB_SERIAL_JTAG_PID_ERR_INT_ST : 1;/*!< The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT - interrupt. */ - __IM uint32_t USB_SERIAL_JTAG_CRC5_ERR_INT_ST : 1;/*!< The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT - interrupt. */ - __IM uint32_t USB_SERIAL_JTAG_CRC16_ERR_INT_ST : 1;/*!< The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT - interrupt. */ - __IM uint32_t USB_SERIAL_JTAG_STUFF_ERR_INT_ST : 1;/*!< The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT - interrupt. */ - __IM uint32_t USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST : 1;/*!< The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT - interrupt. */ - __IM uint32_t USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST : 1;/*!< The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT - interrupt. */ - __IM uint32_t USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST : 1;/*!< The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT - interrupt. */ - __IM uint32_t USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST : 1;/*!< The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT - interrupt. */ - __IM uint32_t USB_SERIAL_JTAG_RTS_CHG_INT_ST : 1;/*!< The raw interrupt status bit for the USB_DEVICE_RTS_CHG_INT - interrupt. */ - __IM uint32_t USB_SERIAL_JTAG_DTR_CHG_INT_ST : 1;/*!< The raw interrupt status bit for the USB_DEVICE_DTR_CHG_INT - interrupt. */ - __IM uint32_t USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST : 1;/*!< The raw interrupt status bit for the USB_DEVICE_GET_LINE_CODE_INT - interrupt. */ - __IM uint32_t USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST : 1;/*!< The raw interrupt status bit for the USB_DEVICE_SET_LINE_CODE_INT - interrupt. */ - uint32_t : 16; - } bit; - } INT_ST; - - union { - __IOM uint32_t reg; /*!< Interrupt enable status register. */ - - struct { - __IOM uint32_t USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA : 1;/*!< The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT - interrupt. */ - __IOM uint32_t USB_SERIAL_JTAG_SOF_INT_ENA : 1;/*!< The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt. */ - __IOM uint32_t USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA : 1;/*!< The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT - interrupt. */ - __IOM uint32_t USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA : 1;/*!< The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT - interrupt. */ - __IOM uint32_t USB_SERIAL_JTAG_PID_ERR_INT_ENA : 1;/*!< The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt. */ - __IOM uint32_t USB_SERIAL_JTAG_CRC5_ERR_INT_ENA : 1;/*!< The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt. */ - __IOM uint32_t USB_SERIAL_JTAG_CRC16_ERR_INT_ENA : 1;/*!< The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt. */ - __IOM uint32_t USB_SERIAL_JTAG_STUFF_ERR_INT_ENA : 1;/*!< The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt. */ - __IOM uint32_t USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA : 1;/*!< The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT - interrupt. */ - __IOM uint32_t USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA : 1;/*!< The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT - interrupt. */ - __IOM uint32_t USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA : 1;/*!< The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT - interrupt. */ - __IOM uint32_t USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA : 1;/*!< The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT - interrupt. */ - __IOM uint32_t USB_SERIAL_JTAG_RTS_CHG_INT_ENA : 1;/*!< The interrupt enable bit for the USB_DEVICE_RTS_CHG_INT interrupt. */ - __IOM uint32_t USB_SERIAL_JTAG_DTR_CHG_INT_ENA : 1;/*!< The interrupt enable bit for the USB_DEVICE_DTR_CHG_INT interrupt. */ - __IOM uint32_t USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA : 1;/*!< The interrupt enable bit for the USB_DEVICE_GET_LINE_CODE_INT - interrupt. */ - __IOM uint32_t USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA : 1;/*!< The interrupt enable bit for the USB_DEVICE_SET_LINE_CODE_INT - interrupt. */ - uint32_t : 16; - } bit; - } INT_ENA; - - union { - __IOM uint32_t reg; /*!< Interrupt clear status register. */ - - struct { - __OM uint32_t USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR : 1;/*!< Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. */ - __OM uint32_t USB_SERIAL_JTAG_SOF_INT_CLR : 1;/*!< Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt. */ - __OM uint32_t USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR : 1;/*!< Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT - interrupt. */ - __OM uint32_t USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR : 1;/*!< Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. */ - __OM uint32_t USB_SERIAL_JTAG_PID_ERR_INT_CLR : 1;/*!< Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt. */ - __OM uint32_t USB_SERIAL_JTAG_CRC5_ERR_INT_CLR : 1;/*!< Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt. */ - __OM uint32_t USB_SERIAL_JTAG_CRC16_ERR_INT_CLR : 1;/*!< Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt. */ - __OM uint32_t USB_SERIAL_JTAG_STUFF_ERR_INT_CLR : 1;/*!< Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt. */ - __OM uint32_t USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR : 1;/*!< Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt. */ - __OM uint32_t USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR : 1;/*!< Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt. */ - __OM uint32_t USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR : 1;/*!< Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT - interrupt. */ - __OM uint32_t USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR : 1;/*!< Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT - interrupt. */ - __OM uint32_t USB_SERIAL_JTAG_RTS_CHG_INT_CLR : 1;/*!< Set this bit to clear the USB_DEVICE_RTS_CHG_INT interrupt. */ - __OM uint32_t USB_SERIAL_JTAG_DTR_CHG_INT_CLR : 1;/*!< Set this bit to clear the USB_DEVICE_DTR_CHG_INT interrupt. */ - __OM uint32_t USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR : 1;/*!< Set this bit to clear the USB_DEVICE_GET_LINE_CODE_INT interrupt. */ - __OM uint32_t USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR : 1;/*!< Set this bit to clear the USB_DEVICE_SET_LINE_CODE_INT interrupt. */ - uint32_t : 16; - } bit; - } INT_CLR; - - union { - __IOM uint32_t reg; /*!< PHY hardware configuration. */ - - struct { - __IOM uint32_t USB_SERIAL_JTAG_PHY_SEL : 1;/*!< Select internal/external PHY */ - __IOM uint32_t USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE : 1;/*!< Enable software control USB D+ D- exchange */ - __IOM uint32_t USB_SERIAL_JTAG_EXCHG_PINS : 1;/*!< USB D+ D- exchange */ - __IOM uint32_t USB_SERIAL_JTAG_VREFH : 2; /*!< Control single-end input high threshold,1.76V to 2V, step 80mV */ - __IOM uint32_t USB_SERIAL_JTAG_VREFL : 2; /*!< Control single-end input low threshold,0.8V to 1.04V, step 80mV */ - __IOM uint32_t USB_SERIAL_JTAG_VREF_OVERRIDE : 1;/*!< Enable software control input threshold */ - __IOM uint32_t USB_SERIAL_JTAG_PAD_PULL_OVERRIDE : 1;/*!< Enable software control USB D+ D- pullup pulldown */ - __IOM uint32_t USB_SERIAL_JTAG_DP_PULLUP : 1;/*!< Control USB D+ pull up. */ - __IOM uint32_t USB_SERIAL_JTAG_DP_PULLDOWN : 1;/*!< Control USB D+ pull down. */ - __IOM uint32_t USB_SERIAL_JTAG_DM_PULLUP : 1;/*!< Control USB D- pull up. */ - __IOM uint32_t USB_SERIAL_JTAG_DM_PULLDOWN : 1;/*!< Control USB D- pull down. */ - __IOM uint32_t USB_SERIAL_JTAG_PULLUP_VALUE : 1;/*!< Control pull up value. */ - __IOM uint32_t USB_SERIAL_JTAG_USB_PAD_ENABLE : 1;/*!< Enable USB pad function. */ - __IOM uint32_t USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN : 1;/*!< Set this bit usb_jtag, the connection between usb_jtag and internal - JTAG is disconnected, and MTMS, MTDI, MTCK are output through - GPIO Matrix, MTDO is input through GPIO Matrix. */ - uint32_t : 16; - } bit; - } CONF0; - - union { - __IOM uint32_t reg; /*!< Registers used for debugging the PHY. */ - - struct { - __IOM uint32_t USB_SERIAL_JTAG_TEST_ENABLE : 1;/*!< Enable test of the USB pad */ - __IOM uint32_t USB_SERIAL_JTAG_TEST_USB_OE : 1;/*!< USB pad oen in test */ - __IOM uint32_t USB_SERIAL_JTAG_TEST_TX_DP : 1;/*!< USB D+ tx value in test */ - __IOM uint32_t USB_SERIAL_JTAG_TEST_TX_DM : 1;/*!< USB D- tx value in test */ - __IM uint32_t USB_SERIAL_JTAG_TEST_RX_RCV : 1;/*!< USB RCV value in test */ - __IM uint32_t USB_SERIAL_JTAG_TEST_RX_DP : 1;/*!< USB D+ rx value in test */ - __IM uint32_t USB_SERIAL_JTAG_TEST_RX_DM : 1;/*!< USB D- rx value in test */ - uint32_t : 25; - } bit; - } TEST; - - union { - __IOM uint32_t reg; /*!< JTAG FIFO status and control registers. */ - - struct { - __IM uint32_t USB_SERIAL_JTAG_IN_FIFO_CNT : 2;/*!< JTAT in fifo counter. */ - __IM uint32_t USB_SERIAL_JTAG_IN_FIFO_EMPTY : 1;/*!< 1: JTAG in fifo is empty. */ - __IM uint32_t USB_SERIAL_JTAG_IN_FIFO_FULL : 1;/*!< 1: JTAG in fifo is full. */ - __IM uint32_t USB_SERIAL_JTAG_OUT_FIFO_CNT : 2;/*!< JTAT out fifo counter. */ - __IM uint32_t USB_SERIAL_JTAG_OUT_FIFO_EMPTY : 1;/*!< 1: JTAG out fifo is empty. */ - __IM uint32_t USB_SERIAL_JTAG_OUT_FIFO_FULL : 1;/*!< 1: JTAG out fifo is full. */ - __IOM uint32_t USB_SERIAL_JTAG_IN_FIFO_RESET : 1;/*!< Write 1 to reset JTAG in fifo. */ - __IOM uint32_t USB_SERIAL_JTAG_OUT_FIFO_RESET : 1;/*!< Write 1 to reset JTAG out fifo. */ - uint32_t : 22; - } bit; - } JFIFO_ST; - - union { - __IOM uint32_t reg; /*!< Last received SOF frame index register. */ - - struct { - __IM uint32_t USB_SERIAL_JTAG_SOF_FRAME_INDEX : 11;/*!< Frame index of received SOF frame. */ - uint32_t : 21; - } bit; - } FRAM_NUM; - - union { - __IOM uint32_t reg; /*!< Control IN endpoint status information. */ - - struct { - __IM uint32_t USB_SERIAL_JTAG_IN_EP0_STATE : 2;/*!< State of IN Endpoint 0. */ - __IM uint32_t USB_SERIAL_JTAG_IN_EP0_WR_ADDR : 7;/*!< Write data address of IN endpoint 0. */ - __IM uint32_t USB_SERIAL_JTAG_IN_EP0_RD_ADDR : 7;/*!< Read data address of IN endpoint 0. */ - uint32_t : 16; - } bit; - } IN_EP0_ST; - - union { - __IOM uint32_t reg; /*!< CDC-ACM IN endpoint status information. */ - - struct { - __IM uint32_t USB_SERIAL_JTAG_IN_EP1_STATE : 2;/*!< State of IN Endpoint 1. */ - __IM uint32_t USB_SERIAL_JTAG_IN_EP1_WR_ADDR : 7;/*!< Write data address of IN endpoint 1. */ - __IM uint32_t USB_SERIAL_JTAG_IN_EP1_RD_ADDR : 7;/*!< Read data address of IN endpoint 1. */ - uint32_t : 16; - } bit; - } IN_EP1_ST; - - union { - __IOM uint32_t reg; /*!< CDC-ACM interrupt IN endpoint status information. */ - - struct { - __IM uint32_t USB_SERIAL_JTAG_IN_EP2_STATE : 2;/*!< State of IN Endpoint 2. */ - __IM uint32_t USB_SERIAL_JTAG_IN_EP2_WR_ADDR : 7;/*!< Write data address of IN endpoint 2. */ - __IM uint32_t USB_SERIAL_JTAG_IN_EP2_RD_ADDR : 7;/*!< Read data address of IN endpoint 2. */ - uint32_t : 16; - } bit; - } IN_EP2_ST; - - union { - __IOM uint32_t reg; /*!< JTAG IN endpoint status information. */ - - struct { - __IM uint32_t USB_SERIAL_JTAG_IN_EP3_STATE : 2;/*!< State of IN Endpoint 3. */ - __IM uint32_t USB_SERIAL_JTAG_IN_EP3_WR_ADDR : 7;/*!< Write data address of IN endpoint 3. */ - __IM uint32_t USB_SERIAL_JTAG_IN_EP3_RD_ADDR : 7;/*!< Read data address of IN endpoint 3. */ - uint32_t : 16; - } bit; - } IN_EP3_ST; - - union { - __IOM uint32_t reg; /*!< Control OUT endpoint status information. */ - - struct { - __IM uint32_t USB_SERIAL_JTAG_OUT_EP0_STATE : 2;/*!< State of OUT Endpoint 0. */ - __IM uint32_t USB_SERIAL_JTAG_OUT_EP0_WR_ADDR : 7;/*!< Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT - is detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes - data in OUT EP0. */ - __IM uint32_t USB_SERIAL_JTAG_OUT_EP0_RD_ADDR : 7;/*!< Read data address of OUT endpoint 0. */ - uint32_t : 16; - } bit; - } OUT_EP0_ST; - - union { - __IOM uint32_t reg; /*!< CDC-ACM OUT endpoint status information. */ - - struct { - __IM uint32_t USB_SERIAL_JTAG_OUT_EP1_STATE : 2;/*!< State of OUT Endpoint 1. */ - __IM uint32_t USB_SERIAL_JTAG_OUT_EP1_WR_ADDR : 7;/*!< Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT - is detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes - data in OUT EP1. */ - __IM uint32_t USB_SERIAL_JTAG_OUT_EP1_RD_ADDR : 7;/*!< Read data address of OUT endpoint 1. */ - __IM uint32_t USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT : 7;/*!< Data count in OUT endpoint 1 when one packet is received. */ - uint32_t : 9; - } bit; - } OUT_EP1_ST; - - union { - __IOM uint32_t reg; /*!< JTAG OUT endpoint status information. */ - - struct { - __IM uint32_t USB_SERIAL_JTAG_OUT_EP2_STATE : 2;/*!< State of OUT Endpoint 2. */ - __IM uint32_t USB_SERIAL_JTAG_OUT_EP2_WR_ADDR : 7;/*!< Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT - is detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes - data in OUT EP2. */ - __IM uint32_t USB_SERIAL_JTAG_OUT_EP2_RD_ADDR : 7;/*!< Read data address of OUT endpoint 2. */ - uint32_t : 16; - } bit; - } OUT_EP2_ST; - - union { - __IOM uint32_t reg; /*!< Clock enable control */ - - struct { - __IOM uint32_t USB_SERIAL_JTAG_CLK_EN : 1;/*!< 1'h1: Force clock on for register. 1'h0: Support clock only - when application writes registers. */ - uint32_t : 31; - } bit; - } MISC_CONF; - - union { - __IOM uint32_t reg; /*!< Memory power control */ - - struct { - __IOM uint32_t USB_SERIAL_JTAG_USB_MEM_PD : 1;/*!< 1: power down usb memory. */ - __IOM uint32_t USB_SERIAL_JTAG_USB_MEM_CLK_EN : 1;/*!< 1: Force clock on for usb memory. */ - uint32_t : 30; - } bit; - } MEM_CONF; - - union { - __IOM uint32_t reg; /*!< CDC-ACM chip reset control. */ - - struct { - __IM uint32_t USB_SERIAL_JTAG_RTS : 1; /*!< 1: Chip reset is detected from usb serial channel. Software - write 1 to clear it. */ - __IM uint32_t USB_SERIAL_JTAG_DTR : 1; /*!< 1: Chip reset is detected from usb jtag channel. Software write - 1 to clear it. */ - __IOM uint32_t USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS : 1;/*!< Set this bit to disable chip reset from usb serial channel to - reset chip. */ - uint32_t : 29; - } bit; - } CHIP_RST; - - union { - __IOM uint32_t reg; /*!< W0 of SET_LINE_CODING command. */ - - struct { - __IM uint32_t USB_SERIAL_JTAG_DW_DTE_RATE : 32;/*!< The value of dwDTERate set by host through SET_LINE_CODING command. */ - } bit; - } SET_LINE_CODE_W0; - - union { - __IOM uint32_t reg; /*!< W1 of SET_LINE_CODING command. */ - - struct { - __IM uint32_t USB_SERIAL_JTAG_BCHAR_FORMAT : 8;/*!< The value of bCharFormat set by host through SET_LINE_CODING - command. */ - __IM uint32_t USB_SERIAL_JTAG_BPARITY_TYPE : 8;/*!< The value of bParityTpye set by host through SET_LINE_CODING - command. */ - __IM uint32_t USB_SERIAL_JTAG_BDATA_BITS : 8;/*!< The value of bDataBits set by host through SET_LINE_CODING command. */ - uint32_t : 8; - } bit; - } SET_LINE_CODE_W1; - - union { - __IOM uint32_t reg; /*!< W0 of GET_LINE_CODING command. */ - - struct { - __IOM uint32_t USB_SERIAL_JTAG_GET_DW_DTE_RATE : 32;/*!< The value of dwDTERate set by software which is requested by - GET_LINE_CODING command. */ - } bit; - } GET_LINE_CODE_W0; - - union { - __IOM uint32_t reg; /*!< W1 of GET_LINE_CODING command. */ - - struct { - __IOM uint32_t USB_SERIAL_JTAG_GET_BDATA_BITS : 8;/*!< The value of bCharFormat set by software which is requested - by GET_LINE_CODING command. */ - __IOM uint32_t USB_SERIAL_JTAG_GET_BPARITY_TYPE : 8;/*!< The value of bParityTpye set by software which is requested - by GET_LINE_CODING command. */ - __IOM uint32_t USB_SERIAL_JTAG_GET_BCHAR_FORMAT : 8;/*!< The value of bDataBits set by software which is requested by - GET_LINE_CODING command. */ - uint32_t : 8; - } bit; - } GET_LINE_CODE_W1; - - union { - __IOM uint32_t reg; /*!< Configuration registers' value update */ - - struct { - __OM uint32_t USB_SERIAL_JTAG_CONFIG_UPDATE : 1;/*!< Write 1 to this register would update the value of configure - registers from APB clock domain to 48MHz clock domain. */ - uint32_t : 31; - } bit; - } CONFIG_UPDATE; - - union { - __IOM uint32_t reg; /*!< Serial AFIFO configure register */ - - struct { - __IOM uint32_t USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR : 1;/*!< Write 1 to reset CDC_ACM IN async FIFO write clock domain. */ - __IOM uint32_t USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD : 1;/*!< Write 1 to reset CDC_ACM IN async FIFO read clock domain. */ - __IOM uint32_t USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR : 1;/*!< Write 1 to reset CDC_ACM OUT async FIFO write clock domain. */ - __IOM uint32_t USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD : 1;/*!< Write 1 to reset CDC_ACM OUT async FIFO read clock domain. */ - __IM uint32_t USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY : 1;/*!< CDC_ACM OUTOUT async FIFO empty signal in read clock domain. */ - __IM uint32_t USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL : 1;/*!< CDC_ACM OUT IN async FIFO empty signal in write clock domain. */ - uint32_t : 26; - } bit; - } SER_AFIFO_CONFIG; - - union { - __IOM uint32_t reg; /*!< USB Bus reset status register */ - - struct { - __IM uint32_t USB_SERIAL_JTAG_USB_BUS_RESET_ST : 1;/*!< USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset - status. 1: USB bus reset is released. */ - uint32_t : 31; - } bit; - } BUS_RESET_ST; - - union { - __IOM uint32_t reg; /*!< Reserved. */ - - struct { - __IOM uint32_t USB_SERIAL_JTAG_RND_ECO_LOW_48 : 32;/*!< Reserved. */ - } bit; - } ECO_LOW_48; - - union { - __IOM uint32_t reg; /*!< Reserved. */ - - struct { - __IOM uint32_t USB_SERIAL_JTAG_RND_ECO_HIGH_48 : 32;/*!< Reserved. */ - } bit; - } ECO_HIGH_48; - - union { - __IOM uint32_t reg; /*!< Reserved. */ - - struct { - __IM uint32_t USB_SERIAL_JTAG_RDN_RESULT_48 : 1;/*!< Reserved. */ - __IOM uint32_t USB_SERIAL_JTAG_RDN_ENA_48 : 1;/*!< Reserved. */ - uint32_t : 30; - } bit; - } ECO_CELL_CTRL_48; - - union { - __IOM uint32_t reg; /*!< Reserved. */ - - struct { - __IOM uint32_t USB_SERIAL_JTAG_RND_ECO_LOW_APB : 32;/*!< Reserved. */ - } bit; - } ECO_LOW_APB; - - union { - __IOM uint32_t reg; /*!< Reserved. */ - - struct { - __IOM uint32_t USB_SERIAL_JTAG_RND_ECO_HIGH_APB : 32;/*!< Reserved. */ - } bit; - } ECO_HIGH_APB; - - union { - __IOM uint32_t reg; /*!< Reserved. */ - - struct { - __IM uint32_t USB_SERIAL_JTAG_RDN_RESULT_APB : 1;/*!< Reserved. */ - __IOM uint32_t USB_SERIAL_JTAG_RDN_ENA_APB : 1;/*!< Reserved. */ - uint32_t : 30; - } bit; - } ECO_CELL_CTRL_APB; - - union { - __IOM uint32_t reg; /*!< PPA SRAM Control Register */ - - struct { - __IOM uint32_t USB_SERIAL_JTAG_MEM_AUX_CTRL : 14;/*!< Control signals */ - uint32_t : 18; - } bit; - } SRAM_CTRL; - - union { - __IOM uint32_t reg; /*!< Date register */ - - struct { - __IOM uint32_t USB_SERIAL_JTAG_DATE : 32; /*!< register version. */ - } bit; - } DATE; -} USB_DEVICE_Type; /*!< Size = 140 (0x8c) */ - - - -/* =========================================================================================================================== */ -/* ================ USB_WRAP ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief USB_WRAP Peripheral (USB_WRAP) - */ - -typedef struct { /*!< USB_WRAP Structure */ - - union { - __IOM uint32_t reg; /*!< USB wrapper configuration registers. */ - - struct { - __IOM uint32_t SRP_SESSEND_OVERRIDE : 1; /*!< This bit is used to enable the software over-ride of srp session - end signal. 1'b0: the signal is controlled by the chip - input, 1'b1: the signal is controlled by the software. */ - __IOM uint32_t SRP_SESSEND_VALUE : 1; /*!< Software over-ride value of srp session end signal. */ - __IOM uint32_t PHY_SEL : 1; /*!< Select internal external PHY. 1'b0: Select internal PHY, 1'b1: - Select external PHY. */ - __IOM uint32_t DFIFO_FORCE_PD : 1; /*!< Force the dfifo to go into low power mode. The data in dfifo - will not lost. */ - __IOM uint32_t DBNCE_FLTR_BYPASS : 1; /*!< Bypass Debounce filters for avalid,bvalid,vbusvalid,session - end, id signals */ - __IOM uint32_t EXCHG_PINS_OVERRIDE : 1; /*!< Enable software controlle USB D+ D- exchange */ - __IOM uint32_t EXCHG_PINS : 1; /*!< USB D+ D- exchange. 1'b0: don't change, 1'b1: exchange D+ D-. */ - __IOM uint32_t VREFH : 2; /*!< Control single-end input high threshold,1.76V to 2V, step 80mV. */ - __IOM uint32_t VREFL : 2; /*!< Control single-end input low threshold,0.8V to 1.04V, step 80mV. */ - __IOM uint32_t VREF_OVERRIDE : 1; /*!< Enable software controlle input threshold. */ - __IOM uint32_t PAD_PULL_OVERRIDE : 1; /*!< Enable software controlle USB D+ D- pullup pulldown. */ - __IOM uint32_t DP_PULLUP : 1; /*!< Controlle USB D+ pullup. */ - __IOM uint32_t DP_PULLDOWN : 1; /*!< Controlle USB D+ pulldown. */ - __IOM uint32_t DM_PULLUP : 1; /*!< Controlle USB D+ pullup. */ - __IOM uint32_t DM_PULLDOWN : 1; /*!< Controlle USB D+ pulldown. */ - __IOM uint32_t PULLUP_VALUE : 1; /*!< Controlle pullup value. 1'b0: typical value is 2.4K, 1'b1: typical - value is 1.2K. */ - __IOM uint32_t USB_PAD_ENABLE : 1; /*!< Enable USB pad function. */ - __IOM uint32_t AHB_CLK_FORCE_ON : 1; /*!< Force ahb clock always on. */ - __IOM uint32_t PHY_CLK_FORCE_ON : 1; /*!< Force phy clock always on. */ - __IOM uint32_t PHY_TX_EDGE_SEL : 1; /*!< Select phy tx signal output clock edge. 1'b0: negedge, 1'b1: - posedge. */ - __IOM uint32_t DFIFO_FORCE_PU : 1; /*!< Disable the dfifo to go into low power mode. The data in dfifo - will not lost. */ - uint32_t : 8; - __IOM uint32_t CLK_EN : 1; /*!< Disable auto clock gating of CSR registers. */ - } bit; - } OTG_CONF; - - union { - __IOM uint32_t reg; /*!< USB wrapper test configuration registers. */ - - struct { - __IOM uint32_t TEST_ENABLE : 1; /*!< Enable test of the USB pad. */ - __IOM uint32_t TEST_USB_OE : 1; /*!< USB pad oen in test. */ - __IOM uint32_t TEST_TX_DP : 1; /*!< USB D+ tx value in test. */ - __IOM uint32_t TEST_TX_DM : 1; /*!< USB D- tx value in test. */ - __IM uint32_t TEST_RX_RCV : 1; /*!< USB differential rx value in test. */ - __IM uint32_t TEST_RX_DP : 1; /*!< USB D+ rx value in test. */ - __IM uint32_t TEST_RX_DM : 1; /*!< USB D- rx value in test. */ - uint32_t : 25; - } bit; - } TEST_CONF; - __IM uint32_t RESERVED[253]; - - union { - __IOM uint32_t reg; /*!< Date register. */ - - struct { - __IM uint32_t USB_WRAP_DATE : 32; /*!< Date register. */ - } bit; - } DATE; -} USB_WRAP_Type; /*!< Size = 1024 (0x400) */ - - -/** @} */ /* End of group Device_Peripheral_peripherals */ - - -/* =========================================================================================================================== */ -/* ================ Device Specific Peripheral Address Map ================ */ -/* =========================================================================================================================== */ - - -/** @addtogroup Device_Peripheral_peripheralAddr - * @{ - */ - -#define ADC_BASE 0x500DE000UL -#define AES_BASE 0x50090000UL -#define AHB_DMA_BASE 0x50085000UL -#define LP_I2C_ANA_MST_BASE 0x50124000UL -#define ASSIST_DEBUG_BASE 0x3FF06000UL -#define AXI_DMA_BASE 0x5008A000UL -#define BITSCRAMBLER_BASE 0x500A3000UL -#define CACHE_BASE 0x3FF10000UL -#define INTERRUPT_CORE0_BASE 0x500D6000UL -#define INTERRUPT_CORE1_BASE 0x500D6800UL -#define MIPI_CSI_BRIDGE_BASE 0x5009F800UL -#define MIPI_CSI_HOST_BASE 0x5009F000UL -#define DMA_BASE 0x50081000UL -#define DS_BASE 0x50094000UL -#define MIPI_DSI_BRIDGE_BASE 0x500A0800UL -#define MIPI_DSI_HOST_BASE 0x500A0000UL -#define ECC_BASE 0x50093000UL -#define ECDSA_BASE 0x50096000UL -#define EFUSE_BASE 0x5012D000UL -#define GPIO_BASE 0x500E0000UL -#define GPIO_SD_BASE 0x500E0F00UL -#define H264_BASE 0x50084000UL -#define H264_DMA_BASE 0x500A7000UL -#define HMAC_BASE 0x50095000UL -#define HP_SYS_BASE 0x500E5000UL -#define HP_SYS_CLKRST_BASE 0x500E6000UL -#define LP_HUK_BASE 0x50114000UL -#define I2C0_BASE 0x500C4000UL -#define I2C1_BASE 0x500C5000UL -#define I2S0_BASE 0x500C6000UL -#define I2S1_BASE 0x500C7000UL -#define I2S2_BASE 0x500C8000UL -#define I3C_MST_BASE 0x500DA000UL -#define I3C_MST_MEM_BASE 0x500DA000UL -#define I3C_SLV_BASE 0x500DB000UL -#define AXI_ICM_BASE 0x500A4000UL -#define IO_MUX_BASE 0x500E1000UL -#define ISP_BASE 0x500A1000UL -#define JPEG_BASE 0x50086000UL -#define LCD_CAM_BASE 0x500DC000UL -#define LEDC_BASE 0x500D3000UL -#define LP_INTR_BASE 0x5012C000UL -#define LP_PERI_BASE 0x50120000UL -#define LP_SYS_BASE 0x50110000UL -#define LP_ANA_PERI_BASE 0x50113000UL -#define LP_AON_CLKRST_BASE 0x50111000UL -#define LP_GPIO_BASE 0x5012A000UL -#define LP_I2C0_BASE 0x50122000UL -#define LP_I2S0_BASE 0x50125000UL -#define LP_IO_MUX_BASE 0x5012B000UL -#define LP_UART_BASE 0x50121000UL -#define MCPWM0_BASE 0x500C0000UL -#define MCPWM1_BASE 0x500C1000UL -#define PARL_IO_BASE 0x500CF000UL -#define PAU_BASE 0x60093000UL -#define PCNT_BASE 0x500C9000UL -#define PMU_BASE 0x50115000UL -#define PPA_BASE 0x50087000UL -#define PVT_BASE 0x5009E000UL -#define RMT_BASE 0x500D4000UL -#define RSA_BASE 0x50092000UL -#define LP_ADC_BASE 0x50127000UL -#define LP_TIMER_BASE 0x50112000UL -#define LP_TOUCH_BASE 0x50128000UL -#define LP_WDT_BASE 0x50116000UL -#define SDHOST_BASE 0x50083000UL -#define SHA_BASE 0x50091000UL -#define SOC_ETM_BASE 0x500D5000UL -#define SPI0_BASE 0x5008C000UL -#define SPI1_BASE 0x5008D000UL -#define SPI2_BASE 0x500D0000UL -#define SPI3_BASE 0x500D1000UL -#define SYSTIMER_BASE 0x500E2000UL -#define TIMG0_BASE 0x500C2000UL -#define TIMG1_BASE 0x500C3000UL -#define TRACE0_BASE 0x3FF04000UL -#define TRACE1_BASE 0x3FF05000UL -#define LP_TSENS_BASE 0x5012F000UL -#define TWAI0_BASE 0x500D7000UL -#define TWAI1_BASE 0x500D8000UL -#define TWAI2_BASE 0x500D9000UL -#define UART0_BASE 0x500CA000UL -#define UART1_BASE 0x500CB000UL -#define UART2_BASE 0x500CC000UL -#define UART3_BASE 0x500CD000UL -#define UART4_BASE 0x500CE000UL -#define UHCI0_BASE 0x500DF000UL -#define USB_DEVICE_BASE 0x500D2000UL -#define USB_WRAP_BASE 0x50080000UL - -/** @} */ /* End of group Device_Peripheral_peripheralAddr */ - - -/* =========================================================================================================================== */ -/* ================ Peripheral declaration ================ */ -/* =========================================================================================================================== */ - - -/** @addtogroup Device_Peripheral_declaration - * @{ - */ - -#define ADC ((ADC_Type*) ADC_BASE) -#define AES ((AES_Type*) AES_BASE) -#define AHB_DMA ((AHB_DMA_Type*) AHB_DMA_BASE) -#define LP_I2C_ANA_MST ((LP_I2C_ANA_MST_Type*) LP_I2C_ANA_MST_BASE) -#define ASSIST_DEBUG ((ASSIST_DEBUG_Type*) ASSIST_DEBUG_BASE) -#define AXI_DMA ((AXI_DMA_Type*) AXI_DMA_BASE) -#define BITSCRAMBLER ((BITSCRAMBLER_Type*) BITSCRAMBLER_BASE) -#define CACHE ((CACHE_Type*) CACHE_BASE) -#define INTERRUPT_CORE0 ((INTERRUPT_CORE0_Type*) INTERRUPT_CORE0_BASE) -#define INTERRUPT_CORE1 ((INTERRUPT_CORE1_Type*) INTERRUPT_CORE1_BASE) -#define MIPI_CSI_BRIDGE ((MIPI_CSI_BRIDGE_Type*) MIPI_CSI_BRIDGE_BASE) -#define MIPI_CSI_HOST ((MIPI_CSI_HOST_Type*) MIPI_CSI_HOST_BASE) -#define DMA ((DMA_Type*) DMA_BASE) -#define DS ((DS_Type*) DS_BASE) -#define MIPI_DSI_BRIDGE ((MIPI_DSI_BRIDGE_Type*) MIPI_DSI_BRIDGE_BASE) -#define MIPI_DSI_HOST ((MIPI_DSI_HOST_Type*) MIPI_DSI_HOST_BASE) -#define ECC ((ECC_Type*) ECC_BASE) -#define ECDSA ((ECDSA_Type*) ECDSA_BASE) -#define EFUSE ((EFUSE_Type*) EFUSE_BASE) -#define GPIO ((GPIO_Type*) GPIO_BASE) -#define GPIO_SD ((GPIO_SD_Type*) GPIO_SD_BASE) -#define H264 ((H264_Type*) H264_BASE) -#define H264_DMA ((H264_DMA_Type*) H264_DMA_BASE) -#define HMAC ((HMAC_Type*) HMAC_BASE) -#define HP_SYS ((HP_SYS_Type*) HP_SYS_BASE) -#define HP_SYS_CLKRST ((HP_SYS_CLKRST_Type*) HP_SYS_CLKRST_BASE) -#define LP_HUK ((LP_HUK_Type*) LP_HUK_BASE) -#define I2C0 ((I2C0_Type*) I2C0_BASE) -#define I2C1 ((I2C0_Type*) I2C1_BASE) -#define I2S0 ((I2S0_Type*) I2S0_BASE) -#define I2S1 ((I2S0_Type*) I2S1_BASE) -#define I2S2 ((I2S0_Type*) I2S2_BASE) -#define I3C_MST ((I3C_MST_Type*) I3C_MST_BASE) -#define I3C_MST_MEM ((I3C_MST_MEM_Type*) I3C_MST_MEM_BASE) -#define I3C_SLV ((I3C_SLV_Type*) I3C_SLV_BASE) -#define AXI_ICM ((AXI_ICM_Type*) AXI_ICM_BASE) -#define IO_MUX ((IO_MUX_Type*) IO_MUX_BASE) -#define ISP ((ISP_Type*) ISP_BASE) -#define JPEG ((JPEG_Type*) JPEG_BASE) -#define LCD_CAM ((LCD_CAM_Type*) LCD_CAM_BASE) -#define LEDC ((LEDC_Type*) LEDC_BASE) -#define LP_INTR ((LP_INTR_Type*) LP_INTR_BASE) -#define LP_PERI ((LP_PERI_Type*) LP_PERI_BASE) -#define LP_SYS ((LP_SYS_Type*) LP_SYS_BASE) -#define LP_ANA_PERI ((LP_ANA_PERI_Type*) LP_ANA_PERI_BASE) -#define LP_AON_CLKRST ((LP_AON_CLKRST_Type*) LP_AON_CLKRST_BASE) -#define LP_GPIO ((LP_GPIO_Type*) LP_GPIO_BASE) -#define LP_I2C0 ((LP_I2C0_Type*) LP_I2C0_BASE) -#define LP_I2S0 ((LP_I2S0_Type*) LP_I2S0_BASE) -#define LP_IO_MUX ((LP_IO_MUX_Type*) LP_IO_MUX_BASE) -#define LP_UART ((LP_UART_Type*) LP_UART_BASE) -#define MCPWM0 ((MCPWM0_Type*) MCPWM0_BASE) -#define MCPWM1 ((MCPWM0_Type*) MCPWM1_BASE) -#define PARL_IO ((PARL_IO_Type*) PARL_IO_BASE) -#define PAU ((PAU_Type*) PAU_BASE) -#define PCNT ((PCNT_Type*) PCNT_BASE) -#define PMU ((PMU_Type*) PMU_BASE) -#define PPA ((PPA_Type*) PPA_BASE) -#define PVT ((PVT_Type*) PVT_BASE) -#define RMT ((RMT_Type*) RMT_BASE) -#define RSA ((RSA_Type*) RSA_BASE) -#define LP_ADC ((LP_ADC_Type*) LP_ADC_BASE) -#define LP_TIMER ((LP_TIMER_Type*) LP_TIMER_BASE) -#define LP_TOUCH ((LP_TOUCH_Type*) LP_TOUCH_BASE) -#define LP_WDT ((LP_WDT_Type*) LP_WDT_BASE) -#define SDHOST ((SDHOST_Type*) SDHOST_BASE) -#define SHA ((SHA_Type*) SHA_BASE) -#define SOC_ETM ((SOC_ETM_Type*) SOC_ETM_BASE) -#define SPI0 ((SPI0_Type*) SPI0_BASE) -#define SPI1 ((SPI1_Type*) SPI1_BASE) -#define SPI2 ((SPI2_Type*) SPI2_BASE) -#define SPI3 ((SPI3_Type*) SPI3_BASE) -#define SYSTIMER ((SYSTIMER_Type*) SYSTIMER_BASE) -#define TIMG0 ((TIMG0_Type*) TIMG0_BASE) -#define TIMG1 ((TIMG0_Type*) TIMG1_BASE) -#define TRACE0 ((TRACE0_Type*) TRACE0_BASE) -#define TRACE1 ((TRACE0_Type*) TRACE1_BASE) -#define LP_TSENS ((LP_TSENS_Type*) LP_TSENS_BASE) -#define TWAI0 ((TWAI0_Type*) TWAI0_BASE) -#define TWAI1 ((TWAI0_Type*) TWAI1_BASE) -#define TWAI2 ((TWAI0_Type*) TWAI2_BASE) -#define UART0 ((UART0_Type*) UART0_BASE) -#define UART1 ((UART0_Type*) UART1_BASE) -#define UART2 ((UART0_Type*) UART2_BASE) -#define UART3 ((UART0_Type*) UART3_BASE) -#define UART4 ((UART0_Type*) UART4_BASE) -#define UHCI0 ((UHCI0_Type*) UHCI0_BASE) -#define USB_DEVICE ((USB_DEVICE_Type*) USB_DEVICE_BASE) -#define USB_WRAP ((USB_WRAP_Type*) USB_WRAP_BASE) - - -#if defined(__cplusplus) -} -#endif - -#endif /* ESP32_P4_H */ diff --git a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/esp32p4.svd b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/esp32p4.svd deleted file mode 100644 index e805dcf66..000000000 --- a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/esp32p4.svd +++ /dev/null @@ -1,133701 +0,0 @@ - - - ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD. - ESPRESSIF - ESP32-P4 - ESP32 P-Series - 2 - 32-bit RISC-V MCU - Copyright 2024 Espressif Systems (Shanghai) PTE LTD - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. - - RV32IMAFC - r0p0 - little - false - true - 0 - false - - 32 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADC - ADC (Analog to Digital Converter) - ADC - 0x500DE000 - - 0x0 - 0x7C - registers - - - - CTRL - Register - 0x0 - 0x20 - 0x403FC120 - - - START_FORCE - need_des - 0 - 1 - read-write - - - START - need_des - 1 - 1 - read-write - - - WORK_MODE - 0: single mode, 1: double mode, 2: alternate mode - 2 - 2 - read-write - - - SAR_SEL - 0: SAR1, 1: SAR2, only work for single SAR mode - 4 - 1 - read-write - - - SAR_CLK_GATED - need_des - 5 - 1 - read-write - - - SAR_CLK_DIV - SAR clock divider - 6 - 8 - read-write - - - SAR1_PATT_LEN - 0 ~ 15 means length 1 ~ 16 - 14 - 4 - read-write - - - SAR2_PATT_LEN - 0 ~ 15 means length 1 ~ 16 - 18 - 4 - read-write - - - SAR1_PATT_P_CLEAR - clear the pointer of pattern table for DIG ADC1 CTRL - 22 - 1 - read-write - - - SAR2_PATT_P_CLEAR - clear the pointer of pattern table for DIG ADC2 CTRL - 23 - 1 - read-write - - - DATA_SAR_SEL - 1: sar_sel will be coded by the MSB of the 16-bit output data, in this case the resolution should not be larger than 11 bits. - 24 - 1 - read-write - - - DATA_TO_I2S - 1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix - 25 - 1 - read-write - - - XPD_SAR1_FORCE - force option to xpd sar1 blocks - 26 - 2 - read-write - - - XPD_SAR2_FORCE - force option to xpd sar2 blocks - 28 - 2 - read-write - - - WAIT_ARB_CYCLE - wait arbit signal stable after sar_done - 30 - 2 - read-write - - - - - CTRL2 - Register - 0x4 - 0x20 - 0x0000A1FE - - - MEAS_NUM_LIMIT - need_des - 0 - 1 - read-write - - - MAX_MEAS_NUM - max conversion number - 1 - 8 - read-write - - - SAR1_INV - 1: data to DIG ADC1 CTRL is inverted, otherwise not - 9 - 1 - read-write - - - SAR2_INV - 1: data to DIG ADC2 CTRL is inverted, otherwise not - 10 - 1 - read-write - - - TIMER_SEL - 1: select saradc timer 0: i2s_ws trigger - 11 - 1 - read-write - - - TIMER_TARGET - to set saradc timer target - 12 - 12 - read-write - - - TIMER_EN - to enable saradc timer trigger - 24 - 1 - read-write - - - - - FILTER_CTRL1 - Register - 0x8 - 0x20 - - - FILTER_FACTOR1 - need_des - 26 - 3 - read-write - - - FILTER_FACTOR0 - need_des - 29 - 3 - read-write - - - - - FSM_WAIT - Register - 0xC - 0x20 - 0x00FF0808 - - - XPD_WAIT - need_des - 0 - 8 - read-write - - - RSTB_WAIT - need_des - 8 - 8 - read-write - - - STANDBY_WAIT - need_des - 16 - 8 - read-write - - - - - SAR1_STATUS - Register - 0x10 - 0x20 - - - SAR1_STATUS - 0 - 32 - read-only - - - - - SAR2_STATUS - Register - 0x14 - 0x20 - - - SAR2_STATUS - 0 - 32 - read-only - - - - - SAR1_PATT_TAB1 - Register - 0x18 - 0x20 - - - SAR1_PATT_TAB1 - item 0 ~ 3 for pattern table 1 (each item one byte) - 0 - 24 - read-write - - - - - SAR1_PATT_TAB2 - Register - 0x1C - 0x20 - - - SAR1_PATT_TAB2 - Item 4 ~ 7 for pattern table 1 (each item one byte) - 0 - 24 - read-write - - - - - SAR1_PATT_TAB3 - Register - 0x20 - 0x20 - - - SAR1_PATT_TAB3 - Item 8 ~ 11 for pattern table 1 (each item one byte) - 0 - 24 - read-write - - - - - SAR1_PATT_TAB4 - Register - 0x24 - 0x20 - - - SAR1_PATT_TAB4 - Item 12 ~ 15 for pattern table 1 (each item one byte) - 0 - 24 - read-write - - - - - SAR2_PATT_TAB1 - Register - 0x28 - 0x20 - - - SAR2_PATT_TAB1 - item 0 ~ 3 for pattern table 2 (each item one byte) - 0 - 24 - read-write - - - - - SAR2_PATT_TAB2 - Register - 0x2C - 0x20 - - - SAR2_PATT_TAB2 - Item 4 ~ 7 for pattern table 2 (each item one byte) - 0 - 24 - read-write - - - - - SAR2_PATT_TAB3 - Register - 0x30 - 0x20 - - - SAR2_PATT_TAB3 - Item 8 ~ 11 for pattern table 2 (each item one byte) - 0 - 24 - read-write - - - - - SAR2_PATT_TAB4 - Register - 0x34 - 0x20 - - - SAR2_PATT_TAB4 - Item 12 ~ 15 for pattern table 2 (each item one byte) - 0 - 24 - read-write - - - - - ARB_CTRL - Register - 0x38 - 0x20 - 0x00000900 - - - ARB_APB_FORCE - adc2 arbiter force to enableapb controller - 2 - 1 - read-write - - - ARB_RTC_FORCE - adc2 arbiter force to enable rtc controller - 3 - 1 - read-write - - - ARB_WIFI_FORCE - adc2 arbiter force to enable wifi controller - 4 - 1 - read-write - - - ARB_GRANT_FORCE - adc2 arbiter force grant - 5 - 1 - read-write - - - ARB_APB_PRIORITY - Set adc2 arbiterapb priority - 6 - 2 - read-write - - - ARB_RTC_PRIORITY - Set adc2 arbiter rtc priority - 8 - 2 - read-write - - - ARB_WIFI_PRIORITY - Set adc2 arbiter wifi priority - 10 - 2 - read-write - - - ARB_FIX_PRIORITY - adc2 arbiter uses fixed priority - 12 - 1 - read-write - - - - - FILTER_CTRL0 - Register - 0x3C - 0x20 - 0x006B4000 - - - FILTER_CHANNEL1 - need_des - 14 - 5 - read-write - - - FILTER_CHANNEL0 - apb_adc1_filter_factor - 19 - 5 - read-write - - - FILTER_RESET - enable apb_adc1_filter - 31 - 1 - read-write - - - - - SAR1_DATA_STATUS - Register - 0x40 - 0x20 - - - APB_SARADC1_DATA - need_des - 0 - 17 - read-only - - - - - THRES0_CTRL - Register - 0x44 - 0x20 - 0x0003FFED - - - THRES0_CHANNEL - need_des - 0 - 5 - read-write - - - THRES0_HIGH - saradc1's thres0 monitor thres - 5 - 13 - read-write - - - THRES0_LOW - saradc1's thres0 monitor thres - 18 - 13 - read-write - - - - - THRES1_CTRL - Register - 0x48 - 0x20 - 0x0003FFED - - - THRES1_CHANNEL - need_des - 0 - 5 - read-write - - - THRES1_HIGH - saradc1's thres0 monitor thres - 5 - 13 - read-write - - - THRES1_LOW - saradc1's thres0 monitor thres - 18 - 13 - read-write - - - - - THRES_CTRL - Register - 0x4C - 0x20 - - - THRES_ALL_EN - need_des - 27 - 1 - read-write - - - THRES3_EN - need_des - 28 - 1 - read-write - - - THRES2_EN - need_des - 29 - 1 - read-write - - - THRES1_EN - need_des - 30 - 1 - read-write - - - THRES0_EN - need_des - 31 - 1 - read-write - - - - - INT_ENA - Register - 0x50 - 0x20 - - - THRES1_LOW_INT_ENA - need_des - 26 - 1 - read-write - - - THRES0_LOW_INT_ENA - need_des - 27 - 1 - read-write - - - THRES1_HIGH_INT_ENA - need_des - 28 - 1 - read-write - - - THRES0_HIGH_INT_ENA - need_des - 29 - 1 - read-write - - - SAR2_DONE_INT_ENA - need_des - 30 - 1 - read-write - - - SAR1_DONE_INT_ENA - need_des - 31 - 1 - read-write - - - - - INT_RAW - Register - 0x54 - 0x20 - - - THRES1_LOW_INT_RAW - need_des - 26 - 1 - read-write - - - THRES0_LOW_INT_RAW - need_des - 27 - 1 - read-write - - - THRES1_HIGH_INT_RAW - need_des - 28 - 1 - read-write - - - THRES0_HIGH_INT_RAW - need_des - 29 - 1 - read-write - - - SAR2_DONE_INT_RAW - need_des - 30 - 1 - read-write - - - SAR1_DONE_INT_RAW - need_des - 31 - 1 - read-write - - - - - INT_ST - Register - 0x58 - 0x20 - - - THRES1_LOW_INT_ST - need_des - 26 - 1 - read-only - - - THRES0_LOW_INT_ST - need_des - 27 - 1 - read-only - - - THRES1_HIGH_INT_ST - need_des - 28 - 1 - read-only - - - THRES0_HIGH_INT_ST - need_des - 29 - 1 - read-only - - - APB_SARADC2_DONE_INT_ST - need_des - 30 - 1 - read-only - - - APB_SARADC1_DONE_INT_ST - need_des - 31 - 1 - read-only - - - - - INT_CLR - Register - 0x5C - 0x20 - - - THRES1_LOW_INT_CLR - need_des - 26 - 1 - write-only - - - THRES0_LOW_INT_CLR - need_des - 27 - 1 - write-only - - - THRES1_HIGH_INT_CLR - need_des - 28 - 1 - write-only - - - THRES0_HIGH_INT_CLR - need_des - 29 - 1 - write-only - - - APB_SARADC2_DONE_INT_CLR - need_des - 30 - 1 - write-only - - - APB_SARADC1_DONE_INT_CLR - need_des - 31 - 1 - write-only - - - - - DMA_CONF - Register - 0x60 - 0x20 - 0x000000FF - - - APB_ADC_EOF_NUM - the dma_in_suc_eof gen when sample cnt = spi_eof_num - 0 - 16 - read-write - - - APB_ADC_RESET_FSM - reset_apb_adc_state - 30 - 1 - read-write - - - APB_ADC_TRANS - enable apb_adc use spi_dma - 31 - 1 - read-write - - - - - SAR2_DATA_STATUS - Register - 0x64 - 0x20 - - - APB_SARADC2_DATA - need_des - 0 - 17 - read-only - - - - - CALI - Register - 0x68 - 0x20 - 0x00008000 - - - CFG - need_des - 0 - 17 - read-write - - - - - RND_ECO_LOW - Register - 0x6C - 0x20 - - - RND_ECO_LOW - rnd eco low - 0 - 32 - read-write - - - - - RND_ECO_HIGH - Register - 0x70 - 0x20 - 0xFFFFFFFF - - - RND_ECO_HIGH - rnd eco high - 0 - 32 - read-write - - - - - RND_ECO_CS - Register - 0x74 - 0x20 - - - RND_ECO_EN - need_des - 0 - 1 - read-write - - - RND_ECO_RESULT - need_des - 1 - 1 - read-only - - - - - CTRL_DATE - Register - 0x3FC - 0x20 - 0x02212260 - - - CTRL_DATE - need_des - 0 - 31 - read-write - - - CLK_EN - need_des - 31 - 1 - read-write - - - - - - - AES - AES (Advanced Encryption Standard) Accelerator - AES - 0x50090000 - - 0x0 - 0xBC - registers - - - AES - 69 - - - - KEY_0 - Key material key_0 configure register - 0x0 - 0x20 - - - KEY_0 - This bits stores key_0 that is a part of key material. - 0 - 32 - read-write - - - - - KEY_1 - Key material key_1 configure register - 0x4 - 0x20 - - - KEY_1 - This bits stores key_1 that is a part of key material. - 0 - 32 - read-write - - - - - KEY_2 - Key material key_2 configure register - 0x8 - 0x20 - - - KEY_2 - This bits stores key_2 that is a part of key material. - 0 - 32 - read-write - - - - - KEY_3 - Key material key_3 configure register - 0xC - 0x20 - - - KEY_3 - This bits stores key_3 that is a part of key material. - 0 - 32 - read-write - - - - - KEY_4 - Key material key_4 configure register - 0x10 - 0x20 - - - KEY_4 - This bits stores key_4 that is a part of key material. - 0 - 32 - read-write - - - - - KEY_5 - Key material key_5 configure register - 0x14 - 0x20 - - - KEY_5 - This bits stores key_5 that is a part of key material. - 0 - 32 - read-write - - - - - KEY_6 - Key material key_6 configure register - 0x18 - 0x20 - - - KEY_6 - This bits stores key_6 that is a part of key material. - 0 - 32 - read-write - - - - - KEY_7 - Key material key_7 configure register - 0x1C - 0x20 - - - KEY_7 - This bits stores key_7 that is a part of key material. - 0 - 32 - read-write - - - - - TEXT_IN_0 - source text material text_in_0 configure register - 0x20 - 0x20 - - - TEXT_IN_0 - This bits stores text_in_0 that is a part of source text material. - 0 - 32 - read-write - - - - - TEXT_IN_1 - source text material text_in_1 configure register - 0x24 - 0x20 - - - TEXT_IN_1 - This bits stores text_in_1 that is a part of source text material. - 0 - 32 - read-write - - - - - TEXT_IN_2 - source text material text_in_2 configure register - 0x28 - 0x20 - - - TEXT_IN_2 - This bits stores text_in_2 that is a part of source text material. - 0 - 32 - read-write - - - - - TEXT_IN_3 - source text material text_in_3 configure register - 0x2C - 0x20 - - - TEXT_IN_3 - This bits stores text_in_3 that is a part of source text material. - 0 - 32 - read-write - - - - - TEXT_OUT_0 - result text material text_out_0 configure register - 0x30 - 0x20 - - - TEXT_OUT_0 - This bits stores text_out_0 that is a part of result text material. - 0 - 32 - read-write - - - - - TEXT_OUT_1 - result text material text_out_1 configure register - 0x34 - 0x20 - - - TEXT_OUT_1 - This bits stores text_out_1 that is a part of result text material. - 0 - 32 - read-write - - - - - TEXT_OUT_2 - result text material text_out_2 configure register - 0x38 - 0x20 - - - TEXT_OUT_2 - This bits stores text_out_2 that is a part of result text material. - 0 - 32 - read-write - - - - - TEXT_OUT_3 - result text material text_out_3 configure register - 0x3C - 0x20 - - - TEXT_OUT_3 - This bits stores text_out_3 that is a part of result text material. - 0 - 32 - read-write - - - - - MODE - AES Mode register - 0x40 - 0x20 - - - MODE - This bits decides which one operation mode will be used. 3'd0: AES-EN-128, 3'd1: AES-EN-192, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: AES-DE-192, 3'd6: AES-DE-256. - 0 - 3 - read-write - - - - - ENDIAN - AES Endian configure register - 0x44 - 0x20 - - - ENDIAN - endian. [1:0] key endian, [3:2] text_in endian or in_stream endian, [5:4] text_out endian or out_stream endian - 0 - 6 - read-write - - - - - TRIGGER - AES trigger register - 0x48 - 0x20 - - - TRIGGER - Set this bit to start AES calculation. - 0 - 1 - write-only - - - - - STATE - AES state register - 0x4C - 0x20 - - - STATE - Those bits shows AES status. For typical AES, 0: idle, 1: busy. For DMA-AES, 0: idle, 1: busy, 2: calculation_done. - 0 - 2 - read-only - - - - - 4 - 0x4 - IV_MEM[%s] - The memory that stores initialization vector - 0x50 - 0x20 - - - 4 - 0x4 - H_MEM[%s] - The memory that stores GCM hash subkey - 0x60 - 0x20 - - - 4 - 0x4 - J0_MEM[%s] - The memory that stores J0 - 0x70 - 0x20 - - - 4 - 0x4 - T0_MEM[%s] - The memory that stores T0 - 0x80 - 0x20 - - - DMA_ENABLE - DMA-AES working mode register - 0x90 - 0x20 - - - DMA_ENABLE - 1'b0: typical AES working mode, 1'b1: DMA-AES working mode. - 0 - 1 - read-write - - - - - BLOCK_MODE - AES cipher block mode register - 0x94 - 0x20 - - - BLOCK_MODE - Those bits decides which block mode will be used. 0x0: ECB, 0x1: CBC, 0x2: OFB, 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: GCM, 0x7: reserved. - 0 - 3 - read-write - - - - - BLOCK_NUM - AES block number register - 0x98 - 0x20 - - - BLOCK_NUM - Those bits stores the number of Plaintext/ciphertext block. - 0 - 32 - read-write - - - - - INC_SEL - Standard incrementing function configure register - 0x9C - 0x20 - - - INC_SEL - This bit decides the standard incrementing function. 0: INC32. 1: INC128. - 0 - 1 - read-write - - - - - AAD_BLOCK_NUM - Additional Authential Data block number register - 0xA0 - 0x20 - - - AAD_BLOCK_NUM - Those bits stores the number of AAD block. - 0 - 32 - read-write - - - - - REMAINDER_BIT_NUM - AES remainder bit number register - 0xA4 - 0x20 - - - REMAINDER_BIT_NUM - Those bits stores the number of remainder bit. - 0 - 7 - read-write - - - - - CONTINUE - AES continue register - 0xA8 - 0x20 - - - CONTINUE - Set this bit to continue GCM operation. - 0 - 1 - write-only - - - - - INT_CLEAR - AES Interrupt clear register - 0xAC - 0x20 - - - INT_CLEAR - Set this bit to clear the AES interrupt. - 0 - 1 - write-only - - - - - INT_ENA - AES Interrupt enable register - 0xB0 - 0x20 - - - INT_ENA - Set this bit to enable interrupt that occurs when DMA-AES calculation is done. - 0 - 1 - read-write - - - - - DATE - AES version control register - 0xB4 - 0x20 - 0x20191210 - - - DATE - This bits stores the version information of AES. - 0 - 30 - read-write - - - - - DMA_EXIT - AES-DMA exit config - 0xB8 - 0x20 - - - DMA_EXIT - Set this register to leave calculation done stage. Recommend to use it after software finishes reading DMA's output buffer. - 0 - 1 - write-only - - - - - - - AHB_DMA - AHB_DMA Peripheral - AHB_DMA - 0x50085000 - - 0x0 - 0x2C4 - registers - - - AHB_PDMA_IN_CH0 - 56 - - - AHB_PDMA_IN_CH1 - 57 - - - AHB_PDMA_IN_CH2 - 58 - - - AHB_PDMA_OUT_CH0 - 59 - - - AHB_PDMA_OUT_CH1 - 60 - - - AHB_PDMA_OUT_CH2 - 61 - - - AXI_PDMA_IN_CH0 - 62 - - - AXI_PDMA_IN_CH1 - 63 - - - AXI_PDMA_IN_CH2 - 64 - - - AXI_PDMA_OUT_CH0 - 65 - - - AXI_PDMA_OUT_CH1 - 66 - - - AXI_PDMA_OUT_CH2 - 67 - - - - 3 - 0x10 - IN_INT_RAW_CH%s - Raw status interrupt of channel 0 - 0x0 - 0x20 - - - IN_DONE_CH_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. - 0 - 1 - read-write - - - IN_SUC_EOF_CH_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0. - 1 - 1 - read-write - - - IN_ERR_EOF_CH_INT_RAW - The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw interrupt is reserved. - 2 - 1 - read-write - - - IN_DSCR_ERR_CH_INT_RAW - The raw interrupt bit turns to high level when detecting inlink descriptor error including owner error and the second and third word error of inlink descriptor for Rx channel 0. - 3 - 1 - read-write - - - IN_DSCR_EMPTY_CH_INT_RAW - The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed but there is no more inlink for Rx channel 0. - 4 - 1 - read-write - - - INFIFO_OVF_CH_INT_RAW - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow. - 5 - 1 - read-write - - - INFIFO_UDF_CH_INT_RAW - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow. - 6 - 1 - read-write - - - - - 3 - 0x10 - IN_INT_ST_CH%s - Masked interrupt of channel 0 - 0x4 - 0x20 - - - IN_DONE_CH_INT_ST - The raw interrupt status bit for the IN_DONE_CH_INT interrupt. - 0 - 1 - read-only - - - IN_SUC_EOF_CH_INT_ST - The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. - 1 - 1 - read-only - - - IN_ERR_EOF_CH_INT_ST - The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. - 2 - 1 - read-only - - - IN_DSCR_ERR_CH_INT_ST - The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. - 3 - 1 - read-only - - - IN_DSCR_EMPTY_CH_INT_ST - The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. - 4 - 1 - read-only - - - INFIFO_OVF_CH_INT_ST - The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. - 5 - 1 - read-only - - - INFIFO_UDF_CH_INT_ST - The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. - 6 - 1 - read-only - - - - - 3 - 0x10 - IN_INT_ENA_CH%s - Interrupt enable bits of channel 0 - 0x8 - 0x20 - - - IN_DONE_CH_INT_ENA - The interrupt enable bit for the IN_DONE_CH_INT interrupt. - 0 - 1 - read-write - - - IN_SUC_EOF_CH_INT_ENA - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. - 1 - 1 - read-write - - - IN_ERR_EOF_CH_INT_ENA - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. - 2 - 1 - read-write - - - IN_DSCR_ERR_CH_INT_ENA - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. - 3 - 1 - read-write - - - IN_DSCR_EMPTY_CH_INT_ENA - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. - 4 - 1 - read-write - - - INFIFO_OVF_CH_INT_ENA - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. - 5 - 1 - read-write - - - INFIFO_UDF_CH_INT_ENA - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. - 6 - 1 - read-write - - - - - 3 - 0x10 - IN_INT_CLR_CH%s - Interrupt clear bits of channel 0 - 0xC - 0x20 - - - IN_DONE_CH_INT_CLR - Set this bit to clear the IN_DONE_CH_INT interrupt. - 0 - 1 - write-only - - - IN_SUC_EOF_CH_INT_CLR - Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. - 1 - 1 - write-only - - - IN_ERR_EOF_CH_INT_CLR - Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. - 2 - 1 - write-only - - - IN_DSCR_ERR_CH_INT_CLR - Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. - 3 - 1 - write-only - - - IN_DSCR_EMPTY_CH_INT_CLR - Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. - 4 - 1 - write-only - - - INFIFO_OVF_CH_INT_CLR - Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. - 5 - 1 - write-only - - - INFIFO_UDF_CH_INT_CLR - Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. - 6 - 1 - write-only - - - - - 3 - 0x10 - OUT_INT_RAW_CH%s - Raw status interrupt of channel 0 - 0x30 - 0x20 - - - OUT_DONE_CH_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0. - 0 - 1 - read-write - - - OUT_EOF_CH_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. - 1 - 1 - read-write - - - OUT_DSCR_ERR_CH_INT_RAW - The raw interrupt bit turns to high level when detecting outlink descriptor error including owner error and the second and third word error of outlink descriptor for Tx channel 0. - 2 - 1 - read-write - - - OUT_TOTAL_EOF_CH_INT_RAW - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0. - 3 - 1 - read-write - - - OUTFIFO_OVF_CH_INT_RAW - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow. - 4 - 1 - read-write - - - OUTFIFO_UDF_CH_INT_RAW - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow. - 5 - 1 - read-write - - - - - 3 - 0x10 - OUT_INT_ST_CH%s - Masked interrupt of channel 0 - 0x34 - 0x20 - - - OUT_DONE_CH_INT_ST - The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. - 0 - 1 - read-only - - - OUT_EOF_CH_INT_ST - The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. - 1 - 1 - read-only - - - OUT_DSCR_ERR_CH_INT_ST - The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. - 2 - 1 - read-only - - - OUT_TOTAL_EOF_CH_INT_ST - The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. - 3 - 1 - read-only - - - OUTFIFO_OVF_CH_INT_ST - The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - 4 - 1 - read-only - - - OUTFIFO_UDF_CH_INT_ST - The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - 5 - 1 - read-only - - - - - 3 - 0x10 - OUT_INT_ENA_CH%s - Interrupt enable bits of channel 0 - 0x38 - 0x20 - - - OUT_DONE_CH_INT_ENA - The interrupt enable bit for the OUT_DONE_CH_INT interrupt. - 0 - 1 - read-write - - - OUT_EOF_CH_INT_ENA - The interrupt enable bit for the OUT_EOF_CH_INT interrupt. - 1 - 1 - read-write - - - OUT_DSCR_ERR_CH_INT_ENA - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. - 2 - 1 - read-write - - - OUT_TOTAL_EOF_CH_INT_ENA - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. - 3 - 1 - read-write - - - OUTFIFO_OVF_CH_INT_ENA - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - 4 - 1 - read-write - - - OUTFIFO_UDF_CH_INT_ENA - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - 5 - 1 - read-write - - - - - 3 - 0x10 - OUT_INT_CLR_CH%s - Interrupt clear bits of channel 0 - 0x3C - 0x20 - - - OUT_DONE_CH_INT_CLR - Set this bit to clear the OUT_DONE_CH_INT interrupt. - 0 - 1 - write-only - - - OUT_EOF_CH_INT_CLR - Set this bit to clear the OUT_EOF_CH_INT interrupt. - 1 - 1 - write-only - - - OUT_DSCR_ERR_CH_INT_CLR - Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. - 2 - 1 - write-only - - - OUT_TOTAL_EOF_CH_INT_CLR - Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. - 3 - 1 - write-only - - - OUTFIFO_OVF_CH_INT_CLR - Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. - 4 - 1 - write-only - - - OUTFIFO_UDF_CH_INT_CLR - Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. - 5 - 1 - write-only - - - - - AHB_TEST - reserved - 0x60 - 0x20 - - - AHB_TESTMODE - reserved - 0 - 3 - read-write - - - AHB_TESTADDR - reserved - 4 - 2 - read-write - - - - - MISC_CONF - MISC register - 0x64 - 0x20 - - - AHBM_RST_INTER - Set this bit then clear this bit to reset the internal ahb FSM. - 0 - 1 - read-write - - - ARB_PRI_DIS - Set this bit to disable priority arbitration function. - 2 - 1 - read-write - - - CLK_EN - 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers. - 3 - 1 - read-write - - - - - DATE - Version control register - 0x68 - 0x20 - 0x02303140 - - - DATE - register version. - 0 - 32 - read-write - - - - - 3 - 0xC0 - IN_CONF0_CH%s - Configure 0 register of Rx channel 0 - 0x70 - 0x20 - - - IN_RST_CH - This bit is used to reset AHB_DMA channel 0 Rx FSM and Rx FIFO pointer. - 0 - 1 - read-write - - - IN_LOOP_TEST_CH - reserved - 1 - 1 - read-write - - - INDSCR_BURST_EN_CH - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM. - 2 - 1 - read-write - - - IN_DATA_BURST_EN_CH - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM. - 3 - 1 - read-write - - - MEM_TRANS_EN_CH - Set this bit 1 to enable automatic transmitting data from memory to memory via AHB_DMA. - 4 - 1 - read-write - - - IN_ETM_EN_CH - Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm task. - 5 - 1 - read-write - - - - - 3 - 0xC0 - IN_CONF1_CH%s - Configure 1 register of Rx channel 0 - 0x74 - 0x20 - - - IN_CHECK_OWNER_CH - Set this bit to enable checking the owner attribute of the link descriptor. - 12 - 1 - read-write - - - - - 3 - 0xC0 - INFIFO_STATUS_CH%s - Receive FIFO status of Rx channel 0 - 0x78 - 0x20 - 0x07800003 - - - INFIFO_FULL_CH - L1 Rx FIFO full signal for Rx channel 0. - 0 - 1 - read-only - - - INFIFO_EMPTY_CH - L1 Rx FIFO empty signal for Rx channel 0. - 1 - 1 - read-only - - - INFIFO_CNT_CH - The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0. - 2 - 6 - read-only - - - IN_REMAIN_UNDER_1B_CH - reserved - 23 - 1 - read-only - - - IN_REMAIN_UNDER_2B_CH - reserved - 24 - 1 - read-only - - - IN_REMAIN_UNDER_3B_CH - reserved - 25 - 1 - read-only - - - IN_REMAIN_UNDER_4B_CH - reserved - 26 - 1 - read-only - - - IN_BUF_HUNGRY_CH - reserved - 27 - 1 - read-only - - - - - 3 - 0xC0 - IN_POP_CH%s - Pop control register of Rx channel 0 - 0x7C - 0x20 - 0x00000800 - - - INFIFO_RDATA_CH - This register stores the data popping from AHB_DMA FIFO. - 0 - 12 - read-only - - - INFIFO_POP_CH - Set this bit to pop data from AHB_DMA FIFO. - 12 - 1 - write-only - - - - - 3 - 0xC0 - IN_LINK_CH%s - Link descriptor configure and control register of Rx channel 0 - 0x80 - 0x20 - 0x00000011 - - - INLINK_AUTO_RET_CH - Set this bit to return to current inlink descriptor's address when there are some errors in current receiving data. - 0 - 1 - read-write - - - INLINK_STOP_CH - Set this bit to stop dealing with the inlink descriptors. - 1 - 1 - write-only - - - INLINK_START_CH - Set this bit to start dealing with the inlink descriptors. - 2 - 1 - write-only - - - INLINK_RESTART_CH - Set this bit to mount a new inlink descriptor. - 3 - 1 - write-only - - - INLINK_PARK_CH - 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. - 4 - 1 - read-only - - - - - 3 - 0xC0 - IN_STATE_CH%s - Receive status of Rx channel 0 - 0x84 - 0x20 - - - INLINK_DSCR_ADDR_CH - This register stores the current inlink descriptor's address. - 0 - 18 - read-only - - - IN_DSCR_STATE_CH - reserved - 18 - 2 - read-only - - - IN_STATE_CH - reserved - 20 - 3 - read-only - - - - - 3 - 0xC0 - IN_SUC_EOF_DES_ADDR_CH%s - Inlink descriptor address when EOF occurs of Rx channel 0 - 0x88 - 0x20 - - - IN_SUC_EOF_DES_ADDR_CH - This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. - 0 - 32 - read-only - - - - - 3 - 0xC0 - IN_ERR_EOF_DES_ADDR_CH%s - Inlink descriptor address when errors occur of Rx channel 0 - 0x8C - 0x20 - - - IN_ERR_EOF_DES_ADDR_CH - This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0. - 0 - 32 - read-only - - - - - 3 - 0xC0 - IN_DSCR_CH%s - Current inlink descriptor address of Rx channel 0 - 0x90 - 0x20 - - - INLINK_DSCR_CH - The address of the current inlink descriptor x. - 0 - 32 - read-only - - - - - 3 - 0xC0 - IN_DSCR_BF0_CH%s - The last inlink descriptor address of Rx channel 0 - 0x94 - 0x20 - - - INLINK_DSCR_BF0_CH - The address of the last inlink descriptor x-1. - 0 - 32 - read-only - - - - - 3 - 0xC0 - IN_DSCR_BF1_CH%s - The second-to-last inlink descriptor address of Rx channel 0 - 0x98 - 0x20 - - - INLINK_DSCR_BF1_CH - The address of the second-to-last inlink descriptor x-2. - 0 - 32 - read-only - - - - - 3 - 0xC0 - IN_PRI_CH%s - Priority register of Rx channel 0 - 0x9C - 0x20 - - - RX_PRI_CH - The priority of Rx channel 0. The larger of the value the higher of the priority. - 0 - 4 - read-write - - - - - 3 - 0xC0 - IN_PERI_SEL_CH%s - Peripheral selection of Rx channel 0 - 0xA0 - 0x20 - 0x0000003F - - - PERI_IN_SEL_CH - This register is used to select peripheral for Rx channel 0. I3C. 1: Dummy. 2: UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: Dummy. 7: Dummy. 8: ADC_DAC. 9: Dummy. 10: RMT,11~15: Dummy - 0 - 6 - read-write - - - - - OUT_CONF0_CH0 - Configure 0 register of Tx channel 0 - 0xD0 - 0x20 - 0x00000008 - - - OUT_RST_CH0 - This bit is used to reset AHB_DMA channel 0 Tx FSM and Tx FIFO pointer. - 0 - 1 - read-write - - - OUT_LOOP_TEST_CH0 - reserved - 1 - 1 - read-write - - - OUT_AUTO_WRBACK_CH0 - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted. - 2 - 1 - read-write - - - OUT_EOF_MODE_CH0 - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in AHB_DMA - 3 - 1 - read-write - - - OUTDSCR_BURST_EN_CH0 - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. - 4 - 1 - read-write - - - OUT_DATA_BURST_EN_CH0 - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM. - 5 - 1 - read-write - - - OUT_ETM_EN_CH0 - Set this bit to 1 to enable etm control mode, dma Tx channel 0 is triggered by etm task. - 6 - 1 - read-write - - - - - 3 - 0xC0 - OUT_CONF1_CH%s - Configure 1 register of Tx channel 0 - 0xD4 - 0x20 - - - OUT_CHECK_OWNER_CH - Set this bit to enable checking the owner attribute of the link descriptor. - 12 - 1 - read-write - - - - - 3 - 0xC0 - OUTFIFO_STATUS_CH%s - Transmit FIFO status of Tx channel 0 - 0xD8 - 0x20 - 0x07800002 - - - OUTFIFO_FULL_CH - L1 Tx FIFO full signal for Tx channel 0. - 0 - 1 - read-only - - - OUTFIFO_EMPTY_CH - L1 Tx FIFO empty signal for Tx channel 0. - 1 - 1 - read-only - - - OUTFIFO_CNT_CH - The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0. - 2 - 6 - read-only - - - OUT_REMAIN_UNDER_1B_CH - reserved - 23 - 1 - read-only - - - OUT_REMAIN_UNDER_2B_CH - reserved - 24 - 1 - read-only - - - OUT_REMAIN_UNDER_3B_CH - reserved - 25 - 1 - read-only - - - OUT_REMAIN_UNDER_4B_CH - reserved - 26 - 1 - read-only - - - - - 3 - 0xC0 - OUT_PUSH_CH%s - Push control register of Rx channel 0 - 0xDC - 0x20 - - - OUTFIFO_WDATA_CH - This register stores the data that need to be pushed into AHB_DMA FIFO. - 0 - 9 - read-write - - - OUTFIFO_PUSH_CH - Set this bit to push data into AHB_DMA FIFO. - 9 - 1 - write-only - - - - - 3 - 0xC0 - OUT_LINK_CH%s - Link descriptor configure and control register of Tx channel 0 - 0xE0 - 0x20 - 0x00000008 - - - OUTLINK_STOP_CH - Set this bit to stop dealing with the outlink descriptors. - 0 - 1 - write-only - - - OUTLINK_START_CH - Set this bit to start dealing with the outlink descriptors. - 1 - 1 - write-only - - - OUTLINK_RESTART_CH - Set this bit to restart a new outlink from the last address. - 2 - 1 - write-only - - - OUTLINK_PARK_CH - 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. - 3 - 1 - read-only - - - - - 3 - 0xC0 - OUT_STATE_CH%s - Transmit status of Tx channel 0 - 0xE4 - 0x20 - - - OUTLINK_DSCR_ADDR_CH - This register stores the current outlink descriptor's address. - 0 - 18 - read-only - - - OUT_DSCR_STATE_CH - reserved - 18 - 2 - read-only - - - OUT_STATE_CH - reserved - 20 - 3 - read-only - - - - - 3 - 0xC0 - OUT_EOF_DES_ADDR_CH%s - Outlink descriptor address when EOF occurs of Tx channel 0 - 0xE8 - 0x20 - - - OUT_EOF_DES_ADDR_CH - This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1. - 0 - 32 - read-only - - - - - 3 - 0xC0 - OUT_EOF_BFR_DES_ADDR_CH%s - The last outlink descriptor address when EOF occurs of Tx channel 0 - 0xEC - 0x20 - - - OUT_EOF_BFR_DES_ADDR_CH - This register stores the address of the outlink descriptor before the last outlink descriptor. - 0 - 32 - read-only - - - - - 3 - 0xC0 - OUT_DSCR_CH%s - Current inlink descriptor address of Tx channel 0 - 0xF0 - 0x20 - - - OUTLINK_DSCR_CH - The address of the current outlink descriptor y. - 0 - 32 - read-only - - - - - 3 - 0xC0 - OUT_DSCR_BF0_CH%s - The last inlink descriptor address of Tx channel 0 - 0xF4 - 0x20 - - - OUTLINK_DSCR_BF0_CH - The address of the last outlink descriptor y-1. - 0 - 32 - read-only - - - - - 3 - 0xC0 - OUT_DSCR_BF1_CH%s - The second-to-last inlink descriptor address of Tx channel 0 - 0xF8 - 0x20 - - - OUTLINK_DSCR_BF1_CH - The address of the second-to-last inlink descriptor x-2. - 0 - 32 - read-only - - - - - 3 - 0xC0 - OUT_PRI_CH%s - Priority register of Tx channel 0. - 0xFC - 0x20 - - - TX_PRI_CH - The priority of Tx channel 0. The larger of the value the higher of the priority. - 0 - 4 - read-write - - - - - 3 - 0xC0 - OUT_PERI_SEL_CH%s - Peripheral selection of Tx channel 0 - 0x100 - 0x20 - 0x0000003F - - - PERI_OUT_SEL_CH - This register is used to select peripheral for Tx channel 0. I3C. 1: Dummy. 2: UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: Dummy. 7: Dummy. 8: ADC_DAC. 9: Dummy. 10: RMT,11~15: Dummy - 0 - 6 - read-write - - - - - 2 - 0xC0 - OUT_CONF0_CH%s - Configure 0 register of Tx channel 1 - 0x190 - 0x20 - 0x00000008 - - - OUT_RST_CH - This bit is used to reset AHB_DMA channel 1 Tx FSM and Tx FIFO pointer. - 0 - 1 - read-write - - - OUT_LOOP_TEST_CH - reserved - 1 - 1 - read-write - - - OUT_AUTO_WRBACK_CH - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted. - 2 - 1 - read-write - - - OUT_EOF_MODE_CH - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 1 is generated when data need to transmit has been popped from FIFO in AHB_DMA - 3 - 1 - read-write - - - OUTDSCR_BURST_EN_CH - Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link descriptor when accessing internal SRAM. - 4 - 1 - read-write - - - OUT_DATA_BURST_EN_CH - Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting data when accessing internal SRAM. - 5 - 1 - read-write - - - OUT_ETM_EN_CH - Set this bit to 1 to enable etm control mode, dma Tx channel 1 is triggered by etm task. - 6 - 1 - read-write - - - - - 3 - 0x28 - OUT_CRC_INIT_DATA_CH%s - This register is used to config ch0 crc initial data(max 32 bit) - 0x2BC - 0x20 - 0xFFFFFFFF - - - OUT_CRC_INIT_DATA_CH - This register is used to config ch0 of tx crc initial value - 0 - 32 - read-write - - - - - 3 - 0x28 - TX_CRC_WIDTH_CH%s - This register is used to confiig tx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean 24<crc_width<=32 - 0x2C0 - 0x20 - - - TX_CRC_WIDTH_CH - reserved - 0 - 2 - read-write - - - TX_CRC_LAUTCH_FLGA_CH - reserved - 2 - 1 - read-write - - - - - 3 - 0x28 - OUT_CRC_CLEAR_CH%s - This register is used to clear ch0 crc result - 0x2C4 - 0x20 - - - OUT_CRC_CLEAR_CH - This register is used to clear ch0 of tx crc result - 0 - 1 - read-write - - - - - 3 - 0x28 - OUT_CRC_FINAL_RESULT_CH%s - This register is used to store ch0 crc result - 0x2C8 - 0x20 - - - OUT_CRC_FINAL_RESULT_CH - This register is used to store result ch0 of tx - 0 - 32 - read-only - - - - - 3 - 0x28 - TX_CRC_EN_WR_DATA_CH%s - This resister is used to config ch0 crc en for every bit - 0x2CC - 0x20 - - - TX_CRC_EN_WR_DATA_CH - This register is used to enable tx ch0 crc 32bit on/off - 0 - 32 - read-write - - - - - 3 - 0x28 - TX_CRC_EN_ADDR_CH%s - This register is used to config ch0 crc en addr - 0x2D0 - 0x20 - - - TX_CRC_EN_ADDR_CH - reserved - 0 - 32 - read-write - - - - - 3 - 0x28 - TX_CRC_DATA_EN_WR_DATA_CH%s - This register is used to config crc data_8bit en - 0x2D4 - 0x20 - - - TX_CRC_DATA_EN_WR_DATA_CH - reserved - 0 - 8 - read-write - - - - - 3 - 0x28 - TX_CRC_DATA_EN_ADDR_CH%s - This register is used to config addr of crc data_8bit en - 0x2D8 - 0x20 - - - TX_CRC_DATA_EN_ADDR_CH - reserved - 0 - 32 - read-write - - - - - 3 - 0x28 - TX_CH_ARB_WEIGH_CH%s - This register is used to config ch0 arbiter weigh - 0x2DC - 0x20 - - - TX_CH_ARB_WEIGH_CH - reserved - 0 - 4 - read-write - - - - - 3 - 0x28 - TX_ARB_WEIGH_OPT_DIR_CH%s - This register is used to config off or on weigh optimization - 0x2E0 - 0x20 - - - TX_ARB_WEIGH_OPT_DIR_CH - reserved - 0 - 1 - read-write - - - - - 3 - 0x28 - IN_CRC_INIT_DATA_CH%s - This register is used to config ch0 crc initial data(max 32 bit) - 0x334 - 0x20 - 0xFFFFFFFF - - - IN_CRC_INIT_DATA_CH - This register is used to config ch0 of rx crc initial value - 0 - 32 - read-write - - - - - 3 - 0x28 - RX_CRC_WIDTH_CH%s - This register is used to confiig rx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean 24<crc_width<=32 - 0x338 - 0x20 - - - RX_CRC_WIDTH_CH - reserved - 0 - 2 - read-write - - - RX_CRC_LAUTCH_FLGA_CH - reserved - 2 - 1 - read-write - - - - - 3 - 0x28 - IN_CRC_CLEAR_CH%s - This register is used to clear ch0 crc result - 0x33C - 0x20 - - - IN_CRC_CLEAR_CH - This register is used to clear ch0 of rx crc result - 0 - 1 - read-write - - - - - 3 - 0x28 - IN_CRC_FINAL_RESULT_CH%s - This register is used to store ch0 crc result - 0x340 - 0x20 - - - IN_CRC_FINAL_RESULT_CH - This register is used to store result ch0 of rx - 0 - 32 - read-only - - - - - 3 - 0x28 - RX_CRC_EN_WR_DATA_CH%s - This resister is used to config ch0 crc en for every bit - 0x344 - 0x20 - - - RX_CRC_EN_WR_DATA_CH - This register is used to enable rx ch0 crc 32bit on/off - 0 - 32 - read-write - - - - - 3 - 0x28 - RX_CRC_EN_ADDR_CH%s - This register is used to config ch0 crc en addr - 0x348 - 0x20 - - - RX_CRC_EN_ADDR_CH - reserved - 0 - 32 - read-write - - - - - 3 - 0x28 - RX_CRC_DATA_EN_WR_DATA_CH%s - This register is used to config crc data_8bit en - 0x34C - 0x20 - - - RX_CRC_DATA_EN_WR_DATA_CH - reserved - 0 - 8 - read-write - - - - - 3 - 0x28 - RX_CRC_DATA_EN_ADDR_CH%s - This register is used to config addr of crc data_8bit en - 0x350 - 0x20 - - - RX_CRC_DATA_EN_ADDR_CH - reserved - 0 - 32 - read-write - - - - - 3 - 0x28 - RX_CH_ARB_WEIGH_CH%s - This register is used to config ch0 arbiter weigh - 0x354 - 0x20 - - - RX_CH_ARB_WEIGH_CH - reserved - 0 - 4 - read-write - - - - - 3 - 0x28 - RX_ARB_WEIGH_OPT_DIR_CH%s - This register is used to config off or on weigh optimization - 0x358 - 0x20 - - - RX_ARB_WEIGH_OPT_DIR_CH - reserved - 0 - 1 - read-write - - - - - 3 - 0x4 - IN_LINK_ADDR_CH%s - Link descriptor configure of Rx channel 0 - 0x3AC - 0x20 - - - INLINK_ADDR_CH - This register stores the 32 least significant bits of the first inlink descriptor's address. - 0 - 32 - read-write - - - - - 3 - 0x4 - OUT_LINK_ADDR_CH%s - Link descriptor configure of Tx channel 0 - 0x3B8 - 0x20 - - - OUTLINK_ADDR_CH - This register stores the 32 least significant bits of the first outlink descriptor's address. - 0 - 32 - read-write - - - - - INTR_MEM_START_ADDR - The start address of accessible address space. - 0x3C4 - 0x20 - - - ACCESS_INTR_MEM_START_ADDR - The start address of accessible address space. - 0 - 32 - read-write - - - - - INTR_MEM_END_ADDR - The end address of accessible address space. The access address beyond this range would lead to descriptor error. - 0x3C8 - 0x20 - 0xFFFFFFFF - - - ACCESS_INTR_MEM_END_ADDR - The end address of accessible address space. The access address beyond this range would lead to descriptor error. - 0 - 32 - read-write - - - - - ARB_TIMEOUT_TX - This retister is used to config arbiter time slice for tx dir - 0x3CC - 0x20 - - - ARB_TIMEOUT_TX - This register is used to config arbiter time out value - 0 - 16 - read-write - - - - - ARB_TIMEOUT_RX - This retister is used to config arbiter time slice for rx dir - 0x3D0 - 0x20 - - - ARB_TIMEOUT_RX - This register is used to config arbiter time out value - 0 - 16 - read-write - - - - - WEIGHT_EN_TX - This register is used to config arbiter weigh function to on or off for tx dir - 0x3D4 - 0x20 - - - WEIGHT_EN_TX - This register is used to config arbiter weight function off/on - 0 - 1 - read-write - - - - - WEIGHT_EN_RX - This register is used to config arbiter weigh function to on or off for rx dir - 0x3D8 - 0x20 - - - WEIGHT_EN_RX - This register is used to config arbiter weight function off/on - 0 - 1 - read-write - - - - - - - LP_I2C_ANA_MST - LP_I2C_ANA_MST Peripheral - ANA_I2C_MST - 0x50124000 - - 0x0 - 0x3C - registers - - - - I2C0_CTRL - need des - 0x0 - 0x20 - - - I2C0_CTRL - need des - 0 - 25 - read-write - - - I2C0_BUSY - need des - 25 - 1 - read-only - - - - - I2C1_CTRL - need des - 0x4 - 0x20 - - - I2C1_CTRL - need des - 0 - 25 - read-write - - - I2C1_BUSY - need des - 25 - 1 - read-only - - - - - I2C0_CONF - need des - 0x8 - 0x20 - - - I2C0_CONF - need des - 0 - 24 - read-write - - - I2C0_STATUS - need des - 24 - 8 - read-only - - - - - I2C1_CONF - need des - 0xC - 0x20 - - - I2C1_CONF - need des - 0 - 24 - read-write - - - I2C1_STATUS - need des - 24 - 8 - read-only - - - - - I2C_BURST_CONF - need des - 0x10 - 0x20 - - - I2C_MST_BURST_CTRL - need des - 0 - 32 - read-write - - - - - I2C_BURST_STATUS - need des - 0x14 - 0x20 - 0x40000000 - - - I2C_MST_BURST_DONE - need des - 0 - 1 - read-only - - - I2C_MST0_BURST_ERR_FLAG - need des - 1 - 1 - read-only - - - I2C_MST1_BURST_ERR_FLAG - need des - 2 - 1 - read-only - - - I2C_MST_BURST_TIMEOUT_CNT - need des - 20 - 12 - read-write - - - - - ANA_CONF0 - need des - 0x18 - 0x20 - - - ANA_CONF0 - need des - 0 - 24 - read-write - - - ANA_STATUS0 - need des - 24 - 8 - read-only - - - - - ANA_CONF1 - need des - 0x1C - 0x20 - - - ANA_CONF1 - need des - 0 - 24 - read-write - - - ANA_STATUS1 - need des - 24 - 8 - read-only - - - - - ANA_CONF2 - need des - 0x20 - 0x20 - - - ANA_CONF2 - need des - 0 - 24 - read-write - - - ANA_STATUS2 - need des - 24 - 8 - read-only - - - - - I2C0_CTRL1 - need des - 0x24 - 0x20 - 0x00000042 - - - I2C0_SCL_PULSE_DUR - need des - 0 - 6 - read-write - - - I2C0_SDA_SIDE_GUARD - need des - 6 - 5 - read-write - - - - - I2C1_CTRL1 - need des - 0x28 - 0x20 - 0x00000042 - - - I2C1_SCL_PULSE_DUR - need des - 0 - 6 - read-write - - - I2C1_SDA_SIDE_GUARD - need des - 6 - 5 - read-write - - - - - HW_I2C_CTRL - need des - 0x2C - 0x20 - 0x00000042 - - - HW_I2C_SCL_PULSE_DUR - need des - 0 - 6 - read-write - - - HW_I2C_SDA_SIDE_GUARD - need des - 6 - 5 - read-write - - - ARBITER_DIS - need des - 11 - 1 - read-write - - - - - NOUSE - need des - 0x30 - 0x20 - - - I2C_MST_NOUSE - need des - 0 - 32 - read-write - - - - - CLK160M - need des - 0x34 - 0x20 - - - CLK_I2C_MST_SEL_160M - need des - 0 - 1 - read-write - - - - - DATE - need des - 0x38 - 0x20 - 0x02201300 - - - DATE - need des - 0 - 28 - read-write - - - I2C_MST_CLK_EN - need des - 28 - 1 - read-write - - - - - - - ASSIST_DEBUG - Debug Assist - ASSIST_DEBUG - 0x3FF06000 - - 0x0 - 0x100 - registers - - - ASSIST_DEBUG - 127 - - - - CORE_0_INTR_ENA - core0 monitor enable configuration register - 0x0 - 0x20 - - - CORE_0_AREA_DRAM0_0_RD_ENA - Core0 dram0 area0 read monitor enable - 0 - 1 - read-write - - - CORE_0_AREA_DRAM0_0_WR_ENA - Core0 dram0 area0 write monitor enable - 1 - 1 - read-write - - - CORE_0_AREA_DRAM0_1_RD_ENA - Core0 dram0 area1 read monitor enable - 2 - 1 - read-write - - - CORE_0_AREA_DRAM0_1_WR_ENA - Core0 dram0 area1 write monitor enable - 3 - 1 - read-write - - - CORE_0_AREA_PIF_0_RD_ENA - Core0 PIF area0 read monitor enable - 4 - 1 - read-write - - - CORE_0_AREA_PIF_0_WR_ENA - Core0 PIF area0 write monitor enable - 5 - 1 - read-write - - - CORE_0_AREA_PIF_1_RD_ENA - Core0 PIF area1 read monitor enable - 6 - 1 - read-write - - - CORE_0_AREA_PIF_1_WR_ENA - Core0 PIF area1 write monitor enable - 7 - 1 - read-write - - - CORE_0_SP_SPILL_MIN_ENA - Core0 stackpoint underflow monitor enable - 8 - 1 - read-write - - - CORE_0_SP_SPILL_MAX_ENA - Core0 stackpoint overflow monitor enable - 9 - 1 - read-write - - - CORE_0_IRAM0_EXCEPTION_MONITOR_ENA - IBUS busy monitor enable - 10 - 1 - read-write - - - CORE_0_DRAM0_EXCEPTION_MONITOR_ENA - DBUS busy monitor enbale - 11 - 1 - read-write - - - - - CORE_0_INTR_RAW - core0 monitor interrupt status register - 0x4 - 0x20 - - - CORE_0_AREA_DRAM0_0_RD_RAW - Core0 dram0 area0 read monitor interrupt status - 0 - 1 - read-only - - - CORE_0_AREA_DRAM0_0_WR_RAW - Core0 dram0 area0 write monitor interrupt status - 1 - 1 - read-only - - - CORE_0_AREA_DRAM0_1_RD_RAW - Core0 dram0 area1 read monitor interrupt status - 2 - 1 - read-only - - - CORE_0_AREA_DRAM0_1_WR_RAW - Core0 dram0 area1 write monitor interrupt status - 3 - 1 - read-only - - - CORE_0_AREA_PIF_0_RD_RAW - Core0 PIF area0 read monitor interrupt status - 4 - 1 - read-only - - - CORE_0_AREA_PIF_0_WR_RAW - Core0 PIF area0 write monitor interrupt status - 5 - 1 - read-only - - - CORE_0_AREA_PIF_1_RD_RAW - Core0 PIF area1 read monitor interrupt status - 6 - 1 - read-only - - - CORE_0_AREA_PIF_1_WR_RAW - Core0 PIF area1 write monitor interrupt status - 7 - 1 - read-only - - - CORE_0_SP_SPILL_MIN_RAW - Core0 stackpoint underflow monitor interrupt status - 8 - 1 - read-only - - - CORE_0_SP_SPILL_MAX_RAW - Core0 stackpoint overflow monitor interrupt status - 9 - 1 - read-only - - - CORE_0_IRAM0_EXCEPTION_MONITOR_RAW - IBUS busy monitor interrupt status - 10 - 1 - read-only - - - CORE_0_DRAM0_EXCEPTION_MONITOR_RAW - DBUS busy monitor initerrupt status - 11 - 1 - read-only - - - - - CORE_0_INTR_RLS - core0 monitor interrupt enable register - 0x8 - 0x20 - - - CORE_0_AREA_DRAM0_0_RD_RLS - Core0 dram0 area0 read monitor interrupt enable - 0 - 1 - read-write - - - CORE_0_AREA_DRAM0_0_WR_RLS - Core0 dram0 area0 write monitor interrupt enable - 1 - 1 - read-write - - - CORE_0_AREA_DRAM0_1_RD_RLS - Core0 dram0 area1 read monitor interrupt enable - 2 - 1 - read-write - - - CORE_0_AREA_DRAM0_1_WR_RLS - Core0 dram0 area1 write monitor interrupt enable - 3 - 1 - read-write - - - CORE_0_AREA_PIF_0_RD_RLS - Core0 PIF area0 read monitor interrupt enable - 4 - 1 - read-write - - - CORE_0_AREA_PIF_0_WR_RLS - Core0 PIF area0 write monitor interrupt enable - 5 - 1 - read-write - - - CORE_0_AREA_PIF_1_RD_RLS - Core0 PIF area1 read monitor interrupt enable - 6 - 1 - read-write - - - CORE_0_AREA_PIF_1_WR_RLS - Core0 PIF area1 write monitor interrupt enable - 7 - 1 - read-write - - - CORE_0_SP_SPILL_MIN_RLS - Core0 stackpoint underflow monitor interrupt enable - 8 - 1 - read-write - - - CORE_0_SP_SPILL_MAX_RLS - Core0 stackpoint overflow monitor interrupt enable - 9 - 1 - read-write - - - CORE_0_IRAM0_EXCEPTION_MONITOR_RLS - IBUS busy monitor interrupt enable - 10 - 1 - read-write - - - CORE_0_DRAM0_EXCEPTION_MONITOR_RLS - DBUS busy monitor interrupt enbale - 11 - 1 - read-write - - - - - CORE_0_INTR_CLR - core0 monitor interrupt clr register - 0xC - 0x20 - - - CORE_0_AREA_DRAM0_0_RD_CLR - Core0 dram0 area0 read monitor interrupt clr - 0 - 1 - write-only - - - CORE_0_AREA_DRAM0_0_WR_CLR - Core0 dram0 area0 write monitor interrupt clr - 1 - 1 - write-only - - - CORE_0_AREA_DRAM0_1_RD_CLR - Core0 dram0 area1 read monitor interrupt clr - 2 - 1 - write-only - - - CORE_0_AREA_DRAM0_1_WR_CLR - Core0 dram0 area1 write monitor interrupt clr - 3 - 1 - write-only - - - CORE_0_AREA_PIF_0_RD_CLR - Core0 PIF area0 read monitor interrupt clr - 4 - 1 - write-only - - - CORE_0_AREA_PIF_0_WR_CLR - Core0 PIF area0 write monitor interrupt clr - 5 - 1 - write-only - - - CORE_0_AREA_PIF_1_RD_CLR - Core0 PIF area1 read monitor interrupt clr - 6 - 1 - write-only - - - CORE_0_AREA_PIF_1_WR_CLR - Core0 PIF area1 write monitor interrupt clr - 7 - 1 - write-only - - - CORE_0_SP_SPILL_MIN_CLR - Core0 stackpoint underflow monitor interrupt clr - 8 - 1 - write-only - - - CORE_0_SP_SPILL_MAX_CLR - Core0 stackpoint overflow monitor interrupt clr - 9 - 1 - write-only - - - CORE_0_IRAM0_EXCEPTION_MONITOR_CLR - IBUS busy monitor interrupt clr - 10 - 1 - write-only - - - CORE_0_DRAM0_EXCEPTION_MONITOR_CLR - DBUS busy monitor interrupt clr - 11 - 1 - write-only - - - - - CORE_0_AREA_DRAM0_0_MIN - core0 dram0 region0 addr configuration register - 0x10 - 0x20 - 0xFFFFFFFF - - - CORE_0_AREA_DRAM0_0_MIN - Core0 dram0 region0 start addr - 0 - 32 - read-write - - - - - CORE_0_AREA_DRAM0_0_MAX - core0 dram0 region0 addr configuration register - 0x14 - 0x20 - - - CORE_0_AREA_DRAM0_0_MAX - Core0 dram0 region0 end addr - 0 - 32 - read-write - - - - - CORE_0_AREA_DRAM0_1_MIN - core0 dram0 region1 addr configuration register - 0x18 - 0x20 - 0xFFFFFFFF - - - CORE_0_AREA_DRAM0_1_MIN - Core0 dram0 region1 start addr - 0 - 32 - read-write - - - - - CORE_0_AREA_DRAM0_1_MAX - core0 dram0 region1 addr configuration register - 0x1C - 0x20 - - - CORE_0_AREA_DRAM0_1_MAX - Core0 dram0 region1 end addr - 0 - 32 - read-write - - - - - CORE_0_AREA_PIF_0_MIN - core0 PIF region0 addr configuration register - 0x20 - 0x20 - 0xFFFFFFFF - - - CORE_0_AREA_PIF_0_MIN - Core0 PIF region0 start addr - 0 - 32 - read-write - - - - - CORE_0_AREA_PIF_0_MAX - core0 PIF region0 addr configuration register - 0x24 - 0x20 - - - CORE_0_AREA_PIF_0_MAX - Core0 PIF region0 end addr - 0 - 32 - read-write - - - - - CORE_0_AREA_PIF_1_MIN - core0 PIF region1 addr configuration register - 0x28 - 0x20 - 0xFFFFFFFF - - - CORE_0_AREA_PIF_1_MIN - Core0 PIF region1 start addr - 0 - 32 - read-write - - - - - CORE_0_AREA_PIF_1_MAX - core0 PIF region1 addr configuration register - 0x2C - 0x20 - - - CORE_0_AREA_PIF_1_MAX - Core0 PIF region1 end addr - 0 - 32 - read-write - - - - - CORE_0_AREA_PC - core0 area pc status register - 0x30 - 0x20 - - - CORE_0_AREA_PC - the stackpointer when first touch region monitor interrupt - 0 - 32 - read-only - - - - - CORE_0_AREA_SP - core0 area sp status register - 0x34 - 0x20 - - - CORE_0_AREA_SP - the PC when first touch region monitor interrupt - 0 - 32 - read-only - - - - - CORE_0_SP_MIN - stack min value - 0x38 - 0x20 - - - CORE_0_SP_MIN - core0 sp region configuration regsiter - 0 - 32 - read-write - - - - - CORE_0_SP_MAX - stack max value - 0x3C - 0x20 - 0xFFFFFFFF - - - CORE_0_SP_MAX - core0 sp pc status register - 0 - 32 - read-write - - - - - CORE_0_SP_PC - stack monitor pc status register - 0x40 - 0x20 - - - CORE_0_SP_PC - This regsiter stores the PC when trigger stack monitor. - 0 - 32 - read-only - - - - - CORE_0_RCD_EN - record enable configuration register - 0x44 - 0x20 - - - CORE_0_RCD_RECORDEN - Set 1 to enable record PC - 0 - 1 - read-write - - - CORE_0_RCD_PDEBUGEN - Set 1 to enable cpu pdebug function, must set this bit can get cpu PC - 1 - 1 - read-write - - - - - CORE_0_RCD_PDEBUGPC - record status regsiter - 0x48 - 0x20 - - - CORE_0_RCD_PDEBUGPC - recorded PC - 0 - 32 - read-only - - - - - CORE_0_RCD_PDEBUGSP - record status regsiter - 0x4C - 0x20 - - - CORE_0_RCD_PDEBUGSP - recorded sp - 0 - 32 - read-only - - - - - CORE_0_IRAM0_EXCEPTION_MONITOR_0 - exception monitor status register0 - 0x50 - 0x20 - - - CORE_0_IRAM0_RECORDING_ADDR_0 - reg_core_0_iram0_recording_addr_0 - 0 - 24 - read-only - - - CORE_0_IRAM0_RECORDING_WR_0 - reg_core_0_iram0_recording_wr_0 - 24 - 1 - read-only - - - CORE_0_IRAM0_RECORDING_LOADSTORE_0 - reg_core_0_iram0_recording_loadstore_0 - 25 - 1 - read-only - - - - - CORE_0_IRAM0_EXCEPTION_MONITOR_1 - exception monitor status register1 - 0x54 - 0x20 - - - CORE_0_IRAM0_RECORDING_ADDR_1 - reg_core_0_iram0_recording_addr_1 - 0 - 24 - read-only - - - CORE_0_IRAM0_RECORDING_WR_1 - reg_core_0_iram0_recording_wr_1 - 24 - 1 - read-only - - - CORE_0_IRAM0_RECORDING_LOADSTORE_1 - reg_core_0_iram0_recording_loadstore_1 - 25 - 1 - read-only - - - - - CORE_0_DRAM0_EXCEPTION_MONITOR_0 - exception monitor status register2 - 0x58 - 0x20 - - - CORE_0_DRAM0_RECORDING_WR_0 - reg_core_0_dram0_recording_wr_0 - 0 - 1 - read-only - - - CORE_0_DRAM0_RECORDING_BYTEEN_0 - reg_core_0_dram0_recording_byteen_0 - 1 - 16 - read-only - - - - - CORE_0_DRAM0_EXCEPTION_MONITOR_1 - exception monitor status register3 - 0x5C - 0x20 - - - CORE_0_DRAM0_RECORDING_ADDR_0 - reg_core_0_dram0_recording_addr_0 - 0 - 24 - read-only - - - - - CORE_0_DRAM0_EXCEPTION_MONITOR_2 - exception monitor status register4 - 0x60 - 0x20 - - - CORE_0_DRAM0_RECORDING_PC_0 - reg_core_0_dram0_recording_pc_0 - 0 - 32 - read-only - - - - - CORE_0_DRAM0_EXCEPTION_MONITOR_3 - exception monitor status register5 - 0x64 - 0x20 - - - CORE_0_DRAM0_RECORDING_WR_1 - reg_core_0_dram0_recording_wr_1 - 0 - 1 - read-only - - - CORE_0_DRAM0_RECORDING_BYTEEN_1 - reg_core_0_dram0_recording_byteen_1 - 1 - 16 - read-only - - - - - CORE_0_DRAM0_EXCEPTION_MONITOR_4 - exception monitor status register6 - 0x68 - 0x20 - - - CORE_0_DRAM0_RECORDING_ADDR_1 - reg_core_0_dram0_recording_addr_1 - 0 - 24 - read-only - - - - - CORE_0_DRAM0_EXCEPTION_MONITOR_5 - exception monitor status register7 - 0x6C - 0x20 - - - CORE_0_DRAM0_RECORDING_PC_1 - reg_core_0_dram0_recording_pc_1 - 0 - 32 - read-only - - - - - CORE_0_LASTPC_BEFORE_EXCEPTION - cpu status register - 0x70 - 0x20 - - - CORE_0_LASTPC_BEFORE_EXC - cpu's lastpc before exception - 0 - 32 - read-only - - - - - CORE_0_DEBUG_MODE - cpu status register - 0x74 - 0x20 - - - CORE_0_DEBUG_MODE - cpu debug mode status, 1 means cpu enter debug mode. - 0 - 1 - read-only - - - CORE_0_DEBUG_MODULE_ACTIVE - cpu debug_module active status - 1 - 1 - read-only - - - - - CORE_1_INTR_ENA - core1 monitor enable configuration register - 0x80 - 0x20 - - - CORE_1_AREA_DRAM0_0_RD_ENA - Core1 dram0 area0 read monitor enable - 0 - 1 - read-write - - - CORE_1_AREA_DRAM0_0_WR_ENA - Core1 dram0 area0 write monitor enable - 1 - 1 - read-write - - - CORE_1_AREA_DRAM0_1_RD_ENA - Core1 dram0 area1 read monitor enable - 2 - 1 - read-write - - - CORE_1_AREA_DRAM0_1_WR_ENA - Core1 dram0 area1 write monitor enable - 3 - 1 - read-write - - - CORE_1_AREA_PIF_0_RD_ENA - Core1 PIF area0 read monitor enable - 4 - 1 - read-write - - - CORE_1_AREA_PIF_0_WR_ENA - Core1 PIF area0 write monitor enable - 5 - 1 - read-write - - - CORE_1_AREA_PIF_1_RD_ENA - Core1 PIF area1 read monitor enable - 6 - 1 - read-write - - - CORE_1_AREA_PIF_1_WR_ENA - Core1 PIF area1 write monitor enable - 7 - 1 - read-write - - - CORE_1_SP_SPILL_MIN_ENA - Core1 stackpoint underflow monitor enable - 8 - 1 - read-write - - - CORE_1_SP_SPILL_MAX_ENA - Core1 stackpoint overflow monitor enable - 9 - 1 - read-write - - - CORE_1_IRAM0_EXCEPTION_MONITOR_ENA - IBUS busy monitor enable - 10 - 1 - read-write - - - CORE_1_DRAM0_EXCEPTION_MONITOR_ENA - DBUS busy monitor enbale - 11 - 1 - read-write - - - - - CORE_1_INTR_RAW - core1 monitor interrupt status register - 0x84 - 0x20 - - - CORE_1_AREA_DRAM0_0_RD_RAW - Core1 dram0 area0 read monitor interrupt status - 0 - 1 - read-only - - - CORE_1_AREA_DRAM0_0_WR_RAW - Core1 dram0 area0 write monitor interrupt status - 1 - 1 - read-only - - - CORE_1_AREA_DRAM0_1_RD_RAW - Core1 dram0 area1 read monitor interrupt status - 2 - 1 - read-only - - - CORE_1_AREA_DRAM0_1_WR_RAW - Core1 dram0 area1 write monitor interrupt status - 3 - 1 - read-only - - - CORE_1_AREA_PIF_0_RD_RAW - Core1 PIF area0 read monitor interrupt status - 4 - 1 - read-only - - - CORE_1_AREA_PIF_0_WR_RAW - Core1 PIF area0 write monitor interrupt status - 5 - 1 - read-only - - - CORE_1_AREA_PIF_1_RD_RAW - Core1 PIF area1 read monitor interrupt status - 6 - 1 - read-only - - - CORE_1_AREA_PIF_1_WR_RAW - Core1 PIF area1 write monitor interrupt status - 7 - 1 - read-only - - - CORE_1_SP_SPILL_MIN_RAW - Core1 stackpoint underflow monitor interrupt status - 8 - 1 - read-only - - - CORE_1_SP_SPILL_MAX_RAW - Core1 stackpoint overflow monitor interrupt status - 9 - 1 - read-only - - - CORE_1_IRAM0_EXCEPTION_MONITOR_RAW - IBUS busy monitor interrupt status - 10 - 1 - read-only - - - CORE_1_DRAM0_EXCEPTION_MONITOR_RAW - DBUS busy monitor initerrupt status - 11 - 1 - read-only - - - - - CORE_1_INTR_RLS - core1 monitor interrupt enable register - 0x88 - 0x20 - - - CORE_1_AREA_DRAM0_0_RD_RLS - Core1 dram0 area0 read monitor interrupt enable - 0 - 1 - read-write - - - CORE_1_AREA_DRAM0_0_WR_RLS - Core1 dram0 area0 write monitor interrupt enable - 1 - 1 - read-write - - - CORE_1_AREA_DRAM0_1_RD_RLS - Core1 dram0 area1 read monitor interrupt enable - 2 - 1 - read-write - - - CORE_1_AREA_DRAM0_1_WR_RLS - Core1 dram0 area1 write monitor interrupt enable - 3 - 1 - read-write - - - CORE_1_AREA_PIF_0_RD_RLS - Core1 PIF area0 read monitor interrupt enable - 4 - 1 - read-write - - - CORE_1_AREA_PIF_0_WR_RLS - Core1 PIF area0 write monitor interrupt enable - 5 - 1 - read-write - - - CORE_1_AREA_PIF_1_RD_RLS - Core1 PIF area1 read monitor interrupt enable - 6 - 1 - read-write - - - CORE_1_AREA_PIF_1_WR_RLS - Core1 PIF area1 write monitor interrupt enable - 7 - 1 - read-write - - - CORE_1_SP_SPILL_MIN_RLS - Core1 stackpoint underflow monitor interrupt enable - 8 - 1 - read-write - - - CORE_1_SP_SPILL_MAX_RLS - Core1 stackpoint overflow monitor interrupt enable - 9 - 1 - read-write - - - CORE_1_IRAM0_EXCEPTION_MONITOR_RLS - IBUS busy monitor interrupt enable - 10 - 1 - read-write - - - CORE_1_DRAM0_EXCEPTION_MONITOR_RLS - DBUS busy monitor interrupt enbale - 11 - 1 - read-write - - - - - CORE_1_INTR_CLR - core1 monitor interrupt clr register - 0x8C - 0x20 - - - CORE_1_AREA_DRAM0_0_RD_CLR - Core1 dram0 area0 read monitor interrupt clr - 0 - 1 - write-only - - - CORE_1_AREA_DRAM0_0_WR_CLR - Core1 dram0 area0 write monitor interrupt clr - 1 - 1 - write-only - - - CORE_1_AREA_DRAM0_1_RD_CLR - Core1 dram0 area1 read monitor interrupt clr - 2 - 1 - write-only - - - CORE_1_AREA_DRAM0_1_WR_CLR - Core1 dram0 area1 write monitor interrupt clr - 3 - 1 - write-only - - - CORE_1_AREA_PIF_0_RD_CLR - Core1 PIF area0 read monitor interrupt clr - 4 - 1 - write-only - - - CORE_1_AREA_PIF_0_WR_CLR - Core1 PIF area0 write monitor interrupt clr - 5 - 1 - write-only - - - CORE_1_AREA_PIF_1_RD_CLR - Core1 PIF area1 read monitor interrupt clr - 6 - 1 - write-only - - - CORE_1_AREA_PIF_1_WR_CLR - Core1 PIF area1 write monitor interrupt clr - 7 - 1 - write-only - - - CORE_1_SP_SPILL_MIN_CLR - Core1 stackpoint underflow monitor interrupt clr - 8 - 1 - write-only - - - CORE_1_SP_SPILL_MAX_CLR - Core1 stackpoint overflow monitor interrupt clr - 9 - 1 - write-only - - - CORE_1_IRAM0_EXCEPTION_MONITOR_CLR - IBUS busy monitor interrupt clr - 10 - 1 - write-only - - - CORE_1_DRAM0_EXCEPTION_MONITOR_CLR - DBUS busy monitor interrupt clr - 11 - 1 - write-only - - - - - CORE_1_AREA_DRAM0_0_MIN - core1 dram0 region0 addr configuration register - 0x90 - 0x20 - 0xFFFFFFFF - - - CORE_1_AREA_DRAM0_0_MIN - Core1 dram0 region0 start addr - 0 - 32 - read-write - - - - - CORE_1_AREA_DRAM0_0_MAX - core1 dram0 region0 addr configuration register - 0x94 - 0x20 - - - CORE_1_AREA_DRAM0_0_MAX - Core1 dram0 region0 end addr - 0 - 32 - read-write - - - - - CORE_1_AREA_DRAM0_1_MIN - core1 dram0 region1 addr configuration register - 0x98 - 0x20 - 0xFFFFFFFF - - - CORE_1_AREA_DRAM0_1_MIN - Core1 dram0 region1 start addr - 0 - 32 - read-write - - - - - CORE_1_AREA_DRAM0_1_MAX - core1 dram0 region1 addr configuration register - 0x9C - 0x20 - - - CORE_1_AREA_DRAM0_1_MAX - Core1 dram0 region1 end addr - 0 - 32 - read-write - - - - - CORE_1_AREA_PIF_0_MIN - core1 PIF region0 addr configuration register - 0xA0 - 0x20 - 0xFFFFFFFF - - - CORE_1_AREA_PIF_0_MIN - Core1 PIF region0 start addr - 0 - 32 - read-write - - - - - CORE_1_AREA_PIF_0_MAX - core1 PIF region0 addr configuration register - 0xA4 - 0x20 - - - CORE_1_AREA_PIF_0_MAX - Core1 PIF region0 end addr - 0 - 32 - read-write - - - - - CORE_1_AREA_PIF_1_MIN - core1 PIF region1 addr configuration register - 0xA8 - 0x20 - 0xFFFFFFFF - - - CORE_1_AREA_PIF_1_MIN - Core1 PIF region1 start addr - 0 - 32 - read-write - - - - - CORE_1_AREA_PIF_1_MAX - core1 PIF region1 addr configuration register - 0xAC - 0x20 - - - CORE_1_AREA_PIF_1_MAX - Core1 PIF region1 end addr - 0 - 32 - read-write - - - - - CORE_1_AREA_PC - core1 area pc status register - 0xB0 - 0x20 - - - CORE_1_AREA_PC - the stackpointer when first touch region monitor interrupt - 0 - 32 - read-only - - - - - CORE_1_AREA_SP - core1 area sp status register - 0xB4 - 0x20 - - - CORE_1_AREA_SP - the PC when first touch region monitor interrupt - 0 - 32 - read-only - - - - - CORE_1_SP_MIN - stack min value - 0xB8 - 0x20 - - - CORE_1_SP_MIN - core1 sp region configuration regsiter - 0 - 32 - read-write - - - - - CORE_1_SP_MAX - stack max value - 0xBC - 0x20 - 0xFFFFFFFF - - - CORE_1_SP_MAX - core1 sp pc status register - 0 - 32 - read-write - - - - - CORE_1_SP_PC - stack monitor pc status register - 0xC0 - 0x20 - - - CORE_1_SP_PC - This regsiter stores the PC when trigger stack monitor. - 0 - 32 - read-only - - - - - CORE_1_RCD_EN - record enable configuration register - 0xC4 - 0x20 - - - CORE_1_RCD_RECORDEN - Set 1 to enable record PC - 0 - 1 - read-write - - - CORE_1_RCD_PDEBUGEN - Set 1 to enable cpu pdebug function, must set this bit can get cpu PC - 1 - 1 - read-write - - - - - CORE_1_RCD_PDEBUGPC - record status regsiter - 0xC8 - 0x20 - - - CORE_1_RCD_PDEBUGPC - recorded PC - 0 - 32 - read-only - - - - - CORE_1_RCD_PDEBUGSP - record status regsiter - 0xCC - 0x20 - - - CORE_1_RCD_PDEBUGSP - recorded sp - 0 - 32 - read-only - - - - - CORE_1_IRAM0_EXCEPTION_MONITOR_0 - exception monitor status register0 - 0xD0 - 0x20 - - - CORE_1_IRAM0_RECORDING_ADDR_0 - reg_core_1_iram0_recording_addr_0 - 0 - 24 - read-only - - - CORE_1_IRAM0_RECORDING_WR_0 - reg_core_1_iram0_recording_wr_0 - 24 - 1 - read-only - - - CORE_1_IRAM0_RECORDING_LOADSTORE_0 - reg_core_1_iram0_recording_loadstore_0 - 25 - 1 - read-only - - - - - CORE_1_IRAM0_EXCEPTION_MONITOR_1 - exception monitor status register1 - 0xD4 - 0x20 - - - CORE_1_IRAM0_RECORDING_ADDR_1 - reg_core_1_iram0_recording_addr_1 - 0 - 24 - read-only - - - CORE_1_IRAM0_RECORDING_WR_1 - reg_core_1_iram0_recording_wr_1 - 24 - 1 - read-only - - - CORE_1_IRAM0_RECORDING_LOADSTORE_1 - reg_core_1_iram0_recording_loadstore_1 - 25 - 1 - read-only - - - - - CORE_1_DRAM0_EXCEPTION_MONITOR_0 - exception monitor status register2 - 0xD8 - 0x20 - - - CORE_1_DRAM0_RECORDING_WR_0 - reg_core_1_dram0_recording_wr_0 - 0 - 1 - read-only - - - CORE_1_DRAM0_RECORDING_BYTEEN_0 - reg_core_1_dram0_recording_byteen_0 - 1 - 16 - read-only - - - - - CORE_1_DRAM0_EXCEPTION_MONITOR_1 - exception monitor status register3 - 0xDC - 0x20 - - - CORE_1_DRAM0_RECORDING_ADDR_0 - reg_core_1_dram0_recording_addr_0 - 0 - 24 - read-only - - - - - CORE_1_DRAM0_EXCEPTION_MONITOR_2 - exception monitor status register4 - 0xE0 - 0x20 - - - CORE_1_DRAM0_RECORDING_PC_0 - reg_core_1_dram0_recording_pc_0 - 0 - 32 - read-only - - - - - CORE_1_DRAM0_EXCEPTION_MONITOR_3 - exception monitor status register5 - 0xE4 - 0x20 - - - CORE_1_DRAM0_RECORDING_WR_1 - reg_core_1_dram0_recording_wr_1 - 0 - 1 - read-only - - - CORE_1_DRAM0_RECORDING_BYTEEN_1 - reg_core_1_dram0_recording_byteen_1 - 1 - 16 - read-only - - - - - CORE_1_DRAM0_EXCEPTION_MONITOR_4 - exception monitor status register6 - 0xE8 - 0x20 - - - CORE_1_DRAM0_RECORDING_ADDR_1 - reg_core_1_dram0_recording_addr_1 - 0 - 24 - read-only - - - - - CORE_1_DRAM0_EXCEPTION_MONITOR_5 - exception monitor status register7 - 0xEC - 0x20 - - - CORE_1_DRAM0_RECORDING_PC_1 - reg_core_1_dram0_recording_pc_1 - 0 - 32 - read-only - - - - - CORE_1_LASTPC_BEFORE_EXCEPTION - cpu status register - 0xF0 - 0x20 - - - CORE_1_LASTPC_BEFORE_EXC - cpu's lastpc before exception - 0 - 32 - read-only - - - - - CORE_1_DEBUG_MODE - cpu status register - 0xF4 - 0x20 - - - CORE_1_DEBUG_MODE - cpu debug mode status, 1 means cpu enter debug mode. - 0 - 1 - read-only - - - CORE_1_DEBUG_MODULE_ACTIVE - cpu debug_module active status - 1 - 1 - read-only - - - - - CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0 - exception monitor status register6 - 0x100 - 0x20 - - - CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 - reg_core_x_iram0_dram0_limit_cycle_0 - 0 - 20 - read-write - - - - - CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1 - exception monitor status register7 - 0x104 - 0x20 - - - CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 - reg_core_x_iram0_dram0_limit_cycle_1 - 0 - 20 - read-write - - - - - CLOCK_GATE - clock register - 0x108 - 0x20 - 0x00000001 - - - CLK_EN - Set 1 force on the clock gate - 0 - 1 - read-write - - - - - DATE - version register - 0x3FC - 0x20 - 0x02109130 - - - ASSIST_DEBUG_DATE - version register - 0 - 28 - read-write - - - - - - - AXI_DMA - AXI_DMA Peripheral - AXI_DMA - 0x5008A000 - - 0x0 - 0x2D8 - registers - - - - 3 - 0x68 - IN_INT_RAW_CH%s - Raw status interrupt of channel 0 - 0x0 - 0x20 - - - IN_DONE_CH_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. - 0 - 1 - read-write - - - IN_SUC_EOF_CH_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0. - 1 - 1 - read-write - - - IN_ERR_EOF_CH_INT_RAW - The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw interrupt is reserved. - 2 - 1 - read-write - - - IN_DSCR_ERR_CH_INT_RAW - The raw interrupt bit turns to high level when detecting inlink descriptor error including owner error and the second and third word error of inlink descriptor for Rx channel 0. - 3 - 1 - read-write - - - IN_DSCR_EMPTY_CH_INT_RAW - The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed but there is no more inlink for Rx channel 0. - 4 - 1 - read-write - - - INFIFO_L1_OVF_CH_INT_RAW - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow. - 5 - 1 - read-write - - - INFIFO_L1_UDF_CH_INT_RAW - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow. - 6 - 1 - read-write - - - INFIFO_L2_OVF_CH_INT_RAW - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow. - 7 - 1 - read-write - - - INFIFO_L2_UDF_CH_INT_RAW - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow. - 8 - 1 - read-write - - - INFIFO_L3_OVF_CH_INT_RAW - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow. - 9 - 1 - read-write - - - INFIFO_L3_UDF_CH_INT_RAW - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow. - 10 - 1 - read-write - - - - - 3 - 0x68 - IN_INT_ST_CH%s - Masked interrupt of channel 0 - 0x4 - 0x20 - - - IN_DONE_CH_INT_ST - The raw interrupt status bit for the IN_DONE_CH_INT interrupt. - 0 - 1 - read-only - - - IN_SUC_EOF_CH_INT_ST - The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. - 1 - 1 - read-only - - - IN_ERR_EOF_CH_INT_ST - The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. - 2 - 1 - read-only - - - IN_DSCR_ERR_CH_INT_ST - The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. - 3 - 1 - read-only - - - IN_DSCR_EMPTY_CH_INT_ST - The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. - 4 - 1 - read-only - - - INFIFO_OVF_CH_INT_ST - The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. - 5 - 1 - read-only - - - INFIFO_UDF_CH_INT_ST - The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. - 6 - 1 - read-only - - - INFIFO_L1_OVF_CH_INT_ST - The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. - 7 - 1 - read-only - - - INFIFO_L1_UDF_CH_INT_ST - The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. - 8 - 1 - read-only - - - INFIFO_L3_OVF_CH_INT_ST - The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt. - 9 - 1 - read-only - - - INFIFO_L3_UDF_CH_INT_ST - The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt. - 10 - 1 - read-only - - - - - 3 - 0x68 - IN_INT_ENA_CH%s - Interrupt enable bits of channel 0 - 0x8 - 0x20 - - - IN_DONE_CH_INT_ENA - The interrupt enable bit for the IN_DONE_CH_INT interrupt. - 0 - 1 - read-write - - - IN_SUC_EOF_CH_INT_ENA - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. - 1 - 1 - read-write - - - IN_ERR_EOF_CH_INT_ENA - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. - 2 - 1 - read-write - - - IN_DSCR_ERR_CH_INT_ENA - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. - 3 - 1 - read-write - - - IN_DSCR_EMPTY_CH_INT_ENA - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. - 4 - 1 - read-write - - - INFIFO_L1_OVF_CH_INT_ENA - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. - 5 - 1 - read-write - - - INFIFO_L1_UDF_CH_INT_ENA - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. - 6 - 1 - read-write - - - INFIFO_L2_OVF_CH_INT_ENA - The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. - 7 - 1 - read-write - - - INFIFO_L2_UDF_CH_INT_ENA - The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. - 8 - 1 - read-write - - - INFIFO_L3_OVF_CH_INT_ENA - The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt. - 9 - 1 - read-write - - - INFIFO_L3_UDF_CH_INT_ENA - The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt. - 10 - 1 - read-write - - - - - 3 - 0x68 - IN_INT_CLR_CH%s - Interrupt clear bits of channel 0 - 0xC - 0x20 - - - IN_DONE_CH_INT_CLR - Set this bit to clear the IN_DONE_CH_INT interrupt. - 0 - 1 - write-only - - - IN_SUC_EOF_CH_INT_CLR - Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. - 1 - 1 - write-only - - - IN_ERR_EOF_CH_INT_CLR - Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. - 2 - 1 - write-only - - - IN_DSCR_ERR_CH_INT_CLR - Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. - 3 - 1 - write-only - - - IN_DSCR_EMPTY_CH_INT_CLR - Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. - 4 - 1 - write-only - - - INFIFO_L1_OVF_CH_INT_CLR - Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. - 5 - 1 - write-only - - - INFIFO_L1_UDF_CH_INT_CLR - Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. - 6 - 1 - write-only - - - INFIFO_L2_OVF_CH_INT_CLR - Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. - 7 - 1 - write-only - - - INFIFO_L2_UDF_CH_INT_CLR - Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. - 8 - 1 - write-only - - - INFIFO_L3_OVF_CH_INT_CLR - Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt. - 9 - 1 - write-only - - - INFIFO_L3_UDF_CH_INT_CLR - Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt. - 10 - 1 - write-only - - - - - 3 - 0x68 - IN_CONF0_CH%s - Configure 0 register of Rx channel 0 - 0x10 - 0x20 - - - IN_RST_CH - This bit is used to reset AXI_DMA channel 0 Rx FSM and Rx FIFO pointer. - 0 - 1 - read-write - - - IN_LOOP_TEST_CH - reserved - 1 - 1 - read-write - - - MEM_TRANS_EN_CH - Set this bit 1 to enable automatic transmitting data from memory to memory via AXI_DMA. - 2 - 1 - read-write - - - IN_ETM_EN_CH - Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm task. - 3 - 1 - read-write - - - IN_BURST_SIZE_SEL_CH - 3'b000-3'b100:burst length 8byte~128byte - 4 - 3 - read-write - - - IN_CMD_DISABLE_CH - 1:mean disable cmd of this ch0 - 7 - 1 - read-write - - - IN_ECC_AEC_EN_CH - 1: mean access ecc or aes domain,0: mean not - 8 - 1 - read-write - - - INDSCR_BURST_EN_CH - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM. - 9 - 1 - read-write - - - - - 3 - 0x68 - IN_CONF1_CH%s - Configure 1 register of Rx channel 0 - 0x14 - 0x20 - - - IN_CHECK_OWNER_CH - Set this bit to enable checking the owner attribute of the link descriptor. - 12 - 1 - read-write - - - - - 3 - 0x68 - INFIFO_STATUS_CH%s - Receive FIFO status of Rx channel 0 - 0x18 - 0x20 - 0x00008803 - - - INFIFO_L3_FULL_CH - L3 Rx FIFO full signal for Rx channel 0. - 0 - 1 - read-only - - - INFIFO_L3_EMPTY_CH - L3 Rx FIFO empty signal for Rx channel 0. - 1 - 1 - read-only - - - INFIFO_L3_CNT_CH - The register stores the byte number of the data in L3 Rx FIFO for Rx channel 0. - 2 - 6 - read-only - - - INFIFO_L3_UDF_CH - L3 Rx FIFO under flow signal for Rx channel 0. - 8 - 1 - read-only - - - INFIFO_L3_OVF_CH - L3 Rx FIFO over flow signal for Rx channel 0. - 9 - 1 - read-only - - - INFIFO_L1_FULL_CH - L1 Rx FIFO full signal for Rx channel 0. - 10 - 1 - read-only - - - INFIFO_L1_EMPTY_CH - L1 Rx FIFO empty signal for Rx channel 0. - 11 - 1 - read-only - - - INFIFO_L1_UDF_CH - L1 Rx FIFO under flow signal for Rx channel 0. - 12 - 1 - read-only - - - INFIFO_L1_OVF_CH - L1 Rx FIFO over flow signal for Rx channel 0. - 13 - 1 - read-only - - - INFIFO_L2_FULL_CH - L2 Rx RAM full signal for Rx channel 0. - 14 - 1 - read-only - - - INFIFO_L2_EMPTY_CH - L2 Rx RAM empty signal for Rx channel 0. - 15 - 1 - read-only - - - INFIFO_L2_UDF_CH - L2 Rx FIFO under flow signal for Rx channel 0. - 16 - 1 - read-only - - - INFIFO_L2_OVF_CH - L2 Rx FIFO over flow signal for Rx channel 0. - 17 - 1 - read-only - - - IN_REMAIN_UNDER_1B_CH - reserved - 23 - 1 - read-only - - - IN_REMAIN_UNDER_2B_CH - reserved - 24 - 1 - read-only - - - IN_REMAIN_UNDER_3B_CH - reserved - 25 - 1 - read-only - - - IN_REMAIN_UNDER_4B_CH - reserved - 26 - 1 - read-only - - - IN_REMAIN_UNDER_5B_CH - reserved - 27 - 1 - read-only - - - IN_REMAIN_UNDER_6B_CH - reserved - 28 - 1 - read-only - - - IN_REMAIN_UNDER_7B_CH - reserved - 29 - 1 - read-only - - - IN_REMAIN_UNDER_8B_CH - reserved - 30 - 1 - read-only - - - IN_BUF_HUNGRY_CH - reserved - 31 - 1 - read-only - - - - - 3 - 0x68 - IN_POP_CH%s - Pop control register of Rx channel 0 - 0x1C - 0x20 - 0x00000800 - - - INFIFO_RDATA_CH - This register stores the data popping from AXI_DMA FIFO. - 0 - 12 - read-only - - - INFIFO_POP_CH - Set this bit to pop data from AXI_DMA FIFO. - 12 - 1 - write-only - - - - - 3 - 0x68 - IN_LINK1_CH%s - Link descriptor configure and control register of Rx channel 0 - 0x20 - 0x20 - 0x00000011 - - - INLINK_AUTO_RET_CH - Set this bit to return to current inlink descriptor's address when there are some errors in current receiving data. - 0 - 1 - read-write - - - INLINK_STOP_CH - Set this bit to stop dealing with the inlink descriptors. - 1 - 1 - write-only - - - INLINK_START_CH - Set this bit to start dealing with the inlink descriptors. - 2 - 1 - write-only - - - INLINK_RESTART_CH - Set this bit to mount a new inlink descriptor. - 3 - 1 - write-only - - - INLINK_PARK_CH - 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. - 4 - 1 - read-only - - - - - 3 - 0x68 - IN_LINK2_CH%s - Link descriptor configure and control register of Rx channel 0 - 0x24 - 0x20 - - - INLINK_ADDR_CH - This register stores the 20 least significant bits of the first inlink descriptor's address. - 0 - 32 - read-write - - - - - 3 - 0x68 - IN_STATE_CH%s - Receive status of Rx channel 0 - 0x28 - 0x20 - - - INLINK_DSCR_ADDR_CH - This register stores the current inlink descriptor's address. - 0 - 18 - read-only - - - IN_DSCR_STATE_CH - reserved - 18 - 2 - read-only - - - IN_STATE_CH - reserved - 20 - 3 - read-only - - - - - 3 - 0x68 - IN_SUC_EOF_DES_ADDR_CH%s - Inlink descriptor address when EOF occurs of Rx channel 0 - 0x2C - 0x20 - - - IN_SUC_EOF_DES_ADDR_CH - This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. - 0 - 32 - read-only - - - - - 3 - 0x68 - IN_ERR_EOF_DES_ADDR_CH%s - Inlink descriptor address when errors occur of Rx channel 0 - 0x30 - 0x20 - - - IN_ERR_EOF_DES_ADDR_CH - This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0. - 0 - 32 - read-only - - - - - 3 - 0x68 - IN_DSCR_CH%s - Current inlink descriptor address of Rx channel 0 - 0x34 - 0x20 - - - INLINK_DSCR_CH - The address of the current inlink descriptor x. - 0 - 32 - read-only - - - - - 3 - 0x68 - IN_DSCR_BF0_CH%s - The last inlink descriptor address of Rx channel 0 - 0x38 - 0x20 - - - INLINK_DSCR_BF0_CH - The address of the last inlink descriptor x-1. - 0 - 32 - read-only - - - - - 3 - 0x68 - IN_DSCR_BF1_CH%s - The second-to-last inlink descriptor address of Rx channel 0 - 0x3C - 0x20 - - - INLINK_DSCR_BF1_CH - The address of the second-to-last inlink descriptor x-2. - 0 - 32 - read-only - - - - - 3 - 0x68 - IN_PRI_CH%s - Priority register of Rx channel 0 - 0x40 - 0x20 - - - RX_PRI_CH - The priority of Rx channel 0. The larger of the value the higher of the priority. - 0 - 4 - read-write - - - RX_CH_ARB_WEIGH_CH - The weight of Rx channel 0 - 4 - 4 - read-write - - - RX_ARB_WEIGH_OPT_DIR_CH - 0: mean not optimazation weight function ,1: mean optimazation - 8 - 1 - read-write - - - - - 3 - 0x68 - IN_PERI_SEL_CH%s - Peripheral selection of Rx channel 0 - 0x44 - 0x20 - 0x0000003F - - - PERI_IN_SEL_CH - This register is used to select peripheral for Rx channel 0. 0:lcdcam. 1: gpspi_2. 2: gpspi_3. 3: parl_io. 4: aes. 5: sha. 6~15: Dummy - 0 - 6 - read-write - - - - - 3 - 0x68 - IN_CRC_INIT_DATA_CH%s - This register is used to config ch0 crc initial data(max 32 bit) - 0x48 - 0x20 - 0xFFFFFFFF - - - IN_CRC_INIT_DATA_CH - This register is used to config ch0 of rx crc initial value - 0 - 32 - read-write - - - - - 3 - 0x68 - RX_CRC_WIDTH_CH%s - This register is used to confiig rx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean 24<crc_width<=32 - 0x4C - 0x20 - - - RX_CRC_WIDTH_CH - reserved - 0 - 2 - read-write - - - RX_CRC_LAUTCH_FLGA_CH - reserved - 2 - 1 - read-write - - - - - 3 - 0x68 - IN_CRC_CLEAR_CH%s - This register is used to clear ch0 crc result - 0x50 - 0x20 - - - IN_CRC_CLEAR_CH - This register is used to clear ch0 of rx crc result - 0 - 1 - read-write - - - - - 3 - 0x68 - IN_CRC_FINAL_RESULT_CH%s - This register is used to store ch0 crc result - 0x54 - 0x20 - - - IN_CRC_FINAL_RESULT_CH - This register is used to store result ch0 of rx - 0 - 32 - read-only - - - - - 3 - 0x68 - RX_CRC_EN_WR_DATA_CH%s - This resister is used to config ch0 crc en for every bit - 0x58 - 0x20 - - - RX_CRC_EN_WR_DATA_CH - This register is used to enable rx ch0 crc 32bit on/off - 0 - 32 - read-write - - - - - 3 - 0x68 - RX_CRC_EN_ADDR_CH%s - This register is used to config ch0 crc en addr - 0x5C - 0x20 - - - RX_CRC_EN_ADDR_CH - reserved - 0 - 32 - read-write - - - - - 3 - 0x68 - RX_CRC_DATA_EN_WR_DATA_CH%s - This register is used to config crc data_8bit en - 0x60 - 0x20 - - - RX_CRC_DATA_EN_WR_DATA_CH - reserved - 0 - 16 - read-write - - - - - 3 - 0x68 - RX_CRC_DATA_EN_ADDR_CH%s - This register is used to config addr of crc data_8bit en - 0x64 - 0x20 - - - RX_CRC_DATA_EN_ADDR_CH - reserved - 0 - 32 - read-write - - - - - 3 - 0x68 - OUT_INT_RAW_CH%s - Raw status interrupt of channel0 - 0x138 - 0x20 - - - OUT_DONE_CH_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel0. - 0 - 1 - read-write - - - OUT_EOF_CH_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel0. - 1 - 1 - read-write - - - OUT_DSCR_ERR_CH_INT_RAW - The raw interrupt bit turns to high level when detecting outlink descriptor error including owner error and the second and third word error of outlink descriptor for Tx channel0. - 2 - 1 - read-write - - - OUT_TOTAL_EOF_CH_INT_RAW - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel0. - 3 - 1 - read-write - - - OUTFIFO_L1_OVF_CH_INT_RAW - This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is overflow. - 4 - 1 - read-write - - - OUTFIFO_L1_UDF_CH_INT_RAW - This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is underflow. - 5 - 1 - read-write - - - OUTFIFO_L2_OVF_CH_INT_RAW - This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is overflow. - 6 - 1 - read-write - - - OUTFIFO_L2_UDF_CH_INT_RAW - This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is underflow. - 7 - 1 - read-write - - - OUTFIFO_L3_OVF_CH_INT_RAW - This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is overflow. - 8 - 1 - read-write - - - OUTFIFO_L3_UDF_CH_INT_RAW - This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is underflow. - 9 - 1 - read-write - - - - - 3 - 0x68 - OUT_INT_ST_CH%s - Masked interrupt of channel0 - 0x13C - 0x20 - - - OUT_DONE_CH_INT_ST - The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. - 0 - 1 - read-only - - - OUT_EOF_CH_INT_ST - The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. - 1 - 1 - read-only - - - OUT_DSCR_ERR_CH_INT_ST - The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. - 2 - 1 - read-only - - - OUT_TOTAL_EOF_CH_INT_ST - The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. - 3 - 1 - read-only - - - OUTFIFO_OVF_CH_INT_ST - The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - 4 - 1 - read-only - - - OUTFIFO_UDF_CH_INT_ST - The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - 5 - 1 - read-only - - - OUTFIFO_L1_OVF_CH_INT_ST - The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. - 6 - 1 - read-only - - - OUTFIFO_L1_UDF_CH_INT_ST - The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. - 7 - 1 - read-only - - - OUTFIFO_L3_OVF_CH_INT_ST - The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt. - 8 - 1 - read-only - - - OUTFIFO_L3_UDF_CH_INT_ST - The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt. - 9 - 1 - read-only - - - - - 3 - 0x68 - OUT_INT_ENA_CH%s - Interrupt enable bits of channel0 - 0x140 - 0x20 - - - OUT_DONE_CH_INT_ENA - The interrupt enable bit for the OUT_DONE_CH_INT interrupt. - 0 - 1 - read-write - - - OUT_EOF_CH_INT_ENA - The interrupt enable bit for the OUT_EOF_CH_INT interrupt. - 1 - 1 - read-write - - - OUT_DSCR_ERR_CH_INT_ENA - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. - 2 - 1 - read-write - - - OUT_TOTAL_EOF_CH_INT_ENA - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. - 3 - 1 - read-write - - - OUTFIFO_L1_OVF_CH_INT_ENA - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - 4 - 1 - read-write - - - OUTFIFO_L1_UDF_CH_INT_ENA - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - 5 - 1 - read-write - - - OUTFIFO_L2_OVF_CH_INT_ENA - The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. - 6 - 1 - read-write - - - OUTFIFO_L2_UDF_CH_INT_ENA - The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. - 7 - 1 - read-write - - - OUTFIFO_L3_OVF_CH_INT_ENA - The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt. - 8 - 1 - read-write - - - OUTFIFO_L3_UDF_CH_INT_ENA - The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt. - 9 - 1 - read-write - - - - - 3 - 0x68 - OUT_INT_CLR_CH%s - Interrupt clear bits of channel0 - 0x144 - 0x20 - - - OUT_DONE_CH_INT_CLR - Set this bit to clear the OUT_DONE_CH_INT interrupt. - 0 - 1 - write-only - - - OUT_EOF_CH_INT_CLR - Set this bit to clear the OUT_EOF_CH_INT interrupt. - 1 - 1 - write-only - - - OUT_DSCR_ERR_CH_INT_CLR - Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. - 2 - 1 - write-only - - - OUT_TOTAL_EOF_CH_INT_CLR - Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. - 3 - 1 - write-only - - - OUTFIFO_L1_OVF_CH_INT_CLR - Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. - 4 - 1 - write-only - - - OUTFIFO_L1_UDF_CH_INT_CLR - Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. - 5 - 1 - write-only - - - OUTFIFO_L2_OVF_CH_INT_CLR - Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. - 6 - 1 - write-only - - - OUTFIFO_L2_UDF_CH_INT_CLR - Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. - 7 - 1 - write-only - - - OUTFIFO_L3_OVF_CH_INT_CLR - Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt. - 8 - 1 - write-only - - - OUTFIFO_L3_UDF_CH_INT_CLR - Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt. - 9 - 1 - write-only - - - - - OUT_CONF0_CH0 - Configure 0 register of Tx channel0 - 0x148 - 0x20 - 0x00000008 - - - OUT_RST_CH0 - This bit is used to reset AXI_DMA channel0 Tx FSM and Tx FIFO pointer. - 0 - 1 - read-write - - - OUT_LOOP_TEST_CH0 - reserved - 1 - 1 - read-write - - - OUT_AUTO_WRBACK_CH0 - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted. - 2 - 1 - read-write - - - OUT_EOF_MODE_CH0 - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel0 is generated when data need to transmit has been popped from FIFO in AXI_DMA - 3 - 1 - read-write - - - OUT_ETM_EN_CH0 - Set this bit to 1 to enable etm control mode, dma Tx channel0 is triggered by etm task. - 4 - 1 - read-write - - - OUT_BURST_SIZE_SEL_CH0 - 3'b000-3'b100:burst length 8byte~128byte - 5 - 3 - read-write - - - OUT_CMD_DISABLE_CH0 - 1:mean disable cmd of this ch0 - 8 - 1 - read-write - - - OUT_ECC_AEC_EN_CH0 - 1: mean access ecc or aes domain,0: mean not - 9 - 1 - read-write - - - OUTDSCR_BURST_EN_CH0 - Set this bit to 1 to enable INCR burst transfer for Tx channel0 reading link descriptor when accessing internal SRAM. - 10 - 1 - read-write - - - - - 3 - 0x68 - OUT_CONF1_CH%s - Configure 1 register of Tx channel0 - 0x14C - 0x20 - - - OUT_CHECK_OWNER_CH - Set this bit to enable checking the owner attribute of the link descriptor. - 12 - 1 - read-write - - - - - 3 - 0x68 - OUTFIFO_STATUS_CH%s - Transmit FIFO status of Tx channel0 - 0x150 - 0x20 - 0x7F808802 - - - OUTFIFO_L3_FULL_CH - L3 Tx FIFO full signal for Tx channel0. - 0 - 1 - read-only - - - OUTFIFO_L3_EMPTY_CH - L3 Tx FIFO empty signal for Tx channel0. - 1 - 1 - read-only - - - OUTFIFO_L3_CNT_CH - The register stores the byte number of the data in L3 Tx FIFO for Tx channel0. - 2 - 6 - read-only - - - OUTFIFO_L3_UDF_CH - L3 Tx FIFO under flow signal for Tx channel0. - 8 - 1 - read-only - - - OUTFIFO_L3_OVF_CH - L3 Tx FIFO over flow signal for Tx channel0. - 9 - 1 - read-only - - - OUTFIFO_L1_FULL_CH - L1 Tx FIFO full signal for Tx channel0. - 10 - 1 - read-only - - - OUTFIFO_L1_EMPTY_CH - L1 Tx FIFO empty signal for Tx channel0. - 11 - 1 - read-only - - - OUTFIFO_L1_UDF_CH - L1 Tx FIFO under flow signal for Tx channel0. - 12 - 1 - read-only - - - OUTFIFO_L1_OVF_CH - L1 Tx FIFO over flow signal for Tx channel0. - 13 - 1 - read-only - - - OUTFIFO_L2_FULL_CH - L2 Tx RAM full signal for Tx channel0. - 14 - 1 - read-only - - - OUTFIFO_L2_EMPTY_CH - L2 Tx RAM empty signal for Tx channel0. - 15 - 1 - read-only - - - OUTFIFO_L2_UDF_CH - L2 Tx FIFO under flow signal for Tx channel0. - 16 - 1 - read-only - - - OUTFIFO_L2_OVF_CH - L2 Tx FIFO over flow signal for Tx channel0. - 17 - 1 - read-only - - - OUT_REMAIN_UNDER_1B_CH - reserved - 23 - 1 - read-only - - - OUT_REMAIN_UNDER_2B_CH - reserved - 24 - 1 - read-only - - - OUT_REMAIN_UNDER_3B_CH - reserved - 25 - 1 - read-only - - - OUT_REMAIN_UNDER_4B_CH - reserved - 26 - 1 - read-only - - - OUT_REMAIN_UNDER_5B_CH - reserved - 27 - 1 - read-only - - - OUT_REMAIN_UNDER_6B_CH - reserved - 28 - 1 - read-only - - - OUT_REMAIN_UNDER_7B_CH - reserved - 29 - 1 - read-only - - - OUT_REMAIN_UNDER_8B_CH - reserved - 30 - 1 - read-only - - - - - 3 - 0x68 - OUT_PUSH_CH%s - Push control register of Tx channel0 - 0x154 - 0x20 - - - OUTFIFO_WDATA_CH - This register stores the data that need to be pushed into AXI_DMA FIFO. - 0 - 9 - read-write - - - OUTFIFO_PUSH_CH - Set this bit to push data into AXI_DMA FIFO. - 9 - 1 - write-only - - - - - 3 - 0x68 - OUT_LINK1_CH%s - Link descriptor configure and control register of Tx channel0 - 0x158 - 0x20 - 0x00000008 - - - OUTLINK_STOP_CH - Set this bit to stop dealing with the outlink descriptors. - 0 - 1 - write-only - - - OUTLINK_START_CH - Set this bit to start dealing with the outlink descriptors. - 1 - 1 - write-only - - - OUTLINK_RESTART_CH - Set this bit to restart a new outlink from the last address. - 2 - 1 - write-only - - - OUTLINK_PARK_CH - 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. - 3 - 1 - read-only - - - - - 3 - 0x68 - OUT_LINK2_CH%s - Link descriptor configure and control register of Tx channel0 - 0x15C - 0x20 - - - OUTLINK_ADDR_CH - This register stores the 32 least significant bits of the first outlink descriptor's address. - 0 - 32 - read-write - - - - - 3 - 0x68 - OUT_STATE_CH%s - Transmit status of Tx channel0 - 0x160 - 0x20 - - - OUTLINK_DSCR_ADDR_CH - This register stores the current outlink descriptor's address. - 0 - 18 - read-only - - - OUT_DSCR_STATE_CH - reserved - 18 - 2 - read-only - - - OUT_STATE_CH - reserved - 20 - 3 - read-only - - - - - 3 - 0x68 - OUT_EOF_DES_ADDR_CH%s - Outlink descriptor address when EOF occurs of Tx channel0 - 0x164 - 0x20 - - - OUT_EOF_DES_ADDR_CH - This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1. - 0 - 32 - read-only - - - - - 3 - 0x68 - OUT_EOF_BFR_DES_ADDR_CH%s - The last outlink descriptor address when EOF occurs of Tx channel0 - 0x168 - 0x20 - - - OUT_EOF_BFR_DES_ADDR_CH - This register stores the address of the outlink descriptor before the last outlink descriptor. - 0 - 32 - read-only - - - - - 3 - 0x68 - OUT_DSCR_CH%s - Current outlink descriptor address of Tx channel0 - 0x16C - 0x20 - - - OUTLINK_DSCR_CH - The address of the current outlink descriptor y. - 0 - 32 - read-only - - - - - 3 - 0x68 - OUT_DSCR_BF0_CH%s - The last outlink descriptor address of Tx channel0 - 0x170 - 0x20 - - - OUTLINK_DSCR_BF0_CH - The address of the last outlink descriptor y-1. - 0 - 32 - read-only - - - - - 3 - 0x68 - OUT_DSCR_BF1_CH%s - The second-to-last outlink descriptor address of Tx channel0 - 0x174 - 0x20 - - - OUTLINK_DSCR_BF1_CH - The address of the second-to-last outlink descriptor x-2. - 0 - 32 - read-only - - - - - 3 - 0x68 - OUT_PRI_CH%s - Priority register of Tx channel0. - 0x178 - 0x20 - - - TX_PRI_CH - The priority of Tx channel0. The larger of the value the higher of the priority. - 0 - 4 - read-write - - - TX_CH_ARB_WEIGH_CH - The weight of Tx channel0 - 4 - 4 - read-write - - - TX_ARB_WEIGH_OPT_DIR_CH - 0: mean not optimazation weight function ,1: mean optimazation - 8 - 1 - read-write - - - - - 3 - 0x68 - OUT_PERI_SEL_CH%s - Peripheral selection of Tx channel0 - 0x17C - 0x20 - 0x0000003F - - - PERI_OUT_SEL_CH - This register is used to select peripheral for Tx channel0. 0:lcdcam. 1: gpspi_2. 2: gpspi_3. 3: parl_io. 4: aes. 5: sha. 6~15: Dummy - 0 - 6 - read-write - - - - - 3 - 0x68 - OUT_CRC_INIT_DATA_CH%s - This register is used to config ch0 crc initial data(max 32 bit) - 0x180 - 0x20 - 0xFFFFFFFF - - - OUT_CRC_INIT_DATA_CH - This register is used to config ch0 of tx crc initial value - 0 - 32 - read-write - - - - - 3 - 0x68 - TX_CRC_WIDTH_CH%s - This register is used to confiig tx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean 24<crc_width<=32 - 0x184 - 0x20 - - - TX_CRC_WIDTH_CH - reserved - 0 - 2 - read-write - - - TX_CRC_LAUTCH_FLGA_CH - reserved - 2 - 1 - read-write - - - - - 3 - 0x68 - OUT_CRC_CLEAR_CH%s - This register is used to clear ch0 crc result - 0x188 - 0x20 - - - OUT_CRC_CLEAR_CH - This register is used to clear ch0 of tx crc result - 0 - 1 - read-write - - - - - 3 - 0x68 - OUT_CRC_FINAL_RESULT_CH%s - This register is used to store ch0 crc result - 0x18C - 0x20 - - - OUT_CRC_FINAL_RESULT_CH - This register is used to store result ch0 of tx - 0 - 32 - read-only - - - - - 3 - 0x68 - TX_CRC_EN_WR_DATA_CH%s - This resister is used to config ch0 crc en for every bit - 0x190 - 0x20 - - - TX_CRC_EN_WR_DATA_CH - This register is used to enable tx ch0 crc 32bit on/off - 0 - 32 - read-write - - - - - 3 - 0x68 - TX_CRC_EN_ADDR_CH%s - This register is used to config ch0 crc en addr - 0x194 - 0x20 - - - TX_CRC_EN_ADDR_CH - reserved - 0 - 32 - read-write - - - - - 3 - 0x68 - TX_CRC_DATA_EN_WR_DATA_CH%s - This register is used to config crc data_8bit en - 0x198 - 0x20 - - - TX_CRC_DATA_EN_WR_DATA_CH - reserved - 0 - 16 - read-write - - - - - 3 - 0x68 - TX_CRC_DATA_EN_ADDR_CH%s - This register is used to config addr of crc data_8bit en - 0x19C - 0x20 - - - TX_CRC_DATA_EN_ADDR_CH - reserved - 0 - 32 - read-write - - - - - OUT_CONF0_CH1 - Configure 0 register of Tx channel1 - 0x1B0 - 0x20 - 0x00000008 - - - OUT_RST_CH1 - This bit is used to reset AXI_DMA channel1 Tx FSM and Tx FIFO pointer. - 0 - 1 - read-write - - - OUT_LOOP_TEST_CH1 - reserved - 1 - 1 - read-write - - - OUT_AUTO_WRBACK_CH1 - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted. - 2 - 1 - read-write - - - OUT_EOF_MODE_CH1 - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel1 is generated when data need to transmit has been popped from FIFO in AXI_DMA - 3 - 1 - read-write - - - OUT_ETM_EN_CH1 - Set this bit to 1 to enable etm control mode, dma Tx channel1 is triggered by etm task. - 4 - 1 - read-write - - - OUT_BURST_SIZE_SEL_CH1 - 3'b000-3'b100:burst length 8byte~128byte - 5 - 3 - read-write - - - OUT_CMD_DISABLE_CH1 - 1:mean disable cmd of this ch1 - 8 - 1 - read-write - - - OUT_ECC_AEC_EN_CH1 - 1: mean access ecc or aes domain,0: mean not - 9 - 1 - read-write - - - OUTDSCR_BURST_EN_CH1 - Set this bit to 1 to enable INCR burst transfer for Tx channel1 reading link descriptor when accessing internal SRAM. - 10 - 1 - read-write - - - - - OUT_CONF0_CH2 - Configure 0 register of Tx channel2 - 0x218 - 0x20 - 0x00000008 - - - OUT_RST_CH2 - This bit is used to reset AXI_DMA channel2 Tx FSM and Tx FIFO pointer. - 0 - 1 - read-write - - - OUT_LOOP_TEST_CH2 - reserved - 1 - 1 - read-write - - - OUT_AUTO_WRBACK_CH2 - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted. - 2 - 1 - read-write - - - OUT_EOF_MODE_CH2 - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel2 is generated when data need to transmit has been popped from FIFO in AXI_DMA - 3 - 1 - read-write - - - OUT_ETM_EN_CH2 - Set this bit to 1 to enable etm control mode, dma Tx channel2 is triggered by etm task. - 4 - 1 - read-write - - - OUT_BURST_SIZE_SEL_CH2 - 3'b000-3'b100:burst length 8byte~128byte - 5 - 3 - read-write - - - OUT_CMD_DISABLE_CH2 - 1:mean disable cmd of this ch2 - 8 - 1 - read-write - - - OUT_ECC_AEC_EN_CH2 - 1: mean access ecc or aes domain,0: mean not - 9 - 1 - read-write - - - OUTDSCR_BURST_EN_CH2 - Set this bit to 1 to enable INCR burst transfer for Tx channel2 reading link descriptor when accessing internal SRAM. - 10 - 1 - read-write - - - - - ARB_TIMEOUT - This retister is used to config arbiter time slice - 0x270 - 0x20 - - - TX - This register is used to config tx arbiter time out value - 0 - 16 - read-write - - - RX - This register is used to config rx arbiter time out value - 16 - 16 - read-write - - - - - WEIGHT_EN - This register is used to config arbiter weight function to on or off - 0x274 - 0x20 - - - TX - This register is used to config tx arbiter weight function off/on - 0 - 1 - read-write - - - RX - This register is used to config rx arbiter weight function off/on - 1 - 1 - read-write - - - - - IN_MEM_CONF - Mem power configure register of Rx channel - 0x278 - 0x20 - - - IN_MEM_CLK_FORCE_EN - 1: Force to open the clock and bypass the gate-clock when accessing the RAM in AXI_DMA. 0: A gate-clock will be used when accessing the RAM in AXI_DMA. - 0 - 1 - read-write - - - IN_MEM_FORCE_PU - Force power up ram - 1 - 1 - read-write - - - IN_MEM_FORCE_PD - Force power down ram - 2 - 1 - read-write - - - OUT_MEM_CLK_FORCE_EN - 1: Force to open the clock and bypass the gate-clock when accessing the RAM in AXI_DMA. 0: A gate-clock will be used when accessing the RAM in AXI_DMA. - 3 - 1 - read-write - - - OUT_MEM_FORCE_PU - Force power up ram - 4 - 1 - read-write - - - OUT_MEM_FORCE_PD - Force power down ram - 5 - 1 - read-write - - - - - INTR_MEM_START_ADDR - The start address of accessible address space. - 0x27C - 0x20 - 0x30100000 - - - ACCESS_INTR_MEM_START_ADDR - The start address of accessible address space. - 0 - 32 - read-write - - - - - INTR_MEM_END_ADDR - The end address of accessible address space. The access address beyond this range would lead to descriptor error. - 0x280 - 0x20 - 0x8FFFFFFF - - - ACCESS_INTR_MEM_END_ADDR - The end address of accessible address space. The access address beyond this range would lead to descriptor error. - 0 - 32 - read-write - - - - - EXTR_MEM_START_ADDR - The start address of accessible address space. - 0x284 - 0x20 - 0x30100000 - - - ACCESS_EXTR_MEM_START_ADDR - The start address of accessible address space. - 0 - 32 - read-write - - - - - EXTR_MEM_END_ADDR - The end address of accessible address space. The access address beyond this range would lead to descriptor error. - 0x288 - 0x20 - 0x8FFFFFFF - - - ACCESS_EXTR_MEM_END_ADDR - The end address of accessible address space. The access address beyond this range would lead to descriptor error. - 0 - 32 - read-write - - - - - 3 - 0x4 - IN_RESET_AVAIL_CH%s - The rx channel 0 reset valid_flag register. - 0x28C - 0x20 - 0x00000001 - - - IN_RESET_AVAIL_CH - rx chan0 reset valid reg. - 0 - 1 - read-only - - - - - 3 - 0x4 - OUT_RESET_AVAIL_CH%s - The tx channel 0 reset valid_flag register. - 0x298 - 0x20 - 0x00000001 - - - OUT_RESET_AVAIL_CH - tx chan0 reset valid reg. - 0 - 1 - read-only - - - - - MISC_CONF - MISC register - 0x2A8 - 0x20 - - - AXIM_RST_WR_INTER - Set this bit then clear this bit to reset the internal axi_wr FSM. - 0 - 1 - read-write - - - AXIM_RST_RD_INTER - Set this bit then clear this bit to reset the internal axi_rd FSM. - 1 - 1 - read-write - - - ARB_PRI_DIS - Set this bit to disable priority arbitration function. - 3 - 1 - read-write - - - CLK_EN - 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers. - 4 - 1 - read-write - - - - - RDN_RESULT - reserved - 0x2AC - 0x20 - - - RDN_ENA - reserved - 0 - 1 - read-write - - - RDN_RESULT - reserved - 1 - 1 - read-only - - - - - RDN_ECO_HIGH - reserved - 0x2B0 - 0x20 - 0xFFFFFFFF - - - RDN_ECO_HIGH - The start address of accessible address space. - 0 - 32 - read-write - - - - - RDN_ECO_LOW - reserved - 0x2B4 - 0x20 - - - RDN_ECO_LOW - The start address of accessible address space. - 0 - 32 - read-write - - - - - WRESP_CNT - AXI wr responce cnt register. - 0x2B8 - 0x20 - - - WRESP_CNT - axi wr responce cnt reg. - 0 - 4 - read-only - - - - - RRESP_CNT - AXI wr responce cnt register. - 0x2BC - 0x20 - - - RRESP_CNT - axi rd responce cnt reg. - 0 - 4 - read-only - - - - - 3 - 0x4 - INFIFO_STATUS1_CH%s - Receive FIFO status of Rx channel 0 - 0x2C0 - 0x20 - - - L1INFIFO_CNT_CH - The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0. - 0 - 6 - read-only - - - L2INFIFO_CNT_CH - The register stores the byte number of the data in L2 Rx FIFO for Rx channel 0. - 6 - 4 - read-only - - - - - 3 - 0x4 - OUTFIFO_STATUS1_CH%s - Receive FIFO status of Tx channel 0 - 0x2CC - 0x20 - - - L1OUTFIFO_CNT_CH - The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0. - 0 - 6 - read-only - - - L2OUTFIFO_CNT_CH - The register stores the byte number of the data in L2 Tx FIFO for Tx channel 0. - 6 - 4 - read-only - - - - - DATE - Version control register - 0x2D8 - 0x20 - 0x02303140 - - - DATE - register version. - 0 - 32 - read-write - - - - - - - BITSCRAMBLER - BITSCRAMBLER Peripheral - BITSCRAMBLER - 0x500A3000 - - 0x0 - 0x40 - registers - - - - TX_INST_CFG0 - Control and configuration registers - 0x0 - 0x20 - - - TX_INST_IDX - write this bits to specify the one of 8 instruction - 0 - 3 - read-write - - - TX_INST_POS - write this bits to specify the bit position of 257 bit instruction which in units of 32 bits - 3 - 4 - read-write - - - - - TX_INST_CFG1 - Control and configuration registers - 0x4 - 0x20 - 0x00000004 - - - TX_INST - write this bits to update instruction which specified by BITSCRAMBLER_TX_INST_CFG0_REG, Read this bits to get instruction which specified by BITSCRAMBLER_TX_INST_CFG0_REG - 0 - 32 - read-write - - - - - RX_INST_CFG0 - Control and configuration registers - 0x8 - 0x20 - - - RX_INST_IDX - write this bits to specify the one of 8 instruction - 0 - 3 - read-write - - - RX_INST_POS - write this bits to specify the bit position of 257 bit instruction which in units of 32 bits - 3 - 4 - read-write - - - - - RX_INST_CFG1 - Control and configuration registers - 0xC - 0x20 - 0x0000000C - - - RX_INST - write this bits to update instruction which specified by BITSCRAMBLER_RX_INST_CFG0_REG, Read this bits to get instruction which specified by BITSCRAMBLER_RX_INST_CFG0_REG - 0 - 32 - read-write - - - - - TX_LUT_CFG0 - Control and configuration registers - 0x10 - 0x20 - - - TX_LUT_IDX - write this bits to specify the bytes position of LUT RAM based on reg_bitscrambler_tx_lut_mode - 0 - 11 - read-write - - - TX_LUT_MODE - write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4 bytes - 11 - 2 - read-write - - - - - TX_LUT_CFG1 - Control and configuration registers - 0x14 - 0x20 - 0x00000014 - - - TX_LUT - write this bits to update LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG, Read this bits to get LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG - 0 - 32 - read-write - - - - - RX_LUT_CFG0 - Control and configuration registers - 0x18 - 0x20 - - - RX_LUT_IDX - write this bits to specify the bytes position of LUT RAM based on reg_bitscrambler_rx_lut_mode - 0 - 11 - read-write - - - RX_LUT_MODE - write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4 bytes - 11 - 2 - read-write - - - - - RX_LUT_CFG1 - Control and configuration registers - 0x1C - 0x20 - 0x0000001C - - - RX_LUT - write this bits to update LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG, Read this bits to get LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG - 0 - 32 - read-write - - - - - TX_TAILING_BITS - Control and configuration registers - 0x20 - 0x20 - - - TX_TAILING_BITS - write this bits to specify the extra data bit length after getting EOF - 0 - 16 - read-write - - - - - RX_TAILING_BITS - Control and configuration registers - 0x24 - 0x20 - - - RX_TAILING_BITS - write this bits to specify the extra data bit length after getting EOF - 0 - 16 - read-write - - - - - TX_CTRL - Control and configuration registers - 0x28 - 0x20 - 0x00000004 - - - TX_ENA - write this bit to enable the bitscrambler tx - 0 - 1 - read-write - - - TX_PAUSE - write this bit to pause the bitscrambler tx core - 1 - 1 - read-write - - - TX_HALT - write this bit to halt the bitscrambler tx core - 2 - 1 - read-write - - - TX_EOF_MODE - write this bit to ser the bitscrambler tx core EOF signal generating mode which is combined with reg_bitscrambler_tx_tailing_bits, 0: counter by read dma fifo, 0 counter by write peripheral buffer - 3 - 1 - read-write - - - TX_COND_MODE - write this bit to specify the LOOP instruction condition mode of bitscrambler tx core, 0: use the little than operator to get the condition, 1: use not equal operator to get the condition - 4 - 1 - read-write - - - TX_FETCH_MODE - write this bit to set the bitscrambler tx core fetch instruction mode, 0: prefetch by reset, 1: fetch by instrutions - 5 - 1 - read-write - - - TX_HALT_MODE - write this bit to set the bitscrambler tx core halt mode when tx_halt is set, 0: wait write data back done, , 1: ignore write data back - 6 - 1 - read-write - - - TX_RD_DUMMY - write this bit to set the bitscrambler tx core read data mode when EOF received.0: wait read data, 1: ignore read data - 7 - 1 - read-write - - - TX_FIFO_RST - write this bit to reset the bitscrambler tx fifo - 8 - 1 - write-only - - - - - RX_CTRL - Control and configuration registers - 0x2C - 0x20 - 0x00000004 - - - RX_ENA - write this bit to enable the bitscrambler rx - 0 - 1 - read-write - - - RX_PAUSE - write this bit to pause the bitscrambler rx core - 1 - 1 - read-write - - - RX_HALT - write this bit to halt the bitscrambler rx core - 2 - 1 - read-write - - - RX_EOF_MODE - write this bit to ser the bitscrambler rx core EOF signal generating mode which is combined with reg_bitscrambler_rx_tailing_bits, 0: counter by read peripheral buffer, 0 counter by write dma fifo - 3 - 1 - read-write - - - RX_COND_MODE - write this bit to specify the LOOP instruction condition mode of bitscrambler rx core, 0: use the little than operator to get the condition, 1: use not equal operator to get the condition - 4 - 1 - read-write - - - RX_FETCH_MODE - write this bit to set the bitscrambler rx core fetch instruction mode, 0: prefetch by reset, 1: fetch by instrutions - 5 - 1 - read-write - - - RX_HALT_MODE - write this bit to set the bitscrambler rx core halt mode when rx_halt is set, 0: wait write data back done, , 1: ignore write data back - 6 - 1 - read-write - - - RX_RD_DUMMY - write this bit to set the bitscrambler rx core read data mode when EOF received.0: wait read data, 1: ignore read data - 7 - 1 - read-write - - - RX_FIFO_RST - write this bit to reset the bitscrambler rx fifo - 8 - 1 - write-only - - - - - TX_STATE - Status registers - 0x30 - 0x20 - 0x00000001 - - - TX_IN_IDLE - represents the bitscrambler tx core in halt mode - 0 - 1 - read-only - - - TX_IN_RUN - represents the bitscrambler tx core in run mode - 1 - 1 - read-only - - - TX_IN_WAIT - represents the bitscrambler tx core in wait mode to wait write back done - 2 - 1 - read-only - - - TX_IN_PAUSE - represents the bitscrambler tx core in pause mode - 3 - 1 - read-only - - - TX_FIFO_EMPTY - represents the bitscrambler tx fifo in empty state - 4 - 1 - read-only - - - TX_EOF_GET_CNT - represents the bytes numbers of bitscrambler tx core when get EOF - 16 - 14 - read-only - - - TX_EOF_OVERLOAD - represents the some EOFs will be lost for bitscrambler tx core - 30 - 1 - read-only - - - TX_EOF_TRACE_CLR - write this bit to clear reg_bitscrambler_tx_eof_overload and reg_bitscrambler_tx_eof_get_cnt registers - 31 - 1 - write-only - - - - - RX_STATE - Status registers - 0x34 - 0x20 - 0x00000001 - - - RX_IN_IDLE - represents the bitscrambler rx core in halt mode - 0 - 1 - read-only - - - RX_IN_RUN - represents the bitscrambler rx core in run mode - 1 - 1 - read-only - - - RX_IN_WAIT - represents the bitscrambler rx core in wait mode to wait write back done - 2 - 1 - read-only - - - RX_IN_PAUSE - represents the bitscrambler rx core in pause mode - 3 - 1 - read-only - - - RX_FIFO_FULL - represents the bitscrambler rx fifo in full state - 4 - 1 - read-only - - - RX_EOF_GET_CNT - represents the bytes numbers of bitscrambler rx core when get EOF - 16 - 14 - read-only - - - RX_EOF_OVERLOAD - represents the some EOFs will be lost for bitscrambler rx core - 30 - 1 - read-only - - - RX_EOF_TRACE_CLR - write this bit to clear reg_bitscrambler_rx_eof_overload and reg_bitscrambler_rx_eof_get_cnt registers - 31 - 1 - write-only - - - - - SYS - Control and configuration registers - 0xF8 - 0x20 - - - LOOP_MODE - write this bit to set the bitscrambler tx loop back to DMA rx - 0 - 1 - read-write - - - CLK_EN - Reserved - 31 - 1 - read-write - - - - - VERSION - Control and configuration registers - 0xFC - 0x20 - 0x02303240 - - - BITSCRAMBLER_VER - Reserved - 0 - 28 - read-write - - - - - - - CACHE - CACHE Peripheral - CACHE - 0x3FF10000 - - 0x0 - 0x3F0 - registers - - - CACHE - 83 - - - - L1_ICACHE_CTRL - L1 instruction Cache(L1-ICache) control register - 0x0 - 0x20 - - - L1_ICACHE_SHUT_IBUS0 - The bit is used to disable core0 ibus access L1-ICache, 0: enable, 1: disable - 0 - 1 - read-write - - - L1_ICACHE_SHUT_IBUS1 - The bit is used to disable core1 ibus access L1-ICache, 0: enable, 1: disable - 1 - 1 - read-write - - - L1_ICACHE_SHUT_IBUS2 - Reserved - 2 - 1 - read-only - - - L1_ICACHE_SHUT_IBUS3 - Reserved - 3 - 1 - read-only - - - L1_ICACHE_UNDEF_OP - Reserved - 8 - 8 - read-write - - - - - L1_DCACHE_CTRL - L1 data Cache(L1-DCache) control register - 0x4 - 0x20 - - - L1_DCACHE_SHUT_DBUS0 - The bit is used to disable core0 dbus access L1-DCache, 0: enable, 1: disable - 0 - 1 - read-write - - - L1_DCACHE_SHUT_DBUS1 - The bit is used to disable core1 dbus access L1-DCache, 0: enable, 1: disable - 1 - 1 - read-write - - - L1_DCACHE_SHUT_DBUS2 - Reserved - 2 - 1 - read-only - - - L1_DCACHE_SHUT_DBUS3 - Reserved - 3 - 1 - read-only - - - L1_DCACHE_SHUT_DMA - The bit is used to disable DMA access L1-DCache, 0: enable, 1: disable - 4 - 1 - read-write - - - L1_DCACHE_UNDEF_OP - Reserved - 8 - 8 - read-write - - - - - L1_BYPASS_CACHE_CONF - Bypass Cache configure register - 0x8 - 0x20 - - - BYPASS_L1_ICACHE0_EN - The bit is used to enable bypass L1-ICache0. 0: disable bypass, 1: enable bypass. - 0 - 1 - read-write - - - BYPASS_L1_ICACHE1_EN - The bit is used to enable bypass L1-ICache1. 0: disable bypass, 1: enable bypass. - 1 - 1 - read-write - - - BYPASS_L1_ICACHE2_EN - Reserved - 2 - 1 - read-only - - - BYPASS_L1_ICACHE3_EN - Reserved - 3 - 1 - read-only - - - BYPASS_L1_DCACHE_EN - The bit is used to enable bypass L1-DCache. 0: disable bypass, 1: enable bypass. - 4 - 1 - read-write - - - - - L1_CACHE_ATOMIC_CONF - L1 Cache atomic feature configure register - 0xC - 0x20 - 0x00000001 - - - L1_DCACHE_ATOMIC_EN - The bit is used to enable atomic feature on L1-DCache when multiple cores access L1-DCache. 1: disable, 1: enable. - 0 - 1 - read-write - - - - - L1_ICACHE_CACHESIZE_CONF - L1 instruction Cache CacheSize mode configure register - 0x10 - 0x20 - 0x00000040 - - - L1_ICACHE_CACHESIZE_256 - The field is used to configure cachesize of L1-ICache as 256 bytes. This field and all other fields within this register is onehot. - 0 - 1 - read-only - - - L1_ICACHE_CACHESIZE_512 - The field is used to configure cachesize of L1-ICache as 512 bytes. This field and all other fields within this register is onehot. - 1 - 1 - read-only - - - L1_ICACHE_CACHESIZE_1K - The field is used to configure cachesize of L1-ICache as 1k bytes. This field and all other fields within this register is onehot. - 2 - 1 - read-only - - - L1_ICACHE_CACHESIZE_2K - The field is used to configure cachesize of L1-ICache as 2k bytes. This field and all other fields within this register is onehot. - 3 - 1 - read-only - - - L1_ICACHE_CACHESIZE_4K - The field is used to configure cachesize of L1-ICache as 4k bytes. This field and all other fields within this register is onehot. - 4 - 1 - read-only - - - L1_ICACHE_CACHESIZE_8K - The field is used to configure cachesize of L1-ICache as 8k bytes. This field and all other fields within this register is onehot. - 5 - 1 - read-only - - - L1_ICACHE_CACHESIZE_16K - The field is used to configure cachesize of L1-ICache as 16k bytes. This field and all other fields within this register is onehot. - 6 - 1 - read-only - - - L1_ICACHE_CACHESIZE_32K - The field is used to configure cachesize of L1-ICache as 32k bytes. This field and all other fields within this register is onehot. - 7 - 1 - read-only - - - L1_ICACHE_CACHESIZE_64K - The field is used to configure cachesize of L1-ICache as 64k bytes. This field and all other fields within this register is onehot. - 8 - 1 - read-only - - - L1_ICACHE_CACHESIZE_128K - The field is used to configure cachesize of L1-ICache as 128k bytes. This field and all other fields within this register is onehot. - 9 - 1 - read-only - - - L1_ICACHE_CACHESIZE_256K - The field is used to configure cachesize of L1-ICache as 256k bytes. This field and all other fields within this register is onehot. - 10 - 1 - read-only - - - L1_ICACHE_CACHESIZE_512K - The field is used to configure cachesize of L1-ICache as 512k bytes. This field and all other fields within this register is onehot. - 11 - 1 - read-only - - - L1_ICACHE_CACHESIZE_1024K - The field is used to configure cachesize of L1-ICache as 1024k bytes. This field and all other fields within this register is onehot. - 12 - 1 - read-only - - - - - L1_ICACHE_BLOCKSIZE_CONF - L1 instruction Cache BlockSize mode configure register - 0x14 - 0x20 - 0x00000008 - - - L1_ICACHE_BLOCKSIZE_8 - The field is used to configureblocksize of L1-ICache as 8 bytes. This field and all other fields within this register is onehot. - 0 - 1 - read-only - - - L1_ICACHE_BLOCKSIZE_16 - The field is used to configureblocksize of L1-ICache as 16 bytes. This field and all other fields within this register is onehot. - 1 - 1 - read-only - - - L1_ICACHE_BLOCKSIZE_32 - The field is used to configureblocksize of L1-ICache as 32 bytes. This field and all other fields within this register is onehot. - 2 - 1 - read-only - - - L1_ICACHE_BLOCKSIZE_64 - The field is used to configureblocksize of L1-ICache as 64 bytes. This field and all other fields within this register is onehot. - 3 - 1 - read-only - - - L1_ICACHE_BLOCKSIZE_128 - The field is used to configureblocksize of L1-ICache as 128 bytes. This field and all other fields within this register is onehot. - 4 - 1 - read-only - - - L1_ICACHE_BLOCKSIZE_256 - The field is used to configureblocksize of L1-ICache as 256 bytes. This field and all other fields within this register is onehot. - 5 - 1 - read-only - - - - - L1_DCACHE_CACHESIZE_CONF - L1 data Cache CacheSize mode configure register - 0x18 - 0x20 - 0x00000100 - - - L1_DCACHE_CACHESIZE_256 - The field is used to configure cachesize of L1-DCache as 256 bytes. This field and all other fields within this register is onehot. - 0 - 1 - read-only - - - L1_DCACHE_CACHESIZE_512 - The field is used to configure cachesize of L1-DCache as 512 bytes. This field and all other fields within this register is onehot. - 1 - 1 - read-only - - - L1_DCACHE_CACHESIZE_1K - The field is used to configure cachesize of L1-DCache as 1k bytes. This field and all other fields within this register is onehot. - 2 - 1 - read-only - - - L1_DCACHE_CACHESIZE_2K - The field is used to configure cachesize of L1-DCache as 2k bytes. This field and all other fields within this register is onehot. - 3 - 1 - read-only - - - L1_DCACHE_CACHESIZE_4K - The field is used to configure cachesize of L1-DCache as 4k bytes. This field and all other fields within this register is onehot. - 4 - 1 - read-only - - - L1_DCACHE_CACHESIZE_8K - The field is used to configure cachesize of L1-DCache as 8k bytes. This field and all other fields within this register is onehot. - 5 - 1 - read-only - - - L1_DCACHE_CACHESIZE_16K - The field is used to configure cachesize of L1-DCache as 16k bytes. This field and all other fields within this register is onehot. - 6 - 1 - read-only - - - L1_DCACHE_CACHESIZE_32K - The field is used to configure cachesize of L1-DCache as 32k bytes. This field and all other fields within this register is onehot. - 7 - 1 - read-only - - - L1_DCACHE_CACHESIZE_64K - The field is used to configure cachesize of L1-DCache as 64k bytes. This field and all other fields within this register is onehot. - 8 - 1 - read-only - - - L1_DCACHE_CACHESIZE_128K - The field is used to configure cachesize of L1-DCache as 128k bytes. This field and all other fields within this register is onehot. - 9 - 1 - read-only - - - L1_DCACHE_CACHESIZE_256K - The field is used to configure cachesize of L1-DCache as 256k bytes. This field and all other fields within this register is onehot. - 10 - 1 - read-only - - - L1_DCACHE_CACHESIZE_512K - The field is used to configure cachesize of L1-DCache as 512k bytes. This field and all other fields within this register is onehot. - 11 - 1 - read-only - - - L1_DCACHE_CACHESIZE_1024K - The field is used to configure cachesize of L1-DCache as 1024k bytes. This field and all other fields within this register is onehot. - 12 - 1 - read-only - - - - - L1_DCACHE_BLOCKSIZE_CONF - L1 data Cache BlockSize mode configure register - 0x1C - 0x20 - 0x00000008 - - - L1_DCACHE_BLOCKSIZE_8 - The field is used to configureblocksize of L1-DCache as 8 bytes. This field and all other fields within this register is onehot. - 0 - 1 - read-only - - - L1_DCACHE_BLOCKSIZE_16 - The field is used to configureblocksize of L1-DCache as 16 bytes. This field and all other fields within this register is onehot. - 1 - 1 - read-only - - - L1_DCACHE_BLOCKSIZE_32 - The field is used to configureblocksize of L1-DCache as 32 bytes. This field and all other fields within this register is onehot. - 2 - 1 - read-only - - - L1_DCACHE_BLOCKSIZE_64 - The field is used to configureblocksize of L1-DCache as 64 bytes. This field and all other fields within this register is onehot. - 3 - 1 - read-only - - - L1_DCACHE_BLOCKSIZE_128 - The field is used to configureblocksize of L1-DCache as 128 bytes. This field and all other fields within this register is onehot. - 4 - 1 - read-only - - - L1_DCACHE_BLOCKSIZE_256 - The field is used to configureblocksize of L1-DCache as 256 bytes. This field and all other fields within this register is onehot. - 5 - 1 - read-only - - - - - L1_CACHE_WRAP_AROUND_CTRL - Cache wrap around control register - 0x20 - 0x20 - - - L1_ICACHE0_WRAP - Set this bit as 1 to enable L1-ICache0 wrap around mode. - 0 - 1 - read-write - - - L1_ICACHE1_WRAP - Set this bit as 1 to enable L1-ICache1 wrap around mode. - 1 - 1 - read-write - - - L1_ICACHE2_WRAP - Reserved - 2 - 1 - read-only - - - L1_ICACHE3_WRAP - Reserved - 3 - 1 - read-only - - - L1_DCACHE_WRAP - Set this bit as 1 to enable L1-DCache wrap around mode. - 4 - 1 - read-write - - - - - L1_CACHE_TAG_MEM_POWER_CTRL - Cache tag memory power control register - 0x24 - 0x20 - 0x00055555 - - - L1_ICACHE0_TAG_MEM_FORCE_ON - The bit is used to close clock gating of L1-ICache0 tag memory. 1: close gating, 0: open clock gating. - 0 - 1 - read-write - - - L1_ICACHE0_TAG_MEM_FORCE_PD - The bit is used to power L1-ICache0 tag memory down. 0: follow rtc_lslp, 1: power down - 1 - 1 - read-write - - - L1_ICACHE0_TAG_MEM_FORCE_PU - The bit is used to power L1-ICache0 tag memory up. 0: follow rtc_lslp, 1: power up - 2 - 1 - read-write - - - L1_ICACHE1_TAG_MEM_FORCE_ON - The bit is used to close clock gating of L1-ICache1 tag memory. 1: close gating, 0: open clock gating. - 4 - 1 - read-write - - - L1_ICACHE1_TAG_MEM_FORCE_PD - The bit is used to power L1-ICache1 tag memory down. 0: follow rtc_lslp, 1: power down - 5 - 1 - read-write - - - L1_ICACHE1_TAG_MEM_FORCE_PU - The bit is used to power L1-ICache1 tag memory up. 0: follow rtc_lslp, 1: power up - 6 - 1 - read-write - - - L1_ICACHE2_TAG_MEM_FORCE_ON - Reserved - 8 - 1 - read-only - - - L1_ICACHE2_TAG_MEM_FORCE_PD - Reserved - 9 - 1 - read-only - - - L1_ICACHE2_TAG_MEM_FORCE_PU - Reserved - 10 - 1 - read-only - - - L1_ICACHE3_TAG_MEM_FORCE_ON - Reserved - 12 - 1 - read-only - - - L1_ICACHE3_TAG_MEM_FORCE_PD - Reserved - 13 - 1 - read-only - - - L1_ICACHE3_TAG_MEM_FORCE_PU - Reserved - 14 - 1 - read-only - - - L1_DCACHE_TAG_MEM_FORCE_ON - The bit is used to close clock gating of L1-DCache tag memory. 1: close gating, 0: open clock gating. - 16 - 1 - read-write - - - L1_DCACHE_TAG_MEM_FORCE_PD - The bit is used to power L1-DCache tag memory down. 0: follow rtc_lslp, 1: power down - 17 - 1 - read-write - - - L1_DCACHE_TAG_MEM_FORCE_PU - The bit is used to power L1-DCache tag memory up. 0: follow rtc_lslp, 1: power up - 18 - 1 - read-write - - - - - L1_CACHE_DATA_MEM_POWER_CTRL - Cache data memory power control register - 0x28 - 0x20 - 0x00055555 - - - L1_ICACHE0_DATA_MEM_FORCE_ON - The bit is used to close clock gating of L1-ICache0 data memory. 1: close gating, 0: open clock gating. - 0 - 1 - read-write - - - L1_ICACHE0_DATA_MEM_FORCE_PD - The bit is used to power L1-ICache0 data memory down. 0: follow rtc_lslp, 1: power down - 1 - 1 - read-write - - - L1_ICACHE0_DATA_MEM_FORCE_PU - The bit is used to power L1-ICache0 data memory up. 0: follow rtc_lslp, 1: power up - 2 - 1 - read-write - - - L1_ICACHE1_DATA_MEM_FORCE_ON - The bit is used to close clock gating of L1-ICache1 data memory. 1: close gating, 0: open clock gating. - 4 - 1 - read-write - - - L1_ICACHE1_DATA_MEM_FORCE_PD - The bit is used to power L1-ICache1 data memory down. 0: follow rtc_lslp, 1: power down - 5 - 1 - read-write - - - L1_ICACHE1_DATA_MEM_FORCE_PU - The bit is used to power L1-ICache1 data memory up. 0: follow rtc_lslp, 1: power up - 6 - 1 - read-write - - - L1_ICACHE2_DATA_MEM_FORCE_ON - Reserved - 8 - 1 - read-only - - - L1_ICACHE2_DATA_MEM_FORCE_PD - Reserved - 9 - 1 - read-only - - - L1_ICACHE2_DATA_MEM_FORCE_PU - Reserved - 10 - 1 - read-only - - - L1_ICACHE3_DATA_MEM_FORCE_ON - Reserved - 12 - 1 - read-only - - - L1_ICACHE3_DATA_MEM_FORCE_PD - Reserved - 13 - 1 - read-only - - - L1_ICACHE3_DATA_MEM_FORCE_PU - Reserved - 14 - 1 - read-only - - - L1_DCACHE_DATA_MEM_FORCE_ON - The bit is used to close clock gating of L1-DCache data memory. 1: close gating, 0: open clock gating. - 16 - 1 - read-write - - - L1_DCACHE_DATA_MEM_FORCE_PD - The bit is used to power L1-DCache data memory down. 0: follow rtc_lslp, 1: power down - 17 - 1 - read-write - - - L1_DCACHE_DATA_MEM_FORCE_PU - The bit is used to power L1-DCache data memory up. 0: follow rtc_lslp, 1: power up - 18 - 1 - read-write - - - - - L1_CACHE_FREEZE_CTRL - Cache Freeze control register - 0x2C - 0x20 - - - L1_ICACHE0_FREEZE_EN - The bit is used to enable freeze operation on L1-ICache0. It can be cleared by software. - 0 - 1 - read-write - - - L1_ICACHE0_FREEZE_MODE - The bit is used to configure mode of freeze operation L1-ICache0. 0: a miss-access will not stuck. 1: a miss-access will stuck. - 1 - 1 - read-write - - - L1_ICACHE0_FREEZE_DONE - The bit is used to indicate whether freeze operation on L1-ICache0 is finished or not. 0: not finished. 1: finished. - 2 - 1 - read-only - - - L1_ICACHE1_FREEZE_EN - The bit is used to enable freeze operation on L1-ICache1. It can be cleared by software. - 4 - 1 - read-write - - - L1_ICACHE1_FREEZE_MODE - The bit is used to configure mode of freeze operation L1-ICache1. 0: a miss-access will not stuck. 1: a miss-access will stuck. - 5 - 1 - read-write - - - L1_ICACHE1_FREEZE_DONE - The bit is used to indicate whether freeze operation on L1-ICache1 is finished or not. 0: not finished. 1: finished. - 6 - 1 - read-only - - - L1_ICACHE2_FREEZE_EN - Reserved - 8 - 1 - read-only - - - L1_ICACHE2_FREEZE_MODE - Reserved - 9 - 1 - read-only - - - L1_ICACHE2_FREEZE_DONE - Reserved - 10 - 1 - read-only - - - L1_ICACHE3_FREEZE_EN - Reserved - 12 - 1 - read-only - - - L1_ICACHE3_FREEZE_MODE - Reserved - 13 - 1 - read-only - - - L1_ICACHE3_FREEZE_DONE - Reserved - 14 - 1 - read-only - - - L1_DCACHE_FREEZE_EN - The bit is used to enable freeze operation on L1-DCache. It can be cleared by software. - 16 - 1 - read-write - - - L1_DCACHE_FREEZE_MODE - The bit is used to configure mode of freeze operation L1-DCache. 0: a miss-access will not stuck. 1: a miss-access will stuck. - 17 - 1 - read-write - - - L1_DCACHE_FREEZE_DONE - The bit is used to indicate whether freeze operation on L1-DCache is finished or not. 0: not finished. 1: finished. - 18 - 1 - read-only - - - - - L1_CACHE_DATA_MEM_ACS_CONF - Cache data memory access configure register - 0x30 - 0x20 - 0x00033333 - - - L1_ICACHE0_DATA_MEM_RD_EN - The bit is used to enable config-bus read L1-ICache0 data memoryory. 0: disable, 1: enable. - 0 - 1 - read-write - - - L1_ICACHE0_DATA_MEM_WR_EN - The bit is used to enable config-bus write L1-ICache0 data memoryory. 0: disable, 1: enable. - 1 - 1 - read-write - - - L1_ICACHE1_DATA_MEM_RD_EN - The bit is used to enable config-bus read L1-ICache1 data memoryory. 0: disable, 1: enable. - 4 - 1 - read-write - - - L1_ICACHE1_DATA_MEM_WR_EN - The bit is used to enable config-bus write L1-ICache1 data memoryory. 0: disable, 1: enable. - 5 - 1 - read-write - - - L1_ICACHE2_DATA_MEM_RD_EN - Reserved - 8 - 1 - read-only - - - L1_ICACHE2_DATA_MEM_WR_EN - Reserved - 9 - 1 - read-only - - - L1_ICACHE3_DATA_MEM_RD_EN - Reserved - 12 - 1 - read-only - - - L1_ICACHE3_DATA_MEM_WR_EN - Reserved - 13 - 1 - read-only - - - L1_DCACHE_DATA_MEM_RD_EN - The bit is used to enable config-bus read L1-DCache data memoryory. 0: disable, 1: enable. - 16 - 1 - read-write - - - L1_DCACHE_DATA_MEM_WR_EN - The bit is used to enable config-bus write L1-DCache data memoryory. 0: disable, 1: enable. - 17 - 1 - read-write - - - - - L1_CACHE_TAG_MEM_ACS_CONF - Cache tag memory access configure register - 0x34 - 0x20 - 0x00033333 - - - L1_ICACHE0_TAG_MEM_RD_EN - The bit is used to enable config-bus read L1-ICache0 tag memoryory. 0: disable, 1: enable. - 0 - 1 - read-write - - - L1_ICACHE0_TAG_MEM_WR_EN - The bit is used to enable config-bus write L1-ICache0 tag memoryory. 0: disable, 1: enable. - 1 - 1 - read-write - - - L1_ICACHE1_TAG_MEM_RD_EN - The bit is used to enable config-bus read L1-ICache1 tag memoryory. 0: disable, 1: enable. - 4 - 1 - read-write - - - L1_ICACHE1_TAG_MEM_WR_EN - The bit is used to enable config-bus write L1-ICache1 tag memoryory. 0: disable, 1: enable. - 5 - 1 - read-write - - - L1_ICACHE2_TAG_MEM_RD_EN - Reserved - 8 - 1 - read-only - - - L1_ICACHE2_TAG_MEM_WR_EN - Reserved - 9 - 1 - read-only - - - L1_ICACHE3_TAG_MEM_RD_EN - Reserved - 12 - 1 - read-only - - - L1_ICACHE3_TAG_MEM_WR_EN - Reserved - 13 - 1 - read-only - - - L1_DCACHE_TAG_MEM_RD_EN - The bit is used to enable config-bus read L1-DCache tag memoryory. 0: disable, 1: enable. - 16 - 1 - read-write - - - L1_DCACHE_TAG_MEM_WR_EN - The bit is used to enable config-bus write L1-DCache tag memoryory. 0: disable, 1: enable. - 17 - 1 - read-write - - - - - L1_ICACHE0_PRELOCK_CONF - L1 instruction Cache 0 prelock configure register - 0x38 - 0x20 - - - L1_ICACHE0_PRELOCK_SCT0_EN - The bit is used to enable the first section of prelock function on L1-ICache0. - 0 - 1 - read-write - - - L1_ICACHE0_PRELOCK_SCT1_EN - The bit is used to enable the second section of prelock function on L1-ICache0. - 1 - 1 - read-write - - - L1_ICACHE0_PRELOCK_RGID - The bit is used to set the gid of l1 icache0 prelock. - 2 - 4 - read-write - - - - - L1_ICACHE0_PRELOCK_SCT0_ADDR - L1 instruction Cache 0 prelock section0 address configure register - 0x3C - 0x20 - - - L1_ICACHE0_PRELOCK_SCT0_ADDR - Those bits are used to configure the start virtual address of the first section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_SIZE_REG - 0 - 32 - read-write - - - - - L1_ICACHE0_PRELOCK_SCT1_ADDR - L1 instruction Cache 0 prelock section1 address configure register - 0x40 - 0x20 - - - L1_ICACHE0_PRELOCK_SCT1_ADDR - Those bits are used to configure the start virtual address of the second section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_SIZE_REG - 0 - 32 - read-write - - - - - L1_ICACHE0_PRELOCK_SCT_SIZE - L1 instruction Cache 0 prelock section size configure register - 0x44 - 0x20 - 0x3FFF3FFF - - - L1_ICACHE0_PRELOCK_SCT0_SIZE - Those bits are used to configure the size of the first section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_ADDR_REG - 0 - 14 - read-write - - - L1_ICACHE0_PRELOCK_SCT1_SIZE - Those bits are used to configure the size of the second section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_ADDR_REG - 16 - 14 - read-write - - - - - L1_ICACHE1_PRELOCK_CONF - L1 instruction Cache 1 prelock configure register - 0x48 - 0x20 - - - L1_ICACHE1_PRELOCK_SCT0_EN - The bit is used to enable the first section of prelock function on L1-ICache1. - 0 - 1 - read-write - - - L1_ICACHE1_PRELOCK_SCT1_EN - The bit is used to enable the second section of prelock function on L1-ICache1. - 1 - 1 - read-write - - - L1_ICACHE1_PRELOCK_RGID - The bit is used to set the gid of l1 icache1 prelock. - 2 - 4 - read-write - - - - - L1_ICACHE1_PRELOCK_SCT0_ADDR - L1 instruction Cache 1 prelock section0 address configure register - 0x4C - 0x20 - - - L1_ICACHE1_PRELOCK_SCT0_ADDR - Those bits are used to configure the start virtual address of the first section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_SIZE_REG - 0 - 32 - read-write - - - - - L1_ICACHE1_PRELOCK_SCT1_ADDR - L1 instruction Cache 1 prelock section1 address configure register - 0x50 - 0x20 - - - L1_ICACHE1_PRELOCK_SCT1_ADDR - Those bits are used to configure the start virtual address of the second section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_SIZE_REG - 0 - 32 - read-write - - - - - L1_ICACHE1_PRELOCK_SCT_SIZE - L1 instruction Cache 1 prelock section size configure register - 0x54 - 0x20 - 0x3FFF3FFF - - - L1_ICACHE1_PRELOCK_SCT0_SIZE - Those bits are used to configure the size of the first section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_ADDR_REG - 0 - 14 - read-write - - - L1_ICACHE1_PRELOCK_SCT1_SIZE - Those bits are used to configure the size of the second section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_ADDR_REG - 16 - 14 - read-write - - - - - L1_ICACHE2_PRELOCK_CONF - L1 instruction Cache 2 prelock configure register - 0x58 - 0x20 - - - L1_ICACHE2_PRELOCK_SCT0_EN - The bit is used to enable the first section of prelock function on L1-ICache2. - 0 - 1 - read-only - - - L1_ICACHE2_PRELOCK_SCT1_EN - The bit is used to enable the second section of prelock function on L1-ICache2. - 1 - 1 - read-only - - - L1_ICACHE2_PRELOCK_RGID - The bit is used to set the gid of l1 icache2 prelock. - 2 - 4 - read-only - - - - - L1_ICACHE2_PRELOCK_SCT0_ADDR - L1 instruction Cache 2 prelock section0 address configure register - 0x5C - 0x20 - - - L1_ICACHE2_PRELOCK_SCT0_ADDR - Those bits are used to configure the start virtual address of the first section of prelock on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT0_SIZE_REG - 0 - 32 - read-only - - - - - L1_ICACHE2_PRELOCK_SCT1_ADDR - L1 instruction Cache 2 prelock section1 address configure register - 0x60 - 0x20 - - - L1_ICACHE2_PRELOCK_SCT1_ADDR - Those bits are used to configure the start virtual address of the second section of prelock on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT1_SIZE_REG - 0 - 32 - read-only - - - - - L1_ICACHE2_PRELOCK_SCT_SIZE - L1 instruction Cache 2 prelock section size configure register - 0x64 - 0x20 - 0x3FFF3FFF - - - L1_ICACHE2_PRELOCK_SCT0_SIZE - Those bits are used to configure the size of the first section of prelock on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT0_ADDR_REG - 0 - 14 - read-only - - - L1_ICACHE2_PRELOCK_SCT1_SIZE - Those bits are used to configure the size of the second section of prelock on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT1_ADDR_REG - 16 - 14 - read-only - - - - - L1_ICACHE3_PRELOCK_CONF - L1 instruction Cache 3 prelock configure register - 0x68 - 0x20 - - - L1_ICACHE3_PRELOCK_SCT0_EN - The bit is used to enable the first section of prelock function on L1-ICache3. - 0 - 1 - read-only - - - L1_ICACHE3_PRELOCK_SCT1_EN - The bit is used to enable the second section of prelock function on L1-ICache3. - 1 - 1 - read-only - - - L1_ICACHE3_PRELOCK_RGID - The bit is used to set the gid of l1 icache3 prelock. - 2 - 4 - read-only - - - - - L1_ICACHE3_PRELOCK_SCT0_ADDR - L1 instruction Cache 3 prelock section0 address configure register - 0x6C - 0x20 - - - L1_ICACHE3_PRELOCK_SCT0_ADDR - Those bits are used to configure the start virtual address of the first section of prelock on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT0_SIZE_REG - 0 - 32 - read-only - - - - - L1_ICACHE3_PRELOCK_SCT1_ADDR - L1 instruction Cache 3 prelock section1 address configure register - 0x70 - 0x20 - - - L1_ICACHE3_PRELOCK_SCT1_ADDR - Those bits are used to configure the start virtual address of the second section of prelock on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT1_SIZE_REG - 0 - 32 - read-only - - - - - L1_ICACHE3_PRELOCK_SCT_SIZE - L1 instruction Cache 3 prelock section size configure register - 0x74 - 0x20 - 0x3FFF3FFF - - - L1_ICACHE3_PRELOCK_SCT0_SIZE - Those bits are used to configure the size of the first section of prelock on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT0_ADDR_REG - 0 - 14 - read-only - - - L1_ICACHE3_PRELOCK_SCT1_SIZE - Those bits are used to configure the size of the second section of prelock on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT1_ADDR_REG - 16 - 14 - read-only - - - - - L1_DCACHE_PRELOCK_CONF - L1 data Cache prelock configure register - 0x78 - 0x20 - - - L1_DCACHE_PRELOCK_SCT0_EN - The bit is used to enable the first section of prelock function on L1-DCache. - 0 - 1 - read-write - - - L1_DCACHE_PRELOCK_SCT1_EN - The bit is used to enable the second section of prelock function on L1-DCache. - 1 - 1 - read-write - - - L1_DCACHE_PRELOCK_RGID - The bit is used to set the gid of l1 dcache prelock. - 2 - 4 - read-write - - - - - L1_DCACHE_PRELOCK_SCT0_ADDR - L1 data Cache prelock section0 address configure register - 0x7C - 0x20 - - - L1_DCACHE_PRELOCK_SCT0_ADDR - Those bits are used to configure the start virtual address of the first section of prelock on L1-DCache, which should be used together with L1_DCACHE_PRELOCK_SCT0_SIZE_REG - 0 - 32 - read-write - - - - - L1_DCACHE_PRELOCK_SCT1_ADDR - L1 data Cache prelock section1 address configure register - 0x80 - 0x20 - - - L1_DCACHE_PRELOCK_SCT1_ADDR - Those bits are used to configure the start virtual address of the second section of prelock on L1-DCache, which should be used together with L1_DCACHE_PRELOCK_SCT1_SIZE_REG - 0 - 32 - read-write - - - - - L1_DCACHE_PRELOCK_SCT_SIZE - L1 data Cache prelock section size configure register - 0x84 - 0x20 - 0x3FFF3FFF - - - L1_DCACHE_PRELOCK_SCT0_SIZE - Those bits are used to configure the size of the first section of prelock on L1-DCache, which should be used together with L1_DCACHE_PRELOCK_SCT0_ADDR_REG - 0 - 14 - read-write - - - L1_DCACHE_PRELOCK_SCT1_SIZE - Those bits are used to configure the size of the second section of prelock on L1-DCache, which should be used together with L1_DCACHE_PRELOCK_SCT1_ADDR_REG - 16 - 14 - read-write - - - - - LOCK_CTRL - Lock-class (manual lock) operation control register - 0x88 - 0x20 - 0x00000004 - - - LOCK_ENA - The bit is used to enable lock operation. It will be cleared by hardware after lock operation done. Note that (1) this bit and unlock_ena bit are mutually exclusive, that is, those bits can not be set to 1 at the same time. (2) lock operation can be applied on LL1-ICache, L1-DCache and L2-Cache. - 0 - 1 - read-write - - - UNLOCK_ENA - The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done. Note that (1) this bit and lock_ena bit are mutually exclusive, that is, those bits can not be set to 1 at the same time. (2) unlock operation can be applied on L1-ICache, L1-DCache and L2-Cache. - 1 - 1 - read-write - - - LOCK_DONE - The bit is used to indicate whether unlock/lock operation is finished or not. 0: not finished. 1: finished. - 2 - 1 - read-only - - - LOCK_RGID - The bit is used to set the gid of cache lock/unlock. - 3 - 4 - read-write - - - - - LOCK_MAP - Lock (manual lock) map configure register - 0x8C - 0x20 - - - LOCK_MAP - Those bits are used to indicate which caches in the two-level cache structure will apply this lock/unlock operation. [0]: L1-ICache0, [1]: L1-ICache1, [2]: L1-ICache2, [3]: L1-ICache3, [4]: L1-DCache, [5]: L2-Cache. - 0 - 6 - read-write - - - - - LOCK_ADDR - Lock (manual lock) address configure register - 0x90 - 0x20 - - - LOCK_ADDR - Those bits are used to configure the start virtual address of the lock/unlock operation, which should be used together with CACHE_LOCK_SIZE_REG - 0 - 32 - read-write - - - - - LOCK_SIZE - Lock (manual lock) size configure register - 0x94 - 0x20 - - - LOCK_SIZE - Those bits are used to configure the size of the lock/unlock operation, which should be used together with CACHE_LOCK_ADDR_REG - 0 - 16 - read-write - - - - - SYNC_CTRL - Sync-class operation control register - 0x98 - 0x20 - 0x00000001 - - - INVALIDATE_ENA - The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done. Note that this bit and the other sync-bits (clean_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time. - 0 - 1 - read-write - - - CLEAN_ENA - The bit is used to enable clean operation. It will be cleared by hardware after clean operation done. Note that this bit and the other sync-bits (invalidate_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time. - 1 - 1 - read-write - - - WRITEBACK_ENA - The bit is used to enable writeback operation. It will be cleared by hardware after writeback operation done. Note that this bit and the other sync-bits (invalidate_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time. - 2 - 1 - read-write - - - WRITEBACK_INVALIDATE_ENA - The bit is used to enable writeback-invalidate operation. It will be cleared by hardware after writeback-invalidate operation done. Note that this bit and the other sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time. - 3 - 1 - read-write - - - SYNC_DONE - The bit is used to indicate whether sync operation (invalidate, clean, writeback, writeback_invalidate) is finished or not. 0: not finished. 1: finished. - 4 - 1 - read-only - - - SYNC_RGID - The bit is used to set the gid of cache sync operation (invalidate, clean, writeback, writeback_invalidate) - 5 - 4 - read-write - - - - - SYNC_MAP - Sync map configure register - 0x9C - 0x20 - 0x0000001F - - - SYNC_MAP - Those bits are used to indicate which caches in the two-level cache structure will apply the sync operation. [0]: L1-ICache0, [1]: L1-ICache1, [2]: L1-ICache2, [3]: L1-ICache3, [4]: L1-DCache, [5]: L2-Cache. - 0 - 6 - read-write - - - - - SYNC_ADDR - Sync address configure register - 0xA0 - 0x20 - - - SYNC_ADDR - Those bits are used to configure the start virtual address of the sync operation, which should be used together with CACHE_SYNC_SIZE_REG - 0 - 32 - read-write - - - - - SYNC_SIZE - Sync size configure register - 0xA4 - 0x20 - - - SYNC_SIZE - Those bits are used to configure the size of the sync operation, which should be used together with CACHE_SYNC_ADDR_REG - 0 - 28 - read-write - - - - - L1_ICACHE0_PRELOAD_CTRL - L1 instruction Cache 0 preload-operation control register - 0xA8 - 0x20 - 0x00000002 - - - L1_ICACHE0_PRELOAD_ENA - The bit is used to enable preload operation on L1-ICache0. It will be cleared by hardware automatically after preload operation is done. - 0 - 1 - read-write - - - L1_ICACHE0_PRELOAD_DONE - The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished. - 1 - 1 - read-only - - - L1_ICACHE0_PRELOAD_ORDER - The bit is used to configure the direction of preload operation. 0: ascending, 1: descending. - 2 - 1 - read-write - - - L1_ICACHE0_PRELOAD_RGID - The bit is used to set the gid of l1 icache0 preload. - 3 - 4 - read-write - - - - - L1_ICACHE0_PRELOAD_ADDR - L1 instruction Cache 0 preload address configure register - 0xAC - 0x20 - - - L1_ICACHE0_PRELOAD_ADDR - Those bits are used to configure the start virtual address of preload on L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_SIZE_REG - 0 - 32 - read-write - - - - - L1_ICACHE0_PRELOAD_SIZE - L1 instruction Cache 0 preload size configure register - 0xB0 - 0x20 - - - L1_ICACHE0_PRELOAD_SIZE - Those bits are used to configure the size of the first section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_ADDR_REG - 0 - 14 - read-write - - - - - L1_ICACHE1_PRELOAD_CTRL - L1 instruction Cache 1 preload-operation control register - 0xB4 - 0x20 - 0x00000002 - - - L1_ICACHE1_PRELOAD_ENA - The bit is used to enable preload operation on L1-ICache1. It will be cleared by hardware automatically after preload operation is done. - 0 - 1 - read-write - - - L1_ICACHE1_PRELOAD_DONE - The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished. - 1 - 1 - read-only - - - L1_ICACHE1_PRELOAD_ORDER - The bit is used to configure the direction of preload operation. 0: ascending, 1: descending. - 2 - 1 - read-write - - - L1_ICACHE1_PRELOAD_RGID - The bit is used to set the gid of l1 icache1 preload. - 3 - 4 - read-write - - - - - L1_ICACHE1_PRELOAD_ADDR - L1 instruction Cache 1 preload address configure register - 0xB8 - 0x20 - - - L1_ICACHE1_PRELOAD_ADDR - Those bits are used to configure the start virtual address of preload on L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_SIZE_REG - 0 - 32 - read-write - - - - - L1_ICACHE1_PRELOAD_SIZE - L1 instruction Cache 1 preload size configure register - 0xBC - 0x20 - - - L1_ICACHE1_PRELOAD_SIZE - Those bits are used to configure the size of the first section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_ADDR_REG - 0 - 14 - read-write - - - - - L1_ICACHE2_PRELOAD_CTRL - L1 instruction Cache 2 preload-operation control register - 0xC0 - 0x20 - 0x00000002 - - - L1_ICACHE2_PRELOAD_ENA - The bit is used to enable preload operation on L1-ICache2. It will be cleared by hardware automatically after preload operation is done. - 0 - 1 - read-only - - - L1_ICACHE2_PRELOAD_DONE - The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished. - 1 - 1 - read-only - - - L1_ICACHE2_PRELOAD_ORDER - The bit is used to configure the direction of preload operation. 0: ascending, 1: descending. - 2 - 1 - read-only - - - L1_ICACHE2_PRELOAD_RGID - The bit is used to set the gid of l1 icache2 preload. - 3 - 4 - read-only - - - - - L1_ICACHE2_PRELOAD_ADDR - L1 instruction Cache 2 preload address configure register - 0xC4 - 0x20 - - - L1_ICACHE2_PRELOAD_ADDR - Those bits are used to configure the start virtual address of preload on L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_SIZE_REG - 0 - 32 - read-only - - - - - L1_ICACHE2_PRELOAD_SIZE - L1 instruction Cache 2 preload size configure register - 0xC8 - 0x20 - - - L1_ICACHE2_PRELOAD_SIZE - Those bits are used to configure the size of the first section of prelock on L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_ADDR_REG - 0 - 14 - read-only - - - - - L1_ICACHE3_PRELOAD_CTRL - L1 instruction Cache 3 preload-operation control register - 0xCC - 0x20 - 0x00000002 - - - L1_ICACHE3_PRELOAD_ENA - The bit is used to enable preload operation on L1-ICache3. It will be cleared by hardware automatically after preload operation is done. - 0 - 1 - read-only - - - L1_ICACHE3_PRELOAD_DONE - The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished. - 1 - 1 - read-only - - - L1_ICACHE3_PRELOAD_ORDER - The bit is used to configure the direction of preload operation. 0: ascending, 1: descending. - 2 - 1 - read-only - - - L1_ICACHE3_PRELOAD_RGID - The bit is used to set the gid of l1 icache3 preload. - 3 - 4 - read-only - - - - - L1_ICACHE3_PRELOAD_ADDR - L1 instruction Cache 3 preload address configure register - 0xD0 - 0x20 - - - L1_ICACHE3_PRELOAD_ADDR - Those bits are used to configure the start virtual address of preload on L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_SIZE_REG - 0 - 32 - read-only - - - - - L1_ICACHE3_PRELOAD_SIZE - L1 instruction Cache 3 preload size configure register - 0xD4 - 0x20 - - - L1_ICACHE3_PRELOAD_SIZE - Those bits are used to configure the size of the first section of prelock on L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_ADDR_REG - 0 - 14 - read-only - - - - - L1_DCACHE_PRELOAD_CTRL - L1 data Cache preload-operation control register - 0xD8 - 0x20 - 0x00000002 - - - L1_DCACHE_PRELOAD_ENA - The bit is used to enable preload operation on L1-DCache. It will be cleared by hardware automatically after preload operation is done. - 0 - 1 - read-write - - - L1_DCACHE_PRELOAD_DONE - The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished. - 1 - 1 - read-only - - - L1_DCACHE_PRELOAD_ORDER - The bit is used to configure the direction of preload operation. 0: ascending, 1: descending. - 2 - 1 - read-write - - - L1_DCACHE_PRELOAD_RGID - The bit is used to set the gid of l1 dcache preload. - 3 - 4 - read-write - - - - - L1_DCACHE_PRELOAD_ADDR - L1 data Cache preload address configure register - 0xDC - 0x20 - - - L1_DCACHE_PRELOAD_ADDR - Those bits are used to configure the start virtual address of preload on L1-DCache, which should be used together with L1_DCACHE_PRELOAD_SIZE_REG - 0 - 32 - read-write - - - - - L1_DCACHE_PRELOAD_SIZE - L1 data Cache preload size configure register - 0xE0 - 0x20 - - - L1_DCACHE_PRELOAD_SIZE - Those bits are used to configure the size of the first section of prelock on L1-DCache, which should be used together with L1_DCACHE_PRELOAD_ADDR_REG - 0 - 14 - read-write - - - - - L1_ICACHE0_AUTOLOAD_CTRL - L1 instruction Cache 0 autoload-operation control register - 0xE4 - 0x20 - 0x00000002 - - - L1_ICACHE0_AUTOLOAD_ENA - The bit is used to enable and disable autoload operation on L1-ICache0. 1: enable, 0: disable. - 0 - 1 - read-write - - - L1_ICACHE0_AUTOLOAD_DONE - The bit is used to indicate whether autoload operation on L1-ICache0 is finished or not. 0: not finished. 1: finished. - 1 - 1 - read-only - - - L1_ICACHE0_AUTOLOAD_ORDER - The bit is used to configure the direction of autoload operation on L1-ICache0. 0: ascending. 1: descending. - 2 - 1 - read-write - - - L1_ICACHE0_AUTOLOAD_TRIGGER_MODE - The field is used to configure trigger mode of autoload operation on L1-ICache0. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. - 3 - 2 - read-write - - - L1_ICACHE0_AUTOLOAD_SCT0_ENA - The bit is used to enable the first section for autoload operation on L1-ICache0. - 8 - 1 - read-write - - - L1_ICACHE0_AUTOLOAD_SCT1_ENA - The bit is used to enable the second section for autoload operation on L1-ICache0. - 9 - 1 - read-write - - - L1_ICACHE0_AUTOLOAD_RGID - The bit is used to set the gid of l1 icache0 autoload. - 10 - 4 - read-write - - - - - L1_ICACHE0_AUTOLOAD_SCT0_ADDR - L1 instruction Cache 0 autoload section 0 address configure register - 0xE8 - 0x20 - - - L1_ICACHE0_AUTOLOAD_SCT0_ADDR - Those bits are used to configure the start virtual address of the first section for autoload operation on L1-ICache0. Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. - 0 - 32 - read-write - - - - - L1_ICACHE0_AUTOLOAD_SCT0_SIZE - L1 instruction Cache 0 autoload section 0 size configure register - 0xEC - 0x20 - - - L1_ICACHE0_AUTOLOAD_SCT0_SIZE - Those bits are used to configure the size of the first section for autoload operation on L1-ICache0. Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. - 0 - 28 - read-write - - - - - L1_ICACHE0_AUTOLOAD_SCT1_ADDR - L1 instruction Cache 0 autoload section 1 address configure register - 0xF0 - 0x20 - - - L1_ICACHE0_AUTOLOAD_SCT1_ADDR - Those bits are used to configure the start virtual address of the second section for autoload operation on L1-ICache0. Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. - 0 - 32 - read-write - - - - - L1_ICACHE0_AUTOLOAD_SCT1_SIZE - L1 instruction Cache 0 autoload section 1 size configure register - 0xF4 - 0x20 - - - L1_ICACHE0_AUTOLOAD_SCT1_SIZE - Those bits are used to configure the size of the second section for autoload operation on L1-ICache0. Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA. - 0 - 28 - read-write - - - - - L1_ICACHE1_AUTOLOAD_CTRL - L1 instruction Cache 1 autoload-operation control register - 0xF8 - 0x20 - 0x00000002 - - - L1_ICACHE1_AUTOLOAD_ENA - The bit is used to enable and disable autoload operation on L1-ICache1. 1: enable, 0: disable. - 0 - 1 - read-write - - - L1_ICACHE1_AUTOLOAD_DONE - The bit is used to indicate whether autoload operation on L1-ICache1 is finished or not. 0: not finished. 1: finished. - 1 - 1 - read-only - - - L1_ICACHE1_AUTOLOAD_ORDER - The bit is used to configure the direction of autoload operation on L1-ICache1. 0: ascending. 1: descending. - 2 - 1 - read-write - - - L1_ICACHE1_AUTOLOAD_TRIGGER_MODE - The field is used to configure trigger mode of autoload operation on L1-ICache1. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. - 3 - 2 - read-write - - - L1_ICACHE1_AUTOLOAD_SCT0_ENA - The bit is used to enable the first section for autoload operation on L1-ICache1. - 8 - 1 - read-write - - - L1_ICACHE1_AUTOLOAD_SCT1_ENA - The bit is used to enable the second section for autoload operation on L1-ICache1. - 9 - 1 - read-write - - - L1_ICACHE1_AUTOLOAD_RGID - The bit is used to set the gid of l1 icache1 autoload. - 10 - 4 - read-write - - - - - L1_ICACHE1_AUTOLOAD_SCT0_ADDR - L1 instruction Cache 1 autoload section 0 address configure register - 0xFC - 0x20 - - - L1_ICACHE1_AUTOLOAD_SCT0_ADDR - Those bits are used to configure the start virtual address of the first section for autoload operation on L1-ICache1. Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. - 0 - 32 - read-write - - - - - L1_ICACHE1_AUTOLOAD_SCT0_SIZE - L1 instruction Cache 1 autoload section 0 size configure register - 0x100 - 0x20 - - - L1_ICACHE1_AUTOLOAD_SCT0_SIZE - Those bits are used to configure the size of the first section for autoload operation on L1-ICache1. Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. - 0 - 28 - read-write - - - - - L1_ICACHE1_AUTOLOAD_SCT1_ADDR - L1 instruction Cache 1 autoload section 1 address configure register - 0x104 - 0x20 - - - L1_ICACHE1_AUTOLOAD_SCT1_ADDR - Those bits are used to configure the start virtual address of the second section for autoload operation on L1-ICache1. Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. - 0 - 32 - read-write - - - - - L1_ICACHE1_AUTOLOAD_SCT1_SIZE - L1 instruction Cache 1 autoload section 1 size configure register - 0x108 - 0x20 - - - L1_ICACHE1_AUTOLOAD_SCT1_SIZE - Those bits are used to configure the size of the second section for autoload operation on L1-ICache1. Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA. - 0 - 28 - read-write - - - - - L1_ICACHE2_AUTOLOAD_CTRL - L1 instruction Cache 2 autoload-operation control register - 0x10C - 0x20 - 0x00000002 - - - L1_ICACHE2_AUTOLOAD_ENA - The bit is used to enable and disable autoload operation on L1-ICache2. 1: enable, 0: disable. - 0 - 1 - read-only - - - L1_ICACHE2_AUTOLOAD_DONE - The bit is used to indicate whether autoload operation on L1-ICache2 is finished or not. 0: not finished. 1: finished. - 1 - 1 - read-only - - - L1_ICACHE2_AUTOLOAD_ORDER - The bit is used to configure the direction of autoload operation on L1-ICache2. 0: ascending. 1: descending. - 2 - 1 - read-only - - - L1_ICACHE2_AUTOLOAD_TRIGGER_MODE - The field is used to configure trigger mode of autoload operation on L1-ICache2. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. - 3 - 2 - read-only - - - L1_ICACHE2_AUTOLOAD_SCT0_ENA - The bit is used to enable the first section for autoload operation on L1-ICache2. - 8 - 1 - read-only - - - L1_ICACHE2_AUTOLOAD_SCT1_ENA - The bit is used to enable the second section for autoload operation on L1-ICache2. - 9 - 1 - read-only - - - L1_ICACHE2_AUTOLOAD_RGID - The bit is used to set the gid of l1 icache2 autoload. - 10 - 4 - read-only - - - - - L1_ICACHE2_AUTOLOAD_SCT0_ADDR - L1 instruction Cache 2 autoload section 0 address configure register - 0x110 - 0x20 - - - L1_ICACHE2_AUTOLOAD_SCT0_ADDR - Those bits are used to configure the start virtual address of the first section for autoload operation on L1-ICache2. Note that it should be used together with L1_ICACHE2_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. - 0 - 32 - read-only - - - - - L1_ICACHE2_AUTOLOAD_SCT0_SIZE - L1 instruction Cache 2 autoload section 0 size configure register - 0x114 - 0x20 - - - L1_ICACHE2_AUTOLOAD_SCT0_SIZE - Those bits are used to configure the size of the first section for autoload operation on L1-ICache2. Note that it should be used together with L1_ICACHE2_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. - 0 - 28 - read-only - - - - - L1_ICACHE2_AUTOLOAD_SCT1_ADDR - L1 instruction Cache 2 autoload section 1 address configure register - 0x118 - 0x20 - - - L1_ICACHE2_AUTOLOAD_SCT1_ADDR - Those bits are used to configure the start virtual address of the second section for autoload operation on L1-ICache2. Note that it should be used together with L1_ICACHE2_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. - 0 - 32 - read-only - - - - - L1_ICACHE2_AUTOLOAD_SCT1_SIZE - L1 instruction Cache 2 autoload section 1 size configure register - 0x11C - 0x20 - - - L1_ICACHE2_AUTOLOAD_SCT1_SIZE - Those bits are used to configure the size of the second section for autoload operation on L1-ICache2. Note that it should be used together with L1_ICACHE2_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA. - 0 - 28 - read-only - - - - - L1_ICACHE3_AUTOLOAD_CTRL - L1 instruction Cache 3 autoload-operation control register - 0x120 - 0x20 - 0x00000002 - - - L1_ICACHE3_AUTOLOAD_ENA - The bit is used to enable and disable autoload operation on L1-ICache3. 1: enable, 0: disable. - 0 - 1 - read-only - - - L1_ICACHE3_AUTOLOAD_DONE - The bit is used to indicate whether autoload operation on L1-ICache3 is finished or not. 0: not finished. 1: finished. - 1 - 1 - read-only - - - L1_ICACHE3_AUTOLOAD_ORDER - The bit is used to configure the direction of autoload operation on L1-ICache3. 0: ascending. 1: descending. - 2 - 1 - read-only - - - L1_ICACHE3_AUTOLOAD_TRIGGER_MODE - The field is used to configure trigger mode of autoload operation on L1-ICache3. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. - 3 - 2 - read-only - - - L1_ICACHE3_AUTOLOAD_SCT0_ENA - The bit is used to enable the first section for autoload operation on L1-ICache3. - 8 - 1 - read-only - - - L1_ICACHE3_AUTOLOAD_SCT1_ENA - The bit is used to enable the second section for autoload operation on L1-ICache3. - 9 - 1 - read-only - - - L1_ICACHE3_AUTOLOAD_RGID - The bit is used to set the gid of l1 icache3 autoload. - 10 - 4 - read-only - - - - - L1_ICACHE3_AUTOLOAD_SCT0_ADDR - L1 instruction Cache 3 autoload section 0 address configure register - 0x124 - 0x20 - - - L1_ICACHE3_AUTOLOAD_SCT0_ADDR - Those bits are used to configure the start virtual address of the first section for autoload operation on L1-ICache3. Note that it should be used together with L1_ICACHE3_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. - 0 - 32 - read-only - - - - - L1_ICACHE3_AUTOLOAD_SCT0_SIZE - L1 instruction Cache 3 autoload section 0 size configure register - 0x128 - 0x20 - - - L1_ICACHE3_AUTOLOAD_SCT0_SIZE - Those bits are used to configure the size of the first section for autoload operation on L1-ICache3. Note that it should be used together with L1_ICACHE3_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. - 0 - 28 - read-only - - - - - L1_ICACHE3_AUTOLOAD_SCT1_ADDR - L1 instruction Cache 3 autoload section 1 address configure register - 0x12C - 0x20 - - - L1_ICACHE3_AUTOLOAD_SCT1_ADDR - Those bits are used to configure the start virtual address of the second section for autoload operation on L1-ICache3. Note that it should be used together with L1_ICACHE3_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. - 0 - 32 - read-only - - - - - L1_ICACHE3_AUTOLOAD_SCT1_SIZE - L1 instruction Cache 3 autoload section 1 size configure register - 0x130 - 0x20 - - - L1_ICACHE3_AUTOLOAD_SCT1_SIZE - Reserved - 0 - 28 - read-only - - - - - L1_DCACHE_AUTOLOAD_CTRL - L1 data Cache autoload-operation control register - 0x134 - 0x20 - 0x00000002 - - - L1_DCACHE_AUTOLOAD_ENA - The bit is used to enable and disable autoload operation on L1-DCache. 1: enable, 0: disable. - 0 - 1 - read-write - - - L1_DCACHE_AUTOLOAD_DONE - The bit is used to indicate whether autoload operation on L1-DCache is finished or not. 0: not finished. 1: finished. - 1 - 1 - read-only - - - L1_DCACHE_AUTOLOAD_ORDER - The bit is used to configure the direction of autoload operation on L1-DCache. 0: ascending. 1: descending. - 2 - 1 - read-write - - - L1_DCACHE_AUTOLOAD_TRIGGER_MODE - The field is used to configure trigger mode of autoload operation on L1-DCache. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. - 3 - 2 - read-write - - - L1_DCACHE_AUTOLOAD_SCT0_ENA - The bit is used to enable the first section for autoload operation on L1-DCache. - 8 - 1 - read-write - - - L1_DCACHE_AUTOLOAD_SCT1_ENA - The bit is used to enable the second section for autoload operation on L1-DCache. - 9 - 1 - read-write - - - L1_DCACHE_AUTOLOAD_SCT2_ENA - The bit is used to enable the third section for autoload operation on L1-DCache. - 10 - 1 - read-write - - - L1_DCACHE_AUTOLOAD_SCT3_ENA - The bit is used to enable the fourth section for autoload operation on L1-DCache. - 11 - 1 - read-write - - - L1_DCACHE_AUTOLOAD_RGID - The bit is used to set the gid of l1 dcache autoload. - 12 - 4 - read-write - - - - - L1_DCACHE_AUTOLOAD_SCT0_ADDR - L1 data Cache autoload section 0 address configure register - 0x138 - 0x20 - - - L1_DCACHE_AUTOLOAD_SCT0_ADDR - Those bits are used to configure the start virtual address of the first section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT0_SIZE and L1_DCACHE_AUTOLOAD_SCT0_ENA. - 0 - 32 - read-write - - - - - L1_DCACHE_AUTOLOAD_SCT0_SIZE - L1 data Cache autoload section 0 size configure register - 0x13C - 0x20 - - - L1_DCACHE_AUTOLOAD_SCT0_SIZE - Those bits are used to configure the size of the first section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT0_ADDR and L1_DCACHE_AUTOLOAD_SCT0_ENA. - 0 - 28 - read-write - - - - - L1_DCACHE_AUTOLOAD_SCT1_ADDR - L1 data Cache autoload section 1 address configure register - 0x140 - 0x20 - - - L1_DCACHE_AUTOLOAD_SCT1_ADDR - Those bits are used to configure the start virtual address of the second section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT1_SIZE and L1_DCACHE_AUTOLOAD_SCT1_ENA. - 0 - 32 - read-write - - - - - L1_DCACHE_AUTOLOAD_SCT1_SIZE - L1 data Cache autoload section 1 size configure register - 0x144 - 0x20 - - - L1_DCACHE_AUTOLOAD_SCT1_SIZE - Those bits are used to configure the size of the second section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT1_ADDR and L1_DCACHE_AUTOLOAD_SCT1_ENA. - 0 - 28 - read-write - - - - - L1_DCACHE_AUTOLOAD_SCT2_ADDR - L1 data Cache autoload section 2 address configure register - 0x148 - 0x20 - - - L1_DCACHE_AUTOLOAD_SCT2_ADDR - Those bits are used to configure the start virtual address of the third section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT2_SIZE and L1_DCACHE_AUTOLOAD_SCT2_ENA. - 0 - 32 - read-write - - - - - L1_DCACHE_AUTOLOAD_SCT2_SIZE - L1 data Cache autoload section 2 size configure register - 0x14C - 0x20 - - - L1_DCACHE_AUTOLOAD_SCT2_SIZE - Those bits are used to configure the size of the third section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT2_ADDR and L1_DCACHE_AUTOLOAD_SCT2_ENA. - 0 - 28 - read-write - - - - - L1_DCACHE_AUTOLOAD_SCT3_ADDR - L1 data Cache autoload section 1 address configure register - 0x150 - 0x20 - - - L1_DCACHE_AUTOLOAD_SCT3_ADDR - Those bits are used to configure the start virtual address of the fourth section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT3_SIZE and L1_DCACHE_AUTOLOAD_SCT3_ENA. - 0 - 32 - read-write - - - - - L1_DCACHE_AUTOLOAD_SCT3_SIZE - L1 data Cache autoload section 1 size configure register - 0x154 - 0x20 - - - L1_DCACHE_AUTOLOAD_SCT3_SIZE - Those bits are used to configure the size of the fourth section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT3_ADDR and L1_DCACHE_AUTOLOAD_SCT3_ENA. - 0 - 28 - read-write - - - - - L1_CACHE_ACS_CNT_INT_ENA - Cache Access Counter Interrupt enable register - 0x158 - 0x20 - - - L1_IBUS0_OVF_INT_ENA - The bit is used to enable interrupt of one of counters overflow that occurs in L1-ICache0 due to bus0 accesses L1-ICache0. - 0 - 1 - read-write - - - L1_IBUS1_OVF_INT_ENA - The bit is used to enable interrupt of one of counters overflow that occurs in L1-ICache1 due to bus1 accesses L1-ICache1. - 1 - 1 - read-write - - - L1_IBUS2_OVF_INT_ENA - Reserved - 2 - 1 - read-only - - - L1_IBUS3_OVF_INT_ENA - Reserved - 3 - 1 - read-only - - - L1_DBUS0_OVF_INT_ENA - The bit is used to enable interrupt of one of counters overflow that occurs in L1-DCache due to bus0 accesses L1-DCache. - 4 - 1 - read-write - - - L1_DBUS1_OVF_INT_ENA - The bit is used to enable interrupt of one of counters overflow that occurs in L1-DCache due to bus1 accesses L1-DCache. - 5 - 1 - read-write - - - L1_DBUS2_OVF_INT_ENA - Reserved - 6 - 1 - read-only - - - L1_DBUS3_OVF_INT_ENA - Reserved - 7 - 1 - read-only - - - - - L1_CACHE_ACS_CNT_INT_CLR - Cache Access Counter Interrupt clear register - 0x15C - 0x20 - - - L1_IBUS0_OVF_INT_CLR - The bit is used to clear counters overflow interrupt and counters in L1-ICache0 due to bus0 accesses L1-ICache0. - 0 - 1 - write-only - - - L1_IBUS1_OVF_INT_CLR - The bit is used to clear counters overflow interrupt and counters in L1-ICache1 due to bus1 accesses L1-ICache1. - 1 - 1 - write-only - - - L1_IBUS2_OVF_INT_CLR - Reserved - 2 - 1 - read-only - - - L1_IBUS3_OVF_INT_CLR - Reserved - 3 - 1 - read-only - - - L1_DBUS0_OVF_INT_CLR - The bit is used to clear counters overflow interrupt and counters in L1-DCache due to bus0 accesses L1-DCache. - 4 - 1 - write-only - - - L1_DBUS1_OVF_INT_CLR - The bit is used to clear counters overflow interrupt and counters in L1-DCache due to bus1 accesses L1-DCache. - 5 - 1 - write-only - - - L1_DBUS2_OVF_INT_CLR - Reserved - 6 - 1 - read-only - - - L1_DBUS3_OVF_INT_CLR - Reserved - 7 - 1 - read-only - - - - - L1_CACHE_ACS_CNT_INT_RAW - Cache Access Counter Interrupt raw register - 0x160 - 0x20 - - - L1_IBUS0_OVF_INT_RAW - The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache0 due to bus0 accesses L1-ICache0. - 0 - 1 - read-write - - - L1_IBUS1_OVF_INT_RAW - The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache1 due to bus1 accesses L1-ICache1. - 1 - 1 - read-write - - - L1_IBUS2_OVF_INT_RAW - The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache2 due to bus2 accesses L1-ICache2. - 2 - 1 - read-write - - - L1_IBUS3_OVF_INT_RAW - The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache3 due to bus3 accesses L1-ICache3. - 3 - 1 - read-write - - - L1_DBUS0_OVF_INT_RAW - The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache due to bus0 accesses L1-DCache. - 4 - 1 - read-write - - - L1_DBUS1_OVF_INT_RAW - The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache due to bus1 accesses L1-DCache. - 5 - 1 - read-write - - - L1_DBUS2_OVF_INT_RAW - The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache due to bus2 accesses L1-DCache. - 6 - 1 - read-write - - - L1_DBUS3_OVF_INT_RAW - The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache due to bus3 accesses L1-DCache. - 7 - 1 - read-write - - - - - L1_CACHE_ACS_CNT_INT_ST - Cache Access Counter Interrupt status register - 0x164 - 0x20 - - - L1_IBUS0_OVF_INT_ST - The bit indicates the interrupt status of one of counters overflow that occurs in L1-ICache0 due to bus0 accesses L1-ICache0. - 0 - 1 - read-only - - - L1_IBUS1_OVF_INT_ST - The bit indicates the interrupt status of one of counters overflow that occurs in L1-ICache1 due to bus1 accesses L1-ICache1. - 1 - 1 - read-only - - - L1_IBUS2_OVF_INT_ST - Reserved - 2 - 1 - read-only - - - L1_IBUS3_OVF_INT_ST - Reserved - 3 - 1 - read-only - - - L1_DBUS0_OVF_INT_ST - The bit indicates the interrupt status of one of counters overflow that occurs in L1-DCache due to bus0 accesses L1-DCache. - 4 - 1 - read-only - - - L1_DBUS1_OVF_INT_ST - The bit indicates the interrupt status of one of counters overflow that occurs in L1-DCache due to bus1 accesses L1-DCache. - 5 - 1 - read-only - - - L1_DBUS2_OVF_INT_ST - Reserved - 6 - 1 - read-only - - - L1_DBUS3_OVF_INT_ST - Reserved - 7 - 1 - read-only - - - - - L1_CACHE_ACS_FAIL_CTRL - Cache Access Fail Configuration register - 0x168 - 0x20 - - - L1_ICACHE0_ACS_FAIL_CHECK_MODE - The bit is used to configure l1 icache0 access fail check mode. 0: the access fail is not propagated to the request, 1: the access fail is propagated to the request - 0 - 1 - read-write - - - L1_ICACHE1_ACS_FAIL_CHECK_MODE - The bit is used to configure l1 icache1 access fail check mode. 0: the access fail is not propagated to the request, 1: the access fail is propagated to the request - 1 - 1 - read-write - - - L1_ICACHE2_ACS_FAIL_CHECK_MODE - The bit is used to configure l1 icache2 access fail check mode. 0: the access fail is not propagated to the request, 1: the access fail is propagated to the request - 2 - 1 - read-write - - - L1_ICACHE3_ACS_FAIL_CHECK_MODE - The bit is used to configure l1 icache3 access fail check mode. 0: the access fail is not propagated to the request, 1: the access fail is propagated to the request - 3 - 1 - read-write - - - L1_DCACHE_ACS_FAIL_CHECK_MODE - The bit is used to configure l1 dcache access fail check mode. 0: the access fail is not propagated to the request, 1: the access fail is propagated to the request - 4 - 1 - read-write - - - - - L1_CACHE_ACS_FAIL_INT_ENA - Cache Access Fail Interrupt enable register - 0x16C - 0x20 - - - L1_ICACHE0_FAIL_INT_ENA - The bit is used to enable interrupt of access fail that occurs in L1-ICache0 due to cpu accesses L1-ICache0. - 0 - 1 - read-write - - - L1_ICACHE1_FAIL_INT_ENA - The bit is used to enable interrupt of access fail that occurs in L1-ICache1 due to cpu accesses L1-ICache1. - 1 - 1 - read-write - - - L1_ICACHE2_FAIL_INT_ENA - Reserved - 2 - 1 - read-only - - - L1_ICACHE3_FAIL_INT_ENA - Reserved - 3 - 1 - read-only - - - L1_DCACHE_FAIL_INT_ENA - The bit is used to enable interrupt of access fail that occurs in L1-DCache due to cpu accesses L1-DCache. - 4 - 1 - read-write - - - - - L1_CACHE_ACS_FAIL_INT_CLR - L1-Cache Access Fail Interrupt clear register - 0x170 - 0x20 - - - L1_ICACHE0_FAIL_INT_CLR - The bit is used to clear interrupt of access fail that occurs in L1-ICache0 due to cpu accesses L1-ICache0. - 0 - 1 - write-only - - - L1_ICACHE1_FAIL_INT_CLR - The bit is used to clear interrupt of access fail that occurs in L1-ICache1 due to cpu accesses L1-ICache1. - 1 - 1 - write-only - - - L1_ICACHE2_FAIL_INT_CLR - Reserved - 2 - 1 - read-only - - - L1_ICACHE3_FAIL_INT_CLR - Reserved - 3 - 1 - read-only - - - L1_DCACHE_FAIL_INT_CLR - The bit is used to clear interrupt of access fail that occurs in L1-DCache due to cpu accesses L1-DCache. - 4 - 1 - write-only - - - - - L1_CACHE_ACS_FAIL_INT_RAW - Cache Access Fail Interrupt raw register - 0x174 - 0x20 - - - L1_ICACHE0_FAIL_INT_RAW - The raw bit of the interrupt of access fail that occurs in L1-ICache0. - 0 - 1 - read-write - - - L1_ICACHE1_FAIL_INT_RAW - The raw bit of the interrupt of access fail that occurs in L1-ICache1. - 1 - 1 - read-write - - - L1_ICACHE2_FAIL_INT_RAW - The raw bit of the interrupt of access fail that occurs in L1-ICache2. - 2 - 1 - read-write - - - L1_ICACHE3_FAIL_INT_RAW - The raw bit of the interrupt of access fail that occurs in L1-ICache3. - 3 - 1 - read-write - - - L1_DCACHE_FAIL_INT_RAW - The raw bit of the interrupt of access fail that occurs in L1-DCache. - 4 - 1 - read-write - - - - - L1_CACHE_ACS_FAIL_INT_ST - Cache Access Fail Interrupt status register - 0x178 - 0x20 - - - L1_ICACHE0_FAIL_INT_ST - The bit indicates the interrupt status of access fail that occurs in L1-ICache0 due to cpu accesses L1-ICache. - 0 - 1 - read-only - - - L1_ICACHE1_FAIL_INT_ST - The bit indicates the interrupt status of access fail that occurs in L1-ICache1 due to cpu accesses L1-ICache. - 1 - 1 - read-only - - - L1_ICACHE2_FAIL_INT_ST - Reserved - 2 - 1 - read-only - - - L1_ICACHE3_FAIL_INT_ST - Reserved - 3 - 1 - read-only - - - L1_DCACHE_FAIL_INT_ST - The bit indicates the interrupt status of access fail that occurs in L1-DCache due to cpu accesses L1-DCache. - 4 - 1 - read-only - - - - - L1_CACHE_ACS_CNT_CTRL - Cache Access Counter enable and clear register - 0x17C - 0x20 - - - L1_IBUS0_CNT_ENA - The bit is used to enable ibus0 counter in L1-ICache0. - 0 - 1 - read-write - - - L1_IBUS1_CNT_ENA - The bit is used to enable ibus1 counter in L1-ICache1. - 1 - 1 - read-write - - - L1_IBUS2_CNT_ENA - Reserved - 2 - 1 - read-only - - - L1_IBUS3_CNT_ENA - Reserved - 3 - 1 - read-only - - - L1_DBUS0_CNT_ENA - The bit is used to enable dbus0 counter in L1-DCache. - 4 - 1 - read-write - - - L1_DBUS1_CNT_ENA - The bit is used to enable dbus1 counter in L1-DCache. - 5 - 1 - read-write - - - L1_DBUS2_CNT_ENA - Reserved - 6 - 1 - read-only - - - L1_DBUS3_CNT_ENA - Reserved - 7 - 1 - read-only - - - L1_IBUS0_CNT_CLR - The bit is used to clear ibus0 counter in L1-ICache0. - 16 - 1 - write-only - - - L1_IBUS1_CNT_CLR - The bit is used to clear ibus1 counter in L1-ICache1. - 17 - 1 - write-only - - - L1_IBUS2_CNT_CLR - Reserved - 18 - 1 - read-only - - - L1_IBUS3_CNT_CLR - Reserved - 19 - 1 - read-only - - - L1_DBUS0_CNT_CLR - The bit is used to clear dbus0 counter in L1-DCache. - 20 - 1 - write-only - - - L1_DBUS1_CNT_CLR - The bit is used to clear dbus1 counter in L1-DCache. - 21 - 1 - write-only - - - L1_DBUS2_CNT_CLR - Reserved - 22 - 1 - read-only - - - L1_DBUS3_CNT_CLR - Reserved - 23 - 1 - read-only - - - - - L1_IBUS0_ACS_HIT_CNT - L1-ICache bus0 Hit-Access Counter register - 0x180 - 0x20 - - - L1_IBUS0_HIT_CNT - The register records the number of hits when bus0 accesses L1-ICache0. - 0 - 32 - read-only - - - - - L1_IBUS0_ACS_MISS_CNT - L1-ICache bus0 Miss-Access Counter register - 0x184 - 0x20 - - - L1_IBUS0_MISS_CNT - The register records the number of missing when bus0 accesses L1-ICache0. - 0 - 32 - read-only - - - - - L1_IBUS0_ACS_CONFLICT_CNT - L1-ICache bus0 Conflict-Access Counter register - 0x188 - 0x20 - - - L1_IBUS0_CONFLICT_CNT - The register records the number of access-conflicts when bus0 accesses L1-ICache0. - 0 - 32 - read-only - - - - - L1_IBUS0_ACS_NXTLVL_RD_CNT - L1-ICache bus0 Next-Level-Access Counter register - 0x18C - 0x20 - - - L1_IBUS0_NXTLVL_RD_CNT - The register records the number of times that L1-ICache accesses L2-Cache due to bus0 accessing L1-ICache0. - 0 - 32 - read-only - - - - - L1_IBUS1_ACS_HIT_CNT - L1-ICache bus1 Hit-Access Counter register - 0x190 - 0x20 - - - L1_IBUS1_HIT_CNT - The register records the number of hits when bus1 accesses L1-ICache1. - 0 - 32 - read-only - - - - - L1_IBUS1_ACS_MISS_CNT - L1-ICache bus1 Miss-Access Counter register - 0x194 - 0x20 - - - L1_IBUS1_MISS_CNT - The register records the number of missing when bus1 accesses L1-ICache1. - 0 - 32 - read-only - - - - - L1_IBUS1_ACS_CONFLICT_CNT - L1-ICache bus1 Conflict-Access Counter register - 0x198 - 0x20 - - - L1_IBUS1_CONFLICT_CNT - The register records the number of access-conflicts when bus1 accesses L1-ICache1. - 0 - 32 - read-only - - - - - L1_IBUS1_ACS_NXTLVL_RD_CNT - L1-ICache bus1 Next-Level-Access Counter register - 0x19C - 0x20 - - - L1_IBUS1_NXTLVL_RD_CNT - The register records the number of times that L1-ICache accesses L2-Cache due to bus1 accessing L1-ICache1. - 0 - 32 - read-only - - - - - L1_IBUS2_ACS_HIT_CNT - L1-ICache bus2 Hit-Access Counter register - 0x1A0 - 0x20 - - - L1_IBUS2_HIT_CNT - The register records the number of hits when bus2 accesses L1-ICache2. - 0 - 32 - read-only - - - - - L1_IBUS2_ACS_MISS_CNT - L1-ICache bus2 Miss-Access Counter register - 0x1A4 - 0x20 - - - L1_IBUS2_MISS_CNT - The register records the number of missing when bus2 accesses L1-ICache2. - 0 - 32 - read-only - - - - - L1_IBUS2_ACS_CONFLICT_CNT - L1-ICache bus2 Conflict-Access Counter register - 0x1A8 - 0x20 - - - L1_IBUS2_CONFLICT_CNT - The register records the number of access-conflicts when bus2 accesses L1-ICache2. - 0 - 32 - read-only - - - - - L1_IBUS2_ACS_NXTLVL_RD_CNT - L1-ICache bus2 Next-Level-Access Counter register - 0x1AC - 0x20 - - - L1_IBUS2_NXTLVL_RD_CNT - The register records the number of times that L1-ICache accesses L2-Cache due to bus2 accessing L1-ICache2. - 0 - 32 - read-only - - - - - L1_IBUS3_ACS_HIT_CNT - L1-ICache bus3 Hit-Access Counter register - 0x1B0 - 0x20 - - - L1_IBUS3_HIT_CNT - The register records the number of hits when bus3 accesses L1-ICache3. - 0 - 32 - read-only - - - - - L1_IBUS3_ACS_MISS_CNT - L1-ICache bus3 Miss-Access Counter register - 0x1B4 - 0x20 - - - L1_IBUS3_MISS_CNT - The register records the number of missing when bus3 accesses L1-ICache3. - 0 - 32 - read-only - - - - - L1_IBUS3_ACS_CONFLICT_CNT - L1-ICache bus3 Conflict-Access Counter register - 0x1B8 - 0x20 - - - L1_IBUS3_CONFLICT_CNT - The register records the number of access-conflicts when bus3 accesses L1-ICache3. - 0 - 32 - read-only - - - - - L1_IBUS3_ACS_NXTLVL_RD_CNT - L1-ICache bus3 Next-Level-Access Counter register - 0x1BC - 0x20 - - - L1_IBUS3_NXTLVL_RD_CNT - The register records the number of times that L1-ICache accesses L2-Cache due to bus3 accessing L1-ICache3. - 0 - 32 - read-only - - - - - L1_DBUS0_ACS_HIT_CNT - L1-DCache bus0 Hit-Access Counter register - 0x1C0 - 0x20 - - - L1_DBUS0_HIT_CNT - The register records the number of hits when bus0 accesses L1-DCache. - 0 - 32 - read-only - - - - - L1_DBUS0_ACS_MISS_CNT - L1-DCache bus0 Miss-Access Counter register - 0x1C4 - 0x20 - - - L1_DBUS0_MISS_CNT - The register records the number of missing when bus0 accesses L1-DCache. - 0 - 32 - read-only - - - - - L1_DBUS0_ACS_CONFLICT_CNT - L1-DCache bus0 Conflict-Access Counter register - 0x1C8 - 0x20 - - - L1_DBUS0_CONFLICT_CNT - The register records the number of access-conflicts when bus0 accesses L1-DCache. - 0 - 32 - read-only - - - - - L1_DBUS0_ACS_NXTLVL_RD_CNT - L1-DCache bus0 Next-Level-Access Counter register - 0x1CC - 0x20 - - - L1_DBUS0_NXTLVL_RD_CNT - The register records the number of times that L1-DCache accesses L2-Cache due to bus0 accessing L1-DCache. - 0 - 32 - read-only - - - - - L1_DBUS0_ACS_NXTLVL_WR_CNT - L1-DCache bus0 WB-Access Counter register - 0x1D0 - 0x20 - - - L1_DBUS0_NXTLVL_WR_CNT - The register records the number of write back when bus0 accesses L1-DCache. - 0 - 32 - read-only - - - - - L1_DBUS1_ACS_HIT_CNT - L1-DCache bus1 Hit-Access Counter register - 0x1D4 - 0x20 - - - L1_DBUS1_HIT_CNT - The register records the number of hits when bus1 accesses L1-DCache. - 0 - 32 - read-only - - - - - L1_DBUS1_ACS_MISS_CNT - L1-DCache bus1 Miss-Access Counter register - 0x1D8 - 0x20 - - - L1_DBUS1_MISS_CNT - The register records the number of missing when bus1 accesses L1-DCache. - 0 - 32 - read-only - - - - - L1_DBUS1_ACS_CONFLICT_CNT - L1-DCache bus1 Conflict-Access Counter register - 0x1DC - 0x20 - - - L1_DBUS1_CONFLICT_CNT - The register records the number of access-conflicts when bus1 accesses L1-DCache. - 0 - 32 - read-only - - - - - L1_DBUS1_ACS_NXTLVL_RD_CNT - L1-DCache bus1 Next-Level-Access Counter register - 0x1E0 - 0x20 - - - L1_DBUS1_NXTLVL_RD_CNT - The register records the number of times that L1-DCache accesses L2-Cache due to bus1 accessing L1-DCache. - 0 - 32 - read-only - - - - - L1_DBUS1_ACS_NXTLVL_WR_CNT - L1-DCache bus1 WB-Access Counter register - 0x1E4 - 0x20 - - - L1_DBUS1_NXTLVL_WR_CNT - The register records the number of write back when bus1 accesses L1-DCache. - 0 - 32 - read-only - - - - - L1_DBUS2_ACS_HIT_CNT - L1-DCache bus2 Hit-Access Counter register - 0x1E8 - 0x20 - - - L1_DBUS2_HIT_CNT - The register records the number of hits when bus2 accesses L1-DCache. - 0 - 32 - read-only - - - - - L1_DBUS2_ACS_MISS_CNT - L1-DCache bus2 Miss-Access Counter register - 0x1EC - 0x20 - - - L1_DBUS2_MISS_CNT - The register records the number of missing when bus2 accesses L1-DCache. - 0 - 32 - read-only - - - - - L1_DBUS2_ACS_CONFLICT_CNT - L1-DCache bus2 Conflict-Access Counter register - 0x1F0 - 0x20 - - - L1_DBUS2_CONFLICT_CNT - The register records the number of access-conflicts when bus2 accesses L1-DCache. - 0 - 32 - read-only - - - - - L1_DBUS2_ACS_NXTLVL_RD_CNT - L1-DCache bus2 Next-Level-Access Counter register - 0x1F4 - 0x20 - - - L1_DBUS2_NXTLVL_RD_CNT - The register records the number of times that L1-DCache accesses L2-Cache due to bus2 accessing L1-DCache. - 0 - 32 - read-only - - - - - L1_DBUS2_ACS_NXTLVL_WR_CNT - L1-DCache bus2 WB-Access Counter register - 0x1F8 - 0x20 - - - L1_DBUS2_NXTLVL_WR_CNT - The register records the number of write back when bus2 accesses L1-DCache. - 0 - 32 - read-only - - - - - L1_DBUS3_ACS_HIT_CNT - L1-DCache bus3 Hit-Access Counter register - 0x1FC - 0x20 - - - L1_DBUS3_HIT_CNT - The register records the number of hits when bus3 accesses L1-DCache. - 0 - 32 - read-only - - - - - L1_DBUS3_ACS_MISS_CNT - L1-DCache bus3 Miss-Access Counter register - 0x200 - 0x20 - - - L1_DBUS3_MISS_CNT - The register records the number of missing when bus3 accesses L1-DCache. - 0 - 32 - read-only - - - - - L1_DBUS3_ACS_CONFLICT_CNT - L1-DCache bus3 Conflict-Access Counter register - 0x204 - 0x20 - - - L1_DBUS3_CONFLICT_CNT - The register records the number of access-conflicts when bus3 accesses L1-DCache. - 0 - 32 - read-only - - - - - L1_DBUS3_ACS_NXTLVL_RD_CNT - L1-DCache bus3 Next-Level-Access Counter register - 0x208 - 0x20 - - - L1_DBUS3_NXTLVL_RD_CNT - The register records the number of times that L1-DCache accesses L2-Cache due to bus3 accessing L1-DCache. - 0 - 32 - read-only - - - - - L1_DBUS3_ACS_NXTLVL_WR_CNT - L1-DCache bus3 WB-Access Counter register - 0x20C - 0x20 - - - L1_DBUS3_NXTLVL_WR_CNT - The register records the number of write back when bus0 accesses L1-DCache. - 0 - 32 - read-only - - - - - L1_ICACHE0_ACS_FAIL_ID_ATTR - L1-ICache0 Access Fail ID/attribution information register - 0x210 - 0x20 - - - L1_ICACHE0_FAIL_ID - The register records the ID of fail-access when cache0 accesses L1-ICache. - 0 - 16 - read-only - - - L1_ICACHE0_FAIL_ATTR - The register records the attribution of fail-access when cache0 accesses L1-ICache. - 16 - 16 - read-only - - - - - L1_ICACHE0_ACS_FAIL_ADDR - L1-ICache0 Access Fail Address information register - 0x214 - 0x20 - - - L1_ICACHE0_FAIL_ADDR - The register records the address of fail-access when cache0 accesses L1-ICache. - 0 - 32 - read-only - - - - - L1_ICACHE1_ACS_FAIL_ID_ATTR - L1-ICache0 Access Fail ID/attribution information register - 0x218 - 0x20 - - - L1_ICACHE1_FAIL_ID - The register records the ID of fail-access when cache1 accesses L1-ICache. - 0 - 16 - read-only - - - L1_ICACHE1_FAIL_ATTR - The register records the attribution of fail-access when cache1 accesses L1-ICache. - 16 - 16 - read-only - - - - - L1_ICACHE1_ACS_FAIL_ADDR - L1-ICache0 Access Fail Address information register - 0x21C - 0x20 - - - L1_ICACHE1_FAIL_ADDR - The register records the address of fail-access when cache1 accesses L1-ICache. - 0 - 32 - read-only - - - - - L1_ICACHE2_ACS_FAIL_ID_ATTR - L1-ICache0 Access Fail ID/attribution information register - 0x220 - 0x20 - - - L1_ICACHE2_FAIL_ID - The register records the ID of fail-access when cache2 accesses L1-ICache. - 0 - 16 - read-only - - - L1_ICACHE2_FAIL_ATTR - The register records the attribution of fail-access when cache2 accesses L1-ICache. - 16 - 16 - read-only - - - - - L1_ICACHE2_ACS_FAIL_ADDR - L1-ICache0 Access Fail Address information register - 0x224 - 0x20 - - - L1_ICACHE2_FAIL_ADDR - The register records the address of fail-access when cache2 accesses L1-ICache. - 0 - 32 - read-only - - - - - L1_ICACHE3_ACS_FAIL_ID_ATTR - L1-ICache0 Access Fail ID/attribution information register - 0x228 - 0x20 - - - L1_ICACHE3_FAIL_ID - The register records the ID of fail-access when cache3 accesses L1-ICache. - 0 - 16 - read-only - - - L1_ICACHE3_FAIL_ATTR - The register records the attribution of fail-access when cache3 accesses L1-ICache. - 16 - 16 - read-only - - - - - L1_ICACHE3_ACS_FAIL_ADDR - L1-ICache0 Access Fail Address information register - 0x22C - 0x20 - - - L1_ICACHE3_FAIL_ADDR - The register records the address of fail-access when cache3 accesses L1-ICache. - 0 - 32 - read-only - - - - - L1_DCACHE_ACS_FAIL_ID_ATTR - L1-DCache Access Fail ID/attribution information register - 0x230 - 0x20 - - - L1_DCACHE_FAIL_ID - The register records the ID of fail-access when cache accesses L1-DCache. - 0 - 16 - read-only - - - L1_DCACHE_FAIL_ATTR - The register records the attribution of fail-access when cache accesses L1-DCache. - 16 - 16 - read-only - - - - - L1_DCACHE_ACS_FAIL_ADDR - L1-DCache Access Fail Address information register - 0x234 - 0x20 - - - L1_DCACHE_FAIL_ADDR - The register records the address of fail-access when cache accesses L1-DCache. - 0 - 32 - read-only - - - - - SYNC_L1_CACHE_PRELOAD_INT_ENA - L1-Cache Access Fail Interrupt enable register - 0x238 - 0x20 - - - L1_ICACHE0_PLD_DONE_INT_ENA - The bit is used to enable interrupt of L1-ICache0 preload-operation. If preload operation is done, interrupt occurs. - 0 - 1 - read-write - - - L1_ICACHE1_PLD_DONE_INT_ENA - The bit is used to enable interrupt of L1-ICache1 preload-operation. If preload operation is done, interrupt occurs. - 1 - 1 - read-write - - - L1_ICACHE2_PLD_DONE_INT_ENA - Reserved - 2 - 1 - read-only - - - L1_ICACHE3_PLD_DONE_INT_ENA - Reserved - 3 - 1 - read-only - - - L1_DCACHE_PLD_DONE_INT_ENA - The bit is used to enable interrupt of L1-DCache preload-operation. If preload operation is done, interrupt occurs. - 4 - 1 - read-write - - - SYNC_DONE_INT_ENA - The bit is used to enable interrupt of Cache sync-operation done. - 6 - 1 - read-write - - - L1_ICACHE0_PLD_ERR_INT_ENA - The bit is used to enable interrupt of L1-ICache0 preload-operation error. - 7 - 1 - read-write - - - L1_ICACHE1_PLD_ERR_INT_ENA - The bit is used to enable interrupt of L1-ICache1 preload-operation error. - 8 - 1 - read-write - - - L1_ICACHE2_PLD_ERR_INT_ENA - Reserved - 9 - 1 - read-only - - - L1_ICACHE3_PLD_ERR_INT_ENA - Reserved - 10 - 1 - read-only - - - L1_DCACHE_PLD_ERR_INT_ENA - The bit is used to enable interrupt of L1-DCache preload-operation error. - 11 - 1 - read-write - - - SYNC_ERR_INT_ENA - The bit is used to enable interrupt of Cache sync-operation error. - 13 - 1 - read-write - - - - - SYNC_L1_CACHE_PRELOAD_INT_CLR - Sync Preload operation Interrupt clear register - 0x23C - 0x20 - - - L1_ICACHE0_PLD_DONE_INT_CLR - The bit is used to clear interrupt that occurs only when L1-ICache0 preload-operation is done. - 0 - 1 - write-only - - - L1_ICACHE1_PLD_DONE_INT_CLR - The bit is used to clear interrupt that occurs only when L1-ICache1 preload-operation is done. - 1 - 1 - write-only - - - L1_ICACHE2_PLD_DONE_INT_CLR - Reserved - 2 - 1 - read-only - - - L1_ICACHE3_PLD_DONE_INT_CLR - Reserved - 3 - 1 - read-only - - - L1_DCACHE_PLD_DONE_INT_CLR - The bit is used to clear interrupt that occurs only when L1-DCache preload-operation is done. - 4 - 1 - write-only - - - SYNC_DONE_INT_CLR - The bit is used to clear interrupt that occurs only when Cache sync-operation is done. - 6 - 1 - write-only - - - L1_ICACHE0_PLD_ERR_INT_CLR - The bit is used to clear interrupt of L1-ICache0 preload-operation error. - 7 - 1 - write-only - - - L1_ICACHE1_PLD_ERR_INT_CLR - The bit is used to clear interrupt of L1-ICache1 preload-operation error. - 8 - 1 - write-only - - - L1_ICACHE2_PLD_ERR_INT_CLR - Reserved - 9 - 1 - read-only - - - L1_ICACHE3_PLD_ERR_INT_CLR - Reserved - 10 - 1 - read-only - - - L1_DCACHE_PLD_ERR_INT_CLR - The bit is used to clear interrupt of L1-DCache preload-operation error. - 11 - 1 - write-only - - - SYNC_ERR_INT_CLR - The bit is used to clear interrupt of Cache sync-operation error. - 13 - 1 - write-only - - - - - SYNC_L1_CACHE_PRELOAD_INT_RAW - Sync Preload operation Interrupt raw register - 0x240 - 0x20 - - - L1_ICACHE0_PLD_DONE_INT_RAW - The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation is done. - 0 - 1 - read-write - - - L1_ICACHE1_PLD_DONE_INT_RAW - The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation is done. - 1 - 1 - read-write - - - L1_ICACHE2_PLD_DONE_INT_RAW - Reserved - 2 - 1 - read-write - - - L1_ICACHE3_PLD_DONE_INT_RAW - Reserved - 3 - 1 - read-write - - - L1_DCACHE_PLD_DONE_INT_RAW - The raw bit of the interrupt that occurs only when L1-DCache preload-operation is done. - 4 - 1 - read-write - - - SYNC_DONE_INT_RAW - The raw bit of the interrupt that occurs only when Cache sync-operation is done. - 6 - 1 - read-write - - - L1_ICACHE0_PLD_ERR_INT_RAW - The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation error occurs. - 7 - 1 - read-write - - - L1_ICACHE1_PLD_ERR_INT_RAW - The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation error occurs. - 8 - 1 - read-write - - - L1_ICACHE2_PLD_ERR_INT_RAW - Reserved - 9 - 1 - read-write - - - L1_ICACHE3_PLD_ERR_INT_RAW - Reserved - 10 - 1 - read-write - - - L1_DCACHE_PLD_ERR_INT_RAW - The raw bit of the interrupt that occurs only when L1-DCache preload-operation error occurs. - 11 - 1 - read-write - - - SYNC_ERR_INT_RAW - The raw bit of the interrupt that occurs only when Cache sync-operation error occurs. - 13 - 1 - read-write - - - - - SYNC_L1_CACHE_PRELOAD_INT_ST - L1-Cache Access Fail Interrupt status register - 0x244 - 0x20 - - - L1_ICACHE0_PLD_DONE_INT_ST - The bit indicates the status of the interrupt that occurs only when L1-ICache0 preload-operation is done. - 0 - 1 - read-only - - - L1_ICACHE1_PLD_DONE_INT_ST - The bit indicates the status of the interrupt that occurs only when L1-ICache1 preload-operation is done. - 1 - 1 - read-only - - - L1_ICACHE2_PLD_DONE_INT_ST - Reserved - 2 - 1 - read-only - - - L1_ICACHE3_PLD_DONE_INT_ST - Reserved - 3 - 1 - read-only - - - L1_DCACHE_PLD_DONE_INT_ST - The bit indicates the status of the interrupt that occurs only when L1-DCache preload-operation is done. - 4 - 1 - read-only - - - SYNC_DONE_INT_ST - The bit indicates the status of the interrupt that occurs only when Cache sync-operation is done. - 6 - 1 - read-only - - - L1_ICACHE0_PLD_ERR_INT_ST - The bit indicates the status of the interrupt of L1-ICache0 preload-operation error. - 7 - 1 - read-only - - - L1_ICACHE1_PLD_ERR_INT_ST - The bit indicates the status of the interrupt of L1-ICache1 preload-operation error. - 8 - 1 - read-only - - - L1_ICACHE2_PLD_ERR_INT_ST - Reserved - 9 - 1 - read-only - - - L1_ICACHE3_PLD_ERR_INT_ST - Reserved - 10 - 1 - read-only - - - L1_DCACHE_PLD_ERR_INT_ST - The bit indicates the status of the interrupt of L1-DCache preload-operation error. - 11 - 1 - read-only - - - SYNC_ERR_INT_ST - The bit indicates the status of the interrupt of Cache sync-operation error. - 13 - 1 - read-only - - - - - SYNC_L1_CACHE_PRELOAD_EXCEPTION - Cache Sync/Preload Operation exception register - 0x248 - 0x20 - - - L1_ICACHE0_PLD_ERR_CODE - The value 2 is Only available which means preload size is error in L1-ICache0. - 0 - 2 - read-only - - - L1_ICACHE1_PLD_ERR_CODE - The value 2 is Only available which means preload size is error in L1-ICache1. - 2 - 2 - read-only - - - L1_ICACHE2_PLD_ERR_CODE - Reserved - 4 - 2 - read-only - - - L1_ICACHE3_PLD_ERR_CODE - Reserved - 6 - 2 - read-only - - - L1_DCACHE_PLD_ERR_CODE - The value 2 is Only available which means preload size is error in L1-DCache. - 8 - 2 - read-only - - - SYNC_ERR_CODE - The values 0-2 are available which means sync map, command conflict and size are error in Cache System. - 12 - 2 - read-only - - - - - L1_CACHE_SYNC_RST_CTRL - Cache Sync Reset control register - 0x24C - 0x20 - - - L1_ICACHE0_SYNC_RST - set this bit to reset sync-logic inside L1-ICache0. Recommend that this should only be used to initialize sync-logic when some fatal error of sync-logic occurs. - 0 - 1 - read-write - - - L1_ICACHE1_SYNC_RST - set this bit to reset sync-logic inside L1-ICache1. Recommend that this should only be used to initialize sync-logic when some fatal error of sync-logic occurs. - 1 - 1 - read-write - - - L1_ICACHE2_SYNC_RST - Reserved - 2 - 1 - read-only - - - L1_ICACHE3_SYNC_RST - Reserved - 3 - 1 - read-only - - - L1_DCACHE_SYNC_RST - set this bit to reset sync-logic inside L1-DCache. Recommend that this should only be used to initialize sync-logic when some fatal error of sync-logic occurs. - 4 - 1 - read-write - - - - - L1_CACHE_PRELOAD_RST_CTRL - Cache Preload Reset control register - 0x250 - 0x20 - - - L1_ICACHE0_PLD_RST - set this bit to reset preload-logic inside L1-ICache0. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs. - 0 - 1 - read-write - - - L1_ICACHE1_PLD_RST - set this bit to reset preload-logic inside L1-ICache1. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs. - 1 - 1 - read-write - - - L1_ICACHE2_PLD_RST - Reserved - 2 - 1 - read-only - - - L1_ICACHE3_PLD_RST - Reserved - 3 - 1 - read-only - - - L1_DCACHE_PLD_RST - set this bit to reset preload-logic inside L1-DCache. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs. - 4 - 1 - read-write - - - - - L1_CACHE_AUTOLOAD_BUF_CLR_CTRL - Cache Autoload buffer clear control register - 0x254 - 0x20 - - - L1_ICACHE0_ALD_BUF_CLR - set this bit to clear autoload-buffer inside L1-ICache0. If this bit is active, autoload will not work in L1-ICache0. This bit should not be active when autoload works in L1-ICache0. - 0 - 1 - read-write - - - L1_ICACHE1_ALD_BUF_CLR - set this bit to clear autoload-buffer inside L1-ICache1. If this bit is active, autoload will not work in L1-ICache1. This bit should not be active when autoload works in L1-ICache1. - 1 - 1 - read-write - - - L1_ICACHE2_ALD_BUF_CLR - Reserved - 2 - 1 - read-only - - - L1_ICACHE3_ALD_BUF_CLR - Reserved - 3 - 1 - read-only - - - L1_DCACHE_ALD_BUF_CLR - set this bit to clear autoload-buffer inside L1-DCache. If this bit is active, autoload will not work in L1-DCache. This bit should not be active when autoload works in L1-DCache. - 4 - 1 - read-write - - - - - L1_UNALLOCATE_BUFFER_CLEAR - Unallocate request buffer clear registers - 0x258 - 0x20 - - - L1_ICACHE0_UNALLOC_CLR - The bit is used to clear the unallocate request buffer of l1 icache0 where the unallocate request is responsed but not completed. - 0 - 1 - read-write - - - L1_ICACHE1_UNALLOC_CLR - The bit is used to clear the unallocate request buffer of l1 icache1 where the unallocate request is responsed but not completed. - 1 - 1 - read-write - - - L1_ICACHE2_UNALLOC_CLR - Reserved - 2 - 1 - read-only - - - L1_ICACHE3_UNALLOC_CLR - Reserved - 3 - 1 - read-only - - - L1_DCACHE_UNALLOC_CLR - The bit is used to clear the unallocate request buffer of l1 dcache where the unallocate request is responsed but not completed. - 4 - 1 - read-write - - - - - L1_CACHE_OBJECT_CTRL - Cache Tag and Data memory Object control register - 0x25C - 0x20 - - - L1_ICACHE0_TAG_OBJECT - Set this bit to set L1-ICache0 tag memory as object. This bit should be onehot with the others fields inside this register. - 0 - 1 - read-write - - - L1_ICACHE1_TAG_OBJECT - Set this bit to set L1-ICache1 tag memory as object. This bit should be onehot with the others fields inside this register. - 1 - 1 - read-write - - - L1_ICACHE2_TAG_OBJECT - Reserved - 2 - 1 - read-only - - - L1_ICACHE3_TAG_OBJECT - Reserved - 3 - 1 - read-only - - - L1_DCACHE_TAG_OBJECT - Set this bit to set L1-DCache tag memory as object. This bit should be onehot with the others fields inside this register. - 4 - 1 - read-write - - - L1_ICACHE0_MEM_OBJECT - Set this bit to set L1-ICache0 data memory as object. This bit should be onehot with the others fields inside this register. - 6 - 1 - read-write - - - L1_ICACHE1_MEM_OBJECT - Set this bit to set L1-ICache1 data memory as object. This bit should be onehot with the others fields inside this register. - 7 - 1 - read-write - - - L1_ICACHE2_MEM_OBJECT - Reserved - 8 - 1 - read-only - - - L1_ICACHE3_MEM_OBJECT - Reserved - 9 - 1 - read-only - - - L1_DCACHE_MEM_OBJECT - Set this bit to set L1-DCache data memory as object. This bit should be onehot with the others fields inside this register. - 10 - 1 - read-write - - - - - L1_CACHE_WAY_OBJECT - Cache Tag and Data memory way register - 0x260 - 0x20 - - - L1_CACHE_WAY_OBJECT - Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: way1, 2: way2, 3: way3, ?, 7: way7. - 0 - 3 - read-write - - - - - L1_CACHE_VADDR - Cache Vaddr register - 0x264 - 0x20 - 0x40000000 - - - L1_CACHE_VADDR - Those bits stores the virtual address which will decide where inside the specified tag memory object will be accessed. - 0 - 32 - read-write - - - - - L1_CACHE_DEBUG_BUS - Cache Tag/data memory content register - 0x268 - 0x20 - 0x00000268 - - - L1_CACHE_DEBUG_BUS - This is a constant place where we can write data to or read data from the tag/data memory on the specified cache. - 0 - 32 - read-write - - - - - LEVEL_SPLIT0 - USED TO SPLIT L1 CACHE AND L2 CACHE - 0x26C - 0x20 - 0x0000026C - - - LEVEL_SPLIT0 - Reserved - 0 - 32 - read-only - - - - - L2_CACHE_CTRL - L2 Cache(L2-Cache) control register - 0x270 - 0x20 - 0x00000010 - - - L2_CACHE_SHUT_DMA - The bit is used to disable DMA access L2-Cache, 0: enable, 1: disable - 4 - 1 - read-write - - - L2_CACHE_UNDEF_OP - Reserved - 8 - 8 - read-write - - - - - L2_BYPASS_CACHE_CONF - Bypass Cache configure register - 0x274 - 0x20 - - - BYPASS_L2_CACHE_EN - The bit is used to enable bypass L2-Cache. 0: disable bypass, 1: enable bypass. - 5 - 1 - read-write - - - - - L2_CACHE_CACHESIZE_CONF - L2 Cache CacheSize mode configure register - 0x278 - 0x20 - 0x00000400 - - - L2_CACHE_CACHESIZE_256 - The field is used to configure cachesize of L2-Cache as 256 bytes. This field and all other fields within this register is onehot. - 0 - 1 - read-only - - - L2_CACHE_CACHESIZE_512 - The field is used to configure cachesize of L2-Cache as 512 bytes. This field and all other fields within this register is onehot. - 1 - 1 - read-only - - - L2_CACHE_CACHESIZE_1K - The field is used to configure cachesize of L2-Cache as 1k bytes. This field and all other fields within this register is onehot. - 2 - 1 - read-only - - - L2_CACHE_CACHESIZE_2K - The field is used to configure cachesize of L2-Cache as 2k bytes. This field and all other fields within this register is onehot. - 3 - 1 - read-only - - - L2_CACHE_CACHESIZE_4K - The field is used to configure cachesize of L2-Cache as 4k bytes. This field and all other fields within this register is onehot. - 4 - 1 - read-only - - - L2_CACHE_CACHESIZE_8K - The field is used to configure cachesize of L2-Cache as 8k bytes. This field and all other fields within this register is onehot. - 5 - 1 - read-only - - - L2_CACHE_CACHESIZE_16K - The field is used to configure cachesize of L2-Cache as 16k bytes. This field and all other fields within this register is onehot. - 6 - 1 - read-only - - - L2_CACHE_CACHESIZE_32K - The field is used to configure cachesize of L2-Cache as 32k bytes. This field and all other fields within this register is onehot. - 7 - 1 - read-only - - - L2_CACHE_CACHESIZE_64K - The field is used to configure cachesize of L2-Cache as 64k bytes. This field and all other fields within this register is onehot. - 8 - 1 - read-only - - - L2_CACHE_CACHESIZE_128K - The field is used to configure cachesize of L2-Cache as 128k bytes. This field and all other fields within this register is onehot. - 9 - 1 - read-write - - - L2_CACHE_CACHESIZE_256K - The field is used to configure cachesize of L2-Cache as 256k bytes. This field and all other fields within this register is onehot. - 10 - 1 - read-write - - - L2_CACHE_CACHESIZE_512K - The field is used to configure cachesize of L2-Cache as 512k bytes. This field and all other fields within this register is onehot. - 11 - 1 - read-write - - - L2_CACHE_CACHESIZE_1024K - The field is used to configure cachesize of L2-Cache as 1024k bytes. This field and all other fields within this register is onehot. - 12 - 1 - read-only - - - - - L2_CACHE_BLOCKSIZE_CONF - L2 Cache BlockSize mode configure register - 0x27C - 0x20 - 0x00000008 - - - L2_CACHE_BLOCKSIZE_8 - The field is used to configureblocksize of L2-Cache as 8 bytes. This field and all other fields within this register is onehot. - 0 - 1 - read-only - - - L2_CACHE_BLOCKSIZE_16 - The field is used to configureblocksize of L2-Cache as 16 bytes. This field and all other fields within this register is onehot. - 1 - 1 - read-only - - - L2_CACHE_BLOCKSIZE_32 - The field is used to configureblocksize of L2-Cache as 32 bytes. This field and all other fields within this register is onehot. - 2 - 1 - read-only - - - L2_CACHE_BLOCKSIZE_64 - The field is used to configureblocksize of L2-Cache as 64 bytes. This field and all other fields within this register is onehot. - 3 - 1 - read-write - - - L2_CACHE_BLOCKSIZE_128 - The field is used to configureblocksize of L2-Cache as 128 bytes. This field and all other fields within this register is onehot. - 4 - 1 - read-write - - - L2_CACHE_BLOCKSIZE_256 - The field is used to configureblocksize of L2-Cache as 256 bytes. This field and all other fields within this register is onehot. - 5 - 1 - read-only - - - - - L2_CACHE_WRAP_AROUND_CTRL - Cache wrap around control register - 0x280 - 0x20 - - - L2_CACHE_WRAP - Set this bit as 1 to enable L2-Cache wrap around mode. - 5 - 1 - read-write - - - - - L2_CACHE_TAG_MEM_POWER_CTRL - Cache tag memory power control register - 0x284 - 0x20 - 0x00500000 - - - L2_CACHE_TAG_MEM_FORCE_ON - The bit is used to close clock gating of L2-Cache tag memory. 1: close gating, 0: open clock gating. - 20 - 1 - read-write - - - L2_CACHE_TAG_MEM_FORCE_PD - The bit is used to power L2-Cache tag memory down. 0: follow rtc_lslp, 1: power down - 21 - 1 - read-write - - - L2_CACHE_TAG_MEM_FORCE_PU - The bit is used to power L2-Cache tag memory up. 0: follow rtc_lslp, 1: power up - 22 - 1 - read-write - - - - - L2_CACHE_DATA_MEM_POWER_CTRL - Cache data memory power control register - 0x288 - 0x20 - 0x00500000 - - - L2_CACHE_DATA_MEM_FORCE_ON - The bit is used to close clock gating of L2-Cache data memory. 1: close gating, 0: open clock gating. - 20 - 1 - read-write - - - L2_CACHE_DATA_MEM_FORCE_PD - The bit is used to power L2-Cache data memory down. 0: follow rtc_lslp, 1: power down - 21 - 1 - read-write - - - L2_CACHE_DATA_MEM_FORCE_PU - The bit is used to power L2-Cache data memory up. 0: follow rtc_lslp, 1: power up - 22 - 1 - read-write - - - - - L2_CACHE_FREEZE_CTRL - Cache Freeze control register - 0x28C - 0x20 - - - L2_CACHE_FREEZE_EN - The bit is used to enable freeze operation on L2-Cache. It can be cleared by software. - 20 - 1 - read-write - - - L2_CACHE_FREEZE_MODE - The bit is used to configure mode of freeze operation L2-Cache. 0: a miss-access will not stuck. 1: a miss-access will stuck. - 21 - 1 - read-write - - - L2_CACHE_FREEZE_DONE - The bit is used to indicate whether freeze operation on L2-Cache is finished or not. 0: not finished. 1: finished. - 22 - 1 - read-only - - - - - L2_CACHE_DATA_MEM_ACS_CONF - Cache data memory access configure register - 0x290 - 0x20 - 0x00300000 - - - L2_CACHE_DATA_MEM_RD_EN - The bit is used to enable config-bus read L2-Cache data memoryory. 0: disable, 1: enable. - 20 - 1 - read-write - - - L2_CACHE_DATA_MEM_WR_EN - The bit is used to enable config-bus write L2-Cache data memoryory. 0: disable, 1: enable. - 21 - 1 - read-write - - - - - L2_CACHE_TAG_MEM_ACS_CONF - Cache tag memory access configure register - 0x294 - 0x20 - 0x00300000 - - - L2_CACHE_TAG_MEM_RD_EN - The bit is used to enable config-bus read L2-Cache tag memoryory. 0: disable, 1: enable. - 20 - 1 - read-write - - - L2_CACHE_TAG_MEM_WR_EN - The bit is used to enable config-bus write L2-Cache tag memoryory. 0: disable, 1: enable. - 21 - 1 - read-write - - - - - L2_CACHE_PRELOCK_CONF - L2 Cache prelock configure register - 0x298 - 0x20 - - - L2_CACHE_PRELOCK_SCT0_EN - The bit is used to enable the first section of prelock function on L2-Cache. - 0 - 1 - read-write - - - L2_CACHE_PRELOCK_SCT1_EN - The bit is used to enable the second section of prelock function on L2-Cache. - 1 - 1 - read-write - - - L2_CACHE_PRELOCK_RGID - The bit is used to set the gid of l2 cache prelock. - 2 - 4 - read-write - - - - - L2_CACHE_PRELOCK_SCT0_ADDR - L2 Cache prelock section0 address configure register - 0x29C - 0x20 - - - L2_CACHE_PRELOCK_SCT0_ADDR - Those bits are used to configure the start virtual address of the first section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_SIZE_REG - 0 - 32 - read-write - - - - - L2_CACHE_PRELOCK_SCT1_ADDR - L2 Cache prelock section1 address configure register - 0x2A0 - 0x20 - - - L2_CACHE_PRELOCK_SCT1_ADDR - Those bits are used to configure the start virtual address of the second section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_SIZE_REG - 0 - 32 - read-write - - - - - L2_CACHE_PRELOCK_SCT_SIZE - L2 Cache prelock section size configure register - 0x2A4 - 0x20 - 0xFFFFFFFF - - - L2_CACHE_PRELOCK_SCT0_SIZE - Those bits are used to configure the size of the first section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_ADDR_REG - 0 - 16 - read-write - - - L2_CACHE_PRELOCK_SCT1_SIZE - Those bits are used to configure the size of the second section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_ADDR_REG - 16 - 16 - read-write - - - - - L2_CACHE_PRELOAD_CTRL - L2 Cache preload-operation control register - 0x2A8 - 0x20 - 0x00000002 - - - L2_CACHE_PRELOAD_ENA - The bit is used to enable preload operation on L2-Cache. It will be cleared by hardware automatically after preload operation is done. - 0 - 1 - read-write - - - L2_CACHE_PRELOAD_DONE - The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished. - 1 - 1 - read-only - - - L2_CACHE_PRELOAD_ORDER - The bit is used to configure the direction of preload operation. 0: ascending, 1: descending. - 2 - 1 - read-write - - - L2_CACHE_PRELOAD_RGID - The bit is used to set the gid of l2 cache preload. - 3 - 4 - read-write - - - - - L2_CACHE_PRELOAD_ADDR - L2 Cache preload address configure register - 0x2AC - 0x20 - - - L2_CACHE_PRELOAD_ADDR - Those bits are used to configure the start virtual address of preload on L2-Cache, which should be used together with L2_CACHE_PRELOAD_SIZE_REG - 0 - 32 - read-write - - - - - L2_CACHE_PRELOAD_SIZE - L2 Cache preload size configure register - 0x2B0 - 0x20 - - - L2_CACHE_PRELOAD_SIZE - Those bits are used to configure the size of the first section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOAD_ADDR_REG - 0 - 16 - read-write - - - - - L2_CACHE_AUTOLOAD_CTRL - L2 Cache autoload-operation control register - 0x2B4 - 0x20 - 0x00000002 - - - L2_CACHE_AUTOLOAD_ENA - The bit is used to enable and disable autoload operation on L2-Cache. 1: enable, 0: disable. - 0 - 1 - read-write - - - L2_CACHE_AUTOLOAD_DONE - The bit is used to indicate whether autoload operation on L2-Cache is finished or not. 0: not finished. 1: finished. - 1 - 1 - read-only - - - L2_CACHE_AUTOLOAD_ORDER - The bit is used to configure the direction of autoload operation on L2-Cache. 0: ascending. 1: descending. - 2 - 1 - read-write - - - L2_CACHE_AUTOLOAD_TRIGGER_MODE - The field is used to configure trigger mode of autoload operation on L2-Cache. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. - 3 - 2 - read-write - - - L2_CACHE_AUTOLOAD_SCT0_ENA - The bit is used to enable the first section for autoload operation on L2-Cache. - 8 - 1 - read-write - - - L2_CACHE_AUTOLOAD_SCT1_ENA - The bit is used to enable the second section for autoload operation on L2-Cache. - 9 - 1 - read-write - - - L2_CACHE_AUTOLOAD_SCT2_ENA - The bit is used to enable the third section for autoload operation on L2-Cache. - 10 - 1 - read-write - - - L2_CACHE_AUTOLOAD_SCT3_ENA - The bit is used to enable the fourth section for autoload operation on L2-Cache. - 11 - 1 - read-write - - - L2_CACHE_AUTOLOAD_RGID - The bit is used to set the gid of l2 cache autoload. - 12 - 4 - read-write - - - - - L2_CACHE_AUTOLOAD_SCT0_ADDR - L2 Cache autoload section 0 address configure register - 0x2B8 - 0x20 - - - L2_CACHE_AUTOLOAD_SCT0_ADDR - Those bits are used to configure the start virtual address of the first section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT0_SIZE and L2_CACHE_AUTOLOAD_SCT0_ENA. - 0 - 32 - read-write - - - - - L2_CACHE_AUTOLOAD_SCT0_SIZE - L2 Cache autoload section 0 size configure register - 0x2BC - 0x20 - - - L2_CACHE_AUTOLOAD_SCT0_SIZE - Those bits are used to configure the size of the first section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT0_ADDR and L2_CACHE_AUTOLOAD_SCT0_ENA. - 0 - 28 - read-write - - - - - L2_CACHE_AUTOLOAD_SCT1_ADDR - L2 Cache autoload section 1 address configure register - 0x2C0 - 0x20 - - - L2_CACHE_AUTOLOAD_SCT1_ADDR - Those bits are used to configure the start virtual address of the second section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT1_SIZE and L2_CACHE_AUTOLOAD_SCT1_ENA. - 0 - 32 - read-write - - - - - L2_CACHE_AUTOLOAD_SCT1_SIZE - L2 Cache autoload section 1 size configure register - 0x2C4 - 0x20 - - - L2_CACHE_AUTOLOAD_SCT1_SIZE - Those bits are used to configure the size of the second section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT1_ADDR and L2_CACHE_AUTOLOAD_SCT1_ENA. - 0 - 28 - read-write - - - - - L2_CACHE_AUTOLOAD_SCT2_ADDR - L2 Cache autoload section 2 address configure register - 0x2C8 - 0x20 - - - L2_CACHE_AUTOLOAD_SCT2_ADDR - Those bits are used to configure the start virtual address of the third section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT2_SIZE and L2_CACHE_AUTOLOAD_SCT2_ENA. - 0 - 32 - read-write - - - - - L2_CACHE_AUTOLOAD_SCT2_SIZE - L2 Cache autoload section 2 size configure register - 0x2CC - 0x20 - - - L2_CACHE_AUTOLOAD_SCT2_SIZE - Those bits are used to configure the size of the third section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT2_ADDR and L2_CACHE_AUTOLOAD_SCT2_ENA. - 0 - 28 - read-write - - - - - L2_CACHE_AUTOLOAD_SCT3_ADDR - L2 Cache autoload section 3 address configure register - 0x2D0 - 0x20 - - - L2_CACHE_AUTOLOAD_SCT3_ADDR - Those bits are used to configure the start virtual address of the fourth section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT3_SIZE and L2_CACHE_AUTOLOAD_SCT3_ENA. - 0 - 32 - read-write - - - - - L2_CACHE_AUTOLOAD_SCT3_SIZE - L2 Cache autoload section 3 size configure register - 0x2D4 - 0x20 - - - L2_CACHE_AUTOLOAD_SCT3_SIZE - Those bits are used to configure the size of the fourth section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT3_ADDR and L2_CACHE_AUTOLOAD_SCT3_ENA. - 0 - 28 - read-write - - - - - L2_CACHE_ACS_CNT_INT_ENA - Cache Access Counter Interrupt enable register - 0x2D8 - 0x20 - - - L2_IBUS0_OVF_INT_ENA - The bit is used to enable interrupt of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-Cache. - 8 - 1 - read-write - - - L2_IBUS1_OVF_INT_ENA - The bit is used to enable interrupt of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-Cache. - 9 - 1 - read-write - - - L2_IBUS2_OVF_INT_ENA - Reserved - 10 - 1 - read-only - - - L2_IBUS3_OVF_INT_ENA - Reserved - 11 - 1 - read-only - - - L2_DBUS0_OVF_INT_ENA - The bit is used to enable interrupt of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-Cache. - 12 - 1 - read-write - - - L2_DBUS1_OVF_INT_ENA - The bit is used to enable interrupt of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-Cache. - 13 - 1 - read-write - - - L2_DBUS2_OVF_INT_ENA - Reserved - 14 - 1 - read-only - - - L2_DBUS3_OVF_INT_ENA - Reserved - 15 - 1 - read-only - - - - - L2_CACHE_ACS_CNT_INT_CLR - Cache Access Counter Interrupt clear register - 0x2DC - 0x20 - - - L2_IBUS0_OVF_INT_CLR - The bit is used to clear counters overflow interrupt and counters in L2-Cache due to bus0 accesses L2-Cache. - 8 - 1 - write-only - - - L2_IBUS1_OVF_INT_CLR - The bit is used to clear counters overflow interrupt and counters in L2-Cache due to bus1 accesses L2-Cache. - 9 - 1 - write-only - - - L2_IBUS2_OVF_INT_CLR - Reserved - 10 - 1 - read-only - - - L2_IBUS3_OVF_INT_CLR - Reserved - 11 - 1 - read-only - - - L2_DBUS0_OVF_INT_CLR - The bit is used to clear counters overflow interrupt and counters in L2-Cache due to bus0 accesses L2-Cache. - 12 - 1 - write-only - - - L2_DBUS1_OVF_INT_CLR - The bit is used to clear counters overflow interrupt and counters in L2-Cache due to bus1 accesses L2-Cache. - 13 - 1 - write-only - - - L2_DBUS2_OVF_INT_CLR - Reserved - 14 - 1 - read-only - - - L2_DBUS3_OVF_INT_CLR - Reserved - 15 - 1 - read-only - - - - - L2_CACHE_ACS_CNT_INT_RAW - Cache Access Counter Interrupt raw register - 0x2E0 - 0x20 - - - L2_IBUS0_OVF_INT_RAW - The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-ICache0. - 8 - 1 - read-write - - - L2_IBUS1_OVF_INT_RAW - The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-ICache1. - 9 - 1 - read-write - - - L2_IBUS2_OVF_INT_RAW - The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus2 accesses L2-ICache2. - 10 - 1 - read-write - - - L2_IBUS3_OVF_INT_RAW - The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus3 accesses L2-ICache3. - 11 - 1 - read-write - - - L2_DBUS0_OVF_INT_RAW - The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-DCache. - 12 - 1 - read-write - - - L2_DBUS1_OVF_INT_RAW - The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-DCache. - 13 - 1 - read-write - - - L2_DBUS2_OVF_INT_RAW - The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus2 accesses L2-DCache. - 14 - 1 - read-write - - - L2_DBUS3_OVF_INT_RAW - The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus3 accesses L2-DCache. - 15 - 1 - read-write - - - - - L2_CACHE_ACS_CNT_INT_ST - Cache Access Counter Interrupt status register - 0x2E4 - 0x20 - - - L2_IBUS0_OVF_INT_ST - The bit indicates the interrupt status of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-Cache. - 8 - 1 - read-only - - - L2_IBUS1_OVF_INT_ST - The bit indicates the interrupt status of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-Cache. - 9 - 1 - read-only - - - L2_IBUS2_OVF_INT_ST - Reserved - 10 - 1 - read-only - - - L2_IBUS3_OVF_INT_ST - Reserved - 11 - 1 - read-only - - - L2_DBUS0_OVF_INT_ST - The bit indicates the interrupt status of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-Cache. - 12 - 1 - read-only - - - L2_DBUS1_OVF_INT_ST - The bit indicates the interrupt status of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-Cache. - 13 - 1 - read-only - - - L2_DBUS2_OVF_INT_ST - Reserved - 14 - 1 - read-only - - - L2_DBUS3_OVF_INT_ST - Reserved - 15 - 1 - read-only - - - - - L2_CACHE_ACS_FAIL_CTRL - Cache Access Fail Configuration register - 0x2E8 - 0x20 - - - L2_CACHE_ACS_FAIL_CHECK_MODE - The bit is used to configure l2 cache access fail check mode. 0: the access fail is not propagated to the request, 1: the access fail is propagated to the request - 0 - 1 - read-write - - - - - L2_CACHE_ACS_FAIL_INT_ENA - Cache Access Fail Interrupt enable register - 0x2EC - 0x20 - - - L2_CACHE_FAIL_INT_ENA - The bit is used to enable interrupt of access fail that occurs in L2-Cache due to l1 cache accesses L2-Cache. - 5 - 1 - read-write - - - - - L2_CACHE_ACS_FAIL_INT_CLR - L1-Cache Access Fail Interrupt clear register - 0x2F0 - 0x20 - - - L2_CACHE_FAIL_INT_CLR - The bit is used to clear interrupt of access fail that occurs in L2-Cache due to l1 cache accesses L2-Cache. - 5 - 1 - write-only - - - - - L2_CACHE_ACS_FAIL_INT_RAW - Cache Access Fail Interrupt raw register - 0x2F4 - 0x20 - - - L2_CACHE_FAIL_INT_RAW - The raw bit of the interrupt of access fail that occurs in L2-Cache. - 5 - 1 - read-write - - - - - L2_CACHE_ACS_FAIL_INT_ST - Cache Access Fail Interrupt status register - 0x2F8 - 0x20 - - - L2_CACHE_FAIL_INT_ST - The bit indicates the interrupt status of access fail that occurs in L2-Cache due to l1 cache accesses L2-Cache. - 5 - 1 - read-only - - - - - L2_CACHE_ACS_CNT_CTRL - Cache Access Counter enable and clear register - 0x2FC - 0x20 - - - L2_IBUS0_CNT_ENA - The bit is used to enable ibus0 counter in L2-Cache. - 8 - 1 - read-write - - - L2_IBUS1_CNT_ENA - The bit is used to enable ibus1 counter in L2-Cache. - 9 - 1 - read-write - - - L2_IBUS2_CNT_ENA - Reserved - 10 - 1 - read-only - - - L2_IBUS3_CNT_ENA - Reserved - 11 - 1 - read-only - - - L2_DBUS0_CNT_ENA - The bit is used to enable dbus0 counter in L2-Cache. - 12 - 1 - read-write - - - L2_DBUS1_CNT_ENA - The bit is used to enable dbus1 counter in L2-Cache. - 13 - 1 - read-write - - - L2_DBUS2_CNT_ENA - Reserved - 14 - 1 - read-only - - - L2_DBUS3_CNT_ENA - Reserved - 15 - 1 - read-only - - - L2_IBUS0_CNT_CLR - The bit is used to clear ibus0 counter in L2-Cache. - 24 - 1 - write-only - - - L2_IBUS1_CNT_CLR - The bit is used to clear ibus1 counter in L2-Cache. - 25 - 1 - write-only - - - L2_IBUS2_CNT_CLR - Reserved - 26 - 1 - read-only - - - L2_IBUS3_CNT_CLR - Reserved - 27 - 1 - read-only - - - L2_DBUS0_CNT_CLR - The bit is used to clear dbus0 counter in L2-Cache. - 28 - 1 - write-only - - - L2_DBUS1_CNT_CLR - The bit is used to clear dbus1 counter in L2-Cache. - 29 - 1 - write-only - - - L2_DBUS2_CNT_CLR - Reserved - 30 - 1 - read-only - - - L2_DBUS3_CNT_CLR - Reserved - 31 - 1 - read-only - - - - - L2_IBUS0_ACS_HIT_CNT - L2-Cache bus0 Hit-Access Counter register - 0x300 - 0x20 - - - L2_IBUS0_HIT_CNT - The register records the number of hits when L1-ICache0 accesses L2-Cache due to bus0 accessing L1-ICache0. - 0 - 32 - read-only - - - - - L2_IBUS0_ACS_MISS_CNT - L2-Cache bus0 Miss-Access Counter register - 0x304 - 0x20 - - - L2_IBUS0_MISS_CNT - The register records the number of missing when L1-ICache0 accesses L2-Cache due to bus0 accessing L1-ICache0. - 0 - 32 - read-only - - - - - L2_IBUS0_ACS_CONFLICT_CNT - L2-Cache bus0 Conflict-Access Counter register - 0x308 - 0x20 - - - L2_IBUS0_CONFLICT_CNT - The register records the number of access-conflicts when L1-ICache0 accesses L2-Cache due to bus0 accessing L1-ICache0. - 0 - 32 - read-only - - - - - L2_IBUS0_ACS_NXTLVL_RD_CNT - L2-Cache bus0 Next-Level-Access Counter register - 0x30C - 0x20 - - - L2_IBUS0_NXTLVL_RD_CNT - The register records the number of times that L2-Cache accesses external memory due to L1-ICache0 accessing L2-Cache due to bus0 accessing L1-ICache0. - 0 - 32 - read-only - - - - - L2_IBUS1_ACS_HIT_CNT - L2-Cache bus1 Hit-Access Counter register - 0x310 - 0x20 - - - L2_IBUS1_HIT_CNT - The register records the number of hits when L1-ICache1 accesses L2-Cache due to bus1 accessing L1-ICache1. - 0 - 32 - read-only - - - - - L2_IBUS1_ACS_MISS_CNT - L2-Cache bus1 Miss-Access Counter register - 0x314 - 0x20 - - - L2_IBUS1_MISS_CNT - The register records the number of missing when L1-ICache1 accesses L2-Cache due to bus1 accessing L1-ICache1. - 0 - 32 - read-only - - - - - L2_IBUS1_ACS_CONFLICT_CNT - L2-Cache bus1 Conflict-Access Counter register - 0x318 - 0x20 - - - L2_IBUS1_CONFLICT_CNT - The register records the number of access-conflicts when L1-ICache1 accesses L2-Cache due to bus1 accessing L1-ICache1. - 0 - 32 - read-only - - - - - L2_IBUS1_ACS_NXTLVL_RD_CNT - L2-Cache bus1 Next-Level-Access Counter register - 0x31C - 0x20 - - - L2_IBUS1_NXTLVL_RD_CNT - The register records the number of times that L2-Cache accesses external memory due to L1-ICache1 accessing L2-Cache due to bus1 accessing L1-ICache1. - 0 - 32 - read-only - - - - - L2_IBUS2_ACS_HIT_CNT - L2-Cache bus2 Hit-Access Counter register - 0x320 - 0x20 - - - L2_IBUS2_HIT_CNT - The register records the number of hits when L1-ICache2 accesses L2-Cache due to bus2 accessing L1-ICache2. - 0 - 32 - read-only - - - - - L2_IBUS2_ACS_MISS_CNT - L2-Cache bus2 Miss-Access Counter register - 0x324 - 0x20 - - - L2_IBUS2_MISS_CNT - The register records the number of missing when L1-ICache2 accesses L2-Cache due to bus2 accessing L1-ICache2. - 0 - 32 - read-only - - - - - L2_IBUS2_ACS_CONFLICT_CNT - L2-Cache bus2 Conflict-Access Counter register - 0x328 - 0x20 - - - L2_IBUS2_CONFLICT_CNT - The register records the number of access-conflicts when L1-ICache2 accesses L2-Cache due to bus2 accessing L1-ICache2. - 0 - 32 - read-only - - - - - L2_IBUS2_ACS_NXTLVL_RD_CNT - L2-Cache bus2 Next-Level-Access Counter register - 0x32C - 0x20 - - - L2_IBUS2_NXTLVL_RD_CNT - The register records the number of times that L2-Cache accesses external memory due to L1-ICache2 accessing L2-Cache due to bus2 accessing L1-ICache2. - 0 - 32 - read-only - - - - - L2_IBUS3_ACS_HIT_CNT - L2-Cache bus3 Hit-Access Counter register - 0x330 - 0x20 - - - L2_IBUS3_HIT_CNT - The register records the number of hits when L1-ICache3 accesses L2-Cache due to bus3 accessing L1-ICache3. - 0 - 32 - read-only - - - - - L2_IBUS3_ACS_MISS_CNT - L2-Cache bus3 Miss-Access Counter register - 0x334 - 0x20 - - - L2_IBUS3_MISS_CNT - The register records the number of missing when L1-ICache3 accesses L2-Cache due to bus3 accessing L1-ICache3. - 0 - 32 - read-only - - - - - L2_IBUS3_ACS_CONFLICT_CNT - L2-Cache bus3 Conflict-Access Counter register - 0x338 - 0x20 - - - L2_IBUS3_CONFLICT_CNT - The register records the number of access-conflicts when L1-ICache3 accesses L2-Cache due to bus3 accessing L1-ICache3. - 0 - 32 - read-only - - - - - L2_IBUS3_ACS_NXTLVL_RD_CNT - L2-Cache bus3 Next-Level-Access Counter register - 0x33C - 0x20 - - - L2_IBUS3_NXTLVL_RD_CNT - The register records the number of times that L2-Cache accesses external memory due to L1-ICache3 accessing L2-Cache due to bus3 accessing L1-ICache3. - 0 - 32 - read-only - - - - - L2_DBUS0_ACS_HIT_CNT - L2-Cache bus0 Hit-Access Counter register - 0x340 - 0x20 - - - L2_DBUS0_HIT_CNT - The register records the number of hits when L1-DCache accesses L2-Cache due to bus0 accessing L1-DCache. - 0 - 32 - read-only - - - - - L2_DBUS0_ACS_MISS_CNT - L2-Cache bus0 Miss-Access Counter register - 0x344 - 0x20 - - - L2_DBUS0_MISS_CNT - The register records the number of missing when L1-DCache accesses L2-Cache due to bus0 accessing L1-DCache. - 0 - 32 - read-only - - - - - L2_DBUS0_ACS_CONFLICT_CNT - L2-Cache bus0 Conflict-Access Counter register - 0x348 - 0x20 - - - L2_DBUS0_CONFLICT_CNT - The register records the number of access-conflicts when L1-DCache accesses L2-Cache due to bus0 accessing L1-DCache. - 0 - 32 - read-only - - - - - L2_DBUS0_ACS_NXTLVL_RD_CNT - L2-Cache bus0 Next-Level-Access Counter register - 0x34C - 0x20 - - - L2_DBUS0_NXTLVL_RD_CNT - The register records the number of times that L2-Cache accesses external memory due to L1-DCache accessing L2-Cache due to bus0 accessing L1-DCache. - 0 - 32 - read-only - - - - - L2_DBUS0_ACS_NXTLVL_WR_CNT - L2-Cache bus0 WB-Access Counter register - 0x350 - 0x20 - - - L2_DBUS0_NXTLVL_WR_CNT - The register records the number of write back when L1-DCache accesses L2-Cache due to bus0 accessing L1-DCache. - 0 - 32 - read-only - - - - - L2_DBUS1_ACS_HIT_CNT - L2-Cache bus1 Hit-Access Counter register - 0x354 - 0x20 - - - L2_DBUS1_HIT_CNT - The register records the number of hits when L1-DCache accesses L2-Cache due to bus1 accessing L1-DCache. - 0 - 32 - read-only - - - - - L2_DBUS1_ACS_MISS_CNT - L2-Cache bus1 Miss-Access Counter register - 0x358 - 0x20 - - - L2_DBUS1_MISS_CNT - The register records the number of missing when L1-DCache accesses L2-Cache due to bus1 accessing L1-DCache. - 0 - 32 - read-only - - - - - L2_DBUS1_ACS_CONFLICT_CNT - L2-Cache bus1 Conflict-Access Counter register - 0x35C - 0x20 - - - L2_DBUS1_CONFLICT_CNT - The register records the number of access-conflicts when L1-DCache accesses L2-Cache due to bus1 accessing L1-DCache. - 0 - 32 - read-only - - - - - L2_DBUS1_ACS_NXTLVL_RD_CNT - L2-Cache bus1 Next-Level-Access Counter register - 0x360 - 0x20 - - - L2_DBUS1_NXTLVL_RD_CNT - The register records the number of times that L2-Cache accesses external memory due to L1-DCache accessing L2-Cache due to bus1 accessing L1-DCache. - 0 - 32 - read-only - - - - - L2_DBUS1_ACS_NXTLVL_WR_CNT - L2-Cache bus1 WB-Access Counter register - 0x364 - 0x20 - - - L2_DBUS1_NXTLVL_WR_CNT - The register records the number of write back when L1-DCache accesses L2-Cache due to bus1 accessing L1-DCache. - 0 - 32 - read-only - - - - - L2_DBUS2_ACS_HIT_CNT - L2-Cache bus2 Hit-Access Counter register - 0x368 - 0x20 - - - L2_DBUS2_HIT_CNT - The register records the number of hits when L1-DCache accesses L2-Cache due to bus2 accessing L1-DCache. - 0 - 32 - read-only - - - - - L2_DBUS2_ACS_MISS_CNT - L2-Cache bus2 Miss-Access Counter register - 0x36C - 0x20 - - - L2_DBUS2_MISS_CNT - The register records the number of missing when L1-DCache accesses L2-Cache due to bus2 accessing L1-DCache. - 0 - 32 - read-only - - - - - L2_DBUS2_ACS_CONFLICT_CNT - L2-Cache bus2 Conflict-Access Counter register - 0x370 - 0x20 - - - L2_DBUS2_CONFLICT_CNT - The register records the number of access-conflicts when L1-DCache accesses L2-Cache due to bus2 accessing L1-DCache. - 0 - 32 - read-only - - - - - L2_DBUS2_ACS_NXTLVL_RD_CNT - L2-Cache bus2 Next-Level-Access Counter register - 0x374 - 0x20 - - - L2_DBUS2_NXTLVL_RD_CNT - The register records the number of times that L2-Cache accesses external memory due to L1-DCache accessing L2-Cache due to bus2 accessing L1-DCache. - 0 - 32 - read-only - - - - - L2_DBUS2_ACS_NXTLVL_WR_CNT - L2-Cache bus2 WB-Access Counter register - 0x378 - 0x20 - - - L2_DBUS2_NXTLVL_WR_CNT - The register records the number of write back when L1-DCache accesses L2-Cache due to bus2 accessing L1-DCache. - 0 - 32 - read-only - - - - - L2_DBUS3_ACS_HIT_CNT - L2-Cache bus3 Hit-Access Counter register - 0x37C - 0x20 - - - L2_DBUS3_HIT_CNT - The register records the number of hits when L1-DCache accesses L2-Cache due to bus3 accessing L1-DCache. - 0 - 32 - read-only - - - - - L2_DBUS3_ACS_MISS_CNT - L2-Cache bus3 Miss-Access Counter register - 0x380 - 0x20 - - - L2_DBUS3_MISS_CNT - The register records the number of missing when L1-DCache accesses L2-Cache due to bus3 accessing L1-DCache. - 0 - 32 - read-only - - - - - L2_DBUS3_ACS_CONFLICT_CNT - L2-Cache bus3 Conflict-Access Counter register - 0x384 - 0x20 - - - L2_DBUS3_CONFLICT_CNT - The register records the number of access-conflicts when L1-DCache accesses L2-Cache due to bus3 accessing L1-DCache. - 0 - 32 - read-only - - - - - L2_DBUS3_ACS_NXTLVL_RD_CNT - L2-Cache bus3 Next-Level-Access Counter register - 0x388 - 0x20 - - - L2_DBUS3_NXTLVL_RD_CNT - The register records the number of times that L2-Cache accesses external memory due to L1-DCache accessing L2-Cache due to bus3 accessing L1-DCache. - 0 - 32 - read-only - - - - - L2_DBUS3_ACS_NXTLVL_WR_CNT - L2-Cache bus3 WB-Access Counter register - 0x38C - 0x20 - - - L2_DBUS3_NXTLVL_WR_CNT - The register records the number of write back when L1-DCache accesses L2-Cache due to bus3 accessing L1-DCache. - 0 - 32 - read-only - - - - - L2_CACHE_ACS_FAIL_ID_ATTR - L2-Cache Access Fail ID/attribution information register - 0x390 - 0x20 - - - L2_CACHE_FAIL_ID - The register records the ID of fail-access when L1-Cache accesses L2-Cache. - 0 - 16 - read-only - - - L2_CACHE_FAIL_ATTR - The register records the attribution of fail-access when L1-Cache accesses L2-Cache due to cache accessing L1-Cache. - 16 - 16 - read-only - - - - - L2_CACHE_ACS_FAIL_ADDR - L2-Cache Access Fail Address information register - 0x394 - 0x20 - - - L2_CACHE_FAIL_ADDR - The register records the address of fail-access when L1-Cache accesses L2-Cache. - 0 - 32 - read-only - - - - - L2_CACHE_SYNC_PRELOAD_INT_ENA - L1-Cache Access Fail Interrupt enable register - 0x398 - 0x20 - - - L2_CACHE_PLD_DONE_INT_ENA - The bit is used to enable interrupt of L2-Cache preload-operation done. - 5 - 1 - read-write - - - L2_CACHE_PLD_ERR_INT_ENA - The bit is used to enable interrupt of L2-Cache preload-operation error. - 12 - 1 - read-write - - - - - L2_CACHE_SYNC_PRELOAD_INT_CLR - Sync Preload operation Interrupt clear register - 0x39C - 0x20 - - - L2_CACHE_PLD_DONE_INT_CLR - The bit is used to clear interrupt that occurs only when L2-Cache preload-operation is done. - 5 - 1 - write-only - - - L2_CACHE_PLD_ERR_INT_CLR - The bit is used to clear interrupt of L2-Cache preload-operation error. - 12 - 1 - write-only - - - - - L2_CACHE_SYNC_PRELOAD_INT_RAW - Sync Preload operation Interrupt raw register - 0x3A0 - 0x20 - - - L2_CACHE_PLD_DONE_INT_RAW - The raw bit of the interrupt that occurs only when L2-Cache preload-operation is done. - 5 - 1 - read-write - - - L2_CACHE_PLD_ERR_INT_RAW - The raw bit of the interrupt that occurs only when L2-Cache preload-operation error occurs. - 12 - 1 - read-write - - - - - L2_CACHE_SYNC_PRELOAD_INT_ST - L1-Cache Access Fail Interrupt status register - 0x3A4 - 0x20 - - - L2_CACHE_PLD_DONE_INT_ST - The bit indicates the status of the interrupt that occurs only when L2-Cache preload-operation is done. - 5 - 1 - read-only - - - L2_CACHE_PLD_ERR_INT_ST - The bit indicates the status of the interrupt of L2-Cache preload-operation error. - 12 - 1 - read-only - - - - - L2_CACHE_SYNC_PRELOAD_EXCEPTION - Cache Sync/Preload Operation exception register - 0x3A8 - 0x20 - - - L2_CACHE_PLD_ERR_CODE - The value 2 is Only available which means preload size is error in L2-Cache. - 10 - 2 - read-only - - - - - L2_CACHE_SYNC_RST_CTRL - Cache Sync Reset control register - 0x3AC - 0x20 - - - L2_CACHE_SYNC_RST - set this bit to reset sync-logic inside L2-Cache. Recommend that this should only be used to initialize sync-logic when some fatal error of sync-logic occurs. - 5 - 1 - read-write - - - - - L2_CACHE_PRELOAD_RST_CTRL - Cache Preload Reset control register - 0x3B0 - 0x20 - - - L2_CACHE_PLD_RST - set this bit to reset preload-logic inside L2-Cache. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs. - 5 - 1 - read-write - - - - - L2_CACHE_AUTOLOAD_BUF_CLR_CTRL - Cache Autoload buffer clear control register - 0x3B4 - 0x20 - - - L2_CACHE_ALD_BUF_CLR - set this bit to clear autoload-buffer inside L2-Cache. If this bit is active, autoload will not work in L2-Cache. This bit should not be active when autoload works in L2-Cache. - 5 - 1 - read-write - - - - - L2_UNALLOCATE_BUFFER_CLEAR - Unallocate request buffer clear registers - 0x3B8 - 0x20 - - - L2_CACHE_UNALLOC_CLR - The bit is used to clear the unallocate request buffer of l2 icache where the unallocate request is responsed but not completed. - 5 - 1 - read-write - - - - - L2_CACHE_ACCESS_ATTR_CTRL - L2 cache access attribute control register - 0x3BC - 0x20 - 0x0000000F - - - L2_CACHE_ACCESS_FORCE_CC - Set this bit to force the request to l2 cache with cacheable attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of cacheable and non-cacheable. - 0 - 1 - read-write - - - L2_CACHE_ACCESS_FORCE_WB - Set this bit to force the request to l2 cache with write-back attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of write-back and write-through. - 1 - 1 - read-write - - - L2_CACHE_ACCESS_FORCE_WMA - Set this bit to force the request to l2 cache with write-miss-allocate attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of write-miss-allocate and write-miss-no-allocate. - 2 - 1 - read-write - - - L2_CACHE_ACCESS_FORCE_RMA - Set this bit to force the request to l2 cache with read-miss-allocate attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of read-miss-allocate and read-miss-no-allocate. - 3 - 1 - read-write - - - - - L2_CACHE_OBJECT_CTRL - Cache Tag and Data memory Object control register - 0x3C0 - 0x20 - - - L2_CACHE_TAG_OBJECT - Set this bit to set L2-Cache tag memory as object. This bit should be onehot with the others fields inside this register. - 5 - 1 - read-write - - - L2_CACHE_MEM_OBJECT - Set this bit to set L2-Cache data memory as object. This bit should be onehot with the others fields inside this register. - 11 - 1 - read-write - - - - - L2_CACHE_WAY_OBJECT - Cache Tag and Data memory way register - 0x3C4 - 0x20 - - - L2_CACHE_WAY_OBJECT - Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: way1, 2: way2, 3: way3, ?, 7: way7. - 0 - 3 - read-write - - - - - L2_CACHE_VADDR - Cache Vaddr register - 0x3C8 - 0x20 - 0x40000000 - - - L2_CACHE_VADDR - Those bits stores the virtual address which will decide where inside the specified tag memory object will be accessed. - 0 - 32 - read-write - - - - - L2_CACHE_DEBUG_BUS - Cache Tag/data memory content register - 0x3CC - 0x20 - 0x000003CC - - - L2_CACHE_DEBUG_BUS - This is a constant place where we can write data to or read data from the tag/data memory on the specified cache. - 0 - 32 - read-write - - - - - LEVEL_SPLIT1 - USED TO SPLIT L1 CACHE AND L2 CACHE - 0x3D0 - 0x20 - 0x000003D0 - - - LEVEL_SPLIT1 - Reserved - 0 - 32 - read-only - - - - - CLOCK_GATE - Clock gate control register - 0x3D4 - 0x20 - 0x00000001 - - - CLK_EN - The bit is used to enable clock gate when access all registers in this module. - 0 - 1 - read-write - - - - - REDUNDANCY_SIG0 - Cache redundancy signal 0 register - 0x3D8 - 0x20 - - - REDCY_SIG0 - Those bits are prepared for ECO. - 0 - 32 - read-write - - - - - REDUNDANCY_SIG1 - Cache redundancy signal 1 register - 0x3DC - 0x20 - - - REDCY_SIG1 - Those bits are prepared for ECO. - 0 - 32 - read-write - - - - - REDUNDANCY_SIG2 - Cache redundancy signal 2 register - 0x3E0 - 0x20 - - - REDCY_SIG2 - Those bits are prepared for ECO. - 0 - 32 - read-write - - - - - REDUNDANCY_SIG3 - Cache redundancy signal 3 register - 0x3E4 - 0x20 - - - REDCY_SIG3 - Those bits are prepared for ECO. - 0 - 32 - read-write - - - - - REDUNDANCY_SIG4 - Cache redundancy signal 0 register - 0x3E8 - 0x20 - - - REDCY_SIG4 - Those bits are prepared for ECO. - 0 - 4 - read-only - - - - - DATE - Version control register - 0x3FC - 0x20 - 0x02304130 - - - DATE - version control register. Note that this default value stored is the latest date when the hardware logic was updated. - 0 - 28 - read-write - - - - - - - INTERRUPT_CORE0 - Interrupt Controller (Core 0) - CORE0 - 0x500D6000 - - 0x0 - 0x218 - registers - - - - LP_RTC_INT_MAP - NA - 0x0 - 0x20 - - - CORE0_LP_RTC_INT_MAP - NA - 0 - 6 - read-write - - - - - LP_WDT_INT_MAP - NA - 0x4 - 0x20 - - - CORE0_LP_WDT_INT_MAP - NA - 0 - 6 - read-write - - - - - LP_TIMER_REG_0_INT_MAP - NA - 0x8 - 0x20 - - - CORE0_LP_TIMER_REG_0_INT_MAP - NA - 0 - 6 - read-write - - - - - LP_TIMER_REG_1_INT_MAP - NA - 0xC - 0x20 - - - CORE0_LP_TIMER_REG_1_INT_MAP - NA - 0 - 6 - read-write - - - - - MB_HP_INT_MAP - NA - 0x10 - 0x20 - - - CORE0_MB_HP_INT_MAP - NA - 0 - 6 - read-write - - - - - MB_LP_INT_MAP - NA - 0x14 - 0x20 - - - CORE0_MB_LP_INT_MAP - NA - 0 - 6 - read-write - - - - - PMU_REG_0_INT_MAP - NA - 0x18 - 0x20 - - - CORE0_PMU_REG_0_INT_MAP - NA - 0 - 6 - read-write - - - - - PMU_REG_1_INT_MAP - NA - 0x1C - 0x20 - - - CORE0_PMU_REG_1_INT_MAP - NA - 0 - 6 - read-write - - - - - LP_ANAPERI_INT_MAP - NA - 0x20 - 0x20 - - - CORE0_LP_ANAPERI_INT_MAP - NA - 0 - 6 - read-write - - - - - LP_ADC_INT_MAP - NA - 0x24 - 0x20 - - - CORE0_LP_ADC_INT_MAP - NA - 0 - 6 - read-write - - - - - LP_GPIO_INT_MAP - NA - 0x28 - 0x20 - - - CORE0_LP_GPIO_INT_MAP - NA - 0 - 6 - read-write - - - - - LP_I2C_INT_MAP - NA - 0x2C - 0x20 - - - CORE0_LP_I2C_INT_MAP - NA - 0 - 6 - read-write - - - - - LP_I2S_INT_MAP - NA - 0x30 - 0x20 - - - CORE0_LP_I2S_INT_MAP - NA - 0 - 6 - read-write - - - - - LP_SPI_INT_MAP - NA - 0x34 - 0x20 - - - CORE0_LP_SPI_INT_MAP - NA - 0 - 6 - read-write - - - - - LP_TOUCH_INT_MAP - NA - 0x38 - 0x20 - - - CORE0_LP_TOUCH_INT_MAP - NA - 0 - 6 - read-write - - - - - LP_TSENS_INT_MAP - NA - 0x3C - 0x20 - - - CORE0_LP_TSENS_INT_MAP - NA - 0 - 6 - read-write - - - - - LP_UART_INT_MAP - NA - 0x40 - 0x20 - - - CORE0_LP_UART_INT_MAP - NA - 0 - 6 - read-write - - - - - LP_EFUSE_INT_MAP - NA - 0x44 - 0x20 - - - CORE0_LP_EFUSE_INT_MAP - NA - 0 - 6 - read-write - - - - - LP_SW_INT_MAP - NA - 0x48 - 0x20 - - - CORE0_LP_SW_INT_MAP - NA - 0 - 6 - read-write - - - - - LP_SYSREG_INT_MAP - NA - 0x4C - 0x20 - - - CORE0_LP_SYSREG_INT_MAP - NA - 0 - 6 - read-write - - - - - LP_HUK_INT_MAP - NA - 0x50 - 0x20 - - - CORE0_LP_HUK_INT_MAP - NA - 0 - 6 - read-write - - - - - SYS_ICM_INT_MAP - NA - 0x54 - 0x20 - - - CORE0_SYS_ICM_INT_MAP - NA - 0 - 6 - read-write - - - - - USB_DEVICE_INT_MAP - NA - 0x58 - 0x20 - - - CORE0_USB_DEVICE_INT_MAP - NA - 0 - 6 - read-write - - - - - SDIO_HOST_INT_MAP - NA - 0x5C - 0x20 - - - CORE0_SDIO_HOST_INT_MAP - NA - 0 - 6 - read-write - - - - - GDMA_INT_MAP - NA - 0x60 - 0x20 - - - CORE0_GDMA_INT_MAP - NA - 0 - 6 - read-write - - - - - SPI2_INT_MAP - NA - 0x64 - 0x20 - - - CORE0_SPI2_INT_MAP - NA - 0 - 6 - read-write - - - - - SPI3_INT_MAP - NA - 0x68 - 0x20 - - - CORE0_SPI3_INT_MAP - NA - 0 - 6 - read-write - - - - - I2S0_INT_MAP - NA - 0x6C - 0x20 - - - CORE0_I2S0_INT_MAP - NA - 0 - 6 - read-write - - - - - I2S1_INT_MAP - NA - 0x70 - 0x20 - - - CORE0_I2S1_INT_MAP - NA - 0 - 6 - read-write - - - - - I2S2_INT_MAP - NA - 0x74 - 0x20 - - - CORE0_I2S2_INT_MAP - NA - 0 - 6 - read-write - - - - - UHCI0_INT_MAP - NA - 0x78 - 0x20 - - - CORE0_UHCI0_INT_MAP - NA - 0 - 6 - read-write - - - - - UART0_INT_MAP - NA - 0x7C - 0x20 - - - CORE0_UART0_INT_MAP - NA - 0 - 6 - read-write - - - - - UART1_INT_MAP - NA - 0x80 - 0x20 - - - CORE0_UART1_INT_MAP - NA - 0 - 6 - read-write - - - - - UART2_INT_MAP - NA - 0x84 - 0x20 - - - CORE0_UART2_INT_MAP - NA - 0 - 6 - read-write - - - - - UART3_INT_MAP - NA - 0x88 - 0x20 - - - CORE0_UART3_INT_MAP - NA - 0 - 6 - read-write - - - - - UART4_INT_MAP - NA - 0x8C - 0x20 - - - CORE0_UART4_INT_MAP - NA - 0 - 6 - read-write - - - - - LCD_CAM_INT_MAP - NA - 0x90 - 0x20 - - - CORE0_LCD_CAM_INT_MAP - NA - 0 - 6 - read-write - - - - - ADC_INT_MAP - NA - 0x94 - 0x20 - - - CORE0_ADC_INT_MAP - NA - 0 - 6 - read-write - - - - - PWM0_INT_MAP - NA - 0x98 - 0x20 - - - CORE0_PWM0_INT_MAP - NA - 0 - 6 - read-write - - - - - PWM1_INT_MAP - NA - 0x9C - 0x20 - - - CORE0_PWM1_INT_MAP - NA - 0 - 6 - read-write - - - - - CAN0_INT_MAP - NA - 0xA0 - 0x20 - - - CORE0_CAN0_INT_MAP - NA - 0 - 6 - read-write - - - - - CAN1_INT_MAP - NA - 0xA4 - 0x20 - - - CORE0_CAN1_INT_MAP - NA - 0 - 6 - read-write - - - - - CAN2_INT_MAP - NA - 0xA8 - 0x20 - - - CORE0_CAN2_INT_MAP - NA - 0 - 6 - read-write - - - - - RMT_INT_MAP - NA - 0xAC - 0x20 - - - CORE0_RMT_INT_MAP - NA - 0 - 6 - read-write - - - - - I2C0_INT_MAP - NA - 0xB0 - 0x20 - - - CORE0_I2C0_INT_MAP - NA - 0 - 6 - read-write - - - - - I2C1_INT_MAP - NA - 0xB4 - 0x20 - - - CORE0_I2C1_INT_MAP - NA - 0 - 6 - read-write - - - - - TIMERGRP0_T0_INT_MAP - NA - 0xB8 - 0x20 - - - CORE0_TIMERGRP0_T0_INT_MAP - NA - 0 - 6 - read-write - - - - - TIMERGRP0_T1_INT_MAP - NA - 0xBC - 0x20 - - - CORE0_TIMERGRP0_T1_INT_MAP - NA - 0 - 6 - read-write - - - - - TIMERGRP0_WDT_INT_MAP - NA - 0xC0 - 0x20 - - - CORE0_TIMERGRP0_WDT_INT_MAP - NA - 0 - 6 - read-write - - - - - TIMERGRP1_T0_INT_MAP - NA - 0xC4 - 0x20 - - - CORE0_TIMERGRP1_T0_INT_MAP - NA - 0 - 6 - read-write - - - - - TIMERGRP1_T1_INT_MAP - NA - 0xC8 - 0x20 - - - CORE0_TIMERGRP1_T1_INT_MAP - NA - 0 - 6 - read-write - - - - - TIMERGRP1_WDT_INT_MAP - NA - 0xCC - 0x20 - - - CORE0_TIMERGRP1_WDT_INT_MAP - NA - 0 - 6 - read-write - - - - - LEDC_INT_MAP - NA - 0xD0 - 0x20 - - - CORE0_LEDC_INT_MAP - NA - 0 - 6 - read-write - - - - - SYSTIMER_TARGET0_INT_MAP - NA - 0xD4 - 0x20 - - - CORE0_SYSTIMER_TARGET0_INT_MAP - NA - 0 - 6 - read-write - - - - - SYSTIMER_TARGET1_INT_MAP - NA - 0xD8 - 0x20 - - - CORE0_SYSTIMER_TARGET1_INT_MAP - NA - 0 - 6 - read-write - - - - - SYSTIMER_TARGET2_INT_MAP - NA - 0xDC - 0x20 - - - CORE0_SYSTIMER_TARGET2_INT_MAP - NA - 0 - 6 - read-write - - - - - AHB_PDMA_IN_CH0_INT_MAP - NA - 0xE0 - 0x20 - - - CORE0_AHB_PDMA_IN_CH0_INT_MAP - NA - 0 - 6 - read-write - - - - - AHB_PDMA_IN_CH1_INT_MAP - NA - 0xE4 - 0x20 - - - CORE0_AHB_PDMA_IN_CH1_INT_MAP - NA - 0 - 6 - read-write - - - - - AHB_PDMA_IN_CH2_INT_MAP - NA - 0xE8 - 0x20 - - - CORE0_AHB_PDMA_IN_CH2_INT_MAP - NA - 0 - 6 - read-write - - - - - AHB_PDMA_OUT_CH0_INT_MAP - NA - 0xEC - 0x20 - - - CORE0_AHB_PDMA_OUT_CH0_INT_MAP - NA - 0 - 6 - read-write - - - - - AHB_PDMA_OUT_CH1_INT_MAP - NA - 0xF0 - 0x20 - - - CORE0_AHB_PDMA_OUT_CH1_INT_MAP - NA - 0 - 6 - read-write - - - - - AHB_PDMA_OUT_CH2_INT_MAP - NA - 0xF4 - 0x20 - - - CORE0_AHB_PDMA_OUT_CH2_INT_MAP - NA - 0 - 6 - read-write - - - - - AXI_PDMA_IN_CH0_INT_MAP - NA - 0xF8 - 0x20 - - - CORE0_AXI_PDMA_IN_CH0_INT_MAP - NA - 0 - 6 - read-write - - - - - AXI_PDMA_IN_CH1_INT_MAP - NA - 0xFC - 0x20 - - - CORE0_AXI_PDMA_IN_CH1_INT_MAP - NA - 0 - 6 - read-write - - - - - AXI_PDMA_IN_CH2_INT_MAP - NA - 0x100 - 0x20 - - - CORE0_AXI_PDMA_IN_CH2_INT_MAP - NA - 0 - 6 - read-write - - - - - AXI_PDMA_OUT_CH0_INT_MAP - NA - 0x104 - 0x20 - - - CORE0_AXI_PDMA_OUT_CH0_INT_MAP - NA - 0 - 6 - read-write - - - - - AXI_PDMA_OUT_CH1_INT_MAP - NA - 0x108 - 0x20 - - - CORE0_AXI_PDMA_OUT_CH1_INT_MAP - NA - 0 - 6 - read-write - - - - - AXI_PDMA_OUT_CH2_INT_MAP - NA - 0x10C - 0x20 - - - CORE0_AXI_PDMA_OUT_CH2_INT_MAP - NA - 0 - 6 - read-write - - - - - RSA_INT_MAP - NA - 0x110 - 0x20 - - - CORE0_RSA_INT_MAP - NA - 0 - 6 - read-write - - - - - AES_INT_MAP - NA - 0x114 - 0x20 - - - CORE0_AES_INT_MAP - NA - 0 - 6 - read-write - - - - - SHA_INT_MAP - NA - 0x118 - 0x20 - - - CORE0_SHA_INT_MAP - NA - 0 - 6 - read-write - - - - - ECC_INT_MAP - NA - 0x11C - 0x20 - - - CORE0_ECC_INT_MAP - NA - 0 - 6 - read-write - - - - - ECDSA_INT_MAP - NA - 0x120 - 0x20 - - - CORE0_ECDSA_INT_MAP - NA - 0 - 6 - read-write - - - - - KM_INT_MAP - NA - 0x124 - 0x20 - - - CORE0_KM_INT_MAP - NA - 0 - 6 - read-write - - - - - GPIO_INT0_MAP - NA - 0x128 - 0x20 - - - CORE0_GPIO_INT0_MAP - NA - 0 - 6 - read-write - - - - - GPIO_INT1_MAP - NA - 0x12C - 0x20 - - - CORE0_GPIO_INT1_MAP - NA - 0 - 6 - read-write - - - - - GPIO_INT2_MAP - NA - 0x130 - 0x20 - - - CORE0_GPIO_INT2_MAP - NA - 0 - 6 - read-write - - - - - GPIO_INT3_MAP - NA - 0x134 - 0x20 - - - CORE0_GPIO_INT3_MAP - NA - 0 - 6 - read-write - - - - - GPIO_PAD_COMP_INT_MAP - NA - 0x138 - 0x20 - - - CORE0_GPIO_PAD_COMP_INT_MAP - NA - 0 - 6 - read-write - - - - - CPU_INT_FROM_CPU_0_MAP - NA - 0x13C - 0x20 - - - CORE0_CPU_INT_FROM_CPU_0_MAP - NA - 0 - 6 - read-write - - - - - CPU_INT_FROM_CPU_1_MAP - NA - 0x140 - 0x20 - - - CORE0_CPU_INT_FROM_CPU_1_MAP - NA - 0 - 6 - read-write - - - - - CPU_INT_FROM_CPU_2_MAP - NA - 0x144 - 0x20 - - - CORE0_CPU_INT_FROM_CPU_2_MAP - NA - 0 - 6 - read-write - - - - - CPU_INT_FROM_CPU_3_MAP - NA - 0x148 - 0x20 - - - CORE0_CPU_INT_FROM_CPU_3_MAP - NA - 0 - 6 - read-write - - - - - CACHE_INT_MAP - NA - 0x14C - 0x20 - - - CORE0_CACHE_INT_MAP - NA - 0 - 6 - read-write - - - - - FLASH_MSPI_INT_MAP - NA - 0x150 - 0x20 - - - CORE0_FLASH_MSPI_INT_MAP - NA - 0 - 6 - read-write - - - - - CSI_BRIDGE_INT_MAP - NA - 0x154 - 0x20 - - - CORE0_CSI_BRIDGE_INT_MAP - NA - 0 - 6 - read-write - - - - - DSI_BRIDGE_INT_MAP - NA - 0x158 - 0x20 - - - CORE0_DSI_BRIDGE_INT_MAP - NA - 0 - 6 - read-write - - - - - CSI_INT_MAP - NA - 0x15C - 0x20 - - - CORE0_CSI_INT_MAP - NA - 0 - 6 - read-write - - - - - DSI_INT_MAP - NA - 0x160 - 0x20 - - - CORE0_DSI_INT_MAP - NA - 0 - 6 - read-write - - - - - GMII_PHY_INT_MAP - NA - 0x164 - 0x20 - - - CORE0_GMII_PHY_INT_MAP - NA - 0 - 6 - read-write - - - - - LPI_INT_MAP - NA - 0x168 - 0x20 - - - CORE0_LPI_INT_MAP - NA - 0 - 6 - read-write - - - - - PMT_INT_MAP - NA - 0x16C - 0x20 - - - CORE0_PMT_INT_MAP - NA - 0 - 6 - read-write - - - - - SBD_INT_MAP - NA - 0x170 - 0x20 - - - CORE0_SBD_INT_MAP - NA - 0 - 6 - read-write - - - - - USB_OTG_INT_MAP - NA - 0x174 - 0x20 - - - CORE0_USB_OTG_INT_MAP - NA - 0 - 6 - read-write - - - - - USB_OTG_ENDP_MULTI_PROC_INT_MAP - NA - 0x178 - 0x20 - - - CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP - NA - 0 - 6 - read-write - - - - - JPEG_INT_MAP - NA - 0x17C - 0x20 - - - CORE0_JPEG_INT_MAP - NA - 0 - 6 - read-write - - - - - PPA_INT_MAP - NA - 0x180 - 0x20 - - - CORE0_PPA_INT_MAP - NA - 0 - 6 - read-write - - - - - CORE0_TRACE_INT_MAP - NA - 0x184 - 0x20 - - - CORE0_CORE0_TRACE_INT_MAP - NA - 0 - 6 - read-write - - - - - CORE1_TRACE_INT_MAP - NA - 0x188 - 0x20 - - - CORE0_CORE1_TRACE_INT_MAP - NA - 0 - 6 - read-write - - - - - HP_CORE_CTRL_INT_MAP - NA - 0x18C - 0x20 - - - CORE0_HP_CORE_CTRL_INT_MAP - NA - 0 - 6 - read-write - - - - - ISP_INT_MAP - NA - 0x190 - 0x20 - - - CORE0_ISP_INT_MAP - NA - 0 - 6 - read-write - - - - - I3C_MST_INT_MAP - NA - 0x194 - 0x20 - - - CORE0_I3C_MST_INT_MAP - NA - 0 - 6 - read-write - - - - - I3C_SLV_INT_MAP - NA - 0x198 - 0x20 - - - CORE0_I3C_SLV_INT_MAP - NA - 0 - 6 - read-write - - - - - USB_OTG11_INT_MAP - NA - 0x19C - 0x20 - - - CORE0_USB_OTG11_INT_MAP - NA - 0 - 6 - read-write - - - - - DMA2D_IN_CH0_INT_MAP - NA - 0x1A0 - 0x20 - - - CORE0_DMA2D_IN_CH0_INT_MAP - NA - 0 - 6 - read-write - - - - - DMA2D_IN_CH1_INT_MAP - NA - 0x1A4 - 0x20 - - - CORE0_DMA2D_IN_CH1_INT_MAP - NA - 0 - 6 - read-write - - - - - DMA2D_OUT_CH0_INT_MAP - NA - 0x1A8 - 0x20 - - - CORE0_DMA2D_OUT_CH0_INT_MAP - NA - 0 - 6 - read-write - - - - - DMA2D_OUT_CH1_INT_MAP - NA - 0x1AC - 0x20 - - - CORE0_DMA2D_OUT_CH1_INT_MAP - NA - 0 - 6 - read-write - - - - - DMA2D_OUT_CH2_INT_MAP - NA - 0x1B0 - 0x20 - - - CORE0_DMA2D_OUT_CH2_INT_MAP - NA - 0 - 6 - read-write - - - - - PSRAM_MSPI_INT_MAP - NA - 0x1B4 - 0x20 - - - CORE0_PSRAM_MSPI_INT_MAP - NA - 0 - 6 - read-write - - - - - HP_SYSREG_INT_MAP - NA - 0x1B8 - 0x20 - - - CORE0_HP_SYSREG_INT_MAP - NA - 0 - 6 - read-write - - - - - PCNT_INT_MAP - NA - 0x1BC - 0x20 - - - CORE0_PCNT_INT_MAP - NA - 0 - 6 - read-write - - - - - HP_PAU_INT_MAP - NA - 0x1C0 - 0x20 - - - CORE0_HP_PAU_INT_MAP - NA - 0 - 6 - read-write - - - - - HP_PARLIO_RX_INT_MAP - NA - 0x1C4 - 0x20 - - - CORE0_HP_PARLIO_RX_INT_MAP - NA - 0 - 6 - read-write - - - - - HP_PARLIO_TX_INT_MAP - NA - 0x1C8 - 0x20 - - - CORE0_HP_PARLIO_TX_INT_MAP - NA - 0 - 6 - read-write - - - - - H264_DMA2D_OUT_CH0_INT_MAP - NA - 0x1CC - 0x20 - - - CORE0_H264_DMA2D_OUT_CH0_INT_MAP - NA - 0 - 6 - read-write - - - - - H264_DMA2D_OUT_CH1_INT_MAP - NA - 0x1D0 - 0x20 - - - CORE0_H264_DMA2D_OUT_CH1_INT_MAP - NA - 0 - 6 - read-write - - - - - H264_DMA2D_OUT_CH2_INT_MAP - NA - 0x1D4 - 0x20 - - - CORE0_H264_DMA2D_OUT_CH2_INT_MAP - NA - 0 - 6 - read-write - - - - - H264_DMA2D_OUT_CH3_INT_MAP - NA - 0x1D8 - 0x20 - - - CORE0_H264_DMA2D_OUT_CH3_INT_MAP - NA - 0 - 6 - read-write - - - - - H264_DMA2D_OUT_CH4_INT_MAP - NA - 0x1DC - 0x20 - - - CORE0_H264_DMA2D_OUT_CH4_INT_MAP - NA - 0 - 6 - read-write - - - - - H264_DMA2D_IN_CH0_INT_MAP - NA - 0x1E0 - 0x20 - - - CORE0_H264_DMA2D_IN_CH0_INT_MAP - NA - 0 - 6 - read-write - - - - - H264_DMA2D_IN_CH1_INT_MAP - NA - 0x1E4 - 0x20 - - - CORE0_H264_DMA2D_IN_CH1_INT_MAP - NA - 0 - 6 - read-write - - - - - H264_DMA2D_IN_CH2_INT_MAP - NA - 0x1E8 - 0x20 - - - CORE0_H264_DMA2D_IN_CH2_INT_MAP - NA - 0 - 6 - read-write - - - - - H264_DMA2D_IN_CH3_INT_MAP - NA - 0x1EC - 0x20 - - - CORE0_H264_DMA2D_IN_CH3_INT_MAP - NA - 0 - 6 - read-write - - - - - H264_DMA2D_IN_CH4_INT_MAP - NA - 0x1F0 - 0x20 - - - CORE0_H264_DMA2D_IN_CH4_INT_MAP - NA - 0 - 6 - read-write - - - - - H264_DMA2D_IN_CH5_INT_MAP - NA - 0x1F4 - 0x20 - - - CORE0_H264_DMA2D_IN_CH5_INT_MAP - NA - 0 - 6 - read-write - - - - - H264_REG_INT_MAP - NA - 0x1F8 - 0x20 - - - CORE0_H264_REG_INT_MAP - NA - 0 - 6 - read-write - - - - - ASSIST_DEBUG_INT_MAP - NA - 0x1FC - 0x20 - - - CORE0_ASSIST_DEBUG_INT_MAP - NA - 0 - 6 - read-write - - - - - INTR_STATUS_REG_0 - NA - 0x200 - 0x20 - - - CORE0_INTR_STATUS_0 - NA - 0 - 32 - read-only - - - - - INTR_STATUS_REG_1 - NA - 0x204 - 0x20 - - - CORE0_INTR_STATUS_1 - NA - 0 - 32 - read-only - - - - - INTR_STATUS_REG_2 - NA - 0x208 - 0x20 - - - CORE0_INTR_STATUS_2 - NA - 0 - 32 - read-only - - - - - INTR_STATUS_REG_3 - NA - 0x20C - 0x20 - - - CORE0_INTR_STATUS_3 - NA - 0 - 32 - read-only - - - - - CLOCK_GATE - NA - 0x210 - 0x20 - 0x00000001 - - - CORE0_REG_CLK_EN - NA - 0 - 1 - read-write - - - - - INTERRUPT_REG_DATE - NA - 0x3FC - 0x20 - 0x02003020 - - - CORE0_INTERRUPT_REG_DATE - NA - 0 - 28 - read-write - - - - - - - INTERRUPT_CORE1 - Interrupt Controller (Core 1) - CORE1 - 0x500D6800 - - 0x0 - 0x218 - registers - - - - LP_RTC_INT_MAP - NA - 0x0 - 0x20 - - - CORE1_LP_RTC_INT_MAP - NA - 0 - 6 - read-write - - - - - LP_WDT_INT_MAP - NA - 0x4 - 0x20 - - - CORE1_LP_WDT_INT_MAP - NA - 0 - 6 - read-write - - - - - LP_TIMER_REG_0_INT_MAP - NA - 0x8 - 0x20 - - - CORE1_LP_TIMER_REG_0_INT_MAP - NA - 0 - 6 - read-write - - - - - LP_TIMER_REG_1_INT_MAP - NA - 0xC - 0x20 - - - CORE1_LP_TIMER_REG_1_INT_MAP - NA - 0 - 6 - read-write - - - - - MB_HP_INT_MAP - NA - 0x10 - 0x20 - - - CORE1_MB_HP_INT_MAP - NA - 0 - 6 - read-write - - - - - MB_LP_INT_MAP - NA - 0x14 - 0x20 - - - CORE1_MB_LP_INT_MAP - NA - 0 - 6 - read-write - - - - - PMU_REG_0_INT_MAP - NA - 0x18 - 0x20 - - - CORE1_PMU_REG_0_INT_MAP - NA - 0 - 6 - read-write - - - - - PMU_REG_1_INT_MAP - NA - 0x1C - 0x20 - - - CORE1_PMU_REG_1_INT_MAP - NA - 0 - 6 - read-write - - - - - LP_ANAPERI_INT_MAP - NA - 0x20 - 0x20 - - - CORE1_LP_ANAPERI_INT_MAP - NA - 0 - 6 - read-write - - - - - LP_ADC_INT_MAP - NA - 0x24 - 0x20 - - - CORE1_LP_ADC_INT_MAP - NA - 0 - 6 - read-write - - - - - LP_GPIO_INT_MAP - NA - 0x28 - 0x20 - - - CORE1_LP_GPIO_INT_MAP - NA - 0 - 6 - read-write - - - - - LP_I2C_INT_MAP - NA - 0x2C - 0x20 - - - CORE1_LP_I2C_INT_MAP - NA - 0 - 6 - read-write - - - - - LP_I2S_INT_MAP - NA - 0x30 - 0x20 - - - CORE1_LP_I2S_INT_MAP - NA - 0 - 6 - read-write - - - - - LP_SPI_INT_MAP - NA - 0x34 - 0x20 - - - CORE1_LP_SPI_INT_MAP - NA - 0 - 6 - read-write - - - - - LP_TOUCH_INT_MAP - NA - 0x38 - 0x20 - - - CORE1_LP_TOUCH_INT_MAP - NA - 0 - 6 - read-write - - - - - LP_TSENS_INT_MAP - NA - 0x3C - 0x20 - - - CORE1_LP_TSENS_INT_MAP - NA - 0 - 6 - read-write - - - - - LP_UART_INT_MAP - NA - 0x40 - 0x20 - - - CORE1_LP_UART_INT_MAP - NA - 0 - 6 - read-write - - - - - LP_EFUSE_INT_MAP - NA - 0x44 - 0x20 - - - CORE1_LP_EFUSE_INT_MAP - NA - 0 - 6 - read-write - - - - - LP_SW_INT_MAP - NA - 0x48 - 0x20 - - - CORE1_LP_SW_INT_MAP - NA - 0 - 6 - read-write - - - - - LP_SYSREG_INT_MAP - NA - 0x4C - 0x20 - - - CORE1_LP_SYSREG_INT_MAP - NA - 0 - 6 - read-write - - - - - LP_HUK_INT_MAP - NA - 0x50 - 0x20 - - - CORE1_LP_HUK_INT_MAP - NA - 0 - 6 - read-write - - - - - SYS_ICM_INT_MAP - NA - 0x54 - 0x20 - - - CORE1_SYS_ICM_INT_MAP - NA - 0 - 6 - read-write - - - - - USB_DEVICE_INT_MAP - NA - 0x58 - 0x20 - - - CORE1_USB_DEVICE_INT_MAP - NA - 0 - 6 - read-write - - - - - SDIO_HOST_INT_MAP - NA - 0x5C - 0x20 - - - CORE1_SDIO_HOST_INT_MAP - NA - 0 - 6 - read-write - - - - - GDMA_INT_MAP - NA - 0x60 - 0x20 - - - CORE1_GDMA_INT_MAP - NA - 0 - 6 - read-write - - - - - SPI2_INT_MAP - NA - 0x64 - 0x20 - - - CORE1_SPI2_INT_MAP - NA - 0 - 6 - read-write - - - - - SPI3_INT_MAP - NA - 0x68 - 0x20 - - - CORE1_SPI3_INT_MAP - NA - 0 - 6 - read-write - - - - - I2S0_INT_MAP - NA - 0x6C - 0x20 - - - CORE1_I2S0_INT_MAP - NA - 0 - 6 - read-write - - - - - I2S1_INT_MAP - NA - 0x70 - 0x20 - - - CORE1_I2S1_INT_MAP - NA - 0 - 6 - read-write - - - - - I2S2_INT_MAP - NA - 0x74 - 0x20 - - - CORE1_I2S2_INT_MAP - NA - 0 - 6 - read-write - - - - - UHCI0_INT_MAP - NA - 0x78 - 0x20 - - - CORE1_UHCI0_INT_MAP - NA - 0 - 6 - read-write - - - - - UART0_INT_MAP - NA - 0x7C - 0x20 - - - CORE1_UART0_INT_MAP - NA - 0 - 6 - read-write - - - - - UART1_INT_MAP - NA - 0x80 - 0x20 - - - CORE1_UART1_INT_MAP - NA - 0 - 6 - read-write - - - - - UART2_INT_MAP - NA - 0x84 - 0x20 - - - CORE1_UART2_INT_MAP - NA - 0 - 6 - read-write - - - - - UART3_INT_MAP - NA - 0x88 - 0x20 - - - CORE1_UART3_INT_MAP - NA - 0 - 6 - read-write - - - - - UART4_INT_MAP - NA - 0x8C - 0x20 - - - CORE1_UART4_INT_MAP - NA - 0 - 6 - read-write - - - - - LCD_CAM_INT_MAP - NA - 0x90 - 0x20 - - - CORE1_LCD_CAM_INT_MAP - NA - 0 - 6 - read-write - - - - - ADC_INT_MAP - NA - 0x94 - 0x20 - - - CORE1_ADC_INT_MAP - NA - 0 - 6 - read-write - - - - - PWM0_INT_MAP - NA - 0x98 - 0x20 - - - CORE1_PWM0_INT_MAP - NA - 0 - 6 - read-write - - - - - PWM1_INT_MAP - NA - 0x9C - 0x20 - - - CORE1_PWM1_INT_MAP - NA - 0 - 6 - read-write - - - - - CAN0_INT_MAP - NA - 0xA0 - 0x20 - - - CORE1_CAN0_INT_MAP - NA - 0 - 6 - read-write - - - - - CAN1_INT_MAP - NA - 0xA4 - 0x20 - - - CORE1_CAN1_INT_MAP - NA - 0 - 6 - read-write - - - - - CAN2_INT_MAP - NA - 0xA8 - 0x20 - - - CORE1_CAN2_INT_MAP - NA - 0 - 6 - read-write - - - - - RMT_INT_MAP - NA - 0xAC - 0x20 - - - CORE1_RMT_INT_MAP - NA - 0 - 6 - read-write - - - - - I2C0_INT_MAP - NA - 0xB0 - 0x20 - - - CORE1_I2C0_INT_MAP - NA - 0 - 6 - read-write - - - - - I2C1_INT_MAP - NA - 0xB4 - 0x20 - - - CORE1_I2C1_INT_MAP - NA - 0 - 6 - read-write - - - - - TIMERGRP0_T0_INT_MAP - NA - 0xB8 - 0x20 - - - CORE1_TIMERGRP0_T0_INT_MAP - NA - 0 - 6 - read-write - - - - - TIMERGRP0_T1_INT_MAP - NA - 0xBC - 0x20 - - - CORE1_TIMERGRP0_T1_INT_MAP - NA - 0 - 6 - read-write - - - - - TIMERGRP0_WDT_INT_MAP - NA - 0xC0 - 0x20 - - - CORE1_TIMERGRP0_WDT_INT_MAP - NA - 0 - 6 - read-write - - - - - TIMERGRP1_T0_INT_MAP - NA - 0xC4 - 0x20 - - - CORE1_TIMERGRP1_T0_INT_MAP - NA - 0 - 6 - read-write - - - - - TIMERGRP1_T1_INT_MAP - NA - 0xC8 - 0x20 - - - CORE1_TIMERGRP1_T1_INT_MAP - NA - 0 - 6 - read-write - - - - - TIMERGRP1_WDT_INT_MAP - NA - 0xCC - 0x20 - - - CORE1_TIMERGRP1_WDT_INT_MAP - NA - 0 - 6 - read-write - - - - - LEDC_INT_MAP - NA - 0xD0 - 0x20 - - - CORE1_LEDC_INT_MAP - NA - 0 - 6 - read-write - - - - - SYSTIMER_TARGET0_INT_MAP - NA - 0xD4 - 0x20 - - - CORE1_SYSTIMER_TARGET0_INT_MAP - NA - 0 - 6 - read-write - - - - - SYSTIMER_TARGET1_INT_MAP - NA - 0xD8 - 0x20 - - - CORE1_SYSTIMER_TARGET1_INT_MAP - NA - 0 - 6 - read-write - - - - - SYSTIMER_TARGET2_INT_MAP - NA - 0xDC - 0x20 - - - CORE1_SYSTIMER_TARGET2_INT_MAP - NA - 0 - 6 - read-write - - - - - AHB_PDMA_IN_CH0_INT_MAP - NA - 0xE0 - 0x20 - - - CORE1_AHB_PDMA_IN_CH0_INT_MAP - NA - 0 - 6 - read-write - - - - - AHB_PDMA_IN_CH1_INT_MAP - NA - 0xE4 - 0x20 - - - CORE1_AHB_PDMA_IN_CH1_INT_MAP - NA - 0 - 6 - read-write - - - - - AHB_PDMA_IN_CH2_INT_MAP - NA - 0xE8 - 0x20 - - - CORE1_AHB_PDMA_IN_CH2_INT_MAP - NA - 0 - 6 - read-write - - - - - AHB_PDMA_OUT_CH0_INT_MAP - NA - 0xEC - 0x20 - - - CORE1_AHB_PDMA_OUT_CH0_INT_MAP - NA - 0 - 6 - read-write - - - - - AHB_PDMA_OUT_CH1_INT_MAP - NA - 0xF0 - 0x20 - - - CORE1_AHB_PDMA_OUT_CH1_INT_MAP - NA - 0 - 6 - read-write - - - - - AHB_PDMA_OUT_CH2_INT_MAP - NA - 0xF4 - 0x20 - - - CORE1_AHB_PDMA_OUT_CH2_INT_MAP - NA - 0 - 6 - read-write - - - - - AXI_PDMA_IN_CH0_INT_MAP - NA - 0xF8 - 0x20 - - - CORE1_AXI_PDMA_IN_CH0_INT_MAP - NA - 0 - 6 - read-write - - - - - AXI_PDMA_IN_CH1_INT_MAP - NA - 0xFC - 0x20 - - - CORE1_AXI_PDMA_IN_CH1_INT_MAP - NA - 0 - 6 - read-write - - - - - AXI_PDMA_IN_CH2_INT_MAP - NA - 0x100 - 0x20 - - - CORE1_AXI_PDMA_IN_CH2_INT_MAP - NA - 0 - 6 - read-write - - - - - AXI_PDMA_OUT_CH0_INT_MAP - NA - 0x104 - 0x20 - - - CORE1_AXI_PDMA_OUT_CH0_INT_MAP - NA - 0 - 6 - read-write - - - - - AXI_PDMA_OUT_CH1_INT_MAP - NA - 0x108 - 0x20 - - - CORE1_AXI_PDMA_OUT_CH1_INT_MAP - NA - 0 - 6 - read-write - - - - - AXI_PDMA_OUT_CH2_INT_MAP - NA - 0x10C - 0x20 - - - CORE1_AXI_PDMA_OUT_CH2_INT_MAP - NA - 0 - 6 - read-write - - - - - RSA_INT_MAP - NA - 0x110 - 0x20 - - - CORE1_RSA_INT_MAP - NA - 0 - 6 - read-write - - - - - AES_INT_MAP - NA - 0x114 - 0x20 - - - CORE1_AES_INT_MAP - NA - 0 - 6 - read-write - - - - - SHA_INT_MAP - NA - 0x118 - 0x20 - - - CORE1_SHA_INT_MAP - NA - 0 - 6 - read-write - - - - - ECC_INT_MAP - NA - 0x11C - 0x20 - - - CORE1_ECC_INT_MAP - NA - 0 - 6 - read-write - - - - - ECDSA_INT_MAP - NA - 0x120 - 0x20 - - - CORE1_ECDSA_INT_MAP - NA - 0 - 6 - read-write - - - - - KM_INT_MAP - NA - 0x124 - 0x20 - - - CORE1_KM_INT_MAP - NA - 0 - 6 - read-write - - - - - GPIO_INT0_MAP - NA - 0x128 - 0x20 - - - CORE1_GPIO_INT0_MAP - NA - 0 - 6 - read-write - - - - - GPIO_INT1_MAP - NA - 0x12C - 0x20 - - - CORE1_GPIO_INT1_MAP - NA - 0 - 6 - read-write - - - - - GPIO_INT2_MAP - NA - 0x130 - 0x20 - - - CORE1_GPIO_INT2_MAP - NA - 0 - 6 - read-write - - - - - GPIO_INT3_MAP - NA - 0x134 - 0x20 - - - CORE1_GPIO_INT3_MAP - NA - 0 - 6 - read-write - - - - - GPIO_PAD_COMP_INT_MAP - NA - 0x138 - 0x20 - - - CORE1_GPIO_PAD_COMP_INT_MAP - NA - 0 - 6 - read-write - - - - - CPU_INT_FROM_CPU_0_MAP - NA - 0x13C - 0x20 - - - CORE1_CPU_INT_FROM_CPU_0_MAP - NA - 0 - 6 - read-write - - - - - CPU_INT_FROM_CPU_1_MAP - NA - 0x140 - 0x20 - - - CORE1_CPU_INT_FROM_CPU_1_MAP - NA - 0 - 6 - read-write - - - - - CPU_INT_FROM_CPU_2_MAP - NA - 0x144 - 0x20 - - - CORE1_CPU_INT_FROM_CPU_2_MAP - NA - 0 - 6 - read-write - - - - - CPU_INT_FROM_CPU_3_MAP - NA - 0x148 - 0x20 - - - CORE1_CPU_INT_FROM_CPU_3_MAP - NA - 0 - 6 - read-write - - - - - CACHE_INT_MAP - NA - 0x14C - 0x20 - - - CORE1_CACHE_INT_MAP - NA - 0 - 6 - read-write - - - - - FLASH_MSPI_INT_MAP - NA - 0x150 - 0x20 - - - CORE1_FLASH_MSPI_INT_MAP - NA - 0 - 6 - read-write - - - - - CSI_BRIDGE_INT_MAP - NA - 0x154 - 0x20 - - - CORE1_CSI_BRIDGE_INT_MAP - NA - 0 - 6 - read-write - - - - - DSI_BRIDGE_INT_MAP - NA - 0x158 - 0x20 - - - CORE1_DSI_BRIDGE_INT_MAP - NA - 0 - 6 - read-write - - - - - CSI_INT_MAP - NA - 0x15C - 0x20 - - - CORE1_CSI_INT_MAP - NA - 0 - 6 - read-write - - - - - DSI_INT_MAP - NA - 0x160 - 0x20 - - - CORE1_DSI_INT_MAP - NA - 0 - 6 - read-write - - - - - GMII_PHY_INT_MAP - NA - 0x164 - 0x20 - - - CORE1_GMII_PHY_INT_MAP - NA - 0 - 6 - read-write - - - - - LPI_INT_MAP - NA - 0x168 - 0x20 - - - CORE1_LPI_INT_MAP - NA - 0 - 6 - read-write - - - - - PMT_INT_MAP - NA - 0x16C - 0x20 - - - CORE1_PMT_INT_MAP - NA - 0 - 6 - read-write - - - - - SBD_INT_MAP - NA - 0x170 - 0x20 - - - CORE1_SBD_INT_MAP - NA - 0 - 6 - read-write - - - - - USB_OTG_INT_MAP - NA - 0x174 - 0x20 - - - CORE1_USB_OTG_INT_MAP - NA - 0 - 6 - read-write - - - - - USB_OTG_ENDP_MULTI_PROC_INT_MAP - NA - 0x178 - 0x20 - - - CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP - NA - 0 - 6 - read-write - - - - - JPEG_INT_MAP - NA - 0x17C - 0x20 - - - CORE1_JPEG_INT_MAP - NA - 0 - 6 - read-write - - - - - PPA_INT_MAP - NA - 0x180 - 0x20 - - - CORE1_PPA_INT_MAP - NA - 0 - 6 - read-write - - - - - CORE0_TRACE_INT_MAP - NA - 0x184 - 0x20 - - - CORE1_CORE0_TRACE_INT_MAP - NA - 0 - 6 - read-write - - - - - CORE1_TRACE_INT_MAP - NA - 0x188 - 0x20 - - - CORE1_CORE1_TRACE_INT_MAP - NA - 0 - 6 - read-write - - - - - HP_CORE_CTRL_INT_MAP - NA - 0x18C - 0x20 - - - CORE1_HP_CORE_CTRL_INT_MAP - NA - 0 - 6 - read-write - - - - - ISP_INT_MAP - NA - 0x190 - 0x20 - - - CORE1_ISP_INT_MAP - NA - 0 - 6 - read-write - - - - - I3C_MST_INT_MAP - NA - 0x194 - 0x20 - - - CORE1_I3C_MST_INT_MAP - NA - 0 - 6 - read-write - - - - - I3C_SLV_INT_MAP - NA - 0x198 - 0x20 - - - CORE1_I3C_SLV_INT_MAP - NA - 0 - 6 - read-write - - - - - USB_OTG11_INT_MAP - NA - 0x19C - 0x20 - - - CORE1_USB_OTG11_INT_MAP - NA - 0 - 6 - read-write - - - - - DMA2D_IN_CH0_INT_MAP - NA - 0x1A0 - 0x20 - - - CORE1_DMA2D_IN_CH0_INT_MAP - NA - 0 - 6 - read-write - - - - - DMA2D_IN_CH1_INT_MAP - NA - 0x1A4 - 0x20 - - - CORE1_DMA2D_IN_CH1_INT_MAP - NA - 0 - 6 - read-write - - - - - DMA2D_OUT_CH0_INT_MAP - NA - 0x1A8 - 0x20 - - - CORE1_DMA2D_OUT_CH0_INT_MAP - NA - 0 - 6 - read-write - - - - - DMA2D_OUT_CH1_INT_MAP - NA - 0x1AC - 0x20 - - - CORE1_DMA2D_OUT_CH1_INT_MAP - NA - 0 - 6 - read-write - - - - - DMA2D_OUT_CH2_INT_MAP - NA - 0x1B0 - 0x20 - - - CORE1_DMA2D_OUT_CH2_INT_MAP - NA - 0 - 6 - read-write - - - - - PSRAM_MSPI_INT_MAP - NA - 0x1B4 - 0x20 - - - CORE1_PSRAM_MSPI_INT_MAP - NA - 0 - 6 - read-write - - - - - HP_SYSREG_INT_MAP - NA - 0x1B8 - 0x20 - - - CORE1_HP_SYSREG_INT_MAP - NA - 0 - 6 - read-write - - - - - PCNT_INT_MAP - NA - 0x1BC - 0x20 - - - CORE1_PCNT_INT_MAP - NA - 0 - 6 - read-write - - - - - HP_PAU_INT_MAP - NA - 0x1C0 - 0x20 - - - CORE1_HP_PAU_INT_MAP - NA - 0 - 6 - read-write - - - - - HP_PARLIO_RX_INT_MAP - NA - 0x1C4 - 0x20 - - - CORE1_HP_PARLIO_RX_INT_MAP - NA - 0 - 6 - read-write - - - - - HP_PARLIO_TX_INT_MAP - NA - 0x1C8 - 0x20 - - - CORE1_HP_PARLIO_TX_INT_MAP - NA - 0 - 6 - read-write - - - - - H264_DMA2D_OUT_CH0_INT_MAP - NA - 0x1CC - 0x20 - - - CORE1_H264_DMA2D_OUT_CH0_INT_MAP - NA - 0 - 6 - read-write - - - - - H264_DMA2D_OUT_CH1_INT_MAP - NA - 0x1D0 - 0x20 - - - CORE1_H264_DMA2D_OUT_CH1_INT_MAP - NA - 0 - 6 - read-write - - - - - H264_DMA2D_OUT_CH2_INT_MAP - NA - 0x1D4 - 0x20 - - - CORE1_H264_DMA2D_OUT_CH2_INT_MAP - NA - 0 - 6 - read-write - - - - - H264_DMA2D_OUT_CH3_INT_MAP - NA - 0x1D8 - 0x20 - - - CORE1_H264_DMA2D_OUT_CH3_INT_MAP - NA - 0 - 6 - read-write - - - - - H264_DMA2D_OUT_CH4_INT_MAP - NA - 0x1DC - 0x20 - - - CORE1_H264_DMA2D_OUT_CH4_INT_MAP - NA - 0 - 6 - read-write - - - - - H264_DMA2D_IN_CH0_INT_MAP - NA - 0x1E0 - 0x20 - - - CORE1_H264_DMA2D_IN_CH0_INT_MAP - NA - 0 - 6 - read-write - - - - - H264_DMA2D_IN_CH1_INT_MAP - NA - 0x1E4 - 0x20 - - - CORE1_H264_DMA2D_IN_CH1_INT_MAP - NA - 0 - 6 - read-write - - - - - H264_DMA2D_IN_CH2_INT_MAP - NA - 0x1E8 - 0x20 - - - CORE1_H264_DMA2D_IN_CH2_INT_MAP - NA - 0 - 6 - read-write - - - - - H264_DMA2D_IN_CH3_INT_MAP - NA - 0x1EC - 0x20 - - - CORE1_H264_DMA2D_IN_CH3_INT_MAP - NA - 0 - 6 - read-write - - - - - H264_DMA2D_IN_CH4_INT_MAP - NA - 0x1F0 - 0x20 - - - CORE1_H264_DMA2D_IN_CH4_INT_MAP - NA - 0 - 6 - read-write - - - - - H264_DMA2D_IN_CH5_INT_MAP - NA - 0x1F4 - 0x20 - - - CORE1_H264_DMA2D_IN_CH5_INT_MAP - NA - 0 - 6 - read-write - - - - - H264_REG_INT_MAP - NA - 0x1F8 - 0x20 - - - CORE1_H264_REG_INT_MAP - NA - 0 - 6 - read-write - - - - - ASSIST_DEBUG_INT_MAP - NA - 0x1FC - 0x20 - - - CORE1_ASSIST_DEBUG_INT_MAP - NA - 0 - 6 - read-write - - - - - INTR_STATUS_REG_0 - NA - 0x200 - 0x20 - - - CORE1_INTR_STATUS_0 - NA - 0 - 32 - read-only - - - - - INTR_STATUS_REG_1 - NA - 0x204 - 0x20 - - - CORE1_INTR_STATUS_1 - NA - 0 - 32 - read-only - - - - - INTR_STATUS_REG_2 - NA - 0x208 - 0x20 - - - CORE1_INTR_STATUS_2 - NA - 0 - 32 - read-only - - - - - INTR_STATUS_REG_3 - NA - 0x20C - 0x20 - - - CORE1_INTR_STATUS_3 - NA - 0 - 32 - read-only - - - - - CLOCK_GATE - NA - 0x210 - 0x20 - 0x00000001 - - - CORE1_REG_CLK_EN - NA - 0 - 1 - read-write - - - - - INTERRUPT_REG_DATE - NA - 0x3FC - 0x20 - 0x02003020 - - - CORE1_INTERRUPT_REG_DATE - NA - 0 - 28 - read-write - - - - - - - MIPI_CSI_BRIDGE - MIPI Camera Interface Bridge - CSI_BRIG - 0x5009F800 - - 0x0 - 0x48 - registers - - - CSI_BRIDGE - 85 - - - - CLK_EN - csi bridge register mapping unit clock gating. - 0x0 - 0x20 - - - CLK_EN - 0: enable clock gating. 1: disable clock gating, clock always on. - 0 - 1 - read-write - - - - - CSI_EN - csi bridge enable. - 0x4 - 0x20 - - - CSI_BRIG_EN - 0: disable csi bridge. 1: enable csi bridge. - 0 - 1 - read-write - - - - - DMA_REQ_CFG - dma request configuration. - 0x8 - 0x20 - 0x00000080 - - - DMA_BURST_LEN - DMA burst length. - 0 - 12 - read-write - - - DMA_CFG_UPD_BY_BLK - 1: reg_dma_burst_len & reg_dma_burst_len will be updated by dma block finish. 0: updated by frame. - 12 - 1 - read-write - - - DMA_FORCE_RD_STATUS - 1: mask dma request when reading frame info. 0: disable mask. - 16 - 1 - read-write - - - - - BUF_FLOW_CTL - csi bridge buffer control. - 0xC - 0x20 - 0x000007F8 - - - CSI_BUF_AFULL_THRD - buffer almost full threshold. - 0 - 14 - read-write - - - CSI_BUF_DEPTH - buffer data count. - 16 - 14 - read-only - - - - - DATA_TYPE_CFG - pixel data type configuration. - 0x10 - 0x20 - 0x00002F18 - - - DATA_TYPE_MIN - the min value of data type used for pixel filter. - 0 - 6 - read-write - - - DATA_TYPE_MAX - the max value of data type used for pixel filter. - 8 - 6 - read-write - - - - - FRAME_CFG - frame configuration. - 0x14 - 0x20 - 0x011E01E0 - - - VADR_NUM - vadr of frame data. - 0 - 12 - read-write - - - HADR_NUM - hadr of frame data. - 12 - 12 - read-write - - - HAS_HSYNC_E - 0: frame data doesn't contain hsync. 1: frame data contains hsync. - 24 - 1 - read-write - - - VADR_NUM_CHECK - 0: disable vadr check. 1: enable vadr check. - 25 - 1 - read-write - - - - - ENDIAN_MODE - data endianness order configuration. - 0x18 - 0x20 - - - BYTE_ENDIAN_ORDER - endianness order in bytes. 2'h0 is normal mode and 2'h3 is useful to YUV420(Legacy) when isp is bapassed. - 0 - 1 - read-write - - - BIT_ENDIAN_ORDER - N/A - 1 - 1 - read-write - - - - - INT_RAW - csi bridge interrupt raw. - 0x1C - 0x20 - - - VADR_NUM_GT_INT_RAW - reg_vadr_num is greater than real interrupt raw. - 0 - 1 - read-write - - - VADR_NUM_LT_INT_RAW - reg_vadr_num is less than real interrupt raw. - 1 - 1 - read-write - - - DISCARD_INT_RAW - an incomplete frame of data was sent interrupt raw. - 2 - 1 - read-write - - - CSI_BUF_OVERRUN_INT_RAW - buffer overrun interrupt raw. - 3 - 1 - read-write - - - CSI_ASYNC_FIFO_OVF_INT_RAW - buffer overflow interrupt raw. - 4 - 1 - read-write - - - DMA_CFG_HAS_UPDATED_INT_RAW - dma configuration update complete interrupt raw. - 5 - 1 - read-write - - - - - INT_CLR - csi bridge interrupt clr. - 0x20 - 0x20 - - - VADR_NUM_GT_REAL_INT_CLR - reg_vadr_num is greater than real interrupt clr. - 0 - 1 - write-only - - - VADR_NUM_LT_REAL_INT_CLR - reg_vadr_num is less than real interrupt clr. - 1 - 1 - write-only - - - DISCARD_INT_CLR - an incomplete frame of data was sent interrupt clr. - 2 - 1 - write-only - - - CSI_BUF_OVERRUN_INT_CLR - buffer overrun interrupt clr. - 3 - 1 - write-only - - - CSI_ASYNC_FIFO_OVF_INT_CLR - buffer overflow interrupt clr. - 4 - 1 - write-only - - - DMA_CFG_HAS_UPDATED_INT_CLR - dma configuration update complete interrupt clr. - 5 - 1 - write-only - - - - - INT_ST - csi bridge interrupt st. - 0x24 - 0x20 - - - VADR_NUM_GT_INT_ST - reg_vadr_num is greater than real interrupt st. - 0 - 1 - read-only - - - VADR_NUM_LT_INT_ST - reg_vadr_num is less than real interrupt st. - 1 - 1 - read-only - - - DISCARD_INT_ST - an incomplete frame of data was sent interrupt st. - 2 - 1 - read-only - - - CSI_BUF_OVERRUN_INT_ST - buffer overrun interrupt st. - 3 - 1 - read-only - - - CSI_ASYNC_FIFO_OVF_INT_ST - buffer overflow interrupt st. - 4 - 1 - read-only - - - DMA_CFG_HAS_UPDATED_INT_ST - dma configuration update complete interrupt st. - 5 - 1 - read-only - - - - - INT_ENA - csi bridge interrupt enable. - 0x28 - 0x20 - - - VADR_NUM_GT_INT_ENA - reg_vadr_num is greater than real interrupt enable. - 0 - 1 - read-write - - - VADR_NUM_LT_INT_ENA - reg_vadr_num is less than real interrupt enable. - 1 - 1 - read-write - - - DISCARD_INT_ENA - an incomplete frame of data was sent interrupt enable. - 2 - 1 - read-write - - - CSI_BUF_OVERRUN_INT_ENA - buffer overrun interrupt enable. - 3 - 1 - read-write - - - CSI_ASYNC_FIFO_OVF_INT_ENA - buffer overflow interrupt enable. - 4 - 1 - read-write - - - DMA_CFG_HAS_UPDATED_INT_ENA - dma configuration update complete interrupt enable. - 5 - 1 - read-write - - - - - DMA_REQ_INTERVAL - DMA interval configuration. - 0x2C - 0x20 - 0x00000001 - - - DMA_REQ_INTERVAL - 16'b1: 1 cycle. 16'b11: 2 cycle. ... ... 16'hFFFF: 16 cycle. - 0 - 16 - read-write - - - - - DMABLK_SIZE - DMA block size configuration. - 0x30 - 0x20 - 0x00001FFF - - - DMABLK_SIZE - the number of reg_dma_burst_len in a block - 0 - 13 - read-write - - - - - RDN_ECO_CS - N/A - 0x34 - 0x20 - - - RDN_ECO_EN - N/A - 0 - 1 - read-write - - - RDN_ECO_RESULT - N/A - 1 - 1 - read-only - - - - - RDN_ECO_LOW - N/A - 0x38 - 0x20 - - - RDN_ECO_LOW - N/A - 0 - 32 - read-write - - - - - RDN_ECO_HIGH - N/A - 0x3C - 0x20 - 0xFFFFFFFF - - - RDN_ECO_HIGH - N/A - 0 - 32 - read-write - - - - - HOST_CTRL - csi host control by csi bridge. - 0x40 - 0x20 - 0x00000003 - - - CSI_ENABLECLK - enable clock lane module of csi phy. - 0 - 1 - read-write - - - CSI_CFG_CLK_EN - enable cfg_clk of csi host module. - 1 - 1 - read-write - - - LOOPBK_TEST_EN - for phy test by loopback dsi phy to csi phy. - 2 - 1 - read-write - - - - - MEM_CTRL - csi bridge buffer control. - 0x44 - 0x20 - 0x00002640 - - - CSI_BRIDGE_MEM_CLK_FORCE_ON - csi bridge memory clock gating force on. - 0 - 1 - read-write - - - CSI_MEM_AUX_CTRL - N/A - 1 - 14 - read-write - - - - - - - MIPI_CSI_HOST - MIPI Camera Interface Host - CSI_HOST - 0x5009F000 - - 0x0 - 0xA8 - registers - - - CSI - 87 - - - - VERSION - NA - 0x0 - 0x20 - 0x3135302A - - - VERSION - NA - 0 - 32 - read-only - - - - - N_LANES - NA - 0x4 - 0x20 - 0x00000001 - - - N_LANES - NA - 0 - 3 - read-write - - - - - CSI2_RESETN - NA - 0x8 - 0x20 - - - CSI2_RESETN - NA - 0 - 1 - read-write - - - - - INT_ST_MAIN - NA - 0xC - 0x20 - - - ST_STATUS_INT_PHY_FATAL - NA - 0 - 1 - read-only - - - ST_STATUS_INT_PKT_FATAL - NA - 1 - 1 - read-only - - - ST_STATUS_INT_BNDRY_FRAME_FATAL - NA - 2 - 1 - read-only - - - ST_STATUS_INT_SEQ_FRAME_FATAL - NA - 3 - 1 - read-only - - - ST_STATUS_INT_CRC_FRAME_FATAL - NA - 4 - 1 - read-only - - - ST_STATUS_INT_PLD_CRC_FATAL - NA - 5 - 1 - read-only - - - ST_STATUS_INT_DATA_ID - NA - 6 - 1 - read-only - - - ST_STATUS_INT_ECC_CORRECTED - NA - 7 - 1 - read-only - - - ST_STATUS_INT_PHY - NA - 16 - 1 - read-only - - - - - PHY_SHUTDOWNZ - NA - 0x40 - 0x20 - - - PHY_SHUTDOWNZ - NA - 0 - 1 - read-write - - - - - DPHY_RSTZ - NA - 0x44 - 0x20 - - - DPHY_RSTZ - NA - 0 - 1 - read-write - - - - - PHY_RX - NA - 0x48 - 0x20 - 0x00010000 - - - PHY_RXULPSESC_0 - NA - 0 - 1 - read-only - - - PHY_RXULPSESC_1 - NA - 1 - 1 - read-only - - - PHY_RXULPSCLKNOT - NA - 16 - 1 - read-only - - - PHY_RXCLKACTIVEHS - NA - 17 - 1 - read-only - - - - - PHY_STOPSTATE - NA - 0x4C - 0x20 - - - PHY_STOPSTATEDATA_0 - NA - 0 - 1 - read-only - - - PHY_STOPSTATEDATA_1 - NA - 1 - 1 - read-only - - - PHY_STOPSTATECLK - NA - 16 - 1 - read-only - - - - - PHY_TEST_CTRL0 - NA - 0x50 - 0x20 - 0x00000001 - - - PHY_TESTCLR - NA - 0 - 1 - read-write - - - PHY_TESTCLK - NA - 1 - 1 - read-write - - - - - PHY_TEST_CTRL1 - NA - 0x54 - 0x20 - - - PHY_TESTDIN - NA - 0 - 8 - read-write - - - PHY_TESTDOUT - NA - 8 - 8 - read-only - - - PHY_TESTEN - NA - 16 - 1 - read-write - - - - - VC_EXTENSION - NA - 0xC8 - 0x20 - - - VCX - NA - 0 - 1 - read-write - - - - - PHY_CAL - NA - 0xCC - 0x20 - - - RXSKEWCALHS - NA - 0 - 1 - read-only - - - - - INT_ST_PHY_FATAL - NA - 0xE0 - 0x20 - - - ST_PHY_ERRSOTSYNCHS_0 - NA - 0 - 1 - read-only - - - ST_PHY_ERRSOTSYNCHS_1 - NA - 1 - 1 - read-only - - - - - INT_MSK_PHY_FATAL - NA - 0xE4 - 0x20 - - - MASK_PHY_ERRSOTSYNCHS_0 - NA - 0 - 1 - read-write - - - MASK_PHY_ERRSOTSYNCHS_1 - NA - 1 - 1 - read-write - - - - - INT_FORCE_PHY_FATAL - NA - 0xE8 - 0x20 - - - FORCE_PHY_ERRSOTSYNCHS_0 - NA - 0 - 1 - read-write - - - FORCE_PHY_ERRSOTSYNCHS_1 - NA - 1 - 1 - read-write - - - - - INT_ST_PKT_FATAL - NA - 0xF0 - 0x20 - - - ST_ERR_ECC_DOUBLE - NA - 0 - 1 - read-only - - - ST_SHORTER_PAYLOAD - NA - 1 - 1 - read-only - - - - - INT_MSK_PKT_FATAL - NA - 0xF4 - 0x20 - - - MASK_ERR_ECC_DOUBLE - NA - 0 - 1 - read-write - - - MASK_SHORTER_PAYLOAD - NA - 1 - 1 - read-write - - - - - INT_FORCE_PKT_FATAL - NA - 0xF8 - 0x20 - - - FORCE_ERR_ECC_DOUBLE - NA - 0 - 1 - read-write - - - FORCE_SHORTER_PAYLOAD - NA - 1 - 1 - read-write - - - - - INT_ST_PHY - NA - 0x110 - 0x20 - - - ST_PHY_ERRSOTHS_0 - NA - 0 - 1 - read-only - - - ST_PHY_ERRSOTHS_1 - NA - 1 - 1 - read-only - - - ST_PHY_ERRESC_0 - NA - 16 - 1 - read-only - - - ST_PHY_ERRESC_1 - NA - 17 - 1 - read-only - - - - - INT_MSK_PHY - NA - 0x114 - 0x20 - - - MASK_PHY_ERRSOTHS_0 - NA - 0 - 1 - read-write - - - MASK_PHY_ERRSOTHS_1 - NA - 1 - 1 - read-write - - - MASK_PHY_ERRESC_0 - NA - 16 - 1 - read-write - - - MASK_PHY_ERRESC_1 - NA - 17 - 1 - read-write - - - - - INT_FORCE_PHY - NA - 0x118 - 0x20 - - - FORCE_PHY_ERRSOTHS_0 - NA - 0 - 1 - read-write - - - FORCE_PHY_ERRSOTHS_1 - NA - 1 - 1 - read-write - - - FORCE_PHY_ERRESC_0 - NA - 16 - 1 - read-write - - - FORCE_PHY_ERRESC_1 - NA - 17 - 1 - read-write - - - - - INT_ST_BNDRY_FRAME_FATAL - NA - 0x280 - 0x20 - - - ST_ERR_F_BNDRY_MATCH_VC0 - NA - 0 - 1 - read-only - - - ST_ERR_F_BNDRY_MATCH_VC1 - NA - 1 - 1 - read-only - - - ST_ERR_F_BNDRY_MATCH_VC2 - NA - 2 - 1 - read-only - - - ST_ERR_F_BNDRY_MATCH_VC3 - NA - 3 - 1 - read-only - - - ST_ERR_F_BNDRY_MATCH_VC4 - NA - 4 - 1 - read-only - - - ST_ERR_F_BNDRY_MATCH_VC5 - NA - 5 - 1 - read-only - - - ST_ERR_F_BNDRY_MATCH_VC6 - NA - 6 - 1 - read-only - - - ST_ERR_F_BNDRY_MATCH_VC7 - NA - 7 - 1 - read-only - - - ST_ERR_F_BNDRY_MATCH_VC8 - NA - 8 - 1 - read-only - - - ST_ERR_F_BNDRY_MATCH_VC9 - NA - 9 - 1 - read-only - - - ST_ERR_F_BNDRY_MATCH_VC10 - NA - 10 - 1 - read-only - - - ST_ERR_F_BNDRY_MATCH_VC11 - NA - 11 - 1 - read-only - - - ST_ERR_F_BNDRY_MATCH_VC12 - NA - 12 - 1 - read-only - - - ST_ERR_F_BNDRY_MATCH_VC13 - NA - 13 - 1 - read-only - - - ST_ERR_F_BNDRY_MATCH_VC14 - NA - 14 - 1 - read-only - - - ST_ERR_F_BNDRY_MATCH_VC15 - NA - 15 - 1 - read-only - - - - - INT_MSK_BNDRY_FRAME_FATAL - NA - 0x284 - 0x20 - - - MASK_ERR_F_BNDRY_MATCH_VC0 - NA - 0 - 1 - read-write - - - MASK_ERR_F_BNDRY_MATCH_VC1 - NA - 1 - 1 - read-write - - - MASK_ERR_F_BNDRY_MATCH_VC2 - NA - 2 - 1 - read-write - - - MASK_ERR_F_BNDRY_MATCH_VC3 - NA - 3 - 1 - read-write - - - MASK_ERR_F_BNDRY_MATCH_VC4 - NA - 4 - 1 - read-write - - - MASK_ERR_F_BNDRY_MATCH_VC5 - NA - 5 - 1 - read-write - - - MASK_ERR_F_BNDRY_MATCH_VC6 - NA - 6 - 1 - read-write - - - MASK_ERR_F_BNDRY_MATCH_VC7 - NA - 7 - 1 - read-write - - - MASK_ERR_F_BNDRY_MATCH_VC8 - NA - 8 - 1 - read-write - - - MASK_ERR_F_BNDRY_MATCH_VC9 - NA - 9 - 1 - read-write - - - MASK_ERR_F_BNDRY_MATCH_VC10 - NA - 10 - 1 - read-write - - - MASK_ERR_F_BNDRY_MATCH_VC11 - NA - 11 - 1 - read-write - - - MASK_ERR_F_BNDRY_MATCH_VC12 - NA - 12 - 1 - read-write - - - MASK_ERR_F_BNDRY_MATCH_VC13 - NA - 13 - 1 - read-write - - - MASK_ERR_F_BNDRY_MATCH_VC14 - NA - 14 - 1 - read-write - - - MASK_ERR_F_BNDRY_MATCH_VC15 - NA - 15 - 1 - read-write - - - - - INT_FORCE_BNDRY_FRAME_FATAL - NA - 0x288 - 0x20 - - - FORCE_ERR_F_BNDRY_MATCH_VC0 - NA - 0 - 1 - read-write - - - FORCE_ERR_F_BNDRY_MATCH_VC1 - NA - 1 - 1 - read-write - - - FORCE_ERR_F_BNDRY_MATCH_VC2 - NA - 2 - 1 - read-write - - - FORCE_ERR_F_BNDRY_MATCH_VC3 - NA - 3 - 1 - read-write - - - FORCE_ERR_F_BNDRY_MATCH_VC4 - NA - 4 - 1 - read-write - - - FORCE_ERR_F_BNDRY_MATCH_VC5 - NA - 5 - 1 - read-write - - - FORCE_ERR_F_BNDRY_MATCH_VC6 - NA - 6 - 1 - read-write - - - FORCE_ERR_F_BNDRY_MATCH_VC7 - NA - 7 - 1 - read-write - - - FORCE_ERR_F_BNDRY_MATCH_VC8 - NA - 8 - 1 - read-write - - - FORCE_ERR_F_BNDRY_MATCH_VC9 - NA - 9 - 1 - read-write - - - FORCE_ERR_F_BNDRY_MATCH_VC10 - NA - 10 - 1 - read-write - - - FORCE_ERR_F_BNDRY_MATCH_VC11 - NA - 11 - 1 - read-write - - - FORCE_ERR_F_BNDRY_MATCH_VC12 - NA - 12 - 1 - read-write - - - FORCE_ERR_F_BNDRY_MATCH_VC13 - NA - 13 - 1 - read-write - - - FORCE_ERR_F_BNDRY_MATCH_VC14 - NA - 14 - 1 - read-write - - - FORCE_ERR_F_BNDRY_MATCH_VC15 - NA - 15 - 1 - read-write - - - - - INT_ST_SEQ_FRAME_FATAL - NA - 0x290 - 0x20 - - - ST_ERR_F_SEQ_VC0 - NA - 0 - 1 - read-only - - - ST_ERR_F_SEQ_VC1 - NA - 1 - 1 - read-only - - - ST_ERR_F_SEQ_VC2 - NA - 2 - 1 - read-only - - - ST_ERR_F_SEQ_VC3 - NA - 3 - 1 - read-only - - - ST_ERR_F_SEQ_VC4 - NA - 4 - 1 - read-only - - - ST_ERR_F_SEQ_VC5 - NA - 5 - 1 - read-only - - - ST_ERR_F_SEQ_VC6 - NA - 6 - 1 - read-only - - - ST_ERR_F_SEQ_VC7 - NA - 7 - 1 - read-only - - - ST_ERR_F_SEQ_VC8 - NA - 8 - 1 - read-only - - - ST_ERR_F_SEQ_VC9 - NA - 9 - 1 - read-only - - - ST_ERR_F_SEQ_VC10 - NA - 10 - 1 - read-only - - - ST_ERR_F_SEQ_VC11 - NA - 11 - 1 - read-only - - - ST_ERR_F_SEQ_VC12 - NA - 12 - 1 - read-only - - - ST_ERR_F_SEQ_VC13 - NA - 13 - 1 - read-only - - - ST_ERR_F_SEQ_VC14 - NA - 14 - 1 - read-only - - - ST_ERR_F_SEQ_VC15 - NA - 15 - 1 - read-only - - - - - INT_MSK_SEQ_FRAME_FATAL - NA - 0x294 - 0x20 - - - MASK_ERR_F_SEQ_VC0 - NA - 0 - 1 - read-write - - - MASK_ERR_F_SEQ_VC1 - NA - 1 - 1 - read-write - - - MASK_ERR_F_SEQ_VC2 - NA - 2 - 1 - read-write - - - MASK_ERR_F_SEQ_VC3 - NA - 3 - 1 - read-write - - - MASK_ERR_F_SEQ_VC4 - NA - 4 - 1 - read-write - - - MASK_ERR_F_SEQ_VC5 - NA - 5 - 1 - read-write - - - MASK_ERR_F_SEQ_VC6 - NA - 6 - 1 - read-write - - - MASK_ERR_F_SEQ_VC7 - NA - 7 - 1 - read-write - - - MASK_ERR_F_SEQ_VC8 - NA - 8 - 1 - read-write - - - MASK_ERR_F_SEQ_VC9 - NA - 9 - 1 - read-write - - - MASK_ERR_F_SEQ_VC10 - NA - 10 - 1 - read-write - - - MASK_ERR_F_SEQ_VC11 - NA - 11 - 1 - read-write - - - MASK_ERR_F_SEQ_VC12 - NA - 12 - 1 - read-write - - - MASK_ERR_F_SEQ_VC13 - NA - 13 - 1 - read-write - - - MASK_ERR_F_SEQ_VC14 - NA - 14 - 1 - read-write - - - MASK_ERR_F_SEQ_VC15 - NA - 15 - 1 - read-write - - - - - INT_FORCE_SEQ_FRAME_FATAL - NA - 0x298 - 0x20 - - - FORCE_ERR_F_SEQ_VC0 - NA - 0 - 1 - read-write - - - FORCE_ERR_F_SEQ_VC1 - NA - 1 - 1 - read-write - - - FORCE_ERR_F_SEQ_VC2 - NA - 2 - 1 - read-write - - - FORCE_ERR_F_SEQ_VC3 - NA - 3 - 1 - read-write - - - FORCE_ERR_F_SEQ_VC4 - NA - 4 - 1 - read-write - - - FORCE_ERR_F_SEQ_VC5 - NA - 5 - 1 - read-write - - - FORCE_ERR_F_SEQ_VC6 - NA - 6 - 1 - read-write - - - FORCE_ERR_F_SEQ_VC7 - NA - 7 - 1 - read-write - - - FORCE_ERR_F_SEQ_VC8 - NA - 8 - 1 - read-write - - - FORCE_ERR_F_SEQ_VC9 - NA - 9 - 1 - read-write - - - FORCE_ERR_F_SEQ_VC10 - NA - 10 - 1 - read-write - - - FORCE_ERR_F_SEQ_VC11 - NA - 11 - 1 - read-write - - - FORCE_ERR_F_SEQ_VC12 - NA - 12 - 1 - read-write - - - FORCE_ERR_F_SEQ_VC13 - NA - 13 - 1 - read-write - - - FORCE_ERR_F_SEQ_VC14 - NA - 14 - 1 - read-write - - - FORCE_ERR_F_SEQ_VC15 - NA - 15 - 1 - read-write - - - - - INT_ST_CRC_FRAME_FATAL - NA - 0x2A0 - 0x20 - - - ST_ERR_FRAME_DATA_VC0 - NA - 0 - 1 - read-only - - - ST_ERR_FRAME_DATA_VC1 - NA - 1 - 1 - read-only - - - ST_ERR_FRAME_DATA_VC2 - NA - 2 - 1 - read-only - - - ST_ERR_FRAME_DATA_VC3 - NA - 3 - 1 - read-only - - - ST_ERR_FRAME_DATA_VC4 - NA - 4 - 1 - read-only - - - ST_ERR_FRAME_DATA_VC5 - NA - 5 - 1 - read-only - - - ST_ERR_FRAME_DATA_VC6 - NA - 6 - 1 - read-only - - - ST_ERR_FRAME_DATA_VC7 - NA - 7 - 1 - read-only - - - ST_ERR_FRAME_DATA_VC8 - NA - 8 - 1 - read-only - - - ST_ERR_FRAME_DATA_VC9 - NA - 9 - 1 - read-only - - - ST_ERR_FRAME_DATA_VC10 - NA - 10 - 1 - read-only - - - ST_ERR_FRAME_DATA_VC11 - NA - 11 - 1 - read-only - - - ST_ERR_FRAME_DATA_VC12 - NA - 12 - 1 - read-only - - - ST_ERR_FRAME_DATA_VC13 - NA - 13 - 1 - read-only - - - ST_ERR_FRAME_DATA_VC14 - NA - 14 - 1 - read-only - - - ST_ERR_FRAME_DATA_VC15 - NA - 15 - 1 - read-only - - - - - INT_MSK_CRC_FRAME_FATAL - NA - 0x2A4 - 0x20 - - - MASK_ERR_FRAME_DATA_VC0 - NA - 0 - 1 - read-write - - - MASK_ERR_FRAME_DATA_VC1 - NA - 1 - 1 - read-write - - - MASK_ERR_FRAME_DATA_VC2 - NA - 2 - 1 - read-write - - - MASK_ERR_FRAME_DATA_VC3 - NA - 3 - 1 - read-write - - - MASK_ERR_FRAME_DATA_VC4 - NA - 4 - 1 - read-write - - - MASK_ERR_FRAME_DATA_VC5 - NA - 5 - 1 - read-write - - - MASK_ERR_FRAME_DATA_VC6 - NA - 6 - 1 - read-write - - - MASK_ERR_FRAME_DATA_VC7 - NA - 7 - 1 - read-write - - - MASK_ERR_FRAME_DATA_VC8 - NA - 8 - 1 - read-write - - - MASK_ERR_FRAME_DATA_VC9 - NA - 9 - 1 - read-write - - - MASK_ERR_FRAME_DATA_VC10 - NA - 10 - 1 - read-write - - - MASK_ERR_FRAME_DATA_VC11 - NA - 11 - 1 - read-write - - - MASK_ERR_FRAME_DATA_VC12 - NA - 12 - 1 - read-write - - - MASK_ERR_FRAME_DATA_VC13 - NA - 13 - 1 - read-write - - - MASK_ERR_FRAME_DATA_VC14 - NA - 14 - 1 - read-write - - - MASK_ERR_FRAME_DATA_VC15 - NA - 15 - 1 - read-write - - - - - INT_FORCE_CRC_FRAME_FATAL - NA - 0x2A8 - 0x20 - - - FORCE_ERR_FRAME_DATA_VC0 - NA - 0 - 1 - read-write - - - FORCE_ERR_FRAME_DATA_VC1 - NA - 1 - 1 - read-write - - - FORCE_ERR_FRAME_DATA_VC2 - NA - 2 - 1 - read-write - - - FORCE_ERR_FRAME_DATA_VC3 - NA - 3 - 1 - read-write - - - FORCE_ERR_FRAME_DATA_VC4 - NA - 4 - 1 - read-write - - - FORCE_ERR_FRAME_DATA_VC5 - NA - 5 - 1 - read-write - - - FORCE_ERR_FRAME_DATA_VC6 - NA - 6 - 1 - read-write - - - FORCE_ERR_FRAME_DATA_VC7 - NA - 7 - 1 - read-write - - - FORCE_ERR_FRAME_DATA_VC8 - NA - 8 - 1 - read-write - - - FORCE_ERR_FRAME_DATA_VC9 - NA - 9 - 1 - read-write - - - FORCE_ERR_FRAME_DATA_VC10 - NA - 10 - 1 - read-write - - - FORCE_ERR_FRAME_DATA_VC11 - NA - 11 - 1 - read-write - - - FORCE_ERR_FRAME_DATA_VC12 - NA - 12 - 1 - read-write - - - FORCE_ERR_FRAME_DATA_VC13 - NA - 13 - 1 - read-write - - - FORCE_ERR_FRAME_DATA_VC14 - NA - 14 - 1 - read-write - - - FORCE_ERR_FRAME_DATA_VC15 - NA - 15 - 1 - read-write - - - - - INT_ST_PLD_CRC_FATAL - NA - 0x2B0 - 0x20 - - - ST_ERR_CRC_VC0 - NA - 0 - 1 - read-only - - - ST_ERR_CRC_VC1 - NA - 1 - 1 - read-only - - - ST_ERR_CRC_VC2 - NA - 2 - 1 - read-only - - - ST_ERR_CRC_VC3 - NA - 3 - 1 - read-only - - - ST_ERR_CRC_VC4 - NA - 4 - 1 - read-only - - - ST_ERR_CRC_VC5 - NA - 5 - 1 - read-only - - - ST_ERR_CRC_VC6 - NA - 6 - 1 - read-only - - - ST_ERR_CRC_VC7 - NA - 7 - 1 - read-only - - - ST_ERR_CRC_VC8 - NA - 8 - 1 - read-only - - - ST_ERR_CRC_VC9 - NA - 9 - 1 - read-only - - - ST_ERR_CRC_VC10 - NA - 10 - 1 - read-only - - - ST_ERR_CRC_VC11 - NA - 11 - 1 - read-only - - - ST_ERR_CRC_VC12 - NA - 12 - 1 - read-only - - - ST_ERR_CRC_VC13 - NA - 13 - 1 - read-only - - - ST_ERR_CRC_VC14 - NA - 14 - 1 - read-only - - - ST_ERR_CRC_VC15 - NA - 15 - 1 - read-only - - - - - INT_MSK_PLD_CRC_FATAL - NA - 0x2B4 - 0x20 - - - MASK_ERR_CRC_VC0 - NA - 0 - 1 - read-write - - - MASK_ERR_CRC_VC1 - NA - 1 - 1 - read-write - - - MASK_ERR_CRC_VC2 - NA - 2 - 1 - read-write - - - MASK_ERR_CRC_VC3 - NA - 3 - 1 - read-write - - - MASK_ERR_CRC_VC4 - NA - 4 - 1 - read-write - - - MASK_ERR_CRC_VC5 - NA - 5 - 1 - read-write - - - MASK_ERR_CRC_VC6 - NA - 6 - 1 - read-write - - - MASK_ERR_CRC_VC7 - NA - 7 - 1 - read-write - - - MASK_ERR_CRC_VC8 - NA - 8 - 1 - read-write - - - MASK_ERR_CRC_VC9 - NA - 9 - 1 - read-write - - - MASK_ERR_CRC_VC10 - NA - 10 - 1 - read-write - - - MASK_ERR_CRC_VC11 - NA - 11 - 1 - read-write - - - MASK_ERR_CRC_VC12 - NA - 12 - 1 - read-write - - - MASK_ERR_CRC_VC13 - NA - 13 - 1 - read-write - - - MASK_ERR_CRC_VC14 - NA - 14 - 1 - read-write - - - MASK_ERR_CRC_VC15 - NA - 15 - 1 - read-write - - - - - INT_FORCE_PLD_CRC_FATAL - NA - 0x2B8 - 0x20 - - - FORCE_ERR_CRC_VC0 - NA - 0 - 1 - read-write - - - FORCE_ERR_CRC_VC1 - NA - 1 - 1 - read-write - - - FORCE_ERR_CRC_VC2 - NA - 2 - 1 - read-write - - - FORCE_ERR_CRC_VC3 - NA - 3 - 1 - read-write - - - FORCE_ERR_CRC_VC4 - NA - 4 - 1 - read-write - - - FORCE_ERR_CRC_VC5 - NA - 5 - 1 - read-write - - - FORCE_ERR_CRC_VC6 - NA - 6 - 1 - read-write - - - FORCE_ERR_CRC_VC7 - NA - 7 - 1 - read-write - - - FORCE_ERR_CRC_VC8 - NA - 8 - 1 - read-write - - - FORCE_ERR_CRC_VC9 - NA - 9 - 1 - read-write - - - FORCE_ERR_CRC_VC10 - NA - 10 - 1 - read-write - - - FORCE_ERR_CRC_VC11 - NA - 11 - 1 - read-write - - - FORCE_ERR_CRC_VC12 - NA - 12 - 1 - read-write - - - FORCE_ERR_CRC_VC13 - NA - 13 - 1 - read-write - - - FORCE_ERR_CRC_VC14 - NA - 14 - 1 - read-write - - - FORCE_ERR_CRC_VC15 - NA - 15 - 1 - read-write - - - - - INT_ST_DATA_ID - NA - 0x2C0 - 0x20 - - - ST_ERR_ID_VC0 - NA - 0 - 1 - read-only - - - ST_ERR_ID_VC1 - NA - 1 - 1 - read-only - - - ST_ERR_ID_VC2 - NA - 2 - 1 - read-only - - - ST_ERR_ID_VC3 - NA - 3 - 1 - read-only - - - ST_ERR_ID_VC4 - NA - 4 - 1 - read-only - - - ST_ERR_ID_VC5 - NA - 5 - 1 - read-only - - - ST_ERR_ID_VC6 - NA - 6 - 1 - read-only - - - ST_ERR_ID_VC7 - NA - 7 - 1 - read-only - - - ST_ERR_ID_VC8 - NA - 8 - 1 - read-only - - - ST_ERR_ID_VC9 - NA - 9 - 1 - read-only - - - ST_ERR_ID_VC10 - NA - 10 - 1 - read-only - - - ST_ERR_ID_VC11 - NA - 11 - 1 - read-only - - - ST_ERR_ID_VC12 - NA - 12 - 1 - read-only - - - ST_ERR_ID_VC13 - NA - 13 - 1 - read-only - - - ST_ERR_ID_VC14 - NA - 14 - 1 - read-only - - - ST_ERR_ID_VC15 - NA - 15 - 1 - read-only - - - - - INT_MSK_DATA_ID - NA - 0x2C4 - 0x20 - - - MASK_ERR_ID_VC0 - NA - 0 - 1 - read-write - - - MASK_ERR_ID_VC1 - NA - 1 - 1 - read-write - - - MASK_ERR_ID_VC2 - NA - 2 - 1 - read-write - - - MASK_ERR_ID_VC3 - NA - 3 - 1 - read-write - - - MASK_ERR_ID_VC4 - NA - 4 - 1 - read-write - - - MASK_ERR_ID_VC5 - NA - 5 - 1 - read-write - - - MASK_ERR_ID_VC6 - NA - 6 - 1 - read-write - - - MASK_ERR_ID_VC7 - NA - 7 - 1 - read-write - - - MASK_ERR_ID_VC8 - NA - 8 - 1 - read-write - - - MASK_ERR_ID_VC9 - NA - 9 - 1 - read-write - - - MASK_ERR_ID_VC10 - NA - 10 - 1 - read-write - - - MASK_ERR_ID_VC11 - NA - 11 - 1 - read-write - - - MASK_ERR_ID_VC12 - NA - 12 - 1 - read-write - - - MASK_ERR_ID_VC13 - NA - 13 - 1 - read-write - - - MASK_ERR_ID_VC14 - NA - 14 - 1 - read-write - - - MASK_ERR_ID_VC15 - NA - 15 - 1 - read-write - - - - - INT_FORCE_DATA_ID - NA - 0x2C8 - 0x20 - - - FORCE_ERR_ID_VC0 - NA - 0 - 1 - read-write - - - FORCE_ERR_ID_VC1 - NA - 1 - 1 - read-write - - - FORCE_ERR_ID_VC2 - NA - 2 - 1 - read-write - - - FORCE_ERR_ID_VC3 - NA - 3 - 1 - read-write - - - FORCE_ERR_ID_VC4 - NA - 4 - 1 - read-write - - - FORCE_ERR_ID_VC5 - NA - 5 - 1 - read-write - - - FORCE_ERR_ID_VC6 - NA - 6 - 1 - read-write - - - FORCE_ERR_ID_VC7 - NA - 7 - 1 - read-write - - - FORCE_ERR_ID_VC8 - NA - 8 - 1 - read-write - - - FORCE_ERR_ID_VC9 - NA - 9 - 1 - read-write - - - FORCE_ERR_ID_VC10 - NA - 10 - 1 - read-write - - - FORCE_ERR_ID_VC11 - NA - 11 - 1 - read-write - - - FORCE_ERR_ID_VC12 - NA - 12 - 1 - read-write - - - FORCE_ERR_ID_VC13 - NA - 13 - 1 - read-write - - - FORCE_ERR_ID_VC14 - NA - 14 - 1 - read-write - - - FORCE_ERR_ID_VC15 - NA - 15 - 1 - read-write - - - - - INT_ST_ECC_CORRECTED - NA - 0x2D0 - 0x20 - - - ST_ERR_ECC_CORRECTED_VC0 - NA - 0 - 1 - read-only - - - ST_ERR_ECC_CORRECTED_VC1 - NA - 1 - 1 - read-only - - - ST_ERR_ECC_CORRECTED_VC2 - NA - 2 - 1 - read-only - - - ST_ERR_ECC_CORRECTED_VC3 - NA - 3 - 1 - read-only - - - ST_ERR_ECC_CORRECTED_VC4 - NA - 4 - 1 - read-only - - - ST_ERR_ECC_CORRECTED_VC5 - NA - 5 - 1 - read-only - - - ST_ERR_ECC_CORRECTED_VC6 - NA - 6 - 1 - read-only - - - ST_ERR_ECC_CORRECTED_VC7 - NA - 7 - 1 - read-only - - - ST_ERR_ECC_CORRECTED_VC8 - NA - 8 - 1 - read-only - - - ST_ERR_ECC_CORRECTED_VC9 - NA - 9 - 1 - read-only - - - ST_ERR_ECC_CORRECTED_VC10 - NA - 10 - 1 - read-only - - - ST_ERR_ECC_CORRECTED_VC11 - NA - 11 - 1 - read-only - - - ST_ERR_ECC_CORRECTED_VC12 - NA - 12 - 1 - read-only - - - ST_ERR_ECC_CORRECTED_VC13 - NA - 13 - 1 - read-only - - - ST_ERR_ECC_CORRECTED_VC14 - NA - 14 - 1 - read-only - - - ST_ERR_ECC_CORRECTED_VC15 - NA - 15 - 1 - read-only - - - - - INT_MSK_ECC_CORRECTED - NA - 0x2D4 - 0x20 - - - MASK_ERR_ECC_CORRECTED_VC0 - NA - 0 - 1 - read-write - - - MASK_ERR_ECC_CORRECTED_VC1 - NA - 1 - 1 - read-write - - - MASK_ERR_ECC_CORRECTED_VC2 - NA - 2 - 1 - read-write - - - MASK_ERR_ECC_CORRECTED_VC3 - NA - 3 - 1 - read-write - - - MASK_ERR_ECC_CORRECTED_VC4 - NA - 4 - 1 - read-write - - - MASK_ERR_ECC_CORRECTED_VC5 - NA - 5 - 1 - read-write - - - MASK_ERR_ECC_CORRECTED_VC6 - NA - 6 - 1 - read-write - - - MASK_ERR_ECC_CORRECTED_VC7 - NA - 7 - 1 - read-write - - - MASK_ERR_ECC_CORRECTED_VC8 - NA - 8 - 1 - read-write - - - MASK_ERR_ECC_CORRECTED_VC9 - NA - 9 - 1 - read-write - - - MASK_ERR_ECC_CORRECTED_VC10 - NA - 10 - 1 - read-write - - - MASK_ERR_ECC_CORRECTED_VC11 - NA - 11 - 1 - read-write - - - MASK_ERR_ECC_CORRECTED_VC12 - NA - 12 - 1 - read-write - - - MASK_ERR_ECC_CORRECTED_VC13 - NA - 13 - 1 - read-write - - - MASK_ERR_ECC_CORRECTED_VC14 - NA - 14 - 1 - read-write - - - MASK_ERR_ECC_CORRECTED_VC15 - NA - 15 - 1 - read-write - - - - - INT_FORCE_ECC_CORRECTED - NA - 0x2D8 - 0x20 - - - FORCE_ERR_ECC_CORRECTED_VC0 - NA - 0 - 1 - read-write - - - FORCE_ERR_ECC_CORRECTED_VC1 - NA - 1 - 1 - read-write - - - FORCE_ERR_ECC_CORRECTED_VC2 - NA - 2 - 1 - read-write - - - FORCE_ERR_ECC_CORRECTED_VC3 - NA - 3 - 1 - read-write - - - FORCE_ERR_ECC_CORRECTED_VC4 - NA - 4 - 1 - read-write - - - FORCE_ERR_ECC_CORRECTED_VC5 - NA - 5 - 1 - read-write - - - FORCE_ERR_ECC_CORRECTED_VC6 - NA - 6 - 1 - read-write - - - FORCE_ERR_ECC_CORRECTED_VC7 - NA - 7 - 1 - read-write - - - FORCE_ERR_ECC_CORRECTED_VC8 - NA - 8 - 1 - read-write - - - FORCE_ERR_ECC_CORRECTED_VC9 - NA - 9 - 1 - read-write - - - FORCE_ERR_ECC_CORRECTED_VC10 - NA - 10 - 1 - read-write - - - FORCE_ERR_ECC_CORRECTED_VC11 - NA - 11 - 1 - read-write - - - FORCE_ERR_ECC_CORRECTED_VC12 - NA - 12 - 1 - read-write - - - FORCE_ERR_ECC_CORRECTED_VC13 - NA - 13 - 1 - read-write - - - FORCE_ERR_ECC_CORRECTED_VC14 - NA - 14 - 1 - read-write - - - FORCE_ERR_ECC_CORRECTED_VC15 - NA - 15 - 1 - read-write - - - - - SCRAMBLING - NA - 0x300 - 0x20 - - - SCRAMBLE_ENABLE - NA - 0 - 1 - read-write - - - - - SCRAMBLING_SEED1 - NA - 0x304 - 0x20 - 0x00001008 - - - SCRAMBLE_SEED_LANE1 - NA - 0 - 16 - read-write - - - - - SCRAMBLING_SEED2 - NA - 0x308 - 0x20 - 0x00001188 - - - SCRAMBLE_SEED_LANE2 - NA - 0 - 16 - read-write - - - - - - - DMA - DMA (Direct Memory Access) Controller - DMAC - 0x50081000 - - 0x0 - 0x234 - registers - - - DMA - 24 - - - - ID0 - NA - 0x0 - 0x20 - - - DMAC_ID - NA - 0 - 32 - read-only - - - - - COMPVER0 - NA - 0x8 - 0x20 - 0x3230302A - - - DMAC_COMPVER - NA - 0 - 32 - read-only - - - - - CFG0 - NA - 0x10 - 0x20 - - - DMAC_EN - NA - 0 - 1 - read-write - - - INT_EN - NA - 1 - 1 - read-write - - - - - CHEN0 - NA - 0x18 - 0x20 - - - CH1_EN - NA - 0 - 1 - read-write - - - CH2_EN - NA - 1 - 1 - read-write - - - CH3_EN - NA - 2 - 1 - read-write - - - CH4_EN - NA - 3 - 1 - read-write - - - CH1_EN_WE - NA - 8 - 1 - write-only - - - CH2_EN_WE - NA - 9 - 1 - write-only - - - CH3_EN_WE - NA - 10 - 1 - write-only - - - CH4_EN_WE - NA - 11 - 1 - write-only - - - CH1_SUSP - NA - 16 - 1 - read-write - - - CH2_SUSP - NA - 17 - 1 - read-write - - - CH3_SUSP - NA - 18 - 1 - read-write - - - CH4_SUSP - NA - 19 - 1 - read-write - - - CH1_SUSP_WE - NA - 24 - 1 - write-only - - - CH2_SUSP_WE - NA - 25 - 1 - write-only - - - CH3_SUSP_WE - NA - 26 - 1 - write-only - - - CH4_SUSP_WE - NA - 27 - 1 - write-only - - - - - CHEN1 - NA - 0x1C - 0x20 - - - CH1_ABORT - NA - 0 - 1 - read-write - - - CH2_ABORT - NA - 1 - 1 - read-write - - - CH3_ABORT - NA - 2 - 1 - read-write - - - CH4_ABORT - NA - 3 - 1 - read-write - - - CH1_ABORT_WE - NA - 8 - 1 - write-only - - - CH2_ABORT_WE - NA - 9 - 1 - write-only - - - CH3_ABORT_WE - NA - 10 - 1 - write-only - - - CH4_ABORT_WE - NA - 11 - 1 - write-only - - - - - INTSTATUS0 - NA - 0x30 - 0x20 - - - CH1_INTSTAT - NA - 0 - 1 - read-only - - - CH2_INTSTAT - NA - 1 - 1 - read-only - - - CH3_INTSTAT - NA - 2 - 1 - read-only - - - CH4_INTSTAT - NA - 3 - 1 - read-only - - - COMMONREG_INTSTAT - NA - 16 - 1 - read-only - - - - - COMMONREG_INTCLEAR0 - NA - 0x38 - 0x20 - - - CLEAR_SLVIF_COMMONREG_DEC_ERR_INTSTAT - NA - 0 - 1 - write-only - - - CLEAR_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT - NA - 1 - 1 - write-only - - - CLEAR_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT - NA - 2 - 1 - write-only - - - CLEAR_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT - NA - 3 - 1 - write-only - - - CLEAR_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT - NA - 7 - 1 - write-only - - - CLEAR_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT - NA - 8 - 1 - write-only - - - CLEAR_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT - NA - 9 - 1 - write-only - - - CLEAR_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT - NA - 10 - 1 - write-only - - - CLEAR_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT - NA - 11 - 1 - write-only - - - CLEAR_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT - NA - 12 - 1 - write-only - - - CLEAR_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT - NA - 13 - 1 - write-only - - - CLEAR_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT - NA - 14 - 1 - write-only - - - CLEAR_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT - NA - 15 - 1 - write-only - - - CLEAR_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT - NA - 16 - 1 - write-only - - - CLEAR_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT - NA - 17 - 1 - write-only - - - CLEAR_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT - NA - 18 - 1 - write-only - - - CLEAR_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT - NA - 19 - 1 - write-only - - - CLEAR_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT - NA - 20 - 1 - write-only - - - - - COMMONREG_INTSTATUS_ENABLE0 - NA - 0x40 - 0x20 - 0x001FFF8F - - - ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSTAT - NA - 0 - 1 - read-write - - - ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT - NA - 1 - 1 - read-write - - - ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT - NA - 2 - 1 - read-write - - - ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT - NA - 3 - 1 - read-write - - - ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT - NA - 7 - 1 - read-only - - - ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT - NA - 8 - 1 - read-write - - - ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT - NA - 9 - 1 - read-only - - - ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT - NA - 10 - 1 - read-only - - - ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT - NA - 11 - 1 - read-only - - - ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT - NA - 12 - 1 - read-only - - - ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT - NA - 13 - 1 - read-only - - - ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT - NA - 14 - 1 - read-only - - - ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT - NA - 15 - 1 - read-only - - - ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT - NA - 16 - 1 - read-only - - - ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT - NA - 17 - 1 - read-only - - - ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT - NA - 18 - 1 - read-only - - - ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT - NA - 19 - 1 - read-only - - - ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT - NA - 20 - 1 - read-only - - - - - COMMONREG_INTSIGNAL_ENABLE0 - NA - 0x48 - 0x20 - 0x001FFF8F - - - ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSIGNAL - NA - 0 - 1 - read-write - - - ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSIGNAL - NA - 1 - 1 - read-write - - - ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSIGNAL - NA - 2 - 1 - read-write - - - ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSIGNAL - NA - 3 - 1 - read-write - - - ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSIGNAL - NA - 7 - 1 - read-only - - - ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSIGNAL - NA - 8 - 1 - read-write - - - ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSIGNAL - NA - 9 - 1 - read-only - - - ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSIGNAL - NA - 10 - 1 - read-only - - - ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSIGNAL - NA - 11 - 1 - read-only - - - ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSIGNAL - NA - 12 - 1 - read-only - - - ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSIGNAL - NA - 13 - 1 - read-only - - - ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSIGNAL - NA - 14 - 1 - read-only - - - ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSIGNAL - NA - 15 - 1 - read-only - - - ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSIGNAL - NA - 16 - 1 - read-only - - - ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSIGNAL - NA - 17 - 1 - read-only - - - ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSIGNAL - NA - 18 - 1 - read-only - - - ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSIGNAL - NA - 19 - 1 - read-only - - - ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSIGNAL - NA - 20 - 1 - read-only - - - - - COMMONREG_INTSTATUS0 - NA - 0x50 - 0x20 - - - SLVIF_COMMONREG_DEC_ERR_INTSTAT - NA - 0 - 1 - read-only - - - SLVIF_COMMONREG_WR2RO_ERR_INTSTAT - NA - 1 - 1 - read-only - - - SLVIF_COMMONREG_RD2WO_ERR_INTSTAT - NA - 2 - 1 - read-only - - - SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT - NA - 3 - 1 - read-only - - - SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT - NA - 7 - 1 - read-only - - - SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT - NA - 8 - 1 - read-only - - - MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT - NA - 9 - 1 - read-only - - - MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT - NA - 10 - 1 - read-only - - - MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT - NA - 11 - 1 - read-only - - - MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT - NA - 12 - 1 - read-only - - - MXIF1_BCH_ECCPROT_CORRERR_INTSTAT - NA - 13 - 1 - read-only - - - MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT - NA - 14 - 1 - read-only - - - MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT - NA - 15 - 1 - read-only - - - MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT - NA - 16 - 1 - read-only - - - MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT - NA - 17 - 1 - read-only - - - MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT - NA - 18 - 1 - read-only - - - MXIF2_BCH_ECCPROT_CORRERR_INTSTAT - NA - 19 - 1 - read-only - - - MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT - NA - 20 - 1 - read-only - - - - - RESET0 - NA - 0x58 - 0x20 - - - DMAC_RST - NA - 0 - 1 - read-write - - - - - LOWPOWER_CFG0 - NA - 0x60 - 0x20 - 0x0000000F - - - GBL_CSLP_EN - NA - 0 - 1 - read-write - - - CHNL_CSLP_EN - NA - 1 - 1 - read-write - - - SBIU_CSLP_EN - NA - 2 - 1 - read-write - - - MXIF_CSLP_EN - NA - 3 - 1 - read-write - - - - - LOWPOWER_CFG1 - NA - 0x64 - 0x20 - 0x00404040 - - - GLCH_LPDLY - NA - 0 - 8 - read-write - - - SBIU_LPDLY - NA - 8 - 8 - read-write - - - MXIF_LPDLY - NA - 16 - 8 - read-write - - - - - CH1_SAR0 - NA - 0x100 - 0x20 - - - CH1_SAR0 - NA - 0 - 32 - read-write - - - - - CH1_SAR1 - NA - 0x104 - 0x20 - - - CH1_SAR1 - NA - 0 - 32 - read-write - - - - - CH1_DAR0 - NA - 0x108 - 0x20 - - - CH1_DAR0 - NA - 0 - 32 - read-write - - - - - CH1_DAR1 - NA - 0x10C - 0x20 - - - CH1_DAR1 - NA - 0 - 32 - read-write - - - - - CH1_BLOCK_TS0 - NA - 0x110 - 0x20 - - - CH1_BLOCK_TS - NA - 0 - 22 - read-write - - - - - CH1_CTL0 - NA - 0x118 - 0x20 - 0x00001200 - - - CH1_SMS - NA - 0 - 1 - read-write - - - CH1_DMS - NA - 2 - 1 - read-write - - - CH1_SINC - NA - 4 - 1 - read-write - - - CH1_DINC - NA - 6 - 1 - read-write - - - CH1_SRC_TR_WIDTH - NA - 8 - 3 - read-write - - - CH1_DST_TR_WIDTH - NA - 11 - 3 - read-write - - - CH1_SRC_MSIZE - NA - 14 - 4 - read-write - - - CH1_DST_MSIZE - NA - 18 - 4 - read-write - - - CH1_AR_CACHE - NA - 22 - 4 - read-write - - - CH1_AW_CACHE - NA - 26 - 4 - read-write - - - CH1_NONPOSTED_LASTWRITE_EN - NA - 30 - 1 - read-write - - - - - CH1_CTL1 - NA - 0x11C - 0x20 - - - CH1_AR_PROT - NA - 0 - 3 - read-write - - - CH1_AW_PROT - NA - 3 - 3 - read-write - - - CH1_ARLEN_EN - NA - 6 - 1 - read-write - - - CH1_ARLEN - NA - 7 - 8 - read-write - - - CH1_AWLEN_EN - NA - 15 - 1 - read-write - - - CH1_AWLEN - NA - 16 - 8 - read-write - - - CH1_SRC_STAT_EN - NA - 24 - 1 - read-write - - - CH1_DST_STAT_EN - NA - 25 - 1 - read-write - - - CH1_IOC_BLKTFR - NA - 26 - 1 - read-write - - - CH1_SHADOWREG_OR_LLI_LAST - NA - 30 - 1 - read-write - - - CH1_SHADOWREG_OR_LLI_VALID - NA - 31 - 1 - read-write - - - - - CH1_CFG0 - NA - 0x120 - 0x20 - - - CH1_SRC_MULTBLK_TYPE - NA - 0 - 2 - read-write - - - CH1_DST_MULTBLK_TYPE - NA - 2 - 2 - read-write - - - CH1_RD_UID - NA - 18 - 4 - read-only - - - CH1_WR_UID - NA - 25 - 4 - read-only - - - - - CH1_CFG1 - NA - 0x124 - 0x20 - 0x0006001B - - - CH1_TT_FC - NA - 0 - 3 - read-write - - - CH1_HS_SEL_SRC - NA - 3 - 1 - read-write - - - CH1_HS_SEL_DST - NA - 4 - 1 - read-write - - - CH1_SRC_HWHS_POL - NA - 5 - 1 - read-only - - - CH1_DST_HWHS_POL - NA - 6 - 1 - read-only - - - CH1_SRC_PER - NA - 7 - 2 - read-write - - - CH1_DST_PER - NA - 12 - 2 - read-write - - - CH1_CH_PRIOR - NA - 17 - 3 - read-write - - - CH1_LOCK_CH - NA - 20 - 1 - read-only - - - CH1_LOCK_CH_L - NA - 21 - 2 - read-only - - - CH1_SRC_OSR_LMT - NA - 23 - 4 - read-write - - - CH1_DST_OSR_LMT - NA - 27 - 4 - read-write - - - - - CH1_LLP0 - NA - 0x128 - 0x20 - - - CH1_LMS - NA - 0 - 1 - read-write - - - CH1_LOC0 - NA - 6 - 26 - read-write - - - - - CH1_LLP1 - NA - 0x12C - 0x20 - - - CH1_LOC1 - NA - 0 - 32 - read-write - - - - - CH1_STATUS0 - NA - 0x130 - 0x20 - - - CH1_CMPLTD_BLK_TFR_SIZE - NA - 0 - 22 - read-only - - - - - CH1_STATUS1 - NA - 0x134 - 0x20 - - - CH1_DATA_LEFT_IN_FIFO - NA - 0 - 15 - read-only - - - - - CH1_SWHSSRC0 - NA - 0x138 - 0x20 - - - CH1_SWHS_REQ_SRC - NA - 0 - 1 - read-write - - - CH1_SWHS_REQ_SRC_WE - NA - 1 - 1 - write-only - - - CH1_SWHS_SGLREQ_SRC - NA - 2 - 1 - read-write - - - CH1_SWHS_SGLREQ_SRC_WE - NA - 3 - 1 - write-only - - - CH1_SWHS_LST_SRC - NA - 4 - 1 - read-write - - - CH1_SWHS_LST_SRC_WE - NA - 5 - 1 - write-only - - - - - CH1_SWHSDST0 - NA - 0x140 - 0x20 - - - CH1_SWHS_REQ_DST - NA - 0 - 1 - read-write - - - CH1_SWHS_REQ_DST_WE - NA - 1 - 1 - write-only - - - CH1_SWHS_SGLREQ_DST - NA - 2 - 1 - read-write - - - CH1_SWHS_SGLREQ_DST_WE - NA - 3 - 1 - write-only - - - CH1_SWHS_LST_DST - NA - 4 - 1 - read-write - - - CH1_SWHS_LST_DST_WE - NA - 5 - 1 - write-only - - - - - CH1_BLK_TFR_RESUMEREQ0 - NA - 0x148 - 0x20 - - - CH1_BLK_TFR_RESUMEREQ - NA - 0 - 1 - write-only - - - - - CH1_AXI_ID0 - NA - 0x150 - 0x20 - - - CH1_AXI_READ_ID_SUFFIX - NA - 0 - 1 - read-write - - - CH1_AXI_WRITE_ID_SUFFIX - NA - 16 - 1 - read-write - - - - - CH1_AXI_QOS0 - NA - 0x158 - 0x20 - - - CH1_AXI_AWQOS - NA - 0 - 4 - read-write - - - CH1_AXI_ARQOS - NA - 4 - 4 - read-write - - - - - CH1_SSTAT0 - NA - 0x160 - 0x20 - - - CH1_SSTAT - NA - 0 - 32 - read-only - - - - - CH1_DSTAT0 - NA - 0x168 - 0x20 - - - CH1_DSTAT - NA - 0 - 32 - read-only - - - - - CH1_SSTATAR0 - NA - 0x170 - 0x20 - - - CH1_SSTATAR0 - NA - 0 - 32 - read-write - - - - - CH1_SSTATAR1 - NA - 0x174 - 0x20 - - - CH1_SSTATAR1 - NA - 0 - 32 - read-write - - - - - CH1_DSTATAR0 - NA - 0x178 - 0x20 - - - CH1_DSTATAR0 - NA - 0 - 32 - read-write - - - - - CH1_DSTATAR1 - NA - 0x17C - 0x20 - - - CH1_DSTATAR1 - NA - 0 - 32 - read-write - - - - - CH1_INTSTATUS_ENABLE0 - NA - 0x180 - 0x20 - 0xFA3F7FFB - - - CH1_ENABLE_BLOCK_TFR_DONE_INTSTAT - NA - 0 - 1 - read-write - - - CH1_ENABLE_DMA_TFR_DONE_INTSTAT - NA - 1 - 1 - read-write - - - CH1_ENABLE_SRC_TRANSCOMP_INTSTAT - NA - 3 - 1 - read-write - - - CH1_ENABLE_DST_TRANSCOMP_INTSTAT - NA - 4 - 1 - read-write - - - CH1_ENABLE_SRC_DEC_ERR_INTSTAT - NA - 5 - 1 - read-write - - - CH1_ENABLE_DST_DEC_ERR_INTSTAT - NA - 6 - 1 - read-write - - - CH1_ENABLE_SRC_SLV_ERR_INTSTAT - NA - 7 - 1 - read-write - - - CH1_ENABLE_DST_SLV_ERR_INTSTAT - NA - 8 - 1 - read-write - - - CH1_ENABLE_LLI_RD_DEC_ERR_INTSTAT - NA - 9 - 1 - read-write - - - CH1_ENABLE_LLI_WR_DEC_ERR_INTSTAT - NA - 10 - 1 - read-write - - - CH1_ENABLE_LLI_RD_SLV_ERR_INTSTAT - NA - 11 - 1 - read-write - - - CH1_ENABLE_LLI_WR_SLV_ERR_INTSTAT - NA - 12 - 1 - read-write - - - CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT - NA - 13 - 1 - read-write - - - CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT - NA - 14 - 1 - read-write - - - CH1_ENABLE_SLVIF_DEC_ERR_INTSTAT - NA - 16 - 1 - read-write - - - CH1_ENABLE_SLVIF_WR2RO_ERR_INTSTAT - NA - 17 - 1 - read-write - - - CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT - NA - 18 - 1 - read-write - - - CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT - NA - 19 - 1 - read-write - - - CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT - NA - 20 - 1 - read-write - - - CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT - NA - 21 - 1 - read-write - - - CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT - NA - 25 - 1 - read-only - - - CH1_ENABLE_CH_LOCK_CLEARED_INTSTAT - NA - 27 - 1 - read-write - - - CH1_ENABLE_CH_SRC_SUSPENDED_INTSTAT - NA - 28 - 1 - read-write - - - CH1_ENABLE_CH_SUSPENDED_INTSTAT - NA - 29 - 1 - read-write - - - CH1_ENABLE_CH_DISABLED_INTSTAT - NA - 30 - 1 - read-write - - - CH1_ENABLE_CH_ABORTED_INTSTAT - NA - 31 - 1 - read-write - - - - - CH1_INTSTATUS_ENABLE1 - NA - 0x184 - 0x20 - 0x0000000F - - - CH1_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT - NA - 0 - 1 - read-only - - - CH1_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT - NA - 1 - 1 - read-only - - - CH1_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT - NA - 2 - 1 - read-only - - - CH1_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT - NA - 3 - 1 - read-only - - - - - CH1_INTSTATUS0 - NA - 0x188 - 0x20 - - - CH1_BLOCK_TFR_DONE_INTSTAT - NA - 0 - 1 - read-only - - - CH1_DMA_TFR_DONE_INTSTAT - NA - 1 - 1 - read-only - - - CH1_SRC_TRANSCOMP_INTSTAT - NA - 3 - 1 - read-only - - - CH1_DST_TRANSCOMP_INTSTAT - NA - 4 - 1 - read-only - - - CH1_SRC_DEC_ERR_INTSTAT - NA - 5 - 1 - read-only - - - CH1_DST_DEC_ERR_INTSTAT - NA - 6 - 1 - read-only - - - CH1_SRC_SLV_ERR_INTSTAT - NA - 7 - 1 - read-only - - - CH1_DST_SLV_ERR_INTSTAT - NA - 8 - 1 - read-only - - - CH1_LLI_RD_DEC_ERR_INTSTAT - NA - 9 - 1 - read-only - - - CH1_LLI_WR_DEC_ERR_INTSTAT - NA - 10 - 1 - read-only - - - CH1_LLI_RD_SLV_ERR_INTSTAT - NA - 11 - 1 - read-only - - - CH1_LLI_WR_SLV_ERR_INTSTAT - NA - 12 - 1 - read-only - - - CH1_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT - NA - 13 - 1 - read-only - - - CH1_SLVIF_MULTIBLKTYPE_ERR_INTSTAT - NA - 14 - 1 - read-only - - - CH1_SLVIF_DEC_ERR_INTSTAT - NA - 16 - 1 - read-only - - - CH1_SLVIF_WR2RO_ERR_INTSTAT - NA - 17 - 1 - read-only - - - CH1_SLVIF_RD2RWO_ERR_INTSTAT - NA - 18 - 1 - read-only - - - CH1_SLVIF_WRONCHEN_ERR_INTSTAT - NA - 19 - 1 - read-only - - - CH1_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT - NA - 20 - 1 - read-only - - - CH1_SLVIF_WRONHOLD_ERR_INTSTAT - NA - 21 - 1 - read-only - - - CH1_SLVIF_WRPARITY_ERR_INTSTAT - NA - 25 - 1 - read-only - - - CH1_CH_LOCK_CLEARED_INTSTAT - NA - 27 - 1 - read-only - - - CH1_CH_SRC_SUSPENDED_INTSTAT - NA - 28 - 1 - read-only - - - CH1_CH_SUSPENDED_INTSTAT - NA - 29 - 1 - read-only - - - CH1_CH_DISABLED_INTSTAT - NA - 30 - 1 - read-only - - - CH1_CH_ABORTED_INTSTAT - NA - 31 - 1 - read-only - - - - - CH1_INTSTATUS1 - NA - 0x18C - 0x20 - - - CH1_ECC_PROT_CHMEM_CORRERR_INTSTAT - NA - 0 - 1 - read-only - - - CH1_ECC_PROT_CHMEM_UNCORRERR_INTSTAT - NA - 1 - 1 - read-only - - - CH1_ECC_PROT_UIDMEM_CORRERR_INTSTAT - NA - 2 - 1 - read-only - - - CH1_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT - NA - 3 - 1 - read-only - - - - - CH1_INTSIGNAL_ENABLE0 - NA - 0x190 - 0x20 - 0xFA3F7FFB - - - CH1_ENABLE_BLOCK_TFR_DONE_INTSIGNAL - NA - 0 - 1 - read-write - - - CH1_ENABLE_DMA_TFR_DONE_INTSIGNAL - NA - 1 - 1 - read-write - - - CH1_ENABLE_SRC_TRANSCOMP_INTSIGNAL - NA - 3 - 1 - read-write - - - CH1_ENABLE_DST_TRANSCOMP_INTSIGNAL - NA - 4 - 1 - read-write - - - CH1_ENABLE_SRC_DEC_ERR_INTSIGNAL - NA - 5 - 1 - read-write - - - CH1_ENABLE_DST_DEC_ERR_INTSIGNAL - NA - 6 - 1 - read-write - - - CH1_ENABLE_SRC_SLV_ERR_INTSIGNAL - NA - 7 - 1 - read-write - - - CH1_ENABLE_DST_SLV_ERR_INTSIGNAL - NA - 8 - 1 - read-write - - - CH1_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL - NA - 9 - 1 - read-write - - - CH1_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL - NA - 10 - 1 - read-write - - - CH1_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL - NA - 11 - 1 - read-write - - - CH1_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL - NA - 12 - 1 - read-write - - - CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL - NA - 13 - 1 - read-write - - - CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL - NA - 14 - 1 - read-write - - - CH1_ENABLE_SLVIF_DEC_ERR_INTSIGNAL - NA - 16 - 1 - read-write - - - CH1_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL - NA - 17 - 1 - read-write - - - CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL - NA - 18 - 1 - read-write - - - CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL - NA - 19 - 1 - read-write - - - CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL - NA - 20 - 1 - read-write - - - CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL - NA - 21 - 1 - read-write - - - CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL - NA - 25 - 1 - read-only - - - CH1_ENABLE_CH_LOCK_CLEARED_INTSIGNAL - NA - 27 - 1 - read-write - - - CH1_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL - NA - 28 - 1 - read-write - - - CH1_ENABLE_CH_SUSPENDED_INTSIGNAL - NA - 29 - 1 - read-write - - - CH1_ENABLE_CH_DISABLED_INTSIGNAL - NA - 30 - 1 - read-write - - - CH1_ENABLE_CH_ABORTED_INTSIGNAL - NA - 31 - 1 - read-write - - - - - CH1_INTSIGNAL_ENABLE1 - NA - 0x194 - 0x20 - 0x0000000F - - - CH1_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL - NA - 0 - 1 - read-only - - - CH1_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL - NA - 1 - 1 - read-only - - - CH1_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL - NA - 2 - 1 - read-only - - - CH1_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL - NA - 3 - 1 - read-only - - - - - CH1_INTCLEAR0 - NA - 0x198 - 0x20 - - - CH1_CLEAR_BLOCK_TFR_DONE_INTSTAT - NA - 0 - 1 - write-only - - - CH1_CLEAR_DMA_TFR_DONE_INTSTAT - NA - 1 - 1 - write-only - - - CH1_CLEAR_SRC_TRANSCOMP_INTSTAT - NA - 3 - 1 - write-only - - - CH1_CLEAR_DST_TRANSCOMP_INTSTAT - NA - 4 - 1 - write-only - - - CH1_CLEAR_SRC_DEC_ERR_INTSTAT - NA - 5 - 1 - write-only - - - CH1_CLEAR_DST_DEC_ERR_INTSTAT - NA - 6 - 1 - write-only - - - CH1_CLEAR_SRC_SLV_ERR_INTSTAT - NA - 7 - 1 - write-only - - - CH1_CLEAR_DST_SLV_ERR_INTSTAT - NA - 8 - 1 - write-only - - - CH1_CLEAR_LLI_RD_DEC_ERR_INTSTAT - NA - 9 - 1 - write-only - - - CH1_CLEAR_LLI_WR_DEC_ERR_INTSTAT - NA - 10 - 1 - write-only - - - CH1_CLEAR_LLI_RD_SLV_ERR_INTSTAT - NA - 11 - 1 - write-only - - - CH1_CLEAR_LLI_WR_SLV_ERR_INTSTAT - NA - 12 - 1 - write-only - - - CH1_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT - NA - 13 - 1 - write-only - - - CH1_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT - NA - 14 - 1 - write-only - - - CH1_CLEAR_SLVIF_DEC_ERR_INTSTAT - NA - 16 - 1 - write-only - - - CH1_CLEAR_SLVIF_WR2RO_ERR_INTSTAT - NA - 17 - 1 - write-only - - - CH1_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT - NA - 18 - 1 - write-only - - - CH1_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT - NA - 19 - 1 - write-only - - - CH1_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT - NA - 20 - 1 - write-only - - - CH1_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT - NA - 21 - 1 - write-only - - - CH1_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT - NA - 25 - 1 - write-only - - - CH1_CLEAR_CH_LOCK_CLEARED_INTSTAT - NA - 27 - 1 - write-only - - - CH1_CLEAR_CH_SRC_SUSPENDED_INTSTAT - NA - 28 - 1 - write-only - - - CH1_CLEAR_CH_SUSPENDED_INTSTAT - NA - 29 - 1 - write-only - - - CH1_CLEAR_CH_DISABLED_INTSTAT - NA - 30 - 1 - write-only - - - CH1_CLEAR_CH_ABORTED_INTSTAT - NA - 31 - 1 - write-only - - - - - CH1_INTCLEAR1 - NA - 0x19C - 0x20 - - - CH1_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT - NA - 0 - 1 - write-only - - - CH1_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT - NA - 1 - 1 - write-only - - - CH1_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT - NA - 2 - 1 - write-only - - - CH1_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT - NA - 3 - 1 - write-only - - - - - CH2_SAR0 - NA - 0x200 - 0x20 - - - CH2_SAR0 - NA - 0 - 32 - read-write - - - - - CH2_SAR1 - NA - 0x204 - 0x20 - - - CH2_SAR1 - NA - 0 - 32 - read-write - - - - - CH2_DAR0 - NA - 0x208 - 0x20 - - - CH2_DAR0 - NA - 0 - 32 - read-write - - - - - CH2_DAR1 - NA - 0x20C - 0x20 - - - CH2_DAR1 - NA - 0 - 32 - read-write - - - - - CH2_BLOCK_TS0 - NA - 0x210 - 0x20 - - - CH2_BLOCK_TS - NA - 0 - 22 - read-write - - - - - CH2_CTL0 - NA - 0x218 - 0x20 - 0x00001200 - - - CH2_SMS - NA - 0 - 1 - read-write - - - CH2_DMS - NA - 2 - 1 - read-write - - - CH2_SINC - NA - 4 - 1 - read-write - - - CH2_DINC - NA - 6 - 1 - read-write - - - CH2_SRC_TR_WIDTH - NA - 8 - 3 - read-write - - - CH2_DST_TR_WIDTH - NA - 11 - 3 - read-write - - - CH2_SRC_MSIZE - NA - 14 - 4 - read-write - - - CH2_DST_MSIZE - NA - 18 - 4 - read-write - - - CH2_AR_CACHE - NA - 22 - 4 - read-write - - - CH2_AW_CACHE - NA - 26 - 4 - read-write - - - CH2_NONPOSTED_LASTWRITE_EN - NA - 30 - 1 - read-write - - - - - CH2_CTL1 - NA - 0x21C - 0x20 - - - CH2_AR_PROT - NA - 0 - 3 - read-write - - - CH2_AW_PROT - NA - 3 - 3 - read-write - - - CH2_ARLEN_EN - NA - 6 - 1 - read-write - - - CH2_ARLEN - NA - 7 - 8 - read-write - - - CH2_AWLEN_EN - NA - 15 - 1 - read-write - - - CH2_AWLEN - NA - 16 - 8 - read-write - - - CH2_SRC_STAT_EN - NA - 24 - 1 - read-write - - - CH2_DST_STAT_EN - NA - 25 - 1 - read-write - - - CH2_IOC_BLKTFR - NA - 26 - 1 - read-write - - - CH2_SHADOWREG_OR_LLI_LAST - NA - 30 - 1 - read-write - - - CH2_SHADOWREG_OR_LLI_VALID - NA - 31 - 1 - read-write - - - - - CH2_CFG0 - NA - 0x220 - 0x20 - - - CH2_SRC_MULTBLK_TYPE - NA - 0 - 2 - read-write - - - CH2_DST_MULTBLK_TYPE - NA - 2 - 2 - read-write - - - CH2_RD_UID - NA - 18 - 4 - read-only - - - CH2_WR_UID - NA - 25 - 4 - read-only - - - - - CH2_CFG1 - NA - 0x224 - 0x20 - 0x0004001B - - - CH2_TT_FC - NA - 0 - 3 - read-write - - - CH2_HS_SEL_SRC - NA - 3 - 1 - read-write - - - CH2_HS_SEL_DST - NA - 4 - 1 - read-write - - - CH2_SRC_HWHS_POL - NA - 5 - 1 - read-only - - - CH2_DST_HWHS_POL - NA - 6 - 1 - read-only - - - CH2_SRC_PER - NA - 7 - 2 - read-write - - - CH2_DST_PER - NA - 12 - 2 - read-write - - - CH2_CH_PRIOR - NA - 17 - 3 - read-write - - - CH2_LOCK_CH - NA - 20 - 1 - read-only - - - CH2_LOCK_CH_L - NA - 21 - 2 - read-only - - - CH2_SRC_OSR_LMT - NA - 23 - 4 - read-write - - - CH2_DST_OSR_LMT - NA - 27 - 4 - read-write - - - - - CH2_LLP0 - NA - 0x228 - 0x20 - - - CH2_LMS - NA - 0 - 1 - read-write - - - CH2_LOC0 - NA - 6 - 26 - read-write - - - - - CH2_LLP1 - NA - 0x22C - 0x20 - - - CH2_LOC1 - NA - 0 - 32 - read-write - - - - - CH2_STATUS0 - NA - 0x230 - 0x20 - - - CH2_CMPLTD_BLK_TFR_SIZE - NA - 0 - 22 - read-only - - - - - CH2_STATUS1 - NA - 0x234 - 0x20 - - - CH2_DATA_LEFT_IN_FIFO - NA - 0 - 15 - read-only - - - - - CH2_SWHSSRC0 - NA - 0x238 - 0x20 - - - CH2_SWHS_REQ_SRC - NA - 0 - 1 - read-write - - - CH2_SWHS_REQ_SRC_WE - NA - 1 - 1 - write-only - - - CH2_SWHS_SGLREQ_SRC - NA - 2 - 1 - read-write - - - CH2_SWHS_SGLREQ_SRC_WE - NA - 3 - 1 - write-only - - - CH2_SWHS_LST_SRC - NA - 4 - 1 - read-write - - - CH2_SWHS_LST_SRC_WE - NA - 5 - 1 - write-only - - - - - CH2_SWHSDST0 - NA - 0x240 - 0x20 - - - CH2_SWHS_REQ_DST - NA - 0 - 1 - read-write - - - CH2_SWHS_REQ_DST_WE - NA - 1 - 1 - write-only - - - CH2_SWHS_SGLREQ_DST - NA - 2 - 1 - read-write - - - CH2_SWHS_SGLREQ_DST_WE - NA - 3 - 1 - write-only - - - CH2_SWHS_LST_DST - NA - 4 - 1 - read-write - - - CH2_SWHS_LST_DST_WE - NA - 5 - 1 - write-only - - - - - CH2_BLK_TFR_RESUMEREQ0 - NA - 0x248 - 0x20 - - - CH2_BLK_TFR_RESUMEREQ - NA - 0 - 1 - write-only - - - - - CH2_AXI_ID0 - NA - 0x250 - 0x20 - - - CH2_AXI_READ_ID_SUFFIX - NA - 0 - 1 - read-write - - - CH2_AXI_WRITE_ID_SUFFIX - NA - 16 - 1 - read-write - - - - - CH2_AXI_QOS0 - NA - 0x258 - 0x20 - - - CH2_AXI_AWQOS - NA - 0 - 4 - read-write - - - CH2_AXI_ARQOS - NA - 4 - 4 - read-write - - - - - CH2_SSTAT0 - NA - 0x260 - 0x20 - - - CH2_SSTAT - NA - 0 - 32 - read-only - - - - - CH2_DSTAT0 - NA - 0x268 - 0x20 - - - CH2_DSTAT - NA - 0 - 32 - read-only - - - - - CH2_SSTATAR0 - NA - 0x270 - 0x20 - - - CH2_SSTATAR0 - NA - 0 - 32 - read-write - - - - - CH2_SSTATAR1 - NA - 0x274 - 0x20 - - - CH2_SSTATAR1 - NA - 0 - 32 - read-write - - - - - CH2_DSTATAR0 - NA - 0x278 - 0x20 - - - CH2_DSTATAR0 - NA - 0 - 32 - read-write - - - - - CH2_DSTATAR1 - NA - 0x27C - 0x20 - - - CH2_DSTATAR1 - NA - 0 - 32 - read-write - - - - - CH2_INTSTATUS_ENABLE0 - NA - 0x280 - 0x20 - 0xFA3F7FFB - - - CH2_ENABLE_BLOCK_TFR_DONE_INTSTAT - NA - 0 - 1 - read-write - - - CH2_ENABLE_DMA_TFR_DONE_INTSTAT - NA - 1 - 1 - read-write - - - CH2_ENABLE_SRC_TRANSCOMP_INTSTAT - NA - 3 - 1 - read-write - - - CH2_ENABLE_DST_TRANSCOMP_INTSTAT - NA - 4 - 1 - read-write - - - CH2_ENABLE_SRC_DEC_ERR_INTSTAT - NA - 5 - 1 - read-write - - - CH2_ENABLE_DST_DEC_ERR_INTSTAT - NA - 6 - 1 - read-write - - - CH2_ENABLE_SRC_SLV_ERR_INTSTAT - NA - 7 - 1 - read-write - - - CH2_ENABLE_DST_SLV_ERR_INTSTAT - NA - 8 - 1 - read-write - - - CH2_ENABLE_LLI_RD_DEC_ERR_INTSTAT - NA - 9 - 1 - read-write - - - CH2_ENABLE_LLI_WR_DEC_ERR_INTSTAT - NA - 10 - 1 - read-write - - - CH2_ENABLE_LLI_RD_SLV_ERR_INTSTAT - NA - 11 - 1 - read-write - - - CH2_ENABLE_LLI_WR_SLV_ERR_INTSTAT - NA - 12 - 1 - read-write - - - CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT - NA - 13 - 1 - read-write - - - CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT - NA - 14 - 1 - read-write - - - CH2_ENABLE_SLVIF_DEC_ERR_INTSTAT - NA - 16 - 1 - read-write - - - CH2_ENABLE_SLVIF_WR2RO_ERR_INTSTAT - NA - 17 - 1 - read-write - - - CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT - NA - 18 - 1 - read-write - - - CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT - NA - 19 - 1 - read-write - - - CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT - NA - 20 - 1 - read-write - - - CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT - NA - 21 - 1 - read-write - - - CH2_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT - NA - 25 - 1 - read-only - - - CH2_ENABLE_CH_LOCK_CLEARED_INTSTAT - NA - 27 - 1 - read-write - - - CH2_ENABLE_CH_SRC_SUSPENDED_INTSTAT - NA - 28 - 1 - read-write - - - CH2_ENABLE_CH_SUSPENDED_INTSTAT - NA - 29 - 1 - read-write - - - CH2_ENABLE_CH_DISABLED_INTSTAT - NA - 30 - 1 - read-write - - - CH2_ENABLE_CH_ABORTED_INTSTAT - NA - 31 - 1 - read-write - - - - - CH2_INTSTATUS_ENABLE1 - NA - 0x284 - 0x20 - 0x0000000F - - - CH2_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT - NA - 0 - 1 - read-only - - - CH2_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT - NA - 1 - 1 - read-only - - - CH2_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT - NA - 2 - 1 - read-only - - - CH2_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT - NA - 3 - 1 - read-only - - - - - CH2_INTSTATUS0 - NA - 0x288 - 0x20 - - - CH2_BLOCK_TFR_DONE_INTSTAT - NA - 0 - 1 - read-only - - - CH2_DMA_TFR_DONE_INTSTAT - NA - 1 - 1 - read-only - - - CH2_SRC_TRANSCOMP_INTSTAT - NA - 3 - 1 - read-only - - - CH2_DST_TRANSCOMP_INTSTAT - NA - 4 - 1 - read-only - - - CH2_SRC_DEC_ERR_INTSTAT - NA - 5 - 1 - read-only - - - CH2_DST_DEC_ERR_INTSTAT - NA - 6 - 1 - read-only - - - CH2_SRC_SLV_ERR_INTSTAT - NA - 7 - 1 - read-only - - - CH2_DST_SLV_ERR_INTSTAT - NA - 8 - 1 - read-only - - - CH2_LLI_RD_DEC_ERR_INTSTAT - NA - 9 - 1 - read-only - - - CH2_LLI_WR_DEC_ERR_INTSTAT - NA - 10 - 1 - read-only - - - CH2_LLI_RD_SLV_ERR_INTSTAT - NA - 11 - 1 - read-only - - - CH2_LLI_WR_SLV_ERR_INTSTAT - NA - 12 - 1 - read-only - - - CH2_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT - NA - 13 - 1 - read-only - - - CH2_SLVIF_MULTIBLKTYPE_ERR_INTSTAT - NA - 14 - 1 - read-only - - - CH2_SLVIF_DEC_ERR_INTSTAT - NA - 16 - 1 - read-only - - - CH2_SLVIF_WR2RO_ERR_INTSTAT - NA - 17 - 1 - read-only - - - CH2_SLVIF_RD2RWO_ERR_INTSTAT - NA - 18 - 1 - read-only - - - CH2_SLVIF_WRONCHEN_ERR_INTSTAT - NA - 19 - 1 - read-only - - - CH2_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT - NA - 20 - 1 - read-only - - - CH2_SLVIF_WRONHOLD_ERR_INTSTAT - NA - 21 - 1 - read-only - - - CH2_SLVIF_WRPARITY_ERR_INTSTAT - NA - 25 - 1 - read-only - - - CH2_CH_LOCK_CLEARED_INTSTAT - NA - 27 - 1 - read-only - - - CH2_CH_SRC_SUSPENDED_INTSTAT - NA - 28 - 1 - read-only - - - CH2_CH_SUSPENDED_INTSTAT - NA - 29 - 1 - read-only - - - CH2_CH_DISABLED_INTSTAT - NA - 30 - 1 - read-only - - - CH2_CH_ABORTED_INTSTAT - NA - 31 - 1 - read-only - - - - - CH2_INTSTATUS1 - NA - 0x28C - 0x20 - - - CH2_ECC_PROT_CHMEM_CORRERR_INTSTAT - NA - 0 - 1 - read-only - - - CH2_ECC_PROT_CHMEM_UNCORRERR_INTSTAT - NA - 1 - 1 - read-only - - - CH2_ECC_PROT_UIDMEM_CORRERR_INTSTAT - NA - 2 - 1 - read-only - - - CH2_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT - NA - 3 - 1 - read-only - - - - - CH2_INTSIGNAL_ENABLE0 - NA - 0x290 - 0x20 - 0xFA3F7FFB - - - CH2_ENABLE_BLOCK_TFR_DONE_INTSIGNAL - NA - 0 - 1 - read-write - - - CH2_ENABLE_DMA_TFR_DONE_INTSIGNAL - NA - 1 - 1 - read-write - - - CH2_ENABLE_SRC_TRANSCOMP_INTSIGNAL - NA - 3 - 1 - read-write - - - CH2_ENABLE_DST_TRANSCOMP_INTSIGNAL - NA - 4 - 1 - read-write - - - CH2_ENABLE_SRC_DEC_ERR_INTSIGNAL - NA - 5 - 1 - read-write - - - CH2_ENABLE_DST_DEC_ERR_INTSIGNAL - NA - 6 - 1 - read-write - - - CH2_ENABLE_SRC_SLV_ERR_INTSIGNAL - NA - 7 - 1 - read-write - - - CH2_ENABLE_DST_SLV_ERR_INTSIGNAL - NA - 8 - 1 - read-write - - - CH2_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL - NA - 9 - 1 - read-write - - - CH2_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL - NA - 10 - 1 - read-write - - - CH2_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL - NA - 11 - 1 - read-write - - - CH2_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL - NA - 12 - 1 - read-write - - - CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL - NA - 13 - 1 - read-write - - - CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL - NA - 14 - 1 - read-write - - - CH2_ENABLE_SLVIF_DEC_ERR_INTSIGNAL - NA - 16 - 1 - read-write - - - CH2_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL - NA - 17 - 1 - read-write - - - CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL - NA - 18 - 1 - read-write - - - CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL - NA - 19 - 1 - read-write - - - CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL - NA - 20 - 1 - read-write - - - CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL - NA - 21 - 1 - read-write - - - CH2_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL - NA - 25 - 1 - read-only - - - CH2_ENABLE_CH_LOCK_CLEARED_INTSIGNAL - NA - 27 - 1 - read-write - - - CH2_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL - NA - 28 - 1 - read-write - - - CH2_ENABLE_CH_SUSPENDED_INTSIGNAL - NA - 29 - 1 - read-write - - - CH2_ENABLE_CH_DISABLED_INTSIGNAL - NA - 30 - 1 - read-write - - - CH2_ENABLE_CH_ABORTED_INTSIGNAL - NA - 31 - 1 - read-write - - - - - CH2_INTSIGNAL_ENABLE1 - NA - 0x294 - 0x20 - 0x0000000F - - - CH2_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL - NA - 0 - 1 - read-only - - - CH2_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL - NA - 1 - 1 - read-only - - - CH2_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL - NA - 2 - 1 - read-only - - - CH2_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL - NA - 3 - 1 - read-only - - - - - CH2_INTCLEAR0 - NA - 0x298 - 0x20 - - - CH2_CLEAR_BLOCK_TFR_DONE_INTSTAT - NA - 0 - 1 - write-only - - - CH2_CLEAR_DMA_TFR_DONE_INTSTAT - NA - 1 - 1 - write-only - - - CH2_CLEAR_SRC_TRANSCOMP_INTSTAT - NA - 3 - 1 - write-only - - - CH2_CLEAR_DST_TRANSCOMP_INTSTAT - NA - 4 - 1 - write-only - - - CH2_CLEAR_SRC_DEC_ERR_INTSTAT - NA - 5 - 1 - write-only - - - CH2_CLEAR_DST_DEC_ERR_INTSTAT - NA - 6 - 1 - write-only - - - CH2_CLEAR_SRC_SLV_ERR_INTSTAT - NA - 7 - 1 - write-only - - - CH2_CLEAR_DST_SLV_ERR_INTSTAT - NA - 8 - 1 - write-only - - - CH2_CLEAR_LLI_RD_DEC_ERR_INTSTAT - NA - 9 - 1 - write-only - - - CH2_CLEAR_LLI_WR_DEC_ERR_INTSTAT - NA - 10 - 1 - write-only - - - CH2_CLEAR_LLI_RD_SLV_ERR_INTSTAT - NA - 11 - 1 - write-only - - - CH2_CLEAR_LLI_WR_SLV_ERR_INTSTAT - NA - 12 - 1 - write-only - - - CH2_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT - NA - 13 - 1 - write-only - - - CH2_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT - NA - 14 - 1 - write-only - - - CH2_CLEAR_SLVIF_DEC_ERR_INTSTAT - NA - 16 - 1 - write-only - - - CH2_CLEAR_SLVIF_WR2RO_ERR_INTSTAT - NA - 17 - 1 - write-only - - - CH2_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT - NA - 18 - 1 - write-only - - - CH2_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT - NA - 19 - 1 - write-only - - - CH2_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT - NA - 20 - 1 - write-only - - - CH2_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT - NA - 21 - 1 - write-only - - - CH2_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT - NA - 25 - 1 - write-only - - - CH2_CLEAR_CH_LOCK_CLEARED_INTSTAT - NA - 27 - 1 - write-only - - - CH2_CLEAR_CH_SRC_SUSPENDED_INTSTAT - NA - 28 - 1 - write-only - - - CH2_CLEAR_CH_SUSPENDED_INTSTAT - NA - 29 - 1 - write-only - - - CH2_CLEAR_CH_DISABLED_INTSTAT - NA - 30 - 1 - write-only - - - CH2_CLEAR_CH_ABORTED_INTSTAT - NA - 31 - 1 - write-only - - - - - CH2_INTCLEAR1 - NA - 0x29C - 0x20 - - - CH2_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT - NA - 0 - 1 - write-only - - - CH2_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT - NA - 1 - 1 - write-only - - - CH2_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT - NA - 2 - 1 - write-only - - - CH2_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT - NA - 3 - 1 - write-only - - - - - CH3_SAR0 - NA - 0x300 - 0x20 - - - CH3_SAR0 - NA - 0 - 32 - read-write - - - - - CH3_SAR1 - NA - 0x304 - 0x20 - - - CH3_SAR1 - NA - 0 - 32 - read-write - - - - - CH3_DAR0 - NA - 0x308 - 0x20 - - - CH3_DAR0 - NA - 0 - 32 - read-write - - - - - CH3_DAR1 - NA - 0x30C - 0x20 - - - CH3_DAR1 - NA - 0 - 32 - read-write - - - - - CH3_BLOCK_TS0 - NA - 0x310 - 0x20 - - - CH3_BLOCK_TS - NA - 0 - 22 - read-write - - - - - CH3_CTL0 - NA - 0x318 - 0x20 - 0x00001200 - - - CH3_SMS - NA - 0 - 1 - read-write - - - CH3_DMS - NA - 2 - 1 - read-write - - - CH3_SINC - NA - 4 - 1 - read-write - - - CH3_DINC - NA - 6 - 1 - read-write - - - CH3_SRC_TR_WIDTH - NA - 8 - 3 - read-write - - - CH3_DST_TR_WIDTH - NA - 11 - 3 - read-write - - - CH3_SRC_MSIZE - NA - 14 - 4 - read-write - - - CH3_DST_MSIZE - NA - 18 - 4 - read-write - - - CH3_AR_CACHE - NA - 22 - 4 - read-write - - - CH3_AW_CACHE - NA - 26 - 4 - read-write - - - CH3_NONPOSTED_LASTWRITE_EN - NA - 30 - 1 - read-write - - - - - CH3_CTL1 - NA - 0x31C - 0x20 - - - CH3_AR_PROT - NA - 0 - 3 - read-write - - - CH3_AW_PROT - NA - 3 - 3 - read-write - - - CH3_ARLEN_EN - NA - 6 - 1 - read-write - - - CH3_ARLEN - NA - 7 - 8 - read-write - - - CH3_AWLEN_EN - NA - 15 - 1 - read-write - - - CH3_AWLEN - NA - 16 - 8 - read-write - - - CH3_SRC_STAT_EN - NA - 24 - 1 - read-write - - - CH3_DST_STAT_EN - NA - 25 - 1 - read-write - - - CH3_IOC_BLKTFR - NA - 26 - 1 - read-write - - - CH3_SHADOWREG_OR_LLI_LAST - NA - 30 - 1 - read-write - - - CH3_SHADOWREG_OR_LLI_VALID - NA - 31 - 1 - read-write - - - - - CH3_CFG0 - NA - 0x320 - 0x20 - - - CH3_SRC_MULTBLK_TYPE - NA - 0 - 2 - read-write - - - CH3_DST_MULTBLK_TYPE - NA - 2 - 2 - read-write - - - CH3_RD_UID - NA - 18 - 4 - read-only - - - CH3_WR_UID - NA - 25 - 4 - read-only - - - - - CH3_CFG1 - NA - 0x324 - 0x20 - 0x0002001B - - - CH3_TT_FC - NA - 0 - 3 - read-write - - - CH3_HS_SEL_SRC - NA - 3 - 1 - read-write - - - CH3_HS_SEL_DST - NA - 4 - 1 - read-write - - - CH3_SRC_HWHS_POL - NA - 5 - 1 - read-only - - - CH3_DST_HWHS_POL - NA - 6 - 1 - read-only - - - CH3_SRC_PER - NA - 7 - 2 - read-write - - - CH3_DST_PER - NA - 12 - 2 - read-write - - - CH3_CH_PRIOR - NA - 17 - 3 - read-write - - - CH3_LOCK_CH - NA - 20 - 1 - read-only - - - CH3_LOCK_CH_L - NA - 21 - 2 - read-only - - - CH3_SRC_OSR_LMT - NA - 23 - 4 - read-write - - - CH3_DST_OSR_LMT - NA - 27 - 4 - read-write - - - - - CH3_LLP0 - NA - 0x328 - 0x20 - - - CH3_LMS - NA - 0 - 1 - read-write - - - CH3_LOC0 - NA - 6 - 26 - read-write - - - - - CH3_LLP1 - NA - 0x32C - 0x20 - - - CH3_LOC1 - NA - 0 - 32 - read-write - - - - - CH3_STATUS0 - NA - 0x330 - 0x20 - - - CH3_CMPLTD_BLK_TFR_SIZE - NA - 0 - 22 - read-only - - - - - CH3_STATUS1 - NA - 0x334 - 0x20 - - - CH3_DATA_LEFT_IN_FIFO - NA - 0 - 15 - read-only - - - - - CH3_SWHSSRC0 - NA - 0x338 - 0x20 - - - CH3_SWHS_REQ_SRC - NA - 0 - 1 - read-write - - - CH3_SWHS_REQ_SRC_WE - NA - 1 - 1 - write-only - - - CH3_SWHS_SGLREQ_SRC - NA - 2 - 1 - read-write - - - CH3_SWHS_SGLREQ_SRC_WE - NA - 3 - 1 - write-only - - - CH3_SWHS_LST_SRC - NA - 4 - 1 - read-write - - - CH3_SWHS_LST_SRC_WE - NA - 5 - 1 - write-only - - - - - CH3_SWHSDST0 - NA - 0x340 - 0x20 - - - CH3_SWHS_REQ_DST - NA - 0 - 1 - read-write - - - CH3_SWHS_REQ_DST_WE - NA - 1 - 1 - write-only - - - CH3_SWHS_SGLREQ_DST - NA - 2 - 1 - read-write - - - CH3_SWHS_SGLREQ_DST_WE - NA - 3 - 1 - write-only - - - CH3_SWHS_LST_DST - NA - 4 - 1 - read-write - - - CH3_SWHS_LST_DST_WE - NA - 5 - 1 - write-only - - - - - CH3_BLK_TFR_RESUMEREQ0 - NA - 0x348 - 0x20 - - - CH3_BLK_TFR_RESUMEREQ - NA - 0 - 1 - write-only - - - - - CH3_AXI_ID0 - NA - 0x350 - 0x20 - - - CH3_AXI_READ_ID_SUFFIX - NA - 0 - 1 - read-write - - - CH3_AXI_WRITE_ID_SUFFIX - NA - 16 - 1 - read-write - - - - - CH3_AXI_QOS0 - NA - 0x358 - 0x20 - - - CH3_AXI_AWQOS - NA - 0 - 4 - read-write - - - CH3_AXI_ARQOS - NA - 4 - 4 - read-write - - - - - CH3_SSTAT0 - NA - 0x360 - 0x20 - - - CH3_SSTAT - NA - 0 - 32 - read-only - - - - - CH3_DSTAT0 - NA - 0x368 - 0x20 - - - CH3_DSTAT - NA - 0 - 32 - read-only - - - - - CH3_SSTATAR0 - NA - 0x370 - 0x20 - - - CH3_SSTATAR0 - NA - 0 - 32 - read-write - - - - - CH3_SSTATAR1 - NA - 0x374 - 0x20 - - - CH3_SSTATAR1 - NA - 0 - 32 - read-write - - - - - CH3_DSTATAR0 - NA - 0x378 - 0x20 - - - CH3_DSTATAR0 - NA - 0 - 32 - read-write - - - - - CH3_DSTATAR1 - NA - 0x37C - 0x20 - - - CH3_DSTATAR1 - NA - 0 - 32 - read-write - - - - - CH3_INTSTATUS_ENABLE0 - NA - 0x380 - 0x20 - 0xFA3F7FFB - - - CH3_ENABLE_BLOCK_TFR_DONE_INTSTAT - NA - 0 - 1 - read-write - - - CH3_ENABLE_DMA_TFR_DONE_INTSTAT - NA - 1 - 1 - read-write - - - CH3_ENABLE_SRC_TRANSCOMP_INTSTAT - NA - 3 - 1 - read-write - - - CH3_ENABLE_DST_TRANSCOMP_INTSTAT - NA - 4 - 1 - read-write - - - CH3_ENABLE_SRC_DEC_ERR_INTSTAT - NA - 5 - 1 - read-write - - - CH3_ENABLE_DST_DEC_ERR_INTSTAT - NA - 6 - 1 - read-write - - - CH3_ENABLE_SRC_SLV_ERR_INTSTAT - NA - 7 - 1 - read-write - - - CH3_ENABLE_DST_SLV_ERR_INTSTAT - NA - 8 - 1 - read-write - - - CH3_ENABLE_LLI_RD_DEC_ERR_INTSTAT - NA - 9 - 1 - read-write - - - CH3_ENABLE_LLI_WR_DEC_ERR_INTSTAT - NA - 10 - 1 - read-write - - - CH3_ENABLE_LLI_RD_SLV_ERR_INTSTAT - NA - 11 - 1 - read-write - - - CH3_ENABLE_LLI_WR_SLV_ERR_INTSTAT - NA - 12 - 1 - read-write - - - CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT - NA - 13 - 1 - read-write - - - CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT - NA - 14 - 1 - read-write - - - CH3_ENABLE_SLVIF_DEC_ERR_INTSTAT - NA - 16 - 1 - read-write - - - CH3_ENABLE_SLVIF_WR2RO_ERR_INTSTAT - NA - 17 - 1 - read-write - - - CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT - NA - 18 - 1 - read-write - - - CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT - NA - 19 - 1 - read-write - - - CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT - NA - 20 - 1 - read-write - - - CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT - NA - 21 - 1 - read-write - - - CH3_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT - NA - 25 - 1 - read-only - - - CH3_ENABLE_CH_LOCK_CLEARED_INTSTAT - NA - 27 - 1 - read-write - - - CH3_ENABLE_CH_SRC_SUSPENDED_INTSTAT - NA - 28 - 1 - read-write - - - CH3_ENABLE_CH_SUSPENDED_INTSTAT - NA - 29 - 1 - read-write - - - CH3_ENABLE_CH_DISABLED_INTSTAT - NA - 30 - 1 - read-write - - - CH3_ENABLE_CH_ABORTED_INTSTAT - NA - 31 - 1 - read-write - - - - - CH3_INTSTATUS_ENABLE1 - NA - 0x384 - 0x20 - 0x0000000F - - - CH3_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT - NA - 0 - 1 - read-only - - - CH3_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT - NA - 1 - 1 - read-only - - - CH3_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT - NA - 2 - 1 - read-only - - - CH3_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT - NA - 3 - 1 - read-only - - - - - CH3_INTSTATUS0 - NA - 0x388 - 0x20 - - - CH3_BLOCK_TFR_DONE_INTSTAT - NA - 0 - 1 - read-only - - - CH3_DMA_TFR_DONE_INTSTAT - NA - 1 - 1 - read-only - - - CH3_SRC_TRANSCOMP_INTSTAT - NA - 3 - 1 - read-only - - - CH3_DST_TRANSCOMP_INTSTAT - NA - 4 - 1 - read-only - - - CH3_SRC_DEC_ERR_INTSTAT - NA - 5 - 1 - read-only - - - CH3_DST_DEC_ERR_INTSTAT - NA - 6 - 1 - read-only - - - CH3_SRC_SLV_ERR_INTSTAT - NA - 7 - 1 - read-only - - - CH3_DST_SLV_ERR_INTSTAT - NA - 8 - 1 - read-only - - - CH3_LLI_RD_DEC_ERR_INTSTAT - NA - 9 - 1 - read-only - - - CH3_LLI_WR_DEC_ERR_INTSTAT - NA - 10 - 1 - read-only - - - CH3_LLI_RD_SLV_ERR_INTSTAT - NA - 11 - 1 - read-only - - - CH3_LLI_WR_SLV_ERR_INTSTAT - NA - 12 - 1 - read-only - - - CH3_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT - NA - 13 - 1 - read-only - - - CH3_SLVIF_MULTIBLKTYPE_ERR_INTSTAT - NA - 14 - 1 - read-only - - - CH3_SLVIF_DEC_ERR_INTSTAT - NA - 16 - 1 - read-only - - - CH3_SLVIF_WR2RO_ERR_INTSTAT - NA - 17 - 1 - read-only - - - CH3_SLVIF_RD2RWO_ERR_INTSTAT - NA - 18 - 1 - read-only - - - CH3_SLVIF_WRONCHEN_ERR_INTSTAT - NA - 19 - 1 - read-only - - - CH3_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT - NA - 20 - 1 - read-only - - - CH3_SLVIF_WRONHOLD_ERR_INTSTAT - NA - 21 - 1 - read-only - - - CH3_SLVIF_WRPARITY_ERR_INTSTAT - NA - 25 - 1 - read-only - - - CH3_CH_LOCK_CLEARED_INTSTAT - NA - 27 - 1 - read-only - - - CH3_CH_SRC_SUSPENDED_INTSTAT - NA - 28 - 1 - read-only - - - CH3_CH_SUSPENDED_INTSTAT - NA - 29 - 1 - read-only - - - CH3_CH_DISABLED_INTSTAT - NA - 30 - 1 - read-only - - - CH3_CH_ABORTED_INTSTAT - NA - 31 - 1 - read-only - - - - - CH3_INTSTATUS1 - NA - 0x38C - 0x20 - - - CH3_ECC_PROT_CHMEM_CORRERR_INTSTAT - NA - 0 - 1 - read-only - - - CH3_ECC_PROT_CHMEM_UNCORRERR_INTSTAT - NA - 1 - 1 - read-only - - - CH3_ECC_PROT_UIDMEM_CORRERR_INTSTAT - NA - 2 - 1 - read-only - - - CH3_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT - NA - 3 - 1 - read-only - - - - - CH3_INTSIGNAL_ENABLE0 - NA - 0x390 - 0x20 - 0xFA3F7FFB - - - CH3_ENABLE_BLOCK_TFR_DONE_INTSIGNAL - NA - 0 - 1 - read-write - - - CH3_ENABLE_DMA_TFR_DONE_INTSIGNAL - NA - 1 - 1 - read-write - - - CH3_ENABLE_SRC_TRANSCOMP_INTSIGNAL - NA - 3 - 1 - read-write - - - CH3_ENABLE_DST_TRANSCOMP_INTSIGNAL - NA - 4 - 1 - read-write - - - CH3_ENABLE_SRC_DEC_ERR_INTSIGNAL - NA - 5 - 1 - read-write - - - CH3_ENABLE_DST_DEC_ERR_INTSIGNAL - NA - 6 - 1 - read-write - - - CH3_ENABLE_SRC_SLV_ERR_INTSIGNAL - NA - 7 - 1 - read-write - - - CH3_ENABLE_DST_SLV_ERR_INTSIGNAL - NA - 8 - 1 - read-write - - - CH3_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL - NA - 9 - 1 - read-write - - - CH3_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL - NA - 10 - 1 - read-write - - - CH3_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL - NA - 11 - 1 - read-write - - - CH3_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL - NA - 12 - 1 - read-write - - - CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL - NA - 13 - 1 - read-write - - - CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL - NA - 14 - 1 - read-write - - - CH3_ENABLE_SLVIF_DEC_ERR_INTSIGNAL - NA - 16 - 1 - read-write - - - CH3_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL - NA - 17 - 1 - read-write - - - CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL - NA - 18 - 1 - read-write - - - CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL - NA - 19 - 1 - read-write - - - CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL - NA - 20 - 1 - read-write - - - CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL - NA - 21 - 1 - read-write - - - CH3_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL - NA - 25 - 1 - read-only - - - CH3_ENABLE_CH_LOCK_CLEARED_INTSIGNAL - NA - 27 - 1 - read-write - - - CH3_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL - NA - 28 - 1 - read-write - - - CH3_ENABLE_CH_SUSPENDED_INTSIGNAL - NA - 29 - 1 - read-write - - - CH3_ENABLE_CH_DISABLED_INTSIGNAL - NA - 30 - 1 - read-write - - - CH3_ENABLE_CH_ABORTED_INTSIGNAL - NA - 31 - 1 - read-write - - - - - CH3_INTSIGNAL_ENABLE1 - NA - 0x394 - 0x20 - 0x0000000F - - - CH3_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL - NA - 0 - 1 - read-only - - - CH3_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL - NA - 1 - 1 - read-only - - - CH3_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL - NA - 2 - 1 - read-only - - - CH3_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL - NA - 3 - 1 - read-only - - - - - CH3_INTCLEAR0 - NA - 0x398 - 0x20 - - - CH3_CLEAR_BLOCK_TFR_DONE_INTSTAT - NA - 0 - 1 - write-only - - - CH3_CLEAR_DMA_TFR_DONE_INTSTAT - NA - 1 - 1 - write-only - - - CH3_CLEAR_SRC_TRANSCOMP_INTSTAT - NA - 3 - 1 - write-only - - - CH3_CLEAR_DST_TRANSCOMP_INTSTAT - NA - 4 - 1 - write-only - - - CH3_CLEAR_SRC_DEC_ERR_INTSTAT - NA - 5 - 1 - write-only - - - CH3_CLEAR_DST_DEC_ERR_INTSTAT - NA - 6 - 1 - write-only - - - CH3_CLEAR_SRC_SLV_ERR_INTSTAT - NA - 7 - 1 - write-only - - - CH3_CLEAR_DST_SLV_ERR_INTSTAT - NA - 8 - 1 - write-only - - - CH3_CLEAR_LLI_RD_DEC_ERR_INTSTAT - NA - 9 - 1 - write-only - - - CH3_CLEAR_LLI_WR_DEC_ERR_INTSTAT - NA - 10 - 1 - write-only - - - CH3_CLEAR_LLI_RD_SLV_ERR_INTSTAT - NA - 11 - 1 - write-only - - - CH3_CLEAR_LLI_WR_SLV_ERR_INTSTAT - NA - 12 - 1 - write-only - - - CH3_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT - NA - 13 - 1 - write-only - - - CH3_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT - NA - 14 - 1 - write-only - - - CH3_CLEAR_SLVIF_DEC_ERR_INTSTAT - NA - 16 - 1 - write-only - - - CH3_CLEAR_SLVIF_WR2RO_ERR_INTSTAT - NA - 17 - 1 - write-only - - - CH3_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT - NA - 18 - 1 - write-only - - - CH3_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT - NA - 19 - 1 - write-only - - - CH3_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT - NA - 20 - 1 - write-only - - - CH3_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT - NA - 21 - 1 - write-only - - - CH3_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT - NA - 25 - 1 - write-only - - - CH3_CLEAR_CH_LOCK_CLEARED_INTSTAT - NA - 27 - 1 - write-only - - - CH3_CLEAR_CH_SRC_SUSPENDED_INTSTAT - NA - 28 - 1 - write-only - - - CH3_CLEAR_CH_SUSPENDED_INTSTAT - NA - 29 - 1 - write-only - - - CH3_CLEAR_CH_DISABLED_INTSTAT - NA - 30 - 1 - write-only - - - CH3_CLEAR_CH_ABORTED_INTSTAT - NA - 31 - 1 - write-only - - - - - CH3_INTCLEAR1 - NA - 0x39C - 0x20 - - - CH3_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT - NA - 0 - 1 - write-only - - - CH3_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT - NA - 1 - 1 - write-only - - - CH3_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT - NA - 2 - 1 - write-only - - - CH3_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT - NA - 3 - 1 - write-only - - - - - CH4_SAR0 - NA - 0x400 - 0x20 - - - CH4_SAR0 - NA - 0 - 32 - read-write - - - - - CH4_SAR1 - NA - 0x404 - 0x20 - - - CH4_SAR1 - NA - 0 - 32 - read-write - - - - - CH4_DAR0 - NA - 0x408 - 0x20 - - - CH4_DAR0 - NA - 0 - 32 - read-write - - - - - CH4_DAR1 - NA - 0x40C - 0x20 - - - CH4_DAR1 - NA - 0 - 32 - read-write - - - - - CH4_BLOCK_TS0 - NA - 0x410 - 0x20 - - - CH4_BLOCK_TS - NA - 0 - 22 - read-write - - - - - CH4_CTL0 - NA - 0x418 - 0x20 - 0x00001200 - - - CH4_SMS - NA - 0 - 1 - read-write - - - CH4_DMS - NA - 2 - 1 - read-write - - - CH4_SINC - NA - 4 - 1 - read-write - - - CH4_DINC - NA - 6 - 1 - read-write - - - CH4_SRC_TR_WIDTH - NA - 8 - 3 - read-write - - - CH4_DST_TR_WIDTH - NA - 11 - 3 - read-write - - - CH4_SRC_MSIZE - NA - 14 - 4 - read-write - - - CH4_DST_MSIZE - NA - 18 - 4 - read-write - - - CH4_AR_CACHE - NA - 22 - 4 - read-write - - - CH4_AW_CACHE - NA - 26 - 4 - read-write - - - CH4_NONPOSTED_LASTWRITE_EN - NA - 30 - 1 - read-write - - - - - CH4_CTL1 - NA - 0x41C - 0x20 - - - CH4_AR_PROT - NA - 0 - 3 - read-write - - - CH4_AW_PROT - NA - 3 - 3 - read-write - - - CH4_ARLEN_EN - NA - 6 - 1 - read-write - - - CH4_ARLEN - NA - 7 - 8 - read-write - - - CH4_AWLEN_EN - NA - 15 - 1 - read-write - - - CH4_AWLEN - NA - 16 - 8 - read-write - - - CH4_SRC_STAT_EN - NA - 24 - 1 - read-write - - - CH4_DST_STAT_EN - NA - 25 - 1 - read-write - - - CH4_IOC_BLKTFR - NA - 26 - 1 - read-write - - - CH4_SHADOWREG_OR_LLI_LAST - NA - 30 - 1 - read-write - - - CH4_SHADOWREG_OR_LLI_VALID - NA - 31 - 1 - read-write - - - - - CH4_CFG0 - NA - 0x420 - 0x20 - - - CH4_SRC_MULTBLK_TYPE - NA - 0 - 2 - read-write - - - CH4_DST_MULTBLK_TYPE - NA - 2 - 2 - read-write - - - CH4_RD_UID - NA - 18 - 4 - read-only - - - CH4_WR_UID - NA - 25 - 4 - read-only - - - - - CH4_CFG1 - NA - 0x424 - 0x20 - 0x0000001B - - - CH4_TT_FC - NA - 0 - 3 - read-write - - - CH4_HS_SEL_SRC - NA - 3 - 1 - read-write - - - CH4_HS_SEL_DST - NA - 4 - 1 - read-write - - - CH4_SRC_HWHS_POL - NA - 5 - 1 - read-only - - - CH4_DST_HWHS_POL - NA - 6 - 1 - read-only - - - CH4_SRC_PER - NA - 7 - 2 - read-write - - - CH4_DST_PER - NA - 12 - 2 - read-write - - - CH4_CH_PRIOR - NA - 17 - 3 - read-write - - - CH4_LOCK_CH - NA - 20 - 1 - read-only - - - CH4_LOCK_CH_L - NA - 21 - 2 - read-only - - - CH4_SRC_OSR_LMT - NA - 23 - 4 - read-write - - - CH4_DST_OSR_LMT - NA - 27 - 4 - read-write - - - - - CH4_LLP0 - NA - 0x428 - 0x20 - - - CH4_LMS - NA - 0 - 1 - read-write - - - CH4_LOC0 - NA - 6 - 26 - read-write - - - - - CH4_LLP1 - NA - 0x42C - 0x20 - - - CH4_LOC1 - NA - 0 - 32 - read-write - - - - - CH4_STATUS0 - NA - 0x430 - 0x20 - - - CH4_CMPLTD_BLK_TFR_SIZE - NA - 0 - 22 - read-only - - - - - CH4_STATUS1 - NA - 0x434 - 0x20 - - - CH4_DATA_LEFT_IN_FIFO - NA - 0 - 15 - read-only - - - - - CH4_SWHSSRC0 - NA - 0x438 - 0x20 - - - CH4_SWHS_REQ_SRC - NA - 0 - 1 - read-write - - - CH4_SWHS_REQ_SRC_WE - NA - 1 - 1 - write-only - - - CH4_SWHS_SGLREQ_SRC - NA - 2 - 1 - read-write - - - CH4_SWHS_SGLREQ_SRC_WE - NA - 3 - 1 - write-only - - - CH4_SWHS_LST_SRC - NA - 4 - 1 - read-write - - - CH4_SWHS_LST_SRC_WE - NA - 5 - 1 - write-only - - - - - CH4_SWHSDST0 - NA - 0x440 - 0x20 - - - CH4_SWHS_REQ_DST - NA - 0 - 1 - read-write - - - CH4_SWHS_REQ_DST_WE - NA - 1 - 1 - write-only - - - CH4_SWHS_SGLREQ_DST - NA - 2 - 1 - read-write - - - CH4_SWHS_SGLREQ_DST_WE - NA - 3 - 1 - write-only - - - CH4_SWHS_LST_DST - NA - 4 - 1 - read-write - - - CH4_SWHS_LST_DST_WE - NA - 5 - 1 - write-only - - - - - CH4_BLK_TFR_RESUMEREQ0 - NA - 0x448 - 0x20 - - - CH4_BLK_TFR_RESUMEREQ - NA - 0 - 1 - write-only - - - - - CH4_AXI_ID0 - NA - 0x450 - 0x20 - - - CH4_AXI_READ_ID_SUFFIX - NA - 0 - 1 - read-write - - - CH4_AXI_WRITE_ID_SUFFIX - NA - 16 - 1 - read-write - - - - - CH4_AXI_QOS0 - NA - 0x458 - 0x20 - - - CH4_AXI_AWQOS - NA - 0 - 4 - read-write - - - CH4_AXI_ARQOS - NA - 4 - 4 - read-write - - - - - CH4_SSTAT0 - NA - 0x460 - 0x20 - - - CH4_SSTAT - NA - 0 - 32 - read-only - - - - - CH4_DSTAT0 - NA - 0x468 - 0x20 - - - CH4_DSTAT - NA - 0 - 32 - read-only - - - - - CH4_SSTATAR0 - NA - 0x470 - 0x20 - - - CH4_SSTATAR0 - NA - 0 - 32 - read-write - - - - - CH4_SSTATAR1 - NA - 0x474 - 0x20 - - - CH4_SSTATAR1 - NA - 0 - 32 - read-write - - - - - CH4_DSTATAR0 - NA - 0x478 - 0x20 - - - CH4_DSTATAR0 - NA - 0 - 32 - read-write - - - - - CH4_DSTATAR1 - NA - 0x47C - 0x20 - - - CH4_DSTATAR1 - NA - 0 - 32 - read-write - - - - - CH4_INTSTATUS_ENABLE0 - NA - 0x480 - 0x20 - 0xFA3F7FFB - - - CH4_ENABLE_BLOCK_TFR_DONE_INTSTAT - NA - 0 - 1 - read-write - - - CH4_ENABLE_DMA_TFR_DONE_INTSTAT - NA - 1 - 1 - read-write - - - CH4_ENABLE_SRC_TRANSCOMP_INTSTAT - NA - 3 - 1 - read-write - - - CH4_ENABLE_DST_TRANSCOMP_INTSTAT - NA - 4 - 1 - read-write - - - CH4_ENABLE_SRC_DEC_ERR_INTSTAT - NA - 5 - 1 - read-write - - - CH4_ENABLE_DST_DEC_ERR_INTSTAT - NA - 6 - 1 - read-write - - - CH4_ENABLE_SRC_SLV_ERR_INTSTAT - NA - 7 - 1 - read-write - - - CH4_ENABLE_DST_SLV_ERR_INTSTAT - NA - 8 - 1 - read-write - - - CH4_ENABLE_LLI_RD_DEC_ERR_INTSTAT - NA - 9 - 1 - read-write - - - CH4_ENABLE_LLI_WR_DEC_ERR_INTSTAT - NA - 10 - 1 - read-write - - - CH4_ENABLE_LLI_RD_SLV_ERR_INTSTAT - NA - 11 - 1 - read-write - - - CH4_ENABLE_LLI_WR_SLV_ERR_INTSTAT - NA - 12 - 1 - read-write - - - CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT - NA - 13 - 1 - read-write - - - CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT - NA - 14 - 1 - read-write - - - CH4_ENABLE_SLVIF_DEC_ERR_INTSTAT - NA - 16 - 1 - read-write - - - CH4_ENABLE_SLVIF_WR2RO_ERR_INTSTAT - NA - 17 - 1 - read-write - - - CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT - NA - 18 - 1 - read-write - - - CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT - NA - 19 - 1 - read-write - - - CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT - NA - 20 - 1 - read-write - - - CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT - NA - 21 - 1 - read-write - - - CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT - NA - 25 - 1 - read-only - - - CH4_ENABLE_CH_LOCK_CLEARED_INTSTAT - NA - 27 - 1 - read-write - - - CH4_ENABLE_CH_SRC_SUSPENDED_INTSTAT - NA - 28 - 1 - read-write - - - CH4_ENABLE_CH_SUSPENDED_INTSTAT - NA - 29 - 1 - read-write - - - CH4_ENABLE_CH_DISABLED_INTSTAT - NA - 30 - 1 - read-write - - - CH4_ENABLE_CH_ABORTED_INTSTAT - NA - 31 - 1 - read-write - - - - - CH4_INTSTATUS_ENABLE1 - NA - 0x484 - 0x20 - 0x0000000F - - - CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT - NA - 0 - 1 - read-only - - - CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT - NA - 1 - 1 - read-only - - - CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT - NA - 2 - 1 - read-only - - - CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT - NA - 3 - 1 - read-only - - - - - CH4_INTSTATUS0 - NA - 0x488 - 0x20 - - - CH4_BLOCK_TFR_DONE_INTSTAT - NA - 0 - 1 - read-only - - - CH4_DMA_TFR_DONE_INTSTAT - NA - 1 - 1 - read-only - - - CH4_SRC_TRANSCOMP_INTSTAT - NA - 3 - 1 - read-only - - - CH4_DST_TRANSCOMP_INTSTAT - NA - 4 - 1 - read-only - - - CH4_SRC_DEC_ERR_INTSTAT - NA - 5 - 1 - read-only - - - CH4_DST_DEC_ERR_INTSTAT - NA - 6 - 1 - read-only - - - CH4_SRC_SLV_ERR_INTSTAT - NA - 7 - 1 - read-only - - - CH4_DST_SLV_ERR_INTSTAT - NA - 8 - 1 - read-only - - - CH4_LLI_RD_DEC_ERR_INTSTAT - NA - 9 - 1 - read-only - - - CH4_LLI_WR_DEC_ERR_INTSTAT - NA - 10 - 1 - read-only - - - CH4_LLI_RD_SLV_ERR_INTSTAT - NA - 11 - 1 - read-only - - - CH4_LLI_WR_SLV_ERR_INTSTAT - NA - 12 - 1 - read-only - - - CH4_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT - NA - 13 - 1 - read-only - - - CH4_SLVIF_MULTIBLKTYPE_ERR_INTSTAT - NA - 14 - 1 - read-only - - - CH4_SLVIF_DEC_ERR_INTSTAT - NA - 16 - 1 - read-only - - - CH4_SLVIF_WR2RO_ERR_INTSTAT - NA - 17 - 1 - read-only - - - CH4_SLVIF_RD2RWO_ERR_INTSTAT - NA - 18 - 1 - read-only - - - CH4_SLVIF_WRONCHEN_ERR_INTSTAT - NA - 19 - 1 - read-only - - - CH4_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT - NA - 20 - 1 - read-only - - - CH4_SLVIF_WRONHOLD_ERR_INTSTAT - NA - 21 - 1 - read-only - - - CH4_SLVIF_WRPARITY_ERR_INTSTAT - NA - 25 - 1 - read-only - - - CH4_CH_LOCK_CLEARED_INTSTAT - NA - 27 - 1 - read-only - - - CH4_CH_SRC_SUSPENDED_INTSTAT - NA - 28 - 1 - read-only - - - CH4_CH_SUSPENDED_INTSTAT - NA - 29 - 1 - read-only - - - CH4_CH_DISABLED_INTSTAT - NA - 30 - 1 - read-only - - - CH4_CH_ABORTED_INTSTAT - NA - 31 - 1 - read-only - - - - - CH4_INTSTATUS1 - NA - 0x48C - 0x20 - - - CH4_ECC_PROT_CHMEM_CORRERR_INTSTAT - NA - 0 - 1 - read-only - - - CH4_ECC_PROT_CHMEM_UNCORRERR_INTSTAT - NA - 1 - 1 - read-only - - - CH4_ECC_PROT_UIDMEM_CORRERR_INTSTAT - NA - 2 - 1 - read-only - - - CH4_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT - NA - 3 - 1 - read-only - - - - - CH4_INTSIGNAL_ENABLE0 - NA - 0x490 - 0x20 - 0xFA3F7FFB - - - CH4_ENABLE_BLOCK_TFR_DONE_INTSIGNAL - NA - 0 - 1 - read-write - - - CH4_ENABLE_DMA_TFR_DONE_INTSIGNAL - NA - 1 - 1 - read-write - - - CH4_ENABLE_SRC_TRANSCOMP_INTSIGNAL - NA - 3 - 1 - read-write - - - CH4_ENABLE_DST_TRANSCOMP_INTSIGNAL - NA - 4 - 1 - read-write - - - CH4_ENABLE_SRC_DEC_ERR_INTSIGNAL - NA - 5 - 1 - read-write - - - CH4_ENABLE_DST_DEC_ERR_INTSIGNAL - NA - 6 - 1 - read-write - - - CH4_ENABLE_SRC_SLV_ERR_INTSIGNAL - NA - 7 - 1 - read-write - - - CH4_ENABLE_DST_SLV_ERR_INTSIGNAL - NA - 8 - 1 - read-write - - - CH4_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL - NA - 9 - 1 - read-write - - - CH4_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL - NA - 10 - 1 - read-write - - - CH4_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL - NA - 11 - 1 - read-write - - - CH4_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL - NA - 12 - 1 - read-write - - - CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL - NA - 13 - 1 - read-write - - - CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL - NA - 14 - 1 - read-write - - - CH4_ENABLE_SLVIF_DEC_ERR_INTSIGNAL - NA - 16 - 1 - read-write - - - CH4_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL - NA - 17 - 1 - read-write - - - CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL - NA - 18 - 1 - read-write - - - CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL - NA - 19 - 1 - read-write - - - CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL - NA - 20 - 1 - read-write - - - CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL - NA - 21 - 1 - read-write - - - CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL - NA - 25 - 1 - read-only - - - CH4_ENABLE_CH_LOCK_CLEARED_INTSIGNAL - NA - 27 - 1 - read-write - - - CH4_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL - NA - 28 - 1 - read-write - - - CH4_ENABLE_CH_SUSPENDED_INTSIGNAL - NA - 29 - 1 - read-write - - - CH4_ENABLE_CH_DISABLED_INTSIGNAL - NA - 30 - 1 - read-write - - - CH4_ENABLE_CH_ABORTED_INTSIGNAL - NA - 31 - 1 - read-write - - - - - CH4_INTSIGNAL_ENABLE1 - NA - 0x494 - 0x20 - 0x0000000F - - - CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL - NA - 0 - 1 - read-only - - - CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL - NA - 1 - 1 - read-only - - - CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL - NA - 2 - 1 - read-only - - - CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL - NA - 3 - 1 - read-only - - - - - CH4_INTCLEAR0 - NA - 0x498 - 0x20 - - - CH4_CLEAR_BLOCK_TFR_DONE_INTSTAT - NA - 0 - 1 - write-only - - - CH4_CLEAR_DMA_TFR_DONE_INTSTAT - NA - 1 - 1 - write-only - - - CH4_CLEAR_SRC_TRANSCOMP_INTSTAT - NA - 3 - 1 - write-only - - - CH4_CLEAR_DST_TRANSCOMP_INTSTAT - NA - 4 - 1 - write-only - - - CH4_CLEAR_SRC_DEC_ERR_INTSTAT - NA - 5 - 1 - write-only - - - CH4_CLEAR_DST_DEC_ERR_INTSTAT - NA - 6 - 1 - write-only - - - CH4_CLEAR_SRC_SLV_ERR_INTSTAT - NA - 7 - 1 - write-only - - - CH4_CLEAR_DST_SLV_ERR_INTSTAT - NA - 8 - 1 - write-only - - - CH4_CLEAR_LLI_RD_DEC_ERR_INTSTAT - NA - 9 - 1 - write-only - - - CH4_CLEAR_LLI_WR_DEC_ERR_INTSTAT - NA - 10 - 1 - write-only - - - CH4_CLEAR_LLI_RD_SLV_ERR_INTSTAT - NA - 11 - 1 - write-only - - - CH4_CLEAR_LLI_WR_SLV_ERR_INTSTAT - NA - 12 - 1 - write-only - - - CH4_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT - NA - 13 - 1 - write-only - - - CH4_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT - NA - 14 - 1 - write-only - - - CH4_CLEAR_SLVIF_DEC_ERR_INTSTAT - NA - 16 - 1 - write-only - - - CH4_CLEAR_SLVIF_WR2RO_ERR_INTSTAT - NA - 17 - 1 - write-only - - - CH4_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT - NA - 18 - 1 - write-only - - - CH4_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT - NA - 19 - 1 - write-only - - - CH4_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT - NA - 20 - 1 - write-only - - - CH4_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT - NA - 21 - 1 - write-only - - - CH4_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT - NA - 25 - 1 - write-only - - - CH4_CLEAR_CH_LOCK_CLEARED_INTSTAT - NA - 27 - 1 - write-only - - - CH4_CLEAR_CH_SRC_SUSPENDED_INTSTAT - NA - 28 - 1 - write-only - - - CH4_CLEAR_CH_SUSPENDED_INTSTAT - NA - 29 - 1 - write-only - - - CH4_CLEAR_CH_DISABLED_INTSTAT - NA - 30 - 1 - write-only - - - CH4_CLEAR_CH_ABORTED_INTSTAT - NA - 31 - 1 - write-only - - - - - CH4_INTCLEAR1 - NA - 0x49C - 0x20 - - - CH4_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT - NA - 0 - 1 - write-only - - - CH4_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT - NA - 1 - 1 - write-only - - - CH4_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT - NA - 2 - 1 - write-only - - - CH4_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT - NA - 3 - 1 - write-only - - - - - - - DS - Digital Signature - DS - 0x50094000 - - 0x0 - 0xA5C - registers - - - - 128 - 0x4 - Y_MEM[%s] - memory that stores Y - 0x0 - 0x20 - - - 128 - 0x4 - M_MEM[%s] - memory that stores M - 0x200 - 0x20 - - - 128 - 0x4 - RB_MEM[%s] - memory that stores Rb - 0x400 - 0x20 - - - 12 - 0x4 - BOX_MEM[%s] - memory that stores BOX - 0x600 - 0x20 - - - 4 - 0x4 - IV_MEM[%s] - memory that stores IV - 0x630 - 0x20 - - - 128 - 0x4 - X_MEM[%s] - memory that stores X - 0x800 - 0x20 - - - 128 - 0x4 - Z_MEM[%s] - memory that stores Z - 0xA00 - 0x20 - - - SET_START - DS start control register - 0xE00 - 0x20 - - - SET_START - set this bit to start DS operation. - 0 - 1 - write-only - - - - - SET_CONTINUE - DS continue control register - 0xE04 - 0x20 - - - SET_CONTINUE - set this bit to continue DS operation. - 0 - 1 - write-only - - - - - SET_FINISH - DS finish control register - 0xE08 - 0x20 - - - SET_FINISH - Set this bit to finish DS process. - 0 - 1 - write-only - - - - - QUERY_BUSY - DS query busy register - 0xE0C - 0x20 - - - QUERY_BUSY - digital signature state. 1'b0: idle, 1'b1: busy - 0 - 1 - read-only - - - - - QUERY_KEY_WRONG - DS query key-wrong counter register - 0xE10 - 0x20 - - - QUERY_KEY_WRONG - digital signature key wrong counter - 0 - 4 - read-only - - - - - QUERY_CHECK - DS query check result register - 0xE14 - 0x20 - - - MD_ERROR - MD checkout result. 1'b0: MD check pass, 1'b1: MD check fail - 0 - 1 - read-only - - - PADDING_BAD - padding checkout result. 1'b0: a good padding, 1'b1: a bad padding - 1 - 1 - read-only - - - - - DATE - DS version control register - 0xE20 - 0x20 - 0x20200618 - - - DATE - ds version information - 0 - 30 - read-write - - - - - - - MIPI_DSI_BRIDGE - MIPI Camera Interface Bridge - DSI_BRG - 0x500A0800 - - 0x0 - 0x94 - registers - - - DSI_BRIDGE - 86 - - - - CLK_EN - dsi bridge clk control register - 0x0 - 0x20 - - - CLK_EN - this bit configures force_on of dsi_bridge register clock gate - 0 - 1 - read-write - - - - - EN - dsi bridge en register - 0x4 - 0x20 - - - DSI_EN - this bit configures module enable of dsi_bridge. 0: disable, 1: enable - 0 - 1 - read-write - - - - - DMA_REQ_CFG - dsi bridge dma burst len register - 0x8 - 0x20 - 0x00000080 - - - DMA_BURST_LEN - this field configures the num of 64-bit in one dma burst transfer, valid only when dsi_bridge as flow controller - 0 - 12 - read-write - - - - - RAW_NUM_CFG - dsi bridge raw number control register - 0xC - 0x20 - 0x00038400 - - - RAW_NUM_TOTAL - this field configures number of total pix bits/64 - 0 - 22 - read-write - - - UNALIGN_64BIT_EN - this field configures whether the total pix bits is a multiple of 64bits. 0: align to 64-bit, 1: unalign to 64-bit - 22 - 1 - read-write - - - RAW_NUM_TOTAL_SET - this bit configures enable of reload reg_raw_num_total to internal cnt. 0: disable, 1: enable. valid only when dsi_bridge as flow controller - 31 - 1 - write-only - - - - - RAW_BUF_CREDIT_CTL - dsi bridge credit register - 0x10 - 0x20 - 0x03200400 - - - CREDIT_THRD - this field configures the threshold whether dsi_bridge fifo can receive one more 64-bit, valid only when dsi_bridge as flow controller - 0 - 15 - read-write - - - CREDIT_BURST_THRD - this field configures the threshold whether dsi_bridge fifo can receive one more dma burst, valid only when dsi_bridge as flow controller - 16 - 15 - read-write - - - CREDIT_RESET - this bit configures internal credit cnt clear, 0: non, 1: reset. valid only when dsi_bridge as flow controller - 31 - 1 - read-write - - - - - FIFO_FLOW_STATUS - dsi bridge raw buffer depth register - 0x14 - 0x20 - - - RAW_BUF_DEPTH - this field configures the depth of dsi_bridge fifo depth - 0 - 14 - read-only - - - - - PIXEL_TYPE - dsi bridge dpi type control register - 0x18 - 0x20 - - - RAW_TYPE - this field configures the pixel type. 0: rgb888, 1:rgb666, 2:rgb565 - 0 - 4 - read-write - - - DPI_CONFIG - this field configures the pixel arrange type of dpi interface - 4 - 2 - read-write - - - DATA_IN_TYPE - input data type, 0: rgb, 1: yuv - 6 - 1 - read-write - - - - - DMA_BLOCK_INTERVAL - dsi bridge dma block interval control register - 0x1C - 0x20 - 0x30002409 - - - DMA_BLOCK_SLOT - this field configures the max block_slot_cnt - 0 - 10 - read-write - - - DMA_BLOCK_INTERVAL - this field configures the max block_interval_cnt, block_interval_cnt increased by 1 when block_slot_cnt if full - 10 - 18 - read-write - - - RAW_NUM_TOTAL_AUTO_RELOAD - this bit configures enable of auto reload reg_raw_num_total, 0: disable, 1: enable - 28 - 1 - read-write - - - EN - this bit configures enable of interval between dma block transfer, 0: disable, 1: enable - 29 - 1 - read-write - - - - - DMA_REQ_INTERVAL - dsi bridge dma req interval control register - 0x20 - 0x20 - 0x00000001 - - - DMA_REQ_INTERVAL - this field configures the interval between dma req events - 0 - 16 - read-write - - - - - DPI_LCD_CTL - dsi bridge dpi signal control register - 0x24 - 0x20 - - - DPISHUTDN - this bit configures dpishutdn signal in dpi interface - 0 - 1 - read-write - - - DPICOLORM - this bit configures dpicolorm signal in dpi interface - 1 - 1 - read-write - - - DPIUPDATECFG - this bit configures dpiupdatecfg signal in dpi interface - 2 - 1 - read-write - - - - - DPI_RSV_DPI_DATA - dsi bridge dpi reserved data register - 0x28 - 0x20 - 0x00003FFF - - - DPI_RSV_DATA - this field controls the pixel data sent to dsi_host when dsi_bridge fifo underflow - 0 - 30 - read-write - - - - - DPI_V_CFG0 - dsi bridge dpi v config register 0 - 0x30 - 0x20 - 0x01E0020D - - - VTOTAL - this field configures the total length of one frame (by line) for dpi output, must meet: reg_vtotal > reg_vdisp+reg_vsync+reg_vbank - 0 - 12 - read-write - - - VDISP - this field configures the length of valid line (by line) for dpi output - 16 - 12 - read-write - - - - - DPI_V_CFG1 - dsi bridge dpi v config register 1 - 0x34 - 0x20 - 0x00020021 - - - VBANK - this field configures the length between vsync and valid line (by line) for dpi output - 0 - 12 - read-write - - - VSYNC - this field configures the length of vsync (by line) for dpi output - 16 - 12 - read-write - - - - - DPI_H_CFG0 - dsi bridge dpi h config register 0 - 0x38 - 0x20 - 0x02800320 - - - HTOTAL - this field configures the total length of one line (by pixel num) for dpi output, must meet: reg_htotal > reg_hdisp+reg_hsync+reg_hbank - 0 - 12 - read-write - - - HDISP - this field configures the length of valid pixel data (by pixel num) for dpi output - 16 - 12 - read-write - - - - - DPI_H_CFG1 - dsi bridge dpi h config register 1 - 0x3C - 0x20 - 0x00600030 - - - HBANK - this field configures the length between hsync and pixel data valid (by pixel num) for dpi output - 0 - 12 - read-write - - - HSYNC - this field configures the length of hsync (by pixel num) for dpi output - 16 - 12 - read-write - - - - - DPI_MISC_CONFIG - dsi_bridge dpi misc config register - 0x40 - 0x20 - 0x000019D0 - - - DPI_EN - this bit configures enable of dpi output, 0: disable, 1: enable - 0 - 1 - read-write - - - FIFO_UNDERRUN_DISCARD_VCNT - this field configures the underrun interrupt musk, when underrun occurs and line cnt is less then this field - 4 - 12 - read-write - - - - - DPI_CONFIG_UPDATE - dsi_bridge dpi config update register - 0x44 - 0x20 - - - DPI_CONFIG_UPDATE - write 1 to this bit to update dpi config register MIPI_DSI_BRG_DPI_* - 0 - 1 - write-only - - - - - INT_ENA - dsi_bridge interrupt enable register - 0x50 - 0x20 - - - UNDERRUN_INT_ENA - write 1 to enables dpi_underrun_int_st field of MIPI_DSI_BRG_INT_ST_REG controlled by dpi_underrun interrupt signal - 0 - 1 - read-write - - - - - INT_CLR - dsi_bridge interrupt clear register - 0x54 - 0x20 - - - UNDERRUN_INT_CLR - write 1 to this bit to clear dpi_underrun_int_raw field of MIPI_DSI_BRG_INT_RAW_REG - 0 - 1 - write-only - - - - - INT_RAW - dsi_bridge raw interrupt register - 0x58 - 0x20 - - - UNDERRUN_INT_RAW - the raw interrupt status of dpi_underrun - 0 - 1 - read-write - - - - - INT_ST - dsi_bridge masked interrupt register - 0x5C - 0x20 - - - UNDERRUN_INT_ST - the masked interrupt status of dpi_underrun - 0 - 1 - read-only - - - - - HOST_BIST_CTL - dsi_bridge host bist control register - 0x60 - 0x20 - - - BISTOK - bistok - 0 - 1 - read-only - - - BISTON - biston - 1 - 1 - read-write - - - - - HOST_TRIGGER_REV - dsi_bridge host trigger reverse control register - 0x64 - 0x20 - - - TX_TRIGGER_REV_EN - tx_trigger reverse. 0: disable, 1: enable - 0 - 1 - read-write - - - RX_TRIGGER_REV_EN - rx_trigger reverse. 0: disable, 1: enable - 1 - 1 - read-write - - - - - BLK_RAW_NUM_CFG - dsi_bridge block raw number control register - 0x68 - 0x20 - 0x00038400 - - - BLK_RAW_NUM_TOTAL - this field configures number of total block pix bits/64 - 0 - 22 - read-write - - - BLK_RAW_NUM_TOTAL_SET - write 1 to reload reg_blk_raw_num_total to internal cnt - 31 - 1 - write-only - - - - - DMA_FRAME_INTERVAL - dsi_bridge dam frame interval control register - 0x6C - 0x20 - 0x20002409 - - - DMA_FRAME_SLOT - this field configures the max frame_slot_cnt - 0 - 10 - read-write - - - DMA_FRAME_INTERVAL - this field configures the max frame_interval_cnt, frame_interval_cnt increased by 1 when frame_slot_cnt if full - 10 - 18 - read-write - - - DMA_MULTIBLK_EN - this bit configures enable multi-blk transfer, 0: disable, 1: enable - 28 - 1 - read-write - - - EN - this bit configures enable interval between frame transfer, 0: disable, 1: enable - 29 - 1 - read-write - - - - - MEM_AUX_CTRL - dsi_bridge mem aux control register - 0x70 - 0x20 - 0x00001320 - - - DSI_MEM_AUX_CTRL - this field configures dsi_bridge fifo memory aux ctrl - 0 - 14 - read-write - - - - - RDN_ECO_CS - dsi_bridge rdn eco cs register - 0x74 - 0x20 - - - RDN_ECO_EN - rdn_eco_en - 0 - 1 - read-write - - - RDN_ECO_RESULT - rdn_eco_result - 1 - 1 - read-only - - - - - RDN_ECO_LOW - dsi_bridge rdn eco all low register - 0x78 - 0x20 - - - RDN_ECO_LOW - rdn_eco_low - 0 - 32 - read-write - - - - - RDN_ECO_HIGH - dsi_bridge rdn eco all high register - 0x7C - 0x20 - 0xFFFFFFFF - - - RDN_ECO_HIGH - rdn_eco_high - 0 - 32 - read-write - - - - - HOST_CTRL - dsi_bridge host control register - 0x80 - 0x20 - 0x00000001 - - - DSI_CFG_REF_CLK_EN - this bit configures the clk enable refclk and cfg_clk of dsi_host. 0: disable, 1: enable - 0 - 1 - read-write - - - - - MEM_CLK_CTRL - dsi_bridge mem force on control register - 0x84 - 0x20 - - - DSI_BRIDGE_MEM_CLK_FORCE_ON - this bit configures the clock force on of dsi_bridge fifo memory. 0: disable, 1: force on - 0 - 1 - read-write - - - DSI_MEM_CLK_FORCE_ON - this bit configures the clock force on of dpi fifo memory. 0: disable, 1: force on - 1 - 1 - read-write - - - - - DMA_FLOW_CTRL - dsi_bridge dma flow controller register - 0x88 - 0x20 - 0x00000011 - - - DSI_DMA_FLOW_CONTROLLER - this bit configures the flow controller, 0: dmac as flow controller, 1:dsi_bridge as flow controller - 0 - 1 - read-write - - - DMA_FLOW_MULTIBLK_NUM - this field configures the num of blocks when multi-blk is enable and dmac as flow controller - 4 - 4 - read-write - - - - - RAW_BUF_ALMOST_EMPTY_THRD - dsi_bridge buffer empty threshold register - 0x8C - 0x20 - 0x00000200 - - - DSI_RAW_BUF_ALMOST_EMPTY_THRD - this field configures the fifo almost empty threshold, is valid only when dmac as flow controller - 0 - 11 - read-write - - - - - YUV_CFG - dsi_bridge yuv format config register - 0x90 - 0x20 - - - PROTOCAL - this bit configures yuv protoocl, 0: bt.601, 1: bt.709 - 0 - 1 - read-write - - - YUV_PIX_ENDIAN - this bit configures yuv pixel endian, 0: y0u0y1v1y2u2y3v3, 1: y3u3y2v2y1u1y0v0 - 1 - 1 - read-write - - - YUV422_FORMAT - this field configures yuv422 store format, 0: yuyv, 1: yvyu, 2: uyvy, 3: vyuy - 2 - 2 - read-write - - - - - PHY_LP_LOOPBACK_CTRL - dsi phy lp_loopback test ctrl - 0x94 - 0x20 - - - PHY_LP_TXDATAESC_1 - txdataesc_1 ctrl when enable dsi phy lp_loopback_test - 0 - 8 - read-write - - - PHY_LP_TXREQUESTESC_1 - txrequestesc_1 ctrl when enable dsi phy lp_loopback_test - 8 - 1 - read-write - - - PHY_LP_TXVALIDESC_1 - txvalidesc_1 ctrl when enable dsi phy lp_loopback_test - 9 - 1 - read-write - - - PHY_LP_TXLPDTESC_1 - txlpdtesc_1 ctrl when enable dsi phy lp_loopback_test - 10 - 1 - read-write - - - PHY_LP_BASEDIR_1 - basedir_1 ctrl when enable dsi phy lp_loopback_test - 11 - 1 - read-write - - - PHY_LP_TXDATAESC_0 - txdataesc_0 ctrl when enable dsi phy lp_loopback_test - 16 - 8 - read-write - - - PHY_LP_TXREQUESTESC_0 - txrequestesc_0 ctrl when enable dsi phy lp_loopback_test - 24 - 1 - read-write - - - PHY_LP_TXVALIDESC_0 - txvalidesc_0 ctrl when enable dsi phy lp_loopback_test - 25 - 1 - read-write - - - PHY_LP_TXLPDTESC_0 - txlpdtesc_0 ctrl when enable dsi phy lp_loopback_test - 26 - 1 - read-write - - - PHY_LP_BASEDIR_0 - basedir_0 ctrl when enable dsi phy lp_loopback_test - 27 - 1 - read-write - - - PHY_LP_LOOPBACK_CHECK - dsi phy lp_loopback test start check - 28 - 1 - write-only - - - PHY_LP_LOOPBACK_CHECK_DONE - dsi phy lp_loopback test check done - 29 - 1 - read-only - - - PHY_LP_LOOPBACK_EN - dsi phy lp_loopback ctrl en - 30 - 1 - read-write - - - PHY_LP_LOOPBACK_OK - result of dsi phy lp_loopback test - 31 - 1 - read-only - - - - - PHY_HS_LOOPBACK_CTRL - dsi phy hp_loopback test ctrl - 0x98 - 0x20 - 0x00000200 - - - PHY_HS_TXDATAHS_1 - txdatahs_1 ctrl when enable dsi phy hs_loopback_test - 0 - 8 - read-write - - - PHY_HS_TXREQUESTDATAHS_1 - txrequestdatahs_1 ctrl when enable dsi phy hs_loopback_test - 8 - 1 - read-write - - - PHY_HS_BASEDIR_1 - basedir_1 ctrl when enable dsi phy hs_loopback_test - 9 - 1 - read-write - - - PHY_HS_TXDATAHS_0 - txdatahs_0 ctrl when enable dsi phy hs_loopback_test - 16 - 8 - read-write - - - PHY_HS_TXREQUESTDATAHS_0 - txrequestdatahs_0 ctrl when enable dsi phy hs_loopback_test - 24 - 1 - read-write - - - PHY_HS_BASEDIR_0 - basedir_0 ctrl when enable dsi phy hs_loopback_test - 25 - 1 - read-write - - - PHY_HS_TXREQUESTHSCLK - txrequesthsclk when enable dsi phy hs_loopback_test - 27 - 1 - read-write - - - PHY_HS_LOOPBACK_CHECK - dsi phy hs_loopback test start check - 28 - 1 - write-only - - - PHY_HS_LOOPBACK_CHECK_DONE - dsi phy hs_loopback test check done - 29 - 1 - read-only - - - PHY_HS_LOOPBACK_EN - dsi phy hs_loopback ctrl en - 30 - 1 - read-write - - - PHY_HS_LOOPBACK_OK - result of dsi phy hs_loopback test - 31 - 1 - read-only - - - - - PHY_LOOPBACK_CNT - loopback test cnt - 0x9C - 0x20 - 0x00400040 - - - PHY_HS_CHECK_CNT_TH - hs_loopback test check cnt - 0 - 8 - read-write - - - PHY_LP_CHECK_CNT_TH - lp_loopback test check cnt - 16 - 8 - read-write - - - - - - - MIPI_DSI_HOST - MIPI Display Interface Host - DSI_HOST - 0x500A0000 - - 0x0 - 0x128 - registers - - - DSI - 88 - - - - VERSION - NA - 0x0 - 0x20 - 0x3134312A - - - VERSION - NA - 0 - 32 - read-only - - - - - PWR_UP - NA - 0x4 - 0x20 - - - SHUTDOWNZ - NA - 0 - 1 - read-write - - - - - CLKMGR_CFG - NA - 0x8 - 0x20 - - - TX_ESC_CLK_DIVISION - NA - 0 - 8 - read-write - - - TO_CLK_DIVISION - NA - 8 - 8 - read-write - - - - - DPI_VCID - NA - 0xC - 0x20 - - - DPI_VCID - NA - 0 - 2 - read-write - - - - - DPI_COLOR_CODING - NA - 0x10 - 0x20 - - - DPI_COLOR_CODING - NA - 0 - 4 - read-write - - - LOOSELY18_EN - NA - 8 - 1 - read-write - - - - - DPI_CFG_POL - NA - 0x14 - 0x20 - - - DATAEN_ACTIVE_LOW - NA - 0 - 1 - read-write - - - VSYNC_ACTIVE_LOW - NA - 1 - 1 - read-write - - - HSYNC_ACTIVE_LOW - NA - 2 - 1 - read-write - - - SHUTD_ACTIVE_LOW - NA - 3 - 1 - read-write - - - COLORM_ACTIVE_LOW - NA - 4 - 1 - read-write - - - - - DPI_LP_CMD_TIM - NA - 0x18 - 0x20 - - - INVACT_LPCMD_TIME - NA - 0 - 8 - read-write - - - OUTVACT_LPCMD_TIME - NA - 16 - 8 - read-write - - - - - DBI_VCID - NA - 0x1C - 0x20 - - - DBI_VCID - NA - 0 - 2 - read-write - - - - - DBI_CFG - NA - 0x20 - 0x20 - - - IN_DBI_CONF - NA - 0 - 4 - read-write - - - OUT_DBI_CONF - NA - 8 - 4 - read-write - - - LUT_SIZE_CONF - NA - 16 - 2 - read-write - - - - - DBI_PARTITIONING_EN - NA - 0x24 - 0x20 - - - PARTITIONING_EN - NA - 0 - 1 - read-write - - - - - DBI_CMDSIZE - NA - 0x28 - 0x20 - - - WR_CMD_SIZE - NA - 0 - 16 - read-write - - - ALLOWED_CMD_SIZE - NA - 16 - 16 - read-write - - - - - PCKHDL_CFG - NA - 0x2C - 0x20 - - - EOTP_TX_EN - NA - 0 - 1 - read-write - - - EOTP_RX_EN - NA - 1 - 1 - read-write - - - BTA_EN - NA - 2 - 1 - read-write - - - ECC_RX_EN - NA - 3 - 1 - read-write - - - CRC_RX_EN - NA - 4 - 1 - read-write - - - EOTP_TX_LP_EN - NA - 5 - 1 - read-write - - - - - GEN_VCID - NA - 0x30 - 0x20 - - - RX - NA - 0 - 2 - read-write - - - TEAR_AUTO - NA - 8 - 2 - read-write - - - TX_AUTO - NA - 16 - 2 - read-write - - - - - MODE_CFG - NA - 0x34 - 0x20 - 0x00000001 - - - CMD_VIDEO_MODE - NA - 0 - 1 - read-write - - - - - VID_MODE_CFG - NA - 0x38 - 0x20 - - - VID_MODE_TYPE - NA - 0 - 2 - read-write - - - LP_VSA_EN - NA - 8 - 1 - read-write - - - LP_VBP_EN - NA - 9 - 1 - read-write - - - LP_VFP_EN - NA - 10 - 1 - read-write - - - LP_VACT_EN - NA - 11 - 1 - read-write - - - LP_HBP_EN - NA - 12 - 1 - read-write - - - LP_HFP_EN - NA - 13 - 1 - read-write - - - FRAME_BTA_ACK_EN - NA - 14 - 1 - read-write - - - LP_CMD_EN - NA - 15 - 1 - read-write - - - VPG_EN - NA - 16 - 1 - read-write - - - VPG_MODE - NA - 20 - 1 - read-write - - - VPG_ORIENTATION - NA - 24 - 1 - read-write - - - - - VID_PKT_SIZE - NA - 0x3C - 0x20 - - - VID_PKT_SIZE - NA - 0 - 14 - read-write - - - - - VID_NUM_CHUNKS - NA - 0x40 - 0x20 - - - VID_NUM_CHUNKS - NA - 0 - 13 - read-write - - - - - VID_NULL_SIZE - NA - 0x44 - 0x20 - - - VID_NULL_SIZE - NA - 0 - 13 - read-write - - - - - VID_HSA_TIME - NA - 0x48 - 0x20 - - - VID_HSA_TIME - NA - 0 - 12 - read-write - - - - - VID_HBP_TIME - NA - 0x4C - 0x20 - - - VID_HBP_TIME - NA - 0 - 12 - read-write - - - - - VID_HLINE_TIME - NA - 0x50 - 0x20 - - - VID_HLINE_TIME - NA - 0 - 15 - read-write - - - - - VID_VSA_LINES - NA - 0x54 - 0x20 - - - VSA_LINES - NA - 0 - 10 - read-write - - - - - VID_VBP_LINES - NA - 0x58 - 0x20 - - - VBP_LINES - NA - 0 - 10 - read-write - - - - - VID_VFP_LINES - NA - 0x5C - 0x20 - - - VFP_LINES - NA - 0 - 10 - read-write - - - - - VID_VACTIVE_LINES - NA - 0x60 - 0x20 - - - V_ACTIVE_LINES - NA - 0 - 14 - read-write - - - - - EDPI_CMD_SIZE - NA - 0x64 - 0x20 - - - EDPI_ALLOWED_CMD_SIZE - NA - 0 - 16 - read-write - - - - - CMD_MODE_CFG - NA - 0x68 - 0x20 - - - TEAR_FX_EN - NA - 0 - 1 - read-write - - - ACK_RQST_EN - NA - 1 - 1 - read-write - - - GEN_SW_0P_TX - NA - 8 - 1 - read-write - - - GEN_SW_1P_TX - NA - 9 - 1 - read-write - - - GEN_SW_2P_TX - NA - 10 - 1 - read-write - - - GEN_SR_0P_TX - NA - 11 - 1 - read-write - - - GEN_SR_1P_TX - NA - 12 - 1 - read-write - - - GEN_SR_2P_TX - NA - 13 - 1 - read-write - - - GEN_LW_TX - NA - 14 - 1 - read-write - - - DCS_SW_0P_TX - NA - 16 - 1 - read-write - - - DCS_SW_1P_TX - NA - 17 - 1 - read-write - - - DCS_SR_0P_TX - NA - 18 - 1 - read-write - - - DCS_LW_TX - NA - 19 - 1 - read-write - - - MAX_RD_PKT_SIZE - NA - 24 - 1 - read-write - - - - - GEN_HDR - NA - 0x6C - 0x20 - - - GEN_DT - NA - 0 - 6 - read-write - - - GEN_VC - NA - 6 - 2 - read-write - - - GEN_WC_LSBYTE - NA - 8 - 8 - read-write - - - GEN_WC_MSBYTE - NA - 16 - 8 - read-write - - - - - GEN_PLD_DATA - NA - 0x70 - 0x20 - - - GEN_PLD_B1 - NA - 0 - 8 - read-write - - - GEN_PLD_B2 - NA - 8 - 8 - read-write - - - GEN_PLD_B3 - NA - 16 - 8 - read-write - - - GEN_PLD_B4 - NA - 24 - 8 - read-write - - - - - CMD_PKT_STATUS - NA - 0x74 - 0x20 - 0x00050015 - - - GEN_CMD_EMPTY - NA - 0 - 1 - read-only - - - GEN_CMD_FULL - NA - 1 - 1 - read-only - - - GEN_PLD_W_EMPTY - NA - 2 - 1 - read-only - - - GEN_PLD_W_FULL - NA - 3 - 1 - read-only - - - GEN_PLD_R_EMPTY - NA - 4 - 1 - read-only - - - GEN_PLD_R_FULL - NA - 5 - 1 - read-only - - - GEN_RD_CMD_BUSY - NA - 6 - 1 - read-only - - - GEN_BUFF_CMD_EMPTY - NA - 16 - 1 - read-only - - - GEN_BUFF_CMD_FULL - NA - 17 - 1 - read-only - - - GEN_BUFF_PLD_EMPTY - NA - 18 - 1 - read-only - - - GEN_BUFF_PLD_FULL - NA - 19 - 1 - read-only - - - - - TO_CNT_CFG - NA - 0x78 - 0x20 - - - LPRX_TO_CNT - NA - 0 - 16 - read-write - - - HSTX_TO_CNT - NA - 16 - 16 - read-write - - - - - HS_RD_TO_CNT - NA - 0x7C - 0x20 - - - HS_RD_TO_CNT - NA - 0 - 16 - read-write - - - - - LP_RD_TO_CNT - NA - 0x80 - 0x20 - - - LP_RD_TO_CNT - NA - 0 - 16 - read-write - - - - - HS_WR_TO_CNT - NA - 0x84 - 0x20 - - - HS_WR_TO_CNT - NA - 0 - 16 - read-write - - - - - LP_WR_TO_CNT - NA - 0x88 - 0x20 - - - LP_WR_TO_CNT - NA - 0 - 16 - read-write - - - - - BTA_TO_CNT - NA - 0x8C - 0x20 - - - BTA_TO_CNT - NA - 0 - 16 - read-write - - - - - SDF_3D - NA - 0x90 - 0x20 - - - MODE_3D - NA - 0 - 2 - read-write - - - FORMAT_3D - NA - 2 - 2 - read-write - - - SECOND_VSYNC - NA - 4 - 1 - read-write - - - RIGHT_FIRST - NA - 5 - 1 - read-write - - - SEND_3D_CFG - NA - 16 - 1 - read-write - - - - - LPCLK_CTRL - NA - 0x94 - 0x20 - - - PHY_TXREQUESTCLKHS - NA - 0 - 1 - read-write - - - AUTO_CLKLANE_CTRL - NA - 1 - 1 - read-write - - - - - PHY_TMR_LPCLK_CFG - NA - 0x98 - 0x20 - - - PHY_CLKLP2HS_TIME - NA - 0 - 10 - read-write - - - PHY_CLKHS2LP_TIME - NA - 16 - 10 - read-write - - - - - PHY_TMR_CFG - NA - 0x9C - 0x20 - - - PHY_LP2HS_TIME - NA - 0 - 10 - read-write - - - PHY_HS2LP_TIME - NA - 16 - 10 - read-write - - - - - PHY_RSTZ - NA - 0xA0 - 0x20 - - - PHY_SHUTDOWNZ - NA - 0 - 1 - read-write - - - PHY_RSTZ - NA - 1 - 1 - read-write - - - PHY_ENABLECLK - NA - 2 - 1 - read-write - - - PHY_FORCEPLL - NA - 3 - 1 - read-write - - - - - PHY_IF_CFG - NA - 0xA4 - 0x20 - 0x00000001 - - - N_LANES - NA - 0 - 2 - read-write - - - PHY_STOP_WAIT_TIME - NA - 8 - 8 - read-write - - - - - PHY_ULPS_CTRL - NA - 0xA8 - 0x20 - - - PHY_TXREQULPSCLK - NA - 0 - 1 - read-write - - - PHY_TXEXITULPSCLK - NA - 1 - 1 - read-write - - - PHY_TXREQULPSLAN - NA - 2 - 1 - read-write - - - PHY_TXEXITULPSLAN - NA - 3 - 1 - read-write - - - - - PHY_TX_TRIGGERS - NA - 0xAC - 0x20 - - - PHY_TX_TRIGGERS - NA - 0 - 4 - read-write - - - - - PHY_STATUS - NA - 0xB0 - 0x20 - 0x00000140 - - - PHY_LOCK - NA - 0 - 1 - read-only - - - PHY_DIRECTION - NA - 1 - 1 - read-only - - - PHY_STOPSTATECLKLANE - NA - 2 - 1 - read-only - - - PHY_ULPSACTIVENOTCLK - NA - 3 - 1 - read-only - - - PHY_STOPSTATE0LANE - NA - 4 - 1 - read-only - - - PHY_ULPSACTIVENOT0LANE - NA - 5 - 1 - read-only - - - PHY_RXULPSESC0LANE - NA - 6 - 1 - read-only - - - PHY_STOPSTATE1LANE - NA - 7 - 1 - read-only - - - PHY_ULPSACTIVENOT1LANE - NA - 8 - 1 - read-only - - - - - PHY_TST_CTRL0 - NA - 0xB4 - 0x20 - 0x00000001 - - - PHY_TESTCLR - NA - 0 - 1 - read-write - - - PHY_TESTCLK - NA - 1 - 1 - read-write - - - - - PHY_TST_CTRL1 - NA - 0xB8 - 0x20 - - - PHY_TESTDIN - NA - 0 - 8 - read-write - - - PHT_TESTDOUT - NA - 8 - 8 - read-only - - - PHY_TESTEN - NA - 16 - 1 - read-write - - - - - INT_ST0 - NA - 0xBC - 0x20 - - - ACK_WITH_ERR_0 - NA - 0 - 1 - read-only - - - ACK_WITH_ERR_1 - NA - 1 - 1 - read-only - - - ACK_WITH_ERR_2 - NA - 2 - 1 - read-only - - - ACK_WITH_ERR_3 - NA - 3 - 1 - read-only - - - ACK_WITH_ERR_4 - NA - 4 - 1 - read-only - - - ACK_WITH_ERR_5 - NA - 5 - 1 - read-only - - - ACK_WITH_ERR_6 - NA - 6 - 1 - read-only - - - ACK_WITH_ERR_7 - NA - 7 - 1 - read-only - - - ACK_WITH_ERR_8 - NA - 8 - 1 - read-only - - - ACK_WITH_ERR_9 - NA - 9 - 1 - read-only - - - ACK_WITH_ERR_10 - NA - 10 - 1 - read-only - - - ACK_WITH_ERR_11 - NA - 11 - 1 - read-only - - - ACK_WITH_ERR_12 - NA - 12 - 1 - read-only - - - ACK_WITH_ERR_13 - NA - 13 - 1 - read-only - - - ACK_WITH_ERR_14 - NA - 14 - 1 - read-only - - - ACK_WITH_ERR_15 - NA - 15 - 1 - read-only - - - DPHY_ERRORS_0 - NA - 16 - 1 - read-only - - - DPHY_ERRORS_1 - NA - 17 - 1 - read-only - - - DPHY_ERRORS_2 - NA - 18 - 1 - read-only - - - DPHY_ERRORS_3 - NA - 19 - 1 - read-only - - - DPHY_ERRORS_4 - NA - 20 - 1 - read-only - - - - - INT_ST1 - NA - 0xC0 - 0x20 - - - TO_HS_TX - NA - 0 - 1 - read-only - - - TO_LP_RX - NA - 1 - 1 - read-only - - - ECC_SINGLE_ERR - NA - 2 - 1 - read-only - - - ECC_MILTI_ERR - NA - 3 - 1 - read-only - - - CRC_ERR - NA - 4 - 1 - read-only - - - PKT_SIZE_ERR - NA - 5 - 1 - read-only - - - EOPT_ERR - NA - 6 - 1 - read-only - - - DPI_PLD_WR_ERR - NA - 7 - 1 - read-only - - - GEN_CMD_WR_ERR - NA - 8 - 1 - read-only - - - GEN_PLD_WR_ERR - NA - 9 - 1 - read-only - - - GEN_PLD_SEND_ERR - NA - 10 - 1 - read-only - - - GEN_PLD_RD_ERR - NA - 11 - 1 - read-only - - - GEN_PLD_RECEV_ERR - NA - 12 - 1 - read-only - - - DPI_BUFF_PLD_UNDER - NA - 19 - 1 - read-only - - - - - INT_MSK0 - NA - 0xC4 - 0x20 - - - MASK_ACK_WITH_ERR_0 - NA - 0 - 1 - read-write - - - MASK_ACK_WITH_ERR_1 - NA - 1 - 1 - read-write - - - MASK_ACK_WITH_ERR_2 - NA - 2 - 1 - read-write - - - MASK_ACK_WITH_ERR_3 - NA - 3 - 1 - read-write - - - MASK_ACK_WITH_ERR_4 - NA - 4 - 1 - read-write - - - MASK_ACK_WITH_ERR_5 - NA - 5 - 1 - read-write - - - MASK_ACK_WITH_ERR_6 - NA - 6 - 1 - read-write - - - MASK_ACK_WITH_ERR_7 - NA - 7 - 1 - read-write - - - MASK_ACK_WITH_ERR_8 - NA - 8 - 1 - read-write - - - MASK_ACK_WITH_ERR_9 - NA - 9 - 1 - read-write - - - MASK_ACK_WITH_ERR_10 - NA - 10 - 1 - read-write - - - MASK_ACK_WITH_ERR_11 - NA - 11 - 1 - read-write - - - MASK_ACK_WITH_ERR_12 - NA - 12 - 1 - read-write - - - MASK_ACK_WITH_ERR_13 - NA - 13 - 1 - read-write - - - MASK_ACK_WITH_ERR_14 - NA - 14 - 1 - read-write - - - MASK_ACK_WITH_ERR_15 - NA - 15 - 1 - read-write - - - MASK_DPHY_ERRORS_0 - NA - 16 - 1 - read-write - - - MASK_DPHY_ERRORS_1 - NA - 17 - 1 - read-write - - - MASK_DPHY_ERRORS_2 - NA - 18 - 1 - read-write - - - MASK_DPHY_ERRORS_3 - NA - 19 - 1 - read-write - - - MASK_DPHY_ERRORS_4 - NA - 20 - 1 - read-write - - - - - INT_MSK1 - NA - 0xC8 - 0x20 - - - MASK_TO_HS_TX - NA - 0 - 1 - read-write - - - MASK_TO_LP_RX - NA - 1 - 1 - read-write - - - MASK_ECC_SINGLE_ERR - NA - 2 - 1 - read-write - - - MASK_ECC_MILTI_ERR - NA - 3 - 1 - read-write - - - MASK_CRC_ERR - NA - 4 - 1 - read-write - - - MASK_PKT_SIZE_ERR - NA - 5 - 1 - read-write - - - MASK_EOPT_ERR - NA - 6 - 1 - read-write - - - MASK_DPI_PLD_WR_ERR - NA - 7 - 1 - read-write - - - MASK_GEN_CMD_WR_ERR - NA - 8 - 1 - read-write - - - MASK_GEN_PLD_WR_ERR - NA - 9 - 1 - read-write - - - MASK_GEN_PLD_SEND_ERR - NA - 10 - 1 - read-write - - - MASK_GEN_PLD_RD_ERR - NA - 11 - 1 - read-write - - - MASK_GEN_PLD_RECEV_ERR - NA - 12 - 1 - read-write - - - MASK_DPI_BUFF_PLD_UNDER - NA - 19 - 1 - read-write - - - - - PHY_CAL - NA - 0xCC - 0x20 - - - TXSKEWCALHS - NA - 0 - 1 - read-write - - - - - INT_FORCE0 - NA - 0xD8 - 0x20 - - - FORCE_ACK_WITH_ERR_0 - NA - 0 - 1 - read-write - - - FORCE_ACK_WITH_ERR_1 - NA - 1 - 1 - read-write - - - FORCE_ACK_WITH_ERR_2 - NA - 2 - 1 - read-write - - - FORCE_ACK_WITH_ERR_3 - NA - 3 - 1 - read-write - - - FORCE_ACK_WITH_ERR_4 - NA - 4 - 1 - read-write - - - FORCE_ACK_WITH_ERR_5 - NA - 5 - 1 - read-write - - - FORCE_ACK_WITH_ERR_6 - NA - 6 - 1 - read-write - - - FORCE_ACK_WITH_ERR_7 - NA - 7 - 1 - read-write - - - FORCE_ACK_WITH_ERR_8 - NA - 8 - 1 - read-write - - - FORCE_ACK_WITH_ERR_9 - NA - 9 - 1 - read-write - - - FORCE_ACK_WITH_ERR_10 - NA - 10 - 1 - read-write - - - FORCE_ACK_WITH_ERR_11 - NA - 11 - 1 - read-write - - - FORCE_ACK_WITH_ERR_12 - NA - 12 - 1 - read-write - - - FORCE_ACK_WITH_ERR_13 - NA - 13 - 1 - read-write - - - FORCE_ACK_WITH_ERR_14 - NA - 14 - 1 - read-write - - - FORCE_ACK_WITH_ERR_15 - NA - 15 - 1 - read-write - - - FORCE_DPHY_ERRORS_0 - NA - 16 - 1 - read-write - - - FORCE_DPHY_ERRORS_1 - NA - 17 - 1 - read-write - - - FORCE_DPHY_ERRORS_2 - NA - 18 - 1 - read-write - - - FORCE_DPHY_ERRORS_3 - NA - 19 - 1 - read-write - - - FORCE_DPHY_ERRORS_4 - NA - 20 - 1 - read-write - - - - - INT_FORCE1 - NA - 0xDC - 0x20 - - - FORCE_TO_HS_TX - NA - 0 - 1 - read-write - - - FORCE_TO_LP_RX - NA - 1 - 1 - read-write - - - FORCE_ECC_SINGLE_ERR - NA - 2 - 1 - read-write - - - FORCE_ECC_MILTI_ERR - NA - 3 - 1 - read-write - - - FORCE_CRC_ERR - NA - 4 - 1 - read-write - - - FORCE_PKT_SIZE_ERR - NA - 5 - 1 - read-write - - - FORCE_EOPT_ERR - NA - 6 - 1 - read-write - - - FORCE_DPI_PLD_WR_ERR - NA - 7 - 1 - read-write - - - FORCE_GEN_CMD_WR_ERR - NA - 8 - 1 - read-write - - - FORCE_GEN_PLD_WR_ERR - NA - 9 - 1 - read-write - - - FORCE_GEN_PLD_SEND_ERR - NA - 10 - 1 - read-write - - - FORCE_GEN_PLD_RD_ERR - NA - 11 - 1 - read-write - - - FORCE_GEN_PLD_RECEV_ERR - NA - 12 - 1 - read-write - - - FORCE_DPI_BUFF_PLD_UNDER - NA - 19 - 1 - read-write - - - - - DSC_PARAMETER - NA - 0xF0 - 0x20 - - - COMPRESSION_MODE - NA - 0 - 1 - read-write - - - COMPRESS_ALGO - NA - 8 - 2 - read-write - - - PPS_SEL - NA - 16 - 2 - read-write - - - - - PHY_TMR_RD_CFG - NA - 0xF4 - 0x20 - - - MAX_RD_TIME - NA - 0 - 15 - read-write - - - - - VID_SHADOW_CTRL - NA - 0x100 - 0x20 - - - VID_SHADOW_EN - NA - 0 - 1 - read-write - - - VID_SHADOW_REQ - NA - 8 - 1 - read-write - - - VID_SHADOW_PIN_REQ - NA - 16 - 1 - read-write - - - - - DPI_VCID_ACT - NA - 0x10C - 0x20 - - - DPI_VCID_ACT - NA - 0 - 2 - read-only - - - - - DPI_COLOR_CODING_ACT - NA - 0x110 - 0x20 - - - DPI_COLOR_CODING_ACT - NA - 0 - 4 - read-only - - - LOOSELY18_EN_ACT - NA - 8 - 1 - read-only - - - - - DPI_LP_CMD_TIM_ACT - NA - 0x118 - 0x20 - - - INVACT_LPCMD_TIME_ACT - NA - 0 - 8 - read-only - - - OUTVACT_LPCMD_TIME_ACT - NA - 16 - 8 - read-only - - - - - EDPI_TE_HW_CFG - NA - 0x11C - 0x20 - - - HW_TEAR_EFFECT_ON - NA - 0 - 1 - read-write - - - HW_TEAR_EFFECT_GEN - NA - 1 - 1 - read-write - - - HW_SET_SCAN_LINE - NA - 4 - 1 - read-write - - - SCAN_LINE_PARAMETER - NA - 16 - 16 - read-write - - - - - VID_MODE_CFG_ACT - NA - 0x138 - 0x20 - - - VID_MODE_TYPE_ACT - NA - 0 - 2 - read-only - - - LP_VSA_EN_ACT - NA - 2 - 1 - read-only - - - LP_VBP_EN_ACT - NA - 3 - 1 - read-only - - - LP_VFP_EN_ACT - NA - 4 - 1 - read-only - - - LP_VACT_EN_ACT - NA - 5 - 1 - read-only - - - LP_HBP_EN_ACT - NA - 6 - 1 - read-only - - - LP_HFP_EN_ACT - NA - 7 - 1 - read-only - - - FRAME_BTA_ACK_EN_ACT - NA - 8 - 1 - read-only - - - LP_CMD_EN_ACT - NA - 9 - 1 - read-only - - - - - VID_PKT_SIZE_ACT - NA - 0x13C - 0x20 - - - VID_PKT_SIZE_ACT - NA - 0 - 14 - read-only - - - - - VID_NUM_CHUNKS_ACT - NA - 0x140 - 0x20 - - - VID_NUM_CHUNKS_ACT - NA - 0 - 13 - read-only - - - - - VID_NULL_SIZE_ACT - NA - 0x144 - 0x20 - - - VID_NULL_SIZE_ACT - NA - 0 - 13 - read-only - - - - - VID_HSA_TIME_ACT - NA - 0x148 - 0x20 - - - VID_HSA_TIME_ACT - NA - 0 - 12 - read-only - - - - - VID_HBP_TIME_ACT - NA - 0x14C - 0x20 - - - VID_HBP_TIME_ACT - NA - 0 - 12 - read-only - - - - - VID_HLINE_TIME_ACT - NA - 0x150 - 0x20 - - - VID_HLINE_TIME_ACT - NA - 0 - 15 - read-only - - - - - VID_VSA_LINES_ACT - NA - 0x154 - 0x20 - - - VSA_LINES_ACT - NA - 0 - 10 - read-only - - - - - VID_VBP_LINES_ACT - NA - 0x158 - 0x20 - - - VBP_LINES_ACT - NA - 0 - 10 - read-only - - - - - VID_VFP_LINES_ACT - NA - 0x15C - 0x20 - - - VFP_LINES_ACT - NA - 0 - 10 - read-only - - - - - VID_VACTIVE_LINES_ACT - NA - 0x160 - 0x20 - - - V_ACTIVE_LINES_ACT - NA - 0 - 14 - read-only - - - - - VID_PKT_STATUS - NA - 0x168 - 0x20 - 0x00010005 - - - DPI_CMD_W_EMPTY - NA - 0 - 1 - read-only - - - DPI_CMD_W_FULL - NA - 1 - 1 - read-only - - - DPI_PLD_W_EMPTY - NA - 2 - 1 - read-only - - - DPI_PLD_W_FULL - NA - 3 - 1 - read-only - - - DPI_BUFF_PLD_EMPTY - NA - 16 - 1 - read-only - - - DPI_BUFF_PLD_FULL - NA - 17 - 1 - read-only - - - - - SDF_3D_ACT - NA - 0x190 - 0x20 - - - MODE_3D_ACT - NA - 0 - 2 - read-only - - - FORMAT_3D_ACT - NA - 2 - 2 - read-only - - - SECOND_VSYNC_ACT - NA - 4 - 1 - read-only - - - RIGHT_FIRST_ACT - NA - 5 - 1 - read-only - - - SEND_3D_CFG_ACT - NA - 16 - 1 - read-only - - - - - - - ECC - ECC (ECC Hardware Accelerator) - ECC - 0x50093000 - - 0x0 - 0x78 - registers - - - ECC - 71 - - - - MULT_INT_RAW - ECC interrupt raw register, valid in level. - 0xC - 0x20 - - - CALC_DONE_INT_RAW - The raw interrupt status bit for the ecc_calc_done_int interrupt - 0 - 1 - read-only - - - - - MULT_INT_ST - ECC interrupt status register. - 0x10 - 0x20 - - - CALC_DONE_INT_ST - The masked interrupt status bit for the ecc_calc_done_int interrupt - 0 - 1 - read-only - - - - - MULT_INT_ENA - ECC interrupt enable register. - 0x14 - 0x20 - - - CALC_DONE_INT_ENA - The interrupt enable bit for the ecc_calc_done_int interrupt - 0 - 1 - read-write - - - - - MULT_INT_CLR - ECC interrupt clear register. - 0x18 - 0x20 - - - CALC_DONE_INT_CLR - Set this bit to clear the ecc_calc_done_int interrupt - 0 - 1 - write-only - - - - - MULT_CONF - ECC configure register - 0x1C - 0x20 - - - START - Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after the caculatrion is done. - 0 - 1 - read-write - - - RESET - Write 1 to reset ECC Accelerator. - 1 - 1 - write-only - - - KEY_LENGTH - The key length mode bit of ECC Accelerator. 0: P-192. 1: P-256. - 2 - 1 - read-write - - - MOD_BASE - The mod base of mod operation, only valid in work_mode 8-11. 0: n(order of curve). 1: p(mod base of curve) - 3 - 1 - read-write - - - WORK_MODE - The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: Reserved. 2: Point verification mode. 3: Point Verif+mult mode. 4: Jacobian Point Mult Mode. 5: Point Add Mode. 6: Jacobian Point Verification Mode. 7: Point Verif + Jacobian Mult Mode. 8: mod addition. 9. mod substraction. 10: mod multiplication. 11: mod division. - 4 - 4 - read-write - - - SECURITY_MODE - Reserved - 8 - 1 - read-write - - - VERIFICATION_RESULT - The verification result bit of ECC Accelerator, only valid when calculation is done. - 29 - 1 - read-only - - - CLK_EN - Write 1 to force on register clock gate. - 30 - 1 - read-write - - - MEM_CLOCK_GATE_FORCE_ON - ECC memory clock gate force on register - 31 - 1 - read-write - - - - - MULT_DATE - Version control register - 0xFC - 0x20 - 0x02305040 - - - DATE - ECC mult version control register - 0 - 28 - read-write - - - - - 8 - 0x4 - K_MEM[%s] - The memory that stores k. - 0x100 - 0x20 - - - 8 - 0x4 - PX_MEM[%s] - The memory that stores Px. - 0x120 - 0x20 - - - 8 - 0x4 - PY_MEM[%s] - The memory that stores Py. - 0x140 - 0x20 - - - - - ECDSA - ECDSA (Elliptic Curve Digital Signature Algorithm) Accelerator - ECDSA - 0x50096000 - - 0x0 - 0xF8 - registers - - - - CONF - ECDSA configure register - 0x4 - 0x20 - - - WORK_MODE - The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature Generate Mode. 2: Export Public Key Mode. 3: invalid. - 0 - 2 - read-write - - - ECC_CURVE - The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256. - 2 - 1 - read-write - - - SOFTWARE_SET_K - The source of k select bit. 0: k is automatically generated by hardware. 1: k is written by software. - 3 - 1 - read-write - - - SOFTWARE_SET_Z - The source of z select bit. 0: z is generated from SHA result. 1: z is written by software. - 4 - 1 - read-write - - - DETERMINISTIC_K - The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by deterministic derivation algorithm. - 5 - 1 - read-write - - - DETERMINISTIC_LOOP - The (loop number - 1) value in the deterministic derivation algorithm to derive k. - 6 - 16 - read-write - - - - - CLK - ECDSA clock gate register - 0x8 - 0x20 - - - GATE_FORCE_ON - Write 1 to force on register clock gate. - 0 - 1 - read-write - - - - - INT_RAW - ECDSA interrupt raw register, valid in level. - 0xC - 0x20 - - - CALC_DONE_INT_RAW - The raw interrupt status bit for the ecdsa_calc_done_int interrupt - 0 - 1 - read-only - - - SHA_RELEASE_INT_RAW - The raw interrupt status bit for the ecdsa_sha_release_int interrupt - 1 - 1 - read-only - - - - - INT_ST - ECDSA interrupt status register. - 0x10 - 0x20 - - - CALC_DONE_INT_ST - The masked interrupt status bit for the ecdsa_calc_done_int interrupt - 0 - 1 - read-only - - - SHA_RELEASE_INT_ST - The masked interrupt status bit for the ecdsa_sha_release_int interrupt - 1 - 1 - read-only - - - - - INT_ENA - ECDSA interrupt enable register. - 0x14 - 0x20 - - - CALC_DONE_INT_ENA - The interrupt enable bit for the ecdsa_calc_done_int interrupt - 0 - 1 - read-write - - - SHA_RELEASE_INT_ENA - The interrupt enable bit for the ecdsa_sha_release_int interrupt - 1 - 1 - read-write - - - - - INT_CLR - ECDSA interrupt clear register. - 0x18 - 0x20 - - - CALC_DONE_INT_CLR - Set this bit to clear the ecdsa_calc_done_int interrupt - 0 - 1 - write-only - - - SHA_RELEASE_INT_CLR - Set this bit to clear the ecdsa_sha_release_int interrupt - 1 - 1 - write-only - - - - - START - ECDSA start register - 0x1C - 0x20 - - - START - Write 1 to start caculation of ECDSA Accelerator. This bit will be self-cleared after configuration. - 0 - 1 - write-only - - - LOAD_DONE - Write 1 to input load done signal of ECDSA Accelerator. This bit will be self-cleared after configuration. - 1 - 1 - write-only - - - GET_DONE - Write 1 to input get done signal of ECDSA Accelerator. This bit will be self-cleared after configuration. - 2 - 1 - write-only - - - - - STATE - ECDSA status register - 0x20 - 0x20 - - - BUSY - The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY state. - 0 - 2 - read-only - - - - - RESULT - ECDSA result register - 0x24 - 0x20 - - - OPERATION_RESULT - The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is done. - 0 - 1 - read-only - - - K_VALUE_WARNING - The k value warning bit of ECDSA Accelerator, valid when k value is bigger than the curve order, then actually taken k = k mod n. - 1 - 1 - read-only - - - - - DATE - Version control register - 0xFC - 0x20 - 0x02304070 - - - DATE - ECDSA version control register - 0 - 28 - read-write - - - - - SHA_MODE - ECDSA control SHA register - 0x200 - 0x20 - - - SHA_MODE - The work mode bits of SHA Calculator in ECDSA Accelerator. 1: SHA-224. 2: SHA-256. Others: invalid. - 0 - 3 - read-write - - - - - SHA_START - ECDSA control SHA register - 0x210 - 0x20 - - - SHA_START - Write 1 to start the first caculation of SHA Calculator in ECDSA Accelerator. This bit will be self-cleared after configuration. - 0 - 1 - write-only - - - - - SHA_CONTINUE - ECDSA control SHA register - 0x214 - 0x20 - - - SHA_CONTINUE - Write 1 to start the latter caculation of SHA Calculator in ECDSA Accelerator. This bit will be self-cleared after configuration. - 0 - 1 - write-only - - - - - SHA_BUSY - ECDSA status register - 0x218 - 0x20 - - - SHA_BUSY - The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in calculation. 0: SHA is idle. - 0 - 1 - read-only - - - - - 8 - 0x4 - MESSAGE_MEM[%s] - The memory that stores message. - 0x280 - 0x20 - - - 8 - 0x4 - R_MEM[%s] - The memory that stores r. - 0xA00 - 0x20 - - - 8 - 0x4 - S_MEM[%s] - The memory that stores s. - 0xA20 - 0x20 - - - 8 - 0x4 - Z_MEM[%s] - The memory that stores software written z. - 0xA40 - 0x20 - - - 8 - 0x4 - QAX_MEM[%s] - The memory that stores x coordinates of QA or software written k. - 0xA60 - 0x20 - - - 8 - 0x4 - QAY_MEM[%s] - The memory that stores y coordinates of QA. - 0xA80 - 0x20 - - - - - EFUSE - eFuse Controller - EFUSE - 0x5012D000 - - 0x0 - 0x3D8 - registers - - - - PGM_DATA0 - Register 0 that stores data to be programmed. - 0x0 - 0x20 - - - PGM_DATA_0 - Configures the 0th 32-bit data to be programmed. - 0 - 32 - read-write - - - - - PGM_DATA1 - Register 1 that stores data to be programmed. - 0x4 - 0x20 - - - PGM_DATA_1 - Configures the 1st 32-bit data to be programmed. - 0 - 32 - read-write - - - - - PGM_DATA2 - Register 2 that stores data to be programmed. - 0x8 - 0x20 - - - PGM_DATA_2 - Configures the 2nd 32-bit data to be programmed. - 0 - 32 - read-write - - - - - PGM_DATA3 - Register 3 that stores data to be programmed. - 0xC - 0x20 - - - PGM_DATA_3 - Configures the 3rd 32-bit data to be programmed. - 0 - 32 - read-write - - - - - PGM_DATA4 - Register 4 that stores data to be programmed. - 0x10 - 0x20 - - - PGM_DATA_4 - Configures the 4th 32-bit data to be programmed. - 0 - 32 - read-write - - - - - PGM_DATA5 - Register 5 that stores data to be programmed. - 0x14 - 0x20 - - - PGM_DATA_5 - Configures the 5th 32-bit data to be programmed. - 0 - 32 - read-write - - - - - PGM_DATA6 - Register 6 that stores data to be programmed. - 0x18 - 0x20 - - - PGM_DATA_6 - Configures the 6th 32-bit data to be programmed. - 0 - 32 - read-write - - - - - PGM_DATA7 - Register 7 that stores data to be programmed. - 0x1C - 0x20 - - - PGM_DATA_7 - Configures the 7th 32-bit data to be programmed. - 0 - 32 - read-write - - - - - PGM_CHECK_VALUE0 - Register 0 that stores the RS code to be programmed. - 0x20 - 0x20 - - - PGM_RS_DATA_0 - Configures the 0th 32-bit RS code to be programmed. - 0 - 32 - read-write - - - - - PGM_CHECK_VALUE1 - Register 1 that stores the RS code to be programmed. - 0x24 - 0x20 - - - PGM_RS_DATA_1 - Configures the 1st 32-bit RS code to be programmed. - 0 - 32 - read-write - - - - - PGM_CHECK_VALUE2 - Register 2 that stores the RS code to be programmed. - 0x28 - 0x20 - - - PGM_RS_DATA_2 - Configures the 2nd 32-bit RS code to be programmed. - 0 - 32 - read-write - - - - - RD_WR_DIS - BLOCK0 data register 0. - 0x2C - 0x20 - - - WR_DIS - Represents whether programming of individual eFuse memory bit is disabled or enabled. 1: Disabled. 0 Enabled. - 0 - 32 - read-only - - - - - RD_REPEAT_DATA0 - BLOCK0 data register 1. - 0x30 - 0x20 - - - RD_DIS - Represents whether reading of individual eFuse block(block4~block10) is disabled or enabled. 1: disabled. 0: enabled. - 0 - 7 - read-only - - - USB_DEVICE_EXCHG_PINS - Enable usb device exchange pins of D+ and D-. - 7 - 1 - read-only - - - USB_OTG11_EXCHG_PINS - Enable usb otg11 exchange pins of D+ and D-. - 8 - 1 - read-only - - - DIS_USB_JTAG - Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled. - 9 - 1 - read-only - - - POWERGLITCH_EN - Represents whether power glitch function is enabled. 1: enabled. 0: disabled. - 10 - 1 - read-only - - - DIS_USB_SERIAL_JTAG - Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled. - 11 - 1 - read-only - - - DIS_FORCE_DOWNLOAD - Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled. - 12 - 1 - read-only - - - SPI_DOWNLOAD_MSPI_DIS - Set this bit to disable accessing MSPI flash/MSPI ram by SYS AXI matrix during boot_mode_download. - 13 - 1 - read-only - - - DIS_TWAI - Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled. - 14 - 1 - read-only - - - JTAG_SEL_ENABLE - Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled. 0: disabled. - 15 - 1 - read-only - - - SOFT_DIS_JTAG - Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled. - 16 - 3 - read-only - - - DIS_PAD_JTAG - Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled. - 19 - 1 - read-only - - - DIS_DOWNLOAD_MANUAL_ENCRYPT - Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled. - 20 - 1 - read-only - - - USB_DEVICE_DREFH - USB intphy of usb device signle-end input high threshold, 1.76V to 2V. Step by 80mV - 21 - 2 - read-only - - - USB_OTG11_DREFH - USB intphy of usb otg11 signle-end input high threshold, 1.76V to 2V. Step by 80mV - 23 - 2 - read-only - - - USB_PHY_SEL - TBD - 25 - 1 - read-only - - - KM_HUK_GEN_STATE_LOW - Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, even of 1 is valid. - 26 - 6 - read-only - - - - - RD_REPEAT_DATA1 - BLOCK0 data register 2. - 0x34 - 0x20 - - - KM_HUK_GEN_STATE_HIGH - Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, even of 1 is valid. - 0 - 3 - read-only - - - KM_RND_SWITCH_CYCLE - Set bits to control key manager random number switch cycle. 0: control by register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles. - 3 - 2 - read-only - - - KM_DEPLOY_ONLY_ONCE - Set each bit to control whether corresponding key can only be deployed once. 1 is true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds. - 5 - 4 - read-only - - - FORCE_USE_KEY_MANAGER_KEY - Set each bit to control whether corresponding key must come from key manager.. 1 is true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds. - 9 - 4 - read-only - - - FORCE_DISABLE_SW_INIT_KEY - Set this bit to disable software written init key, and force use efuse_init_key. - 13 - 1 - read-only - - - XTS_KEY_LENGTH_256 - Set this bit to configure flash encryption use xts-128 key, else use xts-256 key. - 14 - 1 - read-only - - - WDT_DELAY_SEL - Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected. - 16 - 2 - read-only - - - SPI_BOOT_CRYPT_CNT - Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of 1: enabled. Even number of 1: disabled. - 18 - 3 - read-only - - - SECURE_BOOT_KEY_REVOKE0 - Represents whether revoking first secure boot key is enabled or disabled. 1: enabled. 0: disabled. - 21 - 1 - read-only - - - SECURE_BOOT_KEY_REVOKE1 - Represents whether revoking second secure boot key is enabled or disabled. 1: enabled. 0: disabled. - 22 - 1 - read-only - - - SECURE_BOOT_KEY_REVOKE2 - Represents whether revoking third secure boot key is enabled or disabled. 1: enabled. 0: disabled. - 23 - 1 - read-only - - - KEY_PURPOSE_0 - Represents the purpose of Key0. - 24 - 4 - read-only - - - KEY_PURPOSE_1 - Represents the purpose of Key1. - 28 - 4 - read-only - - - - - RD_REPEAT_DATA2 - BLOCK0 data register 3. - 0x38 - 0x20 - 0x00080000 - - - KEY_PURPOSE_2 - Represents the purpose of Key2. - 0 - 4 - read-only - - - KEY_PURPOSE_3 - Represents the purpose of Key3. - 4 - 4 - read-only - - - KEY_PURPOSE_4 - Represents the purpose of Key4. - 8 - 4 - read-only - - - KEY_PURPOSE_5 - Represents the purpose of Key5. - 12 - 4 - read-only - - - SEC_DPA_LEVEL - Represents the spa secure level by configuring the clock random divide mode. - 16 - 2 - read-only - - - ECDSA_ENABLE_SOFT_K - Represents whether hardware random number k is forced used in ESDCA. 1: force used. 0: not force used. - 18 - 1 - read-only - - - CRYPT_DPA_ENABLE - Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled. - 19 - 1 - read-only - - - SECURE_BOOT_EN - Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled. - 20 - 1 - read-only - - - SECURE_BOOT_AGGRESSIVE_REVOKE - Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled. - 21 - 1 - read-only - - - FLASH_TYPE - The type of interfaced flash. 0: four data lines, 1: eight data lines. - 23 - 1 - read-only - - - FLASH_PAGE_SIZE - Set flash page size. - 24 - 2 - read-only - - - FLASH_ECC_EN - Set this bit to enable ecc for flash boot. - 26 - 1 - read-only - - - DIS_USB_OTG_DOWNLOAD_MODE - Set this bit to disable download via USB-OTG. - 27 - 1 - read-only - - - FLASH_TPUW - Represents the flash waiting time after power-up, in unit of ms. When the value less than 15, the waiting time is the programmed value. Otherwise, the waiting time is 2 times the programmed value. - 28 - 4 - read-only - - - - - RD_REPEAT_DATA3 - BLOCK0 data register 4. - 0x3C - 0x20 - - - DIS_DOWNLOAD_MODE - Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled. - 0 - 1 - read-only - - - DIS_DIRECT_BOOT - Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled. - 1 - 1 - read-only - - - DIS_USB_SERIAL_JTAG_ROM_PRINT - Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled. - 2 - 1 - read-only - - - LOCK_KM_KEY - TBD - 3 - 1 - read-only - - - DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE - Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled. - 4 - 1 - read-only - - - ENABLE_SECURITY_DOWNLOAD - Represents whether security download is enabled or disabled. 1: enabled. 0: disabled. - 5 - 1 - read-only - - - UART_PRINT_CONTROL - Represents the type of UART printing. 00: force enable printing. 01: enable printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset at high level. 11: force disable printing. - 6 - 2 - read-only - - - FORCE_SEND_RESUME - Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced. - 8 - 1 - read-only - - - SECURE_VERSION - Represents the version used by ESP-IDF anti-rollback feature. - 9 - 16 - read-only - - - SECURE_BOOT_DISABLE_FAST_WAKE - Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled. - 25 - 1 - read-only - - - HYS_EN_PAD - Represents whether the hysteresis function of corresponding PAD is enabled. 1: enabled. 0:disabled. - 26 - 1 - read-only - - - DCDC_VSET - Set the dcdc voltage default. - 27 - 5 - read-only - - - - - RD_REPEAT_DATA4 - BLOCK0 data register 5. - 0x40 - 0x20 - - - _0PXA_TIEH_SEL_0 - TBD - 0 - 2 - read-only - - - _0PXA_TIEH_SEL_1 - TBD. - 2 - 2 - read-only - - - _0PXA_TIEH_SEL_2 - TBD. - 4 - 2 - read-only - - - _0PXA_TIEH_SEL_3 - TBD. - 6 - 2 - read-only - - - KM_DISABLE_DEPLOY_MODE - TBD. - 8 - 4 - read-only - - - USB_DEVICE_DREFL - Represents the usb device single-end input low threhold, 0.8 V to 1.04 V with step of 80 mV. - 12 - 2 - read-only - - - USB_OTG11_DREFL - Represents the usb otg11 single-end input low threhold, 0.8 V to 1.04 V with step of 80 mV. - 14 - 2 - read-only - - - HP_PWR_SRC_SEL - HP system power source select. 0:LDO. 1: DCDC. - 18 - 1 - read-only - - - DCDC_VSET_EN - Select dcdc vset use efuse_dcdc_vset. - 19 - 1 - read-only - - - DIS_WDT - Set this bit to disable watch dog. - 20 - 1 - read-only - - - DIS_SWD - Set this bit to disable super-watchdog. - 21 - 1 - read-only - - - - - RD_MAC_SYS_0 - BLOCK1 data register $n. - 0x44 - 0x20 - - - MAC_0 - Stores the low 32 bits of MAC address. - 0 - 32 - read-only - - - - - RD_MAC_SYS_1 - BLOCK1 data register $n. - 0x48 - 0x20 - - - MAC_1 - Stores the high 16 bits of MAC address. - 0 - 16 - read-only - - - MAC_EXT - Stores the extended bits of MAC address. - 16 - 16 - read-only - - - - - RD_MAC_SYS_2 - BLOCK1 data register $n. - 0x4C - 0x20 - - - MAC_RESERVED_1 - Reserved. - 0 - 14 - read-only - - - MAC_RESERVED_0 - Reserved. - 14 - 18 - read-only - - - - - RD_MAC_SYS_3 - BLOCK1 data register $n. - 0x50 - 0x20 - - - MAC_RESERVED_2 - Reserved. - 0 - 18 - read-only - - - SYS_DATA_PART0_0 - Stores the first 14 bits of the zeroth part of system data. - 18 - 14 - read-only - - - - - RD_MAC_SYS_4 - BLOCK1 data register $n. - 0x54 - 0x20 - - - SYS_DATA_PART0_1 - Stores the first 32 bits of the zeroth part of system data. - 0 - 32 - read-only - - - - - RD_MAC_SYS_5 - BLOCK1 data register $n. - 0x58 - 0x20 - - - SYS_DATA_PART0_2 - Stores the second 32 bits of the zeroth part of system data. - 0 - 32 - read-only - - - - - RD_SYS_PART1_DATA0 - Register $n of BLOCK2 (system). - 0x5C - 0x20 - - - SYS_DATA_PART1_0 - Stores the zeroth 32 bits of the first part of system data. - 0 - 32 - read-only - - - - - RD_SYS_PART1_DATA1 - Register $n of BLOCK2 (system). - 0x60 - 0x20 - - - SYS_DATA_PART1_1 - Stores the first 32 bits of the first part of system data. - 0 - 32 - read-only - - - - - RD_SYS_PART1_DATA2 - Register $n of BLOCK2 (system). - 0x64 - 0x20 - - - SYS_DATA_PART1_2 - Stores the second 32 bits of the first part of system data. - 0 - 32 - read-only - - - - - RD_SYS_PART1_DATA3 - Register $n of BLOCK2 (system). - 0x68 - 0x20 - - - SYS_DATA_PART1_3 - Stores the third 32 bits of the first part of system data. - 0 - 32 - read-only - - - - - RD_SYS_PART1_DATA4 - Register $n of BLOCK2 (system). - 0x6C - 0x20 - - - SYS_DATA_PART1_4 - Stores the fourth 32 bits of the first part of system data. - 0 - 32 - read-only - - - - - RD_SYS_PART1_DATA5 - Register $n of BLOCK2 (system). - 0x70 - 0x20 - - - SYS_DATA_PART1_5 - Stores the fifth 32 bits of the first part of system data. - 0 - 32 - read-only - - - - - RD_SYS_PART1_DATA6 - Register $n of BLOCK2 (system). - 0x74 - 0x20 - - - SYS_DATA_PART1_6 - Stores the sixth 32 bits of the first part of system data. - 0 - 32 - read-only - - - - - RD_SYS_PART1_DATA7 - Register $n of BLOCK2 (system). - 0x78 - 0x20 - - - SYS_DATA_PART1_7 - Stores the seventh 32 bits of the first part of system data. - 0 - 32 - read-only - - - - - RD_USR_DATA0 - Register $n of BLOCK3 (user). - 0x7C - 0x20 - - - USR_DATA0 - Stores the zeroth 32 bits of BLOCK3 (user). - 0 - 32 - read-only - - - - - RD_USR_DATA1 - Register $n of BLOCK3 (user). - 0x80 - 0x20 - - - USR_DATA1 - Stores the first 32 bits of BLOCK3 (user). - 0 - 32 - read-only - - - - - RD_USR_DATA2 - Register $n of BLOCK3 (user). - 0x84 - 0x20 - - - USR_DATA2 - Stores the second 32 bits of BLOCK3 (user). - 0 - 32 - read-only - - - - - RD_USR_DATA3 - Register $n of BLOCK3 (user). - 0x88 - 0x20 - - - USR_DATA3 - Stores the third 32 bits of BLOCK3 (user). - 0 - 32 - read-only - - - - - RD_USR_DATA4 - Register $n of BLOCK3 (user). - 0x8C - 0x20 - - - USR_DATA4 - Stores the fourth 32 bits of BLOCK3 (user). - 0 - 32 - read-only - - - - - RD_USR_DATA5 - Register $n of BLOCK3 (user). - 0x90 - 0x20 - - - USR_DATA5 - Stores the fifth 32 bits of BLOCK3 (user). - 0 - 32 - read-only - - - - - RD_USR_DATA6 - Register $n of BLOCK3 (user). - 0x94 - 0x20 - - - USR_DATA6 - Stores the sixth 32 bits of BLOCK3 (user). - 0 - 32 - read-only - - - - - RD_USR_DATA7 - Register $n of BLOCK3 (user). - 0x98 - 0x20 - - - USR_DATA7 - Stores the seventh 32 bits of BLOCK3 (user). - 0 - 32 - read-only - - - - - RD_KEY0_DATA0 - Register $n of BLOCK4 (KEY0). - 0x9C - 0x20 - - - KEY0_DATA0 - Stores the zeroth 32 bits of KEY0. - 0 - 32 - read-only - - - - - RD_KEY0_DATA1 - Register $n of BLOCK4 (KEY0). - 0xA0 - 0x20 - - - KEY0_DATA1 - Stores the first 32 bits of KEY0. - 0 - 32 - read-only - - - - - RD_KEY0_DATA2 - Register $n of BLOCK4 (KEY0). - 0xA4 - 0x20 - - - KEY0_DATA2 - Stores the second 32 bits of KEY0. - 0 - 32 - read-only - - - - - RD_KEY0_DATA3 - Register $n of BLOCK4 (KEY0). - 0xA8 - 0x20 - - - KEY0_DATA3 - Stores the third 32 bits of KEY0. - 0 - 32 - read-only - - - - - RD_KEY0_DATA4 - Register $n of BLOCK4 (KEY0). - 0xAC - 0x20 - - - KEY0_DATA4 - Stores the fourth 32 bits of KEY0. - 0 - 32 - read-only - - - - - RD_KEY0_DATA5 - Register $n of BLOCK4 (KEY0). - 0xB0 - 0x20 - - - KEY0_DATA5 - Stores the fifth 32 bits of KEY0. - 0 - 32 - read-only - - - - - RD_KEY0_DATA6 - Register $n of BLOCK4 (KEY0). - 0xB4 - 0x20 - - - KEY0_DATA6 - Stores the sixth 32 bits of KEY0. - 0 - 32 - read-only - - - - - RD_KEY0_DATA7 - Register $n of BLOCK4 (KEY0). - 0xB8 - 0x20 - - - KEY0_DATA7 - Stores the seventh 32 bits of KEY0. - 0 - 32 - read-only - - - - - RD_KEY1_DATA0 - Register $n of BLOCK5 (KEY1). - 0xBC - 0x20 - - - KEY1_DATA0 - Stores the zeroth 32 bits of KEY1. - 0 - 32 - read-only - - - - - RD_KEY1_DATA1 - Register $n of BLOCK5 (KEY1). - 0xC0 - 0x20 - - - KEY1_DATA1 - Stores the first 32 bits of KEY1. - 0 - 32 - read-only - - - - - RD_KEY1_DATA2 - Register $n of BLOCK5 (KEY1). - 0xC4 - 0x20 - - - KEY1_DATA2 - Stores the second 32 bits of KEY1. - 0 - 32 - read-only - - - - - RD_KEY1_DATA3 - Register $n of BLOCK5 (KEY1). - 0xC8 - 0x20 - - - KEY1_DATA3 - Stores the third 32 bits of KEY1. - 0 - 32 - read-only - - - - - RD_KEY1_DATA4 - Register $n of BLOCK5 (KEY1). - 0xCC - 0x20 - - - KEY1_DATA4 - Stores the fourth 32 bits of KEY1. - 0 - 32 - read-only - - - - - RD_KEY1_DATA5 - Register $n of BLOCK5 (KEY1). - 0xD0 - 0x20 - - - KEY1_DATA5 - Stores the fifth 32 bits of KEY1. - 0 - 32 - read-only - - - - - RD_KEY1_DATA6 - Register $n of BLOCK5 (KEY1). - 0xD4 - 0x20 - - - KEY1_DATA6 - Stores the sixth 32 bits of KEY1. - 0 - 32 - read-only - - - - - RD_KEY1_DATA7 - Register $n of BLOCK5 (KEY1). - 0xD8 - 0x20 - - - KEY1_DATA7 - Stores the seventh 32 bits of KEY1. - 0 - 32 - read-only - - - - - RD_KEY2_DATA0 - Register $n of BLOCK6 (KEY2). - 0xDC - 0x20 - - - KEY2_DATA0 - Stores the zeroth 32 bits of KEY2. - 0 - 32 - read-only - - - - - RD_KEY2_DATA1 - Register $n of BLOCK6 (KEY2). - 0xE0 - 0x20 - - - KEY2_DATA1 - Stores the first 32 bits of KEY2. - 0 - 32 - read-only - - - - - RD_KEY2_DATA2 - Register $n of BLOCK6 (KEY2). - 0xE4 - 0x20 - - - KEY2_DATA2 - Stores the second 32 bits of KEY2. - 0 - 32 - read-only - - - - - RD_KEY2_DATA3 - Register $n of BLOCK6 (KEY2). - 0xE8 - 0x20 - - - KEY2_DATA3 - Stores the third 32 bits of KEY2. - 0 - 32 - read-only - - - - - RD_KEY2_DATA4 - Register $n of BLOCK6 (KEY2). - 0xEC - 0x20 - - - KEY2_DATA4 - Stores the fourth 32 bits of KEY2. - 0 - 32 - read-only - - - - - RD_KEY2_DATA5 - Register $n of BLOCK6 (KEY2). - 0xF0 - 0x20 - - - KEY2_DATA5 - Stores the fifth 32 bits of KEY2. - 0 - 32 - read-only - - - - - RD_KEY2_DATA6 - Register $n of BLOCK6 (KEY2). - 0xF4 - 0x20 - - - KEY2_DATA6 - Stores the sixth 32 bits of KEY2. - 0 - 32 - read-only - - - - - RD_KEY2_DATA7 - Register $n of BLOCK6 (KEY2). - 0xF8 - 0x20 - - - KEY2_DATA7 - Stores the seventh 32 bits of KEY2. - 0 - 32 - read-only - - - - - RD_KEY3_DATA0 - Register $n of BLOCK7 (KEY3). - 0xFC - 0x20 - - - KEY3_DATA0 - Stores the zeroth 32 bits of KEY3. - 0 - 32 - read-only - - - - - RD_KEY3_DATA1 - Register $n of BLOCK7 (KEY3). - 0x100 - 0x20 - - - KEY3_DATA1 - Stores the first 32 bits of KEY3. - 0 - 32 - read-only - - - - - RD_KEY3_DATA2 - Register $n of BLOCK7 (KEY3). - 0x104 - 0x20 - - - KEY3_DATA2 - Stores the second 32 bits of KEY3. - 0 - 32 - read-only - - - - - RD_KEY3_DATA3 - Register $n of BLOCK7 (KEY3). - 0x108 - 0x20 - - - KEY3_DATA3 - Stores the third 32 bits of KEY3. - 0 - 32 - read-only - - - - - RD_KEY3_DATA4 - Register $n of BLOCK7 (KEY3). - 0x10C - 0x20 - - - KEY3_DATA4 - Stores the fourth 32 bits of KEY3. - 0 - 32 - read-only - - - - - RD_KEY3_DATA5 - Register $n of BLOCK7 (KEY3). - 0x110 - 0x20 - - - KEY3_DATA5 - Stores the fifth 32 bits of KEY3. - 0 - 32 - read-only - - - - - RD_KEY3_DATA6 - Register $n of BLOCK7 (KEY3). - 0x114 - 0x20 - - - KEY3_DATA6 - Stores the sixth 32 bits of KEY3. - 0 - 32 - read-only - - - - - RD_KEY3_DATA7 - Register $n of BLOCK7 (KEY3). - 0x118 - 0x20 - - - KEY3_DATA7 - Stores the seventh 32 bits of KEY3. - 0 - 32 - read-only - - - - - RD_KEY4_DATA0 - Register $n of BLOCK8 (KEY4). - 0x11C - 0x20 - - - KEY4_DATA0 - Stores the zeroth 32 bits of KEY4. - 0 - 32 - read-only - - - - - RD_KEY4_DATA1 - Register $n of BLOCK8 (KEY4). - 0x120 - 0x20 - - - KEY4_DATA1 - Stores the first 32 bits of KEY4. - 0 - 32 - read-only - - - - - RD_KEY4_DATA2 - Register $n of BLOCK8 (KEY4). - 0x124 - 0x20 - - - KEY4_DATA2 - Stores the second 32 bits of KEY4. - 0 - 32 - read-only - - - - - RD_KEY4_DATA3 - Register $n of BLOCK8 (KEY4). - 0x128 - 0x20 - - - KEY4_DATA3 - Stores the third 32 bits of KEY4. - 0 - 32 - read-only - - - - - RD_KEY4_DATA4 - Register $n of BLOCK8 (KEY4). - 0x12C - 0x20 - - - KEY4_DATA4 - Stores the fourth 32 bits of KEY4. - 0 - 32 - read-only - - - - - RD_KEY4_DATA5 - Register $n of BLOCK8 (KEY4). - 0x130 - 0x20 - - - KEY4_DATA5 - Stores the fifth 32 bits of KEY4. - 0 - 32 - read-only - - - - - RD_KEY4_DATA6 - Register $n of BLOCK8 (KEY4). - 0x134 - 0x20 - - - KEY4_DATA6 - Stores the sixth 32 bits of KEY4. - 0 - 32 - read-only - - - - - RD_KEY4_DATA7 - Register $n of BLOCK8 (KEY4). - 0x138 - 0x20 - - - KEY4_DATA7 - Stores the seventh 32 bits of KEY4. - 0 - 32 - read-only - - - - - RD_KEY5_DATA0 - Register $n of BLOCK9 (KEY5). - 0x13C - 0x20 - - - KEY5_DATA0 - Stores the zeroth 32 bits of KEY5. - 0 - 32 - read-only - - - - - RD_KEY5_DATA1 - Register $n of BLOCK9 (KEY5). - 0x140 - 0x20 - - - KEY5_DATA1 - Stores the first 32 bits of KEY5. - 0 - 32 - read-only - - - - - RD_KEY5_DATA2 - Register $n of BLOCK9 (KEY5). - 0x144 - 0x20 - - - KEY5_DATA2 - Stores the second 32 bits of KEY5. - 0 - 32 - read-only - - - - - RD_KEY5_DATA3 - Register $n of BLOCK9 (KEY5). - 0x148 - 0x20 - - - KEY5_DATA3 - Stores the third 32 bits of KEY5. - 0 - 32 - read-only - - - - - RD_KEY5_DATA4 - Register $n of BLOCK9 (KEY5). - 0x14C - 0x20 - - - KEY5_DATA4 - Stores the fourth 32 bits of KEY5. - 0 - 32 - read-only - - - - - RD_KEY5_DATA5 - Register $n of BLOCK9 (KEY5). - 0x150 - 0x20 - - - KEY5_DATA5 - Stores the fifth 32 bits of KEY5. - 0 - 32 - read-only - - - - - RD_KEY5_DATA6 - Register $n of BLOCK9 (KEY5). - 0x154 - 0x20 - - - KEY5_DATA6 - Stores the sixth 32 bits of KEY5. - 0 - 32 - read-only - - - - - RD_KEY5_DATA7 - Register $n of BLOCK9 (KEY5). - 0x158 - 0x20 - - - KEY5_DATA7 - Stores the seventh 32 bits of KEY5. - 0 - 32 - read-only - - - - - RD_SYS_PART2_DATA0 - Register $n of BLOCK10 (system). - 0x15C - 0x20 - - - SYS_DATA_PART2_0 - Stores the 0th 32 bits of the 2nd part of system data. - 0 - 32 - read-only - - - - - RD_SYS_PART2_DATA1 - Register $n of BLOCK9 (KEY5). - 0x160 - 0x20 - - - SYS_DATA_PART2_1 - Stores the 0th 32 bits of the 2nd part of system data. - 0 - 32 - read-only - - - - - RD_SYS_PART2_DATA2 - Register $n of BLOCK10 (system). - 0x164 - 0x20 - - - SYS_DATA_PART2_2 - Stores the 0th 32 bits of the 2nd part of system data. - 0 - 32 - read-only - - - - - RD_SYS_PART2_DATA3 - Register $n of BLOCK10 (system). - 0x168 - 0x20 - - - SYS_DATA_PART2_3 - Stores the 0th 32 bits of the 2nd part of system data. - 0 - 32 - read-only - - - - - RD_SYS_PART2_DATA4 - Register $n of BLOCK10 (system). - 0x16C - 0x20 - - - SYS_DATA_PART2_4 - Stores the 0th 32 bits of the 2nd part of system data. - 0 - 32 - read-only - - - - - RD_SYS_PART2_DATA5 - Register $n of BLOCK10 (system). - 0x170 - 0x20 - - - SYS_DATA_PART2_5 - Stores the 0th 32 bits of the 2nd part of system data. - 0 - 32 - read-only - - - - - RD_SYS_PART2_DATA6 - Register $n of BLOCK10 (system). - 0x174 - 0x20 - - - SYS_DATA_PART2_6 - Stores the 0th 32 bits of the 2nd part of system data. - 0 - 32 - read-only - - - - - RD_SYS_PART2_DATA7 - Register $n of BLOCK10 (system). - 0x178 - 0x20 - - - SYS_DATA_PART2_7 - Stores the 0th 32 bits of the 2nd part of system data. - 0 - 32 - read-only - - - - - RD_REPEAT_ERR0 - Programming error record register 0 of BLOCK0. - 0x17C - 0x20 - - - RD_DIS_ERR - Indicates a programming error of RD_DIS. - 0 - 7 - read-only - - - DIS_USB_DEVICE_EXCHG_PINS_ERR - Indicates a programming error of DIS_USB_DEVICE_EXCHG_PINS. - 7 - 1 - read-only - - - DIS_USB_OTG11_EXCHG_PINS_ERR - Indicates a programming error of DIS_USB_OTG11_EXCHG_PINS. - 8 - 1 - read-only - - - DIS_USB_JTAG_ERR - Indicates a programming error of DIS_USB_JTAG. - 9 - 1 - read-only - - - POWERGLITCH_EN_ERR - Indicates a programming error of POWERGLITCH_EN. - 10 - 1 - read-only - - - DIS_USB_SERIAL_JTAG_ERR - Indicates a programming error of DIS_USB_SERIAL_JTAG. - 11 - 1 - read-only - - - DIS_FORCE_DOWNLOAD_ERR - Indicates a programming error of DIS_FORCE_DOWNLOAD. - 12 - 1 - read-only - - - SPI_DOWNLOAD_MSPI_DIS_ERR - Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS. - 13 - 1 - read-only - - - DIS_TWAI_ERR - Indicates a programming error of DIS_TWAI. - 14 - 1 - read-only - - - JTAG_SEL_ENABLE_ERR - Indicates a programming error of JTAG_SEL_ENABLE. - 15 - 1 - read-only - - - SOFT_DIS_JTAG_ERR - Indicates a programming error of SOFT_DIS_JTAG. - 16 - 3 - read-only - - - DIS_PAD_JTAG_ERR - Indicates a programming error of DIS_PAD_JTAG. - 19 - 1 - read-only - - - DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR - Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT. - 20 - 1 - read-only - - - USB_DEVICE_DREFH_ERR - Indicates a programming error of USB_DEVICE_DREFH. - 21 - 2 - read-only - - - USB_OTG11_DREFH_ERR - Indicates a programming error of USB_OTG11_DREFH. - 23 - 2 - read-only - - - USB_PHY_SEL_ERR - Indicates a programming error of USB_PHY_SEL. - 25 - 1 - read-only - - - HUK_GEN_STATE_LOW_ERR - Indicates a programming error of HUK_GEN_STATE_LOW. - 26 - 6 - read-only - - - - - RD_REPEAT_ERR1 - Programming error record register 1 of BLOCK0. - 0x180 - 0x20 - - - KM_HUK_GEN_STATE_HIGH_ERR - Indicates a programming error of HUK_GEN_STATE_HIGH. - 0 - 3 - read-only - - - KM_RND_SWITCH_CYCLE_ERR - Indicates a programming error of KM_RND_SWITCH_CYCLE. - 3 - 2 - read-only - - - KM_DEPLOY_ONLY_ONCE_ERR - Indicates a programming error of KM_DEPLOY_ONLY_ONCE. - 5 - 4 - read-only - - - FORCE_USE_KEY_MANAGER_KEY_ERR - Indicates a programming error of FORCE_USE_KEY_MANAGER_KEY. - 9 - 4 - read-only - - - FORCE_DISABLE_SW_INIT_KEY_ERR - Indicates a programming error of FORCE_DISABLE_SW_INIT_KEY. - 13 - 1 - read-only - - - XTS_KEY_LENGTH_256_ERR - Indicates a programming error of XTS_KEY_LENGTH_256. - 14 - 1 - read-only - - - WDT_DELAY_SEL_ERR - Indicates a programming error of WDT_DELAY_SEL. - 16 - 2 - read-only - - - SPI_BOOT_CRYPT_CNT_ERR - Indicates a programming error of SPI_BOOT_CRYPT_CNT. - 18 - 3 - read-only - - - SECURE_BOOT_KEY_REVOKE0_ERR - Indicates a programming error of SECURE_BOOT_KEY_REVOKE0. - 21 - 1 - read-only - - - SECURE_BOOT_KEY_REVOKE1_ERR - Indicates a programming error of SECURE_BOOT_KEY_REVOKE1. - 22 - 1 - read-only - - - SECURE_BOOT_KEY_REVOKE2_ERR - Indicates a programming error of SECURE_BOOT_KEY_REVOKE2. - 23 - 1 - read-only - - - KEY_PURPOSE_0_ERR - Indicates a programming error of KEY_PURPOSE_0. - 24 - 4 - read-only - - - KEY_PURPOSE_1_ERR - Indicates a programming error of KEY_PURPOSE_1. - 28 - 4 - read-only - - - - - RD_REPEAT_ERR2 - Programming error record register 2 of BLOCK0. - 0x184 - 0x20 - - - KEY_PURPOSE_2_ERR - Indicates a programming error of KEY_PURPOSE_2. - 0 - 4 - read-only - - - KEY_PURPOSE_3_ERR - Indicates a programming error of KEY_PURPOSE_3. - 4 - 4 - read-only - - - KEY_PURPOSE_4_ERR - Indicates a programming error of KEY_PURPOSE_4. - 8 - 4 - read-only - - - KEY_PURPOSE_5_ERR - Indicates a programming error of KEY_PURPOSE_5. - 12 - 4 - read-only - - - SEC_DPA_LEVEL_ERR - Indicates a programming error of SEC_DPA_LEVEL. - 16 - 2 - read-only - - - ECDSA_ENABLE_SOFT_K_ERR - Indicates a programming error of ECDSA_FORCE_USE_HARDWARE_K. - 18 - 1 - read-only - - - CRYPT_DPA_ENABLE_ERR - Indicates a programming error of CRYPT_DPA_ENABLE. - 19 - 1 - read-only - - - SECURE_BOOT_EN_ERR - Indicates a programming error of SECURE_BOOT_EN. - 20 - 1 - read-only - - - SECURE_BOOT_AGGRESSIVE_REVOKE_ERR - Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE. - 21 - 1 - read-only - - - FLASH_TYPE_ERR - Indicates a programming error of FLASH_TYPE. - 23 - 1 - read-only - - - FLASH_PAGE_SIZE_ERR - Indicates a programming error of FLASH_PAGE_SIZE. - 24 - 2 - read-only - - - FLASH_ECC_EN_ERR - Indicates a programming error of FLASH_ECC_EN. - 26 - 1 - read-only - - - DIS_USB_OTG_DOWNLOAD_MODE_ERR - Indicates a programming error of DIS_USB_OTG_DOWNLOAD_MODE. - 27 - 1 - read-only - - - FLASH_TPUW_ERR - Indicates a programming error of FLASH_TPUW. - 28 - 4 - read-only - - - - - RD_REPEAT_ERR3 - Programming error record register 3 of BLOCK0. - 0x188 - 0x20 - - - DIS_DOWNLOAD_MODE_ERR - Indicates a programming error of DIS_DOWNLOAD_MODE. - 0 - 1 - read-only - - - DIS_DIRECT_BOOT_ERR - Indicates a programming error of DIS_DIRECT_BOOT. - 1 - 1 - read-only - - - DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR - Indicates a programming error of DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR. - 2 - 1 - read-only - - - LOCK_KM_KEY_ERR - TBD - 3 - 1 - read-only - - - DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR - Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE. - 4 - 1 - read-only - - - ENABLE_SECURITY_DOWNLOAD_ERR - Indicates a programming error of ENABLE_SECURITY_DOWNLOAD. - 5 - 1 - read-only - - - UART_PRINT_CONTROL_ERR - Indicates a programming error of UART_PRINT_CONTROL. - 6 - 2 - read-only - - - FORCE_SEND_RESUME_ERR - Indicates a programming error of FORCE_SEND_RESUME. - 8 - 1 - read-only - - - SECURE_VERSION_ERR - Indicates a programming error of SECURE VERSION. - 9 - 16 - read-only - - - SECURE_BOOT_DISABLE_FAST_WAKE_ERR - Indicates a programming error of SECURE_BOOT_DISABLE_FAST_WAKE. - 25 - 1 - read-only - - - HYS_EN_PAD_ERR - Indicates a programming error of HYS_EN_PAD. - 26 - 1 - read-only - - - DCDC_VSET_ERR - Indicates a programming error of DCDC_VSET. - 27 - 5 - read-only - - - - - RD_REPEAT_ERR4 - Programming error record register 4 of BLOCK0. - 0x18C - 0x20 - - - _0PXA_TIEH_SEL_0_ERR - Indicates a programming error of 0PXA_TIEH_SEL_0. - 0 - 2 - read-only - - - _0PXA_TIEH_SEL_1_ERR - Indicates a programming error of 0PXA_TIEH_SEL_1. - 2 - 2 - read-only - - - _0PXA_TIEH_SEL_2_ERR - Indicates a programming error of 0PXA_TIEH_SEL_2. - 4 - 2 - read-only - - - _0PXA_TIEH_SEL_3_ERR - Indicates a programming error of 0PXA_TIEH_SEL_3. - 6 - 2 - read-only - - - KM_DISABLE_DEPLOY_MODE_ERR - TBD. - 8 - 4 - read-only - - - USB_DEVICE_DREFL_ERR - Indicates a programming error of USB_DEVICE_DREFL. - 12 - 2 - read-only - - - USB_OTG11_DREFL_ERR - Indicates a programming error of USB_OTG11_DREFL. - 14 - 2 - read-only - - - HP_PWR_SRC_SEL_ERR - Indicates a programming error of HP_PWR_SRC_SEL. - 18 - 1 - read-only - - - DCDC_VSET_EN_ERR - Indicates a programming error of DCDC_VSET_EN. - 19 - 1 - read-only - - - DIS_WDT_ERR - Indicates a programming error of DIS_WDT. - 20 - 1 - read-only - - - DIS_SWD_ERR - Indicates a programming error of DIS_SWD. - 21 - 1 - read-only - - - - - RD_RS_ERR0 - Programming error record register 0 of BLOCK1-10. - 0x1C0 - 0x20 - - - MAC_SYS_ERR_NUM - The value of this signal means the number of error bytes. - 0 - 3 - read-only - - - MAC_SYS_FAIL - 0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that programming user data failed and the number of error bytes is over 6. - 3 - 1 - read-only - - - SYS_PART1_ERR_NUM - The value of this signal means the number of error bytes. - 4 - 3 - read-only - - - SYS_PART1_FAIL - 0: Means no failure and that the data of system part1 is reliable 1: Means that programming user data failed and the number of error bytes is over 6. - 7 - 1 - read-only - - - USR_DATA_ERR_NUM - The value of this signal means the number of error bytes. - 8 - 3 - read-only - - - USR_DATA_FAIL - 0: Means no failure and that the user data is reliable 1: Means that programming user data failed and the number of error bytes is over 6. - 11 - 1 - read-only - - - KEY0_ERR_NUM - The value of this signal means the number of error bytes. - 12 - 3 - read-only - - - KEY0_FAIL - 0: Means no failure and that the data of key0 is reliable 1: Means that programming key0 failed and the number of error bytes is over 6. - 15 - 1 - read-only - - - KEY1_ERR_NUM - The value of this signal means the number of error bytes. - 16 - 3 - read-only - - - KEY1_FAIL - 0: Means no failure and that the data of key1 is reliable 1: Means that programming key1 failed and the number of error bytes is over 6. - 19 - 1 - read-only - - - KEY2_ERR_NUM - The value of this signal means the number of error bytes. - 20 - 3 - read-only - - - KEY2_FAIL - 0: Means no failure and that the data of key2 is reliable 1: Means that programming key2 failed and the number of error bytes is over 6. - 23 - 1 - read-only - - - KEY3_ERR_NUM - The value of this signal means the number of error bytes. - 24 - 3 - read-only - - - KEY3_FAIL - 0: Means no failure and that the data of key3 is reliable 1: Means that programming key3 failed and the number of error bytes is over 6. - 27 - 1 - read-only - - - KEY4_ERR_NUM - The value of this signal means the number of error bytes. - 28 - 3 - read-only - - - KEY4_FAIL - 0: Means no failure and that the data of key4 is reliable 1: Means that programming key4 failed and the number of error bytes is over 6. - 31 - 1 - read-only - - - - - RD_RS_ERR1 - Programming error record register 1 of BLOCK1-10. - 0x1C4 - 0x20 - - - KEY5_ERR_NUM - The value of this signal means the number of error bytes. - 0 - 3 - read-only - - - KEY5_FAIL - 0: Means no failure and that the data of key5 is reliable 1: Means that programming key5 failed and the number of error bytes is over 6. - 3 - 1 - read-only - - - SYS_PART2_ERR_NUM - The value of this signal means the number of error bytes. - 4 - 3 - read-only - - - SYS_PART2_FAIL - 0: Means no failure and that the data of system part2 is reliable 1: Means that programming user data failed and the number of error bytes is over 6. - 7 - 1 - read-only - - - - - CLK - eFuse clcok configuration register. - 0x1C8 - 0x20 - - - MEM_FORCE_PD - Set this bit to force eFuse SRAM into power-saving mode. - 0 - 1 - read-write - - - MEM_CLK_FORCE_ON - Set this bit and force to activate clock signal of eFuse SRAM. - 1 - 1 - read-write - - - MEM_FORCE_PU - Set this bit to force eFuse SRAM into working mode. - 2 - 1 - read-write - - - EN - Set this bit to force enable eFuse register configuration clock signal. - 16 - 1 - read-write - - - - - CONF - eFuse operation mode configuraiton register - 0x1CC - 0x20 - - - OP_CODE - 0x5A5A: programming operation command 0x5AA5: read operation command. - 0 - 16 - read-write - - - CFG_ECDSA_BLK - Configures which block to use for ECDSA key output. - 16 - 4 - read-write - - - - - STATUS - eFuse status register. - 0x1D0 - 0x20 - - - STATE - Indicates the state of the eFuse state machine. - 0 - 4 - read-only - - - OTP_LOAD_SW - The value of OTP_LOAD_SW. - 4 - 1 - read-only - - - OTP_VDDQ_C_SYNC2 - The value of OTP_VDDQ_C_SYNC2. - 5 - 1 - read-only - - - OTP_STROBE_SW - The value of OTP_STROBE_SW. - 6 - 1 - read-only - - - OTP_CSB_SW - The value of OTP_CSB_SW. - 7 - 1 - read-only - - - OTP_PGENB_SW - The value of OTP_PGENB_SW. - 8 - 1 - read-only - - - OTP_VDDQ_IS_SW - The value of OTP_VDDQ_IS_SW. - 9 - 1 - read-only - - - BLK0_VALID_BIT_CNT - Indicates the number of block valid bit. - 10 - 10 - read-only - - - CUR_ECDSA_BLK - Indicates which block is used for ECDSA key output. - 20 - 4 - read-only - - - - - CMD - eFuse command register. - 0x1D4 - 0x20 - - - READ_CMD - Set this bit to send read command. - 0 - 1 - read-write - - - PGM_CMD - Set this bit to send programming command. - 1 - 1 - read-write - - - BLK_NUM - The serial number of the block to be programmed. Value 0-10 corresponds to block number 0-10, respectively. - 2 - 4 - read-write - - - - - INT_RAW - eFuse raw interrupt register. - 0x1D8 - 0x20 - - - READ_DONE_INT_RAW - The raw bit signal for read_done interrupt. - 0 - 1 - read-only - - - PGM_DONE_INT_RAW - The raw bit signal for pgm_done interrupt. - 1 - 1 - read-only - - - - - INT_ST - eFuse interrupt status register. - 0x1DC - 0x20 - - - READ_DONE_INT_ST - The status signal for read_done interrupt. - 0 - 1 - read-only - - - PGM_DONE_INT_ST - The status signal for pgm_done interrupt. - 1 - 1 - read-only - - - - - INT_ENA - eFuse interrupt enable register. - 0x1E0 - 0x20 - - - READ_DONE_INT_ENA - The enable signal for read_done interrupt. - 0 - 1 - read-write - - - PGM_DONE_INT_ENA - The enable signal for pgm_done interrupt. - 1 - 1 - read-write - - - - - INT_CLR - eFuse interrupt clear register. - 0x1E4 - 0x20 - - - READ_DONE_INT_CLR - The clear signal for read_done interrupt. - 0 - 1 - write-only - - - PGM_DONE_INT_CLR - The clear signal for pgm_done interrupt. - 1 - 1 - write-only - - - - - DAC_CONF - Controls the eFuse programming voltage. - 0x1E8 - 0x20 - 0x0001FE17 - - - DAC_CLK_DIV - Controls the division factor of the rising clock of the programming voltage. - 0 - 8 - read-write - - - DAC_CLK_PAD_SEL - Don't care. - 8 - 1 - read-write - - - DAC_NUM - Controls the rising period of the programming voltage. - 9 - 8 - read-write - - - OE_CLR - Reduces the power supply of the programming voltage. - 17 - 1 - read-write - - - - - RD_TIM_CONF - Configures read timing parameters. - 0x1EC - 0x20 - 0x0F010201 - - - THR_A - Configures the read hold time. - 0 - 8 - read-write - - - TRD - Configures the read time. - 8 - 8 - read-write - - - TSUR_A - Configures the read setup time. - 16 - 8 - read-write - - - READ_INIT_NUM - Configures the waiting time of reading eFuse memory. - 24 - 8 - read-write - - - - - WR_TIM_CONF1 - Configurarion register 1 of eFuse programming timing parameters. - 0x1F0 - 0x20 - 0x01266701 - - - TSUP_A - Configures the programming setup time. - 0 - 8 - read-write - - - PWR_ON_NUM - Configures the power up time for VDDQ. - 8 - 16 - read-write - - - THP_A - Configures the programming hold time. - 24 - 8 - read-write - - - - - WR_TIM_CONF2 - Configurarion register 2 of eFuse programming timing parameters. - 0x1F4 - 0x20 - 0x00A00140 - - - PWR_OFF_NUM - Configures the power outage time for VDDQ. - 0 - 16 - read-write - - - TPGM - Configures the active programming time. - 16 - 16 - read-write - - - - - WR_TIM_CONF0_RS_BYPASS - Configurarion register0 of eFuse programming time parameters and rs bypass operation. - 0x1F8 - 0x20 - 0x00002000 - - - BYPASS_RS_CORRECTION - Set this bit to bypass reed solomon correction step. - 0 - 1 - read-write - - - BYPASS_RS_BLK_NUM - Configures block number of programming twice operation. - 1 - 11 - read-write - - - UPDATE - Set this bit to update multi-bit register signals. - 12 - 1 - write-only - - - TPGM_INACTIVE - Configures the inactive programming time. - 13 - 8 - read-write - - - - - DATE - eFuse version register. - 0x1FC - 0x20 - 0x02305050 - - - DATE - Stores eFuse version. - 0 - 28 - read-write - - - - - APB2OTP_WR_DIS - eFuse apb2otp block0 data register1. - 0x800 - 0x20 - - - APB2OTP_BLOCK0_WR_DIS - Otp block0 write disable data. - 0 - 32 - read-only - - - - - APB2OTP_BLK0_BACKUP1_W1 - eFuse apb2otp block0 data register2. - 0x804 - 0x20 - - - APB2OTP_BLOCK0_BACKUP1_W1 - Otp block0 backup1 word1 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK0_BACKUP1_W2 - eFuse apb2otp block0 data register3. - 0x808 - 0x20 - - - APB2OTP_BLOCK0_BACKUP1_W2 - Otp block0 backup1 word2 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK0_BACKUP1_W3 - eFuse apb2otp block0 data register4. - 0x80C - 0x20 - - - APB2OTP_BLOCK0_BACKUP1_W3 - Otp block0 backup1 word3 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK0_BACKUP1_W4 - eFuse apb2otp block0 data register5. - 0x810 - 0x20 - - - APB2OTP_BLOCK0_BACKUP1_W4 - Otp block0 backup1 word4 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK0_BACKUP1_W5 - eFuse apb2otp block0 data register6. - 0x814 - 0x20 - - - APB2OTP_BLOCK0_BACKUP1_W5 - Otp block0 backup1 word5 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK0_BACKUP2_W1 - eFuse apb2otp block0 data register7. - 0x818 - 0x20 - - - APB2OTP_BLOCK0_BACKUP2_W1 - Otp block0 backup2 word1 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK0_BACKUP2_W2 - eFuse apb2otp block0 data register8. - 0x81C - 0x20 - - - APB2OTP_BLOCK0_BACKUP2_W2 - Otp block0 backup2 word2 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK0_BACKUP2_W3 - eFuse apb2otp block0 data register9. - 0x820 - 0x20 - - - APB2OTP_BLOCK0_BACKUP2_W3 - Otp block0 backup2 word3 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK0_BACKUP2_W4 - eFuse apb2otp block0 data register10. - 0x824 - 0x20 - - - APB2OTP_BLOCK0_BACKUP2_W4 - Otp block0 backup2 word4 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK0_BACKUP2_W5 - eFuse apb2otp block0 data register11. - 0x828 - 0x20 - - - APB2OTP_BLOCK0_BACKUP2_W5 - Otp block0 backup2 word5 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK0_BACKUP3_W1 - eFuse apb2otp block0 data register12. - 0x82C - 0x20 - - - APB2OTP_BLOCK0_BACKUP3_W1 - Otp block0 backup3 word1 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK0_BACKUP3_W2 - eFuse apb2otp block0 data register13. - 0x830 - 0x20 - - - APB2OTP_BLOCK0_BACKUP3_W2 - Otp block0 backup3 word2 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK0_BACKUP3_W3 - eFuse apb2otp block0 data register14. - 0x834 - 0x20 - - - APB2OTP_BLOCK0_BACKUP3_W3 - Otp block0 backup3 word3 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK0_BACKUP3_W4 - eFuse apb2otp block0 data register15. - 0x838 - 0x20 - - - APB2OTP_BLOCK0_BACKUP3_W4 - Otp block0 backup3 word4 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK0_BACKUP3_W5 - eFuse apb2otp block0 data register16. - 0x83C - 0x20 - - - APB2OTP_BLOCK0_BACKUP3_W5 - Otp block0 backup3 word5 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK0_BACKUP4_W1 - eFuse apb2otp block0 data register17. - 0x840 - 0x20 - - - APB2OTP_BLOCK0_BACKUP4_W1 - Otp block0 backup4 word1 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK0_BACKUP4_W2 - eFuse apb2otp block0 data register18. - 0x844 - 0x20 - - - APB2OTP_BLOCK0_BACKUP4_W2 - Otp block0 backup4 word2 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK0_BACKUP4_W3 - eFuse apb2otp block0 data register19. - 0x848 - 0x20 - - - APB2OTP_BLOCK0_BACKUP4_W3 - Otp block0 backup4 word3 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK0_BACKUP4_W4 - eFuse apb2otp block0 data register20. - 0x84C - 0x20 - - - APB2OTP_BLOCK0_BACKUP4_W4 - Otp block0 backup4 word4 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK0_BACKUP4_W5 - eFuse apb2otp block0 data register21. - 0x850 - 0x20 - - - APB2OTP_BLOCK0_BACKUP4_W5 - Otp block0 backup4 word5 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK1_W1 - eFuse apb2otp block1 data register1. - 0x854 - 0x20 - - - APB2OTP_BLOCK1_W1 - Otp block1 word1 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK1_W2 - eFuse apb2otp block1 data register2. - 0x858 - 0x20 - - - APB2OTP_BLOCK1_W2 - Otp block1 word2 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK1_W3 - eFuse apb2otp block1 data register3. - 0x85C - 0x20 - - - APB2OTP_BLOCK1_W3 - Otp block1 word3 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK1_W4 - eFuse apb2otp block1 data register4. - 0x860 - 0x20 - - - APB2OTP_BLOCK1_W4 - Otp block1 word4 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK1_W5 - eFuse apb2otp block1 data register5. - 0x864 - 0x20 - - - APB2OTP_BLOCK1_W5 - Otp block1 word5 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK1_W6 - eFuse apb2otp block1 data register6. - 0x868 - 0x20 - - - APB2OTP_BLOCK1_W6 - Otp block1 word6 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK1_W7 - eFuse apb2otp block1 data register7. - 0x86C - 0x20 - - - APB2OTP_BLOCK1_W7 - Otp block1 word7 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK1_W8 - eFuse apb2otp block1 data register8. - 0x870 - 0x20 - - - APB2OTP_BLOCK1_W8 - Otp block1 word8 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK1_W9 - eFuse apb2otp block1 data register9. - 0x874 - 0x20 - - - APB2OTP_BLOCK1_W9 - Otp block1 word9 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK2_W1 - eFuse apb2otp block2 data register1. - 0x878 - 0x20 - - - APB2OTP_BLOCK2_W1 - Otp block2 word1 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK2_W2 - eFuse apb2otp block2 data register2. - 0x87C - 0x20 - - - APB2OTP_BLOCK2_W2 - Otp block2 word2 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK2_W3 - eFuse apb2otp block2 data register3. - 0x880 - 0x20 - - - APB2OTP_BLOCK2_W3 - Otp block2 word3 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK2_W4 - eFuse apb2otp block2 data register4. - 0x884 - 0x20 - - - APB2OTP_BLOCK2_W4 - Otp block2 word4 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK2_W5 - eFuse apb2otp block2 data register5. - 0x888 - 0x20 - - - APB2OTP_BLOCK2_W5 - Otp block2 word5 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK2_W6 - eFuse apb2otp block2 data register6. - 0x88C - 0x20 - - - APB2OTP_BLOCK2_W6 - Otp block2 word6 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK2_W7 - eFuse apb2otp block2 data register7. - 0x890 - 0x20 - - - APB2OTP_BLOCK2_W7 - Otp block2 word7 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK2_W8 - eFuse apb2otp block2 data register8. - 0x894 - 0x20 - - - APB2OTP_BLOCK2_W8 - Otp block2 word8 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK2_W9 - eFuse apb2otp block2 data register9. - 0x898 - 0x20 - - - APB2OTP_BLOCK2_W9 - Otp block2 word9 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK2_W10 - eFuse apb2otp block2 data register10. - 0x89C - 0x20 - - - APB2OTP_BLOCK2_W10 - Otp block2 word10 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK2_W11 - eFuse apb2otp block2 data register11. - 0x8A0 - 0x20 - - - APB2OTP_BLOCK2_W11 - Otp block2 word11 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK3_W1 - eFuse apb2otp block3 data register1. - 0x8A4 - 0x20 - - - APB2OTP_BLOCK3_W1 - Otp block3 word1 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK3_W2 - eFuse apb2otp block3 data register2. - 0x8A8 - 0x20 - - - APB2OTP_BLOCK3_W2 - Otp block3 word2 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK3_W3 - eFuse apb2otp block3 data register3. - 0x8AC - 0x20 - - - APB2OTP_BLOCK3_W3 - Otp block3 word3 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK3_W4 - eFuse apb2otp block3 data register4. - 0x8B0 - 0x20 - - - APB2OTP_BLOCK3_W4 - Otp block3 word4 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK3_W5 - eFuse apb2otp block3 data register5. - 0x8B4 - 0x20 - - - APB2OTP_BLOCK3_W5 - Otp block3 word5 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK3_W6 - eFuse apb2otp block3 data register6. - 0x8B8 - 0x20 - - - APB2OTP_BLOCK3_W6 - Otp block3 word6 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK3_W7 - eFuse apb2otp block3 data register7. - 0x8BC - 0x20 - - - APB2OTP_BLOCK3_W7 - Otp block3 word7 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK3_W8 - eFuse apb2otp block3 data register8. - 0x8C0 - 0x20 - - - APB2OTP_BLOCK3_W8 - Otp block3 word8 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK3_W9 - eFuse apb2otp block3 data register9. - 0x8C4 - 0x20 - - - APB2OTP_BLOCK3_W9 - Otp block3 word9 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK3_W10 - eFuse apb2otp block3 data register10. - 0x8C8 - 0x20 - - - APB2OTP_BLOCK3_W10 - Otp block3 word10 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK3_W11 - eFuse apb2otp block3 data register11. - 0x8CC - 0x20 - - - APB2OTP_BLOCK3_W11 - Otp block3 word11 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK4_W1 - eFuse apb2otp block4 data register1. - 0x8D0 - 0x20 - - - APB2OTP_BLOCK4_W1 - Otp block4 word1 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK4_W2 - eFuse apb2otp block4 data register2. - 0x8D4 - 0x20 - - - APB2OTP_BLOCK4_W2 - Otp block4 word2 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK4_W3 - eFuse apb2otp block4 data register3. - 0x8D8 - 0x20 - - - APB2OTP_BLOCK4_W3 - Otp block4 word3 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK4_W4 - eFuse apb2otp block4 data register4. - 0x8DC - 0x20 - - - APB2OTP_BLOCK4_W4 - Otp block4 word4 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK4_W5 - eFuse apb2otp block4 data register5. - 0x8E0 - 0x20 - - - APB2OTP_BLOCK4_W5 - Otp block4 word5 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK4_W6 - eFuse apb2otp block4 data register6. - 0x8E4 - 0x20 - - - APB2OTP_BLOCK4_W6 - Otp block4 word6 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK4_W7 - eFuse apb2otp block4 data register7. - 0x8E8 - 0x20 - - - APB2OTP_BLOCK4_W7 - Otp block4 word7 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK4_W8 - eFuse apb2otp block4 data register8. - 0x8EC - 0x20 - - - APB2OTP_BLOCK4_W8 - Otp block4 word8 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK4_W9 - eFuse apb2otp block4 data register9. - 0x8F0 - 0x20 - - - APB2OTP_BLOCK4_W9 - Otp block4 word9 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK4_W10 - eFuse apb2otp block4 data registe10. - 0x8F4 - 0x20 - - - APB2OTP_BLOCK4_W10 - Otp block4 word10 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK4_W11 - eFuse apb2otp block4 data register11. - 0x8F8 - 0x20 - - - APB2OTP_BLOCK4_W11 - Otp block4 word11 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK5_W1 - eFuse apb2otp block5 data register1. - 0x8FC - 0x20 - - - APB2OTP_BLOCK5_W1 - Otp block5 word1 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK5_W2 - eFuse apb2otp block5 data register2. - 0x900 - 0x20 - - - APB2OTP_BLOCK5_W2 - Otp block5 word2 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK5_W3 - eFuse apb2otp block5 data register3. - 0x904 - 0x20 - - - APB2OTP_BLOCK5_W3 - Otp block5 word3 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK5_W4 - eFuse apb2otp block5 data register4. - 0x908 - 0x20 - - - APB2OTP_BLOCK5_W4 - Otp block5 word4 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK5_W5 - eFuse apb2otp block5 data register5. - 0x90C - 0x20 - - - APB2OTP_BLOCK5_W5 - Otp block5 word5 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK5_W6 - eFuse apb2otp block5 data register6. - 0x910 - 0x20 - - - APB2OTP_BLOCK5_W6 - Otp block5 word6 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK5_W7 - eFuse apb2otp block5 data register7. - 0x914 - 0x20 - - - APB2OTP_BLOCK5_W7 - Otp block5 word7 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK5_W8 - eFuse apb2otp block5 data register8. - 0x918 - 0x20 - - - APB2OTP_BLOCK5_W8 - Otp block5 word8 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK5_W9 - eFuse apb2otp block5 data register9. - 0x91C - 0x20 - - - APB2OTP_BLOCK5_W9 - Otp block5 word9 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK5_W10 - eFuse apb2otp block5 data register10. - 0x920 - 0x20 - - - APB2OTP_BLOCK5_W10 - Otp block5 word10 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK5_W11 - eFuse apb2otp block5 data register11. - 0x924 - 0x20 - - - APB2OTP_BLOCK5_W11 - Otp block5 word11 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK6_W1 - eFuse apb2otp block6 data register1. - 0x928 - 0x20 - - - APB2OTP_BLOCK6_W1 - Otp block6 word1 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK6_W2 - eFuse apb2otp block6 data register2. - 0x92C - 0x20 - - - APB2OTP_BLOCK6_W2 - Otp block6 word2 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK6_W3 - eFuse apb2otp block6 data register3. - 0x930 - 0x20 - - - APB2OTP_BLOCK6_W3 - Otp block6 word3 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK6_W4 - eFuse apb2otp block6 data register4. - 0x934 - 0x20 - - - APB2OTP_BLOCK6_W4 - Otp block6 word4 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK6_W5 - eFuse apb2otp block6 data register5. - 0x938 - 0x20 - - - APB2OTP_BLOCK6_W5 - Otp block6 word5 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK6_W6 - eFuse apb2otp block6 data register6. - 0x93C - 0x20 - - - APB2OTP_BLOCK6_W6 - Otp block6 word6 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK6_W7 - eFuse apb2otp block6 data register7. - 0x940 - 0x20 - - - APB2OTP_BLOCK6_W7 - Otp block6 word7 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK6_W8 - eFuse apb2otp block6 data register8. - 0x944 - 0x20 - - - APB2OTP_BLOCK6_W8 - Otp block6 word8 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK6_W9 - eFuse apb2otp block6 data register9. - 0x948 - 0x20 - - - APB2OTP_BLOCK6_W9 - Otp block6 word9 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK6_W10 - eFuse apb2otp block6 data register10. - 0x94C - 0x20 - - - APB2OTP_BLOCK6_W10 - Otp block6 word10 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK6_W11 - eFuse apb2otp block6 data register11. - 0x950 - 0x20 - - - APB2OTP_BLOCK6_W11 - Otp block6 word11 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK7_W1 - eFuse apb2otp block7 data register1. - 0x954 - 0x20 - - - APB2OTP_BLOCK7_W1 - Otp block7 word1 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK7_W2 - eFuse apb2otp block7 data register2. - 0x958 - 0x20 - - - APB2OTP_BLOCK7_W2 - Otp block7 word2 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK7_W3 - eFuse apb2otp block7 data register3. - 0x95C - 0x20 - - - APB2OTP_BLOCK7_W3 - Otp block7 word3 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK7_W4 - eFuse apb2otp block7 data register4. - 0x960 - 0x20 - - - APB2OTP_BLOCK7_W4 - Otp block7 word4 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK7_W5 - eFuse apb2otp block7 data register5. - 0x964 - 0x20 - - - APB2OTP_BLOCK7_W5 - Otp block7 word5 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK7_W6 - eFuse apb2otp block7 data register6. - 0x968 - 0x20 - - - APB2OTP_BLOCK7_W6 - Otp block7 word6 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK7_W7 - eFuse apb2otp block7 data register7. - 0x96C - 0x20 - - - APB2OTP_BLOCK7_W7 - Otp block7 word7 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK7_W8 - eFuse apb2otp block7 data register8. - 0x970 - 0x20 - - - APB2OTP_BLOCK7_W8 - Otp block7 word8 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK7_W9 - eFuse apb2otp block7 data register9. - 0x974 - 0x20 - - - APB2OTP_BLOCK7_W9 - Otp block7 word9 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK7_W10 - eFuse apb2otp block7 data register10. - 0x978 - 0x20 - - - APB2OTP_BLOCK7_W10 - Otp block7 word10 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK7_W11 - eFuse apb2otp block7 data register11. - 0x97C - 0x20 - - - APB2OTP_BLOCK7_W11 - Otp block7 word11 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK8_W1 - eFuse apb2otp block8 data register1. - 0x980 - 0x20 - - - APB2OTP_BLOCK8_W1 - Otp block8 word1 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK8_W2 - eFuse apb2otp block8 data register2. - 0x984 - 0x20 - - - APB2OTP_BLOCK8_W2 - Otp block8 word2 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK8_W3 - eFuse apb2otp block8 data register3. - 0x988 - 0x20 - - - APB2OTP_BLOCK8_W3 - Otp block8 word3 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK8_W4 - eFuse apb2otp block8 data register4. - 0x98C - 0x20 - - - APB2OTP_BLOCK8_W4 - Otp block8 word4 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK8_W5 - eFuse apb2otp block8 data register5. - 0x990 - 0x20 - - - APB2OTP_BLOCK8_W5 - Otp block8 word5 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK8_W6 - eFuse apb2otp block8 data register6. - 0x994 - 0x20 - - - APB2OTP_BLOCK8_W6 - Otp block8 word6 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK8_W7 - eFuse apb2otp block8 data register7. - 0x998 - 0x20 - - - APB2OTP_BLOCK8_W7 - Otp block8 word7 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK8_W8 - eFuse apb2otp block8 data register8. - 0x99C - 0x20 - - - APB2OTP_BLOCK8_W8 - Otp block8 word8 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK8_W9 - eFuse apb2otp block8 data register9. - 0x9A0 - 0x20 - - - APB2OTP_BLOCK8_W9 - Otp block8 word9 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK8_W10 - eFuse apb2otp block8 data register10. - 0x9A4 - 0x20 - - - APB2OTP_BLOCK8_W10 - Otp block8 word10 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK8_W11 - eFuse apb2otp block8 data register11. - 0x9A8 - 0x20 - - - APB2OTP_BLOCK8_W11 - Otp block8 word11 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK9_W1 - eFuse apb2otp block9 data register1. - 0x9AC - 0x20 - - - APB2OTP_BLOCK9_W1 - Otp block9 word1 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK9_W2 - eFuse apb2otp block9 data register2. - 0x9B0 - 0x20 - - - APB2OTP_BLOCK9_W2 - Otp block9 word2 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK9_W3 - eFuse apb2otp block9 data register3. - 0x9B4 - 0x20 - - - APB2OTP_BLOCK9_W3 - Otp block9 word3 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK9_W4 - eFuse apb2otp block9 data register4. - 0x9B8 - 0x20 - - - APB2OTP_BLOCK9_W4 - Otp block9 word4 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK9_W5 - eFuse apb2otp block9 data register5. - 0x9BC - 0x20 - - - APB2OTP_BLOCK9_W5 - Otp block9 word5 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK9_W6 - eFuse apb2otp block9 data register6. - 0x9C0 - 0x20 - - - APB2OTP_BLOCK9_W6 - Otp block9 word6 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK9_W7 - eFuse apb2otp block9 data register7. - 0x9C4 - 0x20 - - - APB2OTP_BLOCK9_W7 - Otp block9 word7 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK9_W8 - eFuse apb2otp block9 data register8. - 0x9C8 - 0x20 - - - APB2OTP_BLOCK9_W8 - Otp block9 word8 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK9_W9 - eFuse apb2otp block9 data register9. - 0x9CC - 0x20 - - - APB2OTP_BLOCK9_W9 - Otp block9 word9 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK9_W10 - eFuse apb2otp block9 data register10. - 0x9D0 - 0x20 - - - APB2OTP_BLOCK9_W10 - Otp block9 word10 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK9_W11 - eFuse apb2otp block9 data register11. - 0x9D4 - 0x20 - - - APB2OTP_BLOCK9_W11 - Otp block9 word11 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK10_W1 - eFuse apb2otp block10 data register1. - 0x9D8 - 0x20 - - - APB2OTP_BLOCK10_W1 - Otp block10 word1 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK10_W2 - eFuse apb2otp block10 data register2. - 0x9DC - 0x20 - - - APB2OTP_BLOCK10_W2 - Otp block10 word2 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK10_W3 - eFuse apb2otp block10 data register3. - 0x9E0 - 0x20 - - - APB2OTP_BLOCK10_W3 - Otp block10 word3 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK10_W4 - eFuse apb2otp block10 data register4. - 0x9E4 - 0x20 - - - APB2OTP_BLOCK10_W4 - Otp block10 word4 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK10_W5 - eFuse apb2otp block10 data register5. - 0x9E8 - 0x20 - - - APB2OTP_BLOCK10_W5 - Otp block10 word5 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK10_W6 - eFuse apb2otp block10 data register6. - 0x9EC - 0x20 - - - APB2OTP_BLOCK10_W6 - Otp block10 word6 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK10_W7 - eFuse apb2otp block10 data register7. - 0x9F0 - 0x20 - - - APB2OTP_BLOCK10_W7 - Otp block10 word7 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK10_W8 - eFuse apb2otp block10 data register8. - 0x9F4 - 0x20 - - - APB2OTP_BLOCK10_W8 - Otp block10 word8 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK10_W9 - eFuse apb2otp block10 data register9. - 0x9F8 - 0x20 - - - APB2OTP_BLOCK10_W9 - Otp block10 word9 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK10_W10 - eFuse apb2otp block10 data register10. - 0x9FC - 0x20 - - - APB2OTP_BLOCK19_W10 - Otp block10 word10 data. - 0 - 32 - read-only - - - - - APB2OTP_BLK10_W11 - eFuse apb2otp block10 data register11. - 0xA00 - 0x20 - - - APB2OTP_BLOCK10_W11 - Otp block10 word11 data. - 0 - 32 - read-only - - - - - APB2OTP_EN - eFuse apb2otp enable configuration register. - 0xA08 - 0x20 - - - APB2OTP_APB2OTP_EN - Apb2otp mode enable signal. - 0 - 1 - read-write - - - - - - - GPIO - General Purpose Input/Output - GPIO - 0x500E0000 - - 0x0 - 0x5F8 - registers - - - GPIO_INT0 - 74 - - - GPIO_INT1 - 75 - - - GPIO_INT2 - 76 - - - GPIO_INT3 - 77 - - - GPIO_PAD_COMP - 78 - - - - BT_SELECT - GPIO bit select register - 0x0 - 0x20 - - - BT_SEL - GPIO bit select register - 0 - 32 - read-write - - - - - OUT - GPIO output register for GPIO0-31 - 0x4 - 0x20 - - - DATA_ORIG - GPIO output register for GPIO0-31 - 0 - 32 - read-write - - - - - OUT_W1TS - GPIO output set register for GPIO0-31 - 0x8 - 0x20 - - - OUT_W1TS - GPIO output set register for GPIO0-31 - 0 - 32 - write-only - - - - - OUT_W1TC - GPIO output clear register for GPIO0-31 - 0xC - 0x20 - - - OUT_W1TC - GPIO output clear register for GPIO0-31 - 0 - 32 - write-only - - - - - OUT1 - GPIO output register for GPIO32-56 - 0x10 - 0x20 - - - DATA_ORIG - GPIO output register for GPIO32-56 - 0 - 25 - read-write - - - - - OUT1_W1TS - GPIO output set register for GPIO32-56 - 0x14 - 0x20 - - - OUT1_W1TS - GPIO output set register for GPIO32-56 - 0 - 25 - write-only - - - - - OUT1_W1TC - GPIO output clear register for GPIO32-56 - 0x18 - 0x20 - - - OUT1_W1TC - GPIO output clear register for GPIO32-56 - 0 - 25 - write-only - - - - - ENABLE - GPIO output enable register for GPIO0-31 - 0x20 - 0x20 - - - DATA - GPIO output enable register for GPIO0-31 - 0 - 32 - read-write - - - - - ENABLE_W1TS - GPIO output enable set register for GPIO0-31 - 0x24 - 0x20 - - - ENABLE_W1TS - GPIO output enable set register for GPIO0-31 - 0 - 32 - write-only - - - - - ENABLE_W1TC - GPIO output enable clear register for GPIO0-31 - 0x28 - 0x20 - - - ENABLE_W1TC - GPIO output enable clear register for GPIO0-31 - 0 - 32 - write-only - - - - - ENABLE1 - GPIO output enable register for GPIO32-56 - 0x2C - 0x20 - - - DATA - GPIO output enable register for GPIO32-56 - 0 - 25 - read-write - - - - - ENABLE1_W1TS - GPIO output enable set register for GPIO32-56 - 0x30 - 0x20 - - - ENABLE1_W1TS - GPIO output enable set register for GPIO32-56 - 0 - 25 - write-only - - - - - ENABLE1_W1TC - GPIO output enable clear register for GPIO32-56 - 0x34 - 0x20 - - - ENABLE1_W1TC - GPIO output enable clear register for GPIO32-56 - 0 - 25 - write-only - - - - - STRAP - pad strapping register - 0x38 - 0x20 - - - STRAPPING - pad strapping register - 0 - 16 - read-only - - - - - IN - GPIO input register for GPIO0-31 - 0x3C - 0x20 - - - DATA_NEXT - GPIO input register for GPIO0-31 - 0 - 32 - read-only - - - - - IN1 - GPIO input register for GPIO32-56 - 0x40 - 0x20 - - - DATA_NEXT - GPIO input register for GPIO32-56 - 0 - 25 - read-only - - - - - STATUS - GPIO interrupt status register for GPIO0-31 - 0x44 - 0x20 - - - INTERRUPT - GPIO interrupt status register for GPIO0-31 - 0 - 32 - read-write - - - - - STATUS_W1TS - GPIO interrupt status set register for GPIO0-31 - 0x48 - 0x20 - - - STATUS_W1TS - GPIO interrupt status set register for GPIO0-31 - 0 - 32 - write-only - - - - - STATUS_W1TC - GPIO interrupt status clear register for GPIO0-31 - 0x4C - 0x20 - - - STATUS_W1TC - GPIO interrupt status clear register for GPIO0-31 - 0 - 32 - write-only - - - - - STATUS1 - GPIO interrupt status register for GPIO32-56 - 0x50 - 0x20 - - - INTERRUPT - GPIO interrupt status register for GPIO32-56 - 0 - 25 - read-write - - - - - STATUS1_W1TS - GPIO interrupt status set register for GPIO32-56 - 0x54 - 0x20 - - - STATUS1_W1TS - GPIO interrupt status set register for GPIO32-56 - 0 - 25 - write-only - - - - - STATUS1_W1TC - GPIO interrupt status clear register for GPIO32-56 - 0x58 - 0x20 - - - STATUS1_W1TC - GPIO interrupt status clear register for GPIO32-56 - 0 - 25 - write-only - - - - - INTR_0 - GPIO interrupt 0 status register for GPIO0-31 - 0x5C - 0x20 - - - INT_0 - GPIO interrupt 0 status register for GPIO0-31 - 0 - 32 - read-only - - - - - INTR1_0 - GPIO interrupt 0 status register for GPIO32-56 - 0x60 - 0x20 - - - INT1_0 - GPIO interrupt 0 status register for GPIO32-56 - 0 - 25 - read-only - - - - - INTR_1 - GPIO interrupt 1 status register for GPIO0-31 - 0x64 - 0x20 - - - INT_1 - GPIO interrupt 1 status register for GPIO0-31 - 0 - 32 - read-only - - - - - INTR1_1 - GPIO interrupt 1 status register for GPIO32-56 - 0x68 - 0x20 - - - INT1_1 - GPIO interrupt 1 status register for GPIO32-56 - 0 - 25 - read-only - - - - - STATUS_NEXT - GPIO interrupt source register for GPIO0-31 - 0x6C - 0x20 - - - STATUS_INTERRUPT_NEXT - GPIO interrupt source register for GPIO0-31 - 0 - 32 - read-only - - - - - STATUS_NEXT1 - GPIO interrupt source register for GPIO32-56 - 0x70 - 0x20 - - - STATUS_INTERRUPT_NEXT1 - GPIO interrupt source register for GPIO32-56 - 0 - 25 - read-only - - - - - 57 - 0x4 - PIN%s - GPIO pin configuration register - 0x74 - 0x20 - - - SYNC2_BYPASS - set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge. - 0 - 2 - read-write - - - PAD_DRIVER - set this bit to select pad driver. 1:open-drain. 0:normal. - 2 - 1 - read-write - - - SYNC1_BYPASS - set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge. - 3 - 2 - read-write - - - INT_TYPE - set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid at high level - 7 - 3 - read-write - - - WAKEUP_ENABLE - set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) - 10 - 1 - read-write - - - CONFIG - reserved - 11 - 2 - read-write - - - INT_ENA - set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) interrupt. - 13 - 5 - read-write - - - - - 57 - 0x4 - FUNC%s_OUT_SEL_CFG - GPIO output function select register - 0x558 - 0x20 - 0x00000100 - - - OUT_SEL - The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. - 0 - 9 - read-write - - - INV_SEL - set this bit to invert output signal.1:invert.0:not invert. - 9 - 1 - read-write - - - OEN_SEL - set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output enable signal.0:use peripheral output enable signal. - 10 - 1 - read-write - - - OEN_INV_SEL - set this bit to invert output enable signal.1:invert.0:not invert. - 11 - 1 - read-write - - - - - INTR_2 - GPIO interrupt 2 status register for GPIO0-31 - 0x63C - 0x20 - - - INT_2 - GPIO interrupt 2 status register for GPIO0-31 - 0 - 32 - read-only - - - - - INTR1_2 - GPIO interrupt 2 status register for GPIO32-56 - 0x640 - 0x20 - - - INT1_2 - GPIO interrupt 2 status register for GPIO32-56 - 0 - 25 - read-only - - - - - INTR_3 - GPIO interrupt 3 status register for GPIO0-31 - 0x644 - 0x20 - - - INT_3 - GPIO interrupt 3 status register for GPIO0-31 - 0 - 32 - read-only - - - - - INTR1_3 - GPIO interrupt 3 status register for GPIO32-56 - 0x648 - 0x20 - - - INT1_3 - GPIO interrupt 3 status register for GPIO32-56 - 0 - 25 - read-only - - - - - CLOCK_GATE - GPIO clock gate register - 0x64C - 0x20 - 0x00000001 - - - CLK_EN - set this bit to enable GPIO clock gate - 0 - 1 - read-write - - - - - INT_RAW - analog comparator interrupt raw - 0x700 - 0x20 - - - COMP0_NEG_INT_RAW - analog comparator pos edge interrupt raw - 0 - 1 - read-write - - - COMP0_POS_INT_RAW - analog comparator neg edge interrupt raw - 1 - 1 - read-write - - - COMP0_ALL_INT_RAW - analog comparator neg or pos edge interrupt raw - 2 - 1 - read-write - - - COMP1_NEG_INT_RAW - analog comparator pos edge interrupt raw - 3 - 1 - read-write - - - COMP1_POS_INT_RAW - analog comparator neg edge interrupt raw - 4 - 1 - read-write - - - COMP1_ALL_INT_RAW - analog comparator neg or pos edge interrupt raw - 5 - 1 - read-write - - - BISTOK_INT_RAW - pad bistok interrupt raw - 6 - 1 - read-write - - - BISTFAIL_INT_RAW - pad bistfail interrupt raw - 7 - 1 - read-write - - - - - INT_ST - analog comparator interrupt status - 0x704 - 0x20 - - - COMP0_NEG_INT_ST - analog comparator pos edge interrupt status - 0 - 1 - read-only - - - COMP0_POS_INT_ST - analog comparator neg edge interrupt status - 1 - 1 - read-only - - - COMP0_ALL_INT_ST - analog comparator neg or pos edge interrupt status - 2 - 1 - read-only - - - COMP1_NEG_INT_ST - analog comparator pos edge interrupt status - 3 - 1 - read-only - - - COMP1_POS_INT_ST - analog comparator neg edge interrupt status - 4 - 1 - read-only - - - COMP1_ALL_INT_ST - analog comparator neg or pos edge interrupt status - 5 - 1 - read-only - - - BISTOK_INT_ST - pad bistok interrupt status - 6 - 1 - read-only - - - BISTFAIL_INT_ST - pad bistfail interrupt status - 7 - 1 - read-only - - - - - INT_ENA - analog comparator interrupt enable - 0x708 - 0x20 - 0x000000FF - - - COMP0_NEG_INT_ENA - analog comparator pos edge interrupt enable - 0 - 1 - read-write - - - COMP0_POS_INT_ENA - analog comparator neg edge interrupt enable - 1 - 1 - read-write - - - COMP0_ALL_INT_ENA - analog comparator neg or pos edge interrupt enable - 2 - 1 - read-write - - - COMP1_NEG_INT_ENA - analog comparator pos edge interrupt enable - 3 - 1 - read-write - - - COMP1_POS_INT_ENA - analog comparator neg edge interrupt enable - 4 - 1 - read-write - - - COMP1_ALL_INT_ENA - analog comparator neg or pos edge interrupt enable - 5 - 1 - read-write - - - BISTOK_INT_ENA - pad bistok interrupt enable - 6 - 1 - read-write - - - BISTFAIL_INT_ENA - pad bistfail interrupt enable - 7 - 1 - read-write - - - - - INT_CLR - analog comparator interrupt clear - 0x70C - 0x20 - - - COMP0_NEG_INT_CLR - analog comparator pos edge interrupt clear - 0 - 1 - write-only - - - COMP0_POS_INT_CLR - analog comparator neg edge interrupt clear - 1 - 1 - write-only - - - COMP0_ALL_INT_CLR - analog comparator neg or pos edge interrupt clear - 2 - 1 - write-only - - - COMP1_NEG_INT_CLR - analog comparator pos edge interrupt clear - 3 - 1 - write-only - - - COMP1_POS_INT_CLR - analog comparator neg edge interrupt clear - 4 - 1 - write-only - - - COMP1_ALL_INT_CLR - analog comparator neg or pos edge interrupt clear - 5 - 1 - write-only - - - BISTOK_INT_CLR - pad bistok interrupt enable - 6 - 1 - write-only - - - BISTFAIL_INT_CLR - pad bistfail interrupt enable - 7 - 1 - write-only - - - - - ZERO_DET0_FILTER_CNT - GPIO analog comparator zero detect filter count - 0x710 - 0x20 - 0xFFFFFFFF - - - ZERO_DET0_FILTER_CNT - GPIO analog comparator zero detect filter count - 0 - 32 - read-write - - - - - ZERO_DET1_FILTER_CNT - GPIO analog comparator zero detect filter count - 0x714 - 0x20 - 0xFFFFFFFF - - - ZERO_DET1_FILTER_CNT - GPIO analog comparator zero detect filter count - 0 - 32 - read-write - - - - - SEND_SEQ - High speed sdio pad bist send sequence - 0x718 - 0x20 - 0x12345678 - - - SEND_SEQ - High speed sdio pad bist send sequence - 0 - 32 - read-write - - - - - RECIVE_SEQ - High speed sdio pad bist recive sequence - 0x71C - 0x20 - - - RECIVE_SEQ - High speed sdio pad bist recive sequence - 0 - 32 - read-only - - - - - BISTIN_SEL - High speed sdio pad bist in pad sel - 0x720 - 0x20 - 0x0000000F - - - BISTIN_SEL - High speed sdio pad bist in pad sel 0:pad39, 1: pad40... - 0 - 4 - read-write - - - - - BIST_CTRL - High speed sdio pad bist control - 0x724 - 0x20 - 0x00000001 - - - BIST_PAD_OE - High speed sdio pad bist out pad oe - 0 - 1 - read-write - - - BIST_START - High speed sdio pad bist start - 1 - 1 - write-only - - - - - DATE - GPIO version register - 0x7FC - 0x20 - 0x00230403 - - - DATE - version register - 0 - 28 - read-write - - - - - 254 - 0x4 - 1-254 - FUNC%s_IN_SEL_CFG - GPIO input function configuration register - 0x15C - 0x20 - read-write - - - IN_SEL - set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. - 0 - 6 - - - IN_INV_SEL - set this bit to invert input signal. 1:invert. 0:not invert. - 6 - 1 - - - SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - 7 - 1 - - - - - - - GPIO_SD - Sigma-Delta Modulation - GPIOSD - 0x500E0F00 - - 0x0 - 0xA4 - registers - - - - 8 - 0x4 - SIGMADELTA%s - Duty Cycle Configure Register of SDM%s - 0x0 - 0x20 - 0x0000FF00 - - - SD_IN - This field is used to configure the duty cycle of sigma delta modulation output. - 0 - 8 - read-write - - - SD_PRESCALE - This field is used to set a divider value to divide APB clock. - 8 - 8 - read-write - - - - - CLOCK_GATE - Clock Gating Configure Register - 0x20 - 0x20 - - - CLK_EN - Clock enable bit of configuration registers for sigma delta modulation. - 0 - 1 - read-write - - - - - SIGMADELTA_MISC - MISC Register - 0x24 - 0x20 - - - FUNCTION_CLK_EN - Clock enable bit of sigma delta modulation. - 30 - 1 - read-write - - - SPI_SWAP - Reserved. - 31 - 1 - read-write - - - - - 8 - 0x4 - GLITCH_FILTER_CH%s - Glitch Filter Configure Register of Channel%s - 0x30 - 0x20 - - - FILTER_CH0_EN - Glitch Filter channel enable bit. - 0 - 1 - read-write - - - FILTER_CH0_INPUT_IO_NUM - Glitch Filter input io number. - 1 - 6 - read-write - - - FILTER_CH0_WINDOW_THRES - Glitch Filter window threshold. - 7 - 6 - read-write - - - FILTER_CH0_WINDOW_WIDTH - Glitch Filter window width. - 13 - 6 - read-write - - - - - 8 - 0x4 - ETM_EVENT_CH%s_CFG - Etm Config register of Channel%s - 0x60 - 0x20 - - - ETM_CH0_EVENT_SEL - Etm event channel select gpio. - 0 - 6 - read-write - - - ETM_CH0_EVENT_EN - Etm event send enable bit. - 7 - 1 - read-write - - - - - ETM_TASK_P0_CFG - Etm Configure Register to decide which GPIO been chosen - 0xA0 - 0x20 - - - ETM_TASK_GPIO0_EN - Enable bit of GPIO response etm task. - 0 - 1 - read-write - - - ETM_TASK_GPIO0_SEL - GPIO choose a etm task channel. - 1 - 3 - read-write - - - ETM_TASK_GPIO1_EN - Enable bit of GPIO response etm task. - 8 - 1 - read-write - - - ETM_TASK_GPIO1_SEL - GPIO choose a etm task channel. - 9 - 3 - read-write - - - ETM_TASK_GPIO2_EN - Enable bit of GPIO response etm task. - 16 - 1 - read-write - - - ETM_TASK_GPIO2_SEL - GPIO choose a etm task channel. - 17 - 3 - read-write - - - ETM_TASK_GPIO3_EN - Enable bit of GPIO response etm task. - 24 - 1 - read-write - - - ETM_TASK_GPIO3_SEL - GPIO choose a etm task channel. - 25 - 3 - read-write - - - - - ETM_TASK_P1_CFG - Etm Configure Register to decide which GPIO been chosen - 0xA4 - 0x20 - - - ETM_TASK_GPIO4_EN - Enable bit of GPIO response etm task. - 0 - 1 - read-write - - - ETM_TASK_GPIO4_SEL - GPIO choose a etm task channel. - 1 - 3 - read-write - - - ETM_TASK_GPIO5_EN - Enable bit of GPIO response etm task. - 8 - 1 - read-write - - - ETM_TASK_GPIO5_SEL - GPIO choose a etm task channel. - 9 - 3 - read-write - - - ETM_TASK_GPIO6_EN - Enable bit of GPIO response etm task. - 16 - 1 - read-write - - - ETM_TASK_GPIO6_SEL - GPIO choose a etm task channel. - 17 - 3 - read-write - - - ETM_TASK_GPIO7_EN - Enable bit of GPIO response etm task. - 24 - 1 - read-write - - - ETM_TASK_GPIO7_SEL - GPIO choose a etm task channel. - 25 - 3 - read-write - - - - - ETM_TASK_P2_CFG - Etm Configure Register to decide which GPIO been chosen - 0xA8 - 0x20 - - - ETM_TASK_GPIO8_EN - Enable bit of GPIO response etm task. - 0 - 1 - read-write - - - ETM_TASK_GPIO8_SEL - GPIO choose a etm task channel. - 1 - 3 - read-write - - - ETM_TASK_GPIO9_EN - Enable bit of GPIO response etm task. - 8 - 1 - read-write - - - ETM_TASK_GPIO9_SEL - GPIO choose a etm task channel. - 9 - 3 - read-write - - - ETM_TASK_GPIO10_EN - Enable bit of GPIO response etm task. - 16 - 1 - read-write - - - ETM_TASK_GPIO10_SEL - GPIO choose a etm task channel. - 17 - 3 - read-write - - - ETM_TASK_GPIO11_EN - Enable bit of GPIO response etm task. - 24 - 1 - read-write - - - ETM_TASK_GPIO11_SEL - GPIO choose a etm task channel. - 25 - 3 - read-write - - - - - ETM_TASK_P3_CFG - Etm Configure Register to decide which GPIO been chosen - 0xAC - 0x20 - - - ETM_TASK_GPIO12_EN - Enable bit of GPIO response etm task. - 0 - 1 - read-write - - - ETM_TASK_GPIO12_SEL - GPIO choose a etm task channel. - 1 - 3 - read-write - - - ETM_TASK_GPIO13_EN - Enable bit of GPIO response etm task. - 8 - 1 - read-write - - - ETM_TASK_GPIO13_SEL - GPIO choose a etm task channel. - 9 - 3 - read-write - - - ETM_TASK_GPIO14_EN - Enable bit of GPIO response etm task. - 16 - 1 - read-write - - - ETM_TASK_GPIO14_SEL - GPIO choose a etm task channel. - 17 - 3 - read-write - - - ETM_TASK_GPIO15_EN - Enable bit of GPIO response etm task. - 24 - 1 - read-write - - - ETM_TASK_GPIO15_SEL - GPIO choose a etm task channel. - 25 - 3 - read-write - - - - - ETM_TASK_P4_CFG - Etm Configure Register to decide which GPIO been chosen - 0xB0 - 0x20 - - - ETM_TASK_GPIO16_EN - Enable bit of GPIO response etm task. - 0 - 1 - read-write - - - ETM_TASK_GPIO16_SEL - GPIO choose a etm task channel. - 1 - 3 - read-write - - - ETM_TASK_GPIO17_EN - Enable bit of GPIO response etm task. - 8 - 1 - read-write - - - ETM_TASK_GPIO17_SEL - GPIO choose a etm task channel. - 9 - 3 - read-write - - - ETM_TASK_GPIO18_EN - Enable bit of GPIO response etm task. - 16 - 1 - read-write - - - ETM_TASK_GPIO18_SEL - GPIO choose a etm task channel. - 17 - 3 - read-write - - - ETM_TASK_GPIO19_EN - Enable bit of GPIO response etm task. - 24 - 1 - read-write - - - ETM_TASK_GPIO19_SEL - GPIO choose a etm task channel. - 25 - 3 - read-write - - - - - ETM_TASK_P5_CFG - Etm Configure Register to decide which GPIO been chosen - 0xB4 - 0x20 - - - ETM_TASK_GPIO20_EN - Enable bit of GPIO response etm task. - 0 - 1 - read-write - - - ETM_TASK_GPIO20_SEL - GPIO choose a etm task channel. - 1 - 3 - read-write - - - ETM_TASK_GPIO21_EN - Enable bit of GPIO response etm task. - 8 - 1 - read-write - - - ETM_TASK_GPIO21_SEL - GPIO choose a etm task channel. - 9 - 3 - read-write - - - ETM_TASK_GPIO22_EN - Enable bit of GPIO response etm task. - 16 - 1 - read-write - - - ETM_TASK_GPIO22_SEL - GPIO choose a etm task channel. - 17 - 3 - read-write - - - ETM_TASK_GPIO23_EN - Enable bit of GPIO response etm task. - 24 - 1 - read-write - - - ETM_TASK_GPIO23_SEL - GPIO choose a etm task channel. - 25 - 3 - read-write - - - - - ETM_TASK_P6_CFG - Etm Configure Register to decide which GPIO been chosen - 0xB8 - 0x20 - - - ETM_TASK_GPIO24_EN - Enable bit of GPIO response etm task. - 0 - 1 - read-write - - - ETM_TASK_GPIO24_SEL - GPIO choose a etm task channel. - 1 - 3 - read-write - - - ETM_TASK_GPIO25_EN - Enable bit of GPIO response etm task. - 8 - 1 - read-write - - - ETM_TASK_GPIO25_SEL - GPIO choose a etm task channel. - 9 - 3 - read-write - - - ETM_TASK_GPIO26_EN - Enable bit of GPIO response etm task. - 16 - 1 - read-write - - - ETM_TASK_GPIO26_SEL - GPIO choose a etm task channel. - 17 - 3 - read-write - - - ETM_TASK_GPIO27_EN - Enable bit of GPIO response etm task. - 24 - 1 - read-write - - - ETM_TASK_GPIO27_SEL - GPIO choose a etm task channel. - 25 - 3 - read-write - - - - - ETM_TASK_P7_CFG - Etm Configure Register to decide which GPIO been chosen - 0xBC - 0x20 - - - ETM_TASK_GPIO28_EN - Enable bit of GPIO response etm task. - 0 - 1 - read-write - - - ETM_TASK_GPIO28_SEL - GPIO choose a etm task channel. - 1 - 3 - read-write - - - ETM_TASK_GPIO29_EN - Enable bit of GPIO response etm task. - 8 - 1 - read-write - - - ETM_TASK_GPIO29_SEL - GPIO choose a etm task channel. - 9 - 3 - read-write - - - ETM_TASK_GPIO30_EN - Enable bit of GPIO response etm task. - 16 - 1 - read-write - - - ETM_TASK_GPIO30_SEL - GPIO choose a etm task channel. - 17 - 3 - read-write - - - ETM_TASK_GPIO31_EN - Enable bit of GPIO response etm task. - 24 - 1 - read-write - - - ETM_TASK_GPIO31_SEL - GPIO choose a etm task channel. - 25 - 3 - read-write - - - - - ETM_TASK_P8_CFG - Etm Configure Register to decide which GPIO been chosen - 0xC0 - 0x20 - - - ETM_TASK_GPIO32_EN - Enable bit of GPIO response etm task. - 0 - 1 - read-write - - - ETM_TASK_GPIO32_SEL - GPIO choose a etm task channel. - 1 - 3 - read-write - - - ETM_TASK_GPIO33_EN - Enable bit of GPIO response etm task. - 8 - 1 - read-write - - - ETM_TASK_GPIO33_SEL - GPIO choose a etm task channel. - 9 - 3 - read-write - - - ETM_TASK_GPIO34_EN - Enable bit of GPIO response etm task. - 16 - 1 - read-write - - - ETM_TASK_GPIO34_SEL - GPIO choose a etm task channel. - 17 - 3 - read-write - - - ETM_TASK_GPIO35_EN - Enable bit of GPIO response etm task. - 24 - 1 - read-write - - - ETM_TASK_GPIO35_SEL - GPIO choose a etm task channel. - 25 - 3 - read-write - - - - - ETM_TASK_P9_CFG - Etm Configure Register to decide which GPIO been chosen - 0xC4 - 0x20 - - - ETM_TASK_GPIO36_EN - Enable bit of GPIO response etm task. - 0 - 1 - read-write - - - ETM_TASK_GPIO36_SEL - GPIO choose a etm task channel. - 1 - 3 - read-write - - - ETM_TASK_GPIO37_EN - Enable bit of GPIO response etm task. - 8 - 1 - read-write - - - ETM_TASK_GPIO37_SEL - GPIO choose a etm task channel. - 9 - 3 - read-write - - - ETM_TASK_GPIO38_EN - Enable bit of GPIO response etm task. - 16 - 1 - read-write - - - ETM_TASK_GPIO38_SEL - GPIO choose a etm task channel. - 17 - 3 - read-write - - - ETM_TASK_GPIO39_EN - Enable bit of GPIO response etm task. - 24 - 1 - read-write - - - ETM_TASK_GPIO39_SEL - GPIO choose a etm task channel. - 25 - 3 - read-write - - - - - ETM_TASK_P10_CFG - Etm Configure Register to decide which GPIO been chosen - 0xC8 - 0x20 - - - ETM_TASK_GPIO40_EN - Enable bit of GPIO response etm task. - 0 - 1 - read-write - - - ETM_TASK_GPIO40_SEL - GPIO choose a etm task channel. - 1 - 3 - read-write - - - ETM_TASK_GPIO41_EN - Enable bit of GPIO response etm task. - 8 - 1 - read-write - - - ETM_TASK_GPIO41_SEL - GPIO choose a etm task channel. - 9 - 3 - read-write - - - ETM_TASK_GPIO42_EN - Enable bit of GPIO response etm task. - 16 - 1 - read-write - - - ETM_TASK_GPIO42_SEL - GPIO choose a etm task channel. - 17 - 3 - read-write - - - ETM_TASK_GPIO43_EN - Enable bit of GPIO response etm task. - 24 - 1 - read-write - - - ETM_TASK_GPIO43_SEL - GPIO choose a etm task channel. - 25 - 3 - read-write - - - - - ETM_TASK_P11_CFG - Etm Configure Register to decide which GPIO been chosen - 0xCC - 0x20 - - - ETM_TASK_GPIO44_EN - Enable bit of GPIO response etm task. - 0 - 1 - read-write - - - ETM_TASK_GPIO44_SEL - GPIO choose a etm task channel. - 1 - 3 - read-write - - - ETM_TASK_GPIO45_EN - Enable bit of GPIO response etm task. - 8 - 1 - read-write - - - ETM_TASK_GPIO45_SEL - GPIO choose a etm task channel. - 9 - 3 - read-write - - - ETM_TASK_GPIO46_EN - Enable bit of GPIO response etm task. - 16 - 1 - read-write - - - ETM_TASK_GPIO46_SEL - GPIO choose a etm task channel. - 17 - 3 - read-write - - - ETM_TASK_GPIO47_EN - Enable bit of GPIO response etm task. - 24 - 1 - read-write - - - ETM_TASK_GPIO47_SEL - GPIO choose a etm task channel. - 25 - 3 - read-write - - - - - ETM_TASK_P12_CFG - Etm Configure Register to decide which GPIO been chosen - 0xD0 - 0x20 - - - ETM_TASK_GPIO48_EN - Enable bit of GPIO response etm task. - 0 - 1 - read-write - - - ETM_TASK_GPIO48_SEL - GPIO choose a etm task channel. - 1 - 3 - read-write - - - ETM_TASK_GPIO49_EN - Enable bit of GPIO response etm task. - 8 - 1 - read-write - - - ETM_TASK_GPIO49_SEL - GPIO choose a etm task channel. - 9 - 3 - read-write - - - ETM_TASK_GPIO50_EN - Enable bit of GPIO response etm task. - 16 - 1 - read-write - - - ETM_TASK_GPIO50_SEL - GPIO choose a etm task channel. - 17 - 3 - read-write - - - ETM_TASK_GPIO51_EN - Enable bit of GPIO response etm task. - 24 - 1 - read-write - - - ETM_TASK_GPIO51_SEL - GPIO choose a etm task channel. - 25 - 3 - read-write - - - - - ETM_TASK_P13_CFG - Etm Configure Register to decide which GPIO been chosen - 0xD4 - 0x20 - - - ETM_TASK_GPIO52_EN - Enable bit of GPIO response etm task. - 0 - 1 - read-write - - - ETM_TASK_GPIO52_SEL - GPIO choose a etm task channel. - 1 - 3 - read-write - - - ETM_TASK_GPIO53_EN - Enable bit of GPIO response etm task. - 8 - 1 - read-write - - - ETM_TASK_GPIO53_SEL - GPIO choose a etm task channel. - 9 - 3 - read-write - - - ETM_TASK_GPIO54_EN - Enable bit of GPIO response etm task. - 16 - 1 - read-write - - - ETM_TASK_GPIO54_SEL - GPIO choose a etm task channel. - 17 - 3 - read-write - - - - - VERSION - Version Control Register - 0xFC - 0x20 - 0x02203050 - - - GPIO_SD_DATE - Version control register. - 0 - 28 - read-write - - - - - - - H264 - H264 Encoder (Core) - H264 - 0x50084000 - - 0x0 - 0xF4 - registers - - - H264_REG - 126 - - - - SYS_CTRL - H264 system level control register. - 0x0 - 0x20 - - - FRAME_START - Configures whether or not to start encoding one frame.\\0: Invalid. No effect\\1: Start encoding one frame - 0 - 1 - write-only - - - DMA_MOVE_START - Configures whether or not to start moving reference data from external mem.\\0: Invalid. No effect\\1: H264 start moving two MB lines of reference frame from external mem to internal mem - 1 - 1 - write-only - - - FRAME_MODE - Configures H264 running mode. When field H264_DUAL_STREAM_MODE is set to 1, this field must be set to 1 too.\\0: GOP mode. Before every GOP first frame start, need reconfig reference frame DMA\\1: Frame mode. Before every frame start, need reconfig reference frame DMA - 2 - 1 - read-write - - - SYS_RST_PULSE - Configures whether or not to reset H264 ip.\\0: Invalid. No effect\\1: Reset H264 ip - 3 - 1 - write-only - - - - - GOP_CONF - GOP related configuration register. - 0x4 - 0x20 - - - DUAL_STREAM_MODE - Configures whether or not to enable dual stream mode. When this field is set to 1, H264_FRAME_MODE field must be set to 1 too.\\0: Normal mode\\1: Dual stream mode - 0 - 1 - read-write - - - GOP_NUM - Configures the frame number of one GOP.\\0: The frame number of one GOP is infinite\\Others: Actual frame number of one GOP - 1 - 8 - read-write - - - - - A_SYS_MB_RES - Video A horizontal and vertical MB resolution register. - 0x8 - 0x20 - - - A_SYS_TOTAL_MB_Y - Configures video A vertical MB resolution. - 0 - 7 - read-write - - - A_SYS_TOTAL_MB_X - Configures video A horizontal MB resolution. - 7 - 7 - read-write - - - - - A_SYS_CONF - Video A system level configuration register. - 0xC - 0x20 - 0x00000203 - - - A_DB_TMP_READY_TRIGGER_MB_NUM - Configures when to trigger video A H264_DB_TMP_READY_INT. When the (MB number of written db temp+1) is greater than this filed in first MB line, trigger H264_DB_TMP_READY_INT. Min is 3. - 0 - 7 - read-write - - - A_REC_READY_TRIGGER_MB_LINES - Configures when to trigger video A H264_REC_READY_INT. When the MB line number of generated reconstruct pixel is greater than this filed, trigger H264_REC_READY_INT. Min is 4. - 7 - 7 - read-write - - - A_INTRA_COST_CMP_OFFSET - Configures video A intra cost offset when I MB compared with P MB. - 14 - 16 - read-write - - - - - A_DECI_SCORE - Video A luma and chroma MB decimate score Register. - 0x10 - 0x20 - - - A_C_DECI_SCORE - Configures video A chroma MB decimate score. When chroma score is smaller than it, chroma decimate will be enable. - 0 - 10 - read-write - - - A_L_DECI_SCORE - Configures video A luma MB decimate score. When luma score is smaller than it, luma decimate will be enable. - 10 - 10 - read-write - - - - - A_DECI_SCORE_OFFSET - Video A luma and chroma MB decimate score offset Register. - 0x14 - 0x20 - - - A_I16X16_DECI_SCORE_OFFSET - Configures video A i16x16 MB decimate score offset. This offset will be added to i16x16 MB score. - 0 - 6 - read-write - - - A_I_CHROMA_DECI_SCORE_OFFSET - Configures video A I chroma MB decimate score offset. This offset will be added to I chroma MB score. - 6 - 6 - read-write - - - A_P16X16_DECI_SCORE_OFFSET - Configures video A p16x16 MB decimate score offset. This offset will be added to p16x16 MB score. - 12 - 6 - read-write - - - A_P_CHROMA_DECI_SCORE_OFFSET - Configures video A p chroma MB decimate score offset. This offset will be added to p chroma MB score. - 18 - 6 - read-write - - - - - A_RC_CONF0 - Video A rate control configuration register0. - 0x18 - 0x20 - - - A_QP - Configures video A frame level initial luma QP value. - 0 - 6 - read-write - - - A_RATE_CTRL_U - Configures video A parameter U value. U = int((float) u << 8). - 6 - 16 - read-write - - - A_MB_RATE_CTRL_EN - Configures video A whether or not to open macro block rate ctrl.\\1:Open the macro block rate ctrl\\1:Close the macro block rate ctrl. - 22 - 1 - read-write - - - - - A_RC_CONF1 - Video A rate control configuration register1. - 0x1C - 0x20 - - - A_CHROMA_DC_QP_DELTA - Configures video A chroma DC QP offset based on Chroma QP. Chroma DC QP = Chroma QP(after map) + reg_chroma_dc_qp_delta. - 0 - 3 - read-write - - - A_CHROMA_QP_DELTA - Configures video A chroma QP offset based on luma QP. Chroma QP(before map) = Luma QP + reg_chroma_qp_delta. - 3 - 4 - read-write - - - A_QP_MIN - Configures video A allowed luma QP min value. - 7 - 6 - read-write - - - A_QP_MAX - Configures video A allowed luma QP max value. - 13 - 6 - read-write - - - A_MAD_FRAME_PRED - Configures vdieo A frame level predicted MB MAD value. - 19 - 12 - read-write - - - - - A_DB_BYPASS - Video A Deblocking bypass register - 0x20 - 0x20 - - - A_BYPASS_DB_FILTER - Configures whether or not to bypass video A deblcoking filter. \\0: Open the deblock filter\\1: Close the deblock filter - 0 - 1 - read-write - - - - - A_ROI_REGION0 - Video A H264 ROI region0 range configure register. - 0x24 - 0x20 - - - X - Configures the horizontal start macroblocks of region 0 in Video A. - 0 - 7 - read-write - - - Y - Configures the vertical start macroblocks of region 0 in Video A. - 7 - 7 - read-write - - - X_LEN - Configures the number of macroblocks in horizontal direction of the region 0 in Video A. - 14 - 7 - read-write - - - Y_LEN - Configures the number of macroblocks in vertical direction of the region 0 in Video A. - 21 - 7 - read-write - - - EN - Configures whether or not to open Video A ROI of region 0 .\\0:Close ROI\\1:Open ROI. - 28 - 1 - read-write - - - - - A_ROI_REGION1 - Video A H264 ROI region1 range configure register. - 0x28 - 0x20 - - - X - Configures the horizontal start macroblocks of region 1 in Video A. - 0 - 7 - read-write - - - Y - Configures the vertical start macroblocks of region 1 in Video A. - 7 - 7 - read-write - - - X_LEN - Configures the number of macroblocks in horizontal direction of the region 1 in Video A. - 14 - 7 - read-write - - - Y_LEN - Configures the number of macroblocks in vertical direction of the region 1 in Video A. - 21 - 7 - read-write - - - EN - Configures whether or not to open Video A ROI of region 1 .\\0:Close ROI\\1:Open ROI. - 28 - 1 - read-write - - - - - A_ROI_REGION2 - Video A H264 ROI region2 range configure register. - 0x2C - 0x20 - - - X - Configures the horizontal start macroblocks of region 2 in Video A. - 0 - 7 - read-write - - - Y - Configures the vertical start macroblocks of region 2 in Video A. - 7 - 7 - read-write - - - X_LEN - Configures the number of macroblocks in horizontal direction of the region 2 in Video A. - 14 - 7 - read-write - - - Y_LEN - Configures the number of macroblocks in vertical direction of the region 2 in Video A. - 21 - 7 - read-write - - - EN - Configures whether or not to open Video A ROI of region 2 .\\0:Close ROI\\1:Open ROI. - 28 - 1 - read-write - - - - - A_ROI_REGION3 - Video A H264 ROI region3 range configure register. - 0x30 - 0x20 - - - X - Configures the horizontal start macroblocks of region 3 in Video A. - 0 - 7 - read-write - - - Y - Configures the vertical start macroblocks of region 3 in Video A. - 7 - 7 - read-write - - - X_LEN - Configures the number of macroblocks in horizontal direction of the region 3 in video A. - 14 - 7 - read-write - - - Y_LEN - Configures the number of macroblocks in vertical direction of the region 3 in video A. - 21 - 7 - read-write - - - EN - Configures whether or not to open Video A ROI of region 3 .\\0:Close ROI\\1:Open ROI. - 28 - 1 - read-write - - - - - A_ROI_REGION4 - Video A H264 ROI region4 range configure register. - 0x34 - 0x20 - - - X - Configures the horizontal start macroblocks of region 4 in Video A. - 0 - 7 - read-write - - - Y - Configures the vertical start macroblocks of region 4 in Video A. - 7 - 7 - read-write - - - X_LEN - Configures the number of macroblocks in horizontal direction of the region 4 in video A. - 14 - 7 - read-write - - - Y_LEN - Configures the number of macroblocks in vertical direction of the region 4 in video A. - 21 - 7 - read-write - - - EN - Configures whether or not to open Video A ROI of region 4 .\\0:Close ROI\\1:Open ROI. - 28 - 1 - read-write - - - - - A_ROI_REGION5 - Video A H264 ROI region5 range configure register. - 0x38 - 0x20 - - - X - Configures the horizontial start macroblocks of region 5 video A. - 0 - 7 - read-write - - - Y - Configures the vertical start macroblocks of region 5 video A. - 7 - 7 - read-write - - - X_LEN - Configures the number of macroblocks in horizontal direction of the region 5 video A. - 14 - 7 - read-write - - - Y_LEN - Configures the number of macroblocks in vertical direction of the region 5 in video A. - 21 - 7 - read-write - - - EN - Configures whether or not to open Video A ROI of region 5 .\\0:Close ROI\\1:Open ROI. - 28 - 1 - read-write - - - - - A_ROI_REGION6 - Video A H264 ROI region6 range configure register. - 0x3C - 0x20 - - - X - Configures the horizontial start macroblocks of region 6 video A. - 0 - 7 - read-write - - - Y - Configures the vertical start macroblocks of region 6 in video A. - 7 - 7 - read-write - - - X_LEN - Configures the number of macroblocks in horizontal direction of the region 6 in video A. - 14 - 7 - read-write - - - Y_LEN - Configures the number of macroblocks in vertical direction of the region 6 in video A. - 21 - 7 - read-write - - - EN - Configures whether or not to open Video A ROI of region 6 .\\0:Close ROI\\1:Open ROI. - 28 - 1 - read-write - - - - - A_ROI_REGION7 - Video A H264 ROI region7 range configure register. - 0x40 - 0x20 - - - X - Configures the horizontal start macroblocks of region 7 in video A. - 0 - 7 - read-write - - - Y - Configures the vertical start macroblocks of region 7 in video A. - 7 - 7 - read-write - - - X_LEN - Configures the number of macroblocks in horizontal direction of the region 7 in video A. - 14 - 7 - read-write - - - Y_LEN - Configures the number of macroblocks in vertical direction of the region 7 in video A. - 21 - 7 - read-write - - - EN - Configures whether or not to open Video A ROI of region 7 .\\0:Close ROI\\1:Open ROI. - 28 - 1 - read-write - - - - - A_ROI_REGION0_3_QP - Video A H264 ROI region0, region1,region2,region3 QP register. - 0x44 - 0x20 - - - A_ROI_REGION0_QP - Configure H264 ROI region0 qp in video A,fixed qp or delta qp. - 0 - 7 - read-write - - - A_ROI_REGION1_QP - Configure H264 ROI region1 qp in video A,fixed qp or delta qp. - 7 - 7 - read-write - - - A_ROI_REGION2_QP - Configure H264 ROI region2 qp in video A,fixed qp or delta qp. - 14 - 7 - read-write - - - A_ROI_REGION3_QP - Configure H264 ROI region3 qp in video A,fixed qp or delta qp. - 21 - 7 - read-write - - - - - A_ROI_REGION4_7_QP - Video A H264 ROI region4, region5,region6,region7 QP register. - 0x48 - 0x20 - - - A_ROI_REGION4_QP - Configure H264 ROI region4 qp in video A,fixed qp or delta qp. - 0 - 7 - read-write - - - A_ROI_REGION5_QP - Configure H264 ROI region5 qp in video A,fixed qp or delta qp. - 7 - 7 - read-write - - - A_ROI_REGION6_QP - Configure H264 ROI region6 qp in video A,fixed qp or delta qp. - 14 - 7 - read-write - - - A_ROI_REGION7_QP - Configure H264 ROI region7 qp in video A,fixed qp or delta qp. - 21 - 7 - read-write - - - - - A_NO_ROI_REGION_QP_OFFSET - Video A H264 no roi region QP register. - 0x4C - 0x20 - - - A_NO_ROI_REGION_QP - Configure H264 no region qp in video A, delta qp. - 0 - 7 - read-write - - - - - A_ROI_CONFIG - Video A H264 ROI configure register. - 0x50 - 0x20 - - - A_ROI_EN - Configure whether or not to enable ROI in video A.\\0:not enable ROI\\1:enable ROI. - 0 - 1 - read-write - - - A_ROI_MODE - Configure the mode of ROI in video A.\\0:fixed qp\\1:delta qp. - 1 - 1 - read-write - - - - - B_SYS_MB_RES - Video B horizontal and vertical MB resolution register. - 0x54 - 0x20 - - - B_SYS_TOTAL_MB_Y - Configures video B vertical MB resolution. - 0 - 7 - read-write - - - B_SYS_TOTAL_MB_X - Configures video B horizontal MB resolution. - 7 - 7 - read-write - - - - - B_SYS_CONF - Video B system level configuration register. - 0x58 - 0x20 - 0x00000203 - - - B_DB_TMP_READY_TRIGGER_MB_NUM - Configures when to trigger video B H264_DB_TMP_READY_INT. When the (MB number of written db temp+1) is greater than this filed in first MB line, trigger H264_DB_TMP_READY_INT. Min is 3. - 0 - 7 - read-write - - - B_REC_READY_TRIGGER_MB_LINES - Configures when to trigger video B H264_REC_READY_INT. When the MB line number of generated reconstruct pixel is greater than this filed, trigger H264_REC_READY_INT. Min is 4. - 7 - 7 - read-write - - - B_INTRA_COST_CMP_OFFSET - Configures video B intra cost offset when I MB compared with P MB. - 14 - 16 - read-write - - - - - B_DECI_SCORE - Video B luma and chroma MB decimate score Register. - 0x5C - 0x20 - - - B_C_DECI_SCORE - Configures video B chroma MB decimate score. When chroma score is smaller than it, chroma decimate will be enable. - 0 - 10 - read-write - - - B_L_DECI_SCORE - Configures video B luma MB decimate score. When luma score is smaller than it, luma decimate will be enable. - 10 - 10 - read-write - - - - - B_DECI_SCORE_OFFSET - Video B luma and chroma MB decimate score offset Register. - 0x60 - 0x20 - - - B_I16X16_DECI_SCORE_OFFSET - Configures video B i16x16 MB decimate score offset. This offset will be added to i16x16 MB score. - 0 - 6 - read-write - - - B_I_CHROMA_DECI_SCORE_OFFSET - Configures video B I chroma MB decimate score offset. This offset will be added to I chroma MB score. - 6 - 6 - read-write - - - B_P16X16_DECI_SCORE_OFFSET - Configures video B p16x16 MB decimate score offset. This offset will be added to p16x16 MB score. - 12 - 6 - read-write - - - B_P_CHROMA_DECI_SCORE_OFFSET - Configures video B p chroma MB decimate score offset. This offset will be added to p chroma MB score. - 18 - 6 - read-write - - - - - B_RC_CONF0 - Video B rate control configuration register0. - 0x64 - 0x20 - - - B_QP - Configures video B frame level initial luma QP value. - 0 - 6 - read-write - - - B_RATE_CTRL_U - Configures video B parameter U value. U = int((float) u << 8). - 6 - 16 - read-write - - - B_MB_RATE_CTRL_EN - Configures video A whether or not to open macro block rate ctrl.\\1:Open the macro block rate ctrl\\1:Close the macro block rate ctrl. - 22 - 1 - read-write - - - - - B_RC_CONF1 - Video B rate control configuration register1. - 0x68 - 0x20 - - - B_CHROMA_DC_QP_DELTA - Configures video B chroma DC QP offset based on Chroma QP. Chroma DC QP = Chroma QP(after map) + reg_chroma_dc_qp_delta. - 0 - 3 - read-write - - - B_CHROMA_QP_DELTA - Configures video B chroma QP offset based on luma QP. Chroma QP(before map) = Luma QP + reg_chroma_qp_delta. - 3 - 4 - read-write - - - B_QP_MIN - Configures video B allowed luma QP min value. - 7 - 6 - read-write - - - B_QP_MAX - Configures video B allowed luma QP max value. - 13 - 6 - read-write - - - B_MAD_FRAME_PRED - Configures vdieo B frame level predicted MB MAD value. - 19 - 12 - read-write - - - - - B_DB_BYPASS - Video B Deblocking bypass register - 0x6C - 0x20 - - - B_BYPASS_DB_FILTER - Configures whether or not to bypass video B deblcoking filter. \\0: Open the deblock filter\\1: Close the deblock filter - 0 - 1 - read-write - - - - - B_ROI_REGION0 - Video B H264 ROI region0 range configure register. - 0x70 - 0x20 - - - X - Configures the horizontal start macroblocks of region 0 in Video B. - 0 - 7 - read-write - - - Y - Configures the vertical start macroblocks of region 0 in Video B. - 7 - 7 - read-write - - - X_LEN - Configures the number of macroblocks in horizontal direction of the region 0 in Video B. - 14 - 7 - read-write - - - Y_LEN - Configures the number of macroblocks in vertical direction of the region 0 in Video B. - 21 - 7 - read-write - - - EN - Configures whether or not to open Video B ROI of region 0 .\\0:Close ROI\\1:Open ROI. - 28 - 1 - read-write - - - - - B_ROI_REGION1 - Video B H264 ROI region1 range configure register. - 0x74 - 0x20 - - - X - Configures the horizontal start macroblocks of region 1 in Video B. - 0 - 7 - read-write - - - Y - Configures the vertical start macroblocks of region 1 in Video B. - 7 - 7 - read-write - - - X_LEN - Configures the number of macroblocks in horizontal direction of the region 1 in Video B. - 14 - 7 - read-write - - - Y_LEN - Configures the number of macroblocks in vertical direction of the region 1 in Video B. - 21 - 7 - read-write - - - EN - Configures whether or not to open Video B ROI of region 1 .\\0:Close ROI\\1:Open ROI. - 28 - 1 - read-write - - - - - B_ROI_REGION2 - Video B H264 ROI region2 range configure register. - 0x78 - 0x20 - - - X - Configures the horizontal start macroblocks of region 2 in Video B. - 0 - 7 - read-write - - - Y - Configures the vertical start macroblocks of region 2 in Video B. - 7 - 7 - read-write - - - X_LEN - Configures the number of macroblocks in horizontal direction of the region 2 in Video B. - 14 - 7 - read-write - - - Y_LEN - Configures the number of macroblocks in vertical direction of the region 2 in Video B. - 21 - 7 - read-write - - - EN - Configures whether or not to open Video B ROI of region 2 .\\0:Close ROI\\1:Open ROI. - 28 - 1 - read-write - - - - - B_ROI_REGION3 - Video B H264 ROI region3 range configure register. - 0x7C - 0x20 - - - X - Configures the horizontal start macroblocks of region 3 in Video B. - 0 - 7 - read-write - - - Y - Configures the vertical start macroblocks of region 3 in Video B. - 7 - 7 - read-write - - - X_LEN - Configures the number of macroblocks in horizontal direction of the region 3 in video B. - 14 - 7 - read-write - - - Y_LEN - Configures the number of macroblocks in vertical direction of the region 3 in video B. - 21 - 7 - read-write - - - EN - Configures whether or not to open Video B ROI of region 3 .\\0:Close ROI\\1:Open ROI. - 28 - 1 - read-write - - - - - B_ROI_REGION4 - Video B H264 ROI region4 range configure register. - 0x80 - 0x20 - - - X - Configures the horizontal start macroblocks of region 4 in Video B. - 0 - 7 - read-write - - - Y - Configures the vertical start macroblocks of region 4 in Video B. - 7 - 7 - read-write - - - X_LEN - Configures the number of macroblocks in horizontal direction of the region 4 in video B. - 14 - 7 - read-write - - - Y_LEN - Configures the number of macroblocks in vertical direction of the region 4 in video B. - 21 - 7 - read-write - - - EN - Configures whether or not to open Video B ROI of region 4 .\\0:Close ROI\\1:Open ROI. - 28 - 1 - read-write - - - - - B_ROI_REGION5 - Video B H264 ROI region5 range configure register. - 0x84 - 0x20 - - - X - Configures the horizontial start macroblocks of region 5 video B. - 0 - 7 - read-write - - - Y - Configures the vertical start macroblocks of region 5 video B. - 7 - 7 - read-write - - - X_LEN - Configures the number of macroblocks in horizontal direction of the region 5 video B. - 14 - 7 - read-write - - - Y_LEN - Configures the number of macroblocks in vertical direction of the region 5 in video B. - 21 - 7 - read-write - - - EN - Configures whether or not to open Video B ROI of region 5 .\\0:Close ROI\\1:Open ROI. - 28 - 1 - read-write - - - - - B_ROI_REGION6 - Video B H264 ROI region6 range configure register. - 0x88 - 0x20 - - - X - Configures the horizontial start macroblocks of region 6 video B. - 0 - 7 - read-write - - - Y - Configures the vertical start macroblocks of region 6 in video B. - 7 - 7 - read-write - - - X_LEN - Configures the number of macroblocks in horizontal direction of the region 6 in video B. - 14 - 7 - read-write - - - Y_LEN - Configures the number of macroblocks in vertical direction of the region 6 in video B. - 21 - 7 - read-write - - - EN - Configures whether or not to open Video B ROI of region 6 .\\0:Close ROI\\1:Open ROI. - 28 - 1 - read-write - - - - - B_ROI_REGION7 - Video B H264 ROI region7 range configure register. - 0x8C - 0x20 - - - X - Configures the horizontal start macroblocks of region 7 in video B. - 0 - 7 - read-write - - - Y - Configures the vertical start macroblocks of region 7 in video B. - 7 - 7 - read-write - - - X_LEN - Configures the number of macroblocks in horizontal direction of the region 7 in video B. - 14 - 7 - read-write - - - Y_LEN - Configures the number of macroblocks in vertical direction of the region 7 in video B. - 21 - 7 - read-write - - - EN - Configures whether or not to open Video B ROI of region 7 .\\0:Close ROI\\1:Open ROI. - 28 - 1 - read-write - - - - - B_ROI_REGION0_3_QP - Video B H264 ROI region0, region1,region2,region3 QP register. - 0x90 - 0x20 - - - B_ROI_REGION0_QP - Configure H264 ROI region0 qp in video B,fixed qp or delta qp. - 0 - 7 - read-write - - - B_ROI_REGION1_QP - Configure H264 ROI region1 qp in video B,fixed qp or delta qp. - 7 - 7 - read-write - - - B_ROI_REGION2_QP - Configure H264 ROI region2 qp in video B,fixed qp or delta qp. - 14 - 7 - read-write - - - B_ROI_REGION3_QP - Configure H264 ROI region3 qp in video B,fixed qp or delta qp. - 21 - 7 - read-write - - - - - B_ROI_REGION4_7_QP - Video B H264 ROI region4, region5,region6,region7 QP register. - 0x94 - 0x20 - - - B_ROI_REGION4_QP - Configure H264 ROI region4 qp in video B,fixed qp or delta qp. - 0 - 7 - read-write - - - B_ROI_REGION5_QP - Configure H264 ROI region5 qp in video B,fixed qp or delta qp. - 7 - 7 - read-write - - - B_ROI_REGION6_QP - Configure H264 ROI region6 qp in video B,fixed qp or delta qp. - 14 - 7 - read-write - - - B_ROI_REGION7_QP - Configure H264 ROI region7 qp in video B,fixed qp or delta qp. - 21 - 7 - read-write - - - - - B_NO_ROI_REGION_QP_OFFSET - Video B H264 no roi region QP register. - 0x98 - 0x20 - - - B_NO_ROI_REGION_QP - Configure H264 no region qp in video B, delta qp. - 0 - 7 - read-write - - - - - B_ROI_CONFIG - Video B H264 ROI configure register. - 0x9C - 0x20 - - - B_ROI_EN - Configure whether or not to enable ROI in video B.\\0:not enable ROI\\1:enable ROI. - 0 - 1 - read-write - - - B_ROI_MODE - Configure the mode of ROI in video B.\\0:fixed qp\\1:delta qp. - 1 - 1 - read-write - - - - - RC_STATUS0 - Rate control status register0. - 0xA0 - 0x20 - - - FRAME_MAD_SUM - Represents all MB actual MAD sum value of one frame. - 0 - 21 - read-only - - - - - RC_STATUS1 - Rate control status register1. - 0xA4 - 0x20 - - - FRAME_ENC_BITS - Represents all MB actual encoding bits sum value of one frame. - 0 - 27 - read-only - - - - - RC_STATUS2 - Rate control status register2. - 0xA8 - 0x20 - - - FRAME_QP_SUM - Represents all MB actual luma QP sum value of one frame. - 0 - 19 - read-only - - - - - SLICE_HEADER_REMAIN - Frame Slice Header remain bit register. - 0xAC - 0x20 - - - SLICE_REMAIN_BITLENGTH - Configures Slice Header remain bit number - 0 - 3 - read-write - - - SLICE_REMAIN_BIT - Configures Slice Header remain bit - 3 - 8 - read-write - - - - - SLICE_HEADER_BYTE_LENGTH - Frame Slice Header byte length register. - 0xB0 - 0x20 - - - SLICE_BYTE_LENGTH - Configures Slice Header byte number - 0 - 4 - read-write - - - - - BS_THRESHOLD - Bitstream buffer overflow threshold register - 0xB4 - 0x20 - 0x00000030 - - - BS_BUFFER_THRESHOLD - Configures bitstream buffer overflow threshold. This value should be bigger than the encode bytes of one 4x4 submb. - 0 - 7 - read-write - - - - - SLICE_HEADER_BYTE0 - Frame Slice Header byte low 32 bit register. - 0xB8 - 0x20 - - - SLICE_BYTE_LSB - Configures Slice Header low 32 bit - 0 - 32 - read-write - - - - - SLICE_HEADER_BYTE1 - Frame Slice Header byte high 32 bit register. - 0xBC - 0x20 - - - SLICE_BYTE_MSB - Configures Slice Header high 32 bit - 0 - 32 - read-write - - - - - INT_RAW - Interrupt raw status register - 0xC0 - 0x20 - - - DB_TMP_READY_INT_RAW - Raw status bit: The raw interrupt status of H264_DB_TMP_READY_INT. Triggered when H264 written enough db tmp pixel. - 0 - 1 - read-write - - - REC_READY_INT_RAW - Raw status bit: The raw interrupt status of H264_REC_READY_INT. Triggered when H264 encoding enough reconstruct pixel. - 1 - 1 - read-write - - - FRAME_DONE_INT_RAW - Raw status bit: The raw interrupt status of H264_FRAME_DONE_INT. Triggered when H264 encoding one frame done. - 2 - 1 - read-write - - - DMA_MOVE_2MB_LINE_DONE_INT_RAW - Raw status bit: The raw interrupt status of H264_DMA_MOVE_2MB_LINE_DONE_INT. Triggered when H264 move two MB lines of reference frame from external mem to internal mem done. - 3 - 1 - read-write - - - - - INT_ST - Interrupt masked status register - 0xC4 - 0x20 - - - DB_TMP_READY_INT_ST - The masked interrupt status of H264_DB_TMP_READY_INT. Valid only when the H264_DB_TMP_READY_INT_ENA is set to 1. - 0 - 1 - read-only - - - REC_READY_INT_ST - The masked interrupt status of H264_REC_READY_INT. Valid only when the H264_REC_READY_INT_ENA is set to 1. - 1 - 1 - read-only - - - FRAME_DONE_INT_ST - The masked interrupt status of H264_FRAME_DONE_INT. Valid only when the H264_FRAME_DONE_INT_ENA is set to 1. - 2 - 1 - read-only - - - DMA_MOVE_2MB_LINE_DONE_INT_ST - Masked status bit: The masked interrupt status of H264_DMA_MOVE_2MB_LINE_DONE_INT. Valid only when the H264_DMA_MOVE_2MB_LINE_DONE_INT_ENA is set to 1. - 3 - 1 - read-only - - - - - INT_ENA - Interrupt enable register - 0xC8 - 0x20 - - - DB_TMP_READY_INT_ENA - Write 1 to enable H264_DB_TMP_READY_INT. - 0 - 1 - read-write - - - REC_READY_INT_ENA - Write 1 to enable H264_REC_READY_INT. - 1 - 1 - read-write - - - FRAME_DONE_INT_ENA - Write 1 to enable H264_FRAME_DONE_INT. - 2 - 1 - read-write - - - DMA_MOVE_2MB_LINE_DONE_INT_ENA - Enable bit: Write 1 to enable H264_DMA_MOVE_2MB_LINE_DONE_INT. - 3 - 1 - read-write - - - - - INT_CLR - Interrupt clear register - 0xCC - 0x20 - - - DB_TMP_READY_INT_CLR - Write 1 to clear H264_DB_TMP_READY_INT. - 0 - 1 - write-only - - - REC_READY_INT_CLR - Write 1 to clear H264_REC_READY_INT. - 1 - 1 - write-only - - - FRAME_DONE_INT_CLR - Write 1 to clear H264_FRAME_DONE_INT. - 2 - 1 - write-only - - - DMA_MOVE_2MB_LINE_DONE_INT_CLR - Clear bit: Write 1 to clear H264_DMA_MOVE_2MB_LINE_DONE_INT. - 3 - 1 - write-only - - - - - CONF - General configuration register. - 0xD0 - 0x20 - - - CLK_EN - Configures whether or not to open register clock gate.\\0: Open the clock gate only when application writes registers\\1: Force open the clock gate for register - 0 - 1 - read-write - - - REC_RAM_CLK_EN2 - Configures whether or not to open the clock gate for rec ram2.\\0: Open the clock gate only when application writes or reads rec ram2\\1: Force open the clock gate for rec ram2 - 1 - 1 - read-write - - - REC_RAM_CLK_EN1 - Configures whether or not to open the clock gate for rec ram1.\\0: Open the clock gate only when application writes or reads rec ram1\\1: Force open the clock gate for rec ram1 - 2 - 1 - read-write - - - QUANT_RAM_CLK_EN2 - Configures whether or not to open the clock gate for quant ram2.\\0: Open the clock gate only when application writes or reads quant ram2\\1: Force open the clock gate for quant ram2 - 3 - 1 - read-write - - - QUANT_RAM_CLK_EN1 - Configures whether or not to open the clock gate for quant ram1.\\0: Open the clock gate only when application writes or reads quant ram1\\1: Force open the clock gate for quant ram1 - 4 - 1 - read-write - - - PRE_RAM_CLK_EN - Configures whether or not to open the clock gate for pre ram.\\0: Open the clock gate only when application writes or reads pre ram\\1: Force open the clock gate for pre ram - 5 - 1 - read-write - - - MVD_RAM_CLK_EN - Configures whether or not to open the clock gate for mvd ram.\\0: Open the clock gate only when application writes or reads mvd ram\\1: Force open the clock gate for mvd ram - 6 - 1 - read-write - - - MC_RAM_CLK_EN - Configures whether or not to open the clock gate for mc ram.\\0: Open the clock gate only when application writes or reads mc ram\\1: Force open the clock gate for mc ram - 7 - 1 - read-write - - - REF_RAM_CLK_EN - Configures whether or not to open the clock gate for ref ram.\\0: Open the clock gate only when application writes or reads ref ram\\1: Force open the clock gate for ref ram - 8 - 1 - read-write - - - I4X4_REF_RAM_CLK_EN - Configures whether or not to open the clock gate for i4x4_mode ram.\\0: Open the clock gate only when application writes or reads i4x4_mode ram\\1: Force open the clock gate for i4x4_mode ram - 9 - 1 - read-write - - - IME_RAM_CLK_EN - Configures whether or not to open the clock gate for ime ram.\\0: Open the clock gate only when application writes or reads ime ram\\1: Force open the clock gate for ime ram - 10 - 1 - read-write - - - FME_RAM_CLK_EN - Configures whether or not to open the clock gate for fme ram.\\0: Open the clock gate only when application writes or readsfme ram\\1: Force open the clock gate for fme ram - 11 - 1 - read-write - - - FETCH_RAM_CLK_EN - Configures whether or not to open the clock gate for fetch ram.\\0: Open the clock gate only when application writes or reads fetch ram\\1: Force open the clock gate for fetch ram - 12 - 1 - read-write - - - DB_RAM_CLK_EN - Configures whether or not to open the clock gate for db ram.\\0: Open the clock gate only when application writes or reads db ram\\1: Force open the clock gate for db ram - 13 - 1 - read-write - - - CUR_MB_RAM_CLK_EN - Configures whether or not to open the clock gate for cur_mb ram.\\0: Open the clock gate only when application writes or reads cur_mb ram\\1: Force open the clock gate for cur_mb ram - 14 - 1 - read-write - - - CAVLC_RAM_CLK_EN - Configures whether or not to open the clock gate for cavlc ram.\\0: Open the clock gate only when application writes or reads cavlc ram\\1: Force open the clock gate for cavlc ram - 15 - 1 - read-write - - - IME_CLK_EN - Configures whether or not to open the clock gate for ime.\\0: Open the clock gate only when ime work\\1: Force open the clock gate for ime - 16 - 1 - read-write - - - FME_CLK_EN - Configures whether or not to open the clock gate for fme.\\0: Open the clock gate only when fme work\\1: Force open the clock gate for fme - 17 - 1 - read-write - - - MC_CLK_EN - Configures whether or not to open the clock gate for mc.\\0: Open the clock gate only when mc work\\1: Force open the clock gate for mc - 18 - 1 - read-write - - - INTERPOLATOR_CLK_EN - Configures whether or not to open the clock gate for interpolator.\\0: Open the clock gate only when interpolator work\\1: Force open the clock gate for interpolator - 19 - 1 - read-write - - - DB_CLK_EN - Configures whether or not to open the clock gate for deblocking filter.\\0: Open the clock gate only when deblocking filter work\\1: Force open the clock gate for deblocking filter - 20 - 1 - read-write - - - CLAVLC_CLK_EN - Configures whether or not to open the clock gate for cavlc.\\0: Open the clock gate only when cavlc work\\1: Force open the clock gate for cavlc - 21 - 1 - read-write - - - INTRA_CLK_EN - Configures whether or not to open the clock gate for intra.\\0: Open the clock gate only when intra work\\1: Force open the clock gate for intra - 22 - 1 - read-write - - - DECI_CLK_EN - Configures whether or not to open the clock gate for decimate.\\0: Open the clock gate only when decimate work\\1: Force open the clock gate for decimate - 23 - 1 - read-write - - - BS_CLK_EN - Configures whether or not to open the clock gate for bs buffer.\\0: Open the clock gate only when bs buffer work\\1: Force open the clock gate for bs buffer - 24 - 1 - read-write - - - MV_MERGE_CLK_EN - Configures whether or not to open the clock gate for mv merge.\\0: Open the clock gate only when mv merge work\\1: Force open the clock gate for mv merge - 25 - 1 - read-write - - - - - MV_MERGE_CONFIG - Mv merge configuration register. - 0xD4 - 0x20 - - - MV_MERGE_TYPE - Configure mv merge type.\\0: merge p16x16 mv\\1: merge min mv\\2: merge max mv\\3: not valid. - 0 - 2 - read-write - - - INT_MV_OUT_EN - Configure mv merge output integer part not zero mv or all part not zero mv.\\0: output all part not zero mv\\1: output integer part not zero mv. - 2 - 1 - read-write - - - A_MV_MERGE_EN - Configure whether or not to enable video A mv merge.\\0: disable\\1: enable. - 3 - 1 - read-write - - - B_MV_MERGE_EN - Configure whether or not to enable video B mv merge.\\0: disable\\1: enable. - 4 - 1 - read-write - - - MB_VALID_NUM - Represents the valid mb number of mv merge output. - 5 - 13 - read-only - - - - - DEBUG_DMA_SEL - Debug H264 DMA select register - 0xD8 - 0x20 - - - DBG_DMA_SEL - Every bit represents a dma in h264 - 0 - 8 - read-write - - - - - SYS_STATUS - System status register. - 0xDC - 0x20 - - - FRAME_NUM - Represents current frame number. - 0 - 9 - read-only - - - DUAL_STREAM_SEL - Represents which register group is used for cur frame.\\0: Register group A is used\\1: Register group B is used. - 9 - 1 - read-only - - - INTRA_FLAG - Represents the type of current encoding frame.\\0: P frame\\1: I frame. - 10 - 1 - read-only - - - - - FRAME_CODE_LENGTH - Frame code byte length register. - 0xE0 - 0x20 - - - FRAME_CODE_LENGTH - Represents current frame code byte length. - 0 - 24 - read-only - - - - - DEBUG_INFO0 - Debug information register0. - 0xE4 - 0x20 - - - TOP_CTRL_INTER_DEBUG_STATE - Represents top_ctrl_inter module FSM info. - 0 - 4 - read-only - - - TOP_CTRL_INTRA_DEBUG_STATE - Represents top_ctrl_intra module FSM info. - 4 - 3 - read-only - - - P_I_CMP_DEBUG_STATE - Represents p_i_cmp module FSM info. - 7 - 3 - read-only - - - MVD_DEBUG_STATE - Represents mvd module FSM info. - 10 - 3 - read-only - - - MC_CHROMA_IP_DEBUG_STATE - Represents mc_chroma_ip module FSM info. - 13 - 1 - read-only - - - INTRA_16X16_CHROMA_CTRL_DEBUG_STATE - Represents intra_16x16_chroma_ctrl module FSM info. - 14 - 4 - read-only - - - INTRA_4X4_CTRL_DEBUG_STATE - Represents intra_4x4_ctrl module FSM info. - 18 - 4 - read-only - - - INTRA_TOP_CTRL_DEBUG_STATE - Represents intra_top_ctrl module FSM info. - 22 - 3 - read-only - - - IME_CTRL_DEBUG_STATE - Represents ime_ctrl module FSM info. - 25 - 3 - read-only - - - - - DEBUG_INFO1 - Debug information register1. - 0xE8 - 0x20 - - - FME_CTRL_DEBUG_STATE - Represents fme_ctrl module FSM info. - 0 - 3 - read-only - - - DECI_CALC_DEBUG_STATE - Represents deci_calc module's FSM info. DEV use only. - 3 - 2 - read-only - - - DB_DEBUG_STATE - Represents db module FSM info. - 5 - 3 - read-only - - - CAVLC_ENC_DEBUG_STATE - Represents cavlc module enc FSM info. - 8 - 4 - read-only - - - CAVLC_SCAN_DEBUG_STATE - Represents cavlc module scan FSM info. - 12 - 4 - read-only - - - CAVLC_CTRL_DEBUG_STATE - Represents cavlc module ctrl FSM info. - 16 - 2 - read-only - - - BS_BUFFER_DEBUG_STATE - Represents bs buffer overflow info. - 18 - 1 - read-only - - - - - DEBUG_INFO2 - Debug information register2. - 0xEC - 0x20 - - - P_RC_DONE_DEBUG_FLAG - Represents p rate ctrl done status.\\0: not done\\1: done. - 0 - 1 - read-only - - - P_P_I_CMP_DONE_DEBUG_FLAG - Represents p p_i_cmp done status.\\0: not done\\1: done. - 1 - 1 - read-only - - - P_MV_MERGE_DONE_DEBUG_FLAG - Represents p mv merge done status.\\0: not done\\1: done. - 2 - 1 - read-only - - - P_MOVE_ORI_DONE_DEBUG_FLAG - Represents p move origin done status.\\0: not done\\1: done. - 3 - 1 - read-only - - - P_MC_DONE_DEBUG_FLAG - Represents p mc done status.\\0: not done\\1: done. - 4 - 1 - read-only - - - P_IME_DONE_DEBUG_FLAG - Represents p ime done status.\\0: not done\\1: done. - 5 - 1 - read-only - - - P_GET_ORI_DONE_DEBUG_FLAG - Represents p get origin done status.\\0: not done\\1: done. - 6 - 1 - read-only - - - P_FME_DONE_DEBUG_FLAG - Represents p fme done status.\\0: not done\\1: done. - 7 - 1 - read-only - - - P_FETCH_DONE_DEBUG_FLAG - Represents p fetch done status.\\0: not done\\1: done. - 8 - 1 - read-only - - - P_DB_DONE_DEBUG_FLAG - Represents p deblocking done status.\\0: not done\\1: done. - 9 - 1 - read-only - - - P_BS_BUF_DONE_DEBUG_FLAG - Represents p bitstream buffer done status.\\0: not done\\1: done. - 10 - 1 - read-only - - - REF_MOVE_2MB_LINE_DONE_DEBUG_FLAG - Represents dma move 2 ref mb line done status.\\0: not done\\1: done. - 11 - 1 - read-only - - - I_P_I_CMP_DONE_DEBUG_FLAG - Represents I p_i_cmp done status.\\0: not done\\1: done. - 12 - 1 - read-only - - - I_MOVE_ORI_DONE_DEBUG_FLAG - Represents I move origin done status.\\0: not done\\1: done. - 13 - 1 - read-only - - - I_GET_ORI_DONE_DEBUG_FLAG - Represents I get origin done status.\\0: not done\\1: done. - 14 - 1 - read-only - - - I_EC_DONE_DEBUG_FLAG - Represents I encoder done status.\\0: not done\\1: done. - 15 - 1 - read-only - - - I_DB_DONE_DEBUG_FLAG - Represents I deblocking done status.\\0: not done\\1: done. - 16 - 1 - read-only - - - I_BS_BUF_DONE_DEBUG_FLAG - Represents I bitstream buffer done status.\\0: not done\\1: done. - 17 - 1 - read-only - - - - - DATE - Version control register - 0xF0 - 0x20 - 0x02304240 - - - LEDC_DATE - Configures the version. - 0 - 28 - read-write - - - - - - - H264_DMA - H264 Encoder (DMA) - H264_DMA - 0x500A7000 - - 0x0 - 0x3DC - registers - - - H264_DMA2D_OUT_CH0 - 115 - - - H264_DMA2D_OUT_CH1 - 116 - - - H264_DMA2D_OUT_CH2 - 117 - - - H264_DMA2D_OUT_CH3 - 118 - - - H264_DMA2D_OUT_CH4 - 119 - - - H264_DMA2D_IN_CH0 - 120 - - - H264_DMA2D_IN_CH1 - 121 - - - H264_DMA2D_IN_CH2 - 122 - - - H264_DMA2D_IN_CH3 - 123 - - - H264_DMA2D_IN_CH4 - 124 - - - H264_DMA2D_IN_CH5 - 125 - - - - OUT_CONF0_CH0 - TX CH0 config0 register - 0x0 - 0x20 - 0x00000002 - - - OUT_AUTO_WRBACK_CH0 - Set this bit to enable automatic outlink-writeback when all the data pointed by outlink descriptor has been received. - 0 - 1 - read-write - - - OUT_EOF_MODE_CH0 - EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is generated when data need to read has been popped from FIFO in DMA - 1 - 1 - read-write - - - OUTDSCR_BURST_EN_CH0 - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. - 2 - 1 - read-write - - - OUT_ECC_AES_EN_CH0 - When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned. - 3 - 1 - read-write - - - OUT_CHECK_OWNER_CH0 - Set this bit to enable checking the owner attribute of the link descriptor. - 4 - 1 - read-write - - - OUT_MEM_BURST_LENGTH_CH0 - Block size of Tx channel 0. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes - 6 - 3 - read-write - - - OUT_PAGE_BOUND_EN_CH0 - Set this bit to 1 to make sure AXI read data don't cross the address boundary which define by mem_burst_length - 12 - 1 - read-write - - - OUT_REORDER_EN_CH0 - Enable TX channel 0 macro block reorder when set to 1, only channel0 have this selection - 16 - 1 - read-write - - - OUT_RST_CH0 - Write 1 then write 0 to this bit to reset TX channel - 24 - 1 - read-write - - - OUT_CMD_DISABLE_CH0 - Write 1 before reset and write 0 after reset - 25 - 1 - read-write - - - OUT_ARB_WEIGHT_OPT_DIS_CH0 - Set this bit to 1 to disable arbiter optimum weight function. - 26 - 1 - read-write - - - - - OUT_INT_RAW_CH0 - TX CH0 interrupt raw register - 0x4 - 0x20 - - - OUT_DONE_CH0_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0. - 0 - 1 - read-write - - - OUT_EOF_CH0_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. - 1 - 1 - read-write - - - OUT_DSCR_ERR_CH0_INT_RAW - The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0. - 2 - 1 - read-write - - - OUT_TOTAL_EOF_CH0_INT_RAW - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0. - 3 - 1 - read-write - - - OUTFIFO_OVF_L1_CH0_INT_RAW - The raw interrupt bit turns to high level when fifo is overflow. - 4 - 1 - read-write - - - OUTFIFO_UDF_L1_CH0_INT_RAW - The raw interrupt bit turns to high level when fifo is underflow. - 5 - 1 - read-write - - - OUTFIFO_OVF_L2_CH0_INT_RAW - The raw interrupt bit turns to high level when fifo is overflow. - 6 - 1 - read-write - - - OUTFIFO_UDF_L2_CH0_INT_RAW - The raw interrupt bit turns to high level when fifo is underflow. - 7 - 1 - read-write - - - OUT_DSCR_TASK_OVF_CH0_INT_RAW - The raw interrupt bit turns to high level when dscr ready task fifo is overflow. - 8 - 1 - read-write - - - - - OUT_INT_ENA_CH0 - TX CH0 interrupt ena register - 0x8 - 0x20 - - - OUT_DONE_CH0_INT_ENA - The interrupt enable bit for the OUT_DONE_CH_INT interrupt. - 0 - 1 - read-write - - - OUT_EOF_CH0_INT_ENA - The interrupt enable bit for the OUT_EOF_CH_INT interrupt. - 1 - 1 - read-write - - - OUT_DSCR_ERR_CH0_INT_ENA - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. - 2 - 1 - read-write - - - OUT_TOTAL_EOF_CH0_INT_ENA - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. - 3 - 1 - read-write - - - OUTFIFO_OVF_L1_CH0_INT_ENA - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - 4 - 1 - read-write - - - OUTFIFO_UDF_L1_CH0_INT_ENA - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - 5 - 1 - read-write - - - OUTFIFO_OVF_L2_CH0_INT_ENA - The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. - 6 - 1 - read-write - - - OUTFIFO_UDF_L2_CH0_INT_ENA - The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. - 7 - 1 - read-write - - - OUT_DSCR_TASK_OVF_CH0_INT_ENA - The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. - 8 - 1 - read-write - - - - - OUT_INT_ST_CH0 - TX CH0 interrupt st register - 0xC - 0x20 - - - OUT_DONE_CH0_INT_ST - The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. - 0 - 1 - read-only - - - OUT_EOF_CH0_INT_ST - The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. - 1 - 1 - read-only - - - OUT_DSCR_ERR_CH0_INT_ST - The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. - 2 - 1 - read-only - - - OUT_TOTAL_EOF_CH0_INT_ST - The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. - 3 - 1 - read-only - - - OUTFIFO_OVF_L1_CH0_INT_ST - The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - 4 - 1 - read-only - - - OUTFIFO_UDF_L1_CH0_INT_ST - The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - 5 - 1 - read-only - - - OUTFIFO_OVF_L2_CH0_INT_ST - The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. - 6 - 1 - read-only - - - OUTFIFO_UDF_L2_CH0_INT_ST - The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. - 7 - 1 - read-only - - - OUT_DSCR_TASK_OVF_CH0_INT_ST - The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. - 8 - 1 - read-only - - - - - OUT_INT_CLR_CH0 - TX CH0 interrupt clr register - 0x10 - 0x20 - - - OUT_DONE_CH0_INT_CLR - Set this bit to clear the OUT_DONE_CH_INT interrupt. - 0 - 1 - write-only - - - OUT_EOF_CH0_INT_CLR - Set this bit to clear the OUT_EOF_CH_INT interrupt. - 1 - 1 - write-only - - - OUT_DSCR_ERR_CH0_INT_CLR - Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. - 2 - 1 - write-only - - - OUT_TOTAL_EOF_CH0_INT_CLR - Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. - 3 - 1 - write-only - - - OUTFIFO_OVF_L1_CH0_INT_CLR - Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. - 4 - 1 - write-only - - - OUTFIFO_UDF_L1_CH0_INT_CLR - Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. - 5 - 1 - write-only - - - OUTFIFO_OVF_L2_CH0_INT_CLR - Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. - 6 - 1 - write-only - - - OUTFIFO_UDF_L2_CH0_INT_CLR - Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. - 7 - 1 - write-only - - - OUT_DSCR_TASK_OVF_CH0_INT_CLR - Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. - 8 - 1 - write-only - - - - - OUTFIFO_STATUS_CH0 - TX CH0 outfifo status register - 0x14 - 0x20 - 0x00020082 - - - OUTFIFO_FULL_L2_CH0 - Tx FIFO full signal for Tx channel 0. - 0 - 1 - read-only - - - OUTFIFO_EMPTY_L2_CH0 - Tx FIFO empty signal for Tx channel 0. - 1 - 1 - read-only - - - OUTFIFO_CNT_L2_CH0 - The register stores the byte number of the data in Tx FIFO for Tx channel 0. - 2 - 4 - read-only - - - OUTFIFO_FULL_L1_CH0 - Tx FIFO full signal for Tx channel 0. - 6 - 1 - read-only - - - OUTFIFO_EMPTY_L1_CH0 - Tx FIFO empty signal for Tx channel 0. - 7 - 1 - read-only - - - OUTFIFO_CNT_L1_CH0 - The register stores the byte number of the data in Tx FIFO for Tx channel 0. - 8 - 5 - read-only - - - OUTFIFO_FULL_L3_CH0 - Tx FIFO full signal for Tx channel 0. - 16 - 1 - read-only - - - OUTFIFO_EMPTY_L3_CH0 - Tx FIFO empty signal for Tx channel 0. - 17 - 1 - read-only - - - OUTFIFO_CNT_L3_CH0 - The register stores the 8byte number of the data in Tx FIFO for Tx channel 0. - 18 - 2 - read-only - - - - - OUT_PUSH_CH0 - TX CH0 outfifo push register - 0x18 - 0x20 - - - OUTFIFO_WDATA_CH0 - This register stores the data that need to be pushed into DMA Tx FIFO. - 0 - 10 - read-write - - - OUTFIFO_PUSH_CH0 - Set this bit to push data into DMA Tx FIFO. - 10 - 1 - read-write - - - - - OUT_LINK_CONF_CH0 - TX CH0 out_link dscr ctrl register - 0x1C - 0x20 - 0x00800000 - - - OUTLINK_STOP_CH0 - Set this bit to stop dealing with the outlink descriptors. - 20 - 1 - read-write - - - OUTLINK_START_CH0 - Set this bit to start dealing with the outlink descriptors. - 21 - 1 - read-write - - - OUTLINK_RESTART_CH0 - Set this bit to restart a new outlink from the last address. - 22 - 1 - read-write - - - OUTLINK_PARK_CH0 - 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. - 23 - 1 - read-only - - - - - OUT_LINK_ADDR_CH0 - TX CH0 out_link dscr addr register - 0x20 - 0x20 - - - OUTLINK_ADDR_CH0 - This register stores the first outlink descriptor's address. - 0 - 32 - read-write - - - - - OUT_STATE_CH0 - TX CH0 state register - 0x24 - 0x20 - 0x01000000 - - - OUTLINK_DSCR_ADDR_CH0 - This register stores the current outlink descriptor's address. - 0 - 18 - read-only - - - OUT_DSCR_STATE_CH0 - This register stores the current descriptor state machine state. - 18 - 2 - read-only - - - OUT_STATE_CH0 - This register stores the current control module state machine state. - 20 - 4 - read-only - - - OUT_RESET_AVAIL_CH0 - This register indicate that if the channel reset is safety. - 24 - 1 - read-only - - - - - OUT_EOF_DES_ADDR_CH0 - TX CH0 eof des addr register - 0x28 - 0x20 - - - OUT_EOF_DES_ADDR_CH0 - This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1. - 0 - 32 - read-only - - - - - OUT_DSCR_CH0 - TX CH0 next dscr addr register - 0x2C - 0x20 - - - OUTLINK_DSCR_CH0 - The address of the next outlink descriptor address y. - 0 - 32 - read-only - - - - - OUT_DSCR_BF0_CH0 - TX CH0 last dscr addr register - 0x30 - 0x20 - - - OUTLINK_DSCR_BF0_CH0 - The address of the last outlink descriptor's next address y-1. - 0 - 32 - read-only - - - - - OUT_DSCR_BF1_CH0 - TX CH0 second-to-last dscr addr register - 0x34 - 0x20 - - - OUTLINK_DSCR_BF1_CH0 - The address of the second-to-last outlink descriptor's next address y-2. - 0 - 32 - read-only - - - - - OUT_ARB_CH0 - TX CH0 arb register - 0x3C - 0x20 - 0x00000011 - - - OUT_ARB_TOKEN_NUM_CH0 - Set the max number of token count of arbiter - 0 - 4 - read-write - - - EXTER_OUT_ARB_PRIORITY_CH0 - Set the priority of channel - 4 - 2 - read-write - - - - - OUT_RO_STATUS_CH0 - TX CH0 reorder status register - 0x40 - 0x20 - 0x00000800 - - - OUTFIFO_RO_CNT_CH0 - The register stores the 8byte number of the data in reorder Tx FIFO for channel 0. - 0 - 2 - read-only - - - OUT_RO_WR_STATE_CH0 - The register stores the state of read ram of reorder - 6 - 2 - read-only - - - OUT_RO_RD_STATE_CH0 - The register stores the state of write ram of reorder - 8 - 2 - read-only - - - OUT_PIXEL_BYTE_CH0 - the number of bytes contained in a pixel at TX channel 0: 1byte 1: 1.5bytes 2 : 2bytes 3: 2.5bytes 4: 3bytes 5: 4bytes - 10 - 4 - read-only - - - OUT_BURST_BLOCK_NUM_CH0 - the number of macro blocks contained in a burst of data at TX channel - 14 - 4 - read-only - - - - - OUT_RO_PD_CONF_CH0 - TX CH0 reorder power config register - 0x44 - 0x20 - 0x00000020 - - - OUT_RO_RAM_FORCE_PD_CH0 - dma reorder ram power down - 4 - 1 - read-write - - - OUT_RO_RAM_FORCE_PU_CH0 - dma reorder ram power up - 5 - 1 - read-write - - - OUT_RO_RAM_CLK_FO_CH0 - 1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. 0: A gate-clock will be used when accessing the RAM in DMA. - 6 - 1 - read-write - - - - - OUT_MODE_ENABLE_CH0 - tx CH0 mode enable register - 0x50 - 0x20 - - - OUT_TEST_MODE_ENABLE_CH0 - tx CH0 test mode enable.0 : H264_DMA work in normal mode.1 : H264_DMA work in test mode - 0 - 1 - read-write - - - - - OUT_MODE_YUV_CH0 - tx CH0 test mode yuv value register - 0x54 - 0x20 - - - OUT_TEST_Y_VALUE_CH0 - tx CH0 test mode y value - 0 - 8 - read-write - - - OUT_TEST_U_VALUE_CH0 - tx CH0 test mode u value - 8 - 8 - read-write - - - OUT_TEST_V_VALUE_CH0 - tx CH0 test mode v value - 16 - 8 - read-write - - - - - OUT_ETM_CONF_CH0 - TX CH0 ETM config register - 0x68 - 0x20 - 0x00000004 - - - OUT_ETM_EN_CH0 - Set this bit to 1 to enable ETM task function - 0 - 1 - read-write - - - OUT_ETM_LOOP_EN_CH0 - when this bit is 1, dscr can be processed after receiving a task - 1 - 1 - read-write - - - OUT_DSCR_TASK_MAK_CH0 - ETM dscr_ready maximum cache numbers - 2 - 2 - read-write - - - - - OUT_BUF_LEN_CH0 - tx CH0 buf len register - 0x70 - 0x20 - - - OUT_CMDFIFO_BUF_LEN_HB_CH0 - only for debug - 0 - 13 - read-only - - - - - OUT_FIFO_BCNT_CH0 - tx CH0 fifo byte cnt register - 0x74 - 0x20 - - - OUT_CMDFIFO_OUTFIFO_BCNT_CH0 - only for debug - 0 - 10 - read-only - - - - - OUT_PUSH_BYTECNT_CH0 - tx CH0 push byte cnt register - 0x78 - 0x20 - 0x000000FF - - - OUT_CMDFIFO_PUSH_BYTECNT_CH0 - only for debug - 0 - 8 - read-only - - - - - OUT_XADDR_CH0 - tx CH0 xaddr register - 0x7C - 0x20 - - - OUT_CMDFIFO_XADDR_CH0 - only for debug - 0 - 32 - read-only - - - - - OUT_CONF0_CH1 - TX CH1 config0 register - 0x100 - 0x20 - 0x00000002 - - - OUT_AUTO_WRBACK_CH1 - Set this bit to enable automatic outlink-writeback when all the data pointed by outlink descriptor has been received. - 0 - 1 - read-write - - - OUT_EOF_MODE_CH1 - EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is generated when data need to read has been popped from FIFO in DMA - 1 - 1 - read-write - - - OUTDSCR_BURST_EN_CH1 - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. - 2 - 1 - read-write - - - OUT_ECC_AES_EN_CH1 - When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned. - 3 - 1 - read-write - - - OUT_CHECK_OWNER_CH1 - Set this bit to enable checking the owner attribute of the link descriptor. - 4 - 1 - read-write - - - OUT_MEM_BURST_LENGTH_CH1 - Block size of Tx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 64 bytes - 6 - 3 - read-write - - - OUT_PAGE_BOUND_EN_CH1 - Set this bit to 1 to make sure AXI read data don't cross the address boundary which define by mem_burst_length - 12 - 1 - read-write - - - OUT_RST_CH1 - Write 1 then write 0 to this bit to reset TX channel - 24 - 1 - read-write - - - OUT_CMD_DISABLE_CH1 - Write 1 before reset and write 0 after reset - 25 - 1 - read-write - - - OUT_ARB_WEIGHT_OPT_DIS_CH1 - Set this bit to 1 to disable arbiter optimum weight function. - 26 - 1 - read-write - - - - - OUT_INT_RAW_CH1 - TX CH1 interrupt raw register - 0x104 - 0x20 - - - OUT_DONE_CH1_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0. - 0 - 1 - read-write - - - OUT_EOF_CH1_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. - 1 - 1 - read-write - - - OUT_DSCR_ERR_CH1_INT_RAW - The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0. - 2 - 1 - read-write - - - OUT_TOTAL_EOF_CH1_INT_RAW - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0. - 3 - 1 - read-write - - - OUTFIFO_OVF_L1_CH1_INT_RAW - The raw interrupt bit turns to high level when fifo is overflow. - 4 - 1 - read-write - - - OUTFIFO_UDF_L1_CH1_INT_RAW - The raw interrupt bit turns to high level when fifo is underflow. - 5 - 1 - read-write - - - OUTFIFO_OVF_L2_CH1_INT_RAW - The raw interrupt bit turns to high level when fifo is overflow. - 6 - 1 - read-write - - - OUTFIFO_UDF_L2_CH1_INT_RAW - The raw interrupt bit turns to high level when fifo is underflow. - 7 - 1 - read-write - - - OUT_DSCR_TASK_OVF_CH1_INT_RAW - The raw interrupt bit turns to high level when dscr ready task fifo is overflow. - 8 - 1 - read-write - - - - - OUT_INT_ENA_CH1 - TX CH1 interrupt ena register - 0x108 - 0x20 - - - OUT_DONE_CH1_INT_ENA - The interrupt enable bit for the OUT_DONE_CH_INT interrupt. - 0 - 1 - read-write - - - OUT_EOF_CH1_INT_ENA - The interrupt enable bit for the OUT_EOF_CH_INT interrupt. - 1 - 1 - read-write - - - OUT_DSCR_ERR_CH1_INT_ENA - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. - 2 - 1 - read-write - - - OUT_TOTAL_EOF_CH1_INT_ENA - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. - 3 - 1 - read-write - - - OUTFIFO_OVF_L1_CH1_INT_ENA - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - 4 - 1 - read-write - - - OUTFIFO_UDF_L1_CH1_INT_ENA - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - 5 - 1 - read-write - - - OUTFIFO_OVF_L2_CH1_INT_ENA - The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. - 6 - 1 - read-write - - - OUTFIFO_UDF_L2_CH1_INT_ENA - The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. - 7 - 1 - read-write - - - OUT_DSCR_TASK_OVF_CH1_INT_ENA - The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. - 8 - 1 - read-write - - - - - OUT_INT_ST_CH1 - TX CH1 interrupt st register - 0x10C - 0x20 - - - OUT_DONE_CH1_INT_ST - The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. - 0 - 1 - read-only - - - OUT_EOF_CH1_INT_ST - The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. - 1 - 1 - read-only - - - OUT_DSCR_ERR_CH1_INT_ST - The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. - 2 - 1 - read-only - - - OUT_TOTAL_EOF_CH1_INT_ST - The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. - 3 - 1 - read-only - - - OUTFIFO_OVF_L1_CH1_INT_ST - The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - 4 - 1 - read-only - - - OUTFIFO_UDF_L1_CH1_INT_ST - The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - 5 - 1 - read-only - - - OUTFIFO_OVF_L2_CH1_INT_ST - The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. - 6 - 1 - read-only - - - OUTFIFO_UDF_L2_CH1_INT_ST - The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. - 7 - 1 - read-only - - - OUT_DSCR_TASK_OVF_CH1_INT_ST - The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. - 8 - 1 - read-only - - - - - OUT_INT_CLR_CH1 - TX CH1 interrupt clr register - 0x110 - 0x20 - - - OUT_DONE_CH1_INT_CLR - Set this bit to clear the OUT_DONE_CH_INT interrupt. - 0 - 1 - write-only - - - OUT_EOF_CH1_INT_CLR - Set this bit to clear the OUT_EOF_CH_INT interrupt. - 1 - 1 - write-only - - - OUT_DSCR_ERR_CH1_INT_CLR - Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. - 2 - 1 - write-only - - - OUT_TOTAL_EOF_CH1_INT_CLR - Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. - 3 - 1 - write-only - - - OUTFIFO_OVF_L1_CH1_INT_CLR - Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. - 4 - 1 - write-only - - - OUTFIFO_UDF_L1_CH1_INT_CLR - Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. - 5 - 1 - write-only - - - OUTFIFO_OVF_L2_CH1_INT_CLR - Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. - 6 - 1 - write-only - - - OUTFIFO_UDF_L2_CH1_INT_CLR - Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. - 7 - 1 - write-only - - - OUT_DSCR_TASK_OVF_CH1_INT_CLR - Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. - 8 - 1 - write-only - - - - - OUTFIFO_STATUS_CH1 - TX CH1 outfifo status register - 0x114 - 0x20 - 0x00020082 - - - OUTFIFO_FULL_L2_CH1 - Tx FIFO full signal for Tx channel 1. - 0 - 1 - read-only - - - OUTFIFO_EMPTY_L2_CH1 - Tx FIFO empty signal for Tx channel 1. - 1 - 1 - read-only - - - OUTFIFO_CNT_L2_CH1 - The register stores the byte number of the data in Tx FIFO for Tx channel 1. - 2 - 4 - read-only - - - OUTFIFO_FULL_L1_CH1 - Tx FIFO full signal for Tx channel 1. - 6 - 1 - read-only - - - OUTFIFO_EMPTY_L1_CH1 - Tx FIFO empty signal for Tx channel 1. - 7 - 1 - read-only - - - OUTFIFO_CNT_L1_CH1 - The register stores the byte number of the data in Tx FIFO for Tx channel 1. - 8 - 5 - read-only - - - OUTFIFO_FULL_L3_CH1 - Tx FIFO full signal for Tx channel 1. - 16 - 1 - read-only - - - OUTFIFO_EMPTY_L3_CH1 - Tx FIFO empty signal for Tx channel 1. - 17 - 1 - read-only - - - OUTFIFO_CNT_L3_CH1 - The register stores the byte number of the data in Tx FIFO for Tx channel 1. - 18 - 2 - read-only - - - - - OUT_PUSH_CH1 - TX CH1 outfifo push register - 0x118 - 0x20 - - - OUTFIFO_WDATA_CH1 - This register stores the data that need to be pushed into DMA Tx FIFO. - 0 - 10 - read-write - - - OUTFIFO_PUSH_CH1 - Set this bit to push data into DMA Tx FIFO. - 10 - 1 - read-write - - - - - OUT_LINK_CONF_CH1 - TX CH1 out_link dscr ctrl register - 0x11C - 0x20 - 0x00800000 - - - OUTLINK_STOP_CH1 - Set this bit to stop dealing with the outlink descriptors. - 20 - 1 - read-write - - - OUTLINK_START_CH1 - Set this bit to start dealing with the outlink descriptors. - 21 - 1 - read-write - - - OUTLINK_RESTART_CH1 - Set this bit to restart a new outlink from the last address. - 22 - 1 - read-write - - - OUTLINK_PARK_CH1 - 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. - 23 - 1 - read-only - - - - - OUT_LINK_ADDR_CH1 - TX CH1 out_link dscr addr register - 0x120 - 0x20 - - - OUTLINK_ADDR_CH1 - This register stores the first outlink descriptor's address. - 0 - 32 - read-write - - - - - OUT_STATE_CH1 - TX CH1 state register - 0x124 - 0x20 - 0x01000000 - - - OUTLINK_DSCR_ADDR_CH1 - This register stores the current outlink descriptor's address. - 0 - 18 - read-only - - - OUT_DSCR_STATE_CH1 - This register stores the current descriptor state machine state. - 18 - 2 - read-only - - - OUT_STATE_CH1 - This register stores the current control module state machine state. - 20 - 4 - read-only - - - OUT_RESET_AVAIL_CH1 - This register indicate that if the channel reset is safety. - 24 - 1 - read-only - - - - - OUT_EOF_DES_ADDR_CH1 - TX CH1 eof des addr register - 0x128 - 0x20 - - - OUT_EOF_DES_ADDR_CH1 - This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1. - 0 - 32 - read-only - - - - - OUT_DSCR_CH1 - TX CH1 next dscr addr register - 0x12C - 0x20 - - - OUTLINK_DSCR_CH1 - The address of the next outlink descriptor address y. - 0 - 32 - read-only - - - - - OUT_DSCR_BF0_CH1 - TX CH1 last dscr addr register - 0x130 - 0x20 - - - OUTLINK_DSCR_BF0_CH1 - The address of the last outlink descriptor's next address y-1. - 0 - 32 - read-only - - - - - OUT_DSCR_BF1_CH1 - TX CH1 second-to-last dscr addr register - 0x134 - 0x20 - - - OUTLINK_DSCR_BF1_CH1 - The address of the second-to-last outlink descriptor's next address y-2. - 0 - 32 - read-only - - - - - OUT_ARB_CH1 - TX CH1 arb register - 0x13C - 0x20 - 0x00000041 - - - OUT_ARB_TOKEN_NUM_CH1 - Set the max number of token count of arbiter - 0 - 4 - read-write - - - INTER_OUT_ARB_PRIORITY_CH1 - Set the priority of channel - 6 - 1 - read-write - - - - - OUT_ETM_CONF_CH1 - TX CH1 ETM config register - 0x168 - 0x20 - 0x00000004 - - - OUT_ETM_EN_CH1 - Set this bit to 1 to enable ETM task function - 0 - 1 - read-write - - - OUT_ETM_LOOP_EN_CH1 - when this bit is 1, dscr can be processed after receiving a task - 1 - 1 - read-write - - - OUT_DSCR_TASK_MAK_CH1 - ETM dscr_ready maximum cache numbers - 2 - 2 - read-write - - - - - OUT_BUF_LEN_CH1 - tx CH1 buf len register - 0x170 - 0x20 - - - OUT_CMDFIFO_BUF_LEN_HB_CH1 - only for debug - 0 - 13 - read-only - - - - - OUT_FIFO_BCNT_CH1 - tx CH1 fifo byte cnt register - 0x174 - 0x20 - - - OUT_CMDFIFO_OUTFIFO_BCNT_CH1 - only for debug - 0 - 10 - read-only - - - - - OUT_PUSH_BYTECNT_CH1 - tx CH1 push byte cnt register - 0x178 - 0x20 - 0x000000FF - - - OUT_CMDFIFO_PUSH_BYTECNT_CH1 - only for debug - 0 - 8 - read-only - - - - - OUT_XADDR_CH1 - tx CH1 xaddr register - 0x17C - 0x20 - - - OUT_CMDFIFO_XADDR_CH1 - only for debug - 0 - 32 - read-only - - - - - OUT_CONF0_CH2 - TX CH2 config0 register - 0x200 - 0x20 - 0x00000002 - - - OUT_AUTO_WRBACK_CH2 - Set this bit to enable automatic outlink-writeback when all the data pointed by outlink descriptor has been received. - 0 - 1 - read-write - - - OUT_EOF_MODE_CH2 - EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is generated when data need to read has been popped from FIFO in DMA - 1 - 1 - read-write - - - OUTDSCR_BURST_EN_CH2 - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. - 2 - 1 - read-write - - - OUT_ECC_AES_EN_CH2 - When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned. - 3 - 1 - read-write - - - OUT_CHECK_OWNER_CH2 - Set this bit to enable checking the owner attribute of the link descriptor. - 4 - 1 - read-write - - - OUT_MEM_BURST_LENGTH_CH2 - Block size of Tx channel 2. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes - 6 - 3 - read-write - - - OUT_PAGE_BOUND_EN_CH2 - Set this bit to 1 to make sure AXI read data don't cross the address boundary which define by mem_burst_length - 12 - 1 - read-write - - - OUT_RST_CH2 - Write 1 then write 0 to this bit to reset TX channel - 24 - 1 - read-write - - - OUT_CMD_DISABLE_CH2 - Write 1 before reset and write 0 after reset - 25 - 1 - read-write - - - OUT_ARB_WEIGHT_OPT_DIS_CH2 - Set this bit to 1 to disable arbiter optimum weight function. - 26 - 1 - read-write - - - - - OUT_INT_RAW_CH2 - TX CH2 interrupt raw register - 0x204 - 0x20 - - - OUT_DONE_CH2_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0. - 0 - 1 - read-write - - - OUT_EOF_CH2_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. - 1 - 1 - read-write - - - OUT_DSCR_ERR_CH2_INT_RAW - The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0. - 2 - 1 - read-write - - - OUT_TOTAL_EOF_CH2_INT_RAW - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0. - 3 - 1 - read-write - - - OUTFIFO_OVF_L1_CH2_INT_RAW - The raw interrupt bit turns to high level when fifo is overflow. - 4 - 1 - read-write - - - OUTFIFO_UDF_L1_CH2_INT_RAW - The raw interrupt bit turns to high level when fifo is underflow. - 5 - 1 - read-write - - - OUTFIFO_OVF_L2_CH2_INT_RAW - The raw interrupt bit turns to high level when fifo is overflow. - 6 - 1 - read-write - - - OUTFIFO_UDF_L2_CH2_INT_RAW - The raw interrupt bit turns to high level when fifo is underflow. - 7 - 1 - read-write - - - OUT_DSCR_TASK_OVF_CH2_INT_RAW - The raw interrupt bit turns to high level when dscr ready task fifo is overflow. - 8 - 1 - read-write - - - - - OUT_INT_ENA_CH2 - TX CH2 interrupt ena register - 0x208 - 0x20 - - - OUT_DONE_CH2_INT_ENA - The interrupt enable bit for the OUT_DONE_CH_INT interrupt. - 0 - 1 - read-write - - - OUT_EOF_CH2_INT_ENA - The interrupt enable bit for the OUT_EOF_CH_INT interrupt. - 1 - 1 - read-write - - - OUT_DSCR_ERR_CH2_INT_ENA - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. - 2 - 1 - read-write - - - OUT_TOTAL_EOF_CH2_INT_ENA - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. - 3 - 1 - read-write - - - OUTFIFO_OVF_L1_CH2_INT_ENA - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - 4 - 1 - read-write - - - OUTFIFO_UDF_L1_CH2_INT_ENA - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - 5 - 1 - read-write - - - OUTFIFO_OVF_L2_CH2_INT_ENA - The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. - 6 - 1 - read-write - - - OUTFIFO_UDF_L2_CH2_INT_ENA - The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. - 7 - 1 - read-write - - - OUT_DSCR_TASK_OVF_CH2_INT_ENA - The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. - 8 - 1 - read-write - - - - - OUT_INT_ST_CH2 - TX CH2 interrupt st register - 0x20C - 0x20 - - - OUT_DONE_CH2_INT_ST - The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. - 0 - 1 - read-only - - - OUT_EOF_CH2_INT_ST - The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. - 1 - 1 - read-only - - - OUT_DSCR_ERR_CH2_INT_ST - The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. - 2 - 1 - read-only - - - OUT_TOTAL_EOF_CH2_INT_ST - The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. - 3 - 1 - read-only - - - OUTFIFO_OVF_L1_CH2_INT_ST - The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - 4 - 1 - read-only - - - OUTFIFO_UDF_L1_CH2_INT_ST - The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - 5 - 1 - read-only - - - OUTFIFO_OVF_L2_CH2_INT_ST - The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. - 6 - 1 - read-only - - - OUTFIFO_UDF_L2_CH2_INT_ST - The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. - 7 - 1 - read-only - - - OUT_DSCR_TASK_OVF_CH2_INT_ST - The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. - 8 - 1 - read-only - - - - - OUT_INT_CLR_CH2 - TX CH2 interrupt clr register - 0x210 - 0x20 - - - OUT_DONE_CH2_INT_CLR - Set this bit to clear the OUT_DONE_CH_INT interrupt. - 0 - 1 - write-only - - - OUT_EOF_CH2_INT_CLR - Set this bit to clear the OUT_EOF_CH_INT interrupt. - 1 - 1 - write-only - - - OUT_DSCR_ERR_CH2_INT_CLR - Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. - 2 - 1 - write-only - - - OUT_TOTAL_EOF_CH2_INT_CLR - Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. - 3 - 1 - write-only - - - OUTFIFO_OVF_L1_CH2_INT_CLR - Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. - 4 - 1 - write-only - - - OUTFIFO_UDF_L1_CH2_INT_CLR - Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. - 5 - 1 - write-only - - - OUTFIFO_OVF_L2_CH2_INT_CLR - Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. - 6 - 1 - write-only - - - OUTFIFO_UDF_L2_CH2_INT_CLR - Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. - 7 - 1 - write-only - - - OUT_DSCR_TASK_OVF_CH2_INT_CLR - Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. - 8 - 1 - write-only - - - - - OUTFIFO_STATUS_CH2 - TX CH2 outfifo status register - 0x214 - 0x20 - 0x00020082 - - - OUTFIFO_FULL_L2_CH2 - Tx FIFO full signal for Tx channel 2. - 0 - 1 - read-only - - - OUTFIFO_EMPTY_L2_CH2 - Tx FIFO empty signal for Tx channel 2. - 1 - 1 - read-only - - - OUTFIFO_CNT_L2_CH2 - The register stores the byte number of the data in Tx FIFO for Tx channel 2. - 2 - 4 - read-only - - - OUTFIFO_FULL_L1_CH2 - Tx FIFO full signal for Tx channel 2. - 6 - 1 - read-only - - - OUTFIFO_EMPTY_L1_CH2 - Tx FIFO empty signal for Tx channel 2. - 7 - 1 - read-only - - - OUTFIFO_CNT_L1_CH2 - The register stores the byte number of the data in Tx FIFO for Tx channel 2. - 8 - 5 - read-only - - - OUTFIFO_FULL_L3_CH2 - Tx FIFO full signal for Tx channel 2. - 16 - 1 - read-only - - - OUTFIFO_EMPTY_L3_CH2 - Tx FIFO empty signal for Tx channel 2. - 17 - 1 - read-only - - - OUTFIFO_CNT_L3_CH2 - The register stores the byte number of the data in Tx FIFO for Tx channel 2. - 18 - 2 - read-only - - - - - OUT_PUSH_CH2 - TX CH2 outfifo push register - 0x218 - 0x20 - - - OUTFIFO_WDATA_CH2 - This register stores the data that need to be pushed into DMA Tx FIFO. - 0 - 10 - read-write - - - OUTFIFO_PUSH_CH2 - Set this bit to push data into DMA Tx FIFO. - 10 - 1 - read-write - - - - - OUT_LINK_CONF_CH2 - TX CH2 out_link dscr ctrl register - 0x21C - 0x20 - 0x00800000 - - - OUTLINK_STOP_CH2 - Set this bit to stop dealing with the outlink descriptors. - 20 - 1 - read-write - - - OUTLINK_START_CH2 - Set this bit to start dealing with the outlink descriptors. - 21 - 1 - read-write - - - OUTLINK_RESTART_CH2 - Set this bit to restart a new outlink from the last address. - 22 - 1 - read-write - - - OUTLINK_PARK_CH2 - 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. - 23 - 1 - read-only - - - - - OUT_LINK_ADDR_CH2 - TX CH2 out_link dscr addr register - 0x220 - 0x20 - - - OUTLINK_ADDR_CH2 - This register stores the first outlink descriptor's address. - 0 - 32 - read-write - - - - - OUT_STATE_CH2 - TX CH2 state register - 0x224 - 0x20 - 0x01000000 - - - OUTLINK_DSCR_ADDR_CH2 - This register stores the current outlink descriptor's address. - 0 - 18 - read-only - - - OUT_DSCR_STATE_CH2 - This register stores the current descriptor state machine state. - 18 - 2 - read-only - - - OUT_STATE_CH2 - This register stores the current control module state machine state. - 20 - 4 - read-only - - - OUT_RESET_AVAIL_CH2 - This register indicate that if the channel reset is safety. - 24 - 1 - read-only - - - - - OUT_EOF_DES_ADDR_CH2 - TX CH2 eof des addr register - 0x228 - 0x20 - - - OUT_EOF_DES_ADDR_CH2 - This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. - 0 - 32 - read-only - - - - - OUT_DSCR_CH2 - TX CH2 next dscr addr register - 0x22C - 0x20 - - - OUTLINK_DSCR_CH2 - The address of the next outlink descriptor address y. - 0 - 32 - read-only - - - - - OUT_DSCR_BF0_CH2 - TX CH2 last dscr addr register - 0x230 - 0x20 - - - OUTLINK_DSCR_BF0_CH2 - The address of the last outlink descriptor's next address y-1. - 0 - 32 - read-only - - - - - OUT_DSCR_BF1_CH2 - TX CH2 second-to-last dscr addr register - 0x234 - 0x20 - - - OUTLINK_DSCR_BF1_CH2 - The address of the second-to-last outlink descriptor's next address y-2. - 0 - 32 - read-only - - - - - OUT_ARB_CH2 - TX CH2 arb register - 0x23C - 0x20 - 0x00000041 - - - OUT_ARB_TOKEN_NUM_CH2 - Set the max number of token count of arbiter - 0 - 4 - read-write - - - INTER_OUT_ARB_PRIORITY_CH2 - Set the priority of channel - 6 - 1 - read-write - - - - - OUT_ETM_CONF_CH2 - TX CH2 ETM config register - 0x268 - 0x20 - 0x00000004 - - - OUT_ETM_EN_CH2 - Set this bit to 1 to enable ETM task function - 0 - 1 - read-write - - - OUT_ETM_LOOP_EN_CH2 - when this bit is 1, dscr can be processed after receiving a task - 1 - 1 - read-write - - - OUT_DSCR_TASK_MAK_CH2 - ETM dscr_ready maximum cache numbers - 2 - 2 - read-write - - - - - OUT_BUF_LEN_CH2 - tx CH2 buf len register - 0x270 - 0x20 - - - OUT_CMDFIFO_BUF_LEN_HB_CH2 - only for debug - 0 - 13 - read-only - - - - - OUT_FIFO_BCNT_CH2 - tx CH2 fifo byte cnt register - 0x274 - 0x20 - - - OUT_CMDFIFO_OUTFIFO_BCNT_CH2 - only for debug - 0 - 10 - read-only - - - - - OUT_PUSH_BYTECNT_CH2 - tx CH2 push byte cnt register - 0x278 - 0x20 - 0x000000FF - - - OUT_CMDFIFO_PUSH_BYTECNT_CH2 - only for debug - 0 - 8 - read-only - - - - - OUT_XADDR_CH2 - tx CH2 xaddr register - 0x27C - 0x20 - - - OUT_CMDFIFO_XADDR_CH2 - only for debug - 0 - 32 - read-only - - - - - OUT_CONF0_CH3 - TX CH3 config0 register - 0x300 - 0x20 - 0x00000002 - - - OUT_AUTO_WRBACK_CH3 - Set this bit to enable automatic outlink-writeback when all the data pointed by outlink descriptor has been received. - 0 - 1 - read-write - - - OUT_EOF_MODE_CH3 - EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is generated when data need to read has been popped from FIFO in DMA - 1 - 1 - read-write - - - OUTDSCR_BURST_EN_CH3 - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. - 2 - 1 - read-write - - - OUT_ECC_AES_EN_CH3 - When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned. - 3 - 1 - read-write - - - OUT_CHECK_OWNER_CH3 - Set this bit to enable checking the owner attribute of the link descriptor. - 4 - 1 - read-write - - - OUT_MEM_BURST_LENGTH_CH3 - Block size of Tx channel 3. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes - 6 - 3 - read-write - - - OUT_PAGE_BOUND_EN_CH3 - Set this bit to 1 to make sure AXI read data don't cross the address boundary which define by mem_burst_length - 12 - 1 - read-write - - - OUT_ARB_WEIGHT_OPT_DIS_CH3 - Set this bit to 1 to disable arbiter optimum weight function. - 26 - 1 - read-write - - - - - OUT_INT_RAW_CH3 - TX CH3 interrupt raw register - 0x304 - 0x20 - - - OUT_DONE_CH3_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0. - 0 - 1 - read-write - - - OUT_EOF_CH3_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. - 1 - 1 - read-write - - - OUT_DSCR_ERR_CH3_INT_RAW - The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0. - 2 - 1 - read-write - - - OUT_TOTAL_EOF_CH3_INT_RAW - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0. - 3 - 1 - read-write - - - OUTFIFO_OVF_L1_CH3_INT_RAW - The raw interrupt bit turns to high level when fifo is overflow. - 4 - 1 - read-write - - - OUTFIFO_UDF_L1_CH3_INT_RAW - The raw interrupt bit turns to high level when fifo is underflow. - 5 - 1 - read-write - - - OUTFIFO_OVF_L2_CH3_INT_RAW - The raw interrupt bit turns to high level when fifo is overflow. - 6 - 1 - read-write - - - OUTFIFO_UDF_L2_CH3_INT_RAW - The raw interrupt bit turns to high level when fifo is underflow. - 7 - 1 - read-write - - - OUT_DSCR_TASK_OVF_CH3_INT_RAW - The raw interrupt bit turns to high level when dscr ready task fifo is overflow. - 8 - 1 - read-write - - - - - OUT_INT_ENA_CH3 - TX CH3 interrupt ena register - 0x308 - 0x20 - - - OUT_DONE_CH3_INT_ENA - The interrupt enable bit for the OUT_DONE_CH_INT interrupt. - 0 - 1 - read-write - - - OUT_EOF_CH3_INT_ENA - The interrupt enable bit for the OUT_EOF_CH_INT interrupt. - 1 - 1 - read-write - - - OUT_DSCR_ERR_CH3_INT_ENA - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. - 2 - 1 - read-write - - - OUT_TOTAL_EOF_CH3_INT_ENA - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. - 3 - 1 - read-write - - - OUTFIFO_OVF_L1_CH3_INT_ENA - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - 4 - 1 - read-write - - - OUTFIFO_UDF_L1_CH3_INT_ENA - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - 5 - 1 - read-write - - - OUTFIFO_OVF_L2_CH3_INT_ENA - The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. - 6 - 1 - read-write - - - OUTFIFO_UDF_L2_CH3_INT_ENA - The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. - 7 - 1 - read-write - - - OUT_DSCR_TASK_OVF_CH3_INT_ENA - The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. - 8 - 1 - read-write - - - - - OUT_INT_ST_CH3 - TX CH3 interrupt st register - 0x30C - 0x20 - - - OUT_DONE_CH3_INT_ST - The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. - 0 - 1 - read-only - - - OUT_EOF_CH3_INT_ST - The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. - 1 - 1 - read-only - - - OUT_DSCR_ERR_CH3_INT_ST - The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. - 2 - 1 - read-only - - - OUT_TOTAL_EOF_CH3_INT_ST - The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. - 3 - 1 - read-only - - - OUTFIFO_OVF_L1_CH3_INT_ST - The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - 4 - 1 - read-only - - - OUTFIFO_UDF_L1_CH3_INT_ST - The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - 5 - 1 - read-only - - - OUTFIFO_OVF_L2_CH3_INT_ST - The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. - 6 - 1 - read-only - - - OUTFIFO_UDF_L2_CH3_INT_ST - The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. - 7 - 1 - read-only - - - OUT_DSCR_TASK_OVF_CH3_INT_ST - The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. - 8 - 1 - read-only - - - - - OUT_INT_CLR_CH3 - TX CH3 interrupt clr register - 0x310 - 0x20 - - - OUT_DONE_CH3_INT_CLR - Set this bit to clear the OUT_DONE_CH_INT interrupt. - 0 - 1 - write-only - - - OUT_EOF_CH3_INT_CLR - Set this bit to clear the OUT_EOF_CH_INT interrupt. - 1 - 1 - write-only - - - OUT_DSCR_ERR_CH3_INT_CLR - Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. - 2 - 1 - write-only - - - OUT_TOTAL_EOF_CH3_INT_CLR - Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. - 3 - 1 - write-only - - - OUTFIFO_OVF_L1_CH3_INT_CLR - Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. - 4 - 1 - write-only - - - OUTFIFO_UDF_L1_CH3_INT_CLR - Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. - 5 - 1 - write-only - - - OUTFIFO_OVF_L2_CH3_INT_CLR - Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. - 6 - 1 - write-only - - - OUTFIFO_UDF_L2_CH3_INT_CLR - Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. - 7 - 1 - write-only - - - OUT_DSCR_TASK_OVF_CH3_INT_CLR - Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. - 8 - 1 - write-only - - - - - OUTFIFO_STATUS_CH3 - TX CH3 outfifo status register - 0x314 - 0x20 - 0x00020082 - - - OUTFIFO_FULL_L2_CH3 - Tx FIFO full signal for Tx channel 2. - 0 - 1 - read-only - - - OUTFIFO_EMPTY_L2_CH3 - Tx FIFO empty signal for Tx channel 2. - 1 - 1 - read-only - - - OUTFIFO_CNT_L2_CH3 - The register stores the byte number of the data in Tx FIFO for Tx channel 2. - 2 - 4 - read-only - - - OUTFIFO_FULL_L1_CH3 - Tx FIFO full signal for Tx channel 2. - 6 - 1 - read-only - - - OUTFIFO_EMPTY_L1_CH3 - Tx FIFO empty signal for Tx channel 2. - 7 - 1 - read-only - - - OUTFIFO_CNT_L1_CH3 - The register stores the byte number of the data in Tx FIFO for Tx channel 2. - 8 - 5 - read-only - - - OUTFIFO_FULL_L3_CH3 - Tx FIFO full signal for Tx channel 2. - 16 - 1 - read-only - - - OUTFIFO_EMPTY_L3_CH3 - Tx FIFO empty signal for Tx channel 2. - 17 - 1 - read-only - - - OUTFIFO_CNT_L3_CH3 - The register stores the byte number of the data in Tx FIFO for Tx channel 2. - 18 - 2 - read-only - - - - - OUT_PUSH_CH3 - TX CH3 outfifo push register - 0x318 - 0x20 - - - OUTFIFO_WDATA_CH3 - This register stores the data that need to be pushed into DMA Tx FIFO. - 0 - 10 - read-write - - - OUTFIFO_PUSH_CH3 - Set this bit to push data into DMA Tx FIFO. - 10 - 1 - read-write - - - - - OUT_LINK_CONF_CH3 - TX CH3 out_link dscr ctrl register - 0x31C - 0x20 - 0x00800000 - - - OUTLINK_STOP_CH3 - Set this bit to stop dealing with the outlink descriptors. - 20 - 1 - read-write - - - OUTLINK_START_CH3 - Set this bit to start dealing with the outlink descriptors. - 21 - 1 - read-write - - - OUTLINK_RESTART_CH3 - Set this bit to restart a new outlink from the last address. - 22 - 1 - read-write - - - OUTLINK_PARK_CH3 - 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. - 23 - 1 - read-only - - - - - OUT_LINK_ADDR_CH3 - TX CH3 out_link dscr addr register - 0x320 - 0x20 - - - OUTLINK_ADDR_CH3 - This register stores the first outlink descriptor's address. - 0 - 32 - read-write - - - - - OUT_STATE_CH3 - TX CH3 state register - 0x324 - 0x20 - - - OUTLINK_DSCR_ADDR_CH3 - This register stores the current outlink descriptor's address. - 0 - 18 - read-only - - - OUT_DSCR_STATE_CH3 - This register stores the current descriptor state machine state. - 18 - 2 - read-only - - - OUT_STATE_CH3 - This register stores the current control module state machine state. - 20 - 4 - read-only - - - - - OUT_EOF_DES_ADDR_CH3 - TX CH3 eof des addr register - 0x328 - 0x20 - - - OUT_EOF_DES_ADDR_CH3 - This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. - 0 - 32 - read-only - - - - - OUT_DSCR_CH3 - TX CH3 next dscr addr register - 0x32C - 0x20 - - - OUTLINK_DSCR_CH3 - The address of the next outlink descriptor address y. - 0 - 32 - read-only - - - - - OUT_DSCR_BF0_CH3 - TX CH3 last dscr addr register - 0x330 - 0x20 - - - OUTLINK_DSCR_BF0_CH3 - The address of the last outlink descriptor's next address y-1. - 0 - 32 - read-only - - - - - OUT_DSCR_BF1_CH3 - TX CH3 second-to-last dscr addr register - 0x334 - 0x20 - - - OUTLINK_DSCR_BF1_CH3 - The address of the second-to-last outlink descriptor's next address y-2. - 0 - 32 - read-only - - - - - OUT_ARB_CH3 - TX CH3 arb register - 0x33C - 0x20 - 0x00000011 - - - OUT_ARB_TOKEN_NUM_CH3 - Set the max number of token count of arbiter - 0 - 4 - read-write - - - EXTER_OUT_ARB_PRIORITY_CH3 - Set the priority of channel - 4 - 2 - read-write - - - - - OUT_ETM_CONF_CH3 - TX CH3 ETM config register - 0x368 - 0x20 - 0x00000004 - - - OUT_ETM_EN_CH3 - Set this bit to 1 to enable ETM task function - 0 - 1 - read-write - - - OUT_ETM_LOOP_EN_CH3 - when this bit is 1, dscr can be processed after receiving a task - 1 - 1 - read-write - - - OUT_DSCR_TASK_MAK_CH3 - ETM dscr_ready maximum cache numbers - 2 - 2 - read-write - - - - - OUT_BUF_LEN_CH3 - tx CH3 buf len register - 0x370 - 0x20 - - - OUT_CMDFIFO_BUF_LEN_HB_CH3 - only for debug - 0 - 13 - read-only - - - - - OUT_FIFO_BCNT_CH3 - tx CH3 fifo byte cnt register - 0x374 - 0x20 - - - OUT_CMDFIFO_OUTFIFO_BCNT_CH3 - only for debug - 0 - 10 - read-only - - - - - OUT_PUSH_BYTECNT_CH3 - tx CH3 push byte cnt register - 0x378 - 0x20 - 0x0000003F - - - OUT_CMDFIFO_PUSH_BYTECNT_CH3 - only for debug - 0 - 8 - read-only - - - - - OUT_XADDR_CH3 - tx CH3 xaddr register - 0x37C - 0x20 - - - OUT_CMDFIFO_XADDR_CH3 - only for debug - 0 - 32 - read-only - - - - - OUT_BLOCK_BUF_LEN_CH3 - tx CH3 block buf len register - 0x380 - 0x20 - - - OUT_BLOCK_BUF_LEN_CH3 - only for debug - 0 - 28 - read-only - - - - - OUT_CONF0_CH4 - TX CH4 config0 register - 0x400 - 0x20 - 0x00000002 - - - OUT_AUTO_WRBACK_CH4 - Set this bit to enable automatic outlink-writeback when all the data pointed by outlink descriptor has been received. - 0 - 1 - read-write - - - OUT_EOF_MODE_CH4 - EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is generated when data need to read has been popped from FIFO in DMA - 1 - 1 - read-write - - - OUTDSCR_BURST_EN_CH4 - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. - 2 - 1 - read-write - - - OUT_ECC_AES_EN_CH4 - When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned. - 3 - 1 - read-write - - - OUT_CHECK_OWNER_CH4 - Set this bit to enable checking the owner attribute of the link descriptor. - 4 - 1 - read-write - - - OUT_MEM_BURST_LENGTH_CH4 - Block size of Tx channel 4. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes - 6 - 3 - read-write - - - OUT_PAGE_BOUND_EN_CH4 - Set this bit to 1 to make sure AXI read data don't cross the address boundary which define by mem_burst_length - 12 - 1 - read-write - - - OUT_ARB_WEIGHT_OPT_DIS_CH4 - Set this bit to 1 to disable arbiter optimum weight function. - 26 - 1 - read-write - - - - - OUT_INT_RAW_CH4 - TX CH4 interrupt raw register - 0x404 - 0x20 - - - OUT_DONE_CH4_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0. - 0 - 1 - read-write - - - OUT_EOF_CH4_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. - 1 - 1 - read-write - - - OUT_DSCR_ERR_CH4_INT_RAW - The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0. - 2 - 1 - read-write - - - OUT_TOTAL_EOF_CH4_INT_RAW - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0. - 3 - 1 - read-write - - - OUTFIFO_OVF_L1_CH4_INT_RAW - The raw interrupt bit turns to high level when fifo is overflow. - 4 - 1 - read-write - - - OUTFIFO_UDF_L1_CH4_INT_RAW - The raw interrupt bit turns to high level when fifo is underflow. - 5 - 1 - read-write - - - OUTFIFO_OVF_L2_CH4_INT_RAW - The raw interrupt bit turns to high level when fifo is overflow. - 6 - 1 - read-write - - - OUTFIFO_UDF_L2_CH4_INT_RAW - The raw interrupt bit turns to high level when fifo is underflow. - 7 - 1 - read-write - - - OUT_DSCR_TASK_OVF_CH4_INT_RAW - The raw interrupt bit turns to high level when dscr ready task fifo is overflow. - 8 - 1 - read-write - - - - - OUT_INT_ENA_CH4 - TX CH4 interrupt ena register - 0x408 - 0x20 - - - OUT_DONE_CH4_INT_ENA - The interrupt enable bit for the OUT_DONE_CH_INT interrupt. - 0 - 1 - read-write - - - OUT_EOF_CH4_INT_ENA - The interrupt enable bit for the OUT_EOF_CH_INT interrupt. - 1 - 1 - read-write - - - OUT_DSCR_ERR_CH4_INT_ENA - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. - 2 - 1 - read-write - - - OUT_TOTAL_EOF_CH4_INT_ENA - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. - 3 - 1 - read-write - - - OUTFIFO_OVF_L1_CH4_INT_ENA - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - 4 - 1 - read-write - - - OUTFIFO_UDF_L1_CH4_INT_ENA - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - 5 - 1 - read-write - - - OUTFIFO_OVF_L2_CH4_INT_ENA - The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. - 6 - 1 - read-write - - - OUTFIFO_UDF_L2_CH4_INT_ENA - The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. - 7 - 1 - read-write - - - OUT_DSCR_TASK_OVF_CH4_INT_ENA - The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. - 8 - 1 - read-write - - - - - OUT_INT_ST_CH4 - TX CH4 interrupt st register - 0x40C - 0x20 - - - OUT_DONE_CH4_INT_ST - The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. - 0 - 1 - read-only - - - OUT_EOF_CH4_INT_ST - The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. - 1 - 1 - read-only - - - OUT_DSCR_ERR_CH4_INT_ST - The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. - 2 - 1 - read-only - - - OUT_TOTAL_EOF_CH4_INT_ST - The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. - 3 - 1 - read-only - - - OUTFIFO_OVF_L1_CH4_INT_ST - The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - 4 - 1 - read-only - - - OUTFIFO_UDF_L1_CH4_INT_ST - The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - 5 - 1 - read-only - - - OUTFIFO_OVF_L2_CH4_INT_ST - The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. - 6 - 1 - read-only - - - OUTFIFO_UDF_L2_CH4_INT_ST - The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. - 7 - 1 - read-only - - - OUT_DSCR_TASK_OVF_CH4_INT_ST - The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. - 8 - 1 - read-only - - - - - OUT_INT_CLR_CH4 - TX CH4 interrupt clr register - 0x410 - 0x20 - - - OUT_DONE_CH4_INT_CLR - Set this bit to clear the OUT_DONE_CH_INT interrupt. - 0 - 1 - write-only - - - OUT_EOF_CH4_INT_CLR - Set this bit to clear the OUT_EOF_CH_INT interrupt. - 1 - 1 - write-only - - - OUT_DSCR_ERR_CH4_INT_CLR - Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. - 2 - 1 - write-only - - - OUT_TOTAL_EOF_CH4_INT_CLR - Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. - 3 - 1 - write-only - - - OUTFIFO_OVF_L1_CH4_INT_CLR - Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. - 4 - 1 - write-only - - - OUTFIFO_UDF_L1_CH4_INT_CLR - Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. - 5 - 1 - write-only - - - OUTFIFO_OVF_L2_CH4_INT_CLR - Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. - 6 - 1 - write-only - - - OUTFIFO_UDF_L2_CH4_INT_CLR - Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. - 7 - 1 - write-only - - - OUT_DSCR_TASK_OVF_CH4_INT_CLR - Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. - 8 - 1 - write-only - - - - - OUTFIFO_STATUS_CH4 - TX CH4 outfifo status register - 0x414 - 0x20 - 0x00020082 - - - OUTFIFO_FULL_L2_CH4 - Tx FIFO full signal for Tx channel 2. - 0 - 1 - read-only - - - OUTFIFO_EMPTY_L2_CH4 - Tx FIFO empty signal for Tx channel 2. - 1 - 1 - read-only - - - OUTFIFO_CNT_L2_CH4 - The register stores the byte number of the data in Tx FIFO for Tx channel 2. - 2 - 4 - read-only - - - OUTFIFO_FULL_L1_CH4 - Tx FIFO full signal for Tx channel 2. - 6 - 1 - read-only - - - OUTFIFO_EMPTY_L1_CH4 - Tx FIFO empty signal for Tx channel 2. - 7 - 1 - read-only - - - OUTFIFO_CNT_L1_CH4 - The register stores the byte number of the data in Tx FIFO for Tx channel 2. - 8 - 5 - read-only - - - OUTFIFO_FULL_L3_CH4 - Tx FIFO full signal for Tx channel 2. - 16 - 1 - read-only - - - OUTFIFO_EMPTY_L3_CH4 - Tx FIFO empty signal for Tx channel 2. - 17 - 1 - read-only - - - OUTFIFO_CNT_L3_CH4 - The register stores the byte number of the data in Tx FIFO for Tx channel 2. - 18 - 2 - read-only - - - - - OUT_PUSH_CH4 - TX CH4 outfifo push register - 0x418 - 0x20 - - - OUTFIFO_WDATA_CH4 - This register stores the data that need to be pushed into DMA Tx FIFO. - 0 - 10 - read-write - - - OUTFIFO_PUSH_CH4 - Set this bit to push data into DMA Tx FIFO. - 10 - 1 - read-write - - - - - OUT_LINK_CONF_CH4 - TX CH4 out_link dscr ctrl register - 0x41C - 0x20 - 0x00800000 - - - OUTLINK_STOP_CH4 - Set this bit to stop dealing with the outlink descriptors. - 20 - 1 - read-write - - - OUTLINK_START_CH4 - Set this bit to start dealing with the outlink descriptors. - 21 - 1 - read-write - - - OUTLINK_RESTART_CH4 - Set this bit to restart a new outlink from the last address. - 22 - 1 - read-write - - - OUTLINK_PARK_CH4 - 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. - 23 - 1 - read-only - - - - - OUT_LINK_ADDR_CH4 - TX CH4 out_link dscr addr register - 0x420 - 0x20 - - - OUTLINK_ADDR_CH4 - This register stores the first outlink descriptor's address. - 0 - 32 - read-write - - - - - OUT_STATE_CH4 - TX CH4 state register - 0x424 - 0x20 - - - OUTLINK_DSCR_ADDR_CH4 - This register stores the current outlink descriptor's address. - 0 - 18 - read-only - - - OUT_DSCR_STATE_CH4 - This register stores the current descriptor state machine state. - 18 - 2 - read-only - - - OUT_STATE_CH4 - This register stores the current control module state machine state. - 20 - 4 - read-only - - - - - OUT_EOF_DES_ADDR_CH4 - TX CH4 eof des addr register - 0x428 - 0x20 - - - OUT_EOF_DES_ADDR_CH4 - This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. - 0 - 32 - read-only - - - - - OUT_DSCR_CH4 - TX CH4 next dscr addr register - 0x42C - 0x20 - - - OUTLINK_DSCR_CH4 - The address of the next outlink descriptor address y. - 0 - 32 - read-only - - - - - OUT_DSCR_BF0_CH4 - TX CH4 last dscr addr register - 0x430 - 0x20 - - - OUTLINK_DSCR_BF0_CH4 - The address of the last outlink descriptor's next address y-1. - 0 - 32 - read-only - - - - - OUT_DSCR_BF1_CH4 - TX CH4 second-to-last dscr addr register - 0x434 - 0x20 - - - OUTLINK_DSCR_BF1_CH4 - The address of the second-to-last outlink descriptor's next address y-2. - 0 - 32 - read-only - - - - - OUT_ARB_CH4 - TX CH4 arb register - 0x43C - 0x20 - 0x00000011 - - - OUT_ARB_TOKEN_NUM_CH4 - Set the max number of token count of arbiter - 0 - 4 - read-write - - - EXTER_OUT_ARB_PRIORITY_CH4 - Set the priority of channel - 4 - 2 - read-write - - - - - OUT_ETM_CONF_CH4 - TX CH4 ETM config register - 0x468 - 0x20 - 0x00000004 - - - OUT_ETM_EN_CH4 - Set this bit to 1 to enable ETM task function - 0 - 1 - read-write - - - OUT_ETM_LOOP_EN_CH4 - when this bit is 1, dscr can be processed after receiving a task - 1 - 1 - read-write - - - OUT_DSCR_TASK_MAK_CH4 - ETM dscr_ready maximum cache numbers - 2 - 2 - read-write - - - - - OUT_BUF_LEN_CH4 - tx CH4 buf len register - 0x470 - 0x20 - - - OUT_CMDFIFO_BUF_LEN_HB_CH4 - only for debug - 0 - 13 - read-only - - - - - OUT_FIFO_BCNT_CH4 - tx CH4 fifo byte cnt register - 0x474 - 0x20 - - - OUT_CMDFIFO_OUTFIFO_BCNT_CH4 - only for debug - 0 - 10 - read-only - - - - - OUT_PUSH_BYTECNT_CH4 - tx CH4 push byte cnt register - 0x478 - 0x20 - 0x0000003F - - - OUT_CMDFIFO_PUSH_BYTECNT_CH4 - only for debug - 0 - 8 - read-only - - - - - OUT_XADDR_CH4 - tx CH4 xaddr register - 0x47C - 0x20 - - - OUT_CMDFIFO_XADDR_CH4 - only for debug - 0 - 32 - read-only - - - - - OUT_BLOCK_BUF_LEN_CH4 - tx CH4 block buf len register - 0x480 - 0x20 - - - OUT_BLOCK_BUF_LEN_CH4 - only for debug - 0 - 28 - read-only - - - - - IN_CONF0_CH0 - RX CH0 config0 register - 0x500 - 0x20 - - - INDSCR_BURST_EN_CH0 - Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor when accessing SRAM. - 2 - 1 - read-write - - - IN_ECC_AES_EN_CH0 - When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned. - 3 - 1 - read-write - - - IN_CHECK_OWNER_CH0 - Set this bit to enable checking the owner attribute of the link descriptor. - 4 - 1 - read-write - - - IN_MEM_BURST_LENGTH_CH0 - Block size of Rx channel 0. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes - 6 - 3 - read-write - - - IN_PAGE_BOUND_EN_CH0 - Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length - 12 - 1 - read-write - - - IN_RST_CH0 - Write 1 then write 0 to this bit to reset Rx channel - 24 - 1 - read-write - - - IN_CMD_DISABLE_CH0 - Write 1 before reset and write 0 after reset - 25 - 1 - read-write - - - IN_ARB_WEIGHT_OPT_DIS_CH0 - Set this bit to 1 to disable arbiter optimum weight function. - 26 - 1 - read-write - - - - - IN_INT_RAW_CH0 - RX CH0 interrupt raw register - 0x504 - 0x20 - - - IN_DONE_CH0_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 0. - 0 - 1 - read-write - - - IN_SUC_EOF_CH0_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0. - 1 - 1 - read-write - - - IN_ERR_EOF_CH0_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and data error is detected - 2 - 1 - read-write - - - IN_DSCR_ERR_CH0_INT_RAW - The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0. - 3 - 1 - read-write - - - INFIFO_OVF_L1_CH0_INT_RAW - The raw interrupt bit turns to high level when fifo of Rx channel is overflow. - 4 - 1 - read-write - - - INFIFO_UDF_L1_CH0_INT_RAW - The raw interrupt bit turns to high level when fifo of Rx channel is underflow. - 5 - 1 - read-write - - - INFIFO_OVF_L2_CH0_INT_RAW - The raw interrupt bit turns to high level when fifo of Rx channel is overflow. - 6 - 1 - read-write - - - INFIFO_UDF_L2_CH0_INT_RAW - The raw interrupt bit turns to high level when fifo of Rx channel is underflow. - 7 - 1 - read-write - - - IN_DSCR_EMPTY_CH0_INT_RAW - The raw interrupt bit turns to high level when the last descriptor is done but fifo also remain data. - 8 - 1 - read-write - - - IN_DSCR_TASK_OVF_CH0_INT_RAW - The raw interrupt bit turns to high level when dscr ready task fifo is overflow. - 9 - 1 - read-write - - - - - IN_INT_ENA_CH0 - RX CH0 interrupt ena register - 0x508 - 0x20 - - - IN_DONE_CH0_INT_ENA - The interrupt enable bit for the IN_DONE_CH_INT interrupt. - 0 - 1 - read-write - - - IN_SUC_EOF_CH0_INT_ENA - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. - 1 - 1 - read-write - - - IN_ERR_EOF_CH0_INT_ENA - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. - 2 - 1 - read-write - - - IN_DSCR_ERR_CH0_INT_ENA - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. - 3 - 1 - read-write - - - INFIFO_OVF_L1_CH0_INT_ENA - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. - 4 - 1 - read-write - - - INFIFO_UDF_L1_CH0_INT_ENA - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. - 5 - 1 - read-write - - - INFIFO_OVF_L2_CH0_INT_ENA - The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. - 6 - 1 - read-write - - - INFIFO_UDF_L2_CH0_INT_ENA - The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. - 7 - 1 - read-write - - - IN_DSCR_EMPTY_CH0_INT_ENA - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. - 8 - 1 - read-write - - - IN_DSCR_TASK_OVF_CH0_INT_ENA - The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. - 9 - 1 - read-write - - - - - IN_INT_ST_CH0 - RX CH0 interrupt st register - 0x50C - 0x20 - - - IN_DONE_CH0_INT_ST - The raw interrupt status bit for the IN_DONE_CH_INT interrupt. - 0 - 1 - read-only - - - IN_SUC_EOF_CH0_INT_ST - The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. - 1 - 1 - read-only - - - IN_ERR_EOF_CH0_INT_ST - The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. - 2 - 1 - read-only - - - IN_DSCR_ERR_CH0_INT_ST - The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. - 3 - 1 - read-only - - - INFIFO_OVF_L1_CH0_INT_ST - The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. - 4 - 1 - read-only - - - INFIFO_UDF_L1_CH0_INT_ST - The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. - 5 - 1 - read-only - - - INFIFO_OVF_L2_CH0_INT_ST - The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. - 6 - 1 - read-only - - - INFIFO_UDF_L2_CH0_INT_ST - The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. - 7 - 1 - read-only - - - IN_DSCR_EMPTY_CH0_INT_ST - The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. - 8 - 1 - read-only - - - IN_DSCR_TASK_OVF_CH0_INT_ST - The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. - 9 - 1 - read-only - - - - - IN_INT_CLR_CH0 - RX CH0 interrupt clr register - 0x510 - 0x20 - - - IN_DONE_CH0_INT_CLR - Set this bit to clear the IN_DONE_CH_INT interrupt. - 0 - 1 - write-only - - - IN_SUC_EOF_CH0_INT_CLR - Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. - 1 - 1 - write-only - - - IN_ERR_EOF_CH0_INT_CLR - Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. - 2 - 1 - write-only - - - IN_DSCR_ERR_CH0_INT_CLR - Set this bit to clear the INDSCR_ERR_CH_INT interrupt. - 3 - 1 - write-only - - - INFIFO_OVF_L1_CH0_INT_CLR - Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. - 4 - 1 - write-only - - - INFIFO_UDF_L1_CH0_INT_CLR - Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. - 5 - 1 - write-only - - - INFIFO_OVF_L2_CH0_INT_CLR - Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. - 6 - 1 - write-only - - - INFIFO_UDF_L2_CH0_INT_CLR - Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. - 7 - 1 - write-only - - - IN_DSCR_EMPTY_CH0_INT_CLR - Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. - 8 - 1 - write-only - - - IN_DSCR_TASK_OVF_CH0_INT_CLR - Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. - 9 - 1 - write-only - - - - - INFIFO_STATUS_CH0 - RX CH0 INFIFO status register - 0x514 - 0x20 - 0x00020082 - - - INFIFO_FULL_L2_CH0 - Rx FIFO full signal for Rx channel. - 0 - 1 - read-only - - - INFIFO_EMPTY_L2_CH0 - Rx FIFO empty signal for Rx channel. - 1 - 1 - read-only - - - INFIFO_CNT_L2_CH0 - The register stores the byte number of the data in Rx FIFO for Rx channel. - 2 - 4 - read-only - - - INFIFO_FULL_L1_CH0 - Tx FIFO full signal for Tx channel 0. - 6 - 1 - read-only - - - INFIFO_EMPTY_L1_CH0 - Tx FIFO empty signal for Tx channel 0. - 7 - 1 - read-only - - - INFIFO_CNT_L1_CH0 - The register stores the byte number of the data in Tx FIFO for Tx channel 0. - 8 - 5 - read-only - - - INFIFO_FULL_L3_CH0 - Tx FIFO full signal for Tx channel 0. - 16 - 1 - read-only - - - INFIFO_EMPTY_L3_CH0 - Tx FIFO empty signal for Tx channel 0. - 17 - 1 - read-only - - - INFIFO_CNT_L3_CH0 - The register stores the 8byte number of the data in Tx FIFO for Tx channel 0. - 18 - 2 - read-only - - - - - IN_POP_CH0 - RX CH0 INFIFO pop register - 0x518 - 0x20 - 0x00000400 - - - INFIFO_RDATA_CH0 - This register stores the data popping from DMA Rx FIFO. - 0 - 11 - read-only - - - INFIFO_POP_CH0 - Set this bit to pop data from DMA Rx FIFO. - 11 - 1 - read-write - - - - - IN_LINK_CONF_CH0 - RX CH0 in_link dscr ctrl register - 0x51C - 0x20 - 0x01100000 - - - INLINK_AUTO_RET_CH0 - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data. - 20 - 1 - read-write - - - INLINK_STOP_CH0 - Set this bit to stop dealing with the inlink descriptors. - 21 - 1 - read-write - - - INLINK_START_CH0 - Set this bit to start dealing with the inlink descriptors. - 22 - 1 - read-write - - - INLINK_RESTART_CH0 - Set this bit to mount a new inlink descriptor. - 23 - 1 - read-write - - - INLINK_PARK_CH0 - 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. - 24 - 1 - read-only - - - - - IN_LINK_ADDR_CH0 - RX CH0 in_link dscr addr register - 0x520 - 0x20 - - - INLINK_ADDR_CH0 - This register stores the first inlink descriptor's address. - 0 - 32 - read-write - - - - - IN_STATE_CH0 - RX CH0 state register - 0x524 - 0x20 - 0x00800000 - - - INLINK_DSCR_ADDR_CH0 - This register stores the current inlink descriptor's address. - 0 - 18 - read-only - - - IN_DSCR_STATE_CH0 - This register stores the current descriptor state machine state. - 18 - 2 - read-only - - - IN_STATE_CH0 - This register stores the current control module state machine state. - 20 - 3 - read-only - - - IN_RESET_AVAIL_CH0 - This register indicate that if the channel reset is safety. - 23 - 1 - read-only - - - - - IN_SUC_EOF_DES_ADDR_CH0 - RX CH0 eof des addr register - 0x528 - 0x20 - - - IN_SUC_EOF_DES_ADDR_CH0 - This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. - 0 - 32 - read-only - - - - - IN_ERR_EOF_DES_ADDR_CH0 - RX CH0 err eof des addr register - 0x52C - 0x20 - - - IN_ERR_EOF_DES_ADDR_CH0 - This register stores the address of the inlink descriptor when there are some errors in current receiving data. - 0 - 32 - read-only - - - - - IN_DSCR_CH0 - RX CH0 next dscr addr register - 0x530 - 0x20 - - - INLINK_DSCR_CH0 - The address of the next inlink descriptor address x. - 0 - 32 - read-only - - - - - IN_DSCR_BF0_CH0 - RX CH0 last dscr addr register - 0x534 - 0x20 - - - INLINK_DSCR_BF0_CH0 - The address of the last inlink descriptor's next address x-1. - 0 - 32 - read-only - - - - - IN_DSCR_BF1_CH0 - RX CH0 second-to-last dscr addr register - 0x538 - 0x20 - - - INLINK_DSCR_BF1_CH0 - The address of the second-to-last inlink descriptor's next address x-2. - 0 - 32 - read-only - - - - - IN_ARB_CH0 - RX CH0 arb register - 0x540 - 0x20 - 0x00000051 - - - IN_ARB_TOKEN_NUM_CH0 - Set the max number of token count of arbiter - 0 - 4 - read-write - - - EXTER_IN_ARB_PRIORITY_CH0 - Set the priority of channel - 4 - 2 - read-write - - - INTER_IN_ARB_PRIORITY_CH0 - Set the priority of channel - 6 - 3 - read-write - - - - - IN_RO_PD_CONF_CH0 - RX CH0 reorder power config register - 0x548 - 0x20 - - - IN_RO_RAM_CLK_FO_CH0 - 1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. 0: A gate-clock will be used when accessing the RAM in DMA. - 6 - 1 - read-write - - - - - IN_ETM_CONF_CH0 - RX CH0 ETM config register - 0x56C - 0x20 - 0x00000004 - - - IN_ETM_EN_CH0 - Set this bit to 1 to enable ETM task function - 0 - 1 - read-write - - - IN_ETM_LOOP_EN_CH0 - when this bit is 1, dscr can be processed after receiving a task - 1 - 1 - read-write - - - IN_DSCR_TASK_MAK_CH0 - ETM dscr_ready maximum cache numbers - 2 - 2 - read-write - - - - - IN_FIFO_CNT_CH0 - rx CH0 fifo cnt register - 0x580 - 0x20 - - - IN_CMDFIFO_INFIFO_CNT_CH0 - only for debug - 0 - 10 - read-only - - - - - IN_POP_DATA_CNT_CH0 - rx CH0 pop data cnt register - 0x584 - 0x20 - 0x00000007 - - - IN_CMDFIFO_POP_DATA_CNT_CH0 - only for debug - 0 - 8 - read-only - - - - - IN_XADDR_CH0 - rx CH0 xaddr register - 0x588 - 0x20 - - - IN_CMDFIFO_XADDR_CH0 - only for debug - 0 - 32 - read-only - - - - - IN_BUF_HB_RCV_CH0 - rx CH0 buf len hb rcv register - 0x58C - 0x20 - - - IN_CMDFIFO_BUF_HB_RCV_CH0 - only for debug - 0 - 29 - read-only - - - - - IN_CONF0_CH1 - RX CH1 config0 register - 0x600 - 0x20 - - - INDSCR_BURST_EN_CH1 - Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor when accessing SRAM. - 2 - 1 - read-write - - - IN_ECC_AES_EN_CH1 - When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned. - 3 - 1 - read-write - - - IN_CHECK_OWNER_CH1 - Set this bit to enable checking the owner attribute of the link descriptor. - 4 - 1 - read-write - - - IN_MEM_BURST_LENGTH_CH1 - Block size of Rx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes - 6 - 3 - read-write - - - IN_PAGE_BOUND_EN_CH1 - Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length - 12 - 1 - read-write - - - IN_RST_CH1 - Write 1 then write 0 to this bit to reset Rx channel - 24 - 1 - read-write - - - IN_CMD_DISABLE_CH1 - Write 1 before reset and write 0 after reset - 25 - 1 - read-write - - - IN_ARB_WEIGHT_OPT_DIS_CH1 - Set this bit to 1 to disable arbiter optimum weight function. - 26 - 1 - read-write - - - - - IN_INT_RAW_CH1 - RX CH1 interrupt raw register - 0x604 - 0x20 - - - IN_DONE_CH1_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 1. - 0 - 1 - read-write - - - IN_SUC_EOF_CH1_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1. - 1 - 1 - read-write - - - IN_ERR_EOF_CH1_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and data error is detected - 2 - 1 - read-write - - - IN_DSCR_ERR_CH1_INT_RAW - The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 1. - 3 - 1 - read-write - - - INFIFO_OVF_L1_CH1_INT_RAW - This raw interrupt bit turns to high level when fifo of Rx channel is overflow. - 4 - 1 - read-write - - - INFIFO_UDF_L1_CH1_INT_RAW - This raw interrupt bit turns to high level when fifo of Rx channel is underflow. - 5 - 1 - read-write - - - INFIFO_OVF_L2_CH1_INT_RAW - This raw interrupt bit turns to high level when fifo of Rx channel is overflow. - 6 - 1 - read-write - - - INFIFO_UDF_L2_CH1_INT_RAW - This raw interrupt bit turns to high level when fifo of Rx channel is underflow. - 7 - 1 - read-write - - - IN_DSCR_EMPTY_CH1_INT_RAW - The raw interrupt bit turns to high level when the last descriptor is done but fifo also remain data. - 8 - 1 - read-write - - - IN_DSCR_TASK_OVF_CH1_INT_RAW - The raw interrupt bit turns to high level when dscr ready task fifo is overflow. - 9 - 1 - read-write - - - - - IN_INT_ENA_CH1 - RX CH1 interrupt ena register - 0x608 - 0x20 - - - IN_DONE_CH1_INT_ENA - The interrupt enable bit for the IN_DONE_CH_INT interrupt. - 0 - 1 - read-write - - - IN_SUC_EOF_CH1_INT_ENA - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. - 1 - 1 - read-write - - - IN_ERR_EOF_CH1_INT_ENA - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. - 2 - 1 - read-write - - - IN_DSCR_ERR_CH1_INT_ENA - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. - 3 - 1 - read-write - - - INFIFO_OVF_L1_CH1_INT_ENA - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. - 4 - 1 - read-write - - - INFIFO_UDF_L1_CH1_INT_ENA - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. - 5 - 1 - read-write - - - INFIFO_OVF_L2_CH1_INT_ENA - The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. - 6 - 1 - read-write - - - INFIFO_UDF_L2_CH1_INT_ENA - The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. - 7 - 1 - read-write - - - IN_DSCR_EMPTY_CH1_INT_ENA - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. - 8 - 1 - read-write - - - IN_DSCR_TASK_OVF_CH1_INT_ENA - The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. - 9 - 1 - read-write - - - - - IN_INT_ST_CH1 - RX CH1 interrupt st register - 0x60C - 0x20 - - - IN_DONE_CH1_INT_ST - The raw interrupt status bit for the IN_DONE_CH_INT interrupt. - 0 - 1 - read-only - - - IN_SUC_EOF_CH1_INT_ST - The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. - 1 - 1 - read-only - - - IN_ERR_EOF_CH1_INT_ST - The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. - 2 - 1 - read-only - - - IN_DSCR_ERR_CH1_INT_ST - The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. - 3 - 1 - read-only - - - INFIFO_OVF_L1_CH1_INT_ST - The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. - 4 - 1 - read-only - - - INFIFO_UDF_L1_CH1_INT_ST - The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. - 5 - 1 - read-only - - - INFIFO_OVF_L2_CH1_INT_ST - The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. - 6 - 1 - read-only - - - INFIFO_UDF_L2_CH1_INT_ST - The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. - 7 - 1 - read-only - - - IN_DSCR_EMPTY_CH1_INT_ST - The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. - 8 - 1 - read-only - - - IN_DSCR_TASK_OVF_CH1_INT_ST - The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. - 9 - 1 - read-only - - - - - IN_INT_CLR_CH1 - RX CH1 interrupt clr register - 0x610 - 0x20 - - - IN_DONE_CH1_INT_CLR - Set this bit to clear the IN_DONE_CH_INT interrupt. - 0 - 1 - write-only - - - IN_SUC_EOF_CH1_INT_CLR - Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. - 1 - 1 - write-only - - - IN_ERR_EOF_CH1_INT_CLR - Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. - 2 - 1 - write-only - - - IN_DSCR_ERR_CH1_INT_CLR - Set this bit to clear the INDSCR_ERR_CH_INT interrupt. - 3 - 1 - write-only - - - INFIFO_OVF_L1_CH1_INT_CLR - Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. - 4 - 1 - write-only - - - INFIFO_UDF_L1_CH1_INT_CLR - Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. - 5 - 1 - write-only - - - INFIFO_OVF_L2_CH1_INT_CLR - Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. - 6 - 1 - write-only - - - INFIFO_UDF_L2_CH1_INT_CLR - Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. - 7 - 1 - write-only - - - IN_DSCR_EMPTY_CH1_INT_CLR - Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. - 8 - 1 - write-only - - - IN_DSCR_TASK_OVF_CH1_INT_CLR - Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. - 9 - 1 - write-only - - - - - INFIFO_STATUS_CH1 - RX CH1 INFIFO status register - 0x614 - 0x20 - 0x00020082 - - - INFIFO_FULL_L2_CH1 - Rx FIFO full signal for Rx channel. - 0 - 1 - read-only - - - INFIFO_EMPTY_L2_CH1 - Rx FIFO empty signal for Rx channel. - 1 - 1 - read-only - - - INFIFO_CNT_L2_CH1 - The register stores the byte number of the data in Rx FIFO for Rx channel. - 2 - 4 - read-only - - - INFIFO_FULL_L1_CH1 - Tx FIFO full signal for Tx channel 1. - 6 - 1 - read-only - - - INFIFO_EMPTY_L1_CH1 - Tx FIFO empty signal for Tx channel 1. - 7 - 1 - read-only - - - INFIFO_CNT_L1_CH1 - The register stores the byte number of the data in Tx FIFO for Tx channel 1. - 8 - 5 - read-only - - - INFIFO_FULL_L3_CH1 - Tx FIFO full signal for Tx channel 1. - 16 - 1 - read-only - - - INFIFO_EMPTY_L3_CH1 - Tx FIFO empty signal for Tx channel 1. - 17 - 1 - read-only - - - INFIFO_CNT_L3_CH1 - The register stores the byte number of the data in Tx FIFO for Tx channel 1. - 18 - 2 - read-only - - - - - IN_POP_CH1 - RX CH1 INFIFO pop register - 0x618 - 0x20 - 0x00000400 - - - INFIFO_RDATA_CH1 - This register stores the data popping from DMA Rx FIFO. - 0 - 11 - read-only - - - INFIFO_POP_CH1 - Set this bit to pop data from DMA Rx FIFO. - 11 - 1 - read-write - - - - - IN_LINK_CONF_CH1 - RX CH1 in_link dscr ctrl register - 0x61C - 0x20 - 0x01100000 - - - INLINK_AUTO_RET_CH1 - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data. - 20 - 1 - read-write - - - INLINK_STOP_CH1 - Set this bit to stop dealing with the inlink descriptors. - 21 - 1 - read-write - - - INLINK_START_CH1 - Set this bit to start dealing with the inlink descriptors. - 22 - 1 - read-write - - - INLINK_RESTART_CH1 - Set this bit to mount a new inlink descriptor. - 23 - 1 - read-write - - - INLINK_PARK_CH1 - 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. - 24 - 1 - read-only - - - - - IN_LINK_ADDR_CH1 - RX CH1 in_link dscr addr register - 0x620 - 0x20 - - - INLINK_ADDR_CH1 - This register stores the first inlink descriptor's address. - 0 - 32 - read-write - - - - - IN_STATE_CH1 - RX CH1 state register - 0x624 - 0x20 - 0x00800000 - - - INLINK_DSCR_ADDR_CH1 - This register stores the current inlink descriptor's address. - 0 - 18 - read-only - - - IN_DSCR_STATE_CH1 - This register stores the current descriptor state machine state. - 18 - 2 - read-only - - - IN_STATE_CH1 - This register stores the current control module state machine state. - 20 - 3 - read-only - - - IN_RESET_AVAIL_CH1 - This register indicate that if the channel reset is safety. - 23 - 1 - read-only - - - - - IN_SUC_EOF_DES_ADDR_CH1 - RX CH1 eof des addr register - 0x628 - 0x20 - - - IN_SUC_EOF_DES_ADDR_CH1 - This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. - 0 - 32 - read-only - - - - - IN_ERR_EOF_DES_ADDR_CH1 - RX CH1 err eof des addr register - 0x62C - 0x20 - - - IN_ERR_EOF_DES_ADDR_CH1 - This register stores the address of the inlink descriptor when there are some errors in current receiving data. - 0 - 32 - read-only - - - - - IN_DSCR_CH1 - RX CH1 next dscr addr register - 0x630 - 0x20 - - - INLINK_DSCR_CH1 - The address of the next inlink descriptor address x. - 0 - 32 - read-only - - - - - IN_DSCR_BF0_CH1 - RX CH1 last dscr addr register - 0x634 - 0x20 - - - INLINK_DSCR_BF0_CH1 - The address of the last inlink descriptor's next address x-1. - 0 - 32 - read-only - - - - - IN_DSCR_BF1_CH1 - RX CH1 second-to-last dscr addr register - 0x638 - 0x20 - - - INLINK_DSCR_BF1_CH1 - The address of the second-to-last inlink descriptor's next address x-2. - 0 - 32 - read-only - - - - - IN_ARB_CH1 - RX CH1 arb register - 0x640 - 0x20 - 0x00000051 - - - IN_ARB_TOKEN_NUM_CH1 - Set the max number of token count of arbiter - 0 - 4 - read-write - - - EXTER_IN_ARB_PRIORITY_CH1 - Set the priority of channel - 4 - 2 - read-write - - - INTER_IN_ARB_PRIORITY_CH1 - Set the priority of channel - 6 - 3 - read-write - - - - - IN_ETM_CONF_CH1 - RX CH1 ETM config register - 0x648 - 0x20 - 0x00000004 - - - IN_ETM_EN_CH1 - Set this bit to 1 to enable ETM task function - 0 - 1 - read-write - - - IN_ETM_LOOP_EN_CH1 - when this bit is 1, dscr can be processed after receiving a task - 1 - 1 - read-write - - - IN_DSCR_TASK_MAK_CH1 - ETM dscr_ready maximum cache numbers - 2 - 2 - read-write - - - - - IN_FIFO_CNT_CH1 - rx CH1 fifo cnt register - 0x680 - 0x20 - - - IN_CMDFIFO_INFIFO_CNT_CH1 - only for debug - 0 - 10 - read-only - - - - - IN_POP_DATA_CNT_CH1 - rx CH1 pop data cnt register - 0x684 - 0x20 - 0x00000007 - - - IN_CMDFIFO_POP_DATA_CNT_CH1 - only for debug - 0 - 8 - read-only - - - - - IN_XADDR_CH1 - rx CH1 xaddr register - 0x688 - 0x20 - - - IN_CMDFIFO_XADDR_CH1 - only for debug - 0 - 32 - read-only - - - - - IN_BUF_HB_RCV_CH1 - rx CH1 buf len hb rcv register - 0x68C - 0x20 - - - IN_CMDFIFO_BUF_HB_RCV_CH1 - only for debug - 0 - 29 - read-only - - - - - IN_CONF0_CH2 - RX CH2 config0 register - 0x700 - 0x20 - - - INDSCR_BURST_EN_CH2 - Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor when accessing SRAM. - 2 - 1 - read-write - - - IN_ECC_AES_EN_CH2 - When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned. - 3 - 1 - read-write - - - IN_CHECK_OWNER_CH2 - Set this bit to enable checking the owner attribute of the link descriptor. - 4 - 1 - read-write - - - IN_MEM_BURST_LENGTH_CH2 - Block size of Rx channel 2. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes - 6 - 3 - read-write - - - IN_PAGE_BOUND_EN_CH2 - Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length - 12 - 1 - read-write - - - IN_RST_CH2 - Write 1 then write 0 to this bit to reset Rx channel - 24 - 1 - read-write - - - IN_CMD_DISABLE_CH2 - Write 1 before reset and write 0 after reset - 25 - 1 - read-write - - - IN_ARB_WEIGHT_OPT_DIS_CH2 - Set this bit to 1 to disable arbiter optimum weight function. - 26 - 1 - read-write - - - - - IN_INT_RAW_CH2 - RX CH2 interrupt raw register - 0x704 - 0x20 - - - IN_DONE_CH2_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 1. - 0 - 1 - read-write - - - IN_SUC_EOF_CH2_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1. - 1 - 1 - read-write - - - IN_ERR_EOF_CH2_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and data error is detected - 2 - 1 - read-write - - - IN_DSCR_ERR_CH2_INT_RAW - The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 1. - 3 - 1 - read-write - - - INFIFO_OVF_L1_CH2_INT_RAW - This raw interrupt bit turns to high level when fifo of Rx channel is overflow. - 4 - 1 - read-write - - - INFIFO_UDF_L1_CH2_INT_RAW - This raw interrupt bit turns to high level when fifo of Rx channel is underflow. - 5 - 1 - read-write - - - INFIFO_OVF_L2_CH2_INT_RAW - This raw interrupt bit turns to high level when fifo of Rx channel is overflow. - 6 - 1 - read-write - - - INFIFO_UDF_L2_CH2_INT_RAW - This raw interrupt bit turns to high level when fifo of Rx channel is underflow. - 7 - 1 - read-write - - - IN_DSCR_EMPTY_CH2_INT_RAW - The raw interrupt bit turns to high level when the last descriptor is done but fifo also remain data. - 8 - 1 - read-write - - - IN_DSCR_TASK_OVF_CH2_INT_RAW - The raw interrupt bit turns to high level when dscr ready task fifo is overflow. - 9 - 1 - read-write - - - - - IN_INT_ENA_CH2 - RX CH2 interrupt ena register - 0x708 - 0x20 - - - IN_DONE_CH2_INT_ENA - The interrupt enable bit for the IN_DONE_CH_INT interrupt. - 0 - 1 - read-write - - - IN_SUC_EOF_CH2_INT_ENA - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. - 1 - 1 - read-write - - - IN_ERR_EOF_CH2_INT_ENA - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. - 2 - 1 - read-write - - - IN_DSCR_ERR_CH2_INT_ENA - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. - 3 - 1 - read-write - - - INFIFO_OVF_L1_CH2_INT_ENA - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. - 4 - 1 - read-write - - - INFIFO_UDF_L1_CH2_INT_ENA - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. - 5 - 1 - read-write - - - INFIFO_OVF_L2_CH2_INT_ENA - The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. - 6 - 1 - read-write - - - INFIFO_UDF_L2_CH2_INT_ENA - The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. - 7 - 1 - read-write - - - IN_DSCR_EMPTY_CH2_INT_ENA - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. - 8 - 1 - read-write - - - IN_DSCR_TASK_OVF_CH2_INT_ENA - The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. - 9 - 1 - read-write - - - - - IN_INT_ST_CH2 - RX CH2 interrupt st register - 0x70C - 0x20 - - - IN_DONE_CH2_INT_ST - The raw interrupt status bit for the IN_DONE_CH_INT interrupt. - 0 - 1 - read-only - - - IN_SUC_EOF_CH2_INT_ST - The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. - 1 - 1 - read-only - - - IN_ERR_EOF_CH2_INT_ST - The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. - 2 - 1 - read-only - - - IN_DSCR_ERR_CH2_INT_ST - The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. - 3 - 1 - read-only - - - INFIFO_OVF_L1_CH2_INT_ST - The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. - 4 - 1 - read-only - - - INFIFO_UDF_L1_CH2_INT_ST - The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. - 5 - 1 - read-only - - - INFIFO_OVF_L2_CH2_INT_ST - The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. - 6 - 1 - read-only - - - INFIFO_UDF_L2_CH2_INT_ST - The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. - 7 - 1 - read-only - - - IN_DSCR_EMPTY_CH2_INT_ST - The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. - 8 - 1 - read-only - - - IN_DSCR_TASK_OVF_CH2_INT_ST - The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. - 9 - 1 - read-only - - - - - IN_INT_CLR_CH2 - RX CH2 interrupt clr register - 0x710 - 0x20 - - - IN_DONE_CH2_INT_CLR - Set this bit to clear the IN_DONE_CH_INT interrupt. - 0 - 1 - write-only - - - IN_SUC_EOF_CH2_INT_CLR - Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. - 1 - 1 - write-only - - - IN_ERR_EOF_CH2_INT_CLR - Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. - 2 - 1 - write-only - - - IN_DSCR_ERR_CH2_INT_CLR - Set this bit to clear the INDSCR_ERR_CH_INT interrupt. - 3 - 1 - write-only - - - INFIFO_OVF_L1_CH2_INT_CLR - Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. - 4 - 1 - write-only - - - INFIFO_UDF_L1_CH2_INT_CLR - Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. - 5 - 1 - write-only - - - INFIFO_OVF_L2_CH2_INT_CLR - Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. - 6 - 1 - write-only - - - INFIFO_UDF_L2_CH2_INT_CLR - Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. - 7 - 1 - write-only - - - IN_DSCR_EMPTY_CH2_INT_CLR - Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. - 8 - 1 - write-only - - - IN_DSCR_TASK_OVF_CH2_INT_CLR - Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. - 9 - 1 - write-only - - - - - INFIFO_STATUS_CH2 - RX CH2 INFIFO status register - 0x714 - 0x20 - 0x00020082 - - - INFIFO_FULL_L2_CH2 - Rx FIFO full signal for Rx channel. - 0 - 1 - read-only - - - INFIFO_EMPTY_L2_CH2 - Rx FIFO empty signal for Rx channel. - 1 - 1 - read-only - - - INFIFO_CNT_L2_CH2 - The register stores the byte number of the data in Rx FIFO for Rx channel. - 2 - 4 - read-only - - - INFIFO_FULL_L1_CH2 - Tx FIFO full signal for Tx channel 1. - 6 - 1 - read-only - - - INFIFO_EMPTY_L1_CH2 - Tx FIFO empty signal for Tx channel 1. - 7 - 1 - read-only - - - INFIFO_CNT_L1_CH2 - The register stores the byte number of the data in Tx FIFO for Tx channel 1. - 8 - 5 - read-only - - - INFIFO_FULL_L3_CH2 - Tx FIFO full signal for Tx channel 1. - 16 - 1 - read-only - - - INFIFO_EMPTY_L3_CH2 - Tx FIFO empty signal for Tx channel 1. - 17 - 1 - read-only - - - INFIFO_CNT_L3_CH2 - The register stores the byte number of the data in Tx FIFO for Tx channel 1. - 18 - 2 - read-only - - - - - IN_POP_CH2 - RX CH2 INFIFO pop register - 0x718 - 0x20 - 0x00000400 - - - INFIFO_RDATA_CH2 - This register stores the data popping from DMA Rx FIFO. - 0 - 11 - read-only - - - INFIFO_POP_CH2 - Set this bit to pop data from DMA Rx FIFO. - 11 - 1 - read-write - - - - - IN_LINK_CONF_CH2 - RX CH2 in_link dscr ctrl register - 0x71C - 0x20 - 0x01100000 - - - INLINK_AUTO_RET_CH2 - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data. - 20 - 1 - read-write - - - INLINK_STOP_CH2 - Set this bit to stop dealing with the inlink descriptors. - 21 - 1 - read-write - - - INLINK_START_CH2 - Set this bit to start dealing with the inlink descriptors. - 22 - 1 - read-write - - - INLINK_RESTART_CH2 - Set this bit to mount a new inlink descriptor. - 23 - 1 - read-write - - - INLINK_PARK_CH2 - 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. - 24 - 1 - read-only - - - - - IN_LINK_ADDR_CH2 - RX CH2 in_link dscr addr register - 0x720 - 0x20 - - - INLINK_ADDR_CH2 - This register stores the first inlink descriptor's address. - 0 - 32 - read-write - - - - - IN_STATE_CH2 - RX CH2 state register - 0x724 - 0x20 - 0x00800000 - - - INLINK_DSCR_ADDR_CH2 - This register stores the current inlink descriptor's address. - 0 - 18 - read-only - - - IN_DSCR_STATE_CH2 - This register stores the current descriptor state machine state. - 18 - 2 - read-only - - - IN_STATE_CH2 - This register stores the current control module state machine state. - 20 - 3 - read-only - - - IN_RESET_AVAIL_CH2 - This register indicate that if the channel reset is safety. - 23 - 1 - read-only - - - - - IN_SUC_EOF_DES_ADDR_CH2 - RX CH2 eof des addr register - 0x728 - 0x20 - - - IN_SUC_EOF_DES_ADDR_CH2 - This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. - 0 - 32 - read-only - - - - - IN_ERR_EOF_DES_ADDR_CH2 - RX CH2 err eof des addr register - 0x72C - 0x20 - - - IN_ERR_EOF_DES_ADDR_CH2 - This register stores the address of the inlink descriptor when there are some errors in current receiving data. - 0 - 32 - read-only - - - - - IN_DSCR_CH2 - RX CH2 next dscr addr register - 0x730 - 0x20 - - - INLINK_DSCR_CH2 - The address of the next inlink descriptor address x. - 0 - 32 - read-only - - - - - IN_DSCR_BF0_CH2 - RX CH2 last dscr addr register - 0x734 - 0x20 - - - INLINK_DSCR_BF0_CH2 - The address of the last inlink descriptor's next address x-1. - 0 - 32 - read-only - - - - - IN_DSCR_BF1_CH2 - RX CH2 second-to-last dscr addr register - 0x738 - 0x20 - - - INLINK_DSCR_BF1_CH2 - The address of the second-to-last inlink descriptor's next address x-2. - 0 - 32 - read-only - - - - - IN_ARB_CH2 - RX CH2 arb register - 0x740 - 0x20 - 0x00000041 - - - IN_ARB_TOKEN_NUM_CH2 - Set the max number of token count of arbiter - 0 - 4 - read-write - - - INTER_IN_ARB_PRIORITY_CH2 - Set the priority of channel - 6 - 3 - read-write - - - - - IN_ETM_CONF_CH2 - RX CH2 ETM config register - 0x748 - 0x20 - 0x00000004 - - - IN_ETM_EN_CH2 - Set this bit to 1 to enable ETM task function - 0 - 1 - read-write - - - IN_ETM_LOOP_EN_CH2 - when this bit is 1, dscr can be processed after receiving a task - 1 - 1 - read-write - - - IN_DSCR_TASK_MAK_CH2 - ETM dscr_ready maximum cache numbers - 2 - 2 - read-write - - - - - IN_FIFO_CNT_CH2 - rx CH2 fifo cnt register - 0x780 - 0x20 - - - IN_CMDFIFO_INFIFO_CNT_CH2 - only for debug - 0 - 10 - read-only - - - - - IN_POP_DATA_CNT_CH2 - rx CH2 pop data cnt register - 0x784 - 0x20 - 0x00000007 - - - IN_CMDFIFO_POP_DATA_CNT_CH2 - only for debug - 0 - 8 - read-only - - - - - IN_XADDR_CH2 - rx CH2 xaddr register - 0x788 - 0x20 - - - IN_CMDFIFO_XADDR_CH2 - only for debug - 0 - 32 - read-only - - - - - IN_BUF_HB_RCV_CH2 - rx CH2 buf len hb rcv register - 0x78C - 0x20 - - - IN_CMDFIFO_BUF_HB_RCV_CH2 - only for debug - 0 - 29 - read-only - - - - - IN_CONF0_CH3 - RX CH3 config0 register - 0x800 - 0x20 - - - INDSCR_BURST_EN_CH3 - Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor when accessing SRAM. - 2 - 1 - read-write - - - IN_ECC_AES_EN_CH3 - When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned. - 3 - 1 - read-write - - - IN_CHECK_OWNER_CH3 - Set this bit to enable checking the owner attribute of the link descriptor. - 4 - 1 - read-write - - - IN_MEM_BURST_LENGTH_CH3 - Block size of Rx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes - 6 - 3 - read-write - - - IN_PAGE_BOUND_EN_CH3 - Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length - 12 - 1 - read-write - - - IN_RST_CH3 - Write 1 then write 0 to this bit to reset Rx channel - 24 - 1 - read-write - - - IN_CMD_DISABLE_CH3 - Write 1 before reset and write 0 after reset - 25 - 1 - read-write - - - IN_ARB_WEIGHT_OPT_DIS_CH3 - Set this bit to 1 to disable arbiter optimum weight function. - 26 - 1 - read-write - - - - - IN_INT_RAW_CH3 - RX CH3 interrupt raw register - 0x804 - 0x20 - - - IN_DONE_CH3_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 1. - 0 - 1 - read-write - - - IN_SUC_EOF_CH3_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1. - 1 - 1 - read-write - - - IN_ERR_EOF_CH3_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and data error is detected - 2 - 1 - read-write - - - IN_DSCR_ERR_CH3_INT_RAW - The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 1. - 3 - 1 - read-write - - - INFIFO_OVF_L1_CH3_INT_RAW - This raw interrupt bit turns to high level when fifo of Rx channel is overflow. - 4 - 1 - read-write - - - INFIFO_UDF_L1_CH3_INT_RAW - This raw interrupt bit turns to high level when fifo of Rx channel is underflow. - 5 - 1 - read-write - - - INFIFO_OVF_L2_CH3_INT_RAW - This raw interrupt bit turns to high level when fifo of Rx channel is overflow. - 6 - 1 - read-write - - - INFIFO_UDF_L2_CH3_INT_RAW - This raw interrupt bit turns to high level when fifo of Rx channel is underflow. - 7 - 1 - read-write - - - IN_DSCR_EMPTY_CH3_INT_RAW - The raw interrupt bit turns to high level when the last descriptor is done but fifo also remain data. - 8 - 1 - read-write - - - IN_DSCR_TASK_OVF_CH3_INT_RAW - The raw interrupt bit turns to high level when dscr ready task fifo is overflow. - 9 - 1 - read-write - - - - - IN_INT_ENA_CH3 - RX CH3 interrupt ena register - 0x808 - 0x20 - - - IN_DONE_CH3_INT_ENA - The interrupt enable bit for the IN_DONE_CH_INT interrupt. - 0 - 1 - read-write - - - IN_SUC_EOF_CH3_INT_ENA - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. - 1 - 1 - read-write - - - IN_ERR_EOF_CH3_INT_ENA - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. - 2 - 1 - read-write - - - IN_DSCR_ERR_CH3_INT_ENA - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. - 3 - 1 - read-write - - - INFIFO_OVF_L1_CH3_INT_ENA - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. - 4 - 1 - read-write - - - INFIFO_UDF_L1_CH3_INT_ENA - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. - 5 - 1 - read-write - - - INFIFO_OVF_L2_CH3_INT_ENA - The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. - 6 - 1 - read-write - - - INFIFO_UDF_L2_CH3_INT_ENA - The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. - 7 - 1 - read-write - - - IN_DSCR_EMPTY_CH3_INT_ENA - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. - 8 - 1 - read-write - - - IN_DSCR_TASK_OVF_CH3_INT_ENA - The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. - 9 - 1 - read-write - - - - - IN_INT_ST_CH3 - RX CH3 interrupt st register - 0x80C - 0x20 - - - IN_DONE_CH3_INT_ST - The raw interrupt status bit for the IN_DONE_CH_INT interrupt. - 0 - 1 - read-only - - - IN_SUC_EOF_CH3_INT_ST - The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. - 1 - 1 - read-only - - - IN_ERR_EOF_CH3_INT_ST - The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. - 2 - 1 - read-only - - - IN_DSCR_ERR_CH3_INT_ST - The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. - 3 - 1 - read-only - - - INFIFO_OVF_L1_CH3_INT_ST - The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. - 4 - 1 - read-only - - - INFIFO_UDF_L1_CH3_INT_ST - The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. - 5 - 1 - read-only - - - INFIFO_OVF_L2_CH3_INT_ST - The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. - 6 - 1 - read-only - - - INFIFO_UDF_L2_CH3_INT_ST - The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. - 7 - 1 - read-only - - - IN_DSCR_EMPTY_CH3_INT_ST - The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. - 8 - 1 - read-only - - - IN_DSCR_TASK_OVF_CH3_INT_ST - The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. - 9 - 1 - read-only - - - - - IN_INT_CLR_CH3 - RX CH3 interrupt clr register - 0x810 - 0x20 - - - IN_DONE_CH3_INT_CLR - Set this bit to clear the IN_DONE_CH_INT interrupt. - 0 - 1 - write-only - - - IN_SUC_EOF_CH3_INT_CLR - Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. - 1 - 1 - write-only - - - IN_ERR_EOF_CH3_INT_CLR - Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. - 2 - 1 - write-only - - - IN_DSCR_ERR_CH3_INT_CLR - Set this bit to clear the INDSCR_ERR_CH_INT interrupt. - 3 - 1 - write-only - - - INFIFO_OVF_L1_CH3_INT_CLR - Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. - 4 - 1 - write-only - - - INFIFO_UDF_L1_CH3_INT_CLR - Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. - 5 - 1 - write-only - - - INFIFO_OVF_L2_CH3_INT_CLR - Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. - 6 - 1 - write-only - - - INFIFO_UDF_L2_CH3_INT_CLR - Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. - 7 - 1 - write-only - - - IN_DSCR_EMPTY_CH3_INT_CLR - Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. - 8 - 1 - write-only - - - IN_DSCR_TASK_OVF_CH3_INT_CLR - Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. - 9 - 1 - write-only - - - - - INFIFO_STATUS_CH3 - RX CH3 INFIFO status register - 0x814 - 0x20 - 0x00020082 - - - INFIFO_FULL_L2_CH3 - Rx FIFO full signal for Rx channel. - 0 - 1 - read-only - - - INFIFO_EMPTY_L2_CH3 - Rx FIFO empty signal for Rx channel. - 1 - 1 - read-only - - - INFIFO_CNT_L2_CH3 - The register stores the byte number of the data in Rx FIFO for Rx channel. - 2 - 4 - read-only - - - INFIFO_FULL_L1_CH3 - Tx FIFO full signal for Tx channel 1. - 6 - 1 - read-only - - - INFIFO_EMPTY_L1_CH3 - Tx FIFO empty signal for Tx channel 1. - 7 - 1 - read-only - - - INFIFO_CNT_L1_CH3 - The register stores the byte number of the data in Tx FIFO for Tx channel 1. - 8 - 5 - read-only - - - INFIFO_FULL_L3_CH3 - Tx FIFO full signal for Tx channel 1. - 16 - 1 - read-only - - - INFIFO_EMPTY_L3_CH3 - Tx FIFO empty signal for Tx channel 1. - 17 - 1 - read-only - - - INFIFO_CNT_L3_CH3 - The register stores the byte number of the data in Tx FIFO for Tx channel 1. - 18 - 2 - read-only - - - - - IN_POP_CH3 - RX CH3 INFIFO pop register - 0x818 - 0x20 - 0x00000400 - - - INFIFO_RDATA_CH3 - This register stores the data popping from DMA Rx FIFO. - 0 - 11 - read-only - - - INFIFO_POP_CH3 - Set this bit to pop data from DMA Rx FIFO. - 11 - 1 - read-write - - - - - IN_LINK_CONF_CH3 - RX CH3 in_link dscr ctrl register - 0x81C - 0x20 - 0x01100000 - - - INLINK_AUTO_RET_CH3 - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data. - 20 - 1 - read-write - - - INLINK_STOP_CH3 - Set this bit to stop dealing with the inlink descriptors. - 21 - 1 - read-write - - - INLINK_START_CH3 - Set this bit to start dealing with the inlink descriptors. - 22 - 1 - read-write - - - INLINK_RESTART_CH3 - Set this bit to mount a new inlink descriptor. - 23 - 1 - read-write - - - INLINK_PARK_CH3 - 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. - 24 - 1 - read-only - - - - - IN_LINK_ADDR_CH3 - RX CH3 in_link dscr addr register - 0x820 - 0x20 - - - INLINK_ADDR_CH3 - This register stores the first inlink descriptor's address. - 0 - 32 - read-write - - - - - IN_STATE_CH3 - RX CH3 state register - 0x824 - 0x20 - 0x00800000 - - - INLINK_DSCR_ADDR_CH3 - This register stores the current inlink descriptor's address. - 0 - 18 - read-only - - - IN_DSCR_STATE_CH3 - This register stores the current descriptor state machine state. - 18 - 2 - read-only - - - IN_STATE_CH3 - This register stores the current control module state machine state. - 20 - 3 - read-only - - - IN_RESET_AVAIL_CH3 - This register indicate that if the channel reset is safety. - 23 - 1 - read-only - - - - - IN_SUC_EOF_DES_ADDR_CH3 - RX CH3 eof des addr register - 0x828 - 0x20 - - - IN_SUC_EOF_DES_ADDR_CH3 - This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. - 0 - 32 - read-only - - - - - IN_ERR_EOF_DES_ADDR_CH3 - RX CH3 err eof des addr register - 0x82C - 0x20 - - - IN_ERR_EOF_DES_ADDR_CH3 - This register stores the address of the inlink descriptor when there are some errors in current receiving data. - 0 - 32 - read-only - - - - - IN_DSCR_CH3 - RX CH3 next dscr addr register - 0x830 - 0x20 - - - INLINK_DSCR_CH3 - The address of the next inlink descriptor address x. - 0 - 32 - read-only - - - - - IN_DSCR_BF0_CH3 - RX CH3 last dscr addr register - 0x834 - 0x20 - - - INLINK_DSCR_BF0_CH3 - The address of the last inlink descriptor's next address x-1. - 0 - 32 - read-only - - - - - IN_DSCR_BF1_CH3 - RX CH3 second-to-last dscr addr register - 0x838 - 0x20 - - - INLINK_DSCR_BF1_CH3 - The address of the second-to-last inlink descriptor's next address x-2. - 0 - 32 - read-only - - - - - IN_ARB_CH3 - RX CH3 arb register - 0x840 - 0x20 - 0x00000041 - - - IN_ARB_TOKEN_NUM_CH3 - Set the max number of token count of arbiter - 0 - 4 - read-write - - - INTER_IN_ARB_PRIORITY_CH3 - Set the priority of channel - 6 - 3 - read-write - - - - - IN_ETM_CONF_CH3 - RX CH3 ETM config register - 0x848 - 0x20 - 0x00000004 - - - IN_ETM_EN_CH3 - Set this bit to 1 to enable ETM task function - 0 - 1 - read-write - - - IN_ETM_LOOP_EN_CH3 - when this bit is 1, dscr can be processed after receiving a task - 1 - 1 - read-write - - - IN_DSCR_TASK_MAK_CH3 - ETM dscr_ready maximum cache numbers - 2 - 2 - read-write - - - - - IN_FIFO_CNT_CH3 - rx CH3 fifo cnt register - 0x880 - 0x20 - - - IN_CMDFIFO_INFIFO_CNT_CH3 - only for debug - 0 - 10 - read-only - - - - - IN_POP_DATA_CNT_CH3 - rx CH3 pop data cnt register - 0x884 - 0x20 - 0x00000007 - - - IN_CMDFIFO_POP_DATA_CNT_CH3 - only for debug - 0 - 8 - read-only - - - - - IN_XADDR_CH3 - rx CH3 xaddr register - 0x888 - 0x20 - - - IN_CMDFIFO_XADDR_CH3 - only for debug - 0 - 32 - read-only - - - - - IN_BUF_HB_RCV_CH3 - rx CH3 buf len hb rcv register - 0x88C - 0x20 - - - IN_CMDFIFO_BUF_HB_RCV_CH3 - only for debug - 0 - 29 - read-only - - - - - IN_CONF0_CH4 - RX CH4 config0 register - 0x900 - 0x20 - - - INDSCR_BURST_EN_CH4 - Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor when accessing SRAM. - 2 - 1 - read-write - - - IN_ECC_AES_EN_CH4 - When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned. - 3 - 1 - read-write - - - IN_CHECK_OWNER_CH4 - Set this bit to enable checking the owner attribute of the link descriptor. - 4 - 1 - read-write - - - IN_MEM_BURST_LENGTH_CH4 - Block size of Rx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes - 6 - 3 - read-write - - - IN_PAGE_BOUND_EN_CH4 - Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length - 12 - 1 - read-write - - - IN_RST_CH4 - Write 1 then write 0 to this bit to reset Rx channel - 24 - 1 - read-write - - - IN_CMD_DISABLE_CH4 - Write 1 before reset and write 0 after reset - 25 - 1 - read-write - - - IN_ARB_WEIGHT_OPT_DIS_CH4 - Set this bit to 1 to disable arbiter optimum weight function. - 26 - 1 - read-write - - - - - IN_INT_RAW_CH4 - RX CH4 interrupt raw register - 0x904 - 0x20 - - - IN_DONE_CH4_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 1. - 0 - 1 - read-write - - - IN_SUC_EOF_CH4_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1. - 1 - 1 - read-write - - - IN_ERR_EOF_CH4_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and data error is detected - 2 - 1 - read-write - - - IN_DSCR_ERR_CH4_INT_RAW - The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 1. - 3 - 1 - read-write - - - INFIFO_OVF_L1_CH4_INT_RAW - This raw interrupt bit turns to high level when fifo of Rx channel is overflow. - 4 - 1 - read-write - - - INFIFO_UDF_L1_CH4_INT_RAW - This raw interrupt bit turns to high level when fifo of Rx channel is underflow. - 5 - 1 - read-write - - - INFIFO_OVF_L2_CH4_INT_RAW - This raw interrupt bit turns to high level when fifo of Rx channel is overflow. - 6 - 1 - read-write - - - INFIFO_UDF_L2_CH4_INT_RAW - This raw interrupt bit turns to high level when fifo of Rx channel is underflow. - 7 - 1 - read-write - - - IN_DSCR_EMPTY_CH4_INT_RAW - The raw interrupt bit turns to high level when the last descriptor is done but fifo also remain data. - 8 - 1 - read-write - - - IN_DSCR_TASK_OVF_CH4_INT_RAW - The raw interrupt bit turns to high level when dscr ready task fifo is overflow. - 9 - 1 - read-write - - - - - IN_INT_ENA_CH4 - RX CH4 interrupt ena register - 0x908 - 0x20 - - - IN_DONE_CH4_INT_ENA - The interrupt enable bit for the IN_DONE_CH_INT interrupt. - 0 - 1 - read-write - - - IN_SUC_EOF_CH4_INT_ENA - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. - 1 - 1 - read-write - - - IN_ERR_EOF_CH4_INT_ENA - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. - 2 - 1 - read-write - - - IN_DSCR_ERR_CH4_INT_ENA - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. - 3 - 1 - read-write - - - INFIFO_OVF_L1_CH4_INT_ENA - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. - 4 - 1 - read-write - - - INFIFO_UDF_L1_CH4_INT_ENA - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. - 5 - 1 - read-write - - - INFIFO_OVF_L2_CH4_INT_ENA - The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. - 6 - 1 - read-write - - - INFIFO_UDF_L2_CH4_INT_ENA - The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. - 7 - 1 - read-write - - - IN_DSCR_EMPTY_CH4_INT_ENA - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. - 8 - 1 - read-write - - - IN_DSCR_TASK_OVF_CH4_INT_ENA - The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. - 9 - 1 - read-write - - - - - IN_INT_ST_CH4 - RX CH4 interrupt st register - 0x90C - 0x20 - - - IN_DONE_CH4_INT_ST - The raw interrupt status bit for the IN_DONE_CH_INT interrupt. - 0 - 1 - read-only - - - IN_SUC_EOF_CH4_INT_ST - The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. - 1 - 1 - read-only - - - IN_ERR_EOF_CH4_INT_ST - The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. - 2 - 1 - read-only - - - IN_DSCR_ERR_CH4_INT_ST - The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. - 3 - 1 - read-only - - - INFIFO_OVF_L1_CH4_INT_ST - The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. - 4 - 1 - read-only - - - INFIFO_UDF_L1_CH4_INT_ST - The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. - 5 - 1 - read-only - - - INFIFO_OVF_L2_CH4_INT_ST - The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. - 6 - 1 - read-only - - - INFIFO_UDF_L2_CH4_INT_ST - The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. - 7 - 1 - read-only - - - IN_DSCR_EMPTY_CH4_INT_ST - The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. - 8 - 1 - read-only - - - IN_DSCR_TASK_OVF_CH4_INT_ST - The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. - 9 - 1 - read-only - - - - - IN_INT_CLR_CH4 - RX CH4 interrupt clr register - 0x910 - 0x20 - - - IN_DONE_CH4_INT_CLR - Set this bit to clear the IN_DONE_CH_INT interrupt. - 0 - 1 - write-only - - - IN_SUC_EOF_CH4_INT_CLR - Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. - 1 - 1 - write-only - - - IN_ERR_EOF_CH4_INT_CLR - Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. - 2 - 1 - write-only - - - IN_DSCR_ERR_CH4_INT_CLR - Set this bit to clear the INDSCR_ERR_CH_INT interrupt. - 3 - 1 - write-only - - - INFIFO_OVF_L1_CH4_INT_CLR - Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. - 4 - 1 - write-only - - - INFIFO_UDF_L1_CH4_INT_CLR - Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. - 5 - 1 - write-only - - - INFIFO_OVF_L2_CH4_INT_CLR - Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. - 6 - 1 - write-only - - - INFIFO_UDF_L2_CH4_INT_CLR - Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. - 7 - 1 - write-only - - - IN_DSCR_EMPTY_CH4_INT_CLR - Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. - 8 - 1 - write-only - - - IN_DSCR_TASK_OVF_CH4_INT_CLR - Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. - 9 - 1 - write-only - - - - - INFIFO_STATUS_CH4 - RX CH4 INFIFO status register - 0x914 - 0x20 - 0x00020082 - - - INFIFO_FULL_L2_CH4 - Rx FIFO full signal for Rx channel. - 0 - 1 - read-only - - - INFIFO_EMPTY_L2_CH4 - Rx FIFO empty signal for Rx channel. - 1 - 1 - read-only - - - INFIFO_CNT_L2_CH4 - The register stores the byte number of the data in Rx FIFO for Rx channel. - 2 - 4 - read-only - - - INFIFO_FULL_L1_CH4 - Tx FIFO full signal for Tx channel 1. - 6 - 1 - read-only - - - INFIFO_EMPTY_L1_CH4 - Tx FIFO empty signal for Tx channel 1. - 7 - 1 - read-only - - - INFIFO_CNT_L1_CH4 - The register stores the byte number of the data in Tx FIFO for Tx channel 1. - 8 - 5 - read-only - - - INFIFO_FULL_L3_CH4 - Tx FIFO full signal for Tx channel 1. - 16 - 1 - read-only - - - INFIFO_EMPTY_L3_CH4 - Tx FIFO empty signal for Tx channel 1. - 17 - 1 - read-only - - - INFIFO_CNT_L3_CH4 - The register stores the byte number of the data in Tx FIFO for Tx channel 1. - 18 - 2 - read-only - - - - - IN_POP_CH4 - RX CH4 INFIFO pop register - 0x918 - 0x20 - 0x00000400 - - - INFIFO_RDATA_CH4 - This register stores the data popping from DMA Rx FIFO. - 0 - 11 - read-only - - - INFIFO_POP_CH4 - Set this bit to pop data from DMA Rx FIFO. - 11 - 1 - read-write - - - - - IN_LINK_CONF_CH4 - RX CH4 in_link dscr ctrl register - 0x91C - 0x20 - 0x01100000 - - - INLINK_AUTO_RET_CH4 - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data. - 20 - 1 - read-write - - - INLINK_STOP_CH4 - Set this bit to stop dealing with the inlink descriptors. - 21 - 1 - read-write - - - INLINK_START_CH4 - Set this bit to start dealing with the inlink descriptors. - 22 - 1 - read-write - - - INLINK_RESTART_CH4 - Set this bit to mount a new inlink descriptor. - 23 - 1 - read-write - - - INLINK_PARK_CH4 - 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. - 24 - 1 - read-only - - - - - IN_LINK_ADDR_CH4 - RX CH4 in_link dscr addr register - 0x920 - 0x20 - - - INLINK_ADDR_CH4 - This register stores the first inlink descriptor's address. - 0 - 32 - read-write - - - - - IN_STATE_CH4 - RX CH4 state register - 0x924 - 0x20 - 0x00800000 - - - INLINK_DSCR_ADDR_CH4 - This register stores the current inlink descriptor's address. - 0 - 18 - read-only - - - IN_DSCR_STATE_CH4 - This register stores the current descriptor state machine state. - 18 - 2 - read-only - - - IN_STATE_CH4 - This register stores the current control module state machine state. - 20 - 3 - read-only - - - IN_RESET_AVAIL_CH4 - This register indicate that if the channel reset is safety. - 23 - 1 - read-only - - - - - IN_SUC_EOF_DES_ADDR_CH4 - RX CH4 eof des addr register - 0x928 - 0x20 - - - IN_SUC_EOF_DES_ADDR_CH4 - This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. - 0 - 32 - read-only - - - - - IN_ERR_EOF_DES_ADDR_CH4 - RX CH4 err eof des addr register - 0x92C - 0x20 - - - IN_ERR_EOF_DES_ADDR_CH4 - This register stores the address of the inlink descriptor when there are some errors in current receiving data. - 0 - 32 - read-only - - - - - IN_DSCR_CH4 - RX CH4 next dscr addr register - 0x930 - 0x20 - - - INLINK_DSCR_CH4 - The address of the next inlink descriptor address x. - 0 - 32 - read-only - - - - - IN_DSCR_BF0_CH4 - RX CH4 last dscr addr register - 0x934 - 0x20 - - - INLINK_DSCR_BF0_CH4 - The address of the last inlink descriptor's next address x-1. - 0 - 32 - read-only - - - - - IN_DSCR_BF1_CH4 - RX CH4 second-to-last dscr addr register - 0x938 - 0x20 - - - INLINK_DSCR_BF1_CH4 - The address of the second-to-last inlink descriptor's next address x-2. - 0 - 32 - read-only - - - - - IN_ARB_CH4 - RX CH4 arb register - 0x940 - 0x20 - 0x00000051 - - - IN_ARB_TOKEN_NUM_CH4 - Set the max number of token count of arbiter - 0 - 4 - read-write - - - EXTER_IN_ARB_PRIORITY_CH4 - Set the priority of channel - 4 - 2 - read-write - - - INTER_IN_ARB_PRIORITY_CH4 - Set the priority of channel - 6 - 3 - read-write - - - - - IN_ETM_CONF_CH4 - RX CH4 ETM config register - 0x948 - 0x20 - 0x00000004 - - - IN_ETM_EN_CH4 - Set this bit to 1 to enable ETM task function - 0 - 1 - read-write - - - IN_ETM_LOOP_EN_CH4 - when this bit is 1, dscr can be processed after receiving a task - 1 - 1 - read-write - - - IN_DSCR_TASK_MAK_CH4 - ETM dscr_ready maximum cache numbers - 2 - 2 - read-write - - - - - IN_FIFO_CNT_CH4 - rx CH4 fifo cnt register - 0x980 - 0x20 - - - IN_CMDFIFO_INFIFO_CNT_CH4 - only for debug - 0 - 10 - read-only - - - - - IN_POP_DATA_CNT_CH4 - rx CH4 pop data cnt register - 0x984 - 0x20 - 0x00000007 - - - IN_CMDFIFO_POP_DATA_CNT_CH4 - only for debug - 0 - 8 - read-only - - - - - IN_XADDR_CH4 - rx CH4 xaddr register - 0x988 - 0x20 - - - IN_CMDFIFO_XADDR_CH4 - only for debug - 0 - 32 - read-only - - - - - IN_BUF_HB_RCV_CH4 - rx CH4 buf len hb rcv register - 0x98C - 0x20 - - - IN_CMDFIFO_BUF_HB_RCV_CH4 - only for debug - 0 - 29 - read-only - - - - - IN_CONF0_CH5 - RX CH5 config0 register - 0xA00 - 0x20 - - - IN_ECC_AES_EN_CH5 - When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned. - 3 - 1 - read-write - - - IN_MEM_BURST_LENGTH_CH5 - Block size of Rx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes - 6 - 3 - read-write - - - IN_PAGE_BOUND_EN_CH5 - Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length - 12 - 1 - read-write - - - IN_RST_CH5 - Write 1 then write 0 to this bit to reset Rx channel - 24 - 1 - read-write - - - IN_CMD_DISABLE_CH5 - Write 1 before reset and write 0 after reset - 25 - 1 - read-write - - - - - IN_CONF1_CH5 - RX CH5 config1 register - 0xA04 - 0x20 - - - BLOCK_START_ADDR_CH5 - RX Channel 5 destination start address - 0 - 32 - read-write - - - - - IN_CONF2_CH5 - RX CH5 config2 register - 0xA08 - 0x20 - 0x3C007800 - - - BLOCK_ROW_LENGTH_12LINE_CH5 - The number of bytes contained in a row block 12line in RX channel 5 - 0 - 16 - read-write - - - BLOCK_ROW_LENGTH_4LINE_CH5 - The number of bytes contained in a row block 4line in RX channel 5 - 16 - 16 - read-write - - - - - IN_CONF3_CH5 - RX CH5 config3 register - 0xA0C - 0x20 - 0x00200100 - - - BLOCK_LENGTH_12LINE_CH5 - The number of bytes contained in a block 12line - 0 - 14 - read-write - - - BLOCK_LENGTH_4LINE_CH5 - The number of bytes contained in a block 4line - 14 - 14 - read-write - - - - - IN_INT_RAW_CH5 - RX CH5 interrupt raw register - 0xA10 - 0x20 - - - IN_DONE_CH5_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 1. - 0 - 1 - read-write - - - IN_SUC_EOF_CH5_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1. - 1 - 1 - read-write - - - INFIFO_OVF_L1_CH5_INT_RAW - This raw interrupt bit turns to high level when fifo of Rx channel is overflow. - 2 - 1 - read-write - - - INFIFO_UDF_L1_CH5_INT_RAW - This raw interrupt bit turns to high level when fifo of Rx channel is underflow. - 3 - 1 - read-write - - - FETCH_MB_COL_CNT_OVF_CH5_INT_RAW - This raw interrupt bit turns to high level when fifo of Rx channel is underflow. - 4 - 1 - read-write - - - - - IN_INT_ENA_CH5 - RX CH5 interrupt ena register - 0xA14 - 0x20 - - - IN_DONE_CH5_INT_ENA - The interrupt enable bit for the IN_DONE_CH_INT interrupt. - 0 - 1 - read-write - - - IN_SUC_EOF_CH5_INT_ENA - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. - 1 - 1 - read-write - - - INFIFO_OVF_L1_CH5_INT_ENA - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. - 2 - 1 - read-write - - - INFIFO_UDF_L1_CH5_INT_ENA - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. - 3 - 1 - read-write - - - FETCH_MB_COL_CNT_OVF_CH5_INT_ENA - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. - 4 - 1 - read-write - - - - - IN_INT_ST_CH5 - RX CH5 interrupt st register - 0xA18 - 0x20 - - - IN_DONE_CH5_INT_ST - The raw interrupt status bit for the IN_DONE_CH_INT interrupt. - 0 - 1 - read-only - - - IN_SUC_EOF_CH5_INT_ST - The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. - 1 - 1 - read-only - - - INFIFO_OVF_L1_CH5_INT_ST - The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. - 2 - 1 - read-only - - - INFIFO_UDF_L1_CH5_INT_ST - The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. - 3 - 1 - read-only - - - FETCH_MB_COL_CNT_OVF_CH5_INT_ST - The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. - 4 - 1 - read-only - - - - - IN_INT_CLR_CH5 - RX CH5 interrupt clr register - 0xA1C - 0x20 - - - IN_DONE_CH5_INT_CLR - Set this bit to clear the IN_DONE_CH_INT interrupt. - 0 - 1 - write-only - - - IN_SUC_EOF_CH5_INT_CLR - Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. - 1 - 1 - write-only - - - INFIFO_OVF_L1_CH5_INT_CLR - Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. - 2 - 1 - write-only - - - INFIFO_UDF_L1_CH5_INT_CLR - Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. - 3 - 1 - write-only - - - FETCH_MB_COL_CNT_OVF_CH5_INT_CLR - Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. - 4 - 1 - write-only - - - - - INFIFO_STATUS_CH5 - RX CH5 INFIFO status register - 0xA20 - 0x20 - 0x00000002 - - - INFIFO_FULL_L1_CH5 - Tx FIFO full signal for Tx channel 1. - 0 - 1 - read-only - - - INFIFO_EMPTY_L1_CH5 - Tx FIFO empty signal for Tx channel 1. - 1 - 1 - read-only - - - INFIFO_CNT_L1_CH5 - The register stores the byte number of the data in Tx FIFO for Tx channel 1. - 2 - 5 - read-only - - - - - IN_POP_CH5 - RX CH5 INFIFO pop register - 0xA24 - 0x20 - 0x00000400 - - - INFIFO_RDATA_CH5 - This register stores the data popping from DMA Rx FIFO. - 0 - 11 - read-only - - - INFIFO_POP_CH5 - Set this bit to pop data from DMA Rx FIFO. - 11 - 1 - read-write - - - - - IN_STATE_CH5 - RX CH5 state register - 0xA28 - 0x20 - 0x00000008 - - - IN_STATE_CH5 - This register stores the current control module state machine state. - 0 - 3 - read-only - - - IN_RESET_AVAIL_CH5 - This register indicate that if the channel reset is safety. - 3 - 1 - read-only - - - - - IN_ARB_CH5 - RX CH5 arb register - 0xA40 - 0x20 - 0x00000041 - - - IN_ARB_TOKEN_NUM_CH5 - Set the max number of token count of arbiter - 0 - 4 - read-write - - - INTER_IN_ARB_PRIORITY_CH5 - Set the priority of channel - 6 - 3 - read-write - - - - - IN_FIFO_CNT_CH5 - rx CH5 fifo cnt register - 0xA80 - 0x20 - - - IN_CMDFIFO_INFIFO_CNT_CH5 - only for debug - 0 - 10 - read-only - - - - - IN_POP_DATA_CNT_CH5 - rx CH5 pop data cnt register - 0xA84 - 0x20 - 0x000000FF - - - IN_CMDFIFO_POP_DATA_CNT_CH5 - only for debug - 0 - 8 - read-only - - - - - IN_XADDR_CH5 - rx CH5 xaddr register - 0xA88 - 0x20 - - - IN_CMDFIFO_XADDR_CH5 - only for debug - 0 - 32 - read-only - - - - - IN_BUF_HB_RCV_CH5 - rx CH5 buf len hb rcv register - 0xA8C - 0x20 - - - IN_CMDFIFO_BUF_HB_RCV_CH5 - only for debug - 0 - 29 - read-only - - - - - INTER_AXI_ERR - inter memory axi err register - 0xB00 - 0x20 - - - INTER_RID_ERR_CNT - AXI read id err cnt - 0 - 4 - read-only - - - INTER_RRESP_ERR_CNT - AXI read resp err cnt - 4 - 4 - read-only - - - INTER_WRESP_ERR_CNT - AXI write resp err cnt - 8 - 4 - read-only - - - INTER_RD_FIFO_CNT - AXI read cmd fifo remain cmd count - 12 - 3 - read-only - - - INTER_RD_BAK_FIFO_CNT - AXI read backup cmd fifo remain cmd count - 15 - 4 - read-only - - - INTER_WR_FIFO_CNT - AXI write cmd fifo remain cmd count - 19 - 3 - read-only - - - INTER_WR_BAK_FIFO_CNT - AXI write backup cmd fifo remain cmd count - 22 - 4 - read-only - - - - - EXTER_AXI_ERR - exter memory axi err register - 0xB04 - 0x20 - - - EXTER_RID_ERR_CNT - AXI read id err cnt - 0 - 4 - read-only - - - EXTER_RRESP_ERR_CNT - AXI read resp err cnt - 4 - 4 - read-only - - - EXTER_WRESP_ERR_CNT - AXI write resp err cnt - 8 - 4 - read-only - - - EXTER_RD_FIFO_CNT - AXI read cmd fifo remain cmd count - 12 - 3 - read-only - - - EXTER_RD_BAK_FIFO_CNT - AXI read backup cmd fifo remain cmd count - 15 - 4 - read-only - - - EXTER_WR_FIFO_CNT - AXI write cmd fifo remain cmd count - 19 - 3 - read-only - - - EXTER_WR_BAK_FIFO_CNT - AXI write backup cmd fifo remain cmd count - 22 - 4 - read-only - - - - - RST_CONF - axi reset config register - 0xB08 - 0x20 - - - INTER_AXIM_RD_RST - Write 1 then write 0 to this bit to reset axi master read data FIFO. - 0 - 1 - read-write - - - INTER_AXIM_WR_RST - Write 1 then write 0 to this bit to reset axi master write data FIFO. - 1 - 1 - read-write - - - EXTER_AXIM_RD_RST - Write 1 then write 0 to this bit to reset axi master read data FIFO. - 2 - 1 - read-write - - - EXTER_AXIM_WR_RST - Write 1 then write 0 to this bit to reset axi master write data FIFO. - 3 - 1 - read-write - - - CLK_EN - 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers. - 4 - 1 - read-write - - - - - INTER_MEM_START_ADDR0 - Start address of inter memory range0 register - 0xB0C - 0x20 - 0x30100000 - - - ACCESS_INTER_MEM_START_ADDR0 - The start address of accessible address space. - 0 - 32 - read-write - - - - - INTER_MEM_END_ADDR0 - end address of inter memory range0 register - 0xB10 - 0x20 - 0x8FFFFFFF - - - ACCESS_INTER_MEM_END_ADDR0 - The end address of accessible address space. The access address beyond this range would lead to descriptor error. - 0 - 32 - read-write - - - - - INTER_MEM_START_ADDR1 - Start address of inter memory range1 register - 0xB14 - 0x20 - 0x30100000 - - - ACCESS_INTER_MEM_START_ADDR1 - The start address of accessible address space. - 0 - 32 - read-write - - - - - INTER_MEM_END_ADDR1 - end address of inter memory range1 register - 0xB18 - 0x20 - 0x8FFFFFFF - - - ACCESS_INTER_MEM_END_ADDR1 - The end address of accessible address space. The access address beyond this range would lead to descriptor error. - 0 - 32 - read-write - - - - - EXTER_MEM_START_ADDR0 - Start address of exter memory range0 register - 0xB20 - 0x20 - 0x30100000 - - - ACCESS_EXTER_MEM_START_ADDR0 - The start address of accessible address space. - 0 - 32 - read-write - - - - - EXTER_MEM_END_ADDR0 - end address of exter memory range0 register - 0xB24 - 0x20 - 0x8FFFFFFF - - - ACCESS_EXTER_MEM_END_ADDR0 - The end address of accessible address space. The access address beyond this range would lead to descriptor error. - 0 - 32 - read-write - - - - - EXTER_MEM_START_ADDR1 - Start address of exter memory range1 register - 0xB28 - 0x20 - 0x30100000 - - - ACCESS_EXTER_MEM_START_ADDR1 - The start address of accessible address space. - 0 - 32 - read-write - - - - - EXTER_MEM_END_ADDR1 - end address of exter memory range1 register - 0xB2C - 0x20 - 0x8FFFFFFF - - - ACCESS_EXTER_MEM_END_ADDR1 - The end address of accessible address space. The access address beyond this range would lead to descriptor error. - 0 - 32 - read-write - - - - - OUT_ARB_CONFIG - reserved - 0xB30 - 0x20 - - - OUT_ARB_TIMEOUT_NUM - Set the max number of timeout count of arbiter - 0 - 16 - read-write - - - OUT_WEIGHT_EN - reserved - 16 - 1 - read-write - - - - - IN_ARB_CONFIG - reserved - 0xB34 - 0x20 - - - IN_ARB_TIMEOUT_NUM - Set the max number of timeout count of arbiter - 0 - 16 - read-write - - - IN_WEIGHT_EN - reserved - 16 - 1 - read-write - - - - - DATE - reserved - 0xB3C - 0x20 - 0x20230403 - - - DATE - register version. - 0 - 32 - read-write - - - - - COUNTER_RST - counter reset register - 0xB50 - 0x20 - - - RX_CH0_EXTER_COUNTER_RST - Write 1 then write 0 to this bit to reset rx ch0 counter. - 0 - 1 - read-write - - - RX_CH1_EXTER_COUNTER_RST - Write 1 then write 0 to this bit to reset rx ch1 counter. - 1 - 1 - read-write - - - RX_CH2_INTER_COUNTER_RST - Write 1 then write 0 to this bit to reset rx ch2 counter. - 2 - 1 - read-write - - - RX_CH5_INTER_COUNTER_RST - Write 1 then write 0 to this bit to reset rx ch5 counter. - 3 - 1 - read-write - - - - - RX_CH0_COUNTER - rx ch0 counter register - 0xB54 - 0x20 - - - RX_CH0_CNT - rx ch0 counter register - 0 - 23 - read-only - - - - - RX_CH1_COUNTER - rx ch1 counter register - 0xB58 - 0x20 - - - RX_CH1_CNT - rx ch1 counter register - 0 - 21 - read-only - - - - - RX_CH2_COUNTER - rx ch2 counter register - 0xB5C - 0x20 - - - RX_CH2_CNT - rx ch2 counter register - 0 - 11 - read-only - - - - - RX_CH5_COUNTER - rx ch5 counter register - 0xB60 - 0x20 - - - RX_CH5_CNT - rx ch5 counter register - 0 - 17 - read-only - - - - - - - HMAC - HMAC (Hash-based Message Authentication Code) Accelerator - HMAC - 0x50095000 - - 0x0 - 0xA4 - registers - - - - SET_START - Process control register 0. - 0x40 - 0x20 - - - SET_START - Start hmac operation. - 0 - 1 - write-only - - - - - SET_PARA_PURPOSE - Configure purpose. - 0x44 - 0x20 - - - PURPOSE_SET - Set hmac parameter purpose. - 0 - 4 - write-only - - - - - SET_PARA_KEY - Configure key. - 0x48 - 0x20 - - - KEY_SET - Set hmac parameter key. - 0 - 3 - write-only - - - - - SET_PARA_FINISH - Finish initial configuration. - 0x4C - 0x20 - - - SET_PARA_END - Finish hmac configuration. - 0 - 1 - write-only - - - - - SET_MESSAGE_ONE - Process control register 1. - 0x50 - 0x20 - - - SET_TEXT_ONE - Call SHA to calculate one message block. - 0 - 1 - write-only - - - - - SET_MESSAGE_ING - Process control register 2. - 0x54 - 0x20 - - - SET_TEXT_ING - Continue typical hmac. - 0 - 1 - write-only - - - - - SET_MESSAGE_END - Process control register 3. - 0x58 - 0x20 - - - SET_TEXT_END - Start hardware padding. - 0 - 1 - write-only - - - - - SET_RESULT_FINISH - Process control register 4. - 0x5C - 0x20 - - - SET_RESULT_END - After read result from upstream, then let hmac back to idle. - 0 - 1 - write-only - - - - - SET_INVALIDATE_JTAG - Invalidate register 0. - 0x60 - 0x20 - - - SET_INVALIDATE_JTAG - Clear result from hmac downstream JTAG. - 0 - 1 - write-only - - - - - SET_INVALIDATE_DS - Invalidate register 1. - 0x64 - 0x20 - - - SET_INVALIDATE_DS - Clear result from hmac downstream DS. - 0 - 1 - write-only - - - - - QUERY_ERROR - Error register. - 0x68 - 0x20 - - - QUERY_CHECK - Hmac configuration state. 0: key are agree with purpose. 1: error - 0 - 1 - read-only - - - - - QUERY_BUSY - Busy register. - 0x6C - 0x20 - - - BUSY_STATE - Hmac state. 1'b0: idle. 1'b1: busy - 0 - 1 - read-only - - - - - 16 - 0x4 - WR_MESSAGE_MEM[%s] - Message block memory. - 0x80 - 0x20 - - - 8 - 0x4 - RD_RESULT_MEM[%s] - Result from upstream. - 0xC0 - 0x20 - - - SET_MESSAGE_PAD - Process control register 5. - 0xF0 - 0x20 - - - SET_TEXT_PAD - Start software padding. - 0 - 1 - write-only - - - - - ONE_BLOCK - Process control register 6. - 0xF4 - 0x20 - - - SET_ONE_BLOCK - Don't have to do padding. - 0 - 1 - write-only - - - - - SOFT_JTAG_CTRL - Jtag register 0. - 0xF8 - 0x20 - - - SOFT_JTAG_CTRL - Turn on JTAG verification. - 0 - 1 - write-only - - - - - WR_JTAG - Jtag register 1. - 0xFC - 0x20 - - - WR_JTAG - 32-bit of key to be compared. - 0 - 32 - write-only - - - - - DATE - Date register. - 0x1FC - 0x20 - 0x20200618 - - - DATE - Hmac date information/ hmac version information. - 0 - 30 - read-write - - - - - - - HP_SYS - High-Power System - HP_SYS - 0x500E5000 - - 0x0 - 0x16C - registers - - - HP_SYS - 110 - - - - VER_DATE - NA - 0x0 - 0x20 - 0x20230519 - - - REG_VER_DATE - NA - 0 - 32 - read-write - - - - - CLK_EN - NA - 0x4 - 0x20 - - - REG_CLK_EN - NA - 0 - 1 - read-write - - - - - CPU_INTR_FROM_CPU_0 - NA - 0x10 - 0x20 - - - CPU_INTR_FROM_CPU_0 - set 1 will triger a interrupt - 0 - 1 - read-write - - - - - CPU_INTR_FROM_CPU_1 - NA - 0x14 - 0x20 - - - CPU_INTR_FROM_CPU_1 - set 1 will triger a interrupt - 0 - 1 - read-write - - - - - CPU_INTR_FROM_CPU_2 - NA - 0x18 - 0x20 - - - CPU_INTR_FROM_CPU_2 - set 1 will triger a interrupt - 0 - 1 - read-write - - - - - CPU_INTR_FROM_CPU_3 - NA - 0x1C - 0x20 - - - CPU_INTR_FROM_CPU_3 - set 1 will triger a interrupt - 0 - 1 - read-write - - - - - CACHE_CLK_CONFIG - NA - 0x20 - 0x20 - 0x00000033 - - - REG_L2_CACHE_CLK_ON - l2 cahce clk enable - 0 - 1 - read-write - - - REG_L1_D_CACHE_CLK_ON - l1 dcahce clk enable - 1 - 1 - read-write - - - REG_L1_I1_CACHE_CLK_ON - l1 icahce1 clk enable - 4 - 1 - read-write - - - REG_L1_I0_CACHE_CLK_ON - l1 icahce0 clk enable - 5 - 1 - read-write - - - - - CACHE_RESET_CONFIG - NA - 0x24 - 0x20 - - - REG_L1_D_CACHE_RESET - set 1 to reset l1 dcahce - 1 - 1 - read-write - - - REG_L1_I1_CACHE_RESET - set 1 to reset l1 icahce1 - 4 - 1 - read-write - - - REG_L1_I0_CACHE_RESET - set 1 to reset l1 icahce0 - 5 - 1 - read-write - - - - - DMA_ADDR_CTRL - NA - 0x2C - 0x20 - - - REG_SYS_DMA_ADDR_SEL - 0 means dma access extmem use 8xxx_xxxx else use 4xxx_xxxx - 0 - 1 - read-write - - - - - TCM_RAM_WRR_CONFIG - NA - 0x34 - 0x20 - 0x826ED93F - - - REG_TCM_RAM_IBUS0_WT - weight value of ibus0 - 0 - 3 - read-write - - - REG_TCM_RAM_IBUS1_WT - weight value of ibus1 - 3 - 3 - read-write - - - REG_TCM_RAM_IBUS2_WT - weight value of ibus2 - 6 - 3 - read-write - - - REG_TCM_RAM_IBUS3_WT - weight value of ibus3 - 9 - 3 - read-write - - - REG_TCM_RAM_DBUS0_WT - weight value of dbus0 - 12 - 3 - read-write - - - REG_TCM_RAM_DBUS1_WT - weight value of dbus1 - 15 - 3 - read-write - - - REG_TCM_RAM_DBUS2_WT - weight value of dbus2 - 18 - 3 - read-write - - - REG_TCM_RAM_DBUS3_WT - weight value of dbus3 - 21 - 3 - read-write - - - REG_TCM_RAM_DMA_WT - weight value of dma - 24 - 3 - read-write - - - REG_TCM_RAM_WRR_HIGH - enable weighted round robin arbitration - 31 - 1 - read-write - - - - - TCM_SW_PARITY_BWE_MASK - NA - 0x38 - 0x20 - - - REG_TCM_SW_PARITY_BWE_MASK_CTRL - Set 1 to mask tcm bwe parity code bit - 0 - 1 - read-write - - - - - TCM_RAM_PWR_CTRL0 - NA - 0x3C - 0x20 - - - REG_HP_TCM_CLK_FORCE_ON - hp_tcm clk gatig force on - 0 - 1 - read-write - - - - - L2_ROM_PWR_CTRL0 - NA - 0x40 - 0x20 - - - REG_L2_ROM_CLK_FORCE_ON - l2_rom clk gating force on - 0 - 1 - read-write - - - - - PROBEA_CTRL - NA - 0x50 - 0x20 - - - REG_PROBE_A_MOD_SEL - Tihs field is used to selec probe_group from probe_group0 to probe_group15 for module's probe_out[31:0] in a mode - 0 - 16 - read-write - - - REG_PROBE_A_TOP_SEL - Tihs field is used to selec module's probe_out[31:0] as probe out in a mode - 16 - 8 - read-write - - - REG_PROBE_L_SEL - Tihs field is used to selec probe_out[31:16] - 24 - 2 - read-write - - - REG_PROBE_H_SEL - Tihs field is used to selec probe_out[31:16] - 26 - 2 - read-write - - - REG_PROBE_GLOBAL_EN - Set this bit to enable global debug probe in hp system. - 28 - 1 - read-write - - - - - PROBEB_CTRL - NA - 0x54 - 0x20 - - - REG_PROBE_B_MOD_SEL - Tihs field is used to selec probe_group from probe_group0 to probe_group15 for module's probe_out[31:0] in b mode. - 0 - 16 - read-write - - - REG_PROBE_B_TOP_SEL - Tihs field is used to select module's probe_out[31:0] as probe_out in b mode - 16 - 8 - read-write - - - REG_PROBE_B_EN - Set this bit to enable b mode for debug probe. 1: b mode, 0: a mode. - 24 - 1 - read-write - - - - - PROBE_OUT - NA - 0x5C - 0x20 - - - REG_PROBE_TOP_OUT - NA - 0 - 32 - read-only - - - - - L2_MEM_RAM_PWR_CTRL0 - NA - 0x60 - 0x20 - - - REG_L2_MEM_CLK_FORCE_ON - l2ram clk_gating force on - 0 - 1 - read-write - - - - - CPU_CORESTALLED_ST - NA - 0x64 - 0x20 - - - REG_CORE0_CORESTALLED_ST - hp core0 corestalled status - 0 - 1 - read-only - - - REG_CORE1_CORESTALLED_ST - hp core1 corestalled status - 1 - 1 - read-only - - - - - CRYPTO_CTRL - NA - 0x70 - 0x20 - - - REG_ENABLE_SPI_MANUAL_ENCRYPT - NA - 0 - 1 - read-write - - - REG_ENABLE_DOWNLOAD_DB_ENCRYPT - NA - 1 - 1 - read-write - - - REG_ENABLE_DOWNLOAD_G0CB_DECRYPT - NA - 2 - 1 - read-write - - - REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT - NA - 3 - 1 - read-write - - - - - GPIO_O_HOLD_CTRL0 - NA - 0x74 - 0x20 - - - REG_GPIO_0_HOLD_LOW - hold control for gpio47~16 - 0 - 32 - read-write - - - - - GPIO_O_HOLD_CTRL1 - NA - 0x78 - 0x20 - - - REG_GPIO_0_HOLD_HIGH - hold control for gpio56~48 - 0 - 9 - read-write - - - - - RDN_ECO_CS - NA - 0x7C - 0x20 - - - REG_HP_SYS_RDN_ECO_EN - NA - 0 - 1 - read-write - - - REG_HP_SYS_RDN_ECO_RESULT - NA - 1 - 1 - read-only - - - - - CACHE_APB_POSTW_EN - NA - 0x80 - 0x20 - - - REG_CACHE_APB_POSTW_EN - cache apb register interface post write enable, 1 will speed up write, but will take some time to update value to register - 0 - 1 - read-write - - - - - L2_MEM_SUBSIZE - NA - 0x84 - 0x20 - - - REG_L2_MEM_SUB_BLKSIZE - l2mem sub block size 00=>32 01=>64 10=>128 11=>256 - 0 - 2 - read-write - - - - - L2_MEM_INT_RAW - NA - 0x9C - 0x20 - - - REG_L2_MEM_ECC_ERR_INT_RAW - intr triggered when two bit error detected and corrected from ecc - 0 - 1 - read-write - - - REG_L2_MEM_EXCEED_ADDR_INT_RAW - intr triggered when access addr exceeds 0xff9ffff at bypass mode or exceeds 0xff80000 at l2cache 128kb mode or exceeds 0xff60000 at l2cache 256kb mode - 1 - 1 - read-write - - - REG_L2_MEM_ERR_RESP_INT_RAW - intr triggered when err response occurs - 2 - 1 - read-write - - - - - L2_MEM_INT_ST - NA - 0xA0 - 0x20 - - - REG_L2_MEM_ECC_ERR_INT_ST - NA - 0 - 1 - read-only - - - REG_L2_MEM_EXCEED_ADDR_INT_ST - NA - 1 - 1 - read-only - - - REG_L2_MEM_ERR_RESP_INT_ST - NA - 2 - 1 - read-only - - - - - L2_MEM_INT_ENA - NA - 0xA4 - 0x20 - - - REG_L2_MEM_ECC_ERR_INT_ENA - NA - 0 - 1 - read-write - - - REG_L2_MEM_EXCEED_ADDR_INT_ENA - NA - 1 - 1 - read-write - - - REG_L2_MEM_ERR_RESP_INT_ENA - NA - 2 - 1 - read-write - - - - - L2_MEM_INT_CLR - NA - 0xA8 - 0x20 - - - REG_L2_MEM_ECC_ERR_INT_CLR - NA - 0 - 1 - write-only - - - REG_L2_MEM_EXCEED_ADDR_INT_CLR - NA - 1 - 1 - write-only - - - REG_L2_MEM_ERR_RESP_INT_CLR - NA - 2 - 1 - write-only - - - - - L2_MEM_L2_RAM_ECC - NA - 0xAC - 0x20 - - - REG_L2_RAM_UNIT0_ECC_EN - NA - 0 - 1 - read-write - - - REG_L2_RAM_UNIT1_ECC_EN - NA - 1 - 1 - read-write - - - REG_L2_RAM_UNIT2_ECC_EN - NA - 2 - 1 - read-write - - - REG_L2_RAM_UNIT3_ECC_EN - NA - 3 - 1 - read-write - - - REG_L2_RAM_UNIT4_ECC_EN - NA - 4 - 1 - read-write - - - REG_L2_RAM_UNIT5_ECC_EN - NA - 5 - 1 - read-write - - - - - L2_MEM_INT_RECORD0 - NA - 0xB0 - 0x20 - - - REG_L2_MEM_EXCEED_ADDR_INT_ADDR - NA - 0 - 21 - read-only - - - REG_L2_MEM_EXCEED_ADDR_INT_WE - NA - 21 - 1 - read-only - - - REG_L2_MEM_EXCEED_ADDR_INT_MASTER - NA - 22 - 3 - read-only - - - - - L2_MEM_INT_RECORD1 - NA - 0xB4 - 0x20 - - - REG_L2_MEM_ECC_ERR_INT_ADDR - NA - 0 - 15 - read-only - - - REG_L2_MEM_ECC_ONE_BIT_ERR - NA - 15 - 1 - read-only - - - REG_L2_MEM_ECC_TWO_BIT_ERR - NA - 16 - 1 - read-only - - - REG_L2_MEM_ECC_ERR_BIT - NA - 17 - 9 - read-only - - - REG_L2_CACHE_ERR_BANK - NA - 26 - 1 - read-only - - - - - L2_MEM_L2_CACHE_ECC - NA - 0xC4 - 0x20 - - - REG_L2_CACHE_ECC_EN - NA - 0 - 1 - read-write - - - - - L1CACHE_BUS0_ID - NA - 0xC8 - 0x20 - - - REG_L1_CACHE_BUS0_ID - NA - 0 - 4 - read-write - - - - - L1CACHE_BUS1_ID - NA - 0xCC - 0x20 - - - REG_L1_CACHE_BUS1_ID - NA - 0 - 4 - read-write - - - - - L2_MEM_RDN_ECO_CS - NA - 0xD8 - 0x20 - - - REG_L2_MEM_RDN_ECO_EN - NA - 0 - 1 - read-write - - - REG_L2_MEM_RDN_ECO_RESULT - NA - 1 - 1 - read-only - - - - - L2_MEM_RDN_ECO_LOW - NA - 0xDC - 0x20 - - - REG_L2_MEM_RDN_ECO_LOW - NA - 0 - 32 - read-write - - - - - L2_MEM_RDN_ECO_HIGH - NA - 0xE0 - 0x20 - 0xFFFFFFFF - - - REG_L2_MEM_RDN_ECO_HIGH - NA - 0 - 32 - read-write - - - - - TCM_RDN_ECO_CS - NA - 0xE4 - 0x20 - - - REG_HP_TCM_RDN_ECO_EN - NA - 0 - 1 - read-write - - - REG_HP_TCM_RDN_ECO_RESULT - NA - 1 - 1 - read-only - - - - - TCM_RDN_ECO_LOW - NA - 0xE8 - 0x20 - - - REG_HP_TCM_RDN_ECO_LOW - NA - 0 - 32 - read-write - - - - - TCM_RDN_ECO_HIGH - NA - 0xEC - 0x20 - 0xFFFFFFFF - - - REG_HP_TCM_RDN_ECO_HIGH - NA - 0 - 32 - read-write - - - - - GPIO_DED_HOLD_CTRL - NA - 0xF0 - 0x20 - - - REG_GPIO_DED_HOLD - hold control for gpio63~56 - 0 - 26 - read-write - - - - - L2_MEM_SW_ECC_BWE_MASK - NA - 0xF4 - 0x20 - - - REG_L2_MEM_SW_ECC_BWE_MASK_CTRL - Set 1 to mask bwe hamming code bit - 0 - 1 - read-write - - - - - USB20OTG_MEM_CTRL - NA - 0xF8 - 0x20 - - - REG_USB20_MEM_CLK_FORCE_ON - NA - 0 - 1 - read-write - - - - - TCM_INT_RAW - need_des - 0xFC - 0x20 - - - TCM_PARITY_ERR_INT_RAW - need_des - 31 - 1 - read-write - - - - - TCM_INT_ST - need_des - 0x100 - 0x20 - - - TCM_PARITY_ERR_INT_ST - need_des - 31 - 1 - read-only - - - - - TCM_INT_ENA - need_des - 0x104 - 0x20 - - - TCM_PARITY_ERR_INT_ENA - need_des - 31 - 1 - read-write - - - - - TCM_INT_CLR - need_des - 0x108 - 0x20 - - - TCM_PARITY_ERR_INT_CLR - need_des - 31 - 1 - write-only - - - - - TCM_PARITY_INT_RECORD - need_des - 0x10C - 0x20 - - - TCM_PARITY_ERR_INT_ADDR - hp tcm_parity_err_addr - 0 - 13 - read-only - - - - - L1_CACHE_PWR_CTRL - NA - 0x110 - 0x20 - - - REG_L1_CACHE_MEM_FO - need_des - 0 - 6 - read-write - - - - - L2_CACHE_PWR_CTRL - NA - 0x114 - 0x20 - - - REG_L2_CACHE_MEM_FO - need_des - 0 - 2 - read-write - - - - - CPU_WAITI_CONF - CPU_WAITI configuration register - 0x118 - 0x20 - 0x00000001 - - - CPU_WAIT_MODE_FORCE_ON - Set 1 to force cpu_waiti_clk enable. - 0 - 1 - read-write - - - CPU_WAITI_DELAY_NUM - This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk will close - 1 - 4 - read-write - - - - - CORE_DEBUG_RUNSTALL_CONF - Core Debug runstall configure register - 0x11C - 0x20 - - - CORE_DEBUG_RUNSTALL_ENABLE - Set this field to 1 to enable debug runstall feature between HP-core and LP-core. - 0 - 1 - read-write - - - - - CORE_AHB_TIMEOUT - need_des - 0x120 - 0x20 - 0x0001FFFF - - - EN - set this field to 1 to enable hp core0&1 ahb timeout handle - 0 - 1 - read-write - - - THRES - This field used to set hp core0&1 ahb bus timeout threshold - 1 - 16 - read-write - - - - - CORE_IBUS_TIMEOUT - need_des - 0x124 - 0x20 - 0x0001FFFF - - - EN - set this field to 1 to enable hp core0&1 ibus timeout handle - 0 - 1 - read-write - - - THRES - This field used to set hp core0&1 ibus timeout threshold - 1 - 16 - read-write - - - - - CORE_DBUS_TIMEOUT - need_des - 0x128 - 0x20 - 0x0001FFFF - - - EN - set this field to 1 to enable hp core0&1 dbus timeout handle - 0 - 1 - read-write - - - THRES - This field used to set hp core0&1 dbus timeout threshold - 1 - 16 - read-write - - - - - ICM_CPU_H2X_CFG - need_des - 0x138 - 0x20 - 0x00000003 - - - CPU_ICM_H2X_POST_WR_EN - need_des - 0 - 1 - read-write - - - CPU_ICM_H2X_CUT_THROUGH_EN - need_des - 1 - 1 - read-write - - - CPU_ICM_H2X_BRIDGE_BUSY - need_des - 2 - 1 - read-only - - - - - PERI1_APB_POSTW_EN - NA - 0x13C - 0x20 - - - PERI1_APB_POSTW_EN - hp_peri1 apb register interface post write enable, 1 will speed up write, but will take some time to update value to register - 0 - 1 - read-write - - - - - BITSCRAMBLER_PERI_SEL - Bitscrambler Peri Sel - 0x140 - 0x20 - 0x000000FF - - - BITSCRAMBLER_PERI_RX_SEL - Set this field to sel peri with DMA RX interface to connec with bitscrambler: 4'h0 : lcd_cam, 4'h1: gpspi2, 4'h2: gpspi3, 4'h3: parl_io, 4'h4: aes, 4'h5: sha, 4'h6: adc, 4'h7: i2s0, 4'h8: i2s1, 4'h9: i2s2, 4'ha: i3c_mst, 4'hb: uhci0, 4'hc: RMT, else : none - 0 - 4 - read-write - - - BITSCRAMBLER_PERI_TX_SEL - Set this field to sel peri with DMA TX interface to connec with bitscrambler: 4'h0 : lcd_cam, 4'h1: gpspi2, 4'h2: gpspi3, 4'h3: parl_io, 4'h4: aes, 4'h5: sha, 4'h6: adc, 4'h7: i2s0, 4'h8: i2s1, 4'h9: i2s2, 4'ha: i3c_mst, 4'hb: uhci0, 4'hc: RMT, else : none - 4 - 4 - read-write - - - - - APB_SYNC_POSTW_EN - N/A - 0x144 - 0x20 - - - GMAC_APB_POSTW_EN - N/A - 0 - 1 - read-write - - - DSI_HOST_APB_POSTW_EN - N/A - 1 - 1 - read-write - - - CSI_HOST_APB_SYNC_POSTW_EN - N/A - 2 - 1 - read-write - - - CSI_HOST_APB_ASYNC_POSTW_EN - N/A - 3 - 1 - read-write - - - - - GDMA_CTRL - N/A - 0x148 - 0x20 - - - DEBUG_CH_NUM - N/A - 0 - 2 - read-write - - - - - GMAC_CTRL0 - N/A - 0x14C - 0x20 - - - PTP_PPS - N/A - 0 - 1 - read-only - - - SBD_FLOWCTRL - N/A - 1 - 1 - read-write - - - PHY_INTF_SEL - N/A - 2 - 3 - read-write - - - GMAC_MEM_CLK_FORCE_ON - N/A - 5 - 1 - read-write - - - GMAC_RST_CLK_TX_N - N/A - 6 - 1 - read-only - - - GMAC_RST_CLK_RX_N - N/A - 7 - 1 - read-only - - - - - GMAC_CTRL1 - N/A - 0x150 - 0x20 - - - PTP_TIMESTAMP_L - N/A - 0 - 32 - read-only - - - - - GMAC_CTRL2 - N/A - 0x154 - 0x20 - - - PTP_TIMESTAMP_H - N/A - 0 - 32 - read-only - - - - - VPU_CTRL - N/A - 0x158 - 0x20 - - - PPA_LSLP_MEM_PD - N/A - 0 - 1 - read-write - - - JPEG_SDSLP_MEM_PD - N/A - 1 - 1 - read-write - - - JPEG_LSLP_MEM_PD - N/A - 2 - 1 - read-write - - - JPEG_DSLP_MEM_PD - N/A - 3 - 1 - read-write - - - DMA2D_LSLP_MEM_PD - N/A - 4 - 1 - read-write - - - - - USBOTG20_CTRL - N/A - 0x15C - 0x20 - 0x00822640 - - - OTG_PHY_TEST_DONE - N/A - 0 - 1 - read-only - - - USB_MEM_AUX_CTRL - N/A - 1 - 14 - read-write - - - PHY_SUSPENDM - N/A - 15 - 1 - read-write - - - PHY_SUSPEND_FORCE_EN - N/A - 16 - 1 - read-write - - - PHY_RSTN - N/A - 17 - 1 - read-write - - - PHY_RESET_FORCE_EN - N/A - 18 - 1 - read-write - - - PHY_PLL_FORCE_EN - N/A - 19 - 1 - read-write - - - PHY_PLL_EN - N/A - 20 - 1 - read-write - - - OTG_SUSPENDM - N/A - 21 - 1 - read-write - - - OTG_PHY_TXBITSTUFF_EN - N/A - 22 - 1 - read-write - - - OTG_PHY_REFCLK_MODE - N/A - 23 - 1 - read-write - - - OTG_PHY_BISTEN - N/A - 24 - 1 - read-write - - - - - TCM_ERR_RESP_CTRL - need_des - 0x160 - 0x20 - - - TCM_ERR_RESP_EN - Set 1 to turn on tcm error response - 0 - 1 - read-write - - - - - L2_MEM_REFRESH - NA - 0x164 - 0x20 - 0x00000040 - - - REG_L2_MEM_UNIT0_REFERSH_EN - NA - 0 - 1 - read-write - - - REG_L2_MEM_UNIT1_REFERSH_EN - NA - 1 - 1 - read-write - - - REG_L2_MEM_UNIT2_REFERSH_EN - NA - 2 - 1 - read-write - - - REG_L2_MEM_UNIT3_REFERSH_EN - NA - 3 - 1 - read-write - - - REG_L2_MEM_UNIT4_REFERSH_EN - NA - 4 - 1 - read-write - - - REG_L2_MEM_UNIT5_REFERSH_EN - NA - 5 - 1 - read-write - - - REG_L2_MEM_REFERSH_CNT_RESET - Set 1 to reset l2mem_refresh_cnt - 6 - 1 - read-write - - - REG_L2_MEM_UNIT0_REFRESH_DONE - NA - 7 - 1 - read-only - - - REG_L2_MEM_UNIT1_REFRESH_DONE - NA - 8 - 1 - read-only - - - REG_L2_MEM_UNIT2_REFRESH_DONE - NA - 9 - 1 - read-only - - - REG_L2_MEM_UNIT3_REFRESH_DONE - NA - 10 - 1 - read-only - - - REG_L2_MEM_UNIT4_REFRESH_DONE - NA - 11 - 1 - read-only - - - REG_L2_MEM_UNIT5_REFRESH_DONE - NA - 12 - 1 - read-only - - - - - TCM_INIT - NA - 0x168 - 0x20 - 0x00000002 - - - REG_TCM_INIT_EN - NA - 0 - 1 - read-write - - - REG_TCM_INIT_CNT_RESET - Set 1 to reset tcm init cnt - 1 - 1 - read-write - - - REG_TCM_INIT_DONE - NA - 2 - 1 - read-only - - - - - TCM_PARITY_CHECK_CTRL - need_des - 0x16C - 0x20 - - - TCM_PARITY_CHECK_EN - Set 1 to turn on tcm parity check - 0 - 1 - read-write - - - - - DESIGN_FOR_VERIFICATION0 - need_des - 0x170 - 0x20 - - - DFV0 - register for DV - 0 - 32 - read-write - - - - - DESIGN_FOR_VERIFICATION1 - need_des - 0x174 - 0x20 - - - DFV1 - register for DV - 0 - 32 - read-write - - - - - PSRAM_FLASH_ADDR_INTERCHANGE - need_des - 0x180 - 0x20 - - - CPU - Set 1 to enable addr interchange between psram and flash in axi matrix when hp cpu access through cache - 0 - 1 - read-write - - - DMA - Set 1 to enable addr interchange between psram and flash in axi matrix when dma device access, lp core access and hp core access through ahb - 1 - 1 - read-write - - - - - AHB2AXI_BRESP_ERR_INT_RAW - NA - 0x188 - 0x20 - - - CPU_ICM_H2X_BRESP_ERR_INT_RAW - the raw interrupt status of bresp error, triggered when if bresp err occurs in post write mode in ahb2axi. - 0 - 1 - read-write - - - - - AHB2AXI_BRESP_ERR_INT_ST - need_des - 0x18C - 0x20 - - - CPU_ICM_H2X_BRESP_ERR_INT_ST - the masked interrupt status of cpu_icm_h2x_bresp_err - 31 - 1 - read-only - - - - - AHB2AXI_BRESP_ERR_INT_ENA - need_des - 0x190 - 0x20 - - - CPU_ICM_H2X_BRESP_ERR_INT_ENA - Write 1 to enable cpu_icm_h2x_bresp_err int - 31 - 1 - read-write - - - - - AHB2AXI_BRESP_ERR_INT_CLR - need_des - 0x194 - 0x20 - - - CPU_ICM_H2X_BRESP_ERR_INT_CLR - Write 1 to clear cpu_icm_h2x_bresp_err int - 31 - 1 - write-only - - - - - L2_MEM_ERR_RESP_CTRL - need_des - 0x198 - 0x20 - - - L2_MEM_ERR_RESP_EN - Set 1 to turn on l2mem error response - 0 - 1 - read-write - - - - - L2_MEM_AHB_BUFFER_CTRL - need_des - 0x19C - 0x20 - - - L2_MEM_AHB_WRBUFFER_EN - Set 1 to turn on l2mem ahb wr buffer - 0 - 1 - read-write - - - L2_MEM_AHB_RDBUFFER_EN - Set 1 to turn on l2mem ahb rd buffer - 1 - 1 - read-write - - - - - CORE_DMACTIVE_LPCORE - need_des - 0x1A0 - 0x20 - - - CORE_DMACTIVE_LPCORE - hp core dmactive_lpcore value - 0 - 1 - read-only - - - - - CORE_ERR_RESP_DIS - need_des - 0x1A4 - 0x20 - - - CORE_ERR_RESP_DIS - Set bit0 to disable ibus err resp. Set bit1 to disable dbus err resp. Set bit 2 to disable ahb err resp. - 0 - 3 - read-write - - - - - CORE_TIMEOUT_INT_RAW - Hp core bus timeout interrupt raw register - 0x1A8 - 0x20 - - - CORE0_AHB_TIMEOUT_INT_RAW - the raw interrupt status of hp core0 ahb timeout - 0 - 1 - read-write - - - CORE1_AHB_TIMEOUT_INT_RAW - the raw interrupt status of hp core1 ahb timeout - 1 - 1 - read-write - - - CORE0_IBUS_TIMEOUT_INT_RAW - the raw interrupt status of hp core0 ibus timeout - 2 - 1 - read-write - - - CORE1_IBUS_TIMEOUT_INT_RAW - the raw interrupt status of hp core1 ibus timeout - 3 - 1 - read-write - - - CORE0_DBUS_TIMEOUT_INT_RAW - the raw interrupt status of hp core0 dbus timeout - 4 - 1 - read-write - - - CORE1_DBUS_TIMEOUT_INT_RAW - the raw interrupt status of hp core1 dbus timeout - 5 - 1 - read-write - - - - - CORE_TIMEOUT_INT_ST - masked interrupt register - 0x1AC - 0x20 - - - CORE0_AHB_TIMEOUT_INT_ST - the masked interrupt status of hp core0 ahb timeout - 0 - 1 - read-only - - - CORE1_AHB_TIMEOUT_INT_ST - the masked interrupt status of hp core1 ahb timeout - 1 - 1 - read-only - - - CORE0_IBUS_TIMEOUT_INT_ST - the masked interrupt status of hp core0 ibus timeout - 2 - 1 - read-only - - - CORE1_IBUS_TIMEOUT_INT_ST - the masked interrupt status of hp core1 ibus timeout - 3 - 1 - read-only - - - CORE0_DBUS_TIMEOUT_INT_ST - the masked interrupt status of hp core0 dbus timeout - 4 - 1 - read-only - - - CORE1_DBUS_TIMEOUT_INT_ST - the masked interrupt status of hp core1 dbus timeout - 5 - 1 - read-only - - - - - CORE_TIMEOUT_INT_ENA - masked interrupt register - 0x1B0 - 0x20 - - - CORE0_AHB_TIMEOUT_INT_ENA - Write 1 to enable hp_core0_ahb_timeout int - 0 - 1 - read-write - - - CORE1_AHB_TIMEOUT_INT_ENA - Write 1 to enable hp_core1_ahb_timeout int - 1 - 1 - read-write - - - CORE0_IBUS_TIMEOUT_INT_ENA - Write 1 to enable hp_core0_ibus_timeout int - 2 - 1 - read-write - - - CORE1_IBUS_TIMEOUT_INT_ENA - Write 1 to enable hp_core1_ibus_timeout int - 3 - 1 - read-write - - - CORE0_DBUS_TIMEOUT_INT_ENA - Write 1 to enable hp_core0_dbus_timeout int - 4 - 1 - read-write - - - CORE1_DBUS_TIMEOUT_INT_ENA - Write 1 to enable hp_core1_dbus_timeout int - 5 - 1 - read-write - - - - - CORE_TIMEOUT_INT_CLR - interrupt clear register - 0x1B4 - 0x20 - - - CORE0_AHB_TIMEOUT_INT_CLR - Write 1 to clear hp_core0_ahb_timeout int - 0 - 1 - write-only - - - CORE1_AHB_TIMEOUT_INT_CLR - Write 1 to clear hp_core1_ahb_timeout int - 1 - 1 - write-only - - - CORE0_IBUS_TIMEOUT_INT_CLR - Write 1 to clear hp_core0_ibus_timeout int - 2 - 1 - write-only - - - CORE1_IBUS_TIMEOUT_INT_CLR - Write 1 to clear hp_core1_ibus_timeout int - 3 - 1 - write-only - - - CORE0_DBUS_TIMEOUT_INT_CLR - Write 1 to clear hp_core0_dbus_timeout int - 4 - 1 - write-only - - - CORE1_DBUS_TIMEOUT_INT_CLR - Write 1 to clear hp_core1_dbus_timeout int - 5 - 1 - write-only - - - - - GPIO_O_HYS_CTRL0 - NA - 0x1C0 - 0x20 - - - REG_GPIO_0_HYS_LOW - hys control for gpio47~16 - 0 - 32 - read-write - - - - - GPIO_O_HYS_CTRL1 - NA - 0x1C4 - 0x20 - - - REG_GPIO_0_HYS_HIGH - hys control for gpio56~48 - 0 - 9 - read-write - - - - - RSA_PD_CTRL - rsa pd ctrl register - 0x1D0 - 0x20 - 0x00000002 - - - RSA_MEM_FORCE_PD - Set this bit to power down rsa internal memory. - 0 - 1 - read-write - - - RSA_MEM_FORCE_PU - Set this bit to force power up rsa internal memory - 1 - 1 - read-write - - - RSA_MEM_PD - Set this bit to force power down rsa internal memory. - 2 - 1 - read-write - - - - - ECC_PD_CTRL - ecc pd ctrl register - 0x1D4 - 0x20 - 0x00000002 - - - ECC_MEM_FORCE_PD - Set this bit to power down ecc internal memory. - 0 - 1 - read-write - - - ECC_MEM_FORCE_PU - Set this bit to force power up ecc internal memory - 1 - 1 - read-write - - - ECC_MEM_PD - Set this bit to force power down ecc internal memory. - 2 - 1 - read-write - - - - - RNG_CFG - rng cfg register - 0x1D8 - 0x20 - - - RNG_SAMPLE_ENABLE - enable rng sample chain - 0 - 1 - read-write - - - RNG_CHAIN_CLK_DIV_NUM - chain clk div num to pad for debug - 16 - 8 - read-write - - - RNG_SAMPLE_CNT - debug rng sample cnt - 24 - 8 - read-only - - - - - UART_PD_CTRL - ecc pd ctrl register - 0x1DC - 0x20 - 0x00000002 - - - UART_MEM_FORCE_PD - Set this bit to power down hp uart internal memory. - 0 - 1 - read-write - - - UART_MEM_FORCE_PU - Set this bit to force power up hp uart internal memory - 1 - 1 - read-write - - - - - PERI_MEM_CLK_FORCE_ON - hp peri mem clk force on regpster - 0x1E0 - 0x20 - - - RMT_MEM_CLK_FORCE_ON - Set this bit to force on mem clk in rmt - 0 - 1 - read-write - - - BITSCRAMBLER_TX_MEM_CLK_FORCE_ON - Set this bit to force on tx mem clk in bitscrambler - 1 - 1 - read-write - - - BITSCRAMBLER_RX_MEM_CLK_FORCE_ON - Set this bit to force on rx mem clk in bitscrambler - 2 - 1 - read-write - - - GDMA_MEM_CLK_FORCE_ON - Set this bit to force on mem clk in gdma - 3 - 1 - read-write - - - - - - - HP_SYS_CLKRST - HP_SYS_CLKRST Peripheral - HP_SYS_CLKRST - 0x500E6000 - - 0x0 - 0xF0 - registers - - - - CLK_EN0 - Reserved - 0x0 - 0x20 - 0x00000001 - - - REG_CLK_EN - Reserved - 0 - 1 - read-write - - - - - ROOT_CLK_CTRL0 - Reserved - 0x4 - 0x20 - - - REG_CPUICM_DELAY_NUM - Reserved - 0 - 4 - read-write - - - REG_SOC_CLK_DIV_UPDATE - Reserved - 4 - 1 - write-only - - - REG_CPU_CLK_DIV_NUM - Reserved - 5 - 8 - read-write - - - REG_CPU_CLK_DIV_NUMERATOR - Reserved - 13 - 8 - read-write - - - REG_CPU_CLK_DIV_DENOMINATOR - Reserved - 21 - 8 - read-write - - - - - ROOT_CLK_CTRL1 - Reserved - 0x8 - 0x20 - 0x00000001 - - - REG_MEM_CLK_DIV_NUM - Reserved - 0 - 8 - read-write - - - REG_MEM_CLK_DIV_NUMERATOR - Reserved - 8 - 8 - read-write - - - REG_MEM_CLK_DIV_DENOMINATOR - Reserved - 16 - 8 - read-write - - - REG_SYS_CLK_DIV_NUM - Reserved - 24 - 8 - read-write - - - - - ROOT_CLK_CTRL2 - Reserved - 0xC - 0x20 - 0x00010000 - - - REG_SYS_CLK_DIV_NUMERATOR - Reserved - 0 - 8 - read-write - - - REG_SYS_CLK_DIV_DENOMINATOR - Reserved - 8 - 8 - read-write - - - REG_APB_CLK_DIV_NUM - Reserved - 16 - 8 - read-write - - - REG_APB_CLK_DIV_NUMERATOR - Reserved - 24 - 8 - read-write - - - - - ROOT_CLK_CTRL3 - Reserved - 0x10 - 0x20 - - - REG_APB_CLK_DIV_DENOMINATOR - Reserved - 0 - 8 - read-write - - - - - SOC_CLK_CTRL0 - Reserved - 0x14 - 0x20 - 0xE6DF97AF - - - REG_CORE0_CLIC_CLK_EN - Reserved - 0 - 1 - read-write - - - REG_CORE1_CLIC_CLK_EN - Reserved - 1 - 1 - read-write - - - REG_MISC_CPU_CLK_EN - Reserved - 2 - 1 - read-write - - - REG_CORE0_CPU_CLK_EN - Reserved - 3 - 1 - read-write - - - REG_CORE1_CPU_CLK_EN - Reserved - 4 - 1 - read-write - - - REG_TCM_CPU_CLK_EN - Reserved - 5 - 1 - read-write - - - REG_BUSMON_CPU_CLK_EN - Reserved - 6 - 1 - read-write - - - REG_L1CACHE_CPU_CLK_EN - Reserved - 7 - 1 - read-write - - - REG_L1CACHE_D_CPU_CLK_EN - Reserved - 8 - 1 - read-write - - - REG_L1CACHE_I0_CPU_CLK_EN - Reserved - 9 - 1 - read-write - - - REG_L1CACHE_I1_CPU_CLK_EN - Reserved - 10 - 1 - read-write - - - REG_TRACE_CPU_CLK_EN - Reserved - 11 - 1 - read-write - - - REG_ICM_CPU_CLK_EN - Reserved - 12 - 1 - read-write - - - REG_GDMA_CPU_CLK_EN - Reserved - 13 - 1 - read-write - - - REG_VPU_CPU_CLK_EN - Reserved - 14 - 1 - read-write - - - REG_L1CACHE_MEM_CLK_EN - Reserved - 15 - 1 - read-write - - - REG_L1CACHE_D_MEM_CLK_EN - Reserved - 16 - 1 - read-write - - - REG_L1CACHE_I0_MEM_CLK_EN - Reserved - 17 - 1 - read-write - - - REG_L1CACHE_I1_MEM_CLK_EN - Reserved - 18 - 1 - read-write - - - REG_L2CACHE_MEM_CLK_EN - Reserved - 19 - 1 - read-write - - - REG_L2MEM_MEM_CLK_EN - Reserved - 20 - 1 - read-write - - - REG_L2MEMMON_MEM_CLK_EN - Reserved - 21 - 1 - read-write - - - REG_ICM_MEM_CLK_EN - Reserved - 22 - 1 - read-write - - - REG_MISC_SYS_CLK_EN - Reserved - 23 - 1 - read-write - - - REG_TRACE_SYS_CLK_EN - Reserved - 24 - 1 - read-write - - - REG_L2CACHE_SYS_CLK_EN - Reserved - 25 - 1 - read-write - - - REG_L2MEM_SYS_CLK_EN - Reserved - 26 - 1 - read-write - - - REG_L2MEMMON_SYS_CLK_EN - Reserved - 27 - 1 - read-write - - - REG_TCMMON_SYS_CLK_EN - Reserved - 28 - 1 - read-write - - - REG_ICM_SYS_CLK_EN - Reserved - 29 - 1 - read-write - - - REG_FLASH_SYS_CLK_EN - Reserved - 30 - 1 - read-write - - - REG_PSRAM_SYS_CLK_EN - Reserved - 31 - 1 - read-write - - - - - SOC_CLK_CTRL1 - Reserved - 0x18 - 0x20 - 0x7C7F801F - - - REG_GPSPI2_SYS_CLK_EN - Reserved - 0 - 1 - read-write - - - REG_GPSPI3_SYS_CLK_EN - Reserved - 1 - 1 - read-write - - - REG_REGDMA_SYS_CLK_EN - Reserved - 2 - 1 - read-write - - - REG_AHB_PDMA_SYS_CLK_EN - Reserved - 3 - 1 - read-write - - - REG_AXI_PDMA_SYS_CLK_EN - Reserved - 4 - 1 - read-write - - - REG_GDMA_SYS_CLK_EN - Reserved - 5 - 1 - read-write - - - REG_DMA2D_SYS_CLK_EN - Reserved - 6 - 1 - read-write - - - REG_VPU_SYS_CLK_EN - Reserved - 7 - 1 - read-write - - - REG_JPEG_SYS_CLK_EN - Reserved - 8 - 1 - read-write - - - REG_PPA_SYS_CLK_EN - Reserved - 9 - 1 - read-write - - - REG_CSI_BRG_SYS_CLK_EN - Reserved - 10 - 1 - read-write - - - REG_CSI_HOST_SYS_CLK_EN - Reserved - 11 - 1 - read-write - - - REG_DSI_SYS_CLK_EN - Reserved - 12 - 1 - read-write - - - REG_EMAC_SYS_CLK_EN - Reserved - 13 - 1 - read-write - - - REG_SDMMC_SYS_CLK_EN - Reserved - 14 - 1 - read-write - - - REG_USB_OTG11_SYS_CLK_EN - Reserved - 15 - 1 - read-write - - - REG_USB_OTG20_SYS_CLK_EN - Reserved - 16 - 1 - read-write - - - REG_UHCI_SYS_CLK_EN - Reserved - 17 - 1 - read-write - - - REG_UART0_SYS_CLK_EN - Reserved - 18 - 1 - read-write - - - REG_UART1_SYS_CLK_EN - Reserved - 19 - 1 - read-write - - - REG_UART2_SYS_CLK_EN - Reserved - 20 - 1 - read-write - - - REG_UART3_SYS_CLK_EN - Reserved - 21 - 1 - read-write - - - REG_UART4_SYS_CLK_EN - Reserved - 22 - 1 - read-write - - - REG_PARLIO_SYS_CLK_EN - Reserved - 23 - 1 - read-write - - - REG_ETM_SYS_CLK_EN - Reserved - 24 - 1 - read-write - - - REG_PVT_SYS_CLK_EN - Reserved - 25 - 1 - read-write - - - REG_CRYPTO_SYS_CLK_EN - Reserved - 26 - 1 - read-write - - - REG_KEY_MANAGER_SYS_CLK_EN - Reserved - 27 - 1 - read-write - - - REG_BITSRAMBLER_SYS_CLK_EN - Reserved - 28 - 1 - read-write - - - REG_BITSRAMBLER_RX_SYS_CLK_EN - Reserved - 29 - 1 - read-write - - - REG_BITSRAMBLER_TX_SYS_CLK_EN - Reserved - 30 - 1 - read-write - - - REG_H264_SYS_CLK_EN - Reserved - 31 - 1 - read-write - - - - - SOC_CLK_CTRL2 - Reserved - 0x1C - 0x20 - 0x20F80FDE - - - REG_RMT_SYS_CLK_EN - Reserved - 0 - 1 - read-write - - - REG_HP_CLKRST_APB_CLK_EN - Reserved - 1 - 1 - read-write - - - REG_SYSREG_APB_CLK_EN - Reserved - 2 - 1 - read-write - - - REG_ICM_APB_CLK_EN - Reserved - 3 - 1 - read-write - - - REG_INTRMTX_APB_CLK_EN - Reserved - 4 - 1 - read-write - - - REG_ADC_APB_CLK_EN - Reserved - 5 - 1 - read-write - - - REG_UHCI_APB_CLK_EN - Reserved - 6 - 1 - read-write - - - REG_UART0_APB_CLK_EN - Reserved - 7 - 1 - read-write - - - REG_UART1_APB_CLK_EN - Reserved - 8 - 1 - read-write - - - REG_UART2_APB_CLK_EN - Reserved - 9 - 1 - read-write - - - REG_UART3_APB_CLK_EN - Reserved - 10 - 1 - read-write - - - REG_UART4_APB_CLK_EN - Reserved - 11 - 1 - read-write - - - REG_I2C0_APB_CLK_EN - Reserved - 12 - 1 - read-write - - - REG_I2C1_APB_CLK_EN - Reserved - 13 - 1 - read-write - - - REG_I2S0_APB_CLK_EN - Reserved - 14 - 1 - read-write - - - REG_I2S1_APB_CLK_EN - Reserved - 15 - 1 - read-write - - - REG_I2S2_APB_CLK_EN - Reserved - 16 - 1 - read-write - - - REG_I3C_MST_APB_CLK_EN - Reserved - 17 - 1 - read-write - - - REG_I3C_SLV_APB_CLK_EN - Reserved - 18 - 1 - read-write - - - REG_GPSPI2_APB_CLK_EN - Reserved - 19 - 1 - read-write - - - REG_GPSPI3_APB_CLK_EN - Reserved - 20 - 1 - read-write - - - REG_TIMERGRP0_APB_CLK_EN - Reserved - 21 - 1 - read-write - - - REG_TIMERGRP1_APB_CLK_EN - Reserved - 22 - 1 - read-write - - - REG_SYSTIMER_APB_CLK_EN - Reserved - 23 - 1 - read-write - - - REG_TWAI0_APB_CLK_EN - Reserved - 24 - 1 - read-write - - - REG_TWAI1_APB_CLK_EN - Reserved - 25 - 1 - read-write - - - REG_TWAI2_APB_CLK_EN - Reserved - 26 - 1 - read-write - - - REG_MCPWM0_APB_CLK_EN - Reserved - 27 - 1 - read-write - - - REG_MCPWM1_APB_CLK_EN - Reserved - 28 - 1 - read-write - - - REG_USB_DEVICE_APB_CLK_EN - Reserved - 29 - 1 - read-write - - - REG_PCNT_APB_CLK_EN - Reserved - 30 - 1 - read-write - - - REG_PARLIO_APB_CLK_EN - Reserved - 31 - 1 - read-write - - - - - SOC_CLK_CTRL3 - Reserved - 0x20 - 0x20 - 0x00000008 - - - REG_LEDC_APB_CLK_EN - Reserved - 0 - 1 - read-write - - - REG_LCDCAM_APB_CLK_EN - Reserved - 1 - 1 - read-write - - - REG_ETM_APB_CLK_EN - Reserved - 2 - 1 - read-write - - - REG_IOMUX_APB_CLK_EN - Reserved - 3 - 1 - read-write - - - - - REF_CLK_CTRL0 - Reserved - 0x24 - 0x20 - 0x02011309 - - - REG_REF_50M_CLK_DIV_NUM - Reserved - 0 - 8 - read-write - - - REG_REF_25M_CLK_DIV_NUM - Reserved - 8 - 8 - read-write - - - REG_REF_240M_CLK_DIV_NUM - Reserved - 16 - 8 - read-write - - - REG_REF_160M_CLK_DIV_NUM - Reserved - 24 - 8 - read-write - - - - - REF_CLK_CTRL1 - Reserved - 0x28 - 0x20 - 0x58170503 - - - REG_REF_120M_CLK_DIV_NUM - Reserved - 0 - 8 - read-write - - - REG_REF_80M_CLK_DIV_NUM - Reserved - 8 - 8 - read-write - - - REG_REF_20M_CLK_DIV_NUM - Reserved - 16 - 8 - read-write - - - REG_TM_400M_CLK_EN - Reserved - 24 - 1 - read-write - - - REG_TM_200M_CLK_EN - Reserved - 25 - 1 - read-write - - - REG_TM_100M_CLK_EN - Reserved - 26 - 1 - read-write - - - REG_REF_50M_CLK_EN - Reserved - 27 - 1 - read-write - - - REG_REF_25M_CLK_EN - Reserved - 28 - 1 - read-write - - - REG_TM_480M_CLK_EN - Reserved - 29 - 1 - read-write - - - REG_REF_240M_CLK_EN - Reserved - 30 - 1 - read-write - - - REG_TM_240M_CLK_EN - Reserved - 31 - 1 - read-write - - - - - REF_CLK_CTRL2 - Reserved - 0x2C - 0x20 - 0x00000115 - - - REG_REF_160M_CLK_EN - Reserved - 0 - 1 - read-write - - - REG_TM_160M_CLK_EN - Reserved - 1 - 1 - read-write - - - REG_REF_120M_CLK_EN - Reserved - 2 - 1 - read-write - - - REG_TM_120M_CLK_EN - Reserved - 3 - 1 - read-write - - - REG_REF_80M_CLK_EN - Reserved - 4 - 1 - read-write - - - REG_TM_80M_CLK_EN - Reserved - 5 - 1 - read-write - - - REG_TM_60M_CLK_EN - Reserved - 6 - 1 - read-write - - - REG_TM_48M_CLK_EN - Reserved - 7 - 1 - read-write - - - REG_REF_20M_CLK_EN - Reserved - 8 - 1 - read-write - - - REG_TM_20M_CLK_EN - Reserved - 9 - 1 - read-write - - - - - PERI_CLK_CTRL00 - Reserved - 0x30 - 0x20 - 0x0000C03C - - - REG_FLASH_CLK_SRC_SEL - Reserved - 0 - 2 - read-write - - - REG_FLASH_PLL_CLK_EN - Reserved - 2 - 1 - read-write - - - REG_FLASH_CORE_CLK_EN - Reserved - 3 - 1 - read-write - - - REG_FLASH_CORE_CLK_DIV_NUM - Reserved - 4 - 8 - read-write - - - REG_PSRAM_CLK_SRC_SEL - Reserved - 12 - 2 - read-write - - - REG_PSRAM_PLL_CLK_EN - Reserved - 14 - 1 - read-write - - - REG_PSRAM_CORE_CLK_EN - Reserved - 15 - 1 - read-write - - - REG_PSRAM_CORE_CLK_DIV_NUM - Reserved - 16 - 8 - read-write - - - REG_PAD_EMAC_REF_CLK_EN - Reserved - 24 - 1 - read-write - - - REG_EMAC_RMII_CLK_SRC_SEL - Reserved - 25 - 2 - read-write - - - REG_EMAC_RMII_CLK_EN - Reserved - 27 - 1 - read-write - - - REG_EMAC_RX_CLK_SRC_SEL - Reserved - 28 - 1 - read-write - - - REG_EMAC_RX_CLK_EN - Reserved - 29 - 1 - read-write - - - - - PERI_CLK_CTRL01 - Reserved - 0x34 - 0x20 - 0x00000401 - - - REG_EMAC_RX_CLK_DIV_NUM - Reserved - 0 - 8 - read-write - - - REG_EMAC_TX_CLK_SRC_SEL - Reserved - 8 - 1 - read-write - - - REG_EMAC_TX_CLK_EN - Reserved - 9 - 1 - read-write - - - REG_EMAC_TX_CLK_DIV_NUM - Reserved - 10 - 8 - read-write - - - REG_EMAC_PTP_REF_CLK_SRC_SEL - Reserved - 18 - 1 - read-write - - - REG_EMAC_PTP_REF_CLK_EN - Reserved - 19 - 1 - read-write - - - REG_EMAC_UNUSED0_CLK_EN - Reserved - 20 - 1 - read-write - - - REG_EMAC_UNUSED1_CLK_EN - Reserved - 21 - 1 - read-write - - - REG_SDIO_HS_MODE - Reserved - 22 - 1 - read-write - - - REG_SDIO_LS_CLK_SRC_SEL - Reserved - 23 - 1 - read-write - - - REG_SDIO_LS_CLK_EN - Reserved - 24 - 1 - read-write - - - - - PERI_CLK_CTRL02 - Reserved - 0x38 - 0x20 - - - REG_SDIO_LS_CLK_DIV_NUM - Reserved - 0 - 8 - read-write - - - REG_SDIO_LS_CLK_EDGE_CFG_UPDATE - Reserved - 8 - 1 - write-only - - - REG_SDIO_LS_CLK_EDGE_L - Reserved - 9 - 4 - read-write - - - REG_SDIO_LS_CLK_EDGE_H - Reserved - 13 - 4 - read-write - - - REG_SDIO_LS_CLK_EDGE_N - Reserved - 17 - 4 - read-write - - - REG_SDIO_LS_SLF_CLK_EDGE_SEL - Reserved - 21 - 2 - read-write - - - REG_SDIO_LS_DRV_CLK_EDGE_SEL - Reserved - 23 - 2 - read-write - - - REG_SDIO_LS_SAM_CLK_EDGE_SEL - Reserved - 25 - 2 - read-write - - - REG_SDIO_LS_SLF_CLK_EN - Reserved - 27 - 1 - read-write - - - REG_SDIO_LS_DRV_CLK_EN - Reserved - 28 - 1 - read-write - - - REG_SDIO_LS_SAM_CLK_EN - Reserved - 29 - 1 - read-write - - - REG_MIPI_DSI_DPHY_CLK_SRC_SEL - Reserved - 30 - 2 - read-write - - - - - PERI_CLK_CTRL03 - Reserved - 0x3C - 0x20 - - - REG_MIPI_DSI_DPHY_CFG_CLK_EN - Reserved - 0 - 1 - read-write - - - REG_MIPI_DSI_DPHY_PLL_REFCLK_EN - Reserved - 1 - 1 - read-write - - - REG_MIPI_CSI_DPHY_CLK_SRC_SEL - Reserved - 2 - 2 - read-write - - - REG_MIPI_CSI_DPHY_CFG_CLK_EN - Reserved - 4 - 1 - read-write - - - REG_MIPI_DSI_DPICLK_SRC_SEL - Reserved - 5 - 2 - read-write - - - REG_MIPI_DSI_DPICLK_EN - Reserved - 7 - 1 - read-write - - - REG_MIPI_DSI_DPICLK_DIV_NUM - Reserved - 8 - 8 - read-write - - - - - PERI_CLK_CTRL10 - Reserved - 0x40 - 0x20 - - - REG_I2C0_CLK_SRC_SEL - Reserved - 0 - 1 - read-write - - - REG_I2C0_CLK_EN - Reserved - 1 - 1 - read-write - - - REG_I2C0_CLK_DIV_NUM - Reserved - 2 - 8 - read-write - - - REG_I2C0_CLK_DIV_NUMERATOR - Reserved - 10 - 8 - read-write - - - REG_I2C0_CLK_DIV_DENOMINATOR - Reserved - 18 - 8 - read-write - - - REG_I2C1_CLK_SRC_SEL - Reserved - 26 - 1 - read-write - - - REG_I2C1_CLK_EN - Reserved - 27 - 1 - read-write - - - - - PERI_CLK_CTRL11 - Reserved - 0x44 - 0x20 - - - REG_I2C1_CLK_DIV_NUM - Reserved - 0 - 8 - read-write - - - REG_I2C1_CLK_DIV_NUMERATOR - Reserved - 8 - 8 - read-write - - - REG_I2C1_CLK_DIV_DENOMINATOR - Reserved - 16 - 8 - read-write - - - REG_I2S0_RX_CLK_EN - Reserved - 24 - 1 - read-write - - - REG_I2S0_RX_CLK_SRC_SEL - Reserved - 25 - 2 - read-write - - - - - PERI_CLK_CTRL12 - Reserved - 0x48 - 0x20 - - - REG_I2S0_RX_DIV_N - Reserved - 0 - 8 - read-write - - - REG_I2S0_RX_DIV_X - Reserved - 8 - 9 - read-write - - - REG_I2S0_RX_DIV_Y - Reserved - 17 - 9 - read-write - - - - - PERI_CLK_CTRL13 - Reserved - 0x4C - 0x20 - - - REG_I2S0_RX_DIV_Z - Reserved - 0 - 9 - read-write - - - REG_I2S0_RX_DIV_YN1 - Reserved - 9 - 1 - read-write - - - REG_I2S0_TX_CLK_EN - Reserved - 10 - 1 - read-write - - - REG_I2S0_TX_CLK_SRC_SEL - Reserved - 11 - 2 - read-write - - - REG_I2S0_TX_DIV_N - Reserved - 13 - 8 - read-write - - - REG_I2S0_TX_DIV_X - Reserved - 21 - 9 - read-write - - - - - PERI_CLK_CTRL14 - Reserved - 0x50 - 0x20 - - - REG_I2S0_TX_DIV_Y - Reserved - 0 - 9 - read-write - - - REG_I2S0_TX_DIV_Z - Reserved - 9 - 9 - read-write - - - REG_I2S0_TX_DIV_YN1 - Reserved - 18 - 1 - read-write - - - REG_I2S0_MST_CLK_SEL - Reserved - 19 - 1 - read-write - - - REG_I2S1_RX_CLK_EN - Reserved - 20 - 1 - read-write - - - REG_I2S1_RX_CLK_SRC_SEL - Reserved - 21 - 2 - read-write - - - REG_I2S1_RX_DIV_N - Reserved - 23 - 8 - read-write - - - - - PERI_CLK_CTRL15 - Reserved - 0x54 - 0x20 - - - REG_I2S1_RX_DIV_X - Reserved - 0 - 9 - read-write - - - REG_I2S1_RX_DIV_Y - Reserved - 9 - 9 - read-write - - - REG_I2S1_RX_DIV_Z - Reserved - 18 - 9 - read-write - - - REG_I2S1_RX_DIV_YN1 - Reserved - 27 - 1 - read-write - - - REG_I2S1_TX_CLK_EN - Reserved - 28 - 1 - read-write - - - REG_I2S1_TX_CLK_SRC_SEL - Reserved - 29 - 2 - read-write - - - - - PERI_CLK_CTRL16 - Reserved - 0x58 - 0x20 - - - REG_I2S1_TX_DIV_N - Reserved - 0 - 8 - read-write - - - REG_I2S1_TX_DIV_X - Reserved - 8 - 9 - read-write - - - REG_I2S1_TX_DIV_Y - Reserved - 17 - 9 - read-write - - - - - PERI_CLK_CTRL17 - Reserved - 0x5C - 0x20 - - - REG_I2S1_TX_DIV_Z - Reserved - 0 - 9 - read-write - - - REG_I2S1_TX_DIV_YN1 - Reserved - 9 - 1 - read-write - - - REG_I2S1_MST_CLK_SEL - Reserved - 10 - 1 - read-write - - - REG_I2S2_RX_CLK_EN - Reserved - 11 - 1 - read-write - - - REG_I2S2_RX_CLK_SRC_SEL - Reserved - 12 - 2 - read-write - - - REG_I2S2_RX_DIV_N - Reserved - 14 - 8 - read-write - - - REG_I2S2_RX_DIV_X - Reserved - 22 - 9 - read-write - - - - - PERI_CLK_CTRL18 - Reserved - 0x60 - 0x20 - - - REG_I2S2_RX_DIV_Y - Reserved - 0 - 9 - read-write - - - REG_I2S2_RX_DIV_Z - Reserved - 9 - 9 - read-write - - - REG_I2S2_RX_DIV_YN1 - Reserved - 18 - 1 - read-write - - - REG_I2S2_TX_CLK_EN - Reserved - 19 - 1 - read-write - - - REG_I2S2_TX_CLK_SRC_SEL - Reserved - 20 - 2 - read-write - - - REG_I2S2_TX_DIV_N - Reserved - 22 - 8 - read-write - - - - - PERI_CLK_CTRL19 - Reserved - 0x64 - 0x20 - - - REG_I2S2_TX_DIV_X - Reserved - 0 - 9 - read-write - - - REG_I2S2_TX_DIV_Y - Reserved - 9 - 9 - read-write - - - REG_I2S2_TX_DIV_Z - Reserved - 18 - 9 - read-write - - - REG_I2S2_TX_DIV_YN1 - Reserved - 27 - 1 - read-write - - - REG_I2S2_MST_CLK_SEL - Reserved - 28 - 1 - read-write - - - REG_LCD_CLK_SRC_SEL - Reserved - 29 - 2 - read-write - - - REG_LCD_CLK_EN - Reserved - 31 - 1 - read-write - - - - - PERI_CLK_CTRL110 - Reserved - 0x68 - 0x20 - 0x04000000 - - - REG_LCD_CLK_DIV_NUM - Reserved - 0 - 8 - read-write - - - REG_LCD_CLK_DIV_NUMERATOR - Reserved - 8 - 8 - read-write - - - REG_LCD_CLK_DIV_DENOMINATOR - Reserved - 16 - 8 - read-write - - - REG_UART0_CLK_SRC_SEL - Reserved - 24 - 2 - read-write - - - REG_UART0_CLK_EN - Reserved - 26 - 1 - read-write - - - - - PERI_CLK_CTRL111 - Reserved - 0x6C - 0x20 - 0x04000000 - - - REG_UART0_SCLK_DIV_NUM - Reserved - 0 - 8 - read-write - - - REG_UART0_SCLK_DIV_NUMERATOR - Reserved - 8 - 8 - read-write - - - REG_UART0_SCLK_DIV_DENOMINATOR - Reserved - 16 - 8 - read-write - - - REG_UART1_CLK_SRC_SEL - Reserved - 24 - 2 - read-write - - - REG_UART1_CLK_EN - Reserved - 26 - 1 - read-write - - - - - PERI_CLK_CTRL112 - Reserved - 0x70 - 0x20 - 0x04000000 - - - REG_UART1_SCLK_DIV_NUM - Reserved - 0 - 8 - read-write - - - REG_UART1_SCLK_DIV_NUMERATOR - Reserved - 8 - 8 - read-write - - - REG_UART1_SCLK_DIV_DENOMINATOR - Reserved - 16 - 8 - read-write - - - REG_UART2_CLK_SRC_SEL - Reserved - 24 - 2 - read-write - - - REG_UART2_CLK_EN - Reserved - 26 - 1 - read-write - - - - - PERI_CLK_CTRL113 - Reserved - 0x74 - 0x20 - 0x04000000 - - - REG_UART2_SCLK_DIV_NUM - Reserved - 0 - 8 - read-write - - - REG_UART2_SCLK_DIV_NUMERATOR - Reserved - 8 - 8 - read-write - - - REG_UART2_SCLK_DIV_DENOMINATOR - Reserved - 16 - 8 - read-write - - - REG_UART3_CLK_SRC_SEL - Reserved - 24 - 2 - read-write - - - REG_UART3_CLK_EN - Reserved - 26 - 1 - read-write - - - - - PERI_CLK_CTRL114 - Reserved - 0x78 - 0x20 - 0x04000000 - - - REG_UART3_SCLK_DIV_NUM - Reserved - 0 - 8 - read-write - - - REG_UART3_SCLK_DIV_NUMERATOR - Reserved - 8 - 8 - read-write - - - REG_UART3_SCLK_DIV_DENOMINATOR - Reserved - 16 - 8 - read-write - - - REG_UART4_CLK_SRC_SEL - Reserved - 24 - 2 - read-write - - - REG_UART4_CLK_EN - Reserved - 26 - 1 - read-write - - - - - PERI_CLK_CTRL115 - Reserved - 0x7C - 0x20 - - - REG_UART4_SCLK_DIV_NUM - Reserved - 0 - 8 - read-write - - - REG_UART4_SCLK_DIV_NUMERATOR - Reserved - 8 - 8 - read-write - - - REG_UART4_SCLK_DIV_DENOMINATOR - Reserved - 16 - 8 - read-write - - - REG_TWAI0_CLK_SRC_SEL - Reserved - 24 - 1 - read-write - - - REG_TWAI0_CLK_EN - Reserved - 25 - 1 - read-write - - - REG_TWAI1_CLK_SRC_SEL - Reserved - 26 - 1 - read-write - - - REG_TWAI1_CLK_EN - Reserved - 27 - 1 - read-write - - - REG_TWAI2_CLK_SRC_SEL - Reserved - 28 - 1 - read-write - - - REG_TWAI2_CLK_EN - Reserved - 29 - 1 - read-write - - - - - PERI_CLK_CTRL116 - Reserved - 0x80 - 0x20 - 0x01100008 - - - REG_GPSPI2_CLK_SRC_SEL - Reserved - 0 - 3 - read-write - - - REG_GPSPI2_HS_CLK_EN - Reserved - 3 - 1 - read-write - - - REG_GPSPI2_HS_CLK_DIV_NUM - Reserved - 4 - 8 - read-write - - - REG_GPSPI2_MST_CLK_DIV_NUM - Reserved - 12 - 8 - read-write - - - REG_GPSPI2_MST_CLK_EN - Reserved - 20 - 1 - read-write - - - REG_GPSPI3_CLK_SRC_SEL - Reserved - 21 - 3 - read-write - - - REG_GPSPI3_HS_CLK_EN - Reserved - 24 - 1 - read-write - - - - - PERI_CLK_CTRL117 - Reserved - 0x84 - 0x20 - 0x00010000 - - - REG_GPSPI3_HS_CLK_DIV_NUM - Reserved - 0 - 8 - read-write - - - REG_GPSPI3_MST_CLK_DIV_NUM - Reserved - 8 - 8 - read-write - - - REG_GPSPI3_MST_CLK_EN - Reserved - 16 - 1 - read-write - - - REG_PARLIO_RX_CLK_SRC_SEL - Reserved - 17 - 2 - read-write - - - REG_PARLIO_RX_CLK_EN - Reserved - 19 - 1 - read-write - - - REG_PARLIO_RX_CLK_DIV_NUM - Reserved - 20 - 8 - read-write - - - - - PERI_CLK_CTRL118 - Reserved - 0x88 - 0x20 - - - REG_PARLIO_RX_CLK_DIV_NUMERATOR - Reserved - 0 - 8 - read-write - - - REG_PARLIO_RX_CLK_DIV_DENOMINATOR - Reserved - 8 - 8 - read-write - - - REG_PARLIO_TX_CLK_SRC_SEL - Reserved - 16 - 2 - read-write - - - REG_PARLIO_TX_CLK_EN - Reserved - 18 - 1 - read-write - - - REG_PARLIO_TX_CLK_DIV_NUM - Reserved - 19 - 8 - read-write - - - - - PERI_CLK_CTRL119 - Reserved - 0x8C - 0x20 - - - REG_PARLIO_TX_CLK_DIV_NUMERATOR - Reserved - 0 - 8 - read-write - - - REG_PARLIO_TX_CLK_DIV_DENOMINATOR - Reserved - 8 - 8 - read-write - - - REG_I3C_MST_CLK_SRC_SEL - Reserved - 16 - 2 - read-write - - - REG_I3C_MST_CLK_EN - Reserved - 18 - 1 - read-write - - - REG_I3C_MST_CLK_DIV_NUM - Reserved - 19 - 8 - read-write - - - REG_CAM_CLK_SRC_SEL - Reserved - 27 - 2 - read-write - - - REG_CAM_CLK_EN - Reserved - 29 - 1 - read-write - - - - - PERI_CLK_CTRL120 - Reserved - 0x90 - 0x20 - - - REG_CAM_CLK_DIV_NUM - Reserved - 0 - 8 - read-write - - - REG_CAM_CLK_DIV_NUMERATOR - Reserved - 8 - 8 - read-write - - - REG_CAM_CLK_DIV_DENOMINATOR - Reserved - 16 - 8 - read-write - - - - - PERI_CLK_CTRL20 - Reserved - 0x94 - 0x20 - 0xC9000000 - - - REG_MCPWM0_CLK_SRC_SEL - Reserved - 0 - 2 - read-write - - - REG_MCPWM0_CLK_EN - Reserved - 2 - 1 - read-write - - - REG_MCPWM0_CLK_DIV_NUM - Reserved - 3 - 8 - read-write - - - REG_MCPWM1_CLK_SRC_SEL - Reserved - 11 - 2 - read-write - - - REG_MCPWM1_CLK_EN - Reserved - 13 - 1 - read-write - - - REG_MCPWM1_CLK_DIV_NUM - Reserved - 14 - 8 - read-write - - - REG_TIMERGRP0_T0_SRC_SEL - Reserved - 22 - 2 - read-write - - - REG_TIMERGRP0_T0_CLK_EN - Reserved - 24 - 1 - read-write - - - REG_TIMERGRP0_T1_SRC_SEL - Reserved - 25 - 2 - read-write - - - REG_TIMERGRP0_T1_CLK_EN - Reserved - 27 - 1 - read-write - - - REG_TIMERGRP0_WDT_SRC_SEL - Reserved - 28 - 2 - read-write - - - REG_TIMERGRP0_WDT_CLK_EN - Reserved - 30 - 1 - read-write - - - REG_TIMERGRP0_TGRT_CLK_EN - Reserved - 31 - 1 - read-write - - - - - PERI_CLK_CTRL21 - Reserved - 0x98 - 0x20 - 0x52400000 - - - REG_TIMERGRP0_TGRT_CLK_SRC_SEL - Reserved - 0 - 4 - read-write - - - REG_TIMERGRP0_TGRT_CLK_DIV_NUM - Reserved - 4 - 16 - read-write - - - REG_TIMERGRP1_T0_SRC_SEL - Reserved - 20 - 2 - read-write - - - REG_TIMERGRP1_T0_CLK_EN - Reserved - 22 - 1 - read-write - - - REG_TIMERGRP1_T1_SRC_SEL - Reserved - 23 - 2 - read-write - - - REG_TIMERGRP1_T1_CLK_EN - Reserved - 25 - 1 - read-write - - - REG_TIMERGRP1_WDT_SRC_SEL - Reserved - 26 - 2 - read-write - - - REG_TIMERGRP1_WDT_CLK_EN - Reserved - 28 - 1 - read-write - - - REG_SYSTIMER_CLK_SRC_SEL - Reserved - 29 - 1 - read-write - - - REG_SYSTIMER_CLK_EN - Reserved - 30 - 1 - read-write - - - - - PERI_CLK_CTRL22 - Reserved - 0x9C - 0x20 - - - REG_LEDC_CLK_SRC_SEL - Reserved - 0 - 2 - read-write - - - REG_LEDC_CLK_EN - Reserved - 2 - 1 - read-write - - - REG_RMT_CLK_SRC_SEL - Reserved - 3 - 2 - read-write - - - REG_RMT_CLK_EN - Reserved - 5 - 1 - read-write - - - REG_RMT_CLK_DIV_NUM - Reserved - 6 - 8 - read-write - - - REG_RMT_CLK_DIV_NUMERATOR - Reserved - 14 - 8 - read-write - - - REG_RMT_CLK_DIV_DENOMINATOR - Reserved - 22 - 8 - read-write - - - REG_ADC_CLK_SRC_SEL - Reserved - 30 - 2 - read-write - - - - - PERI_CLK_CTRL23 - Reserved - 0xA0 - 0x20 - 0x00000008 - - - REG_ADC_CLK_EN - Reserved - 0 - 1 - read-write - - - REG_ADC_CLK_DIV_NUM - Reserved - 1 - 8 - read-write - - - REG_ADC_CLK_DIV_NUMERATOR - Reserved - 9 - 8 - read-write - - - REG_ADC_CLK_DIV_DENOMINATOR - Reserved - 17 - 8 - read-write - - - - - PERI_CLK_CTRL24 - Reserved - 0xA4 - 0x20 - 0x00000404 - - - REG_ADC_SAR1_CLK_DIV_NUM - Reserved - 0 - 8 - read-write - - - REG_ADC_SAR2_CLK_DIV_NUM - Reserved - 8 - 8 - read-write - - - REG_PVT_CLK_DIV_NUM - Reserved - 16 - 8 - read-write - - - REG_PVT_CLK_EN - Reserved - 24 - 1 - read-write - - - - - PERI_CLK_CTRL25 - Reserved - 0xA8 - 0x20 - 0x007FC000 - - - REG_PVT_PERI_GROUP_CLK_DIV_NUM - Reserved - 0 - 8 - read-write - - - REG_PVT_PERI_GROUP1_CLK_EN - Reserved - 8 - 1 - read-write - - - REG_PVT_PERI_GROUP2_CLK_EN - Reserved - 9 - 1 - read-write - - - REG_PVT_PERI_GROUP3_CLK_EN - Reserved - 10 - 1 - read-write - - - REG_PVT_PERI_GROUP4_CLK_EN - Reserved - 11 - 1 - read-write - - - REG_CRYPTO_CLK_SRC_SEL - Reserved - 12 - 2 - read-write - - - REG_CRYPTO_AES_CLK_EN - Reserved - 14 - 1 - read-write - - - REG_CRYPTO_DS_CLK_EN - Reserved - 15 - 1 - read-write - - - REG_CRYPTO_ECC_CLK_EN - Reserved - 16 - 1 - read-write - - - REG_CRYPTO_HMAC_CLK_EN - Reserved - 17 - 1 - read-write - - - REG_CRYPTO_RSA_CLK_EN - Reserved - 18 - 1 - read-write - - - REG_CRYPTO_SEC_CLK_EN - Reserved - 19 - 1 - read-write - - - REG_CRYPTO_SHA_CLK_EN - Reserved - 20 - 1 - read-write - - - REG_CRYPTO_ECDSA_CLK_EN - Reserved - 21 - 1 - read-write - - - REG_CRYPTO_KM_CLK_EN - Reserved - 22 - 1 - read-write - - - REG_ISP_CLK_SRC_SEL - Reserved - 23 - 2 - read-write - - - REG_ISP_CLK_EN - Reserved - 25 - 1 - read-write - - - - - PERI_CLK_CTRL26 - Reserved - 0xAC - 0x20 - 0x00000200 - - - REG_ISP_CLK_DIV_NUM - Reserved - 0 - 8 - read-write - - - REG_IOMUX_CLK_SRC_SEL - Reserved - 8 - 1 - read-write - - - REG_IOMUX_CLK_EN - Reserved - 9 - 1 - read-write - - - REG_IOMUX_CLK_DIV_NUM - Reserved - 10 - 8 - read-write - - - REG_H264_CLK_SRC_SEL - Reserved - 18 - 1 - read-write - - - REG_H264_CLK_EN - Reserved - 19 - 1 - read-write - - - REG_H264_CLK_DIV_NUM - Reserved - 20 - 8 - read-write - - - REG_PADBIST_RX_CLK_SRC_SEL - Reserved - 28 - 1 - read-write - - - REG_PADBIST_RX_CLK_EN - Reserved - 29 - 1 - read-write - - - - - PERI_CLK_CTRL27 - Reserved - 0xB0 - 0x20 - - - REG_PADBIST_RX_CLK_DIV_NUM - Reserved - 0 - 8 - read-write - - - REG_PADBIST_TX_CLK_SRC_SEL - Reserved - 8 - 1 - read-write - - - REG_PADBIST_TX_CLK_EN - Reserved - 9 - 1 - read-write - - - REG_PADBIST_TX_CLK_DIV_NUM - Reserved - 10 - 8 - read-write - - - - - CLK_FORCE_ON_CTRL0 - Reserved - 0xB4 - 0x20 - 0x0003FFFF - - - REG_CPUICM_GATED_CLK_FORCE_ON - Reserved - 0 - 1 - read-write - - - REG_TCM_CPU_CLK_FORCE_ON - Reserved - 1 - 1 - read-write - - - REG_BUSMON_CPU_CLK_FORCE_ON - Reserved - 2 - 1 - read-write - - - REG_L1CACHE_CPU_CLK_FORCE_ON - Reserved - 3 - 1 - read-write - - - REG_L1CACHE_D_CPU_CLK_FORCE_ON - Reserved - 4 - 1 - read-write - - - REG_L1CACHE_I0_CPU_CLK_FORCE_ON - Reserved - 5 - 1 - read-write - - - REG_L1CACHE_I1_CPU_CLK_FORCE_ON - Reserved - 6 - 1 - read-write - - - REG_TRACE_CPU_CLK_FORCE_ON - Reserved - 7 - 1 - read-write - - - REG_TRACE_SYS_CLK_FORCE_ON - Reserved - 8 - 1 - read-write - - - REG_L1CACHE_MEM_CLK_FORCE_ON - Reserved - 9 - 1 - read-write - - - REG_L1CACHE_D_MEM_CLK_FORCE_ON - Reserved - 10 - 1 - read-write - - - REG_L1CACHE_I0_MEM_CLK_FORCE_ON - Reserved - 11 - 1 - read-write - - - REG_L1CACHE_I1_MEM_CLK_FORCE_ON - Reserved - 12 - 1 - read-write - - - REG_L2CACHE_MEM_CLK_FORCE_ON - Reserved - 13 - 1 - read-write - - - REG_L2MEM_MEM_CLK_FORCE_ON - Reserved - 14 - 1 - read-write - - - REG_SAR1_CLK_FORCE_ON - Reserved - 15 - 1 - read-write - - - REG_SAR2_CLK_FORCE_ON - Reserved - 16 - 1 - read-write - - - REG_GMAC_TX_CLK_FORCE_ON - Reserved - 17 - 1 - read-write - - - - - DPA_CTRL0 - Reserved - 0xB8 - 0x20 - - - REG_SEC_DPA_LEVEL - Reserved - 0 - 2 - read-write - - - REG_SEC_DPA_CFG_SEL - Reserved - 2 - 1 - read-write - - - - - ANA_PLL_CTRL0 - Reserved - 0xBC - 0x20 - - - REG_PLLA_CAL_END - Reserved - 0 - 1 - read-only - - - REG_PLLA_CAL_STOP - Reserved - 1 - 1 - read-write - - - REG_CPU_PLL_CAL_END - Reserved - 2 - 1 - read-only - - - REG_CPU_PLL_CAL_STOP - Reserved - 3 - 1 - read-write - - - REG_SDIO_PLL_CAL_END - Reserved - 4 - 1 - read-only - - - REG_SDIO_PLL_CAL_STOP - Reserved - 5 - 1 - read-write - - - REG_SYS_PLL_CAL_END - Reserved - 6 - 1 - read-only - - - REG_SYS_PLL_CAL_STOP - Reserved - 7 - 1 - read-write - - - REG_MSPI_CAL_END - Reserved - 8 - 1 - read-only - - - REG_MSPI_CAL_STOP - Reserved - 9 - 1 - read-write - - - - - HP_RST_EN0 - Reserved - 0xC0 - 0x20 - 0x00000100 - - - REG_RST_EN_CORECTRL - Reserved - 0 - 1 - read-write - - - REG_RST_EN_PVT_TOP - Reserved - 1 - 1 - read-write - - - REG_RST_EN_PVT_PERI_GROUP1 - Reserved - 2 - 1 - read-write - - - REG_RST_EN_PVT_PERI_GROUP2 - Reserved - 3 - 1 - read-write - - - REG_RST_EN_PVT_PERI_GROUP3 - Reserved - 4 - 1 - read-write - - - REG_RST_EN_PVT_PERI_GROUP4 - Reserved - 5 - 1 - read-write - - - REG_RST_EN_REGDMA - Reserved - 6 - 1 - read-write - - - REG_RST_EN_CORE0_GLOBAL - Reserved - 7 - 1 - read-write - - - REG_RST_EN_CORE1_GLOBAL - Reserved - 8 - 1 - read-write - - - REG_RST_EN_CORETRACE0 - Reserved - 9 - 1 - read-write - - - REG_RST_EN_CORETRACE1 - Reserved - 10 - 1 - read-write - - - REG_RST_EN_HP_TCM - Reserved - 11 - 1 - read-write - - - REG_RST_EN_HP_CACHE - Reserved - 12 - 1 - read-write - - - REG_RST_EN_L1_I0_CACHE - Reserved - 13 - 1 - read-write - - - REG_RST_EN_L1_I1_CACHE - Reserved - 14 - 1 - read-write - - - REG_RST_EN_L1_D_CACHE - Reserved - 15 - 1 - read-write - - - REG_RST_EN_L2_CACHE - Reserved - 16 - 1 - read-write - - - REG_RST_EN_L2_MEM - Reserved - 17 - 1 - read-write - - - REG_RST_EN_L2MEMMON - Reserved - 18 - 1 - read-write - - - REG_RST_EN_TCMMON - Reserved - 19 - 1 - read-write - - - REG_RST_EN_PVT_APB - Reserved - 20 - 1 - read-write - - - REG_RST_EN_GDMA - Reserved - 21 - 1 - read-write - - - REG_RST_EN_MSPI_AXI - Reserved - 22 - 1 - read-write - - - REG_RST_EN_DUAL_MSPI_AXI - Reserved - 23 - 1 - read-write - - - REG_RST_EN_MSPI_APB - Reserved - 24 - 1 - read-write - - - REG_RST_EN_DUAL_MSPI_APB - Reserved - 25 - 1 - read-write - - - REG_RST_EN_DSI_BRG - Reserved - 26 - 1 - read-write - - - REG_RST_EN_CSI_HOST - Reserved - 27 - 1 - read-write - - - REG_RST_EN_CSI_BRG - Reserved - 28 - 1 - read-write - - - REG_RST_EN_ISP - Reserved - 29 - 1 - read-write - - - REG_RST_EN_JPEG - Reserved - 30 - 1 - read-write - - - REG_RST_EN_DMA2D - Reserved - 31 - 1 - read-write - - - - - HP_RST_EN1 - Reserved - 0xC4 - 0x20 - - - REG_RST_EN_PPA - Reserved - 0 - 1 - read-write - - - REG_RST_EN_AHB_PDMA - Reserved - 1 - 1 - read-write - - - REG_RST_EN_AXI_PDMA - Reserved - 2 - 1 - read-write - - - REG_RST_EN_IOMUX - Reserved - 3 - 1 - read-write - - - REG_RST_EN_PADBIST - Reserved - 4 - 1 - read-write - - - REG_RST_EN_STIMER - Reserved - 5 - 1 - read-write - - - REG_RST_EN_TIMERGRP0 - Reserved - 6 - 1 - read-write - - - REG_RST_EN_TIMERGRP1 - Reserved - 7 - 1 - read-write - - - REG_RST_EN_UART0_CORE - Reserved - 8 - 1 - read-write - - - REG_RST_EN_UART1_CORE - Reserved - 9 - 1 - read-write - - - REG_RST_EN_UART2_CORE - Reserved - 10 - 1 - read-write - - - REG_RST_EN_UART3_CORE - Reserved - 11 - 1 - read-write - - - REG_RST_EN_UART4_CORE - Reserved - 12 - 1 - read-write - - - REG_RST_EN_UART0_APB - Reserved - 13 - 1 - read-write - - - REG_RST_EN_UART1_APB - Reserved - 14 - 1 - read-write - - - REG_RST_EN_UART2_APB - Reserved - 15 - 1 - read-write - - - REG_RST_EN_UART3_APB - Reserved - 16 - 1 - read-write - - - REG_RST_EN_UART4_APB - Reserved - 17 - 1 - read-write - - - REG_RST_EN_UHCI - Reserved - 18 - 1 - read-write - - - REG_RST_EN_I3CMST - Reserved - 19 - 1 - read-write - - - REG_RST_EN_I3CSLV - Reserved - 20 - 1 - read-write - - - REG_RST_EN_I2C1 - Reserved - 21 - 1 - read-write - - - REG_RST_EN_I2C0 - Reserved - 22 - 1 - read-write - - - REG_RST_EN_RMT - Reserved - 23 - 1 - read-write - - - REG_RST_EN_PWM0 - Reserved - 24 - 1 - read-write - - - REG_RST_EN_PWM1 - Reserved - 25 - 1 - read-write - - - REG_RST_EN_CAN0 - Reserved - 26 - 1 - read-write - - - REG_RST_EN_CAN1 - Reserved - 27 - 1 - read-write - - - REG_RST_EN_CAN2 - Reserved - 28 - 1 - read-write - - - REG_RST_EN_LEDC - Reserved - 29 - 1 - read-write - - - REG_RST_EN_PCNT - Reserved - 30 - 1 - read-write - - - REG_RST_EN_ETM - Reserved - 31 - 1 - read-write - - - - - HP_RST_EN2 - Reserved - 0xC8 - 0x20 - - - REG_RST_EN_INTRMTX - Reserved - 0 - 1 - read-write - - - REG_RST_EN_PARLIO - Reserved - 1 - 1 - read-write - - - REG_RST_EN_PARLIO_RX - Reserved - 2 - 1 - read-write - - - REG_RST_EN_PARLIO_TX - Reserved - 3 - 1 - read-write - - - REG_RST_EN_I2S0_APB - Reserved - 4 - 1 - read-write - - - REG_RST_EN_I2S1_APB - Reserved - 5 - 1 - read-write - - - REG_RST_EN_I2S2_APB - Reserved - 6 - 1 - read-write - - - REG_RST_EN_SPI2 - Reserved - 7 - 1 - read-write - - - REG_RST_EN_SPI3 - Reserved - 8 - 1 - read-write - - - REG_RST_EN_LCDCAM - Reserved - 9 - 1 - read-write - - - REG_RST_EN_ADC - Reserved - 10 - 1 - read-write - - - REG_RST_EN_BITSRAMBLER - Reserved - 11 - 1 - read-write - - - REG_RST_EN_BITSRAMBLER_RX - Reserved - 12 - 1 - read-write - - - REG_RST_EN_BITSRAMBLER_TX - Reserved - 13 - 1 - read-write - - - REG_RST_EN_CRYPTO - Reserved - 14 - 1 - read-write - - - REG_RST_EN_SEC - Reserved - 15 - 1 - read-write - - - REG_RST_EN_AES - Reserved - 16 - 1 - read-write - - - REG_RST_EN_DS - Reserved - 17 - 1 - read-write - - - REG_RST_EN_SHA - Reserved - 18 - 1 - read-write - - - REG_RST_EN_HMAC - Reserved - 19 - 1 - read-write - - - REG_RST_EN_ECDSA - Reserved - 20 - 1 - read-write - - - REG_RST_EN_RSA - Reserved - 21 - 1 - read-write - - - REG_RST_EN_ECC - Reserved - 22 - 1 - read-write - - - REG_RST_EN_KM - Reserved - 23 - 1 - read-write - - - REG_RST_EN_H264 - Reserved - 24 - 1 - read-write - - - - - HP_FORCE_NORST0 - Reserved - 0xCC - 0x20 - - - REG_FORCE_NORST_CORE0 - Reserved - 0 - 1 - read-write - - - REG_FORCE_NORST_CORE1 - Reserved - 1 - 1 - read-write - - - REG_FORCE_NORST_CORETRACE0 - Reserved - 2 - 1 - read-write - - - REG_FORCE_NORST_CORETRACE1 - Reserved - 3 - 1 - read-write - - - REG_FORCE_NORST_L2MEMMON - Reserved - 4 - 1 - read-write - - - REG_FORCE_NORST_TCMMON - Reserved - 5 - 1 - read-write - - - REG_FORCE_NORST_GDMA - Reserved - 6 - 1 - read-write - - - REG_FORCE_NORST_MSPI_AXI - Reserved - 7 - 1 - read-write - - - REG_FORCE_NORST_DUAL_MSPI_AXI - Reserved - 8 - 1 - read-write - - - REG_FORCE_NORST_MSPI_APB - Reserved - 9 - 1 - read-write - - - REG_FORCE_NORST_DUAL_MSPI_APB - Reserved - 10 - 1 - read-write - - - REG_FORCE_NORST_DSI_BRG - Reserved - 11 - 1 - read-write - - - REG_FORCE_NORST_CSI_HOST - Reserved - 12 - 1 - read-write - - - REG_FORCE_NORST_CSI_BRG - Reserved - 13 - 1 - read-write - - - REG_FORCE_NORST_ISP - Reserved - 14 - 1 - read-write - - - REG_FORCE_NORST_JPEG - Reserved - 15 - 1 - read-write - - - REG_FORCE_NORST_DMA2D - Reserved - 16 - 1 - read-write - - - REG_FORCE_NORST_PPA - Reserved - 17 - 1 - read-write - - - REG_FORCE_NORST_AHB_PDMA - Reserved - 18 - 1 - read-write - - - REG_FORCE_NORST_AXI_PDMA - Reserved - 19 - 1 - read-write - - - REG_FORCE_NORST_IOMUX - Reserved - 20 - 1 - read-write - - - REG_FORCE_NORST_PADBIST - Reserved - 21 - 1 - read-write - - - REG_FORCE_NORST_STIMER - Reserved - 22 - 1 - read-write - - - REG_FORCE_NORST_TIMERGRP0 - Reserved - 23 - 1 - read-write - - - REG_FORCE_NORST_TIMERGRP1 - Reserved - 24 - 1 - read-write - - - REG_FORCE_NORST_UART0 - Reserved - 25 - 1 - read-write - - - REG_FORCE_NORST_UART1 - Reserved - 26 - 1 - read-write - - - REG_FORCE_NORST_UART2 - Reserved - 27 - 1 - read-write - - - REG_FORCE_NORST_UART3 - Reserved - 28 - 1 - read-write - - - REG_FORCE_NORST_UART4 - Reserved - 29 - 1 - read-write - - - REG_FORCE_NORST_UHCI - Reserved - 30 - 1 - read-write - - - REG_FORCE_NORST_I3CMST - Reserved - 31 - 1 - read-write - - - - - HP_FORCE_NORST1 - Reserved - 0xD0 - 0x20 - - - REG_FORCE_NORST_I3CSLV - Reserved - 0 - 1 - read-write - - - REG_FORCE_NORST_I2C1 - Reserved - 1 - 1 - read-write - - - REG_FORCE_NORST_I2C0 - Reserved - 2 - 1 - read-write - - - REG_FORCE_NORST_RMT - Reserved - 3 - 1 - read-write - - - REG_FORCE_NORST_PWM0 - Reserved - 4 - 1 - read-write - - - REG_FORCE_NORST_PWM1 - Reserved - 5 - 1 - read-write - - - REG_FORCE_NORST_CAN0 - Reserved - 6 - 1 - read-write - - - REG_FORCE_NORST_CAN1 - Reserved - 7 - 1 - read-write - - - REG_FORCE_NORST_CAN2 - Reserved - 8 - 1 - read-write - - - REG_FORCE_NORST_LEDC - Reserved - 9 - 1 - read-write - - - REG_FORCE_NORST_PCNT - Reserved - 10 - 1 - read-write - - - REG_FORCE_NORST_ETM - Reserved - 11 - 1 - read-write - - - REG_FORCE_NORST_INTRMTX - Reserved - 12 - 1 - read-write - - - REG_FORCE_NORST_PARLIO - Reserved - 13 - 1 - read-write - - - REG_FORCE_NORST_PARLIO_RX - Reserved - 14 - 1 - read-write - - - REG_FORCE_NORST_PARLIO_TX - Reserved - 15 - 1 - read-write - - - REG_FORCE_NORST_I2S0 - Reserved - 16 - 1 - read-write - - - REG_FORCE_NORST_I2S1 - Reserved - 17 - 1 - read-write - - - REG_FORCE_NORST_I2S2 - Reserved - 18 - 1 - read-write - - - REG_FORCE_NORST_SPI2 - Reserved - 19 - 1 - read-write - - - REG_FORCE_NORST_SPI3 - Reserved - 20 - 1 - read-write - - - REG_FORCE_NORST_LCDCAM - Reserved - 21 - 1 - read-write - - - REG_FORCE_NORST_ADC - Reserved - 22 - 1 - read-write - - - REG_FORCE_NORST_BITSRAMBLER - Reserved - 23 - 1 - read-write - - - REG_FORCE_NORST_BITSRAMBLER_RX - Reserved - 24 - 1 - read-write - - - REG_FORCE_NORST_BITSRAMBLER_TX - Reserved - 25 - 1 - read-write - - - REG_FORCE_NORST_H264 - Reserved - 26 - 1 - read-write - - - - - HPWDT_CORE0_RST_CTRL0 - Reserved - 0xD4 - 0x20 - 0x00001011 - - - REG_HPCORE0_STALL_EN - Reserved - 0 - 1 - read-write - - - REG_HPCORE0_STALL_WAIT_NUM - Reserved - 1 - 8 - read-write - - - REG_WDT_HPCORE0_RST_LEN - Reserved - 9 - 8 - read-write - - - - - HPWDT_CORE1_RST_CTRL0 - Reserved - 0xD8 - 0x20 - 0x00001011 - - - REG_HPCORE1_STALL_EN - Reserved - 0 - 1 - read-write - - - REG_HPCORE1_STALL_WAIT_NUM - Reserved - 1 - 8 - read-write - - - REG_WDT_HPCORE1_RST_LEN - Reserved - 9 - 8 - read-write - - - - - CPU_SRC_FREQ0 - CPU Source Frequency - 0xDC - 0x20 - - - REG_CPU_SRC_FREQ - cpu source clock frequency, step by 0.25MHz - 0 - 32 - read-only - - - - - CPU_CLK_STATUS0 - CPU Clock Status - 0xE0 - 0x20 - - - REG_ASIC_OR_FPGA - 0: ASIC mode, 1: FPGA mode - 0 - 1 - read-only - - - REG_CPU_DIV_EFFECT - 0: Divider bypass, 1: Divider takes effect - 1 - 1 - read-only - - - REG_CPU_SRC_IS_CPLL - 0: CPU source isn't cpll_400m, 1: CPU Source is cll_400m - 2 - 1 - read-only - - - REG_CPU_DIV_NUM_CUR - cpu current div number - 3 - 8 - read-only - - - REG_CPU_DIV_NUMERATOR_CUR - cpu current div numerator - 11 - 8 - read-only - - - REG_CPU_DIV_DENOMINATOR_CUR - cpu current div denominator - 19 - 8 - read-only - - - - - DBG_CLK_CTRL0 - Reserved - 0xE4 - 0x20 - 0x03FFFFFF - - - REG_DBG_CH0_SEL - Reserved - 0 - 8 - read-write - - - REG_DBG_CH1_SEL - Reserved - 8 - 8 - read-write - - - REG_DBG_CH2_SEL - Reserved - 16 - 8 - read-write - - - REG_DBG_CH0_DIV_NUM - Reserved - 24 - 8 - read-write - - - - - DBG_CLK_CTRL1 - Reserved - 0xE8 - 0x20 - 0x00000303 - - - REG_DBG_CH1_DIV_NUM - Reserved - 0 - 8 - read-write - - - REG_DBG_CH2_DIV_NUM - Reserved - 8 - 8 - read-write - - - REG_DBG_CH0_EN - Reserved - 16 - 1 - read-write - - - REG_DBG_CH1_EN - Reserved - 17 - 1 - read-write - - - REG_DBG_CH2_EN - Reserved - 18 - 1 - read-write - - - - - HPCORE_WDT_RESET_SOURCE0 - Reserved - 0xEC - 0x20 - 0x00000002 - - - REG_HPCORE0_WDT_RESET_SOURCE_SEL - 1'b0: use wdt0 to reset hpcore0, 1'b1: use wdt1 to reset hpcore0 - 0 - 1 - read-write - - - REG_HPCORE1_WDT_RESET_SOURCE_SEL - 1'b0: use wdt0 to reset hpcore1, 1'b1: use wdt1 to reset hpcore1 - 1 - 1 - read-write - - - - - - - LP_HUK - LP_HUK Peripheral - HUK - 0x50114000 - - 0x0 - 0x1A8 - registers - - - LP_HUK - 20 - - - - CLK - HUK Generator clock gate control register - 0x4 - 0x20 - 0x00000001 - - - EN - Write 1 to force on register clock gate. - 0 - 1 - read-write - - - MEM_CG_FORCE_ON - Write 1 to force on memory clock gate. - 1 - 1 - read-write - - - - - INT_RAW - HUK Generator interrupt raw register, valid in level. - 0x8 - 0x20 - - - PREP_DONE_INT_RAW - The raw interrupt status bit for the huk_prep_done_int interrupt - 0 - 1 - read-only - - - PROC_DONE_INT_RAW - The raw interrupt status bit for the huk_proc_done_int interrupt - 1 - 1 - read-only - - - POST_DONE_INT_RAW - The raw interrupt status bit for the huk_post_done_int interrupt - 2 - 1 - read-only - - - - - INT_ST - HUK Generator interrupt status register. - 0xC - 0x20 - - - PREP_DONE_INT_ST - The masked interrupt status bit for the huk_prep_done_int interrupt - 0 - 1 - read-only - - - PROC_DONE_INT_ST - The masked interrupt status bit for the huk_proc_done_int interrupt - 1 - 1 - read-only - - - POST_DONE_INT_ST - The masked interrupt status bit for the huk_post_done_int interrupt - 2 - 1 - read-only - - - - - INT_ENA - HUK Generator interrupt enable register. - 0x10 - 0x20 - - - PREP_DONE_INT_ENA - The interrupt enable bit for the huk_prep_done_int interrupt - 0 - 1 - read-write - - - PROC_DONE_INT_ENA - The interrupt enable bit for the huk_proc_done_int interrupt - 1 - 1 - read-write - - - POST_DONE_INT_ENA - The interrupt enable bit for the huk_post_done_int interrupt - 2 - 1 - read-write - - - - - INT_CLR - HUK Generator interrupt clear register. - 0x14 - 0x20 - - - PREP_DONE_INT_CLR - Set this bit to clear the huk_prep_done_int interrupt - 0 - 1 - write-only - - - PROC_DONE_INT_CLR - Set this bit to clear the huk_proc_done_int interrupt - 1 - 1 - write-only - - - POST_DONE_INT_CLR - Set this bit to clear the huk_post_done_int interrupt - 2 - 1 - write-only - - - - - CONF - HUK Generator configuration register - 0x20 - 0x20 - - - MODE - Set this field to choose the huk process. 1: process huk generate mode. 0: process huk recovery mode. - 0 - 1 - read-write - - - - - START - HUK Generator control register - 0x24 - 0x20 - - - START - Write 1 to continue HUK Generator operation at LOAD/GAIN state. - 0 - 1 - write-only - - - CONTINUE - Write 1 to start HUK Generator at IDLE state. - 1 - 1 - write-only - - - - - STATE - HUK Generator state register - 0x28 - 0x20 - - - STATE - The state of HUK Generator. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY. - 0 - 2 - read-only - - - - - STATUS - HUK Generator HUK status register - 0x34 - 0x20 - - - STATUS - The HUK generation status. 0: HUK is not generated. 1: HUK is generated and valid. 2: HUK is generated but invalid. 3: reserved. - 0 - 2 - read-only - - - RISK_LEVEL - The risk level of HUK. 0-6: the higher the risk level is, the more error bits there are in the PUF SRAM. 7: Error Level, HUK is invalid. - 2 - 3 - read-only - - - - - DATE - Version control register - 0xFC - 0x20 - 0x02305040 - - - DATE - HUK Generator version control register. - 0 - 28 - read-write - - - - - 96 - 0x4 - INFO_MEM[%s] - The memory that stores HUK info. - 0x100 - 0x20 - - - - - I2C0 - I2C (Inter-Integrated Circuit) Controller 0 - I2C - 0x500C4000 - - 0x0 - 0x90 - registers - - - I2C0 - 44 - - - - SCL_LOW_PERIOD - Configures the low level width of the SCL Clock. - 0x0 - 0x20 - - - SCL_LOW_PERIOD - Configures the low level width of the SCL Clock. -Measurement unit: i2c_sclk. - 0 - 9 - read-write - - - - - CTR - Transmission setting - 0x4 - 0x20 - 0x00000208 - - - SDA_FORCE_OUT - Configures the SDA output mode -1: Direct output, - -0: Open drain output. - 0 - 1 - read-write - - - SCL_FORCE_OUT - Configures the SCL output mode -1: Direct output, - -0: Open drain output. - 1 - 1 - read-write - - - SAMPLE_SCL_LEVEL - Configures the sample mode for SDA. -1: Sample SDA data on the SCL low level. - -0: Sample SDA data on the SCL high level. - 2 - 1 - read-write - - - RX_FULL_ACK_LEVEL - Configures the ACK value that needs to be sent by master when the rx_fifo_cnt has reached the threshold. - 3 - 1 - read-write - - - MS_MODE - Configures the module as an I2C Master or Slave. -0: Slave - -1: Master - 4 - 1 - read-write - - - TRANS_START - Configures to start sending the data in txfifo for slave. -0: No effect - -1: Start - 5 - 1 - write-only - - - TX_LSB_FIRST - Configures to control the sending order for data needing to be sent. -1: send data from the least significant bit, - -0: send data from the most significant bit. - 6 - 1 - read-write - - - RX_LSB_FIRST - Configures to control the storage order for received data. -1: receive data from the least significant bit - -0: receive data from the most significant bit. - 7 - 1 - read-write - - - CLK_EN - Configures whether to gate clock signal for registers. - -0: Force clock on for registers - -1: Support clock only when registers are read or written to by software. - 8 - 1 - read-write - - - ARBITRATION_EN - Configures to enable I2C bus arbitration detection. -0: No effect - -1: Enable - 9 - 1 - read-write - - - FSM_RST - Configures to reset the SCL_FSM. -0: No effect - -1: Reset - 10 - 1 - write-only - - - CONF_UPGATE - Configures this bit for synchronization -0: No effect - -1: Synchronize - 11 - 1 - write-only - - - SLV_TX_AUTO_START_EN - Configures to enable slave to send data automatically -0: Disable - -1: Enable - 12 - 1 - read-write - - - ADDR_10BIT_RW_CHECK_EN - Configures to check if the r/w bit of 10bit addressing consists with I2C protocol. -0: Not check - -1: Check - 13 - 1 - read-write - - - ADDR_BROADCASTING_EN - Configures to support the 7bit general call function. -0: Not support - -1: Support - 14 - 1 - read-write - - - - - SR - Describe I2C work status. - 0x8 - 0x20 - 0x0000C000 - - - RESP_REC - Represents the received ACK value in master mode or slave mode. -0: ACK, - -1: NACK. - 0 - 1 - read-only - - - SLAVE_RW - Represents the transfer direction in slave mode,. -1: Master reads from slave, - -0: Master writes to slave. - 1 - 1 - read-only - - - ARB_LOST - Represents whether the I2C controller loses control of SCL line. -0: No arbitration lost - -1: Arbitration lost - 3 - 1 - read-only - - - BUS_BUSY - Represents the I2C bus state. -1: The I2C bus is busy transferring data, - -0: The I2C bus is in idle state. - 4 - 1 - read-only - - - SLAVE_ADDRESSED - Represents whether the address sent by the master is equal to the address of the slave. -Valid only when the module is configured as an I2C Slave. -0: Not equal - -1: Equal - 5 - 1 - read-only - - - RXFIFO_CNT - Represents the number of data bytes to be sent. - 8 - 6 - read-only - - - STRETCH_CAUSE - Represents the cause of SCL clocking stretching in slave mode. -0: Stretching SCL low when the master starts to read data. - -1: Stretching SCL low when I2C TX FIFO is empty in slave mode. - -2: Stretching SCL low when I2C RX FIFO is full in slave mode. - 14 - 2 - read-only - - - TXFIFO_CNT - Represents the number of data bytes received in RAM. - 18 - 6 - read-only - - - SCL_MAIN_STATE_LAST - Represents the states of the I2C module state machine. -0: Idle, - -1: Address shift, - -2: ACK address, - -3: Rx data, - -4: Tx data, - -5: Send ACK, - -6: Wait ACK - 24 - 3 - read-only - - - SCL_STATE_LAST - Represents the states of the state machine used to produce SCL. -0: Idle, - -1: Start, - -2: Negative edge, - -3: Low, - -4: Positive edge, - -5: High, - -6: Stop - 28 - 3 - read-only - - - - - TO - Setting time out control for receiving data. - 0xC - 0x20 - 0x00000010 - - - TIME_OUT_VALUE - Configures the timeout threshold period for SCL stucking at high or low level. The actual period is 2^(reg_time_out_value). -Measurement unit: i2c_sclk. - 0 - 5 - read-write - - - TIME_OUT_EN - Configures to enable time out control. -0: No effect - -1: Enable - 5 - 1 - read-write - - - - - SLAVE_ADDR - Local slave address setting - 0x10 - 0x20 - - - SLAVE_ADDR - Configure the slave address of I2C Slave. - 0 - 15 - read-write - - - ADDR_10BIT_EN - Configures to enable the slave 10-bit addressing mode in master mode. -0: No effect - -1: Enable - 31 - 1 - read-write - - - - - FIFO_ST - FIFO status register. - 0x14 - 0x20 - - - RXFIFO_RADDR - Represents the offset address of the APB reading from RXFIFO - 0 - 5 - read-only - - - RXFIFO_WADDR - Represents the offset address of i2c module receiving data and writing to RXFIFO. - 5 - 5 - read-only - - - TXFIFO_RADDR - Represents the offset address of i2c module reading from TXFIFO. - 10 - 5 - read-only - - - TXFIFO_WADDR - Represents the offset address of APB bus writing to TXFIFO. - 15 - 5 - read-only - - - SLAVE_RW_POINT - Represents the offset address in the I2C Slave RAM addressed by I2C Master when in I2C slave mode. - 22 - 8 - read-only - - - - - FIFO_CONF - FIFO configuration register. - 0x18 - 0x20 - 0x0000408B - - - RXFIFO_WM_THRHD - Configures the water mark threshold of RXFIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd[4:0], reg_rxfifo_wm_int_raw bit will be valid. - 0 - 5 - read-write - - - TXFIFO_WM_THRHD - Configures the water mark threshold of TXFIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than reg_txfifo_wm_thrhd[4:0], reg_txfifo_wm_int_raw bit will be valid. - 5 - 5 - read-write - - - NONFIFO_EN - Configures to enable APB nonfifo access. - 10 - 1 - read-write - - - FIFO_ADDR_CFG_EN - Configures to enable double addressing mode. When this mode is enabled, the byte received after the I2C address byte represents the offset address in the I2C Slave RAM. -0: Disable - -1: Enable - 11 - 1 - read-write - - - RX_FIFO_RST - Configures to reset RXFIFO. -0: No effect - -1: Reset - 12 - 1 - read-write - - - TX_FIFO_RST - Configures to reset TXFIFO. -0: No effect - -1: Reset - 13 - 1 - read-write - - - FIFO_PRT_EN - Configures to enable FIFO pointer in non-fifo access mode. This bit controls the valid bits and the TX/RX FIFO overflow, underflow, full and empty interrupts. -0: No effect - -1: Enable - 14 - 1 - read-write - - - - - DATA - Rx FIFO read data. - 0x1C - 0x20 - - - FIFO_RDATA - Represents the value of RXFIFO read data. - 0 - 8 - read-only - - - - - INT_RAW - Raw interrupt status - 0x20 - 0x20 - 0x00000002 - - - RXFIFO_WM_INT_RAW - The raw interrupt status of I2C_RXFIFO_WM_INT interrupt. - 0 - 1 - read-only - - - TXFIFO_WM_INT_RAW - The raw interrupt status of I2C_TXFIFO_WM_INT interrupt. - 1 - 1 - read-only - - - RXFIFO_OVF_INT_RAW - The raw interrupt status of I2C_RXFIFO_OVF_INT interrupt. - 2 - 1 - read-only - - - END_DETECT_INT_RAW - The raw interrupt status of the I2C_END_DETECT_INT interrupt. - 3 - 1 - read-only - - - BYTE_TRANS_DONE_INT_RAW - The raw interrupt status of the I2C_END_DETECT_INT interrupt. - 4 - 1 - read-only - - - ARBITRATION_LOST_INT_RAW - The raw interrupt status of the I2C_ARBITRATION_LOST_INT interrupt. - 5 - 1 - read-only - - - MST_TXFIFO_UDF_INT_RAW - The raw interrupt status of I2C_TRANS_COMPLETE_INT interrupt. - 6 - 1 - read-only - - - TRANS_COMPLETE_INT_RAW - The raw interrupt status of the I2C_TRANS_COMPLETE_INT interrupt. - 7 - 1 - read-only - - - TIME_OUT_INT_RAW - The raw interrupt status of the I2C_TIME_OUT_INT interrupt. - 8 - 1 - read-only - - - TRANS_START_INT_RAW - The raw interrupt status of the I2C_TRANS_START_INT interrupt. - 9 - 1 - read-only - - - NACK_INT_RAW - The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt. - 10 - 1 - read-only - - - TXFIFO_OVF_INT_RAW - The raw interrupt status of I2C_TXFIFO_OVF_INT interrupt. - 11 - 1 - read-only - - - RXFIFO_UDF_INT_RAW - The raw interrupt status of I2C_RXFIFO_UDF_INT interrupt. - 12 - 1 - read-only - - - SCL_ST_TO_INT_RAW - The raw interrupt status of I2C_SCL_ST_TO_INT interrupt. - 13 - 1 - read-only - - - SCL_MAIN_ST_TO_INT_RAW - The raw interrupt status of I2C_SCL_MAIN_ST_TO_INT interrupt. - 14 - 1 - read-only - - - DET_START_INT_RAW - The raw interrupt status of I2C_DET_START_INT interrupt. - 15 - 1 - read-only - - - SLAVE_STRETCH_INT_RAW - The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt. - 16 - 1 - read-only - - - GENERAL_CALL_INT_RAW - The raw interrupt status of I2C_GENARAL_CALL_INT interrupt. - 17 - 1 - read-only - - - SLAVE_ADDR_UNMATCH_INT_RAW - The raw interrupt status of I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt. - 18 - 1 - read-only - - - - - INT_CLR - Interrupt clear bits - 0x24 - 0x20 - - - RXFIFO_WM_INT_CLR - Write 1 to clear I2C_RXFIFO_WM_INT interrupt. - 0 - 1 - write-only - - - TXFIFO_WM_INT_CLR - Write 1 to clear I2C_TXFIFO_WM_INT interrupt. - 1 - 1 - write-only - - - RXFIFO_OVF_INT_CLR - Write 1 to clear I2C_RXFIFO_OVF_INT interrupt. - 2 - 1 - write-only - - - END_DETECT_INT_CLR - Write 1 to clear the I2C_END_DETECT_INT interrupt. - 3 - 1 - write-only - - - BYTE_TRANS_DONE_INT_CLR - Write 1 to clear the I2C_END_DETECT_INT interrupt. - 4 - 1 - write-only - - - ARBITRATION_LOST_INT_CLR - Write 1 to clear the I2C_ARBITRATION_LOST_INT interrupt. - 5 - 1 - write-only - - - MST_TXFIFO_UDF_INT_CLR - Write 1 to clear I2C_TRANS_COMPLETE_INT interrupt. - 6 - 1 - write-only - - - TRANS_COMPLETE_INT_CLR - Write 1 to clear the I2C_TRANS_COMPLETE_INT interrupt. - 7 - 1 - write-only - - - TIME_OUT_INT_CLR - Write 1 to clear the I2C_TIME_OUT_INT interrupt. - 8 - 1 - write-only - - - TRANS_START_INT_CLR - Write 1 to clear the I2C_TRANS_START_INT interrupt. - 9 - 1 - write-only - - - NACK_INT_CLR - Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt. - 10 - 1 - write-only - - - TXFIFO_OVF_INT_CLR - Write 1 to clear I2C_TXFIFO_OVF_INT interrupt. - 11 - 1 - write-only - - - RXFIFO_UDF_INT_CLR - Write 1 to clear I2C_RXFIFO_UDF_INT interrupt. - 12 - 1 - write-only - - - SCL_ST_TO_INT_CLR - Write 1 to clear I2C_SCL_ST_TO_INT interrupt. - 13 - 1 - write-only - - - SCL_MAIN_ST_TO_INT_CLR - Write 1 to clear I2C_SCL_MAIN_ST_TO_INT interrupt. - 14 - 1 - write-only - - - DET_START_INT_CLR - Write 1 to clear I2C_DET_START_INT interrupt. - 15 - 1 - write-only - - - SLAVE_STRETCH_INT_CLR - Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt. - 16 - 1 - write-only - - - GENERAL_CALL_INT_CLR - Write 1 to clear I2C_GENARAL_CALL_INT interrupt. - 17 - 1 - write-only - - - SLAVE_ADDR_UNMATCH_INT_CLR - Write 1 to clear I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt. - 18 - 1 - write-only - - - - - INT_ENA - Interrupt enable bits - 0x28 - 0x20 - - - RXFIFO_WM_INT_ENA - Write 1 to enable I2C_RXFIFO_WM_INT interrupt. - 0 - 1 - read-write - - - TXFIFO_WM_INT_ENA - Write 1 to enable I2C_TXFIFO_WM_INT interrupt. - 1 - 1 - read-write - - - RXFIFO_OVF_INT_ENA - Write 1 to enable I2C_RXFIFO_OVF_INT interrupt. - 2 - 1 - read-write - - - END_DETECT_INT_ENA - Write 1 to enable the I2C_END_DETECT_INT interrupt. - 3 - 1 - read-write - - - BYTE_TRANS_DONE_INT_ENA - Write 1 to enable the I2C_END_DETECT_INT interrupt. - 4 - 1 - read-write - - - ARBITRATION_LOST_INT_ENA - Write 1 to enable the I2C_ARBITRATION_LOST_INT interrupt. - 5 - 1 - read-write - - - MST_TXFIFO_UDF_INT_ENA - Write 1 to enable I2C_TRANS_COMPLETE_INT interrupt. - 6 - 1 - read-write - - - TRANS_COMPLETE_INT_ENA - Write 1 to enable the I2C_TRANS_COMPLETE_INT interrupt. - 7 - 1 - read-write - - - TIME_OUT_INT_ENA - Write 1 to enable the I2C_TIME_OUT_INT interrupt. - 8 - 1 - read-write - - - TRANS_START_INT_ENA - Write 1 to enable the I2C_TRANS_START_INT interrupt. - 9 - 1 - read-write - - - NACK_INT_ENA - Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt. - 10 - 1 - read-write - - - TXFIFO_OVF_INT_ENA - Write 1 to enable I2C_TXFIFO_OVF_INT interrupt. - 11 - 1 - read-write - - - RXFIFO_UDF_INT_ENA - Write 1 to enable I2C_RXFIFO_UDF_INT interrupt. - 12 - 1 - read-write - - - SCL_ST_TO_INT_ENA - Write 1 to enable I2C_SCL_ST_TO_INT interrupt. - 13 - 1 - read-write - - - SCL_MAIN_ST_TO_INT_ENA - Write 1 to enable I2C_SCL_MAIN_ST_TO_INT interrupt. - 14 - 1 - read-write - - - DET_START_INT_ENA - Write 1 to enable I2C_DET_START_INT interrupt. - 15 - 1 - read-write - - - SLAVE_STRETCH_INT_ENA - Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt. - 16 - 1 - read-write - - - GENERAL_CALL_INT_ENA - Write 1 to enable I2C_GENARAL_CALL_INT interrupt. - 17 - 1 - read-write - - - SLAVE_ADDR_UNMATCH_INT_ENA - Write 1 to enable I2C_SLAVE_ADDR_UNMATCH_INT interrupt. - 18 - 1 - read-write - - - - - INT_STATUS - Status of captured I2C communication events - 0x2C - 0x20 - - - RXFIFO_WM_INT_ST - The masked interrupt status status of I2C_RXFIFO_WM_INT interrupt. - 0 - 1 - read-only - - - TXFIFO_WM_INT_ST - The masked interrupt status status of I2C_TXFIFO_WM_INT interrupt. - 1 - 1 - read-only - - - RXFIFO_OVF_INT_ST - The masked interrupt status status of I2C_RXFIFO_OVF_INT interrupt. - 2 - 1 - read-only - - - END_DETECT_INT_ST - The masked interrupt status status of the I2C_END_DETECT_INT interrupt. - 3 - 1 - read-only - - - BYTE_TRANS_DONE_INT_ST - The masked interrupt status status of the I2C_END_DETECT_INT interrupt. - 4 - 1 - read-only - - - ARBITRATION_LOST_INT_ST - The masked interrupt status status of the I2C_ARBITRATION_LOST_INT interrupt. - 5 - 1 - read-only - - - MST_TXFIFO_UDF_INT_ST - The masked interrupt status status of I2C_TRANS_COMPLETE_INT interrupt. - 6 - 1 - read-only - - - TRANS_COMPLETE_INT_ST - The masked interrupt status status of the I2C_TRANS_COMPLETE_INT interrupt. - 7 - 1 - read-only - - - TIME_OUT_INT_ST - The masked interrupt status status of the I2C_TIME_OUT_INT interrupt. - 8 - 1 - read-only - - - TRANS_START_INT_ST - The masked interrupt status status of the I2C_TRANS_START_INT interrupt. - 9 - 1 - read-only - - - NACK_INT_ST - The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt. - 10 - 1 - read-only - - - TXFIFO_OVF_INT_ST - The masked interrupt status status of I2C_TXFIFO_OVF_INT interrupt. - 11 - 1 - read-only - - - RXFIFO_UDF_INT_ST - The masked interrupt status status of I2C_RXFIFO_UDF_INT interrupt. - 12 - 1 - read-only - - - SCL_ST_TO_INT_ST - The masked interrupt status status of I2C_SCL_ST_TO_INT interrupt. - 13 - 1 - read-only - - - SCL_MAIN_ST_TO_INT_ST - The masked interrupt status status of I2C_SCL_MAIN_ST_TO_INT interrupt. - 14 - 1 - read-only - - - DET_START_INT_ST - The masked interrupt status status of I2C_DET_START_INT interrupt. - 15 - 1 - read-only - - - SLAVE_STRETCH_INT_ST - The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt. - 16 - 1 - read-only - - - GENERAL_CALL_INT_ST - The masked interrupt status status of I2C_GENARAL_CALL_INT interrupt. - 17 - 1 - read-only - - - SLAVE_ADDR_UNMATCH_INT_ST - The masked interrupt status status of I2C_SLAVE_ADDR_UNMATCH_INT interrupt. - 18 - 1 - read-only - - - - - SDA_HOLD - Configures the hold time after a negative SCL edge. - 0x30 - 0x20 - - - TIME - Configures the time to hold the data after the falling edge of SCL. -Measurement unit: i2c_sclk - 0 - 9 - read-write - - - - - SDA_SAMPLE - Configures the sample time after a positive SCL edge. - 0x34 - 0x20 - - - TIME - Configures the sample time after a positive SCL edge. -Measurement unit: i2c_sclk - 0 - 9 - read-write - - - - - SCL_HIGH_PERIOD - Configures the high level width of SCL - 0x38 - 0x20 - - - SCL_HIGH_PERIOD - Configures for how long SCL remains high in master mode. -Measurement unit: i2c_sclk - 0 - 9 - read-write - - - SCL_WAIT_HIGH_PERIOD - Configures the SCL_FSM's waiting period for SCL high level in master mode. -Measurement unit: i2c_sclk - 9 - 7 - read-write - - - - - SCL_START_HOLD - Configures the delay between the SDA and SCL negative edge for a start condition - 0x40 - 0x20 - 0x00000008 - - - TIME - Configures the time between the falling edge of SDA and the falling edge of SCL for a START condition. -Measurement unit: i2c_sclk. - 0 - 9 - read-write - - - - - SCL_RSTART_SETUP - Configures the delay between the positive edge of SCL and the negative edge of SDA - 0x44 - 0x20 - 0x00000008 - - - TIME - Configures the time between the positive edge of SCL and the negative edge of SDA for a RESTART condition. -Measurement unit: i2c_sclk - 0 - 9 - read-write - - - - - SCL_STOP_HOLD - Configures the delay after the SCL clock edge for a stop condition - 0x48 - 0x20 - 0x00000008 - - - TIME - Configures the delay after the STOP condition. -Measurement unit: i2c_sclk - 0 - 9 - read-write - - - - - SCL_STOP_SETUP - Configures the delay between the SDA and SCL rising edge for a stop condition. -Measurement unit: i2c_sclk - 0x4C - 0x20 - 0x00000008 - - - TIME - Configures the time between the rising edge of SCL and the rising edge of SDA. -Measurement unit: i2c_sclk - 0 - 9 - read-write - - - - - FILTER_CFG - SCL and SDA filter configuration register - 0x50 - 0x20 - 0x00000300 - - - SCL_FILTER_THRES - Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL input has smaller width than this register value, the I2C controller will ignore that pulse. -Measurement unit: i2c_sclk - 0 - 4 - read-write - - - SDA_FILTER_THRES - Configures the threshold pulse width to be filtered on SDA. When a pulse on the SDA input has smaller width than this register value, the I2C controller will ignore that pulse. -Measurement unit: i2c_sclk - 4 - 4 - read-write - - - SCL_FILTER_EN - Configures to enable the filter function for SCL. - 8 - 1 - read-write - - - SDA_FILTER_EN - Configures to enable the filter function for SDA. - 9 - 1 - read-write - - - - - CLK_CONF - I2C CLK configuration register - 0x54 - 0x20 - 0x00200000 - - - SCLK_DIV_NUM - the integral part of the fractional divisor for i2c module - 0 - 8 - read-write - - - SCLK_DIV_A - the numerator of the fractional part of the fractional divisor for i2c module - 8 - 6 - read-write - - - SCLK_DIV_B - the denominator of the fractional part of the fractional divisor for i2c module - 14 - 6 - read-write - - - SCLK_SEL - The clock selection for i2c module:0-XTAL,1-CLK_8MHz. - 20 - 1 - read-write - - - SCLK_ACTIVE - The clock switch for i2c module - 21 - 1 - read-write - - - - - COMD0 - I2C command register 0 - 0x58 - 0x20 - - - COMMAND0 - Configures command 0. It consists of three parts: -op_code is the command, -0: RSTART, -1: WRITE, -2: READ, -3: STOP, -4: END. - -Byte_num represents the number of bytes that need to be sent or received. -ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more information. - 0 - 14 - read-write - - - COMMAND0_DONE - Represents whether command 0 is done in I2C Master mode. -0: Not done - -1: Done - 31 - 1 - read-write - - - - - COMD1 - I2C command register 1 - 0x5C - 0x20 - - - COMMAND1 - Configures command 1. See details in I2C_CMD0_REG[13:0]. - 0 - 14 - read-write - - - COMMAND1_DONE - Represents whether command 1 is done in I2C Master mode. -0: Not done - -1: Done - 31 - 1 - read-write - - - - - COMD2 - I2C command register 2 - 0x60 - 0x20 - - - COMMAND2 - Configures command 2. See details in I2C_CMD0_REG[13:0]. - 0 - 14 - read-write - - - COMMAND2_DONE - Represents whether command 2 is done in I2C Master mode. -0: Not done - -1: Done - 31 - 1 - read-write - - - - - COMD3 - I2C command register 3 - 0x64 - 0x20 - - - COMMAND3 - Configures command 3. See details in I2C_CMD0_REG[13:0]. - 0 - 14 - read-write - - - COMMAND3_DONE - Represents whether command 3 is done in I2C Master mode. -0: Not done - -1: Done - 31 - 1 - read-write - - - - - COMD4 - I2C command register 4 - 0x68 - 0x20 - - - COMMAND4 - Configures command 4. See details in I2C_CMD0_REG[13:0]. - 0 - 14 - read-write - - - COMMAND4_DONE - Represents whether command 4 is done in I2C Master mode. -0: Not done - -1: Done - 31 - 1 - read-write - - - - - COMD5 - I2C command register 5 - 0x6C - 0x20 - - - COMMAND5 - Configures command 5. See details in I2C_CMD0_REG[13:0]. - 0 - 14 - read-write - - - COMMAND5_DONE - Represents whether command 5 is done in I2C Master mode. -0: Not done - -1: Done - 31 - 1 - read-write - - - - - COMD6 - I2C command register 6 - 0x70 - 0x20 - - - COMMAND6 - Configures command 6. See details in I2C_CMD0_REG[13:0]. - 0 - 14 - read-write - - - COMMAND6_DONE - Represents whether command 6 is done in I2C Master mode. -0: Not done - -1: Done - 31 - 1 - read-write - - - - - COMD7 - I2C command register 7 - 0x74 - 0x20 - - - COMMAND7 - Configures command 7. See details in I2C_CMD0_REG[13:0]. - 0 - 14 - read-write - - - COMMAND7_DONE - Represents whether command 7 is done in I2C Master mode. -0: Not done - -1: Done - 31 - 1 - read-write - - - - - SCL_ST_TIME_OUT - SCL status time out register - 0x78 - 0x20 - 0x00000010 - - - SCL_ST_TO_I2C - Configures the threshold value of SCL_FSM state unchanged period. It should be no more than 23. -Measurement unit: i2c_sclk - 0 - 5 - read-write - - - - - SCL_MAIN_ST_TIME_OUT - SCL main status time out register - 0x7C - 0x20 - 0x00000010 - - - SCL_MAIN_ST_TO_I2C - Configures the threshold value of SCL_MAIN_FSM state unchanged period.nIt should be no more than 23. -Measurement unit: i2c_sclk - 0 - 5 - read-write - - - - - SCL_SP_CONF - Power configuration register - 0x80 - 0x20 - - - SCL_RST_SLV_EN - Configures to send out SCL pulses when I2C master is IDLE. The number of pulses equals to reg_scl_rst_slv_num[4:0]. - 0 - 1 - read-write - - - SCL_RST_SLV_NUM - Configure the pulses of SCL generated in I2C master mode. -Valid when reg_scl_rst_slv_en is 1. -Measurement unit: i2c_sclk - 1 - 5 - read-write - - - SCL_PD_EN - Configures to power down the I2C output SCL line. -0: Not power down. - -1: Power down. -Valid only when reg_scl_force_out is 1. - 6 - 1 - read-write - - - SDA_PD_EN - Configures to power down the I2C output SDA line. -0: Not power down. - -1: Power down. -Valid only when reg_sda_force_out is 1. - 7 - 1 - read-write - - - - - SCL_STRETCH_CONF - Set SCL stretch of I2C slave - 0x84 - 0x20 - - - STRETCH_PROTECT_NUM - Configures the time period to release the SCL line from stretching to avoid timing violation. Usually it should be larger than the SDA setup time. -Measurement unit: i2c_sclk - 0 - 10 - read-write - - - SLAVE_SCL_STRETCH_EN - Configures to enable slave SCL stretch function. -0: Disable - -1: Enable -The SCL output line will be stretched low when reg_slave_scl_stretch_en is 1 and stretch event happens. The stretch cause can be seen in reg_stretch_cause. - 10 - 1 - read-write - - - SLAVE_SCL_STRETCH_CLR - Configures to clear the I2C slave SCL stretch function. -0: No effect - -1: Clear - 11 - 1 - write-only - - - SLAVE_BYTE_ACK_CTL_EN - Configures to enable the function for slave to control ACK level. -0: Disable - -1: Enable - 12 - 1 - read-write - - - SLAVE_BYTE_ACK_LVL - Set the ACK level when slave controlling ACK level function enables. -0: Low level - -1: High level - 13 - 1 - read-write - - - - - DATE - Version register - 0xF8 - 0x20 - 0x02201172 - - - DATE - Version control register. - 0 - 32 - read-write - - - - - TXFIFO_START_ADDR - I2C TXFIFO base address register - 0x100 - 0x20 - - - TXFIFO_START_ADDR - Represents the I2C txfifo first address. - 0 - 32 - read-only - - - - - RXFIFO_START_ADDR - I2C RXFIFO base address register - 0x180 - 0x20 - - - RXFIFO_START_ADDR - Represents the I2C rxfifo first address. - 0 - 32 - read-only - - - - - - - I2C1 - I2C (Inter-Integrated Circuit) Controller 1 - 0x500C5000 - - I2C1 - 45 - - - - I2S0 - I2S (Inter-IC Sound) Controller 0 - I2S - 0x500C6000 - - 0x0 - 0x60 - registers - - - I2S0 - 27 - - - - INT_RAW - I2S interrupt raw register, valid in level. - 0xC - 0x20 - - - RX_DONE_INT_RAW - The raw interrupt status bit for the i2s_rx_done_int interrupt - 0 - 1 - read-only - - - TX_DONE_INT_RAW - The raw interrupt status bit for the i2s_tx_done_int interrupt - 1 - 1 - read-only - - - RX_HUNG_INT_RAW - The raw interrupt status bit for the i2s_rx_hung_int interrupt - 2 - 1 - read-only - - - TX_HUNG_INT_RAW - The raw interrupt status bit for the i2s_tx_hung_int interrupt - 3 - 1 - read-only - - - - - INT_ST - I2S interrupt status register. - 0x10 - 0x20 - - - RX_DONE_INT_ST - The masked interrupt status bit for the i2s_rx_done_int interrupt - 0 - 1 - read-only - - - TX_DONE_INT_ST - The masked interrupt status bit for the i2s_tx_done_int interrupt - 1 - 1 - read-only - - - RX_HUNG_INT_ST - The masked interrupt status bit for the i2s_rx_hung_int interrupt - 2 - 1 - read-only - - - TX_HUNG_INT_ST - The masked interrupt status bit for the i2s_tx_hung_int interrupt - 3 - 1 - read-only - - - - - INT_ENA - I2S interrupt enable register. - 0x14 - 0x20 - - - RX_DONE_INT_ENA - The interrupt enable bit for the i2s_rx_done_int interrupt - 0 - 1 - read-write - - - TX_DONE_INT_ENA - The interrupt enable bit for the i2s_tx_done_int interrupt - 1 - 1 - read-write - - - RX_HUNG_INT_ENA - The interrupt enable bit for the i2s_rx_hung_int interrupt - 2 - 1 - read-write - - - TX_HUNG_INT_ENA - The interrupt enable bit for the i2s_tx_hung_int interrupt - 3 - 1 - read-write - - - - - INT_CLR - I2S interrupt clear register. - 0x18 - 0x20 - - - RX_DONE_INT_CLR - Set this bit to clear the i2s_rx_done_int interrupt - 0 - 1 - write-only - - - TX_DONE_INT_CLR - Set this bit to clear the i2s_tx_done_int interrupt - 1 - 1 - write-only - - - RX_HUNG_INT_CLR - Set this bit to clear the i2s_rx_hung_int interrupt - 2 - 1 - write-only - - - TX_HUNG_INT_CLR - Set this bit to clear the i2s_tx_hung_int interrupt - 3 - 1 - write-only - - - - - RX_CONF - I2S RX configure register - 0x20 - 0x20 - 0x00C0B600 - - - RX_RESET - Set this bit to reset receiver - 0 - 1 - write-only - - - RX_FIFO_RESET - Set this bit to reset Rx AFIFO - 1 - 1 - write-only - - - RX_START - Set this bit to start receiving data - 2 - 1 - read-write - - - RX_SLAVE_MOD - Set this bit to enable slave receiver mode - 3 - 1 - read-write - - - RX_STOP_MODE - 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full. - 4 - 2 - read-write - - - RX_MONO - Set this bit to enable receiver in mono mode - 6 - 1 - read-write - - - RX_BIG_ENDIAN - I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value. - 7 - 1 - read-write - - - RX_UPDATE - Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done. - 8 - 1 - read-write - - - RX_MONO_FST_VLD - 1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode. - 9 - 1 - read-write - - - RX_PCM_CONF - I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & - 10 - 2 - read-write - - - RX_PCM_BYPASS - Set this bit to bypass Compress/Decompress module for received data. - 12 - 1 - read-write - - - RX_MSB_SHIFT - Set this bit to enable receiver in Phillips standard mode - 13 - 1 - read-write - - - RX_LEFT_ALIGN - 1: I2S RX left alignment mode. 0: I2S RX right alignment mode. - 15 - 1 - read-write - - - RX_24_FILL_EN - 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits. - 16 - 1 - read-write - - - RX_WS_IDLE_POL - 0: WS should be 0 when receiving left channel data, and WS is 1in right channel. 1: WS should be 1 when receiving left channel data, and WS is 0in right channel. - 17 - 1 - read-write - - - RX_BIT_ORDER - I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first. - 18 - 1 - read-write - - - RX_TDM_EN - 1: Enable I2S TDM Rx mode . 0: Disable. - 19 - 1 - read-write - - - RX_PDM_EN - 1: Enable I2S PDM Rx mode . 0: Disable. - 20 - 1 - read-write - - - RX_BCK_DIV_NUM - Bit clock configuration bits in receiver mode. - 21 - 6 - read-write - - - - - TX_CONF - I2S TX configure register - 0x24 - 0x20 - 0x00C0F210 - - - TX_RESET - Set this bit to reset transmitter - 0 - 1 - write-only - - - TX_FIFO_RESET - Set this bit to reset Tx AFIFO - 1 - 1 - write-only - - - TX_START - Set this bit to start transmitting data - 2 - 1 - read-write - - - TX_SLAVE_MOD - Set this bit to enable slave transmitter mode - 3 - 1 - read-write - - - TX_STOP_EN - Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy - 4 - 1 - read-write - - - TX_CHAN_EQUAL - 1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode. - 5 - 1 - read-write - - - TX_MONO - Set this bit to enable transmitter in mono mode - 6 - 1 - read-write - - - TX_BIG_ENDIAN - I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr value. - 7 - 1 - read-write - - - TX_UPDATE - Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done. - 8 - 1 - read-write - - - TX_MONO_FST_VLD - 1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode. - 9 - 1 - read-write - - - TX_PCM_CONF - I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & - 10 - 2 - read-write - - - TX_PCM_BYPASS - Set this bit to bypass Compress/Decompress module for transmitted data. - 12 - 1 - read-write - - - TX_MSB_SHIFT - Set this bit to enable transmitter in Phillips standard mode - 13 - 1 - read-write - - - TX_BCK_NO_DLY - 1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode. - 14 - 1 - read-write - - - TX_LEFT_ALIGN - 1: I2S TX left alignment mode. 0: I2S TX right alignment mode. - 15 - 1 - read-write - - - TX_24_FILL_EN - 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode - 16 - 1 - read-write - - - TX_WS_IDLE_POL - 0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: WS should be 1 when sending left channel data, and WS is 0in right channel. - 17 - 1 - read-write - - - TX_BIT_ORDER - I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first. - 18 - 1 - read-write - - - TX_TDM_EN - 1: Enable I2S TDM Tx mode . 0: Disable. - 19 - 1 - read-write - - - TX_PDM_EN - 1: Enable I2S PDM Tx mode . 0: Disable. - 20 - 1 - read-write - - - TX_BCK_DIV_NUM - Bit clock configuration bits in transmitter mode. - 21 - 6 - read-write - - - TX_CHAN_MOD - I2S transmitter channel mode configuration bits. - 27 - 3 - read-write - - - SIG_LOOPBACK - Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals. - 30 - 1 - read-write - - - - - RX_CONF1 - I2S RX configure register 1 - 0x28 - 0x20 - 0x787BC000 - - - RX_TDM_WS_WIDTH - The width of rx_ws_out at idle level in TDM mode is (I2S_RX_TDM_WS_WIDTH[8:0] +1) * T_bck - 0 - 9 - read-write - - - RX_BITS_MOD - Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode. - 14 - 5 - read-write - - - RX_HALF_SAMPLE_BITS - I2S Rx half sample bits -1. - 19 - 8 - read-write - - - RX_TDM_CHAN_BITS - The Rx bit number for each channel minus 1in TDM mode. - 27 - 5 - read-write - - - - - TX_CONF1 - I2S TX configure register 1 - 0x2C - 0x20 - 0x787BC000 - - - TX_TDM_WS_WIDTH - The width of tx_ws_out at idle level in TDM mode is (I2S_TX_TDM_WS_WIDTH[8:0] +1) * T_bck - 0 - 9 - read-write - - - TX_BITS_MOD - Set the bits to configure the valid data bit length of I2S transmitter channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode. - 14 - 5 - read-write - - - TX_HALF_SAMPLE_BITS - I2S Tx half sample bits -1. - 19 - 8 - read-write - - - TX_TDM_CHAN_BITS - The Tx bit number for each channel minus 1in TDM mode. - 27 - 5 - read-write - - - - - TX_PCM2PDM_CONF - I2S TX PCM2PDM configuration register - 0x40 - 0x20 - 0x004AA004 - - - TX_PDM_HP_BYPASS - I2S TX PDM bypass hp filter or not. The option has been removed. - 0 - 1 - read-write - - - TX_PDM_SINC_OSR2 - I2S TX PDM OSR2 value - 1 - 4 - read-write - - - TX_PDM_PRESCALE - I2S TX PDM prescale for sigmadelta - 5 - 8 - read-write - - - TX_PDM_HP_IN_SHIFT - I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 - 13 - 2 - read-write - - - TX_PDM_LP_IN_SHIFT - I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 - 15 - 2 - read-write - - - TX_PDM_SINC_IN_SHIFT - I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 - 17 - 2 - read-write - - - TX_PDM_SIGMADELTA_IN_SHIFT - I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 - 19 - 2 - read-write - - - TX_PDM_SIGMADELTA_DITHER2 - I2S TX PDM sigmadelta dither2 value - 21 - 1 - read-write - - - TX_PDM_SIGMADELTA_DITHER - I2S TX PDM sigmadelta dither value - 22 - 1 - read-write - - - TX_PDM_DAC_2OUT_EN - I2S TX PDM dac mode enable - 23 - 1 - read-write - - - TX_PDM_DAC_MODE_EN - I2S TX PDM dac 2channel enable - 24 - 1 - read-write - - - PCM2PDM_CONV_EN - I2S TX PDM Converter enable - 25 - 1 - read-write - - - - - TX_PCM2PDM_CONF1 - I2S TX PCM2PDM configuration register - 0x44 - 0x20 - 0x03F783C0 - - - TX_PDM_FP - I2S TX PDM Fp - 0 - 10 - read-write - - - TX_PDM_FS - I2S TX PDM Fs - 10 - 10 - read-write - - - TX_IIR_HP_MULT12_5 - The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MULT12_5[2:0]) - 20 - 3 - read-write - - - TX_IIR_HP_MULT12_0 - The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MULT12_0[2:0]) - 23 - 3 - read-write - - - - - RX_PDM2PCM_CONF - I2S RX configure register - 0x48 - 0x20 - 0xF8200000 - - - RX_PDM2PCM_EN - 1: Enable PDM2PCM RX mode. 0: DIsable. - 19 - 1 - read-write - - - RX_PDM_SINC_DSR_16_EN - Configure the down sampling rate of PDM RX filter group1 module. 1: The down sampling rate is 128. 0: down sampling rate is 64. - 20 - 1 - read-write - - - RX_PDM2PCM_AMPLIFY_NUM - Configure PDM RX amplify number. - 21 - 4 - read-write - - - RX_PDM_HP_BYPASS - I2S PDM RX bypass hp filter or not. - 25 - 1 - read-write - - - RX_IIR_HP_MULT12_5 - The fourth parameter of PDM RX IIR_HP filter stage 2 is (504 + LP_I2S_RX_IIR_HP_MULT12_5[2:0]) - 26 - 3 - read-write - - - RX_IIR_HP_MULT12_0 - The fourth parameter of PDM RX IIR_HP filter stage 1 is (504 + LP_I2S_RX_IIR_HP_MULT12_0[2:0]) - 29 - 3 - read-write - - - - - RX_TDM_CTRL - I2S TX TDM mode control register - 0x50 - 0x20 - 0x0000FFFF - - - RX_TDM_PDM_CHAN0_EN - 1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0: Disable, just input 0 in this channel. - 0 - 1 - read-write - - - RX_TDM_PDM_CHAN1_EN - 1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0: Disable, just input 0 in this channel. - 1 - 1 - read-write - - - RX_TDM_PDM_CHAN2_EN - 1: Enable the valid data input of I2S RX TDM or PDM channel 2. 0: Disable, just input 0 in this channel. - 2 - 1 - read-write - - - RX_TDM_PDM_CHAN3_EN - 1: Enable the valid data input of I2S RX TDM or PDM channel 3. 0: Disable, just input 0 in this channel. - 3 - 1 - read-write - - - RX_TDM_PDM_CHAN4_EN - 1: Enable the valid data input of I2S RX TDM or PDM channel 4. 0: Disable, just input 0 in this channel. - 4 - 1 - read-write - - - RX_TDM_PDM_CHAN5_EN - 1: Enable the valid data input of I2S RX TDM or PDM channel 5. 0: Disable, just input 0 in this channel. - 5 - 1 - read-write - - - RX_TDM_PDM_CHAN6_EN - 1: Enable the valid data input of I2S RX TDM or PDM channel 6. 0: Disable, just input 0 in this channel. - 6 - 1 - read-write - - - RX_TDM_PDM_CHAN7_EN - 1: Enable the valid data input of I2S RX TDM or PDM channel 7. 0: Disable, just input 0 in this channel. - 7 - 1 - read-write - - - RX_TDM_CHAN8_EN - 1: Enable the valid data input of I2S RX TDM channel 8. 0: Disable, just input 0 in this channel. - 8 - 1 - read-write - - - RX_TDM_CHAN9_EN - 1: Enable the valid data input of I2S RX TDM channel 9. 0: Disable, just input 0 in this channel. - 9 - 1 - read-write - - - RX_TDM_CHAN10_EN - 1: Enable the valid data input of I2S RX TDM channel 10. 0: Disable, just input 0 in this channel. - 10 - 1 - read-write - - - RX_TDM_CHAN11_EN - 1: Enable the valid data input of I2S RX TDM channel 11. 0: Disable, just input 0 in this channel. - 11 - 1 - read-write - - - RX_TDM_CHAN12_EN - 1: Enable the valid data input of I2S RX TDM channel 12. 0: Disable, just input 0 in this channel. - 12 - 1 - read-write - - - RX_TDM_CHAN13_EN - 1: Enable the valid data input of I2S RX TDM channel 13. 0: Disable, just input 0 in this channel. - 13 - 1 - read-write - - - RX_TDM_CHAN14_EN - 1: Enable the valid data input of I2S RX TDM channel 14. 0: Disable, just input 0 in this channel. - 14 - 1 - read-write - - - RX_TDM_CHAN15_EN - 1: Enable the valid data input of I2S RX TDM channel 15. 0: Disable, just input 0 in this channel. - 15 - 1 - read-write - - - RX_TDM_TOT_CHAN_NUM - The total channel number of I2S TX TDM mode. - 16 - 4 - read-write - - - - - TX_TDM_CTRL - I2S TX TDM mode control register - 0x54 - 0x20 - 0x0000FFFF - - - TX_TDM_CHAN0_EN - 1: Enable the valid data output of I2S TX TDM channel 0. 0: Disable, just output 0 in this channel. - 0 - 1 - read-write - - - TX_TDM_CHAN1_EN - 1: Enable the valid data output of I2S TX TDM channel 1. 0: Disable, just output 0 in this channel. - 1 - 1 - read-write - - - TX_TDM_CHAN2_EN - 1: Enable the valid data output of I2S TX TDM channel 2. 0: Disable, just output 0 in this channel. - 2 - 1 - read-write - - - TX_TDM_CHAN3_EN - 1: Enable the valid data output of I2S TX TDM channel 3. 0: Disable, just output 0 in this channel. - 3 - 1 - read-write - - - TX_TDM_CHAN4_EN - 1: Enable the valid data output of I2S TX TDM channel 4. 0: Disable, just output 0 in this channel. - 4 - 1 - read-write - - - TX_TDM_CHAN5_EN - 1: Enable the valid data output of I2S TX TDM channel 5. 0: Disable, just output 0 in this channel. - 5 - 1 - read-write - - - TX_TDM_CHAN6_EN - 1: Enable the valid data output of I2S TX TDM channel 6. 0: Disable, just output 0 in this channel. - 6 - 1 - read-write - - - TX_TDM_CHAN7_EN - 1: Enable the valid data output of I2S TX TDM channel 7. 0: Disable, just output 0 in this channel. - 7 - 1 - read-write - - - TX_TDM_CHAN8_EN - 1: Enable the valid data output of I2S TX TDM channel 8. 0: Disable, just output 0 in this channel. - 8 - 1 - read-write - - - TX_TDM_CHAN9_EN - 1: Enable the valid data output of I2S TX TDM channel 9. 0: Disable, just output 0 in this channel. - 9 - 1 - read-write - - - TX_TDM_CHAN10_EN - 1: Enable the valid data output of I2S TX TDM channel 10. 0: Disable, just output 0 in this channel. - 10 - 1 - read-write - - - TX_TDM_CHAN11_EN - 1: Enable the valid data output of I2S TX TDM channel 11. 0: Disable, just output 0 in this channel. - 11 - 1 - read-write - - - TX_TDM_CHAN12_EN - 1: Enable the valid data output of I2S TX TDM channel 12. 0: Disable, just output 0 in this channel. - 12 - 1 - read-write - - - TX_TDM_CHAN13_EN - 1: Enable the valid data output of I2S TX TDM channel 13. 0: Disable, just output 0 in this channel. - 13 - 1 - read-write - - - TX_TDM_CHAN14_EN - 1: Enable the valid data output of I2S TX TDM channel 14. 0: Disable, just output 0 in this channel. - 14 - 1 - read-write - - - TX_TDM_CHAN15_EN - 1: Enable the valid data output of I2S TX TDM channel 15. 0: Disable, just output 0 in this channel. - 15 - 1 - read-write - - - TX_TDM_TOT_CHAN_NUM - The total channel number of I2S TX TDM mode. - 16 - 4 - read-write - - - TX_TDM_SKIP_MSK_EN - When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels, and only the data of the enabled channels is sent, then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels. - 20 - 1 - read-write - - - - - RX_TIMING - I2S RX timing control register - 0x58 - 0x20 - - - RX_SD_IN_DM - The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. - 0 - 2 - read-write - - - RX_SD1_IN_DM - The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. - 4 - 2 - read-write - - - RX_SD2_IN_DM - The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. - 8 - 2 - read-write - - - RX_SD3_IN_DM - The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. - 12 - 2 - read-write - - - RX_WS_OUT_DM - The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. - 16 - 2 - read-write - - - RX_BCK_OUT_DM - The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. - 20 - 2 - read-write - - - RX_WS_IN_DM - The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. - 24 - 2 - read-write - - - RX_BCK_IN_DM - The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. - 28 - 2 - read-write - - - - - TX_TIMING - I2S TX timing control register - 0x5C - 0x20 - - - TX_SD_OUT_DM - The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. - 0 - 2 - read-write - - - TX_SD1_OUT_DM - The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. - 4 - 2 - read-write - - - TX_WS_OUT_DM - The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. - 16 - 2 - read-write - - - TX_BCK_OUT_DM - The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. - 20 - 2 - read-write - - - TX_WS_IN_DM - The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. - 24 - 2 - read-write - - - TX_BCK_IN_DM - The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. - 28 - 2 - read-write - - - - - LC_HUNG_CONF - I2S HUNG configure register. - 0x60 - 0x20 - 0x00000810 - - - LC_FIFO_TIMEOUT - the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value - 0 - 8 - read-write - - - LC_FIFO_TIMEOUT_SHIFT - The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift - 8 - 3 - read-write - - - LC_FIFO_TIMEOUT_ENA - The enable bit for FIFO timeout - 11 - 1 - read-write - - - - - RXEOF_NUM - I2S RX data number control register. - 0x64 - 0x20 - 0x00000040 - - - RX_EOF_NUM - The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel. - 0 - 12 - read-write - - - - - CONF_SIGLE_DATA - I2S signal data register - 0x68 - 0x20 - - - SINGLE_DATA - The configured constant channel data to be sent out. - 0 - 32 - read-write - - - - - STATE - I2S TX status register - 0x6C - 0x20 - 0x00000001 - - - TX_IDLE - 1: i2s_tx is idle state. 0: i2s_tx is working. - 0 - 1 - read-only - - - - - ETM_CONF - I2S ETM configure register - 0x70 - 0x20 - 0x00010040 - - - ETM_TX_SEND_WORD_NUM - I2S ETM send x words event. When sending word number of reg_etm_tx_send_word_num[9:0], i2s will trigger an etm event. - 0 - 10 - read-write - - - ETM_RX_RECEIVE_WORD_NUM - I2S ETM receive x words event. When receiving word number of reg_etm_rx_receive_word_num[9:0], i2s will trigger an etm event. - 10 - 10 - read-write - - - - - FIFO_CNT - I2S sync counter register - 0x74 - 0x20 - - - TX_FIFO_CNT - tx fifo counter value. - 0 - 31 - read-only - - - TX_FIFO_CNT_RST - Set this bit to reset tx fifo counter. - 31 - 1 - write-only - - - - - BCK_CNT - I2S sync counter register - 0x78 - 0x20 - - - TX_BCK_CNT - tx bck counter value. - 0 - 31 - read-only - - - TX_BCK_CNT_RST - Set this bit to reset tx bck counter. - 31 - 1 - write-only - - - - - CLK_GATE - Clock gate register - 0x7C - 0x20 - - - CLK_EN - set this bit to enable clock gate - 0 - 1 - read-write - - - - - DATE - Version control register - 0x80 - 0x20 - 0x02303240 - - - DATE - I2S version control register - 0 - 28 - read-write - - - - - - - I2S1 - I2S (Inter-IC Sound) Controller 1 - 0x500C7000 - - I2S1 - 28 - - - - I2S2 - I2S (Inter-IC Sound) Controller 2 - 0x500C8000 - - I2S2 - 29 - - - - I3C_MST - I3C Controller (Master) - I3C_MST - 0x500DA000 - - 0x0 - 0x90 - registers - - - I3C - 101 - - - - DEVICE_CTRL - DEVICE_CTRL register controls the transfer properties and disposition of controllers capabilities. - 0x0 - 0x20 - 0x00001020 - - - REG_BA_INCLUDE - This bit is used to include I3C broadcast address(0x7E) for private transfer.(If I3C broadcast address is not include for the private transfer, In-Band Interrupts driven from Slaves may not win address arbitration. Hence IBIs will get delayed) - 1 - 1 - read-write - - - REG_TRANS_START - Transfer Start - 2 - 1 - read-write - - - REG_CLK_EN - NA - 3 - 1 - read-write - - - REG_IBI_RSTART_TRANS_EN - NA - 4 - 1 - read-write - - - REG_AUTO_DIS_IBI_EN - NA - 5 - 1 - read-write - - - REG_DMA_RX_EN - NA - 6 - 1 - read-write - - - REG_DMA_TX_EN - NA - 7 - 1 - read-write - - - REG_MULTI_SLV_SINGLE_CCC_EN - 0: rx high bit first, 1: rx low bit first - 8 - 1 - read-write - - - REG_RX_BIT_ORDER - 0: rx low byte fist, 1: rx high byte first - 9 - 1 - read-write - - - REG_RX_BYTE_ORDER - NA - 10 - 1 - read-write - - - REG_SCL_PULLUP_FORCE_EN - This bit is used to force scl_pullup_en - 11 - 1 - read-write - - - REG_SCL_OE_FORCE_EN - This bit is used to force scl_oe - 12 - 1 - read-write - - - REG_SDA_PP_RD_PULLUP_EN - NA - 13 - 1 - read-write - - - REG_SDA_RD_TBIT_HLVL_PULLUP_EN - NA - 14 - 1 - read-write - - - REG_SDA_PP_WR_PULLUP_EN - NA - 15 - 1 - read-write - - - REG_DATA_BYTE_CNT_UNLATCH - 1: read current real-time updated value 0: read latch data byte cnt value - 16 - 1 - read-write - - - REG_MEM_CLK_FORCE_ON - 1: dev characteristic and address table memory clk date force on . 0 : clock gating by rd/wr. - 17 - 1 - read-write - - - - - BUFFER_THLD_CTRL - In-Band Interrupt Status Threshold Value . Every In Band Interrupt received by I3C controller generates an IBI status. This field controls the number of IBI status entries in the IBI buffer that trigger the IBI_STATUS_THLD_STAT interrupt. - 0x1C - 0x20 - 0x00041041 - - - REG_CMD_BUF_EMPTY_THLD - Command Buffer Empty Threshold Value is used to control the number of empty locations(or greater) in the Command Buffer that trigger CMD_BUFFER_READY_STAT interrupt. - 0 - 4 - read-write - - - REG_RESP_BUF_THLD - Response Buffer Threshold Value is used to control the number of entries in the Response Buffer that trigger the RESP_READY_STAT_INTR. - 6 - 3 - read-write - - - REG_IBI_DATA_BUF_THLD - In-Band Interrupt Data Threshold Value . Every In Band Interrupt received by I3C controller generates an IBI status. This field controls the number of IBI data entries in the IBI buffer that trigger the IBI_DATA_THLD_STAT interrupt. - 12 - 3 - read-write - - - REG_IBI_STATUS_BUF_THLD - NA - 18 - 3 - read-write - - - - - DATA_BUFFER_THLD_CTRL - NA - 0x20 - 0x20 - 0x00000009 - - - REG_TX_DATA_BUF_THLD - Transmit Buffer Threshold Value. This field controls the number of empty locations in the Transmit FIFO that trigger the TX_THLD_STAT interrupt. Supports values: 000:2 001:4 010:8 011:16 100:31, else:31 - 0 - 3 - read-write - - - REG_RX_DATA_BUF_THLD - Receive Buffer Threshold Value. This field controls the number of empty locations in the Receive FIFO that trigger the RX_THLD_STAT interrupt. Supports: 000:2 001:4 010:8 011:16 100:31, else:31 - 3 - 3 - read-write - - - - - IBI_NOTIFY_CTRL - NA - 0x24 - 0x20 - - - REG_NOTIFY_SIR_REJECTED - Notify Rejected Slave Interrupt Request Control. This bit is used to suppress reporting to the application about Slave Interrupt Request. 0:Suppress passing the IBI Status to the IBI FIFO(hence not notifying the application) when a SIR request is NACKed and auto-disabled base on the IBI_SIR_REQ_REJECT register. 1: Writes IBI Status to the IBI FIFO(hence notifying the application) when SIR request is NACKed and auto-disabled based on the IBI_SIR_REQ_REJECT registerl. - 2 - 1 - read-write - - - - - IBI_SIR_REQ_PAYLOAD - NA - 0x28 - 0x20 - - - REG_SIR_REQ_PAYLOAD - NA - 0 - 32 - read-write - - - - - IBI_SIR_REQ_REJECT - NA - 0x2C - 0x20 - - - REG_SIR_REQ_REJECT - The application of controller can decide whether to send ACK or NACK for Slave request received from any I3C device. A device specific response control bit is provided to select the response option, Master will ACK/NACK the Master Request based on programming of control bit, corresponding to the interrupting device. 0:ACK the SIR Request 1:NACK and send direct auto disable CCC - 0 - 32 - read-write - - - - - INT_CLR - NA - 0x30 - 0x20 - - - TX_DATA_BUF_THLD_INT_CLR - NA - 0 - 1 - write-only - - - RX_DATA_BUF_THLD_INT_CLR - NA - 1 - 1 - write-only - - - IBI_STATUS_THLD_INT_CLR - NA - 2 - 1 - write-only - - - CMD_BUF_EMPTY_THLD_INT_CLR - NA - 3 - 1 - write-only - - - RESP_READY_INT_CLR - NA - 4 - 1 - write-only - - - NXT_CMD_REQ_ERR_INT_CLR - NA - 5 - 1 - write-only - - - TRANSFER_ERR_INT_CLR - NA - 6 - 1 - write-only - - - TRANSFER_COMPLETE_INT_CLR - NA - 7 - 1 - write-only - - - COMMAND_DONE_INT_CLR - NA - 8 - 1 - write-only - - - DETECT_START_INT_CLR - NA - 9 - 1 - write-only - - - RESP_BUF_OVF_INT_CLR - NA - 10 - 1 - write-only - - - IBI_DATA_BUF_OVF_INT_CLR - NA - 11 - 1 - write-only - - - IBI_STATUS_BUF_OVF_INT_CLR - NA - 12 - 1 - write-only - - - IBI_HANDLE_DONE_INT_CLR - NA - 13 - 1 - write-only - - - IBI_DETECT_INT_CLR - NA - 14 - 1 - write-only - - - CMD_CCC_MISMATCH_INT_CLR - NA - 15 - 1 - write-only - - - - - INT_RAW - NA - 0x34 - 0x20 - 0x00000008 - - - TX_DATA_BUF_THLD_INT_RAW - NA - 0 - 1 - read-write - - - RX_DATA_BUF_THLD_INT_RAW - NA - 1 - 1 - read-write - - - IBI_STATUS_THLD_INT_RAW - NA - 2 - 1 - read-write - - - CMD_BUF_EMPTY_THLD_INT_RAW - NA - 3 - 1 - read-write - - - RESP_READY_INT_RAW - NA - 4 - 1 - read-write - - - NXT_CMD_REQ_ERR_INT_RAW - NA - 5 - 1 - read-write - - - TRANSFER_ERR_INT_RAW - NA - 6 - 1 - read-write - - - TRANSFER_COMPLETE_INT_RAW - NA - 7 - 1 - read-write - - - COMMAND_DONE_INT_RAW - NA - 8 - 1 - read-write - - - DETECT_START_INT_RAW - NA - 9 - 1 - read-write - - - RESP_BUF_OVF_INT_RAW - NA - 10 - 1 - read-write - - - IBI_DATA_BUF_OVF_INT_RAW - NA - 11 - 1 - read-write - - - IBI_STATUS_BUF_OVF_INT_RAW - NA - 12 - 1 - read-write - - - IBI_HANDLE_DONE_INT_RAW - NA - 13 - 1 - read-write - - - IBI_DETECT_INT_RAW - NA - 14 - 1 - read-write - - - CMD_CCC_MISMATCH_INT_RAW - NA - 15 - 1 - read-write - - - - - INT_ST - NA - 0x38 - 0x20 - - - TX_DATA_BUF_THLD_INT_ST - This interrupt is generated when number of empty locations in transmit buffer is greater than or equal to threshold value specified by TX_EMPTY_BUS_THLD field in DATA_BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of empty locations in transmit buffer is less than threshold value. - 0 - 1 - read-only - - - RX_DATA_BUF_THLD_INT_ST - This interrupt is generated when number of entries in receive buffer is greater than or equal to threshold value specified by RX_BUF_THLD field in DATA_BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of entries in receive buffer is less than threshold value. - 1 - 1 - read-only - - - IBI_STATUS_THLD_INT_ST - Only used in master mode. This interrupt is generated when number of entries in IBI buffer is greater than or equal to threshold value specified by IBI_BUF_THLD field in BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of entries in IBI buffer is less than threshold value. - 2 - 1 - read-only - - - CMD_BUF_EMPTY_THLD_INT_ST - This interrupt is generated when number of empty locations in command buffer is greater than or equal to threshold value specified by CMD_EMPTY_BUF_THLD field in BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of empty locations in command buffer is less than threshold value. - 3 - 1 - read-only - - - RESP_READY_INT_ST - This interrupt is generated when number of entries in response buffer is greater than or equal to threshold value specified by RESP_BUF_THLD field in BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of entries in response buffer is less than threshold value. - 4 - 1 - read-only - - - NXT_CMD_REQ_ERR_INT_ST - This interrupt is generated if toc is 0(master will restart next command), but command buf is empty. - 5 - 1 - read-only - - - TRANSFER_ERR_INT_ST - This interrupt is generated if any error occurs during transfer. The error type will be specified in the response packet associated with the command (in ERR_STATUS field of RESPONSE_BUFFER_PORT register). This bit can be cleared by writing 1'h1. - 6 - 1 - read-only - - - TRANSFER_COMPLETE_INT_ST - NA - 7 - 1 - read-only - - - COMMAND_DONE_INT_ST - NA - 8 - 1 - read-only - - - DETECT_START_INT_ST - NA - 9 - 1 - read-only - - - RESP_BUF_OVF_INT_ST - NA - 10 - 1 - read-only - - - IBI_DATA_BUF_OVF_INT_ST - NA - 11 - 1 - read-only - - - IBI_STATUS_BUF_OVF_INT_ST - NA - 12 - 1 - read-only - - - IBI_HANDLE_DONE_INT_ST - NA - 13 - 1 - read-only - - - IBI_DETECT_INT_ST - NA - 14 - 1 - read-only - - - CMD_CCC_MISMATCH_INT_ST - NA - 15 - 1 - read-only - - - - - INT_ST_ENA - The Interrupt status will be updated in INTR_STATUS register if corresponding Status Enable bit set. - 0x3C - 0x20 - - - TX_DATA_BUF_THLD_INT_ENA - Transmit Buffer threshold status enable. - 0 - 1 - read-write - - - RX_DATA_BUF_THLD_INT_ENA - Receive Buffer threshold status enable. - 1 - 1 - read-write - - - IBI_STATUS_THLD_INT_ENA - Only used in master mode. IBI Buffer threshold status enable. - 2 - 1 - read-write - - - CMD_BUF_EMPTY_THLD_INT_ENA - Command buffer ready status enable. - 3 - 1 - read-write - - - RESP_READY_INT_ENA - Response buffer ready status enable. - 4 - 1 - read-write - - - NXT_CMD_REQ_ERR_INT_ENA - next command request error status enable - 5 - 1 - read-write - - - TRANSFER_ERR_INT_ENA - Transfer error status enable - 6 - 1 - read-write - - - TRANSFER_COMPLETE_INT_ENA - NA - 7 - 1 - read-write - - - COMMAND_DONE_INT_ENA - NA - 8 - 1 - read-write - - - DETECT_START_INT_ENA - NA - 9 - 1 - read-write - - - RESP_BUF_OVF_INT_ENA - NA - 10 - 1 - read-write - - - IBI_DATA_BUF_OVF_INT_ENA - NA - 11 - 1 - read-write - - - IBI_STATUS_BUF_OVF_INT_ENA - NA - 12 - 1 - read-write - - - IBI_HANDLE_DONE_INT_ENA - NA - 13 - 1 - read-write - - - IBI_DETECT_INT_ENA - NA - 14 - 1 - read-write - - - CMD_CCC_MISMATCH_INT_ENA - NA - 15 - 1 - read-write - - - - - RESET_CTRL - NA - 0x44 - 0x20 - - - REG_CORE_SOFT_RST - NA - 0 - 1 - write-only - - - REG_CMD_BUF_RST - NA - 1 - 1 - read-write - - - REG_RESP_BUF_RST - NA - 2 - 1 - read-write - - - REG_TX_DATA_BUF_BUF_RST - NA - 3 - 1 - read-write - - - REG_RX_DATA_BUF_RST - NA - 4 - 1 - read-write - - - REG_IBI_DATA_BUF_RST - NA - 5 - 1 - read-write - - - REG_IBI_STATUS_BUF_RST - NA - 6 - 1 - read-write - - - - - BUFFER_STATUS_LEVEL - BUFFER_STATUS_LEVEL reflects the status level of Buffers in the controller. - 0x48 - 0x20 - 0x00000010 - - - CMD_BUF_EMPTY_CNT - Command Buffer Empty Locations contains the number of empty locations in the command buffer. - 0 - 5 - read-only - - - RESP_BUF_CNT - Response Buffer Level Value contains the number of valid data entries in the response buffer. - 8 - 4 - read-only - - - IBI_DATA_BUF_CNT - IBI Buffer Level Value contains the number of valid entries in the IBI Buffer. This is field is used in master mode. - 16 - 4 - read-only - - - IBI_STATUS_BUF_CNT - IBI Buffer Status Count contains the number of IBI status entries in the IBI Buffer. This field is used in master mode. - 24 - 4 - read-only - - - - - DATA_BUFFER_STATUS_LEVEL - DATA_BUFFER_STATUS_LEVEL reflects the status level of the Buffers in the controller. - 0x4C - 0x20 - 0x00000020 - - - TX_DATA_BUF_EMPTY_CNT - Transmit Buffer Empty Level Value contains the number of empty locations in the transmit Buffer. - 0 - 6 - read-only - - - RX_DATA_BUF_CNT - Receive Buffer Level value contains the number of valid data entries in the receive buffer. - 16 - 6 - read-only - - - - - PRESENT_STATE0 - NA - 0x50 - 0x20 - 0x00000003 - - - SDA_LVL - This bit is used to check the SCL line level to recover from error and for debugging. This bit reflects the value of synchronized scl_in_a. - 0 - 1 - read-only - - - SCL_LVL - This bit is used to check the SDA line level to recover from error and for debugging. This bit reflects the value of synchronized sda_in_a. - 1 - 1 - read-only - - - BUS_BUSY - NA - 2 - 1 - read-only - - - BUS_FREE - NA - 3 - 1 - read-only - - - CMD_TID - NA - 9 - 4 - read-only - - - SCL_GEN_FSM_STATE - NA - 13 - 3 - read-only - - - IBI_EV_HANDLE_FSM_STATE - NA - 16 - 3 - read-only - - - I2C_MODE_FSM_STATE - NA - 19 - 3 - read-only - - - SDR_MODE_FSM_STATE - NA - 22 - 4 - read-only - - - DAA_MODE_FSM_STATE - Reflects whether the Master Controller is in IDLE or not. This bit will be set when all the buffer(Command, Response, IBI, Transmit, Receive) are empty along with the Master State machine is in idle state. 0X0: not in idle 0x1: in idle - 26 - 3 - read-only - - - MAIN_FSM_STATE - NA - 29 - 3 - read-only - - - - - PRESENT_STATE1 - NA - 0x54 - 0x20 - - - DATA_BYTE_CNT - Present transfer data byte cnt: tx data byte cnt if write rx data byte cnt if read ibi data byte cnt if IBI handle. - 0 - 16 - read-only - - - - - DEVICE_TABLE - Pointer for Device Address Table - 0x58 - 0x20 - - - REG_DCT_DAA_INIT_INDEX - Reserved - 0 - 4 - read-write - - - REG_DAT_DAA_INIT_INDEX - NA - 4 - 4 - read-write - - - PRESENT_DCT_INDEX - NA - 8 - 4 - read-only - - - PRESENT_DAT_INDEX - NA - 12 - 4 - read-only - - - - - TIME_OUT_VALUE - NA - 0x5C - 0x20 - 0x00410410 - - - REG_RESP_BUF_TO_VALUE - NA - 0 - 5 - read-write - - - REG_RESP_BUF_TO_EN - NA - 5 - 1 - read-write - - - REG_IBI_DATA_BUF_TO_VALUE - NA - 6 - 5 - read-write - - - REG_IBI_DATA_BUF_TO_EN - NA - 11 - 1 - read-write - - - REG_IBI_STATUS_BUF_TO_VALUE - NA - 12 - 5 - read-write - - - REG_IBI_STATUS_BUF_TO_EN - NA - 17 - 1 - read-write - - - REG_RX_DATA_BUF_TO_VALUE - NA - 18 - 5 - read-write - - - REG_RX_DATA_BUF_TO_EN - NA - 23 - 1 - read-write - - - - - SCL_I3C_MST_OD_TIME - NA - 0x60 - 0x20 - 0x00050019 - - - REG_I3C_MST_OD_LOW_PERIOD - SCL Open-Drain low count for I3C transfers targeted to I3C devices. - 0 - 16 - read-write - - - REG_I3C_MST_OD_HIGH_PERIOD - SCL Open-Drain High count for I3C transfers targeted to I3C devices. - 16 - 16 - read-write - - - - - SCL_I3C_MST_PP_TIME - NA - 0x64 - 0x20 - 0x00050005 - - - REG_I3C_MST_PP_LOW_PERIOD - NA - 0 - 8 - read-write - - - REG_I3C_MST_PP_HIGH_PERIOD - NA - 16 - 8 - read-write - - - - - SCL_I2C_FM_TIME - NA - 0x68 - 0x20 - 0x004B00A3 - - - REG_I2C_FM_LOW_PERIOD - NA - 0 - 16 - read-write - - - REG_I2C_FM_HIGH_PERIOD - The SCL open-drain low count timing for I2C Fast Mode transfers. - 16 - 16 - read-write - - - - - SCL_I2C_FMP_TIME - NA - 0x6C - 0x20 - 0x0021003F - - - REG_I2C_FMP_LOW_PERIOD - NA - 0 - 16 - read-write - - - REG_I2C_FMP_HIGH_PERIOD - NA - 16 - 8 - read-write - - - - - SCL_EXT_LOW_TIME - NA - 0x70 - 0x20 - - - REG_I3C_MST_EXT_LOW_PERIOD1 - NA - 0 - 8 - read-write - - - REG_I3C_MST_EXT_LOW_PERIOD2 - NA - 8 - 8 - read-write - - - REG_I3C_MST_EXT_LOW_PERIOD3 - NA - 16 - 8 - read-write - - - REG_I3C_MST_EXT_LOW_PERIOD4 - NA - 24 - 8 - read-write - - - - - SDA_SAMPLE_TIME - NA - 0x74 - 0x20 - - - REG_SDA_OD_SAMPLE_TIME - It is used to adjust sda sample point when scl high under open drain speed - 0 - 9 - read-write - - - REG_SDA_PP_SAMPLE_TIME - It is used to adjust sda sample point when scl high under push pull speed - 9 - 5 - read-write - - - - - SDA_HOLD_TIME - NA - 0x78 - 0x20 - 0x00000001 - - - REG_SDA_OD_TX_HOLD_TIME - It is used to adjust sda drive point after scl neg under open drain speed - 0 - 9 - read-write - - - REG_SDA_PP_TX_HOLD_TIME - It is used to adjust sda dirve point after scl neg under push pull speed - 9 - 5 - read-write - - - - - SCL_START_HOLD - NA - 0x7C - 0x20 - 0x00000008 - - - REG_SCL_START_HOLD_TIME - I2C_SCL_START_HOLD_TIME - 0 - 9 - read-write - - - REG_START_DET_HOLD_TIME - NA - 9 - 2 - read-write - - - - - SCL_RSTART_SETUP - NA - 0x80 - 0x20 - 0x00000008 - - - REG_SCL_RSTART_SETUP_TIME - I2C_SCL_RSTART_SETUP_TIME - 0 - 9 - read-write - - - - - SCL_STOP_HOLD - NA - 0x84 - 0x20 - 0x00000008 - - - REG_SCL_STOP_HOLD_TIME - I2C_SCL_STOP_HOLD_TIME - 0 - 9 - read-write - - - - - SCL_STOP_SETUP - NA - 0x88 - 0x20 - 0x00000008 - - - REG_SCL_STOP_SETUP_TIME - I2C_SCL_STOP_SETUP_TIME - 0 - 9 - read-write - - - - - BUS_FREE_TIME - NA - 0x90 - 0x20 - 0x00000005 - - - REG_BUS_FREE_TIME - I3C Bus Free Count Value. This field is used only in Master mode. In pure Bus System, this field represents tCAS. In Mixed Bus System, this field is expected to be programmed to tLOW of I2C Timing. - 0 - 16 - read-write - - - - - SCL_TERMN_T_EXT_LOW_TIME - NA - 0x94 - 0x20 - 0x00000002 - - - REG_I3C_MST_TERMN_T_EXT_LOW_TIME - NA - 0 - 8 - read-write - - - - - VER_ID - NA - 0xA0 - 0x20 - 0x20230504 - - - REG_I3C_MST_VER_ID - This field indicates the controller current release number that is read by an application. - 0 - 32 - read-write - - - - - VER_TYPE - NA - 0xA4 - 0x20 - - - REG_I3C_MST_VER_TYPE - This field indicates the controller current release type that is read by an application. - 0 - 32 - read-write - - - - - FPGA_DEBUG_PROBE - NA - 0xAC - 0x20 - 0x00000001 - - - REG_I3C_MST_FPGA_DEBUG_PROBE - For Debug Probe Test on FPGA - 0 - 32 - read-write - - - - - RND_ECO_CS - NA - 0xB0 - 0x20 - - - REG_RND_ECO_EN - NA - 0 - 1 - read-write - - - RND_ECO_RESULT - NA - 1 - 1 - read-only - - - - - RND_ECO_LOW - NA - 0xB4 - 0x20 - - - REG_RND_ECO_LOW - NA - 0 - 32 - read-write - - - - - RND_ECO_HIGH - NA - 0xB8 - 0x20 - 0x0000FFFF - - - REG_RND_ECO_HIGH - NA - 0 - 32 - read-write - - - - - - - I3C_MST_MEM - I3C_MST_MEM Peripheral - I3C_MST_MEM - 0x500DA000 - - 0x0 - 0x108 - registers - - - - COMMAND_BUF_PORT - NA - 0x8 - 0x20 - - - REG_COMMAND - Contains a Command Descriptor structure that depends on the requested transfer type. Command Descriptor structure is used to schedule the transfers to devices on I3C bus. - 0 - 32 - read-write - - - - - RESPONSE_BUF_PORT - NA - 0xC - 0x20 - - - RESPONSE - The Response Buffer can be read through this register. The response status for each Command is written into the Response Buffer by the controller if ROC (Response On Completion) bit is set or if transfer error has occurred. The response buffer can be read through this register. - 0 - 32 - read-only - - - - - RX_DATA_PORT - NA - 0x10 - 0x20 - - - RX_DATA_PORT - Receive Data Port. Receive data is mapped to the Rx-data buffer and receive data is always packed in 4-byte aligned data words. If the length of data transfer is not aligned to 4-bytes boundary, then there will be extra(unused) bytes(the additional data bytes have to be ignored) at the end of the transferred data. The valid data must be identified using the DATA_LENGTH filed in the Response Descriptor. - 0 - 32 - read-only - - - - - TX_DATA_PORT - NA - 0x14 - 0x20 - - - REG_TX_DATA_PORT - Transmit Data Port. Transmit data is mapped to the Tx-data buffer and transmit data is always packed in 4-byte aligned data words. If the length of data transfer is not aligned to 4-bytes boundary, then there will be extra(unused) bytes(the additional data bytes have to be ignored) at the end of the transferred data. The valid data must be identified using the DATA_LENGTH filed in the Response Descriptor. - 0 - 32 - read-write - - - - - IBI_STATUS_BUF - In-Band Interrupt Buffer Status/Data Register. When receiving an IBI, IBI_PORT is used to both: Read the IBI Status Read the IBI Data(which is raw/opaque data) - 0x18 - 0x20 - - - DATA_LENGTH - This field represents the length of data received along with IBI, in bytes. - 0 - 8 - read-only - - - IBI_ID - IBI Identifier. The byte received after START which includes the address the R/W bit: Device address and R/W bit in case of Slave Interrupt or Master Request. - 8 - 8 - read-only - - - IBI_STS - IBI received data/status. IBI Data register is mapped to the IBI Buffer. The IBI Data is always packed in4-byte aligned and put to the IBI Buffer. This register When read from, reads the data from the IBI buffer. IBI Status register when read from, returns the data from the IBI Buffer and indicates how the controller responded to incoming IBI(SIR, MR and HJ). - 28 - 1 - read-only - - - - - IBI_DATA_BUF - NA - 0x40 - 0x20 - - - IBI_DATA - NA - 0 - 32 - read-only - - - - - DEV_ADDR_TABLE1_LOC - NA - 0xC0 - 0x20 - - - REG_DAT_DEV1_STATIC_ADDR - NA - 0 - 7 - read-write - - - REG_DAT_DEV1_DYNAMIC_ADDR - Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. - 16 - 8 - read-write - - - REG_DAT_DEV1_NACK_RETRY_CNT - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. - 29 - 2 - read-write - - - REG_DAT_DEV1_I2C - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. - 31 - 1 - read-write - - - - - DEV_ADDR_TABLE2_LOC - NA - 0xC4 - 0x20 - - - REG_DAT_DEV2_STATIC_ADDR - NA - 0 - 7 - read-write - - - REG_DAT_DEV2_DYNAMIC_ADDR - Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. - 16 - 8 - read-write - - - REG_DAT_DEV2_NACK_RETRY_CNT - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. - 29 - 2 - read-write - - - REG_DAT_DEV2_I2C - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. - 31 - 1 - read-write - - - - - DEV_ADDR_TABLE3_LOC - NA - 0xC8 - 0x20 - - - REG_DAT_DEV3_STATIC_ADDR - NA - 0 - 7 - read-write - - - REG_DAT_DEV3_DYNAMIC_ADDR - Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. - 16 - 8 - read-write - - - REG_DAT_DEV3_NACK_RETRY_CNT - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. - 29 - 2 - read-write - - - REG_DAT_DEV3_I2C - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. - 31 - 1 - read-write - - - - - DEV_ADDR_TABLE4_LOC - NA - 0xCC - 0x20 - - - REG_DAT_DEV4_STATIC_ADDR - NA - 0 - 7 - read-write - - - REG_DAT_DEV4_DYNAMIC_ADDR - Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. - 16 - 8 - read-write - - - REG_DAT_DEV4_NACK_RETRY_CNT - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. - 29 - 2 - read-write - - - REG_DAT_DEV4_I2C - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. - 31 - 1 - read-write - - - - - DEV_ADDR_TABLE5_LOC - NA - 0xD0 - 0x20 - - - REG_DAT_DEV5_STATIC_ADDR - NA - 0 - 7 - read-write - - - REG_DAT_DEV5_DYNAMIC_ADDR - Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. - 16 - 8 - read-write - - - REG_DAT_DEV5_NACK_RETRY_CNT - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. - 29 - 2 - read-write - - - REG_DAT_DEV5_I2C - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. - 31 - 1 - read-write - - - - - DEV_ADDR_TABLE6_LOC - NA - 0xD4 - 0x20 - - - REG_DAT_DEV6_STATIC_ADDR - NA - 0 - 7 - read-write - - - REG_DAT_DEV6_DYNAMIC_ADDR - Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. - 16 - 8 - read-write - - - REG_DAT_DEV6_NACK_RETRY_CNT - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. - 29 - 2 - read-write - - - REG_DAT_DEV6_I2C - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. - 31 - 1 - read-write - - - - - DEV_ADDR_TABLE7_LOC - NA - 0xD8 - 0x20 - - - REG_DAT_DEV7_STATIC_ADDR - NA - 0 - 7 - read-write - - - REG_DAT_DEV7_DYNAMIC_ADDR - Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. - 16 - 8 - read-write - - - REG_DAT_DEV7_NACK_RETRY_CNT - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. - 29 - 2 - read-write - - - REG_DAT_DEV7_I2C - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. - 31 - 1 - read-write - - - - - DEV_ADDR_TABLE8_LOC - NA - 0xDC - 0x20 - - - REG_DAT_DEV8_STATIC_ADDR - NA - 0 - 7 - read-write - - - REG_DAT_DEV8_DYNAMIC_ADDR - Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. - 16 - 8 - read-write - - - REG_DAT_DEV8_NACK_RETRY_CNT - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. - 29 - 2 - read-write - - - REG_DAT_DEV8_I2C - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. - 31 - 1 - read-write - - - - - DEV_ADDR_TABLE9_LOC - NA - 0xE0 - 0x20 - - - REG_DAT_DEV9_STATIC_ADDR - NA - 0 - 7 - read-write - - - REG_DAT_DEV9_DYNAMIC_ADDR - Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. - 16 - 8 - read-write - - - REG_DAT_DEV9_NACK_RETRY_CNT - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. - 29 - 2 - read-write - - - REG_DAT_DEV9_I2C - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. - 31 - 1 - read-write - - - - - DEV_ADDR_TABLE10_LOC - NA - 0xE4 - 0x20 - - - REG_DAT_DEV10_STATIC_ADDR - NA - 0 - 7 - read-write - - - REG_DAT_DEV10_DYNAMIC_ADDR - Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. - 16 - 8 - read-write - - - REG_DAT_DEV10_NACK_RETRY_CNT - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. - 29 - 2 - read-write - - - REG_DAT_DEV10_I2C - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. - 31 - 1 - read-write - - - - - DEV_ADDR_TABLE11_LOC - NA - 0xE8 - 0x20 - - - REG_DAT_DEV11_STATIC_ADDR - NA - 0 - 7 - read-write - - - REG_DAT_DEV11_DYNAMIC_ADDR - Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. - 16 - 8 - read-write - - - REG_DAT_DEV11_NACK_RETRY_CNT - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. - 29 - 2 - read-write - - - REG_DAT_DEV11_I2C - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. - 31 - 1 - read-write - - - - - DEV_ADDR_TABLE12_LOC - NA - 0xEC - 0x20 - - - REG_DAT_DEV12_STATIC_ADDR - NA - 0 - 7 - read-write - - - REG_DAT_DEV12_DYNAMIC_ADDR - Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. - 16 - 8 - read-write - - - REG_DAT_DEV12_NACK_RETRY_CNT - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. - 29 - 2 - read-write - - - REG_DAT_DEV12_I2C - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. - 31 - 1 - read-write - - - - - DEV_CHAR_TABLE1_LOC1 - NA - 0x100 - 0x20 - - - DCT_DEV1_LOC1 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE1_LOC2 - NA - 0x104 - 0x20 - - - DCT_DEV1_LOC2 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE1_LOC3 - NA - 0x108 - 0x20 - - - DCT_DEV1_LOC3 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE1_LOC4 - NA - 0x10C - 0x20 - - - DCT_DEV1_LOC4 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE2_LOC1 - NA - 0x110 - 0x20 - - - DCT_DEV2_LOC1 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE2_LOC2 - NA - 0x114 - 0x20 - - - DCT_DEV2_LOC2 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE2_LOC3 - NA - 0x118 - 0x20 - - - DCT_DEV2_LOC3 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE2_LOC4 - NA - 0x11C - 0x20 - - - DCT_DEV2_LOC4 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE3_LOC1 - NA - 0x120 - 0x20 - - - DCT_DEV3_LOC1 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE3_LOC2 - NA - 0x124 - 0x20 - - - DCT_DEV3_LOC2 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE3_LOC3 - NA - 0x128 - 0x20 - - - DCT_DEV3_LOC3 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE3_LOC4 - NA - 0x12C - 0x20 - - - DCT_DEV3_LOC4 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE4_LOC1 - NA - 0x130 - 0x20 - - - DCT_DEV4_LOC1 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE4_LOC2 - NA - 0x134 - 0x20 - - - DCT_DEV4_LOC2 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE4_LOC3 - NA - 0x138 - 0x20 - - - DCT_DEV4_LOC3 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE4_LOC4 - NA - 0x13C - 0x20 - - - DCT_DEV4_LOC4 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE5_LOC1 - NA - 0x140 - 0x20 - - - DCT_DEV5_LOC1 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE5_LOC2 - NA - 0x144 - 0x20 - - - DCT_DEV5_LOC2 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE5_LOC3 - NA - 0x148 - 0x20 - - - DCT_DEV5_LOC3 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE5_LOC4 - NA - 0x14C - 0x20 - - - DCT_DEV5_LOC4 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE6_LOC1 - NA - 0x150 - 0x20 - - - DCT_DEV6_LOC1 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE6_LOC2 - NA - 0x154 - 0x20 - - - DCT_DEV6_LOC2 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE6_LOC3 - NA - 0x158 - 0x20 - - - DCT_DEV6_LOC3 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE6_LOC4 - NA - 0x15C - 0x20 - - - DCT_DEV6_LOC4 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE7_LOC1 - NA - 0x160 - 0x20 - - - DCT_DEV7_LOC1 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE7_LOC2 - NA - 0x164 - 0x20 - - - DCT_DEV7_LOC2 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE7_LOC3 - NA - 0x168 - 0x20 - - - DCT_DEV7_LOC3 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE7_LOC4 - NA - 0x16C - 0x20 - - - DCT_DEV7_LOC4 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE8_LOC1 - NA - 0x170 - 0x20 - - - DCT_DEV8_LOC1 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE8_LOC2 - NA - 0x174 - 0x20 - - - DCT_DEV8_LOC2 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE8_LOC3 - NA - 0x178 - 0x20 - - - DCT_DEV8_LOC3 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE8_LOC4 - NA - 0x17C - 0x20 - - - DCT_DEV8_LOC4 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE9_LOC1 - NA - 0x180 - 0x20 - - - DCT_DEV9_LOC1 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE9_LOC2 - NA - 0x184 - 0x20 - - - DCT_DEV9_LOC2 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE9_LOC3 - NA - 0x188 - 0x20 - - - DCT_DEV9_LOC3 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE9_LOC4 - NA - 0x18C - 0x20 - - - DCT_DEV9_LOC4 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE10_LOC1 - NA - 0x190 - 0x20 - - - DCT_DEV10_LOC1 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE10_LOC2 - NA - 0x194 - 0x20 - - - DCT_DEV10_LOC2 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE10_LOC3 - NA - 0x198 - 0x20 - - - DCT_DEV10_LOC3 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE10_LOC4 - NA - 0x19C - 0x20 - - - DCT_DEV10_LOC4 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE11_LOC1 - NA - 0x1A0 - 0x20 - - - DCT_DEV11_LOC1 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE11_LOC2 - NA - 0x1A4 - 0x20 - - - DCT_DEV11_LOC2 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE11_LOC3 - NA - 0x1A8 - 0x20 - - - DCT_DEV11_LOC3 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE11_LOC4 - NA - 0x1AC - 0x20 - - - DCT_DEV11_LOC4 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE12_LOC1 - NA - 0x1B0 - 0x20 - - - DCT_DEV12_LOC1 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE12_LOC2 - NA - 0x1B4 - 0x20 - - - DCT_DEV12_LOC2 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE12_LOC3 - NA - 0x1B8 - 0x20 - - - DCT_DEV12_LOC3 - NA - 0 - 32 - read-only - - - - - DEV_CHAR_TABLE12_LOC4 - NA - 0x1BC - 0x20 - - - DCT_DEV12_LOC4 - NA - 0 - 32 - read-only - - - - - - - I3C_SLV - I3C Controller (Slave) - I3C_SLV - 0x500DB000 - - 0x0 - 0x40 - registers - - - I3C_SLV - 102 - - - - CONFIG - NA - 0x4 - 0x20 - 0x002F0001 - - - SLVENA - 1: allow the slave to operate on i2c or i3c bus. 0: the slave will ignore the bus. This should be not set until registers such as PARTNO, IDEXT and the like are set 1st -if used- since they impact data to the master - 0 - 1 - read-write - - - NACK - 1:the slave will NACK all requests to it except CCC broadcast. This should be used with caution as the Master may determine the slave is missing if overused. - 1 - 1 - read-write - - - MATCHSS - 1: the START and STOP sticky STATUS bits will only be set if MATCHED is set..This allows START and STOP to be used to detect end of a message to /from this slave. - 2 - 1 - read-write - - - S0IGNORE - If 1, the Slave will not detect S0 or S1 errors and so not lock up waiting on an Exit Pattern. This should only be used when the bus will not use HDR. - 3 - 1 - read-write - - - DDROK - NA - 4 - 1 - read-write - - - IDRAND - NA - 8 - 1 - read-write - - - OFFLINE - NA - 9 - 1 - read-write - - - BAMATCH - Bus Available condition match value for current ???Slow clock???. This provides the count of the slow clock to count out 1us (or more) to allow an IBI to drive SDA Low when the Master is not doing so. The max width , and so max value, is controlled by the block. Only if enabled for events such IBI or MR or HJ, and if enabled to provide this as a register. With is limited to CLK_SLOW_BITS - 16 - 8 - read-write - - - SADDR - If allowed by the block:sets i2c 7 bits static address,else should be 0. If enabled to use one and to be provided by SW. Block may provide in HW as well. - 25 - 7 - read-write - - - - - STATUS - NA - 0x8 - 0x20 - - - STNOTSTOP - Is 1 if bus is busy(activity) and 0 when in a STOP condition. Other bits may also set when busy. Note that this can also be true from an S0 or S1 error, which waits for an Exit Pattern. - 0 - 1 - read-only - - - STMSG - Is 1 if this bus Slave is listening to the bus traffic or repsonding, If STNOSTOP=1, then this will be 0 when a non-matching address seen until next respeated START it STOP. - 1 - 1 - read-only - - - STCCCH - Is 1 if a CCC message is being handled automatically. - 2 - 1 - read-only - - - STREQRD - 1 if the req in process is an sdr read from this slave or an IBI is being pushed out, - 3 - 1 - read-only - - - STREQWR - NA - 4 - 1 - read-only - - - STDAA - NA - 5 - 1 - read-only - - - STHDR - NA - 6 - 1 - read-only - - - START - NA - 8 - 1 - read-write - - - MATCHED - NA - 9 - 1 - read-write - - - STOP - NA - 10 - 1 - read-write - - - RXPEND - Receiving a message from master,which is not being handled by block(not a CCC internally processed). For all but External FIFO, this uses DATACTRL RXTRIG, which defaults to not-empty. If DMA is enabled for RX, DMA will be signaled as well. Will self-clear if data is read(FIFO and non-FIFO) - 11 - 1 - read-only - - - TXNOTFULL - Is 1 when the To-bus buffer/FIFO can accept more data to go out. Defau:1. For all but External FIFO, this uses DATACTRL TXTRIG,which defaults to not-full. If DMA is enabled for TX, it will also be signaled to provide more. - 12 - 1 - read-only - - - DACHG - The Slv Dynamic Address has been assigned, reassigned, or reset(lost) and is now in that state of being valid or none. Actual DA can be seen in the DYNADDR register. Note that this will also be used when MAP Auto feature is configured. This will be changing one or more MAP items. See DYNADDR and/or MAPCTRLn. DYNAADDR for the main DA(0) will indicate if last change was due to Auto MAP. - 13 - 1 - read-write - - - CCC - A common -command-code(CCC), not handled by block, has been received. This acts differently between: *Broadcasted ones, which will then also correspond with RXPEND and the 1st byte will be the CCC(command) . *Direct ones, which may never be directed to this device. If it is, then the TXSEND or RXPEND will be triggered with this end the RXPEND will contain the command. - 14 - 1 - read-write - - - ERRWARN - NA - 15 - 1 - read-only - - - HDRMATCH - NA - 16 - 1 - read-write - - - - - CTRL - NA - 0xC - 0x20 - - - SLV_EVENT - If set to non-0, will request an event. Once requested, STATUS.EVENT and EVDET will show the status as it progresses. Once completed, the field will automatically return to 0. Once non-0, only 0 can be written(to cancel) until done. 0: Normal mode. If set to 0 after was a non-0 value, will cancel if not already in flight. 1: start an IBI. This will try to push through an IBI on the bus. If data associate with the IBI, it will be drawn from the IBIDATA field. Note that if Time control is enabled, this will include anytime control related bytes further, the IBIDATA byte will have bit7 set to 1. - 0 - 2 - read-write - - - EXTDATA - reserved - 3 - 1 - read-write - - - MAPIDX - Index of Dynamic Address that IBI is for. This is 0 for the main or base Dynamic Address, or can be any valid index. - 4 - 4 - read-write - - - IBIDATA - Data byte to go with an IBI, if enabled for it. If enabled (was in BCR), then it is required. - 8 - 8 - read-write - - - PENDINT - Should be set to the pending interrupt that GETSTATUS CCC will return. This should be maintained by the application if used and configured, as the Master will read this. If not configured, the GETSTATUS field will return 1 if an IBI is pending, and 0 otherwise. - 16 - 4 - read-write - - - ACTSTATE - NA - 20 - 2 - read-write - - - VENDINFO - NA - 24 - 8 - read-write - - - - - INTSET - INSET allows setting enables for interrupts(connecting the corresponding STATUS source to causing an IRQ to the processor) - 0x10 - 0x20 - - - STOP_ENA - Interrupt on STOP state on the bus. See Start as the preferred interrupt when needed. This interrupt may not trigger for quick STOP/START combination, as it relates to the state of being stopped. - 10 - 1 - read-write - - - RXPEND_ENA - Interrupt when receiving a message from Master, which is not being handled by the block (excludes CCCs being handled automatically). If FIFO, then RX fullness trigger. If DMA, then message end. - 11 - 1 - read-write - - - TXSEND_ENA - NA - 12 - 1 - read-write - - - - - INTCLR - NA - 0x14 - 0x20 - - - STOP_CLR - Interrupt on STOP state on the bus. See Start as the preferred interrupt when needed. This interrupt may not trigger for quick STOP/START combination, as it relates to the state of being stopped. - 10 - 1 - write-only - - - RXPEND_CLR - Interrupt when receiving a message from Master, which is not being handled by the block (excludes CCCs being handled automatically). If FIFO, then RX fullness trigger. If DMA, then message end. - 11 - 1 - write-only - - - TXSEND_CLR - NA - 12 - 1 - write-only - - - - - INTMASKED - NA - 0x18 - 0x20 - - - STOP_MASK - Interrupt on STOP state on the bus. See Start as the preferred interrupt when needed. This interrupt may not trigger for quick STOP/START combination, as it relates to the state of being stopped. - 10 - 1 - read-only - - - RXPEND_MASK - Interrupt when receiving a message from Master, which is not being handled by the block (excludes CCCs being handled automatically). If FIFO, then RX fullness trigger. If DMA, then message end. - 11 - 1 - read-only - - - TXSEND_MASK - NA - 12 - 1 - read-only - - - - - DATACTRL - NA - 0x2C - 0x20 - 0x000000B0 - - - FLUSHTB - Flushes the from-bus buffer/FIFO. Not normally used - 0 - 1 - write-only - - - FLUSHFB - Flushes the to-bus buffer/FIFO. Used when Master terminates a to-bus (read) message prematurely - 1 - 1 - write-only - - - UNLOCK - If this bit is not written 1, the register bits from 7 to 4 are not changed on write. - 3 - 1 - write-only - - - TXTRIG - Trigger level for tx emptiness when FIFOed, Affects interrupt and DMA(if enabled). The defaults is 3 - 4 - 2 - read-write - - - RXTRIG - Trigger level for rx fulless when FIFOed, Affects interrupt and DMA(if enabled). The defaults is 3 - 6 - 2 - read-write - - - TXCOUNT - NA - 16 - 5 - read-only - - - RXCOUNT - NA - 24 - 5 - read-only - - - TXFULL - NA - 30 - 1 - read-only - - - RXEMPTY - NA - 31 - 1 - read-only - - - - - WDATAB - NA - 0x30 - 0x20 - - - WDATAB - NA - 0 - 8 - write-only - - - WDATA_END - NA - 8 - 1 - write-only - - - - - WDATABE - NA - 0x34 - 0x20 - - - WDATABE - NA - 0 - 8 - write-only - - - - - RDARAB - Read Byte Data (from-bus) register - 0x40 - 0x20 - - - DATA0 - This register allows reading a byte from the bus unless external FIFO is used. A byte should not be read unless there is data waiting, as indicated by the RXPEND bit being set in the STATUS register - 0 - 8 - read-only - - - - - RDATAH - Read Half-word Data (from-bus) register - 0x48 - 0x20 - - - DATA_LSB - NA - 0 - 8 - read-only - - - DATA_MSB - This register allows reading a Half-word (byte pair) from the bus unless external FIFO is used. A Half-word should not be read unless there is at least 2 bytes of data waiting, as indicated by the RX FIFO level trigger or RXCOUNT available space in the DATACTRL register - 8 - 8 - read-only - - - - - CAPABILITIES2 - NA - 0x5C - 0x20 - 0x00000100 - - - CAPABLITIES2 - NA - 0 - 32 - read-only - - - - - CAPABILITIES - NA - 0x60 - 0x20 - 0x7C13FC1C - - - CAPABLITIES - NA - 0 - 32 - read-only - - - - - IDPARTNO - NA - 0x6C - 0x20 - - - PARTNO - NA - 0 - 32 - read-write - - - - - IDEXT - NA - 0x70 - 0x20 - - - IDEXT - NA - 0 - 32 - read-write - - - - - VENDORID - NA - 0x74 - 0x20 - 0x00005550 - - - VID - NA - 0 - 15 - read-write - - - - - - - AXI_ICM - AXI_ICM Peripheral - ICM_AXI - 0x500A4000 - - 0x0 - 0x10 - registers - - - - VERID_FILEDS - NA - 0x0 - 0x20 - 0x3430342A - - - ICM_REG_VERID - NA - 0 - 32 - read-only - - - - - HW_CFG - NA - 0x4 - 0x20 - 0x0070D151 - - - ICM_REG_AXI_HWCFG_QOS_SUPPORT - NA - 0 - 1 - read-only - - - ICM_REG_AXI_HWCFG_APB3_SUPPORT - NA - 1 - 1 - read-only - - - ICM_REG_AXI_HWCFG_AXI4_SUPPORT - NA - 2 - 1 - read-only - - - ICM_REG_AXI_HWCFG_LOCK_EN - NA - 3 - 1 - read-only - - - ICM_REG_AXI_HWCFG_TRUST_ZONE_EN - NA - 4 - 1 - read-only - - - ICM_REG_AXI_HWCFG_DECODER_TYPE - NA - 5 - 1 - read-only - - - ICM_REG_AXI_HWCFG_REMAP_EN - NA - 6 - 1 - read-only - - - ICM_REG_AXI_HWCFG_BI_DIR_CMD_EN - NA - 7 - 1 - read-only - - - ICM_REG_AXI_HWCFG_LOW_POWER_INF_EN - NA - 8 - 1 - read-only - - - ICM_REG_AXI_HWCFG_AXI_NUM_MASTERS - NA - 12 - 5 - read-only - - - ICM_REG_AXI_HWCFG_AXI_NUM_SLAVES - NA - 20 - 5 - read-only - - - - - CMD - NA - 0x8 - 0x20 - - - ICM_REG_AXI_CMD - NA - 0 - 3 - read-write - - - ICM_REG_RD_WR_CHAN - NA - 7 - 1 - read-write - - - ICM_REG_AXI_MASTER_PORT - NA - 8 - 4 - read-write - - - ICM_REG_AXI_ERR_BIT - NA - 28 - 1 - read-only - - - ICM_REG_AXI_SOFT_RESET_BIT - NA - 29 - 1 - read-write - - - ICM_REG_AXI_RD_WR_CMD - NA - 30 - 1 - read-write - - - ICM_REG_AXI_CMD_EN - NA - 31 - 1 - read-write - - - - - DATA - NA - 0xC - 0x20 - - - ICM_REG_DATA - NA - 0 - 32 - read-write - - - - - - - IO_MUX - Input/Output Multiplexer - IO_MUX - 0x500E1000 - - 0x0 - 0xE8 - registers - - - - DATE - iomux version - 0x104 - 0x20 - 0x00201222 - - - DATE - csv date - 0 - 28 - read-write - - - - - 54 - 0x4 - 0-53 - GPIO%s - IO_MUX Control Register - 0x4 - 0x20 - read-write - - - MCU_OE - Configures whether or not to enable the output of GPIOn in sleep mode. 0: Disable 1: Enable - 0 - 1 - - - SLP_SEL - Configures whether or not to enter sleep mode for GPIOn. 0: Not enter 1: Enter - 1 - 1 - - - MCU_WPD - Configure whether or not to enable pull-down resistor of GPIOn during sleep mode. 0: Disable 1: Enable - 2 - 1 - - - MCU_WPU - Configures whether or not to enable pull-up resistor of GPIOn during sleep mode. 0: Disable 1: Enable - 3 - 1 - - - MCU_IE - Configures whether or not to enable the input of GPIOn during sleep mode. 0: Disable 1: Enable - 4 - 1 - - - MCU_DRV - Configures the drive strength of GPIOn during sleep mode. 0: ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA - 5 - 2 - - - FUN_WPD - Configures whether or not to enable pull-down resistor of GPIOn. 0: Disable 1: Enable - 7 - 1 - - - FUN_WPU - Configures whether or not enable pull-up resistor of GPIOn. 0: Disable 1: Enable - 8 - 1 - - - FUN_IE - Configures whether or not to enable input of GPIOn. 0: Disable 1: Enable - 9 - 1 - - - FUN_DRV - Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA - 10 - 2 - - - MCU_SEL - Configures to select IO MUX function for this pin. 0: Select Function 0 1: Select Function 1 ...... - 12 - 3 - - - FILTER_EN - Configures whether or not to enable filter for pin input signals. 0: Disable 1: Enable - 15 - 1 - - - - - - - ISP - ISP Peripheral - ISP - 0x500A1000 - - 0x0 - 0x244 - registers - - - ISP - 100 - - - - VER_DATE - version control register - 0x0 - 0x20 - 0x20210608 - - - VER_DATA - csv version - 0 - 32 - read-write - - - - - CLK_EN - isp clk control register - 0x4 - 0x20 - - - CLK_EN - this bit configures the clk force on of isp reg. 0: disable, 1: enable - 0 - 1 - read-write - - - CLK_BLC_FORCE_ON - this bit configures the clk force on of blc. 0: disable, 1: enable - 1 - 1 - read-write - - - CLK_DPC_FORCE_ON - this bit configures the clk force on of dpc. 0: disable, 1: enable - 2 - 1 - read-write - - - CLK_BF_FORCE_ON - this bit configures the clk force on of bf. 0: disable, 1: enable - 3 - 1 - read-write - - - CLK_LSC_FORCE_ON - this bit configures the clk force on of lsc. 0: disable, 1: enable - 4 - 1 - read-write - - - CLK_DEMOSAIC_FORCE_ON - this bit configures the clk force on of demosaic. 0: disable, 1: enable - 5 - 1 - read-write - - - CLK_MEDIAN_FORCE_ON - this bit configures the clk force on of median. 0: disable, 1: enable - 6 - 1 - read-write - - - CLK_CCM_FORCE_ON - this bit configures the clk force on of ccm. 0: disable, 1: enable - 7 - 1 - read-write - - - CLK_GAMMA_FORCE_ON - this bit configures the clk force on of gamma. 0: disable, 1: enable - 8 - 1 - read-write - - - CLK_RGB2YUV_FORCE_ON - this bit configures the clk force on of rgb2yuv. 0: disable, 1: enable - 9 - 1 - read-write - - - CLK_SHARP_FORCE_ON - this bit configures the clk force on of sharp. 0: disable, 1: enable - 10 - 1 - read-write - - - CLK_COLOR_FORCE_ON - this bit configures the clk force on of color. 0: disable, 1: enable - 11 - 1 - read-write - - - CLK_YUV2RGB_FORCE_ON - this bit configures the clk force on of yuv2rgb. 0: disable, 1: enable - 12 - 1 - read-write - - - CLK_AE_FORCE_ON - this bit configures the clk force on of ae. 0: disable, 1: enable - 13 - 1 - read-write - - - CLK_AF_FORCE_ON - this bit configures the clk force on of af. 0: disable, 1: enable - 14 - 1 - read-write - - - CLK_AWB_FORCE_ON - this bit configures the clk force on of awb. 0: disable, 1: enable - 15 - 1 - read-write - - - CLK_HIST_FORCE_ON - this bit configures the clk force on of hist. 0: disable, 1: enable - 16 - 1 - read-write - - - CLK_MIPI_IDI_FORCE_ON - this bit configures the clk force on of mipi idi input. 0: disable, 1: enable - 17 - 1 - read-write - - - ISP_MEM_CLK_FORCE_ON - this bit configures the clk force on of all isp memory. 0: disable, 1: enable - 18 - 1 - read-write - - - - - CNTL - isp module enable control register - 0x8 - 0x20 - 0x40002442 - - - MIPI_DATA_EN - this bit configures mipi input data enable. 0: disable, 1: enable - 0 - 1 - read-write - - - ISP_EN - this bit configures isp global enable. 0: disable, 1: enable - 1 - 1 - read-write - - - BLC_EN - this bit configures blc enable. 0: disable, 1: enable - 2 - 1 - read-write - - - DPC_EN - this bit configures dpc enable. 0: disable, 1: enable - 3 - 1 - read-write - - - BF_EN - this bit configures bf enable. 0: disable, 1: enable - 4 - 1 - read-write - - - LSC_EN - this bit configures lsc enable. 0: disable, 1: enable - 5 - 1 - read-write - - - DEMOSAIC_EN - this bit configures demosaic enable. 0: disable, 1: enable - 6 - 1 - read-write - - - MEDIAN_EN - this bit configures median enable. 0: disable, 1: enable - 7 - 1 - read-write - - - CCM_EN - this bit configures ccm enable. 0: disable, 1: enable - 8 - 1 - read-write - - - GAMMA_EN - this bit configures gamma enable. 0: disable, 1: enable - 9 - 1 - read-write - - - RGB2YUV_EN - this bit configures rgb2yuv enable. 0: disable, 1: enable - 10 - 1 - read-write - - - SHARP_EN - this bit configures sharp enable. 0: disable, 1: enable - 11 - 1 - read-write - - - COLOR_EN - this bit configures color enable. 0: disable, 1: enable - 12 - 1 - read-write - - - YUV2RGB_EN - this bit configures yuv2rgb enable. 0: disable, 1: enable - 13 - 1 - read-write - - - AE_EN - this bit configures ae enable. 0: disable, 1: enable - 14 - 1 - read-write - - - AF_EN - this bit configures af enable. 0: disable, 1: enable - 15 - 1 - read-write - - - AWB_EN - this bit configures awb enable. 0: disable, 1: enable - 16 - 1 - read-write - - - HIST_EN - this bit configures hist enable. 0: disable, 1: enable - 17 - 1 - read-write - - - BYTE_ENDIAN_ORDER - select input idi data byte_endian_order when isp is bypass, 0: csi_data[31:0], 1: {[7:0], [15:8], [23:16], [31:24]} - 24 - 1 - read-write - - - ISP_DATA_TYPE - this field configures input data type, 0:RAW8 1:RAW10 2:RAW12 - 25 - 2 - read-write - - - ISP_IN_SRC - this field configures input data source, 0:CSI HOST 1:CAM 2:DMA - 27 - 2 - read-write - - - ISP_OUT_TYPE - this field configures pixel output type, 0: RAW8 1: YUV422 2: RGB888 3: YUV420 4: RGB565 - 29 - 3 - read-write - - - - - HSYNC_CNT - header hsync interval control register - 0xC - 0x20 - 0x00000007 - - - HSYNC_CNT - this field configures the number of clock before hsync and after vsync and line_end when decodes pix data from idi to isp - 0 - 8 - read-write - - - - - FRAME_CFG - frame control parameter register - 0x10 - 0x20 - 0x601E01E0 - - - VADR_NUM - this field configures input image size in y-direction, image row number - 1 - 0 - 12 - read-write - - - HADR_NUM - this field configures input image size in x-direction, image line number - 1 - 12 - 12 - read-write - - - BAYER_MODE - this field configures the bayer mode of input pixel. 00 : BG/GR 01 : GB/RG 10 : GR/BG 11 : RG/GB - 27 - 2 - read-write - - - HSYNC_START_EXIST - this bit configures the line end packet exist or not. 0: not exist, 1: exist - 29 - 1 - read-write - - - HSYNC_END_EXIST - this bit configures the line start packet exist or not. 0: not exist, 1: exist - 30 - 1 - read-write - - - - - CCM_COEF0 - ccm coef register 0 - 0x14 - 0x20 - 0x02500740 - - - CCM_RR - this field configures the color correction matrix coefficient - 0 - 13 - read-write - - - CCM_RG - this field configures the color correction matrix coefficient - 13 - 13 - read-write - - - - - CCM_COEF1 - ccm coef register 1 - 0x18 - 0x20 - 0x022810C0 - - - CCM_RB - this field configures the color correction matrix coefficient - 0 - 13 - read-write - - - CCM_GR - this field configures the color correction matrix coefficient - 13 - 13 - read-write - - - - - CCM_COEF3 - ccm coef register 3 - 0x1C - 0x20 - 0x02200680 - - - CCM_GG - this field configures the color correction matrix coefficient - 0 - 13 - read-write - - - CCM_GB - this field configures the color correction matrix coefficient - 13 - 13 - read-write - - - - - CCM_COEF4 - ccm coef register 4 - 0x20 - 0x20 - 0x02581040 - - - CCM_BR - this field configures the color correction matrix coefficient - 0 - 13 - read-write - - - CCM_BG - this field configures the color correction matrix coefficient - 13 - 13 - read-write - - - - - CCM_COEF5 - ccm coef register 5 - 0x24 - 0x20 - 0x00000740 - - - CCM_BB - this field configures the color correction matrix coefficient - 0 - 13 - read-write - - - - - BF_MATRIX_CTRL - bf pix2matrix ctrl - 0x28 - 0x20 - - - BF_TAIL_PIXEN_PULSE_TL - matrix tail pixen low level threshold, should not to large to prevent expanding to next frame, only reg_bf_tail_pixen_pulse_th!=0 and reg_bf_tail_pixen_pulse_tl!=0 and reg_bf_tail_pixen_pulse_th < reg_bf_tail_pixen_pulse_tl will enable tail pulse function - 0 - 8 - read-write - - - BF_TAIL_PIXEN_PULSE_TH - matrix tail pixen high level threshold, must < hnum-1, only reg_bf_tail_pixen_pulse_th!=0 and reg_bf_tail_pixen_pulse_tl!=0 and reg_bf_tail_pixen_pulse_th < reg_bf_tail_pixen_pulse_tl will enable tail pulse function - 8 - 8 - read-write - - - BF_PADDING_DATA - this field configures bf matrix padding data - 16 - 8 - read-write - - - BF_PADDING_MODE - this bit configures the padding mode of bf matrix. 0: use pixel in image to do padding 1: use reg_padding_data to do padding - 24 - 1 - read-write - - - - - BF_SIGMA - bf denoising level control register - 0x2C - 0x20 - 0x00000002 - - - SIGMA - this field configures the bayer denoising level, valid data from 2 to 20 - 0 - 6 - read-write - - - - - BF_GAU0 - bf gau template register 0 - 0x30 - 0x20 - 0xFFFFFFFF - - - GAU_TEMPLATE21 - this field configures index 21 of gausian template - 0 - 4 - read-write - - - GAU_TEMPLATE20 - this field configures index 20 of gausian template - 4 - 4 - read-write - - - GAU_TEMPLATE12 - this field configures index 12 of gausian template - 8 - 4 - read-write - - - GAU_TEMPLATE11 - this field configures index 11 of gausian template - 12 - 4 - read-write - - - GAU_TEMPLATE10 - this field configures index 10 of gausian template - 16 - 4 - read-write - - - GAU_TEMPLATE02 - this field configures index 02 of gausian template - 20 - 4 - read-write - - - GAU_TEMPLATE01 - this field configures index 01 of gausian template - 24 - 4 - read-write - - - GAU_TEMPLATE00 - this field configures index 00 of gausian template - 28 - 4 - read-write - - - - - BF_GAU1 - bf gau template register 1 - 0x34 - 0x20 - 0x0000000F - - - GAU_TEMPLATE22 - this field configures index 22 of gausian template - 0 - 4 - read-write - - - - - DPC_CTRL - DPC mode control register - 0x38 - 0x20 - 0x00000004 - - - DPC_CHECK_EN - this bit configures the check mode enable. 0: disable, 1: enable - 0 - 1 - read-write - - - STA_EN - this bit configures the sta dpc enable. 0: disable, 1: enable - 1 - 1 - read-write - - - DYN_EN - this bit configures the dyn dpc enable. 0: disable, 1: enable - 2 - 1 - read-write - - - DPC_BLACK_EN - this bit configures input image type select when in check mode, 0: white img, 1: black img - 3 - 1 - read-write - - - DPC_METHOD_SEL - this bit configures dyn dpc method select. 0: simple method, 1: hard method - 4 - 1 - read-write - - - DPC_CHECK_OD_EN - this bit configures output pixel data when in check mode or not. 0: no data output, 1: data output - 5 - 1 - read-write - - - - - DPC_CONF - DPC parameter config register - 0x3C - 0x20 - 0x04103030 - - - DPC_THRESHOLD_L - this bit configures the threshold to detect black img in check mode, or the low threshold(use 8 bit 0~255) in dyn method 0, or the low threshold factor (use 5 bit 10000-> 16/16, 00001->1/16, 0/16~16/16) in dyn method 1 - 0 - 8 - read-write - - - DPC_THRESHOLD_H - this bit configures the threshold to detect white img in check mode, or the high threshold(use 8 bit 0~255) in dyn method 0, or the high threshold factor (use 5 bit 10000-> 16/16, 00001->1/16, 0/16~16/16) in dyn method 1 - 8 - 8 - read-write - - - DPC_FACTOR_DARK - this field configures the dynamic correction method 1 dark factor - 16 - 6 - read-write - - - DPC_FACTOR_BRIG - this field configures the dynamic correction method 1 bright factor - 22 - 6 - read-write - - - - - DPC_MATRIX_CTRL - dpc pix2matrix ctrl - 0x40 - 0x20 - - - DPC_TAIL_PIXEN_PULSE_TL - matrix tail pixen low level threshold, should not to large to prevent expanding to next frame, only reg_dpc_tail_pixen_pulse_th!=0 and reg_dpc_tail_pixen_pulse_tl!=0 and reg_dpc_tail_pixen_pulse_th < reg_dpc_tail_pixen_pulse_tl will enable tail pulse function - 0 - 8 - read-write - - - DPC_TAIL_PIXEN_PULSE_TH - matrix tail pixen high level threshold, must < hnum-1, only reg_dpc_tail_pixen_pulse_th!=0 and reg_dpc_tail_pixen_pulse_tl!=0 and reg_dpc_tail_pixen_pulse_th < reg_dpc_tail_pixen_pulse_tl will enable tail pulse function - 8 - 8 - read-write - - - DPC_PADDING_DATA - this field configures dpc matrix padding data - 16 - 8 - read-write - - - DPC_PADDING_MODE - this bit configures the padding mode of dpc matrix. 0: use pixel in image to do padding 1: use reg_padding_data to do padding - 24 - 1 - read-write - - - - - DPC_DEADPIX_CNT - DPC dead-pix number register - 0x44 - 0x20 - - - DPC_DEADPIX_CNT - this field represents the dead pixel count - 0 - 10 - read-only - - - - - LUT_CMD - LUT command register - 0x48 - 0x20 - - - LUT_ADDR - this field configures the lut access addr, when select lsc lut, [11:10]:00 sel gb_b lut, 01 sel r_gr lut - 0 - 12 - write-only - - - LUT_NUM - this field configures the lut selection. 0000:LSC LUT 0001:DPC LUT - 12 - 4 - write-only - - - LUT_CMD - this bit configures the access event of lut. 0:rd 1: wr - 16 - 1 - write-only - - - - - LUT_WDATA - LUT write data register - 0x4C - 0x20 - - - LUT_WDATA - this field configures the write data of lut. please initial ISP_LUT_WDATA before write ISP_LUT_CMD register - 0 - 32 - read-write - - - - - LUT_RDATA - LUT read data register - 0x50 - 0x20 - - - LUT_RDATA - this field represents the read data of lut. read ISP_LUT_RDATA after write ISP_LUT_CMD register - 0 - 32 - read-only - - - - - LSC_TABLESIZE - LSC point in x-direction - 0x54 - 0x20 - 0x0000001F - - - LSC_XTABLESIZE - this field configures lsc table size in x-direction - 0 - 5 - read-write - - - - - DEMOSAIC_MATRIX_CTRL - demosaic pix2matrix ctrl - 0x58 - 0x20 - - - DEMOSAIC_TAIL_PIXEN_PULSE_TL - matrix tail pixen low level threshold, should not to large to prevent expanding to next frame, only reg_demosaic_tail_pixen_pulse_th!=0 and reg_demosaic_tail_pixen_pulse_tl!=0 and reg_demosaic_tail_pixen_pulse_th < reg_demosaic_tail_pixen_pulse_tl will enable tail pulse function - 0 - 8 - read-write - - - DEMOSAIC_TAIL_PIXEN_PULSE_TH - matrix tail pixen high level threshold, must < hnum-1, only reg_demosaic_tail_pixen_pulse_th!=0 and reg_demosaic_tail_pixen_pulse_tl!=0 and reg_demosaic_tail_pixen_pulse_th < reg_demosaic_tail_pixen_pulse_tl will enable tail pulse function - 8 - 8 - read-write - - - DEMOSAIC_PADDING_DATA - this field configures demosaic matrix padding data - 16 - 8 - read-write - - - DEMOSAIC_PADDING_MODE - this bit configures the padding mode of demosaic matrix. 0: use pixel in image to do padding 1: use reg_padding_data to do padding - 24 - 1 - read-write - - - - - DEMOSAIC_GRAD_RATIO - demosaic gradient select ratio - 0x5C - 0x20 - 0x00000010 - - - DEMOSAIC_GRAD_RATIO - this field configures demosaic gradient select ratio - 0 - 6 - read-write - - - - - MEDIAN_MATRIX_CTRL - median pix2matrix ctrl - 0x60 - 0x20 - - - MEDIAN_PADDING_DATA - this field configures median matrix padding data - 0 - 8 - read-write - - - MEDIAN_PADDING_MODE - this bit configures the padding mode of median matrix. 0: use pixel in image to do padding 1: use reg_padding_data to do padding - 8 - 1 - read-write - - - - - INT_RAW - raw interrupt register - 0x64 - 0x20 - - - ISP_DATA_TYPE_ERR_INT_RAW - the raw interrupt status of input data type error. isp only support RGB bayer data type, other type will report type_err_int - 0 - 1 - read-only - - - ISP_ASYNC_FIFO_OVF_INT_RAW - the raw interrupt status of isp input fifo overflow - 1 - 1 - read-only - - - ISP_BUF_FULL_INT_RAW - the raw interrupt status of isp input buffer full - 2 - 1 - read-only - - - ISP_HVNUM_SETTING_ERR_INT_RAW - the raw interrupt status of hnum and vnum setting format error - 3 - 1 - read-only - - - ISP_DATA_TYPE_SETTING_ERR_INT_RAW - the raw interrupt status of setting invalid reg_data_type - 4 - 1 - read-only - - - ISP_MIPI_HNUM_UNMATCH_INT_RAW - the raw interrupt status of hnum setting unmatch with mipi input - 5 - 1 - read-only - - - DPC_CHECK_DONE_INT_RAW - the raw interrupt status of dpc check done - 6 - 1 - read-only - - - GAMMA_XCOORD_ERR_INT_RAW - the raw interrupt status of gamma setting error. it report the sum of the lengths represented by reg_gamma_x00~x0F isn't equal to 256 - 7 - 1 - read-only - - - AE_MONITOR_INT_RAW - the raw interrupt status of ae monitor - 8 - 1 - read-only - - - AE_FRAME_DONE_INT_RAW - the raw interrupt status of ae. - 9 - 1 - read-only - - - AF_FDONE_INT_RAW - the raw interrupt status of af statistic. when auto_update enable, each frame done will send one int pulse when manual_update, each time when write 1 to reg_manual_update will send a int pulse when next frame done - 10 - 1 - read-only - - - AF_ENV_INT_RAW - the raw interrupt status of af monitor. send a int pulse when env_det function enabled and environment changes detected - 11 - 1 - read-only - - - AWB_FDONE_INT_RAW - the raw interrupt status of awb. send a int pulse when statistic of one awb frame done - 12 - 1 - read-only - - - HIST_FDONE_INT_RAW - the raw interrupt status of histogram. send a int pulse when statistic of one frame histogram done - 13 - 1 - read-only - - - FRAME_INT_RAW - the raw interrupt status of isp frame end - 14 - 1 - read-only - - - BLC_FRAME_INT_RAW - the raw interrupt status of blc frame done - 15 - 1 - read-only - - - LSC_FRAME_INT_RAW - the raw interrupt status of lsc frame done - 16 - 1 - read-only - - - DPC_FRAME_INT_RAW - the raw interrupt status of dpc frame done - 17 - 1 - read-only - - - BF_FRAME_INT_RAW - the raw interrupt status of bf frame done - 18 - 1 - read-only - - - DEMOSAIC_FRAME_INT_RAW - the raw interrupt status of demosaic frame done - 19 - 1 - read-only - - - MEDIAN_FRAME_INT_RAW - the raw interrupt status of median frame done - 20 - 1 - read-only - - - CCM_FRAME_INT_RAW - the raw interrupt status of ccm frame done - 21 - 1 - read-only - - - GAMMA_FRAME_INT_RAW - the raw interrupt status of gamma frame done - 22 - 1 - read-only - - - RGB2YUV_FRAME_INT_RAW - the raw interrupt status of rgb2yuv frame done - 23 - 1 - read-only - - - SHARP_FRAME_INT_RAW - the raw interrupt status of sharp frame done - 24 - 1 - read-only - - - COLOR_FRAME_INT_RAW - the raw interrupt status of color frame done - 25 - 1 - read-only - - - YUV2RGB_FRAME_INT_RAW - the raw interrupt status of yuv2rgb frame done - 26 - 1 - read-only - - - TAIL_IDI_FRAME_INT_RAW - the raw interrupt status of isp_tail idi frame_end - 27 - 1 - read-only - - - HEADER_IDI_FRAME_INT_RAW - the raw interrupt status of real input frame end of isp_input - 28 - 1 - read-only - - - - - INT_ST - masked interrupt register - 0x68 - 0x20 - - - ISP_DATA_TYPE_ERR_INT_ST - the masked interrupt status of input data type error - 0 - 1 - read-only - - - ISP_ASYNC_FIFO_OVF_INT_ST - the masked interrupt status of isp input fifo overflow - 1 - 1 - read-only - - - ISP_BUF_FULL_INT_ST - the masked interrupt status of isp input buffer full - 2 - 1 - read-only - - - ISP_HVNUM_SETTING_ERR_INT_ST - the masked interrupt status of hnum and vnum setting format error - 3 - 1 - read-only - - - ISP_DATA_TYPE_SETTING_ERR_INT_ST - the masked interrupt status of setting invalid reg_data_type - 4 - 1 - read-only - - - ISP_MIPI_HNUM_UNMATCH_INT_ST - the masked interrupt status of hnum setting unmatch with mipi input - 5 - 1 - read-only - - - DPC_CHECK_DONE_INT_ST - the masked interrupt status of dpc check done - 6 - 1 - read-only - - - GAMMA_XCOORD_ERR_INT_ST - the masked interrupt status of gamma setting error - 7 - 1 - read-only - - - AE_MONITOR_INT_ST - the masked interrupt status of ae monitor - 8 - 1 - read-only - - - AE_FRAME_DONE_INT_ST - the masked interrupt status of ae - 9 - 1 - read-only - - - AF_FDONE_INT_ST - the masked interrupt status of af statistic - 10 - 1 - read-only - - - AF_ENV_INT_ST - the masked interrupt status of af monitor - 11 - 1 - read-only - - - AWB_FDONE_INT_ST - the masked interrupt status of awb - 12 - 1 - read-only - - - HIST_FDONE_INT_ST - the masked interrupt status of histogram - 13 - 1 - read-only - - - FRAME_INT_ST - the masked interrupt status of isp frame end - 14 - 1 - read-only - - - BLC_FRAME_INT_ST - the masked interrupt status of blc frame done - 15 - 1 - read-only - - - LSC_FRAME_INT_ST - the masked interrupt status of lsc frame done - 16 - 1 - read-only - - - DPC_FRAME_INT_ST - the masked interrupt status of dpc frame done - 17 - 1 - read-only - - - BF_FRAME_INT_ST - the masked interrupt status of bf frame done - 18 - 1 - read-only - - - DEMOSAIC_FRAME_INT_ST - the masked interrupt status of demosaic frame done - 19 - 1 - read-only - - - MEDIAN_FRAME_INT_ST - the masked interrupt status of median frame done - 20 - 1 - read-only - - - CCM_FRAME_INT_ST - the masked interrupt status of ccm frame done - 21 - 1 - read-only - - - GAMMA_FRAME_INT_ST - the masked interrupt status of gamma frame done - 22 - 1 - read-only - - - RGB2YUV_FRAME_INT_ST - the masked interrupt status of rgb2yuv frame done - 23 - 1 - read-only - - - SHARP_FRAME_INT_ST - the masked interrupt status of sharp frame done - 24 - 1 - read-only - - - COLOR_FRAME_INT_ST - the masked interrupt status of color frame done - 25 - 1 - read-only - - - YUV2RGB_FRAME_INT_ST - the masked interrupt status of yuv2rgb frame done - 26 - 1 - read-only - - - TAIL_IDI_FRAME_INT_ST - the masked interrupt status of isp_tail idi frame_end - 27 - 1 - read-only - - - HEADER_IDI_FRAME_INT_ST - the masked interrupt status of real input frame end of isp_input - 28 - 1 - read-only - - - - - INT_ENA - interrupt enable register - 0x6C - 0x20 - 0x000000C3 - - - ISP_DATA_TYPE_ERR_INT_ENA - write 1 to enable input data type error - 0 - 1 - read-write - - - ISP_ASYNC_FIFO_OVF_INT_ENA - write 1 to enable isp input fifo overflow - 1 - 1 - read-write - - - ISP_BUF_FULL_INT_ENA - write 1 to enable isp input buffer full - 2 - 1 - read-write - - - ISP_HVNUM_SETTING_ERR_INT_ENA - write 1 to enable hnum and vnum setting format error - 3 - 1 - read-write - - - ISP_DATA_TYPE_SETTING_ERR_INT_ENA - write 1 to enable setting invalid reg_data_type - 4 - 1 - read-write - - - ISP_MIPI_HNUM_UNMATCH_INT_ENA - write 1 to enable hnum setting unmatch with mipi input - 5 - 1 - read-write - - - DPC_CHECK_DONE_INT_ENA - write 1 to enable dpc check done - 6 - 1 - read-write - - - GAMMA_XCOORD_ERR_INT_ENA - write 1 to enable gamma setting error - 7 - 1 - read-write - - - AE_MONITOR_INT_ENA - write 1 to enable ae monitor - 8 - 1 - read-write - - - AE_FRAME_DONE_INT_ENA - write 1 to enable ae - 9 - 1 - read-write - - - AF_FDONE_INT_ENA - write 1 to enable af statistic - 10 - 1 - read-write - - - AF_ENV_INT_ENA - write 1 to enable af monitor - 11 - 1 - read-write - - - AWB_FDONE_INT_ENA - write 1 to enable awb - 12 - 1 - read-write - - - HIST_FDONE_INT_ENA - write 1 to enable histogram - 13 - 1 - read-write - - - FRAME_INT_ENA - write 1 to enable isp frame end - 14 - 1 - read-write - - - BLC_FRAME_INT_ENA - write 1 to enable blc frame done - 15 - 1 - read-write - - - LSC_FRAME_INT_ENA - write 1 to enable lsc frame done - 16 - 1 - read-write - - - DPC_FRAME_INT_ENA - write 1 to enable dpc frame done - 17 - 1 - read-write - - - BF_FRAME_INT_ENA - write 1 to enable bf frame done - 18 - 1 - read-write - - - DEMOSAIC_FRAME_INT_ENA - write 1 to enable demosaic frame done - 19 - 1 - read-write - - - MEDIAN_FRAME_INT_ENA - write 1 to enable median frame done - 20 - 1 - read-write - - - CCM_FRAME_INT_ENA - write 1 to enable ccm frame done - 21 - 1 - read-write - - - GAMMA_FRAME_INT_ENA - write 1 to enable gamma frame done - 22 - 1 - read-write - - - RGB2YUV_FRAME_INT_ENA - write 1 to enable rgb2yuv frame done - 23 - 1 - read-write - - - SHARP_FRAME_INT_ENA - write 1 to enable sharp frame done - 24 - 1 - read-write - - - COLOR_FRAME_INT_ENA - write 1 to enable color frame done - 25 - 1 - read-write - - - YUV2RGB_FRAME_INT_ENA - write 1 to enable yuv2rgb frame done - 26 - 1 - read-write - - - TAIL_IDI_FRAME_INT_ENA - write 1 to enable isp_tail idi frame_end - 27 - 1 - read-write - - - HEADER_IDI_FRAME_INT_ENA - write 1 to enable real input frame end of isp_input - 28 - 1 - read-write - - - - - INT_CLR - interrupt clear register - 0x70 - 0x20 - - - ISP_DATA_TYPE_ERR_INT_CLR - write 1 to clear input data type error - 0 - 1 - write-only - - - ISP_ASYNC_FIFO_OVF_INT_CLR - write 1 to clear isp input fifo overflow - 1 - 1 - write-only - - - ISP_BUF_FULL_INT_CLR - write 1 to clear isp input buffer full - 2 - 1 - write-only - - - ISP_HVNUM_SETTING_ERR_INT_CLR - write 1 to clear hnum and vnum setting format error - 3 - 1 - write-only - - - ISP_DATA_TYPE_SETTING_ERR_INT_CLR - write 1 to clear setting invalid reg_data_type - 4 - 1 - write-only - - - ISP_MIPI_HNUM_UNMATCH_INT_CLR - write 1 to clear hnum setting unmatch with mipi input - 5 - 1 - write-only - - - DPC_CHECK_DONE_INT_CLR - write 1 to clear dpc check done - 6 - 1 - write-only - - - GAMMA_XCOORD_ERR_INT_CLR - write 1 to clear gamma setting error - 7 - 1 - write-only - - - AE_MONITOR_INT_CLR - write 1 to clear ae monitor - 8 - 1 - write-only - - - AE_FRAME_DONE_INT_CLR - write 1 to clear ae - 9 - 1 - write-only - - - AF_FDONE_INT_CLR - write 1 to clear af statistic - 10 - 1 - write-only - - - AF_ENV_INT_CLR - write 1 to clear af monitor - 11 - 1 - write-only - - - AWB_FDONE_INT_CLR - write 1 to clear awb - 12 - 1 - write-only - - - HIST_FDONE_INT_CLR - write 1 to clear histogram - 13 - 1 - write-only - - - FRAME_INT_CLR - write 1 to clear isp frame end - 14 - 1 - write-only - - - BLC_FRAME_INT_CLR - write 1 to clear blc frame done - 15 - 1 - write-only - - - LSC_FRAME_INT_CLR - write 1 to clear lsc frame done - 16 - 1 - write-only - - - DPC_FRAME_INT_CLR - write 1 to clear dpc frame done - 17 - 1 - write-only - - - BF_FRAME_INT_CLR - write 1 to clear bf frame done - 18 - 1 - write-only - - - DEMOSAIC_FRAME_INT_CLR - write 1 to clear demosaic frame done - 19 - 1 - write-only - - - MEDIAN_FRAME_INT_CLR - write 1 to clear median frame done - 20 - 1 - write-only - - - CCM_FRAME_INT_CLR - write 1 to clear ccm frame done - 21 - 1 - write-only - - - GAMMA_FRAME_INT_CLR - write 1 to clear gamma frame done - 22 - 1 - write-only - - - RGB2YUV_FRAME_INT_CLR - write 1 to clear rgb2yuv frame done - 23 - 1 - write-only - - - SHARP_FRAME_INT_CLR - write 1 to clear sharp frame done - 24 - 1 - write-only - - - COLOR_FRAME_INT_CLR - write 1 to clear color frame done - 25 - 1 - write-only - - - YUV2RGB_FRAME_INT_CLR - write 1 to clear yuv2rgb frame done - 26 - 1 - write-only - - - TAIL_IDI_FRAME_INT_CLR - write 1 to clear isp_tail idi frame_end - 27 - 1 - write-only - - - HEADER_IDI_FRAME_INT_CLR - write 1 to clear real input frame end of isp_input - 28 - 1 - write-only - - - - - GAMMA_CTRL - gamma control register - 0x74 - 0x20 - 0x0000000E - - - GAMMA_UPDATE - Indicates that gamma register configuration is complete - 0 - 1 - read-write - - - GAMMA_B_LAST_CORRECT - this bit configures enable of last b segment correcction. 0: disable, 1: enable - 1 - 1 - read-write - - - GAMMA_G_LAST_CORRECT - this bit configures enable of last g segment correcction. 0: disable, 1: enable - 2 - 1 - read-write - - - GAMMA_R_LAST_CORRECT - this bit configures enable of last r segment correcction. 0: disable, 1: enable - 3 - 1 - read-write - - - - - GAMMA_RY1 - point of Y-axis of r channel gamma curve register 1 - 0x78 - 0x20 - 0x10203040 - - - GAMMA_R_Y03 - this field configures the point 3 of Y-axis of r channel gamma curve - 0 - 8 - read-write - - - GAMMA_R_Y02 - this field configures the point 2 of Y-axis of r channel gamma curve - 8 - 8 - read-write - - - GAMMA_R_Y01 - this field configures the point 1 of Y-axis of r channel gamma curve - 16 - 8 - read-write - - - GAMMA_R_Y00 - this field configures the point 0 of Y-axis of r channel gamma curve - 24 - 8 - read-write - - - - - GAMMA_RY2 - point of Y-axis of r channel gamma curve register 2 - 0x7C - 0x20 - 0x50607080 - - - GAMMA_R_Y07 - this field configures the point 7 of Y-axis of r channel gamma curve - 0 - 8 - read-write - - - GAMMA_R_Y06 - this field configures the point 6 of Y-axis of r channel gamma curve - 8 - 8 - read-write - - - GAMMA_R_Y05 - this field configures the point 5 of Y-axis of r channel gamma curve - 16 - 8 - read-write - - - GAMMA_R_Y04 - this field configures the point 4 of Y-axis of r channel gamma curve - 24 - 8 - read-write - - - - - GAMMA_RY3 - point of Y-axis of r channel gamma curve register 3 - 0x80 - 0x20 - 0x90A0B0C0 - - - GAMMA_R_Y0B - this field configures the point 11 of Y-axis of r channel gamma curve - 0 - 8 - read-write - - - GAMMA_R_Y0A - this field configures the point 10 of Y-axis of r channel gamma curve - 8 - 8 - read-write - - - GAMMA_R_Y09 - this field configures the point 9 of Y-axis of r channel gamma curve - 16 - 8 - read-write - - - GAMMA_R_Y08 - this field configures the point 8 of Y-axis of r channel gamma curve - 24 - 8 - read-write - - - - - GAMMA_RY4 - point of Y-axis of r channel gamma curve register 4 - 0x84 - 0x20 - 0xD0E0F0FF - - - GAMMA_R_Y0F - this field configures the point 15 of Y-axis of r channel gamma curve - 0 - 8 - read-write - - - GAMMA_R_Y0E - this field configures the point 14 of Y-axis of r channel gamma curve - 8 - 8 - read-write - - - GAMMA_R_Y0D - this field configures the point 13 of Y-axis of r channel gamma curve - 16 - 8 - read-write - - - GAMMA_R_Y0C - this field configures the point 12 of Y-axis of r channel gamma curve - 24 - 8 - read-write - - - - - GAMMA_GY1 - point of Y-axis of g channel gamma curve register 1 - 0x88 - 0x20 - 0x10203040 - - - GAMMA_G_Y03 - this field configures the point 3 of Y-axis of g channel gamma curve - 0 - 8 - read-write - - - GAMMA_G_Y02 - this field configures the point 2 of Y-axis of g channel gamma curve - 8 - 8 - read-write - - - GAMMA_G_Y01 - this field configures the point 1 of Y-axis of g channel gamma curve - 16 - 8 - read-write - - - GAMMA_G_Y00 - this field configures the point 0 of Y-axis of g channel gamma curve - 24 - 8 - read-write - - - - - GAMMA_GY2 - point of Y-axis of g channel gamma curve register 2 - 0x8C - 0x20 - 0x50607080 - - - GAMMA_G_Y07 - this field configures the point 7 of Y-axis of g channel gamma curve - 0 - 8 - read-write - - - GAMMA_G_Y06 - this field configures the point 6 of Y-axis of g channel gamma curve - 8 - 8 - read-write - - - GAMMA_G_Y05 - this field configures the point 5 of Y-axis of g channel gamma curve - 16 - 8 - read-write - - - GAMMA_G_Y04 - this field configures the point 4 of Y-axis of g channel gamma curve - 24 - 8 - read-write - - - - - GAMMA_GY3 - point of Y-axis of g channel gamma curve register 3 - 0x90 - 0x20 - 0x90A0B0C0 - - - GAMMA_G_Y0B - this field configures the point 11 of Y-axis of g channel gamma curve - 0 - 8 - read-write - - - GAMMA_G_Y0A - this field configures the point 10 of Y-axis of g channel gamma curve - 8 - 8 - read-write - - - GAMMA_G_Y09 - this field configures the point 9 of Y-axis of g channel gamma curve - 16 - 8 - read-write - - - GAMMA_G_Y08 - this field configures the point 8 of Y-axis of g channel gamma curve - 24 - 8 - read-write - - - - - GAMMA_GY4 - point of Y-axis of g channel gamma curve register 4 - 0x94 - 0x20 - 0xD0E0F0FF - - - GAMMA_G_Y0F - this field configures the point 15 of Y-axis of g channel gamma curve - 0 - 8 - read-write - - - GAMMA_G_Y0E - this field configures the point 14 of Y-axis of g channel gamma curve - 8 - 8 - read-write - - - GAMMA_G_Y0D - this field configures the point 13 of Y-axis of g channel gamma curve - 16 - 8 - read-write - - - GAMMA_G_Y0C - this field configures the point 12 of Y-axis of g channel gamma curve - 24 - 8 - read-write - - - - - GAMMA_BY1 - point of Y-axis of b channel gamma curve register 1 - 0x98 - 0x20 - 0x10203040 - - - GAMMA_B_Y03 - this field configures the point 3 of Y-axis of b channel gamma curve - 0 - 8 - read-write - - - GAMMA_B_Y02 - this field configures the point 2 of Y-axis of b channel gamma curve - 8 - 8 - read-write - - - GAMMA_B_Y01 - this field configures the point 1 of Y-axis of b channel gamma curve - 16 - 8 - read-write - - - GAMMA_B_Y00 - this field configures the point 0 of Y-axis of b channel gamma curve - 24 - 8 - read-write - - - - - GAMMA_BY2 - point of Y-axis of b channel gamma curve register 2 - 0x9C - 0x20 - 0x50607080 - - - GAMMA_B_Y07 - this field configures the point 7 of Y-axis of b channel gamma curve - 0 - 8 - read-write - - - GAMMA_B_Y06 - this field configures the point 6 of Y-axis of b channel gamma curve - 8 - 8 - read-write - - - GAMMA_B_Y05 - this field configures the point 5 of Y-axis of b channel gamma curve - 16 - 8 - read-write - - - GAMMA_B_Y04 - this field configures the point 4 of Y-axis of b channel gamma curve - 24 - 8 - read-write - - - - - GAMMA_BY3 - point of Y-axis of b channel gamma curve register 3 - 0xA0 - 0x20 - 0x90A0B0C0 - - - GAMMA_B_Y0B - this field configures the point 11 of Y-axis of b channel gamma curve - 0 - 8 - read-write - - - GAMMA_B_Y0A - this field configures the point 10 of Y-axis of b channel gamma curve - 8 - 8 - read-write - - - GAMMA_B_Y09 - this field configures the point 9 of Y-axis of b channel gamma curve - 16 - 8 - read-write - - - GAMMA_B_Y08 - this field configures the point 8 of Y-axis of b channel gamma curve - 24 - 8 - read-write - - - - - GAMMA_BY4 - point of Y-axis of b channel gamma curve register 4 - 0xA4 - 0x20 - 0xD0E0F0FF - - - GAMMA_B_Y0F - this field configures the point 15 of Y-axis of b channel gamma curve - 0 - 8 - read-write - - - GAMMA_B_Y0E - this field configures the point 14 of Y-axis of b channel gamma curve - 8 - 8 - read-write - - - GAMMA_B_Y0D - this field configures the point 13 of Y-axis of b channel gamma curve - 16 - 8 - read-write - - - GAMMA_B_Y0C - this field configures the point 12 of Y-axis of b channel gamma curve - 24 - 8 - read-write - - - - - GAMMA_RX1 - point of X-axis of r channel gamma curve register 1 - 0xA8 - 0x20 - 0x00924924 - - - GAMMA_R_X07 - this field configures the point 7 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point - 0 - 3 - read-write - - - GAMMA_R_X06 - this field configures the point 6 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point - 3 - 3 - read-write - - - GAMMA_R_X05 - this field configures the point 5 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point - 6 - 3 - read-write - - - GAMMA_R_X04 - this field configures the point 4 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point - 9 - 3 - read-write - - - GAMMA_R_X03 - this field configures the point 3 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point - 12 - 3 - read-write - - - GAMMA_R_X02 - this field configures the point 2 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point - 15 - 3 - read-write - - - GAMMA_R_X01 - this field configures the point 1 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point - 18 - 3 - read-write - - - GAMMA_R_X00 - this field configures the point 0 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point - 21 - 3 - read-write - - - - - GAMMA_RX2 - point of X-axis of r channel gamma curve register 2 - 0xAC - 0x20 - 0x00924924 - - - GAMMA_R_X0F - this field configures the point 15 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point - 0 - 3 - read-write - - - GAMMA_R_X0E - this field configures the point 14 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point - 3 - 3 - read-write - - - GAMMA_R_X0D - this field configures the point 13 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point - 6 - 3 - read-write - - - GAMMA_R_X0C - this field configures the point 12 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point - 9 - 3 - read-write - - - GAMMA_R_X0B - this field configures the point 11 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point - 12 - 3 - read-write - - - GAMMA_R_X0A - this field configures the point 10 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point - 15 - 3 - read-write - - - GAMMA_R_X09 - this field configures the point 9 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point - 18 - 3 - read-write - - - GAMMA_R_X08 - this field configures the point 8 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point - 21 - 3 - read-write - - - - - GAMMA_GX1 - point of X-axis of g channel gamma curve register 1 - 0xB0 - 0x20 - 0x00924924 - - - GAMMA_G_X07 - this field configures the point 7 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point - 0 - 3 - read-write - - - GAMMA_G_X06 - this field configures the point 6 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point - 3 - 3 - read-write - - - GAMMA_G_X05 - this field configures the point 5 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point - 6 - 3 - read-write - - - GAMMA_G_X04 - this field configures the point 4 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point - 9 - 3 - read-write - - - GAMMA_G_X03 - this field configures the point 3 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point - 12 - 3 - read-write - - - GAMMA_G_X02 - this field configures the point 2 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point - 15 - 3 - read-write - - - GAMMA_G_X01 - this field configures the point 1 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point - 18 - 3 - read-write - - - GAMMA_G_X00 - this field configures the point 0 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point - 21 - 3 - read-write - - - - - GAMMA_GX2 - point of X-axis of g channel gamma curve register 2 - 0xB4 - 0x20 - 0x00924924 - - - GAMMA_G_X0F - this field configures the point 15 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point - 0 - 3 - read-write - - - GAMMA_G_X0E - this field configures the point 14 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point - 3 - 3 - read-write - - - GAMMA_G_X0D - this field configures the point 13 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point - 6 - 3 - read-write - - - GAMMA_G_X0C - this field configures the point 12 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point - 9 - 3 - read-write - - - GAMMA_G_X0B - this field configures the point 11 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point - 12 - 3 - read-write - - - GAMMA_G_X0A - this field configures the point 10 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point - 15 - 3 - read-write - - - GAMMA_G_X09 - this field configures the point 9 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point - 18 - 3 - read-write - - - GAMMA_G_X08 - this field configures the point 8 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point - 21 - 3 - read-write - - - - - GAMMA_BX1 - point of X-axis of b channel gamma curve register 1 - 0xB8 - 0x20 - 0x00924924 - - - GAMMA_B_X07 - this field configures the point 7 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point - 0 - 3 - read-write - - - GAMMA_B_X06 - this field configures the point 6 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point - 3 - 3 - read-write - - - GAMMA_B_X05 - this field configures the point 5 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point - 6 - 3 - read-write - - - GAMMA_B_X04 - this field configures the point 4 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point - 9 - 3 - read-write - - - GAMMA_B_X03 - this field configures the point 3 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point - 12 - 3 - read-write - - - GAMMA_B_X02 - this field configures the point 2 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point - 15 - 3 - read-write - - - GAMMA_B_X01 - this field configures the point 1 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point - 18 - 3 - read-write - - - GAMMA_B_X00 - this field configures the point 0 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point - 21 - 3 - read-write - - - - - GAMMA_BX2 - point of X-axis of b channel gamma curve register 2 - 0xBC - 0x20 - 0x00924924 - - - GAMMA_B_X0F - this field configures the point 15 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point - 0 - 3 - read-write - - - GAMMA_B_X0E - this field configures the point 14 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point - 3 - 3 - read-write - - - GAMMA_B_X0D - this field configures the point 13 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point - 6 - 3 - read-write - - - GAMMA_B_X0C - this field configures the point 12 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point - 9 - 3 - read-write - - - GAMMA_B_X0B - this field configures the point 11 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point - 12 - 3 - read-write - - - GAMMA_B_X0A - this field configures the point 10 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point - 15 - 3 - read-write - - - GAMMA_B_X09 - this field configures the point 9 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point - 18 - 3 - read-write - - - GAMMA_B_X08 - this field configures the point 8 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point - 21 - 3 - read-write - - - - - AE_CTRL - ae control register - 0xC0 - 0x20 - - - AE_UPDATE - write 1 to this bit triggers one statistic event - 0 - 1 - write-only - - - AE_SELECT - this field configures ae input data source, 0: data from median, 1: data from gama - 1 - 1 - read-write - - - - - AE_MONITOR - ae monitor control register - 0xC4 - 0x20 - - - TL - this field configures the lower lum threshold of ae monitor - 0 - 8 - read-write - - - TH - this field configures the higher lum threshold of ae monitor - 8 - 8 - read-write - - - PERIOD - this field cnfigures ae monitor frame period - 16 - 6 - read-write - - - - - AE_BX - ae window register in x-direction - 0xC8 - 0x20 - 0x00000180 - - - AE_X_BSIZE - this field configures every block x size - 0 - 11 - read-write - - - AE_X_START - this field configures first block start x address - 11 - 11 - read-write - - - - - AE_BY - ae window register in y-direction - 0xCC - 0x20 - 0x000000D8 - - - AE_Y_BSIZE - this field configures every block y size - 0 - 11 - read-write - - - AE_Y_START - this field configures first block start y address - 11 - 11 - read-write - - - - - AE_WINPIXNUM - ae sub-window pix num register - 0xD0 - 0x20 - 0x00014400 - - - AE_SUBWIN_PIXNUM - this field configures the pixel number of each sub win - 0 - 17 - read-write - - - - - AE_WIN_RECIPROCAL - reciprocal of ae sub-window pixel number - 0xD4 - 0x20 - - - AE_SUBWIN_RECIP - this field configures the reciprocal of each subwin_pixnum, 20bit fraction - 0 - 20 - read-write - - - - - AE_BLOCK_MEAN_0 - ae statistic result register 0 - 0xD8 - 0x20 - - - AE_B03_MEAN - this field configures block03 Y mean data - 0 - 8 - read-only - - - AE_B02_MEAN - this field configures block02 Y mean data - 8 - 8 - read-only - - - AE_B01_MEAN - this field configures block01 Y mean data - 16 - 8 - read-only - - - AE_B00_MEAN - this field configures block00 Y mean data - 24 - 8 - read-only - - - - - AE_BLOCK_MEAN_1 - ae statistic result register 1 - 0xDC - 0x20 - - - AE_B12_MEAN - this field configures block12 Y mean data - 0 - 8 - read-only - - - AE_B11_MEAN - this field configures block11 Y mean data - 8 - 8 - read-only - - - AE_B10_MEAN - this field configures block10 Y mean data - 16 - 8 - read-only - - - AE_B04_MEAN - this field configures block04 Y mean data - 24 - 8 - read-only - - - - - AE_BLOCK_MEAN_2 - ae statistic result register 2 - 0xE0 - 0x20 - - - AE_B21_MEAN - this field configures block21 Y mean data - 0 - 8 - read-only - - - AE_B20_MEAN - this field configures block20 Y mean data - 8 - 8 - read-only - - - AE_B14_MEAN - this field configures block14 Y mean data - 16 - 8 - read-only - - - AE_B13_MEAN - this field configures block13 Y mean data - 24 - 8 - read-only - - - - - AE_BLOCK_MEAN_3 - ae statistic result register 3 - 0xE4 - 0x20 - - - AE_B30_MEAN - this field configures block30 Y mean data - 0 - 8 - read-only - - - AE_B24_MEAN - this field configures block24 Y mean data - 8 - 8 - read-only - - - AE_B23_MEAN - this field configures block23 Y mean data - 16 - 8 - read-only - - - AE_B22_MEAN - this field configures block22 Y mean data - 24 - 8 - read-only - - - - - AE_BLOCK_MEAN_4 - ae statistic result register 4 - 0xE8 - 0x20 - - - AE_B34_MEAN - this field configures block34 Y mean data - 0 - 8 - read-only - - - AE_B33_MEAN - this field configures block33 Y mean data - 8 - 8 - read-only - - - AE_B32_MEAN - this field configures block32 Y mean data - 16 - 8 - read-only - - - AE_B31_MEAN - this field configures block31 Y mean data - 24 - 8 - read-only - - - - - AE_BLOCK_MEAN_5 - ae statistic result register 5 - 0xEC - 0x20 - - - AE_B43_MEAN - this field configures block43 Y mean data - 0 - 8 - read-only - - - AE_B42_MEAN - this field configures block42 Y mean data - 8 - 8 - read-only - - - AE_B41_MEAN - this field configures block41 Y mean data - 16 - 8 - read-only - - - AE_B40_MEAN - this field configures block40 Y mean data - 24 - 8 - read-only - - - - - AE_BLOCK_MEAN_6 - ae statistic result register 6 - 0xF0 - 0x20 - - - AE_B44_MEAN - this field configures block44 Y mean data - 24 - 8 - read-only - - - - - SHARP_CTRL0 - sharp control register 0 - 0xF4 - 0x20 - - - SHARP_THRESHOLD_LOW - this field configures sharpen threshold for detail - 0 - 8 - read-write - - - SHARP_THRESHOLD_HIGH - this field configures sharpen threshold for edge - 8 - 8 - read-write - - - SHARP_AMOUNT_LOW - this field configures sharpen amount for detail - 16 - 8 - read-write - - - SHARP_AMOUNT_HIGH - this field configures sharpen amount for edge - 24 - 8 - read-write - - - - - SHARP_FILTER0 - sharp usm config register 0 - 0xF8 - 0x20 - 0x00000441 - - - SHARP_FILTER_COE00 - this field configures unsharp masking(usm) filter coefficient - 0 - 5 - read-write - - - SHARP_FILTER_COE01 - this field configures usm filter coefficient - 5 - 5 - read-write - - - SHARP_FILTER_COE02 - this field configures usm filter coefficient - 10 - 5 - read-write - - - - - SHARP_FILTER1 - sharp usm config register 1 - 0xFC - 0x20 - 0x00000882 - - - SHARP_FILTER_COE10 - this field configures usm filter coefficient - 0 - 5 - read-write - - - SHARP_FILTER_COE11 - this field configures usm filter coefficient - 5 - 5 - read-write - - - SHARP_FILTER_COE12 - this field configures usm filter coefficient - 10 - 5 - read-write - - - - - SHARP_FILTER2 - sharp usm config register 2 - 0x100 - 0x20 - 0x00000441 - - - SHARP_FILTER_COE20 - this field configures usm filter coefficient - 0 - 5 - read-write - - - SHARP_FILTER_COE21 - this field configures usm filter coefficient - 5 - 5 - read-write - - - SHARP_FILTER_COE22 - this field configures usm filter coefficient - 10 - 5 - read-write - - - - - SHARP_MATRIX_CTRL - sharp pix2matrix ctrl - 0x104 - 0x20 - - - SHARP_TAIL_PIXEN_PULSE_TL - matrix tail pixen low level threshold, should not to large to prevent expanding to next frame, only reg_demosaic_tail_pixen_pulse_th!=0 and reg_demosaic_tail_pixen_pulse_tl!=0 and reg_demosaic_tail_pixen_pulse_th < reg_demosaic_tail_pixen_pulse_tl will enable tail pulse function - 0 - 8 - read-write - - - SHARP_TAIL_PIXEN_PULSE_TH - matrix tail pixen high level threshold, must < hnum-1, only reg_sharp_tail_pixen_pulse_th!=0 and reg_sharp_tail_pixen_pulse_tl!=0 and reg_sharp_tail_pixen_pulse_th < reg_sharp_tail_pixen_pulse_tl will enable tail pulse function - 8 - 8 - read-write - - - SHARP_PADDING_DATA - this field configures sharp padding data - 16 - 8 - read-write - - - SHARP_PADDING_MODE - this field configures sharp padding mode - 24 - 1 - read-write - - - - - SHARP_CTRL1 - sharp control register 1 - 0x108 - 0x20 - - - SHARP_GRADIENT_MAX - this field configures sharp max gradient, refresh at the end of each frame end - 0 - 8 - read-only - - - - - DMA_CNTL - isp dma source trans control register - 0x10C - 0x20 - 0x001080A8 - - - DMA_EN - write 1 to triger dma to get 1 frame - 0 - 1 - write-only - - - DMA_UPDATE - write 1 to update reg_dma_burst_len & reg_dma_data_type - 1 - 1 - read-write - - - DMA_DATA_TYPE - this field configures the idi data type for image data - 2 - 6 - read-write - - - DMA_BURST_LEN - this field configures dma burst len when data source is dma. set according to dma_msize, it is the number of 64bits in a dma transfer - 8 - 12 - read-write - - - DMA_INTERVAL - this field configures dma req interval, 12'b1: 1 cycle, 12'b11 2 cycle ... - 20 - 12 - read-write - - - - - DMA_RAW_DATA - isp dma source total raw number set register - 0x110 - 0x20 - - - DMA_RAW_NUM_TOTAL - this field configures the the number of 64bits in a frame - 0 - 22 - read-write - - - DMA_RAW_NUM_TOTAL_SET - write 1 to update reg_dma_raw_num_total - 31 - 1 - write-only - - - - - CAM_CNTL - isp cam source control register - 0x114 - 0x20 - 0x00000004 - - - CAM_EN - write 1 to start recive camera data, write 0 to disable - 0 - 1 - read-write - - - CAM_UPDATE - write 1 to update ISP_CAM_CONF - 1 - 1 - read-write - - - CAM_RESET - this bit configures cam clk domain reset, 1: reset cam input logic, 0: release reset - 2 - 1 - read-write - - - CAM_CLK_INV - this bit configures the invertion of cam clk from pad. 0: not invert cam clk, 1: invert cam clk - 3 - 1 - read-write - - - - - CAM_CONF - isp cam source config register - 0x118 - 0x20 - 0x000000A8 - - - CAM_DATA_ORDER - this field configures data order of cam port, 0: cam_data_in, 1:{cam_data_in[7:0], cam_data_in[15:8]} - 0 - 1 - read-write - - - CAM_2BYTE_MODE - this field configures enable of cam 2 byte mode(input 2 bytes each clock). 0: disable, 1: enable - 1 - 1 - read-write - - - CAM_DATA_TYPE - this field configures idi data type for image data, 0x2a: RAW8, 0x2b: RAW10, 0x2c: RAW12 - 2 - 6 - read-write - - - CAM_DE_INV - this bit configures cam data enable invert. 0: not invert, 1: invert - 8 - 1 - read-write - - - CAM_HSYNC_INV - this bit configures cam hsync invert. 0: not invert, 1: invert - 9 - 1 - read-write - - - CAM_VSYNC_INV - this bit configures cam vsync invert. 0: not invert, 1: invert - 10 - 1 - read-write - - - CAM_VSYNC_FILTER_THRES - this bit configures the number of clock of vsync filter length - 11 - 3 - read-write - - - CAM_VSYNC_FILTER_EN - this bit configures vsync filter en - 14 - 1 - read-write - - - - - AF_CTRL0 - af control register 0 - 0x11C - 0x20 - - - AF_AUTO_UPDATE - this bit configures auto_update enable. when set to 1, will update sum and lum each frame - 0 - 1 - read-write - - - AF_MANUAL_UPDATE - write 1 to this bit will update the sum and lum once - 4 - 1 - write-only - - - AF_ENV_THRESHOLD - this field configures env threshold. when both sum and lum changes larger than this value, consider environment changes and need to trigger a new autofocus. 4Bit fractional - 8 - 4 - read-write - - - AF_ENV_PERIOD - this field configures environment changes detection period (frame). When set to 0, disable this function - 16 - 8 - read-write - - - - - AF_CTRL1 - af control register 1 - 0x120 - 0x20 - - - AF_THPIXNUM - this field configures pixnum used when calculating the autofocus threshold. Set to 0 to disable threshold calculation - 0 - 22 - read-write - - - - - AF_GEN_TH_CTRL - af gen threshold control register - 0x124 - 0x20 - 0x04400080 - - - AF_GEN_THRESHOLD_MIN - this field configures min threshold when use auto_threshold - 0 - 16 - read-write - - - AF_GEN_THRESHOLD_MAX - this field configures max threshold when use auto_threshold - 16 - 16 - read-write - - - - - AF_ENV_USER_TH_SUM - af monitor user sum threshold register - 0x128 - 0x20 - - - AF_ENV_USER_THRESHOLD_SUM - this field configures user setup env detect sum threshold - 0 - 32 - read-write - - - - - AF_ENV_USER_TH_LUM - af monitor user lum threshold register - 0x12C - 0x20 - - - AF_ENV_USER_THRESHOLD_LUM - this field configures user setup env detect lum threshold - 0 - 30 - read-write - - - - - AF_THRESHOLD - af threshold register - 0x130 - 0x20 - 0x00000100 - - - AF_THRESHOLD - this field configures user threshold. When set to non-zero, autofocus will use this threshold - 0 - 16 - read-write - - - AF_GEN_THRESHOLD - this field represents the last calculated threshold - 16 - 16 - read-only - - - - - AF_HSCALE_A - h-scale of af window a register - 0x134 - 0x20 - 0x00010080 - - - AF_RPOINT_A - this field configures left coordinate of focus window a, must >= 2 - 0 - 12 - read-write - - - AF_LPOINT_A - this field configures top coordinate of focus window a, must >= 2 - 16 - 12 - read-write - - - - - AF_VSCALE_A - v-scale of af window a register - 0x138 - 0x20 - 0x00010080 - - - AF_BPOINT_A - this field configures right coordinate of focus window a, must <= hnum-2 - 0 - 12 - read-write - - - AF_TPOINT_A - this field configures bottom coordinate of focus window a, must <= hnum-2 - 16 - 12 - read-write - - - - - AF_HSCALE_B - h-scale of af window b register - 0x13C - 0x20 - 0x00010080 - - - AF_RPOINT_B - this field configures left coordinate of focus window b, must >= 2 - 0 - 12 - read-write - - - AF_LPOINT_B - this field configures top coordinate of focus window b, must >= 2 - 16 - 12 - read-write - - - - - AF_VSCALE_B - v-scale of af window b register - 0x140 - 0x20 - 0x00010080 - - - AF_BPOINT_B - this field configures right coordinate of focus window b, must <= hnum-2 - 0 - 12 - read-write - - - AF_TPOINT_B - this field configures bottom coordinate of focus window b, must <= hnum-2 - 16 - 12 - read-write - - - - - AF_HSCALE_C - v-scale of af window c register - 0x144 - 0x20 - 0x00010080 - - - AF_RPOINT_C - this field configures left coordinate of focus window c, must >= 2 - 0 - 12 - read-write - - - AF_LPOINT_C - this field configures top coordinate of focus window c, must >= 2 - 16 - 12 - read-write - - - - - AF_VSCALE_C - v-scale of af window c register - 0x148 - 0x20 - 0x00010080 - - - AF_BPOINT_C - this field configures right coordinate of focus window c, must <= hnum-2 - 0 - 12 - read-write - - - AF_TPOINT_C - this field configures bottom coordinate of focus window c, must <= hnum-2 - 16 - 12 - read-write - - - - - AF_SUM_A - result of sum of af window a - 0x14C - 0x20 - - - AF_SUMA - this field represents the result of accumulation of pix grad of focus window a - 0 - 30 - read-only - - - - - AF_SUM_B - result of sum of af window b - 0x150 - 0x20 - - - AF_SUMB - this field represents the result of accumulation of pix grad of focus window b - 0 - 30 - read-only - - - - - AF_SUM_C - result of sum of af window c - 0x154 - 0x20 - - - AF_SUMC - this field represents the result of accumulation of pix grad of focus window c - 0 - 30 - read-only - - - - - AF_LUM_A - result of lum of af window a - 0x158 - 0x20 - - - AF_LUMA - this field represents the result of accumulation of pix light of focus window a - 0 - 28 - read-only - - - - - AF_LUM_B - result of lum of af window b - 0x15C - 0x20 - - - AF_LUMB - this field represents the result of accumulation of pix light of focus window b - 0 - 28 - read-only - - - - - AF_LUM_C - result of lum of af window c - 0x160 - 0x20 - - - AF_LUMC - this field represents the result of accumulation of pix light of focus window c - 0 - 28 - read-only - - - - - AWB_MODE - awb mode control register - 0x164 - 0x20 - 0x00000003 - - - AWB_MODE - this field configures awb algo sel. 00: none sellected. 01: sel algo0. 10: sel algo1. 11: sel both algo0 and algo1 - 0 - 2 - read-write - - - AWB_SAMPLE - this bit configures awb sample location, 0:before ccm, 1:after ccm - 4 - 1 - read-write - - - - - AWB_HSCALE - h-scale of awb window - 0x168 - 0x20 - 0x0000077F - - - AWB_RPOINT - this field configures awb window right coordinate - 0 - 12 - read-write - - - AWB_LPOINT - this field configures awb window left coordinate - 16 - 12 - read-write - - - - - AWB_VSCALE - v-scale of awb window - 0x16C - 0x20 - 0x00000437 - - - AWB_BPOINT - this field configures awb window bottom coordinate - 0 - 12 - read-write - - - AWB_TPOINT - this field configures awb window top coordinate - 16 - 12 - read-write - - - - - AWB_TH_LUM - awb lum threshold register - 0x170 - 0x20 - 0x02FD0000 - - - AWB_MIN_LUM - this field configures lower threshold of r+g+b - 0 - 10 - read-write - - - AWB_MAX_LUM - this field configures upper threshold of r+g+b - 16 - 10 - read-write - - - - - AWB_TH_RG - awb r/g threshold register - 0x174 - 0x20 - 0x03FF0000 - - - AWB_MIN_RG - this field configures lower threshold of r/g, 2bit integer and 8bit fraction - 0 - 10 - read-write - - - AWB_MAX_RG - this field configures upper threshold of r/g, 2bit integer and 8bit fraction - 16 - 10 - read-write - - - - - AWB_TH_BG - awb b/g threshold register - 0x178 - 0x20 - 0x03FF0000 - - - AWB_MIN_BG - this field configures lower threshold of b/g, 2bit integer and 8bit fraction - 0 - 10 - read-write - - - AWB_MAX_BG - this field configures upper threshold of b/g, 2bit integer and 8bit fraction - 16 - 10 - read-write - - - - - AWB0_WHITE_CNT - result of awb white point number - 0x17C - 0x20 - - - AWB0_WHITE_CNT - this field configures number of white point detected of algo0 - 0 - 24 - read-only - - - - - AWB0_ACC_R - result of accumulate of r channel of all white points - 0x180 - 0x20 - - - AWB0_ACC_R - this field represents accumulate of channel r of all white point of algo0 - 0 - 32 - read-only - - - - - AWB0_ACC_G - result of accumulate of g channel of all white points - 0x184 - 0x20 - - - AWB0_ACC_G - this field represents accumulate of channel g of all white point of algo0 - 0 - 32 - read-only - - - - - AWB0_ACC_B - result of accumulate of b channel of all white points - 0x188 - 0x20 - - - AWB0_ACC_B - this field represents accumulate of channel b of all white point of algo0 - 0 - 32 - read-only - - - - - COLOR_CTRL - color control register - 0x18C - 0x20 - 0x00800080 - - - COLOR_SATURATION - this field configures the color saturation value - 0 - 8 - read-write - - - COLOR_HUE - this field configures the color hue angle - 8 - 8 - read-write - - - COLOR_CONTRAST - this field configures the color contrast value - 16 - 8 - read-write - - - COLOR_BRIGHTNESS - this field configures the color brightness value, signed 2's complement - 24 - 8 - read-write - - - - - BLC_VALUE - blc black level register - 0x190 - 0x20 - - - BLC_R3_VALUE - this field configures the black level of bottom right channel of bayer img - 0 - 8 - read-write - - - BLC_R2_VALUE - this field configures the black level of bottom left channel of bayer img - 8 - 8 - read-write - - - BLC_R1_VALUE - this field configures the black level of top right channel of bayer img - 16 - 8 - read-write - - - BLC_R0_VALUE - this field configures the black level of top left channel of bayer img - 24 - 8 - read-write - - - - - BLC_CTRL0 - blc stretch control register - 0x194 - 0x20 - - - BLC_R3_STRETCH - this bit configures the stretch feature of bottom right channel. 0: stretch disable, 1: stretch enable - 0 - 1 - read-write - - - BLC_R2_STRETCH - this bit configures the stretch feature of bottom left channel. 0: stretch disable, 1: stretch enable - 1 - 1 - read-write - - - BLC_R1_STRETCH - this bit configures the stretch feature of top right channel. 0: stretch disable, 1: stretch enable - 2 - 1 - read-write - - - BLC_R0_STRETCH - this bit configures the stretch feature of top left channel. 0: stretch disable, 1: stretch enable - 3 - 1 - read-write - - - - - BLC_CTRL1 - blc window control register - 0x198 - 0x20 - - - BLC_WINDOW_TOP - this field configures blc average calculation window top - 0 - 11 - read-write - - - BLC_WINDOW_LEFT - this field configures blc average calculation window left - 11 - 11 - read-write - - - BLC_WINDOW_VNUM - this field configures blc average calculation window vnum - 22 - 4 - read-write - - - BLC_WINDOW_HNUM - this field configures blc average calculation window hnum - 26 - 4 - read-write - - - BLC_FILTER_EN - this bit configures enable blc average input filter. 0: disable, 1: enable - 30 - 1 - read-write - - - - - BLC_CTRL2 - blc black threshold control register - 0x19C - 0x20 - - - BLC_R3_TH - this field configures black threshold when get blc average of bottom right channel - 0 - 8 - read-write - - - BLC_R2_TH - this field configures black threshold when get blc average of bottom left channel - 8 - 8 - read-write - - - BLC_R1_TH - this field configures black threshold when get blc average of top right channel - 16 - 8 - read-write - - - BLC_R0_TH - this field configures black threshold when get blc average of top left channel - 24 - 8 - read-write - - - - - BLC_MEAN - results of the average of black window - 0x1A0 - 0x20 - - - BLC_R3_MEAN - this field represents the average black value of bottom right channel - 0 - 8 - read-only - - - BLC_R2_MEAN - this field represents the average black value of bottom left channel - 8 - 8 - read-only - - - BLC_R1_MEAN - this field represents the average black value of top right channel - 16 - 8 - read-only - - - BLC_R0_MEAN - this field represents the average black value of top left channel - 24 - 8 - read-only - - - - - HIST_MODE - histogram mode control register - 0x1A4 - 0x20 - 0x00000004 - - - HIST_MODE - this field configures statistic mode. 0: RAW_B, 1: RAW_GB, 2: RAW_GR 3: RAW_R, 4: RGB, 5:YUV_Y, 6:YUV_U, 7:YUV_V - 0 - 3 - read-write - - - - - HIST_COEFF - histogram rgb to gray coefficients register - 0x1A8 - 0x20 - 0x00555555 - - - B - this field configures coefficient of B when set hist_mode to RGB, sum of coeff_r and coeff_g and coeff_b should be 256 - 0 - 8 - read-write - - - G - this field configures coefficient of G when set hist_mode to RGB, sum of coeff_r and coeff_g and coeff_b should be 256 - 8 - 8 - read-write - - - R - this field configures coefficient of R when set hist_mode to RGB, sum of coeff_r and coeff_g and coeff_b should be 256 - 16 - 8 - read-write - - - - - HIST_OFFS - histogram window offsets register - 0x1AC - 0x20 - - - HIST_Y_OFFS - this field configures y coordinate of first window - 0 - 12 - read-write - - - HIST_X_OFFS - this field configures x coordinate of first window - 16 - 12 - read-write - - - - - HIST_SIZE - histogram sub-window size register - 0x1B0 - 0x20 - 0x00120020 - - - HIST_Y_SIZE - this field configures y direction size of subwindow - 0 - 9 - read-write - - - HIST_X_SIZE - this field configures x direction size of subwindow - 16 - 9 - read-write - - - - - HIST_SEG0 - histogram bin control register 0 - 0x1B4 - 0x20 - 0x10203040 - - - HIST_SEG_3_4 - this field configures threshold of histogram bin 3 and bin 4 - 0 - 8 - read-write - - - HIST_SEG_2_3 - this field configures threshold of histogram bin 2 and bin 3 - 8 - 8 - read-write - - - HIST_SEG_1_2 - this field configures threshold of histogram bin 1 and bin 2 - 16 - 8 - read-write - - - HIST_SEG_0_1 - this field configures threshold of histogram bin 0 and bin 1 - 24 - 8 - read-write - - - - - HIST_SEG1 - histogram bin control register 1 - 0x1B8 - 0x20 - 0x50607080 - - - HIST_SEG_7_8 - this field configures threshold of histogram bin 7 and bin 8 - 0 - 8 - read-write - - - HIST_SEG_6_7 - this field configures threshold of histogram bin 6 and bin 7 - 8 - 8 - read-write - - - HIST_SEG_5_6 - this field configures threshold of histogram bin 5 and bin 6 - 16 - 8 - read-write - - - HIST_SEG_4_5 - this field configures threshold of histogram bin 4 and bin 5 - 24 - 8 - read-write - - - - - HIST_SEG2 - histogram bin control register 2 - 0x1BC - 0x20 - 0x90A0B0C0 - - - HIST_SEG_11_12 - this field configures threshold of histogram bin 11 and bin 12 - 0 - 8 - read-write - - - HIST_SEG_10_11 - this field configures threshold of histogram bin 10 and bin 11 - 8 - 8 - read-write - - - HIST_SEG_9_10 - this field configures threshold of histogram bin 9 and bin 10 - 16 - 8 - read-write - - - HIST_SEG_8_9 - this field configures threshold of histogram bin 8 and bin 9 - 24 - 8 - read-write - - - - - HIST_SEG3 - histogram bin control register 3 - 0x1C0 - 0x20 - 0x00D0E0F0 - - - HIST_SEG_14_15 - this field configures threshold of histogram bin 14 and bin 15 - 0 - 8 - read-write - - - HIST_SEG_13_14 - this field configures threshold of histogram bin 13 and bin 14 - 8 - 8 - read-write - - - HIST_SEG_12_13 - this field configures threshold of histogram bin 12 and bin 13 - 16 - 8 - read-write - - - - - HIST_WEIGHT0 - histogram sub-window weight register 0 - 0x1C4 - 0x20 - 0x01010101 - - - HIST_WEIGHT_03 - this field configures weight of subwindow 03 - 0 - 8 - read-write - - - HIST_WEIGHT_02 - this field configures weight of subwindow 02 - 8 - 8 - read-write - - - HIST_WEIGHT_01 - this field configures weight of subwindow 01 - 16 - 8 - read-write - - - HIST_WEIGHT_00 - this field configures weight of subwindow 00 and sum of all weight should be 256 - 24 - 8 - read-write - - - - - HIST_WEIGHT1 - histogram sub-window weight register 1 - 0x1C8 - 0x20 - 0x01010101 - - - HIST_WEIGHT_12 - this field configures weight of subwindow 12 - 0 - 8 - read-write - - - HIST_WEIGHT_11 - this field configures weight of subwindow 11 - 8 - 8 - read-write - - - HIST_WEIGHT_10 - this field configures weight of subwindow 10 - 16 - 8 - read-write - - - HIST_WEIGHT_04 - this field configures weight of subwindow 04 - 24 - 8 - read-write - - - - - HIST_WEIGHT2 - histogram sub-window weight register 2 - 0x1CC - 0x20 - 0x01010101 - - - HIST_WEIGHT_21 - this field configures weight of subwindow 21 - 0 - 8 - read-write - - - HIST_WEIGHT_20 - this field configures weight of subwindow 20 - 8 - 8 - read-write - - - HIST_WEIGHT_14 - this field configures weight of subwindow 04 - 16 - 8 - read-write - - - HIST_WEIGHT_13 - this field configures weight of subwindow 13 - 24 - 8 - read-write - - - - - HIST_WEIGHT3 - histogram sub-window weight register 3 - 0x1D0 - 0x20 - 0xE8010101 - - - HIST_WEIGHT_30 - this field configures weight of subwindow 30 - 0 - 8 - read-write - - - HIST_WEIGHT_24 - this field configures weight of subwindow 24 - 8 - 8 - read-write - - - HIST_WEIGHT_23 - this field configures weight of subwindow 23 - 16 - 8 - read-write - - - HIST_WEIGHT_22 - this field configures weight of subwindow 22 - 24 - 8 - read-write - - - - - HIST_WEIGHT4 - histogram sub-window weight register 4 - 0x1D4 - 0x20 - 0x01010101 - - - HIST_WEIGHT_34 - this field configures weight of subwindow 34 - 0 - 8 - read-write - - - HIST_WEIGHT_33 - this field configures weight of subwindow 33 - 8 - 8 - read-write - - - HIST_WEIGHT_32 - this field configures weight of subwindow 32 - 16 - 8 - read-write - - - HIST_WEIGHT_31 - this field configures weight of subwindow 31 - 24 - 8 - read-write - - - - - HIST_WEIGHT5 - histogram sub-window weight register 5 - 0x1D8 - 0x20 - 0x01010101 - - - HIST_WEIGHT_43 - this field configures weight of subwindow 43 - 0 - 8 - read-write - - - HIST_WEIGHT_42 - this field configures weight of subwindow 42 - 8 - 8 - read-write - - - HIST_WEIGHT_41 - this field configures weight of subwindow 41 - 16 - 8 - read-write - - - HIST_WEIGHT_40 - this field configures weight of subwindow 40 - 24 - 8 - read-write - - - - - HIST_WEIGHT6 - histogram sub-window weight register 6 - 0x1DC - 0x20 - 0x00000001 - - - HIST_WEIGHT_44 - this field configures weight of subwindow 44 - 0 - 8 - read-write - - - - - HIST_BIN0 - result of histogram bin 0 - 0x1E0 - 0x20 - - - HIST_BIN_0 - this field represents result of histogram bin 0 - 0 - 17 - read-only - - - - - HIST_BIN1 - result of histogram bin 1 - 0x1E4 - 0x20 - - - HIST_BIN_1 - this field represents result of histogram bin 1 - 0 - 17 - read-only - - - - - HIST_BIN2 - result of histogram bin 2 - 0x1E8 - 0x20 - - - HIST_BIN_2 - this field represents result of histogram bin 2 - 0 - 17 - read-only - - - - - HIST_BIN3 - result of histogram bin 3 - 0x1EC - 0x20 - - - HIST_BIN_3 - this field represents result of histogram bin 3 - 0 - 17 - read-only - - - - - HIST_BIN4 - result of histogram bin 4 - 0x1F0 - 0x20 - - - HIST_BIN_4 - this field represents result of histogram bin 4 - 0 - 17 - read-only - - - - - HIST_BIN5 - result of histogram bin 5 - 0x1F4 - 0x20 - - - HIST_BIN_5 - this field represents result of histogram bin 5 - 0 - 17 - read-only - - - - - HIST_BIN6 - result of histogram bin 6 - 0x1F8 - 0x20 - - - HIST_BIN_6 - this field represents result of histogram bin 6 - 0 - 17 - read-only - - - - - HIST_BIN7 - result of histogram bin 7 - 0x1FC - 0x20 - - - HIST_BIN_7 - this field represents result of histogram bin 7 - 0 - 17 - read-only - - - - - HIST_BIN8 - result of histogram bin 8 - 0x200 - 0x20 - - - HIST_BIN_8 - this field represents result of histogram bin 8 - 0 - 17 - read-only - - - - - HIST_BIN9 - result of histogram bin 9 - 0x204 - 0x20 - - - HIST_BIN_9 - this field represents result of histogram bin 9 - 0 - 17 - read-only - - - - - HIST_BIN10 - result of histogram bin 10 - 0x208 - 0x20 - - - HIST_BIN_10 - this field represents result of histogram bin 10 - 0 - 17 - read-only - - - - - HIST_BIN11 - result of histogram bin 11 - 0x20C - 0x20 - - - HIST_BIN_11 - this field represents result of histogram bin 11 - 0 - 17 - read-only - - - - - HIST_BIN12 - result of histogram bin 12 - 0x210 - 0x20 - - - HIST_BIN_12 - this field represents result of histogram bin 12 - 0 - 17 - read-only - - - - - HIST_BIN13 - result of histogram bin 13 - 0x214 - 0x20 - - - HIST_BIN_13 - this field represents result of histogram bin 13 - 0 - 17 - read-only - - - - - HIST_BIN14 - result of histogram bin 14 - 0x218 - 0x20 - - - HIST_BIN_14 - this field represents result of histogram bin 14 - 0 - 17 - read-only - - - - - HIST_BIN15 - result of histogram bin 15 - 0x21C - 0x20 - - - HIST_BIN_15 - this field represents result of histogram bin 15 - 0 - 17 - read-only - - - - - MEM_AUX_CTRL_0 - mem aux control register 0 - 0x220 - 0x20 - 0x13201320 - - - HEADER_MEM_AUX_CTRL - this field configures the mem_aux of isp input buffer memory - 0 - 14 - read-write - - - DPC_LUT_MEM_AUX_CTRL - this field represents this field configures the mem_aux of dpc lut memory - 16 - 14 - read-write - - - - - MEM_AUX_CTRL_1 - mem aux control register 1 - 0x224 - 0x20 - 0x13201320 - - - LSC_LUT_R_GR_MEM_AUX_CTRL - this field configures the mem_aux of lsc r gr lut memory - 0 - 14 - read-write - - - LSC_LUT_GB_B_MEM_AUX_CTRL - this field configures the mem_aux of lsc gb b lut memory - 16 - 14 - read-write - - - - - MEM_AUX_CTRL_2 - mem aux control register 2 - 0x228 - 0x20 - 0x13201320 - - - BF_MATRIX_MEM_AUX_CTRL - this field configures the mem_aux of bf line buffer memory - 0 - 14 - read-write - - - DPC_MATRIX_MEM_AUX_CTRL - this field configures the mem_aux of dpc line buffer memory - 16 - 14 - read-write - - - - - MEM_AUX_CTRL_3 - mem aux control register 3 - 0x22C - 0x20 - 0x13201320 - - - SHARP_MATRIX_Y_MEM_AUX_CTRL - this field configures the mem_aux of sharp y line buffer memory - 0 - 14 - read-write - - - DEMOSAIC_MATRIX_MEM_AUX_CTRL - this field configures the mem_aux of demosaic line buffer memory - 16 - 14 - read-write - - - - - MEM_AUX_CTRL_4 - mem aux control register 4 - 0x230 - 0x20 - 0x00001320 - - - SHARP_MATRIX_UV_MEM_AUX_CTRL - this field configures the mem_aux of sharp uv line buffer memory - 0 - 14 - read-write - - - - - YUV_FORMAT - yuv format control register - 0x234 - 0x20 - - - YUV_MODE - this bit configures the yuv mode. 0: ITU-R BT.601, 1: ITU-R BT.709 - 0 - 1 - read-write - - - YUV_RANGE - this bit configures the yuv range. 0: full range, 1: limit range - 1 - 1 - read-write - - - - - RDN_ECO_CS - rdn eco cs register - 0x238 - 0x20 - - - RDN_ECO_EN - rdn_eco_en - 0 - 1 - read-write - - - RDN_ECO_RESULT - rdn_eco_result - 1 - 1 - read-only - - - - - RDN_ECO_LOW - rdn eco all low register - 0x23C - 0x20 - - - RDN_ECO_LOW - rdn_eco_low - 0 - 32 - read-write - - - - - RDN_ECO_HIGH - rdn eco all high register - 0x240 - 0x20 - 0xFFFFFFFF - - - RDN_ECO_HIGH - rdn_eco_high - 0 - 32 - read-write - - - - - - - JPEG - JPEG Codec - JPEG - 0x50086000 - - 0x0 - 0xB0 - registers - - - JPEG - 95 - - - - CONFIG - Control and configuration registers - 0x0 - 0x20 - 0x00408958 - - - FSM_RST - fsm reset - 0 - 1 - write-only - - - JPEG_START - start to compress a new pic(in dma reg mode) - 1 - 1 - write-only - - - QNR_PRESITION - 0:8bit qnr,1:12bit qnr(TBD) - 2 - 1 - read-write - - - FF_CHECK_EN - enable whether to add "00" after "ff" - 3 - 1 - read-write - - - SAMPLE_SEL - 0:yuv444,1:yuv422, 2:yuv420 - 4 - 2 - read-write - - - DMA_LINKLIST_MODE - 1:use linklist to configure dma - 6 - 1 - read-only - - - DEBUG_DIRECT_OUT_EN - 0:normal mode,1:debug mode for direct output from input - 7 - 1 - read-write - - - GRAY_SEL - 0:use non-fifo way to access qnr ram,1:use fifo way to access qnr ram - 8 - 1 - read-write - - - LQNR_TBL_SEL - choose luminance quntization table id(TBD) - 9 - 2 - read-write - - - CQNR_TBL_SEL - choose chrominance quntization table id (TBD) - 11 - 2 - read-write - - - COLOR_SPACE - configure picture's color space:0-rb888,1-yuv422,2-rgb565, 3-gray - 13 - 2 - read-write - - - DHT_FIFO_EN - 0:use non-fifo way to write dht len_total/codemin/value table,1:use fifo way to write dht len_total/codemin/value table. Reading dht len_total/codemin/value table only has nonfifo way - 15 - 1 - read-write - - - MEM_CLK_FORCE_ON - force memory's clock enabled - 16 - 1 - read-write - - - JFIF_VER - decode pause period to trigger decode_timeout int, the timeout periods =2 power (reg_decode_timeout_thres) -1 - 17 - 6 - read-write - - - DECODE_TIMEOUT_TASK_SEL - 0: software use reset to abort decode process ,1: decoder abort decode process by itself - 23 - 1 - read-write - - - SOFT_RST - when set to 1, soft reset JPEG module except jpeg_reg module - 24 - 1 - read-write - - - FIFO_RST - fifo reset - 25 - 1 - read-write - - - PIXEL_REV - reverse the source color pixel - 26 - 1 - read-write - - - TAILER_EN - set this bit to add EOI of "0xffd9" at the end of bitstream - 27 - 1 - read-write - - - PAUSE_EN - set this bit to pause jpeg encoding - 28 - 1 - read-write - - - MEM_FORCE_PD - 0: no operation,1:force jpeg memory to power down - 29 - 1 - read-write - - - MEM_FORCE_PU - 0: no operation,1:force jpeg memory to power up - 30 - 1 - read-write - - - MODE - 0:encoder mode, 1: decoder mode - 31 - 1 - read-write - - - - - DQT_INFO - Control and configuration registers - 0x4 - 0x20 - 0x03020100 - - - T0_DQT_INFO - Configure dqt table0's quantization coefficient precision in bit[7:4], configure dqt table0's table id in bit[3:0] - 0 - 8 - read-write - - - T1_DQT_INFO - Configure dqt table1's quantization coefficient precision in bit[7:4], configure dqt table1's table id in bit[3:0] - 8 - 8 - read-write - - - T2_DQT_INFO - Configure dqt table2's quantization coefficient precision in bit[7:4], configure dqt table2's table id in bit[3:0] - 16 - 8 - read-write - - - T3_DQT_INFO - Configure dqt table3's quantization coefficient precision in bit[7:4], configure dqt table3's table id in bit[3:0] - 24 - 8 - read-write - - - - - PIC_SIZE - Control and configuration registers - 0x8 - 0x20 - 0x028001E0 - - - VA - configure picture's height. when encode, the max configurable bits is 14, when decode, the max configurable bits is 16 - 0 - 16 - read-write - - - HA - configure picture's width. when encode, the max configurable bits is 14, when decode, the max configurable bits is 16 - 16 - 16 - read-write - - - - - T0QNR - Control and configuration registers - 0x10 - 0x20 - - - T0_QNR_VAL - write this reg to configure 64 quantization coefficient in t0 table - 0 - 32 - read-only - - - - - T1QNR - Control and configuration registers - 0x14 - 0x20 - - - CHROMINANCE_QNR_VAL - write this reg to configure 64 quantization coefficient in t1 table - 0 - 32 - read-only - - - - - T2QNR - Control and configuration registers - 0x18 - 0x20 - - - T2_QNR_VAL - write this reg to configure 64 quantization coefficient in t2 table - 0 - 32 - read-only - - - - - T3QNR - Control and configuration registers - 0x1C - 0x20 - - - T3_QNR_VAL - write this reg to configure 64 quantization coefficient in t3 table - 0 - 32 - read-only - - - - - DECODE_CONF - Control and configuration registers - 0x20 - 0x20 - 0x5F030000 - - - RESTART_INTERVAL - configure restart interval in DRI marker when decode - 0 - 16 - read-write - - - COMPONENT_NUM - configure number of components in frame when decode - 16 - 8 - read-write - - - SW_DHT_EN - software decode dht table enable - 24 - 1 - read-only - - - SOS_CHECK_BYTE_NUM - Configure the byte number to check next sos marker in the multi-scan picture after one scan is decoded down. The real check number is reg_sos_check_byte_num+1 - 25 - 2 - read-write - - - RST_CHECK_BYTE_NUM - Configure the byte number to check next rst marker after one rst interval is decoded down. The real check number is reg_rst_check_byte_num+1 - 27 - 2 - read-write - - - MULTI_SCAN_ERR_CHECK - reserved for decoder - 29 - 1 - read-write - - - DEZIGZAG_READY_CTL - reserved for decoder - 30 - 1 - read-write - - - - - C0 - Control and configuration registers - 0x24 - 0x20 - 0x00001100 - - - DQT_TBL_SEL - choose c0 quntization table id (TBD) - 0 - 8 - read-write - - - Y_FACTOR - vertical sampling factor of c0 - 8 - 4 - read-write - - - X_FACTOR - horizontal sampling factor of c0 - 12 - 4 - read-write - - - ID - the identifier of c0 - 16 - 8 - read-write - - - - - C1 - Control and configuration registers - 0x28 - 0x20 - 0x00001100 - - - DQT_TBL_SEL - choose c1 quntization table id (TBD) - 0 - 8 - read-write - - - Y_FACTOR - vertical sampling factor of c1 - 8 - 4 - read-write - - - X_FACTOR - horizontal sampling factor of c1 - 12 - 4 - read-write - - - ID - the identifier of c1 - 16 - 8 - read-write - - - - - C2 - Control and configuration registers - 0x2C - 0x20 - 0x00001100 - - - DQT_TBL_SEL - choose c2 quntization table id (TBD) - 0 - 8 - read-write - - - Y_FACTOR - vertical sampling factor of c2 - 8 - 4 - read-write - - - X_FACTOR - horizontal sampling factor of c2 - 12 - 4 - read-write - - - ID - the identifier of c2 - 16 - 8 - read-write - - - - - C3 - Control and configuration registers - 0x30 - 0x20 - 0x00001100 - - - DQT_TBL_SEL - choose c3 quntization table id (TBD) - 0 - 8 - read-write - - - Y_FACTOR - vertical sampling factor of c3 - 8 - 4 - read-write - - - X_FACTOR - horizontal sampling factor of c3 - 12 - 4 - read-write - - - ID - the identifier of c3 - 16 - 8 - read-write - - - - - DHT_INFO - Control and configuration registers - 0x34 - 0x20 - 0x00001010 - - - DC0_DHT_ID - configure dht dc table 0 id - 0 - 4 - read-write - - - DC1_DHT_ID - configure dht dc table 1 id - 4 - 4 - read-write - - - AC0_DHT_ID - configure dht ac table 0 id - 8 - 4 - read-write - - - AC1_DHT_ID - configure dht ac table 1 id - 12 - 4 - read-write - - - - - INT_RAW - Interrupt raw registers - 0x38 - 0x20 - - - DONE_INT_RAW - This raw interrupt bit turns to high level when JPEG finishes encoding a picture.. - 0 - 1 - read-write - - - RLE_PARALLEL_ERR_INT_RAW - The raw interrupt bit to sign that rle parallel error when decoding. - 1 - 1 - read-write - - - CID_ERR_INT_RAW - The raw interrupt bit to sign that scan id check with component fails when decoding. - 2 - 1 - read-write - - - C_DHT_DC_ID_ERR_INT_RAW - The raw interrupt bit to sign that scan component's dc dht id check with dc dht table's id fails when decoding. - 3 - 1 - read-write - - - C_DHT_AC_ID_ERR_INT_RAW - The raw interrupt bit to sign that scan component's ac dht id check with ac dht table's id fails when decoding. - 4 - 1 - read-write - - - C_DQT_ID_ERR_INT_RAW - The raw interrupt bit to sign that scan component's dqt id check with dqt table's id fails when decoding. - 5 - 1 - read-write - - - RST_UXP_ERR_INT_RAW - The raw interrupt bit to sign that RST header marker is detected but restart interval is 0 when decoding. - 6 - 1 - read-write - - - RST_CHECK_NONE_ERR_INT_RAW - The raw interrupt bit to sign that RST header marker is not detected but restart interval is not 0 when decoding. - 7 - 1 - read-write - - - RST_CHECK_POS_ERR_INT_RAW - The raw interrupt bit to sign that RST header marker position mismatches with restart interval when decoding. - 8 - 1 - read-write - - - OUT_EOF_INT_RAW - The raw interrupt bit turns to high level when the last pixel of one square has been transmitted for Tx channel. - 9 - 1 - read-write - - - SR_COLOR_MODE_ERR_INT_RAW - The raw interrupt bit to sign that the selected source color mode is not supported. - 10 - 1 - read-write - - - DCT_DONE_INT_RAW - The raw interrupt bit to sign that one dct calculation is finished. - 11 - 1 - read-write - - - BS_LAST_BLOCK_EOF_INT_RAW - The raw interrupt bit to sign that the coding process for last block is finished. - 12 - 1 - read-write - - - SCAN_CHECK_NONE_ERR_INT_RAW - The raw interrupt bit to sign that SOS header marker is not detected but there are still components left to be decoded. - 13 - 1 - read-write - - - SCAN_CHECK_POS_ERR_INT_RAW - The raw interrupt bit to sign that SOS header marker position wrong when decoding. - 14 - 1 - read-write - - - UXP_DET_INT_RAW - The raw interrupt bit to sign that unsupported header marker is detected when decoding. - 15 - 1 - read-write - - - EN_FRAME_EOF_ERR_INT_RAW - The raw interrupt bit to sign that received pixel blocks are smaller than expected when encoding. - 16 - 1 - read-write - - - EN_FRAME_EOF_LACK_INT_RAW - The raw interrupt bit to sign that the frame eof sign bit from dma input is missing when encoding. But the number of pixel blocks is enough. - 17 - 1 - read-write - - - DE_FRAME_EOF_ERR_INT_RAW - The raw interrupt bit to sign that decoded blocks are smaller than expected when decoding. - 18 - 1 - read-write - - - DE_FRAME_EOF_LACK_INT_RAW - The raw interrupt bit to sign that the either frame eof from dma input or eoi marker is missing when encoding. But the number of decoded blocks is enough. - 19 - 1 - read-write - - - SOS_UNMATCH_ERR_INT_RAW - The raw interrupt bit to sign that the component number of a scan is 0 or does not match the sos marker's length when decoding. - 20 - 1 - read-write - - - MARKER_ERR_FST_SCAN_INT_RAW - The raw interrupt bit to sign that the first scan has header marker error when decoding. - 21 - 1 - read-write - - - MARKER_ERR_OTHER_SCAN_INT_RAW - The raw interrupt bit to sign that the following scans but not the first scan have header marker error when decoding. - 22 - 1 - read-write - - - UNDET_INT_RAW - The raw interrupt bit to sign that JPEG format is not detected at the eof data of a packet when decoding. - 23 - 1 - read-write - - - DECODE_TIMEOUT_INT_RAW - The raw interrupt bit to sign that decode pause time is longer than the setting decode timeout time when decoding. - 24 - 1 - read-write - - - - - INT_ENA - Interrupt enable registers - 0x3C - 0x20 - - - DONE_INT_ENA - This enable interrupt bit turns to high level when JPEG finishes encoding a picture.. - 0 - 1 - read-write - - - RLE_PARALLEL_ERR_INT_ENA - The enable interrupt bit to sign that rle parallel error when decoding. - 1 - 1 - read-write - - - CID_ERR_INT_ENA - The enable interrupt bit to sign that scan id check with component fails when decoding. - 2 - 1 - read-write - - - C_DHT_DC_ID_ERR_INT_ENA - The enable interrupt bit to sign that scan component's dc dht id check with dc dht table's id fails when decoding. - 3 - 1 - read-write - - - C_DHT_AC_ID_ERR_INT_ENA - The enable interrupt bit to sign that scan component's ac dht id check with ac dht table's id fails when decoding. - 4 - 1 - read-write - - - C_DQT_ID_ERR_INT_ENA - The enable interrupt bit to sign that scan component's dqt id check with dqt table's id fails when decoding. - 5 - 1 - read-write - - - RST_UXP_ERR_INT_ENA - The enable interrupt bit to sign that RST header marker is detected but restart interval is 0 when decoding. - 6 - 1 - read-write - - - RST_CHECK_NONE_ERR_INT_ENA - The enable interrupt bit to sign that RST header marker is not detected but restart interval is not 0 when decoding. - 7 - 1 - read-write - - - RST_CHECK_POS_ERR_INT_ENA - The enable interrupt bit to sign that RST header marker position mismatches with restart interval when decoding. - 8 - 1 - read-write - - - OUT_EOF_INT_ENA - The enable interrupt bit turns to high level when the last pixel of one square has been transmitted for Tx channel. - 9 - 1 - read-write - - - SR_COLOR_MODE_ERR_INT_ENA - The enable interrupt bit to sign that the selected source color mode is not supported. - 10 - 1 - read-write - - - DCT_DONE_INT_ENA - The enable interrupt bit to sign that one dct calculation is finished. - 11 - 1 - read-write - - - BS_LAST_BLOCK_EOF_INT_ENA - The enable interrupt bit to sign that the coding process for last block is finished. - 12 - 1 - read-write - - - SCAN_CHECK_NONE_ERR_INT_ENA - The enable interrupt bit to sign that SOS header marker is not detected but there are still components left to be decoded. - 13 - 1 - read-write - - - SCAN_CHECK_POS_ERR_INT_ENA - The enable interrupt bit to sign that SOS header marker position wrong when decoding. - 14 - 1 - read-write - - - UXP_DET_INT_ENA - The enable interrupt bit to sign that unsupported header marker is detected when decoding. - 15 - 1 - read-write - - - EN_FRAME_EOF_ERR_INT_ENA - The enable interrupt bit to sign that received pixel blocks are smaller than expected when encoding. - 16 - 1 - read-write - - - EN_FRAME_EOF_LACK_INT_ENA - The enable interrupt bit to sign that the frame eof sign bit from dma input is missing when encoding. But the number of pixel blocks is enough. - 17 - 1 - read-write - - - DE_FRAME_EOF_ERR_INT_ENA - The enable interrupt bit to sign that decoded blocks are smaller than expected when decoding. - 18 - 1 - read-write - - - DE_FRAME_EOF_LACK_INT_ENA - The enable interrupt bit to sign that the either frame eof from dma input or eoi marker is missing when encoding. But the number of decoded blocks is enough. - 19 - 1 - read-write - - - SOS_UNMATCH_ERR_INT_ENA - The enable interrupt bit to sign that the component number of a scan is 0 or does not match the sos marker's length when decoding. - 20 - 1 - read-write - - - MARKER_ERR_FST_SCAN_INT_ENA - The enable interrupt bit to sign that the first scan has header marker error when decoding. - 21 - 1 - read-write - - - MARKER_ERR_OTHER_SCAN_INT_ENA - The enable interrupt bit to sign that the following scans but not the first scan have header marker error when decoding. - 22 - 1 - read-write - - - UNDET_INT_ENA - The enable interrupt bit to sign that JPEG format is not detected at the eof data of a packet when decoding. - 23 - 1 - read-write - - - DECODE_TIMEOUT_INT_ENA - The enable interrupt bit to sign that decode pause time is longer than the setting decode timeout time when decoding. - 24 - 1 - read-write - - - - - INT_ST - Interrupt status registers - 0x40 - 0x20 - - - DONE_INT_ST - This status interrupt bit turns to high level when JPEG finishes encoding a picture.. - 0 - 1 - read-only - - - RLE_PARALLEL_ERR_INT_ST - The status interrupt bit to sign that rle parallel error when decoding. - 1 - 1 - read-only - - - CID_ERR_INT_ST - The status interrupt bit to sign that scan id check with component fails when decoding. - 2 - 1 - read-only - - - C_DHT_DC_ID_ERR_INT_ST - The status interrupt bit to sign that scan component's dc dht id check with dc dht table's id fails when decoding. - 3 - 1 - read-only - - - C_DHT_AC_ID_ERR_INT_ST - The status interrupt bit to sign that scan component's ac dht id check with ac dht table's id fails when decoding. - 4 - 1 - read-only - - - C_DQT_ID_ERR_INT_ST - The status interrupt bit to sign that scan component's dqt id check with dqt table's id fails when decoding. - 5 - 1 - read-only - - - RST_UXP_ERR_INT_ST - The status interrupt bit to sign that RST header marker is detected but restart interval is 0 when decoding. - 6 - 1 - read-only - - - RST_CHECK_NONE_ERR_INT_ST - The status interrupt bit to sign that RST header marker is not detected but restart interval is not 0 when decoding. - 7 - 1 - read-only - - - RST_CHECK_POS_ERR_INT_ST - The status interrupt bit to sign that RST header marker position mismatches with restart interval when decoding. - 8 - 1 - read-only - - - OUT_EOF_INT_ST - The status interrupt bit turns to high level when the last pixel of one square has been transmitted for Tx channel. - 9 - 1 - read-only - - - SR_COLOR_MODE_ERR_INT_ST - The status interrupt bit to sign that the selected source color mode is not supported. - 10 - 1 - read-only - - - DCT_DONE_INT_ST - The status interrupt bit to sign that one dct calculation is finished. - 11 - 1 - read-only - - - BS_LAST_BLOCK_EOF_INT_ST - The status interrupt bit to sign that the coding process for last block is finished. - 12 - 1 - read-only - - - SCAN_CHECK_NONE_ERR_INT_ST - The status interrupt bit to sign that SOS header marker is not detected but there are still components left to be decoded. - 13 - 1 - read-only - - - SCAN_CHECK_POS_ERR_INT_ST - The status interrupt bit to sign that SOS header marker position wrong when decoding. - 14 - 1 - read-only - - - UXP_DET_INT_ST - The status interrupt bit to sign that unsupported header marker is detected when decoding. - 15 - 1 - read-only - - - EN_FRAME_EOF_ERR_INT_ST - The status interrupt bit to sign that received pixel blocks are smaller than expected when encoding. - 16 - 1 - read-only - - - EN_FRAME_EOF_LACK_INT_ST - The status interrupt bit to sign that the frame eof sign bit from dma input is missing when encoding. But the number of pixel blocks is enough. - 17 - 1 - read-only - - - DE_FRAME_EOF_ERR_INT_ST - The status interrupt bit to sign that decoded blocks are smaller than expected when decoding. - 18 - 1 - read-only - - - DE_FRAME_EOF_LACK_INT_ST - The status interrupt bit to sign that the either frame eof from dma input or eoi marker is missing when encoding. But the number of decoded blocks is enough. - 19 - 1 - read-only - - - SOS_UNMATCH_ERR_INT_ST - The status interrupt bit to sign that the component number of a scan is 0 or does not match the sos marker's length when decoding. - 20 - 1 - read-only - - - MARKER_ERR_FST_SCAN_INT_ST - The status interrupt bit to sign that the first scan has header marker error when decoding. - 21 - 1 - read-only - - - MARKER_ERR_OTHER_SCAN_INT_ST - The status interrupt bit to sign that the following scans but not the first scan have header marker error when decoding. - 22 - 1 - read-only - - - UNDET_INT_ST - The status interrupt bit to sign that JPEG format is not detected at the eof data of a packet when decoding. - 23 - 1 - read-only - - - DECODE_TIMEOUT_INT_ST - The status interrupt bit to sign that decode pause time is longer than the setting decode timeout time when decoding. - 24 - 1 - read-only - - - - - INT_CLR - Interrupt clear registers - 0x44 - 0x20 - - - DONE_INT_CLR - This clear interrupt bit turns to high level when JPEG finishes encoding a picture.. - 0 - 1 - write-only - - - RLE_PARALLEL_ERR_INT_CLR - The clear interrupt bit to sign that rle parallel error when decoding. - 1 - 1 - write-only - - - CID_ERR_INT_CLR - The clear interrupt bit to sign that scan id check with component fails when decoding. - 2 - 1 - write-only - - - C_DHT_DC_ID_ERR_INT_CLR - The clear interrupt bit to sign that scan component's dc dht id check with dc dht table's id fails when decoding. - 3 - 1 - write-only - - - C_DHT_AC_ID_ERR_INT_CLR - The clear interrupt bit to sign that scan component's ac dht id check with ac dht table's id fails when decoding. - 4 - 1 - write-only - - - C_DQT_ID_ERR_INT_CLR - The clear interrupt bit to sign that scan component's dqt id check with dqt table's id fails when decoding. - 5 - 1 - write-only - - - RST_UXP_ERR_INT_CLR - The clear interrupt bit to sign that RST header marker is detected but restart interval is 0 when decoding. - 6 - 1 - write-only - - - RST_CHECK_NONE_ERR_INT_CLR - The clear interrupt bit to sign that RST header marker is not detected but restart interval is not 0 when decoding. - 7 - 1 - write-only - - - RST_CHECK_POS_ERR_INT_CLR - The clear interrupt bit to sign that RST header marker position mismatches with restart interval when decoding. - 8 - 1 - write-only - - - OUT_EOF_INT_CLR - The clear interrupt bit turns to high level when the last pixel of one square has been transmitted for Tx channel. - 9 - 1 - write-only - - - SR_COLOR_MODE_ERR_INT_CLR - The clear interrupt bit to sign that the selected source color mode is not supported. - 10 - 1 - write-only - - - DCT_DONE_INT_CLR - The clear interrupt bit to sign that one dct calculation is finished. - 11 - 1 - write-only - - - BS_LAST_BLOCK_EOF_INT_CLR - The clear interrupt bit to sign that the coding process for last block is finished. - 12 - 1 - write-only - - - SCAN_CHECK_NONE_ERR_INT_CLR - The clear interrupt bit to sign that SOS header marker is not detected but there are still components left to be decoded. - 13 - 1 - write-only - - - SCAN_CHECK_POS_ERR_INT_CLR - The clear interrupt bit to sign that SOS header marker position wrong when decoding. - 14 - 1 - write-only - - - UXP_DET_INT_CLR - The clear interrupt bit to sign that unsupported header marker is detected when decoding. - 15 - 1 - write-only - - - EN_FRAME_EOF_ERR_INT_CLR - The clear interrupt bit to sign that received pixel blocks are smaller than expected when encoding. - 16 - 1 - write-only - - - EN_FRAME_EOF_LACK_INT_CLR - The clear interrupt bit to sign that the frame eof sign bit from dma input is missing when encoding. But the number of pixel blocks is enough. - 17 - 1 - write-only - - - DE_FRAME_EOF_ERR_INT_CLR - The clear interrupt bit to sign that decoded blocks are smaller than expected when decoding. - 18 - 1 - write-only - - - DE_FRAME_EOF_LACK_INT_CLR - The clear interrupt bit to sign that the either frame eof from dma input or eoi marker is missing when encoding. But the number of decoded blocks is enough. - 19 - 1 - write-only - - - SOS_UNMATCH_ERR_INT_CLR - The clear interrupt bit to sign that the component number of a scan is 0 or does not match the sos marker's length when decoding. - 20 - 1 - write-only - - - MARKER_ERR_FST_SCAN_INT_CLR - The clear interrupt bit to sign that the first scan has header marker error when decoding. - 21 - 1 - write-only - - - MARKER_ERR_OTHER_SCAN_INT_CLR - The clear interrupt bit to sign that the following scans but not the first scan have header marker error when decoding. - 22 - 1 - write-only - - - UNDET_INT_CLR - The clear interrupt bit to sign that JPEG format is not detected at the eof data of a packet when decoding. - 23 - 1 - write-only - - - DECODE_TIMEOUT_INT_CLR - The clear interrupt bit to sign that decode pause time is longer than the setting decode timeout time when decoding. - 24 - 1 - write-only - - - - - STATUS0 - Trace and Debug registers - 0x48 - 0x20 - - - BITSTREAM_EOF_VLD_CNT - the valid bit count for last bitstream - 11 - 6 - read-only - - - DCTOUT_ZZSCAN_ADDR - the zig-zag read addr from dctout_ram - 17 - 6 - read-only - - - QNRVAL_ZZSCAN_ADDR - the zig-zag read addr from qnrval_ram - 23 - 6 - read-only - - - REG_STATE_YUV - the state of jpeg fsm - 29 - 3 - read-only - - - - - STATUS2 - Trace and Debug registers - 0x4C - 0x20 - 0x08000000 - - - SOURCE_PIXEL - source pixels fetched from dma - 0 - 24 - read-only - - - LAST_BLOCK - indicate the encoding process for the last mcu of the picture - 24 - 1 - read-only - - - LAST_MCU - indicate the encoding process for the last block of the picture - 25 - 1 - read-only - - - LAST_DC - indicate the encoding process is at the header of the last block of the picture - 26 - 1 - read-only - - - PACKFIFO_READY - the jpeg pack_fifo ready signal, high active - 27 - 1 - read-only - - - - - STATUS3 - Trace and Debug registers - 0x50 - 0x20 - - - YO - component y transferred from rgb input - 0 - 9 - read-only - - - Y_READY - component y valid signal, high active - 9 - 1 - read-only - - - CBO - component cb transferred from rgb input - 10 - 9 - read-only - - - CB_READY - component cb valid signal, high active - 19 - 1 - read-only - - - CRO - component cr transferred from rgb input - 20 - 9 - read-only - - - CR_READY - component cr valid signal, high active - 29 - 1 - read-only - - - - - STATUS4 - Trace and Debug registers - 0x54 - 0x20 - - - HFM_BITSTREAM - the hufman bitstream during encoding process - 0 - 32 - read-only - - - - - DHT_TOTLEN_DC0 - Trace and Debug registers - 0x58 - 0x20 - - - DHT_TOTLEN_DC0 - write the numbers of 1~n codeword length sum from 1~16 of dc0 table - 0 - 32 - read-only - - - - - DHT_VAl_DC0 - Trace and Debug registers - 0x5C - 0x20 - - - DHT_VAL_DC0 - write codeword corresponding huffman values of dc0 table - 0 - 32 - read-only - - - - - DHT_TOTLEN_AC0 - Trace and Debug registers - 0x60 - 0x20 - - - DHT_TOTLEN_AC0 - write the numbers of 1~n codeword length sum from 1~16 of ac0 table - 0 - 32 - read-only - - - - - DHT_VAl_AC0 - Trace and Debug registers - 0x64 - 0x20 - - - DHT_VAL_AC0 - write codeword corresponding huffman values of ac0 table - 0 - 32 - read-only - - - - - DHT_TOTLEN_DC1 - Trace and Debug registers - 0x68 - 0x20 - - - DHT_TOTLEN_DC1 - write the numbers of 1~n codeword length sum from 1~16 of dc1 table - 0 - 32 - read-only - - - - - DHT_VAl_DC1 - Trace and Debug registers - 0x6C - 0x20 - - - DHT_VAL_DC1 - write codeword corresponding huffman values of dc1 table - 0 - 32 - read-only - - - - - DHT_TOTLEN_AC1 - Trace and Debug registers - 0x70 - 0x20 - - - DHT_TOTLEN_AC1 - write the numbers of 1~n codeword length sum from 1~16 of ac1 table - 0 - 32 - read-only - - - - - DHT_VAl_AC1 - Trace and Debug registers - 0x74 - 0x20 - - - DHT_VAL_AC1 - write codeword corresponding huffman values of ac1 table - 0 - 32 - read-only - - - - - DHT_CODEMIN_DC0 - Trace and Debug registers - 0x78 - 0x20 - - - DHT_CODEMIN_DC0 - write the minimum codeword of code length from 1~16 of dc0 table. The codeword is left shifted to the MSB position of a 16bit word - 0 - 32 - read-only - - - - - DHT_CODEMIN_AC0 - Trace and Debug registers - 0x7C - 0x20 - - - DHT_CODEMIN_AC0 - write the minimum codeword of code length from 1~16 of ac0 table. The codeword is left shifted to the MSB position of a 16bit word - 0 - 32 - read-only - - - - - DHT_CODEMIN_DC1 - Trace and Debug registers - 0x80 - 0x20 - - - DHT_CODEMIN_DC1 - write the minimum codeword of code length from 1~16 of dc1 table. The codeword is left shifted to the MSB position of a 16bit word - 0 - 32 - read-only - - - - - DHT_CODEMIN_AC1 - Trace and Debug registers - 0x84 - 0x20 - - - DHT_CODEMIN_AC1 - write the minimum codeword of code length from 1~16 of ac1 table. The codeword is left shifted to the MSB position of a 16bit word - 0 - 32 - read-only - - - - - DECODER_STATUS0 - Trace and Debug registers - 0x88 - 0x20 - - - DECODE_BYTE_CNT - Reserved - 0 - 26 - read-only - - - HEADER_DEC_ST - Reserved - 26 - 4 - read-only - - - DECODE_SAMPLE_SEL - Reserved - 30 - 2 - read-only - - - - - DECODER_STATUS1 - Trace and Debug registers - 0x8C - 0x20 - - - ENCODE_DATA - Reserved - 0 - 16 - read-only - - - COUNT_Q - Reserved - 16 - 7 - read-only - - - MCU_FSM_READY - Reserved - 23 - 1 - read-only - - - DECODE_DATA - Reserved - 24 - 8 - read-only - - - - - DECODER_STATUS2 - Trace and Debug registers - 0x90 - 0x20 - - - COMP_BLOCK_NUM - Reserved - 0 - 26 - read-only - - - SCAN_NUM - Reserved - 26 - 3 - read-only - - - RST_CHECK_WAIT - Reserved - 29 - 1 - read-only - - - SCAN_CHECK_WAIT - Reserved - 30 - 1 - read-only - - - MCU_IN_PROC - Reserved - 31 - 1 - read-only - - - - - DECODER_STATUS3 - Trace and Debug registers - 0x94 - 0x20 - - - LOOKUP_DATA - Reserved - 0 - 32 - read-only - - - - - DECODER_STATUS4 - Trace and Debug registers - 0x98 - 0x20 - - - BLOCK_EOF_CNT - Reserved - 0 - 26 - read-only - - - DEZIGZAG_READY - Reserved - 26 - 1 - read-only - - - DE_FRAME_EOF_CHECK - Reserved - 27 - 1 - read-only - - - DE_DMA2D_IN_PUSH - Reserved - 28 - 1 - read-only - - - - - DECODER_STATUS5 - Trace and Debug registers - 0x9C - 0x20 - - - IDCT_HFM_DATA - Reserved - 0 - 16 - read-only - - - NS0 - Reserved - 16 - 3 - read-only - - - NS1 - Reserved - 19 - 3 - read-only - - - NS2 - Reserved - 22 - 3 - read-only - - - NS3 - Reserved - 25 - 3 - read-only - - - DATA_LAST_O - Reserved - 28 - 1 - read-only - - - RDN_RESULT - redundant registers for jpeg - 29 - 1 - read-only - - - RDN_ENA - redundant control registers for jpeg - 30 - 1 - read-write - - - - - STATUS5 - Trace and Debug registers - 0xA0 - 0x20 - - - PIC_BLOCK_NUM - Reserved - 0 - 24 - read-only - - - - - ECO_LOW - Trace and Debug registers - 0xA4 - 0x20 - - - RDN_ECO_LOW - redundant registers for jpeg - 0 - 32 - read-write - - - - - ECO_HIGH - Trace and Debug registers - 0xA8 - 0x20 - 0xFFFFFFFF - - - RDN_ECO_HIGH - redundant registers for jpeg - 0 - 32 - read-write - - - - - SYS - Trace and Debug registers - 0xF8 - 0x20 - - - CLK_EN - Reserved - 31 - 1 - read-write - - - - - VERSION - Trace and Debug registers - 0xFC - 0x20 - 0x02111190 - - - JPEG_VER - Reserved - 0 - 28 - read-write - - - - - - - LCD_CAM - Camera/LCD Controller - LCDCAM - 0x500DC000 - - 0x0 - 0x4C - registers - - - - LCD_CLOCK - LCD clock config register. - 0x0 - 0x20 - 0x00000843 - - - LCD_CLKCNT_N - f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0. - 0 - 6 - read-write - - - LCD_CLK_EQU_SYSCLK - 1: f_LCD_PCLK = f_LCD_CLK. 0: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1). - 6 - 1 - read-write - - - LCD_CK_IDLE_EDGE - 1: LCD_PCLK line is high when idle 0: LCD_PCLK line is low when idle. - 7 - 1 - read-write - - - LCD_CK_OUT_EDGE - 1: LCD_PCLK line is high in the first half data cycle. 0: LCD_PCLK line is low in the second half data cycle. - 8 - 1 - read-write - - - LCD_CLKM_DIV_NUM - Integral LCD clock divider value - 9 - 8 - read-write - - - LCD_CLKM_DIV_B - Fractional clock divider numerator value - 17 - 6 - read-write - - - LCD_CLKM_DIV_A - Fractional clock divider denominator value - 23 - 6 - read-write - - - LCD_CLK_SEL - Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock. - 29 - 2 - read-write - - - CLK_EN - Set this bit to enable clk gate - 31 - 1 - read-write - - - - - CAM_CTRL - CAM config register. - 0x4 - 0x20 - 0x00000800 - - - CAM_STOP_EN - Camera stop enable signal, 1: camera stops when DMA Rx FIFO is full. 0: Not stop. - 0 - 1 - read-write - - - CAM_VSYNC_FILTER_THRES - Filter threshold value for CAM_VSYNC signal. - 1 - 3 - read-write - - - CAM_UPDATE - 1: Update Camera registers, will be cleared by hardware. 0 : Not care. - 4 - 1 - read-write - - - CAM_BYTE_ORDER - 1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in one byte mode, and bits[15:0] to bits[0:15] in two byte mode. 0: Not change. - 5 - 1 - read-write - - - CAM_BIT_ORDER - 1: invert data byte order, only valid in 2 byte mode. 0: Not change. - 6 - 1 - read-write - - - CAM_LINE_INT_EN - 1: Enable to generate CAM_HS_INT. 0: Disable. - 7 - 1 - read-write - - - CAM_VS_EOF_EN - 1: CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by reg_cam_rec_data_cyclelen. - 8 - 1 - read-write - - - CAM_CLKM_DIV_NUM - Integral Camera clock divider value - 9 - 8 - read-write - - - CAM_CLKM_DIV_B - Fractional clock divider numerator value - 17 - 6 - read-write - - - CAM_CLKM_DIV_A - Fractional clock divider denominator value - 23 - 6 - read-write - - - CAM_CLK_SEL - Select Camera module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock. - 29 - 2 - read-write - - - - - CAM_CTRL1 - CAM config register. - 0x8 - 0x20 - - - CAM_REC_DATA_BYTELEN - Camera receive data byte length minus 1 to set DMA in_suc_eof_int. - 0 - 16 - read-write - - - CAM_LINE_INT_NUM - The line number minus 1 to generate cam_hs_int. - 16 - 6 - read-write - - - CAM_CLK_INV - 1: Invert the input signal CAM_PCLK. 0: Not invert. - 22 - 1 - read-write - - - CAM_VSYNC_FILTER_EN - 1: Enable CAM_VSYNC filter function. 0: bypass. - 23 - 1 - read-write - - - CAM_2BYTE_EN - 1: The bit number of input data is 9~16. 0: The bit number of input data is 0~8. - 24 - 1 - read-write - - - CAM_DE_INV - CAM_DE invert enable signal, valid in high level. - 25 - 1 - read-write - - - CAM_HSYNC_INV - CAM_HSYNC invert enable signal, valid in high level. - 26 - 1 - read-write - - - CAM_VSYNC_INV - CAM_VSYNC invert enable signal, valid in high level. - 27 - 1 - read-write - - - CAM_VH_DE_MODE_EN - 1: Input control signals are CAM_DE CAM_HSYNC and CAM_VSYNC. 0: Input control signals are CAM_DE and CAM_VSYNC. - 28 - 1 - read-write - - - CAM_START - Camera module start signal. - 29 - 1 - read-write - - - CAM_RESET - Camera module reset signal. - 30 - 1 - write-only - - - CAM_AFIFO_RESET - Camera AFIFO reset signal. - 31 - 1 - write-only - - - - - CAM_RGB_YUV - CAM YUV/RGB converter configuration register. - 0xC - 0x20 - 0x00C00000 - - - CAM_CONV_8BITS_DATA_INV - 1:invert every two 8bits input data. 2. disabled. - 21 - 1 - read-write - - - CAM_CONV_YUV2YUV_MODE - 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable yuv2yuv mode, trans_mode must be set to 1. - 22 - 2 - read-write - - - CAM_CONV_YUV_MODE - 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv mode of Data_in - 24 - 2 - read-write - - - CAM_CONV_PROTOCOL_MODE - 0:BT601. 1:BT709. - 26 - 1 - read-write - - - CAM_CONV_DATA_OUT_MODE - LIMIT or FULL mode of Data out. 0: limit. 1: full - 27 - 1 - read-write - - - CAM_CONV_DATA_IN_MODE - LIMIT or FULL mode of Data in. 0: limit. 1: full - 28 - 1 - read-write - - - CAM_CONV_MODE_8BITS_ON - 0: 16bits mode. 1: 8bits mode. - 29 - 1 - read-write - - - CAM_CONV_TRANS_MODE - 0: YUV to RGB. 1: RGB to YUV. - 30 - 1 - read-write - - - CAM_CONV_ENABLE - 0: Bypass converter. 1: Enable converter. - 31 - 1 - read-write - - - - - LCD_RGB_YUV - LCD YUV/RGB converter configuration register. - 0x10 - 0x20 - 0x00C00000 - - - LCD_CONV_8BITS_DATA_INV - 1:invert every two 8bits input data. 2. disabled. - 20 - 1 - read-write - - - LCD_CONV_TXTORX - 0: txtorx mode off. 1: txtorx mode on. - 21 - 1 - read-write - - - LCD_CONV_YUV2YUV_MODE - 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable yuv2yuv mode, trans_mode must be set to 1. - 22 - 2 - read-write - - - LCD_CONV_YUV_MODE - 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv mode of Data_in - 24 - 2 - read-write - - - LCD_CONV_PROTOCOL_MODE - 0:BT601. 1:BT709. - 26 - 1 - read-write - - - LCD_CONV_DATA_OUT_MODE - LIMIT or FULL mode of Data out. 0: limit. 1: full - 27 - 1 - read-write - - - LCD_CONV_DATA_IN_MODE - LIMIT or FULL mode of Data in. 0: limit. 1: full - 28 - 1 - read-write - - - LCD_CONV_MODE_8BITS_ON - 0: 16bits mode. 1: 8bits mode. - 29 - 1 - read-write - - - LCD_CONV_TRANS_MODE - 0: YUV to RGB. 1: RGB to YUV. - 30 - 1 - read-write - - - LCD_CONV_ENABLE - 0: Bypass converter. 1: Enable converter. - 31 - 1 - read-write - - - - - LCD_USER - LCD config register. - 0x14 - 0x20 - 0x00000001 - - - LCD_DOUT_CYCLELEN - The output data cycles minus 1 of LCD module. - 0 - 13 - read-write - - - LCD_ALWAYS_OUT_EN - LCD always output when LCD is in LCD_DOUT state, unless reg_lcd_start is cleared or reg_lcd_reset is set. - 13 - 1 - read-write - - - LCD_DOUT_BYTE_SWIZZLE_MODE - 0: ABAB->BABA. 1: ABC->ACB. 2: ABC->BAC. 3: ABC->BCA. 4:ABC->CAB. 5:ABC->CBA - 14 - 3 - read-write - - - LCD_DOUT_BYTE_SWIZZLE_ENABLE - 1: enable byte swizzle 0: disable - 17 - 1 - read-write - - - LCD_DOUT_BIT_ORDER - 1: change bit order in every byte. 0: Not change. - 18 - 1 - read-write - - - LCD_BYTE_MODE - 2: 24bit mode. 1: 16bit mode. 0: 8bit mode - 19 - 2 - read-write - - - LCD_UPDATE - 1: Update LCD registers, will be cleared by hardware. 0 : Not care. - 21 - 1 - read-write - - - LCD_BIT_ORDER - 1: Change data bit order, change LCD_DATA_out[7:0] to LCD_DATA_out[0:7] in one byte mode, and bits[15:0] to bits[0:15] in two byte mode. 0: Not change. - 22 - 1 - read-write - - - LCD_BYTE_ORDER - 1: invert data byte order, only valid in 2 byte mode. 0: Not change. - 23 - 1 - read-write - - - LCD_DOUT - 1: Be able to send data out in LCD sequence when LCD starts. 0: Disable. - 24 - 1 - read-write - - - LCD_DUMMY - 1: Enable DUMMY phase in LCD sequence when LCD starts. 0: Disable. - 25 - 1 - read-write - - - LCD_CMD - 1: Be able to send command in LCD sequence when LCD starts. 0: Disable. - 26 - 1 - read-write - - - LCD_START - LCD start sending data enable signal, valid in high level. - 27 - 1 - read-write - - - LCD_RESET - The value of command. - 28 - 1 - write-only - - - LCD_DUMMY_CYCLELEN - The dummy cycle length minus 1. - 29 - 2 - read-write - - - LCD_CMD_2_CYCLE_EN - The cycle length of command phase. 1: 2 cycles. 0: 1 cycle. - 31 - 1 - read-write - - - - - LCD_MISC - LCD config register. - 0x18 - 0x20 - 0x000000C0 - - - LCD_WIRE_MODE - The wire width of LCD output. 0: 8bit. 1: 16bit 2: 24bit - 4 - 2 - read-write - - - LCD_VFK_CYCLELEN - The setup cycle length minus 1 in LCD non-RGB mode. - 6 - 6 - read-write - - - LCD_VBK_CYCLELEN - The vertical back blank region cycle length minus 1 in LCD RGB mode, or the hold time cycle length in LCD non-RGB mode. - 12 - 13 - read-write - - - LCD_NEXT_FRAME_EN - 1: Send the next frame data when the current frame is sent out. 0: LCD stops when the current frame is sent out. - 25 - 1 - read-write - - - LCD_BK_EN - 1: Enable blank region when LCD sends data out. 0: No blank region. - 26 - 1 - read-write - - - LCD_AFIFO_RESET - LCD AFIFO reset signal. - 27 - 1 - write-only - - - LCD_CD_DATA_SET - 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DOUT state. 0: LCD_CD = reg_cd_idle_edge. - 28 - 1 - read-write - - - LCD_CD_DUMMY_SET - 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DUMMY state. 0: LCD_CD = reg_cd_idle_edge. - 29 - 1 - read-write - - - LCD_CD_CMD_SET - 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_CMD state. 0: LCD_CD = reg_cd_idle_edge. - 30 - 1 - read-write - - - LCD_CD_IDLE_EDGE - The default value of LCD_CD. - 31 - 1 - read-write - - - - - LCD_CTRL - LCD config register. - 0x1C - 0x20 - - - LCD_HB_FRONT - It is the horizontal blank front porch of a frame. - 0 - 11 - read-write - - - LCD_VA_HEIGHT - It is the vertical active height of a frame. - 11 - 10 - read-write - - - LCD_VT_HEIGHT - It is the vertical total height of a frame. - 21 - 10 - read-write - - - LCD_RGB_MODE_EN - 1: Enable LCD RGB mode. 0: Disable LCD RGB mode. - 31 - 1 - read-write - - - - - LCD_CTRL1 - LCD config register. - 0x20 - 0x20 - - - LCD_VB_FRONT - It is the vertical blank front porch of a frame. - 0 - 8 - read-write - - - LCD_HA_WIDTH - It is the horizontal active width of a frame. - 8 - 12 - read-write - - - LCD_HT_WIDTH - It is the horizontal total width of a frame. - 20 - 12 - read-write - - - - - LCD_CTRL2 - LCD config register. - 0x24 - 0x20 - 0x00010001 - - - LCD_VSYNC_WIDTH - It is the position of LCD_VSYNC active pulse in a line. - 0 - 7 - read-write - - - LCD_VSYNC_IDLE_POL - It is the idle value of LCD_VSYNC. - 7 - 1 - read-write - - - LCD_DE_IDLE_POL - It is the idle value of LCD_DE. - 8 - 1 - read-write - - - LCD_HS_BLANK_EN - 1: The pulse of LCD_HSYNC is out in vertical blanking lines RGB mode. 0: LCD_HSYNC pulse is valid only in active region lines in RGB mode. - 9 - 1 - read-write - - - LCD_HSYNC_WIDTH - It is the position of LCD_HSYNC active pulse in a line. - 16 - 7 - read-write - - - LCD_HSYNC_IDLE_POL - It is the idle value of LCD_HSYNC. - 23 - 1 - read-write - - - LCD_HSYNC_POSITION - It is the position of LCD_HSYNC active pulse in a line. - 24 - 8 - read-write - - - - - LCD_FIRST_CMD_VAL - LCD config register. - 0x28 - 0x20 - - - LCD_FIRST_CMD_VALUE - The LCD write command value of first cmd cycle. - 0 - 32 - read-write - - - - - LCD_LATTER_CMD_VAL - LCD config register. - 0x2C - 0x20 - - - LCD_LATTER_CMD_VALUE - The LCD write command value of latter cmd cycle. - 0 - 32 - read-write - - - - - LCD_DLY_MODE_CFG1 - LCD config register. - 0x30 - 0x20 - - - DOUT16_MODE - The output data bit 0 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. - 0 - 2 - read-write - - - DOUT17_MODE - The output data bit 2 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. - 2 - 2 - read-write - - - DOUT18_MODE - The output data bit 4 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. - 4 - 2 - read-write - - - DOUT19_MODE - The output data bit 6 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. - 6 - 2 - read-write - - - DOUT20_MODE - The output data bit 8 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. - 8 - 2 - read-write - - - DOUT21_MODE - The output data bit 10 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. - 10 - 2 - read-write - - - DOUT22_MODE - The output data bit 12 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. - 12 - 2 - read-write - - - DOUT23_MODE - The output data bit 14 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. - 14 - 2 - read-write - - - LCD_CD_MODE - The output LCD_CD is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. - 16 - 2 - read-write - - - LCD_DE_MODE - The output LCD_DE is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. - 18 - 2 - read-write - - - LCD_HSYNC_MODE - The output LCD_HSYNC is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. - 20 - 2 - read-write - - - LCD_VSYNC_MODE - The output LCD_VSYNC is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. - 22 - 2 - read-write - - - - - LCD_DLY_MODE_CFG2 - LCD config register. - 0x38 - 0x20 - - - DOUT0_MODE - The output data bit 0 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. - 0 - 2 - read-write - - - DOUT1_MODE - The output data bit 2 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. - 2 - 2 - read-write - - - DOUT2_MODE - The output data bit 4 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. - 4 - 2 - read-write - - - DOUT3_MODE - The output data bit 6 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. - 6 - 2 - read-write - - - DOUT4_MODE - The output data bit 8 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. - 8 - 2 - read-write - - - DOUT5_MODE - The output data bit 10 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. - 10 - 2 - read-write - - - DOUT6_MODE - The output data bit 12 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. - 12 - 2 - read-write - - - DOUT7_MODE - The output data bit 14 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. - 14 - 2 - read-write - - - DOUT8_MODE - The output data bit 16 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. - 16 - 2 - read-write - - - DOUT9_MODE - The output data bit 18 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. - 18 - 2 - read-write - - - DOUT10_MODE - The output data bit 20 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. - 20 - 2 - read-write - - - DOUT11_MODE - The output data bit 22 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. - 22 - 2 - read-write - - - DOUT12_MODE - The output data bit 24 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. - 24 - 2 - read-write - - - DOUT13_MODE - The output data bit 26 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. - 26 - 2 - read-write - - - DOUT14_MODE - The output data bit 28 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. - 28 - 2 - read-write - - - DOUT15_MODE - The output data bit 30 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. - 30 - 2 - read-write - - - - - LC_DMA_INT_ENA - LCDCAM interrupt enable register. - 0x64 - 0x20 - - - LCD_VSYNC_INT_ENA - The enable bit for LCD frame end interrupt. - 0 - 1 - read-write - - - LCD_TRANS_DONE_INT_ENA - The enable bit for lcd transfer end interrupt. - 1 - 1 - read-write - - - CAM_VSYNC_INT_ENA - The enable bit for Camera frame end interrupt. - 2 - 1 - read-write - - - CAM_HS_INT_ENA - The enable bit for Camera line interrupt. - 3 - 1 - read-write - - - - - LC_DMA_INT_RAW - LCDCAM interrupt raw register, valid in level. - 0x68 - 0x20 - - - LCD_VSYNC_INT_RAW - The raw bit for LCD frame end interrupt. - 0 - 1 - read-only - - - LCD_TRANS_DONE_INT_RAW - The raw bit for lcd transfer end interrupt. - 1 - 1 - read-only - - - CAM_VSYNC_INT_RAW - The raw bit for Camera frame end interrupt. - 2 - 1 - read-only - - - CAM_HS_INT_RAW - The raw bit for Camera line interrupt. - 3 - 1 - read-only - - - - - LC_DMA_INT_ST - LCDCAM interrupt status register. - 0x6C - 0x20 - - - LCD_VSYNC_INT_ST - The status bit for LCD frame end interrupt. - 0 - 1 - read-only - - - LCD_TRANS_DONE_INT_ST - The status bit for lcd transfer end interrupt. - 1 - 1 - read-only - - - CAM_VSYNC_INT_ST - The status bit for Camera frame end interrupt. - 2 - 1 - read-only - - - CAM_HS_INT_ST - The status bit for Camera transfer end interrupt. - 3 - 1 - read-only - - - - - LC_DMA_INT_CLR - LCDCAM interrupt clear register. - 0x70 - 0x20 - - - LCD_VSYNC_INT_CLR - The clear bit for LCD frame end interrupt. - 0 - 1 - write-only - - - LCD_TRANS_DONE_INT_CLR - The clear bit for lcd transfer end interrupt. - 1 - 1 - write-only - - - CAM_VSYNC_INT_CLR - The clear bit for Camera frame end interrupt. - 2 - 1 - write-only - - - CAM_HS_INT_CLR - The clear bit for Camera line interrupt. - 3 - 1 - write-only - - - - - LC_REG_DATE - Version register - 0xFC - 0x20 - 0x02303090 - - - LC_DATE - LCD_CAM version control register - 0 - 28 - read-write - - - - - - - LEDC - LED Control PWM (Pulse Width Modulation) - LEDC - 0x500D3000 - - 0x0 - 0x124 - registers - - - LEDC - 52 - - - - 8 - 0x14 - CH%s_CONF0 - Configuration register 0 for channel %s - 0x0 - 0x20 - - - TIMER_SEL_CH - Configures which timer is channel %s selected.\\0: Select timer0\\1: Select timer1\\2: Select timer2\\3: Select timer3 - 0 - 2 - read-write - - - SIG_OUT_EN_CH - Configures whether or not to enable signal output on channel %s.\\0: Signal output disable\\1: Signal output enable - 2 - 1 - read-write - - - IDLE_LV_CH - Configures the output value when channel %s is inactive. Valid only when LEDC_SIG_OUT_EN_CH%s is 0.\\0: Output level is low\\1: Output level is high - 3 - 1 - read-write - - - PARA_UP_CH - Configures whether or not to update LEDC_HPOINT_CH%s, LEDC_DUTY_START_CH%s, LEDC_SIG_OUT_EN_CH%s, LEDC_TIMER_SEL_CH%s, LEDC_DUTY_NUM_CH%s, LEDC_DUTY_CYCLE_CH%s, LEDC_DUTY_SCALE_CH%s, LEDC_DUTY_INC_CH%s, and LEDC_OVF_CNT_EN_CH%s fields for channel %s, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update - 4 - 1 - write-only - - - OVF_NUM_CH - Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH%s_INT interrupt will be triggered when channel %s overflows for (LEDC_OVF_NUM_CH%s + 1) times. - 5 - 10 - read-write - - - OVF_CNT_EN_CH - Configures whether or not to enable the ovf_cnt of channel %s.\\0: Disable\\1: Enable - 15 - 1 - read-write - - - OVF_CNT_RESET_CH - Configures whether or not to reset the ovf_cnt of channel %s.\\0: Invalid. No effect\\1: Reset the ovf_cnt - 16 - 1 - write-only - - - - - 8 - 0x14 - CH%s_HPOINT - High point register for channel %s - 0x4 - 0x20 - - - HPOINT_CH - Configures high point of signal output on channel %s. The output value changes to high when the selected timers has reached the value specified by this register. - 0 - 20 - read-write - - - - - 8 - 0x14 - CH%s_DUTY - Initial duty cycle register for channel %s - 0x8 - 0x20 - - - DUTY_CH - Configures the duty of signal output on channel %s. - 0 - 25 - read-write - - - - - 8 - 0x14 - CH%s_CONF1 - Configuration register 1 for channel %s - 0xC - 0x20 - - - DUTY_START_CH - Configures whether the duty cycle fading configurations take effect.\\0: Not take effect\\1: Take effect - 31 - 1 - read-write - - - - - 8 - 0x14 - CH%s_DUTY_R - Current duty cycle register for channel %s - 0x10 - 0x20 - - - DUTY_CH_R - Represents the current duty of output signal on channel %s. - 0 - 25 - read-only - - - - - 4 - 0x8 - TIMER%s_CONF - Timer %s configuration register - 0xA0 - 0x20 - 0x01000000 - - - TIMER_DUTY_RES - Configures the range of the counter in timer %s. - 0 - 5 - read-write - - - CLK_DIV_TIMER - Configures the divisor for the divider in timer %s.The least significant eight bits represent the fractional part. - 5 - 18 - read-write - - - TIMER_PAUSE - Configures whether or not to pause the counter in timer %s.\\0: Normal\\1: Pause - 23 - 1 - read-write - - - TIMER_RST - Configures whether or not to reset timer %s. The counter will show 0 after reset.\\0: Not reset\\1: Reset - 24 - 1 - read-write - - - TICK_SEL_TIMER - Configures which clock is timer %s selected. Unused. - 25 - 1 - read-write - - - TIMER_PARA_UP - Configures whether or not to update LEDC_CLK_DIV_TIMER%s and LEDC_TIMER%s_DUTY_RES.\\0: Invalid. No effect\\1: Update - 26 - 1 - write-only - - - - - 4 - 0x8 - TIMER%s_VALUE - Timer %s current counter value register - 0xA4 - 0x20 - - - TIMER_CNT - Represents the current counter value of timer %s. - 0 - 20 - read-only - - - - - INT_RAW - Interrupt raw status register - 0xC0 - 0x20 - - - TIMER0_OVF_INT_RAW - Raw status bit: The raw interrupt status of LEDC_TIMER0_OVF_INT. Triggered when the timer0 has reached its maximum counter value. - 0 - 1 - read-write - - - TIMER1_OVF_INT_RAW - Raw status bit: The raw interrupt status of LEDC_TIMER1_OVF_INT. Triggered when the timer1 has reached its maximum counter value. - 1 - 1 - read-write - - - TIMER2_OVF_INT_RAW - Raw status bit: The raw interrupt status of LEDC_TIMER2_OVF_INT. Triggered when the timer2 has reached its maximum counter value. - 2 - 1 - read-write - - - TIMER3_OVF_INT_RAW - Raw status bit: The raw interrupt status of LEDC_TIMER3_OVF_INT. Triggered when the timer3 has reached its maximum counter value. - 3 - 1 - read-write - - - DUTY_CHNG_END_CH0_INT_RAW - Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. Triggered when the fading of duty has finished. - 4 - 1 - read-write - - - DUTY_CHNG_END_CH1_INT_RAW - Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. Triggered when the fading of duty has finished. - 5 - 1 - read-write - - - DUTY_CHNG_END_CH2_INT_RAW - Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. Triggered when the fading of duty has finished. - 6 - 1 - read-write - - - DUTY_CHNG_END_CH3_INT_RAW - Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. Triggered when the fading of duty has finished. - 7 - 1 - read-write - - - DUTY_CHNG_END_CH4_INT_RAW - Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. Triggered when the fading of duty has finished. - 8 - 1 - read-write - - - DUTY_CHNG_END_CH5_INT_RAW - Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. Triggered when the fading of duty has finished. - 9 - 1 - read-write - - - DUTY_CHNG_END_CH6_INT_RAW - Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH6_INT. Triggered when the fading of duty has finished. - 10 - 1 - read-write - - - DUTY_CHNG_END_CH7_INT_RAW - Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH7_INT. Triggered when the fading of duty has finished. - 11 - 1 - read-write - - - OVF_CNT_CH0_INT_RAW - Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH0_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH0. - 12 - 1 - read-write - - - OVF_CNT_CH1_INT_RAW - Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH1_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH1. - 13 - 1 - read-write - - - OVF_CNT_CH2_INT_RAW - Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH2_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH2. - 14 - 1 - read-write - - - OVF_CNT_CH3_INT_RAW - Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH3_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH3. - 15 - 1 - read-write - - - OVF_CNT_CH4_INT_RAW - Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH4_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH4. - 16 - 1 - read-write - - - OVF_CNT_CH5_INT_RAW - Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH5_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH5. - 17 - 1 - read-write - - - OVF_CNT_CH6_INT_RAW - Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH6_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH6. - 18 - 1 - read-write - - - OVF_CNT_CH7_INT_RAW - Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH7_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH7. - 19 - 1 - read-write - - - - - INT_ST - Interrupt masked status register - 0xC4 - 0x20 - - - TIMER0_OVF_INT_ST - Masked status bit: The masked interrupt status of LEDC_TIMER0_OVF_INT. Valid only when LEDC_TIMER0_OVF_INT_ENA is set to 1. - 0 - 1 - read-only - - - TIMER1_OVF_INT_ST - Masked status bit: The masked interrupt status of LEDC_TIMER1_OVF_INT. Valid only when LEDC_TIMER1_OVF_INT_ENA is set to 1. - 1 - 1 - read-only - - - TIMER2_OVF_INT_ST - Masked status bit: The masked interrupt status of LEDC_TIMER2_OVF_INT. Valid only when LEDC_TIMER2_OVF_INT_ENA is set to 1. - 2 - 1 - read-only - - - TIMER3_OVF_INT_ST - Masked status bit: The masked interrupt status of LEDC_TIMER3_OVF_INT. Valid only when LEDC_TIMER3_OVF_INT_ENA is set to 1. - 3 - 1 - read-only - - - DUTY_CHNG_END_CH0_INT_ST - Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. Valid only when LEDC_DUTY_CHNG_END_CH0_INT_ENA is set to 1. - 4 - 1 - read-only - - - DUTY_CHNG_END_CH1_INT_ST - Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. Valid only when LEDC_DUTY_CHNG_END_CH1_INT_ENA is set to 1. - 5 - 1 - read-only - - - DUTY_CHNG_END_CH2_INT_ST - Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. Valid only when LEDC_DUTY_CHNG_END_CH2_INT_ENA is set to 1. - 6 - 1 - read-only - - - DUTY_CHNG_END_CH3_INT_ST - Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. Valid only when LEDC_DUTY_CHNG_END_CH3_INT_ENA is set to 1. - 7 - 1 - read-only - - - DUTY_CHNG_END_CH4_INT_ST - Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. Valid only when LEDC_DUTY_CHNG_END_CH4_INT_ENA is set to 1. - 8 - 1 - read-only - - - DUTY_CHNG_END_CH5_INT_ST - Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. Valid only when LEDC_DUTY_CHNG_END_CH5_INT_ENA is set to 1. - 9 - 1 - read-only - - - DUTY_CHNG_END_CH6_INT_ST - Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH6_INT. Valid only when LEDC_DUTY_CHNG_END_CH6_INT_ENA is set to 1. - 10 - 1 - read-only - - - DUTY_CHNG_END_CH7_INT_ST - Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH7_INT. Valid only when LEDC_DUTY_CHNG_END_CH7_INT_ENA is set to 1. - 11 - 1 - read-only - - - OVF_CNT_CH0_INT_ST - Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH0_INT. Valid only when LEDC_OVF_CNT_CH0_INT_ENA is set to 1. - 12 - 1 - read-only - - - OVF_CNT_CH1_INT_ST - Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH1_INT. Valid only when LEDC_OVF_CNT_CH1_INT_ENA is set to 1. - 13 - 1 - read-only - - - OVF_CNT_CH2_INT_ST - Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH2_INT. Valid only when LEDC_OVF_CNT_CH2_INT_ENA is set to 1. - 14 - 1 - read-only - - - OVF_CNT_CH3_INT_ST - Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH3_INT. Valid only when LEDC_OVF_CNT_CH3_INT_ENA is set to 1. - 15 - 1 - read-only - - - OVF_CNT_CH4_INT_ST - Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH4_INT. Valid only when LEDC_OVF_CNT_CH4_INT_ENA is set to 1. - 16 - 1 - read-only - - - OVF_CNT_CH5_INT_ST - Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH5_INT. Valid only when LEDC_OVF_CNT_CH5_INT_ENA is set to 1. - 17 - 1 - read-only - - - OVF_CNT_CH6_INT_ST - Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH6_INT. Valid only when LEDC_OVF_CNT_CH6_INT_ENA is set to 1. - 18 - 1 - read-only - - - OVF_CNT_CH7_INT_ST - Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH7_INT. Valid only when LEDC_OVF_CNT_CH7_INT_ENA is set to 1. - 19 - 1 - read-only - - - - - INT_ENA - Interrupt enable register - 0xC8 - 0x20 - - - TIMER0_OVF_INT_ENA - Enable bit: Write 1 to enable LEDC_TIMER0_OVF_INT. - 0 - 1 - read-write - - - TIMER1_OVF_INT_ENA - Enable bit: Write 1 to enable LEDC_TIMER1_OVF_INT. - 1 - 1 - read-write - - - TIMER2_OVF_INT_ENA - Enable bit: Write 1 to enable LEDC_TIMER2_OVF_INT. - 2 - 1 - read-write - - - TIMER3_OVF_INT_ENA - Enable bit: Write 1 to enable LEDC_TIMER3_OVF_INT. - 3 - 1 - read-write - - - DUTY_CHNG_END_CH0_INT_ENA - Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH0_INT. - 4 - 1 - read-write - - - DUTY_CHNG_END_CH1_INT_ENA - Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH1_INT. - 5 - 1 - read-write - - - DUTY_CHNG_END_CH2_INT_ENA - Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH2_INT. - 6 - 1 - read-write - - - DUTY_CHNG_END_CH3_INT_ENA - Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH3_INT. - 7 - 1 - read-write - - - DUTY_CHNG_END_CH4_INT_ENA - Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH4_INT. - 8 - 1 - read-write - - - DUTY_CHNG_END_CH5_INT_ENA - Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH5_INT. - 9 - 1 - read-write - - - DUTY_CHNG_END_CH6_INT_ENA - Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH6_INT. - 10 - 1 - read-write - - - DUTY_CHNG_END_CH7_INT_ENA - Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH7_INT. - 11 - 1 - read-write - - - OVF_CNT_CH0_INT_ENA - Enable bit: Write 1 to enable LEDC_OVF_CNT_CH0_INT. - 12 - 1 - read-write - - - OVF_CNT_CH1_INT_ENA - Enable bit: Write 1 to enable LEDC_OVF_CNT_CH1_INT. - 13 - 1 - read-write - - - OVF_CNT_CH2_INT_ENA - Enable bit: Write 1 to enable LEDC_OVF_CNT_CH2_INT. - 14 - 1 - read-write - - - OVF_CNT_CH3_INT_ENA - Enable bit: Write 1 to enable LEDC_OVF_CNT_CH3_INT. - 15 - 1 - read-write - - - OVF_CNT_CH4_INT_ENA - Enable bit: Write 1 to enable LEDC_OVF_CNT_CH4_INT. - 16 - 1 - read-write - - - OVF_CNT_CH5_INT_ENA - Enable bit: Write 1 to enable LEDC_OVF_CNT_CH5_INT. - 17 - 1 - read-write - - - OVF_CNT_CH6_INT_ENA - Enable bit: Write 1 to enable LEDC_OVF_CNT_CH6_INT. - 18 - 1 - read-write - - - OVF_CNT_CH7_INT_ENA - Enable bit: Write 1 to enable LEDC_OVF_CNT_CH7_INT. - 19 - 1 - read-write - - - - - INT_CLR - Interrupt clear register - 0xCC - 0x20 - - - TIMER0_OVF_INT_CLR - Clear bit: Write 1 to clear LEDC_TIMER0_OVF_INT. - 0 - 1 - write-only - - - TIMER1_OVF_INT_CLR - Clear bit: Write 1 to clear LEDC_TIMER1_OVF_INT. - 1 - 1 - write-only - - - TIMER2_OVF_INT_CLR - Clear bit: Write 1 to clear LEDC_TIMER2_OVF_INT. - 2 - 1 - write-only - - - TIMER3_OVF_INT_CLR - Clear bit: Write 1 to clear LEDC_TIMER3_OVF_INT. - 3 - 1 - write-only - - - DUTY_CHNG_END_CH0_INT_CLR - Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH0_INT. - 4 - 1 - write-only - - - DUTY_CHNG_END_CH1_INT_CLR - Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH1_INT. - 5 - 1 - write-only - - - DUTY_CHNG_END_CH2_INT_CLR - Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH2_INT. - 6 - 1 - write-only - - - DUTY_CHNG_END_CH3_INT_CLR - Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH3_INT. - 7 - 1 - write-only - - - DUTY_CHNG_END_CH4_INT_CLR - Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH4_INT. - 8 - 1 - write-only - - - DUTY_CHNG_END_CH5_INT_CLR - Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH5_INT. - 9 - 1 - write-only - - - DUTY_CHNG_END_CH6_INT_CLR - Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH6_INT. - 10 - 1 - write-only - - - DUTY_CHNG_END_CH7_INT_CLR - Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH7_INT. - 11 - 1 - write-only - - - OVF_CNT_CH0_INT_CLR - Clear bit: Write 1 to clear LEDC_OVF_CNT_CH0_INT. - 12 - 1 - write-only - - - OVF_CNT_CH1_INT_CLR - Clear bit: Write 1 to clear LEDC_OVF_CNT_CH1_INT. - 13 - 1 - write-only - - - OVF_CNT_CH2_INT_CLR - Clear bit: Write 1 to clear LEDC_OVF_CNT_CH2_INT. - 14 - 1 - write-only - - - OVF_CNT_CH3_INT_CLR - Clear bit: Write 1 to clear LEDC_OVF_CNT_CH3_INT. - 15 - 1 - write-only - - - OVF_CNT_CH4_INT_CLR - Clear bit: Write 1 to clear LEDC_OVF_CNT_CH4_INT. - 16 - 1 - write-only - - - OVF_CNT_CH5_INT_CLR - Clear bit: Write 1 to clear LEDC_OVF_CNT_CH5_INT. - 17 - 1 - write-only - - - OVF_CNT_CH6_INT_CLR - Clear bit: Write 1 to clear LEDC_OVF_CNT_CH6_INT. - 18 - 1 - write-only - - - OVF_CNT_CH7_INT_CLR - Clear bit: Write 1 to clear LEDC_OVF_CNT_CH7_INT. - 19 - 1 - write-only - - - - - 8 - 0x4 - CH%s_GAMMA_CONF - Ledc ch%s gamma config register. - 0x100 - 0x20 - - - CH_GAMMA_ENTRY_NUM - Configures the number of duty cycle fading rages for LEDC ch%s. - 0 - 5 - read-write - - - CH_GAMMA_PAUSE - Configures whether or not to pause duty cycle fading of LEDC ch%s.\\0: Invalid. No effect\\1: Pause - 5 - 1 - write-only - - - CH_GAMMA_RESUME - Configures whether or nor to resume duty cycle fading of LEDC ch%s.\\0: Invalid. No effect\\1: Resume - 6 - 1 - write-only - - - - - EVT_TASK_EN0 - Ledc event task enable bit register0. - 0x120 - 0x20 - - - EVT_DUTY_CHNG_END_CH0_EN - Configures whether or not to enable the ledc_ch0_duty_chng_end event.\\0: Disable\\1: Enable - 0 - 1 - read-write - - - EVT_DUTY_CHNG_END_CH1_EN - Configures whether or not to enable the ledc_ch1_duty_chng_end event.\\0: Disable\\1: Enable - 1 - 1 - read-write - - - EVT_DUTY_CHNG_END_CH2_EN - Configures whether or not to enable the ledc_ch2_duty_chng_end event.\\0: Disable\\1: Enable - 2 - 1 - read-write - - - EVT_DUTY_CHNG_END_CH3_EN - Configures whether or not to enable the ledc_ch3_duty_chng_end event.\\0: Disable\\1: Enable - 3 - 1 - read-write - - - EVT_DUTY_CHNG_END_CH4_EN - Configures whether or not to enable the ledc_ch4_duty_chng_end event.\\0: Disable\\1: Enable - 4 - 1 - read-write - - - EVT_DUTY_CHNG_END_CH5_EN - Configures whether or not to enable the ledc_ch5_duty_chng_end event.\\0: Disable\\1: Enable - 5 - 1 - read-write - - - EVT_DUTY_CHNG_END_CH6_EN - Configures whether or not to enable the ledc_ch6_duty_chng_end event.\\0: Disable\\1: Enable - 6 - 1 - read-write - - - EVT_DUTY_CHNG_END_CH7_EN - Configures whether or not to enable the ledc_ch7_duty_chng_end event.\\0: Disable\\1: Enable - 7 - 1 - read-write - - - EVT_OVF_CNT_PLS_CH0_EN - Configures whether or not to enable the ledc_ch0_ovf_cnt_pls event.\\0: Disable\\1: Enable - 8 - 1 - read-write - - - EVT_OVF_CNT_PLS_CH1_EN - Configures whether or not to enable the ledc_ch1_ovf_cnt_pls event.\\0: Disable\\1: Enable - 9 - 1 - read-write - - - EVT_OVF_CNT_PLS_CH2_EN - Configures whether or not to enable the ledc_ch2_ovf_cnt_pls event.\\0: Disable\\1: Enable - 10 - 1 - read-write - - - EVT_OVF_CNT_PLS_CH3_EN - Configures whether or not to enable the ledc_ch3_ovf_cnt_pls event.\\0: Disable\\1: Enable - 11 - 1 - read-write - - - EVT_OVF_CNT_PLS_CH4_EN - Configures whether or not to enable the ledc_ch4_ovf_cnt_pls event.\\0: Disable\\1: Enable - 12 - 1 - read-write - - - EVT_OVF_CNT_PLS_CH5_EN - Configures whether or not to enable the ledc_ch5_ovf_cnt_pls event.\\0: Disable\\1: Enable - 13 - 1 - read-write - - - EVT_OVF_CNT_PLS_CH6_EN - Configures whether or not to enable the ledc_ch6_ovf_cnt_pls event.\\0: Disable\\1: Enable - 14 - 1 - read-write - - - EVT_OVF_CNT_PLS_CH7_EN - Configures whether or not to enable the ledc_ch7_ovf_cnt_pls event.\\0: Disable\\1: Enable - 15 - 1 - read-write - - - EVT_TIME_OVF_TIMER0_EN - Configures whether or not to enable the ledc_timer0_ovf event.\\0: Disable\\1: Enable - 16 - 1 - read-write - - - EVT_TIME_OVF_TIMER1_EN - Configures whether or not to enable the ledc_timer1_ovf event.\\0: Disable\\1: Enable - 17 - 1 - read-write - - - EVT_TIME_OVF_TIMER2_EN - Configures whether or not to enable the ledc_timer2_ovf event.\\0: Disable\\1: Enable - 18 - 1 - read-write - - - EVT_TIME_OVF_TIMER3_EN - Configures whether or not to enable the ledc_timer3_ovf event.\\0: Disable\\1: Enable - 19 - 1 - read-write - - - EVT_TIME0_CMP_EN - Configures whether or not to enable the ledc_timer0_cmp event.\\0: Disable\\1: Enable - 20 - 1 - read-write - - - EVT_TIME1_CMP_EN - Configures whether or not to enable the ledc_timer1_cmp event.\\0: Disable\\1: Enable - 21 - 1 - read-write - - - EVT_TIME2_CMP_EN - Configures whether or not to enable the ledc_timer2_cmp event.\\0: Disable\\1: Enable - 22 - 1 - read-write - - - EVT_TIME3_CMP_EN - Configures whether or not to enable the ledc_timer3_cmp event.\\0: Disable\\1: Enable - 23 - 1 - read-write - - - TASK_DUTY_SCALE_UPDATE_CH0_EN - Configures whether or not to enable the ledc_ch0_duty_scale_update task.\\0: Disable\\1: Enable - 24 - 1 - read-write - - - TASK_DUTY_SCALE_UPDATE_CH1_EN - Configures whether or not to enable the ledc_ch1_duty_scale_update task.\\0: Disable\\1: Enable - 25 - 1 - read-write - - - TASK_DUTY_SCALE_UPDATE_CH2_EN - Configures whether or not to enable the ledc_ch2_duty_scale_update task.\\0: Disable\\1: Enable - 26 - 1 - read-write - - - TASK_DUTY_SCALE_UPDATE_CH3_EN - Configures whether or not to enable the ledc_ch3_duty_scale_update task.\\0: Disable\\1: Enable - 27 - 1 - read-write - - - TASK_DUTY_SCALE_UPDATE_CH4_EN - Configures whether or not to enable the ledc_ch4_duty_scale_update task.\\0: Disable\\1: Enable - 28 - 1 - read-write - - - TASK_DUTY_SCALE_UPDATE_CH5_EN - Configures whether or not to enable the ledc_ch5_duty_scale_update task.\\0: Disable\\1: Enable - 29 - 1 - read-write - - - TASK_DUTY_SCALE_UPDATE_CH6_EN - Configures whether or not to enable the ledc_ch6_duty_scale_update task.\\0: Disable\\1: Enable - 30 - 1 - read-write - - - TASK_DUTY_SCALE_UPDATE_CH7_EN - Configures whether or not to enable the ledc_ch7_duty_scale_update task.\\0: Disable\\1: Enable - 31 - 1 - read-write - - - - - EVT_TASK_EN1 - Ledc event task enable bit register1. - 0x124 - 0x20 - - - TASK_TIMER0_RES_UPDATE_EN - Configures whether or not to enable ledc_timer0_res_update task.\\0: Disable\\1: Enable - 0 - 1 - read-write - - - TASK_TIMER1_RES_UPDATE_EN - Configures whether or not to enable ledc_timer1_res_update task.\\0: Disable\\1: Enable - 1 - 1 - read-write - - - TASK_TIMER2_RES_UPDATE_EN - Configures whether or not to enable ledc_timer2_res_update task.\\0: Disable\\1: Enable - 2 - 1 - read-write - - - TASK_TIMER3_RES_UPDATE_EN - Configures whether or not to enable ledc_timer3_res_update task.\\0: Disable\\1: Enable - 3 - 1 - read-write - - - TASK_TIMER0_CAP_EN - Configures whether or not to enable ledc_timer0_cap task.\\0: Disable\\1: Enable - 4 - 1 - read-write - - - TASK_TIMER1_CAP_EN - Configures whether or not to enable ledc_timer1_cap task.\\0: Disable\\1: Enable - 5 - 1 - read-write - - - TASK_TIMER2_CAP_EN - Configures whether or not to enable ledc_timer2_cap task.\\0: Disable\\1: Enable - 6 - 1 - read-write - - - TASK_TIMER3_CAP_EN - Configures whether or not to enable ledc_timer3_cap task.\\0: Disable\\1: Enable - 7 - 1 - read-write - - - TASK_SIG_OUT_DIS_CH0_EN - Configures whether or not to enable ledc_ch0_sig_out_dis task.\\0: Disable\\1: Enable - 8 - 1 - read-write - - - TASK_SIG_OUT_DIS_CH1_EN - Configures whether or not to enable ledc_ch1_sig_out_dis task.\\0: Disable\\1: Enable - 9 - 1 - read-write - - - TASK_SIG_OUT_DIS_CH2_EN - Configures whether or not to enable ledc_ch2_sig_out_dis task.\\0: Disable\\1: Enable - 10 - 1 - read-write - - - TASK_SIG_OUT_DIS_CH3_EN - Configures whether or not to enable ledc_ch3_sig_out_dis task.\\0: Disable\\1: Enable - 11 - 1 - read-write - - - TASK_SIG_OUT_DIS_CH4_EN - Configures whether or not to enable ledc_ch4_sig_out_dis task.\\0: Disable\\1: Enable - 12 - 1 - read-write - - - TASK_SIG_OUT_DIS_CH5_EN - Configures whether or not to enable ledc_ch5_sig_out_dis task.\\0: Disable\\1: Enable - 13 - 1 - read-write - - - TASK_SIG_OUT_DIS_CH6_EN - Configures whether or not to enable ledc_ch6_sig_out_dis task.\\0: Disable\\1: Enable - 14 - 1 - read-write - - - TASK_SIG_OUT_DIS_CH7_EN - Configures whether or not to enable ledc_ch7_sig_out_dis task.\\0: Disable\\1: Enable - 15 - 1 - read-write - - - TASK_OVF_CNT_RST_CH0_EN - Configures whether or not to enable ledc_ch0_ovf_cnt_rst task.\\0: Disable\\1: Enable - 16 - 1 - read-write - - - TASK_OVF_CNT_RST_CH1_EN - Configures whether or not to enable ledc_ch1_ovf_cnt_rst task.\\0: Disable\\1: Enable - 17 - 1 - read-write - - - TASK_OVF_CNT_RST_CH2_EN - Configures whether or not to enable ledc_ch2_ovf_cnt_rst task.\\0: Disable\\1: Enable - 18 - 1 - read-write - - - TASK_OVF_CNT_RST_CH3_EN - Configures whether or not to enable ledc_ch3_ovf_cnt_rst task.\\0: Disable\\1: Enable - 19 - 1 - read-write - - - TASK_OVF_CNT_RST_CH4_EN - Configures whether or not to enable ledc_ch4_ovf_cnt_rst task.\\0: Disable\\1: Enable - 20 - 1 - read-write - - - TASK_OVF_CNT_RST_CH5_EN - Configures whether or not to enable ledc_ch5_ovf_cnt_rst task.\\0: Disable\\1: Enable - 21 - 1 - read-write - - - TASK_OVF_CNT_RST_CH6_EN - Configures whether or not to enable ledc_ch6_ovf_cnt_rst task.\\0: Disable\\1: Enable - 22 - 1 - read-write - - - TASK_OVF_CNT_RST_CH7_EN - Configures whether or not to enable ledc_ch7_ovf_cnt_rst task.\\0: Disable\\1: Enable - 23 - 1 - read-write - - - TASK_TIMER0_RST_EN - Configures whether or not to enable ledc_timer0_rst task.\\0: Disable\\1: Enable - 24 - 1 - read-write - - - TASK_TIMER1_RST_EN - Configures whether or not to enable ledc_timer1_rst task.\\0: Disable\\1: Enable - 25 - 1 - read-write - - - TASK_TIMER2_RST_EN - Configures whether or not to enable ledc_timer2_rst task.\\0: Disable\\1: Enable - 26 - 1 - read-write - - - TASK_TIMER3_RST_EN - Configures whether or not to enable ledc_timer3_rst task.\\0: Disable\\1: Enable - 27 - 1 - read-write - - - TASK_TIMER0_PAUSE_RESUME_EN - Configures whether or not to enable ledc_timer0_pause_resume task.\\0: Disable\\1: Enable - 28 - 1 - read-write - - - TASK_TIMER1_PAUSE_RESUME_EN - Configures whether or not to enable ledc_timer1_pause_resume task.\\0: Disable\\1: Enable - 29 - 1 - read-write - - - TASK_TIMER2_PAUSE_RESUME_EN - Configures whether or not to enable ledc_timer2_pause_resume task.\\0: Disable\\1: Enable - 30 - 1 - read-write - - - TASK_TIMER3_PAUSE_RESUME_EN - Configures whether or not to enable ledc_timer3_pause_resume task.\\0: Disable\\1: Enable - 31 - 1 - read-write - - - - - EVT_TASK_EN2 - Ledc event task enable bit register2. - 0x128 - 0x20 - - - TASK_GAMMA_RESTART_CH0_EN - Configures whether or not to enable ledc_ch0_gamma_restart task.\\0: Disable\\1: Enable - 0 - 1 - read-write - - - TASK_GAMMA_RESTART_CH1_EN - Configures whether or not to enable ledc_ch1_gamma_restart task.\\0: Disable\\1: Enable - 1 - 1 - read-write - - - TASK_GAMMA_RESTART_CH2_EN - Configures whether or not to enable ledc_ch2_gamma_restart task.\\0: Disable\\1: Enable - 2 - 1 - read-write - - - TASK_GAMMA_RESTART_CH3_EN - Configures whether or not to enable ledc_ch3_gamma_restart task.\\0: Disable\\1: Enable - 3 - 1 - read-write - - - TASK_GAMMA_RESTART_CH4_EN - Configures whether or not to enable ledc_ch4_gamma_restart task.\\0: Disable\\1: Enable - 4 - 1 - read-write - - - TASK_GAMMA_RESTART_CH5_EN - Configures whether or not to enable ledc_ch5_gamma_restart task.\\0: Disable\\1: Enable - 5 - 1 - read-write - - - TASK_GAMMA_RESTART_CH6_EN - Configures whether or not to enable ledc_ch6_gamma_restart task.\\0: Disable\\1: Enable - 6 - 1 - read-write - - - TASK_GAMMA_RESTART_CH7_EN - Configures whether or not to enable ledc_ch7_gamma_restart task.\\0: Disable\\1: Enable - 7 - 1 - read-write - - - TASK_GAMMA_PAUSE_CH0_EN - Configures whether or not to enable ledc_ch0_gamma_pause task.\\0: Disable\\1: Enable - 8 - 1 - read-write - - - TASK_GAMMA_PAUSE_CH1_EN - Configures whether or not to enable ledc_ch1_gamma_pause task.\\0: Disable\\1: Enable - 9 - 1 - read-write - - - TASK_GAMMA_PAUSE_CH2_EN - Configures whether or not to enable ledc_ch2_gamma_pause task.\\0: Disable\\1: Enable - 10 - 1 - read-write - - - TASK_GAMMA_PAUSE_CH3_EN - Configures whether or not to enable ledc_ch3_gamma_pause task.\\0: Disable\\1: Enable - 11 - 1 - read-write - - - TASK_GAMMA_PAUSE_CH4_EN - Configures whether or not to enable ledc_ch4_gamma_pause task.\\0: Disable\\1: Enable - 12 - 1 - read-write - - - TASK_GAMMA_PAUSE_CH5_EN - Configures whether or not to enable ledc_ch5_gamma_pause task.\\0: Disable\\1: Enable - 13 - 1 - read-write - - - TASK_GAMMA_PAUSE_CH6_EN - Configures whether or not to enable ledc_ch6_gamma_pause task.\\0: Disable\\1: Enable - 14 - 1 - read-write - - - TASK_GAMMA_PAUSE_CH7_EN - Configures whether or not to enable ledc_ch7_gamma_pause task.\\0: Disable\\1: Enable - 15 - 1 - read-write - - - TASK_GAMMA_RESUME_CH0_EN - Configures whether or not to enable ledc_ch0_gamma_resume task.\\0: Disable\\1: Enable - 16 - 1 - read-write - - - TASK_GAMMA_RESUME_CH1_EN - Configures whether or not to enable ledc_ch1_gamma_resume task.\\0: Disable\\1: Enable - 17 - 1 - read-write - - - TASK_GAMMA_RESUME_CH2_EN - Configures whether or not to enable ledc_ch2_gamma_resume task.\\0: Disable\\1: Enable - 18 - 1 - read-write - - - TASK_GAMMA_RESUME_CH3_EN - Configures whether or not to enable ledc_ch3_gamma_resume task.\\0: Disable\\1: Enable - 19 - 1 - read-write - - - TASK_GAMMA_RESUME_CH4_EN - Configures whether or not to enable ledc_ch4_gamma_resume task.\\0: Disable\\1: Enable - 20 - 1 - read-write - - - TASK_GAMMA_RESUME_CH5_EN - Configures whether or not to enable ledc_ch5_gamma_resume task.\\0: Disable\\1: Enable - 21 - 1 - read-write - - - TASK_GAMMA_RESUME_CH6_EN - Configures whether or not to enable ledc_ch6_gamma_resume task.\\0: Disable\\1: Enable - 22 - 1 - read-write - - - TASK_GAMMA_RESUME_CH7_EN - Configures whether or not to enable ledc_ch7_gamma_resume task.\\0: Disable\\1: Enable - 23 - 1 - read-write - - - - - 4 - 0x4 - TIMER%s_CMP - Ledc timer%s compare value register. - 0x140 - 0x20 - - - TIMER_CMP - Configures the comparison value for LEDC timer%s. - 0 - 20 - read-write - - - - - 4 - 0x4 - TIMER%s_CNT_CAP - Ledc timer%s captured count value register. - 0x150 - 0x20 - - - TIMER_CNT_CAP - Represents the captured LEDC timer%s count value. - 0 - 20 - read-only - - - - - CONF - LEDC global configuration register - 0x170 - 0x20 - - - APB_CLK_SEL - Configures the clock source for the four timers.\\0: APB_CLK\\1: RC_FAST_CLK\\2: XTAL_CLK\\3: Invalid. No clock - 0 - 2 - read-write - - - GAMMA_RAM_CLK_EN_CH0 - Configures whether or not to open LEDC ch0 gamma ram clock gate.\\0: Open the clock gate only when application writes or reads LEDC ch0 gamma ram\\1: Force open the clock gate for LEDC ch0 gamma ram - 2 - 1 - read-write - - - GAMMA_RAM_CLK_EN_CH1 - Configures whether or not to open LEDC ch1 gamma ram clock gate.\\0: Open the clock gate only when application writes or reads LEDC ch1 gamma ram\\1: Force open the clock gate for LEDC ch1 gamma ram - 3 - 1 - read-write - - - GAMMA_RAM_CLK_EN_CH2 - Configures whether or not to open LEDC ch2 gamma ram clock gate.\\0: Open the clock gate only when application writes or reads LEDC ch2 gamma ram\\1: Force open the clock gate for LEDC ch2 gamma ram - 4 - 1 - read-write - - - GAMMA_RAM_CLK_EN_CH3 - Configures whether or not to open LEDC ch3 gamma ram clock gate.\\0: Open the clock gate only when application writes or reads LEDC ch3 gamma ram\\1: Force open the clock gate for LEDC ch3 gamma ram - 5 - 1 - read-write - - - GAMMA_RAM_CLK_EN_CH4 - Configures whether or not to open LEDC ch4 gamma ram clock gate.\\0: Open the clock gate only when application writes or reads LEDC ch4 gamma ram\\1: Force open the clock gate for LEDC ch4 gamma ram - 6 - 1 - read-write - - - GAMMA_RAM_CLK_EN_CH5 - Configures whether or not to open LEDC ch5 gamma ram clock gate.\\0: Open the clock gate only when application writes or reads LEDC ch5 gamma ram\\1: Force open the clock gate for LEDC ch5 gamma ram - 7 - 1 - read-write - - - GAMMA_RAM_CLK_EN_CH6 - Configures whether or not to open LEDC ch6 gamma ram clock gate.\\0: Open the clock gate only when application writes or reads LEDC ch6 gamma ram\\1: Force open the clock gate for LEDC ch6 gamma ram - 8 - 1 - read-write - - - GAMMA_RAM_CLK_EN_CH7 - Configures whether or not to open LEDC ch7 gamma ram clock gate.\\0: Open the clock gate only when application writes or reads LEDC ch7 gamma ram\\1: Force open the clock gate for LEDC ch7 gamma ram - 9 - 1 - read-write - - - CLK_EN - Configures whether or not to open register clock gate.\\0: Open the clock gate only when application writes registers\\1: Force open the clock gate for register - 31 - 1 - read-write - - - - - DATE - Version control register - 0x174 - 0x20 - 0x02303070 - - - LEDC_DATE - Configures the version. - 0 - 28 - read-write - - - - - - - LP_INTR - Low-power Interrupt Controller - LPINTR - 0x5012C000 - - 0x0 - 0x18 - registers - - - - SW_INT_RAW - need_des - 0x0 - 0x20 - - - LP_SW_INT_RAW - need_des - 31 - 1 - read-write - - - - - SW_INT_ST - need_des - 0x4 - 0x20 - - - LP_SW_INT_ST - need_des - 31 - 1 - read-only - - - - - SW_INT_ENA - need_des - 0x8 - 0x20 - - - LP_SW_INT_ENA - need_des - 31 - 1 - read-write - - - - - SW_INT_CLR - need_des - 0xC - 0x20 - - - LP_SW_INT_CLR - need_des - 31 - 1 - write-only - - - - - STATUS - need_des - 0x10 - 0x20 - - - LP_HUK_INTR_ST - need_des - 10 - 1 - read-only - - - SYSREG_INTR_ST - need_des - 11 - 1 - read-only - - - LP_SW_INTR_ST - need_des - 12 - 1 - read-only - - - LP_EFUSE_INTR_ST - need_des - 13 - 1 - read-only - - - LP_UART_INTR_ST - need_des - 14 - 1 - read-only - - - LP_TSENS_INTR_ST - need_des - 15 - 1 - read-only - - - LP_TOUCH_INTR_ST - need_des - 16 - 1 - read-only - - - LP_SPI_INTR_ST - need_des - 17 - 1 - read-only - - - LP_I2S_INTR_ST - need_des - 18 - 1 - read-only - - - LP_I2C_INTR_ST - need_des - 19 - 1 - read-only - - - LP_GPIO_INTR_ST - need_des - 20 - 1 - read-only - - - LP_ADC_INTR_ST - need_des - 21 - 1 - read-only - - - ANAPERI_INTR_ST - need_des - 22 - 1 - read-only - - - PMU_REG_1_INTR_ST - need_des - 23 - 1 - read-only - - - PMU_REG_0_INTR_ST - need_des - 24 - 1 - read-only - - - MB_LP_INTR_ST - need_des - 25 - 1 - read-only - - - MB_HP_INTR_ST - need_des - 26 - 1 - read-only - - - LP_TIMER_REG_1_INTR_ST - need_des - 27 - 1 - read-only - - - LP_TIMER_REG_0_INTR_ST - need_des - 28 - 1 - read-only - - - LP_WDT_INTR_ST - need_des - 29 - 1 - read-only - - - LP_RTC_INTR_ST - need_des - 30 - 1 - read-only - - - HP_INTR_ST - need_des - 31 - 1 - read-only - - - - - DATE - need_des - 0x3FC - 0x20 - - - CLK_EN - need_des - 31 - 1 - read-write - - - - - - - LP_PERI - LP_PERI Peripheral - LPPERI - 0x50120000 - - 0x0 - 0x2C - registers - - - - CLK_EN - need_des - 0x0 - 0x20 - 0x7FFF0000 - - - CK_EN_RNG - need_des - 16 - 1 - read-write - - - CK_EN_LP_TSENS - need_des - 17 - 1 - read-write - - - CK_EN_LP_PMS - need_des - 18 - 1 - read-write - - - CK_EN_LP_EFUSE - need_des - 19 - 1 - read-write - - - CK_EN_LP_IOMUX - need_des - 20 - 1 - read-write - - - CK_EN_LP_TOUCH - need_des - 21 - 1 - read-write - - - CK_EN_LP_SPI - need_des - 22 - 1 - read-write - - - CK_EN_LP_ADC - need_des - 23 - 1 - read-write - - - CK_EN_LP_I2S_TX - need_des - 24 - 1 - read-write - - - CK_EN_LP_I2S_RX - need_des - 25 - 1 - read-write - - - CK_EN_LP_I2S - need_des - 26 - 1 - read-write - - - CK_EN_LP_I2CMST - need_des - 27 - 1 - read-write - - - CK_EN_LP_I2C - need_des - 28 - 1 - read-write - - - CK_EN_LP_UART - need_des - 29 - 1 - read-write - - - CK_EN_LP_INTR - need_des - 30 - 1 - read-write - - - CK_EN_LP_CORE - write 1 to force on lp_core clk - 31 - 1 - read-write - - - - - CORE_CLK_SEL - need_des - 0x4 - 0x20 - - - LP_I2S_TX_CLK_SEL - need_des - 24 - 2 - read-write - - - LP_I2S_RX_CLK_SEL - need_des - 26 - 2 - read-write - - - LP_I2C_CLK_SEL - need_des - 28 - 2 - read-write - - - LP_UART_CLK_SEL - need_des - 30 - 2 - read-write - - - - - RESET_EN - need_des - 0x8 - 0x20 - - - RST_EN_LP_TSENS - need_des - 18 - 1 - read-write - - - RST_EN_LP_PMS - need_des - 19 - 1 - read-write - - - RST_EN_LP_EFUSE - need_des - 20 - 1 - read-write - - - RST_EN_LP_IOMUX - need_des - 21 - 1 - read-write - - - RST_EN_LP_TOUCH - need_des - 22 - 1 - read-write - - - RST_EN_LP_SPI - need_des - 23 - 1 - read-write - - - RST_EN_LP_ADC - need_des - 24 - 1 - read-write - - - RST_EN_LP_I2S - need_des - 25 - 1 - read-write - - - RST_EN_LP_I2CMST - need_des - 26 - 1 - read-write - - - RST_EN_LP_I2C - need_des - 27 - 1 - read-write - - - RST_EN_LP_UART - need_des - 28 - 1 - read-write - - - RST_EN_LP_INTR - need_des - 29 - 1 - read-write - - - RST_EN_LP_ROM - need_des - 30 - 1 - read-write - - - RST_EN_LP_CORE - need_des - 31 - 1 - write-only - - - - - CPU - need_des - 0xC - 0x20 - 0x80000000 - - - LPCORE_DBGM_UNAVAILABLE - need_des - 31 - 1 - read-write - - - - - MEM_CTRL - need_des - 0x28 - 0x20 - 0x80000000 - - - LP_UART_WAKEUP_FLAG_CLR - need_des - 0 - 1 - write-only - - - LP_UART_WAKEUP_FLAG - need_des - 1 - 1 - read-write - - - LP_UART_WAKEUP_EN - need_des - 29 - 1 - read-write - - - LP_UART_MEM_FORCE_PD - need_des - 30 - 1 - read-write - - - LP_UART_MEM_FORCE_PU - need_des - 31 - 1 - read-write - - - - - ADC_CTRL - need_des - 0x2C - 0x20 - 0x04040400 - - - SAR2_CLK_FORCE_ON - need_des - 6 - 1 - read-write - - - SAR1_CLK_FORCE_ON - need_des - 7 - 1 - read-write - - - LPADC_FUNC_DIV_NUM - need_des - 8 - 8 - read-write - - - LPADC_SAR2_DIV_NUM - need_des - 16 - 8 - read-write - - - LPADC_SAR1_DIV_NUM - need_des - 24 - 8 - read-write - - - - - LP_I2S_RXCLK_DIV_NUM - need_des - 0x30 - 0x20 - 0x02000000 - - - LP_I2S_RX_CLKM_DIV_NUM - need_des - 24 - 8 - read-write - - - - - LP_I2S_RXCLK_DIV_XYZ - need_des - 0x34 - 0x20 - 0x00004000 - - - LP_I2S_RX_CLKM_DIV_YN1 - need_des - 4 - 1 - read-write - - - LP_I2S_RX_CLKM_DIV_Z - need_des - 5 - 9 - read-write - - - LP_I2S_RX_CLKM_DIV_Y - need_des - 14 - 9 - read-write - - - LP_I2S_RX_CLKM_DIV_X - need_des - 23 - 9 - read-write - - - - - LP_I2S_TXCLK_DIV_NUM - need_des - 0x38 - 0x20 - 0x02000000 - - - LP_I2S_TX_CLKM_DIV_NUM - need_des - 24 - 8 - read-write - - - - - LP_I2S_TXCLK_DIV_XYZ - need_des - 0x3C - 0x20 - 0x00004000 - - - LP_I2S_TX_CLKM_DIV_YN1 - need_des - 4 - 1 - read-write - - - LP_I2S_TX_CLKM_DIV_Z - need_des - 5 - 9 - read-write - - - LP_I2S_TX_CLKM_DIV_Y - need_des - 14 - 9 - read-write - - - LP_I2S_TX_CLKM_DIV_X - need_des - 23 - 9 - read-write - - - - - DATE - need_des - 0x3FC - 0x20 - - - CLK_EN - need_des - 31 - 1 - read-write - - - - - - - LP_SYS - LP_SYS Peripheral - LPSYSREG - 0x50110000 - - 0x0 - 0x110 - registers - - - LP_SYS - 19 - - - - LP_SYS_VER_DATE - need_des - 0x0 - 0x20 - 0x20230509 - - - VER_DATE - need_des - 0 - 32 - read-write - - - - - CLK_SEL_CTRL - need_des - 0x4 - 0x20 - - - ENA_SW_SEL_SYS_CLK - reserved - 16 - 1 - read-write - - - SW_SYS_CLK_SRC_SEL - reserved - 17 - 1 - read-write - - - - - SYS_CTRL - need_des - 0x8 - 0x20 - 0x1FFFC7F8 - - - LP_CORE_DISABLE - lp cpu disable - 0 - 1 - read-write - - - SYS_SW_RST - digital system software reset bit - 1 - 1 - write-only - - - FORCE_DOWNLOAD_BOOT - need_des - 2 - 1 - read-write - - - DIG_FIB - need_des - 3 - 8 - read-write - - - IO_MUX_RESET_DISABLE - reset disable bit for LP IOMUX - 11 - 1 - read-write - - - ANA_FIB - need_des - 14 - 7 - read-only - - - LP_FIB_SEL - need_des - 21 - 8 - read-write - - - LP_CORE_ETM_WAKEUP_FLAG_CLR - need_des - 29 - 1 - write-only - - - LP_CORE_ETM_WAKEUP_FLAG - need_des - 30 - 1 - read-write - - - SYSTIMER_STALL_SEL - 0: use systimer_stall signal from hp_core0, 1: use systimer_stall signal from hp_core1 - 31 - 1 - read-write - - - - - LP_CLK_CTRL - need_des - 0xC - 0x20 - 0x00004001 - - - CLK_EN - need_des - 0 - 1 - read-write - - - LP_FOSC_HP_CKEN - reserved - 14 - 1 - read-write - - - - - LP_RST_CTRL - need_des - 0x10 - 0x20 - 0x00000003 - - - ANA_RST_BYPASS - analog source reset bypass : wdt,brown out,super wdt,glitch - 0 - 1 - read-write - - - SYS_RST_BYPASS - system source reset bypass : software reset,hp wdt,lp wdt,efuse - 1 - 1 - read-write - - - EFUSE_FORCE_NORST - efuse force no reset control - 2 - 1 - read-write - - - - - LP_CORE_BOOT_ADDR - need_des - 0x18 - 0x20 - 0x50100000 - - - LP_CPU_BOOT_ADDR - need_des - 0 - 32 - read-write - - - - - EXT_WAKEUP1 - need_des - 0x1C - 0x20 - - - SEL - Bitmap to select RTC pads for ext wakeup1 - 0 - 16 - read-write - - - STATUS_CLR - clear ext wakeup1 status - 16 - 1 - write-only - - - - - EXT_WAKEUP1_STATUS - need_des - 0x20 - 0x20 - - - EXT_WAKEUP1_STATUS - ext wakeup1 status - 0 - 16 - read-only - - - - - LP_TCM_PWR_CTRL - need_des - 0x24 - 0x20 - - - LP_TCM_ROM_CLK_FORCE_ON - need_des - 5 - 1 - read-write - - - LP_TCM_RAM_CLK_FORCE_ON - need_des - 7 - 1 - read-write - - - - - BOOT_ADDR_HP_LP - need_des - 0x28 - 0x20 - - - BOOT_ADDR_HP_LP - need_des - 0 - 32 - read-write - - - - - LP_STORE0 - need_des - 0x2C - 0x20 - - - LP_SCRATCH0 - need_des - 0 - 32 - read-write - - - - - LP_STORE1 - need_des - 0x30 - 0x20 - - - LP_SCRATCH1 - need_des - 0 - 32 - read-write - - - - - LP_STORE2 - need_des - 0x34 - 0x20 - - - LP_SCRATCH2 - need_des - 0 - 32 - read-write - - - - - LP_STORE3 - need_des - 0x38 - 0x20 - - - LP_SCRATCH3 - need_des - 0 - 32 - read-write - - - - - LP_STORE4 - need_des - 0x3C - 0x20 - - - LP_SCRATCH4 - need_des - 0 - 32 - read-write - - - - - LP_STORE5 - need_des - 0x40 - 0x20 - - - LP_SCRATCH5 - need_des - 0 - 32 - read-write - - - - - LP_STORE6 - need_des - 0x44 - 0x20 - - - LP_SCRATCH6 - need_des - 0 - 32 - read-write - - - - - LP_STORE7 - need_des - 0x48 - 0x20 - - - LP_SCRATCH7 - need_des - 0 - 32 - read-write - - - - - LP_STORE8 - need_des - 0x4C - 0x20 - - - LP_SCRATCH8 - need_des - 0 - 32 - read-write - - - - - LP_STORE9 - need_des - 0x50 - 0x20 - - - LP_SCRATCH9 - need_des - 0 - 32 - read-write - - - - - LP_STORE10 - need_des - 0x54 - 0x20 - - - LP_SCRATCH10 - need_des - 0 - 32 - read-write - - - - - LP_STORE11 - need_des - 0x58 - 0x20 - - - LP_SCRATCH11 - need_des - 0 - 32 - read-write - - - - - LP_STORE12 - need_des - 0x5C - 0x20 - - - LP_SCRATCH12 - need_des - 0 - 32 - read-write - - - - - LP_STORE13 - need_des - 0x60 - 0x20 - - - LP_SCRATCH13 - need_des - 0 - 32 - read-write - - - - - LP_STORE14 - need_des - 0x64 - 0x20 - - - LP_SCRATCH14 - need_des - 0 - 32 - read-write - - - - - LP_STORE15 - need_des - 0x68 - 0x20 - - - LP_SCRATCH15 - need_des - 0 - 32 - read-write - - - - - LP_PROBEA_CTRL - need_des - 0x6C - 0x20 - - - PROBE_A_MOD_SEL - need_des - 0 - 16 - read-write - - - PROBE_A_TOP_SEL - need_des - 16 - 8 - read-write - - - PROBE_L_SEL - need_des - 24 - 2 - read-write - - - PROBE_H_SEL - need_des - 26 - 2 - read-write - - - PROBE_GLOBAL_EN - need_des - 28 - 1 - read-write - - - - - LP_PROBEB_CTRL - need_des - 0x70 - 0x20 - - - PROBE_B_MOD_SEL - need_des - 0 - 16 - read-write - - - PROBE_B_TOP_SEL - need_des - 16 - 8 - read-write - - - PROBE_B_EN - need_des - 24 - 1 - read-write - - - - - LP_PROBE_OUT - need_des - 0x74 - 0x20 - - - PROBE_TOP_OUT - need_des - 0 - 32 - read-only - - - - - F2S_APB_BRG_CNTL - need_des - 0x9C - 0x20 - - - F2S_APB_POSTW_EN - reserved - 0 - 1 - read-write - - - - - USB_CTRL - need_des - 0x100 - 0x20 - - - SW_HW_USB_PHY_SEL - need_des - 0 - 1 - read-write - - - SW_USB_PHY_SEL - need_des - 1 - 1 - read-write - - - USBOTG20_WAKEUP_CLR - clear usb wakeup to PMU. - 2 - 1 - write-only - - - USBOTG20_IN_SUSPEND - indicate usb otg2.0 is in suspend state. - 3 - 1 - read-write - - - - - ANA_XPD_PAD_GROUP - need_des - 0x10C - 0x20 - 0x000000FF - - - ANA_REG_XPD_PAD_GROUP - Set 1 to power up pad group - 0 - 8 - read-write - - - - - LP_TCM_RAM_RDN_ECO_CS - need_des - 0x110 - 0x20 - - - LP_TCM_RAM_RDN_ECO_EN - need_des - 0 - 1 - read-write - - - LP_TCM_RAM_RDN_ECO_RESULT - need_des - 1 - 1 - read-only - - - - - LP_TCM_RAM_RDN_ECO_LOW - need_des - 0x114 - 0x20 - - - LP_TCM_RAM_RDN_ECO_LOW - need_des - 0 - 32 - read-write - - - - - LP_TCM_RAM_RDN_ECO_HIGH - need_des - 0x118 - 0x20 - 0xFFFFFFFF - - - LP_TCM_RAM_RDN_ECO_HIGH - need_des - 0 - 32 - read-write - - - - - LP_TCM_ROM_RDN_ECO_CS - need_des - 0x11C - 0x20 - - - LP_TCM_ROM_RDN_ECO_EN - need_des - 0 - 1 - read-write - - - LP_TCM_ROM_RDN_ECO_RESULT - need_des - 1 - 1 - read-only - - - - - LP_TCM_ROM_RDN_ECO_LOW - need_des - 0x120 - 0x20 - - - LP_TCM_ROM_RDN_ECO_LOW - need_des - 0 - 32 - read-write - - - - - LP_TCM_ROM_RDN_ECO_HIGH - need_des - 0x124 - 0x20 - 0xFFFFFFFF - - - LP_TCM_ROM_RDN_ECO_HIGH - need_des - 0 - 32 - read-write - - - - - HP_ROOT_CLK_CTRL - need_des - 0x130 - 0x20 - 0x00000003 - - - CPU_CLK_EN - clock gate enable for hp cpu root 400M clk - 0 - 1 - read-write - - - SYS_CLK_EN - clock gate enable for hp sys root 480M clk - 1 - 1 - read-write - - - - - LP_PMU_RDN_ECO_LOW - need_des - 0x138 - 0x20 - - - PMU_RDN_ECO_LOW - need_des - 0 - 32 - read-write - - - - - LP_PMU_RDN_ECO_HIGH - need_des - 0x13C - 0x20 - 0xFFFFFFFF - - - PMU_RDN_ECO_HIGH - need_des - 0 - 32 - read-write - - - - - PAD_COMP0 - need_des - 0x148 - 0x20 - - - DREF_COMP0 - pad comp dref - 0 - 3 - read-write - - - MODE_COMP0 - pad comp mode - 3 - 1 - read-write - - - XPD_COMP0 - pad comp xpd - 4 - 1 - read-write - - - - - PAD_COMP1 - need_des - 0x14C - 0x20 - - - DREF_COMP1 - pad comp dref - 0 - 3 - read-write - - - MODE_COMP1 - pad comp mode - 3 - 1 - read-write - - - XPD_COMP1 - pad comp xpd - 4 - 1 - read-write - - - - - BACKUP_DMA_CFG0 - need_des - 0x154 - 0x20 - 0x1906414A - - - BURST_LIMIT_AON - need_des - 0 - 5 - read-write - - - READ_INTERVAL_AON - need_des - 5 - 7 - read-write - - - LINK_BACKUP_TOUT_THRES_AON - need_des - 12 - 10 - read-write - - - LINK_TOUT_THRES_AON - need_des - 22 - 10 - read-write - - - - - BACKUP_DMA_CFG1 - need_des - 0x158 - 0x20 - - - AON_BYPASS - need_des - 31 - 1 - read-write - - - - - BACKUP_DMA_CFG2 - need_des - 0x15C - 0x20 - - - LINK_ADDR_AON - need_des - 0 - 32 - read-write - - - - - BOOT_ADDR_HP_CORE1 - need_des - 0x164 - 0x20 - - - BOOT_ADDR_HP_CORE1 - need_des - 0 - 32 - read-write - - - - - LP_ADDRHOLE_ADDR - need_des - 0x168 - 0x20 - - - LP_ADDRHOLE_ADDR - need_des - 0 - 32 - read-only - - - - - LP_ADDRHOLE_INFO - need_des - 0x16C - 0x20 - - - LP_ADDRHOLE_ID - master id: 5'h0: hp core0, 5'h1:hp core1, 5'h2:lp core, 5'h3:usb otg11, 5'h4: regdma, 5'h5: gmac, 5'h5 sdmmc, 5'h7: usbotg20, 5'h8: trace0, 5'h9: trace1, 5'ha tcm monitor, 5'hb: l2mem monitor. 5'h10~5'h1f: ahb pdma. - 0 - 5 - read-only - - - LP_ADDRHOLE_WR - 1:write trans, 0: read trans. - 5 - 1 - read-only - - - LP_ADDRHOLE_SECURE - 1: illegal address access, 0: access without permission - 6 - 1 - read-only - - - - - INT_RAW - raw interrupt register - 0x170 - 0x20 - - - LP_ADDRHOLE_INT_RAW - the raw interrupt status of lp addrhole(for lp peri and lp ram tee apm, and lp matrix default slave) - 0 - 1 - read-only - - - IDBUS_ADDRHOLE_INT_RAW - the raw interrupt status of idbus addrhole(only for lp cpu ibus and dbus) - 1 - 1 - read-only - - - LP_CORE_AHB_TIMEOUT_INT_RAW - the raw interrupt status of lp core ahb bus timeout - 2 - 1 - read-only - - - LP_CORE_IBUS_TIMEOUT_INT_RAW - the raw interrupt status of lp core ibus timeout - 3 - 1 - read-only - - - LP_CORE_DBUS_TIMEOUT_INT_RAW - the raw interrupt status of lp core dbus timeout - 4 - 1 - read-only - - - ETM_TASK_ULP_INT_RAW - the raw interrupt status of etm task ulp - 5 - 1 - read-only - - - SLOW_CLK_TICK_INT_RAW - the raw interrupt status of slow_clk_tick - 6 - 1 - read-only - - - - - INT_ST - masked interrupt register - 0x174 - 0x20 - - - LP_ADDRHOLE_INT_ST - the masked interrupt status of lp addrhole (for lp peri and lp ram tee apm, and lp matrix default slave) - 0 - 1 - read-only - - - IDBUS_ADDRHOLE_INT_ST - the masked interrupt status of idbus addrhole(only for lp cpu ibus and dbus) - 1 - 1 - read-only - - - LP_CORE_AHB_TIMEOUT_INT_ST - the masked interrupt status of lp core ahb bus timeout - 2 - 1 - read-only - - - LP_CORE_IBUS_TIMEOUT_INT_ST - the masked interrupt status of lp core ibus timeout - 3 - 1 - read-only - - - LP_CORE_DBUS_TIMEOUT_INT_ST - the masked interrupt status of lp core dbus timeout - 4 - 1 - read-only - - - ETM_TASK_ULP_INT_ST - the masked interrupt status of etm task ulp - 5 - 1 - read-only - - - SLOW_CLK_TICK_INT_ST - the masked interrupt status of slow_clk_tick - 6 - 1 - read-only - - - - - INT_ENA - masked interrupt register - 0x178 - 0x20 - - - LP_ADDRHOLE_INT_ENA - Write 1 to enable lp addrhole int - 0 - 1 - read-write - - - IDBUS_ADDRHOLE_INT_ENA - Write 1 to enable idbus addrhole int - 1 - 1 - read-write - - - LP_CORE_AHB_TIMEOUT_INT_ENA - Write 1 to enable lp_core_ahb_timeout int - 2 - 1 - read-write - - - LP_CORE_IBUS_TIMEOUT_INT_ENA - Write 1 to enable lp_core_ibus_timeout int - 3 - 1 - read-write - - - LP_CORE_DBUS_TIMEOUT_INT_ENA - Write 1 to enable lp_core_dbus_timeout int - 4 - 1 - read-write - - - ETM_TASK_ULP_INT_ENA - Write 1 to enable etm task ulp int - 5 - 1 - read-write - - - SLOW_CLK_TICK_INT_ENA - Write 1 to enable slow_clk_tick int - 6 - 1 - read-write - - - - - INT_CLR - interrupt clear register - 0x17C - 0x20 - - - LP_ADDRHOLE_INT_CLR - write 1 to clear lp addrhole int - 0 - 1 - write-only - - - IDBUS_ADDRHOLE_INT_CLR - write 1 to clear idbus addrhole int - 1 - 1 - write-only - - - LP_CORE_AHB_TIMEOUT_INT_CLR - Write 1 to clear lp_core_ahb_timeout int - 2 - 1 - write-only - - - LP_CORE_IBUS_TIMEOUT_INT_CLR - Write 1 to clear lp_core_ibus_timeout int - 3 - 1 - write-only - - - LP_CORE_DBUS_TIMEOUT_INT_CLR - Write 1 to clear lp_core_dbus_timeout int - 4 - 1 - write-only - - - ETM_TASK_ULP_INT_CLR - Write 1 to clear etm tasl ulp int - 5 - 1 - write-only - - - SLOW_CLK_TICK_INT_CLR - Write 1 to clear slow_clk_tick int - 6 - 1 - write-only - - - - - HP_MEM_AUX_CTRL - need_des - 0x180 - 0x20 - 0x00002070 - - - HP_MEM_AUX_CTRL - need_des - 0 - 32 - read-write - - - - - LP_MEM_AUX_CTRL - need_des - 0x184 - 0x20 - 0x00002070 - - - LP_MEM_AUX_CTRL - need_des - 0 - 32 - read-write - - - - - HP_ROM_AUX_CTRL - need_des - 0x188 - 0x20 - 0x00000070 - - - HP_ROM_AUX_CTRL - need_des - 0 - 32 - read-write - - - - - LP_ROM_AUX_CTRL - need_des - 0x18C - 0x20 - 0x00000070 - - - LP_ROM_AUX_CTRL - need_des - 0 - 32 - read-write - - - - - LP_CPU_DBG_PC - need_des - 0x190 - 0x20 - - - LP_CPU_DBG_PC - need_des - 0 - 32 - read-only - - - - - LP_CPU_EXC_PC - need_des - 0x194 - 0x20 - - - LP_CPU_EXC_PC - need_des - 0 - 32 - read-only - - - - - IDBUS_ADDRHOLE_ADDR - need_des - 0x198 - 0x20 - - - IDBUS_ADDRHOLE_ADDR - need_des - 0 - 32 - read-only - - - - - IDBUS_ADDRHOLE_INFO - need_des - 0x19C - 0x20 - - - IDBUS_ADDRHOLE_ID - need_des - 0 - 5 - read-only - - - IDBUS_ADDRHOLE_WR - need_des - 5 - 1 - read-only - - - IDBUS_ADDRHOLE_SECURE - need_des - 6 - 1 - read-only - - - - - HP_POR_RST_BYPASS_CTRL - need_des - 0x1A0 - 0x20 - 0xFF00FF00 - - - HP_PO_CNNT_RSTN_BYPASS_CTRL - [15] 1'b1: po_cnnt_rstn bypass sys_sw_rstn -[14] 1'b1: po_cnnt_rstn bypass hp_wdt_sys_rstn -[13] 1'b1: po_cnnt_rstn bypass hp_cpu_intrusion_rstn -[12] 1'b1: po_cnnt_rstn bypass hp_sdio_sys_rstn -[11] 1'b1: po_cnnt_rstn bypass usb_jtag_chip_rst -[10] 1'b1: po_cnnt_rstn bypass usb_uart_chip_rst -[9] 1'b1: po_cnnt_rstn bypass lp_wdt_hp_sys_rstn -[8] 1'b1: po_cnnt_rstn bypass efuse_err_rstn - 8 - 8 - read-write - - - HP_PO_RSTN_BYPASS_CTRL - [31] 1'b1: po_rstn bypass sys_sw_rstn -[30] 1'b1: po_rstn bypass hp_wdt_sys_rstn -[29] 1'b1: po_rstn bypass hp_cpu_intrusion_rstn -[28] 1'b1: po_rstn bypass hp_sdio_sys_rstn -[27] 1'b1: po_rstn bypass usb_jtag_chip_rst -[26] 1'b1: po_rstn bypass usb_uart_chip_rst -[25] 1'b1: po_rstn bypass lp_wdt_hp_sys_rstn -[24] 1'b1: po_rstn bypass efuse_err_rstn - 24 - 8 - read-write - - - - - RNG_DATA - rng data register - 0x1A4 - 0x20 - - - RND_DATA - result of rng output - 0 - 32 - read-only - - - - - LP_CORE_AHB_TIMEOUT - need_des - 0x1B0 - 0x20 - 0x007FFFFF - - - EN - set this field to 1 to enable lp core ahb timeout handle - 0 - 1 - read-write - - - THRES - This field used to set lp core ahb bus timeout threshold - 1 - 16 - read-write - - - LP2HP_AHB_TIMEOUT_EN - set this field to 1 to enable lp2hp ahb timeout handle - 17 - 1 - read-write - - - LP2HP_AHB_TIMEOUT_THRES - This field used to set lp2hp ahb bus timeout threshold - 18 - 5 - read-write - - - - - LP_CORE_IBUS_TIMEOUT - need_des - 0x1B4 - 0x20 - 0x0001FFFF - - - EN - set this field to 1 to enable lp core ibus timeout handle - 0 - 1 - read-write - - - THRES - This field used to set lp core ibus timeout threshold - 1 - 16 - read-write - - - - - LP_CORE_DBUS_TIMEOUT - need_des - 0x1B8 - 0x20 - 0x0001FFFF - - - EN - set this field to 1 to enable lp core dbus timeout handle - 0 - 1 - read-write - - - THRES - This field used to set lp core dbus timeout threshold - 1 - 16 - read-write - - - - - LP_CORE_ERR_RESP_DIS - need_des - 0x1BC - 0x20 - - - LP_CORE_ERR_RESP_DIS - Set bit0 to disable ibus err resp;Set bit1 to disable dbus err resp; Set bit 2 to disable ahb err resp. - 0 - 3 - read-write - - - - - RNG_CFG - rng cfg register - 0x1C0 - 0x20 - 0x00000003 - - - RNG_TIMER_EN - enable rng timer - 0 - 1 - read-write - - - RNG_TIMER_PSCALE - configure ng timer pscale - 1 - 8 - read-write - - - RNG_SAR_ENABLE - enable rng_saradc - 9 - 1 - read-write - - - RNG_SAR_DATA - debug rng sar sample cnt - 16 - 13 - read-only - - - - - - - LP_ANA_PERI - LP_ANA_PERI Peripheral - LP_ANA_PERI - 0x50113000 - - 0x0 - 0x140 - registers - - - LP_ANA - 8 - - - - LP_ANA_BOD_MODE0_CNTL - need_des - 0x0 - 0x20 - 0x0FFC0100 - - - LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA - need_des - 6 - 1 - read-write - - - LP_ANA_BOD_MODE0_PD_RF_ENA - need_des - 7 - 1 - read-write - - - LP_ANA_BOD_MODE0_INTR_WAIT - need_des - 8 - 10 - read-write - - - LP_ANA_BOD_MODE0_RESET_WAIT - need_des - 18 - 10 - read-write - - - LP_ANA_BOD_MODE0_CNT_CLR - need_des - 28 - 1 - read-write - - - LP_ANA_BOD_MODE0_INTR_ENA - need_des - 29 - 1 - read-write - - - LP_ANA_BOD_MODE0_RESET_SEL - need_des - 30 - 1 - read-write - - - LP_ANA_BOD_MODE0_RESET_ENA - need_des - 31 - 1 - read-write - - - - - LP_ANA_BOD_MODE1_CNTL - need_des - 0x4 - 0x20 - - - LP_ANA_BOD_MODE1_RESET_ENA - need_des - 31 - 1 - read-write - - - - - LP_ANA_VDD_SOURCE_CNTL - need_des - 0x8 - 0x20 - 0x040000FF - - - LP_ANA_DETMODE_SEL - need_des - 0 - 8 - read-write - - - LP_ANA_VGOOD_EVENT_RECORD - need_des - 8 - 8 - read-only - - - LP_ANA_VBAT_EVENT_RECORD_CLR - need_des - 16 - 8 - write-only - - - LP_ANA_BOD_SOURCE_ENA - need_des - 24 - 8 - read-write - - - - - LP_ANA_VDDBAT_BOD_CNTL - need_des - 0xC - 0x20 - 0xFFC00000 - - - LP_ANA_VDDBAT_UNDERVOLTAGE_FLAG - need_des - 0 - 1 - read-only - - - LP_ANA_VDDBAT_CHARGER - need_des - 10 - 1 - read-write - - - LP_ANA_VDDBAT_CNT_CLR - need_des - 11 - 1 - read-write - - - LP_ANA_VDDBAT_UPVOLTAGE_TARGET - need_des - 12 - 10 - read-write - - - LP_ANA_VDDBAT_UNDERVOLTAGE_TARGET - need_des - 22 - 10 - read-write - - - - - LP_ANA_VDDBAT_CHARGE_CNTL - need_des - 0x10 - 0x20 - 0xFFC00000 - - - LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG - need_des - 0 - 1 - read-only - - - LP_ANA_VDDBAT_CHARGE_CHARGER - need_des - 10 - 1 - read-write - - - LP_ANA_VDDBAT_CHARGE_CNT_CLR - need_des - 11 - 1 - read-write - - - LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_TARGET - need_des - 12 - 10 - read-write - - - LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET - need_des - 22 - 10 - read-write - - - - - LP_ANA_CK_GLITCH_CNTL - need_des - 0x14 - 0x20 - - - LP_ANA_CK_GLITCH_RESET_ENA - need_des - 31 - 1 - read-write - - - - - LP_ANA_PG_GLITCH_CNTL - need_des - 0x18 - 0x20 - - - LP_ANA_POWER_GLITCH_RESET_ENA - need_des - 31 - 1 - read-write - - - - - LP_ANA_FIB_ENABLE - need_des - 0x1C - 0x20 - 0xFFFFFFFF - - - LP_ANA_ANA_FIB_ENA - need_des - 0 - 32 - read-write - - - - - LP_ANA_INT_RAW - need_des - 0x20 - 0x20 - - - LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW - need_des - 27 - 1 - read-write - - - LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW - need_des - 28 - 1 - read-write - - - LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW - need_des - 29 - 1 - read-write - - - LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW - need_des - 30 - 1 - read-write - - - LP_ANA_BOD_MODE0_INT_RAW - need_des - 31 - 1 - read-write - - - - - LP_ANA_INT_ST - need_des - 0x24 - 0x20 - - - LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ST - need_des - 27 - 1 - read-only - - - LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST - need_des - 28 - 1 - read-only - - - LP_ANA_VDDBAT_UPVOLTAGE_INT_ST - need_des - 29 - 1 - read-only - - - LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ST - need_des - 30 - 1 - read-only - - - LP_ANA_BOD_MODE0_INT_ST - need_des - 31 - 1 - read-only - - - - - LP_ANA_INT_ENA - need_des - 0x28 - 0x20 - - - LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA - need_des - 27 - 1 - read-write - - - LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA - need_des - 28 - 1 - read-write - - - LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA - need_des - 29 - 1 - read-write - - - LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA - need_des - 30 - 1 - read-write - - - LP_ANA_BOD_MODE0_INT_ENA - need_des - 31 - 1 - read-write - - - - - LP_ANA_INT_CLR - need_des - 0x2C - 0x20 - - - LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR - need_des - 27 - 1 - write-only - - - LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR - need_des - 28 - 1 - write-only - - - LP_ANA_VDDBAT_UPVOLTAGE_INT_CLR - need_des - 29 - 1 - write-only - - - LP_ANA_VDDBAT_UNDERVOLTAGE_INT_CLR - need_des - 30 - 1 - write-only - - - LP_ANA_BOD_MODE0_INT_CLR - need_des - 31 - 1 - write-only - - - - - LP_ANA_LP_INT_RAW - need_des - 0x30 - 0x20 - - - LP_ANA_BOD_MODE0_LP_INT_RAW - need_des - 31 - 1 - read-write - - - - - LP_ANA_LP_INT_ST - need_des - 0x34 - 0x20 - - - LP_ANA_BOD_MODE0_LP_INT_ST - need_des - 31 - 1 - read-only - - - - - LP_ANA_LP_INT_ENA - need_des - 0x38 - 0x20 - - - LP_ANA_BOD_MODE0_LP_INT_ENA - need_des - 31 - 1 - read-write - - - - - LP_ANA_LP_INT_CLR - need_des - 0x3C - 0x20 - - - LP_ANA_BOD_MODE0_LP_INT_CLR - need_des - 31 - 1 - write-only - - - - - LP_ANA_TOUCH_APPROACH_WORK_MEAS_NUM - need_des - 0xFC - 0x20 - 0x06419064 - - - LP_ANA_TOUCH_APPROACH_MEAS_NUM2 - need_des - 0 - 10 - read-write - - - LP_ANA_TOUCH_APPROACH_MEAS_NUM1 - need_des - 10 - 10 - read-write - - - LP_ANA_TOUCH_APPROACH_MEAS_NUM0 - need_des - 20 - 10 - read-write - - - - - LP_ANA_TOUCH_SCAN_CTRL1 - need_des - 0x100 - 0x20 - 0x00080000 - - - LP_ANA_TOUCH_SHIELD_PAD_EN - need_des - 0 - 1 - read-write - - - LP_ANA_TOUCH_INACTIVE_CONNECTION - need_des - 1 - 1 - read-write - - - LP_ANA_TOUCH_SCAN_PAD_MAP - need_des - 2 - 15 - read-write - - - LP_ANA_TOUCH_XPD_WAIT - need_des - 17 - 15 - read-write - - - - - LP_ANA_TOUCH_SCAN_CTRL2 - need_des - 0x104 - 0x20 - 0x37BFFFC0 - - - LP_ANA_TOUCH_TIMEOUT_NUM - need_des - 6 - 16 - read-write - - - LP_ANA_TOUCH_TIMEOUT_EN - need_des - 22 - 1 - read-write - - - LP_ANA_TOUCH_OUT_RING - need_des - 23 - 4 - read-write - - - LP_ANA_FREQ_SCAN_EN - need_des - 27 - 1 - read-write - - - LP_ANA_FREQ_SCAN_CNT_LIMIT - need_des - 28 - 2 - read-write - - - - - LP_ANA_TOUCH_WORK - need_des - 0x108 - 0x20 - - - LP_ANA_DIV_NUM2 - need_des - 16 - 3 - read-write - - - LP_ANA_DIV_NUM1 - need_des - 19 - 3 - read-write - - - LP_ANA_DIV_NUM0 - need_des - 22 - 3 - read-write - - - LP_ANA_TOUCH_OUT_SEL - need_des - 25 - 1 - read-write - - - LP_ANA_TOUCH_OUT_RESET - need_des - 26 - 1 - write-only - - - LP_ANA_TOUCH_OUT_GATE - need_des - 27 - 1 - read-write - - - - - LP_ANA_TOUCH_WORK_MEAS_NUM - need_des - 0x10C - 0x20 - 0x06419064 - - - LP_ANA_TOUCH_MEAS_NUM2 - need_des - 0 - 10 - read-write - - - LP_ANA_TOUCH_MEAS_NUM1 - need_des - 10 - 10 - read-write - - - LP_ANA_TOUCH_MEAS_NUM0 - need_des - 20 - 10 - read-write - - - - - LP_ANA_TOUCH_FILTER1 - need_des - 0x110 - 0x20 - 0x6A0A0200 - - - LP_ANA_TOUCH_NEG_NOISE_DISUPDATE_BASELINE_EN - Reserved - 0 - 1 - read-write - - - LP_ANA_TOUCH_HYSTERESIS - need_des - 1 - 2 - read-write - - - LP_ANA_TOUCH_NEG_NOISE_THRES - need_des - 3 - 2 - read-write - - - LP_ANA_TOUCH_NOISE_THRES - need_des - 5 - 2 - read-write - - - LP_ANA_TOUCH_SMOOTH_LVL - need_des - 7 - 2 - read-write - - - LP_ANA_TOUCH_JITTER_STEP - need_des - 9 - 4 - read-write - - - LP_ANA_TOUCH_FILTER_MODE - need_des - 13 - 3 - read-write - - - LP_ANA_TOUCH_FILTER_EN - need_des - 16 - 1 - read-write - - - LP_ANA_TOUCH_NEG_NOISE_LIMIT - need_des - 17 - 4 - read-write - - - LP_ANA_TOUCH_APPROACH_LIMIT - need_des - 21 - 8 - read-write - - - LP_ANA_TOUCH_DEBOUNCE_LIMIT - need_des - 29 - 3 - read-write - - - - - LP_ANA_TOUCH_FILTER2 - need_des - 0x114 - 0x20 - 0x1FFF8000 - - - LP_ANA_TOUCH_OUTEN - need_des - 15 - 15 - read-write - - - LP_ANA_TOUCH_BYPASS_NOISE_THRES - need_des - 30 - 1 - read-write - - - LP_ANA_TOUCH_BYPASS_NEG_NOISE_THRES - need_des - 31 - 1 - read-write - - - - - LP_ANA_TOUCH_FILTER3 - need_des - 0x118 - 0x20 - - - LP_ANA_TOUCH_BASELINE_SW - need_des - 0 - 16 - read-write - - - LP_ANA_TOUCH_UPDATE_BASELINE_SW - need_des - 16 - 1 - write-only - - - - - LP_ANA_TOUCH_SLP0 - need_des - 0x11C - 0x20 - 0x001E0000 - - - LP_ANA_TOUCH_SLP_TH0 - need_des - 0 - 16 - read-write - - - LP_ANA_TOUCH_SLP_CHANNEL_CLR - need_des - 16 - 1 - write-only - - - LP_ANA_TOUCH_SLP_PAD - need_des - 17 - 4 - read-write - - - - - LP_ANA_TOUCH_SLP1 - need_des - 0x120 - 0x20 - - - LP_ANA_TOUCH_SLP_TH2 - need_des - 0 - 16 - read-write - - - LP_ANA_TOUCH_SLP_TH1 - need_des - 16 - 16 - read-write - - - - - LP_ANA_TOUCH_CLR - need_des - 0x124 - 0x20 - - - LP_ANA_TOUCH_CHANNEL_CLR - need_des - 0 - 15 - write-only - - - LP_ANA_TOUCH_STATUS_CLR - need_des - 15 - 1 - write-only - - - - - LP_ANA_TOUCH_APPROACH - need_des - 0x128 - 0x20 - 0x00000FFF - - - PAD0 - need_des - 0 - 4 - read-write - - - PAD1 - need_des - 4 - 4 - read-write - - - PAD2 - need_des - 8 - 4 - read-write - - - LP_ANA_TOUCH_SLP_APPROACH_EN - need_des - 12 - 1 - read-write - - - - - LP_ANA_TOUCH_FREQ0_SCAN_PARA - need_des - 0x12C - 0x20 - - - LP_ANA_TOUCH_FREQ0_DCAP_LPF - need_des - 0 - 7 - read-write - - - LP_ANA_TOUCH_FREQ0_DRES_LPF - need_des - 7 - 2 - read-write - - - LP_ANA_TOUCH_FREQ0_DRV_LS - need_des - 9 - 4 - read-write - - - LP_ANA_TOUCH_FREQ0_DRV_HS - need_des - 13 - 5 - read-write - - - LP_ANA_TOUCH_FREQ0_DBIAS - need_des - 18 - 5 - read-write - - - - - LP_ANA_TOUCH_FREQ1_SCAN_PARA - need_des - 0x130 - 0x20 - - - LP_ANA_TOUCH_FREQ1_DCAP_LPF - need_des - 0 - 7 - read-write - - - LP_ANA_TOUCH_FREQ1_DRES_LPF - need_des - 7 - 2 - read-write - - - LP_ANA_TOUCH_FREQ1_DRV_LS - need_des - 9 - 4 - read-write - - - LP_ANA_TOUCH_FREQ1_DRV_HS - need_des - 13 - 5 - read-write - - - LP_ANA_TOUCH_FREQ1_DBIAS - need_des - 18 - 5 - read-write - - - - - LP_ANA_TOUCH_FREQ2_SCAN_PARA - need_des - 0x134 - 0x20 - - - LP_ANA_TOUCH_FREQ2_DCAP_LPF - need_des - 0 - 7 - read-write - - - LP_ANA_TOUCH_FREQ2_DRES_LPF - need_des - 7 - 2 - read-write - - - LP_ANA_TOUCH_FREQ2_DRV_LS - need_des - 9 - 4 - read-write - - - LP_ANA_TOUCH_FREQ2_DRV_HS - need_des - 13 - 5 - read-write - - - LP_ANA_TOUCH_FREQ2_DBIAS - need_des - 18 - 5 - read-write - - - - - LP_ANA_TOUCH_ANA_PARA - need_des - 0x138 - 0x20 - - - LP_ANA_TOUCH_TOUCH_BUF_DRV - need_des - 0 - 3 - read-write - - - LP_ANA_TOUCH_TOUCH_EN_CAL - need_des - 3 - 1 - read-write - - - LP_ANA_TOUCH_TOUCH_DCAP_CAL - need_des - 4 - 7 - read-write - - - - - LP_ANA_TOUCH_MUX0 - need_des - 0x13C - 0x20 - 0x20000000 - - - LP_ANA_TOUCH_DATA_SEL - need_des - 8 - 2 - read-write - - - LP_ANA_TOUCH_FREQ_SEL - need_des - 10 - 2 - read-write - - - LP_ANA_TOUCH_BUFSEL - need_des - 12 - 15 - read-write - - - LP_ANA_TOUCH_DONE_EN - need_des - 27 - 1 - read-write - - - LP_ANA_TOUCH_DONE_FORCE - need_des - 28 - 1 - read-write - - - LP_ANA_TOUCH_FSM_EN - need_des - 29 - 1 - read-write - - - LP_ANA_TOUCH_START_EN - need_des - 30 - 1 - read-write - - - LP_ANA_TOUCH_START_FORCE - need_des - 31 - 1 - read-write - - - - - LP_ANA_TOUCH_MUX1 - need_des - 0x140 - 0x20 - - - LP_ANA_TOUCH_START - need_des - 0 - 15 - read-write - - - LP_ANA_TOUCH_XPD - need_des - 15 - 15 - read-write - - - - - LP_ANA_TOUCH_PAD0_TH0 - need_des - 0x144 - 0x20 - - - LP_ANA_TOUCH_PAD0_TH0 - Reserved - 16 - 16 - read-write - - - - - LP_ANA_TOUCH_PAD0_TH1 - need_des - 0x148 - 0x20 - - - LP_ANA_TOUCH_PAD0_TH1 - Reserved - 16 - 16 - read-write - - - - - LP_ANA_TOUCH_PAD0_TH2 - need_des - 0x14C - 0x20 - - - LP_ANA_TOUCH_PAD0_TH2 - Reserved - 16 - 16 - read-write - - - - - LP_ANA_TOUCH_PAD1_TH0 - need_des - 0x150 - 0x20 - - - LP_ANA_TOUCH_PAD1_TH0 - Reserved - 16 - 16 - read-write - - - - - LP_ANA_TOUCH_PAD1_TH1 - need_des - 0x154 - 0x20 - - - LP_ANA_TOUCH_PAD1_TH1 - Reserved - 16 - 16 - read-write - - - - - LP_ANA_TOUCH_PAD1_TH2 - need_des - 0x158 - 0x20 - - - LP_ANA_TOUCH_PAD1_TH2 - Reserved - 16 - 16 - read-write - - - - - LP_ANA_TOUCH_PAD2_TH0 - need_des - 0x15C - 0x20 - - - LP_ANA_TOUCH_PAD2_TH0 - Reserved - 16 - 16 - read-write - - - - - LP_ANA_TOUCH_PAD2_TH1 - need_des - 0x160 - 0x20 - - - LP_ANA_TOUCH_PAD2_TH1 - Reserved - 16 - 16 - read-write - - - - - LP_ANA_TOUCH_PAD2_TH2 - need_des - 0x164 - 0x20 - - - LP_ANA_TOUCH_PAD2_TH2 - Reserved - 16 - 16 - read-write - - - - - LP_ANA_TOUCH_PAD3_TH0 - need_des - 0x168 - 0x20 - - - LP_ANA_TOUCH_PAD3_TH0 - Reserved - 16 - 16 - read-write - - - - - LP_ANA_TOUCH_PAD3_TH1 - need_des - 0x16C - 0x20 - - - LP_ANA_TOUCH_PAD3_TH1 - Reserved - 16 - 16 - read-write - - - - - LP_ANA_TOUCH_PAD3_TH2 - need_des - 0x170 - 0x20 - - - LP_ANA_TOUCH_PAD3_TH2 - Reserved - 16 - 16 - read-write - - - - - LP_ANA_TOUCH_PAD4_TH0 - need_des - 0x174 - 0x20 - - - LP_ANA_TOUCH_PAD4_TH0 - Reserved - 16 - 16 - read-write - - - - - LP_ANA_TOUCH_PAD4_TH1 - need_des - 0x178 - 0x20 - - - LP_ANA_TOUCH_PAD4_TH1 - Reserved - 16 - 16 - read-write - - - - - LP_ANA_TOUCH_PAD4_TH2 - need_des - 0x17C - 0x20 - - - LP_ANA_TOUCH_PAD4_TH2 - Reserved - 16 - 16 - read-write - - - - - LP_ANA_TOUCH_PAD5_TH0 - need_des - 0x180 - 0x20 - - - LP_ANA_TOUCH_PAD5_TH0 - Reserved - 16 - 16 - read-write - - - - - LP_ANA_TOUCH_PAD5_TH1 - need_des - 0x184 - 0x20 - - - LP_ANA_TOUCH_PAD5_TH1 - Reserved - 16 - 16 - read-write - - - - - LP_ANA_TOUCH_PAD5_TH2 - need_des - 0x188 - 0x20 - - - LP_ANA_TOUCH_PAD5_TH2 - Reserved - 16 - 16 - read-write - - - - - LP_ANA_TOUCH_PAD6_TH0 - need_des - 0x18C - 0x20 - - - LP_ANA_TOUCH_PAD6_TH0 - Reserved - 16 - 16 - read-write - - - - - LP_ANA_TOUCH_PAD6_TH1 - need_des - 0x190 - 0x20 - - - LP_ANA_TOUCH_PAD6_TH1 - Reserved - 16 - 16 - read-write - - - - - LP_ANA_TOUCH_PAD6_TH2 - need_des - 0x194 - 0x20 - - - LP_ANA_TOUCH_PAD6_TH2 - Reserved - 16 - 16 - read-write - - - - - LP_ANA_TOUCH_PAD7_TH0 - need_des - 0x198 - 0x20 - - - LP_ANA_TOUCH_PAD7_TH0 - Reserved - 16 - 16 - read-write - - - - - LP_ANA_TOUCH_PAD7_TH1 - need_des - 0x19C - 0x20 - - - LP_ANA_TOUCH_PAD7_TH1 - Reserved - 16 - 16 - read-write - - - - - LP_ANA_TOUCH_PAD7_TH2 - need_des - 0x1A0 - 0x20 - - - LP_ANA_TOUCH_PAD7_TH2 - Reserved - 16 - 16 - read-write - - - - - LP_ANA_TOUCH_PAD8_TH0 - need_des - 0x1A4 - 0x20 - - - LP_ANA_TOUCH_PAD8_TH0 - Reserved - 16 - 16 - read-write - - - - - LP_ANA_TOUCH_PAD8_TH1 - need_des - 0x1A8 - 0x20 - - - LP_ANA_TOUCH_PAD8_TH1 - Reserved - 16 - 16 - read-write - - - - - LP_ANA_TOUCH_PAD8_TH2 - need_des - 0x1AC - 0x20 - - - LP_ANA_TOUCH_PAD8_TH2 - Reserved - 16 - 16 - read-write - - - - - LP_ANA_TOUCH_PAD9_TH0 - need_des - 0x1B0 - 0x20 - - - LP_ANA_TOUCH_PAD9_TH0 - Reserved - 16 - 16 - read-write - - - - - LP_ANA_TOUCH_PAD9_TH1 - need_des - 0x1B4 - 0x20 - - - LP_ANA_TOUCH_PAD9_TH1 - Reserved - 16 - 16 - read-write - - - - - LP_ANA_TOUCH_PAD9_TH2 - need_des - 0x1B8 - 0x20 - - - LP_ANA_TOUCH_PAD9_TH2 - Reserved - 16 - 16 - read-write - - - - - LP_ANA_TOUCH_PAD10_TH0 - need_des - 0x1BC - 0x20 - - - LP_ANA_TOUCH_PAD10_TH0 - Reserved - 16 - 16 - read-write - - - - - LP_ANA_TOUCH_PAD10_TH1 - need_des - 0x1C0 - 0x20 - - - LP_ANA_TOUCH_PAD10_TH1 - Reserved - 16 - 16 - read-write - - - - - LP_ANA_TOUCH_PAD10_TH2 - need_des - 0x1C4 - 0x20 - - - LP_ANA_TOUCH_PAD10_TH2 - Reserved - 16 - 16 - read-write - - - - - LP_ANA_TOUCH_PAD11_TH0 - need_des - 0x1C8 - 0x20 - - - LP_ANA_TOUCH_PAD11_TH0 - Reserved - 16 - 16 - read-write - - - - - LP_ANA_TOUCH_PAD11_TH1 - need_des - 0x1CC - 0x20 - - - LP_ANA_TOUCH_PAD11_TH1 - Reserved - 16 - 16 - read-write - - - - - LP_ANA_TOUCH_PAD11_TH2 - need_des - 0x1D0 - 0x20 - - - LP_ANA_TOUCH_PAD11_TH2 - Reserved - 16 - 16 - read-write - - - - - LP_ANA_TOUCH_PAD12_TH0 - need_des - 0x1D4 - 0x20 - - - LP_ANA_TOUCH_PAD12_TH0 - Reserved - 16 - 16 - read-write - - - - - LP_ANA_TOUCH_PAD12_TH1 - need_des - 0x1D8 - 0x20 - - - LP_ANA_TOUCH_PAD12_TH1 - Reserved - 16 - 16 - read-write - - - - - LP_ANA_TOUCH_PAD12_TH2 - need_des - 0x1DC - 0x20 - - - LP_ANA_TOUCH_PAD12_TH2 - Reserved - 16 - 16 - read-write - - - - - LP_ANA_TOUCH_PAD13_TH0 - need_des - 0x1E0 - 0x20 - - - LP_ANA_TOUCH_PAD13_TH0 - Reserved - 16 - 16 - read-write - - - - - LP_ANA_TOUCH_PAD13_TH1 - need_des - 0x1E4 - 0x20 - - - LP_ANA_TOUCH_PAD13_TH1 - Reserved - 16 - 16 - read-write - - - - - LP_ANA_TOUCH_PAD13_TH2 - need_des - 0x1E8 - 0x20 - - - LP_ANA_TOUCH_PAD13_TH2 - Reserved - 16 - 16 - read-write - - - - - LP_ANA_TOUCH_PAD14_TH0 - need_des - 0x1EC - 0x20 - - - LP_ANA_TOUCH_PAD14_TH0 - Reserved - 16 - 16 - read-write - - - - - LP_ANA_TOUCH_PAD14_TH1 - need_des - 0x1F0 - 0x20 - - - LP_ANA_TOUCH_PAD14_TH1 - Reserved - 16 - 16 - read-write - - - - - LP_ANA_TOUCH_PAD14_TH2 - need_des - 0x1F4 - 0x20 - - - LP_ANA_TOUCH_PAD14_TH2 - Reserved - 16 - 16 - read-write - - - - - LP_ANA_DATE - need_des - 0x3FC - 0x20 - 0x00230420 - - - LP_ANA_LP_ANA_DATE - need_des - 0 - 31 - read-write - - - LP_ANA_CLK_EN - need_des - 31 - 1 - read-write - - - - - - - LP_AON_CLKRST - LP_AON_CLKRST Peripheral - LP_AON_CLKRST - 0x50111000 - - 0x0 - 0x54 - registers - - - - LP_AONCLKRST_LP_CLK_CONF - need_des - 0x0 - 0x20 - 0x00000004 - - - LP_AONCLKRST_SLOW_CLK_SEL - need_des - 0 - 2 - read-write - - - LP_AONCLKRST_FAST_CLK_SEL - need_des - 2 - 2 - read-write - - - LP_AONCLKRST_LP_PERI_DIV_NUM - need_des - 4 - 6 - read-write - - - LP_AONCLKRST_ANA_SEL_REF_PLL8M - need_des - 10 - 1 - read-write - - - - - LP_AONCLKRST_LP_CLK_PO_EN - need_des - 0x4 - 0x20 - - - LP_AONCLKRST_CLK_CORE_EFUSE_OEN - need_des - 0 - 1 - read-write - - - LP_AONCLKRST_CLK_LP_BUS_OEN - need_des - 1 - 1 - read-write - - - LP_AONCLKRST_CLK_AON_SLOW_OEN - need_des - 2 - 1 - read-write - - - LP_AONCLKRST_CLK_AON_FAST_OEN - need_des - 3 - 1 - read-write - - - LP_AONCLKRST_CLK_SLOW_OEN - need_des - 4 - 1 - read-write - - - LP_AONCLKRST_CLK_FAST_OEN - need_des - 5 - 1 - read-write - - - LP_AONCLKRST_CLK_FOSC_OEN - need_des - 6 - 1 - read-write - - - LP_AONCLKRST_CLK_RC32K_OEN - need_des - 7 - 1 - read-write - - - LP_AONCLKRST_CLK_SXTAL_OEN - need_des - 8 - 1 - read-write - - - LP_AONCLKRST_CLK_SOSC_OEN - 1'b1: probe sosc clk on -1'b0: probe sosc clk off - 9 - 1 - read-write - - - - - LP_AONCLKRST_LP_CLK_EN - need_des - 0x8 - 0x20 - 0x08000000 - - - LP_AONCLKRST_LP_RTC_XTAL_FORCE_ON - need_des - 26 - 1 - read-write - - - LP_AONCLKRST_CK_EN_LP_RAM - need_des - 27 - 1 - read-write - - - LP_AONCLKRST_ETM_EVENT_TICK_EN - need_des - 28 - 1 - read-write - - - LP_AONCLKRST_PLL8M_CLK_FORCE_ON - need_des - 29 - 1 - read-write - - - LP_AONCLKRST_XTAL_CLK_FORCE_ON - need_des - 30 - 1 - read-write - - - LP_AONCLKRST_FOSC_CLK_FORCE_ON - need_des - 31 - 1 - read-write - - - - - LP_AONCLKRST_LP_RST_EN - need_des - 0xC - 0x20 - - - LP_AONCLKRST_RST_EN_LP_HUK - need_des - 24 - 1 - read-write - - - LP_AONCLKRST_RST_EN_LP_ANAPERI - need_des - 25 - 1 - read-write - - - LP_AONCLKRST_RST_EN_LP_WDT - need_des - 26 - 1 - read-write - - - LP_AONCLKRST_RST_EN_LP_TIMER - need_des - 27 - 1 - read-write - - - LP_AONCLKRST_RST_EN_LP_RTC - need_des - 28 - 1 - read-write - - - LP_AONCLKRST_RST_EN_LP_MAILBOX - need_des - 29 - 1 - read-write - - - LP_AONCLKRST_RST_EN_LP_AONEFUSEREG - need_des - 30 - 1 - read-write - - - LP_AONCLKRST_RST_EN_LP_RAM - need_des - 31 - 1 - read-write - - - - - LP_AONCLKRST_RESET_CAUSE - need_des - 0x10 - 0x20 - 0x02000000 - - - LP_AONCLKRST_LPCORE_RESET_CAUSE - 6'h1: POR reset -6'h9: PMU LP PERI power down reset -6'ha: PMU LP CPU reset -6'hf: brown out reset -6'h10: LP watchdog chip reset -6'h12: super watch dog reset -6'h13: glitch reset -6'h14: software reset - 0 - 6 - read-only - - - LP_AONCLKRST_LPCORE_RESET_FLAG - need_des - 6 - 1 - read-only - - - LP_AONCLKRST_HPCORE0_RESET_CAUSE - 6'h1: POR reset -6'h3: digital system software reset -6'h5: PMU HP system power down reset -6'h7: HP system reset from HP watchdog -6'h9: HP system reset from LP watchdog -6'hb: HP core reset from HP watchdog -6'hc: HP core software reset -6'hd: HP core reset from LP watchdog -6'hf: brown out reset -6'h10: LP watchdog chip reset -6'h12: super watch dog reset -6'h13: glitch reset -6'h14: efuse crc error reset -6'h16: HP usb jtag chip reset -6'h17: HP usb uart chip reset -6'h18: HP jtag reset -6'h1a: HP core lockup - 7 - 6 - read-only - - - LP_AONCLKRST_HPCORE0_RESET_FLAG - need_des - 13 - 1 - read-only - - - LP_AONCLKRST_HPCORE1_RESET_CAUSE - 6'h1: POR reset -6'h3: digital system software reset -6'h5: PMU HP system power down reset -6'h7: HP system reset from HP watchdog -6'h9: HP system reset from LP watchdog -6'hb: HP core reset from HP watchdog -6'hc: HP core software reset -6'hd: HP core reset from LP watchdog -6'hf: brown out reset -6'h10: LP watchdog chip reset -6'h12: super watch dog reset -6'h13: glitch reset -6'h14: efuse crc error reset -6'h16: HP usb jtag chip reset -6'h17: HP usb uart chip reset -6'h18: HP jtag reset -6'h1a: HP core lockup - 14 - 6 - read-only - - - LP_AONCLKRST_HPCORE1_RESET_FLAG - need_des - 20 - 1 - read-only - - - LP_AONCLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK - 1'b0: enable lpcore pmu_lp_cpu_reset reset_cause, 1'b1: disable lpcore pmu_lp_cpu_reset reset_cause - 25 - 1 - read-write - - - LP_AONCLKRST_LPCORE_RESET_CAUSE_CLR - need_des - 26 - 1 - write-only - - - LP_AONCLKRST_LPCORE_RESET_FLAG_CLR - need_des - 27 - 1 - write-only - - - LP_AONCLKRST_HPCORE0_RESET_CAUSE_CLR - need_des - 28 - 1 - write-only - - - LP_AONCLKRST_HPCORE0_RESET_FLAG_CLR - need_des - 29 - 1 - write-only - - - LP_AONCLKRST_HPCORE1_RESET_CAUSE_CLR - need_des - 30 - 1 - write-only - - - LP_AONCLKRST_HPCORE1_RESET_FLAG_CLR - need_des - 31 - 1 - write-only - - - - - LP_AONCLKRST_HPCPU_RESET_CTRL0 - need_des - 0x14 - 0x20 - 0x80028002 - - - LP_AONCLKRST_HPCORE0_LOCKUP_RESET_EN - write 1 to enable hpcore0 lockup reset feature, write 0 to disable hpcore0 lockup reset feature - 0 - 1 - read-write - - - LP_AONCLKRST_LP_WDT_HPCORE0_RESET_LENGTH - need_des - 1 - 3 - read-write - - - LP_AONCLKRST_LP_WDT_HPCORE0_RESET_EN - write 1 to enable lp_wdt reset hpcore0 feature, write 0 to disable lp_wdt reset hpcore0 feature - 4 - 1 - read-write - - - LP_AONCLKRST_HPCORE0_STALL_WAIT - need_des - 5 - 7 - read-write - - - LP_AONCLKRST_HPCORE0_STALL_EN - need_des - 12 - 1 - read-write - - - LP_AONCLKRST_HPCORE0_SW_RESET - need_des - 13 - 1 - write-only - - - LP_AONCLKRST_HPCORE0_OCD_HALT_ON_RESET - need_des - 14 - 1 - read-write - - - LP_AONCLKRST_HPCORE0_STAT_VECTOR_SEL - 1'b1: boot from HP TCM ROM: 0x4FC00000 -1'b0: boot from LP TCM RAM: 0x50108000 - 15 - 1 - read-write - - - LP_AONCLKRST_HPCORE1_LOCKUP_RESET_EN - write 1 to enable hpcore1 lockup reset feature, write 0 to disable hpcore1 lockup reset feature - 16 - 1 - read-write - - - LP_AONCLKRST_LP_WDT_HPCORE1_RESET_LENGTH - need_des - 17 - 3 - read-write - - - LP_AONCLKRST_LP_WDT_HPCORE1_RESET_EN - write 1 to enable lp_wdt reset hpcore1 feature, write 0 to disable lp_wdt reset hpcore1 feature - 20 - 1 - read-write - - - LP_AONCLKRST_HPCORE1_STALL_WAIT - need_des - 21 - 7 - read-write - - - LP_AONCLKRST_HPCORE1_STALL_EN - need_des - 28 - 1 - read-write - - - LP_AONCLKRST_HPCORE1_SW_RESET - need_des - 29 - 1 - write-only - - - LP_AONCLKRST_HPCORE1_OCD_HALT_ON_RESET - need_des - 30 - 1 - read-write - - - LP_AONCLKRST_HPCORE1_STAT_VECTOR_SEL - 1'b1: boot from HP TCM ROM: 0x4FC00000 -1'b0: boot from LP TCM RAM: 0x50108000 - 31 - 1 - read-write - - - - - LP_AONCLKRST_HPCPU_RESET_CTRL1 - need_des - 0x18 - 0x20 - - - LP_AONCLKRST_HPCORE0_SW_STALL_CODE - HP core0 software stall when set to 8'h86 - 16 - 8 - read-write - - - LP_AONCLKRST_HPCORE1_SW_STALL_CODE - HP core1 software stall when set to 8'h86 - 24 - 8 - read-write - - - - - LP_AONCLKRST_FOSC_CNTL - need_des - 0x1C - 0x20 - 0x64000000 - - - LP_AONCLKRST_FOSC_DFREQ - need_des - 22 - 10 - read-write - - - - - LP_AONCLKRST_RC32K_CNTL - need_des - 0x20 - 0x20 - 0x0000028A - - - LP_AONCLKRST_RC32K_DFREQ - need_des - 0 - 32 - read-write - - - - - LP_AONCLKRST_SOSC_CNTL - need_des - 0x24 - 0x20 - 0x2B000000 - - - LP_AONCLKRST_SOSC_DFREQ - need_des - 22 - 10 - read-write - - - - - LP_AONCLKRST_CLK_TO_HP - need_des - 0x28 - 0x20 - 0xF0000000 - - - LP_AONCLKRST_ICG_HP_XTAL32K - reserved - 28 - 1 - read-write - - - LP_AONCLKRST_ICG_HP_SOSC - reserved - 29 - 1 - read-write - - - LP_AONCLKRST_ICG_HP_OSC32K - reserved - 30 - 1 - read-write - - - LP_AONCLKRST_ICG_HP_FOSC - reserved - 31 - 1 - read-write - - - - - LP_AONCLKRST_LPMEM_FORCE - need_des - 0x2C - 0x20 - - - LP_AONCLKRST_LPMEM_CLK_FORCE_ON - reserved - 31 - 1 - read-write - - - - - LP_AONCLKRST_XTAL32K - need_des - 0x30 - 0x20 - 0x66C00000 - - - LP_AONCLKRST_DRES_XTAL32K - need_des - 22 - 3 - read-write - - - LP_AONCLKRST_DGM_XTAL32K - need_des - 25 - 3 - read-write - - - LP_AONCLKRST_DBUF_XTAL32K - need_des - 28 - 1 - read-write - - - LP_AONCLKRST_DAC_XTAL32K - need_des - 29 - 3 - read-write - - - - - LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS - need_des - 0x34 - 0x20 - 0xFFFFFFFF - - - LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS - reserved - 0 - 32 - read-write - - - - - LP_AONCLKRST_HPSYS_0_RESET_BYPASS - need_des - 0x38 - 0x20 - 0xFFFFFFFF - - - LP_AONCLKRST_HPSYS_0_RESET_BYPASS - reserved - 0 - 32 - read-write - - - - - LP_AONCLKRST_HPSYS_APM_RESET_BYPASS - need_des - 0x3C - 0x20 - 0xFFFFFFFF - - - LP_AONCLKRST_HPSYS_APM_RESET_BYPASS - reserved - 0 - 32 - read-write - - - - - LP_AONCLKRST_HP_CLK_CTRL - HP Clock Control Register. - 0x40 - 0x20 - 0x1FFFFFFC - - - LP_AONCLKRST_HP_ROOT_CLK_SRC_SEL - HP SoC Root Clock Source Select. 2'd0: xtal_40m, 2'd1: cpll_400m, 2'd2: fosc_20m. - 0 - 2 - read-write - - - LP_AONCLKRST_HP_ROOT_CLK_EN - HP SoC Root Clock Enable. - 2 - 1 - read-write - - - LP_AONCLKRST_HP_PAD_PARLIO_TX_CLK_EN - PARLIO TX Clock From Pad Enable. - 3 - 1 - read-write - - - LP_AONCLKRST_HP_PAD_PARLIO_RX_CLK_EN - PARLIO RX Clock From Pad Enable. - 4 - 1 - read-write - - - LP_AONCLKRST_HP_PAD_UART4_SLP_CLK_EN - UART4 SLP Clock From Pad Enable. - 5 - 1 - read-write - - - LP_AONCLKRST_HP_PAD_UART3_SLP_CLK_EN - UART3 SLP Clock From Pad Enable. - 6 - 1 - read-write - - - LP_AONCLKRST_HP_PAD_UART2_SLP_CLK_EN - UART2 SLP Clock From Pad Enable. - 7 - 1 - read-write - - - LP_AONCLKRST_HP_PAD_UART1_SLP_CLK_EN - UART1 SLP Clock From Pad Enable. - 8 - 1 - read-write - - - LP_AONCLKRST_HP_PAD_UART0_SLP_CLK_EN - UART0 SLP Clock From Pad Enable. - 9 - 1 - read-write - - - LP_AONCLKRST_HP_PAD_I2S2_MCLK_EN - I2S2 MCLK Clock From Pad Enable. - 10 - 1 - read-write - - - LP_AONCLKRST_HP_PAD_I2S1_MCLK_EN - I2S1 MCLK Clock From Pad Enable. - 11 - 1 - read-write - - - LP_AONCLKRST_HP_PAD_I2S0_MCLK_EN - I2S0 MCLK Clock From Pad Enable. - 12 - 1 - read-write - - - LP_AONCLKRST_HP_PAD_EMAC_TX_CLK_EN - EMAC RX Clock From Pad Enable. - 13 - 1 - read-write - - - LP_AONCLKRST_HP_PAD_EMAC_RX_CLK_EN - EMAC TX Clock From Pad Enable. - 14 - 1 - read-write - - - LP_AONCLKRST_HP_PAD_EMAC_TXRX_CLK_EN - EMAC TXRX Clock From Pad Enable. - 15 - 1 - read-write - - - LP_AONCLKRST_HP_XTAL_32K_CLK_EN - XTAL 32K Clock Enable. - 16 - 1 - read-write - - - LP_AONCLKRST_HP_RC_32K_CLK_EN - RC 32K Clock Enable. - 17 - 1 - read-write - - - LP_AONCLKRST_HP_SOSC_150K_CLK_EN - SOSC 150K Clock Enable. - 18 - 1 - read-write - - - LP_AONCLKRST_HP_PLL_8M_CLK_EN - PLL 8M Clock Enable. - 19 - 1 - read-write - - - LP_AONCLKRST_HP_AUDIO_PLL_CLK_EN - AUDIO PLL Clock Enable. - 20 - 1 - read-write - - - LP_AONCLKRST_HP_SDIO_PLL2_CLK_EN - SDIO PLL2 Clock Enable. - 21 - 1 - read-write - - - LP_AONCLKRST_HP_SDIO_PLL1_CLK_EN - SDIO PLL1 Clock Enable. - 22 - 1 - read-write - - - LP_AONCLKRST_HP_SDIO_PLL0_CLK_EN - SDIO PLL0 Clock Enable. - 23 - 1 - read-write - - - LP_AONCLKRST_HP_FOSC_20M_CLK_EN - FOSC 20M Clock Enable. - 24 - 1 - read-write - - - LP_AONCLKRST_HP_XTAL_40M_CLK_EN - XTAL 40M Clock Enalbe. - 25 - 1 - read-write - - - LP_AONCLKRST_HP_CPLL_400M_CLK_EN - CPLL 400M Clock Enable. - 26 - 1 - read-write - - - LP_AONCLKRST_HP_SPLL_480M_CLK_EN - SPLL 480M Clock Enable. - 27 - 1 - read-write - - - LP_AONCLKRST_HP_MPLL_500M_CLK_EN - MPLL 500M Clock Enable. - 28 - 1 - read-write - - - - - LP_AONCLKRST_HP_USB_CLKRST_CTRL0 - HP USB Clock Reset Control Register. - 0x44 - 0x20 - 0x09C4C27A - - - LP_AONCLKRST_USB_OTG20_SLEEP_MODE - unused. - 0 - 1 - read-write - - - LP_AONCLKRST_USB_OTG20_BK_SYS_CLK_EN - unused. - 1 - 1 - read-write - - - LP_AONCLKRST_USB_OTG11_SLEEP_MODE - unused. - 2 - 1 - read-write - - - LP_AONCLKRST_USB_OTG11_BK_SYS_CLK_EN - unused. - 3 - 1 - read-write - - - LP_AONCLKRST_USB_OTG11_48M_CLK_EN - usb otg11 fs phy clock enable. - 4 - 1 - read-write - - - LP_AONCLKRST_USB_DEVICE_48M_CLK_EN - usb device fs phy clock enable. - 5 - 1 - read-write - - - LP_AONCLKRST_USB_48M_DIV_NUM - usb 480m to 25m divide number. - 6 - 8 - read-write - - - LP_AONCLKRST_USB_25M_DIV_NUM - usb 500m to 25m divide number. - 14 - 8 - read-write - - - LP_AONCLKRST_USB_12M_DIV_NUM - usb 480m to 12m divide number. - 22 - 8 - read-write - - - - - LP_AONCLKRST_HP_USB_CLKRST_CTRL1 - HP USB Clock Reset Control Register. - 0x48 - 0x20 - 0xC0000000 - - - LP_AONCLKRST_RST_EN_USB_OTG20_ADP - usb otg20 adp reset en - 0 - 1 - read-write - - - LP_AONCLKRST_RST_EN_USB_OTG20_PHY - usb otg20 phy reset en - 1 - 1 - read-write - - - LP_AONCLKRST_RST_EN_USB_OTG20 - usb otg20 reset en - 2 - 1 - read-write - - - LP_AONCLKRST_RST_EN_USB_OTG11 - usb org11 reset en - 3 - 1 - read-write - - - LP_AONCLKRST_RST_EN_USB_DEVICE - usb device reset en - 4 - 1 - read-write - - - LP_AONCLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL - usb otg20 hs phy src sel. 2'd0: 12m, 2'd1: 25m, 2'd2: pad_hsphy_refclk. - 28 - 2 - read-write - - - LP_AONCLKRST_USB_OTG20_PHYREF_CLK_EN - usb otg20 hs phy refclk enable. - 30 - 1 - read-write - - - LP_AONCLKRST_USB_OTG20_ULPI_CLK_EN - usb otg20 ulpi clock enable. - 31 - 1 - read-write - - - - - LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL - need_des - 0x4C - 0x20 - - - LP_AONCLKRST_RST_EN_SDMMC - hp sdmmc reset en - 28 - 1 - read-write - - - LP_AONCLKRST_FORCE_NORST_SDMMC - hp sdmmc force norst - 29 - 1 - read-write - - - LP_AONCLKRST_RST_EN_EMAC - hp emac reset en - 30 - 1 - read-write - - - LP_AONCLKRST_FORCE_NORST_EMAC - hp emac force norst - 31 - 1 - read-write - - - - - LP_AONCLKRST_DATE - need_des - 0x3FC - 0x20 - - - LP_AONCLKRST_CLK_EN - need_des - 31 - 1 - read-write - - - - - - - LP_GPIO - Low-power General Purpose Input/Output - LP_GPIO - 0x5012A000 - - 0x0 - 0xEC - registers - - - LP_GPIO - 10 - - - - CLK_EN - Reserved - 0x0 - 0x20 - 0x00000001 - - - REG_CLK_EN - Reserved - 0 - 1 - read-write - - - - - VER_DATE - Reserved - 0x4 - 0x20 - 0x00230323 - - - REG_VER_DATE - Reserved - 0 - 28 - read-write - - - - - OUT - Reserved - 0x8 - 0x20 - - - REG_GPIO_OUT_DATA - Reserved - 0 - 16 - read-write - - - - - OUT_W1TS - Reserved - 0xC - 0x20 - - - REG_GPIO_OUT_DATA_W1TS - Reserved - 0 - 16 - write-only - - - - - OUT_W1TC - Reserved - 0x10 - 0x20 - - - REG_GPIO_OUT_DATA_W1TC - Reserved - 0 - 16 - write-only - - - - - ENABLE - Reserved - 0x14 - 0x20 - - - REG_GPIO_ENABLE_DATA - Reserved - 0 - 16 - read-write - - - - - ENABLE_W1TS - Reserved - 0x18 - 0x20 - - - REG_GPIO_ENABLE_DATA_W1TS - Reserved - 0 - 16 - write-only - - - - - ENABLE_W1TC - Reserved - 0x1C - 0x20 - - - REG_GPIO_ENABLE_DATA_W1TC - Reserved - 0 - 16 - write-only - - - - - STATUS - Reserved - 0x20 - 0x20 - - - REG_GPIO_STATUS_DATA - Reserved - 0 - 16 - read-write - - - - - STATUS_W1TS - Reserved - 0x24 - 0x20 - - - REG_GPIO_STATUS_DATA_W1TS - Reserved - 0 - 16 - write-only - - - - - STATUS_W1TC - Reserved - 0x28 - 0x20 - - - REG_GPIO_STATUS_DATA_W1TC - Reserved - 0 - 16 - write-only - - - - - STATUS_NEXT - Reserved - 0x2C - 0x20 - - - REG_GPIO_STATUS_INTERRUPT_NEXT - Reserved - 0 - 16 - read-only - - - - - IN - Reserved - 0x30 - 0x20 - - - REG_GPIO_IN_DATA_NEXT - Reserved - 0 - 16 - read-only - - - - - PIN0 - Reserved - 0x34 - 0x20 - - - REG_GPIO_PIN0_WAKEUP_ENABLE - Reserved - 0 - 1 - read-write - - - REG_GPIO_PIN0_INT_TYPE - Reserved - 1 - 3 - read-write - - - REG_GPIO_PIN0_PAD_DRIVER - Reserved - 4 - 1 - read-write - - - REG_GPIO_PIN0_EDGE_WAKEUP_CLR - need des - 5 - 1 - write-only - - - - - PIN1 - Reserved - 0x38 - 0x20 - - - REG_GPIO_PIN1_WAKEUP_ENABLE - Reserved - 0 - 1 - read-write - - - REG_GPIO_PIN1_INT_TYPE - Reserved - 1 - 3 - read-write - - - REG_GPIO_PIN1_PAD_DRIVER - Reserved - 4 - 1 - read-write - - - REG_GPI1_PIN0_EDGE_WAKEUP_CLR - need des - 5 - 1 - write-only - - - - - PIN2 - Reserved - 0x3C - 0x20 - - - REG_GPIO_PIN2_WAKEUP_ENABLE - Reserved - 0 - 1 - read-write - - - REG_GPIO_PIN2_INT_TYPE - Reserved - 1 - 3 - read-write - - - REG_GPIO_PIN2_PAD_DRIVER - Reserved - 4 - 1 - read-write - - - REG_GPI2_PIN0_EDGE_WAKEUP_CLR - need des - 5 - 1 - write-only - - - - - PIN3 - Reserved - 0x40 - 0x20 - - - REG_GPIO_PIN3_WAKEUP_ENABLE - Reserved - 0 - 1 - read-write - - - REG_GPIO_PIN3_INT_TYPE - Reserved - 1 - 3 - read-write - - - REG_GPIO_PIN3_PAD_DRIVER - Reserved - 4 - 1 - read-write - - - REG_GPI3_PIN0_EDGE_WAKEUP_CLR - need des - 5 - 1 - write-only - - - - - PIN4 - Reserved - 0x44 - 0x20 - - - REG_GPIO_PIN4_WAKEUP_ENABLE - Reserved - 0 - 1 - read-write - - - REG_GPIO_PIN4_INT_TYPE - Reserved - 1 - 3 - read-write - - - REG_GPIO_PIN4_PAD_DRIVER - Reserved - 4 - 1 - read-write - - - REG_GPI4_PIN0_EDGE_WAKEUP_CLR - need des - 5 - 1 - write-only - - - - - PIN5 - Reserved - 0x48 - 0x20 - - - REG_GPIO_PIN5_WAKEUP_ENABLE - Reserved - 0 - 1 - read-write - - - REG_GPIO_PIN5_INT_TYPE - Reserved - 1 - 3 - read-write - - - REG_GPIO_PIN5_PAD_DRIVER - Reserved - 4 - 1 - read-write - - - REG_GPI5_PIN0_EDGE_WAKEUP_CLR - need des - 5 - 1 - write-only - - - - - PIN6 - Reserved - 0x4C - 0x20 - - - REG_GPIO_PIN6_WAKEUP_ENABLE - Reserved - 0 - 1 - read-write - - - REG_GPIO_PIN6_INT_TYPE - Reserved - 1 - 3 - read-write - - - REG_GPIO_PIN6_PAD_DRIVER - Reserved - 4 - 1 - read-write - - - REG_GPI6_PIN0_EDGE_WAKEUP_CLR - need des - 5 - 1 - write-only - - - - - PIN7 - Reserved - 0x50 - 0x20 - - - REG_GPIO_PIN7_WAKEUP_ENABLE - Reserved - 0 - 1 - read-write - - - REG_GPIO_PIN7_INT_TYPE - Reserved - 1 - 3 - read-write - - - REG_GPIO_PIN7_PAD_DRIVER - Reserved - 4 - 1 - read-write - - - REG_GPI7_PIN0_EDGE_WAKEUP_CLR - need des - 5 - 1 - write-only - - - - - PIN8 - Reserved - 0x54 - 0x20 - - - REG_GPIO_PIN8_WAKEUP_ENABLE - Reserved - 0 - 1 - read-write - - - REG_GPIO_PIN8_INT_TYPE - Reserved - 1 - 3 - read-write - - - REG_GPIO_PIN8_PAD_DRIVER - Reserved - 4 - 1 - read-write - - - REG_GPI8_PIN0_EDGE_WAKEUP_CLR - need des - 5 - 1 - write-only - - - - - PIN9 - Reserved - 0x58 - 0x20 - - - REG_GPIO_PIN9_WAKEUP_ENABLE - Reserved - 0 - 1 - read-write - - - REG_GPIO_PIN9_INT_TYPE - Reserved - 1 - 3 - read-write - - - REG_GPIO_PIN9_PAD_DRIVER - Reserved - 4 - 1 - read-write - - - REG_GPI9_PIN0_EDGE_WAKEUP_CLR - need des - 5 - 1 - write-only - - - - - PIN10 - Reserved - 0x5C - 0x20 - - - REG_GPIO_PIN10_WAKEUP_ENABLE - Reserved - 0 - 1 - read-write - - - REG_GPIO_PIN10_INT_TYPE - Reserved - 1 - 3 - read-write - - - REG_GPIO_PIN10_PAD_DRIVER - Reserved - 4 - 1 - read-write - - - REG_GPI10_PIN0_EDGE_WAKEUP_CLR - need des - 5 - 1 - write-only - - - - - PIN11 - Reserved - 0x60 - 0x20 - - - REG_GPIO_PIN11_WAKEUP_ENABLE - Reserved - 0 - 1 - read-write - - - REG_GPIO_PIN11_INT_TYPE - Reserved - 1 - 3 - read-write - - - REG_GPIO_PIN11_PAD_DRIVER - Reserved - 4 - 1 - read-write - - - REG_GPI11_PIN0_EDGE_WAKEUP_CLR - need des - 5 - 1 - write-only - - - - - PIN12 - Reserved - 0x64 - 0x20 - - - REG_GPIO_PIN12_WAKEUP_ENABLE - Reserved - 0 - 1 - read-write - - - REG_GPIO_PIN12_INT_TYPE - Reserved - 1 - 3 - read-write - - - REG_GPIO_PIN12_PAD_DRIVER - Reserved - 4 - 1 - read-write - - - REG_GPI12_PIN0_EDGE_WAKEUP_CLR - need des - 5 - 1 - write-only - - - - - PIN13 - Reserved - 0x68 - 0x20 - - - REG_GPIO_PIN13_WAKEUP_ENABLE - Reserved - 0 - 1 - read-write - - - REG_GPIO_PIN13_INT_TYPE - Reserved - 1 - 3 - read-write - - - REG_GPIO_PIN13_PAD_DRIVER - Reserved - 4 - 1 - read-write - - - REG_GPI13_PIN0_EDGE_WAKEUP_CLR - need des - 5 - 1 - write-only - - - - - PIN14 - Reserved - 0x6C - 0x20 - - - REG_GPIO_PIN14_WAKEUP_ENABLE - Reserved - 0 - 1 - read-write - - - REG_GPIO_PIN14_INT_TYPE - Reserved - 1 - 3 - read-write - - - REG_GPIO_PIN14_PAD_DRIVER - Reserved - 4 - 1 - read-write - - - REG_GPI14_PIN0_EDGE_WAKEUP_CLR - need des - 5 - 1 - write-only - - - - - PIN15 - Reserved - 0x70 - 0x20 - - - REG_GPIO_PIN15_WAKEUP_ENABLE - Reserved - 0 - 1 - read-write - - - REG_GPIO_PIN15_INT_TYPE - Reserved - 1 - 3 - read-write - - - REG_GPIO_PIN15_PAD_DRIVER - Reserved - 4 - 1 - read-write - - - REG_GPI15_PIN0_EDGE_WAKEUP_CLR - need des - 5 - 1 - write-only - - - - - FUNC0_IN_SEL_CFG - Reserved - 0x74 - 0x20 - 0x000000C0 - - - REG_GPIO_FUNC0_IN_INV_SEL - Reserved - 0 - 1 - read-write - - - REG_GPIO_SIG0_IN_SEL - Reserved - 1 - 1 - read-write - - - REG_GPIO_FUNC0_IN_SEL - reg_gpio_func0_in_sel[5:4]==2'b11->constant 1,reg_gpio_func0_in_sel[5:4]==2'b10->constant 0 - 2 - 6 - read-write - - - - - FUNC1_IN_SEL_CFG - Reserved - 0x78 - 0x20 - 0x000000C0 - - - REG_GPIO_FUNC1_IN_INV_SEL - Reserved - 0 - 1 - read-write - - - REG_GPIO_SIG1_IN_SEL - Reserved - 1 - 1 - read-write - - - REG_GPIO_FUNC1_IN_SEL - Reserved - 2 - 6 - read-write - - - - - FUNC2_IN_SEL_CFG - Reserved - 0x7C - 0x20 - 0x00000080 - - - REG_GPIO_FUNC2_IN_INV_SEL - Reserved - 0 - 1 - read-write - - - REG_GPIO_SIG2_IN_SEL - Reserved - 1 - 1 - read-write - - - REG_GPIO_FUNC2_IN_SEL - Reserved - 2 - 6 - read-write - - - - - FUNC3_IN_SEL_CFG - Reserved - 0x80 - 0x20 - 0x000000C0 - - - REG_GPIO_FUNC3_IN_INV_SEL - Reserved - 0 - 1 - read-write - - - REG_GPIO_SIG3_IN_SEL - Reserved - 1 - 1 - read-write - - - REG_GPIO_FUNC3_IN_SEL - Reserved - 2 - 6 - read-write - - - - - FUNC4_IN_SEL_CFG - Reserved - 0x84 - 0x20 - 0x000000C0 - - - REG_GPIO_FUNC4_IN_INV_SEL - Reserved - 0 - 1 - read-write - - - REG_GPIO_SIG4_IN_SEL - Reserved - 1 - 1 - read-write - - - REG_GPIO_FUNC4_IN_SEL - Reserved - 2 - 6 - read-write - - - - - FUNC5_IN_SEL_CFG - Reserved - 0x88 - 0x20 - 0x00000080 - - - REG_GPIO_FUNC5_IN_INV_SEL - Reserved - 0 - 1 - read-write - - - REG_GPIO_SIG5_IN_SEL - Reserved - 1 - 1 - read-write - - - REG_GPIO_FUNC5_IN_SEL - Reserved - 2 - 6 - read-write - - - - - FUNC6_IN_SEL_CFG - Reserved - 0x8C - 0x20 - 0x00000080 - - - REG_GPIO_FUNC6_IN_INV_SEL - Reserved - 0 - 1 - read-write - - - REG_GPIO_SIG6_IN_SEL - Reserved - 1 - 1 - read-write - - - REG_GPIO_FUNC6_IN_SEL - Reserved - 2 - 6 - read-write - - - - - FUNC7_IN_SEL_CFG - Reserved - 0x90 - 0x20 - 0x00000080 - - - REG_GPIO_FUNC7_IN_INV_SEL - Reserved - 0 - 1 - read-write - - - REG_GPIO_SIG7_IN_SEL - Reserved - 1 - 1 - read-write - - - REG_GPIO_FUNC7_IN_SEL - Reserved - 2 - 6 - read-write - - - - - FUNC8_IN_SEL_CFG - Reserved - 0x94 - 0x20 - 0x00000080 - - - REG_GPIO_FUNC8_IN_INV_SEL - Reserved - 0 - 1 - read-write - - - REG_GPIO_SIG8_IN_SEL - Reserved - 1 - 1 - read-write - - - REG_GPIO_FUNC8_IN_SEL - Reserved - 2 - 6 - read-write - - - - - FUNC9_IN_SEL_CFG - Reserved - 0x98 - 0x20 - 0x00000080 - - - REG_GPIO_FUNC9_IN_INV_SEL - Reserved - 0 - 1 - read-write - - - REG_GPIO_SIG9_IN_SEL - Reserved - 1 - 1 - read-write - - - REG_GPIO_FUNC9_IN_SEL - Reserved - 2 - 6 - read-write - - - - - FUNC10_IN_SEL_CFG - Reserved - 0x9C - 0x20 - 0x00000080 - - - REG_GPIO_FUNC10_IN_INV_SEL - Reserved - 0 - 1 - read-write - - - REG_GPIO_SIG10_IN_SEL - Reserved - 1 - 1 - read-write - - - REG_GPIO_FUNC10_IN_SEL - Reserved - 2 - 6 - read-write - - - - - FUNC11_IN_SEL_CFG - Reserved - 0xA0 - 0x20 - 0x00000080 - - - REG_GPIO_FUNC11_IN_INV_SEL - Reserved - 0 - 1 - read-write - - - REG_GPIO_SIG11_IN_SEL - Reserved - 1 - 1 - read-write - - - REG_GPIO_FUNC11_IN_SEL - Reserved - 2 - 6 - read-write - - - - - FUNC12_IN_SEL_CFG - Reserved - 0xA4 - 0x20 - 0x00000080 - - - REG_GPIO_FUNC12_IN_INV_SEL - Reserved - 0 - 1 - read-write - - - REG_GPIO_SIG12_IN_SEL - Reserved - 1 - 1 - read-write - - - REG_GPIO_FUNC12_IN_SEL - Reserved - 2 - 6 - read-write - - - - - FUNC13_IN_SEL_CFG - Reserved - 0xA8 - 0x20 - 0x00000080 - - - REG_GPIO_FUNC13_IN_INV_SEL - Reserved - 0 - 1 - read-write - - - REG_GPIO_SIG13_IN_SEL - Reserved - 1 - 1 - read-write - - - REG_GPIO_FUNC13_IN_SEL - Reserved - 2 - 6 - read-write - - - - - FUNC0_OUT_SEL_CFG - Reserved - 0xF4 - 0x20 - 0x00000100 - - - REG_GPIO_FUNC0_OE_INV_SEL - Reserved - 0 - 1 - read-write - - - REG_GPIO_FUNC0_OE_SEL - Reserved - 1 - 1 - read-write - - - REG_GPIO_FUNC0_OUT_INV_SEL - Reserved - 2 - 1 - read-write - - - REG_GPIO_FUNC0_OUT_SEL - reg_gpio_func0_out_sel[5:1]==16 -> output gpio register value to pad - 3 - 6 - read-write - - - - - FUNC1_OUT_SEL_CFG - Reserved - 0xF8 - 0x20 - 0x00000100 - - - REG_GPIO_FUNC1_OE_INV_SEL - Reserved - 0 - 1 - read-write - - - REG_GPIO_FUNC1_OE_SEL - Reserved - 1 - 1 - read-write - - - REG_GPIO_FUNC1_OUT_INV_SEL - Reserved - 2 - 1 - read-write - - - REG_GPIO_FUNC1_OUT_SEL - Reserved - 3 - 6 - read-write - - - - - FUNC2_OUT_SEL_CFG - Reserved - 0xFC - 0x20 - 0x00000100 - - - REG_GPIO_FUNC2_OE_INV_SEL - Reserved - 0 - 1 - read-write - - - REG_GPIO_FUNC2_OE_SEL - Reserved - 1 - 1 - read-write - - - REG_GPIO_FUNC2_OUT_INV_SEL - Reserved - 2 - 1 - read-write - - - REG_GPIO_FUNC2_OUT_SEL - Reserved - 3 - 6 - read-write - - - - - FUNC3_OUT_SEL_CFG - Reserved - 0x100 - 0x20 - 0x00000100 - - - REG_GPIO_FUNC3_OE_INV_SEL - Reserved - 0 - 1 - read-write - - - REG_GPIO_FUNC3_OE_SEL - Reserved - 1 - 1 - read-write - - - REG_GPIO_FUNC3_OUT_INV_SEL - Reserved - 2 - 1 - read-write - - - REG_GPIO_FUNC3_OUT_SEL - Reserved - 3 - 6 - read-write - - - - - FUNC4_OUT_SEL_CFG - Reserved - 0x104 - 0x20 - 0x00000100 - - - REG_GPIO_FUNC4_OE_INV_SEL - Reserved - 0 - 1 - read-write - - - REG_GPIO_FUNC4_OE_SEL - Reserved - 1 - 1 - read-write - - - REG_GPIO_FUNC4_OUT_INV_SEL - Reserved - 2 - 1 - read-write - - - REG_GPIO_FUNC4_OUT_SEL - Reserved - 3 - 6 - read-write - - - - - FUNC5_OUT_SEL_CFG - Reserved - 0x108 - 0x20 - 0x00000100 - - - REG_GPIO_FUNC5_OE_INV_SEL - Reserved - 0 - 1 - read-write - - - REG_GPIO_FUNC5_OE_SEL - Reserved - 1 - 1 - read-write - - - REG_GPIO_FUNC5_OUT_INV_SEL - Reserved - 2 - 1 - read-write - - - REG_GPIO_FUNC5_OUT_SEL - Reserved - 3 - 6 - read-write - - - - - FUNC6_OUT_SEL_CFG - Reserved - 0x10C - 0x20 - 0x00000100 - - - REG_GPIO_FUNC6_OE_INV_SEL - Reserved - 0 - 1 - read-write - - - REG_GPIO_FUNC6_OE_SEL - Reserved - 1 - 1 - read-write - - - REG_GPIO_FUNC6_OUT_INV_SEL - Reserved - 2 - 1 - read-write - - - REG_GPIO_FUNC6_OUT_SEL - Reserved - 3 - 6 - read-write - - - - - FUNC7_OUT_SEL_CFG - Reserved - 0x110 - 0x20 - 0x00000100 - - - REG_GPIO_FUNC7_OE_INV_SEL - Reserved - 0 - 1 - read-write - - - REG_GPIO_FUNC7_OE_SEL - Reserved - 1 - 1 - read-write - - - REG_GPIO_FUNC7_OUT_INV_SEL - Reserved - 2 - 1 - read-write - - - REG_GPIO_FUNC7_OUT_SEL - Reserved - 3 - 6 - read-write - - - - - FUNC8_OUT_SEL_CFG - Reserved - 0x114 - 0x20 - 0x00000100 - - - REG_GPIO_FUNC8_OE_INV_SEL - Reserved - 0 - 1 - read-write - - - REG_GPIO_FUNC8_OE_SEL - Reserved - 1 - 1 - read-write - - - REG_GPIO_FUNC8_OUT_INV_SEL - Reserved - 2 - 1 - read-write - - - REG_GPIO_FUNC8_OUT_SEL - Reserved - 3 - 6 - read-write - - - - - FUNC9_OUT_SEL_CFG - Reserved - 0x118 - 0x20 - 0x00000100 - - - REG_GPIO_FUNC9_OE_INV_SEL - Reserved - 0 - 1 - read-write - - - REG_GPIO_FUNC9_OE_SEL - Reserved - 1 - 1 - read-write - - - REG_GPIO_FUNC9_OUT_INV_SEL - Reserved - 2 - 1 - read-write - - - REG_GPIO_FUNC9_OUT_SEL - Reserved - 3 - 6 - read-write - - - - - FUNC10_OUT_SEL_CFG - Reserved - 0x11C - 0x20 - 0x00000100 - - - REG_GPIO_FUNC10_OE_INV_SEL - Reserved - 0 - 1 - read-write - - - REG_GPIO_FUNC10_OE_SEL - Reserved - 1 - 1 - read-write - - - REG_GPIO_FUNC10_OUT_INV_SEL - Reserved - 2 - 1 - read-write - - - REG_GPIO_FUNC10_OUT_SEL - Reserved - 3 - 6 - read-write - - - - - FUNC11_OUT_SEL_CFG - Reserved - 0x120 - 0x20 - 0x00000100 - - - REG_GPIO_FUNC11_OE_INV_SEL - Reserved - 0 - 1 - read-write - - - REG_GPIO_FUNC11_OE_SEL - Reserved - 1 - 1 - read-write - - - REG_GPIO_FUNC11_OUT_INV_SEL - Reserved - 2 - 1 - read-write - - - REG_GPIO_FUNC11_OUT_SEL - Reserved - 3 - 6 - read-write - - - - - FUNC12_OUT_SEL_CFG - Reserved - 0x124 - 0x20 - 0x00000100 - - - REG_GPIO_FUNC12_OE_INV_SEL - Reserved - 0 - 1 - read-write - - - REG_GPIO_FUNC12_OE_SEL - Reserved - 1 - 1 - read-write - - - REG_GPIO_FUNC12_OUT_INV_SEL - Reserved - 2 - 1 - read-write - - - REG_GPIO_FUNC12_OUT_SEL - Reserved - 3 - 6 - read-write - - - - - FUNC13_OUT_SEL_CFG - Reserved - 0x128 - 0x20 - 0x00000100 - - - REG_GPIO_FUNC13_OE_INV_SEL - Reserved - 0 - 1 - read-write - - - REG_GPIO_FUNC13_OE_SEL - Reserved - 1 - 1 - read-write - - - REG_GPIO_FUNC13_OUT_INV_SEL - Reserved - 2 - 1 - read-write - - - REG_GPIO_FUNC13_OUT_SEL - Reserved - 3 - 6 - read-write - - - - - FUNC14_OUT_SEL_CFG - Reserved - 0x12C - 0x20 - 0x00000100 - - - REG_GPIO_FUNC14_OE_INV_SEL - Reserved - 0 - 1 - read-write - - - REG_GPIO_FUNC14_OE_SEL - Reserved - 1 - 1 - read-write - - - REG_GPIO_FUNC14_OUT_INV_SEL - Reserved - 2 - 1 - read-write - - - REG_GPIO_FUNC14_OUT_SEL - Reserved - 3 - 6 - read-write - - - - - FUNC15_OUT_SEL_CFG - Reserved - 0x130 - 0x20 - 0x00000100 - - - REG_GPIO_FUNC15_OE_INV_SEL - Reserved - 0 - 1 - read-write - - - REG_GPIO_FUNC15_OE_SEL - Reserved - 1 - 1 - read-write - - - REG_GPIO_FUNC15_OUT_INV_SEL - Reserved - 2 - 1 - read-write - - - REG_GPIO_FUNC15_OUT_SEL - Reserved - 3 - 6 - read-write - - - - - - - LP_I2C0 - Low-power I2C (Inter-Integrated Circuit) Controller 0 - LP_I2C - 0x50122000 - - 0x0 - 0x88 - registers - - - LP_I2C0 - 11 - - - - SCL_LOW_PERIOD - Configures the low level width of the SCL -Clock - 0x0 - 0x20 - - - SCL_LOW_PERIOD - Configures the low level width of the SCL Clock. -Measurement unit: i2c_sclk. - 0 - 9 - read-write - - - - - CTR - Transmission setting - 0x4 - 0x20 - 0x00000208 - - - SDA_FORCE_OUT - Configures the SDA output mode -1: Direct output, - -0: Open drain output. - 0 - 1 - read-write - - - SCL_FORCE_OUT - Configures the SCL output mode -1: Direct output, - -0: Open drain output. - 1 - 1 - read-write - - - SAMPLE_SCL_LEVEL - Configures the sample mode for SDA. -1: Sample SDA data on the SCL low level. - -0: Sample SDA data on the SCL high level. - 2 - 1 - read-write - - - RX_FULL_ACK_LEVEL - Configures the ACK value that needs to be sent by master when the rx_fifo_cnt has reached the threshold. - 3 - 1 - read-write - - - TRANS_START - Configures to start sending the data in txfifo for slave. -0: No effect - -1: Start - 5 - 1 - write-only - - - TX_LSB_FIRST - Configures to control the sending order for data needing to be sent. -1: send data from the least significant bit, - -0: send data from the most significant bit. - 6 - 1 - read-write - - - RX_LSB_FIRST - Configures to control the storage order for received data. -1: receive data from the least significant bit - -0: receive data from the most significant bit. - 7 - 1 - read-write - - - CLK_EN - Configures whether to gate clock signal for registers. - -0: Force clock on for registers - -1: Support clock only when registers are read or written to by software. - 8 - 1 - read-write - - - ARBITRATION_EN - Configures to enable I2C bus arbitration detection. -0: No effect - -1: Enable - 9 - 1 - read-write - - - FSM_RST - Configures to reset the SCL_FSM. -0: No effect - -1: Reset - 10 - 1 - write-only - - - CONF_UPGATE - Configures this bit for synchronization -0: No effect - -1: Synchronize - 11 - 1 - write-only - - - - - SR - Describe I2C work status. - 0x8 - 0x20 - - - RESP_REC - Represents the received ACK value in master mode or slave mode. -0: ACK, - -1: NACK. - 0 - 1 - read-only - - - ARB_LOST - Represents whether the I2C controller loses control of SCL line. -0: No arbitration lost - -1: Arbitration lost - 3 - 1 - read-only - - - BUS_BUSY - Represents the I2C bus state. -1: The I2C bus is busy transferring data, - -0: The I2C bus is in idle state. - 4 - 1 - read-only - - - RXFIFO_CNT - Represents the number of data bytes to be sent. - 8 - 5 - read-only - - - TXFIFO_CNT - Represents the number of data bytes received in RAM. - 18 - 5 - read-only - - - SCL_MAIN_STATE_LAST - Represents the states of the I2C module state machine. -0: Idle, - -1: Address shift, - -2: ACK address, - -3: Rx data, - -4: Tx data, - -5: Send ACK, - -6: Wait ACK - 24 - 3 - read-only - - - SCL_STATE_LAST - Represents the states of the state machine used to produce SCL. -0: Idle, - -1: Start, - -2: Negative edge, - -3: Low, - -4: Positive edge, - -5: High, - -6: Stop - 28 - 3 - read-only - - - - - TO - Setting time out control for receiving data. - 0xC - 0x20 - 0x00000010 - - - TIME_OUT_VALUE - Configures the timeout threshold period for SCL stucking at high or low level. The actual period is 2^(reg_time_out_value). -Measurement unit: i2c_sclk. - 0 - 5 - read-write - - - TIME_OUT_EN - Configures to enable time out control. -0: No effect - -1: Enable - 5 - 1 - read-write - - - - - FIFO_ST - FIFO status register. - 0x14 - 0x20 - - - RXFIFO_RADDR - Represents the offset address of the APB reading from RXFIFO - 0 - 4 - read-only - - - RXFIFO_WADDR - Represents the offset address of i2c module receiving data and writing to RXFIFO. - 5 - 4 - read-only - - - TXFIFO_RADDR - Represents the offset address of i2c module reading from TXFIFO. - 10 - 4 - read-only - - - TXFIFO_WADDR - Represents the offset address of APB bus writing to TXFIFO. - 15 - 4 - read-only - - - - - FIFO_CONF - FIFO configuration register. - 0x18 - 0x20 - 0x00004046 - - - RXFIFO_WM_THRHD - Configures the water mark threshold of RXFIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd[3:0], reg_rxfifo_wm_int_raw bit will be valid. - 0 - 4 - read-write - - - TXFIFO_WM_THRHD - Configures the water mark threshold of TXFIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than reg_txfifo_wm_thrhd[3:0], reg_txfifo_wm_int_raw bit will be valid. - 5 - 4 - read-write - - - NONFIFO_EN - Configures to enable APB nonfifo access. - 10 - 1 - read-write - - - RX_FIFO_RST - Configures to reset RXFIFO. -0: No effect - -1: Reset - 12 - 1 - read-write - - - TX_FIFO_RST - Configures to reset TXFIFO. -0: No effect - -1: Reset - 13 - 1 - read-write - - - FIFO_PRT_EN - Configures to enable FIFO pointer in non-fifo access mode. This bit controls the valid bits and the TX/RX FIFO overflow, underflow, full and empty interrupts. -0: No effect - -1: Enable - 14 - 1 - read-write - - - - - DATA - Rx FIFO read data. - 0x1C - 0x20 - - - FIFO_RDATA - Represents the value of RXFIFO read data. - 0 - 8 - read-only - - - - - INT_RAW - Raw interrupt status - 0x20 - 0x20 - 0x00000002 - - - RXFIFO_WM_INT_RAW - The raw interrupt status of I2C_RXFIFO_WM_INT interrupt. - 0 - 1 - read-only - - - TXFIFO_WM_INT_RAW - The raw interrupt status of I2C_TXFIFO_WM_INT interrupt. - 1 - 1 - read-only - - - RXFIFO_OVF_INT_RAW - The raw interrupt status of I2C_RXFIFO_OVF_INT interrupt. - 2 - 1 - read-only - - - END_DETECT_INT_RAW - The raw interrupt status of the I2C_END_DETECT_INT interrupt. - 3 - 1 - read-only - - - BYTE_TRANS_DONE_INT_RAW - The raw interrupt status of the I2C_END_DETECT_INT interrupt. - 4 - 1 - read-only - - - ARBITRATION_LOST_INT_RAW - The raw interrupt status of the I2C_ARBITRATION_LOST_INT interrupt. - 5 - 1 - read-only - - - MST_TXFIFO_UDF_INT_RAW - The raw interrupt status of I2C_TRANS_COMPLETE_INT interrupt. - 6 - 1 - read-only - - - TRANS_COMPLETE_INT_RAW - The raw interrupt status of the I2C_TRANS_COMPLETE_INT interrupt. - 7 - 1 - read-only - - - TIME_OUT_INT_RAW - The raw interrupt status of the I2C_TIME_OUT_INT interrupt. - 8 - 1 - read-only - - - TRANS_START_INT_RAW - The raw interrupt status of the I2C_TRANS_START_INT interrupt. - 9 - 1 - read-only - - - NACK_INT_RAW - The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt. - 10 - 1 - read-only - - - TXFIFO_OVF_INT_RAW - The raw interrupt status of I2C_TXFIFO_OVF_INT interrupt. - 11 - 1 - read-only - - - RXFIFO_UDF_INT_RAW - The raw interrupt status of I2C_RXFIFO_UDF_INT interrupt. - 12 - 1 - read-only - - - SCL_ST_TO_INT_RAW - The raw interrupt status of I2C_SCL_ST_TO_INT interrupt. - 13 - 1 - read-only - - - SCL_MAIN_ST_TO_INT_RAW - The raw interrupt status of I2C_SCL_MAIN_ST_TO_INT interrupt. - 14 - 1 - read-only - - - DET_START_INT_RAW - The raw interrupt status of I2C_DET_START_INT interrupt. - 15 - 1 - read-only - - - - - INT_CLR - Interrupt clear bits - 0x24 - 0x20 - - - RXFIFO_WM_INT_CLR - Write 1 to clear I2C_RXFIFO_WM_INT interrupt. - 0 - 1 - write-only - - - TXFIFO_WM_INT_CLR - Write 1 to clear I2C_TXFIFO_WM_INT interrupt. - 1 - 1 - write-only - - - RXFIFO_OVF_INT_CLR - Write 1 to clear I2C_RXFIFO_OVF_INT interrupt. - 2 - 1 - write-only - - - END_DETECT_INT_CLR - Write 1 to clear the I2C_END_DETECT_INT interrupt. - 3 - 1 - write-only - - - BYTE_TRANS_DONE_INT_CLR - Write 1 to clear the I2C_END_DETECT_INT interrupt. - 4 - 1 - write-only - - - ARBITRATION_LOST_INT_CLR - Write 1 to clear the I2C_ARBITRATION_LOST_INT interrupt. - 5 - 1 - write-only - - - MST_TXFIFO_UDF_INT_CLR - Write 1 to clear I2C_TRANS_COMPLETE_INT interrupt. - 6 - 1 - write-only - - - TRANS_COMPLETE_INT_CLR - Write 1 to clear the I2C_TRANS_COMPLETE_INT interrupt. - 7 - 1 - write-only - - - TIME_OUT_INT_CLR - Write 1 to clear the I2C_TIME_OUT_INT interrupt. - 8 - 1 - write-only - - - TRANS_START_INT_CLR - Write 1 to clear the I2C_TRANS_START_INT interrupt. - 9 - 1 - write-only - - - NACK_INT_CLR - Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt. - 10 - 1 - write-only - - - TXFIFO_OVF_INT_CLR - Write 1 to clear I2C_TXFIFO_OVF_INT interrupt. - 11 - 1 - write-only - - - RXFIFO_UDF_INT_CLR - Write 1 to clear I2C_RXFIFO_UDF_INT interrupt. - 12 - 1 - write-only - - - SCL_ST_TO_INT_CLR - Write 1 to clear I2C_SCL_ST_TO_INT interrupt. - 13 - 1 - write-only - - - SCL_MAIN_ST_TO_INT_CLR - Write 1 to clear I2C_SCL_MAIN_ST_TO_INT interrupt. - 14 - 1 - write-only - - - DET_START_INT_CLR - Write 1 to clear I2C_DET_START_INT interrupt. - 15 - 1 - write-only - - - - - INT_ENA - Interrupt enable bits - 0x28 - 0x20 - - - RXFIFO_WM_INT_ENA - Write 1 to anable I2C_RXFIFO_WM_INT interrupt. - 0 - 1 - read-write - - - TXFIFO_WM_INT_ENA - Write 1 to anable I2C_TXFIFO_WM_INT interrupt. - 1 - 1 - read-write - - - RXFIFO_OVF_INT_ENA - Write 1 to anable I2C_RXFIFO_OVF_INT interrupt. - 2 - 1 - read-write - - - END_DETECT_INT_ENA - Write 1 to anable the I2C_END_DETECT_INT interrupt. - 3 - 1 - read-write - - - BYTE_TRANS_DONE_INT_ENA - Write 1 to anable the I2C_END_DETECT_INT interrupt. - 4 - 1 - read-write - - - ARBITRATION_LOST_INT_ENA - Write 1 to anable the I2C_ARBITRATION_LOST_INT interrupt. - 5 - 1 - read-write - - - MST_TXFIFO_UDF_INT_ENA - Write 1 to anable I2C_TRANS_COMPLETE_INT interrupt. - 6 - 1 - read-write - - - TRANS_COMPLETE_INT_ENA - Write 1 to anable the I2C_TRANS_COMPLETE_INT interrupt. - 7 - 1 - read-write - - - TIME_OUT_INT_ENA - Write 1 to anable the I2C_TIME_OUT_INT interrupt. - 8 - 1 - read-write - - - TRANS_START_INT_ENA - Write 1 to anable the I2C_TRANS_START_INT interrupt. - 9 - 1 - read-write - - - NACK_INT_ENA - Write 1 to anable I2C_SLAVE_STRETCH_INT interrupt. - 10 - 1 - read-write - - - TXFIFO_OVF_INT_ENA - Write 1 to anable I2C_TXFIFO_OVF_INT interrupt. - 11 - 1 - read-write - - - RXFIFO_UDF_INT_ENA - Write 1 to anable I2C_RXFIFO_UDF_INT interrupt. - 12 - 1 - read-write - - - SCL_ST_TO_INT_ENA - Write 1 to anable I2C_SCL_ST_TO_INT interrupt. - 13 - 1 - read-write - - - SCL_MAIN_ST_TO_INT_ENA - Write 1 to anable I2C_SCL_MAIN_ST_TO_INT interrupt. - 14 - 1 - read-write - - - DET_START_INT_ENA - Write 1 to anable I2C_DET_START_INT interrupt. - 15 - 1 - read-write - - - - - INT_STATUS - Status of captured I2C communication events - 0x2C - 0x20 - - - RXFIFO_WM_INT_ST - The masked interrupt status status of I2C_RXFIFO_WM_INT interrupt. - 0 - 1 - read-only - - - TXFIFO_WM_INT_ST - The masked interrupt status status of I2C_TXFIFO_WM_INT interrupt. - 1 - 1 - read-only - - - RXFIFO_OVF_INT_ST - The masked interrupt status status of I2C_RXFIFO_OVF_INT interrupt. - 2 - 1 - read-only - - - END_DETECT_INT_ST - The masked interrupt status status of the I2C_END_DETECT_INT interrupt. - 3 - 1 - read-only - - - BYTE_TRANS_DONE_INT_ST - The masked interrupt status status of the I2C_END_DETECT_INT interrupt. - 4 - 1 - read-only - - - ARBITRATION_LOST_INT_ST - The masked interrupt status status of the I2C_ARBITRATION_LOST_INT interrupt. - 5 - 1 - read-only - - - MST_TXFIFO_UDF_INT_ST - The masked interrupt status status of I2C_TRANS_COMPLETE_INT interrupt. - 6 - 1 - read-only - - - TRANS_COMPLETE_INT_ST - The masked interrupt status status of the I2C_TRANS_COMPLETE_INT interrupt. - 7 - 1 - read-only - - - TIME_OUT_INT_ST - The masked interrupt status status of the I2C_TIME_OUT_INT interrupt. - 8 - 1 - read-only - - - TRANS_START_INT_ST - The masked interrupt status status of the I2C_TRANS_START_INT interrupt. - 9 - 1 - read-only - - - NACK_INT_ST - The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt. - 10 - 1 - read-only - - - TXFIFO_OVF_INT_ST - The masked interrupt status status of I2C_TXFIFO_OVF_INT interrupt. - 11 - 1 - read-only - - - RXFIFO_UDF_INT_ST - The masked interrupt status status of I2C_RXFIFO_UDF_INT interrupt. - 12 - 1 - read-only - - - SCL_ST_TO_INT_ST - The masked interrupt status status of I2C_SCL_ST_TO_INT interrupt. - 13 - 1 - read-only - - - SCL_MAIN_ST_TO_INT_ST - The masked interrupt status status of I2C_SCL_MAIN_ST_TO_INT interrupt. - 14 - 1 - read-only - - - DET_START_INT_ST - The masked interrupt status status of I2C_DET_START_INT interrupt. - 15 - 1 - read-only - - - - - SDA_HOLD - Configures the hold time after a negative SCL edge. - 0x30 - 0x20 - - - TIME - Configures the time to hold the data after the falling edge of SCL. -Measurement unit: i2c_sclk - 0 - 9 - read-write - - - - - SDA_SAMPLE - Configures the sample time after a positive SCL edge. - 0x34 - 0x20 - - - TIME - Configures the sample time after a positive SCL edge. -Measurement unit: i2c_sclk - 0 - 9 - read-write - - - - - SCL_HIGH_PERIOD - Configures the high level width of SCL - 0x38 - 0x20 - - - SCL_HIGH_PERIOD - Configures for how long SCL remains high in master mode. -Measurement unit: i2c_sclk - 0 - 9 - read-write - - - SCL_WAIT_HIGH_PERIOD - Configures the SCL_FSM's waiting period for SCL high level in master mode. -Measurement unit: i2c_sclk - 9 - 7 - read-write - - - - - SCL_START_HOLD - Configures the delay between the SDA and SCL negative edge for a start condition - 0x40 - 0x20 - 0x00000008 - - - TIME - Configures the time between the falling edge of SDA and the falling edge of SCL for a START condition. -Measurement unit: i2c_sclk. - 0 - 9 - read-write - - - - - SCL_RSTART_SETUP - Configures the delay between the positive -edge of SCL and the negative edge of SDA - 0x44 - 0x20 - 0x00000008 - - - TIME - Configures the time between the positive edge of SCL and the negative edge of SDA for a RESTART condition. -Measurement unit: i2c_sclk - 0 - 9 - read-write - - - - - SCL_STOP_HOLD - Configures the delay after the SCL clock -edge for a stop condition - 0x48 - 0x20 - 0x00000008 - - - TIME - Configures the delay after the STOP condition. -Measurement unit: i2c_sclk - 0 - 9 - read-write - - - - - SCL_STOP_SETUP - Configures the delay between the SDA and -SCL positive edge for a stop condition - 0x4C - 0x20 - 0x00000008 - - - TIME - Configures the time between the rising edge of SCL and the rising edge of SDA. -Measurement unit: i2c_sclk - 0 - 9 - read-write - - - - - FILTER_CFG - SCL and SDA filter configuration register - 0x50 - 0x20 - 0x00000300 - - - SCL_FILTER_THRES - Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL input has smaller width than this register value, the I2C controller will ignore that pulse. -Measurement unit: i2c_sclk - 0 - 4 - read-write - - - SDA_FILTER_THRES - Configures the threshold pulse width to be filtered on SDA. When a pulse on the SDA input has smaller width than this register value, the I2C controller will ignore that pulse. -Measurement unit: i2c_sclk - 4 - 4 - read-write - - - SCL_FILTER_EN - Configures to enable the filter function for SCL. - 8 - 1 - read-write - - - SDA_FILTER_EN - Configures to enable the filter function for SDA. - 9 - 1 - read-write - - - - - CLK_CONF - I2C CLK configuration register - 0x54 - 0x20 - 0x00200000 - - - SCLK_DIV_NUM - the integral part of the fractional divisor for i2c module - 0 - 8 - read-write - - - SCLK_DIV_A - the numerator of the fractional part of the fractional divisor for i2c module - 8 - 6 - read-write - - - SCLK_DIV_B - the denominator of the fractional part of the fractional divisor for i2c module - 14 - 6 - read-write - - - SCLK_SEL - The clock selection for i2c module:0-XTAL,1-CLK_8MHz. - 20 - 1 - read-write - - - SCLK_ACTIVE - The clock switch for i2c module - 21 - 1 - read-write - - - - - COMD0 - I2C command register 0 - 0x58 - 0x20 - - - COMMAND0 - Configures command 0. It consists of three parts: -op_code is the command, -0: RSTART, -1: WRITE, -2: READ, -3: STOP, -4: END. - -Byte_num represents the number of bytes that need to be sent or received. -ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more information. - 0 - 14 - read-write - - - COMMAND0_DONE - Represents whether command 0 is done in I2C Master mode. -0: Not done - -1: Done - 31 - 1 - read-write - - - - - COMD1 - I2C command register 1 - 0x5C - 0x20 - - - COMMAND1 - Configures command 1. See details in I2C_CMD0_REG[13:0]. - 0 - 14 - read-write - - - COMMAND1_DONE - Represents whether command 1 is done in I2C Master mode. -0: Not done - -1: Done - 31 - 1 - read-write - - - - - COMD2 - I2C command register 2 - 0x60 - 0x20 - - - COMMAND2 - Configures command 2. See details in I2C_CMD0_REG[13:0]. - 0 - 14 - read-write - - - COMMAND2_DONE - Represents whether command 2 is done in I2C Master mode. -0: Not done - -1: Done - 31 - 1 - read-write - - - - - COMD3 - I2C command register 3 - 0x64 - 0x20 - - - COMMAND3 - Configures command 3. See details in I2C_CMD0_REG[13:0]. - 0 - 14 - read-write - - - COMMAND3_DONE - Represents whether command 3 is done in I2C Master mode. -0: Not done - -1: Done - 31 - 1 - read-write - - - - - COMD4 - I2C command register 4 - 0x68 - 0x20 - - - COMMAND4 - Configures command 4. See details in I2C_CMD0_REG[13:0]. - 0 - 14 - read-write - - - COMMAND4_DONE - Represents whether command 4 is done in I2C Master mode. -0: Not done - -1: Done - 31 - 1 - read-write - - - - - COMD5 - I2C command register 5 - 0x6C - 0x20 - - - COMMAND5 - Configures command 5. See details in I2C_CMD0_REG[13:0]. - 0 - 14 - read-write - - - COMMAND5_DONE - Represents whether command 5 is done in I2C Master mode. -0: Not done - -1: Done - 31 - 1 - read-write - - - - - COMD6 - I2C command register 6 - 0x70 - 0x20 - - - COMMAND6 - Configures command 6. See details in I2C_CMD0_REG[13:0]. - 0 - 14 - read-write - - - COMMAND6_DONE - Represents whether command 6 is done in I2C Master mode. -0: Not done - -1: Done - 31 - 1 - read-write - - - - - COMD7 - I2C command register 7 - 0x74 - 0x20 - - - COMMAND7 - Configures command 7. See details in I2C_CMD0_REG[13:0]. - 0 - 14 - read-write - - - COMMAND7_DONE - Represents whether command 7 is done in I2C Master mode. -0: Not done - -1: Done - 31 - 1 - read-write - - - - - SCL_ST_TIME_OUT - SCL status time out register - 0x78 - 0x20 - 0x00000010 - - - SCL_ST_TO_I2C - Configures the threshold value of SCL_FSM state unchanged period. It should be no more than 23. -Measurement unit: i2c_sclk - 0 - 5 - read-write - - - - - SCL_MAIN_ST_TIME_OUT - SCL main status time out register - 0x7C - 0x20 - 0x00000010 - - - SCL_MAIN_ST_TO_I2C - Configures the threshold value of SCL_MAIN_FSM state unchanged period.nIt should be no more than 23. -Measurement unit: i2c_sclk - 0 - 5 - read-write - - - - - SCL_SP_CONF - Power configuration register - 0x80 - 0x20 - - - SCL_RST_SLV_EN - When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to reg_scl_rst_slv_num[4:0]. - 0 - 1 - read-write - - - SCL_RST_SLV_NUM - Configures to send out SCL pulses when I2C master is IDLE. The number of pulses equals to reg_scl_rst_slv_num[4:0]. - 1 - 5 - read-write - - - SCL_PD_EN - Configure the pulses of SCL generated in I2C master mode. -Valid when reg_scl_rst_slv_en is 1. -Measurement unit: i2c_sclk - 6 - 1 - read-write - - - SDA_PD_EN - Configures to power down the I2C output SCL line. -0: Not power down. - -1: Power down. -Valid only when reg_scl_force_out is 1. - 7 - 1 - read-write - - - - - DATE - Version register - 0xF8 - 0x20 - 0x02201143 - - - DATE - Version control register. - 0 - 32 - read-write - - - - - TXFIFO_START_ADDR - I2C TXFIFO base address register - 0x100 - 0x20 - - - TXFIFO_START_ADDR - Represents the I2C txfifo first address. - 0 - 32 - read-only - - - - - RXFIFO_START_ADDR - I2C RXFIFO base address register - 0x180 - 0x20 - - - RXFIFO_START_ADDR - Represents the I2C rxfifo first address. - 0 - 32 - read-only - - - - - - - LP_I2S0 - Low-power I2S (Inter-IC Sound) Controller 0 - LP_I2S - 0x50125000 - - 0x0 - 0x98 - registers - - - LP_I2S0 - 12 - - - - VAD_CONF - I2S VAD Configure register - 0x0 - 0x20 - - - VAD_EN - VAD enable register - 0 - 1 - read-write - - - VAD_RESET - VAD reset register - 1 - 1 - write-only - - - VAD_FORCE_START - VAD force start register. - 2 - 1 - write-only - - - - - VAD_RESULT - I2S VAD Result register - 0x4 - 0x20 - - - VAD_FLAG - Reg vad flag observe signal - 0 - 1 - read-only - - - ENERGY_ENOUGH - Reg energy enough observe signal - 1 - 1 - read-only - - - - - RX_MEM_CONF - I2S VAD Observe register - 0x8 - 0x20 - 0x00007E00 - - - RX_MEM_FIFO_CNT - The number of data in the rx mem - 0 - 9 - read-only - - - RX_MEM_THRESHOLD - I2S rx mem will trigger an interrupt when the data in the mem is over(not including equal) reg_rx_mem_threshold - 9 - 8 - read-write - - - - - INT_RAW - I2S interrupt raw register, valid in level. - 0xC - 0x20 - - - RX_DONE_INT_RAW - The raw interrupt status bit for the i2s_rx_done_int interrupt - 0 - 1 - read-only - - - RX_HUNG_INT_RAW - The raw interrupt status bit for the i2s_rx_hung_int interrupt - 1 - 1 - read-only - - - RX_FIFOMEM_UDF_INT_RAW - The raw interrupt status bit for the i2s_rx_fifomem_udf_int interrupt - 2 - 1 - read-only - - - VAD_DONE_INT_RAW - The raw interrupt status bit for the vad_done_int interrupt - 3 - 1 - read-only - - - VAD_RESET_DONE_INT_RAW - The raw interrupt status bit for the vad_reset_done_int interrupt - 4 - 1 - read-only - - - RX_MEM_THRESHOLD_INT_RAW - The raw interrupt status bit for the rx_mem_threshold_int interrupt - 5 - 1 - read-only - - - - - INT_ST - I2S interrupt status register. - 0x10 - 0x20 - - - RX_DONE_INT_ST - The masked interrupt status bit for the i2s_rx_done_int interrupt - 0 - 1 - read-only - - - RX_HUNG_INT_ST - The masked interrupt status bit for the i2s_rx_hung_int interrupt - 1 - 1 - read-only - - - RX_FIFOMEM_UDF_INT_ST - The masked interrupt status bit for the i2s_rx_fifomem_udf_int interrupt - 2 - 1 - read-only - - - LP_VAD_DONE_INT_ST - The masked interrupt status bit for the vad_done_int interrupt - 3 - 1 - read-only - - - LP_VAD_RESET_DONE_INT_ST - The masked interrupt status bit for the vad_reset_done_int interrupt - 4 - 1 - read-only - - - RX_MEM_THRESHOLD_INT_ST - The masked interrupt status bit for the rx_mem_threshold_int interrupt - 5 - 1 - read-only - - - - - INT_ENA - I2S interrupt enable register. - 0x14 - 0x20 - - - RX_DONE_INT_ENA - The interrupt enable bit for the i2s_rx_done_int interrupt - 0 - 1 - read-write - - - RX_HUNG_INT_ENA - The interrupt enable bit for the i2s_rx_hung_int interrupt - 1 - 1 - read-write - - - RX_FIFOMEM_UDF_INT_ENA - The interrupt enable bit for the i2s_rx_fifomem_udf_int interrupt - 2 - 1 - read-write - - - LP_VAD_DONE_INT_ENA - The interrupt enable bit for the vad_done_int interrupt - 3 - 1 - read-write - - - LP_VAD_RESET_DONE_INT_ENA - The interrupt enable bit for the vad_reset_done_int interrupt - 4 - 1 - read-write - - - RX_MEM_THRESHOLD_INT_ENA - The interrupt enable bit for the rx_mem_threshold_int interrupt - 5 - 1 - read-write - - - - - INT_CLR - I2S interrupt clear register. - 0x18 - 0x20 - - - RX_DONE_INT_CLR - Set this bit to clear the i2s_rx_done_int interrupt - 0 - 1 - write-only - - - RX_HUNG_INT_CLR - Set this bit to clear the i2s_rx_hung_int interrupt - 1 - 1 - write-only - - - RX_FIFOMEM_UDF_INT_CLR - Set this bit to clear the i2s_rx_fifomem_udf_int interrupt - 2 - 1 - write-only - - - LP_VAD_DONE_INT_CLR - Set this bit to clear the vad_done_int interrupt - 3 - 1 - write-only - - - LP_VAD_RESET_DONE_INT_CLR - Set this bit to clear the vad_reset_done_int interrupt - 4 - 1 - write-only - - - RX_MEM_THRESHOLD_INT_CLR - Set this bit to clear the rx_mem_threshold_int interrupt - 5 - 1 - write-only - - - - - RX_CONF - I2S RX configure register - 0x20 - 0x20 - 0x00009600 - - - RX_RESET - Set this bit to reset receiver - 0 - 1 - write-only - - - RX_FIFO_RESET - Set this bit to reset Rx AFIFO - 1 - 1 - write-only - - - RX_START - Set this bit to start receiving data - 2 - 1 - read-write - - - RX_SLAVE_MOD - Set this bit to enable slave receiver mode - 3 - 1 - read-write - - - RX_FIFOMEM_RESET - Set this bit to reset Rx Syncfifomem - 4 - 1 - write-only - - - RX_MONO - Set this bit to enable receiver in mono mode - 5 - 1 - read-write - - - RX_BIG_ENDIAN - I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value. - 7 - 1 - read-write - - - RX_UPDATE - Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done. - 8 - 1 - read-write - - - RX_MONO_FST_VLD - 1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode. - 9 - 1 - read-write - - - RX_PCM_CONF - I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & - 10 - 2 - read-write - - - RX_PCM_BYPASS - Set this bit to bypass Compress/Decompress module for received data. - 12 - 1 - read-write - - - RX_STOP_MODE - 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full. - 13 - 2 - read-write - - - RX_LEFT_ALIGN - 1: I2S RX left alignment mode. 0: I2S RX right alignment mode. - 15 - 1 - read-write - - - RX_24_FILL_EN - 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits. - 16 - 1 - read-write - - - RX_WS_IDLE_POL - 0: WS should be 0 when receiving left channel data, and WS is 1in right channel. 1: WS should be 1 when receiving left channel data, and WS is 0in right channel. - 17 - 1 - read-write - - - RX_BIT_ORDER - I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first. - 18 - 1 - read-write - - - RX_TDM_EN - 1: Enable I2S TDM Rx mode . 0: Disable. - 19 - 1 - read-write - - - RX_PDM_EN - 1: Enable I2S PDM Rx mode . 0: Disable. - 20 - 1 - read-write - - - - - RX_CONF1 - I2S RX configure register 1 - 0x28 - 0x20 - 0x2F3DE300 - - - RX_TDM_WS_WIDTH - The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH[6:0] +1) * T_bck - 0 - 7 - read-write - - - RX_BCK_DIV_NUM - Bit clock configuration bits in receiver mode. - 7 - 6 - read-write - - - RX_BITS_MOD - Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode. - 13 - 5 - read-write - - - RX_HALF_SAMPLE_BITS - I2S Rx half sample bits -1. - 18 - 6 - read-write - - - RX_TDM_CHAN_BITS - The Rx bit number for each channel minus 1in TDM mode. - 24 - 5 - read-write - - - RX_MSB_SHIFT - Set this bit to enable receiver in Phillips standard mode - 29 - 1 - read-write - - - - - RX_TDM_CTRL - I2S TX TDM mode control register - 0x50 - 0x20 - 0x00000003 - - - RX_TDM_PDM_CHAN0_EN - 1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0: Disable, just input 0 in this channel. - 0 - 1 - read-write - - - RX_TDM_PDM_CHAN1_EN - 1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0: Disable, just input 0 in this channel. - 1 - 1 - read-write - - - RX_TDM_TOT_CHAN_NUM - The total channel number of I2S TX TDM mode. - 16 - 4 - read-write - - - - - RX_TIMING - I2S RX timing control register - 0x58 - 0x20 - - - RX_SD_IN_DM - The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. - 0 - 2 - read-write - - - RX_WS_OUT_DM - The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. - 16 - 2 - read-write - - - RX_BCK_OUT_DM - The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. - 20 - 2 - read-write - - - RX_WS_IN_DM - The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. - 24 - 2 - read-write - - - RX_BCK_IN_DM - The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. - 28 - 2 - read-write - - - - - LC_HUNG_CONF - I2S HUNG configure register. - 0x60 - 0x20 - 0x00000810 - - - LC_FIFO_TIMEOUT - the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value - 0 - 8 - read-write - - - LC_FIFO_TIMEOUT_SHIFT - The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift - 8 - 3 - read-write - - - LC_FIFO_TIMEOUT_ENA - The enable bit for FIFO timeout - 11 - 1 - read-write - - - - - RXEOF_NUM - I2S RX data number control register. - 0x64 - 0x20 - 0x00000040 - - - RX_EOF_NUM - The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel. - 0 - 12 - read-write - - - - - CONF_SIGLE_DATA - I2S signal data register - 0x68 - 0x20 - - - SINGLE_DATA - The configured constant channel data to be sent out. - 0 - 32 - read-write - - - - - RX_PDM_CONF - I2S RX configure register - 0x70 - 0x20 - 0xF8200000 - - - RX_PDM2PCM_EN - 1: Enable PDM2PCM RX mode. 0: DIsable. - 19 - 1 - read-write - - - RX_PDM_SINC_DSR_16_EN - Configure the down sampling rate of PDM RX filter group1 module. 1: The down sampling rate is 128. 0: down sampling rate is 64. - 20 - 1 - read-write - - - RX_PDM2PCM_AMPLIFY_NUM - Configure PDM RX amplify number. - 21 - 4 - read-write - - - RX_PDM_HP_BYPASS - I2S PDM RX bypass hp filter or not. - 25 - 1 - read-write - - - RX_IIR_HP_MULT12_5 - The fourth parameter of PDM RX IIR_HP filter stage 2 is (504 + LP_I2S_RX_IIR_HP_MULT12_5[2:0]) - 26 - 3 - read-write - - - RX_IIR_HP_MULT12_0 - The fourth parameter of PDM RX IIR_HP filter stage 1 is (504 + LP_I2S_RX_IIR_HP_MULT12_0[2:0]) - 29 - 3 - read-write - - - - - ECO_LOW - I2S ECO register - 0x74 - 0x20 - - - RDN_ECO_LOW - logic low eco registers - 0 - 32 - read-write - - - - - ECO_HIGH - I2S ECO register - 0x78 - 0x20 - 0xFFFFFFFF - - - RDN_ECO_HIGH - logic high eco registers - 0 - 32 - read-write - - - - - ECO_CONF - I2S ECO register - 0x7C - 0x20 - - - RDN_ENA - enable rdn counter bit - 0 - 1 - read-write - - - RDN_RESULT - rdn result - 1 - 1 - read-only - - - - - VAD_PARAM0 - I2S VAD Parameter register - 0x80 - 0x20 - 0x00C81388 - - - PARAM_MIN_ENERGY - VAD parameter - 0 - 16 - read-write - - - PARAM_INIT_FRAME_NUM - VAD parameter - 16 - 9 - read-write - - - - - VAD_PARAM1 - I2S VAD Parameter register - 0x84 - 0x20 - 0x281E1E43 - - - PARAM_MIN_SPEECH_COUNT - VAD parameter - 0 - 4 - read-write - - - PARAM_MAX_SPEECH_COUNT - VAD parameter - 4 - 7 - read-write - - - PARAM_HANGOVER_SPEECH - VAD parameter - 11 - 5 - read-write - - - PARAM_HANGOVER_SILENT - VAD parameter - 16 - 8 - read-write - - - PARAM_MAX_OFFSET - VAD parameter - 24 - 7 - read-write - - - PARAM_SKIP_BAND_ENERGY - Set 1 to skip band energy check. - 31 - 1 - read-write - - - - - VAD_PARAM2 - I2S VAD Parameter register - 0x88 - 0x20 - 0x7EB86666 - - - PARAM_NOISE_AMP_DOWN - VAD parameter - 0 - 16 - read-write - - - PARAM_NOISE_AMP_UP - VAD parameter - 16 - 16 - read-write - - - - - VAD_PARAM3 - I2S VAD Parameter register - 0x8C - 0x20 - 0x7D717FDF - - - PARAM_NOISE_SPE_UP0 - VAD parameter - 0 - 16 - read-write - - - PARAM_NOISE_SPE_UP1 - VAD parameter - 16 - 16 - read-write - - - - - VAD_PARAM4 - I2S VAD Parameter register - 0x90 - 0x20 - 0x799A6666 - - - PARAM_NOISE_SPE_DOWN - VAD parameter - 0 - 16 - read-write - - - PARAM_NOISE_MEAN_DOWN - VAD parameter - 16 - 16 - read-write - - - - - VAD_PARAM5 - I2S VAD Parameter register - 0x94 - 0x20 - 0x7C287D71 - - - PARAM_NOISE_MEAN_UP0 - VAD parameter - 0 - 16 - read-write - - - PARAM_NOISE_MEAN_UP1 - VAD parameter - 16 - 16 - read-write - - - - - VAD_PARAM6 - I2S VAD Parameter register - 0x98 - 0x20 - 0xB4007D00 - - - PARAM_NOISE_STD_FS_THSL - Feature_sum threshold to determine noise_std max value when vad_tag=1, equal to ((noise_std_max)>>11)^2*5 - 0 - 16 - read-write - - - PARAM_NOISE_STD_FS_THSH - Feature_sum threshold to determine noise_std max value when vad_tag=0, equal to ((noise_std_max)>>11)^2*5 - 16 - 16 - read-write - - - - - VAD_PARAM7 - I2S VAD Parameter register - 0x9C - 0x20 - 0x01487EB8 - - - PARAM_THRES_UPD_BASE - VAD parameter - 0 - 16 - read-write - - - PARAM_THRES_UPD_VARY - VAD parameter - 16 - 16 - read-write - - - - - VAD_PARAM8 - I2S VAD Parameter register - 0xA0 - 0x20 - 0x20005040 - - - PARAM_THRES_UPD_BDL - Noise_std boundary low when updating threshold. - 0 - 8 - read-write - - - PARAM_THRES_UPD_BDH - Noise_std boundary high when updating threshold. - 8 - 8 - read-write - - - PARAM_FEATURE_BURST - VAD parameter - 16 - 16 - read-write - - - - - VAD_OB0 - I2S VAD Observe register - 0xB0 - 0x20 - - - SPEECH_COUNT_OB - Reg silent count observe - 0 - 8 - read-only - - - SILENT_COUNT_OB - Reg speech count observe - 8 - 8 - read-only - - - MAX_SIGNAL0_OB - Reg max signal0 observe - 16 - 16 - read-only - - - - - VAD_OB1 - I2S VAD Observe register - 0xB4 - 0x20 - - - MAX_SIGNAL1_OB - Reg max signal1 observe - 0 - 16 - read-only - - - MAX_SIGNAL2_OB - Reg max signal2 observe - 16 - 16 - read-only - - - - - VAD_OB2 - I2S VAD Observe register - 0xB8 - 0x20 - - - NOISE_AMP_OB - Reg noise_amp observe signal - 0 - 32 - read-only - - - - - VAD_OB3 - I2S VAD Observe register - 0xBC - 0x20 - - - NOISE_MEAN_OB - Reg noise_mean observe signal - 0 - 32 - read-only - - - - - VAD_OB4 - I2S VAD Observe register - 0xC0 - 0x20 - - - NOISE_STD_OB - Reg noise_std observe signal - 0 - 32 - read-only - - - - - VAD_OB5 - I2S VAD Observe register - 0xC4 - 0x20 - - - OFFSET_OB - Reg offset observe signal - 0 - 32 - read-only - - - - - VAD_OB6 - I2S VAD Observe register - 0xC8 - 0x20 - - - THRESHOLD_OB - Reg threshold observe signal - 0 - 32 - read-only - - - - - VAD_OB7 - I2S VAD Observe register - 0xCC - 0x20 - - - ENERGY_LOW_OB - Reg energy bit 31~0 observe signal - 0 - 32 - read-only - - - - - VAD_OB8 - I2S VAD Observe register - 0xD0 - 0x20 - - - ENERGY_HIGH_OB - Reg energy bit 63~32 observe signal - 0 - 32 - read-only - - - - - CLK_GATE - Clock gate register - 0xF8 - 0x20 - 0x0000000A - - - CLK_EN - set this bit to enable clock gate - 0 - 1 - read-write - - - VAD_CG_FORCE_ON - VAD clock gate force on register - 1 - 1 - read-write - - - RX_MEM_CG_FORCE_ON - I2S rx mem clock gate force on register - 2 - 1 - read-write - - - RX_REG_CG_FORCE_ON - I2S rx reg clock gate force on register - 3 - 1 - read-write - - - - - DATE - Version control register - 0xFC - 0x20 - 0x02305040 - - - DATE - I2S version control register - 0 - 28 - read-write - - - - - - - LP_IO_MUX - Low-power Input/Output Multiplexer - LP_IOMUX - 0x5012B000 - - 0x0 - 0x54 - registers - - - - CLK_EN - Reserved - 0x0 - 0x20 - 0x00000001 - - - REG_CLK_EN - Reserved - 0 - 1 - read-write - - - - - VER_DATE - Reserved - 0x4 - 0x20 - 0x00230313 - - - REG_VER_DATE - Reserved - 0 - 28 - read-write - - - - - PAD0 - Reserved - 0x8 - 0x20 - 0x00000002 - - - REG_PAD0_DRV - Reserved - 0 - 2 - read-write - - - REG_PAD0_RDE - Reserved - 2 - 1 - read-write - - - REG_PAD0_RUE - Reserved - 3 - 1 - read-write - - - REG_PAD0_MUX_SEL - 1:use LP GPIO,0: use digital GPIO - 4 - 1 - read-write - - - REG_PAD0_FUN_SEL - function sel - 5 - 2 - read-write - - - REG_PAD0_SLP_SEL - 1: enable sleep mode during sleep,0: no sleep mode - 7 - 1 - read-write - - - REG_PAD0_SLP_IE - input enable in sleep mode - 8 - 1 - read-write - - - REG_PAD0_SLP_OE - output enable in sleep mode - 9 - 1 - read-write - - - REG_PAD0_FUN_IE - input enable in work mode - 10 - 1 - read-write - - - REG_PAD0_FILTER_EN - need des - 11 - 1 - read-write - - - - - PAD1 - Reserved - 0xC - 0x20 - 0x00000002 - - - REG_PAD1_DRV - Reserved - 0 - 2 - read-write - - - REG_PAD1_RDE - Reserved - 2 - 1 - read-write - - - REG_PAD1_RUE - Reserved - 3 - 1 - read-write - - - REG_PAD1_MUX_SEL - 1:use LP GPIO,0: use digital GPIO - 4 - 1 - read-write - - - REG_PAD1_FUN_SEL - function sel - 5 - 2 - read-write - - - REG_PAD1_SLP_SEL - 1: enable sleep mode during sleep,0: no sleep mode - 7 - 1 - read-write - - - REG_PAD1_SLP_IE - input enable in sleep mode - 8 - 1 - read-write - - - REG_PAD1_SLP_OE - output enable in sleep mode - 9 - 1 - read-write - - - REG_PAD1_FUN_IE - input enable in work mode - 10 - 1 - read-write - - - REG_PAD1_FILTER_EN - need des - 11 - 1 - read-write - - - - - PAD2 - Reserved - 0x10 - 0x20 - 0x00000002 - - - REG_PAD2_DRV - Reserved - 0 - 2 - read-write - - - REG_PAD2_RDE - Reserved - 2 - 1 - read-write - - - REG_PAD2_RUE - Reserved - 3 - 1 - read-write - - - REG_PAD2_MUX_SEL - 1:use LP GPIO,0: use digital GPIO - 4 - 1 - read-write - - - REG_PAD2_FUN_SEL - function sel - 5 - 2 - read-write - - - REG_PAD2_SLP_SEL - 1: enable sleep mode during sleep,0: no sleep mode - 7 - 1 - read-write - - - REG_PAD2_SLP_IE - input enable in sleep mode - 8 - 1 - read-write - - - REG_PAD2_SLP_OE - output enable in sleep mode - 9 - 1 - read-write - - - REG_PAD2_FUN_IE - input enable in work mode - 10 - 1 - read-write - - - REG_PAD2_FILTER_EN - need des - 11 - 1 - read-write - - - - - PAD3 - Reserved - 0x14 - 0x20 - 0x00000002 - - - REG_PAD3_DRV - Reserved - 0 - 2 - read-write - - - REG_PAD3_RDE - Reserved - 2 - 1 - read-write - - - REG_PAD3_RUE - Reserved - 3 - 1 - read-write - - - REG_PAD3_MUX_SEL - 1:use LP GPIO,0: use digital GPIO - 4 - 1 - read-write - - - REG_PAD3_FUN_SEL - function sel - 5 - 2 - read-write - - - REG_PAD3_SLP_SEL - 1: enable sleep mode during sleep,0: no sleep mode - 7 - 1 - read-write - - - REG_PAD3_SLP_IE - input enable in sleep mode - 8 - 1 - read-write - - - REG_PAD3_SLP_OE - output enable in sleep mode - 9 - 1 - read-write - - - REG_PAD3_FUN_IE - input enable in work mode - 10 - 1 - read-write - - - REG_PAD3_FILTER_EN - need des - 11 - 1 - read-write - - - - - PAD4 - Reserved - 0x18 - 0x20 - 0x00000002 - - - REG_PAD4_DRV - Reserved - 0 - 2 - read-write - - - REG_PAD4_RDE - Reserved - 2 - 1 - read-write - - - REG_PAD4_RUE - Reserved - 3 - 1 - read-write - - - REG_PAD4_MUX_SEL - 1:use LP GPIO,0: use digital GPIO - 4 - 1 - read-write - - - REG_PAD4_FUN_SEL - function sel - 5 - 2 - read-write - - - REG_PAD4_SLP_SEL - 1: enable sleep mode during sleep,0: no sleep mode - 7 - 1 - read-write - - - REG_PAD4_SLP_IE - input enable in sleep mode - 8 - 1 - read-write - - - REG_PAD4_SLP_OE - output enable in sleep mode - 9 - 1 - read-write - - - REG_PAD4_FUN_IE - input enable in work mode - 10 - 1 - read-write - - - REG_PAD4_FILTER_EN - need des - 11 - 1 - read-write - - - - - PAD5 - Reserved - 0x1C - 0x20 - 0x00000002 - - - REG_PAD5_DRV - Reserved - 0 - 2 - read-write - - - REG_PAD5_RDE - Reserved - 2 - 1 - read-write - - - REG_PAD5_RUE - Reserved - 3 - 1 - read-write - - - REG_PAD5_MUX_SEL - 1:use LP GPIO,0: use digital GPIO - 4 - 1 - read-write - - - REG_PAD5_FUN_SEL - function sel - 5 - 2 - read-write - - - REG_PAD5_SLP_SEL - 1: enable sleep mode during sleep,0: no sleep mode - 7 - 1 - read-write - - - REG_PAD5_SLP_IE - input enable in sleep mode - 8 - 1 - read-write - - - REG_PAD5_SLP_OE - output enable in sleep mode - 9 - 1 - read-write - - - REG_PAD5_FUN_IE - input enable in work mode - 10 - 1 - read-write - - - REG_PAD5_FILTER_EN - need des - 11 - 1 - read-write - - - - - PAD6 - Reserved - 0x20 - 0x20 - 0x00000002 - - - REG_PAD6_DRV - Reserved - 0 - 2 - read-write - - - REG_PAD6_RDE - Reserved - 2 - 1 - read-write - - - REG_PAD6_RUE - Reserved - 3 - 1 - read-write - - - REG_PAD6_MUX_SEL - 1:use LP GPIO,0: use digital GPIO - 4 - 1 - read-write - - - REG_PAD6_FUN_SEL - function sel - 5 - 2 - read-write - - - REG_PAD6_SLP_SEL - 1: enable sleep mode during sleep,0: no sleep mode - 7 - 1 - read-write - - - REG_PAD6_SLP_IE - input enable in sleep mode - 8 - 1 - read-write - - - REG_PAD6_SLP_OE - output enable in sleep mode - 9 - 1 - read-write - - - REG_PAD6_FUN_IE - input enable in work mode - 10 - 1 - read-write - - - REG_PAD6_FILTER_EN - need des - 11 - 1 - read-write - - - - - PAD7 - Reserved - 0x24 - 0x20 - 0x00000002 - - - REG_PAD7_DRV - Reserved - 0 - 2 - read-write - - - REG_PAD7_RDE - Reserved - 2 - 1 - read-write - - - REG_PAD7_RUE - Reserved - 3 - 1 - read-write - - - REG_PAD7_MUX_SEL - 1:use LP GPIO,0: use digital GPIO - 4 - 1 - read-write - - - REG_PAD7_FUN_SEL - function sel - 5 - 2 - read-write - - - REG_PAD7_SLP_SEL - 1: enable sleep mode during sleep,0: no sleep mode - 7 - 1 - read-write - - - REG_PAD7_SLP_IE - input enable in sleep mode - 8 - 1 - read-write - - - REG_PAD7_SLP_OE - output enable in sleep mode - 9 - 1 - read-write - - - REG_PAD7_FUN_IE - input enable in work mode - 10 - 1 - read-write - - - REG_PAD7_FILTER_EN - need des - 11 - 1 - read-write - - - - - PAD8 - Reserved - 0x28 - 0x20 - 0x00000002 - - - REG_PAD8_DRV - Reserved - 0 - 2 - read-write - - - REG_PAD8_RDE - Reserved - 2 - 1 - read-write - - - REG_PAD8_RUE - Reserved - 3 - 1 - read-write - - - REG_PAD8_MUX_SEL - 1:use LP GPIO,0: use digital GPIO - 4 - 1 - read-write - - - REG_PAD8_FUN_SEL - function sel - 5 - 2 - read-write - - - REG_PAD8_SLP_SEL - 1: enable sleep mode during sleep,0: no sleep mode - 7 - 1 - read-write - - - REG_PAD8_SLP_IE - input enable in sleep mode - 8 - 1 - read-write - - - REG_PAD8_SLP_OE - output enable in sleep mode - 9 - 1 - read-write - - - REG_PAD8_FUN_IE - input enable in work mode - 10 - 1 - read-write - - - REG_PAD8_FILTER_EN - need des - 11 - 1 - read-write - - - - - PAD9 - Reserved - 0x2C - 0x20 - 0x00000002 - - - REG_PAD9_DRV - Reserved - 0 - 2 - read-write - - - REG_PAD9_RDE - Reserved - 2 - 1 - read-write - - - REG_PAD9_RUE - Reserved - 3 - 1 - read-write - - - REG_PAD9_MUX_SEL - 1:use LP GPIO,0: use digital GPIO - 4 - 1 - read-write - - - REG_PAD9_FUN_SEL - function sel - 5 - 2 - read-write - - - REG_PAD9_SLP_SEL - 1: enable sleep mode during sleep,0: no sleep mode - 7 - 1 - read-write - - - REG_PAD9_SLP_IE - input enable in sleep mode - 8 - 1 - read-write - - - REG_PAD9_SLP_OE - output enable in sleep mode - 9 - 1 - read-write - - - REG_PAD9_FUN_IE - input enable in work mode - 10 - 1 - read-write - - - REG_PAD9_FILTER_EN - need des - 11 - 1 - read-write - - - - - PAD10 - Reserved - 0x30 - 0x20 - 0x00000002 - - - REG_PAD10_DRV - Reserved - 0 - 2 - read-write - - - REG_PAD10_RDE - Reserved - 2 - 1 - read-write - - - REG_PAD10_RUE - Reserved - 3 - 1 - read-write - - - REG_PAD10_MUX_SEL - 1:use LP GPIO,0: use digital GPIO - 4 - 1 - read-write - - - REG_PAD10_FUN_SEL - function sel - 5 - 2 - read-write - - - REG_PAD10_SLP_SEL - 1: enable sleep mode during sleep,0: no sleep mode - 7 - 1 - read-write - - - REG_PAD10_SLP_IE - input enable in sleep mode - 8 - 1 - read-write - - - REG_PAD10_SLP_OE - output enable in sleep mode - 9 - 1 - read-write - - - REG_PAD10_FUN_IE - input enable in work mode - 10 - 1 - read-write - - - REG_PAD10_FILTER_EN - need des - 11 - 1 - read-write - - - - - PAD11 - Reserved - 0x34 - 0x20 - 0x00000002 - - - REG_PAD11_DRV - Reserved - 0 - 2 - read-write - - - REG_PAD11_RDE - Reserved - 2 - 1 - read-write - - - REG_PAD11_RUE - Reserved - 3 - 1 - read-write - - - REG_PAD11_MUX_SEL - 1:use LP GPIO,0: use digital GPIO - 4 - 1 - read-write - - - REG_PAD11_FUN_SEL - function sel - 5 - 2 - read-write - - - REG_PAD11_SLP_SEL - 1: enable sleep mode during sleep,0: no sleep mode - 7 - 1 - read-write - - - REG_PAD11_SLP_IE - input enable in sleep mode - 8 - 1 - read-write - - - REG_PAD11_SLP_OE - output enable in sleep mode - 9 - 1 - read-write - - - REG_PAD11_FUN_IE - input enable in work mode - 10 - 1 - read-write - - - REG_PAD11_FILTER_EN - need des - 11 - 1 - read-write - - - - - PAD120 - Reserved - 0x38 - 0x20 - 0x00000002 - - - REG_PAD12_DRV - Reserved - 0 - 2 - read-write - - - REG_PAD12_RDE - Reserved - 2 - 1 - read-write - - - REG_PAD12_RUE - Reserved - 3 - 1 - read-write - - - REG_PAD12_MUX_SEL - 1:use LP GPIO,0: use digital GPIO - 4 - 1 - read-write - - - REG_PAD12_FUN_SEL - function sel - 5 - 2 - read-write - - - REG_PAD12_SLP_SEL - 1: enable sleep mode during sleep,0: no sleep mode - 7 - 1 - read-write - - - REG_PAD12_SLP_IE - input enable in sleep mode - 8 - 1 - read-write - - - REG_PAD12_SLP_OE - output enable in sleep mode - 9 - 1 - read-write - - - REG_PAD12_FUN_IE - input enable in work mode - 10 - 1 - read-write - - - REG_PAD12_FILTER_EN - need des - 11 - 1 - read-write - - - - - PAD13 - Reserved - 0x3C - 0x20 - 0x00000002 - - - REG_PAD13_DRV - Reserved - 0 - 2 - read-write - - - REG_PAD13_RDE - Reserved - 2 - 1 - read-write - - - REG_PAD13_RUE - Reserved - 3 - 1 - read-write - - - REG_PAD13_MUX_SEL - 1:use LP GPIO,0: use digital GPIO - 4 - 1 - read-write - - - REG_PAD13_FUN_SEL - function sel - 5 - 2 - read-write - - - REG_PAD13_SLP_SEL - 1: enable sleep mode during sleep,0: no sleep mode - 7 - 1 - read-write - - - REG_PAD13_SLP_IE - input enable in sleep mode - 8 - 1 - read-write - - - REG_PAD13_SLP_OE - output enable in sleep mode - 9 - 1 - read-write - - - REG_PAD13_FUN_IE - input enable in work mode - 10 - 1 - read-write - - - REG_PAD13_FILTER_EN - need des - 11 - 1 - read-write - - - - - PAD14 - Reserved - 0x40 - 0x20 - 0x00000002 - - - REG_PAD14_DRV - Reserved - 0 - 2 - read-write - - - REG_PAD14_RDE - Reserved - 2 - 1 - read-write - - - REG_PAD14_RUE - Reserved - 3 - 1 - read-write - - - REG_PAD14_MUX_SEL - 1:use LP GPIO,0: use digital GPIO - 4 - 1 - read-write - - - REG_PAD14_FUN_SEL - function sel - 5 - 2 - read-write - - - REG_PAD14_SLP_SEL - 1: enable sleep mode during sleep,0: no sleep mode - 7 - 1 - read-write - - - REG_PAD14_SLP_IE - input enable in sleep mode - 8 - 1 - read-write - - - REG_PAD14_SLP_OE - output enable in sleep mode - 9 - 1 - read-write - - - REG_PAD14_FUN_IE - input enable in work mode - 10 - 1 - read-write - - - REG_PAD14_FILTER_EN - need des - 11 - 1 - read-write - - - - - PAD15 - Reserved - 0x44 - 0x20 - 0x00000002 - - - REG_PAD15_DRV - Reserved - 0 - 2 - read-write - - - REG_PAD15_RDE - Reserved - 2 - 1 - read-write - - - REG_PAD15_RUE - Reserved - 3 - 1 - read-write - - - REG_PAD15_MUX_SEL - 1:use LP GPIO,0: use digital GPIO - 4 - 1 - read-write - - - REG_PAD15_FUN_SEL - function sel - 5 - 2 - read-write - - - REG_PAD15_SLP_SEL - 1: enable sleep mode during sleep,0: no sleep mode - 7 - 1 - read-write - - - REG_PAD15_SLP_IE - input enable in sleep mode - 8 - 1 - read-write - - - REG_PAD15_SLP_OE - output enable in sleep mode - 9 - 1 - read-write - - - REG_PAD15_FUN_IE - input enable in work mode - 10 - 1 - read-write - - - REG_PAD15_FILTER_EN - need des - 11 - 1 - read-write - - - - - EXT_WAKEUP0_SEL - Reserved - 0x48 - 0x20 - - - REG_XTL_EXT_CTR_SEL - select LP GPIO 0 ~ 15 to control XTAL - 0 - 5 - read-write - - - REG_EXT_WAKEUP0_SEL - Reserved - 5 - 5 - read-write - - - - - LP_PAD_HOLD - Reserved - 0x4C - 0x20 - - - REG_LP_GPIO_HOLD - Reserved - 0 - 16 - read-write - - - - - LP_PAD_HYS - Reserved - 0x50 - 0x20 - - - REG_LP_GPIO_HYS - Reserved - 0 - 16 - read-write - - - - - - - LP_UART - Low-power UART (Universal Asynchronous Receiver-Transmitter) Controller - LP_UART - 0x50121000 - - 0x0 - 0x84 - registers - - - LP_UART - 16 - - - - FIFO - FIFO data register - 0x0 - 0x20 - - - RXFIFO_RD_BYTE - UART 0 accesses FIFO via this register. - 0 - 8 - read-only - - - - - INT_RAW - Raw interrupt status - 0x4 - 0x20 - 0x00000002 - - - RXFIFO_FULL_INT_RAW - This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies. - 0 - 1 - read-write - - - TXFIFO_EMPTY_INT_RAW - This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies . - 1 - 1 - read-write - - - PARITY_ERR_INT_RAW - This interrupt raw bit turns to high level when receiver detects a parity error in the data. - 2 - 1 - read-write - - - FRM_ERR_INT_RAW - This interrupt raw bit turns to high level when receiver detects a data frame error . - 3 - 1 - read-write - - - RXFIFO_OVF_INT_RAW - This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store. - 4 - 1 - read-write - - - DSR_CHG_INT_RAW - This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal. - 5 - 1 - read-write - - - CTS_CHG_INT_RAW - This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal. - 6 - 1 - read-write - - - BRK_DET_INT_RAW - This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit. - 7 - 1 - read-write - - - RXFIFO_TOUT_INT_RAW - This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte. - 8 - 1 - read-write - - - SW_XON_INT_RAW - This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1. - 9 - 1 - read-write - - - SW_XOFF_INT_RAW - This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1. - 10 - 1 - read-write - - - GLITCH_DET_INT_RAW - This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit. - 11 - 1 - read-write - - - TX_BRK_DONE_INT_RAW - This interrupt raw bit turns to high level when transmitter completes sending NULL characters after all data in Tx-FIFO are sent. - 12 - 1 - read-write - - - TX_BRK_IDLE_DONE_INT_RAW - This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data. - 13 - 1 - read-write - - - TX_DONE_INT_RAW - This interrupt raw bit turns to high level when transmitter has send out all data in FIFO. - 14 - 1 - read-write - - - AT_CMD_CHAR_DET_INT_RAW - This interrupt raw bit turns to high level when receiver detects the configured at_cmd char. - 18 - 1 - read-write - - - WAKEUP_INT_RAW - This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode. - 19 - 1 - read-write - - - - - INT_ST - Masked interrupt status - 0x8 - 0x20 - - - RXFIFO_FULL_INT_ST - This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. - 0 - 1 - read-only - - - TXFIFO_EMPTY_INT_ST - This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1. - 1 - 1 - read-only - - - PARITY_ERR_INT_ST - This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. - 2 - 1 - read-only - - - FRM_ERR_INT_ST - This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1. - 3 - 1 - read-only - - - RXFIFO_OVF_INT_ST - This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. - 4 - 1 - read-only - - - DSR_CHG_INT_ST - This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. - 5 - 1 - read-only - - - CTS_CHG_INT_ST - This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. - 6 - 1 - read-only - - - BRK_DET_INT_ST - This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. - 7 - 1 - read-only - - - RXFIFO_TOUT_INT_ST - This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. - 8 - 1 - read-only - - - SW_XON_INT_ST - This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. - 9 - 1 - read-only - - - SW_XOFF_INT_ST - This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. - 10 - 1 - read-only - - - GLITCH_DET_INT_ST - This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. - 11 - 1 - read-only - - - TX_BRK_DONE_INT_ST - This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. - 12 - 1 - read-only - - - TX_BRK_IDLE_DONE_INT_ST - This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1. - 13 - 1 - read-only - - - TX_DONE_INT_ST - This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. - 14 - 1 - read-only - - - AT_CMD_CHAR_DET_INT_ST - This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1. - 18 - 1 - read-only - - - WAKEUP_INT_ST - This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1. - 19 - 1 - read-only - - - - - INT_ENA - Interrupt enable bits - 0xC - 0x20 - - - RXFIFO_FULL_INT_ENA - This is the enable bit for rxfifo_full_int_st register. - 0 - 1 - read-write - - - TXFIFO_EMPTY_INT_ENA - This is the enable bit for txfifo_empty_int_st register. - 1 - 1 - read-write - - - PARITY_ERR_INT_ENA - This is the enable bit for parity_err_int_st register. - 2 - 1 - read-write - - - FRM_ERR_INT_ENA - This is the enable bit for frm_err_int_st register. - 3 - 1 - read-write - - - RXFIFO_OVF_INT_ENA - This is the enable bit for rxfifo_ovf_int_st register. - 4 - 1 - read-write - - - DSR_CHG_INT_ENA - This is the enable bit for dsr_chg_int_st register. - 5 - 1 - read-write - - - CTS_CHG_INT_ENA - This is the enable bit for cts_chg_int_st register. - 6 - 1 - read-write - - - BRK_DET_INT_ENA - This is the enable bit for brk_det_int_st register. - 7 - 1 - read-write - - - RXFIFO_TOUT_INT_ENA - This is the enable bit for rxfifo_tout_int_st register. - 8 - 1 - read-write - - - SW_XON_INT_ENA - This is the enable bit for sw_xon_int_st register. - 9 - 1 - read-write - - - SW_XOFF_INT_ENA - This is the enable bit for sw_xoff_int_st register. - 10 - 1 - read-write - - - GLITCH_DET_INT_ENA - This is the enable bit for glitch_det_int_st register. - 11 - 1 - read-write - - - TX_BRK_DONE_INT_ENA - This is the enable bit for tx_brk_done_int_st register. - 12 - 1 - read-write - - - TX_BRK_IDLE_DONE_INT_ENA - This is the enable bit for tx_brk_idle_done_int_st register. - 13 - 1 - read-write - - - TX_DONE_INT_ENA - This is the enable bit for tx_done_int_st register. - 14 - 1 - read-write - - - AT_CMD_CHAR_DET_INT_ENA - This is the enable bit for at_cmd_char_det_int_st register. - 18 - 1 - read-write - - - WAKEUP_INT_ENA - This is the enable bit for uart_wakeup_int_st register. - 19 - 1 - read-write - - - - - INT_CLR - Interrupt clear bits - 0x10 - 0x20 - - - RXFIFO_FULL_INT_CLR - Set this bit to clear the rxfifo_full_int_raw interrupt. - 0 - 1 - write-only - - - TXFIFO_EMPTY_INT_CLR - Set this bit to clear txfifo_empty_int_raw interrupt. - 1 - 1 - write-only - - - PARITY_ERR_INT_CLR - Set this bit to clear parity_err_int_raw interrupt. - 2 - 1 - write-only - - - FRM_ERR_INT_CLR - Set this bit to clear frm_err_int_raw interrupt. - 3 - 1 - write-only - - - RXFIFO_OVF_INT_CLR - Set this bit to clear rxfifo_ovf_int_raw interrupt. - 4 - 1 - write-only - - - DSR_CHG_INT_CLR - Set this bit to clear the dsr_chg_int_raw interrupt. - 5 - 1 - write-only - - - CTS_CHG_INT_CLR - Set this bit to clear the cts_chg_int_raw interrupt. - 6 - 1 - write-only - - - BRK_DET_INT_CLR - Set this bit to clear the brk_det_int_raw interrupt. - 7 - 1 - write-only - - - RXFIFO_TOUT_INT_CLR - Set this bit to clear the rxfifo_tout_int_raw interrupt. - 8 - 1 - write-only - - - SW_XON_INT_CLR - Set this bit to clear the sw_xon_int_raw interrupt. - 9 - 1 - write-only - - - SW_XOFF_INT_CLR - Set this bit to clear the sw_xoff_int_raw interrupt. - 10 - 1 - write-only - - - GLITCH_DET_INT_CLR - Set this bit to clear the glitch_det_int_raw interrupt. - 11 - 1 - write-only - - - TX_BRK_DONE_INT_CLR - Set this bit to clear the tx_brk_done_int_raw interrupt.. - 12 - 1 - write-only - - - TX_BRK_IDLE_DONE_INT_CLR - Set this bit to clear the tx_brk_idle_done_int_raw interrupt. - 13 - 1 - write-only - - - TX_DONE_INT_CLR - Set this bit to clear the tx_done_int_raw interrupt. - 14 - 1 - write-only - - - AT_CMD_CHAR_DET_INT_CLR - Set this bit to clear the at_cmd_char_det_int_raw interrupt. - 18 - 1 - write-only - - - WAKEUP_INT_CLR - Set this bit to clear the uart_wakeup_int_raw interrupt. - 19 - 1 - write-only - - - - - CLKDIV_SYNC - Clock divider configuration - 0x14 - 0x20 - 0x000002B6 - - - CLKDIV - The integral part of the frequency divider factor. - 0 - 12 - read-write - - - CLKDIV_FRAG - The decimal part of the frequency divider factor. - 20 - 4 - read-write - - - - - RX_FILT - Rx Filter configuration - 0x18 - 0x20 - 0x00000008 - - - GLITCH_FILT - when input pulse width is lower than this value the pulse is ignored. - 0 - 8 - read-write - - - GLITCH_FILT_EN - Set this bit to enable Rx signal filter. - 8 - 1 - read-write - - - - - STATUS - UART status register - 0x1C - 0x20 - 0xE000C000 - - - RXFIFO_CNT - Stores the byte number of valid data in Rx-FIFO. - 3 - 5 - read-only - - - DSRN - The register represent the level value of the internal uart dsr signal. - 13 - 1 - read-only - - - CTSN - This register represent the level value of the internal uart cts signal. - 14 - 1 - read-only - - - RXD - This register represent the level value of the internal uart rxd signal. - 15 - 1 - read-only - - - TXFIFO_CNT - Stores the byte number of data in Tx-FIFO. - 19 - 5 - read-only - - - DTRN - This bit represents the level of the internal uart dtr signal. - 29 - 1 - read-only - - - RTSN - This bit represents the level of the internal uart rts signal. - 30 - 1 - read-only - - - TXD - This bit represents the level of the internal uart txd signal. - 31 - 1 - read-only - - - - - CONF0_SYNC - Configuration register 0 - 0x20 - 0x20 - 0x0000001C - - - PARITY - This register is used to configure the parity check mode. - 0 - 1 - read-write - - - PARITY_EN - Set this bit to enable uart parity check. - 1 - 1 - read-write - - - BIT_NUM - This register is used to set the length of data. - 2 - 2 - read-write - - - STOP_BIT_NUM - This register is used to set the length of stop bit. - 4 - 2 - read-write - - - TXD_BRK - Set this bit to enbale transmitter to send NULL when the process of sending data is done. - 6 - 1 - read-write - - - LOOPBACK - Set this bit to enable uart loopback test mode. - 12 - 1 - read-write - - - TX_FLOW_EN - Set this bit to enable flow control function for transmitter. - 13 - 1 - read-write - - - RXD_INV - Set this bit to inverse the level value of uart rxd signal. - 15 - 1 - read-write - - - TXD_INV - Set this bit to inverse the level value of uart txd signal. - 16 - 1 - read-write - - - DIS_RX_DAT_OVF - Disable UART Rx data overflow detect. - 17 - 1 - read-write - - - ERR_WR_MASK - 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong. - 18 - 1 - read-write - - - MEM_CLK_EN - UART memory clock gate enable signal. - 20 - 1 - read-write - - - SW_RTS - This register is used to configure the software rts signal which is used in software flow control. - 21 - 1 - read-write - - - RXFIFO_RST - Set this bit to reset the uart receive-FIFO. - 22 - 1 - read-write - - - TXFIFO_RST - Set this bit to reset the uart transmit-FIFO. - 23 - 1 - read-write - - - - - CONF1 - Configuration register 1 - 0x24 - 0x20 - 0x00006060 - - - RXFIFO_FULL_THRHD - It will produce rxfifo_full_int interrupt when receiver receives more data than this register value. - 3 - 5 - read-write - - - TXFIFO_EMPTY_THRHD - It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value. - 11 - 5 - read-write - - - CTS_INV - Set this bit to inverse the level value of uart cts signal. - 16 - 1 - read-write - - - DSR_INV - Set this bit to inverse the level value of uart dsr signal. - 17 - 1 - read-write - - - RTS_INV - Set this bit to inverse the level value of uart rts signal. - 18 - 1 - read-write - - - DTR_INV - Set this bit to inverse the level value of uart dtr signal. - 19 - 1 - read-write - - - SW_DTR - This register is used to configure the software dtr signal which is used in software flow control. - 20 - 1 - read-write - - - CLK_EN - 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers. - 21 - 1 - read-write - - - - - HWFC_CONF_SYNC - Hardware flow-control configuration - 0x2C - 0x20 - - - RX_FLOW_THRHD - This register is used to configure the maximum amount of data that can be received when hardware flow control works. - 3 - 5 - read-write - - - RX_FLOW_EN - This is the flow enable bit for UART receiver. - 8 - 1 - read-write - - - - - SLEEP_CONF0 - UART sleep configure register 0 - 0x30 - 0x20 - - - WK_CHAR1 - This register restores the specified wake up char1 to wake up - 0 - 8 - read-write - - - WK_CHAR2 - This register restores the specified wake up char2 to wake up - 8 - 8 - read-write - - - WK_CHAR3 - This register restores the specified wake up char3 to wake up - 16 - 8 - read-write - - - WK_CHAR4 - This register restores the specified wake up char4 to wake up - 24 - 8 - read-write - - - - - SLEEP_CONF1 - UART sleep configure register 1 - 0x34 - 0x20 - - - WK_CHAR0 - This register restores the specified char0 to wake up - 0 - 8 - read-write - - - - - SLEEP_CONF2 - UART sleep configure register 2 - 0x38 - 0x20 - 0x001420F0 - - - ACTIVE_THRESHOLD - The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value. - 0 - 10 - read-write - - - RX_WAKE_UP_THRHD - In wake up mode 1 this field is used to set the received data number threshold to wake up chip. - 13 - 5 - read-write - - - WK_CHAR_NUM - This register is used to select number of wake up char. - 18 - 3 - read-write - - - WK_CHAR_MASK - This register is used to mask wake up char. - 21 - 5 - read-write - - - WK_MODE_SEL - This register is used to select wake up mode. 0: RXD toggling to wake up. 1: received data number larger than - 26 - 2 - read-write - - - - - SWFC_CONF0_SYNC - Software flow-control character configuration - 0x3C - 0x20 - 0x00001311 - - - XON_CHAR - This register stores the Xon flow control char. - 0 - 8 - read-write - - - XOFF_CHAR - This register stores the Xoff flow control char. - 8 - 8 - read-write - - - XON_XOFF_STILL_SEND - In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In this status, UART Tx can not transmit XOFF even the received data number is larger than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when UART Tx is disabled. - 16 - 1 - read-write - - - SW_FLOW_CON_EN - Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff. - 17 - 1 - read-write - - - XONOFF_DEL - Set this bit to remove flow control char from the received data. - 18 - 1 - read-write - - - FORCE_XON - Set this bit to enable the transmitter to go on sending data. - 19 - 1 - read-write - - - FORCE_XOFF - Set this bit to stop the transmitter from sending data. - 20 - 1 - read-write - - - SEND_XON - Set this bit to send Xon char. It is cleared by hardware automatically. - 21 - 1 - read-write - - - SEND_XOFF - Set this bit to send Xoff char. It is cleared by hardware automatically. - 22 - 1 - read-write - - - - - SWFC_CONF1 - Software flow-control character configuration - 0x40 - 0x20 - 0x00006000 - - - XON_THRESHOLD - When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1 it will send a Xon char. - 3 - 5 - read-write - - - XOFF_THRESHOLD - When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1 it will send a Xoff char. - 11 - 5 - read-write - - - - - TXBRK_CONF_SYNC - Tx Break character configuration - 0x44 - 0x20 - 0x0000000A - - - TX_BRK_NUM - This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1. - 0 - 8 - read-write - - - - - IDLE_CONF_SYNC - Frame-end idle configuration - 0x48 - 0x20 - 0x00040100 - - - RX_IDLE_THRHD - It will produce frame end signal when receiver takes more time to receive one byte data than this register value. - 0 - 10 - read-write - - - TX_IDLE_NUM - This register is used to configure the duration time between transfers. - 10 - 10 - read-write - - - - - RS485_CONF_SYNC - RS485 mode configuration - 0x4C - 0x20 - - - DL0_EN - Set this bit to delay the stop bit by 1 bit. - 1 - 1 - read-write - - - DL1_EN - Set this bit to delay the stop bit by 1 bit. - 2 - 1 - read-write - - - - - AT_CMD_PRECNT_SYNC - Pre-sequence timing configuration - 0x50 - 0x20 - 0x00000901 - - - PRE_IDLE_NUM - This register is used to configure the idle duration time before the first at_cmd is received by receiver. - 0 - 16 - read-write - - - - - AT_CMD_POSTCNT_SYNC - Post-sequence timing configuration - 0x54 - 0x20 - 0x00000901 - - - POST_IDLE_NUM - This register is used to configure the duration time between the last at_cmd and the next data. - 0 - 16 - read-write - - - - - AT_CMD_GAPTOUT_SYNC - Timeout configuration - 0x58 - 0x20 - 0x0000000B - - - RX_GAP_TOUT - This register is used to configure the duration time between the at_cmd chars. - 0 - 16 - read-write - - - - - AT_CMD_CHAR_SYNC - AT escape sequence detection configuration - 0x5C - 0x20 - 0x0000032B - - - AT_CMD_CHAR - This register is used to configure the content of at_cmd char. - 0 - 8 - read-write - - - CHAR_NUM - This register is used to configure the num of continuous at_cmd chars received by receiver. - 8 - 8 - read-write - - - - - MEM_CONF - UART memory power configuration - 0x60 - 0x20 - - - MEM_FORCE_PD - Set this bit to force power down UART memory. - 25 - 1 - read-write - - - MEM_FORCE_PU - Set this bit to force power up UART memory. - 26 - 1 - read-write - - - - - TOUT_CONF_SYNC - UART threshold and allocation configuration - 0x64 - 0x20 - 0x00000028 - - - RX_TOUT_EN - This is the enble bit for uart receiver's timeout function. - 0 - 1 - read-write - - - RX_TOUT_FLOW_DIS - Set this bit to stop accumulating idle_cnt when hardware flow control works. - 1 - 1 - read-write - - - RX_TOUT_THRHD - This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1. - 2 - 10 - read-write - - - - - MEM_TX_STATUS - Tx-SRAM write and read offset address. - 0x68 - 0x20 - - - TX_SRAM_WADDR - This register stores the offset write address in Tx-SRAM. - 3 - 5 - read-only - - - TX_SRAM_RADDR - This register stores the offset read address in Tx-SRAM. - 12 - 5 - read-only - - - - - MEM_RX_STATUS - Rx-SRAM write and read offset address. - 0x6C - 0x20 - 0x00010080 - - - RX_SRAM_RADDR - This register stores the offset read address in RX-SRAM. - 3 - 5 - read-only - - - RX_SRAM_WADDR - This register stores the offset write address in Rx-SRAM. - 12 - 5 - read-only - - - - - FSM_STATUS - UART transmit and receive status. - 0x70 - 0x20 - - - ST_URX_OUT - This is the status register of receiver. - 0 - 4 - read-only - - - ST_UTX_OUT - This is the status register of transmitter. - 4 - 4 - read-only - - - - - CLK_CONF - UART core clock configuration - 0x88 - 0x20 - 0x03000000 - - - TX_SCLK_EN - Set this bit to enable UART Tx clock. - 24 - 1 - read-write - - - RX_SCLK_EN - Set this bit to enable UART Rx clock. - 25 - 1 - read-write - - - TX_RST_CORE - Write 1 then write 0 to this bit to reset UART Tx. - 26 - 1 - read-write - - - RX_RST_CORE - Write 1 then write 0 to this bit to reset UART Rx. - 27 - 1 - read-write - - - - - DATE - UART Version register - 0x8C - 0x20 - 0x02305050 - - - DATE - This is the version register. - 0 - 32 - read-write - - - - - AFIFO_STATUS - UART AFIFO Status - 0x90 - 0x20 - 0x0000000A - - - TX_AFIFO_FULL - Full signal of APB TX AFIFO. - 0 - 1 - read-only - - - TX_AFIFO_EMPTY - Empty signal of APB TX AFIFO. - 1 - 1 - read-only - - - RX_AFIFO_FULL - Full signal of APB RX AFIFO. - 2 - 1 - read-only - - - RX_AFIFO_EMPTY - Empty signal of APB RX AFIFO. - 3 - 1 - read-only - - - - - REG_UPDATE - UART Registers Configuration Update register - 0x98 - 0x20 - - - REG_UPDATE - Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done. - 0 - 1 - read-write - - - - - ID - UART ID register - 0x9C - 0x20 - 0x00000500 - - - ID - This register is used to configure the uart_id. - 0 - 32 - read-write - - - - - - - MCPWM0 - Motor Control Pulse-Width Modulation 0 - MCPWM - 0x500C0000 - - 0x0 - 0x14C - registers - - - PWM0 - 38 - - - - CLK_CFG - PWM clock prescaler register. - 0x0 - 0x20 - - - CLK_PRESCALE - Configures the prescaler value of clock, so that the period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1). - 0 - 8 - read-write - - - - - 3 - 0x10 - TIMER%s_CFG0 - PWM timer%s period and update method configuration register. - 0x4 - 0x20 - 0x0000FF00 - - - TIMER_PRESCALE - Configures the prescaler value of timer%s, so that the period of PT0_clk = Period of PWM_clk * (PWM_TIMER%s_PRESCALE + 1) - 0 - 8 - read-write - - - TIMER_PERIOD - Configures the period shadow of PWM timer%s - 8 - 16 - read-write - - - TIMER_PERIOD_UPMETHOD - Configures the update method for active register of PWM timer%s period.\\0: Immediate\\1: TEZ\\2: Sync\\3: TEZ or sync\\TEZ here and below means timer equal zero event - 24 - 2 - read-write - - - - - 3 - 0x10 - TIMER%s_CFG1 - PWM timer%s working mode and start/stop control register. - 0x8 - 0x20 - - - TIMER_START - Configures whether or not to start/stop PWM timer%s.\\0: If PWM timer%s starts, then stops at TEZ\\1: If timer%s starts, then stops at TEP\\2: PWM timer%s starts and runs on\\3: Timer%s starts and stops at the next TEZ\\4: Timer0 starts and stops at the next TEP.\\TEP here and below means the event that happens when the timer equals to period - 0 - 3 - read-write - - - TIMER_MOD - Configures the working mode of PWM timer%s.\\0: Freeze\\1: Increase mode\\2: Decrease mode\\3: Up-down mode - 3 - 2 - read-write - - - - - 3 - 0x10 - TIMER%s_SYNC - PWM timer%s sync function configuration register. - 0xC - 0x20 - - - TIMER_SYNCI_EN - Configures whether or not to enable timer%s reloading with phase on sync input event is enabled.\\0: Disable\\1: Enable - 0 - 1 - read-write - - - SW - Configures the generation of software sync. Toggling this bit will trigger a software sync. - 1 - 1 - read-write - - - TIMER_SYNCO_SEL - Configures the selection of PWM timer%s sync_out.\\0: Sync_in\\1: TEZ\\2: TEP\\3: Invalid, sync_out selects noting - 2 - 2 - read-write - - - TIMER_PHASE - Configures the phase for timer%s reload on sync event. - 4 - 16 - read-write - - - TIMER_PHASE_DIRECTION - Configures the PWM timer%s's direction when timer%s mode is up-down mode.\\0: Increase\\1: Decrease - 20 - 1 - read-write - - - - - 3 - 0x10 - TIMER%s_STATUS - PWM timer%s status register. - 0x10 - 0x20 - - - TIMER_VALUE - Represents current PWM timer%s counter value. - 0 - 16 - read-only - - - TIMER_DIRECTION - Represents current PWM timer%s counter direction.\\0: Increment\\1: Decrement - 16 - 1 - read-only - - - - - TIMER_SYNCI_CFG - Synchronization input selection register for PWM timers. - 0x34 - 0x20 - - - TIMER0_SYNCISEL - Configures the selection of sync input for PWM timer0.\\1: PWM timer0 sync_out\\2: PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1 from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected - 0 - 3 - read-write - - - TIMER1_SYNCISEL - Configures the selection of sync input for PWM timer1.\\1: PWM timer0 sync_out\\2: PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1 from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected - 3 - 3 - read-write - - - TIMER2_SYNCISEL - Configures the selection of sync input for PWM timer2.\\1: PWM timer0 sync_out\\2: PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1 from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected - 6 - 3 - read-write - - - EXTERNAL_SYNCI0_INVERT - Configures whether or not to invert SYNC0 from GPIO matrix.\\0: Not invert\\1: Invert - 9 - 1 - read-write - - - EXTERNAL_SYNCI1_INVERT - Configures whether or not to invert SYNC1 from GPIO matrix.\\0: Not invert\\1: Invert - 10 - 1 - read-write - - - EXTERNAL_SYNCI2_INVERT - Configures whether or not to invert SYNC2 from GPIO matrix.\\0: Not invert\\1: Invert - 11 - 1 - read-write - - - - - OPERATOR_TIMERSEL - PWM operator's timer select register - 0x38 - 0x20 - - - OPERATOR0_TIMERSEL - Configures which PWM timer will be the timing reference for PWM operator0.\\0: Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2 - 0 - 2 - read-write - - - OPERATOR1_TIMERSEL - Configures which PWM timer will be the timing reference for PWM operator1.\\0: Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2 - 2 - 2 - read-write - - - OPERATOR2_TIMERSEL - Configures which PWM timer will be the timing reference for PWM operator2.\\0: Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2 - 4 - 2 - read-write - - - - - 3 - 0x38 - GEN%s_STMP_CFG - Generator%s time stamp registers A and B transfer status and update method register - 0x3C - 0x20 - - - CMPR_A_UPMETHOD - Configures the update method for PWM generator %s time stamp A's active register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: Sync\\Bit3 is set to 1: Disable the update - 0 - 4 - read-write - - - CMPR_B_UPMETHOD - Configures the update method for PWM generator %s time stamp B's active register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: Sync\\Bit3 is set to 1: Disable the update - 4 - 4 - read-write - - - CMPR_A_SHDW_FULL - Represents whether or not generator%s time stamp A's shadow reg is transferred.\\0: A's active reg has been updated with shadow register latest value.\\1: A's shadow reg is filled and waiting to be transferred to A's active reg - 8 - 1 - read-write - - - CMPR_B_SHDW_FULL - Represents whether or not generator%s time stamp B's shadow reg is transferred.\\0: B's active reg has been updated with shadow register latest value.\\1: B's shadow reg is filled and waiting to be transferred to B's active reg - 9 - 1 - read-write - - - - - 3 - 0x38 - GEN%s_TSTMP_A - Generator%s time stamp A's shadow register - 0x40 - 0x20 - - - CMPR_A - Configures the value of PWM generator %s time stamp A's shadow register. - 0 - 16 - read-write - - - - - 3 - 0x38 - GEN%s_TSTMP_B - Generator%s time stamp B's shadow register - 0x44 - 0x20 - - - CMPR_B - Configures the value of PWM generator %s time stamp B's shadow register. - 0 - 16 - read-write - - - - - 3 - 0x38 - GEN%s_CFG0 - Generator%s fault event T0 and T1 configuration register - 0x48 - 0x20 - - - GEN_CFG_UPMETHOD - Configures update method for PWM generator %s's active register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: Sync\\Bit3 is set to 1: Disable the update - 0 - 4 - read-write - - - GEN_T0_SEL - Configures source selection for PWM generator %s event_t0, take effect immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4: Invalid, Select nothing - 4 - 3 - read-write - - - GEN_T1_SEL - Configures source selection for PWM generator %s event_t1, take effect immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4: Invalid, Select nothing - 7 - 3 - read-write - - - - - 3 - 0x38 - GEN%s_FORCE - Generator%s output signal force mode register. - 0x4C - 0x20 - 0x00000020 - - - GEN_CNTUFORCE_UPMETHOD - Configures update method for continuous software force of PWM generator%s.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: TEA\\Bit3 is set to 1: TEB\\Bit4 is set to 1: Sync\\Bit5 is set to 1: Disable update. TEA/B here and below means an event generated when the timer's value equals to that of register A/B. - 0 - 6 - read-write - - - GEN_A_CNTUFORCE_MODE - Configures continuous software force mode for PWM%s A.\\0: Disabled\\1: Low\\2: High\\3: Disabled - 6 - 2 - read-write - - - GEN_B_CNTUFORCE_MODE - Configures continuous software force mode for PWM%s B.\\0: Disabled\\1: Low\\2: High\\3: Disabled - 8 - 2 - read-write - - - GEN_A_NCIFORCE - Configures the generation of non-continuous immediate software-force event for PWM%s A, a toggle will trigger a force event. - 10 - 1 - read-write - - - GEN_A_NCIFORCE_MODE - Configures non-continuous immediate software force mode for PWM%s A.\\0: Disabled\\1: Low\\2: High\\3: Disabled - 11 - 2 - read-write - - - GEN_B_NCIFORCE - Configures the generation of non-continuous immediate software-force event for PWM%s B, a toggle will trigger a force event. - 13 - 1 - read-write - - - GEN_B_NCIFORCE_MODE - Configures non-continuous immediate software force mode for PWM%s B.\\0: Disabled\\1: Low\\2: High\\3: Disabled - 14 - 2 - read-write - - - - - 3 - 0x38 - GEN%s_A - PWM%s output signal A actions configuration register - 0x50 - 0x20 - - - UTEZ - Configures action on PWM%s A triggered by event TEZ when timer increasing.\\0: No change\\1: Low\\2: High\\3: Toggle - 0 - 2 - read-write - - - UTEP - Configures action on PWM%s A triggered by event TEP when timer increasing.\\0: No change\\1: Low\\2: High\\3: Toggle - 2 - 2 - read-write - - - UTEA - Configures action on PWM%s A triggered by event TEA when timer increasing.\\0: No change\\1: Low\\2: High\\3: Toggle - 4 - 2 - read-write - - - UTEB - Configures action on PWM%s A triggered by event TEB when timer increasing.\\0: No change\\1: Low\\2: High\\3: Toggle - 6 - 2 - read-write - - - UT0 - Configures action on PWM%s A triggered by event_t0 when timer increasing.\\0: No change\\1: Low\\2: High\\3: Toggle - 8 - 2 - read-write - - - UT1 - Configures action on PWM%s A triggered by event_t1 when timer increasing.\\0: No change\\1: Low\\2: High\\3: Toggle - 10 - 2 - read-write - - - DTEZ - Configures action on PWM%s A triggered by event TEZ when timer decreasing.\\0: No change\\1: Low\\2: High\\3: Toggle - 12 - 2 - read-write - - - DTEP - Configures action on PWM%s A triggered by event TEP when timer decreasing.\\0: No change\\1: Low\\2: High\\3: Toggle - 14 - 2 - read-write - - - DTEA - Configures action on PWM%s A triggered by event TEA when timer decreasing.\\0: No change\\1: Low\\2: High\\3: Toggle - 16 - 2 - read-write - - - DTEB - Configures action on PWM%s A triggered by event TEB when timer decreasing.\\0: No change\\1: Low\\2: High\\3: Toggle - 18 - 2 - read-write - - - DT0 - Configures action on PWM%s A triggered by event_t0 when timer decreasing.\\0: No change\\1: Low\\2: High\\3: Toggle - 20 - 2 - read-write - - - DT1 - Configures action on PWM%s A triggered by event_t1 when timer decreasing.\\0: No change\\1: Low\\2: High\\3: Toggle - 22 - 2 - read-write - - - - - 3 - 0x38 - GEN%s_B - PWM%s output signal B actions configuration register - 0x54 - 0x20 - - - UTEZ - Configures action on PWM%s B triggered by event TEZ when timer increasing.\\0: No change\\1: Low\\2: High\\3: Toggle - 0 - 2 - read-write - - - UTEP - Configures action on PWM%s B triggered by event TEP when timer increasing.\\0: No change\\1: Low\\2: High\\3: Toggle - 2 - 2 - read-write - - - UTEA - Configures action on PWM%s B triggered by event TEA when timer increasing.\\0: No change\\1: Low\\2: High\\3: Toggle - 4 - 2 - read-write - - - UTEB - Configures action on PWM%s B triggered by event TEB when timer increasing.\\0: No change\\1: Low\\2: High\\3: Toggle - 6 - 2 - read-write - - - UT0 - Configures action on PWM%s B triggered by event_t0 when timer increasing.\\0: No change\\1: Low\\2: High\\3: Toggle - 8 - 2 - read-write - - - UT1 - Configures action on PWM%s B triggered by event_t1 when timer increasing.\\0: No change\\1: Low\\2: High\\3: Toggle - 10 - 2 - read-write - - - DTEZ - Configures action on PWM%s B triggered by event TEZ when timer decreasing.\\0: No change\\1: Low\\2: High\\3: Toggle - 12 - 2 - read-write - - - DTEP - Configures action on PWM%s B triggered by event TEP when timer decreasing.\\0: No change\\1: Low\\2: High\\3: Toggle - 14 - 2 - read-write - - - DTEA - Configures action on PWM%s B triggered by event TEA when timer decreasing.\\0: No change\\1: Low\\2: High\\3: Toggle - 16 - 2 - read-write - - - DTEB - Configures action on PWM%s B triggered by event TEB when timer decreasing.\\0: No change\\1: Low\\2: High\\3: Toggle - 18 - 2 - read-write - - - DT0 - Configures action on PWM%s B triggered by event_t0 when timer decreasing.\\0: No change\\1: Low\\2: High\\3: Toggle - 20 - 2 - read-write - - - DT1 - Configures action on PWM%s B triggered by event_t1 when timer decreasing.\\0: No change\\1: Low\\2: High\\3: Toggle - 22 - 2 - read-write - - - - - 3 - 0x38 - DT%s_CFG - Dead time configuration register - 0x58 - 0x20 - 0x00018000 - - - DB_FED_UPMETHOD - Configures update method for FED (Falling edge delay) active register.\\0: Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: Sync\\Bit3 is set to 1: Disable the update - 0 - 4 - read-write - - - DB_RED_UPMETHOD - Configures update method for RED (rising edge delay) active register.\\0: Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: Sync\\Bit3 is set to 1: Disable the update - 4 - 4 - read-write - - - DB_DEB_MODE - Configures S8 in table, dual-edge B mode.\\0: fed/red take effect on different path separately\\1: fed/red take effect on B path, A out is in bypass or dulpB mode - 8 - 1 - read-write - - - DB_A_OUTSWAP - Configures S6 in table. - 9 - 1 - read-write - - - DB_B_OUTSWAP - Configures S7 in table. - 10 - 1 - read-write - - - DB_RED_INSEL - Configures S4 in table. - 11 - 1 - read-write - - - DB_FED_INSEL - Configures S5 in table. - 12 - 1 - read-write - - - DB_RED_OUTINVERT - Configures S2 in table. - 13 - 1 - read-write - - - DB_FED_OUTINVERT - Configures S3 in table. - 14 - 1 - read-write - - - DB_A_OUTBYPASS - Configures S1 in table. - 15 - 1 - read-write - - - DB_B_OUTBYPASS - Configures S0 in table. - 16 - 1 - read-write - - - DB_CLK_SEL - Configures dead time generator %s clock selection.\\0: PWM_clk\\1: PT_clk - 17 - 1 - read-write - - - - - 3 - 0x38 - DT%s_FED_CFG - Falling edge delay (FED) shadow register - 0x5C - 0x20 - - - DB_FED - Configures shadow register for FED. - 0 - 16 - read-write - - - - - 3 - 0x38 - DT%s_RED_CFG - Rising edge delay (RED) shadow register - 0x60 - 0x20 - - - DB_RED - Configures shadow register for RED. - 0 - 16 - read-write - - - - - 3 - 0x38 - CARRIER%s_CFG - Carrier%s configuration register - 0x64 - 0x20 - - - CHOPPER_EN - Configures whether or not to enable carrier%s.\\0: Bypassed\\1: Enabled - 0 - 1 - read-write - - - CHOPPER_PRESCALE - Configures the prescale value of PWM carrier%s clock (PC_clk), so that period of PC_clk = period of PWM_clk * (PWM_CARRIER%s_PRESCALE + 1) - 1 - 4 - read-write - - - CHOPPER_DUTY - Configures carrier duty. Duty = PWM_CARRIER%s_DUTY / 8 - 5 - 3 - read-write - - - CHOPPER_OSHTWTH - Configures width of the first pulse. Measurement unit: Periods of the carrier. - 8 - 4 - read-write - - - CHOPPER_OUT_INVERT - Configures whether or not to invert the output of PWM%s A and PWM%s B for this submodule.\\0: Normal\\1: Invert - 12 - 1 - read-write - - - CHOPPER_IN_INVERT - Configures whether or not to invert the input of PWM%s A and PWM%s B for this submodule.\\0: Normal\\1: Invert - 13 - 1 - read-write - - - - - 3 - 0x38 - FH%s_CFG0 - PWM%s A and PWM%s B trip events actions configuration register - 0x68 - 0x20 - - - TZ_SW_CBC - Configures whether or not to enable software force cycle-by-cycle mode action.\\0: Disable\\1: Enable - 0 - 1 - read-write - - - TZ_F2_CBC - Configures whether or not event_f2 will trigger cycle-by-cycle mode action.\\0: Disable\\1: Enable - 1 - 1 - read-write - - - TZ_F1_CBC - Configures whether or not event_f1 will trigger cycle-by-cycle mode action.\\0: Disable\\1: Enable - 2 - 1 - read-write - - - TZ_F0_CBC - Configures whether or not event_f0 will trigger cycle-by-cycle mode action.\\0: Disable\\1: Enable - 3 - 1 - read-write - - - TZ_SW_OST - Configures whether or not to enable software force one-shot mode action.\\0: Disable\\1: Enable - 4 - 1 - read-write - - - TZ_F2_OST - Configures whether or not event_f2 will trigger one-shot mode action.\\0: Disable\\1: Enable - 5 - 1 - read-write - - - TZ_F1_OST - Configures whether or not event_f1 will trigger one-shot mode action.\\0: Disable\\1: Enable - 6 - 1 - read-write - - - TZ_F0_OST - Configures whether or not event_f0 will trigger one-shot mode action.\\0: Disable\\1: Enable - 7 - 1 - read-write - - - TZ_A_CBC_D - Configures cycle-by-cycle mode action on PWM%s A when fault event occurs and timer is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle - 8 - 2 - read-write - - - TZ_A_CBC_U - Configures cycle-by-cycle mode action on PWM%s A when fault event occurs and timer is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle - 10 - 2 - read-write - - - TZ_A_OST_D - Configures one-shot mode action on PWM%s A when fault event occurs and timer is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle - 12 - 2 - read-write - - - TZ_A_OST_U - Configures one-shot mode action on PWM%s A when fault event occurs and timer is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle - 14 - 2 - read-write - - - TZ_B_CBC_D - Configures cycle-by-cycle mode action on PWM%s B when fault event occurs and timer is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle - 16 - 2 - read-write - - - TZ_B_CBC_U - Configures cycle-by-cycle mode action on PWM%s B when fault event occurs and timer is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle - 18 - 2 - read-write - - - TZ_B_OST_D - Configures one-shot mode action on PWM%s B when fault event occurs and timer is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle - 20 - 2 - read-write - - - TZ_B_OST_U - Configures one-shot mode action on PWM%s B when fault event occurs and timer is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle - 22 - 2 - read-write - - - - - 3 - 0x38 - FH%s_CFG1 - Software triggers for fault handler actions configuration register - 0x6C - 0x20 - - - TZ_CLR_OST - Configures the generation of software one-shot mode action clear. A toggle (software negate its value) triggers a clear for on going one-shot mode action. - 0 - 1 - read-write - - - TZ_CBCPULSE - Configures the refresh moment selection of cycle-by-cycle mode action.\\0: Select nothing, will not refresh\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP - 1 - 2 - read-write - - - TZ_FORCE_CBC - Configures the generation of software cycle-by-cycle mode action. A toggle (software negate its value) triggers a cycle-by-cycle mode action. - 3 - 1 - read-write - - - TZ_FORCE_OST - Configures the generation of software one-shot mode action. A toggle (software negate its value) triggers a one-shot mode action. - 4 - 1 - read-write - - - - - 3 - 0x38 - FH%s_STATUS - Fault events status register - 0x70 - 0x20 - - - TZ_CBC_ON - Represents whether or not an cycle-by-cycle mode action is on going.\\0:No action\\1: On going - 0 - 1 - read-only - - - TZ_OST_ON - Represents whether or not an one-shot mode action is on going.\\0:No action\\1: On going - 1 - 1 - read-only - - - - - FAULT_DETECT - Fault detection configuration and status register - 0xE4 - 0x20 - - - F0_EN - Configures whether or not to enable event_f0 generation.\\0: Disable\\1: Enable - 0 - 1 - read-write - - - F1_EN - Configures whether or not to enable event_f1 generation.\\0: Disable\\1: Enable - 1 - 1 - read-write - - - F2_EN - Configures whether or not to enable event_f2 generation.\\0: Disable\\1: Enable - 2 - 1 - read-write - - - F0_POLE - Configures event_f0 trigger polarity on FAULT0 source from GPIO matrix.\\0: Level low\\1: Level high - 3 - 1 - read-write - - - F1_POLE - Configures event_f1 trigger polarity on FAULT1 source from GPIO matrix.\\0: Level low\\1: Level high - 4 - 1 - read-write - - - F2_POLE - Configures event_f2 trigger polarity on FAULT2 source from GPIO matrix.\\0: Level low\\1: Level high - 5 - 1 - read-write - - - EVENT_F0 - Represents whether or not an event_f0 is on going.\\0: No action\\1: On going - 6 - 1 - read-only - - - EVENT_F1 - Represents whether or not an event_f1 is on going.\\0: No action\\1: On going - 7 - 1 - read-only - - - EVENT_F2 - Represents whether or not an event_f2 is on going.\\0: No action\\1: On going - 8 - 1 - read-only - - - - - CAP_TIMER_CFG - Capture timer configuration register - 0xE8 - 0x20 - - - CAP_TIMER_EN - Configures whether or not to enable capture timer increment.\\0: Disable\\1: Enable - 0 - 1 - read-write - - - CAP_SYNCI_EN - Configures whether or not to enable capture timer sync.\\0: Disable\\1: Enable - 1 - 1 - read-write - - - CAP_SYNCI_SEL - Configures the selection of capture module sync input.\\0: None\\1: Timer0 sync_out\\2: Timer1 sync_out\\3: Timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1 from GPIO matrix\\6: SYNC2 from GPIO matrix\\7: None - 2 - 3 - read-write - - - CAP_SYNC_SW - Configures the generation of a capture timer sync when reg_cap_synci_en is 1.\\0: Invalid, No effect\\1: Trigger a capture timer sync, capture timer is loaded with value in phase register - 5 - 1 - write-only - - - - - CAP_TIMER_PHASE - Capture timer sync phase register - 0xEC - 0x20 - - - CAP_PHASE - Configures phase value for capture timer sync operation. - 0 - 32 - read-write - - - - - 3 - 0x4 - CAP_CH%s_CFG - Capture channel %s configuration register - 0xF0 - 0x20 - - - CAP_EN - Configures whether or not to enable capture on channel %s.\\0: Disable\\1: Enable - 0 - 1 - read-write - - - CAP_MODE - Configures which edge of capture on channel %s after prescaling is used.\\0: None\\Bit0 is set to 1: Rnable capture on the negative edge\\Bit1 is set to 1: Enable capture on the positive edge - 1 - 2 - read-write - - - CAP_PRESCALE - Configures prescale value on possitive edge of CAP%s. Prescale value = PWM_CAP%s_PRESCALE + 1 - 3 - 8 - read-write - - - CAP_IN_INVERT - Configures whether or not to invert CAP%s from GPIO matrix before prescale.\\0: Normal\\1: Invert - 11 - 1 - read-write - - - CAP_SW - Configures the generation of software capture.\\0: Invalid, No effect\\1: Trigger a software forced capture on channel %s - 12 - 1 - write-only - - - - - 3 - 0x4 - CAP_CH%s - CAP%s capture value register - 0xFC - 0x20 - - - CAP_VALUE - Represents value of last capture on CAP%s - 0 - 32 - read-only - - - - - CAP_STATUS - Last capture trigger edge information register - 0x108 - 0x20 - - - CAP0_EDGE - Represents edge of last capture trigger on channel0.\\0: Posedge\\1: Negedge - 0 - 1 - read-only - - - CAP1_EDGE - Represents edge of last capture trigger on channel1.\\0: Posedge\\1: Negedge - 1 - 1 - read-only - - - CAP2_EDGE - Represents edge of last capture trigger on channel2.\\0: Posedge\\1: Negedge - 2 - 1 - read-only - - - - - UPDATE_CFG - Generator Update configuration register - 0x10C - 0x20 - 0x00000005 - - - GLOBAL_UP_EN - Configures whether or not to enable global update for all active registers in MCPWM module.\\0: Disable\\1: Enable - 0 - 1 - read-write - - - GLOBAL_FORCE_UP - Configures the generation of global forced update for all active registers in MCPWM module. A toggle (software invert its value) will trigger a global forced update. Valid only when MCPWM_GLOBAL_UP_EN and MCPWM_OP0/1/2_UP_EN are both set to 1. - 1 - 1 - read-write - - - OP0_UP_EN - Configures whether or not to enable update of active registers in PWM operator0. Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable - 2 - 1 - read-write - - - OP0_FORCE_UP - Configures the generation of forced update for active registers in PWM operator0. A toggle (software invert its value) will trigger a forced update. Valid only when MCPWM_GLOBAL_UP_EN and MCPWM_OP0_UP_EN are both set to 1. - 3 - 1 - read-write - - - OP1_UP_EN - Configures whether or not to enable update of active registers in PWM operator1. Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable - 4 - 1 - read-write - - - OP1_FORCE_UP - Configures the generation of forced update for active registers in PWM operator1. A toggle (software invert its value) will trigger a forced update. Valid only when MCPWM_GLOBAL_UP_EN and MCPWM_OP1_UP_EN are both set to 1. - 5 - 1 - read-write - - - OP2_UP_EN - Configures whether or not to enable update of active registers in PWM operator2. Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable - 6 - 1 - read-write - - - OP2_FORCE_UP - Configures the generation of forced update for active registers in PWM operator2. A toggle (software invert its value) will trigger a forced update. Valid only when MCPWM_GLOBAL_UP_EN and MCPWM_OP2_UP_EN are both set to 1. - 7 - 1 - read-write - - - - - INT_ENA - Interrupt enable register - 0x110 - 0x20 - - - TIMER0_STOP_INT_ENA - Enable bit: Write 1 to enable the interrupt triggered when the timer 0 stops. - 0 - 1 - read-write - - - TIMER1_STOP_INT_ENA - Enable bit: Write 1 to enable the interrupt triggered when the timer 1 stops. - 1 - 1 - read-write - - - TIMER2_STOP_INT_ENA - Enable bit: Write 1 to enable the interrupt triggered when the timer 2 stops. - 2 - 1 - read-write - - - TIMER0_TEZ_INT_ENA - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEZ event. - 3 - 1 - read-write - - - TIMER1_TEZ_INT_ENA - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEZ event. - 4 - 1 - read-write - - - TIMER2_TEZ_INT_ENA - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEZ event. - 5 - 1 - read-write - - - TIMER0_TEP_INT_ENA - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEP event. - 6 - 1 - read-write - - - TIMER1_TEP_INT_ENA - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEP event. - 7 - 1 - read-write - - - TIMER2_TEP_INT_ENA - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEP event. - 8 - 1 - read-write - - - FAULT0_INT_ENA - Enable bit: Write 1 to enable the interrupt triggered when event_f0 starts. - 9 - 1 - read-write - - - FAULT1_INT_ENA - Enable bit: Write 1 to enable the interrupt triggered when event_f1 starts. - 10 - 1 - read-write - - - FAULT2_INT_ENA - Enable bit: Write 1 to enable the interrupt triggered when event_f2 starts. - 11 - 1 - read-write - - - FAULT0_CLR_INT_ENA - Enable bit: Write 1 to enable the interrupt triggered when event_f0 clears. - 12 - 1 - read-write - - - FAULT1_CLR_INT_ENA - Enable bit: Write 1 to enable the interrupt triggered when event_f1 clears. - 13 - 1 - read-write - - - FAULT2_CLR_INT_ENA - Enable bit: Write 1 to enable the interrupt triggered when event_f2 clears. - 14 - 1 - read-write - - - CMPR0_TEA_INT_ENA - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEA event. - 15 - 1 - read-write - - - CMPR1_TEA_INT_ENA - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEA event. - 16 - 1 - read-write - - - CMPR2_TEA_INT_ENA - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEA event. - 17 - 1 - read-write - - - CMPR0_TEB_INT_ENA - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEB event. - 18 - 1 - read-write - - - CMPR1_TEB_INT_ENA - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEB event. - 19 - 1 - read-write - - - CMPR2_TEB_INT_ENA - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEB event. - 20 - 1 - read-write - - - TZ0_CBC_INT_ENA - Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode action on PWM0. - 21 - 1 - read-write - - - TZ1_CBC_INT_ENA - Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode action on PWM1. - 22 - 1 - read-write - - - TZ2_CBC_INT_ENA - Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode action on PWM2. - 23 - 1 - read-write - - - TZ0_OST_INT_ENA - Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on PWM0. - 24 - 1 - read-write - - - TZ1_OST_INT_ENA - Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on PWM1. - 25 - 1 - read-write - - - TZ2_OST_INT_ENA - Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on PWM2. - 26 - 1 - read-write - - - CAP0_INT_ENA - Enable bit: Write 1 to enable the interrupt triggered by capture on CAP0. - 27 - 1 - read-write - - - CAP1_INT_ENA - Enable bit: Write 1 to enable the interrupt triggered by capture on CAP1. - 28 - 1 - read-write - - - CAP2_INT_ENA - Enable bit: Write 1 to enable the interrupt triggered by capture on CAP2. - 29 - 1 - read-write - - - - - INT_RAW - Interrupt raw status register - 0x114 - 0x20 - - - TIMER0_STOP_INT_RAW - Raw status bit: The raw interrupt status of the interrupt triggered when the timer 0 stops. - 0 - 1 - read-write - - - TIMER1_STOP_INT_RAW - Raw status bit: The raw interrupt status of the interrupt triggered when the timer 1 stops. - 1 - 1 - read-write - - - TIMER2_STOP_INT_RAW - Raw status bit: The raw interrupt status of the interrupt triggered when the timer 2 stops. - 2 - 1 - read-write - - - TIMER0_TEZ_INT_RAW - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 0 TEZ event. - 3 - 1 - read-write - - - TIMER1_TEZ_INT_RAW - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 1 TEZ event. - 4 - 1 - read-write - - - TIMER2_TEZ_INT_RAW - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 2 TEZ event. - 5 - 1 - read-write - - - TIMER0_TEP_INT_RAW - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 0 TEP event. - 6 - 1 - read-write - - - TIMER1_TEP_INT_RAW - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 1 TEP event. - 7 - 1 - read-write - - - TIMER2_TEP_INT_RAW - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 2 TEP event. - 8 - 1 - read-write - - - FAULT0_INT_RAW - Raw status bit: The raw interrupt status of the interrupt triggered when event_f0 starts. - 9 - 1 - read-write - - - FAULT1_INT_RAW - Raw status bit: The raw interrupt status of the interrupt triggered when event_f1 starts. - 10 - 1 - read-write - - - FAULT2_INT_RAW - Raw status bit: The raw interrupt status of the interrupt triggered when event_f2 starts. - 11 - 1 - read-write - - - FAULT0_CLR_INT_RAW - Raw status bit: The raw interrupt status of the interrupt triggered when event_f0 clears. - 12 - 1 - read-write - - - FAULT1_CLR_INT_RAW - Raw status bit: The raw interrupt status of the interrupt triggered when event_f1 clears. - 13 - 1 - read-write - - - FAULT2_CLR_INT_RAW - Raw status bit: The raw interrupt status of the interrupt triggered when event_f2 clears. - 14 - 1 - read-write - - - CMPR0_TEA_INT_RAW - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 0 TEA event - 15 - 1 - read-write - - - CMPR1_TEA_INT_RAW - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 1 TEA event - 16 - 1 - read-write - - - CMPR2_TEA_INT_RAW - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 2 TEA event - 17 - 1 - read-write - - - CMPR0_TEB_INT_RAW - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 0 TEB event - 18 - 1 - read-write - - - CMPR1_TEB_INT_RAW - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 1 TEB event - 19 - 1 - read-write - - - CMPR2_TEB_INT_RAW - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 2 TEB event - 20 - 1 - read-write - - - TZ0_CBC_INT_RAW - Raw status bit: The raw interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM0. - 21 - 1 - read-write - - - TZ1_CBC_INT_RAW - Raw status bit: The raw interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM1. - 22 - 1 - read-write - - - TZ2_CBC_INT_RAW - Raw status bit: The raw interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM2. - 23 - 1 - read-write - - - TZ0_OST_INT_RAW - Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot mode action on PWM0. - 24 - 1 - read-write - - - TZ1_OST_INT_RAW - Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot mode action on PWM1. - 25 - 1 - read-write - - - TZ2_OST_INT_RAW - Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot mode action on PWM2. - 26 - 1 - read-write - - - CAP0_INT_RAW - Raw status bit: The raw interrupt status of the interrupt triggered by capture on CAP0. - 27 - 1 - read-write - - - CAP1_INT_RAW - Raw status bit: The raw interrupt status of the interrupt triggered by capture on CAP1. - 28 - 1 - read-write - - - CAP2_INT_RAW - Raw status bit: The raw interrupt status of the interrupt triggered by capture on CAP2. - 29 - 1 - read-write - - - - - INT_ST - Interrupt masked status register - 0x118 - 0x20 - - - TIMER0_STOP_INT_ST - Masked status bit: The masked interrupt status of the interrupt triggered when the timer 0 stops. - 0 - 1 - read-only - - - TIMER1_STOP_INT_ST - Masked status bit: The masked interrupt status of the interrupt triggered when the timer 1 stops. - 1 - 1 - read-only - - - TIMER2_STOP_INT_ST - Masked status bit: The masked interrupt status of the interrupt triggered when the timer 2 stops. - 2 - 1 - read-only - - - TIMER0_TEZ_INT_ST - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 0 TEZ event. - 3 - 1 - read-only - - - TIMER1_TEZ_INT_ST - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 1 TEZ event. - 4 - 1 - read-only - - - TIMER2_TEZ_INT_ST - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 2 TEZ event. - 5 - 1 - read-only - - - TIMER0_TEP_INT_ST - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 0 TEP event. - 6 - 1 - read-only - - - TIMER1_TEP_INT_ST - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 1 TEP event. - 7 - 1 - read-only - - - TIMER2_TEP_INT_ST - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 2 TEP event. - 8 - 1 - read-only - - - FAULT0_INT_ST - Masked status bit: The masked interrupt status of the interrupt triggered when event_f0 starts. - 9 - 1 - read-only - - - FAULT1_INT_ST - Masked status bit: The masked interrupt status of the interrupt triggered when event_f1 starts. - 10 - 1 - read-only - - - FAULT2_INT_ST - Masked status bit: The masked interrupt status of the interrupt triggered when event_f2 starts. - 11 - 1 - read-only - - - FAULT0_CLR_INT_ST - Masked status bit: The masked interrupt status of the interrupt triggered when event_f0 clears. - 12 - 1 - read-only - - - FAULT1_CLR_INT_ST - Masked status bit: The masked interrupt status of the interrupt triggered when event_f1 clears. - 13 - 1 - read-only - - - FAULT2_CLR_INT_ST - Masked status bit: The masked interrupt status of the interrupt triggered when event_f2 clears. - 14 - 1 - read-only - - - CMPR0_TEA_INT_ST - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 0 TEA event - 15 - 1 - read-only - - - CMPR1_TEA_INT_ST - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 1 TEA event - 16 - 1 - read-only - - - CMPR2_TEA_INT_ST - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 2 TEA event - 17 - 1 - read-only - - - CMPR0_TEB_INT_ST - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 0 TEB event - 18 - 1 - read-only - - - CMPR1_TEB_INT_ST - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 1 TEB event - 19 - 1 - read-only - - - CMPR2_TEB_INT_ST - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 2 TEB event - 20 - 1 - read-only - - - TZ0_CBC_INT_ST - Masked status bit: The masked interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM0. - 21 - 1 - read-only - - - TZ1_CBC_INT_ST - Masked status bit: The masked interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM1. - 22 - 1 - read-only - - - TZ2_CBC_INT_ST - Masked status bit: The masked interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM2. - 23 - 1 - read-only - - - TZ0_OST_INT_ST - Masked status bit: The masked interrupt status of the interrupt triggered by a one-shot mode action on PWM0. - 24 - 1 - read-only - - - TZ1_OST_INT_ST - Masked status bit: The masked interrupt status of the interrupt triggered by a one-shot mode action on PWM1. - 25 - 1 - read-only - - - TZ2_OST_INT_ST - Masked status bit: The masked interrupt status of the interrupt triggered by a one-shot mode action on PWM2. - 26 - 1 - read-only - - - CAP0_INT_ST - Masked status bit: The masked interrupt status of the interrupt triggered by capture on CAP0. - 27 - 1 - read-only - - - CAP1_INT_ST - Masked status bit: The masked interrupt status of the interrupt triggered by capture on CAP1. - 28 - 1 - read-only - - - CAP2_INT_ST - Masked status bit: The masked interrupt status of the interrupt triggered by capture on CAP2. - 29 - 1 - read-only - - - - - INT_CLR - Interrupt clear register - 0x11C - 0x20 - - - TIMER0_STOP_INT_CLR - Clear bit: Write 1 to clear the interrupt triggered when the timer 0 stops. - 0 - 1 - write-only - - - TIMER1_STOP_INT_CLR - Clear bit: Write 1 to clear the interrupt triggered when the timer 1 stops. - 1 - 1 - write-only - - - TIMER2_STOP_INT_CLR - Clear bit: Write 1 to clear the interrupt triggered when the timer 2 stops. - 2 - 1 - write-only - - - TIMER0_TEZ_INT_CLR - Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEZ event. - 3 - 1 - write-only - - - TIMER1_TEZ_INT_CLR - Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEZ event. - 4 - 1 - write-only - - - TIMER2_TEZ_INT_CLR - Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEZ event. - 5 - 1 - write-only - - - TIMER0_TEP_INT_CLR - Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEP event. - 6 - 1 - write-only - - - TIMER1_TEP_INT_CLR - Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEP event. - 7 - 1 - write-only - - - TIMER2_TEP_INT_CLR - Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEP event. - 8 - 1 - write-only - - - FAULT0_INT_CLR - Clear bit: Write 1 to clear the interrupt triggered when event_f0 starts. - 9 - 1 - write-only - - - FAULT1_INT_CLR - Clear bit: Write 1 to clear the interrupt triggered when event_f1 starts. - 10 - 1 - write-only - - - FAULT2_INT_CLR - Clear bit: Write 1 to clear the interrupt triggered when event_f2 starts. - 11 - 1 - write-only - - - FAULT0_CLR_INT_CLR - Clear bit: Write 1 to clear the interrupt triggered when event_f0 clears. - 12 - 1 - write-only - - - FAULT1_CLR_INT_CLR - Clear bit: Write 1 to clear the interrupt triggered when event_f1 clears. - 13 - 1 - write-only - - - FAULT2_CLR_INT_CLR - Clear bit: Write 1 to clear the interrupt triggered when event_f2 clears. - 14 - 1 - write-only - - - CMPR0_TEA_INT_CLR - Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEA event - 15 - 1 - write-only - - - CMPR1_TEA_INT_CLR - Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEA event - 16 - 1 - write-only - - - CMPR2_TEA_INT_CLR - Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEA event - 17 - 1 - write-only - - - CMPR0_TEB_INT_CLR - Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEB event - 18 - 1 - write-only - - - CMPR1_TEB_INT_CLR - Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEB event - 19 - 1 - write-only - - - CMPR2_TEB_INT_CLR - Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEB event - 20 - 1 - write-only - - - TZ0_CBC_INT_CLR - Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action on PWM0. - 21 - 1 - write-only - - - TZ1_CBC_INT_CLR - Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action on PWM1. - 22 - 1 - write-only - - - TZ2_CBC_INT_CLR - Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action on PWM2. - 23 - 1 - write-only - - - TZ0_OST_INT_CLR - Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on PWM0. - 24 - 1 - write-only - - - TZ1_OST_INT_CLR - Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on PWM1. - 25 - 1 - write-only - - - TZ2_OST_INT_CLR - Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on PWM2. - 26 - 1 - write-only - - - CAP0_INT_CLR - Clear bit: Write 1 to clear the interrupt triggered by capture on CAP0. - 27 - 1 - write-only - - - CAP1_INT_CLR - Clear bit: Write 1 to clear the interrupt triggered by capture on CAP1. - 28 - 1 - write-only - - - CAP2_INT_CLR - Clear bit: Write 1 to clear the interrupt triggered by capture on CAP2. - 29 - 1 - write-only - - - - - EVT_EN - Event enable register - 0x120 - 0x20 - - - EVT_TIMER0_STOP_EN - Configures whether or not to enable timer0 stop event generate.\\0: Disable\\1: Enable - 0 - 1 - read-write - - - EVT_TIMER1_STOP_EN - Configures whether or not to enable timer1 stop event generate.\\0: Disable\\1: Enable - 1 - 1 - read-write - - - EVT_TIMER2_STOP_EN - Configures whether or not to enable timer2 stop event generate.\\0: Disable\\1: Enable - 2 - 1 - read-write - - - EVT_TIMER0_TEZ_EN - Configures whether or not to enable timer0 equal zero event generate.\\0: Disable\\1: Enable - 3 - 1 - read-write - - - EVT_TIMER1_TEZ_EN - Configures whether or not to enable timer1 equal zero event generate.\\0: Disable\\1: Enable - 4 - 1 - read-write - - - EVT_TIMER2_TEZ_EN - Configures whether or not to enable timer2 equal zero event generate.\\0: Disable\\1: Enable - 5 - 1 - read-write - - - EVT_TIMER0_TEP_EN - Configures whether or not to enable timer0 equal period event generate.\\0: Disable\\1: Enable - 6 - 1 - read-write - - - EVT_TIMER1_TEP_EN - Configures whether or not to enable timer1 equal period event generate.\\0: Disable\\1: Enable - 7 - 1 - read-write - - - EVT_TIMER2_TEP_EN - Configures whether or not to enable timer2 equal period event generate.\\0: Disable\\1: Enable - 8 - 1 - read-write - - - EVT_OP0_TEA_EN - Configures whether or not to enable PWM generator0 timer equal a event generate.\\0: Disable\\1: Enable - 9 - 1 - read-write - - - EVT_OP1_TEA_EN - Configures whether or not to enable PWM generator1 timer equal a event generate.\\0: Disable\\1: Enable - 10 - 1 - read-write - - - EVT_OP2_TEA_EN - Configures whether or not to enable PWM generator2 timer equal a event generate.\\0: Disable\\1: Enable - 11 - 1 - read-write - - - EVT_OP0_TEB_EN - Configures whether or not to enable PWM generator0 timer equal b event generate.\\0: Disable\\1: Enable - 12 - 1 - read-write - - - EVT_OP1_TEB_EN - Configures whether or not to enable PWM generator1 timer equal b event generate.\\0: Disable\\1: Enable - 13 - 1 - read-write - - - EVT_OP2_TEB_EN - Configures whether or not to enable PWM generator2 timer equal b event generate.\\0: Disable\\1: Enable - 14 - 1 - read-write - - - EVT_F0_EN - Configures whether or not to enable fault0 event generate.\\0: Disable\\1: Enable - 15 - 1 - read-write - - - EVT_F1_EN - Configures whether or not to enable fault1 event generate.\\0: Disable\\1: Enable - 16 - 1 - read-write - - - EVT_F2_EN - Configures whether or not to enable fault2 event generate.\\0: Disable\\1: Enable - 17 - 1 - read-write - - - EVT_F0_CLR_EN - Configures whether or not to enable fault0 clear event generate.\\0: Disable\\1: Enable - 18 - 1 - read-write - - - EVT_F1_CLR_EN - Configures whether or not to enable fault1 clear event generate.\\0: Disable\\1: Enable - 19 - 1 - read-write - - - EVT_F2_CLR_EN - Configures whether or not to enable fault2 clear event generate.\\0: Disable\\1: Enable - 20 - 1 - read-write - - - EVT_TZ0_CBC_EN - Configures whether or not to enable cycle-by-cycle trip0 event generate.\\0: Disable\\1: Enable - 21 - 1 - read-write - - - EVT_TZ1_CBC_EN - Configures whether or not to enable cycle-by-cycle trip1 event generate.\\0: Disable\\1: Enable - 22 - 1 - read-write - - - EVT_TZ2_CBC_EN - Configures whether or not to enable cycle-by-cycle trip2 event generate.\\0: Disable\\1: Enable - 23 - 1 - read-write - - - EVT_TZ0_OST_EN - Configures whether or not to enable one-shot trip0 event generate.\\0: Disable\\1: Enable - 24 - 1 - read-write - - - EVT_TZ1_OST_EN - Configures whether or not to enable one-shot trip1 event generate.\\0: Disable\\1: Enable - 25 - 1 - read-write - - - EVT_TZ2_OST_EN - Configures whether or not to enable one-shot trip2 event generate.\\0: Disable\\1: Enable - 26 - 1 - read-write - - - EVT_CAP0_EN - Configures whether or not to enable capture0 event generate.\\0: Disable\\1: Enable - 27 - 1 - read-write - - - EVT_CAP1_EN - Configures whether or not to enable capture1 event generate.\\0: Disable\\1: Enable - 28 - 1 - read-write - - - EVT_CAP2_EN - Configures whether or not to enable capture2 event generate.\\0: Disable\\1: Enable - 29 - 1 - read-write - - - - - TASK_EN - Task enable register - 0x124 - 0x20 - - - TASK_CMPR0_A_UP_EN - Configures whether or not to enable PWM generator0 timer stamp A's shadow register update task receive.\\0: Disable\\1: Enable - 0 - 1 - read-write - - - TASK_CMPR1_A_UP_EN - Configures whether or not to enable PWM generator1 timer stamp A's shadow register update task receive.\\0: Disable\\1: Enable - 1 - 1 - read-write - - - TASK_CMPR2_A_UP_EN - Configures whether or not to enable PWM generator2 timer stamp A's shadow register update task receive.\\0: Disable\\1: Enable - 2 - 1 - read-write - - - TASK_CMPR0_B_UP_EN - Configures whether or not to enable PWM generator0 timer stamp B's shadow register update task receive.\\0: Disable\\1: Enable - 3 - 1 - read-write - - - TASK_CMPR1_B_UP_EN - Configures whether or not to enable PWM generator1 timer stamp B's shadow register update task receive.\\0: Disable\\1: Enable - 4 - 1 - read-write - - - TASK_CMPR2_B_UP_EN - Configures whether or not to enable PWM generator2 timer stamp B's shadow register update task receive.\\0: Disable\\1: Enable - 5 - 1 - read-write - - - TASK_GEN_STOP_EN - Configures whether or not to enable all PWM generate stop task receive.\\0: Disable\\1: Enable - 6 - 1 - read-write - - - TASK_TIMER0_SYNC_EN - Configures whether or not to enable timer0 sync task receive.\\0: Disable\\1: Enable - 7 - 1 - read-write - - - TASK_TIMER1_SYNC_EN - Configures whether or not to enable timer1 sync task receive.\\0: Disable\\1: Enable - 8 - 1 - read-write - - - TASK_TIMER2_SYNC_EN - Configures whether or not to enable timer2 sync task receive.\\0: Disable\\1: Enable - 9 - 1 - read-write - - - TASK_TIMER0_PERIOD_UP_EN - Configures whether or not to enable timer0 period update task receive.\\0: Disable\\1: Enable - 10 - 1 - read-write - - - TASK_TIMER1_PERIOD_UP_EN - Configures whether or not to enable timer1 period update task receive.\\0: Disable\\1: Enable - 11 - 1 - read-write - - - TASK_TIMER2_PERIOD_UP_EN - Configures whether or not to enable timer2 period update task receive.\\0: Disable\\1: Enable - 12 - 1 - read-write - - - TASK_TZ0_OST_EN - Configures whether or not to enable one shot trip0 task receive.\\0: Disable\\1: Enable - 13 - 1 - read-write - - - TASK_TZ1_OST_EN - Configures whether or not to enable one shot trip1 task receive.\\0: Disable\\1: Enable - 14 - 1 - read-write - - - TASK_TZ2_OST_EN - Configures whether or not to enable one shot trip2 task receive.\\0: Disable\\1: Enable - 15 - 1 - read-write - - - TASK_CLR0_OST_EN - Configures whether or not to enable one shot trip0 clear task receive.\\0: Disable\\1: Enable - 16 - 1 - read-write - - - TASK_CLR1_OST_EN - Configures whether or not to enable one shot trip1 clear task receive.\\0: Disable\\1: Enable - 17 - 1 - read-write - - - TASK_CLR2_OST_EN - Configures whether or not to enable one shot trip2 clear task receive.\\0: Disable\\1: Enable - 18 - 1 - read-write - - - TASK_CAP0_EN - Configures whether or not to enable capture0 task receive.\\0: Disable\\1: Enable - 19 - 1 - read-write - - - TASK_CAP1_EN - Configures whether or not to enable capture1 task receive.\\0: Disable\\1: Enable - 20 - 1 - read-write - - - TASK_CAP2_EN - Configures whether or not to enable capture2 task receive.\\0: Disable\\1: Enable - 21 - 1 - read-write - - - - - EVT_EN2 - Event enable register2 - 0x128 - 0x20 - - - EVT_OP0_TEE1_EN - Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E1_REG event generate.\\0: Disable\\1: Enable - 0 - 1 - read-write - - - EVT_OP1_TEE1_EN - Configures whether or not to enable PWM generator1 timer equal OP1_TSTMP_E1_REG event generate.\\0: Disable\\1: Enable - 1 - 1 - read-write - - - EVT_OP2_TEE1_EN - Configures whether or not to enable PWM generator2 timer equal OP2_TSTMP_E1_REG event generate.\\0: Disable\\1: Enable - 2 - 1 - read-write - - - EVT_OP0_TEE2_EN - Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E2_REG event generate.\\0: Disable\\1: Enable - 3 - 1 - read-write - - - EVT_OP1_TEE2_EN - Configures whether or not to enable PWM generator1 timer equal OP1_TSTMP_E2_REG event generate.\\0: Disable\\1: Enable - 4 - 1 - read-write - - - EVT_OP2_TEE2_EN - Configures whether or not to enable PWM generator2 timer equal OP2_TSTMP_E2_REG event generate.\\0: Disable\\1: Enable - 5 - 1 - read-write - - - - - 3 - 0x8 - OP%s_TSTMP_E1 - Generator%s timer stamp E1 value register - 0x12C - 0x20 - - - OP_TSTMP_E1 - Configures generator%s timer stamp E1 value register - 0 - 16 - read-write - - - - - 3 - 0x8 - OP%s_TSTMP_E2 - Generator%s timer stamp E2 value register - 0x130 - 0x20 - - - OP_TSTMP_E2 - Configures generator%s timer stamp E2 value register - 0 - 16 - read-write - - - - - CLK - Global configuration register - 0x144 - 0x20 - - - EN - Configures whether or not to open register clock gate.\\0: Open the clock gate only when application writes registers\\1: Force open the clock gate for register - 0 - 1 - read-write - - - - - VERSION - Version register. - 0x148 - 0x20 - 0x02212290 - - - DATE - Configures the version. - 0 - 28 - read-write - - - - - - - MCPWM1 - Motor Control Pulse-Width Modulation 1 - 0x500C1000 - - PWM1 - 39 - - - - PARL_IO - Parallel IO Controller - PARL_IO - 0x500CF000 - - 0x0 - 0x54 - registers - - - PARLIO_RX - 113 - - - PARLIO_TX - 114 - - - - RX_MODE_CFG - Parallel RX Sampling mode configuration register. - 0x0 - 0x20 - 0x00E00000 - - - RX_EXT_EN_SEL - Configures rx external enable signal selection from IO PAD. - 21 - 4 - read-write - - - RX_SW_EN - Set this bit to enable data sampling by software. - 25 - 1 - read-write - - - RX_EXT_EN_INV - Set this bit to invert the external enable signal. - 26 - 1 - read-write - - - RX_PULSE_SUBMODE_SEL - Configures the rxd pulse sampling submode. -4'd0: positive pulse start(data bit included) && positive pulse end(data bit included) -4'd1: positive pulse start(data bit included) && positive pulse end (data bit excluded) -4'd2: positive pulse start(data bit excluded) && positive pulse end (data bit included) -4'd3: positive pulse start(data bit excluded) && positive pulse end (data bit excluded) -4'd4: positive pulse start(data bit included) && length end -4'd5: positive pulse start(data bit excluded) && length end - 27 - 3 - read-write - - - RX_SMP_MODE_SEL - Configures the rxd sampling mode. -2'b00: external level enable mode -2'b01: external pulse enable mode -2'b10: internal software enable mode - 30 - 2 - read-write - - - - - RX_DATA_CFG - Parallel RX data configuration register. - 0x4 - 0x20 - 0x60000000 - - - RX_BITLEN - Configures expected byte number of received data. - 9 - 19 - read-write - - - RX_DATA_ORDER_INV - Set this bit to invert bit order of one byte sent from RX_FIFO to DMA. - 28 - 1 - read-write - - - RX_BUS_WID_SEL - Configures the rxd bus width. -3'd0: bus width is 1. -3'd1: bus width is 2. -3'd2: bus width is 4. -3'd3: bus width is 8. - 29 - 3 - read-write - - - - - RX_GENRL_CFG - Parallel RX general configuration register. - 0x8 - 0x20 - 0x21FFE000 - - - RX_GATING_EN - Set this bit to enable the clock gating of output rx clock. - 12 - 1 - read-write - - - RX_TIMEOUT_THRES - Configures threshold of timeout counter. - 13 - 16 - read-write - - - RX_TIMEOUT_EN - Set this bit to enable timeout function to generate error eof. - 29 - 1 - read-write - - - RX_EOF_GEN_SEL - Configures the DMA eof generated mechanism. 1'b0: eof generated by data bit length. 1'b1: eof generated by external enable signal. - 30 - 1 - read-write - - - - - RX_START_CFG - Parallel RX Start configuration register. - 0xC - 0x20 - - - RX_START - Set this bit to start rx data sampling. - 31 - 1 - read-write - - - - - TX_DATA_CFG - Parallel TX data configuration register. - 0x10 - 0x20 - 0x60000000 - - - TX_BITLEN - Configures expected byte number of sent data. - 9 - 19 - read-write - - - TX_DATA_ORDER_INV - Set this bit to invert bit order of one byte sent from TX_FIFO to IO data. - 28 - 1 - read-write - - - TX_BUS_WID_SEL - Configures the txd bus width. -3'd0: bus width is 1. -3'd1: bus width is 2. -3'd2: bus width is 4. -3'd3: bus width is 8. - 29 - 3 - read-write - - - - - TX_START_CFG - Parallel TX Start configuration register. - 0x14 - 0x20 - - - TX_START - Set this bit to start tx data transmit. - 31 - 1 - read-write - - - - - TX_GENRL_CFG - Parallel TX general configuration register. - 0x18 - 0x20 - - - TX_EOF_GEN_SEL - Configures the tx eof generated mechanism. 1'b0: eof generated by data bit length. 1'b1: eof generated by DMA eof. - 13 - 1 - read-write - - - TX_IDLE_VALUE - Configures bus value of transmitter in IDLE state. - 14 - 16 - read-write - - - TX_GATING_EN - Set this bit to enable the clock gating of output tx clock. - 30 - 1 - read-write - - - TX_VALID_OUTPUT_EN - Set this bit to enable the output of tx data valid signal. - 31 - 1 - read-write - - - - - FIFO_CFG - Parallel IO FIFO configuration register. - 0x1C - 0x20 - - - TX_FIFO_SRST - Set this bit to reset async fifo in tx module. - 30 - 1 - read-write - - - RX_FIFO_SRST - Set this bit to reset async fifo in rx module. - 31 - 1 - read-write - - - - - REG_UPDATE - Parallel IO FIFO configuration register. - 0x20 - 0x20 - - - RX_REG_UPDATE - Set this bit to update rx register configuration. - 31 - 1 - write-only - - - - - ST - Parallel IO module status register0. - 0x24 - 0x20 - - - TX_READY - Represents the status that tx is ready to transmit. - 31 - 1 - read-only - - - - - INT_ENA - Parallel IO interrupt enable singal configuration register. - 0x28 - 0x20 - - - TX_FIFO_REMPTY_INT_ENA - Set this bit to enable TX_FIFO_REMPTY_INT. - 0 - 1 - read-write - - - RX_FIFO_WOVF_INT_ENA - Set this bit to enable RX_FIFO_WOVF_INT. - 1 - 1 - read-write - - - TX_EOF_INT_ENA - Set this bit to enable TX_EOF_INT. - 2 - 1 - read-write - - - - - INT_RAW - Parallel IO interrupt raw singal status register. - 0x2C - 0x20 - - - TX_FIFO_REMPTY_INT_RAW - The raw interrupt status of TX_FIFO_REMPTY_INT. - 0 - 1 - read-write - - - RX_FIFO_WOVF_INT_RAW - The raw interrupt status of RX_FIFO_WOVF_INT. - 1 - 1 - read-write - - - TX_EOF_INT_RAW - The raw interrupt status of TX_EOF_INT. - 2 - 1 - read-write - - - - - INT_ST - Parallel IO interrupt singal status register. - 0x30 - 0x20 - - - TX_FIFO_REMPTY_INT_ST - The masked interrupt status of TX_FIFO_REMPTY_INT. - 0 - 1 - read-only - - - RX_FIFO_WOVF_INT_ST - The masked interrupt status of RX_FIFO_WOVF_INT. - 1 - 1 - read-only - - - TX_EOF_INT_ST - The masked interrupt status of TX_EOF_INT. - 2 - 1 - read-only - - - - - INT_CLR - Parallel IO interrupt clear singal configuration register. - 0x34 - 0x20 - - - TX_FIFO_REMPTY_INT_CLR - Set this bit to clear TX_FIFO_REMPTY_INT. - 0 - 1 - write-only - - - RX_FIFO_WOVF_INT_CLR - Set this bit to clear RX_FIFO_WOVF_INT. - 1 - 1 - write-only - - - TX_EOF_INT_CLR - Set this bit to clear TX_EOF_INT. - 2 - 1 - write-only - - - - - RX_ST0 - Parallel IO RX status register0 - 0x38 - 0x20 - - - RX_CNT - Indicates the cycle number of reading Rx FIFO. - 8 - 5 - read-only - - - RX_FIFO_WR_BIT_CNT - Indicates the current written bit number into Rx FIFO. - 13 - 19 - read-only - - - - - RX_ST1 - Parallel IO RX status register1 - 0x3C - 0x20 - - - RX_FIFO_RD_BIT_CNT - Indicates the current read bit number from Rx FIFO. - 13 - 19 - read-only - - - - - TX_ST0 - Parallel IO TX status register0 - 0x40 - 0x20 - - - TX_CNT - Indicates the cycle number of reading Tx FIFO. - 6 - 7 - read-only - - - TX_FIFO_RD_BIT_CNT - Indicates the current read bit number from Tx FIFO. - 13 - 19 - read-only - - - - - RX_CLK_CFG - Parallel IO RX clk configuration register - 0x44 - 0x20 - - - RX_CLK_I_INV - Set this bit to invert the input Rx core clock. - 30 - 1 - read-write - - - RX_CLK_O_INV - Set this bit to invert the output Rx core clock. - 31 - 1 - read-write - - - - - TX_CLK_CFG - Parallel IO TX clk configuration register - 0x48 - 0x20 - - - TX_CLK_I_INV - Set this bit to invert the input Tx core clock. - 30 - 1 - read-write - - - TX_CLK_O_INV - Set this bit to invert the output Tx core clock. - 31 - 1 - read-write - - - - - CLK - Parallel IO clk configuration register - 0x120 - 0x20 - - - EN - Force clock on for this register file - 31 - 1 - read-write - - - - - VERSION - Version register. - 0x3FC - 0x20 - 0x02212260 - - - DATE - Version of this register file - 0 - 28 - read-write - - - - - - - PAU - PAU Peripheral - PAU - 0x60093000 - - 0x0 - 0x44 - registers - - - PAU - 112 - - - - REGDMA_CONF - Peri backup control register - 0x0 - 0x20 - - - FLOW_ERR - backup error type - 0 - 3 - read-only - - - START - backup start signal - 3 - 1 - write-only - - - TO_MEM - backup direction(reg to mem / mem to reg) - 4 - 1 - read-write - - - LINK_SEL - Link select - 5 - 2 - read-write - - - START_MAC - mac sw backup start signal - 7 - 1 - write-only - - - TO_MEM_MAC - mac sw backup direction(reg to mem / mem to reg) - 8 - 1 - read-write - - - SEL_MAC - mac hw/sw select - 9 - 1 - read-write - - - - - REGDMA_CLK_CONF - Clock control register - 0x4 - 0x20 - - - CLK_EN - clock enable - 0 - 1 - read-write - - - - - REGDMA_ETM_CTRL - ETM start ctrl reg - 0x8 - 0x20 - - - ETM_START_0 - etm_start_0 reg - 0 - 1 - write-only - - - ETM_START_1 - etm_start_1 reg - 1 - 1 - write-only - - - ETM_START_2 - etm_start_2 reg - 2 - 1 - write-only - - - ETM_START_3 - etm_start_3 reg - 3 - 1 - write-only - - - - - REGDMA_LINK_0_ADDR - link_0_addr - 0xC - 0x20 - - - LINK_ADDR_0 - link_0_addr reg - 0 - 32 - read-write - - - - - REGDMA_LINK_1_ADDR - Link_1_addr - 0x10 - 0x20 - - - LINK_ADDR_1 - Link_1_addr reg - 0 - 32 - read-write - - - - - REGDMA_LINK_2_ADDR - Link_2_addr - 0x14 - 0x20 - - - LINK_ADDR_2 - Link_2_addr reg - 0 - 32 - read-write - - - - - REGDMA_LINK_3_ADDR - Link_3_addr - 0x18 - 0x20 - - - LINK_ADDR_3 - Link_3_addr reg - 0 - 32 - read-write - - - - - REGDMA_LINK_MAC_ADDR - Link_mac_addr - 0x1C - 0x20 - - - LINK_ADDR_MAC - Link_mac_addr reg - 0 - 32 - read-write - - - - - REGDMA_CURRENT_LINK_ADDR - current link addr - 0x20 - 0x20 - - - CURRENT_LINK_ADDR - current link addr reg - 0 - 32 - read-only - - - - - REGDMA_BACKUP_ADDR - Backup addr - 0x24 - 0x20 - - - BACKUP_ADDR - backup addr reg - 0 - 32 - read-only - - - - - REGDMA_MEM_ADDR - mem addr - 0x28 - 0x20 - - - MEM_ADDR - mem addr reg - 0 - 32 - read-only - - - - - REGDMA_BKP_CONF - backup config - 0x2C - 0x20 - 0x7D101920 - - - READ_INTERVAL - Link read_interval - 0 - 7 - read-write - - - LINK_TOUT_THRES - link wait timeout threshold - 7 - 10 - read-write - - - BURST_LIMIT - burst limit - 17 - 5 - read-write - - - BACKUP_TOUT_THRES - Backup timeout threshold - 22 - 10 - read-write - - - - - INT_ENA - Read only register for error and done - 0x30 - 0x20 - - - DONE_INT_ENA - backup done flag - 0 - 1 - read-write - - - ERROR_INT_ENA - error flag - 1 - 1 - read-write - - - - - INT_RAW - Read only register for error and done - 0x34 - 0x20 - - - DONE_INT_RAW - backup done flag - 0 - 1 - read-write - - - ERROR_INT_RAW - error flag - 1 - 1 - read-write - - - - - INT_CLR - Read only register for error and done - 0x38 - 0x20 - - - DONE_INT_CLR - backup done flag - 0 - 1 - write-only - - - ERROR_INT_CLR - error flag - 1 - 1 - write-only - - - - - INT_ST - Read only register for error and done - 0x3C - 0x20 - - - DONE_INT_ST - backup done flag - 0 - 1 - read-only - - - ERROR_INT_ST - error flag - 1 - 1 - read-only - - - - - DATE - Date register. - 0x3FC - 0x20 - 0x02203070 - - - DATE - REGDMA date information/ REGDMA version information. - 0 - 28 - read-write - - - - - - - PCNT - Pulse Count Controller - PCNT - 0x500C9000 - - 0x0 - 0x78 - registers - - - PCNT - 111 - - - - 4 - 0xC - U%s_CONF0 - Configuration register 0 for unit %s - 0x0 - 0x20 - 0x00003C10 - - - FILTER_THRES_U - This sets the maximum threshold, in APB_CLK cycles, for the filter. - -Any pulses with width less than this will be ignored when the filter is enabled. - 0 - 10 - read-write - - - FILTER_EN_U - This is the enable bit for unit %s's input filter. - 10 - 1 - read-write - - - THR_ZERO_EN_U - This is the enable bit for unit %s's zero comparator. - 11 - 1 - read-write - - - THR_H_LIM_EN_U - This is the enable bit for unit %s's thr_h_lim comparator. Configures it to enable the high limit interrupt. - 12 - 1 - read-write - - - THR_L_LIM_EN_U - This is the enable bit for unit %s's thr_l_lim comparator. Configures it to enable the low limit interrupt. - 13 - 1 - read-write - - - THR_THRES0_EN_U - This is the enable bit for unit %s's thres0 comparator. - 14 - 1 - read-write - - - THR_THRES1_EN_U - This is the enable bit for unit %s's thres1 comparator. - 15 - 1 - read-write - - - CH0_NEG_MODE_U - This register sets the behavior when the signal input of channel 0 detects a negative edge. - -1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter - 16 - 2 - read-write - - - CH0_POS_MODE_U - This register sets the behavior when the signal input of channel 0 detects a positive edge. - -1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter - 18 - 2 - read-write - - - CH0_HCTRL_MODE_U - This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high. - -0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification - 20 - 2 - read-write - - - CH0_LCTRL_MODE_U - This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low. - -0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification - 22 - 2 - read-write - - - CH1_NEG_MODE_U - This register sets the behavior when the signal input of channel 1 detects a negative edge. - -1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter - 24 - 2 - read-write - - - CH1_POS_MODE_U - This register sets the behavior when the signal input of channel 1 detects a positive edge. - -1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter - 26 - 2 - read-write - - - CH1_HCTRL_MODE_U - This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high. - -0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification - 28 - 2 - read-write - - - CH1_LCTRL_MODE_U - This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low. - -0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification - 30 - 2 - read-write - - - - - 4 - 0xC - U%s_CONF1 - Configuration register 1 for unit %s - 0x4 - 0x20 - - - CNT_THRES0_U - This register is used to configure the thres0 value for unit %s. - 0 - 16 - read-write - - - CNT_THRES1_U - This register is used to configure the thres1 value for unit %s. - 16 - 16 - read-write - - - - - 4 - 0xC - U%s_CONF2 - Configuration register 2 for unit %s - 0x8 - 0x20 - - - CNT_H_LIM_U - This register is used to configure the thr_h_lim value for unit %s. When pcnt reaches this value, the counter will be cleared to 0. - 0 - 16 - read-write - - - CNT_L_LIM_U - This register is used to configure the thr_l_lim value for unit %s. When pcnt reaches this value, the counter will be cleared to 0. - 16 - 16 - read-write - - - - - 4 - 0x4 - U%s_CNT - Counter value for unit %s - 0x30 - 0x20 - - - PULSE_CNT_U - This register stores the current pulse count value for unit %s. - 0 - 16 - read-only - - - - - INT_RAW - Interrupt raw status register - 0x40 - 0x20 - - - CNT_THR_EVENT_U0_INT_RAW - The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. - 0 - 1 - read-write - - - CNT_THR_EVENT_U1_INT_RAW - The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. - 1 - 1 - read-write - - - CNT_THR_EVENT_U2_INT_RAW - The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. - 2 - 1 - read-write - - - CNT_THR_EVENT_U3_INT_RAW - The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. - 3 - 1 - read-write - - - - - INT_ST - Interrupt status register - 0x44 - 0x20 - - - CNT_THR_EVENT_U0_INT_ST - The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. - 0 - 1 - read-only - - - CNT_THR_EVENT_U1_INT_ST - The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. - 1 - 1 - read-only - - - CNT_THR_EVENT_U2_INT_ST - The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. - 2 - 1 - read-only - - - CNT_THR_EVENT_U3_INT_ST - The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. - 3 - 1 - read-only - - - - - INT_ENA - Interrupt enable register - 0x48 - 0x20 - - - CNT_THR_EVENT_U0_INT_ENA - The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. - 0 - 1 - read-write - - - CNT_THR_EVENT_U1_INT_ENA - The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. - 1 - 1 - read-write - - - CNT_THR_EVENT_U2_INT_ENA - The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. - 2 - 1 - read-write - - - CNT_THR_EVENT_U3_INT_ENA - The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. - 3 - 1 - read-write - - - - - INT_CLR - Interrupt clear register - 0x4C - 0x20 - - - CNT_THR_EVENT_U0_INT_CLR - Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt. - 0 - 1 - write-only - - - CNT_THR_EVENT_U1_INT_CLR - Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt. - 1 - 1 - write-only - - - CNT_THR_EVENT_U2_INT_CLR - Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt. - 2 - 1 - write-only - - - CNT_THR_EVENT_U3_INT_CLR - Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt. - 3 - 1 - write-only - - - - - 4 - 0x4 - U%s_STATUS - PNCT UNIT%s status register - 0x50 - 0x20 - - - CNT_THR_ZERO_MODE_U - The pulse counter status of PCNT_U%s corresponding to 0. 0: pulse counter decreases from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter is negative. 3: pulse counter is positive. - 0 - 2 - read-only - - - CNT_THR_THRES1_LAT_U - The latched value of thres1 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0: others - 2 - 1 - read-only - - - CNT_THR_THRES0_LAT_U - The latched value of thres0 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0: others - 3 - 1 - read-only - - - CNT_THR_L_LIM_LAT_U - The latched value of low limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_l_lim and low limit event is valid. 0: others - 4 - 1 - read-only - - - CNT_THR_H_LIM_LAT_U - The latched value of high limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_h_lim and high limit event is valid. 0: others - 5 - 1 - read-only - - - CNT_THR_ZERO_LAT_U - The latched value of zero threshold event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to 0 and zero threshold event is valid. 0: others - 6 - 1 - read-only - - - - - CTRL - Control register for all counters - 0x60 - 0x20 - 0x00000001 - - - PULSE_CNT_RST_U0 - Set this bit to clear unit 0's counter. - 0 - 1 - read-write - - - CNT_PAUSE_U0 - Set this bit to freeze unit 0's counter. - 1 - 1 - read-write - - - PULSE_CNT_RST_U1 - Set this bit to clear unit 1's counter. - 2 - 1 - read-write - - - CNT_PAUSE_U1 - Set this bit to freeze unit 1's counter. - 3 - 1 - read-write - - - PULSE_CNT_RST_U2 - Set this bit to clear unit 2's counter. - 4 - 1 - read-write - - - CNT_PAUSE_U2 - Set this bit to freeze unit 2's counter. - 5 - 1 - read-write - - - PULSE_CNT_RST_U3 - Set this bit to clear unit 3's counter. - 6 - 1 - read-write - - - CNT_PAUSE_U3 - Set this bit to freeze unit 3's counter. - 7 - 1 - read-write - - - DALTA_CHANGE_EN_U0 - Configures this bit to enable unit 0's step comparator. - 8 - 1 - read-write - - - DALTA_CHANGE_EN_U1 - Configures this bit to enable unit 1's step comparator. - 9 - 1 - read-write - - - DALTA_CHANGE_EN_U2 - Configures this bit to enable unit 2's step comparator. - 10 - 1 - read-write - - - DALTA_CHANGE_EN_U3 - Configures this bit to enable unit 3's step comparator. - 11 - 1 - read-write - - - CLK_EN - The registers clock gate enable signal of PCNT module. 1: the registers can be read and written by application. 0: the registers can not be read or written by application - 16 - 1 - read-write - - - - - U3_CHANGE_CONF - Configuration register for unit $n's step value. - 0x64 - 0x20 - - - CNT_STEP_U3 - Configures the step value for unit 3. - 0 - 16 - read-write - - - CNT_STEP_LIM_U3 - Configures the step limit value for unit 3. - 16 - 16 - read-write - - - - - U2_CHANGE_CONF - Configuration register for unit $n's step value. - 0x68 - 0x20 - - - CNT_STEP_U2 - Configures the step value for unit 2. - 0 - 16 - read-write - - - CNT_STEP_LIM_U2 - Configures the step limit value for unit 2. - 16 - 16 - read-write - - - - - U1_CHANGE_CONF - Configuration register for unit $n's step value. - 0x6C - 0x20 - - - CNT_STEP_U1 - Configures the step value for unit 1. - 0 - 16 - read-write - - - CNT_STEP_LIM_U1 - Configures the step limit value for unit 1. - 16 - 16 - read-write - - - - - U0_CHANGE_CONF - Configuration register for unit $n's step value. - 0x70 - 0x20 - - - CNT_STEP_U0 - Configures the step value for unit 0. - 0 - 16 - read-write - - - CNT_STEP_LIM_U0 - Configures the step limit value for unit 0. - 16 - 16 - read-write - - - - - DATE - PCNT version control register - 0xFC - 0x20 - 0x22091900 - - - DATE - This is the PCNT version control register. - 0 - 32 - read-write - - - - - - - PMU - PMU Peripheral - PMU - 0x50115000 - - 0x0 - 0x21C - registers - - - PMU0 - 6 - - - PMU1 - 7 - - - - HP_ACTIVE_DIG_POWER - need_des - 0x0 - 0x20 - - - HP_ACTIVE_DCDC_SWITCH_PD_EN - need_des - 21 - 1 - read-write - - - HP_ACTIVE_HP_MEM_DSLP - need_des - 22 - 1 - read-write - - - HP_ACTIVE_PD_HP_MEM_PD_EN - need_des - 23 - 1 - read-write - - - HP_ACTIVE_PD_CNNT_PD_EN - need_des - 30 - 1 - read-write - - - HP_ACTIVE_PD_TOP_PD_EN - need_des - 31 - 1 - read-write - - - - - HP_ACTIVE_ICG_HP_FUNC - need_des - 0x4 - 0x20 - 0xFFFFFFFF - - - HP_ACTIVE_DIG_ICG_FUNC_EN - need_des - 0 - 32 - read-write - - - - - HP_ACTIVE_ICG_HP_APB - need_des - 0x8 - 0x20 - 0xFFFFFFFF - - - HP_ACTIVE_DIG_ICG_APB_EN - need_des - 0 - 32 - read-write - - - - - HP_ACTIVE_ICG_MODEM - need_des - 0xC - 0x20 - - - HP_ACTIVE_DIG_ICG_MODEM_CODE - need_des - 30 - 2 - read-write - - - - - HP_ACTIVE_HP_SYS_CNTL - need_des - 0x10 - 0x20 - - - HP_ACTIVE_HP_POWER_DET_BYPASS - need_des - 23 - 1 - read-write - - - HP_ACTIVE_UART_WAKEUP_EN - need_des - 24 - 1 - read-write - - - HP_ACTIVE_LP_PAD_HOLD_ALL - need_des - 25 - 1 - read-write - - - HP_ACTIVE_HP_PAD_HOLD_ALL - need_des - 26 - 1 - read-write - - - HP_ACTIVE_DIG_PAD_SLP_SEL - need_des - 27 - 1 - read-write - - - HP_ACTIVE_DIG_PAUSE_WDT - need_des - 28 - 1 - read-write - - - HP_ACTIVE_DIG_CPU_STALL - need_des - 29 - 1 - read-write - - - - - HP_ACTIVE_HP_CK_POWER - need_des - 0x14 - 0x20 - - - HP_ACTIVE_I2C_ISO_EN - need_des - 21 - 1 - read-write - - - HP_ACTIVE_I2C_RETENTION - need_des - 22 - 1 - read-write - - - HP_ACTIVE_XPD_PLL_I2C - need_des - 23 - 4 - read-write - - - HP_ACTIVE_XPD_PLL - need_des - 27 - 4 - read-write - - - - - HP_ACTIVE_BIAS - need_des - 0x18 - 0x20 - 0x00500000 - - - HP_ACTIVE_DCM_VSET - need_des - 18 - 5 - read-write - - - HP_ACTIVE_DCM_MODE - need_des - 23 - 2 - read-write - - - HP_ACTIVE_XPD_BIAS - need_des - 25 - 1 - read-write - - - HP_ACTIVE_DBG_ATTEN - need_des - 26 - 4 - read-write - - - HP_ACTIVE_PD_CUR - need_des - 30 - 1 - read-write - - - SLEEP - need_des - 31 - 1 - read-write - - - - - HP_ACTIVE_BACKUP - need_des - 0x1C - 0x20 - - - HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE - need_des - 4 - 2 - read-write - - - HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE - need_des - 6 - 2 - read-write - - - HP_ACTIVE_RETENTION_MODE - need_des - 10 - 1 - read-write - - - HP_SLEEP2ACTIVE_RETENTION_EN - need_des - 11 - 1 - read-write - - - HP_MODEM2ACTIVE_RETENTION_EN - need_des - 12 - 1 - read-write - - - HP_SLEEP2ACTIVE_BACKUP_CLK_SEL - need_des - 14 - 2 - read-write - - - HP_MODEM2ACTIVE_BACKUP_CLK_SEL - need_des - 16 - 2 - read-write - - - HP_SLEEP2ACTIVE_BACKUP_MODE - need_des - 20 - 3 - read-write - - - HP_MODEM2ACTIVE_BACKUP_MODE - need_des - 23 - 3 - read-write - - - HP_SLEEP2ACTIVE_BACKUP_EN - need_des - 29 - 1 - read-write - - - HP_MODEM2ACTIVE_BACKUP_EN - need_des - 30 - 1 - read-write - - - - - HP_ACTIVE_BACKUP_CLK - need_des - 0x20 - 0x20 - - - HP_ACTIVE_BACKUP_ICG_FUNC_EN - need_des - 0 - 32 - read-write - - - - - HP_ACTIVE_SYSCLK - need_des - 0x24 - 0x20 - - - HP_ACTIVE_DIG_SYS_CLK_NO_DIV - need_des - 26 - 1 - read-write - - - HP_ACTIVE_ICG_SYS_CLOCK_EN - need_des - 27 - 1 - read-write - - - HP_ACTIVE_SYS_CLK_SLP_SEL - need_des - 28 - 1 - read-write - - - HP_ACTIVE_ICG_SLP_SEL - need_des - 29 - 1 - read-write - - - HP_ACTIVE_DIG_SYS_CLK_SEL - need_des - 30 - 2 - read-write - - - - - HP_ACTIVE_HP_REGULATOR0 - need_des - 0x28 - 0x20 - 0xC6677180 - - - LP_DBIAS_VOL - need_des - 4 - 5 - read-only - - - HP_DBIAS_VOL - need_des - 9 - 5 - read-only - - - DIG_REGULATOR0_DBIAS_SEL - need_des - 14 - 1 - read-write - - - DIG_DBIAS_INIT - need_des - 15 - 1 - write-only - - - HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD - need_des - 16 - 1 - read-write - - - HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD - need_des - 17 - 1 - read-write - - - HP_ACTIVE_HP_REGULATOR_XPD - need_des - 18 - 1 - read-write - - - HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS - need_des - 19 - 4 - read-write - - - HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS - need_des - 23 - 4 - read-write - - - HP_ACTIVE_HP_REGULATOR_DBIAS - need_des - 27 - 5 - read-write - - - - - HP_ACTIVE_HP_REGULATOR1 - need_des - 0x2C - 0x20 - - - HP_ACTIVE_HP_REGULATOR_DRV_B - need_des - 26 - 6 - read-write - - - - - HP_ACTIVE_XTAL - need_des - 0x30 - 0x20 - 0x80000000 - - - HP_ACTIVE_XPD_XTAL - need_des - 31 - 1 - read-write - - - - - HP_MODEM_DIG_POWER - need_des - 0x34 - 0x20 - - - HP_MODEM_DCDC_SWITCH_PD_EN - need_des - 21 - 1 - read-write - - - HP_MODEM_HP_MEM_DSLP - need_des - 22 - 1 - write-only - - - HP_MODEM_PD_HP_MEM_PD_EN - need_des - 23 - 4 - write-only - - - HP_MODEM_PD_HP_WIFI_PD_EN - need_des - 27 - 1 - write-only - - - HP_MODEM_PD_HP_CPU_PD_EN - need_des - 29 - 1 - write-only - - - HP_MODEM_PD_CNNT_PD_EN - need_des - 30 - 1 - write-only - - - HP_MODEM_PD_TOP_PD_EN - need_des - 31 - 1 - write-only - - - - - HP_MODEM_ICG_HP_FUNC - need_des - 0x38 - 0x20 - 0xFFFFFFFF - - - HP_MODEM_DIG_ICG_FUNC_EN - need_des - 0 - 32 - write-only - - - - - HP_MODEM_ICG_HP_APB - need_des - 0x3C - 0x20 - 0xFFFFFFFF - - - HP_MODEM_DIG_ICG_APB_EN - need_des - 0 - 32 - write-only - - - - - HP_MODEM_ICG_MODEM - need_des - 0x40 - 0x20 - - - HP_MODEM_DIG_ICG_MODEM_CODE - need_des - 30 - 2 - write-only - - - - - HP_MODEM_HP_SYS_CNTL - need_des - 0x44 - 0x20 - - - HP_MODEM_HP_POWER_DET_BYPASS - need_des - 23 - 1 - write-only - - - HP_MODEM_UART_WAKEUP_EN - need_des - 24 - 1 - write-only - - - HP_MODEM_LP_PAD_HOLD_ALL - need_des - 25 - 1 - write-only - - - HP_MODEM_HP_PAD_HOLD_ALL - need_des - 26 - 1 - write-only - - - HP_MODEM_DIG_PAD_SLP_SEL - need_des - 27 - 1 - write-only - - - HP_MODEM_DIG_PAUSE_WDT - need_des - 28 - 1 - write-only - - - HP_MODEM_DIG_CPU_STALL - need_des - 29 - 1 - write-only - - - - - HP_MODEM_HP_CK_POWER - need_des - 0x48 - 0x20 - - - HP_MODEM_I2C_ISO_EN - need_des - 21 - 1 - write-only - - - HP_MODEM_I2C_RETENTION - need_des - 22 - 1 - write-only - - - HP_MODEM_XPD_PLL_I2C - need_des - 23 - 4 - write-only - - - HP_MODEM_XPD_PLL - need_des - 27 - 4 - write-only - - - - - HP_MODEM_BIAS - need_des - 0x4C - 0x20 - 0x00500000 - - - HP_MODEM_DCM_VSET - need_des - 18 - 5 - write-only - - - HP_MODEM_DCM_MODE - need_des - 23 - 2 - write-only - - - HP_MODEM_XPD_BIAS - need_des - 25 - 1 - write-only - - - HP_MODEM_DBG_ATTEN - need_des - 26 - 4 - write-only - - - HP_MODEM_PD_CUR - need_des - 30 - 1 - write-only - - - SLEEP - need_des - 31 - 1 - write-only - - - - - HP_MODEM_BACKUP - need_des - 0x50 - 0x20 - - - HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE - need_des - 4 - 2 - write-only - - - HP_MODEM_RETENTION_MODE - need_des - 10 - 1 - write-only - - - HP_SLEEP2MODEM_RETENTION_EN - need_des - 11 - 1 - write-only - - - HP_SLEEP2MODEM_BACKUP_CLK_SEL - need_des - 14 - 2 - write-only - - - HP_SLEEP2MODEM_BACKUP_MODE - need_des - 20 - 3 - write-only - - - HP_SLEEP2MODEM_BACKUP_EN - need_des - 29 - 1 - write-only - - - - - HP_MODEM_BACKUP_CLK - need_des - 0x54 - 0x20 - - - HP_MODEM_BACKUP_ICG_FUNC_EN - need_des - 0 - 32 - write-only - - - - - HP_MODEM_SYSCLK - need_des - 0x58 - 0x20 - - - HP_MODEM_DIG_SYS_CLK_NO_DIV - need_des - 26 - 1 - write-only - - - HP_MODEM_ICG_SYS_CLOCK_EN - need_des - 27 - 1 - write-only - - - HP_MODEM_SYS_CLK_SLP_SEL - need_des - 28 - 1 - write-only - - - HP_MODEM_ICG_SLP_SEL - need_des - 29 - 1 - write-only - - - HP_MODEM_DIG_SYS_CLK_SEL - need_des - 30 - 2 - write-only - - - - - HP_MODEM_HP_REGULATOR0 - need_des - 0x5C - 0x20 - 0xC6670000 - - - HP_MODEM_HP_REGULATOR_SLP_MEM_XPD - need_des - 16 - 1 - write-only - - - HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD - need_des - 17 - 1 - write-only - - - HP_MODEM_HP_REGULATOR_XPD - need_des - 18 - 1 - write-only - - - HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS - need_des - 19 - 4 - write-only - - - HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS - need_des - 23 - 4 - write-only - - - HP_MODEM_HP_REGULATOR_DBIAS - need_des - 27 - 5 - write-only - - - - - HP_MODEM_HP_REGULATOR1 - need_des - 0x60 - 0x20 - - - HP_MODEM_HP_REGULATOR_DRV_B - need_des - 8 - 24 - write-only - - - - - HP_MODEM_XTAL - need_des - 0x64 - 0x20 - 0x80000000 - - - HP_MODEM_XPD_XTAL - need_des - 31 - 1 - write-only - - - - - HP_SLEEP_DIG_POWER - need_des - 0x68 - 0x20 - - - HP_SLEEP_DCDC_SWITCH_PD_EN - need_des - 21 - 1 - read-write - - - HP_SLEEP_HP_MEM_DSLP - need_des - 22 - 1 - read-write - - - HP_SLEEP_PD_HP_MEM_PD_EN - need_des - 23 - 1 - read-write - - - HP_SLEEP_PD_CNNT_PD_EN - need_des - 30 - 1 - read-write - - - HP_SLEEP_PD_TOP_PD_EN - need_des - 31 - 1 - read-write - - - - - HP_SLEEP_ICG_HP_FUNC - need_des - 0x6C - 0x20 - 0xFFFFFFFF - - - HP_SLEEP_DIG_ICG_FUNC_EN - need_des - 0 - 32 - read-write - - - - - HP_SLEEP_ICG_HP_APB - need_des - 0x70 - 0x20 - 0xFFFFFFFF - - - HP_SLEEP_DIG_ICG_APB_EN - need_des - 0 - 32 - read-write - - - - - HP_SLEEP_ICG_MODEM - need_des - 0x74 - 0x20 - - - HP_SLEEP_DIG_ICG_MODEM_CODE - need_des - 30 - 2 - read-write - - - - - HP_SLEEP_HP_SYS_CNTL - need_des - 0x78 - 0x20 - - - HP_SLEEP_HP_POWER_DET_BYPASS - need_des - 23 - 1 - read-write - - - HP_SLEEP_UART_WAKEUP_EN - need_des - 24 - 1 - read-write - - - HP_SLEEP_LP_PAD_HOLD_ALL - need_des - 25 - 1 - read-write - - - HP_SLEEP_HP_PAD_HOLD_ALL - need_des - 26 - 1 - read-write - - - HP_SLEEP_DIG_PAD_SLP_SEL - need_des - 27 - 1 - read-write - - - HP_SLEEP_DIG_PAUSE_WDT - need_des - 28 - 1 - read-write - - - HP_SLEEP_DIG_CPU_STALL - need_des - 29 - 1 - read-write - - - - - HP_SLEEP_HP_CK_POWER - need_des - 0x7C - 0x20 - - - HP_SLEEP_I2C_ISO_EN - need_des - 21 - 1 - read-write - - - HP_SLEEP_I2C_RETENTION - need_des - 22 - 1 - read-write - - - HP_SLEEP_XPD_PLL_I2C - need_des - 23 - 4 - read-write - - - HP_SLEEP_XPD_PLL - need_des - 27 - 4 - read-write - - - - - HP_SLEEP_BIAS - need_des - 0x80 - 0x20 - 0x00500000 - - - HP_SLEEP_DCM_VSET - need_des - 18 - 5 - read-write - - - HP_SLEEP_DCM_MODE - need_des - 23 - 2 - read-write - - - HP_SLEEP_XPD_BIAS - need_des - 25 - 1 - read-write - - - HP_SLEEP_DBG_ATTEN - need_des - 26 - 4 - read-write - - - HP_SLEEP_PD_CUR - need_des - 30 - 1 - read-write - - - SLEEP - need_des - 31 - 1 - read-write - - - - - HP_SLEEP_BACKUP - need_des - 0x84 - 0x20 - - - HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE - need_des - 6 - 2 - read-write - - - HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE - need_des - 8 - 2 - read-write - - - HP_SLEEP_RETENTION_MODE - need_des - 10 - 1 - read-write - - - HP_MODEM2SLEEP_RETENTION_EN - need_des - 12 - 1 - read-write - - - HP_ACTIVE2SLEEP_RETENTION_EN - need_des - 13 - 1 - read-write - - - HP_MODEM2SLEEP_BACKUP_CLK_SEL - need_des - 16 - 2 - read-write - - - HP_ACTIVE2SLEEP_BACKUP_CLK_SEL - need_des - 18 - 2 - read-write - - - HP_MODEM2SLEEP_BACKUP_MODE - need_des - 23 - 3 - read-write - - - HP_ACTIVE2SLEEP_BACKUP_MODE - need_des - 26 - 3 - read-write - - - HP_MODEM2SLEEP_BACKUP_EN - need_des - 30 - 1 - read-write - - - HP_ACTIVE2SLEEP_BACKUP_EN - need_des - 31 - 1 - read-write - - - - - HP_SLEEP_BACKUP_CLK - need_des - 0x88 - 0x20 - - - HP_SLEEP_BACKUP_ICG_FUNC_EN - need_des - 0 - 32 - read-write - - - - - HP_SLEEP_SYSCLK - need_des - 0x8C - 0x20 - - - HP_SLEEP_DIG_SYS_CLK_NO_DIV - need_des - 26 - 1 - read-write - - - HP_SLEEP_ICG_SYS_CLOCK_EN - need_des - 27 - 1 - read-write - - - HP_SLEEP_SYS_CLK_SLP_SEL - need_des - 28 - 1 - read-write - - - HP_SLEEP_ICG_SLP_SEL - need_des - 29 - 1 - read-write - - - HP_SLEEP_DIG_SYS_CLK_SEL - need_des - 30 - 2 - read-write - - - - - HP_SLEEP_HP_REGULATOR0 - need_des - 0x90 - 0x20 - 0xC6670000 - - - HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD - need_des - 16 - 1 - read-write - - - HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD - need_des - 17 - 1 - read-write - - - HP_SLEEP_HP_REGULATOR_XPD - need_des - 18 - 1 - read-write - - - HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS - need_des - 19 - 4 - read-write - - - HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS - need_des - 23 - 4 - read-write - - - HP_SLEEP_HP_REGULATOR_DBIAS - need_des - 27 - 5 - read-write - - - - - HP_SLEEP_HP_REGULATOR1 - need_des - 0x94 - 0x20 - - - HP_SLEEP_HP_REGULATOR_DRV_B - need_des - 26 - 6 - read-write - - - - - HP_SLEEP_XTAL - need_des - 0x98 - 0x20 - 0x80000000 - - - HP_SLEEP_XPD_XTAL - need_des - 31 - 1 - read-write - - - - - HP_SLEEP_LP_REGULATOR0 - need_des - 0x9C - 0x20 - 0xC6600000 - - - HP_SLEEP_LP_REGULATOR_SLP_XPD - need_des - 21 - 1 - read-write - - - HP_SLEEP_LP_REGULATOR_XPD - need_des - 22 - 1 - read-write - - - HP_SLEEP_LP_REGULATOR_SLP_DBIAS - need_des - 23 - 4 - read-write - - - HP_SLEEP_LP_REGULATOR_DBIAS - need_des - 27 - 5 - read-write - - - - - HP_SLEEP_LP_REGULATOR1 - need_des - 0xA0 - 0x20 - - - HP_SLEEP_LP_REGULATOR_DRV_B - need_des - 26 - 6 - read-write - - - - - HP_SLEEP_LP_DCDC_RESERVE - need_des - 0xA4 - 0x20 - - - PMU_HP_SLEEP_LP_DCDC_RESERVE - need_des - 0 - 32 - write-only - - - - - HP_SLEEP_LP_DIG_POWER - need_des - 0xA8 - 0x20 - - - HP_SLEEP_LP_PAD_SLP_SEL - need_des - 26 - 1 - read-write - - - HP_SLEEP_BOD_SOURCE_SEL - need_des - 27 - 1 - read-write - - - HP_SLEEP_VDDBAT_MODE - need_des - 28 - 2 - read-write - - - HP_SLEEP_LP_MEM_DSLP - need_des - 30 - 1 - read-write - - - HP_SLEEP_PD_LP_PERI_PD_EN - need_des - 31 - 1 - read-write - - - - - HP_SLEEP_LP_CK_POWER - need_des - 0xAC - 0x20 - 0x40000000 - - - HP_SLEEP_XPD_LPPLL - need_des - 27 - 1 - read-write - - - HP_SLEEP_XPD_XTAL32K - need_des - 28 - 1 - read-write - - - HP_SLEEP_XPD_RC32K - need_des - 29 - 1 - read-write - - - HP_SLEEP_XPD_FOSC_CLK - need_des - 30 - 1 - read-write - - - HP_SLEEP_PD_OSC_CLK - need_des - 31 - 1 - read-write - - - - - LP_SLEEP_LP_BIAS_RESERVE - need_des - 0xB0 - 0x20 - - - PMU_LP_SLEEP_LP_BIAS_RESERVE - need_des - 0 - 32 - write-only - - - - - LP_SLEEP_LP_REGULATOR0 - need_des - 0xB4 - 0x20 - 0xC6600000 - - - LP_SLEEP_LP_REGULATOR_SLP_XPD - need_des - 21 - 1 - read-write - - - LP_SLEEP_LP_REGULATOR_XPD - need_des - 22 - 1 - read-write - - - LP_SLEEP_LP_REGULATOR_SLP_DBIAS - need_des - 23 - 4 - read-write - - - LP_SLEEP_LP_REGULATOR_DBIAS - need_des - 27 - 5 - read-write - - - - - LP_SLEEP_LP_REGULATOR1 - need_des - 0xB8 - 0x20 - - - LP_SLEEP_LP_REGULATOR_DRV_B - need_des - 26 - 6 - read-write - - - - - LP_SLEEP_XTAL - need_des - 0xBC - 0x20 - 0x80000000 - - - LP_SLEEP_XPD_XTAL - need_des - 31 - 1 - read-write - - - - - LP_SLEEP_LP_DIG_POWER - need_des - 0xC0 - 0x20 - - - LP_SLEEP_LP_PAD_SLP_SEL - need_des - 26 - 1 - read-write - - - LP_SLEEP_BOD_SOURCE_SEL - need_des - 27 - 1 - read-write - - - LP_SLEEP_VDDBAT_MODE - need_des - 28 - 2 - read-write - - - LP_SLEEP_LP_MEM_DSLP - need_des - 30 - 1 - read-write - - - LP_SLEEP_PD_LP_PERI_PD_EN - need_des - 31 - 1 - read-write - - - - - LP_SLEEP_LP_CK_POWER - need_des - 0xC4 - 0x20 - 0x40000000 - - - LP_SLEEP_XPD_LPPLL - need_des - 27 - 1 - read-write - - - LP_SLEEP_XPD_XTAL32K - need_des - 28 - 1 - read-write - - - LP_SLEEP_XPD_RC32K - need_des - 29 - 1 - read-write - - - LP_SLEEP_XPD_FOSC_CLK - need_des - 30 - 1 - read-write - - - LP_SLEEP_PD_OSC_CLK - need_des - 31 - 1 - read-write - - - - - LP_SLEEP_BIAS - need_des - 0xC8 - 0x20 - - - LP_SLEEP_XPD_BIAS - need_des - 25 - 1 - read-write - - - LP_SLEEP_DBG_ATTEN - need_des - 26 - 4 - read-write - - - LP_SLEEP_PD_CUR - need_des - 30 - 1 - read-write - - - SLEEP - need_des - 31 - 1 - read-write - - - - - IMM_HP_CK_POWER - need_des - 0xCC - 0x20 - - - TIE_LOW_CALI_XTAL_ICG - need_des - 0 - 1 - read-write - - - TIE_LOW_GLOBAL_PLL_ICG - need_des - 1 - 4 - write-only - - - TIE_LOW_GLOBAL_XTAL_ICG - need_des - 5 - 1 - write-only - - - TIE_LOW_I2C_RETENTION - need_des - 6 - 1 - write-only - - - TIE_LOW_XPD_PLL_I2C - need_des - 7 - 4 - write-only - - - TIE_LOW_XPD_PLL - need_des - 11 - 4 - write-only - - - TIE_LOW_XPD_XTAL - need_des - 15 - 1 - write-only - - - TIE_HIGH_CALI_XTAL_ICG - need_des - 16 - 1 - read-write - - - TIE_HIGH_GLOBAL_PLL_ICG - need_des - 17 - 4 - write-only - - - TIE_HIGH_GLOBAL_XTAL_ICG - need_des - 21 - 1 - write-only - - - TIE_HIGH_I2C_RETENTION - need_des - 22 - 1 - write-only - - - TIE_HIGH_XPD_PLL_I2C - need_des - 23 - 4 - write-only - - - TIE_HIGH_XPD_PLL - need_des - 27 - 4 - write-only - - - TIE_HIGH_XPD_XTAL - need_des - 31 - 1 - write-only - - - - - IMM_SLEEP_SYSCLK - need_des - 0xD0 - 0x20 - - - UPDATE_DIG_ICG_SWITCH - need_des - 28 - 1 - write-only - - - TIE_LOW_ICG_SLP_SEL - need_des - 29 - 1 - write-only - - - TIE_HIGH_ICG_SLP_SEL - need_des - 30 - 1 - write-only - - - UPDATE_DIG_SYS_CLK_SEL - need_des - 31 - 1 - write-only - - - - - IMM_HP_FUNC_ICG - need_des - 0xD4 - 0x20 - - - UPDATE_DIG_ICG_FUNC_EN - need_des - 31 - 1 - write-only - - - - - IMM_HP_APB_ICG - need_des - 0xD8 - 0x20 - - - UPDATE_DIG_ICG_APB_EN - need_des - 31 - 1 - write-only - - - - - IMM_MODEM_ICG - need_des - 0xDC - 0x20 - - - UPDATE_DIG_ICG_MODEM_EN - need_des - 31 - 1 - write-only - - - - - IMM_LP_ICG - need_des - 0xE0 - 0x20 - - - TIE_LOW_LP_ROOTCLK_SEL - need_des - 30 - 1 - write-only - - - TIE_HIGH_LP_ROOTCLK_SEL - need_des - 31 - 1 - write-only - - - - - IMM_PAD_HOLD_ALL - need_des - 0xE4 - 0x20 - - - PAD_SLP_SEL - need_des - 0 - 1 - read-only - - - LP_PAD_HOLD_ALL - need_des - 1 - 1 - read-only - - - HP_PAD_HOLD_ALL - need_des - 2 - 1 - read-only - - - TIE_HIGH_PAD_SLP_SEL - need_des - 26 - 1 - write-only - - - TIE_LOW_PAD_SLP_SEL - need_des - 27 - 1 - write-only - - - TIE_HIGH_LP_PAD_HOLD_ALL - need_des - 28 - 1 - write-only - - - TIE_LOW_LP_PAD_HOLD_ALL - need_des - 29 - 1 - write-only - - - TIE_HIGH_HP_PAD_HOLD_ALL - need_des - 30 - 1 - write-only - - - TIE_LOW_HP_PAD_HOLD_ALL - need_des - 31 - 1 - write-only - - - - - IMM_I2C_ISO - need_des - 0xE8 - 0x20 - - - TIE_HIGH_I2C_ISO_EN - need_des - 30 - 1 - write-only - - - TIE_LOW_I2C_ISO_EN - need_des - 31 - 1 - write-only - - - - - POWER_WAIT_TIMER0 - need_des - 0xEC - 0x20 - 0x7FBFDFE0 - - - DG_HP_POWERDOWN_TIMER - need_des - 5 - 9 - read-write - - - DG_HP_POWERUP_TIMER - need_des - 14 - 9 - read-write - - - DG_HP_WAIT_TIMER - need_des - 23 - 9 - read-write - - - - - POWER_WAIT_TIMER1 - need_des - 0xF0 - 0x20 - 0x7FBFDFE0 - - - DG_LP_POWERDOWN_TIMER - need_des - 5 - 9 - read-write - - - DG_LP_POWERUP_TIMER - need_des - 14 - 9 - read-write - - - DG_LP_WAIT_TIMER - need_des - 23 - 9 - read-write - - - - - POWER_PD_TOP_CNTL - need_des - 0xF4 - 0x20 - 0x0000001C - - - FORCE_TOP_RESET - need_des - 0 - 1 - read-write - - - FORCE_TOP_ISO - need_des - 1 - 1 - read-write - - - FORCE_TOP_PU - need_des - 2 - 1 - read-write - - - FORCE_TOP_NO_RESET - need_des - 3 - 1 - read-write - - - FORCE_TOP_NO_ISO - need_des - 4 - 1 - read-write - - - FORCE_TOP_PD - need_des - 5 - 1 - read-write - - - - - POWER_PD_CNNT_CNTL - need_des - 0xF8 - 0x20 - 0x0000001C - - - FORCE_CNNT_RESET - need_des - 0 - 1 - read-write - - - FORCE_CNNT_ISO - need_des - 1 - 1 - read-write - - - FORCE_CNNT_PU - need_des - 2 - 1 - read-write - - - FORCE_CNNT_NO_RESET - need_des - 3 - 1 - read-write - - - FORCE_CNNT_NO_ISO - need_des - 4 - 1 - read-write - - - FORCE_CNNT_PD - need_des - 5 - 1 - read-write - - - - - POWER_PD_HPMEM_CNTL - need_des - 0xFC - 0x20 - 0x0000001C - - - FORCE_HP_MEM_RESET - need_des - 0 - 1 - read-write - - - FORCE_HP_MEM_ISO - need_des - 1 - 1 - read-write - - - FORCE_HP_MEM_PU - need_des - 2 - 1 - read-write - - - FORCE_HP_MEM_NO_RESET - need_des - 3 - 1 - read-write - - - FORCE_HP_MEM_NO_ISO - need_des - 4 - 1 - read-write - - - FORCE_HP_MEM_PD - need_des - 5 - 1 - read-write - - - - - POWER_PD_TOP_MASK - need_des - 0x100 - 0x20 - - - XPD_TOP_MASK - need_des - 0 - 5 - read-write - - - PD_TOP_MASK - need_des - 27 - 5 - read-write - - - - - POWER_PD_CNNT_MASK - need_des - 0x104 - 0x20 - - - XPD_CNNT_MASK - need_des - 0 - 5 - read-write - - - PD_CNNT_MASK - need_des - 27 - 5 - read-write - - - - - POWER_PD_HPMEM_MASK - need_des - 0x108 - 0x20 - - - XPD_HP_MEM_MASK - need_des - 0 - 6 - read-write - - - PD_HP_MEM_MASK - need_des - 26 - 6 - read-write - - - - - POWER_DCDC_SWITCH - need_des - 0x10C - 0x20 - 0x00000001 - - - FORCE_DCDC_SWITCH_PU - need_des - 0 - 1 - read-write - - - FORCE_DCDC_SWITCH_PD - need_des - 1 - 1 - read-write - - - - - POWER_PD_LPPERI_CNTL - need_des - 0x110 - 0x20 - 0x0000001C - - - FORCE_LP_PERI_RESET - need_des - 0 - 1 - read-write - - - FORCE_LP_PERI_ISO - need_des - 1 - 1 - read-write - - - FORCE_LP_PERI_PU - need_des - 2 - 1 - read-write - - - FORCE_LP_PERI_NO_RESET - need_des - 3 - 1 - read-write - - - FORCE_LP_PERI_NO_ISO - need_des - 4 - 1 - read-write - - - FORCE_LP_PERI_PD - need_des - 5 - 1 - read-write - - - - - POWER_PD_LPPERI_MASK - need_des - 0x114 - 0x20 - - - XPD_LP_PERI_MASK - need_des - 0 - 5 - read-write - - - PD_LP_PERI_MASK - need_des - 27 - 5 - read-write - - - - - POWER_HP_PAD - need_des - 0x118 - 0x20 - - - FORCE_HP_PAD_NO_ISO_ALL - need_des - 0 - 1 - read-write - - - FORCE_HP_PAD_ISO_ALL - need_des - 1 - 1 - read-write - - - - - POWER_CK_WAIT_CNTL - need_des - 0x11C - 0x20 - 0x01000100 - - - PMU_WAIT_XTL_STABLE - need_des - 0 - 16 - read-write - - - PMU_WAIT_PLL_STABLE - need_des - 16 - 16 - read-write - - - - - SLP_WAKEUP_CNTL0 - need_des - 0x120 - 0x20 - - - SLEEP_REQ - need_des - 31 - 1 - write-only - - - - - SLP_WAKEUP_CNTL1 - need_des - 0x124 - 0x20 - - - SLEEP_REJECT_ENA - need_des - 0 - 31 - read-write - - - SLP_REJECT_EN - need_des - 31 - 1 - read-write - - - - - SLP_WAKEUP_CNTL2 - need_des - 0x128 - 0x20 - - - WAKEUP_ENA - need_des - 0 - 31 - read-write - - - - - SLP_WAKEUP_CNTL3 - need_des - 0x12C - 0x20 - - - LP_MIN_SLP_VAL - need_des - 0 - 8 - read-write - - - HP_MIN_SLP_VAL - need_des - 8 - 8 - read-write - - - SLEEP_PRT_SEL - need_des - 16 - 2 - read-write - - - - - SLP_WAKEUP_CNTL4 - need_des - 0x130 - 0x20 - - - SLP_REJECT_CAUSE_CLR - need_des - 31 - 1 - write-only - - - - - SLP_WAKEUP_CNTL5 - need_des - 0x134 - 0x20 - 0x01000080 - - - MODEM_WAIT_TARGET - need_des - 0 - 20 - read-write - - - LP_ANA_WAIT_TARGET - need_des - 24 - 8 - read-write - - - - - SLP_WAKEUP_CNTL6 - need_des - 0x138 - 0x20 - 0x00000080 - - - SOC_WAKEUP_WAIT - need_des - 0 - 20 - read-write - - - SOC_WAKEUP_WAIT_CFG - need_des - 30 - 2 - read-write - - - - - SLP_WAKEUP_CNTL7 - need_des - 0x13C - 0x20 - 0x00010000 - - - ANA_WAIT_TARGET - need_des - 16 - 16 - read-write - - - - - SLP_WAKEUP_CNTL8 - need_des - 0x140 - 0x20 - - - LP_LITE_WAKEUP_ENA - need_des - 31 - 1 - read-write - - - - - SLP_WAKEUP_STATUS0 - need_des - 0x144 - 0x20 - - - WAKEUP_CAUSE - need_des - 0 - 31 - read-only - - - - - SLP_WAKEUP_STATUS1 - need_des - 0x148 - 0x20 - - - REJECT_CAUSE - need_des - 0 - 31 - read-only - - - - - SLP_WAKEUP_STATUS2 - need_des - 0x14C - 0x20 - - - LP_LITE_WAKEUP_CAUSE - need_des - 31 - 1 - read-only - - - - - HP_CK_POWERON - need_des - 0x150 - 0x20 - 0x00000032 - - - I2C_POR_WAIT_TARGET - need_des - 0 - 8 - read-write - - - - - HP_CK_CNTL - need_des - 0x154 - 0x20 - 0x00000A0A - - - MODIFY_ICG_CNTL_WAIT - need_des - 0 - 8 - read-write - - - SWITCH_ICG_CNTL_WAIT - need_des - 8 - 8 - read-write - - - - - POR_STATUS - need_des - 0x158 - 0x20 - 0x80000000 - - - POR_DONE - need_des - 31 - 1 - read-only - - - - - RF_PWC - need_des - 0x15C - 0x20 - 0x08000000 - - - MSPI_PHY_XPD - need_des - 24 - 1 - read-write - - - SDIO_PLL_XPD - need_des - 25 - 1 - read-write - - - PERIF_I2C_RSTB - need_des - 26 - 1 - read-write - - - XPD_PERIF_I2C - need_des - 27 - 1 - read-write - - - XPD_TXRF_I2C - need_des - 28 - 1 - read-write - - - XPD_RFRX_PBUS - need_des - 29 - 1 - read-write - - - XPD_CKGEN_I2C - need_des - 30 - 1 - read-write - - - - - BACKUP_CFG - need_des - 0x160 - 0x20 - 0x80000000 - - - BACKUP_SYS_CLK_NO_DIV - need_des - 31 - 1 - read-write - - - - - INT_RAW - need_des - 0x164 - 0x20 - - - _0P1A_CNT_TARGET0_REACH_0_HP_INT_RAW - reg_0p1a_0_counter after xpd reach target0 - 14 - 1 - read-write - - - _0P1A_CNT_TARGET1_REACH_0_HP_INT_RAW - reg_0p1a_1_counter after xpd reach target1 - 15 - 1 - read-write - - - _0P1A_CNT_TARGET0_REACH_1_HP_INT_RAW - reg_0p1a_0 counter after xpd reach target0 - 16 - 1 - read-write - - - _0P1A_CNT_TARGET1_REACH_1_HP_INT_RAW - reg_0p1a_1_counter after xpd reach target1 - 17 - 1 - read-write - - - _0P2A_CNT_TARGET0_REACH_0_HP_INT_RAW - reg_0p2a_0 counter after xpd reach target0 - 18 - 1 - read-write - - - _0P2A_CNT_TARGET1_REACH_0_HP_INT_RAW - reg_0p2a_1_counter after xpd reach target1 - 19 - 1 - read-write - - - _0P2A_CNT_TARGET0_REACH_1_HP_INT_RAW - reg_0p2a_0 counter after xpd reach target0 - 20 - 1 - read-write - - - _0P2A_CNT_TARGET1_REACH_1_HP_INT_RAW - reg_0p2a_1_counter after xpd reach target1 - 21 - 1 - read-write - - - _0P3A_CNT_TARGET0_REACH_0_HP_INT_RAW - reg_0p3a_0 counter after xpd reach target0 - 22 - 1 - read-write - - - _0P3A_CNT_TARGET1_REACH_0_HP_INT_RAW - reg_0p3a_1_counter after xpd reach target1 - 23 - 1 - read-write - - - _0P3A_CNT_TARGET0_REACH_1_HP_INT_RAW - reg_0p3a_0_counter after xpd reach target0 - 24 - 1 - read-write - - - _0P3A_CNT_TARGET1_REACH_1_HP_INT_RAW - reg_0p3a_1_counter after xpd reach target1 - 25 - 1 - read-write - - - LP_CPU_EXC_INT_RAW - need_des - 27 - 1 - read-write - - - SDIO_IDLE_INT_RAW - need_des - 28 - 1 - read-write - - - SW_INT_RAW - need_des - 29 - 1 - read-write - - - SOC_SLEEP_REJECT_INT_RAW - need_des - 30 - 1 - read-write - - - SOC_WAKEUP_INT_RAW - need_des - 31 - 1 - read-write - - - - - HP_INT_ST - need_des - 0x168 - 0x20 - - - _0P1A_CNT_TARGET0_REACH_0_HP_INT_ST - reg_0p1a_0_counter after xpd reach target0 - 14 - 1 - read-only - - - _0P1A_CNT_TARGET1_REACH_0_HP_INT_ST - reg_0p1a_1_counter after xpd reach target1 - 15 - 1 - read-only - - - _0P1A_CNT_TARGET0_REACH_1_HP_INT_ST - reg_0p1a_0 counter after xpd reach target0 - 16 - 1 - read-only - - - _0P1A_CNT_TARGET1_REACH_1_HP_INT_ST - reg_0p1a_1_counter after xpd reach target1 - 17 - 1 - read-only - - - _0P2A_CNT_TARGET0_REACH_0_HP_INT_ST - reg_0p2a_0 counter after xpd reach target0 - 18 - 1 - read-only - - - _0P2A_CNT_TARGET1_REACH_0_HP_INT_ST - reg_0p2a_1_counter after xpd reach target1 - 19 - 1 - read-only - - - _0P2A_CNT_TARGET0_REACH_1_HP_INT_ST - reg_0p2a_0 counter after xpd reach target0 - 20 - 1 - read-only - - - _0P2A_CNT_TARGET1_REACH_1_HP_INT_ST - reg_0p2a_1_counter after xpd reach target1 - 21 - 1 - read-only - - - _0P3A_CNT_TARGET0_REACH_0_HP_INT_ST - reg_0p3a_0 counter after xpd reach target0 - 22 - 1 - read-only - - - _0P3A_CNT_TARGET1_REACH_0_HP_INT_ST - reg_0p3a_1_counter after xpd reach target1 - 23 - 1 - read-only - - - _0P3A_CNT_TARGET0_REACH_1_HP_INT_ST - reg_0p3a_0_counter after xpd reach target0 - 24 - 1 - read-only - - - _0P3A_CNT_TARGET1_REACH_1_HP_INT_ST - reg_0p3a_1_counter after xpd reach target1 - 25 - 1 - read-only - - - LP_CPU_EXC_INT_ST - need_des - 27 - 1 - read-only - - - SDIO_IDLE_INT_ST - need_des - 28 - 1 - read-only - - - SW_INT_ST - need_des - 29 - 1 - read-only - - - SOC_SLEEP_REJECT_INT_ST - need_des - 30 - 1 - read-only - - - SOC_WAKEUP_INT_ST - need_des - 31 - 1 - read-only - - - - - HP_INT_ENA - need_des - 0x16C - 0x20 - - - _0P1A_CNT_TARGET0_REACH_0_HP_INT_ENA - reg_0p1a_0_counter after xpd reach target0 - 14 - 1 - read-write - - - _0P1A_CNT_TARGET1_REACH_0_HP_INT_ENA - reg_0p1a_1_counter after xpd reach target1 - 15 - 1 - read-write - - - _0P1A_CNT_TARGET0_REACH_1_HP_INT_ENA - reg_0p1a_0 counter after xpd reach target0 - 16 - 1 - read-write - - - _0P1A_CNT_TARGET1_REACH_1_HP_INT_ENA - reg_0p1a_1_counter after xpd reach target1 - 17 - 1 - read-write - - - _0P2A_CNT_TARGET0_REACH_0_HP_INT_ENA - reg_0p2a_0 counter after xpd reach target0 - 18 - 1 - read-write - - - _0P2A_CNT_TARGET1_REACH_0_HP_INT_ENA - reg_0p2a_1_counter after xpd reach target1 - 19 - 1 - read-write - - - _0P2A_CNT_TARGET0_REACH_1_HP_INT_ENA - reg_0p2a_0 counter after xpd reach target0 - 20 - 1 - read-write - - - _0P2A_CNT_TARGET1_REACH_1_HP_INT_ENA - reg_0p2a_1_counter after xpd reach target1 - 21 - 1 - read-write - - - _0P3A_CNT_TARGET0_REACH_0_HP_INT_ENA - reg_0p3a_0 counter after xpd reach target0 - 22 - 1 - read-write - - - _0P3A_CNT_TARGET1_REACH_0_HP_INT_ENA - reg_0p3a_1_counter after xpd reach target1 - 23 - 1 - read-write - - - _0P3A_CNT_TARGET0_REACH_1_HP_INT_ENA - reg_0p3a_0_counter after xpd reach target0 - 24 - 1 - read-write - - - _0P3A_CNT_TARGET1_REACH_1_HP_INT_ENA - reg_0p3a_1_counter after xpd reach target1 - 25 - 1 - read-write - - - LP_CPU_EXC_INT_ENA - need_des - 27 - 1 - read-write - - - SDIO_IDLE_INT_ENA - need_des - 28 - 1 - read-write - - - SW_INT_ENA - need_des - 29 - 1 - read-write - - - SOC_SLEEP_REJECT_INT_ENA - need_des - 30 - 1 - read-write - - - SOC_WAKEUP_INT_ENA - need_des - 31 - 1 - read-write - - - - - HP_INT_CLR - need_des - 0x170 - 0x20 - - - _0P1A_CNT_TARGET0_REACH_0_HP_INT_CLR - reg_0p1a_0_counter after xpd reach target0 - 14 - 1 - write-only - - - _0P1A_CNT_TARGET1_REACH_0_HP_INT_CLR - reg_0p1a_1_counter after xpd reach target1 - 15 - 1 - write-only - - - _0P1A_CNT_TARGET0_REACH_1_HP_INT_CLR - reg_0p1a_0 counter after xpd reach target0 - 16 - 1 - write-only - - - _0P1A_CNT_TARGET1_REACH_1_HP_INT_CLR - reg_0p1a_1_counter after xpd reach target1 - 17 - 1 - write-only - - - _0P2A_CNT_TARGET0_REACH_0_HP_INT_CLR - reg_0p2a_0 counter after xpd reach target0 - 18 - 1 - write-only - - - _0P2A_CNT_TARGET1_REACH_0_HP_INT_CLR - reg_0p2a_1_counter after xpd reach target1 - 19 - 1 - write-only - - - _0P2A_CNT_TARGET0_REACH_1_HP_INT_CLR - reg_0p2a_0 counter after xpd reach target0 - 20 - 1 - write-only - - - _0P2A_CNT_TARGET1_REACH_1_HP_INT_CLR - reg_0p2a_1_counter after xpd reach target1 - 21 - 1 - write-only - - - _0P3A_CNT_TARGET0_REACH_0_HP_INT_CLR - reg_0p3a_0 counter after xpd reach target0 - 22 - 1 - write-only - - - _0P3A_CNT_TARGET1_REACH_0_HP_INT_CLR - reg_0p3a_1_counter after xpd reach target1 - 23 - 1 - write-only - - - _0P3A_CNT_TARGET0_REACH_1_HP_INT_CLR - reg_0p3a_0_counter after xpd reach target0 - 24 - 1 - write-only - - - _0P3A_CNT_TARGET1_REACH_1_HP_INT_CLR - reg_0p3a_1_counter after xpd reach target1 - 25 - 1 - write-only - - - LP_CPU_EXC_INT_CLR - need_des - 27 - 1 - write-only - - - SDIO_IDLE_INT_CLR - need_des - 28 - 1 - write-only - - - SW_INT_CLR - need_des - 29 - 1 - write-only - - - SOC_SLEEP_REJECT_INT_CLR - need_des - 30 - 1 - write-only - - - SOC_WAKEUP_INT_CLR - need_des - 31 - 1 - write-only - - - - - LP_INT_RAW - need_des - 0x174 - 0x20 - - - LP_CPU_SLEEP_REJECT_INT_RAW - need_des - 13 - 1 - read-write - - - _0P1A_CNT_TARGET0_REACH_0_LP_INT_RAW - reg_0p1a_0_counter after xpd reach target0 - 14 - 1 - read-write - - - _0P1A_CNT_TARGET1_REACH_0_LP_INT_RAW - reg_0p1a_1_counter after xpd reach target1 - 15 - 1 - read-write - - - _0P1A_CNT_TARGET0_REACH_1_LP_INT_RAW - reg_0p1a_0 counter after xpd reach target0 - 16 - 1 - read-write - - - _0P1A_CNT_TARGET1_REACH_1_LP_INT_RAW - reg_0p1a_1_counter after xpd reach target1 - 17 - 1 - read-write - - - _0P2A_CNT_TARGET0_REACH_0_LP_INT_RAW - reg_0p2a_0 counter after xpd reach target0 - 18 - 1 - read-write - - - _0P2A_CNT_TARGET1_REACH_0_LP_INT_RAW - reg_0p2a_1_counter after xpd reach target1 - 19 - 1 - read-write - - - _0P2A_CNT_TARGET0_REACH_1_LP_INT_RAW - reg_0p2a_0 counter after xpd reach target0 - 20 - 1 - read-write - - - _0P2A_CNT_TARGET1_REACH_1_LP_INT_RAW - reg_0p2a_1_counter after xpd reach target1 - 21 - 1 - read-write - - - _0P3A_CNT_TARGET0_REACH_0_LP_INT_RAW - reg_0p3a_0 counter after xpd reach target0 - 22 - 1 - read-write - - - _0P3A_CNT_TARGET1_REACH_0_LP_INT_RAW - reg_0p3a_1_counter after xpd reach target1 - 23 - 1 - read-write - - - _0P3A_CNT_TARGET0_REACH_1_LP_INT_RAW - reg_0p3a_0_counter after xpd reach target0 - 24 - 1 - read-write - - - _0P3A_CNT_TARGET1_REACH_1_LP_INT_RAW - reg_0p3a_1_counter after xpd reach target1 - 25 - 1 - read-write - - - LP_CPU_WAKEUP_INT_RAW - need_des - 26 - 1 - read-write - - - SLEEP_SWITCH_ACTIVE_END_INT_RAW - need_des - 27 - 1 - read-write - - - ACTIVE_SWITCH_SLEEP_END_INT_RAW - need_des - 28 - 1 - read-write - - - SLEEP_SWITCH_ACTIVE_START_INT_RAW - need_des - 29 - 1 - read-write - - - ACTIVE_SWITCH_SLEEP_START_INT_RAW - need_des - 30 - 1 - read-write - - - HP_SW_TRIGGER_INT_RAW - need_des - 31 - 1 - read-write - - - - - LP_INT_ST - need_des - 0x178 - 0x20 - - - LP_CPU_SLEEP_REJECT_INT_ST - need_des - 13 - 1 - read-only - - - _0P1A_CNT_TARGET0_REACH_0_LP_INT_ST - reg_0p1a_0_counter after xpd reach target0 - 14 - 1 - read-only - - - _0P1A_CNT_TARGET1_REACH_0_LP_INT_ST - reg_0p1a_1_counter after xpd reach target1 - 15 - 1 - read-only - - - _0P1A_CNT_TARGET0_REACH_1_LP_INT_ST - reg_0p1a_0 counter after xpd reach target0 - 16 - 1 - read-only - - - _0P1A_CNT_TARGET1_REACH_1_LP_INT_ST - reg_0p1a_1_counter after xpd reach target1 - 17 - 1 - read-only - - - _0P2A_CNT_TARGET0_REACH_0_LP_INT_ST - reg_0p2a_0 counter after xpd reach target0 - 18 - 1 - read-only - - - _0P2A_CNT_TARGET1_REACH_0_LP_INT_ST - reg_0p2a_1_counter after xpd reach target1 - 19 - 1 - read-only - - - _0P2A_CNT_TARGET0_REACH_1_LP_INT_ST - reg_0p2a_0 counter after xpd reach target0 - 20 - 1 - read-only - - - _0P2A_CNT_TARGET1_REACH_1_LP_INT_ST - reg_0p2a_1_counter after xpd reach target1 - 21 - 1 - read-only - - - _0P3A_CNT_TARGET0_REACH_0_LP_INT_ST - reg_0p3a_0 counter after xpd reach target0 - 22 - 1 - read-only - - - _0P3A_CNT_TARGET1_REACH_0_LP_INT_ST - reg_0p3a_1_counter after xpd reach target1 - 23 - 1 - read-only - - - _0P3A_CNT_TARGET0_REACH_1_LP_INT_ST - reg_0p3a_0_counter after xpd reach target0 - 24 - 1 - read-only - - - _0P3A_CNT_TARGET1_REACH_1_LP_INT_ST - reg_0p3a_1_counter after xpd reach target1 - 25 - 1 - read-only - - - LP_CPU_WAKEUP_INT_ST - need_des - 26 - 1 - read-only - - - SLEEP_SWITCH_ACTIVE_END_INT_ST - need_des - 27 - 1 - read-only - - - ACTIVE_SWITCH_SLEEP_END_INT_ST - need_des - 28 - 1 - read-only - - - SLEEP_SWITCH_ACTIVE_START_INT_ST - need_des - 29 - 1 - read-only - - - ACTIVE_SWITCH_SLEEP_START_INT_ST - need_des - 30 - 1 - read-only - - - HP_SW_TRIGGER_INT_ST - need_des - 31 - 1 - read-only - - - - - LP_INT_ENA - need_des - 0x17C - 0x20 - - - LP_CPU_SLEEP_REJECT_INT_ENA - need_des - 13 - 1 - read-write - - - _0P1A_CNT_TARGET0_REACH_0_LP_INT_ENA - reg_0p1a_0_counter after xpd reach target0 - 14 - 1 - read-write - - - _0P1A_CNT_TARGET1_REACH_0_LP_INT_ENA - reg_0p1a_1_counter after xpd reach target1 - 15 - 1 - read-write - - - _0P1A_CNT_TARGET0_REACH_1_LP_INT_ENA - reg_0p1a_0 counter after xpd reach target0 - 16 - 1 - read-write - - - _0P1A_CNT_TARGET1_REACH_1_LP_INT_ENA - reg_0p1a_1_counter after xpd reach target1 - 17 - 1 - read-write - - - _0P2A_CNT_TARGET0_REACH_0_LP_INT_ENA - reg_0p2a_0 counter after xpd reach target0 - 18 - 1 - read-write - - - _0P2A_CNT_TARGET1_REACH_0_LP_INT_ENA - reg_0p2a_1_counter after xpd reach target1 - 19 - 1 - read-write - - - _0P2A_CNT_TARGET0_REACH_1_LP_INT_ENA - reg_0p2a_0 counter after xpd reach target0 - 20 - 1 - read-write - - - _0P2A_CNT_TARGET1_REACH_1_LP_INT_ENA - reg_0p2a_1_counter after xpd reach target1 - 21 - 1 - read-write - - - _0P3A_CNT_TARGET0_REACH_0_LP_INT_ENA - reg_0p3a_0 counter after xpd reach target0 - 22 - 1 - read-write - - - _0P3A_CNT_TARGET1_REACH_0_LP_INT_ENA - reg_0p3a_1_counter after xpd reach target1 - 23 - 1 - read-write - - - _0P3A_CNT_TARGET0_REACH_1_LP_INT_ENA - reg_0p3a_0_counter after xpd reach target0 - 24 - 1 - read-write - - - _0P3A_CNT_TARGET1_REACH_1_LP_INT_ENA - reg_0p3a_1_counter after xpd reach target1 - 25 - 1 - read-write - - - LP_CPU_WAKEUP_INT_ENA - need_des - 26 - 1 - read-write - - - SLEEP_SWITCH_ACTIVE_END_INT_ENA - need_des - 27 - 1 - read-write - - - ACTIVE_SWITCH_SLEEP_END_INT_ENA - need_des - 28 - 1 - read-write - - - SLEEP_SWITCH_ACTIVE_START_INT_ENA - need_des - 29 - 1 - read-write - - - ACTIVE_SWITCH_SLEEP_START_INT_ENA - need_des - 30 - 1 - read-write - - - HP_SW_TRIGGER_INT_ENA - need_des - 31 - 1 - read-write - - - - - LP_INT_CLR - need_des - 0x180 - 0x20 - - - LP_CPU_SLEEP_REJECT_LP_INT_CLR - need_des - 13 - 1 - write-only - - - _0P1A_CNT_TARGET0_REACH_0_LP_INT_CLR - reg_0p1a_0_counter after xpd reach target0 - 14 - 1 - write-only - - - _0P1A_CNT_TARGET1_REACH_0_LP_INT_CLR - reg_0p1a_1_counter after xpd reach target1 - 15 - 1 - write-only - - - _0P1A_CNT_TARGET0_REACH_1_LP_INT_CLR - reg_0p1a_0 counter after xpd reach target0 - 16 - 1 - write-only - - - _0P1A_CNT_TARGET1_REACH_1_LP_INT_CLR - reg_0p1a_1_counter after xpd reach target1 - 17 - 1 - write-only - - - _0P2A_CNT_TARGET0_REACH_0_LP_INT_CLR - reg_0p2a_0 counter after xpd reach target0 - 18 - 1 - write-only - - - _0P2A_CNT_TARGET1_REACH_0_LP_INT_CLR - reg_0p2a_1_counter after xpd reach target1 - 19 - 1 - write-only - - - _0P2A_CNT_TARGET0_REACH_1_LP_INT_CLR - reg_0p2a_0 counter after xpd reach target0 - 20 - 1 - write-only - - - _0P2A_CNT_TARGET1_REACH_1_LP_INT_CLR - reg_0p2a_1_counter after xpd reach target1 - 21 - 1 - write-only - - - _0P3A_CNT_TARGET0_REACH_0_LP_INT_CLR - reg_0p3a_0 counter after xpd reach target0 - 22 - 1 - write-only - - - _0P3A_CNT_TARGET1_REACH_0_LP_INT_CLR - reg_0p3a_1_counter after xpd reach target1 - 23 - 1 - write-only - - - _0P3A_CNT_TARGET0_REACH_1_LP_INT_CLR - reg_0p3a_0_counter after xpd reach target0 - 24 - 1 - write-only - - - _0P3A_CNT_TARGET1_REACH_1_LP_INT_CLR - reg_0p3a_1_counter after xpd reach target1 - 25 - 1 - write-only - - - LP_CPU_WAKEUP_INT_CLR - need_des - 26 - 1 - write-only - - - SLEEP_SWITCH_ACTIVE_END_INT_CLR - need_des - 27 - 1 - write-only - - - ACTIVE_SWITCH_SLEEP_END_INT_CLR - need_des - 28 - 1 - write-only - - - SLEEP_SWITCH_ACTIVE_START_INT_CLR - need_des - 29 - 1 - write-only - - - ACTIVE_SWITCH_SLEEP_START_INT_CLR - need_des - 30 - 1 - write-only - - - HP_SW_TRIGGER_INT_CLR - need_des - 31 - 1 - write-only - - - - - LP_CPU_PWR0 - need_des - 0x184 - 0x20 - 0x1FF00000 - - - LP_CPU_WAITI_RDY - need_des - 0 - 1 - read-only - - - LP_CPU_STALL_RDY - need_des - 1 - 1 - read-only - - - LP_CPU_FORCE_STALL - need_des - 18 - 1 - read-write - - - LP_CPU_SLP_WAITI_FLAG_EN - need_des - 19 - 1 - read-write - - - LP_CPU_SLP_STALL_FLAG_EN - need_des - 20 - 1 - read-write - - - LP_CPU_SLP_STALL_WAIT - need_des - 21 - 8 - read-write - - - LP_CPU_SLP_STALL_EN - need_des - 29 - 1 - read-write - - - LP_CPU_SLP_RESET_EN - need_des - 30 - 1 - read-write - - - LP_CPU_SLP_BYPASS_INTR_EN - need_des - 31 - 1 - read-write - - - - - LP_CPU_PWR1 - need_des - 0x188 - 0x20 - - - LP_CPU_SLEEP_REQ - need_des - 31 - 1 - write-only - - - - - LP_CPU_PWR2 - need_des - 0x18C - 0x20 - - - LP_CPU_WAKEUP_EN - need_des - 0 - 31 - read-write - - - - - LP_CPU_PWR3 - need_des - 0x190 - 0x20 - - - LP_CPU_WAKEUP_CAUSE - need_des - 0 - 31 - read-only - - - - - LP_CPU_PWR4 - need_des - 0x194 - 0x20 - - - LP_CPU_REJECT_EN - need_des - 0 - 31 - read-write - - - - - LP_CPU_PWR5 - need_des - 0x198 - 0x20 - - - LP_CPU_REJECT_CAUSE - need_des - 0 - 31 - read-only - - - - - HP_LP_CPU_COMM - need_des - 0x19C - 0x20 - - - LP_TRIGGER_HP - need_des - 30 - 1 - write-only - - - HP_TRIGGER_LP - need_des - 31 - 1 - write-only - - - - - HP_REGULATOR_CFG - need_des - 0x1A0 - 0x20 - - - DIG_REGULATOR_EN_CAL - need_des - 31 - 1 - read-write - - - - - MAIN_STATE - need_des - 0x1A4 - 0x20 - 0x08100801 - - - ENABLE_CALI_PMU_CNTL - need_des - 0 - 1 - read-write - - - PMU_MAIN_LAST_ST_STATE - need_des - 11 - 7 - read-only - - - PMU_MAIN_TAR_ST_STATE - need_des - 18 - 7 - read-only - - - PMU_MAIN_CUR_ST_STATE - need_des - 25 - 7 - read-only - - - - - PWR_STATE - need_des - 0x1A8 - 0x20 - 0x00802000 - - - PMU_BACKUP_ST_STATE - need_des - 13 - 5 - read-only - - - PMU_LP_PWR_ST_STATE - need_des - 18 - 5 - read-only - - - PMU_HP_PWR_ST_STATE - need_des - 23 - 9 - read-only - - - - - CLK_STATE0 - need_des - 0x1AC - 0x20 - 0x0000000F - - - STABLE_XPD_PLL_STATE - need_des - 0 - 3 - read-only - - - STABLE_XPD_XTAL_STATE - need_des - 3 - 1 - read-only - - - PMU_ANA_XPD_PLL_I2C_STATE - need_des - 4 - 3 - read-only - - - PMU_SYS_CLK_SLP_SEL_STATE - need_des - 10 - 1 - read-only - - - PMU_SYS_CLK_SEL_STATE - need_des - 11 - 2 - read-only - - - PMU_SYS_CLK_NO_DIV_STATE - need_des - 13 - 1 - read-only - - - PMU_ICG_SYS_CLK_EN_STATE - need_des - 14 - 1 - read-only - - - PMU_ICG_MODEM_SWITCH_STATE - need_des - 15 - 1 - read-only - - - PMU_ICG_MODEM_CODE_STATE - need_des - 16 - 2 - read-only - - - PMU_ICG_SLP_SEL_STATE - need_des - 18 - 1 - read-only - - - PMU_ICG_GLOBAL_XTAL_STATE - need_des - 19 - 1 - read-only - - - PMU_ICG_GLOBAL_PLL_STATE - need_des - 20 - 4 - read-only - - - PMU_ANA_I2C_ISO_EN_STATE - need_des - 24 - 1 - read-only - - - PMU_ANA_I2C_RETENTION_STATE - need_des - 25 - 1 - read-only - - - PMU_ANA_XPD_PLL_STATE - need_des - 27 - 4 - read-only - - - PMU_ANA_XPD_XTAL_STATE - need_des - 31 - 1 - read-only - - - - - CLK_STATE1 - need_des - 0x1B0 - 0x20 - 0xFFFFFFFF - - - PMU_ICG_FUNC_EN_STATE - need_des - 0 - 32 - read-only - - - - - CLK_STATE2 - need_des - 0x1B4 - 0x20 - 0xFFFFFFFF - - - PMU_ICG_APB_EN_STATE - need_des - 0 - 32 - read-only - - - - - EXT_LDO_P0_0P1A - need_des - 0x1B8 - 0x20 - 0x40200100 - - - _0P1A_FORCE_TIEH_SEL_0 - need_des - 7 - 1 - read-write - - - _0P1A_XPD_0 - need_des - 8 - 1 - read-write - - - _0P1A_TIEH_SEL_0 - need_des - 9 - 3 - read-write - - - _0P1A_TIEH_POS_EN_0 - need_des - 12 - 1 - read-write - - - _0P1A_TIEH_NEG_EN_0 - need_des - 13 - 1 - read-write - - - _0P1A_TIEH_0 - need_des - 14 - 1 - read-write - - - _0P1A_TARGET1_0 - need_des - 15 - 8 - read-write - - - _0P1A_TARGET0_0 - need_des - 23 - 8 - read-write - - - _0P1A_LDO_CNT_PRESCALER_SEL_0 - need_des - 31 - 1 - read-write - - - - - EXT_LDO_P0_0P1A_ANA - need_des - 0x1BC - 0x20 - 0xB1000000 - - - ANA_0P1A_MUL_0 - need_des - 23 - 3 - read-write - - - ANA_0P1A_EN_VDET_0 - need_des - 26 - 1 - read-write - - - ANA_0P1A_EN_CUR_LIM_0 - need_des - 27 - 1 - read-write - - - ANA_0P1A_DREF_0 - need_des - 28 - 4 - read-write - - - - - EXT_LDO_P0_0P2A - need_des - 0x1C0 - 0x20 - 0x40200000 - - - _0P2A_FORCE_TIEH_SEL_0 - need_des - 7 - 1 - read-write - - - _0P2A_XPD_0 - need_des - 8 - 1 - read-write - - - _0P2A_TIEH_SEL_0 - need_des - 9 - 3 - read-write - - - _0P2A_TIEH_POS_EN_0 - need_des - 12 - 1 - read-write - - - _0P2A_TIEH_NEG_EN_0 - need_des - 13 - 1 - read-write - - - _0P2A_TIEH_0 - need_des - 14 - 1 - read-write - - - _0P2A_TARGET1_0 - need_des - 15 - 8 - read-write - - - _0P2A_TARGET0_0 - need_des - 23 - 8 - read-write - - - _0P2A_LDO_CNT_PRESCALER_SEL_0 - need_des - 31 - 1 - read-write - - - - - EXT_LDO_P0_0P2A_ANA - need_des - 0x1C4 - 0x20 - 0xA0000000 - - - ANA_0P2A_MUL_0 - need_des - 23 - 3 - read-write - - - ANA_0P2A_EN_VDET_0 - need_des - 26 - 1 - read-write - - - ANA_0P2A_EN_CUR_LIM_0 - need_des - 27 - 1 - read-write - - - ANA_0P2A_DREF_0 - need_des - 28 - 4 - read-write - - - - - EXT_LDO_P0_0P3A - need_des - 0x1C8 - 0x20 - 0x40200000 - - - _0P3A_FORCE_TIEH_SEL_0 - need_des - 7 - 1 - read-write - - - _0P3A_XPD_0 - need_des - 8 - 1 - read-write - - - _0P3A_TIEH_SEL_0 - need_des - 9 - 3 - read-write - - - _0P3A_TIEH_POS_EN_0 - need_des - 12 - 1 - read-write - - - _0P3A_TIEH_NEG_EN_0 - need_des - 13 - 1 - read-write - - - _0P3A_TIEH_0 - need_des - 14 - 1 - read-write - - - _0P3A_TARGET1_0 - need_des - 15 - 8 - read-write - - - _0P3A_TARGET0_0 - need_des - 23 - 8 - read-write - - - _0P3A_LDO_CNT_PRESCALER_SEL_0 - need_des - 31 - 1 - read-write - - - - - EXT_LDO_P0_0P3A_ANA - need_des - 0x1CC - 0x20 - 0xA0000000 - - - ANA_0P3A_MUL_0 - need_des - 23 - 3 - read-write - - - ANA_0P3A_EN_VDET_0 - need_des - 26 - 1 - read-write - - - ANA_0P3A_EN_CUR_LIM_0 - need_des - 27 - 1 - read-write - - - ANA_0P3A_DREF_0 - need_des - 28 - 4 - read-write - - - - - EXT_LDO_P1_0P1A - need_des - 0x1D0 - 0x20 - 0x40200000 - - - _0P1A_FORCE_TIEH_SEL_1 - need_des - 7 - 1 - read-write - - - _0P1A_XPD_1 - need_des - 8 - 1 - read-write - - - _0P1A_TIEH_SEL_1 - need_des - 9 - 3 - read-write - - - _0P1A_TIEH_POS_EN_1 - need_des - 12 - 1 - read-write - - - _0P1A_TIEH_NEG_EN_1 - need_des - 13 - 1 - read-write - - - _0P1A_TIEH_1 - need_des - 14 - 1 - read-write - - - _0P1A_TARGET1_1 - need_des - 15 - 8 - read-write - - - _0P1A_TARGET0_1 - need_des - 23 - 8 - read-write - - - _0P1A_LDO_CNT_PRESCALER_SEL_1 - need_des - 31 - 1 - read-write - - - - - EXT_LDO_P1_0P1A_ANA - need_des - 0x1D4 - 0x20 - 0xA0000000 - - - ANA_0P1A_MUL_1 - need_des - 23 - 3 - read-write - - - ANA_0P1A_EN_VDET_1 - need_des - 26 - 1 - read-write - - - ANA_0P1A_EN_CUR_LIM_1 - need_des - 27 - 1 - read-write - - - ANA_0P1A_DREF_1 - need_des - 28 - 4 - read-write - - - - - EXT_LDO_P1_0P2A - need_des - 0x1D8 - 0x20 - 0x40200000 - - - _0P2A_FORCE_TIEH_SEL_1 - need_des - 7 - 1 - read-write - - - _0P2A_XPD_1 - need_des - 8 - 1 - read-write - - - _0P2A_TIEH_SEL_1 - need_des - 9 - 3 - read-write - - - _0P2A_TIEH_POS_EN_1 - need_des - 12 - 1 - read-write - - - _0P2A_TIEH_NEG_EN_1 - need_des - 13 - 1 - read-write - - - _0P2A_TIEH_1 - need_des - 14 - 1 - read-write - - - _0P2A_TARGET1_1 - need_des - 15 - 8 - read-write - - - _0P2A_TARGET0_1 - need_des - 23 - 8 - read-write - - - _0P2A_LDO_CNT_PRESCALER_SEL_1 - need_des - 31 - 1 - read-write - - - - - EXT_LDO_P1_0P2A_ANA - need_des - 0x1DC - 0x20 - 0xA0000000 - - - ANA_0P2A_MUL_1 - need_des - 23 - 3 - read-write - - - ANA_0P2A_EN_VDET_1 - need_des - 26 - 1 - read-write - - - ANA_0P2A_EN_CUR_LIM_1 - need_des - 27 - 1 - read-write - - - ANA_0P2A_DREF_1 - need_des - 28 - 4 - read-write - - - - - EXT_LDO_P1_0P3A - need_des - 0x1E0 - 0x20 - 0x40200000 - - - _0P3A_FORCE_TIEH_SEL_1 - need_des - 7 - 1 - read-write - - - _0P3A_XPD_1 - need_des - 8 - 1 - read-write - - - _0P3A_TIEH_SEL_1 - need_des - 9 - 3 - read-write - - - _0P3A_TIEH_POS_EN_1 - need_des - 12 - 1 - read-write - - - _0P3A_TIEH_NEG_EN_1 - need_des - 13 - 1 - read-write - - - _0P3A_TIEH_1 - need_des - 14 - 1 - read-write - - - _0P3A_TARGET1_1 - need_des - 15 - 8 - read-write - - - _0P3A_TARGET0_1 - need_des - 23 - 8 - read-write - - - _0P3A_LDO_CNT_PRESCALER_SEL_1 - need_des - 31 - 1 - read-write - - - - - EXT_LDO_P1_0P3A_ANA - need_des - 0x1E4 - 0x20 - 0xA0000000 - - - ANA_0P3A_MUL_1 - need_des - 23 - 3 - read-write - - - ANA_0P3A_EN_VDET_1 - need_des - 26 - 1 - read-write - - - ANA_0P3A_EN_CUR_LIM_1 - need_des - 27 - 1 - read-write - - - ANA_0P3A_DREF_1 - need_des - 28 - 4 - read-write - - - - - EXT_WAKEUP_LV - need_des - 0x1E8 - 0x20 - - - EXT_WAKEUP_LV - need_des - 0 - 32 - read-write - - - - - EXT_WAKEUP_SEL - need_des - 0x1EC - 0x20 - - - EXT_WAKEUP_SEL - need_des - 0 - 32 - read-write - - - - - EXT_WAKEUP_ST - need_des - 0x1F0 - 0x20 - - - EXT_WAKEUP_STATUS - need_des - 0 - 32 - read-only - - - - - EXT_WAKEUP_CNTL - need_des - 0x1F4 - 0x20 - - - EXT_WAKEUP_STATUS_CLR - need_des - 30 - 1 - read-write - - - EXT_WAKEUP_FILTER - need_des - 31 - 1 - read-write - - - - - SDIO_WAKEUP_CNTL - need_des - 0x1F8 - 0x20 - 0x000003FF - - - SDIO_ACT_DNUM - need_des - 0 - 10 - read-write - - - - - XTAL_SLP - need_des - 0x1FC - 0x20 - 0x000F0000 - - - CNT_TARGET - need_des - 16 - 16 - read-write - - - - - CPU_SW_STALL - need_des - 0x200 - 0x20 - - - HPCORE1_SW_STALL_CODE - need_des - 16 - 8 - read-write - - - HPCORE0_SW_STALL_CODE - need_des - 24 - 8 - read-write - - - - - DCM_CTRL - need_des - 0x204 - 0x20 - 0x00010000 - - - DCDC_ON_REQ - SW trigger dcdc on - 0 - 1 - write-only - - - DCDC_OFF_REQ - SW trigger dcdc off - 1 - 1 - write-only - - - DCDC_LIGHTSLP_REQ - SW trigger dcdc enter lightsleep - 2 - 1 - write-only - - - DCDC_DEEPSLP_REQ - SW trigger dcdc enter deepsleep - 3 - 1 - write-only - - - DCDC_DONE_FORCE - need_des - 7 - 1 - read-write - - - DCDC_ON_FORCE_PU - need_des - 8 - 1 - read-write - - - DCDC_ON_FORCE_PD - need_des - 9 - 1 - read-write - - - DCDC_FB_RES_FORCE_PU - need_des - 10 - 1 - read-write - - - DCDC_FB_RES_FORCE_PD - need_des - 11 - 1 - read-write - - - DCDC_LS_FORCE_PU - need_des - 12 - 1 - read-write - - - DCDC_LS_FORCE_PD - need_des - 13 - 1 - read-write - - - DCDC_DS_FORCE_PU - need_des - 14 - 1 - read-write - - - DCDC_DS_FORCE_PD - need_des - 15 - 1 - read-write - - - DCM_CUR_ST - need_des - 16 - 8 - read-only - - - DCDC_EN_AMUX_TEST - Enable analog mux to pull PAD TEST_DCDC voltage signal - 29 - 1 - read-write - - - - - DCM_WAIT_DELAY - need_des - 0x208 - 0x20 - 0x004B0205 - - - DCDC_PRE_DELAY - DCDC pre-on/post off delay - 0 - 8 - read-write - - - DCDC_RES_OFF_DELAY - DCDC fb res off delay - 8 - 8 - read-write - - - DCDC_STABLE_DELAY - DCDC stable delay - 16 - 10 - read-write - - - - - VDDBAT_CFG - need_des - 0x20C - 0x20 - - - ANA_VDDBAT_MODE - need_des - 0 - 2 - read-only - - - VDDBAT_SW_UPDATE - need_des - 31 - 1 - write-only - - - - - TOUCH_PWR_CNTL - need_des - 0x210 - 0x20 - 0x00190140 - - - TOUCH_WAIT_CYCLES - need_des - 5 - 9 - read-write - - - TOUCH_SLEEP_CYCLES - need_des - 14 - 16 - read-write - - - TOUCH_FORCE_DONE - need_des - 30 - 1 - read-write - - - TOUCH_SLEEP_TIMER_EN - need_des - 31 - 1 - read-write - - - - - RDN_ECO - need_des - 0x214 - 0x20 - - - PMU_RDN_ECO_RESULT - need_des - 0 - 1 - read-only - - - PMU_RDN_ECO_EN - need_des - 31 - 1 - read-write - - - - - DATE - need_des - 0x3FC - 0x20 - 0x02303140 - - - PMU_DATE - need_des - 0 - 31 - read-write - - - CLK_EN - need_des - 31 - 1 - read-write - - - - - - - PPA - PPA Peripheral - PPA - 0x50087000 - - 0x0 - 0x88 - registers - - - PPA - 96 - - - - BLEND0_CLUT_DATA - CLUT sram data read/write register in background plane of blender - 0x0 - 0x20 - - - RDWR_WORD_BLEND0_CLUT - Write and read data to/from CLUT RAM in background plane of blender engine through this field in fifo mode. - 0 - 32 - read-write - - - - - BLEND1_CLUT_DATA - CLUT sram data read/write register in foreground plane of blender - 0x4 - 0x20 - - - RDWR_WORD_BLEND1_CLUT - Write and read data to/from CLUT RAM in foreground plane of blender engine through this field in fifo mode. - 0 - 32 - read-write - - - - - CLUT_CONF - CLUT configure register - 0xC - 0x20 - - - APB_FIFO_MASK - 1'b0: fifo mode to wr/rd clut0/clut1 RAM through register PPA_SR_CLUT_DATA_REG/PPA_BLEND0_CLUT_DATA_REG/PPA_BLEND1_CLUT_DATA_REG. 1'b1: memory mode to wr/rd sr/blend0/blend1 clut RAM. The bit 11 and 10 of the waddr should be 01 to access sr clut and should be 10 to access blend0 clut and should be 11 to access blend 1 clut in memory mode. - 0 - 1 - read-write - - - BLEND0_CLUT_MEM_RST - Write 1 then write 0 to this bit to reset BLEND0 CLUT. - 1 - 1 - read-write - - - BLEND1_CLUT_MEM_RST - Write 1 then write 0 to this bit to reset BLEND1 CLUT. - 2 - 1 - read-write - - - BLEND0_CLUT_MEM_RDADDR_RST - Write 1 then write 0 to reset the read address of BLEND0 CLUT in fifo mode. - 3 - 1 - read-write - - - BLEND1_CLUT_MEM_RDADDR_RST - Write 1 then write 0 to reset the read address of BLEND1 CLUT in fifo mode. - 4 - 1 - read-write - - - BLEND0_CLUT_MEM_FORCE_PD - 1: force power down BLEND CLUT memory. - 5 - 1 - read-write - - - BLEND0_CLUT_MEM_FORCE_PU - 1: force power up BLEND CLUT memory. - 6 - 1 - read-write - - - BLEND0_CLUT_MEM_CLK_ENA - 1: Force clock on for BLEND CLUT memory. - 7 - 1 - read-write - - - - - INT_RAW - Raw status interrupt - 0x10 - 0x20 - - - SR_EOF_INT_RAW - The raw interrupt bit turns to high level when scaling and rotating engine calculate one frame image. - 0 - 1 - read-write - - - BLEND_EOF_INT_RAW - The raw interrupt bit turns to high level when blending engine calculate one frame image. - 1 - 1 - read-write - - - SR_PARAM_CFG_ERR_INT_RAW - The raw interrupt bit turns to high level when the configured scaling and rotating coefficient is wrong. User can check the reasons through register PPA_SR_PARAM_ERR_ST_REG. - 2 - 1 - read-write - - - - - INT_ST - Masked interrupt - 0x14 - 0x20 - - - SR_EOF_INT_ST - The raw interrupt status bit for the PPA_SR_EOF_INT interrupt. - 0 - 1 - read-only - - - BLEND_EOF_INT_ST - The raw interrupt status bit for the PPA_BLEND_EOF_INT interrupt. - 1 - 1 - read-only - - - SR_PARAM_CFG_ERR_INT_ST - The raw interrupt status bit for the PPA_SR_RX_YSCAL_ERR_INT interrupt. - 2 - 1 - read-only - - - - - INT_ENA - Interrupt enable bits - 0x18 - 0x20 - - - SR_EOF_INT_ENA - The interrupt enable bit for the PPA_SR_EOF_INT interrupt. - 0 - 1 - read-write - - - BLEND_EOF_INT_ENA - The interrupt enable bit for the PPA_BLEND_EOF_INT interrupt. - 1 - 1 - read-write - - - SR_PARAM_CFG_ERR_INT_ENA - The interrupt enable bit for the PPA_SR_RX_YSCAL_ERR_INT interrupt. - 2 - 1 - read-write - - - - - INT_CLR - Interrupt clear bits - 0x1C - 0x20 - - - SR_EOF_INT_CLR - Set this bit to clear the PPA_SR_EOF_INT interrupt. - 0 - 1 - write-only - - - BLEND_EOF_INT_CLR - Set this bit to clear the PPA_BLEND_EOF_INT interrupt. - 1 - 1 - write-only - - - SR_PARAM_CFG_ERR_INT_CLR - Set this bit to clear the PPA_SR_RX_YSCAL_ERR_INT interrupt. - 2 - 1 - write-only - - - - - SR_COLOR_MODE - Scaling and rotating engine color mode register - 0x20 - 0x20 - - - SR_RX_CM - The source image color mode for Scaling and Rotating engine Rx. 0: ARGB8888. 1: RGB888. 2: RGB565. 8: YUV420. others: Reserved. - 0 - 4 - read-write - - - SR_TX_CM - The destination image color mode for Scaling and Rotating engine Tx. 0: ARGB8888. 1: RGB888. 2: RGB565. 8: YUV420. others: Reserved. - 4 - 4 - read-write - - - YUV_RX_RANGE - YUV input range when reg_sr_rx_cm is 4'd8. 0: limit range. 1: full range - 8 - 1 - read-write - - - YUV_TX_RANGE - YUV output range when reg_sr_tx_cm is 4'd8. 0: limit range. 1: full range - 9 - 1 - read-write - - - YUV2RGB_PROTOCAL - YUV to RGB protocal when reg_sr_rx_cm is 4'd8. 0: BT601. 1: BT709 - 10 - 1 - read-write - - - RGB2YUV_PROTOCAL - RGB to YUV protocal when reg_sr_tx_cm is 4'd8. 0: BT601. 1: BT709 - 11 - 1 - read-write - - - - - BLEND_COLOR_MODE - blending engine color mode register - 0x24 - 0x20 - - - BLEND0_RX_CM - The source image color mode for background plane. 0: ARGB8888. 1: RGB888. 2: RGB565. 3: Reserved. 4: L8. 5: L4. - 0 - 4 - read-write - - - BLEND1_RX_CM - The source image color mode for foreground plane. 0: ARGB8888. 1: RGB888. 2: RGB565. 3: Reserved. 4: L8. 5: L4. 6: A8. 7: A4. - 4 - 4 - read-write - - - BLEND_TX_CM - The destination image color mode for output of blender. 0: ARGB8888. 1: RGB888. 2: RGB565. 3: Reserved.. - 8 - 4 - read-write - - - - - SR_BYTE_ORDER - Scaling and rotating engine byte order register - 0x28 - 0x20 - - - SR_RX_BYTE_SWAP_EN - Set this bit to 1 the data into Rx channel 0 would be swapped in byte. The Byte0 and Byte1 would be swapped while byte 2 and byte 3 would be swappped. - 0 - 1 - read-write - - - SR_RX_RGB_SWAP_EN - Set this bit to 1 the data into Rx channel 0 would be swapped in rgb. It means rgb would be swap to bgr. - 1 - 1 - read-write - - - SR_MACRO_BK_RO_BYPASS - Set this bit to 1 to bypass the macro block order function. This function is used to improve efficient accessing external memory. - 2 - 1 - read-write - - - - - BLEND_BYTE_ORDER - Blending engine byte order register - 0x2C - 0x20 - - - BLEND0_RX_BYTE_SWAP_EN - Set this bit to 1 the data into Rx channel 0 would be swapped in byte. The Byte0 and Byte1 would be swapped while byte 2 and byte 3 would be swappped. - 0 - 1 - read-write - - - BLEND1_RX_BYTE_SWAP_EN - Set this bit to 1 the data into Rx channel 0 would be swapped in byte. The Byte0 and Byte1 would be swapped while byte 2 and byte 3 would be swappped. - 1 - 1 - read-write - - - BLEND0_RX_RGB_SWAP_EN - Set this bit to 1 the data into Rx channel 0 would be swapped in rgb. It means rgb would be swap to bgr. - 2 - 1 - read-write - - - BLEND1_RX_RGB_SWAP_EN - Set this bit to 1 the data into Rx channel 0 would be swapped in rgb. It means rgb would be swap to bgr. - 3 - 1 - read-write - - - - - BLEND_TRANS_MODE - Blending engine mode configure register - 0x34 - 0x20 - - - BLEND_EN - Set this bit to enable alpha blending. - 0 - 1 - read-write - - - BLEND_BYPASS - Set this bit to bypass blender. Then background date would be output. - 1 - 1 - read-write - - - BLEND_FIX_PIXEL_FILL_EN - This bit is used to enable fix pixel filling. When this mode is enable only Tx channel is work and the output pixel is configured by PPA_OUT_FIX_PIXEL. - 2 - 1 - read-write - - - UPDATE - Set this bit to update the transfer mode. Only the bit is set the transfer mode is valid. - 3 - 1 - write-only - - - BLEND_RST - write 1 then write 0 to reset blending engine. - 4 - 1 - read-write - - - - - SR_FIX_ALPHA - Scaling and rotating engine alpha override register - 0x38 - 0x20 - 0x00000080 - - - SR_RX_FIX_ALPHA - The value would replace the alpha value in received pixel for Scaling and Rotating engine when PPA_SR_RX_ALPHA_CONF_EN is enabled. - 0 - 8 - read-write - - - SR_RX_ALPHA_MOD - Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_SR_FIX_ALPHA. 2: Original alpha multiply with PPA_SR_FIX_ALPHA/256. - 8 - 2 - read-write - - - SR_RX_ALPHA_INV - Set this bit to invert the original alpha value. When RX color mode is RGB565/RGB88. The original alpha value is 255. - 10 - 1 - read-write - - - - - BLEND_TX_SIZE - Fix pixel filling mode image size register - 0x3C - 0x20 - - - BLEND_HB - The horizontal width of image block that would be filled in fix pixel filling mode. The unit is pixel - 0 - 14 - read-write - - - BLEND_VB - The vertical width of image block that would be filled in fix pixel filling mode. The unit is pixel - 14 - 14 - read-write - - - - - BLEND_FIX_ALPHA - Blending engine alpha override register - 0x40 - 0x20 - 0x00008080 - - - BLEND0_RX_FIX_ALPHA - The value would replace the alpha value in received pixel for background plane of blender when PPA_BLEND0_RX_ALPHA_CONF_EN is enabled. - 0 - 8 - read-write - - - BLEND1_RX_FIX_ALPHA - The value would replace the alpha value in received pixel for foreground plane of blender when PPA_BLEND1_RX_ALPHA_CONF_EN is enabled. - 8 - 8 - read-write - - - BLEND0_RX_ALPHA_MOD - Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_SR_FIX_ALPHA. 2: Original alpha multiply with PPA_SR_FIX_ALPHA/256. - 16 - 2 - read-write - - - BLEND1_RX_ALPHA_MOD - Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_SR_FIX_ALPHA. 2: Original alpha multiply with PPA_SR_FIX_ALPHA/256. - 18 - 2 - read-write - - - BLEND0_RX_ALPHA_INV - Set this bit to invert the original alpha value. When RX color mode is RGB565/RGB88. The original alpha value is 255. - 20 - 1 - read-write - - - BLEND1_RX_ALPHA_INV - Set this bit to invert the original alpha value. When RX color mode is RGB565/RGB88. The original alpha value is 255. - 21 - 1 - read-write - - - - - BLEND_RGB - RGB color register - 0x48 - 0x20 - 0x00808080 - - - BLEND1_RX_B - blue color for A4/A8 mode. - 0 - 8 - read-write - - - BLEND1_RX_G - green color for A4/A8 mode. - 8 - 8 - read-write - - - BLEND1_RX_R - red color for A4/A8 mode. - 16 - 8 - read-write - - - - - BLEND_FIX_PIXEL - Blending engine fix pixel register - 0x4C - 0x20 - - - BLEND_TX_FIX_PIXEL - The configure fix pixel in fix pixel filling mode for blender engine. - 0 - 32 - read-write - - - - - CK_FG_LOW - foreground color key lower threshold - 0x50 - 0x20 - 0x00FFFFFF - - - COLORKEY_FG_B_LOW - color key lower threshold of foreground b channel - 0 - 8 - read-write - - - COLORKEY_FG_G_LOW - color key lower threshold of foreground g channel - 8 - 8 - read-write - - - COLORKEY_FG_R_LOW - color key lower threshold of foreground r channel - 16 - 8 - read-write - - - - - CK_FG_HIGH - foreground color key higher threshold - 0x54 - 0x20 - - - COLORKEY_FG_B_HIGH - color key higher threshold of foreground b channel - 0 - 8 - read-write - - - COLORKEY_FG_G_HIGH - color key higher threshold of foreground g channel - 8 - 8 - read-write - - - COLORKEY_FG_R_HIGH - color key higher threshold of foreground r channel - 16 - 8 - read-write - - - - - CK_BG_LOW - background color key lower threshold - 0x58 - 0x20 - 0x00FFFFFF - - - COLORKEY_BG_B_LOW - color key lower threshold of background b channel - 0 - 8 - read-write - - - COLORKEY_BG_G_LOW - color key lower threshold of background g channel - 8 - 8 - read-write - - - COLORKEY_BG_R_LOW - color key lower threshold of background r channel - 16 - 8 - read-write - - - - - CK_BG_HIGH - background color key higher threshold - 0x5C - 0x20 - - - COLORKEY_BG_B_HIGH - color key higher threshold of background b channel - 0 - 8 - read-write - - - COLORKEY_BG_G_HIGH - color key higher threshold of background g channel - 8 - 8 - read-write - - - COLORKEY_BG_R_HIGH - color key higher threshold of background r channel - 16 - 8 - read-write - - - - - CK_DEFAULT - default value when foreground and background both in color key range - 0x60 - 0x20 - - - COLORKEY_DEFAULT_B - default B channle value of color key - 0 - 8 - read-write - - - COLORKEY_DEFAULT_G - default G channle value of color key - 8 - 8 - read-write - - - COLORKEY_DEFAULT_R - default R channle value of color key - 16 - 8 - read-write - - - COLORKEY_FG_BG_REVERSE - when pixel in bg ck range but not in fg ck range, 0: the result is bg, 1: the result is fg - 24 - 1 - read-write - - - - - SR_SCAL_ROTATE - Scaling and rotating coefficient register - 0x64 - 0x20 - 0x00001001 - - - SR_SCAL_X_INT - The integrated part of scaling coefficient in X direction. - 0 - 8 - read-write - - - SR_SCAL_X_FRAG - The fragment part of scaling coefficient in X direction. - 8 - 4 - read-write - - - SR_SCAL_Y_INT - The integrated part of scaling coefficient in Y direction. - 12 - 8 - read-write - - - SR_SCAL_Y_FRAG - The fragment part of scaling coefficient in Y direction. - 20 - 4 - read-write - - - SR_ROTATE_ANGLE - The rotate angle. 0: 0 degree. 1: 90 degree. 2: 180 degree. 3: 270 degree. - 24 - 2 - read-write - - - SCAL_ROTATE_RST - Write 1 then write 0 to this bit to reset scaling and rotating engine. - 26 - 1 - read-write - - - SCAL_ROTATE_START - Write 1 to enable scaling and rotating engine after parameter is configured. - 27 - 1 - write-only - - - SR_MIRROR_X - Image mirror in X direction. 0: disable, 1: enable - 28 - 1 - read-write - - - SR_MIRROR_Y - Image mirror in Y direction. 0: disable, 1: enable - 29 - 1 - read-write - - - - - SR_MEM_PD - SR memory power done register - 0x68 - 0x20 - - - SR_MEM_CLK_ENA - Set this bit to force clock enable of scaling and rotating engine's data memory. - 0 - 1 - read-write - - - SR_MEM_FORCE_PD - Set this bit to force power down scaling and rotating engine's data memory. - 1 - 1 - read-write - - - SR_MEM_FORCE_PU - Set this bit to force power up scaling and rotating engine's data memory. - 2 - 1 - read-write - - - - - REG_CONF - Register clock enable register - 0x6C - 0x20 - - - CLK_EN - PPA register clock gate enable signal. - 0 - 1 - read-write - - - - - CLUT_CNT - BLEND CLUT write counter register - 0x70 - 0x20 - - - BLEND0_CLUT_CNT - The write data counter of BLEND0 CLUT in fifo mode. - 0 - 9 - read-only - - - BLEND1_CLUT_CNT - The write data counter of BLEND1 CLUT in fifo mode. - 9 - 9 - read-only - - - - - BLEND_ST - Blending engine status register - 0x74 - 0x20 - - - BLEND_SIZE_DIFF_ST - 1: indicate the size of two image is different. - 0 - 1 - read-only - - - - - SR_PARAM_ERR_ST - Scaling and rotating coefficient error register - 0x78 - 0x20 - - - TX_DSCR_VB_ERR_ST - The error is that the scaled VB plus the offset of Y coordinate in 2DDMA receive descriptor is larger than VA in 2DDMA receive descriptor. - 0 - 1 - read-only - - - TX_DSCR_HB_ERR_ST - The error is that the scaled HB plus the offset of X coordinate in 2DDMA receive descriptor is larger than HA in 2DDMA receive descriptor. - 1 - 1 - read-only - - - Y_RX_SCAL_EQUAL_0_ERR_ST - The error is that the PPA_SR_SCAL_Y_INT and PPA_SR_CAL_Y_FRAG both are 0. - 2 - 1 - read-only - - - RX_DSCR_VB_ERR_ST - The error is that VB in 2DDMA receive descriptor plus the offset of Y coordinate in 2DDMA transmit descriptor is larger than VA in 2DDMA transmit descriptor - 3 - 1 - read-only - - - YDST_LEN_TOO_SAMLL_ERR_ST - The error is that the scaled image width is 0. For example. when source width is 14. scaled value is 1/16. and no rotate operation. then scaled width would be 0 as the result would be floored. - 4 - 1 - read-only - - - YDST_LEN_TOO_LARGE_ERR_ST - The error is that the scaled width is larger than (2^13 - 1). - 5 - 1 - read-only - - - X_RX_SCAL_EQUAL_0_ERR_ST - The error is that the scaled image height is 0. - 6 - 1 - read-only - - - RX_DSCR_HB_ERR_ST - The error is that the HB in 2DDMA transmit descriptor plus the offset of X coordinate in 2DDMA transmit descriptor is larger than HA in 2DDMA transmit descriptor. - 7 - 1 - read-only - - - XDST_LEN_TOO_SAMLL_ERR_ST - The error is that the scaled image height is 0. For example. when source height is 14. scaled value is 1/16. and no rotate operation. then scaled height would be 0 as the result would be floored. - 8 - 1 - read-only - - - XDST_LEN_TOO_LARGE_ERR_ST - The error is that the scaled image height is larger than (2^13 - 1). - 9 - 1 - read-only - - - X_YUV420_RX_SCALE_ERR_ST - The error is that the ha/hb/x param in dma2d descriptor is an odd num when enable yuv420 rx - 10 - 1 - read-only - - - Y_YUV420_RX_SCALE_ERR_ST - The error is that the va/vb/y param in dma2d descriptor is an odd num when enable yuv420 rx - 11 - 1 - read-only - - - X_YUV420_TX_SCALE_ERR_ST - The error is that the ha/hb/x param in dma2d descriptor is an odd num when enable yuv420 tx - 12 - 1 - read-only - - - Y_YUV420_TX_SCALE_ERR_ST - The error is that the va/vb/y param in dma2d descriptor is an odd num when enable yuv420 tx - 13 - 1 - read-only - - - - - SR_STATUS - SR FSM register - 0x7C - 0x20 - - - SR_RX_DSCR_SAMPLE_STATE - Reserved. - 0 - 2 - read-only - - - SR_RX_SCAN_STATE - Reserved. - 2 - 2 - read-only - - - SR_TX_DSCR_SAMPLE_STATE - Reserved. - 4 - 2 - read-only - - - SR_TX_SCAN_STATE - Reserved. - 6 - 3 - read-only - - - - - ECO_LOW - Reserved. - 0x80 - 0x20 - - - RND_ECO_LOW - Reserved. - 0 - 32 - read-write - - - - - ECO_HIGH - Reserved. - 0x84 - 0x20 - 0xFFFFFFFF - - - RND_ECO_HIGH - Reserved. - 0 - 32 - read-write - - - - - ECO_CELL_CTRL - Reserved. - 0x88 - 0x20 - - - RDN_RESULT - Reserved. - 0 - 1 - read-only - - - RDN_ENA - Reserved. - 1 - 1 - read-write - - - - - SRAM_CTRL - PPA SRAM Control Register - 0x8C - 0x20 - 0x00001320 - - - MEM_AUX_CTRL - Control signals - 0 - 14 - read-write - - - - - DATE - PPA Version register - 0x100 - 0x20 - 0x02304041 - - - DATE - register version. - 0 - 32 - read-write - - - - - - - PVT - PVT Peripheral - PVT - 0x5009E000 - - 0x0 - 0x1F0 - registers - - - - PMUP_BITMAP_HIGH0 - select valid pvt channel - 0x0 - 0x20 - - - PUMP_BITMAP_HIGH0 - select valid high channel0 - 0 - 32 - read-write - - - - - PMUP_BITMAP_HIGH1 - select valid pvt channel - 0x4 - 0x20 - - - PUMP_BITMAP_HIGH1 - select valid high channel1 - 0 - 32 - read-write - - - - - PMUP_BITMAP_HIGH2 - select valid pvt channel - 0x8 - 0x20 - - - PUMP_BITMAP_HIGH2 - select valid high channel2 - 0 - 32 - read-write - - - - - PMUP_BITMAP_HIGH3 - select valid pvt channel - 0xC - 0x20 - - - PUMP_BITMAP_HIGH3 - select valid high channel3 - 0 - 32 - read-write - - - - - PMUP_BITMAP_HIGH4 - select valid pvt channel - 0x10 - 0x20 - - - PUMP_BITMAP_HIGH4 - select valid high channel4 - 0 - 32 - read-write - - - - - PMUP_BITMAP_LOW0 - select valid pvt channel - 0x14 - 0x20 - - - PUMP_BITMAP_LOW0 - select valid low channel0 - 0 - 32 - read-write - - - - - PMUP_BITMAP_LOW1 - select valid pvt channel - 0x18 - 0x20 - - - PUMP_BITMAP_LOW1 - select valid low channel1 - 0 - 32 - read-write - - - - - PMUP_BITMAP_LOW2 - select valid pvt channel - 0x1C - 0x20 - - - PUMP_BITMAP_LOW2 - select valid low channel2 - 0 - 32 - read-write - - - - - PMUP_BITMAP_LOW3 - select valid pvt channel - 0x20 - 0x20 - - - PUMP_BITMAP_LOW3 - select valid low channel3 - 0 - 32 - read-write - - - - - PMUP_BITMAP_LOW4 - select valid pvt channel - 0x24 - 0x20 - - - PUMP_BITMAP_LOW4 - select valid low channel4 - 0 - 32 - read-write - - - - - PMUP_DRV_CFG - configure pump drv - 0x28 - 0x20 - - - PUMP_EN - configure pvt charge xpd - 9 - 1 - read-write - - - CLK_EN - force register clken - 10 - 1 - read-write - - - PUMP_DRV4 - configure cmd4 drv - 11 - 4 - read-write - - - PUMP_DRV3 - configure cmd3 drv - 15 - 4 - read-write - - - PUMP_DRV2 - configure cmd2 drv - 19 - 4 - read-write - - - PUMP_DRV1 - configure cmd1 drv - 23 - 4 - read-write - - - PUMP_DRV0 - configure cmd0 drv - 27 - 4 - read-write - - - - - PMUP_CHANNEL_CFG - configure the code of valid pump channel code - 0x2C - 0x20 - - - PUMP_CHANNEL_CODE4 - configure cmd4 code - 7 - 5 - read-write - - - PUMP_CHANNEL_CODE3 - configure cmd3 code - 12 - 5 - read-write - - - PUMP_CHANNEL_CODE2 - configure cmd2 code - 17 - 5 - read-write - - - PUMP_CHANNEL_CODE1 - configure cmd1 code - 22 - 5 - read-write - - - PUMP_CHANNEL_CODE0 - configure cmd0 code - 27 - 5 - read-write - - - - - CLK_CFG - configure pvt clk - 0x30 - 0x20 - - - PUMP_CLK_DIV_NUM - needs field desc - 0 - 8 - read-write - - - MONITOR_CLK_PVT_EN - needs field desc - 8 - 1 - read-write - - - CLK_SEL - select pvt clk - 31 - 1 - read-write - - - - - DBIAS_CHANNEL_SEL0 - needs desc - 0x34 - 0x20 - 0x81020400 - - - DBIAS_CHANNEL3_SEL - needs field desc - 4 - 7 - read-write - - - DBIAS_CHANNEL2_SEL - needs field desc - 11 - 7 - read-write - - - DBIAS_CHANNEL1_SEL - needs field desc - 18 - 7 - read-write - - - DBIAS_CHANNEL0_SEL - needs field desc - 25 - 7 - read-write - - - - - DBIAS_CHANNEL_SEL1 - needs desc - 0x38 - 0x20 - 0x80000000 - - - DBIAS_CHANNEL4_SEL - needs field desc - 25 - 7 - read-write - - - - - DBIAS_CHANNEL0_SEL - needs desc - 0x3C - 0x20 - - - DBIAS_CHANNEL0_CFG - needs field desc - 0 - 17 - read-write - - - - - DBIAS_CHANNEL1_SEL - needs desc - 0x40 - 0x20 - - - DBIAS_CHANNEL1_CFG - needs field desc - 0 - 17 - read-write - - - - - DBIAS_CHANNEL2_SEL - needs desc - 0x44 - 0x20 - - - DBIAS_CHANNEL2_CFG - needs field desc - 0 - 17 - read-write - - - - - DBIAS_CHANNEL3_SEL - needs desc - 0x48 - 0x20 - - - DBIAS_CHANNEL3_CFG - needs field desc - 0 - 17 - read-write - - - - - DBIAS_CHANNEL4_SEL - needs desc - 0x4C - 0x20 - - - DBIAS_CHANNEL4_CFG - needs field desc - 0 - 17 - read-write - - - - - DBIAS_CMD0 - needs desc - 0x50 - 0x20 - - - DBIAS_CMD0 - needs field desc - 0 - 17 - read-write - - - - - DBIAS_CMD1 - needs desc - 0x54 - 0x20 - - - DBIAS_CMD1 - needs field desc - 0 - 17 - read-write - - - - - DBIAS_CMD2 - needs desc - 0x58 - 0x20 - - - DBIAS_CMD2 - needs field desc - 0 - 17 - read-write - - - - - DBIAS_CMD3 - needs desc - 0x5C - 0x20 - - - DBIAS_CMD3 - needs field desc - 0 - 17 - read-write - - - - - DBIAS_CMD4 - needs desc - 0x60 - 0x20 - - - DBIAS_CMD4 - needs field desc - 0 - 17 - read-write - - - - - DBIAS_TIMER - needs desc - 0x64 - 0x20 - 0x7FFF8000 - - - TIMER_TARGET - needs field desc - 15 - 16 - read-write - - - TIMER_EN - needs field desc - 31 - 1 - read-write - - - - - COMB_PD_SITE0_UNIT0_VT0_CONF1 - needs desc - 0x68 - 0x20 - 0x00000050 - - - MONITOR_EN_VT0_PD_SITE0_UNIT0 - needs field desc - 0 - 1 - read-write - - - TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT0 - needs field desc - 1 - 1 - write-only - - - DELAY_LIMIT_VT0_PD_SITE0_UNIT0 - needs field desc - 2 - 8 - read-write - - - DELAY_NUM_O_VT0_PD_SITE0_UNIT0 - needs field desc - 23 - 8 - read-only - - - TIMING_ERR_VT0_PD_SITE0_UNIT0 - needs field desc - 31 - 1 - read-only - - - - - COMB_PD_SITE0_UNIT1_VT0_CONF1 - needs desc - 0x6C - 0x20 - 0x00000050 - - - MONITOR_EN_VT0_PD_SITE0_UNIT1 - needs field desc - 0 - 1 - read-write - - - TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT1 - needs field desc - 1 - 1 - write-only - - - DELAY_LIMIT_VT0_PD_SITE0_UNIT1 - needs field desc - 2 - 8 - read-write - - - DELAY_NUM_O_VT0_PD_SITE0_UNIT1 - needs field desc - 23 - 8 - read-only - - - TIMING_ERR_VT0_PD_SITE0_UNIT1 - needs field desc - 31 - 1 - read-only - - - - - COMB_PD_SITE0_UNIT2_VT0_CONF1 - needs desc - 0x70 - 0x20 - 0x00000050 - - - MONITOR_EN_VT0_PD_SITE0_UNIT2 - needs field desc - 0 - 1 - read-write - - - TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT2 - needs field desc - 1 - 1 - write-only - - - DELAY_LIMIT_VT0_PD_SITE0_UNIT2 - needs field desc - 2 - 8 - read-write - - - DELAY_NUM_O_VT0_PD_SITE0_UNIT2 - needs field desc - 23 - 8 - read-only - - - TIMING_ERR_VT0_PD_SITE0_UNIT2 - needs field desc - 31 - 1 - read-only - - - - - COMB_PD_SITE0_UNIT3_VT0_CONF1 - needs desc - 0x74 - 0x20 - 0x00000050 - - - MONITOR_EN_VT0_PD_SITE0_UNIT3 - needs field desc - 0 - 1 - read-write - - - TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT3 - needs field desc - 1 - 1 - write-only - - - DELAY_LIMIT_VT0_PD_SITE0_UNIT3 - needs field desc - 2 - 8 - read-write - - - DELAY_NUM_O_VT0_PD_SITE0_UNIT3 - needs field desc - 23 - 8 - read-only - - - TIMING_ERR_VT0_PD_SITE0_UNIT3 - needs field desc - 31 - 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15 - 1 - read-only - - - TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT3 - needs field desc - 16 - 16 - read-only - - - - - COMB_PD_SITE2_UNIT0_VT2_CONF2 - needs desc - 0x1A8 - 0x20 - - - MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0 - needs field desc - 0 - 2 - read-write - - - DELAY_OVF_VT2_PD_SITE2_UNIT0 - needs field desc - 15 - 1 - read-only - - - TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT0 - needs field desc - 16 - 16 - read-only - - - - - COMB_PD_SITE2_UNIT1_VT2_CONF2 - needs desc - 0x1AC - 0x20 - - - MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT1 - needs field desc - 0 - 2 - read-write - - - DELAY_OVF_VT2_PD_SITE2_UNIT1 - needs field desc - 15 - 1 - read-only - - - TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT1 - needs field desc - 16 - 16 - read-only - - - - - COMB_PD_SITE2_UNIT2_VT2_CONF2 - needs desc - 0x1B0 - 0x20 - - - MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT2 - needs field desc - 0 - 2 - read-write - - - DELAY_OVF_VT2_PD_SITE2_UNIT2 - needs field desc - 15 - 1 - read-only - - - TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT2 - needs field desc - 16 - 16 - read-only - - - - - COMB_PD_SITE2_UNIT3_VT2_CONF2 - needs desc - 0x1B4 - 0x20 - - - MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT3 - needs field desc - 0 - 2 - read-write - - - DELAY_OVF_VT2_PD_SITE2_UNIT3 - needs field desc - 15 - 1 - read-only - - - TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT3 - needs field desc - 16 - 16 - read-only - - - - - COMB_PD_SITE3_UNIT0_VT0_CONF2 - needs desc - 0x1B8 - 0x20 - - - MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT0 - needs field desc - 0 - 2 - read-write - - - DELAY_OVF_VT0_PD_SITE3_UNIT0 - needs field desc - 15 - 1 - read-only - - - TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT0 - needs field desc - 16 - 16 - read-only - - - - - COMB_PD_SITE3_UNIT1_VT0_CONF2 - needs desc - 0x1BC - 0x20 - - - MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT1 - needs field desc - 0 - 2 - read-write - - - DELAY_OVF_VT0_PD_SITE3_UNIT1 - needs field desc - 15 - 1 - read-only - - - TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT1 - needs field desc - 16 - 16 - read-only - - - - - COMB_PD_SITE3_UNIT2_VT0_CONF2 - needs desc - 0x1C0 - 0x20 - - - MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT2 - needs field desc - 0 - 2 - read-write - - - DELAY_OVF_VT0_PD_SITE3_UNIT2 - needs field desc - 15 - 1 - read-only - - - TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT2 - needs field desc - 16 - 16 - read-only - - - - - COMB_PD_SITE3_UNIT3_VT0_CONF2 - needs desc - 0x1C4 - 0x20 - - - MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT3 - needs field desc - 0 - 2 - read-write - - - DELAY_OVF_VT0_PD_SITE3_UNIT3 - needs field desc - 15 - 1 - read-only - - - TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT3 - needs field desc - 16 - 16 - read-only - - - - - COMB_PD_SITE3_UNIT0_VT1_CONF2 - needs desc - 0x1C8 - 0x20 - - - MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT0 - needs field desc - 0 - 2 - read-write - - - DELAY_OVF_VT1_PD_SITE3_UNIT0 - needs field desc - 15 - 1 - read-only - - - TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT0 - needs field desc - 16 - 16 - read-only - - - - - COMB_PD_SITE3_UNIT1_VT1_CONF2 - needs desc - 0x1CC - 0x20 - - - MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT1 - needs field desc - 0 - 2 - read-write - - - DELAY_OVF_VT1_PD_SITE3_UNIT1 - needs field desc - 15 - 1 - read-only - - - TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT1 - needs field desc - 16 - 16 - read-only - - - - - COMB_PD_SITE3_UNIT2_VT1_CONF2 - needs desc - 0x1D0 - 0x20 - - - MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT2 - needs field desc - 0 - 2 - read-write - - - DELAY_OVF_VT1_PD_SITE3_UNIT2 - needs field desc - 15 - 1 - read-only - - - TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT2 - needs field desc - 16 - 16 - read-only - - - - - COMB_PD_SITE3_UNIT3_VT1_CONF2 - needs desc - 0x1D4 - 0x20 - - - MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT3 - needs field desc - 0 - 2 - read-write - - - DELAY_OVF_VT1_PD_SITE3_UNIT3 - needs field desc - 15 - 1 - read-only - - - TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT3 - needs field desc - 16 - 16 - read-only - - - - - COMB_PD_SITE3_UNIT0_VT2_CONF2 - needs desc - 0x1D8 - 0x20 - - - MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT0 - needs field desc - 0 - 2 - read-write - - - DELAY_OVF_VT2_PD_SITE3_UNIT0 - needs field desc - 15 - 1 - read-only - - - TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT0 - needs field desc - 16 - 16 - read-only - - - - - COMB_PD_SITE3_UNIT1_VT2_CONF2 - needs desc - 0x1DC - 0x20 - - - MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT1 - needs field desc - 0 - 2 - read-write - - - DELAY_OVF_VT2_PD_SITE3_UNIT1 - needs field desc - 15 - 1 - read-only - - - TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT1 - needs field desc - 16 - 16 - read-only - - - - - COMB_PD_SITE3_UNIT2_VT2_CONF2 - needs desc - 0x1E0 - 0x20 - - - MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT2 - needs field desc - 0 - 2 - read-write - - - DELAY_OVF_VT2_PD_SITE3_UNIT2 - needs field desc - 15 - 1 - read-only - - - TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT2 - needs field desc - 16 - 16 - read-only - - - - - COMB_PD_SITE3_UNIT3_VT2_CONF2 - needs desc - 0x1E4 - 0x20 - - - MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT3 - needs field desc - 0 - 2 - read-write - - - DELAY_OVF_VT2_PD_SITE3_UNIT3 - needs field desc - 15 - 1 - read-only - - - TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT3 - needs field desc - 16 - 16 - read-only - - - - - VALUE_UPDATE - needs field desc - 0x1E8 - 0x20 - - - VALUE_UPDATE - needs field desc - 0 - 1 - write-only - - - BYPASS - needs field desc - 1 - 1 - read-write - - - - - DATE - version register - 0xFFC - 0x20 - 0x02112130 - - - DATE - version register - 0 - 32 - read-write - - - - - - - RMT - Remote Control - RMT - 0x500D4000 - - 0x0 - 0xD0 - registers - - - RMT - 43 - - - - 4 - 0x4 - TX_CH%sDATA - The read and write data register for CHANNEL%s by apb fifo access. - 0x0 - 0x20 - - - CHDATA - Read and write data for channel %s via APB FIFO. - 0 - 32 - read-only - - - - - 4 - 0x4 - RX_CH%sDATA - The read and write data register for CHANNEL$n by apb fifo access. - 0x10 - 0x20 - - - CHDATA - Read and write data for channel 0 via APB FIFO. - 0 - 32 - read-only - - - - - 4 - 0x4 - TX_CH%sCONF0 - Channel %s configure register 0 - 0x20 - 0x20 - 0x00710200 - - - TX_START_CH0 - Set this bit to start sending data on CHANNEL%s. - 0 - 1 - write-only - - - MEM_RD_RST_CH0 - Set this bit to reset read ram address for CHANNEL%s by accessing transmitter. - 1 - 1 - write-only - - - APB_MEM_RST_CH0 - Set this bit to reset W/R ram address for CHANNEL%s by accessing apb fifo. - 2 - 1 - write-only - - - TX_CONTI_MODE_CH0 - Set this bit to restart transmission from the first data to the last data in CHANNEL%s. - 3 - 1 - read-write - - - MEM_TX_WRAP_EN_CH0 - This is the channel %s enable bit for wraparound mode: it will resume sending at the start when the data to be sent is more than its memory size. - 4 - 1 - read-write - - - IDLE_OUT_LV_CH0 - This bit configures the level of output signal in CHANNEL%s when the latter is in IDLE state. - 5 - 1 - read-write - - - IDLE_OUT_EN_CH0 - This is the output enable-control bit for CHANNEL%s in IDLE state. - 6 - 1 - read-write - - - TX_STOP_CH0 - Set this bit to stop the transmitter of CHANNEL%s sending data out. - 7 - 1 - read-write - - - DIV_CNT_CH0 - This register is used to configure the divider for clock of CHANNEL%s. - 8 - 8 - read-write - - - MEM_SIZE_CH0 - This register is used to configure the maximum size of memory allocated to CHANNEL%s. - 16 - 4 - read-write - - - CARRIER_EFF_EN_CH0 - 1: Add carrier modulation on the output signal only at the send data state for CHANNEL%s. 0: Add carrier modulation on the output signal at all state for CHANNEL%s. Only valid when RMT_CARRIER_EN_CH%s is 1. - 20 - 1 - read-write - - - CARRIER_EN_CH0 - This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out. - 21 - 1 - read-write - - - CARRIER_OUT_LV_CH0 - This bit is used to configure the position of carrier wave for CHANNEL%s.1'h0: add carrier wave on low level.1'h1: add carrier wave on high level. - 22 - 1 - read-write - - - AFIFO_RST_CH0 - Reserved - 23 - 1 - write-only - - - CONF_UPDATE_CH0 - synchronization bit for CHANNEL%s - 24 - 1 - write-only - - - - - 4 - 0x8 - RX_CH%sCONF0 - Channel %s configure register 0 - 0x30 - 0x20 - 0x317FFF02 - - - DIV_CNT_CH4 - This register is used to configure the divider for clock of CHANNEL%s. - 0 - 8 - read-write - - - IDLE_THRES_CH4 - When no edge is detected on the input signal and continuous clock cycles is longer than this register value, received process is finished. - 8 - 15 - read-write - - - MEM_SIZE_CH4 - This register is used to configure the maximum size of memory allocated to CHANNEL%s. - 24 - 4 - read-write - - - CARRIER_EN_CH4 - This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out. - 28 - 1 - read-write - - - CARRIER_OUT_LV_CH4 - This bit is used to configure the position of carrier wave for CHANNEL%s.1'h0: add carrier wave on low level.1'h1: add carrier wave on high level. - 29 - 1 - read-write - - - - - 4 - 0x8 - RX_CH%sCONF1 - Channel %s configure register 1 - 0x34 - 0x20 - 0x000001E8 - - - RX_EN_CH4 - Set this bit to enable receiver to receive data on CHANNEL%s. - 0 - 1 - read-write - - - MEM_WR_RST_CH4 - Set this bit to reset write ram address for CHANNEL%s by accessing receiver. - 1 - 1 - write-only - - - APB_MEM_RST_CH4 - Set this bit to reset W/R ram address for CHANNEL%s by accessing apb fifo. - 2 - 1 - write-only - - - MEM_OWNER_CH4 - This register marks the ownership of CHANNEL%s's ram block.1'h1: Receiver is using the ram. 1'h0: APB bus is using the ram. - 3 - 1 - read-write - - - RX_FILTER_EN_CH4 - This is the receive filter's enable bit for CHANNEL%s. - 4 - 1 - read-write - - - RX_FILTER_THRES_CH4 - Ignores the input pulse when its width is smaller than this register value in APB clock periods (in receive mode). - 5 - 8 - read-write - - - MEM_RX_WRAP_EN_CH4 - This is the channel %s enable bit for wraparound mode: it will resume receiving at the start when the data to be received is more than its memory size. - 13 - 1 - read-write - - - AFIFO_RST_CH4 - Reserved - 14 - 1 - write-only - - - CONF_UPDATE_CH4 - synchronization bit for CHANNEL%s - 15 - 1 - write-only - - - - - 4 - 0x4 - TX_CH%sSTATUS - Channel %s status register - 0x50 - 0x20 - - - MEM_RADDR_EX_CH0 - This register records the memory address offset when transmitter of CHANNEL%s is using the RAM. - 0 - 10 - read-only - - - APB_MEM_WADDR_CH0 - This register records the memory address offset when writes RAM over APB bus. - 11 - 10 - read-only - - - STATE_CH0 - This register records the FSM status of CHANNEL%s. - 22 - 3 - read-only - - - MEM_EMPTY_CH0 - This status bit will be set when the data to be set is more than memory size and the wraparound mode is disabled. - 25 - 1 - read-only - - - APB_MEM_WR_ERR_CH0 - This status bit will be set if the offset address out of memory size when writes via APB bus. - 26 - 1 - read-only - - - - - 4 - 0x4 - RX_CH%sSTATUS - Channel %s status register - 0x60 - 0x20 - 0x000600C0 - - - MEM_WADDR_EX_CH4 - This register records the memory address offset when receiver of CHANNEL%s is using the RAM. - 0 - 10 - read-only - - - APB_MEM_RADDR_CH4 - This register records the memory address offset when reads RAM over APB bus. - 11 - 10 - read-only - - - STATE_CH4 - This register records the FSM status of CHANNEL%s. - 22 - 3 - read-only - - - MEM_OWNER_ERR_CH4 - This status bit will be set when the ownership of memory block is wrong. - 25 - 1 - read-only - - - MEM_FULL_CH4 - This status bit will be set if the receiver receives more data than the memory size. - 26 - 1 - read-only - - - APB_MEM_RD_ERR_CH4 - This status bit will be set if the offset address out of memory size when reads via APB bus. - 27 - 1 - read-only - - - - - INT_RAW - Raw interrupt status - 0x70 - 0x20 - - - CH0_TX_END_INT_RAW - The interrupt raw bit for CHANNEL0. Triggered when transmission done. - 0 - 1 - read-write - - - CH1_TX_END_INT_RAW - The interrupt raw bit for CHANNEL1. Triggered when transmission done. - 1 - 1 - read-write - - - CH2_TX_END_INT_RAW - The interrupt raw bit for CHANNEL2. Triggered when transmission done. - 2 - 1 - read-write - - - CH3_TX_END_INT_RAW - The interrupt raw bit for CHANNEL3. Triggered when transmission done. - 3 - 1 - read-write - - - TX_CH0_ERR_INT_RAW - The interrupt raw bit for CHANNEL0. Triggered when error occurs. - 4 - 1 - read-write - - - TX_CH1_ERR_INT_RAW - The interrupt raw bit for CHANNEL1. Triggered when error occurs. - 5 - 1 - read-write - - - TX_CH2_ERR_INT_RAW - The interrupt raw bit for CHANNEL2. Triggered when error occurs. - 6 - 1 - read-write - - - TX_CH3_ERR_INT_RAW - The interrupt raw bit for CHANNEL3. Triggered when error occurs. - 7 - 1 - read-write - - - CH0_TX_THR_EVENT_INT_RAW - The interrupt raw bit for CHANNEL0. Triggered when transmitter sent more data than configured value. - 8 - 1 - read-write - - - CH1_TX_THR_EVENT_INT_RAW - The interrupt raw bit for CHANNEL1. Triggered when transmitter sent more data than configured value. - 9 - 1 - read-write - - - CH2_TX_THR_EVENT_INT_RAW - The interrupt raw bit for CHANNEL2. Triggered when transmitter sent more data than configured value. - 10 - 1 - read-write - - - CH3_TX_THR_EVENT_INT_RAW - The interrupt raw bit for CHANNEL3. Triggered when transmitter sent more data than configured value. - 11 - 1 - read-write - - - CH0_TX_LOOP_INT_RAW - The interrupt raw bit for CHANNEL0. Triggered when the loop count reaches the configured threshold value. - 12 - 1 - read-write - - - CH1_TX_LOOP_INT_RAW - The interrupt raw bit for CHANNEL1. Triggered when the loop count reaches the configured threshold value. - 13 - 1 - read-write - - - CH2_TX_LOOP_INT_RAW - The interrupt raw bit for CHANNEL2. Triggered when the loop count reaches the configured threshold value. - 14 - 1 - read-write - - - CH3_TX_LOOP_INT_RAW - The interrupt raw bit for CHANNEL3. Triggered when the loop count reaches the configured threshold value. - 15 - 1 - read-write - - - CH4_RX_END_INT_RAW - The interrupt raw bit for CHANNEL4. Triggered when reception done. - 16 - 1 - read-write - - - CH5_RX_END_INT_RAW - The interrupt raw bit for CHANNEL5. Triggered when reception done. - 17 - 1 - read-write - - - CH6_RX_END_INT_RAW - The interrupt raw bit for CHANNEL6. Triggered when reception done. - 18 - 1 - read-write - - - CH7_RX_END_INT_RAW - The interrupt raw bit for CHANNEL7. Triggered when reception done. - 19 - 1 - read-write - - - RX_CH4_ERR_INT_RAW - The interrupt raw bit for CHANNEL4. Triggered when error occurs. - 20 - 1 - read-write - - - RX_CH5_ERR_INT_RAW - The interrupt raw bit for CHANNEL5. Triggered when error occurs. - 21 - 1 - read-write - - - RX_CH6_ERR_INT_RAW - The interrupt raw bit for CHANNEL6. Triggered when error occurs. - 22 - 1 - read-write - - - RX_CH7_ERR_INT_RAW - The interrupt raw bit for CHANNEL7. Triggered when error occurs. - 23 - 1 - read-write - - - CH4_RX_THR_EVENT_INT_RAW - The interrupt raw bit for CHANNEL4. Triggered when receiver receive more data than configured value. - 24 - 1 - read-write - - - CH5_RX_THR_EVENT_INT_RAW - The interrupt raw bit for CHANNEL5. Triggered when receiver receive more data than configured value. - 25 - 1 - read-write - - - CH6_RX_THR_EVENT_INT_RAW - The interrupt raw bit for CHANNEL6. Triggered when receiver receive more data than configured value. - 26 - 1 - read-write - - - CH7_RX_THR_EVENT_INT_RAW - The interrupt raw bit for CHANNEL7. Triggered when receiver receive more data than configured value. - 27 - 1 - read-write - - - TX_CH3_DMA_ACCESS_FAIL_INT_RAW - The interrupt raw bit for CHANNEL3. Triggered when dma accessing CHANNEL3 fails. - 28 - 1 - read-write - - - RX_CH7_DMA_ACCESS_FAIL_INT_RAW - The interrupt raw bit for CHANNEL7. Triggered when dma accessing CHANNEL7 fails. - 29 - 1 - read-write - - - - - INT_ST - Masked interrupt status - 0x74 - 0x20 - - - CH0_TX_END_INT_ST - The masked interrupt status bit for CH0_TX_END_INT. - 0 - 1 - read-only - - - CH1_TX_END_INT_ST - The masked interrupt status bit for CH1_TX_END_INT. - 1 - 1 - read-only - - - CH2_TX_END_INT_ST - The masked interrupt status bit for CH2_TX_END_INT. - 2 - 1 - read-only - - - CH3_TX_END_INT_ST - The masked interrupt status bit for CH3_TX_END_INT. - 3 - 1 - read-only - - - TX_CH0_ERR_INT_ST - The masked interrupt status bit for CH0_ERR_INT. - 4 - 1 - read-only - - - TX_CH1_ERR_INT_ST - The masked interrupt status bit for CH1_ERR_INT. - 5 - 1 - read-only - - - TX_CH2_ERR_INT_ST - The masked interrupt status bit for CH2_ERR_INT. - 6 - 1 - read-only - - - TX_CH3_ERR_INT_ST - The masked interrupt status bit for CH3_ERR_INT. - 7 - 1 - read-only - - - CH0_TX_THR_EVENT_INT_ST - The masked interrupt status bit for CH0_TX_THR_EVENT_INT. - 8 - 1 - read-only - - - CH1_TX_THR_EVENT_INT_ST - The masked interrupt status bit for CH1_TX_THR_EVENT_INT. - 9 - 1 - read-only - - - CH2_TX_THR_EVENT_INT_ST - The masked interrupt status bit for CH2_TX_THR_EVENT_INT. - 10 - 1 - read-only - - - CH3_TX_THR_EVENT_INT_ST - The masked interrupt status bit for CH3_TX_THR_EVENT_INT. - 11 - 1 - read-only - - - CH0_TX_LOOP_INT_ST - The masked interrupt status bit for CH0_TX_LOOP_INT. - 12 - 1 - read-only - - - CH1_TX_LOOP_INT_ST - The masked interrupt status bit for CH1_TX_LOOP_INT. - 13 - 1 - read-only - - - CH2_TX_LOOP_INT_ST - The masked interrupt status bit for CH2_TX_LOOP_INT. - 14 - 1 - read-only - - - CH3_TX_LOOP_INT_ST - The masked interrupt status bit for CH3_TX_LOOP_INT. - 15 - 1 - read-only - - - CH4_RX_END_INT_ST - The masked interrupt status bit for CH4_RX_END_INT. - 16 - 1 - read-only - - - CH5_RX_END_INT_ST - The masked interrupt status bit for CH5_RX_END_INT. - 17 - 1 - read-only - - - CH6_RX_END_INT_ST - The masked interrupt status bit for CH6_RX_END_INT. - 18 - 1 - read-only - - - CH7_RX_END_INT_ST - The masked interrupt status bit for CH7_RX_END_INT. - 19 - 1 - read-only - - - RX_CH4_ERR_INT_ST - The masked interrupt status bit for CH4_ERR_INT. - 20 - 1 - read-only - - - RX_CH5_ERR_INT_ST - The masked interrupt status bit for CH5_ERR_INT. - 21 - 1 - read-only - - - RX_CH6_ERR_INT_ST - The masked interrupt status bit for CH6_ERR_INT. - 22 - 1 - read-only - - - RX_CH7_ERR_INT_ST - The masked interrupt status bit for CH7_ERR_INT. - 23 - 1 - read-only - - - CH4_RX_THR_EVENT_INT_ST - The masked interrupt status bit for CH4_RX_THR_EVENT_INT. - 24 - 1 - read-only - - - CH5_RX_THR_EVENT_INT_ST - The masked interrupt status bit for CH5_RX_THR_EVENT_INT. - 25 - 1 - read-only - - - CH6_RX_THR_EVENT_INT_ST - The masked interrupt status bit for CH6_RX_THR_EVENT_INT. - 26 - 1 - read-only - - - CH7_RX_THR_EVENT_INT_ST - The masked interrupt status bit for CH7_RX_THR_EVENT_INT. - 27 - 1 - read-only - - - TX_CH3_DMA_ACCESS_FAIL_INT_ST - The masked interrupt status bit for CH3_DMA_ACCESS_FAIL_INT. - 28 - 1 - read-only - - - RX_CH7_DMA_ACCESS_FAIL_INT_ST - The masked interrupt status bit for CH7_DMA_ACCESS_FAIL_INT. - 29 - 1 - read-only - - - - - INT_ENA - Interrupt enable bits - 0x78 - 0x20 - - - CH0_TX_END_INT_ENA - The interrupt enable bit for CH0_TX_END_INT. - 0 - 1 - read-write - - - CH1_TX_END_INT_ENA - The interrupt enable bit for CH1_TX_END_INT. - 1 - 1 - read-write - - - CH2_TX_END_INT_ENA - The interrupt enable bit for CH2_TX_END_INT. - 2 - 1 - read-write - - - CH3_TX_END_INT_ENA - The interrupt enable bit for CH3_TX_END_INT. - 3 - 1 - read-write - - - TX_CH0_ERR_INT_ENA - The interrupt enable bit for CH0_ERR_INT. - 4 - 1 - read-write - - - TX_CH1_ERR_INT_ENA - The interrupt enable bit for CH1_ERR_INT. - 5 - 1 - read-write - - - TX_CH2_ERR_INT_ENA - The interrupt enable bit for CH2_ERR_INT. - 6 - 1 - read-write - - - TX_CH3_ERR_INT_ENA - The interrupt enable bit for CH3_ERR_INT. - 7 - 1 - read-write - - - CH0_TX_THR_EVENT_INT_ENA - The interrupt enable bit for CH0_TX_THR_EVENT_INT. - 8 - 1 - read-write - - - CH1_TX_THR_EVENT_INT_ENA - The interrupt enable bit for CH1_TX_THR_EVENT_INT. - 9 - 1 - read-write - - - CH2_TX_THR_EVENT_INT_ENA - The interrupt enable bit for CH2_TX_THR_EVENT_INT. - 10 - 1 - read-write - - - CH3_TX_THR_EVENT_INT_ENA - The interrupt enable bit for CH3_TX_THR_EVENT_INT. - 11 - 1 - read-write - - - CH0_TX_LOOP_INT_ENA - The interrupt enable bit for CH0_TX_LOOP_INT. - 12 - 1 - read-write - - - CH1_TX_LOOP_INT_ENA - The interrupt enable bit for CH1_TX_LOOP_INT. - 13 - 1 - read-write - - - CH2_TX_LOOP_INT_ENA - The interrupt enable bit for CH2_TX_LOOP_INT. - 14 - 1 - read-write - - - CH3_TX_LOOP_INT_ENA - The interrupt enable bit for CH3_TX_LOOP_INT. - 15 - 1 - read-write - - - CH4_RX_END_INT_ENA - The interrupt enable bit for CH4_RX_END_INT. - 16 - 1 - read-write - - - CH5_RX_END_INT_ENA - The interrupt enable bit for CH5_RX_END_INT. - 17 - 1 - read-write - - - CH6_RX_END_INT_ENA - The interrupt enable bit for CH6_RX_END_INT. - 18 - 1 - read-write - - - CH7_RX_END_INT_ENA - The interrupt enable bit for CH7_RX_END_INT. - 19 - 1 - read-write - - - CH4_ERR_INT_ENA - The interrupt enable bit for CH4_ERR_INT. - 20 - 1 - read-write - - - CH5_ERR_INT_ENA - The interrupt enable bit for CH5_ERR_INT. - 21 - 1 - read-write - - - CH6_ERR_INT_ENA - The interrupt enable bit for CH6_ERR_INT. - 22 - 1 - read-write - - - CH7_ERR_INT_ENA - The interrupt enable bit for CH7_ERR_INT. - 23 - 1 - read-write - - - CH4_RX_THR_EVENT_INT_ENA - The interrupt enable bit for CH4_RX_THR_EVENT_INT. - 24 - 1 - read-write - - - CH5_RX_THR_EVENT_INT_ENA - The interrupt enable bit for CH5_RX_THR_EVENT_INT. - 25 - 1 - read-write - - - CH6_RX_THR_EVENT_INT_ENA - The interrupt enable bit for CH6_RX_THR_EVENT_INT. - 26 - 1 - read-write - - - CH7_RX_THR_EVENT_INT_ENA - The interrupt enable bit for CH7_RX_THR_EVENT_INT. - 27 - 1 - read-write - - - TX_CH3_DMA_ACCESS_FAIL_INT_ENA - The interrupt enable bit for CH3_DMA_ACCESS_FAIL_INT. - 28 - 1 - read-write - - - RX_CH7_DMA_ACCESS_FAIL_INT_ENA - The interrupt enable bit for CH7_DMA_ACCESS_FAIL_INT. - 29 - 1 - read-write - - - - - INT_CLR - Interrupt clear bits - 0x7C - 0x20 - - - CH0_TX_END_INT_CLR - Set this bit to clear theCH0_TX_END_INT interrupt. - 0 - 1 - write-only - - - CH1_TX_END_INT_CLR - Set this bit to clear theCH1_TX_END_INT interrupt. - 1 - 1 - write-only - - - CH2_TX_END_INT_CLR - Set this bit to clear theCH2_TX_END_INT interrupt. - 2 - 1 - write-only - - - CH3_TX_END_INT_CLR - Set this bit to clear theCH3_TX_END_INT interrupt. - 3 - 1 - write-only - - - TX_CH0_ERR_INT_CLR - Set this bit to clear theCH0_ERR_INT interrupt. - 4 - 1 - write-only - - - TX_CH1_ERR_INT_CLR - Set this bit to clear theCH1_ERR_INT interrupt. - 5 - 1 - write-only - - - TX_CH2_ERR_INT_CLR - Set this bit to clear theCH2_ERR_INT interrupt. - 6 - 1 - write-only - - - TX_CH3_ERR_INT_CLR - Set this bit to clear theCH3_ERR_INT interrupt. - 7 - 1 - write-only - - - CH0_TX_THR_EVENT_INT_CLR - Set this bit to clear theCH0_TX_THR_EVENT_INT interrupt. - 8 - 1 - write-only - - - CH1_TX_THR_EVENT_INT_CLR - Set this bit to clear theCH1_TX_THR_EVENT_INT interrupt. - 9 - 1 - write-only - - - CH2_TX_THR_EVENT_INT_CLR - Set this bit to clear theCH2_TX_THR_EVENT_INT interrupt. - 10 - 1 - write-only - - - CH3_TX_THR_EVENT_INT_CLR - Set this bit to clear theCH3_TX_THR_EVENT_INT interrupt. - 11 - 1 - write-only - - - CH0_TX_LOOP_INT_CLR - Set this bit to clear theCH0_TX_LOOP_INT interrupt. - 12 - 1 - write-only - - - CH1_TX_LOOP_INT_CLR - Set this bit to clear theCH1_TX_LOOP_INT interrupt. - 13 - 1 - write-only - - - CH2_TX_LOOP_INT_CLR - Set this bit to clear theCH2_TX_LOOP_INT interrupt. - 14 - 1 - write-only - - - CH3_TX_LOOP_INT_CLR - Set this bit to clear theCH3_TX_LOOP_INT interrupt. - 15 - 1 - write-only - - - CH4_RX_END_INT_CLR - Set this bit to clear theCH4_RX_END_INT interrupt. - 16 - 1 - write-only - - - CH5_RX_END_INT_CLR - Set this bit to clear theCH5_RX_END_INT interrupt. - 17 - 1 - write-only - - - CH6_RX_END_INT_CLR - Set this bit to clear theCH6_RX_END_INT interrupt. - 18 - 1 - write-only - - - CH7_RX_END_INT_CLR - Set this bit to clear theCH7_RX_END_INT interrupt. - 19 - 1 - write-only - - - RX_CH4_ERR_INT_CLR - Set this bit to clear theCH4_ERR_INT interrupt. - 20 - 1 - write-only - - - RX_CH5_ERR_INT_CLR - Set this bit to clear theCH5_ERR_INT interrupt. - 21 - 1 - write-only - - - RX_CH6_ERR_INT_CLR - Set this bit to clear theCH6_ERR_INT interrupt. - 22 - 1 - write-only - - - RX_CH7_ERR_INT_CLR - Set this bit to clear theCH7_ERR_INT interrupt. - 23 - 1 - write-only - - - CH4_RX_THR_EVENT_INT_CLR - Set this bit to clear theCH4_RX_THR_EVENT_INT interrupt. - 24 - 1 - write-only - - - CH5_RX_THR_EVENT_INT_CLR - Set this bit to clear theCH5_RX_THR_EVENT_INT interrupt. - 25 - 1 - write-only - - - CH6_RX_THR_EVENT_INT_CLR - Set this bit to clear theCH6_RX_THR_EVENT_INT interrupt. - 26 - 1 - write-only - - - CH7_RX_THR_EVENT_INT_CLR - Set this bit to clear theCH7_RX_THR_EVENT_INT interrupt. - 27 - 1 - write-only - - - TX_CH3_DMA_ACCESS_FAIL_INT_CLR - Set this bit to clear the CH3_DMA_ACCESS_FAIL_INT interrupt. - 28 - 1 - write-only - - - RX_CH7_DMA_ACCESS_FAIL_INT_CLR - Set this bit to clear the CH7_DMA_ACCESS_FAIL_INT interrupt. - 29 - 1 - write-only - - - - - 4 - 0x4 - CH%sCARRIER_DUTY - Channel %s duty cycle configuration register - 0x80 - 0x20 - 0x00400040 - - - CARRIER_LOW_CH - This register is used to configure carrier wave 's low level clock period for CHANNEL%s. - 0 - 16 - read-write - - - CARRIER_HIGH_CH - This register is used to configure carrier wave 's high level clock period for CHANNEL%s. - 16 - 16 - read-write - - - - - 4 - 0x4 - CH%s_RX_CARRIER_RM - Channel %s carrier remove register - 0x90 - 0x20 - - - CARRIER_LOW_THRES_CH - The low level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_LOW_THRES_CH%s + 1) for channel %s. - 0 - 16 - read-write - - - CARRIER_HIGH_THRES_CH - The high level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_HIGH_THRES_CH%s + 1) for channel %s. - 16 - 16 - read-write - - - - - 4 - 0x4 - CH%s_TX_LIM - Channel %s Tx event configuration register - 0xA0 - 0x20 - 0x00000080 - - - TX_LIM_CH - This register is used to configure the maximum entries that CHANNEL%s can send out. - 0 - 9 - read-write - - - TX_LOOP_NUM_CH - This register is used to configure the maximum loop count when tx_conti_mode is valid. - 9 - 10 - read-write - - - TX_LOOP_CNT_EN_CH - This register is the enabled bit for loop count. - 19 - 1 - read-write - - - LOOP_COUNT_RESET_CH - This register is used to reset the loop count when tx_conti_mode is valid. - 20 - 1 - write-only - - - LOOP_STOP_EN_CH - This bit is used to enable the loop send stop function after the loop counter counts to loop number for CHANNEL%s. - 21 - 1 - read-write - - - - - 4 - 0x4 - CH%s_RX_LIM - Channel %s Rx event configuration register - 0xB0 - 0x20 - 0x00000080 - - - RX_LIM_CH4 - This register is used to configure the maximum entries that CHANNEL%s can receive. - 0 - 9 - read-write - - - - - SYS_CONF - RMT apb configuration register - 0xC0 - 0x20 - 0x05000010 - - - APB_FIFO_MASK - 1'h1: access memory directly. 1'h0: access memory by FIFO. - 0 - 1 - read-write - - - MEM_CLK_FORCE_ON - Set this bit to enable the clock for RMT memory. - 1 - 1 - read-write - - - MEM_FORCE_PD - Set this bit to power down RMT memory. - 2 - 1 - read-write - - - MEM_FORCE_PU - 1: Disable RMT memory light sleep power down function. 0: Power down RMT memory when RMT is in light sleep mode. - 3 - 1 - read-write - - - SCLK_DIV_NUM - the integral part of the fractional divisor - 4 - 8 - read-write - - - SCLK_DIV_A - the numerator of the fractional part of the fractional divisor - 12 - 6 - read-write - - - SCLK_DIV_B - the denominator of the fractional part of the fractional divisor - 18 - 6 - read-write - - - SCLK_SEL - choose the clock source of rmt_sclk. 1:CLK_80Mhz.2:CLK_8MHz.3:XTAL - 24 - 2 - read-write - - - SCLK_ACTIVE - rmt_sclk switch - 26 - 1 - read-write - - - CLK_EN - RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0: Power down the drive clock of registers - 31 - 1 - read-write - - - - - TX_SIM - RMT TX synchronous register - 0xC4 - 0x20 - - - CH0 - Set this bit to enable CHANNEL0 to start sending data synchronously with other enabled channels. - 0 - 1 - read-write - - - CH1 - Set this bit to enable CHANNEL1 to start sending data synchronously with other enabled channels. - 1 - 1 - read-write - - - CH2 - Set this bit to enable CHANNEL2 to start sending data synchronously with other enabled channels. - 2 - 1 - read-write - - - CH3 - Set this bit to enable CHANNEL3 to start sending data synchronously with other enabled channels. - 3 - 1 - read-write - - - EN - This register is used to enable multiple of channels to start sending data synchronously. - 4 - 1 - read-write - - - - - REF_CNT_RST - RMT clock divider reset register - 0xC8 - 0x20 - - - TX_REF_CNT_RST_CH0 - This register is used to reset the clock divider of CHANNEL0. - 0 - 1 - write-only - - - TX_REF_CNT_RST_CH1 - This register is used to reset the clock divider of CHANNEL1. - 1 - 1 - write-only - - - TX_REF_CNT_RST_CH2 - This register is used to reset the clock divider of CHANNEL2. - 2 - 1 - write-only - - - TX_REF_CNT_RST_CH3 - This register is used to reset the clock divider of CHANNEL3. - 3 - 1 - write-only - - - RX_REF_CNT_RST_CH4 - This register is used to reset the clock divider of CHANNEL4. - 4 - 1 - write-only - - - RX_REF_CNT_RST_CH5 - This register is used to reset the clock divider of CHANNEL5. - 5 - 1 - write-only - - - RX_REF_CNT_RST_CH6 - This register is used to reset the clock divider of CHANNEL6. - 6 - 1 - write-only - - - RX_REF_CNT_RST_CH7 - This register is used to reset the clock divider of CHANNEL7. - 7 - 1 - write-only - - - - - DATE - RMT version register - 0xCC - 0x20 - 0x02201111 - - - DATE - This is the version register. - 0 - 28 - read-write - - - - - - - RSA - RSA (Rivest Shamir Adleman) Accelerator - RSA - 0x50092000 - - 0x0 - 0x74 - registers - - - RSA - 68 - - - - 4 - 0x4 - M_MEM[%s] - Represents M - 0x0 - 0x20 - - - 4 - 0x4 - Z_MEM[%s] - Represents Z - 0x200 - 0x20 - - - 4 - 0x4 - Y_MEM[%s] - Represents Y - 0x400 - 0x20 - - - 4 - 0x4 - X_MEM[%s] - Represents X - 0x600 - 0x20 - - - M_PRIME - Represents M’ - 0x800 - 0x20 - - - M_PRIME - Represents M’ - 0 - 32 - read-write - - - - - MODE - Configures RSA length - 0x804 - 0x20 - - - MODE - Configures the RSA length. - 0 - 7 - read-write - - - - - QUERY_CLEAN - RSA clean register - 0x808 - 0x20 - - - QUERY_CLEAN - Represents whether or not the RSA memory completes initialization. - -0: Not complete - -1: Completed - 0 - 1 - read-only - - - - - SET_START_MODEXP - Starts modular exponentiation - 0x80C - 0x20 - - - SET_START_MODEXP - Configure whether or not to start the modular exponentiation. - -0: No effect - -1: Start - 0 - 1 - write-only - - - - - SET_START_MODMULT - Starts modular multiplication - 0x810 - 0x20 - - - SET_START_MODMULT - Configure whether or not to start the modular multiplication. - -0: No effect - -1: Start - 0 - 1 - write-only - - - - - SET_START_MULT - Starts multiplication - 0x814 - 0x20 - - - SET_START_MULT - Configure whether or not to start the multiplication. - -0: No effect - -1: Start - 0 - 1 - write-only - - - - - QUERY_IDLE - Represents the RSA status - 0x818 - 0x20 - - - QUERY_IDLE - Represents the RSA status. - -0: Busy - -1: Idle - 0 - 1 - read-only - - - - - INT_CLR - Clears RSA interrupt - 0x81C - 0x20 - - - CLEAR_INTERRUPT - Write 1 to clear the RSA interrupt. - 0 - 1 - write-only - - - - - CONSTANT_TIME - Configures the constant_time option - 0x820 - 0x20 - 0x00000001 - - - CONSTANT_TIME - Configures the constant_time option. - -0: Acceleration - -1: No acceleration (default) - 0 - 1 - read-write - - - - - SEARCH_ENABLE - Configures the search option - 0x824 - 0x20 - - - SEARCH_ENABLE - Configure the search option. - -0: No acceleration (default) - -1: Acceleration - -This option should be used together with RSA_SEARCH_POS. - 0 - 1 - read-write - - - - - SEARCH_POS - Configures the search position - 0x828 - 0x20 - - - SEARCH_POS - Configures the starting address to start search. This field should be used together with RSA_SEARCH_ENABLE. The field is only valid when RSA_SEARCH_ENABLE is high. - 0 - 12 - read-write - - - - - INT_ENA - Enables the RSA interrupt - 0x82C - 0x20 - - - INT_ENA - Write 1 to enable the RSA interrupt. - 0 - 1 - read-write - - - - - DATE - Version control register - 0x830 - 0x20 - 0x20200618 - - - DATE - Version control register. - 0 - 30 - read-write - - - - - - - LP_ADC - Low-power Analog to Digital Converter - RTCADC - 0x50127000 - - 0x0 - 0x80 - registers - - - LP_ADC - 9 - - - - READER1_CTRL - Control the read operation of ADC1. - 0x0 - 0x20 - 0x20040002 - - - SAR1_CLK_DIV - Clock divider. - 0 - 8 - read-write - - - SAR1_CLK_GATED - N/A - 18 - 1 - read-write - - - SAR1_SAMPLE_NUM - N/A - 19 - 8 - read-write - - - SAR1_DATA_INV - Invert SAR ADC1 data. - 28 - 1 - read-write - - - SAR1_INT_EN - Enable saradc1 to send out interrupt. - 29 - 1 - read-write - - - SAR1_EN_PAD_FORCE_ENABLE - Force enable adc en_pad to analog circuit 2'b11: force enable . - 30 - 2 - read-write - - - - - READER1_STATUS - N/A - 0x4 - 0x20 - 0x20000000 - - - SAR1_READER_STATUS - N/A - 0 - 32 - read-only - - - - - MEAS1_CTRL1 - N/A - 0x8 - 0x20 - - - FORCE_XPD_AMP - N/A - 24 - 2 - read-write - - - AMP_RST_FB_FORCE - N/A - 26 - 2 - read-write - - - AMP_SHORT_REF_FORCE - N/A - 28 - 2 - read-write - - - AMP_SHORT_REF_GND_FORCE - N/A - 30 - 2 - read-write - - - - - MEAS1_CTRL2 - ADC1 configuration registers. - 0xC - 0x20 - - - MEAS1_DATA_SAR - SAR ADC1 data. - 0 - 16 - read-only - - - MEAS1_DONE_SAR - SAR ADC1 conversion done indication. - 16 - 1 - read-only - - - MEAS1_START_SAR - SAR ADC1 controller (in RTC) starts conversion. - 17 - 1 - read-write - - - MEAS1_START_FORCE - 1: SAR ADC1 controller (in RTC) is started by SW. - 18 - 1 - read-write - - - SAR1_EN_PAD - SAR ADC1 pad enable bitmap. - 19 - 12 - read-write - - - SAR1_EN_PAD_FORCE - 1: SAR ADC1 pad enable bitmap is controlled by SW. - 31 - 1 - read-write - - - - - MEAS1_MUX - SAR ADC1 MUX register. - 0x10 - 0x20 - - - SAR1_DIG_FORCE - 1: SAR ADC1 controlled by DIG ADC1 CTRL. - 31 - 1 - read-write - - - - - ATTEN1 - ADC1 attenuation registers. - 0x14 - 0x20 - 0xFFFFFFFF - - - SAR1_ATTEN - 2-bit attenuation for each pad. - 0 - 32 - read-write - - - - - AMP_CTRL1 - N/A - 0x18 - 0x20 - 0x000A000A - - - SAR_AMP_WAIT1 - N/A - 0 - 16 - read-write - - - SAR_AMP_WAIT2 - N/A - 16 - 16 - read-write - - - - - AMP_CTRL2 - N/A - 0x1C - 0x20 - 0x000A0000 - - - SAR1_DAC_XPD_FSM_IDLE - N/A - 0 - 1 - read-write - - - XPD_SAR_AMP_FSM_IDLE - N/A - 1 - 1 - read-write - - - AMP_RST_FB_FSM_IDLE - N/A - 2 - 1 - read-write - - - AMP_SHORT_REF_FSM_IDLE - N/A - 3 - 1 - read-write - - - AMP_SHORT_REF_GND_FSM_IDLE - N/A - 4 - 1 - read-write - - - XPD_SAR_FSM_IDLE - N/A - 5 - 1 - read-write - - - SAR_RSTB_FSM_IDLE - N/A - 6 - 1 - read-write - - - SAR_AMP_WAIT3 - N/A - 16 - 16 - read-write - - - - - AMP_CTRL3 - N/A - 0x20 - 0x20 - 0x007338F3 - - - SAR1_DAC_XPD_FSM - N/A - 0 - 4 - read-write - - - XPD_SAR_AMP_FSM - N/A - 4 - 4 - read-write - - - AMP_RST_FB_FSM - N/A - 8 - 4 - read-write - - - AMP_SHORT_REF_FSM - N/A - 12 - 4 - read-write - - - AMP_SHORT_REF_GND_FSM - N/A - 16 - 4 - read-write - - - XPD_SAR_FSM - N/A - 20 - 4 - read-write - - - SAR_RSTB_FSM - N/A - 24 - 4 - read-write - - - - - READER2_CTRL - Control the read operation of ADC2. - 0x24 - 0x20 - 0x40050002 - - - SAR2_CLK_DIV - Clock divider. - 0 - 8 - read-write - - - SAR2_WAIT_ARB_CYCLE - Wait arbit stable after sar_done. - 16 - 2 - read-write - - - SAR2_CLK_GATED - N/A - 18 - 1 - read-write - - - SAR2_SAMPLE_NUM - N/A - 19 - 8 - read-write - - - SAR2_EN_PAD_FORCE_ENABLE - Force enable adc en_pad to analog circuit 2'b11: force enable . - 27 - 2 - read-write - - - SAR2_DATA_INV - Invert SAR ADC2 data. - 29 - 1 - read-write - - - SAR2_INT_EN - Enable saradc2 to send out interrupt. - 30 - 1 - read-write - - - - - READER2_STATUS - N/A - 0x28 - 0x20 - - - SAR2_READER_STATUS - N/A - 0 - 32 - read-only - - - - - MEAS2_CTRL1 - ADC2 configuration registers. - 0x2C - 0x20 - 0x07020200 - - - SAR2_CNTL_STATE - saradc2_cntl_fsm. - 0 - 3 - read-only - - - SAR2_PWDET_CAL_EN - RTC control pwdet enable. - 3 - 1 - read-write - - - SAR2_PKDET_CAL_EN - RTC control pkdet enable. - 4 - 1 - read-write - - - SAR2_EN_TEST - SAR2_EN_TEST. - 5 - 1 - read-write - - - SAR2_RSTB_FORCE - N/A - 6 - 2 - read-write - - - SAR2_STANDBY_WAIT - N/A - 8 - 8 - read-write - - - SAR2_RSTB_WAIT - N/A - 16 - 8 - read-write - - - SAR2_XPD_WAIT - N/A - 24 - 8 - read-write - - - - - MEAS2_CTRL2 - ADC2 configuration registers. - 0x30 - 0x20 - - - MEAS2_DATA_SAR - SAR ADC2 data. - 0 - 16 - read-only - - - MEAS2_DONE_SAR - SAR ADC2 conversion done indication. - 16 - 1 - read-only - - - MEAS2_START_SAR - SAR ADC2 controller (in RTC) starts conversion. - 17 - 1 - read-write - - - MEAS2_START_FORCE - 1: SAR ADC2 controller (in RTC) is started by SW. - 18 - 1 - read-write - - - SAR2_EN_PAD - SAR ADC2 pad enable bitmap. - 19 - 12 - read-write - - - SAR2_EN_PAD_FORCE - 1: SAR ADC2 pad enable bitmap is controlled by SW. - 31 - 1 - read-write - - - - - MEAS2_MUX - SAR ADC2 MUX register. - 0x34 - 0x20 - - - SAR2_PWDET_CCT - SAR2_PWDET_CCT. - 28 - 3 - read-write - - - SAR2_RTC_FORCE - In sleep, force to use rtc to control ADC. - 31 - 1 - read-write - - - - - ATTEN2 - ADC1 attenuation registers. - 0x38 - 0x20 - 0xFFFFFFFF - - - SAR2_ATTEN - 2-bit attenuation for each pad. - 0 - 32 - read-write - - - - - FORCE_WPD_SAR - In sleep, force to use rtc to control ADC - 0x3C - 0x20 - - - FORCE_XPD_SAR1 - 2'b11:software control, force on. 2'b10:software control, force off. 2'b0x:hardware control. - 0 - 2 - read-write - - - FORCE_XPD_SAR2 - 2'b11:software control, force on. 2'b10:software control, force off. 2'b0x:hardware control. - 2 - 2 - read-write - - - - - MEAS_STATUS - N/A - 0x40 - 0x20 - - - SARADC_MEAS_STATUS - N/A - 0 - 8 - read-only - - - - - REG_CLKEN - N/A - 0x44 - 0x20 - - - CLK_EN - N/A - 0 - 1 - read-write - - - - - COCPU_INT_RAW - Interrupt raw registers. - 0x48 - 0x20 - - - COCPU_SARADC1_INT_RAW - ADC1 Conversion is done, int raw. - 0 - 1 - read-write - - - COCPU_SARADC2_INT_RAW - ADC2 Conversion is done, int raw. - 1 - 1 - read-write - - - COCPU_SARADC1_ERROR_INT_RAW - An errro occurs from ADC1, int raw. - 2 - 1 - read-write - - - COCPU_SARADC2_ERROR_INT_RAW - An errro occurs from ADC2, int raw. - 3 - 1 - read-write - - - COCPU_SARADC1_WAKE_INT_RAW - A wakeup event is triggered from ADC1, int raw. - 4 - 1 - read-write - - - COCPU_SARADC2_WAKE_INT_RAW - A wakeup event is triggered from ADC2, int raw. - 5 - 1 - read-write - - - - - INT_ENA - Interrupt enable registers. - 0x4C - 0x20 - - - COCPU_SARADC1_INT_ENA - ADC1 Conversion is done, int enable. - 0 - 1 - read-write - - - COCPU_SARADC2_INT_ENA - ADC2 Conversion is done, int enable. - 1 - 1 - read-write - - - COCPU_SARADC1_ERROR_INT_ENA - An errro occurs from ADC1, int enable. - 2 - 1 - read-write - - - COCPU_SARADC2_ERROR_INT_ENA - An errro occurs from ADC2, int enable. - 3 - 1 - read-write - - - COCPU_SARADC1_WAKE_INT_ENA - A wakeup event is triggered from ADC1, int enable. - 4 - 1 - read-write - - - COCPU_SARADC2_WAKE_INT_ENA - A wakeup event is triggered from ADC2, int enable. - 5 - 1 - read-write - - - - - INT_ST - Interrupt status registers. - 0x50 - 0x20 - - - COCPU_SARADC1_INT_ST - ADC1 Conversion is done, int status. - 0 - 1 - read-only - - - COCPU_SARADC2_INT_ST - ADC2 Conversion is done, int status. - 1 - 1 - read-only - - - COCPU_SARADC1_ERROR_INT_ST - An errro occurs from ADC1, int status. - 2 - 1 - read-only - - - COCPU_SARADC2_ERROR_INT_ST - An errro occurs from ADC2, int status. - 3 - 1 - read-only - - - COCPU_SARADC1_WAKE_INT_ST - A wakeup event is triggered from ADC1, int status. - 4 - 1 - read-only - - - COCPU_SARADC2_WAKE_INT_ST - A wakeup event is triggered from ADC2, int status. - 5 - 1 - read-only - - - - - INT_CLR - Interrupt clear registers. - 0x54 - 0x20 - - - COCPU_SARADC1_INT_CLR - ADC1 Conversion is done, int clear. - 0 - 1 - write-only - - - COCPU_SARADC2_INT_CLR - ADC2 Conversion is done, int clear. - 1 - 1 - write-only - - - COCPU_SARADC1_ERROR_INT_CLR - An errro occurs from ADC1, int clear. - 2 - 1 - write-only - - - COCPU_SARADC2_ERROR_INT_CLR - An errro occurs from ADC2, int clear. - 3 - 1 - write-only - - - COCPU_SARADC1_WAKE_INT_CLR - A wakeup event is triggered from ADC1, int clear. - 4 - 1 - write-only - - - COCPU_SARADC2_WAKE_INT_CLR - A wakeup event is triggered from ADC2, int clear. - 5 - 1 - write-only - - - - - INT_ENA_W1TS - Interrupt enable assert registers. - 0x58 - 0x20 - - - COCPU_SARADC1_INT_ENA_W1TS - ADC1 Conversion is done, write 1 to assert int enable. - 0 - 1 - write-only - - - COCPU_SARADC2_INT_ENA_W1TS - ADC2 Conversion is done, write 1 to assert int enable. - 1 - 1 - write-only - - - COCPU_SARADC1_ERROR_INT_ENA_W1TS - An errro occurs from ADC1, write 1 to assert int enable. - 2 - 1 - write-only - - - COCPU_SARADC2_ERROR_INT_ENA_W1TS - An errro occurs from ADC2, write 1 to assert int enable. - 3 - 1 - write-only - - - COCPU_SARADC1_WAKE_INT_ENA_W1TS - A wakeup event is triggered from ADC1, write 1 to assert int enable. - 4 - 1 - write-only - - - COCPU_SARADC2_WAKE_INT_ENA_W1TS - A wakeup event is triggered from ADC2, write 1 to assert int enable. - 5 - 1 - write-only - - - - - INT_ENA_W1TC - Interrupt enable deassert registers. - 0x5C - 0x20 - - - COCPU_SARADC1_INT_ENA_W1TC - ADC1 Conversion is done, write 1 to deassert int enable. - 0 - 1 - write-only - - - COCPU_SARADC2_INT_ENA_W1TC - ADC2 Conversion is done, write 1 to deassert int enable. - 1 - 1 - write-only - - - COCPU_SARADC1_ERROR_INT_ENA_W1TC - An errro occurs from ADC1, write 1 to deassert int enable. - 2 - 1 - write-only - - - COCPU_SARADC2_ERROR_INT_ENA_W1TC - An errro occurs from ADC2, write 1 to deassert int enable. - 3 - 1 - write-only - - - COCPU_SARADC1_WAKE_INT_ENA_W1TC - A wakeup event is triggered from ADC1, write 1 to deassert int enable. - 4 - 1 - write-only - - - COCPU_SARADC2_WAKE_INT_ENA_W1TC - A wakeup event is triggered from ADC2, write 1 to deassert int enable. - 5 - 1 - write-only - - - - - WAKEUP1 - ADC1 wakeup configuration registers. - 0x60 - 0x20 - 0x03FFC000 - - - SAR1_WAKEUP_TH_LOW - Lower threshold. - 0 - 12 - read-write - - - SAR1_WAKEUP_TH_HIGH - Upper threshold. - 14 - 12 - read-write - - - SAR1_WAKEUP_OVER_UPPER_TH - Indicates that this wakeup event arose from exceeding upper threshold. - 29 - 1 - read-only - - - SAR1_WAKEUP_EN - Wakeup function enable. - 30 - 1 - read-write - - - SAR1_WAKEUP_MODE - 0:absolute value comparison mode. 1: relative value comparison mode. - 31 - 1 - read-write - - - - - WAKEUP2 - ADC2 wakeup configuration registers. - 0x64 - 0x20 - 0x03FFC000 - - - SAR2_WAKEUP_TH_LOW - Lower threshold. - 0 - 12 - read-write - - - SAR2_WAKEUP_TH_HIGH - Upper threshold. - 14 - 12 - read-write - - - SAR2_WAKEUP_OVER_UPPER_TH - Indicates that this wakeup event arose from exceeding upper threshold. - 29 - 1 - read-only - - - SAR2_WAKEUP_EN - Wakeup function enable. - 30 - 1 - read-write - - - SAR2_WAKEUP_MODE - 0:absolute value comparison mode. 1: relative value comparison mode. - 31 - 1 - read-write - - - - - WAKEUP_SEL - Wakeup source select register. - 0x68 - 0x20 - - - SAR_WAKEUP_SEL - 0: ADC1. 1: ADC2. - 0 - 1 - read-write - - - - - SAR1_HW_WAKEUP - Hardware automatic sampling registers for wakeup function. - 0x6C - 0x20 - 0x000000C8 - - - ADC1_HW_READ_EN_I - Enable hardware automatic sampling. - 0 - 1 - read-write - - - ADC1_HW_READ_RATE_I - Hardware automatic sampling rate. - 1 - 16 - read-write - - - - - SAR2_HW_WAKEUP - Hardware automatic sampling registers for wakeup function. - 0x70 - 0x20 - 0x000000C8 - - - ADC2_HW_READ_EN_I - Enable hardware automatic sampling. - 0 - 1 - read-write - - - ADC2_HW_READ_RATE_I - Hardware automatic sampling rate. - 1 - 16 - read-write - - - - - RND_ECO_LOW - N/A - 0x74 - 0x20 - - - RND_ECO_LOW - N/A - 0 - 32 - read-write - - - - - RND_ECO_HIGH - N/A - 0x78 - 0x20 - 0xFFFFFFFF - - - RND_ECO_HIGH - N/A - 0 - 32 - read-write - - - - - RND_ECO_CS - N/A - 0x7C - 0x20 - - - RND_ECO_EN - N/A - 0 - 1 - read-write - - - RND_ECO_RESULT - N/A - 1 - 1 - read-only - - - - - - - LP_TIMER - Low-power Timer - RTC_TIMER - 0x50112000 - - 0x0 - 0x4C - registers - - - LP_TIMER0 - 2 - - - LP_TIMER1 - 3 - - - - TAR0_LOW - need_des - 0x0 - 0x20 - - - MAIN_TIMER_TAR_LOW0 - need_des - 0 - 32 - read-write - - - - - TAR0_HIGH - need_des - 0x4 - 0x20 - - - MAIN_TIMER_TAR_HIGH0 - need_des - 0 - 16 - read-write - - - MAIN_TIMER_TAR_EN0 - need_des - 31 - 1 - write-only - - - - - TAR1_LOW - need_des - 0x8 - 0x20 - - - MAIN_TIMER_TAR_LOW1 - need_des - 0 - 32 - read-write - - - - - TAR1_HIGH - need_des - 0xC - 0x20 - - - MAIN_TIMER_TAR_HIGH1 - need_des - 0 - 16 - read-write - - - MAIN_TIMER_TAR_EN1 - need_des - 31 - 1 - write-only - - - - - UPDATE - need_des - 0x10 - 0x20 - - - MAIN_TIMER_UPDATE - need_des - 28 - 1 - write-only - - - MAIN_TIMER_XTAL_OFF - need_des - 29 - 1 - read-write - - - MAIN_TIMER_SYS_STALL - need_des - 30 - 1 - read-write - - - MAIN_TIMER_SYS_RST - need_des - 31 - 1 - read-write - - - - - MAIN_BUF0_LOW - need_des - 0x14 - 0x20 - - - MAIN_TIMER_BUF0_LOW - need_des - 0 - 32 - read-only - - - - - MAIN_BUF0_HIGH - need_des - 0x18 - 0x20 - - - MAIN_TIMER_BUF0_HIGH - need_des - 0 - 16 - read-only - - - - - MAIN_BUF1_LOW - need_des - 0x1C - 0x20 - - - MAIN_TIMER_BUF1_LOW - need_des - 0 - 32 - read-only - - - - - MAIN_BUF1_HIGH - need_des - 0x20 - 0x20 - - - MAIN_TIMER_BUF1_HIGH - need_des - 0 - 16 - read-only - - - - - MAIN_OVERFLOW - need_des - 0x24 - 0x20 - - - MAIN_TIMER_ALARM_LOAD - need_des - 31 - 1 - write-only - - - - - INT_RAW - need_des - 0x28 - 0x20 - - - OVERFLOW_RAW - need_des - 30 - 1 - read-write - - - SOC_WAKEUP_INT_RAW - need_des - 31 - 1 - read-write - - - - - INT_ST - need_des - 0x2C - 0x20 - - - OVERFLOW_ST - need_des - 30 - 1 - read-only - - - SOC_WAKEUP_INT_ST - need_des - 31 - 1 - read-only - - - - - INT_ENA - need_des - 0x30 - 0x20 - - - OVERFLOW_ENA - need_des - 30 - 1 - read-write - - - SOC_WAKEUP_INT_ENA - need_des - 31 - 1 - read-write - - - - - INT_CLR - need_des - 0x34 - 0x20 - - - OVERFLOW_CLR - need_des - 30 - 1 - write-only - - - SOC_WAKEUP_INT_CLR - need_des - 31 - 1 - write-only - - - - - LP_INT_RAW - need_des - 0x38 - 0x20 - - - MAIN_TIMER_OVERFLOW_LP_INT_RAW - need_des - 30 - 1 - read-write - - - MAIN_TIMER_LP_INT_RAW - need_des - 31 - 1 - read-write - - - - - LP_INT_ST - need_des - 0x3C - 0x20 - - - MAIN_TIMER_OVERFLOW_LP_INT_ST - need_des - 30 - 1 - read-only - - - MAIN_TIMER_LP_INT_ST - need_des - 31 - 1 - read-only - - - - - LP_INT_ENA - need_des - 0x40 - 0x20 - - - MAIN_TIMER_OVERFLOW_LP_INT_ENA - need_des - 30 - 1 - read-write - - - MAIN_TIMER_LP_INT_ENA - need_des - 31 - 1 - read-write - - - - - LP_INT_CLR - need_des - 0x44 - 0x20 - - - MAIN_TIMER_OVERFLOW_LP_INT_CLR - need_des - 30 - 1 - write-only - - - MAIN_TIMER_LP_INT_CLR - need_des - 31 - 1 - write-only - - - - - DATE - need_des - 0x3FC - 0x20 - 0x02111150 - - - DATE - need_des - 0 - 31 - read-write - - - CLK_EN - need_des - 31 - 1 - read-write - - - - - - - LP_TOUCH - LP_TOUCH Peripheral - RTC_TOUCH - 0x50128000 - - 0x0 - 0x64 - registers - - - LP_TOUCH - 14 - - - - INT_RAW - need_des - 0x0 - 0x20 - - - SCAN_DONE_INT_RAW - need_des - 0 - 1 - read-write - - - DONE_INT_RAW - need_des - 1 - 1 - read-write - - - ACTIVE_INT_RAW - need_des - 2 - 1 - read-write - - - INACTIVE_INT_RAW - need_des - 3 - 1 - read-write - - - TIMEOUT_INT_RAW - need_des - 4 - 1 - read-write - - - APPROACH_LOOP_DONE_INT_RAW - need_des - 5 - 1 - read-write - - - - - INT_ST - need_des - 0x4 - 0x20 - - - SCAN_DONE_INT_ST - need_des - 0 - 1 - read-only - - - DONE_INT_ST - need_des - 1 - 1 - read-only - - - ACTIVE_INT_ST - need_des - 2 - 1 - read-only - - - INACTIVE_INT_ST - need_des - 3 - 1 - read-only - - - TIMEOUT_INT_ST - need_des - 4 - 1 - read-only - - - APPROACH_LOOP_DONE_INT_ST - need_des - 5 - 1 - read-only - - - - - INT_ENA - need_des - 0x8 - 0x20 - - - SCAN_DONE_INT_ENA - need_des - 0 - 1 - read-write - - - DONE_INT_ENA - need_des - 1 - 1 - read-write - - - ACTIVE_INT_ENA - need_des - 2 - 1 - read-write - - - INACTIVE_INT_ENA - need_des - 3 - 1 - read-write - - - TIMEOUT_INT_ENA - need_des - 4 - 1 - read-write - - - APPROACH_LOOP_DONE_INT_ENA - need_des - 5 - 1 - read-write - - - - - INT_CLR - need_des - 0xC - 0x20 - - - SCAN_DONE_INT_CLR - need_des - 0 - 1 - write-only - - - DONE_INT_CLR - need_des - 1 - 1 - write-only - - - ACTIVE_INT_CLR - need_des - 2 - 1 - write-only - - - INACTIVE_INT_CLR - need_des - 3 - 1 - write-only - - - TIMEOUT_INT_CLR - need_des - 4 - 1 - write-only - - - APPROACH_LOOP_DONE_INT_CLR - need_des - 5 - 1 - write-only - - - - - CHN_STATUS - need_des - 0x10 - 0x20 - - - PAD_ACTIVE - need_des - 0 - 15 - read-only - - - MEAS_DONE - need_des - 15 - 1 - read-only - - - SCAN_CURR - need_des - 16 - 4 - read-only - - - - - STATUS_0 - need_des - 0x14 - 0x20 - - - PAD0_DATA - need_des - 0 - 16 - read-only - - - PAD0_DEBOUNCE_CNT - need_des - 16 - 3 - read-only - - - PAD0_NEG_NOISE_CNT - need_des - 19 - 4 - read-only - - - - - STATUS_1 - need_des - 0x18 - 0x20 - - - PAD1_DATA - need_des - 0 - 16 - read-only - - - PAD1_DEBOUNCE_CNT - need_des - 16 - 3 - read-only - - - PAD1_NEG_NOISE_CNT - need_des - 19 - 4 - read-only - - - - - STATUS_2 - need_des - 0x1C - 0x20 - - - PAD2_DATA - need_des - 0 - 16 - read-only - - - PAD2_DEBOUNCE_CNT - need_des - 16 - 3 - read-only - - - PAD2_NEG_NOISE_CNT - need_des - 19 - 4 - read-only - - - - - STATUS_3 - need_des - 0x20 - 0x20 - - - PAD3_DATA - need_des - 0 - 16 - read-only - - - PAD3_DEBOUNCE_CNT - need_des - 16 - 3 - read-only - - - PAD3_NEG_NOISE_CNT - need_des - 19 - 4 - read-only - - - - - STATUS_4 - need_des - 0x24 - 0x20 - - - PAD4_DATA - need_des - 0 - 16 - read-only - - - PAD4_DEBOUNCE_CNT - need_des - 16 - 3 - read-only - - - PAD4_NEG_NOISE_CNT - need_des - 19 - 4 - read-only - - - - - STATUS_5 - need_des - 0x28 - 0x20 - - - PAD5_DATA - need_des - 0 - 16 - read-only - - - PAD5_DEBOUNCE_CNT - need_des - 16 - 3 - read-only - - - PAD5_NEG_NOISE_CNT - need_des - 19 - 4 - read-only - - - - - STATUS_6 - need_des - 0x2C - 0x20 - - - PAD6_DATA - need_des - 0 - 16 - read-only - - - PAD6_DEBOUNCE_CNT - need_des - 16 - 3 - read-only - - - PAD6_NEG_NOISE_CNT - need_des - 19 - 4 - read-only - - - - - STATUS_7 - need_des - 0x30 - 0x20 - - - PAD7_DATA - need_des - 0 - 16 - read-only - - - PAD7_DEBOUNCE_CNT - need_des - 16 - 3 - read-only - - - PAD7_NEG_NOISE_CNT - need_des - 19 - 4 - read-only - - - - - STATUS_8 - need_des - 0x34 - 0x20 - - - PAD8_DATA - need_des - 0 - 16 - read-only - - - PAD8_DEBOUNCE_CNT - need_des - 16 - 3 - read-only - - - PAD8_NEG_NOISE_CNT - need_des - 19 - 4 - read-only - - - - - STATUS_9 - need_des - 0x38 - 0x20 - - - PAD9_DATA - need_des - 0 - 16 - read-only - - - PAD9_DEBOUNCE_CNT - need_des - 16 - 3 - read-only - - - PAD9_NEG_NOISE_CNT - need_des - 19 - 4 - read-only - - - - - STATUS_10 - need_des - 0x3C - 0x20 - - - PAD10_DATA - need_des - 0 - 16 - read-only - - - PAD10_DEBOUNCE_CNT - need_des - 16 - 3 - read-only - - - PAD10_NEG_NOISE_CNT - need_des - 19 - 4 - read-only - - - - - STATUS_11 - need_des - 0x40 - 0x20 - - - PAD11_DATA - need_des - 0 - 16 - read-only - - - PAD11_DEBOUNCE_CNT - need_des - 16 - 3 - read-only - - - PAD11_NEG_NOISE_CNT - need_des - 19 - 4 - read-only - - - - - STATUS_12 - need_des - 0x44 - 0x20 - - - PAD12_DATA - need_des - 0 - 16 - read-only - - - PAD12_DEBOUNCE_CNT - need_des - 16 - 3 - read-only - - - PAD12_NEG_NOISE_CNT - need_des - 19 - 4 - read-only - - - - - STATUS_13 - need_des - 0x48 - 0x20 - - - PAD13_DATA - need_des - 0 - 16 - read-only - - - PAD13_DEBOUNCE_CNT - need_des - 16 - 3 - read-only - - - PAD13_NEG_NOISE_CNT - need_des - 19 - 4 - read-only - - - - - STATUS_14 - need_des - 0x4C - 0x20 - - - PAD14_DATA - need_des - 0 - 16 - read-only - - - PAD14_DEBOUNCE_CNT - need_des - 16 - 3 - read-only - - - PAD14_NEG_NOISE_CNT - need_des - 19 - 4 - read-only - - - - - STATUS_15 - need_des - 0x50 - 0x20 - - - SLP_DATA - need_des - 0 - 16 - read-only - - - SLP_DEBOUNCE_CNT - need_des - 16 - 3 - read-only - - - SLP_NEG_NOISE_CNT - need_des - 19 - 4 - read-only - - - - - STATUS_16 - need_des - 0x54 - 0x20 - - - APPROACH_PAD2_CNT - need_des - 0 - 8 - read-only - - - APPROACH_PAD1_CNT - need_des - 8 - 8 - read-only - - - APPROACH_PAD0_CNT - need_des - 16 - 8 - read-only - - - SLP_APPROACH_CNT - need_des - 24 - 8 - read-only - - - - - STATUS_17 - need_des - 0x58 - 0x20 - - - DCAP_LPF - Reserved - 0 - 7 - read-only - - - DRES_LPF - need_des - 7 - 2 - read-only - - - DRV_LS - need_des - 9 - 4 - read-only - - - DRV_HS - need_des - 13 - 5 - read-only - - - DBIAS - need_des - 18 - 5 - read-only - - - RTC_FREQ_SCAN_CNT - need_des - 23 - 2 - read-only - - - - - CHN_TMP_STATUS - need_des - 0x5C - 0x20 - - - PAD_INACTIVE_STATUS - need_des - 0 - 15 - read-only - - - PAD_ACTIVE_STATUS - need_des - 15 - 15 - read-only - - - - - DATE - need_des - 0x100 - 0x20 - 0x00230314 - - - RTC_DATE - need_des - 0 - 28 - read-write - - - RTC_CLK_EN - need_des - 31 - 1 - read-write - - - - - - - LP_WDT - Low-power Watchdog Timer - RTC_WDT - 0x50116000 - - 0x0 - 0x38 - registers - - - LP_WDT - 1 - - - - CONFIG0 - need_des - 0x0 - 0x20 - 0x00013214 - - - WDT_CHIP_RESET_WIDTH - need_des - 0 - 8 - read-write - - - WDT_CHIP_RESET_EN - need_des - 8 - 1 - read-write - - - WDT_PAUSE_IN_SLP - need_des - 9 - 1 - read-write - - - WDT_APPCPU_RESET_EN - need_des - 10 - 1 - read-write - - - WDT_PROCPU_RESET_EN - need_des - 11 - 1 - read-write - - - WDT_FLASHBOOT_MOD_EN - need_des - 12 - 1 - read-write - - - WDT_SYS_RESET_LENGTH - need_des - 13 - 3 - read-write - - - WDT_CPU_RESET_LENGTH - need_des - 16 - 3 - read-write - - - WDT_STG3 - need_des - 19 - 3 - read-write - - - WDT_STG2 - need_des - 22 - 3 - read-write - - - WDT_STG1 - need_des - 25 - 3 - read-write - - - WDT_STG0 - need_des - 28 - 3 - read-write - - - WDT_EN - need_des - 31 - 1 - read-write - - - - - CONFIG1 - need_des - 0x4 - 0x20 - 0x00030D40 - - - WDT_STG0_HOLD - need_des - 0 - 32 - read-write - - - - - CONFIG2 - need_des - 0x8 - 0x20 - 0x00013880 - - - WDT_STG1_HOLD - need_des - 0 - 32 - read-write - - - - - CONFIG3 - need_des - 0xC - 0x20 - 0x00000FFF - - - WDT_STG2_HOLD - need_des - 0 - 32 - read-write - - - - - CONFIG4 - need_des - 0x10 - 0x20 - 0x00000FFF - - - WDT_STG3_HOLD - need_des - 0 - 32 - read-write - - - - - FEED - need_des - 0x14 - 0x20 - - - FEED - need_des - 31 - 1 - write-only - - - - - WPROTECT - need_des - 0x18 - 0x20 - - - WDT_WKEY - need_des - 0 - 32 - read-write - - - - - SWD_CONFIG - need_des - 0x1C - 0x20 - 0x12C00000 - - - SWD_RESET_FLAG - need_des - 0 - 1 - read-only - - - SWD_AUTO_FEED_EN - need_des - 18 - 1 - read-write - - - SWD_RST_FLAG_CLR - need_des - 19 - 1 - write-only - - - SWD_SIGNAL_WIDTH - need_des - 20 - 10 - read-write - - - SWD_DISABLE - need_des - 30 - 1 - read-write - - - SWD_FEED - need_des - 31 - 1 - write-only - - - - - SWD_WPROTECT - need_des - 0x20 - 0x20 - - - SWD_WKEY - need_des - 0 - 32 - read-write - - - - - INT_RAW - need_des - 0x24 - 0x20 - - - SUPER_WDT_INT_RAW - need_des - 30 - 1 - read-write - - - LP_WDT_INT_RAW - need_des - 31 - 1 - read-write - - - - - INT_ST - need_des - 0x28 - 0x20 - - - SUPER_WDT_INT_ST - need_des - 30 - 1 - read-only - - - LP_WDT_INT_ST - need_des - 31 - 1 - read-only - - - - - INT_ENA - need_des - 0x2C - 0x20 - - - SUPER_WDT_INT_ENA - need_des - 30 - 1 - read-write - - - LP_WDT_INT_ENA - need_des - 31 - 1 - read-write - - - - - INT_CLR - need_des - 0x30 - 0x20 - - - SUPER_WDT_INT_CLR - need_des - 30 - 1 - write-only - - - LP_WDT_INT_CLR - need_des - 31 - 1 - write-only - - - - - DATE - need_des - 0x3FC - 0x20 - 0x02112080 - - - LP_WDT_DATE - need_des - 0 - 31 - read-write - - - CLK_EN - need_des - 31 - 1 - read-write - - - - - - - SDHOST - SD/MMC Host Controller - SDHOST - 0x50083000 - - 0x0 - 0xB0 - registers - - - - CTRL - Control register - 0x0 - 0x20 - - - CONTROLLER_RESET - To reset controller, firmware should set this bit. This bit is auto-cleared after two AHB and two sdhost_cclk_in clock cycles. - 0 - 1 - read-write - - - FIFO_RESET - To reset FIFO, firmware should set bit to 1. This bit is auto-cleared after completion of reset operation. -Note: FIFO pointers will be out of reset after 2 cycles of system clocks in addition to synchronization delay (2 cycles of card clock), after the fifo_reset is cleared. - 1 - 1 - read-write - - - DMA_RESET - To reset DMA interface, firmware should set bit to 1. This bit is auto-cleared after two AHB clocks. - 2 - 1 - read-write - - - INT_ENABLE - Global interrupt enable/disable bit. 0: Disable; 1: Enable. - 4 - 1 - read-write - - - READ_WAIT - For sending read-wait to SDIO cards. - 6 - 1 - read-write - - - SEND_IRQ_RESPONSE - Bit automatically clears once response is sent. To wait for MMC card interrupts, host issues CMD40 and waits for interrupt response from MMC card(s). In the meantime, if host wants SD/MMC to exit waiting for interrupt state, it can set this bit, at which time SD/MMC command state-machine sends CMD40 response on bus and returns to idle state. - 7 - 1 - read-write - - - ABORT_READ_DATA - After a suspend-command is issued during a read-operation, software polls the card to find when the suspend-event occurred. Once the suspend-event has occurred, software sets the bit which will reset the data state machine that is waiting for the next block of data. This bit is automatically cleared once the data state machine is reset to idle. - 8 - 1 - read-write - - - SEND_CCSD - When set, SD/MMC sends CCSD to the CE-ATA device. Software sets this bit only if the current command is expecting CCS (that is, RW_BLK), and if interrupts are enabled for the CE-ATA device. Once the CCSD pattern is sent to the device, SD/MMC automatically clears the SDHOST_SEND_CCSD bit. It also sets the Command Done (CD) bit in the SDHOST_RINTSTS_REG register, and generates an interrupt for the host, in case the Command Done interrupt is not masked. -NOTE: Once the SDHOST_SEND_CCSD bit is set, it takes two card clock cycles to drive the CCSD on the CMD line. Due to this, within the boundary conditions the CCSD may be sent to the CE-ATA device, even if the device has signalled CCS. - 9 - 1 - read-write - - - SEND_AUTO_STOP_CCSD - Always Set SDHOST_SEND_AUTO_STOP_CCSD and SDHOST_SEND_CCSD bits together; SDHOST_SEND_AUTO_STOP_CCSD should not be set independently of send_ccsd. When set, SD/MMC automatically sends an internally-generated STOP command (CMD12) to the CE-ATA device. After sending this internally-generated STOP command, the Auto Command Done (ACD) bit in SDHOST_RINTSTS_REG is set and an interrupt is generated for the host, in case the ACD interrupt is not masked. After sending the Command Completion Signal Disable (CCSD), SD/MMC automatically clears the SDHOST_SEND_AUTO_STOP_CCSD bit. - 10 - 1 - read-write - - - CEATA_DEVICE_INTERRUPT_STATUS - Software should appropriately write to this bit after the power-on reset or any other reset to the CE-ATA device. After reset, the CE-ATA device's interrupt is usually disabled (nIEN = 1). If the host enables the CE-ATA device's interrupt, then software should set this bit. - 11 - 1 - read-write - - - - - CLKDIV - Clock divider configuration register - 0x8 - 0x20 - - - CLK_DIVIDER0 - Clock divider0 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on. - 0 - 8 - read-write - - - CLK_DIVIDER1 - Clock divider1 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on. - 8 - 8 - read-write - - - CLK_DIVIDER2 - Clock divider2 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on. - 16 - 8 - read-write - - - CLK_DIVIDER3 - Clock divider3 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on. - 24 - 8 - read-write - - - - - CLKSRC - Clock source selection register - 0xC - 0x20 - - - CLKSRC - Clock divider source for two SD cards is supported. Each card has two bits assigned to it. For example, bit[1:0] are assigned for card 0, bit[3:2] are assigned for card 1. Card 0 maps and internally routes clock divider[0:3] outputs to cclk_out[1:0] pins, depending on bit value. -00 : Clock divider 0; -01 : Clock divider 1; -10 : Clock divider 2; -11 : Clock divider 3. - 0 - 4 - read-write - - - - - CLKENA - Clock enable register - 0x10 - 0x20 - - - CCLK_ENABLE - Clock-enable control for two SD card clocks and one MMC card clock is supported. One bit per card. -0: Clock disabled; -1: Clock enabled. - 0 - 2 - read-write - - - LP_ENABLE - Disable clock when the card is in IDLE state. One bit per card. -0: clock disabled; -1: clock enabled. - 16 - 2 - read-write - - - - - TMOUT - Data and response timeout configuration register - 0x14 - 0x20 - 0xFFFFFF40 - - - RESPONSE_TIMEOUT - Response timeout value. Value is specified in terms of number of card output clocks, i.e., sdhost_cclk_out. - 0 - 8 - read-write - - - DATA_TIMEOUT - Value for card data read timeout. This value is also used for data starvation by host timeout. The timeout counter is started only after the card clock is stopped. This value is specified in number of card output clocks, i.e. sdhost_cclk_out of the selected card. -NOTE: The software timer should be used if the timeout value is in the order of 100 ms. In this case, read data timeout interrupt needs to be disabled. - 8 - 24 - read-write - - - - - CTYPE - Card bus width configuration register - 0x18 - 0x20 - - - CARD_WIDTH4 - One bit per card indicates if card is 1-bit or 4-bit mode. -0: 1-bit mode; -1: 4-bit mode. -Bit[1:0] correspond to card[1:0] respectively. - 0 - 2 - read-write - - - CARD_WIDTH8 - One bit per card indicates if card is in 8-bit mode. -0: Non 8-bit mode; -1: 8-bit mode. -Bit[17:16] correspond to card[1:0] respectively. - 16 - 2 - read-write - - - - - BLKSIZ - Card data block size configuration register - 0x1C - 0x20 - 0x00000200 - - - BLOCK_SIZE - Block size. - 0 - 16 - read-write - - - - - BYTCNT - Data transfer length configuration register - 0x20 - 0x20 - 0x00000200 - - - BYTE_COUNT - Number of bytes to be transferred, should be an integral multiple of Block Size for block transfers. For data transfers of undefined byte lengths, byte count should be set to 0. When byte count is set to 0, it is the responsibility of host to explicitly send stop/abort command to terminate data transfer. - 0 - 32 - read-write - - - - - INTMASK - SDIO interrupt mask register - 0x24 - 0x20 - - - INT_MASK - These bits used to mask unwanted interrupts. A value of 0 masks interrupt, and a value of 1 enables the interrupt. -Bit 15 (EBE): End-bit error/no CRC error; -Bit 14 (ACD): Auto command done; -Bit 13 (SBE/BCI): Rx Start Bit Error; -Bit 12 (HLE): Hardware locked write error; -Bit 11 (FRUN): FIFO underrun/overrun error; -Bit 10 (HTO): Data starvation-by-host timeout; -Bit 9 (DRTO): Data read timeout; -Bit 8 (RTO): Response timeout; -Bit 7 (DCRC): Data CRC error; -Bit 6 (RCRC): Response CRC error; -Bit 5 (RXDR): Receive FIFO data request; -Bit 4 (TXDR): Transmit FIFO data request; -Bit 3 (DTO): Data transfer over; -Bit 2 (CD): Command done; -Bit 1 (RE): Response error; -Bit 0 (CD): Card detect. - 0 - 16 - read-write - - - SDIO_INT_MASK - SDIO interrupt mask, one bit for each card. Bit[17:16] correspond to card[15:0] respectively. When masked, SDIO interrupt detection for that card is disabled. 0 masks an interrupt, and 1 enables an interrupt. - 16 - 2 - read-write - - - - - CMDARG - Command argument data register - 0x28 - 0x20 - - - CMDARG - Value indicates command argument to be passed to the card. - 0 - 32 - read-write - - - - - CMD - Command and boot configuration register - 0x2C - 0x20 - 0x20000000 - - - INDEX - Command index. - 0 - 6 - read-write - - - RESPONSE_EXPECT - 0: No response expected from card; 1: Response expected from card. - 6 - 1 - read-write - - - RESPONSE_LENGTH - 0: Short response expected from card; 1: Long response expected from card. - 7 - 1 - read-write - - - CHECK_RESPONSE_CRC - 0: Do not check; 1: Check response CRC. -Some of command responses do not return valid CRC bits. Software should disable CRC checks for those commands in order to disable CRC checking by controller. - 8 - 1 - read-write - - - DATA_EXPECTED - 0: No data transfer expected; 1: Data transfer expected. - 9 - 1 - read-write - - - READ_WRITE - 0: Read from card; 1: Write to card. -Don't care if no data is expected from card. - 10 - 1 - read-write - - - TRANSFER_MODE - 0: Block data transfer command; 1: Stream data transfer command. -Don't care if no data expected. - 11 - 1 - read-write - - - SEND_AUTO_STOP - 0: No stop command is sent at the end of data transfer; 1: Send stop command at the end of data transfer. - 12 - 1 - read-write - - - WAIT_PRVDATA_COMPLETE - 0: Send command at once, even if previous data transfer has not completed; 1: Wait for previous data transfer to complete before sending Command. -The SDHOST_WAIT_PRVDATA_COMPLETE] = 0 option is typically used to query status of card during data transfer or to stop current data transfer. SDHOST_CARD_NUMBERr should be same as in previous command. - 13 - 1 - read-write - - - STOP_ABORT_CMD - 0: Neither stop nor abort command can stop current data transfer. If abort is sent to function-number currently selected or not in data-transfer mode, then bit should be set to 0; 1: Stop or abort command intended to stop current data transfer in progress. -When open-ended or predefined data transfer is in progress, and host issues stop or abort command to stop data transfer, bit should be set so that command/data state-machines of CIU can return correctly to idle state. - 14 - 1 - read-write - - - SEND_INITIALIZATION - 0: Do not send initialization sequence (80 clocks of 1) before sending this command; 1: Send initialization sequence before sending this command. -After powered on, 80 clocks must be sent to card for initialization before sending any commands to card. Bit should be set while sending first command to card so that controller will initialize clocks before sending command to card. - 15 - 1 - read-write - - - CARD_NUMBER - Card number in use. Represents physical slot number of card being accessed. In SD-only mode, up to two cards are supported. - 16 - 5 - read-write - - - UPDATE_CLOCK_REGISTERS_ONLY - 0: Normal command sequence; 1: Do not send commands, just update clock register value into card clock domain. -Following register values are transferred into card clock domain: CLKDIV, CLRSRC, and CLKENA. -Changes card clocks (change frequency, truncate off or on, and set low-frequency mode). This is provided in order to change clock frequency or stop clock without having to send command to cards. During normal command sequence, when sdhost_update_clock_registers_only = 0, following control registers are transferred from BIU to CIU: CMD, CMDARG, TMOUT, CTYPE, BLKSIZ, and BYTCNT. CIU uses new register values for new command sequence to card(s). When bit is set, there are no Command Done interrupts because no command is sent to SD_MMC_CEATA cards. - 21 - 1 - read-write - - - READ_CEATA_DEVICE - Read access flag. -0: Host is not performing read access (RW_REG or RW_BLK)towards CE-ATA device; -1: Host is performing read access (RW_REG or RW_BLK) towards CE-ATA device. -Software should set this bit to indicate that CE-ATA device is being accessed for read transfer. This bit is used to disable read data timeout indication while performing CE-ATA read transfers. Maximum value of I/O transmission delay can be no less than 10 seconds. SD/MMC should not indicate read data timeout while waiting for data from CE-ATA device. - 22 - 1 - read-write - - - CCS_EXPECTED - Expected Command Completion Signal (CCS) configuration. -0: Interrupts are not enabled in CE-ATA device (nIEN = 1 in ATA control register), or command does not expect CCS from device; -1: Interrupts are enabled in CE-ATA device (nIEN = 0), and RW_BLK command expects command completion signal from CE-ATA device. -If the command expects Command Completion Signal (CCS) from the CE-ATA device, the software should set this control bit. SD/MMC sets Data Transfer Over (DTO) bit in RINTSTS register and generates interrupt to host if Data Transfer Over interrupt is not masked. - 23 - 1 - read-write - - - USE_HOLE - Use Hold Register. -0: CMD and DATA sent to card bypassing HOLD Register; -1: CMD and DATA sent to card through the HOLD Register. - 29 - 1 - read-write - - - START_CMD - Start command. Once command is served by the CIU, this bit is automatically cleared. When this bit is set, host should not attempt to write to any command registers. If a write is attempted, hardware lock error is set in raw interrupt register. Once command is sent and a response is received from SD_MMC_CEATA cards, Command Done bit is set in the raw interrupt Register. - 31 - 1 - read-write - - - - - RESP0 - Response data register - 0x30 - 0x20 - - - RESPONSE0 - Bit[31:0] of response. - 0 - 32 - read-only - - - - - RESP1 - Long response data register - 0x34 - 0x20 - - - RESPONSE1 - Bit[63:32] of long response. - 0 - 32 - read-only - - - - - RESP2 - Long response data register - 0x38 - 0x20 - - - RESPONSE2 - Bit[95:64] of long response. - 0 - 32 - read-only - - - - - RESP3 - Long response data register - 0x3C - 0x20 - - - RESPONSE3 - Bit[127:96] of long response. - 0 - 32 - read-only - - - - - MINTSTS - Masked interrupt status register - 0x40 - 0x20 - - - INT_STATUS_MSK - Interrupt enabled only if corresponding bit in interrupt mask register is set. -Bit 15 (EBE): End-bit error/no CRC error; -Bit 14 (ACD): Auto command done; -Bit 13 (SBE/BCI): RX Start Bit Error; -Bit 12 (HLE): Hardware locked write error; -Bit 11 (FRUN): FIFO underrun/overrun error; -Bit 10 (HTO): Data starvation by host timeout (HTO); -Bit 9 (DTRO): Data read timeout; -Bit 8 (RTO): Response timeout; -Bit 7 (DCRC): Data CRC error; -Bit 6 (RCRC): Response CRC error; -Bit 5 (RXDR): Receive FIFO data request; -Bit 4 (TXDR): Transmit FIFO data request; -Bit 3 (DTO): Data transfer over; -Bit 2 (CD): Command done; -Bit 1 (RE): Response error; -Bit 0 (CD): Card detect. - 0 - 16 - read-only - - - SDIO_INTERRUPT_MSK - Interrupt from SDIO card, one bit for each card. Bit[17:16] correspond to card1 and card0, respectively. SDIO interrupt for card is enabled only if corresponding sdhost_sdio_int_mask bit is set in Interrupt mask register (Setting mask bit enables interrupt). - 16 - 2 - read-only - - - - - RINTSTS - Raw interrupt status register - 0x44 - 0x20 - - - INT_STATUS_RAW - Setting a bit clears the corresponding interrupt and writing 0 has no effect. Bits are logged regardless of interrupt mask status. -Bit 15 (EBE): End-bit error/no CRC error; -Bit 14 (ACD): Auto command done; -Bit 13 (SBE/BCI): RX Start Bit Error; -Bit 12 (HLE): Hardware locked write error; -Bit 11 (FRUN): FIFO underrun/overrun error; -Bit 10 (HTO): Data starvation by host timeout (HTO); -Bit 9 (DTRO): Data read timeout; -Bit 8 (RTO): Response timeout; -Bit 7 (DCRC): Data CRC error; -Bit 6 (RCRC): Response CRC error; -Bit 5 (RXDR): Receive FIFO data request; -Bit 4 (TXDR): Transmit FIFO data request; -Bit 3 (DTO): Data transfer over; -Bit 2 (CD): Command done; -Bit 1 (RE): Response error; -Bit 0 (CD): Card detect. - 0 - 16 - read-write - - - SDIO_INTERRUPT_RAW - Interrupt from SDIO card, one bit for each card. Bit[17:16] correspond to card1 and card0, respectively. Setting a bit clears the corresponding interrupt bit and writing 0 has no effect. -0: No SDIO interrupt from card; -1: SDIO interrupt from card. - 16 - 2 - read-write - - - - - STATUS - SD/MMC status register - 0x48 - 0x20 - 0x00000716 - - - FIFO_RX_WATERMARK - FIFO reached Receive watermark level, not qualified with data transfer. - 0 - 1 - read-only - - - FIFO_TX_WATERMARK - FIFO reached Transmit watermark level, not qualified with data transfer. - 1 - 1 - read-only - - - FIFO_EMPTY - FIFO is empty status. - 2 - 1 - read-only - - - FIFO_FULL - FIFO is full status. - 3 - 1 - read-only - - - COMMAND_FSM_STATES - Command FSM states. -0: Idle; -1: Send init sequence; -2: Send cmd start bit; -3: Send cmd tx bit; -4: Send cmd index + arg; -5: Send cmd crc7; -6: Send cmd end bit; -7: Receive resp start bit; -8: Receive resp IRQ response; -9: Receive resp tx bit; -10: Receive resp cmd idx; -11: Receive resp data; -12: Receive resp crc7; -13: Receive resp end bit; -14: Cmd path wait NCC; -15: Wait, cmd-to-response turnaround. - 4 - 4 - read-only - - - DATA_3_STATUS - Raw selected sdhost_card_data[3], checks whether card is present. -0: card not present; -1: card present. - 8 - 1 - read-only - - - DATA_BUSY - Inverted version of raw selected sdhost_card_data[0]. -0: Card data not busy; -1: Card data busy. - 9 - 1 - read-only - - - DATA_STATE_MC_BUSY - Data transmit or receive state-machine is busy. - 10 - 1 - read-only - - - RESPONSE_INDEX - Index of previous response, including any auto-stop sent by core. - 11 - 6 - read-only - - - FIFO_COUNT - FIFO count, number of filled locations in FIFO. - 17 - 13 - read-only - - - - - FIFOTH - FIFO configuration register - 0x4C - 0x20 - - - TX_WMARK - FIFO threshold watermark level when transmitting data to card. When FIFO data count is less than or equal to this number, DMA/FIFO request is raised. If Interrupt is enabled, then interrupt occurs. During end of packet, request or interrupt is generated, regardless of threshold programming.In non-DMA mode, when transmit FIFO threshold (TXDR) interrupt is enabled, then interrupt is generated instead of DMA request. During end of packet, on last interrupt, host is responsible for filling FIFO with only required remaining bytes (not before FIFO is full or after CIU completes data transfers, because FIFO may not be empty). In DMA mode, at end of packet, if last transfer is less than burst size, DMA controller does single cycles until required bytes are transferred. - 0 - 12 - read-write - - - RX_WMARK - FIFO threshold watermark level when receiving data to card.When FIFO data count reaches greater than this number , DMA/FIFO request is raised. During end of packet, request is generated regardless of threshold programming in order to complete any remaining data.In non-DMA mode, when receiver FIFO threshold (RXDR) interrupt is enabled, then interrupt is generated instead of DMA request.During end of packet, interrupt is not generated if threshold programming is larger than any remaining data. It is responsibility of host to read remaining bytes on seeing Data Transfer Done interrupt.In DMA mode, at end of packet, even if remaining bytes are less than threshold, DMA request does single transfers to flush out any remaining bytes before Data Transfer Done interrupt is set. - 16 - 11 - read-write - - - DMA_MULTIPLE_TRANSACTION_SIZE - Burst size of multiple transaction, should be programmed same as DMA controller multiple-transaction-size SDHOST_SRC/DEST_MSIZE. -000: 1-byte transfer; -001: 4-byte transfer; -010: 8-byte transfer; -011: 16-byte transfer; -100: 32-byte transfer; -101: 64-byte transfer; -110: 128-byte transfer; -111: 256-byte transfer. - 28 - 3 - read-write - - - - - CDETECT - Card detect register - 0x50 - 0x20 - - - CARD_DETECT_N - Value on sdhost_card_detect_n input ports (1 bit per card), read-only bits. 0 represents presence of card. Only NUM_CARDS number of bits are implemented. - 0 - 2 - read-only - - - - - WRTPRT - Card write protection (WP) status register - 0x54 - 0x20 - - - WRITE_PROTECT - Value on sdhost_card_write_prt input ports (1 bit per card). 1 represents write protection. Only NUM_CARDS number of bits are implemented. - 0 - 2 - read-only - - - - - TCBCNT - Transferred byte count register - 0x5C - 0x20 - - - TCBCNT - Number of bytes transferred by CIU unit to card. - 0 - 32 - read-only - - - - - TBBCNT - Transferred byte count register - 0x60 - 0x20 - - - TBBCNT - Number of bytes transferred between Host/DMA memory and BIU FIFO. - 0 - 32 - read-only - - - - - DEBNCE - Debounce filter time configuration register - 0x64 - 0x20 - - - DEBOUNCE_COUNT - Number of host clocks (clk) used by debounce filter logic. The typical debounce time is 5 \verb+~+ 25 ms to prevent the card instability when the card is inserted or removed. - 0 - 24 - read-write - - - - - USRID - User ID (scratchpad) register - 0x68 - 0x20 - - - USRID - User identification register, value set by user. Can also be used as a scratchpad register by user. - 0 - 32 - read-write - - - - - VERID - Version ID (scratchpad) register - 0x6C - 0x20 - 0x5432270A - - - VERSIONID - Hardware version register. Can also be read by fireware. - 0 - 32 - read-only - - - - - HCON - Hardware feature register - 0x70 - 0x20 - 0x03444CC3 - - - CARD_TYPE - Hardware support SDIO and MMC. - 0 - 1 - read-only - - - CARD_NUM - Support card number is 2. - 1 - 5 - read-only - - - BUS_TYPE - Register config is APB bus. - 6 - 1 - read-only - - - DATA_WIDTH - Regisger data widht is 32. - 7 - 3 - read-only - - - ADDR_WIDTH - Register address width is 32. - 10 - 6 - read-only - - - DMA_WIDTH - DMA data witdth is 32. - 18 - 3 - read-only - - - RAM_INDISE - Inside RAM in SDMMC module. - 21 - 1 - read-only - - - HOLD - Have a hold regiser in data path . - 22 - 1 - read-only - - - NUM_CLK_DIV - Have 4 clk divider in design . - 24 - 2 - read-only - - - - - UHS - UHS-1 register - 0x74 - 0x20 - - - DDR - DDR mode selecton,1 bit for each card. -0-Non-DDR mdoe. -1-DDR mdoe. - 16 - 2 - read-write - - - - - RST_N - Card reset register - 0x78 - 0x20 - 0x00000001 - - - CARD_RESET - Hardware reset. -1: Active mode; -0: Reset. -These bits cause the cards to enter pre-idle state, which requires them to be re-initialized. SDHOST_RST_CARD_RESET[0] should be set to 1'b0 to reset card0, SDHOST_RST_CARD_RESET[1] should be set to 1'b0 to reset card1. - 0 - 2 - read-write - - - - - BMOD - Burst mode transfer configuration register - 0x80 - 0x20 - - - SWR - Software Reset. When set, the DMA Controller resets all its internal registers. It is automatically cleared after one clock cycle. - 0 - 1 - read-write - - - FB - Fixed Burst. Controls whether the AHB Master interface performs fixed burst transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16 during start of normal burst transfers. When reset, the AHB will use SINGLE and INCR burst transfer operations. - 1 - 1 - read-write - - - DE - IDMAC Enable. When set, the IDMAC is enabled. - 7 - 1 - read-write - - - PBL - Programmable Burst Length. These bits indicate the maximum number of beats to be performed in one IDMAC???Internal DMA Control???transaction. The IDMAC will always attempt to burst as specified in PBL each time it starts a burst transfer on the host bus. The permissible values are 1, 4, 8, 16, 32, 64, 128 and 256. This value is the mirror of MSIZE of FIFOTH register. In order to change this value, write the required value to FIFOTH register. This is an encode value as follows: -000: 1-byte transfer; -001: 4-byte transfer; -010: 8-byte transfer; -011: 16-byte transfer; -100: 32-byte transfer; -101: 64-byte transfer; -110: 128-byte transfer; -111: 256-byte transfer. -PBL is a read-only value and is applicable only for data access, it does not apply to descriptor access. - 8 - 3 - read-write - - - - - PLDMND - Poll demand configuration register - 0x84 - 0x20 - - - PD - Poll Demand. If the OWNER bit of a descriptor is not set, the FSM goes to the Suspend state. The host needs to write any value into this register for the IDMAC FSM to resume normal descriptor fetch operation. This is a write only . - 0 - 32 - write-only - - - - - DBADDR - Descriptor base address register - 0x88 - 0x20 - - - DBADDR - Start of Descriptor List. Contains the base address of the First Descriptor. The LSB bits [1:0] are ignored and taken as all-zero by the IDMAC internally. Hence these LSB bits may be treated as read-only. - 0 - 32 - read-write - - - - - IDSTS - IDMAC status register - 0x8C - 0x20 - - - TI - Transmit Interrupt. Indicates that data transmission is finished for a descriptor. Writing 1 clears this bit. - 0 - 1 - read-write - - - RI - Receive Interrupt. Indicates the completion of data reception for a descriptor. Writing 1 clears this bit. - 1 - 1 - read-write - - - FBE - Fatal Bus Error Interrupt. Indicates that a Bus Error occurred (IDSTS[12:10]) . When this bit is set, the DMA disables all its bus accesses. Writing 1 clears this bit. - 2 - 1 - read-write - - - DU - Descriptor Unavailable Interrupt. This bit is set when the descriptor is unavailable due to OWNER bit = 0 (DES0[31] = 0). Writing 1 clears this bit. - 4 - 1 - read-write - - - CES - Card Error Summary. Indicates the status of the transaction to/from the card, also present in RINTSTS. Indicates the logical OR of the following bits: -EBE : End Bit Error; -RTO : Response Timeout/Boot Ack Timeout; -RCRC : Response CRC; -SBE : Start Bit Error; -DRTO : Data Read Timeout/BDS timeout; -DCRC : Data CRC for Receive; -RE : Response Error. -Writing 1 clears this bit. The abort condition of the IDMAC depends on the setting of this CES bit. If the CES bit is enabled, then the IDMAC aborts on a response error. - 5 - 1 - read-write - - - NIS - Normal Interrupt Summary. Logical OR of the following: IDSTS[0] : Transmit Interrupt, IDSTS[1] : Receive Interrupt. Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes NIS to be set is cleared. Writing 1 clears this bit. - 8 - 1 - read-write - - - AIS - Abnormal Interrupt Summary. Logical OR of the following: IDSTS[2] : Fatal Bus Interrupt, IDSTS[4] : DU bit Interrupt. Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes AIS to be set is cleared. Writing 1 clears this bit. - 9 - 1 - read-write - - - FBE_CODE - Fatal Bus Error Code. Indicates the type of error that caused a Bus Error. Valid only when the Fatal Bus Error bit IDSTS[2] is set. This field does not generate an interrupt. -001: Host Abort received during transmission; -010: Host Abort received during reception; -Others: Reserved. - 10 - 3 - read-write - - - FSM - DMAC FSM present state. -0: DMA_IDLE (idle state); -1: DMA_SUSPEND (suspend state); -2: DESC_RD (descriptor reading state); -3: DESC_CHK (descriptor checking state); -4: DMA_RD_REQ_WAIT (read-data request waiting state); -5: DMA_WR_REQ_WAIT (write-data request waiting state); -6: DMA_RD (data-read state); -7: DMA_WR (data-write state); -8: DESC_CLOSE (descriptor close state). - 13 - 4 - read-write - - - - - IDINTEN - IDMAC interrupt enable register - 0x90 - 0x20 - - - TI - Transmit Interrupt Enable. When set with Normal Interrupt Summary Enable, Transmit Interrupt is enabled. When reset, Transmit Interrupt is disabled. - 0 - 1 - read-write - - - RI - Receive Interrupt Enable. When set with Normal Interrupt Summary Enable, Receive Interrupt is enabled. When reset, Receive Interrupt is disabled. - 1 - 1 - read-write - - - FBE - Fatal Bus Error Enable. When set with Abnormal Interrupt Summary Enable, the Fatal Bus Error Interrupt is enabled. When reset, Fatal Bus Error Enable Interrupt is disabled. - 2 - 1 - read-write - - - DU - Descriptor Unavailable Interrupt. When set along with Abnormal Interrupt Summary Enable, the DU interrupt is enabled. - 4 - 1 - read-write - - - CES - Card Error summary Interrupt Enable. When set, it enables the Card Interrupt summary. - 5 - 1 - read-write - - - NI - Normal Interrupt Summary Enable. When set, a normal interrupt is enabled. When reset, a normal interrupt is disabled. This bit enables the following bits: -IDINTEN[0]: Transmit Interrupt; -IDINTEN[1]: Receive Interrupt. - 8 - 1 - read-write - - - AI - Abnormal Interrupt Summary Enable. When set, an abnormal interrupt is enabled. This bit enables the following bits: -IDINTEN[2]: Fatal Bus Error Interrupt; -IDINTEN[4]: DU Interrupt. - 9 - 1 - read-write - - - - - DSCADDR - Host descriptor address pointer - 0x94 - 0x20 - - - DSCADDR - Host Descriptor Address Pointer, updated by IDMAC during operation and cleared on reset. This register points to the start address of the current descriptor read by the IDMAC. - 0 - 32 - read-only - - - - - BUFADDR - Host buffer address pointer register - 0x98 - 0x20 - - - BUFADDR - Host Buffer Address Pointer, updated by IDMAC during operation and cleared on reset. This register points to the current Data Buffer Address being accessed by the IDMAC. - 0 - 32 - read-only - - - - - CARDTHRCTL - Card Threshold Control register - 0x100 - 0x20 - - - CARDRDTHREN - Card read threshold enable. -1'b0-Card read threshold disabled. -1'b1-Card read threshold enabled. - 0 - 1 - read-write - - - CARDCLRINTEN - Busy clear interrupt generation: -1'b0-Busy clear interrypt disabled. -1'b1-Busy clear interrypt enabled. - 1 - 1 - read-write - - - CARDWRTHREN - Applicable when HS400 mode is enabled. -1'b0-Card write Threshold disabled. -1'b1-Card write Threshold enabled. - 2 - 1 - read-write - - - CARDTHRESHOLD - The inside FIFO size is 512,This register is applicable when SDHOST_CARDERTHREN_REG is set to 1 or SDHOST_CARDRDTHREN_REG set to 1. - 16 - 16 - read-write - - - - - EMMCDDR - eMMC DDR register - 0x10C - 0x20 - - - HALFSTARTBIT - Control for start bit detection mechanism duration of start bit.Each bit refers to one slot.Set this bit to 1 for eMMC4.5 and above,set to 0 for SD applications.For eMMC4.5,start bit can be: -1'b0-Full cycle. -1'b1-less than one full cycle. - 0 - 2 - read-write - - - HS400_MODE - Set 1 to enable HS400 mode. - 31 - 1 - read-write - - - - - ENSHIFT - Enable Phase Shift register - 0x110 - 0x20 - - - ENABLE_SHIFT - Control for the amount of phase shift provided on the default enables in the design.Two bits assigned for each card. -2'b00-Default phase shift. -2'b01-Enables shifted to next immediate positive edge. -2'b10-Enables shifted to next immediate negative edge. -2'b11-Reserved. - 0 - 4 - read-write - - - - - BUFFIFO - CPU write and read transmit data by FIFO - 0x200 - 0x20 - - - BUFFIFO - CPU write and read transmit data by FIFO. This register points to the current Data FIFO . - 0 - 32 - read-write - - - - - CLK_EDGE_SEL - SDIO control register. - 0x800 - 0x20 - 0x00820200 - - - CCLKIN_EDGE_DRV_SEL - It's used to select the clock phase of the output signal from phase 0, phase 90, phase 180, phase 270. - 0 - 3 - read-write - - - CCLKIN_EDGE_SAM_SEL - It's used to select the clock phase of the input signal from phase 0, phase 90, phase 180, phase 270. - 3 - 3 - read-write - - - CCLKIN_EDGE_SLF_SEL - It's used to select the clock phase of the internal signal from phase 0, phase 90, phase 180, phase 270. - 6 - 3 - read-write - - - CCLLKIN_EDGE_H - The high level of the divider clock. The value should be smaller than CCLKIN_EDGE_L. - 9 - 4 - read-write - - - CCLLKIN_EDGE_L - The low level of the divider clock. The value should be larger than CCLKIN_EDGE_H. - 13 - 4 - read-write - - - CCLLKIN_EDGE_N - The clock division of cclk_in. - 17 - 4 - read-write - - - ESDIO_MODE - Enable esdio mode. - 21 - 1 - read-write - - - ESD_MODE - Enable esd mode. - 22 - 1 - read-write - - - CCLK_EN - Sdio clock enable. - 23 - 1 - read-write - - - ULTRA_HIGH_SPEED_MODE - Enable ultra high speed mode, use dll to generate clk. - 24 - 1 - read-write - - - - - RAW_INTS - SDIO raw ints register. - 0x804 - 0x20 - - - RAW_INTS - It indicates raw ints. - 0 - 32 - read-only - - - - - DLL_CLK_CONF - SDIO DLL clock control register. - 0x808 - 0x20 - - - DLL_CCLK_IN_SLF_EN - Clock enable of cclk_in_slf when ULTRA_HIGH_SPEED_MODE==1. - 0 - 1 - read-write - - - DLL_CCLK_IN_DRV_EN - Clock enable of cclk_in_drv when ULTRA_HIGH_SPEED_MODE==1. - 1 - 1 - read-write - - - DLL_CCLK_IN_SAM_EN - Clock enable of cclk_in_sam when ULTRA_HIGH_SPEED_MODE==1. - 2 - 1 - read-write - - - DLL_CCLK_IN_SLF_PHASE - It's used to control the phase of cclk_in_slf when ULTRA_HIGH_SPEED_MODE==1. - 3 - 6 - read-write - - - DLL_CCLK_IN_DRV_PHASE - It's used to control the phase of cclk_in_drv when ULTRA_HIGH_SPEED_MODE==1. - 9 - 6 - read-write - - - DLL_CCLK_IN_SAM_PHASE - It's used to control the phase of cclk_in_sam when ULTRA_HIGH_SPEED_MODE==1. - 15 - 6 - read-write - - - - - DLL_CONF - SDIO DLL configuration register. - 0x80C - 0x20 - - - DLL_CAL_STOP - Set 1 to stop calibration. - 0 - 1 - read-write - - - DLL_CAL_END - 1 means calibration finished. - 1 - 1 - read-only - - - - - - - SHA - SHA (Secure Hash Algorithm) Accelerator - SHA - 0x50091000 - - 0x0 - 0xB0 - registers - - - SHA - 70 - - - - MODE - Initial configuration register. - 0x0 - 0x20 - - - MODE - Sha mode. - 0 - 3 - read-write - - - - - T_STRING - SHA 512/t configuration register 0. - 0x4 - 0x20 - - - T_STRING - Sha t_string (used if and only if mode == SHA_512/t). - 0 - 32 - read-write - - - - - T_LENGTH - SHA 512/t configuration register 1. - 0x8 - 0x20 - - - T_LENGTH - Sha t_length (used if and only if mode == SHA_512/t). - 0 - 6 - read-write - - - - - DMA_BLOCK_NUM - DMA configuration register 0. - 0xC - 0x20 - - - DMA_BLOCK_NUM - Dma-sha block number. - 0 - 6 - read-write - - - - - START - Typical SHA configuration register 0. - 0x10 - 0x20 - - - START - Reserved. - 1 - 31 - read-only - - - - - CONTINUE - Typical SHA configuration register 1. - 0x14 - 0x20 - - - CONTINUE - Reserved. - 1 - 31 - read-only - - - - - BUSY - Busy register. - 0x18 - 0x20 - - - STATE - Sha busy state. 1'b0: idle. 1'b1: busy. - 0 - 1 - read-only - - - - - DMA_START - DMA configuration register 1. - 0x1C - 0x20 - - - DMA_START - Start dma-sha. - 0 - 1 - write-only - - - - - DMA_CONTINUE - DMA configuration register 2. - 0x20 - 0x20 - - - DMA_CONTINUE - Continue dma-sha. - 0 - 1 - write-only - - - - - CLEAR_IRQ - Interrupt clear register. - 0x24 - 0x20 - - - CLEAR_INTERRUPT - Clear sha interrupt. - 0 - 1 - write-only - - - - - IRQ_ENA - Interrupt enable register. - 0x28 - 0x20 - - - INTERRUPT_ENA - Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable. - 0 - 1 - read-write - - - - - DATE - Date register. - 0x2C - 0x20 - 0x20201229 - - - DATE - Sha date information/ sha version information. - 0 - 30 - read-write - - - - - 16 - 0x4 - H_MEM[%s] - Sha H memory which contains intermediate hash or finial hash. - 0x40 - 0x20 - - - 16 - 0x4 - M_MEM[%s] - Sha M memory which contains message. - 0x80 - 0x20 - - - - - SOC_ETM - Event Task Matrix - SOC_ETM - 0x500D5000 - - 0x0 - 0x228 - registers - - - - CH_ENA_AD0 - Channel enable status register - 0x0 - 0x20 - - - CH_ENA0 - Represents ch0 enable status.\\0: Disable\\1: Enable - 0 - 1 - read-write - - - CH_ENA1 - Represents ch1 enable status.\\0: Disable\\1: Enable - 1 - 1 - read-write - - - CH_ENA2 - Represents ch2 enable status.\\0: Disable\\1: Enable - 2 - 1 - read-write - - - CH_ENA3 - Represents ch3 enable status.\\0: Disable\\1: Enable - 3 - 1 - read-write - - - CH_ENA4 - Represents ch4 enable status.\\0: Disable\\1: Enable - 4 - 1 - read-write - - - CH_ENA5 - Represents ch5 enable status.\\0: Disable\\1: Enable - 5 - 1 - read-write - - - CH_ENA6 - Represents ch6 enable status.\\0: Disable\\1: Enable - 6 - 1 - read-write - - - CH_ENA7 - Represents ch7 enable status.\\0: Disable\\1: Enable - 7 - 1 - read-write - - - CH_ENA8 - Represents ch8 enable status.\\0: Disable\\1: Enable - 8 - 1 - read-write - - - CH_ENA9 - Represents ch9 enable status.\\0: Disable\\1: Enable - 9 - 1 - read-write - - - CH_ENA10 - Represents ch10 enable status.\\0: Disable\\1: Enable - 10 - 1 - read-write - - - CH_ENA11 - Represents ch11 enable status.\\0: Disable\\1: Enable - 11 - 1 - read-write - - - CH_ENA12 - Represents ch12 enable status.\\0: Disable\\1: Enable - 12 - 1 - read-write - - - CH_ENA13 - Represents ch13 enable status.\\0: Disable\\1: Enable - 13 - 1 - read-write - - - CH_ENA14 - Represents ch14 enable status.\\0: Disable\\1: Enable - 14 - 1 - read-write - - - CH_ENA15 - Represents ch15 enable status.\\0: Disable\\1: Enable - 15 - 1 - read-write - - - CH_ENA16 - Represents ch16 enable status.\\0: Disable\\1: Enable - 16 - 1 - read-write - - - CH_ENA17 - Represents ch17 enable status.\\0: Disable\\1: Enable - 17 - 1 - read-write - - - CH_ENA18 - Represents ch18 enable status.\\0: Disable\\1: Enable - 18 - 1 - read-write - - - CH_ENA19 - Represents ch19 enable status.\\0: Disable\\1: Enable - 19 - 1 - read-write - - - CH_ENA20 - Represents ch20 enable status.\\0: Disable\\1: Enable - 20 - 1 - read-write - - - CH_ENA21 - Represents ch21 enable status.\\0: Disable\\1: Enable - 21 - 1 - read-write - - - CH_ENA22 - Represents ch22 enable status.\\0: Disable\\1: Enable - 22 - 1 - read-write - - - CH_ENA23 - Represents ch23 enable status.\\0: Disable\\1: Enable - 23 - 1 - read-write - - - CH_ENA24 - Represents ch24 enable status.\\0: Disable\\1: Enable - 24 - 1 - read-write - - - CH_ENA25 - Represents ch25 enable status.\\0: Disable\\1: Enable - 25 - 1 - read-write - - - CH_ENA26 - Represents ch26 enable status.\\0: Disable\\1: Enable - 26 - 1 - read-write - - - CH_ENA27 - Represents ch27 enable status.\\0: Disable\\1: Enable - 27 - 1 - read-write - - - CH_ENA28 - Represents ch28 enable status.\\0: Disable\\1: Enable - 28 - 1 - read-write - - - CH_ENA29 - Represents ch29 enable status.\\0: Disable\\1: Enable - 29 - 1 - read-write - - - CH_ENA30 - Represents ch30 enable status.\\0: Disable\\1: Enable - 30 - 1 - read-write - - - CH_ENA31 - Represents ch31 enable status.\\0: Disable\\1: Enable - 31 - 1 - read-write - - - - - CH_ENA_AD0_SET - Channel enable set register - 0x4 - 0x20 - - - CH_SET0 - Configures whether or not to enable ch0.\\0: Invalid, No effect\\1: Enable - 0 - 1 - write-only - - - CH_SET1 - Configures whether or not to enable ch1.\\0: Invalid, No effect\\1: Enable - 1 - 1 - write-only - - - CH_SET2 - Configures whether or not to enable ch2.\\0: Invalid, No effect\\1: Enable - 2 - 1 - write-only - - - CH_SET3 - Configures whether or not to enable ch3.\\0: Invalid, No effect\\1: Enable - 3 - 1 - write-only - - - CH_SET4 - Configures whether or not to enable ch4.\\0: Invalid, No effect\\1: Enable - 4 - 1 - write-only - - - CH_SET5 - Configures whether or not to enable ch5.\\0: Invalid, No effect\\1: Enable - 5 - 1 - write-only - - - CH_SET6 - Configures whether or not to enable ch6.\\0: Invalid, No effect\\1: Enable - 6 - 1 - write-only - - - CH_SET7 - Configures whether or not to enable ch7.\\0: Invalid, No effect\\1: Enable - 7 - 1 - write-only - - - CH_SET8 - Configures whether or not to enable ch8.\\0: Invalid, No effect\\1: Enable - 8 - 1 - write-only - - - CH_SET9 - Configures whether or not to enable ch9.\\0: Invalid, No effect\\1: Enable - 9 - 1 - write-only - - - CH_SET10 - Configures whether or not to enable ch10.\\0: Invalid, No effect\\1: Enable - 10 - 1 - write-only - - - CH_SET11 - Configures whether or not to enable ch11.\\0: Invalid, No effect\\1: Enable - 11 - 1 - write-only - - - CH_SET12 - Configures whether or not to enable ch12.\\0: Invalid, No effect\\1: Enable - 12 - 1 - write-only - - - CH_SET13 - Configures whether or not to enable ch13.\\0: Invalid, No effect\\1: Enable - 13 - 1 - write-only - - - CH_SET14 - Configures whether or not to enable ch14.\\0: Invalid, No effect\\1: Enable - 14 - 1 - write-only - - - CH_SET15 - Configures whether or not to enable ch15.\\0: Invalid, No effect\\1: Enable - 15 - 1 - write-only - - - CH_SET16 - Configures whether or not to enable ch16.\\0: Invalid, No effect\\1: Enable - 16 - 1 - write-only - - - CH_SET17 - Configures whether or not to enable ch17.\\0: Invalid, No effect\\1: Enable - 17 - 1 - write-only - - - CH_SET18 - Configures whether or not to enable ch18.\\0: Invalid, No effect\\1: Enable - 18 - 1 - write-only - - - CH_SET19 - Configures whether or not to enable ch19.\\0: Invalid, No effect\\1: Enable - 19 - 1 - write-only - - - CH_SET20 - Configures whether or not to enable ch20.\\0: Invalid, No effect\\1: Enable - 20 - 1 - write-only - - - CH_SET21 - Configures whether or not to enable ch21.\\0: Invalid, No effect\\1: Enable - 21 - 1 - write-only - - - CH_SET22 - Configures whether or not to enable ch22.\\0: Invalid, No effect\\1: Enable - 22 - 1 - write-only - - - CH_SET23 - Configures whether or not to enable ch23.\\0: Invalid, No effect\\1: Enable - 23 - 1 - write-only - - - CH_SET24 - Configures whether or not to enable ch24.\\0: Invalid, No effect\\1: Enable - 24 - 1 - write-only - - - CH_SET25 - Configures whether or not to enable ch25.\\0: Invalid, No effect\\1: Enable - 25 - 1 - write-only - - - CH_SET26 - Configures whether or not to enable ch26.\\0: Invalid, No effect\\1: Enable - 26 - 1 - write-only - - - CH_SET27 - Configures whether or not to enable ch27.\\0: Invalid, No effect\\1: Enable - 27 - 1 - write-only - - - CH_SET28 - Configures whether or not to enable ch28.\\0: Invalid, No effect\\1: Enable - 28 - 1 - write-only - - - CH_SET29 - Configures whether or not to enable ch29.\\0: Invalid, No effect\\1: Enable - 29 - 1 - write-only - - - CH_SET30 - Configures whether or not to enable ch30.\\0: Invalid, No effect\\1: Enable - 30 - 1 - write-only - - - CH_SET31 - Configures whether or not to enable ch31.\\0: Invalid, No effect\\1: Enable - 31 - 1 - write-only - - - - - CH_ENA_AD0_CLR - Channel enable clear register - 0x8 - 0x20 - - - CH_CLR0 - Configures whether or not to clear ch0 enable.\\0: Invalid, No effect\\1: Clear - 0 - 1 - write-only - - - CH_CLR1 - Configures whether or not to clear ch1 enable.\\0: Invalid, No effect\\1: Clear - 1 - 1 - write-only - - - CH_CLR2 - Configures whether or not to clear ch2 enable.\\0: Invalid, No effect\\1: Clear - 2 - 1 - write-only - - - CH_CLR3 - Configures whether or not to clear ch3 enable.\\0: Invalid, No effect\\1: Clear - 3 - 1 - write-only - - - CH_CLR4 - Configures whether or not to clear ch4 enable.\\0: Invalid, No effect\\1: Clear - 4 - 1 - write-only - - - CH_CLR5 - Configures whether or not to clear ch5 enable.\\0: Invalid, No effect\\1: Clear - 5 - 1 - write-only - - - CH_CLR6 - Configures whether or not to clear ch6 enable.\\0: Invalid, No effect\\1: Clear - 6 - 1 - write-only - - - CH_CLR7 - Configures whether or not to clear ch7 enable.\\0: Invalid, No effect\\1: Clear - 7 - 1 - write-only - - - CH_CLR8 - Configures whether or not to clear ch8 enable.\\0: Invalid, No effect\\1: Clear - 8 - 1 - write-only - - - CH_CLR9 - Configures whether or not to clear ch9 enable.\\0: Invalid, No effect\\1: Clear - 9 - 1 - write-only - - - CH_CLR10 - Configures whether or not to clear ch10 enable.\\0: Invalid, No effect\\1: Clear - 10 - 1 - write-only - - - CH_CLR11 - Configures whether or not to clear ch11 enable.\\0: Invalid, No effect\\1: Clear - 11 - 1 - write-only - - - CH_CLR12 - Configures whether or not to clear ch12 enable.\\0: Invalid, No effect\\1: Clear - 12 - 1 - write-only - - - CH_CLR13 - Configures whether or not to clear ch13 enable.\\0: Invalid, No effect\\1: Clear - 13 - 1 - write-only - - - CH_CLR14 - Configures whether or not to clear ch14 enable.\\0: Invalid, No effect\\1: Clear - 14 - 1 - write-only - - - CH_CLR15 - Configures whether or not to clear ch15 enable.\\0: Invalid, No effect\\1: Clear - 15 - 1 - write-only - - - CH_CLR16 - Configures whether or not to clear ch16 enable.\\0: Invalid, No effect\\1: Clear - 16 - 1 - write-only - - - CH_CLR17 - Configures whether or not to clear ch17 enable.\\0: Invalid, No effect\\1: Clear - 17 - 1 - write-only - - - CH_CLR18 - Configures whether or not to clear ch18 enable.\\0: Invalid, No effect\\1: Clear - 18 - 1 - write-only - - - CH_CLR19 - Configures whether or not to clear ch19 enable.\\0: Invalid, No effect\\1: Clear - 19 - 1 - write-only - - - CH_CLR20 - Configures whether or not to clear ch20 enable.\\0: Invalid, No effect\\1: Clear - 20 - 1 - write-only - - - CH_CLR21 - Configures whether or not to clear ch21 enable.\\0: Invalid, No effect\\1: Clear - 21 - 1 - write-only - - - CH_CLR22 - Configures whether or not to clear ch22 enable.\\0: Invalid, No effect\\1: Clear - 22 - 1 - write-only - - - CH_CLR23 - Configures whether or not to clear ch23 enable.\\0: Invalid, No effect\\1: Clear - 23 - 1 - write-only - - - CH_CLR24 - Configures whether or not to clear ch24 enable.\\0: Invalid, No effect\\1: Clear - 24 - 1 - write-only - - - CH_CLR25 - Configures whether or not to clear ch25 enable.\\0: Invalid, No effect\\1: Clear - 25 - 1 - write-only - - - CH_CLR26 - Configures whether or not to clear ch26 enable.\\0: Invalid, No effect\\1: Clear - 26 - 1 - write-only - - - CH_CLR27 - Configures whether or not to clear ch27 enable.\\0: Invalid, No effect\\1: Clear - 27 - 1 - write-only - - - CH_CLR28 - Configures whether or not to clear ch28 enable.\\0: Invalid, No effect\\1: Clear - 28 - 1 - write-only - - - CH_CLR29 - Configures whether or not to clear ch29 enable.\\0: Invalid, No effect\\1: Clear - 29 - 1 - write-only - - - CH_CLR30 - Configures whether or not to clear ch30 enable.\\0: Invalid, No effect\\1: Clear - 30 - 1 - write-only - - - CH_CLR31 - Configures whether or not to clear ch31 enable.\\0: Invalid, No effect\\1: Clear - 31 - 1 - write-only - - - - - CH_ENA_AD1 - Channel enable status register - 0xC - 0x20 - - - CH_ENA32 - Represents ch32 enable status.\\0: Disable\\1: Enable - 0 - 1 - read-write - - - CH_ENA33 - Represents ch33 enable status.\\0: Disable\\1: Enable - 1 - 1 - read-write - - - CH_ENA34 - Represents ch34 enable status.\\0: Disable\\1: Enable - 2 - 1 - read-write - - - CH_ENA35 - Represents ch35 enable status.\\0: Disable\\1: Enable - 3 - 1 - read-write - - - CH_ENA36 - Represents ch36 enable status.\\0: Disable\\1: Enable - 4 - 1 - read-write - - - CH_ENA37 - Represents ch37 enable status.\\0: Disable\\1: Enable - 5 - 1 - read-write - - - CH_ENA38 - Represents ch38 enable status.\\0: Disable\\1: Enable - 6 - 1 - read-write - - - CH_ENA39 - Represents ch39 enable status.\\0: Disable\\1: Enable - 7 - 1 - read-write - - - CH_ENA40 - Represents ch40 enable status.\\0: Disable\\1: Enable - 8 - 1 - read-write - - - CH_ENA41 - Represents ch41 enable status.\\0: Disable\\1: Enable - 9 - 1 - read-write - - - CH_ENA42 - Represents ch42 enable status.\\0: Disable\\1: Enable - 10 - 1 - read-write - - - CH_ENA43 - Represents ch43 enable status.\\0: Disable\\1: Enable - 11 - 1 - read-write - - - CH_ENA44 - Represents ch44 enable status.\\0: Disable\\1: Enable - 12 - 1 - read-write - - - CH_ENA45 - Represents ch45 enable status.\\0: Disable\\1: Enable - 13 - 1 - read-write - - - CH_ENA46 - Represents ch46 enable status.\\0: Disable\\1: Enable - 14 - 1 - read-write - - - CH_ENA47 - Represents ch47 enable status.\\0: Disable\\1: Enable - 15 - 1 - read-write - - - CH_ENA48 - Represents ch48 enable status.\\0: Disable\\1: Enable - 16 - 1 - read-write - - - CH_ENA49 - Represents ch49 enable status.\\0: Disable\\1: Enable - 17 - 1 - read-write - - - - - CH_ENA_AD1_SET - Channel enable set register - 0x10 - 0x20 - - - CH_SET32 - Configures whether or not to enable ch32.\\0: Invalid, No effect\\1: Enable - 0 - 1 - write-only - - - CH_SET33 - Configures whether or not to enable ch33.\\0: Invalid, No effect\\1: Enable - 1 - 1 - write-only - - - CH_SET34 - Configures whether or not to enable ch34.\\0: Invalid, No effect\\1: Enable - 2 - 1 - write-only - - - CH_SET35 - Configures whether or not to enable ch35.\\0: Invalid, No effect\\1: Enable - 3 - 1 - write-only - - - CH_SET36 - Configures whether or not to enable ch36.\\0: Invalid, No effect\\1: Enable - 4 - 1 - write-only - - - CH_SET37 - Configures whether or not to enable ch37.\\0: Invalid, No effect\\1: Enable - 5 - 1 - write-only - - - CH_SET38 - Configures whether or not to enable ch38.\\0: Invalid, No effect\\1: Enable - 6 - 1 - write-only - - - CH_SET39 - Configures whether or not to enable ch39.\\0: Invalid, No effect\\1: Enable - 7 - 1 - write-only - - - CH_SET40 - Configures whether or not to enable ch40.\\0: Invalid, No effect\\1: Enable - 8 - 1 - write-only - - - CH_SET41 - Configures whether or not to enable ch41.\\0: Invalid, No effect\\1: Enable - 9 - 1 - write-only - - - CH_SET42 - Configures whether or not to enable ch42.\\0: Invalid, No effect\\1: Enable - 10 - 1 - write-only - - - CH_SET43 - Configures whether or not to enable ch43.\\0: Invalid, No effect\\1: Enable - 11 - 1 - write-only - - - CH_SET44 - Configures whether or not to enable ch44.\\0: Invalid, No effect\\1: Enable - 12 - 1 - write-only - - - CH_SET45 - Configures whether or not to enable ch45.\\0: Invalid, No effect\\1: Enable - 13 - 1 - write-only - - - CH_SET46 - Configures whether or not to enable ch46.\\0: Invalid, No effect\\1: Enable - 14 - 1 - write-only - - - CH_SET47 - Configures whether or not to enable ch47.\\0: Invalid, No effect\\1: Enable - 15 - 1 - write-only - - - CH_SET48 - Configures whether or not to enable ch48.\\0: Invalid, No effect\\1: Enable - 16 - 1 - write-only - - - CH_SET49 - Configures whether or not to enable ch49.\\0: Invalid, No effect\\1: Enable - 17 - 1 - write-only - - - - - CH_ENA_AD1_CLR - Channel enable clear register - 0x14 - 0x20 - - - CH_CLR32 - Configures whether or not to clear ch32 enable.\\0: Invalid, No effect\\1: Clear - 0 - 1 - write-only - - - CH_CLR33 - Configures whether or not to clear ch33 enable.\\0: Invalid, No effect\\1: Clear - 1 - 1 - write-only - - - CH_CLR34 - Configures whether or not to clear ch34 enable.\\0: Invalid, No effect\\1: Clear - 2 - 1 - write-only - - - CH_CLR35 - Configures whether or not to clear ch35 enable.\\0: Invalid, No effect\\1: Clear - 3 - 1 - write-only - - - CH_CLR36 - Configures whether or not to clear ch36 enable.\\0: Invalid, No effect\\1: Clear - 4 - 1 - write-only - - - CH_CLR37 - Configures whether or not to clear ch37 enable.\\0: Invalid, No effect\\1: Clear - 5 - 1 - write-only - - - CH_CLR38 - Configures whether or not to clear ch38 enable.\\0: Invalid, No effect\\1: Clear - 6 - 1 - write-only - - - CH_CLR39 - Configures whether or not to clear ch39 enable.\\0: Invalid, No effect\\1: Clear - 7 - 1 - write-only - - - CH_CLR40 - Configures whether or not to clear ch40 enable.\\0: Invalid, No effect\\1: Clear - 8 - 1 - write-only - - - CH_CLR41 - Configures whether or not to clear ch41 enable.\\0: Invalid, No effect\\1: Clear - 9 - 1 - write-only - - - CH_CLR42 - Configures whether or not to clear ch42 enable.\\0: Invalid, No effect\\1: Clear - 10 - 1 - write-only - - - CH_CLR43 - Configures whether or not to clear ch43 enable.\\0: Invalid, No effect\\1: Clear - 11 - 1 - write-only - - - CH_CLR44 - Configures whether or not to clear ch44 enable.\\0: Invalid, No effect\\1: Clear - 12 - 1 - write-only - - - CH_CLR45 - Configures whether or not to clear ch45 enable.\\0: Invalid, No effect\\1: Clear - 13 - 1 - write-only - - - CH_CLR46 - Configures whether or not to clear ch46 enable.\\0: Invalid, No effect\\1: Clear - 14 - 1 - write-only - - - CH_CLR47 - Configures whether or not to clear ch47 enable.\\0: Invalid, No effect\\1: Clear - 15 - 1 - write-only - - - CH_CLR48 - Configures whether or not to clear ch48 enable.\\0: Invalid, No effect\\1: Clear - 16 - 1 - write-only - - - CH_CLR49 - Configures whether or not to clear ch49 enable.\\0: Invalid, No effect\\1: Clear - 17 - 1 - write-only - - - - - CH0_EVT_ID - Channel0 event id register - 0x18 - 0x20 - - - CH0_EVT_ID - Configures ch0_evt_id - 0 - 8 - read-write - - - - - CH0_TASK_ID - Channel0 task id register - 0x1C - 0x20 - - - CH0_TASK_ID - Configures ch0_task_id - 0 - 8 - read-write - - - - - CH1_EVT_ID - Channel1 event id register - 0x20 - 0x20 - - - CH1_EVT_ID - Configures ch1_evt_id - 0 - 8 - read-write - - - - - CH1_TASK_ID - Channel1 task id register - 0x24 - 0x20 - - - CH1_TASK_ID - Configures ch1_task_id - 0 - 8 - read-write - - - - - CH2_EVT_ID - Channel2 event id register - 0x28 - 0x20 - - - CH2_EVT_ID - Configures ch2_evt_id - 0 - 8 - read-write - - - - - CH2_TASK_ID - Channel2 task id register - 0x2C - 0x20 - - - CH2_TASK_ID - Configures ch2_task_id - 0 - 8 - read-write - - - - - CH3_EVT_ID - Channel3 event id register - 0x30 - 0x20 - - - CH3_EVT_ID - Configures ch3_evt_id - 0 - 8 - read-write - - - - - CH3_TASK_ID - Channel3 task id register - 0x34 - 0x20 - - - CH3_TASK_ID - Configures ch3_task_id - 0 - 8 - read-write - - - - - CH4_EVT_ID - Channel4 event id register - 0x38 - 0x20 - - - CH4_EVT_ID - Configures ch4_evt_id - 0 - 8 - read-write - - - - - CH4_TASK_ID - Channel4 task id register - 0x3C - 0x20 - - - CH4_TASK_ID - Configures ch4_task_id - 0 - 8 - read-write - - - - - CH5_EVT_ID - Channel5 event id register - 0x40 - 0x20 - - - CH5_EVT_ID - Configures ch5_evt_id - 0 - 8 - read-write - - - - - CH5_TASK_ID - Channel5 task id register - 0x44 - 0x20 - - - CH5_TASK_ID - Configures ch5_task_id - 0 - 8 - read-write - - - - - CH6_EVT_ID - Channel6 event id register - 0x48 - 0x20 - - - CH6_EVT_ID - Configures ch6_evt_id - 0 - 8 - read-write - - - - - CH6_TASK_ID - Channel6 task id register - 0x4C - 0x20 - - - CH6_TASK_ID - Configures ch6_task_id - 0 - 8 - read-write - - - - - CH7_EVT_ID - Channel7 event id register - 0x50 - 0x20 - - - CH7_EVT_ID - Configures ch7_evt_id - 0 - 8 - read-write - - - - - CH7_TASK_ID - Channel7 task id register - 0x54 - 0x20 - - - CH7_TASK_ID - Configures ch7_task_id - 0 - 8 - read-write - - - - - CH8_EVT_ID - Channel8 event id register - 0x58 - 0x20 - - - CH8_EVT_ID - Configures ch8_evt_id - 0 - 8 - read-write - - - - - CH8_TASK_ID - Channel8 task id register - 0x5C - 0x20 - - - CH8_TASK_ID - Configures ch8_task_id - 0 - 8 - read-write - - - - - CH9_EVT_ID - Channel9 event id register - 0x60 - 0x20 - - - CH9_EVT_ID - Configures ch9_evt_id - 0 - 8 - read-write - - - - - CH9_TASK_ID - Channel9 task id register - 0x64 - 0x20 - - - CH9_TASK_ID - Configures ch9_task_id - 0 - 8 - read-write - - - - - CH10_EVT_ID - Channel10 event id register - 0x68 - 0x20 - - - CH10_EVT_ID - Configures ch10_evt_id - 0 - 8 - read-write - - - - - CH10_TASK_ID - Channel10 task id register - 0x6C - 0x20 - - - CH10_TASK_ID - Configures ch10_task_id - 0 - 8 - read-write - - - - - CH11_EVT_ID - Channel11 event id register - 0x70 - 0x20 - - - CH11_EVT_ID - Configures ch11_evt_id - 0 - 8 - read-write - - - - - CH11_TASK_ID - Channel11 task id register - 0x74 - 0x20 - - - CH11_TASK_ID - Configures ch11_task_id - 0 - 8 - read-write - - - - - CH12_EVT_ID - Channel12 event id register - 0x78 - 0x20 - - - CH12_EVT_ID - Configures ch12_evt_id - 0 - 8 - read-write - - - - - CH12_TASK_ID - Channel12 task id register - 0x7C - 0x20 - - - CH12_TASK_ID - Configures ch12_task_id - 0 - 8 - read-write - - - - - CH13_EVT_ID - Channel13 event id register - 0x80 - 0x20 - - - CH13_EVT_ID - Configures ch13_evt_id - 0 - 8 - read-write - - - - - CH13_TASK_ID - Channel13 task id register - 0x84 - 0x20 - - - CH13_TASK_ID - Configures ch13_task_id - 0 - 8 - read-write - - - - - CH14_EVT_ID - Channel14 event id register - 0x88 - 0x20 - - - CH14_EVT_ID - Configures ch14_evt_id - 0 - 8 - read-write - - - - - CH14_TASK_ID - Channel14 task id register - 0x8C - 0x20 - - - CH14_TASK_ID - Configures ch14_task_id - 0 - 8 - read-write - - - - - CH15_EVT_ID - Channel15 event id register - 0x90 - 0x20 - - - CH15_EVT_ID - Configures ch15_evt_id - 0 - 8 - read-write - - - - - CH15_TASK_ID - Channel15 task id register - 0x94 - 0x20 - - - CH15_TASK_ID - Configures ch15_task_id - 0 - 8 - read-write - - - - - CH16_EVT_ID - Channel16 event id register - 0x98 - 0x20 - - - CH16_EVT_ID - Configures ch16_evt_id - 0 - 8 - read-write - - - - - CH16_TASK_ID - Channel16 task id register - 0x9C - 0x20 - - - CH16_TASK_ID - Configures ch16_task_id - 0 - 8 - read-write - - - - - CH17_EVT_ID - Channel17 event id register - 0xA0 - 0x20 - - - CH17_EVT_ID - Configures ch17_evt_id - 0 - 8 - read-write - - - - - CH17_TASK_ID - Channel17 task id register - 0xA4 - 0x20 - - - CH17_TASK_ID - Configures ch17_task_id - 0 - 8 - read-write - - - - - CH18_EVT_ID - Channel18 event id register - 0xA8 - 0x20 - - - CH18_EVT_ID - Configures ch18_evt_id - 0 - 8 - read-write - - - - - CH18_TASK_ID - Channel18 task id register - 0xAC - 0x20 - - - CH18_TASK_ID - Configures ch18_task_id - 0 - 8 - read-write - - - - - CH19_EVT_ID - Channel19 event id register - 0xB0 - 0x20 - - - CH19_EVT_ID - Configures ch19_evt_id - 0 - 8 - read-write - - - - - CH19_TASK_ID - Channel19 task id register - 0xB4 - 0x20 - - - CH19_TASK_ID - Configures ch19_task_id - 0 - 8 - read-write - - - - - CH20_EVT_ID - Channel20 event id register - 0xB8 - 0x20 - - - CH20_EVT_ID - Configures ch20_evt_id - 0 - 8 - read-write - - - - - CH20_TASK_ID - Channel20 task id register - 0xBC - 0x20 - - - CH20_TASK_ID - Configures ch20_task_id - 0 - 8 - read-write - - - - - CH21_EVT_ID - Channel21 event id register - 0xC0 - 0x20 - - - CH21_EVT_ID - Configures ch21_evt_id - 0 - 8 - read-write - - - - - CH21_TASK_ID - Channel21 task id register - 0xC4 - 0x20 - - - CH21_TASK_ID - Configures ch21_task_id - 0 - 8 - read-write - - - - - CH22_EVT_ID - Channel22 event id register - 0xC8 - 0x20 - - - CH22_EVT_ID - Configures ch22_evt_id - 0 - 8 - read-write - - - - - CH22_TASK_ID - Channel22 task id register - 0xCC - 0x20 - - - CH22_TASK_ID - Configures ch22_task_id - 0 - 8 - read-write - - - - - CH23_EVT_ID - Channel23 event id register - 0xD0 - 0x20 - - - CH23_EVT_ID - Configures ch23_evt_id - 0 - 8 - read-write - - - - - CH23_TASK_ID - Channel23 task id register - 0xD4 - 0x20 - - - CH23_TASK_ID - Configures ch23_task_id - 0 - 8 - read-write - - - - - CH24_EVT_ID - Channel24 event id register - 0xD8 - 0x20 - - - CH24_EVT_ID - Configures ch24_evt_id - 0 - 8 - read-write - - - - - CH24_TASK_ID - Channel24 task id register - 0xDC - 0x20 - - - CH24_TASK_ID - Configures ch24_task_id - 0 - 8 - read-write - - - - - CH25_EVT_ID - Channel25 event id register - 0xE0 - 0x20 - - - CH25_EVT_ID - Configures ch25_evt_id - 0 - 8 - read-write - - - - - CH25_TASK_ID - Channel25 task id register - 0xE4 - 0x20 - - - CH25_TASK_ID - Configures ch25_task_id - 0 - 8 - read-write - - - - - CH26_EVT_ID - Channel26 event id register - 0xE8 - 0x20 - - - CH26_EVT_ID - Configures ch26_evt_id - 0 - 8 - read-write - - - - - CH26_TASK_ID - Channel26 task id register - 0xEC - 0x20 - - - CH26_TASK_ID - Configures ch26_task_id - 0 - 8 - read-write - - - - - CH27_EVT_ID - Channel27 event id register - 0xF0 - 0x20 - - - CH27_EVT_ID - Configures ch27_evt_id - 0 - 8 - read-write - - - - - CH27_TASK_ID - Channel27 task id register - 0xF4 - 0x20 - - - CH27_TASK_ID - Configures ch27_task_id - 0 - 8 - read-write - - - - - CH28_EVT_ID - Channel28 event id register - 0xF8 - 0x20 - - - CH28_EVT_ID - Configures ch28_evt_id - 0 - 8 - read-write - - - - - CH28_TASK_ID - Channel28 task id register - 0xFC - 0x20 - - - CH28_TASK_ID - Configures ch28_task_id - 0 - 8 - read-write - - - - - CH29_EVT_ID - Channel29 event id register - 0x100 - 0x20 - - - CH29_EVT_ID - Configures ch29_evt_id - 0 - 8 - read-write - - - - - CH29_TASK_ID - Channel29 task id register - 0x104 - 0x20 - - - CH29_TASK_ID - Configures ch29_task_id - 0 - 8 - read-write - - - - - CH30_EVT_ID - Channel30 event id register - 0x108 - 0x20 - - - CH30_EVT_ID - Configures ch30_evt_id - 0 - 8 - read-write - - - - - CH30_TASK_ID - Channel30 task id register - 0x10C - 0x20 - - - CH30_TASK_ID - Configures ch30_task_id - 0 - 8 - read-write - - - - - CH31_EVT_ID - Channel31 event id register - 0x110 - 0x20 - - - CH31_EVT_ID - Configures ch31_evt_id - 0 - 8 - read-write - - - - - CH31_TASK_ID - Channel31 task id register - 0x114 - 0x20 - - - CH31_TASK_ID - Configures ch31_task_id - 0 - 8 - read-write - - - - - CH32_EVT_ID - Channel32 event id register - 0x118 - 0x20 - - - CH32_EVT_ID - Configures ch32_evt_id - 0 - 8 - read-write - - - - - CH32_TASK_ID - Channel32 task id register - 0x11C - 0x20 - - - CH32_TASK_ID - Configures ch32_task_id - 0 - 8 - read-write - - - - - CH33_EVT_ID - Channel33 event id register - 0x120 - 0x20 - - - CH33_EVT_ID - Configures ch33_evt_id - 0 - 8 - read-write - - - - - CH33_TASK_ID - Channel33 task id register - 0x124 - 0x20 - - - CH33_TASK_ID - Configures ch33_task_id - 0 - 8 - read-write - - - - - CH34_EVT_ID - Channel34 event id register - 0x128 - 0x20 - - - CH34_EVT_ID - Configures ch34_evt_id - 0 - 8 - read-write - - - - - CH34_TASK_ID - Channel34 task id register - 0x12C - 0x20 - - - CH34_TASK_ID - Configures ch34_task_id - 0 - 8 - read-write - - - - - CH35_EVT_ID - Channel35 event id register - 0x130 - 0x20 - - - CH35_EVT_ID - Configures ch35_evt_id - 0 - 8 - read-write - - - - - CH35_TASK_ID - Channel35 task id register - 0x134 - 0x20 - - - CH35_TASK_ID - Configures ch35_task_id - 0 - 8 - read-write - - - - - CH36_EVT_ID - Channel36 event id register - 0x138 - 0x20 - - - CH36_EVT_ID - Configures ch36_evt_id - 0 - 8 - read-write - - - - - CH36_TASK_ID - Channel36 task id register - 0x13C - 0x20 - - - CH36_TASK_ID - Configures ch36_task_id - 0 - 8 - read-write - - - - - CH37_EVT_ID - Channel37 event id register - 0x140 - 0x20 - - - CH37_EVT_ID - Configures ch37_evt_id - 0 - 8 - read-write - - - - - CH37_TASK_ID - Channel37 task id register - 0x144 - 0x20 - - - CH37_TASK_ID - Configures ch37_task_id - 0 - 8 - read-write - - - - - CH38_EVT_ID - Channel38 event id register - 0x148 - 0x20 - - - CH38_EVT_ID - Configures ch38_evt_id - 0 - 8 - read-write - - - - - CH38_TASK_ID - Channel38 task id register - 0x14C - 0x20 - - - CH38_TASK_ID - Configures ch38_task_id - 0 - 8 - read-write - - - - - CH39_EVT_ID - Channel39 event id register - 0x150 - 0x20 - - - CH39_EVT_ID - Configures ch39_evt_id - 0 - 8 - read-write - - - - - CH39_TASK_ID - Channel39 task id register - 0x154 - 0x20 - - - CH39_TASK_ID - Configures ch39_task_id - 0 - 8 - read-write - - - - - CH40_EVT_ID - Channel40 event id register - 0x158 - 0x20 - - - CH40_EVT_ID - Configures ch40_evt_id - 0 - 8 - read-write - - - - - CH40_TASK_ID - Channel40 task id register - 0x15C - 0x20 - - - CH40_TASK_ID - Configures ch40_task_id - 0 - 8 - read-write - - - - - CH41_EVT_ID - Channel41 event id register - 0x160 - 0x20 - - - CH41_EVT_ID - Configures ch41_evt_id - 0 - 8 - read-write - - - - - CH41_TASK_ID - Channel41 task id register - 0x164 - 0x20 - - - CH41_TASK_ID - Configures ch41_task_id - 0 - 8 - read-write - - - - - CH42_EVT_ID - Channel42 event id register - 0x168 - 0x20 - - - CH42_EVT_ID - Configures ch42_evt_id - 0 - 8 - read-write - - - - - CH42_TASK_ID - Channel42 task id register - 0x16C - 0x20 - - - CH42_TASK_ID - Configures ch42_task_id - 0 - 8 - read-write - - - - - CH43_EVT_ID - Channel43 event id register - 0x170 - 0x20 - - - CH43_EVT_ID - Configures ch43_evt_id - 0 - 8 - read-write - - - - - CH43_TASK_ID - Channel43 task id register - 0x174 - 0x20 - - - CH43_TASK_ID - Configures ch43_task_id - 0 - 8 - read-write - - - - - CH44_EVT_ID - Channel44 event id register - 0x178 - 0x20 - - - CH44_EVT_ID - Configures ch44_evt_id - 0 - 8 - read-write - - - - - CH44_TASK_ID - Channel44 task id register - 0x17C - 0x20 - - - CH44_TASK_ID - Configures ch44_task_id - 0 - 8 - read-write - - - - - CH45_EVT_ID - Channel45 event id register - 0x180 - 0x20 - - - CH45_EVT_ID - Configures ch45_evt_id - 0 - 8 - read-write - - - - - CH45_TASK_ID - Channel45 task id register - 0x184 - 0x20 - - - CH45_TASK_ID - Configures ch45_task_id - 0 - 8 - read-write - - - - - CH46_EVT_ID - Channel46 event id register - 0x188 - 0x20 - - - CH46_EVT_ID - Configures ch46_evt_id - 0 - 8 - read-write - - - - - CH46_TASK_ID - Channel46 task id register - 0x18C - 0x20 - - - CH46_TASK_ID - Configures ch46_task_id - 0 - 8 - read-write - - - - - CH47_EVT_ID - Channel47 event id register - 0x190 - 0x20 - - - CH47_EVT_ID - Configures ch47_evt_id - 0 - 8 - read-write - - - - - CH47_TASK_ID - Channel47 task id register - 0x194 - 0x20 - - - CH47_TASK_ID - Configures ch47_task_id - 0 - 8 - read-write - - - - - CH48_EVT_ID - Channel48 event id register - 0x198 - 0x20 - - - CH48_EVT_ID - Configures ch48_evt_id - 0 - 8 - read-write - - - - - CH48_TASK_ID - Channel48 task id register - 0x19C - 0x20 - - - CH48_TASK_ID - Configures ch48_task_id - 0 - 8 - read-write - - - - - CH49_EVT_ID - Channel49 event id register - 0x1A0 - 0x20 - - - CH49_EVT_ID - Configures ch49_evt_id - 0 - 8 - read-write - - - - - CH49_TASK_ID - Channel49 task id register - 0x1A4 - 0x20 - - - CH49_TASK_ID - Configures ch49_task_id - 0 - 8 - read-write - - - - - EVT_ST0 - Events trigger status register - 0x1A8 - 0x20 - - - GPIO_EVT_CH0_RISE_EDGE_ST - Represents GPIO_evt_ch0_rise_edge trigger status.\\0: Not triggered\\1: Triggered - 0 - 1 - read-write - - - GPIO_EVT_CH1_RISE_EDGE_ST - Represents GPIO_evt_ch1_rise_edge trigger status.\\0: Not triggered\\1: Triggered - 1 - 1 - read-write - - - GPIO_EVT_CH2_RISE_EDGE_ST - Represents GPIO_evt_ch2_rise_edge trigger status.\\0: Not triggered\\1: Triggered - 2 - 1 - read-write - - - GPIO_EVT_CH3_RISE_EDGE_ST - Represents GPIO_evt_ch3_rise_edge trigger status.\\0: Not triggered\\1: Triggered - 3 - 1 - read-write - - - GPIO_EVT_CH4_RISE_EDGE_ST - Represents GPIO_evt_ch4_rise_edge trigger status.\\0: Not triggered\\1: Triggered - 4 - 1 - read-write - - - GPIO_EVT_CH5_RISE_EDGE_ST - Represents GPIO_evt_ch5_rise_edge trigger status.\\0: Not triggered\\1: Triggered - 5 - 1 - read-write - - - GPIO_EVT_CH6_RISE_EDGE_ST - Represents GPIO_evt_ch6_rise_edge trigger status.\\0: Not triggered\\1: Triggered - 6 - 1 - read-write - - - GPIO_EVT_CH7_RISE_EDGE_ST - Represents GPIO_evt_ch7_rise_edge trigger status.\\0: Not triggered\\1: Triggered - 7 - 1 - read-write - - - GPIO_EVT_CH0_FALL_EDGE_ST - Represents GPIO_evt_ch0_fall_edge trigger status.\\0: Not triggered\\1: Triggered - 8 - 1 - read-write - - - GPIO_EVT_CH1_FALL_EDGE_ST - Represents GPIO_evt_ch1_fall_edge trigger status.\\0: Not triggered\\1: Triggered - 9 - 1 - read-write - - - GPIO_EVT_CH2_FALL_EDGE_ST - Represents GPIO_evt_ch2_fall_edge trigger status.\\0: Not triggered\\1: Triggered - 10 - 1 - read-write - - - GPIO_EVT_CH3_FALL_EDGE_ST - Represents GPIO_evt_ch3_fall_edge trigger status.\\0: Not triggered\\1: Triggered - 11 - 1 - read-write - - - GPIO_EVT_CH4_FALL_EDGE_ST - Represents GPIO_evt_ch4_fall_edge trigger status.\\0: Not triggered\\1: Triggered - 12 - 1 - read-write - - - GPIO_EVT_CH5_FALL_EDGE_ST - Represents GPIO_evt_ch5_fall_edge trigger status.\\0: Not triggered\\1: Triggered - 13 - 1 - read-write - - - GPIO_EVT_CH6_FALL_EDGE_ST - Represents GPIO_evt_ch6_fall_edge trigger status.\\0: Not triggered\\1: Triggered - 14 - 1 - read-write - - - GPIO_EVT_CH7_FALL_EDGE_ST - Represents GPIO_evt_ch7_fall_edge trigger status.\\0: Not triggered\\1: Triggered - 15 - 1 - read-write - - - GPIO_EVT_CH0_ANY_EDGE_ST - Represents GPIO_evt_ch0_any_edge trigger status.\\0: Not triggered\\1: Triggered - 16 - 1 - read-write - - - GPIO_EVT_CH1_ANY_EDGE_ST - Represents GPIO_evt_ch1_any_edge trigger status.\\0: Not triggered\\1: Triggered - 17 - 1 - read-write - - - GPIO_EVT_CH2_ANY_EDGE_ST - Represents GPIO_evt_ch2_any_edge trigger status.\\0: Not triggered\\1: Triggered - 18 - 1 - read-write - - - GPIO_EVT_CH3_ANY_EDGE_ST - Represents GPIO_evt_ch3_any_edge trigger status.\\0: Not triggered\\1: Triggered - 19 - 1 - read-write - - - GPIO_EVT_CH4_ANY_EDGE_ST - Represents GPIO_evt_ch4_any_edge trigger status.\\0: Not triggered\\1: Triggered - 20 - 1 - read-write - - - GPIO_EVT_CH5_ANY_EDGE_ST - Represents GPIO_evt_ch5_any_edge trigger status.\\0: Not triggered\\1: Triggered - 21 - 1 - read-write - - - GPIO_EVT_CH6_ANY_EDGE_ST - Represents GPIO_evt_ch6_any_edge trigger status.\\0: Not triggered\\1: Triggered - 22 - 1 - read-write - - - GPIO_EVT_CH7_ANY_EDGE_ST - Represents GPIO_evt_ch7_any_edge trigger status.\\0: Not triggered\\1: Triggered - 23 - 1 - read-write - - - GPIO_EVT_ZERO_DET_POS0_ST - Represents GPIO_evt_zero_det_pos0 trigger status.\\0: Not triggered\\1: Triggered - 24 - 1 - read-write - - - GPIO_EVT_ZERO_DET_NEG0_ST - Represents GPIO_evt_zero_det_neg0 trigger status.\\0: Not triggered\\1: Triggered - 25 - 1 - read-write - - - GPIO_EVT_ZERO_DET_POS1_ST - Represents GPIO_evt_zero_det_pos1 trigger status.\\0: Not triggered\\1: Triggered - 26 - 1 - read-write - - - GPIO_EVT_ZERO_DET_NEG1_ST - Represents GPIO_evt_zero_det_neg1 trigger status.\\0: Not triggered\\1: Triggered - 27 - 1 - read-write - - - LEDC_EVT_DUTY_CHNG_END_CH0_ST - Represents LEDC_evt_duty_chng_end_ch0 trigger status.\\0: Not triggered\\1: Triggered - 28 - 1 - read-write - - - LEDC_EVT_DUTY_CHNG_END_CH1_ST - Represents LEDC_evt_duty_chng_end_ch1 trigger status.\\0: Not triggered\\1: Triggered - 29 - 1 - read-write - - - LEDC_EVT_DUTY_CHNG_END_CH2_ST - Represents LEDC_evt_duty_chng_end_ch2 trigger status.\\0: Not triggered\\1: Triggered - 30 - 1 - read-write - - - LEDC_EVT_DUTY_CHNG_END_CH3_ST - Represents LEDC_evt_duty_chng_end_ch3 trigger status.\\0: Not triggered\\1: Triggered - 31 - 1 - read-write - - - - - EVT_ST0_CLR - Events trigger status clear register - 0x1AC - 0x20 - - - GPIO_EVT_CH0_RISE_EDGE_ST_CLR - Configures whether or not to clear GPIO_evt_ch0_rise_edge trigger status.\\0: Invalid, No effect\\1: Clear - 0 - 1 - write-only - - - GPIO_EVT_CH1_RISE_EDGE_ST_CLR - Configures whether or not to clear GPIO_evt_ch1_rise_edge trigger status.\\0: Invalid, No effect\\1: Clear - 1 - 1 - write-only - - - GPIO_EVT_CH2_RISE_EDGE_ST_CLR - Configures whether or not to clear GPIO_evt_ch2_rise_edge trigger status.\\0: Invalid, No effect\\1: Clear - 2 - 1 - write-only - - - GPIO_EVT_CH3_RISE_EDGE_ST_CLR - Configures whether or not to clear GPIO_evt_ch3_rise_edge trigger status.\\0: Invalid, No effect\\1: Clear - 3 - 1 - write-only - - - GPIO_EVT_CH4_RISE_EDGE_ST_CLR - Configures whether or not to clear GPIO_evt_ch4_rise_edge trigger status.\\0: Invalid, No effect\\1: Clear - 4 - 1 - write-only - - - GPIO_EVT_CH5_RISE_EDGE_ST_CLR - Configures whether or not to clear GPIO_evt_ch5_rise_edge trigger status.\\0: Invalid, No effect\\1: Clear - 5 - 1 - write-only - - - GPIO_EVT_CH6_RISE_EDGE_ST_CLR - Configures whether or not to clear GPIO_evt_ch6_rise_edge trigger status.\\0: Invalid, No effect\\1: Clear - 6 - 1 - write-only - - - GPIO_EVT_CH7_RISE_EDGE_ST_CLR - Configures whether or not to clear GPIO_evt_ch7_rise_edge trigger status.\\0: Invalid, No effect\\1: Clear - 7 - 1 - write-only - - - GPIO_EVT_CH0_FALL_EDGE_ST_CLR - Configures whether or not to clear GPIO_evt_ch0_fall_edge trigger status.\\0: Invalid, No effect\\1: Clear - 8 - 1 - write-only - - - GPIO_EVT_CH1_FALL_EDGE_ST_CLR - Configures whether or not to clear GPIO_evt_ch1_fall_edge trigger status.\\0: Invalid, No effect\\1: Clear - 9 - 1 - write-only - - - GPIO_EVT_CH2_FALL_EDGE_ST_CLR - Configures whether or not to clear GPIO_evt_ch2_fall_edge trigger status.\\0: Invalid, No effect\\1: Clear - 10 - 1 - write-only - - - GPIO_EVT_CH3_FALL_EDGE_ST_CLR - Configures whether or not to clear GPIO_evt_ch3_fall_edge trigger status.\\0: Invalid, No effect\\1: Clear - 11 - 1 - write-only - - - GPIO_EVT_CH4_FALL_EDGE_ST_CLR - Configures whether or not to clear GPIO_evt_ch4_fall_edge trigger status.\\0: Invalid, No effect\\1: Clear - 12 - 1 - write-only - - - GPIO_EVT_CH5_FALL_EDGE_ST_CLR - Configures whether or not to clear GPIO_evt_ch5_fall_edge trigger status.\\0: Invalid, No effect\\1: Clear - 13 - 1 - write-only - - - GPIO_EVT_CH6_FALL_EDGE_ST_CLR - Configures whether or not to clear GPIO_evt_ch6_fall_edge trigger status.\\0: Invalid, No effect\\1: Clear - 14 - 1 - write-only - - - GPIO_EVT_CH7_FALL_EDGE_ST_CLR - Configures whether or not to clear GPIO_evt_ch7_fall_edge trigger status.\\0: Invalid, No effect\\1: Clear - 15 - 1 - write-only - - - GPIO_EVT_CH0_ANY_EDGE_ST_CLR - Configures whether or not to clear GPIO_evt_ch0_any_edge trigger status.\\0: Invalid, No effect\\1: Clear - 16 - 1 - write-only - - - GPIO_EVT_CH1_ANY_EDGE_ST_CLR - Configures whether or not to clear GPIO_evt_ch1_any_edge trigger status.\\0: Invalid, No effect\\1: Clear - 17 - 1 - write-only - - - GPIO_EVT_CH2_ANY_EDGE_ST_CLR - Configures whether or not to clear GPIO_evt_ch2_any_edge trigger status.\\0: Invalid, No effect\\1: Clear - 18 - 1 - write-only - - - GPIO_EVT_CH3_ANY_EDGE_ST_CLR - Configures whether or not to clear GPIO_evt_ch3_any_edge trigger status.\\0: Invalid, No effect\\1: Clear - 19 - 1 - write-only - - - GPIO_EVT_CH4_ANY_EDGE_ST_CLR - Configures whether or not to clear GPIO_evt_ch4_any_edge trigger status.\\0: Invalid, No effect\\1: Clear - 20 - 1 - write-only - - - GPIO_EVT_CH5_ANY_EDGE_ST_CLR - Configures whether or not to clear GPIO_evt_ch5_any_edge trigger status.\\0: Invalid, No effect\\1: Clear - 21 - 1 - write-only - - - GPIO_EVT_CH6_ANY_EDGE_ST_CLR - Configures whether or not to clear GPIO_evt_ch6_any_edge trigger status.\\0: Invalid, No effect\\1: Clear - 22 - 1 - write-only - - - GPIO_EVT_CH7_ANY_EDGE_ST_CLR - Configures whether or not to clear GPIO_evt_ch7_any_edge trigger status.\\0: Invalid, No effect\\1: Clear - 23 - 1 - write-only - - - GPIO_EVT_ZERO_DET_POS0_ST_CLR - Configures whether or not to clear GPIO_evt_zero_det_pos0 trigger status.\\0: Invalid, No effect\\1: Clear - 24 - 1 - write-only - - - GPIO_EVT_ZERO_DET_NEG0_ST_CLR - Configures whether or not to clear GPIO_evt_zero_det_neg0 trigger status.\\0: Invalid, No effect\\1: Clear - 25 - 1 - write-only - - - GPIO_EVT_ZERO_DET_POS1_ST_CLR - Configures whether or not to clear GPIO_evt_zero_det_pos1 trigger status.\\0: Invalid, No effect\\1: Clear - 26 - 1 - write-only - - - GPIO_EVT_ZERO_DET_NEG1_ST_CLR - Configures whether or not to clear GPIO_evt_zero_det_neg1 trigger status.\\0: Invalid, No effect\\1: Clear - 27 - 1 - write-only - - - LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR - Configures whether or not to clear LEDC_evt_duty_chng_end_ch0 trigger status.\\0: Invalid, No effect\\1: Clear - 28 - 1 - write-only - - - LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR - Configures whether or not to clear LEDC_evt_duty_chng_end_ch1 trigger status.\\0: Invalid, No effect\\1: Clear - 29 - 1 - write-only - - - LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR - Configures whether or not to clear LEDC_evt_duty_chng_end_ch2 trigger status.\\0: Invalid, No effect\\1: Clear - 30 - 1 - write-only - - - LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR - Configures whether or not to clear LEDC_evt_duty_chng_end_ch3 trigger status.\\0: Invalid, No effect\\1: Clear - 31 - 1 - write-only - - - - - EVT_ST1 - Events trigger status register - 0x1B0 - 0x20 - - - LEDC_EVT_DUTY_CHNG_END_CH4_ST - Represents LEDC_evt_duty_chng_end_ch4 trigger status.\\0: Not triggered\\1: Triggered - 0 - 1 - read-write - - - LEDC_EVT_DUTY_CHNG_END_CH5_ST - Represents LEDC_evt_duty_chng_end_ch5 trigger status.\\0: Not triggered\\1: Triggered - 1 - 1 - read-write - - - LEDC_EVT_DUTY_CHNG_END_CH6_ST - Represents LEDC_evt_duty_chng_end_ch6 trigger status.\\0: Not triggered\\1: Triggered - 2 - 1 - read-write - - - LEDC_EVT_DUTY_CHNG_END_CH7_ST - Represents LEDC_evt_duty_chng_end_ch7 trigger status.\\0: Not triggered\\1: Triggered - 3 - 1 - read-write - - - LEDC_EVT_OVF_CNT_PLS_CH0_ST - Represents LEDC_evt_ovf_cnt_pls_ch0 trigger status.\\0: Not triggered\\1: Triggered - 4 - 1 - read-write - - - LEDC_EVT_OVF_CNT_PLS_CH1_ST - Represents LEDC_evt_ovf_cnt_pls_ch1 trigger status.\\0: Not triggered\\1: Triggered - 5 - 1 - read-write - - - LEDC_EVT_OVF_CNT_PLS_CH2_ST - Represents LEDC_evt_ovf_cnt_pls_ch2 trigger status.\\0: Not triggered\\1: Triggered - 6 - 1 - read-write - - - LEDC_EVT_OVF_CNT_PLS_CH3_ST - Represents LEDC_evt_ovf_cnt_pls_ch3 trigger status.\\0: Not triggered\\1: Triggered - 7 - 1 - read-write - - - LEDC_EVT_OVF_CNT_PLS_CH4_ST - Represents LEDC_evt_ovf_cnt_pls_ch4 trigger status.\\0: Not triggered\\1: Triggered - 8 - 1 - read-write - - - LEDC_EVT_OVF_CNT_PLS_CH5_ST - Represents LEDC_evt_ovf_cnt_pls_ch5 trigger status.\\0: Not triggered\\1: Triggered - 9 - 1 - read-write - - - LEDC_EVT_OVF_CNT_PLS_CH6_ST - Represents LEDC_evt_ovf_cnt_pls_ch6 trigger status.\\0: Not triggered\\1: Triggered - 10 - 1 - read-write - - - LEDC_EVT_OVF_CNT_PLS_CH7_ST - Represents LEDC_evt_ovf_cnt_pls_ch7 trigger status.\\0: Not triggered\\1: Triggered - 11 - 1 - read-write - - - LEDC_EVT_TIME_OVF_TIMER0_ST - Represents LEDC_evt_time_ovf_timer0 trigger status.\\0: Not triggered\\1: Triggered - 12 - 1 - read-write - - - LEDC_EVT_TIME_OVF_TIMER1_ST - Represents LEDC_evt_time_ovf_timer1 trigger status.\\0: Not triggered\\1: Triggered - 13 - 1 - read-write - - - LEDC_EVT_TIME_OVF_TIMER2_ST - Represents LEDC_evt_time_ovf_timer2 trigger status.\\0: Not triggered\\1: Triggered - 14 - 1 - read-write - - - LEDC_EVT_TIME_OVF_TIMER3_ST - Represents LEDC_evt_time_ovf_timer3 trigger status.\\0: Not triggered\\1: Triggered - 15 - 1 - read-write - - - LEDC_EVT_TIMER0_CMP_ST - Represents LEDC_evt_timer0_cmp trigger status.\\0: Not triggered\\1: Triggered - 16 - 1 - read-write - - - LEDC_EVT_TIMER1_CMP_ST - Represents LEDC_evt_timer1_cmp trigger status.\\0: Not triggered\\1: Triggered - 17 - 1 - read-write - - - LEDC_EVT_TIMER2_CMP_ST - Represents LEDC_evt_timer2_cmp trigger status.\\0: Not triggered\\1: Triggered - 18 - 1 - read-write - - - LEDC_EVT_TIMER3_CMP_ST - Represents LEDC_evt_timer3_cmp trigger status.\\0: Not triggered\\1: Triggered - 19 - 1 - read-write - - - TG0_EVT_CNT_CMP_TIMER0_ST - Represents TG0_evt_cnt_cmp_timer0 trigger status.\\0: Not triggered\\1: Triggered - 20 - 1 - read-write - - - TG0_EVT_CNT_CMP_TIMER1_ST - Represents TG0_evt_cnt_cmp_timer1 trigger status.\\0: Not triggered\\1: Triggered - 21 - 1 - read-write - - - TG1_EVT_CNT_CMP_TIMER0_ST - Represents TG1_evt_cnt_cmp_timer0 trigger status.\\0: Not triggered\\1: Triggered - 22 - 1 - read-write - - - TG1_EVT_CNT_CMP_TIMER1_ST - Represents TG1_evt_cnt_cmp_timer1 trigger status.\\0: Not triggered\\1: Triggered - 23 - 1 - read-write - - - SYSTIMER_EVT_CNT_CMP0_ST - Represents SYSTIMER_evt_cnt_cmp0 trigger status.\\0: Not triggered\\1: Triggered - 24 - 1 - read-write - - - SYSTIMER_EVT_CNT_CMP1_ST - Represents SYSTIMER_evt_cnt_cmp1 trigger status.\\0: Not triggered\\1: Triggered - 25 - 1 - read-write - - - SYSTIMER_EVT_CNT_CMP2_ST - Represents SYSTIMER_evt_cnt_cmp2 trigger status.\\0: Not triggered\\1: Triggered - 26 - 1 - read-write - - - MCPWM0_EVT_TIMER0_STOP_ST - Represents MCPWM0_evt_timer0_stop trigger status.\\0: Not triggered\\1: Triggered - 27 - 1 - read-write - - - MCPWM0_EVT_TIMER1_STOP_ST - Represents MCPWM0_evt_timer1_stop trigger status.\\0: Not triggered\\1: Triggered - 28 - 1 - read-write - - - MCPWM0_EVT_TIMER2_STOP_ST - Represents MCPWM0_evt_timer2_stop trigger status.\\0: Not triggered\\1: Triggered - 29 - 1 - read-write - - - MCPWM0_EVT_TIMER0_TEZ_ST - Represents MCPWM0_evt_timer0_tez trigger status.\\0: Not triggered\\1: Triggered - 30 - 1 - read-write - - - MCPWM0_EVT_TIMER1_TEZ_ST - Represents MCPWM0_evt_timer1_tez trigger status.\\0: Not triggered\\1: Triggered - 31 - 1 - read-write - - - - - EVT_ST1_CLR - Events trigger status clear register - 0x1B4 - 0x20 - - - LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR - Configures whether or not to clear LEDC_evt_duty_chng_end_ch4 trigger status.\\0: Invalid, No effect\\1: Clear - 0 - 1 - write-only - - - LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR - Configures whether or not to clear LEDC_evt_duty_chng_end_ch5 trigger status.\\0: Invalid, No effect\\1: Clear - 1 - 1 - write-only - - - LEDC_EVT_DUTY_CHNG_END_CH6_ST_CLR - Configures whether or not to clear LEDC_evt_duty_chng_end_ch6 trigger status.\\0: Invalid, No effect\\1: Clear - 2 - 1 - write-only - - - LEDC_EVT_DUTY_CHNG_END_CH7_ST_CLR - Configures whether or not to clear LEDC_evt_duty_chng_end_ch7 trigger status.\\0: Invalid, No effect\\1: Clear - 3 - 1 - write-only - - - LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR - Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch0 trigger status.\\0: Invalid, No effect\\1: Clear - 4 - 1 - write-only - - - LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR - Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch1 trigger status.\\0: Invalid, No effect\\1: Clear - 5 - 1 - write-only - - - LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR - Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch2 trigger status.\\0: Invalid, No effect\\1: Clear - 6 - 1 - write-only - - - LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR - Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch3 trigger status.\\0: Invalid, No effect\\1: Clear - 7 - 1 - write-only - - - LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR - Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch4 trigger status.\\0: Invalid, No effect\\1: Clear - 8 - 1 - write-only - - - LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR - Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch5 trigger status.\\0: Invalid, No effect\\1: Clear - 9 - 1 - write-only - - - LEDC_EVT_OVF_CNT_PLS_CH6_ST_CLR - Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch6 trigger status.\\0: Invalid, No effect\\1: Clear - 10 - 1 - write-only - - - LEDC_EVT_OVF_CNT_PLS_CH7_ST_CLR - Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch7 trigger status.\\0: Invalid, No effect\\1: Clear - 11 - 1 - write-only - - - LEDC_EVT_TIME_OVF_TIMER0_ST_CLR - Configures whether or not to clear LEDC_evt_time_ovf_timer0 trigger status.\\0: Invalid, No effect\\1: Clear - 12 - 1 - write-only - - - LEDC_EVT_TIME_OVF_TIMER1_ST_CLR - Configures whether or not to clear LEDC_evt_time_ovf_timer1 trigger status.\\0: Invalid, No effect\\1: Clear - 13 - 1 - write-only - - - LEDC_EVT_TIME_OVF_TIMER2_ST_CLR - Configures whether or not to clear LEDC_evt_time_ovf_timer2 trigger status.\\0: Invalid, No effect\\1: Clear - 14 - 1 - write-only - - - LEDC_EVT_TIME_OVF_TIMER3_ST_CLR - Configures whether or not to clear LEDC_evt_time_ovf_timer3 trigger status.\\0: Invalid, No effect\\1: Clear - 15 - 1 - write-only - - - LEDC_EVT_TIMER0_CMP_ST_CLR - Configures whether or not to clear LEDC_evt_timer0_cmp trigger status.\\0: Invalid, No effect\\1: Clear - 16 - 1 - write-only - - - LEDC_EVT_TIMER1_CMP_ST_CLR - Configures whether or not to clear LEDC_evt_timer1_cmp trigger status.\\0: Invalid, No effect\\1: Clear - 17 - 1 - write-only - - - LEDC_EVT_TIMER2_CMP_ST_CLR - Configures whether or not to clear LEDC_evt_timer2_cmp trigger status.\\0: Invalid, No effect\\1: Clear - 18 - 1 - write-only - - - LEDC_EVT_TIMER3_CMP_ST_CLR - Configures whether or not to clear LEDC_evt_timer3_cmp trigger status.\\0: Invalid, No effect\\1: Clear - 19 - 1 - write-only - - - TG0_EVT_CNT_CMP_TIMER0_ST_CLR - Configures whether or not to clear TG0_evt_cnt_cmp_timer0 trigger status.\\0: Invalid, No effect\\1: Clear - 20 - 1 - write-only - - - TG0_EVT_CNT_CMP_TIMER1_ST_CLR - Configures whether or not to clear TG0_evt_cnt_cmp_timer1 trigger status.\\0: Invalid, No effect\\1: Clear - 21 - 1 - write-only - - - TG1_EVT_CNT_CMP_TIMER0_ST_CLR - Configures whether or not to clear TG1_evt_cnt_cmp_timer0 trigger status.\\0: Invalid, No effect\\1: Clear - 22 - 1 - write-only - - - TG1_EVT_CNT_CMP_TIMER1_ST_CLR - Configures whether or not to clear TG1_evt_cnt_cmp_timer1 trigger status.\\0: Invalid, No effect\\1: Clear - 23 - 1 - write-only - - - SYSTIMER_EVT_CNT_CMP0_ST_CLR - Configures whether or not to clear SYSTIMER_evt_cnt_cmp0 trigger status.\\0: Invalid, No effect\\1: Clear - 24 - 1 - write-only - - - SYSTIMER_EVT_CNT_CMP1_ST_CLR - Configures whether or not to clear SYSTIMER_evt_cnt_cmp1 trigger status.\\0: Invalid, No effect\\1: Clear - 25 - 1 - write-only - - - SYSTIMER_EVT_CNT_CMP2_ST_CLR - Configures whether or not to clear SYSTIMER_evt_cnt_cmp2 trigger status.\\0: Invalid, No effect\\1: Clear - 26 - 1 - write-only - - - MCPWM0_EVT_TIMER0_STOP_ST_CLR - Configures whether or not to clear MCPWM0_evt_timer0_stop trigger status.\\0: Invalid, No effect\\1: Clear - 27 - 1 - write-only - - - MCPWM0_EVT_TIMER1_STOP_ST_CLR - Configures whether or not to clear MCPWM0_evt_timer1_stop trigger status.\\0: Invalid, No effect\\1: Clear - 28 - 1 - write-only - - - MCPWM0_EVT_TIMER2_STOP_ST_CLR - Configures whether or not to clear MCPWM0_evt_timer2_stop trigger status.\\0: Invalid, No effect\\1: Clear - 29 - 1 - write-only - - - MCPWM0_EVT_TIMER0_TEZ_ST_CLR - Configures whether or not to clear MCPWM0_evt_timer0_tez trigger status.\\0: Invalid, No effect\\1: Clear - 30 - 1 - write-only - - - MCPWM0_EVT_TIMER1_TEZ_ST_CLR - Configures whether or not to clear MCPWM0_evt_timer1_tez trigger status.\\0: Invalid, No effect\\1: Clear - 31 - 1 - write-only - - - - - EVT_ST2 - Events trigger status register - 0x1B8 - 0x20 - - - MCPWM0_EVT_TIMER2_TEZ_ST - Represents MCPWM0_evt_timer2_tez trigger status.\\0: Not triggered\\1: Triggered - 0 - 1 - read-write - - - MCPWM0_EVT_TIMER0_TEP_ST - Represents MCPWM0_evt_timer0_tep trigger status.\\0: Not triggered\\1: Triggered - 1 - 1 - read-write - - - MCPWM0_EVT_TIMER1_TEP_ST - Represents MCPWM0_evt_timer1_tep trigger status.\\0: Not triggered\\1: Triggered - 2 - 1 - read-write - - - MCPWM0_EVT_TIMER2_TEP_ST - Represents MCPWM0_evt_timer2_tep trigger status.\\0: Not triggered\\1: Triggered - 3 - 1 - read-write - - - MCPWM0_EVT_OP0_TEA_ST - Represents MCPWM0_evt_op0_tea trigger status.\\0: Not triggered\\1: Triggered - 4 - 1 - read-write - - - MCPWM0_EVT_OP1_TEA_ST - Represents MCPWM0_evt_op1_tea trigger status.\\0: Not triggered\\1: Triggered - 5 - 1 - read-write - - - MCPWM0_EVT_OP2_TEA_ST - Represents MCPWM0_evt_op2_tea trigger status.\\0: Not triggered\\1: Triggered - 6 - 1 - read-write - - - MCPWM0_EVT_OP0_TEB_ST - Represents MCPWM0_evt_op0_teb trigger status.\\0: Not triggered\\1: Triggered - 7 - 1 - read-write - - - MCPWM0_EVT_OP1_TEB_ST - Represents MCPWM0_evt_op1_teb trigger status.\\0: Not triggered\\1: Triggered - 8 - 1 - read-write - - - MCPWM0_EVT_OP2_TEB_ST - Represents MCPWM0_evt_op2_teb trigger status.\\0: Not triggered\\1: Triggered - 9 - 1 - read-write - - - MCPWM0_EVT_F0_ST - Represents MCPWM0_evt_f0 trigger status.\\0: Not triggered\\1: Triggered - 10 - 1 - read-write - - - MCPWM0_EVT_F1_ST - Represents MCPWM0_evt_f1 trigger status.\\0: Not triggered\\1: Triggered - 11 - 1 - read-write - - - MCPWM0_EVT_F2_ST - Represents MCPWM0_evt_f2 trigger status.\\0: Not triggered\\1: Triggered - 12 - 1 - read-write - - - MCPWM0_EVT_F0_CLR_ST - Represents MCPWM0_evt_f0_clr trigger status.\\0: Not triggered\\1: Triggered - 13 - 1 - read-write - - - MCPWM0_EVT_F1_CLR_ST - Represents MCPWM0_evt_f1_clr trigger status.\\0: Not triggered\\1: Triggered - 14 - 1 - read-write - - - MCPWM0_EVT_F2_CLR_ST - Represents MCPWM0_evt_f2_clr trigger status.\\0: Not triggered\\1: Triggered - 15 - 1 - read-write - - - MCPWM0_EVT_TZ0_CBC_ST - Represents MCPWM0_evt_tz0_cbc trigger status.\\0: Not triggered\\1: Triggered - 16 - 1 - read-write - - - MCPWM0_EVT_TZ1_CBC_ST - Represents MCPWM0_evt_tz1_cbc trigger status.\\0: Not triggered\\1: Triggered - 17 - 1 - read-write - - - MCPWM0_EVT_TZ2_CBC_ST - Represents MCPWM0_evt_tz2_cbc trigger status.\\0: Not triggered\\1: Triggered - 18 - 1 - read-write - - - MCPWM0_EVT_TZ0_OST_ST - Represents MCPWM0_evt_tz0_ost trigger status.\\0: Not triggered\\1: Triggered - 19 - 1 - read-write - - - MCPWM0_EVT_TZ1_OST_ST - Represents MCPWM0_evt_tz1_ost trigger status.\\0: Not triggered\\1: Triggered - 20 - 1 - read-write - - - MCPWM0_EVT_TZ2_OST_ST - Represents MCPWM0_evt_tz2_ost trigger status.\\0: Not triggered\\1: Triggered - 21 - 1 - read-write - - - MCPWM0_EVT_CAP0_ST - Represents MCPWM0_evt_cap0 trigger status.\\0: Not triggered\\1: Triggered - 22 - 1 - read-write - - - MCPWM0_EVT_CAP1_ST - Represents MCPWM0_evt_cap1 trigger status.\\0: Not triggered\\1: Triggered - 23 - 1 - read-write - - - MCPWM0_EVT_CAP2_ST - Represents MCPWM0_evt_cap2 trigger status.\\0: Not triggered\\1: Triggered - 24 - 1 - read-write - - - MCPWM0_EVT_OP0_TEE1_ST - Represents MCPWM0_evt_op0_tee1 trigger status.\\0: Not triggered\\1: Triggered - 25 - 1 - read-write - - - MCPWM0_EVT_OP1_TEE1_ST - Represents MCPWM0_evt_op1_tee1 trigger status.\\0: Not triggered\\1: Triggered - 26 - 1 - read-write - - - MCPWM0_EVT_OP2_TEE1_ST - Represents MCPWM0_evt_op2_tee1 trigger status.\\0: Not triggered\\1: Triggered - 27 - 1 - read-write - - - MCPWM0_EVT_OP0_TEE2_ST - Represents MCPWM0_evt_op0_tee2 trigger status.\\0: Not triggered\\1: Triggered - 28 - 1 - read-write - - - MCPWM0_EVT_OP1_TEE2_ST - Represents MCPWM0_evt_op1_tee2 trigger status.\\0: Not triggered\\1: Triggered - 29 - 1 - read-write - - - MCPWM0_EVT_OP2_TEE2_ST - Represents MCPWM0_evt_op2_tee2 trigger status.\\0: Not triggered\\1: Triggered - 30 - 1 - read-write - - - MCPWM1_EVT_TIMER0_STOP_ST - Represents MCPWM1_evt_timer0_stop trigger status.\\0: Not triggered\\1: Triggered - 31 - 1 - read-write - - - - - EVT_ST2_CLR - Events trigger status clear register - 0x1BC - 0x20 - - - MCPWM0_EVT_TIMER2_TEZ_ST_CLR - Configures whether or not to clear MCPWM0_evt_timer2_tez trigger status.\\0: Invalid, No effect\\1: Clear - 0 - 1 - write-only - - - MCPWM0_EVT_TIMER0_TEP_ST_CLR - Configures whether or not to clear MCPWM0_evt_timer0_tep trigger status.\\0: Invalid, No effect\\1: Clear - 1 - 1 - write-only - - - MCPWM0_EVT_TIMER1_TEP_ST_CLR - Configures whether or not to clear MCPWM0_evt_timer1_tep trigger status.\\0: Invalid, No effect\\1: Clear - 2 - 1 - write-only - - - MCPWM0_EVT_TIMER2_TEP_ST_CLR - Configures whether or not to clear MCPWM0_evt_timer2_tep trigger status.\\0: Invalid, No effect\\1: Clear - 3 - 1 - write-only - - - MCPWM0_EVT_OP0_TEA_ST_CLR - Configures whether or not to clear MCPWM0_evt_op0_tea trigger status.\\0: Invalid, No effect\\1: Clear - 4 - 1 - write-only - - - MCPWM0_EVT_OP1_TEA_ST_CLR - Configures whether or not to clear MCPWM0_evt_op1_tea trigger status.\\0: Invalid, No effect\\1: Clear - 5 - 1 - write-only - - - MCPWM0_EVT_OP2_TEA_ST_CLR - Configures whether or not to clear MCPWM0_evt_op2_tea trigger status.\\0: Invalid, No effect\\1: Clear - 6 - 1 - write-only - - - MCPWM0_EVT_OP0_TEB_ST_CLR - Configures whether or not to clear MCPWM0_evt_op0_teb trigger status.\\0: Invalid, No effect\\1: Clear - 7 - 1 - write-only - - - MCPWM0_EVT_OP1_TEB_ST_CLR - Configures whether or not to clear MCPWM0_evt_op1_teb trigger status.\\0: Invalid, No effect\\1: Clear - 8 - 1 - write-only - - - MCPWM0_EVT_OP2_TEB_ST_CLR - Configures whether or not to clear MCPWM0_evt_op2_teb trigger status.\\0: Invalid, No effect\\1: Clear - 9 - 1 - write-only - - - MCPWM0_EVT_F0_ST_CLR - Configures whether or not to clear MCPWM0_evt_f0 trigger status.\\0: Invalid, No effect\\1: Clear - 10 - 1 - write-only - - - MCPWM0_EVT_F1_ST_CLR - Configures whether or not to clear MCPWM0_evt_f1 trigger status.\\0: Invalid, No effect\\1: Clear - 11 - 1 - write-only - - - MCPWM0_EVT_F2_ST_CLR - Configures whether or not to clear MCPWM0_evt_f2 trigger status.\\0: Invalid, No effect\\1: Clear - 12 - 1 - write-only - - - MCPWM0_EVT_F0_CLR_ST_CLR - Configures whether or not to clear MCPWM0_evt_f0_clr trigger status.\\0: Invalid, No effect\\1: Clear - 13 - 1 - write-only - - - MCPWM0_EVT_F1_CLR_ST_CLR - Configures whether or not to clear MCPWM0_evt_f1_clr trigger status.\\0: Invalid, No effect\\1: Clear - 14 - 1 - write-only - - - MCPWM0_EVT_F2_CLR_ST_CLR - Configures whether or not to clear MCPWM0_evt_f2_clr trigger status.\\0: Invalid, No effect\\1: Clear - 15 - 1 - write-only - - - MCPWM0_EVT_TZ0_CBC_ST_CLR - Configures whether or not to clear MCPWM0_evt_tz0_cbc trigger status.\\0: Invalid, No effect\\1: Clear - 16 - 1 - write-only - - - MCPWM0_EVT_TZ1_CBC_ST_CLR - Configures whether or not to clear MCPWM0_evt_tz1_cbc trigger status.\\0: Invalid, No effect\\1: Clear - 17 - 1 - write-only - - - MCPWM0_EVT_TZ2_CBC_ST_CLR - Configures whether or not to clear MCPWM0_evt_tz2_cbc trigger status.\\0: Invalid, No effect\\1: Clear - 18 - 1 - write-only - - - MCPWM0_EVT_TZ0_OST_ST_CLR - Configures whether or not to clear MCPWM0_evt_tz0_ost trigger status.\\0: Invalid, No effect\\1: Clear - 19 - 1 - write-only - - - MCPWM0_EVT_TZ1_OST_ST_CLR - Configures whether or not to clear MCPWM0_evt_tz1_ost trigger status.\\0: Invalid, No effect\\1: Clear - 20 - 1 - write-only - - - MCPWM0_EVT_TZ2_OST_ST_CLR - Configures whether or not to clear MCPWM0_evt_tz2_ost trigger status.\\0: Invalid, No effect\\1: Clear - 21 - 1 - write-only - - - MCPWM0_EVT_CAP0_ST_CLR - Configures whether or not to clear MCPWM0_evt_cap0 trigger status.\\0: Invalid, No effect\\1: Clear - 22 - 1 - write-only - - - MCPWM0_EVT_CAP1_ST_CLR - Configures whether or not to clear MCPWM0_evt_cap1 trigger status.\\0: Invalid, No effect\\1: Clear - 23 - 1 - write-only - - - MCPWM0_EVT_CAP2_ST_CLR - Configures whether or not to clear MCPWM0_evt_cap2 trigger status.\\0: Invalid, No effect\\1: Clear - 24 - 1 - write-only - - - MCPWM0_EVT_OP0_TEE1_ST_CLR - Configures whether or not to clear MCPWM0_evt_op0_tee1 trigger status.\\0: Invalid, No effect\\1: Clear - 25 - 1 - write-only - - - MCPWM0_EVT_OP1_TEE1_ST_CLR - Configures whether or not to clear MCPWM0_evt_op1_tee1 trigger status.\\0: Invalid, No effect\\1: Clear - 26 - 1 - write-only - - - MCPWM0_EVT_OP2_TEE1_ST_CLR - Configures whether or not to clear MCPWM0_evt_op2_tee1 trigger status.\\0: Invalid, No effect\\1: Clear - 27 - 1 - write-only - - - MCPWM0_EVT_OP0_TEE2_ST_CLR - Configures whether or not to clear MCPWM0_evt_op0_tee2 trigger status.\\0: Invalid, No effect\\1: Clear - 28 - 1 - write-only - - - MCPWM0_EVT_OP1_TEE2_ST_CLR - Configures whether or not to clear MCPWM0_evt_op1_tee2 trigger status.\\0: Invalid, No effect\\1: Clear - 29 - 1 - write-only - - - MCPWM0_EVT_OP2_TEE2_ST_CLR - Configures whether or not to clear MCPWM0_evt_op2_tee2 trigger status.\\0: Invalid, No effect\\1: Clear - 30 - 1 - write-only - - - MCPWM1_EVT_TIMER0_STOP_ST_CLR - Configures whether or not to clear MCPWM1_evt_timer0_stop trigger status.\\0: Invalid, No effect\\1: Clear - 31 - 1 - write-only - - - - - EVT_ST3 - Events trigger status register - 0x1C0 - 0x20 - - - MCPWM1_EVT_TIMER1_STOP_ST - Represents MCPWM1_evt_timer1_stop trigger status.\\0: Not triggered\\1: Triggered - 0 - 1 - read-write - - - MCPWM1_EVT_TIMER2_STOP_ST - Represents MCPWM1_evt_timer2_stop trigger status.\\0: Not triggered\\1: Triggered - 1 - 1 - read-write - - - MCPWM1_EVT_TIMER0_TEZ_ST - Represents MCPWM1_evt_timer0_tez trigger status.\\0: Not triggered\\1: Triggered - 2 - 1 - read-write - - - MCPWM1_EVT_TIMER1_TEZ_ST - Represents MCPWM1_evt_timer1_tez trigger status.\\0: Not triggered\\1: Triggered - 3 - 1 - read-write - - - MCPWM1_EVT_TIMER2_TEZ_ST - Represents MCPWM1_evt_timer2_tez trigger status.\\0: Not triggered\\1: Triggered - 4 - 1 - read-write - - - MCPWM1_EVT_TIMER0_TEP_ST - Represents MCPWM1_evt_timer0_tep trigger status.\\0: Not triggered\\1: Triggered - 5 - 1 - read-write - - - MCPWM1_EVT_TIMER1_TEP_ST - Represents MCPWM1_evt_timer1_tep trigger status.\\0: Not triggered\\1: Triggered - 6 - 1 - read-write - - - MCPWM1_EVT_TIMER2_TEP_ST - Represents MCPWM1_evt_timer2_tep trigger status.\\0: Not triggered\\1: Triggered - 7 - 1 - read-write - - - MCPWM1_EVT_OP0_TEA_ST - Represents MCPWM1_evt_op0_tea trigger status.\\0: Not triggered\\1: Triggered - 8 - 1 - read-write - - - MCPWM1_EVT_OP1_TEA_ST - Represents MCPWM1_evt_op1_tea trigger status.\\0: Not triggered\\1: Triggered - 9 - 1 - read-write - - - MCPWM1_EVT_OP2_TEA_ST - Represents MCPWM1_evt_op2_tea trigger status.\\0: Not triggered\\1: Triggered - 10 - 1 - read-write - - - MCPWM1_EVT_OP0_TEB_ST - Represents MCPWM1_evt_op0_teb trigger status.\\0: Not triggered\\1: Triggered - 11 - 1 - read-write - - - MCPWM1_EVT_OP1_TEB_ST - Represents MCPWM1_evt_op1_teb trigger status.\\0: Not triggered\\1: Triggered - 12 - 1 - read-write - - - MCPWM1_EVT_OP2_TEB_ST - Represents MCPWM1_evt_op2_teb trigger status.\\0: Not triggered\\1: Triggered - 13 - 1 - read-write - - - MCPWM1_EVT_F0_ST - Represents MCPWM1_evt_f0 trigger status.\\0: Not triggered\\1: Triggered - 14 - 1 - read-write - - - MCPWM1_EVT_F1_ST - Represents MCPWM1_evt_f1 trigger status.\\0: Not triggered\\1: Triggered - 15 - 1 - read-write - - - MCPWM1_EVT_F2_ST - Represents MCPWM1_evt_f2 trigger status.\\0: Not triggered\\1: Triggered - 16 - 1 - read-write - - - MCPWM1_EVT_F0_CLR_ST - Represents MCPWM1_evt_f0_clr trigger status.\\0: Not triggered\\1: Triggered - 17 - 1 - read-write - - - MCPWM1_EVT_F1_CLR_ST - Represents MCPWM1_evt_f1_clr trigger status.\\0: Not triggered\\1: Triggered - 18 - 1 - read-write - - - MCPWM1_EVT_F2_CLR_ST - Represents MCPWM1_evt_f2_clr trigger status.\\0: Not triggered\\1: Triggered - 19 - 1 - read-write - - - MCPWM1_EVT_TZ0_CBC_ST - Represents MCPWM1_evt_tz0_cbc trigger status.\\0: Not triggered\\1: Triggered - 20 - 1 - read-write - - - MCPWM1_EVT_TZ1_CBC_ST - Represents MCPWM1_evt_tz1_cbc trigger status.\\0: Not triggered\\1: Triggered - 21 - 1 - read-write - - - MCPWM1_EVT_TZ2_CBC_ST - Represents MCPWM1_evt_tz2_cbc trigger status.\\0: Not triggered\\1: Triggered - 22 - 1 - read-write - - - MCPWM1_EVT_TZ0_OST_ST - Represents MCPWM1_evt_tz0_ost trigger status.\\0: Not triggered\\1: Triggered - 23 - 1 - read-write - - - MCPWM1_EVT_TZ1_OST_ST - Represents MCPWM1_evt_tz1_ost trigger status.\\0: Not triggered\\1: Triggered - 24 - 1 - read-write - - - MCPWM1_EVT_TZ2_OST_ST - Represents MCPWM1_evt_tz2_ost trigger status.\\0: Not triggered\\1: Triggered - 25 - 1 - read-write - - - MCPWM1_EVT_CAP0_ST - Represents MCPWM1_evt_cap0 trigger status.\\0: Not triggered\\1: Triggered - 26 - 1 - read-write - - - MCPWM1_EVT_CAP1_ST - Represents MCPWM1_evt_cap1 trigger status.\\0: Not triggered\\1: Triggered - 27 - 1 - read-write - - - MCPWM1_EVT_CAP2_ST - Represents MCPWM1_evt_cap2 trigger status.\\0: Not triggered\\1: Triggered - 28 - 1 - read-write - - - MCPWM1_EVT_OP0_TEE1_ST - Represents MCPWM1_evt_op0_tee1 trigger status.\\0: Not triggered\\1: Triggered - 29 - 1 - read-write - - - MCPWM1_EVT_OP1_TEE1_ST - Represents MCPWM1_evt_op1_tee1 trigger status.\\0: Not triggered\\1: Triggered - 30 - 1 - read-write - - - MCPWM1_EVT_OP2_TEE1_ST - Represents MCPWM1_evt_op2_tee1 trigger status.\\0: Not triggered\\1: Triggered - 31 - 1 - read-write - - - - - EVT_ST3_CLR - Events trigger status clear register - 0x1C4 - 0x20 - - - MCPWM1_EVT_TIMER1_STOP_ST_CLR - Configures whether or not to clear MCPWM1_evt_timer1_stop trigger status.\\0: Invalid, No effect\\1: Clear - 0 - 1 - write-only - - - MCPWM1_EVT_TIMER2_STOP_ST_CLR - Configures whether or not to clear MCPWM1_evt_timer2_stop trigger status.\\0: Invalid, No effect\\1: Clear - 1 - 1 - write-only - - - MCPWM1_EVT_TIMER0_TEZ_ST_CLR - Configures whether or not to clear MCPWM1_evt_timer0_tez trigger status.\\0: Invalid, No effect\\1: Clear - 2 - 1 - write-only - - - MCPWM1_EVT_TIMER1_TEZ_ST_CLR - Configures whether or not to clear MCPWM1_evt_timer1_tez trigger status.\\0: Invalid, No effect\\1: Clear - 3 - 1 - write-only - - - MCPWM1_EVT_TIMER2_TEZ_ST_CLR - Configures whether or not to clear MCPWM1_evt_timer2_tez trigger status.\\0: Invalid, No effect\\1: Clear - 4 - 1 - write-only - - - MCPWM1_EVT_TIMER0_TEP_ST_CLR - Configures whether or not to clear MCPWM1_evt_timer0_tep trigger status.\\0: Invalid, No effect\\1: Clear - 5 - 1 - write-only - - - MCPWM1_EVT_TIMER1_TEP_ST_CLR - Configures whether or not to clear MCPWM1_evt_timer1_tep trigger status.\\0: Invalid, No effect\\1: Clear - 6 - 1 - write-only - - - MCPWM1_EVT_TIMER2_TEP_ST_CLR - Configures whether or not to clear MCPWM1_evt_timer2_tep trigger status.\\0: Invalid, No effect\\1: Clear - 7 - 1 - write-only - - - MCPWM1_EVT_OP0_TEA_ST_CLR - Configures whether or not to clear MCPWM1_evt_op0_tea trigger status.\\0: Invalid, No effect\\1: Clear - 8 - 1 - write-only - - - MCPWM1_EVT_OP1_TEA_ST_CLR - Configures whether or not to clear MCPWM1_evt_op1_tea trigger status.\\0: Invalid, No effect\\1: Clear - 9 - 1 - write-only - - - MCPWM1_EVT_OP2_TEA_ST_CLR - Configures whether or not to clear MCPWM1_evt_op2_tea trigger status.\\0: Invalid, No effect\\1: Clear - 10 - 1 - write-only - - - MCPWM1_EVT_OP0_TEB_ST_CLR - Configures whether or not to clear MCPWM1_evt_op0_teb trigger status.\\0: Invalid, No effect\\1: Clear - 11 - 1 - write-only - - - MCPWM1_EVT_OP1_TEB_ST_CLR - Configures whether or not to clear MCPWM1_evt_op1_teb trigger status.\\0: Invalid, No effect\\1: Clear - 12 - 1 - write-only - - - MCPWM1_EVT_OP2_TEB_ST_CLR - Configures whether or not to clear MCPWM1_evt_op2_teb trigger status.\\0: Invalid, No effect\\1: Clear - 13 - 1 - write-only - - - MCPWM1_EVT_F0_ST_CLR - Configures whether or not to clear MCPWM1_evt_f0 trigger status.\\0: Invalid, No effect\\1: Clear - 14 - 1 - write-only - - - MCPWM1_EVT_F1_ST_CLR - Configures whether or not to clear MCPWM1_evt_f1 trigger status.\\0: Invalid, No effect\\1: Clear - 15 - 1 - write-only - - - MCPWM1_EVT_F2_ST_CLR - Configures whether or not to clear MCPWM1_evt_f2 trigger status.\\0: Invalid, No effect\\1: Clear - 16 - 1 - write-only - - - MCPWM1_EVT_F0_CLR_ST_CLR - Configures whether or not to clear MCPWM1_evt_f0_clr trigger status.\\0: Invalid, No effect\\1: Clear - 17 - 1 - write-only - - - MCPWM1_EVT_F1_CLR_ST_CLR - Configures whether or not to clear MCPWM1_evt_f1_clr trigger status.\\0: Invalid, No effect\\1: Clear - 18 - 1 - write-only - - - MCPWM1_EVT_F2_CLR_ST_CLR - Configures whether or not to clear MCPWM1_evt_f2_clr trigger status.\\0: Invalid, No effect\\1: Clear - 19 - 1 - write-only - - - MCPWM1_EVT_TZ0_CBC_ST_CLR - Configures whether or not to clear MCPWM1_evt_tz0_cbc trigger status.\\0: Invalid, No effect\\1: Clear - 20 - 1 - write-only - - - MCPWM1_EVT_TZ1_CBC_ST_CLR - Configures whether or not to clear MCPWM1_evt_tz1_cbc trigger status.\\0: Invalid, No effect\\1: Clear - 21 - 1 - write-only - - - MCPWM1_EVT_TZ2_CBC_ST_CLR - Configures whether or not to clear MCPWM1_evt_tz2_cbc trigger status.\\0: Invalid, No effect\\1: Clear - 22 - 1 - write-only - - - MCPWM1_EVT_TZ0_OST_ST_CLR - Configures whether or not to clear MCPWM1_evt_tz0_ost trigger status.\\0: Invalid, No effect\\1: Clear - 23 - 1 - write-only - - - MCPWM1_EVT_TZ1_OST_ST_CLR - Configures whether or not to clear MCPWM1_evt_tz1_ost trigger status.\\0: Invalid, No effect\\1: Clear - 24 - 1 - write-only - - - MCPWM1_EVT_TZ2_OST_ST_CLR - Configures whether or not to clear MCPWM1_evt_tz2_ost trigger status.\\0: Invalid, No effect\\1: Clear - 25 - 1 - write-only - - - MCPWM1_EVT_CAP0_ST_CLR - Configures whether or not to clear MCPWM1_evt_cap0 trigger status.\\0: Invalid, No effect\\1: Clear - 26 - 1 - write-only - - - MCPWM1_EVT_CAP1_ST_CLR - Configures whether or not to clear MCPWM1_evt_cap1 trigger status.\\0: Invalid, No effect\\1: Clear - 27 - 1 - write-only - - - MCPWM1_EVT_CAP2_ST_CLR - Configures whether or not to clear MCPWM1_evt_cap2 trigger status.\\0: Invalid, No effect\\1: Clear - 28 - 1 - write-only - - - MCPWM1_EVT_OP0_TEE1_ST_CLR - Configures whether or not to clear MCPWM1_evt_op0_tee1 trigger status.\\0: Invalid, No effect\\1: Clear - 29 - 1 - write-only - - - MCPWM1_EVT_OP1_TEE1_ST_CLR - Configures whether or not to clear MCPWM1_evt_op1_tee1 trigger status.\\0: Invalid, No effect\\1: Clear - 30 - 1 - write-only - - - MCPWM1_EVT_OP2_TEE1_ST_CLR - Configures whether or not to clear MCPWM1_evt_op2_tee1 trigger status.\\0: Invalid, No effect\\1: Clear - 31 - 1 - write-only - - - - - EVT_ST4 - Events trigger status register - 0x1C8 - 0x20 - - - MCPWM1_EVT_OP0_TEE2_ST - Represents MCPWM1_evt_op0_tee2 trigger status.\\0: Not triggered\\1: Triggered - 0 - 1 - read-write - - - MCPWM1_EVT_OP1_TEE2_ST - Represents MCPWM1_evt_op1_tee2 trigger status.\\0: Not triggered\\1: Triggered - 1 - 1 - read-write - - - MCPWM1_EVT_OP2_TEE2_ST - Represents MCPWM1_evt_op2_tee2 trigger status.\\0: Not triggered\\1: Triggered - 2 - 1 - read-write - - - ADC_EVT_CONV_CMPLT0_ST - Represents ADC_evt_conv_cmplt0 trigger status.\\0: Not triggered\\1: Triggered - 3 - 1 - read-write - - - ADC_EVT_EQ_ABOVE_THRESH0_ST - Represents ADC_evt_eq_above_thresh0 trigger status.\\0: Not triggered\\1: Triggered - 4 - 1 - read-write - - - ADC_EVT_EQ_ABOVE_THRESH1_ST - Represents ADC_evt_eq_above_thresh1 trigger status.\\0: Not triggered\\1: Triggered - 5 - 1 - read-write - - - ADC_EVT_EQ_BELOW_THRESH0_ST - Represents ADC_evt_eq_below_thresh0 trigger status.\\0: Not triggered\\1: Triggered - 6 - 1 - read-write - - - ADC_EVT_EQ_BELOW_THRESH1_ST - Represents ADC_evt_eq_below_thresh1 trigger status.\\0: Not triggered\\1: Triggered - 7 - 1 - read-write - - - ADC_EVT_RESULT_DONE0_ST - Represents ADC_evt_result_done0 trigger status.\\0: Not triggered\\1: Triggered - 8 - 1 - read-write - - - ADC_EVT_STOPPED0_ST - Represents ADC_evt_stopped0 trigger status.\\0: Not triggered\\1: Triggered - 9 - 1 - read-write - - - ADC_EVT_STARTED0_ST - Represents ADC_evt_started0 trigger status.\\0: Not triggered\\1: Triggered - 10 - 1 - read-write - - - REGDMA_EVT_DONE0_ST - Represents REGDMA_evt_done0 trigger status.\\0: Not triggered\\1: Triggered - 11 - 1 - read-write - - - REGDMA_EVT_DONE1_ST - Represents REGDMA_evt_done1 trigger status.\\0: Not triggered\\1: Triggered - 12 - 1 - read-write - - - REGDMA_EVT_DONE2_ST - Represents REGDMA_evt_done2 trigger status.\\0: Not triggered\\1: Triggered - 13 - 1 - read-write - - - REGDMA_EVT_DONE3_ST - Represents REGDMA_evt_done3 trigger status.\\0: Not triggered\\1: Triggered - 14 - 1 - read-write - - - REGDMA_EVT_ERR0_ST - Represents REGDMA_evt_err0 trigger status.\\0: Not triggered\\1: Triggered - 15 - 1 - read-write - - - REGDMA_EVT_ERR1_ST - Represents REGDMA_evt_err1 trigger status.\\0: Not triggered\\1: Triggered - 16 - 1 - read-write - - - REGDMA_EVT_ERR2_ST - Represents REGDMA_evt_err2 trigger status.\\0: Not triggered\\1: Triggered - 17 - 1 - read-write - - - REGDMA_EVT_ERR3_ST - Represents REGDMA_evt_err3 trigger status.\\0: Not triggered\\1: Triggered - 18 - 1 - read-write - - - TMPSNSR_EVT_OVER_LIMIT_ST - Represents TMPSNSR_evt_over_limit trigger status.\\0: Not triggered\\1: Triggered - 19 - 1 - read-write - - - I2S0_EVT_RX_DONE_ST - Represents I2S0_evt_rx_done trigger status.\\0: Not triggered\\1: Triggered - 20 - 1 - read-write - - - I2S0_EVT_TX_DONE_ST - Represents I2S0_evt_tx_done trigger status.\\0: Not triggered\\1: Triggered - 21 - 1 - read-write - - - I2S0_EVT_X_WORDS_RECEIVED_ST - Represents I2S0_evt_x_words_received trigger status.\\0: Not triggered\\1: Triggered - 22 - 1 - read-write - - - I2S0_EVT_X_WORDS_SENT_ST - Represents I2S0_evt_x_words_sent trigger status.\\0: Not triggered\\1: Triggered - 23 - 1 - read-write - - - I2S1_EVT_RX_DONE_ST - Represents I2S1_evt_rx_done trigger status.\\0: Not triggered\\1: Triggered - 24 - 1 - read-write - - - I2S1_EVT_TX_DONE_ST - Represents I2S1_evt_tx_done trigger status.\\0: Not triggered\\1: Triggered - 25 - 1 - read-write - - - I2S1_EVT_X_WORDS_RECEIVED_ST - Represents I2S1_evt_x_words_received trigger status.\\0: Not triggered\\1: Triggered - 26 - 1 - read-write - - - I2S1_EVT_X_WORDS_SENT_ST - Represents I2S1_evt_x_words_sent trigger status.\\0: Not triggered\\1: Triggered - 27 - 1 - read-write - - - I2S2_EVT_RX_DONE_ST - Represents I2S2_evt_rx_done trigger status.\\0: Not triggered\\1: Triggered - 28 - 1 - read-write - - - I2S2_EVT_TX_DONE_ST - Represents I2S2_evt_tx_done trigger status.\\0: Not triggered\\1: Triggered - 29 - 1 - read-write - - - I2S2_EVT_X_WORDS_RECEIVED_ST - Represents I2S2_evt_x_words_received trigger status.\\0: Not triggered\\1: Triggered - 30 - 1 - read-write - - - I2S2_EVT_X_WORDS_SENT_ST - Represents I2S2_evt_x_words_sent trigger status.\\0: Not triggered\\1: Triggered - 31 - 1 - read-write - - - - - EVT_ST4_CLR - Events trigger status clear register - 0x1CC - 0x20 - - - MCPWM1_EVT_OP0_TEE2_ST_CLR - Configures whether or not to clear MCPWM1_evt_op0_tee2 trigger status.\\0: Invalid, No effect\\1: Clear - 0 - 1 - write-only - - - MCPWM1_EVT_OP1_TEE2_ST_CLR - Configures whether or not to clear MCPWM1_evt_op1_tee2 trigger status.\\0: Invalid, No effect\\1: Clear - 1 - 1 - write-only - - - MCPWM1_EVT_OP2_TEE2_ST_CLR - Configures whether or not to clear MCPWM1_evt_op2_tee2 trigger status.\\0: Invalid, No effect\\1: Clear - 2 - 1 - write-only - - - ADC_EVT_CONV_CMPLT0_ST_CLR - Configures whether or not to clear ADC_evt_conv_cmplt0 trigger status.\\0: Invalid, No effect\\1: Clear - 3 - 1 - write-only - - - ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR - Configures whether or not to clear ADC_evt_eq_above_thresh0 trigger status.\\0: Invalid, No effect\\1: Clear - 4 - 1 - write-only - - - ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR - Configures whether or not to clear ADC_evt_eq_above_thresh1 trigger status.\\0: Invalid, No effect\\1: Clear - 5 - 1 - write-only - - - ADC_EVT_EQ_BELOW_THRESH0_ST_CLR - Configures whether or not to clear ADC_evt_eq_below_thresh0 trigger status.\\0: Invalid, No effect\\1: Clear - 6 - 1 - write-only - - - ADC_EVT_EQ_BELOW_THRESH1_ST_CLR - Configures whether or not to clear ADC_evt_eq_below_thresh1 trigger status.\\0: Invalid, No effect\\1: Clear - 7 - 1 - write-only - - - ADC_EVT_RESULT_DONE0_ST_CLR - Configures whether or not to clear ADC_evt_result_done0 trigger status.\\0: Invalid, No effect\\1: Clear - 8 - 1 - write-only - - - ADC_EVT_STOPPED0_ST_CLR - Configures whether or not to clear ADC_evt_stopped0 trigger status.\\0: Invalid, No effect\\1: Clear - 9 - 1 - write-only - - - ADC_EVT_STARTED0_ST_CLR - Configures whether or not to clear ADC_evt_started0 trigger status.\\0: Invalid, No effect\\1: Clear - 10 - 1 - write-only - - - REGDMA_EVT_DONE0_ST_CLR - Configures whether or not to clear REGDMA_evt_done0 trigger status.\\0: Invalid, No effect\\1: Clear - 11 - 1 - write-only - - - REGDMA_EVT_DONE1_ST_CLR - Configures whether or not to clear REGDMA_evt_done1 trigger status.\\0: Invalid, No effect\\1: Clear - 12 - 1 - write-only - - - REGDMA_EVT_DONE2_ST_CLR - Configures whether or not to clear REGDMA_evt_done2 trigger status.\\0: Invalid, No effect\\1: Clear - 13 - 1 - write-only - - - REGDMA_EVT_DONE3_ST_CLR - Configures whether or not to clear REGDMA_evt_done3 trigger status.\\0: Invalid, No effect\\1: Clear - 14 - 1 - write-only - - - REGDMA_EVT_ERR0_ST_CLR - Configures whether or not to clear REGDMA_evt_err0 trigger status.\\0: Invalid, No effect\\1: Clear - 15 - 1 - write-only - - - REGDMA_EVT_ERR1_ST_CLR - Configures whether or not to clear REGDMA_evt_err1 trigger status.\\0: Invalid, No effect\\1: Clear - 16 - 1 - write-only - - - REGDMA_EVT_ERR2_ST_CLR - Configures whether or not to clear REGDMA_evt_err2 trigger status.\\0: Invalid, No effect\\1: Clear - 17 - 1 - write-only - - - REGDMA_EVT_ERR3_ST_CLR - Configures whether or not to clear REGDMA_evt_err3 trigger status.\\0: Invalid, No effect\\1: Clear - 18 - 1 - write-only - - - TMPSNSR_EVT_OVER_LIMIT_ST_CLR - Configures whether or not to clear TMPSNSR_evt_over_limit trigger status.\\0: Invalid, No effect\\1: Clear - 19 - 1 - write-only - - - I2S0_EVT_RX_DONE_ST_CLR - Configures whether or not to clear I2S0_evt_rx_done trigger status.\\0: Invalid, No effect\\1: Clear - 20 - 1 - write-only - - - I2S0_EVT_TX_DONE_ST_CLR - Configures whether or not to clear I2S0_evt_tx_done trigger status.\\0: Invalid, No effect\\1: Clear - 21 - 1 - write-only - - - I2S0_EVT_X_WORDS_RECEIVED_ST_CLR - Configures whether or not to clear I2S0_evt_x_words_received trigger status.\\0: Invalid, No effect\\1: Clear - 22 - 1 - write-only - - - I2S0_EVT_X_WORDS_SENT_ST_CLR - Configures whether or not to clear I2S0_evt_x_words_sent trigger status.\\0: Invalid, No effect\\1: Clear - 23 - 1 - write-only - - - I2S1_EVT_RX_DONE_ST_CLR - Configures whether or not to clear I2S1_evt_rx_done trigger status.\\0: Invalid, No effect\\1: Clear - 24 - 1 - write-only - - - I2S1_EVT_TX_DONE_ST_CLR - Configures whether or not to clear I2S1_evt_tx_done trigger status.\\0: Invalid, No effect\\1: Clear - 25 - 1 - write-only - - - I2S1_EVT_X_WORDS_RECEIVED_ST_CLR - Configures whether or not to clear I2S1_evt_x_words_received trigger status.\\0: Invalid, No effect\\1: Clear - 26 - 1 - write-only - - - I2S1_EVT_X_WORDS_SENT_ST_CLR - Configures whether or not to clear I2S1_evt_x_words_sent trigger status.\\0: Invalid, No effect\\1: Clear - 27 - 1 - write-only - - - I2S2_EVT_RX_DONE_ST_CLR - Configures whether or not to clear I2S2_evt_rx_done trigger status.\\0: Invalid, No effect\\1: Clear - 28 - 1 - write-only - - - I2S2_EVT_TX_DONE_ST_CLR - Configures whether or not to clear I2S2_evt_tx_done trigger status.\\0: Invalid, No effect\\1: Clear - 29 - 1 - write-only - - - I2S2_EVT_X_WORDS_RECEIVED_ST_CLR - Configures whether or not to clear I2S2_evt_x_words_received trigger status.\\0: Invalid, No effect\\1: Clear - 30 - 1 - write-only - - - I2S2_EVT_X_WORDS_SENT_ST_CLR - Configures whether or not to clear I2S2_evt_x_words_sent trigger status.\\0: Invalid, No effect\\1: Clear - 31 - 1 - write-only - - - - - EVT_ST5 - Events trigger status register - 0x1D0 - 0x20 - - - ULP_EVT_ERR_INTR_ST - Represents ULP_evt_err_intr trigger status.\\0: Not triggered\\1: Triggered - 0 - 1 - read-write - - - ULP_EVT_HALT_ST - Represents ULP_evt_halt trigger status.\\0: Not triggered\\1: Triggered - 1 - 1 - read-write - - - ULP_EVT_START_INTR_ST - Represents ULP_evt_start_intr trigger status.\\0: Not triggered\\1: Triggered - 2 - 1 - read-write - - - RTC_EVT_TICK_ST - Represents RTC_evt_tick trigger status.\\0: Not triggered\\1: Triggered - 3 - 1 - read-write - - - RTC_EVT_OVF_ST - Represents RTC_evt_ovf trigger status.\\0: Not triggered\\1: Triggered - 4 - 1 - read-write - - - RTC_EVT_CMP_ST - Represents RTC_evt_cmp trigger status.\\0: Not triggered\\1: Triggered - 5 - 1 - read-write - - - PDMA_AHB_EVT_IN_DONE_CH0_ST - Represents PDMA_AHB_evt_in_done_ch0 trigger status.\\0: Not triggered\\1: Triggered - 6 - 1 - read-write - - - PDMA_AHB_EVT_IN_DONE_CH1_ST - Represents PDMA_AHB_evt_in_done_ch1 trigger status.\\0: Not triggered\\1: Triggered - 7 - 1 - read-write - - - PDMA_AHB_EVT_IN_DONE_CH2_ST - Represents PDMA_AHB_evt_in_done_ch2 trigger status.\\0: Not triggered\\1: Triggered - 8 - 1 - read-write - - - PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST - Represents PDMA_AHB_evt_in_suc_eof_ch0 trigger status.\\0: Not triggered\\1: Triggered - 9 - 1 - read-write - - - PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST - Represents PDMA_AHB_evt_in_suc_eof_ch1 trigger status.\\0: Not triggered\\1: Triggered - 10 - 1 - read-write - - - PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST - Represents PDMA_AHB_evt_in_suc_eof_ch2 trigger status.\\0: Not triggered\\1: Triggered - 11 - 1 - read-write - - - PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST - Represents PDMA_AHB_evt_in_fifo_empty_ch0 trigger status.\\0: Not triggered\\1: Triggered - 12 - 1 - read-write - - - PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST - Represents PDMA_AHB_evt_in_fifo_empty_ch1 trigger status.\\0: Not triggered\\1: Triggered - 13 - 1 - read-write - - - PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST - Represents PDMA_AHB_evt_in_fifo_empty_ch2 trigger status.\\0: Not triggered\\1: Triggered - 14 - 1 - read-write - - - PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST - Represents PDMA_AHB_evt_in_fifo_full_ch0 trigger status.\\0: Not triggered\\1: Triggered - 15 - 1 - read-write - - - PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST - Represents PDMA_AHB_evt_in_fifo_full_ch1 trigger status.\\0: Not triggered\\1: Triggered - 16 - 1 - read-write - - - PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST - Represents PDMA_AHB_evt_in_fifo_full_ch2 trigger status.\\0: Not triggered\\1: Triggered - 17 - 1 - read-write - - - PDMA_AHB_EVT_OUT_DONE_CH0_ST - Represents PDMA_AHB_evt_out_done_ch0 trigger status.\\0: Not triggered\\1: Triggered - 18 - 1 - read-write - - - PDMA_AHB_EVT_OUT_DONE_CH1_ST - Represents PDMA_AHB_evt_out_done_ch1 trigger status.\\0: Not triggered\\1: Triggered - 19 - 1 - read-write - - - PDMA_AHB_EVT_OUT_DONE_CH2_ST - Represents PDMA_AHB_evt_out_done_ch2 trigger status.\\0: Not triggered\\1: Triggered - 20 - 1 - read-write - - - PDMA_AHB_EVT_OUT_EOF_CH0_ST - Represents PDMA_AHB_evt_out_eof_ch0 trigger status.\\0: Not triggered\\1: Triggered - 21 - 1 - read-write - - - PDMA_AHB_EVT_OUT_EOF_CH1_ST - Represents PDMA_AHB_evt_out_eof_ch1 trigger status.\\0: Not triggered\\1: Triggered - 22 - 1 - read-write - - - PDMA_AHB_EVT_OUT_EOF_CH2_ST - Represents PDMA_AHB_evt_out_eof_ch2 trigger status.\\0: Not triggered\\1: Triggered - 23 - 1 - read-write - - - PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST - Represents PDMA_AHB_evt_out_total_eof_ch0 trigger status.\\0: Not triggered\\1: Triggered - 24 - 1 - read-write - - - PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST - Represents PDMA_AHB_evt_out_total_eof_ch1 trigger status.\\0: Not triggered\\1: Triggered - 25 - 1 - read-write - - - PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST - Represents PDMA_AHB_evt_out_total_eof_ch2 trigger status.\\0: Not triggered\\1: Triggered - 26 - 1 - read-write - - - PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST - Represents PDMA_AHB_evt_out_fifo_empty_ch0 trigger status.\\0: Not triggered\\1: Triggered - 27 - 1 - read-write - - - PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST - Represents PDMA_AHB_evt_out_fifo_empty_ch1 trigger status.\\0: Not triggered\\1: Triggered - 28 - 1 - read-write - - - PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST - Represents PDMA_AHB_evt_out_fifo_empty_ch2 trigger status.\\0: Not triggered\\1: Triggered - 29 - 1 - read-write - - - PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST - Represents PDMA_AHB_evt_out_fifo_full_ch0 trigger status.\\0: Not triggered\\1: Triggered - 30 - 1 - read-write - - - PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST - Represents PDMA_AHB_evt_out_fifo_full_ch1 trigger status.\\0: Not triggered\\1: Triggered - 31 - 1 - read-write - - - - - EVT_ST5_CLR - Events trigger status clear register - 0x1D4 - 0x20 - - - ULP_EVT_ERR_INTR_ST_CLR - Configures whether or not to clear ULP_evt_err_intr trigger status.\\0: Invalid, No effect\\1: Clear - 0 - 1 - write-only - - - ULP_EVT_HALT_ST_CLR - Configures whether or not to clear ULP_evt_halt trigger status.\\0: Invalid, No effect\\1: Clear - 1 - 1 - write-only - - - ULP_EVT_START_INTR_ST_CLR - Configures whether or not to clear ULP_evt_start_intr trigger status.\\0: Invalid, No effect\\1: Clear - 2 - 1 - write-only - - - RTC_EVT_TICK_ST_CLR - Configures whether or not to clear RTC_evt_tick trigger status.\\0: Invalid, No effect\\1: Clear - 3 - 1 - write-only - - - RTC_EVT_OVF_ST_CLR - Configures whether or not to clear RTC_evt_ovf trigger status.\\0: Invalid, No effect\\1: Clear - 4 - 1 - write-only - - - RTC_EVT_CMP_ST_CLR - Configures whether or not to clear RTC_evt_cmp trigger status.\\0: Invalid, No effect\\1: Clear - 5 - 1 - write-only - - - PDMA_AHB_EVT_IN_DONE_CH0_ST_CLR - Configures whether or not to clear PDMA_AHB_evt_in_done_ch0 trigger status.\\0: Invalid, No effect\\1: Clear - 6 - 1 - write-only - - - PDMA_AHB_EVT_IN_DONE_CH1_ST_CLR - Configures whether or not to clear PDMA_AHB_evt_in_done_ch1 trigger status.\\0: Invalid, No effect\\1: Clear - 7 - 1 - write-only - - - PDMA_AHB_EVT_IN_DONE_CH2_ST_CLR - Configures whether or not to clear PDMA_AHB_evt_in_done_ch2 trigger status.\\0: Invalid, No effect\\1: Clear - 8 - 1 - write-only - - - PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_CLR - Configures whether or not to clear PDMA_AHB_evt_in_suc_eof_ch0 trigger status.\\0: Invalid, No effect\\1: Clear - 9 - 1 - write-only - - - PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_CLR - Configures whether or not to clear PDMA_AHB_evt_in_suc_eof_ch1 trigger status.\\0: Invalid, No effect\\1: Clear - 10 - 1 - write-only - - - PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_CLR - Configures whether or not to clear PDMA_AHB_evt_in_suc_eof_ch2 trigger status.\\0: Invalid, No effect\\1: Clear - 11 - 1 - write-only - - - PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_CLR - Configures whether or not to clear PDMA_AHB_evt_in_fifo_empty_ch0 trigger status.\\0: Invalid, No effect\\1: Clear - 12 - 1 - write-only - - - PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_CLR - Configures whether or not to clear PDMA_AHB_evt_in_fifo_empty_ch1 trigger status.\\0: Invalid, No effect\\1: Clear - 13 - 1 - write-only - - - PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_CLR - Configures whether or not to clear PDMA_AHB_evt_in_fifo_empty_ch2 trigger status.\\0: Invalid, No effect\\1: Clear - 14 - 1 - write-only - - - PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_CLR - Configures whether or not to clear PDMA_AHB_evt_in_fifo_full_ch0 trigger status.\\0: Invalid, No effect\\1: Clear - 15 - 1 - write-only - - - PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_CLR - Configures whether or not to clear PDMA_AHB_evt_in_fifo_full_ch1 trigger status.\\0: Invalid, No effect\\1: Clear - 16 - 1 - write-only - - - PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_CLR - Configures whether or not to clear PDMA_AHB_evt_in_fifo_full_ch2 trigger status.\\0: Invalid, No effect\\1: Clear - 17 - 1 - write-only - - - PDMA_AHB_EVT_OUT_DONE_CH0_ST_CLR - Configures whether or not to clear PDMA_AHB_evt_out_done_ch0 trigger status.\\0: Invalid, No effect\\1: Clear - 18 - 1 - write-only - - - PDMA_AHB_EVT_OUT_DONE_CH1_ST_CLR - Configures whether or not to clear PDMA_AHB_evt_out_done_ch1 trigger status.\\0: Invalid, No effect\\1: Clear - 19 - 1 - write-only - - - PDMA_AHB_EVT_OUT_DONE_CH2_ST_CLR - Configures whether or not to clear PDMA_AHB_evt_out_done_ch2 trigger status.\\0: Invalid, No effect\\1: Clear - 20 - 1 - write-only - - - PDMA_AHB_EVT_OUT_EOF_CH0_ST_CLR - Configures whether or not to clear PDMA_AHB_evt_out_eof_ch0 trigger status.\\0: Invalid, No effect\\1: Clear - 21 - 1 - write-only - - - PDMA_AHB_EVT_OUT_EOF_CH1_ST_CLR - Configures whether or not to clear PDMA_AHB_evt_out_eof_ch1 trigger status.\\0: Invalid, No effect\\1: Clear - 22 - 1 - write-only - - - PDMA_AHB_EVT_OUT_EOF_CH2_ST_CLR - Configures whether or not to clear PDMA_AHB_evt_out_eof_ch2 trigger status.\\0: Invalid, No effect\\1: Clear - 23 - 1 - write-only - - - PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_CLR - Configures whether or not to clear PDMA_AHB_evt_out_total_eof_ch0 trigger status.\\0: Invalid, No effect\\1: Clear - 24 - 1 - write-only - - - PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_CLR - Configures whether or not to clear PDMA_AHB_evt_out_total_eof_ch1 trigger status.\\0: Invalid, No effect\\1: Clear - 25 - 1 - write-only - - - PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_CLR - Configures whether or not to clear PDMA_AHB_evt_out_total_eof_ch2 trigger status.\\0: Invalid, No effect\\1: Clear - 26 - 1 - write-only - - - PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR - Configures whether or not to clear PDMA_AHB_evt_out_fifo_empty_ch0 trigger status.\\0: Invalid, No effect\\1: Clear - 27 - 1 - write-only - - - PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR - Configures whether or not to clear PDMA_AHB_evt_out_fifo_empty_ch1 trigger status.\\0: Invalid, No effect\\1: Clear - 28 - 1 - write-only - - - PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR - Configures whether or not to clear PDMA_AHB_evt_out_fifo_empty_ch2 trigger status.\\0: Invalid, No effect\\1: Clear - 29 - 1 - write-only - - - PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_CLR - Configures whether or not to clear PDMA_AHB_evt_out_fifo_full_ch0 trigger status.\\0: Invalid, No effect\\1: Clear - 30 - 1 - write-only - - - PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_CLR - Configures whether or not to clear PDMA_AHB_evt_out_fifo_full_ch1 trigger status.\\0: Invalid, No effect\\1: Clear - 31 - 1 - write-only - - - - - EVT_ST6 - Events trigger status register - 0x1D8 - 0x20 - - - PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST - Represents PDMA_AHB_evt_out_fifo_full_ch2 trigger status.\\0: Not triggered\\1: Triggered - 0 - 1 - read-write - - - PDMA_AXI_EVT_IN_DONE_CH0_ST - Represents PDMA_AXI_evt_in_done_ch0 trigger status.\\0: Not triggered\\1: Triggered - 1 - 1 - read-write - - - PDMA_AXI_EVT_IN_DONE_CH1_ST - Represents PDMA_AXI_evt_in_done_ch1 trigger status.\\0: Not triggered\\1: Triggered - 2 - 1 - read-write - - - PDMA_AXI_EVT_IN_DONE_CH2_ST - Represents PDMA_AXI_evt_in_done_ch2 trigger status.\\0: Not triggered\\1: Triggered - 3 - 1 - read-write - - - PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST - Represents PDMA_AXI_evt_in_suc_eof_ch0 trigger status.\\0: Not triggered\\1: Triggered - 4 - 1 - read-write - - - PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST - Represents PDMA_AXI_evt_in_suc_eof_ch1 trigger status.\\0: Not triggered\\1: Triggered - 5 - 1 - read-write - - - PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST - Represents PDMA_AXI_evt_in_suc_eof_ch2 trigger status.\\0: Not triggered\\1: Triggered - 6 - 1 - read-write - - - PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST - Represents PDMA_AXI_evt_in_fifo_empty_ch0 trigger status.\\0: Not triggered\\1: Triggered - 7 - 1 - read-write - - - PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST - Represents PDMA_AXI_evt_in_fifo_empty_ch1 trigger status.\\0: Not triggered\\1: Triggered - 8 - 1 - read-write - - - PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST - Represents PDMA_AXI_evt_in_fifo_empty_ch2 trigger status.\\0: Not triggered\\1: Triggered - 9 - 1 - read-write - - - PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST - Represents PDMA_AXI_evt_in_fifo_full_ch0 trigger status.\\0: Not triggered\\1: Triggered - 10 - 1 - read-write - - - PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST - Represents PDMA_AXI_evt_in_fifo_full_ch1 trigger status.\\0: Not triggered\\1: Triggered - 11 - 1 - read-write - - - PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST - Represents PDMA_AXI_evt_in_fifo_full_ch2 trigger status.\\0: Not triggered\\1: Triggered - 12 - 1 - read-write - - - PDMA_AXI_EVT_OUT_DONE_CH0_ST - Represents PDMA_AXI_evt_out_done_ch0 trigger status.\\0: Not triggered\\1: Triggered - 13 - 1 - read-write - - - PDMA_AXI_EVT_OUT_DONE_CH1_ST - Represents PDMA_AXI_evt_out_done_ch1 trigger status.\\0: Not triggered\\1: Triggered - 14 - 1 - read-write - - - PDMA_AXI_EVT_OUT_DONE_CH2_ST - Represents PDMA_AXI_evt_out_done_ch2 trigger status.\\0: Not triggered\\1: Triggered - 15 - 1 - read-write - - - PDMA_AXI_EVT_OUT_EOF_CH0_ST - Represents PDMA_AXI_evt_out_eof_ch0 trigger status.\\0: Not triggered\\1: Triggered - 16 - 1 - read-write - - - PDMA_AXI_EVT_OUT_EOF_CH1_ST - Represents PDMA_AXI_evt_out_eof_ch1 trigger status.\\0: Not triggered\\1: Triggered - 17 - 1 - read-write - - - PDMA_AXI_EVT_OUT_EOF_CH2_ST - Represents PDMA_AXI_evt_out_eof_ch2 trigger status.\\0: Not triggered\\1: Triggered - 18 - 1 - read-write - - - PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST - Represents PDMA_AXI_evt_out_total_eof_ch0 trigger status.\\0: Not triggered\\1: Triggered - 19 - 1 - read-write - - - PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST - Represents PDMA_AXI_evt_out_total_eof_ch1 trigger status.\\0: Not triggered\\1: Triggered - 20 - 1 - read-write - - - PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST - Represents PDMA_AXI_evt_out_total_eof_ch2 trigger status.\\0: Not triggered\\1: Triggered - 21 - 1 - read-write - - - PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST - Represents PDMA_AXI_evt_out_fifo_empty_ch0 trigger status.\\0: Not triggered\\1: Triggered - 22 - 1 - read-write - - - PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST - Represents PDMA_AXI_evt_out_fifo_empty_ch1 trigger status.\\0: Not triggered\\1: Triggered - 23 - 1 - read-write - - - PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST - Represents PDMA_AXI_evt_out_fifo_empty_ch2 trigger status.\\0: Not triggered\\1: Triggered - 24 - 1 - read-write - - - PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST - Represents PDMA_AXI_evt_out_fifo_full_ch0 trigger status.\\0: Not triggered\\1: Triggered - 25 - 1 - read-write - - - PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST - Represents PDMA_AXI_evt_out_fifo_full_ch1 trigger status.\\0: Not triggered\\1: Triggered - 26 - 1 - read-write - - - PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST - Represents PDMA_AXI_evt_out_fifo_full_ch2 trigger status.\\0: Not triggered\\1: Triggered - 27 - 1 - read-write - - - PMU_EVT_SLEEP_WEEKUP_ST - Represents PMU_evt_sleep_weekup trigger status.\\0: Not triggered\\1: Triggered - 28 - 1 - read-write - - - DMA2D_EVT_IN_DONE_CH0_ST - Represents DMA2D_evt_in_done_ch0 trigger status.\\0: Not triggered\\1: Triggered - 29 - 1 - read-write - - - DMA2D_EVT_IN_DONE_CH1_ST - Represents DMA2D_evt_in_done_ch1 trigger status.\\0: Not triggered\\1: Triggered - 30 - 1 - read-write - - - DMA2D_EVT_IN_SUC_EOF_CH0_ST - Represents DMA2D_evt_in_suc_eof_ch0 trigger status.\\0: Not triggered\\1: Triggered - 31 - 1 - read-write - - - - - EVT_ST6_CLR - Events trigger status clear register - 0x1DC - 0x20 - - - PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_CLR - Configures whether or not to clear PDMA_AHB_evt_out_fifo_full_ch2 trigger status.\\0: Invalid, No effect\\1: Clear - 0 - 1 - write-only - - - PDMA_AXI_EVT_IN_DONE_CH0_ST_CLR - Configures whether or not to clear PDMA_AXI_evt_in_done_ch0 trigger status.\\0: Invalid, No effect\\1: Clear - 1 - 1 - write-only - - - PDMA_AXI_EVT_IN_DONE_CH1_ST_CLR - Configures whether or not to clear PDMA_AXI_evt_in_done_ch1 trigger status.\\0: Invalid, No effect\\1: Clear - 2 - 1 - write-only - - - PDMA_AXI_EVT_IN_DONE_CH2_ST_CLR - Configures whether or not to clear PDMA_AXI_evt_in_done_ch2 trigger status.\\0: Invalid, No effect\\1: Clear - 3 - 1 - write-only - - - PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST_CLR - Configures whether or not to clear PDMA_AXI_evt_in_suc_eof_ch0 trigger status.\\0: Invalid, No effect\\1: Clear - 4 - 1 - write-only - - - PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST_CLR - Configures whether or not to clear PDMA_AXI_evt_in_suc_eof_ch1 trigger status.\\0: Invalid, No effect\\1: Clear - 5 - 1 - write-only - - - PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST_CLR - Configures whether or not to clear PDMA_AXI_evt_in_suc_eof_ch2 trigger status.\\0: Invalid, No effect\\1: Clear - 6 - 1 - write-only - - - PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST_CLR - Configures whether or not to clear PDMA_AXI_evt_in_fifo_empty_ch0 trigger status.\\0: Invalid, No effect\\1: Clear - 7 - 1 - write-only - - - PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST_CLR - Configures whether or not to clear PDMA_AXI_evt_in_fifo_empty_ch1 trigger status.\\0: Invalid, No effect\\1: Clear - 8 - 1 - write-only - - - PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST_CLR - Configures whether or not to clear PDMA_AXI_evt_in_fifo_empty_ch2 trigger status.\\0: Invalid, No effect\\1: Clear - 9 - 1 - write-only - - - PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST_CLR - Configures whether or not to clear PDMA_AXI_evt_in_fifo_full_ch0 trigger status.\\0: Invalid, No effect\\1: Clear - 10 - 1 - write-only - - - PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST_CLR - Configures whether or not to clear PDMA_AXI_evt_in_fifo_full_ch1 trigger status.\\0: Invalid, No effect\\1: Clear - 11 - 1 - write-only - - - PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST_CLR - Configures whether or not to clear PDMA_AXI_evt_in_fifo_full_ch2 trigger status.\\0: Invalid, No effect\\1: Clear - 12 - 1 - write-only - - - PDMA_AXI_EVT_OUT_DONE_CH0_ST_CLR - Configures whether or not to clear PDMA_AXI_evt_out_done_ch0 trigger status.\\0: Invalid, No effect\\1: Clear - 13 - 1 - write-only - - - PDMA_AXI_EVT_OUT_DONE_CH1_ST_CLR - Configures whether or not to clear PDMA_AXI_evt_out_done_ch1 trigger status.\\0: Invalid, No effect\\1: Clear - 14 - 1 - write-only - - - PDMA_AXI_EVT_OUT_DONE_CH2_ST_CLR - Configures whether or not to clear PDMA_AXI_evt_out_done_ch2 trigger status.\\0: Invalid, No effect\\1: Clear - 15 - 1 - write-only - - - PDMA_AXI_EVT_OUT_EOF_CH0_ST_CLR - Configures whether or not to clear PDMA_AXI_evt_out_eof_ch0 trigger status.\\0: Invalid, No effect\\1: Clear - 16 - 1 - write-only - - - PDMA_AXI_EVT_OUT_EOF_CH1_ST_CLR - Configures whether or not to clear PDMA_AXI_evt_out_eof_ch1 trigger status.\\0: Invalid, No effect\\1: Clear - 17 - 1 - write-only - - - PDMA_AXI_EVT_OUT_EOF_CH2_ST_CLR - Configures whether or not to clear PDMA_AXI_evt_out_eof_ch2 trigger status.\\0: Invalid, No effect\\1: Clear - 18 - 1 - write-only - - - PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST_CLR - Configures whether or not to clear PDMA_AXI_evt_out_total_eof_ch0 trigger status.\\0: Invalid, No effect\\1: Clear - 19 - 1 - write-only - - - PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST_CLR - Configures whether or not to clear PDMA_AXI_evt_out_total_eof_ch1 trigger status.\\0: Invalid, No effect\\1: Clear - 20 - 1 - write-only - - - PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST_CLR - Configures whether or not to clear PDMA_AXI_evt_out_total_eof_ch2 trigger status.\\0: Invalid, No effect\\1: Clear - 21 - 1 - write-only - - - PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR - Configures whether or not to clear PDMA_AXI_evt_out_fifo_empty_ch0 trigger status.\\0: Invalid, No effect\\1: Clear - 22 - 1 - write-only - - - PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR - Configures whether or not to clear PDMA_AXI_evt_out_fifo_empty_ch1 trigger status.\\0: Invalid, No effect\\1: Clear - 23 - 1 - write-only - - - PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR - Configures whether or not to clear PDMA_AXI_evt_out_fifo_empty_ch2 trigger status.\\0: Invalid, No effect\\1: Clear - 24 - 1 - write-only - - - PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST_CLR - Configures whether or not to clear PDMA_AXI_evt_out_fifo_full_ch0 trigger status.\\0: Invalid, No effect\\1: Clear - 25 - 1 - write-only - - - PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST_CLR - Configures whether or not to clear PDMA_AXI_evt_out_fifo_full_ch1 trigger status.\\0: Invalid, No effect\\1: Clear - 26 - 1 - write-only - - - PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST_CLR - Configures whether or not to clear PDMA_AXI_evt_out_fifo_full_ch2 trigger status.\\0: Invalid, No effect\\1: Clear - 27 - 1 - write-only - - - PMU_EVT_SLEEP_WEEKUP_ST_CLR - Configures whether or not to clear PMU_evt_sleep_weekup trigger status.\\0: Invalid, No effect\\1: Clear - 28 - 1 - write-only - - - DMA2D_EVT_IN_DONE_CH0_ST_CLR - Configures whether or not to clear DMA2D_evt_in_done_ch0 trigger status.\\0: Invalid, No effect\\1: Clear - 29 - 1 - write-only - - - DMA2D_EVT_IN_DONE_CH1_ST_CLR - Configures whether or not to clear DMA2D_evt_in_done_ch1 trigger status.\\0: Invalid, No effect\\1: Clear - 30 - 1 - write-only - - - DMA2D_EVT_IN_SUC_EOF_CH0_ST_CLR - Configures whether or not to clear DMA2D_evt_in_suc_eof_ch0 trigger status.\\0: Invalid, No effect\\1: Clear - 31 - 1 - write-only - - - - - EVT_ST7 - Events trigger status register - 0x1E0 - 0x20 - - - DMA2D_EVT_IN_SUC_EOF_CH1_ST - Represents DMA2D_evt_in_suc_eof_ch1 trigger status.\\0: Not triggered\\1: Triggered - 0 - 1 - read-write - - - DMA2D_EVT_OUT_DONE_CH0_ST - Represents DMA2D_evt_out_done_ch0 trigger status.\\0: Not triggered\\1: Triggered - 1 - 1 - read-write - - - DMA2D_EVT_OUT_DONE_CH1_ST - Represents DMA2D_evt_out_done_ch1 trigger status.\\0: Not triggered\\1: Triggered - 2 - 1 - read-write - - - DMA2D_EVT_OUT_DONE_CH2_ST - Represents DMA2D_evt_out_done_ch2 trigger status.\\0: Not triggered\\1: Triggered - 3 - 1 - read-write - - - DMA2D_EVT_OUT_EOF_CH0_ST - Represents DMA2D_evt_out_eof_ch0 trigger status.\\0: Not triggered\\1: Triggered - 4 - 1 - read-write - - - DMA2D_EVT_OUT_EOF_CH1_ST - Represents DMA2D_evt_out_eof_ch1 trigger status.\\0: Not triggered\\1: Triggered - 5 - 1 - read-write - - - DMA2D_EVT_OUT_EOF_CH2_ST - Represents DMA2D_evt_out_eof_ch2 trigger status.\\0: Not triggered\\1: Triggered - 6 - 1 - read-write - - - DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST - Represents DMA2D_evt_out_total_eof_ch0 trigger status.\\0: Not triggered\\1: Triggered - 7 - 1 - read-write - - - DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST - Represents DMA2D_evt_out_total_eof_ch1 trigger status.\\0: Not triggered\\1: Triggered - 8 - 1 - read-write - - - DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST - Represents DMA2D_evt_out_total_eof_ch2 trigger status.\\0: Not triggered\\1: Triggered - 9 - 1 - read-write - - - - - EVT_ST7_CLR - Events trigger status clear register - 0x1E4 - 0x20 - - - DMA2D_EVT_IN_SUC_EOF_CH1_ST_CLR - Configures whether or not to clear DMA2D_evt_in_suc_eof_ch1 trigger status.\\0: Invalid, No effect\\1: Clear - 0 - 1 - write-only - - - DMA2D_EVT_OUT_DONE_CH0_ST_CLR - Configures whether or not to clear DMA2D_evt_out_done_ch0 trigger status.\\0: Invalid, No effect\\1: Clear - 1 - 1 - write-only - - - DMA2D_EVT_OUT_DONE_CH1_ST_CLR - Configures whether or not to clear DMA2D_evt_out_done_ch1 trigger status.\\0: Invalid, No effect\\1: Clear - 2 - 1 - write-only - - - DMA2D_EVT_OUT_DONE_CH2_ST_CLR - Configures whether or not to clear DMA2D_evt_out_done_ch2 trigger status.\\0: Invalid, No effect\\1: Clear - 3 - 1 - write-only - - - DMA2D_EVT_OUT_EOF_CH0_ST_CLR - Configures whether or not to clear DMA2D_evt_out_eof_ch0 trigger status.\\0: Invalid, No effect\\1: Clear - 4 - 1 - write-only - - - DMA2D_EVT_OUT_EOF_CH1_ST_CLR - Configures whether or not to clear DMA2D_evt_out_eof_ch1 trigger status.\\0: Invalid, No effect\\1: Clear - 5 - 1 - write-only - - - DMA2D_EVT_OUT_EOF_CH2_ST_CLR - Configures whether or not to clear DMA2D_evt_out_eof_ch2 trigger status.\\0: Invalid, No effect\\1: Clear - 6 - 1 - write-only - - - DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST_CLR - Configures whether or not to clear DMA2D_evt_out_total_eof_ch0 trigger status.\\0: Invalid, No effect\\1: Clear - 7 - 1 - write-only - - - DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST_CLR - Configures whether or not to clear DMA2D_evt_out_total_eof_ch1 trigger status.\\0: Invalid, No effect\\1: Clear - 8 - 1 - write-only - - - DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST_CLR - Configures whether or not to clear DMA2D_evt_out_total_eof_ch2 trigger status.\\0: Invalid, No effect\\1: Clear - 9 - 1 - write-only - - - - - TASK_ST0 - Tasks trigger status register - 0x1E8 - 0x20 - - - GPIO_TASK_CH0_SET_ST - Represents GPIO_task_ch0_set trigger status.\\0: Not triggered\\1: Triggered - 0 - 1 - read-write - - - GPIO_TASK_CH1_SET_ST - Represents GPIO_task_ch1_set trigger status.\\0: Not triggered\\1: Triggered - 1 - 1 - read-write - - - GPIO_TASK_CH2_SET_ST - Represents GPIO_task_ch2_set trigger status.\\0: Not triggered\\1: Triggered - 2 - 1 - read-write - - - GPIO_TASK_CH3_SET_ST - Represents GPIO_task_ch3_set trigger status.\\0: Not triggered\\1: Triggered - 3 - 1 - read-write - - - GPIO_TASK_CH4_SET_ST - Represents GPIO_task_ch4_set trigger status.\\0: Not triggered\\1: Triggered - 4 - 1 - read-write - - - GPIO_TASK_CH5_SET_ST - Represents GPIO_task_ch5_set trigger status.\\0: Not triggered\\1: Triggered - 5 - 1 - read-write - - - GPIO_TASK_CH6_SET_ST - Represents GPIO_task_ch6_set trigger status.\\0: Not triggered\\1: Triggered - 6 - 1 - read-write - - - GPIO_TASK_CH7_SET_ST - Represents GPIO_task_ch7_set trigger status.\\0: Not triggered\\1: Triggered - 7 - 1 - read-write - - - GPIO_TASK_CH0_CLEAR_ST - Represents GPIO_task_ch0_clear trigger status.\\0: Not triggered\\1: Triggered - 8 - 1 - read-write - - - GPIO_TASK_CH1_CLEAR_ST - Represents GPIO_task_ch1_clear trigger status.\\0: Not triggered\\1: Triggered - 9 - 1 - read-write - - - GPIO_TASK_CH2_CLEAR_ST - Represents GPIO_task_ch2_clear trigger status.\\0: Not triggered\\1: Triggered - 10 - 1 - read-write - - - GPIO_TASK_CH3_CLEAR_ST - Represents GPIO_task_ch3_clear trigger status.\\0: Not triggered\\1: Triggered - 11 - 1 - read-write - - - GPIO_TASK_CH4_CLEAR_ST - Represents GPIO_task_ch4_clear trigger status.\\0: Not triggered\\1: Triggered - 12 - 1 - read-write - - - GPIO_TASK_CH5_CLEAR_ST - Represents GPIO_task_ch5_clear trigger status.\\0: Not triggered\\1: Triggered - 13 - 1 - read-write - - - GPIO_TASK_CH6_CLEAR_ST - Represents GPIO_task_ch6_clear trigger status.\\0: Not triggered\\1: Triggered - 14 - 1 - read-write - - - GPIO_TASK_CH7_CLEAR_ST - Represents GPIO_task_ch7_clear trigger status.\\0: Not triggered\\1: Triggered - 15 - 1 - read-write - - - GPIO_TASK_CH0_TOGGLE_ST - Represents GPIO_task_ch0_toggle trigger status.\\0: Not triggered\\1: Triggered - 16 - 1 - read-write - - - GPIO_TASK_CH1_TOGGLE_ST - Represents GPIO_task_ch1_toggle trigger status.\\0: Not triggered\\1: Triggered - 17 - 1 - read-write - - - GPIO_TASK_CH2_TOGGLE_ST - Represents GPIO_task_ch2_toggle trigger status.\\0: Not triggered\\1: Triggered - 18 - 1 - read-write - - - GPIO_TASK_CH3_TOGGLE_ST - Represents GPIO_task_ch3_toggle trigger status.\\0: Not triggered\\1: Triggered - 19 - 1 - read-write - - - GPIO_TASK_CH4_TOGGLE_ST - Represents GPIO_task_ch4_toggle trigger status.\\0: Not triggered\\1: Triggered - 20 - 1 - read-write - - - GPIO_TASK_CH5_TOGGLE_ST - Represents GPIO_task_ch5_toggle trigger status.\\0: Not triggered\\1: Triggered - 21 - 1 - read-write - - - GPIO_TASK_CH6_TOGGLE_ST - Represents GPIO_task_ch6_toggle trigger status.\\0: Not triggered\\1: Triggered - 22 - 1 - read-write - - - GPIO_TASK_CH7_TOGGLE_ST - Represents GPIO_task_ch7_toggle trigger status.\\0: Not triggered\\1: Triggered - 23 - 1 - read-write - - - LEDC_TASK_TIMER0_RES_UPDATE_ST - Represents LEDC_task_timer0_res_update trigger status.\\0: Not triggered\\1: Triggered - 24 - 1 - read-write - - - LEDC_TASK_TIMER1_RES_UPDATE_ST - Represents LEDC_task_timer1_res_update trigger status.\\0: Not triggered\\1: Triggered - 25 - 1 - read-write - - - LEDC_TASK_TIMER2_RES_UPDATE_ST - Represents LEDC_task_timer2_res_update trigger status.\\0: Not triggered\\1: Triggered - 26 - 1 - read-write - - - LEDC_TASK_TIMER3_RES_UPDATE_ST - Represents LEDC_task_timer3_res_update trigger status.\\0: Not triggered\\1: Triggered - 27 - 1 - read-write - - - LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST - Represents LEDC_task_duty_scale_update_ch0 trigger status.\\0: Not triggered\\1: Triggered - 28 - 1 - read-write - - - LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST - Represents LEDC_task_duty_scale_update_ch1 trigger status.\\0: Not triggered\\1: Triggered - 29 - 1 - read-write - - - LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST - Represents LEDC_task_duty_scale_update_ch2 trigger status.\\0: Not triggered\\1: Triggered - 30 - 1 - read-write - - - LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST - Represents LEDC_task_duty_scale_update_ch3 trigger status.\\0: Not triggered\\1: Triggered - 31 - 1 - read-write - - - - - TASK_ST0_CLR - Tasks trigger status clear register - 0x1EC - 0x20 - - - GPIO_TASK_CH0_SET_ST_CLR - Configures whether or not to clear GPIO_task_ch0_set trigger status.\\0: Invalid, No effect\\1: Clear - 0 - 1 - write-only - - - GPIO_TASK_CH1_SET_ST_CLR - Configures whether or not to clear GPIO_task_ch1_set trigger status.\\0: Invalid, No effect\\1: Clear - 1 - 1 - write-only - - - GPIO_TASK_CH2_SET_ST_CLR - Configures whether or not to clear GPIO_task_ch2_set trigger status.\\0: Invalid, No effect\\1: Clear - 2 - 1 - write-only - - - GPIO_TASK_CH3_SET_ST_CLR - Configures whether or not to clear GPIO_task_ch3_set trigger status.\\0: Invalid, No effect\\1: Clear - 3 - 1 - write-only - - - GPIO_TASK_CH4_SET_ST_CLR - Configures whether or not to clear GPIO_task_ch4_set trigger status.\\0: Invalid, No effect\\1: Clear - 4 - 1 - write-only - - - GPIO_TASK_CH5_SET_ST_CLR - Configures whether or not to clear GPIO_task_ch5_set trigger status.\\0: Invalid, No effect\\1: Clear - 5 - 1 - write-only - - - GPIO_TASK_CH6_SET_ST_CLR - Configures whether or not to clear GPIO_task_ch6_set trigger status.\\0: Invalid, No effect\\1: Clear - 6 - 1 - write-only - - - GPIO_TASK_CH7_SET_ST_CLR - Configures whether or not to clear GPIO_task_ch7_set trigger status.\\0: Invalid, No effect\\1: Clear - 7 - 1 - write-only - - - GPIO_TASK_CH0_CLEAR_ST_CLR - Configures whether or not to clear GPIO_task_ch0_clear trigger status.\\0: Invalid, No effect\\1: Clear - 8 - 1 - write-only - - - GPIO_TASK_CH1_CLEAR_ST_CLR - Configures whether or not to clear GPIO_task_ch1_clear trigger status.\\0: Invalid, No effect\\1: Clear - 9 - 1 - write-only - - - GPIO_TASK_CH2_CLEAR_ST_CLR - Configures whether or not to clear GPIO_task_ch2_clear trigger status.\\0: Invalid, No effect\\1: Clear - 10 - 1 - write-only - - - GPIO_TASK_CH3_CLEAR_ST_CLR - Configures whether or not to clear GPIO_task_ch3_clear trigger status.\\0: Invalid, No effect\\1: Clear - 11 - 1 - write-only - - - GPIO_TASK_CH4_CLEAR_ST_CLR - Configures whether or not to clear GPIO_task_ch4_clear trigger status.\\0: Invalid, No effect\\1: Clear - 12 - 1 - write-only - - - GPIO_TASK_CH5_CLEAR_ST_CLR - Configures whether or not to clear GPIO_task_ch5_clear trigger status.\\0: Invalid, No effect\\1: Clear - 13 - 1 - write-only - - - GPIO_TASK_CH6_CLEAR_ST_CLR - Configures whether or not to clear GPIO_task_ch6_clear trigger status.\\0: Invalid, No effect\\1: Clear - 14 - 1 - write-only - - - GPIO_TASK_CH7_CLEAR_ST_CLR - Configures whether or not to clear GPIO_task_ch7_clear trigger status.\\0: Invalid, No effect\\1: Clear - 15 - 1 - write-only - - - GPIO_TASK_CH0_TOGGLE_ST_CLR - Configures whether or not to clear GPIO_task_ch0_toggle trigger status.\\0: Invalid, No effect\\1: Clear - 16 - 1 - write-only - - - GPIO_TASK_CH1_TOGGLE_ST_CLR - Configures whether or not to clear GPIO_task_ch1_toggle trigger status.\\0: Invalid, No effect\\1: Clear - 17 - 1 - write-only - - - GPIO_TASK_CH2_TOGGLE_ST_CLR - Configures whether or not to clear GPIO_task_ch2_toggle trigger status.\\0: Invalid, No effect\\1: Clear - 18 - 1 - write-only - - - GPIO_TASK_CH3_TOGGLE_ST_CLR - Configures whether or not to clear GPIO_task_ch3_toggle trigger status.\\0: Invalid, No effect\\1: Clear - 19 - 1 - write-only - - - GPIO_TASK_CH4_TOGGLE_ST_CLR - Configures whether or not to clear GPIO_task_ch4_toggle trigger status.\\0: Invalid, No effect\\1: Clear - 20 - 1 - write-only - - - GPIO_TASK_CH5_TOGGLE_ST_CLR - Configures whether or not to clear GPIO_task_ch5_toggle trigger status.\\0: Invalid, No effect\\1: Clear - 21 - 1 - write-only - - - GPIO_TASK_CH6_TOGGLE_ST_CLR - Configures whether or not to clear GPIO_task_ch6_toggle trigger status.\\0: Invalid, No effect\\1: Clear - 22 - 1 - write-only - - - GPIO_TASK_CH7_TOGGLE_ST_CLR - Configures whether or not to clear GPIO_task_ch7_toggle trigger status.\\0: Invalid, No effect\\1: Clear - 23 - 1 - write-only - - - LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR - Configures whether or not to clear LEDC_task_timer0_res_update trigger status.\\0: Invalid, No effect\\1: Clear - 24 - 1 - write-only - - - LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR - Configures whether or not to clear LEDC_task_timer1_res_update trigger status.\\0: Invalid, No effect\\1: Clear - 25 - 1 - write-only - - - LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR - Configures whether or not to clear LEDC_task_timer2_res_update trigger status.\\0: Invalid, No effect\\1: Clear - 26 - 1 - write-only - - - LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR - Configures whether or not to clear LEDC_task_timer3_res_update trigger status.\\0: Invalid, No effect\\1: Clear - 27 - 1 - write-only - - - LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR - Configures whether or not to clear LEDC_task_duty_scale_update_ch0 trigger status.\\0: Invalid, No effect\\1: Clear - 28 - 1 - write-only - - - LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR - Configures whether or not to clear LEDC_task_duty_scale_update_ch1 trigger status.\\0: Invalid, No effect\\1: Clear - 29 - 1 - write-only - - - LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR - Configures whether or not to clear LEDC_task_duty_scale_update_ch2 trigger status.\\0: Invalid, No effect\\1: Clear - 30 - 1 - write-only - - - LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR - Configures whether or not to clear LEDC_task_duty_scale_update_ch3 trigger status.\\0: Invalid, No effect\\1: Clear - 31 - 1 - write-only - - - - - TASK_ST1 - Tasks trigger status register - 0x1F0 - 0x20 - - - LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST - Represents LEDC_task_duty_scale_update_ch4 trigger status.\\0: Not triggered\\1: Triggered - 0 - 1 - read-write - - - LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST - Represents LEDC_task_duty_scale_update_ch5 trigger status.\\0: Not triggered\\1: Triggered - 1 - 1 - read-write - - - LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST - Represents LEDC_task_duty_scale_update_ch6 trigger status.\\0: Not triggered\\1: Triggered - 2 - 1 - read-write - - - LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST - Represents LEDC_task_duty_scale_update_ch7 trigger status.\\0: Not triggered\\1: Triggered - 3 - 1 - read-write - - - LEDC_TASK_TIMER0_CAP_ST - Represents LEDC_task_timer0_cap trigger status.\\0: Not triggered\\1: Triggered - 4 - 1 - read-write - - - LEDC_TASK_TIMER1_CAP_ST - Represents LEDC_task_timer1_cap trigger status.\\0: Not triggered\\1: Triggered - 5 - 1 - read-write - - - LEDC_TASK_TIMER2_CAP_ST - Represents LEDC_task_timer2_cap trigger status.\\0: Not triggered\\1: Triggered - 6 - 1 - read-write - - - LEDC_TASK_TIMER3_CAP_ST - Represents LEDC_task_timer3_cap trigger status.\\0: Not triggered\\1: Triggered - 7 - 1 - read-write - - - LEDC_TASK_SIG_OUT_DIS_CH0_ST - Represents LEDC_task_sig_out_dis_ch0 trigger status.\\0: Not triggered\\1: Triggered - 8 - 1 - read-write - - - LEDC_TASK_SIG_OUT_DIS_CH1_ST - Represents LEDC_task_sig_out_dis_ch1 trigger status.\\0: Not triggered\\1: Triggered - 9 - 1 - read-write - - - LEDC_TASK_SIG_OUT_DIS_CH2_ST - Represents LEDC_task_sig_out_dis_ch2 trigger status.\\0: Not triggered\\1: Triggered - 10 - 1 - read-write - - - LEDC_TASK_SIG_OUT_DIS_CH3_ST - Represents LEDC_task_sig_out_dis_ch3 trigger status.\\0: Not triggered\\1: Triggered - 11 - 1 - read-write - - - LEDC_TASK_SIG_OUT_DIS_CH4_ST - Represents LEDC_task_sig_out_dis_ch4 trigger status.\\0: Not triggered\\1: Triggered - 12 - 1 - read-write - - - LEDC_TASK_SIG_OUT_DIS_CH5_ST - Represents LEDC_task_sig_out_dis_ch5 trigger status.\\0: Not triggered\\1: Triggered - 13 - 1 - read-write - - - LEDC_TASK_SIG_OUT_DIS_CH6_ST - Represents LEDC_task_sig_out_dis_ch6 trigger status.\\0: Not triggered\\1: Triggered - 14 - 1 - read-write - - - LEDC_TASK_SIG_OUT_DIS_CH7_ST - Represents LEDC_task_sig_out_dis_ch7 trigger status.\\0: Not triggered\\1: Triggered - 15 - 1 - read-write - - - LEDC_TASK_OVF_CNT_RST_CH0_ST - Represents LEDC_task_ovf_cnt_rst_ch0 trigger status.\\0: Not triggered\\1: Triggered - 16 - 1 - read-write - - - LEDC_TASK_OVF_CNT_RST_CH1_ST - Represents LEDC_task_ovf_cnt_rst_ch1 trigger status.\\0: Not triggered\\1: Triggered - 17 - 1 - read-write - - - LEDC_TASK_OVF_CNT_RST_CH2_ST - Represents LEDC_task_ovf_cnt_rst_ch2 trigger status.\\0: Not triggered\\1: Triggered - 18 - 1 - read-write - - - LEDC_TASK_OVF_CNT_RST_CH3_ST - Represents LEDC_task_ovf_cnt_rst_ch3 trigger status.\\0: Not triggered\\1: Triggered - 19 - 1 - read-write - - - LEDC_TASK_OVF_CNT_RST_CH4_ST - Represents LEDC_task_ovf_cnt_rst_ch4 trigger status.\\0: Not triggered\\1: Triggered - 20 - 1 - read-write - - - LEDC_TASK_OVF_CNT_RST_CH5_ST - Represents LEDC_task_ovf_cnt_rst_ch5 trigger status.\\0: Not triggered\\1: Triggered - 21 - 1 - read-write - - - LEDC_TASK_OVF_CNT_RST_CH6_ST - Represents LEDC_task_ovf_cnt_rst_ch6 trigger status.\\0: Not triggered\\1: Triggered - 22 - 1 - read-write - - - LEDC_TASK_OVF_CNT_RST_CH7_ST - Represents LEDC_task_ovf_cnt_rst_ch7 trigger status.\\0: Not triggered\\1: Triggered - 23 - 1 - read-write - - - LEDC_TASK_TIMER0_RST_ST - Represents LEDC_task_timer0_rst trigger status.\\0: Not triggered\\1: Triggered - 24 - 1 - read-write - - - LEDC_TASK_TIMER1_RST_ST - Represents LEDC_task_timer1_rst trigger status.\\0: Not triggered\\1: Triggered - 25 - 1 - read-write - - - LEDC_TASK_TIMER2_RST_ST - Represents LEDC_task_timer2_rst trigger status.\\0: Not triggered\\1: Triggered - 26 - 1 - read-write - - - LEDC_TASK_TIMER3_RST_ST - Represents LEDC_task_timer3_rst trigger status.\\0: Not triggered\\1: Triggered - 27 - 1 - read-write - - - LEDC_TASK_TIMER0_RESUME_ST - Represents LEDC_task_timer0_resume trigger status.\\0: Not triggered\\1: Triggered - 28 - 1 - read-write - - - LEDC_TASK_TIMER1_RESUME_ST - Represents LEDC_task_timer1_resume trigger status.\\0: Not triggered\\1: Triggered - 29 - 1 - read-write - - - LEDC_TASK_TIMER2_RESUME_ST - Represents LEDC_task_timer2_resume trigger status.\\0: Not triggered\\1: Triggered - 30 - 1 - read-write - - - LEDC_TASK_TIMER3_RESUME_ST - Represents LEDC_task_timer3_resume trigger status.\\0: Not triggered\\1: Triggered - 31 - 1 - read-write - - - - - TASK_ST1_CLR - Tasks trigger status clear register - 0x1F4 - 0x20 - - - LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR - Configures whether or not to clear LEDC_task_duty_scale_update_ch4 trigger status.\\0: Invalid, No effect\\1: Clear - 0 - 1 - write-only - - - LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR - Configures whether or not to clear LEDC_task_duty_scale_update_ch5 trigger status.\\0: Invalid, No effect\\1: Clear - 1 - 1 - write-only - - - LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST_CLR - Configures whether or not to clear LEDC_task_duty_scale_update_ch6 trigger status.\\0: Invalid, No effect\\1: Clear - 2 - 1 - write-only - - - LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST_CLR - Configures whether or not to clear LEDC_task_duty_scale_update_ch7 trigger status.\\0: Invalid, No effect\\1: Clear - 3 - 1 - write-only - - - LEDC_TASK_TIMER0_CAP_ST_CLR - Configures whether or not to clear LEDC_task_timer0_cap trigger status.\\0: Invalid, No effect\\1: Clear - 4 - 1 - write-only - - - LEDC_TASK_TIMER1_CAP_ST_CLR - Configures whether or not to clear LEDC_task_timer1_cap trigger status.\\0: Invalid, No effect\\1: Clear - 5 - 1 - write-only - - - LEDC_TASK_TIMER2_CAP_ST_CLR - Configures whether or not to clear LEDC_task_timer2_cap trigger status.\\0: Invalid, No effect\\1: Clear - 6 - 1 - write-only - - - LEDC_TASK_TIMER3_CAP_ST_CLR - Configures whether or not to clear LEDC_task_timer3_cap trigger status.\\0: Invalid, No effect\\1: Clear - 7 - 1 - write-only - - - LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR - Configures whether or not to clear LEDC_task_sig_out_dis_ch0 trigger status.\\0: Invalid, No effect\\1: Clear - 8 - 1 - write-only - - - LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR - Configures whether or not to clear LEDC_task_sig_out_dis_ch1 trigger status.\\0: Invalid, No effect\\1: Clear - 9 - 1 - write-only - - - LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR - Configures whether or not to clear LEDC_task_sig_out_dis_ch2 trigger status.\\0: Invalid, No effect\\1: Clear - 10 - 1 - write-only - - - LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR - Configures whether or not to clear LEDC_task_sig_out_dis_ch3 trigger status.\\0: Invalid, No effect\\1: Clear - 11 - 1 - write-only - - - LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR - Configures whether or not to clear LEDC_task_sig_out_dis_ch4 trigger status.\\0: Invalid, No effect\\1: Clear - 12 - 1 - write-only - - - LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR - Configures whether or not to clear LEDC_task_sig_out_dis_ch5 trigger status.\\0: Invalid, No effect\\1: Clear - 13 - 1 - write-only - - - LEDC_TASK_SIG_OUT_DIS_CH6_ST_CLR - Configures whether or not to clear LEDC_task_sig_out_dis_ch6 trigger status.\\0: Invalid, No effect\\1: Clear - 14 - 1 - write-only - - - LEDC_TASK_SIG_OUT_DIS_CH7_ST_CLR - Configures whether or not to clear LEDC_task_sig_out_dis_ch7 trigger status.\\0: Invalid, No effect\\1: Clear - 15 - 1 - write-only - - - LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR - Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch0 trigger status.\\0: Invalid, No effect\\1: Clear - 16 - 1 - write-only - - - LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR - Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch1 trigger status.\\0: Invalid, No effect\\1: Clear - 17 - 1 - write-only - - - LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR - Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch2 trigger status.\\0: Invalid, No effect\\1: Clear - 18 - 1 - write-only - - - LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR - Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch3 trigger status.\\0: Invalid, No effect\\1: Clear - 19 - 1 - write-only - - - LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR - Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch4 trigger status.\\0: Invalid, No effect\\1: Clear - 20 - 1 - write-only - - - LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR - Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch5 trigger status.\\0: Invalid, No effect\\1: Clear - 21 - 1 - write-only - - - LEDC_TASK_OVF_CNT_RST_CH6_ST_CLR - Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch6 trigger status.\\0: Invalid, No effect\\1: Clear - 22 - 1 - write-only - - - LEDC_TASK_OVF_CNT_RST_CH7_ST_CLR - Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch7 trigger status.\\0: Invalid, No effect\\1: Clear - 23 - 1 - write-only - - - LEDC_TASK_TIMER0_RST_ST_CLR - Configures whether or not to clear LEDC_task_timer0_rst trigger status.\\0: Invalid, No effect\\1: Clear - 24 - 1 - write-only - - - LEDC_TASK_TIMER1_RST_ST_CLR - Configures whether or not to clear LEDC_task_timer1_rst trigger status.\\0: Invalid, No effect\\1: Clear - 25 - 1 - write-only - - - LEDC_TASK_TIMER2_RST_ST_CLR - Configures whether or not to clear LEDC_task_timer2_rst trigger status.\\0: Invalid, No effect\\1: Clear - 26 - 1 - write-only - - - LEDC_TASK_TIMER3_RST_ST_CLR - Configures whether or not to clear LEDC_task_timer3_rst trigger status.\\0: Invalid, No effect\\1: Clear - 27 - 1 - write-only - - - LEDC_TASK_TIMER0_RESUME_ST_CLR - Configures whether or not to clear LEDC_task_timer0_resume trigger status.\\0: Invalid, No effect\\1: Clear - 28 - 1 - write-only - - - LEDC_TASK_TIMER1_RESUME_ST_CLR - Configures whether or not to clear LEDC_task_timer1_resume trigger status.\\0: Invalid, No effect\\1: Clear - 29 - 1 - write-only - - - LEDC_TASK_TIMER2_RESUME_ST_CLR - Configures whether or not to clear LEDC_task_timer2_resume trigger status.\\0: Invalid, No effect\\1: Clear - 30 - 1 - write-only - - - LEDC_TASK_TIMER3_RESUME_ST_CLR - Configures whether or not to clear LEDC_task_timer3_resume trigger status.\\0: Invalid, No effect\\1: Clear - 31 - 1 - write-only - - - - - TASK_ST2 - Tasks trigger status register - 0x1F8 - 0x20 - - - LEDC_TASK_TIMER0_PAUSE_ST - Represents LEDC_task_timer0_pause trigger status.\\0: Not triggered\\1: Triggered - 0 - 1 - read-write - - - LEDC_TASK_TIMER1_PAUSE_ST - Represents LEDC_task_timer1_pause trigger status.\\0: Not triggered\\1: Triggered - 1 - 1 - read-write - - - LEDC_TASK_TIMER2_PAUSE_ST - Represents LEDC_task_timer2_pause trigger status.\\0: Not triggered\\1: Triggered - 2 - 1 - read-write - - - LEDC_TASK_TIMER3_PAUSE_ST - Represents LEDC_task_timer3_pause trigger status.\\0: Not triggered\\1: Triggered - 3 - 1 - read-write - - - LEDC_TASK_GAMMA_RESTART_CH0_ST - Represents LEDC_task_gamma_restart_ch0 trigger status.\\0: Not triggered\\1: Triggered - 4 - 1 - read-write - - - LEDC_TASK_GAMMA_RESTART_CH1_ST - Represents LEDC_task_gamma_restart_ch1 trigger status.\\0: Not triggered\\1: Triggered - 5 - 1 - read-write - - - LEDC_TASK_GAMMA_RESTART_CH2_ST - Represents LEDC_task_gamma_restart_ch2 trigger status.\\0: Not triggered\\1: Triggered - 6 - 1 - read-write - - - LEDC_TASK_GAMMA_RESTART_CH3_ST - Represents LEDC_task_gamma_restart_ch3 trigger status.\\0: Not triggered\\1: Triggered - 7 - 1 - read-write - - - LEDC_TASK_GAMMA_RESTART_CH4_ST - Represents LEDC_task_gamma_restart_ch4 trigger status.\\0: Not triggered\\1: Triggered - 8 - 1 - read-write - - - LEDC_TASK_GAMMA_RESTART_CH5_ST - Represents LEDC_task_gamma_restart_ch5 trigger status.\\0: Not triggered\\1: Triggered - 9 - 1 - read-write - - - LEDC_TASK_GAMMA_RESTART_CH6_ST - Represents LEDC_task_gamma_restart_ch6 trigger status.\\0: Not triggered\\1: Triggered - 10 - 1 - read-write - - - LEDC_TASK_GAMMA_RESTART_CH7_ST - Represents LEDC_task_gamma_restart_ch7 trigger status.\\0: Not triggered\\1: Triggered - 11 - 1 - read-write - - - LEDC_TASK_GAMMA_PAUSE_CH0_ST - Represents LEDC_task_gamma_pause_ch0 trigger status.\\0: Not triggered\\1: Triggered - 12 - 1 - read-write - - - LEDC_TASK_GAMMA_PAUSE_CH1_ST - Represents LEDC_task_gamma_pause_ch1 trigger status.\\0: Not triggered\\1: Triggered - 13 - 1 - read-write - - - LEDC_TASK_GAMMA_PAUSE_CH2_ST - Represents LEDC_task_gamma_pause_ch2 trigger status.\\0: Not triggered\\1: Triggered - 14 - 1 - read-write - - - LEDC_TASK_GAMMA_PAUSE_CH3_ST - Represents LEDC_task_gamma_pause_ch3 trigger status.\\0: Not triggered\\1: Triggered - 15 - 1 - read-write - - - LEDC_TASK_GAMMA_PAUSE_CH4_ST - Represents LEDC_task_gamma_pause_ch4 trigger status.\\0: Not triggered\\1: Triggered - 16 - 1 - read-write - - - LEDC_TASK_GAMMA_PAUSE_CH5_ST - Represents LEDC_task_gamma_pause_ch5 trigger status.\\0: Not triggered\\1: Triggered - 17 - 1 - read-write - - - LEDC_TASK_GAMMA_PAUSE_CH6_ST - Represents LEDC_task_gamma_pause_ch6 trigger status.\\0: Not triggered\\1: Triggered - 18 - 1 - read-write - - - LEDC_TASK_GAMMA_PAUSE_CH7_ST - Represents LEDC_task_gamma_pause_ch7 trigger status.\\0: Not triggered\\1: Triggered - 19 - 1 - read-write - - - LEDC_TASK_GAMMA_RESUME_CH0_ST - Represents LEDC_task_gamma_resume_ch0 trigger status.\\0: Not triggered\\1: Triggered - 20 - 1 - read-write - - - LEDC_TASK_GAMMA_RESUME_CH1_ST - Represents LEDC_task_gamma_resume_ch1 trigger status.\\0: Not triggered\\1: Triggered - 21 - 1 - read-write - - - LEDC_TASK_GAMMA_RESUME_CH2_ST - Represents LEDC_task_gamma_resume_ch2 trigger status.\\0: Not triggered\\1: Triggered - 22 - 1 - read-write - - - LEDC_TASK_GAMMA_RESUME_CH3_ST - Represents LEDC_task_gamma_resume_ch3 trigger status.\\0: Not triggered\\1: Triggered - 23 - 1 - read-write - - - LEDC_TASK_GAMMA_RESUME_CH4_ST - Represents LEDC_task_gamma_resume_ch4 trigger status.\\0: Not triggered\\1: Triggered - 24 - 1 - read-write - - - LEDC_TASK_GAMMA_RESUME_CH5_ST - Represents LEDC_task_gamma_resume_ch5 trigger status.\\0: Not triggered\\1: Triggered - 25 - 1 - read-write - - - LEDC_TASK_GAMMA_RESUME_CH6_ST - Represents LEDC_task_gamma_resume_ch6 trigger status.\\0: Not triggered\\1: Triggered - 26 - 1 - read-write - - - LEDC_TASK_GAMMA_RESUME_CH7_ST - Represents LEDC_task_gamma_resume_ch7 trigger status.\\0: Not triggered\\1: Triggered - 27 - 1 - read-write - - - TG0_TASK_CNT_START_TIMER0_ST - Represents TG0_task_cnt_start_timer0 trigger status.\\0: Not triggered\\1: Triggered - 28 - 1 - read-write - - - TG0_TASK_ALARM_START_TIMER0_ST - Represents TG0_task_alarm_start_timer0 trigger status.\\0: Not triggered\\1: Triggered - 29 - 1 - read-write - - - TG0_TASK_CNT_STOP_TIMER0_ST - Represents TG0_task_cnt_stop_timer0 trigger status.\\0: Not triggered\\1: Triggered - 30 - 1 - read-write - - - TG0_TASK_CNT_RELOAD_TIMER0_ST - Represents TG0_task_cnt_reload_timer0 trigger status.\\0: Not triggered\\1: Triggered - 31 - 1 - read-write - - - - - TASK_ST2_CLR - Tasks trigger status clear register - 0x1FC - 0x20 - - - LEDC_TASK_TIMER0_PAUSE_ST_CLR - Configures whether or not to clear LEDC_task_timer0_pause trigger status.\\0: Invalid, No effect\\1: Clear - 0 - 1 - write-only - - - LEDC_TASK_TIMER1_PAUSE_ST_CLR - Configures whether or not to clear LEDC_task_timer1_pause trigger status.\\0: Invalid, No effect\\1: Clear - 1 - 1 - write-only - - - LEDC_TASK_TIMER2_PAUSE_ST_CLR - Configures whether or not to clear LEDC_task_timer2_pause trigger status.\\0: Invalid, No effect\\1: Clear - 2 - 1 - write-only - - - LEDC_TASK_TIMER3_PAUSE_ST_CLR - Configures whether or not to clear LEDC_task_timer3_pause trigger status.\\0: Invalid, No effect\\1: Clear - 3 - 1 - write-only - - - LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR - Configures whether or not to clear LEDC_task_gamma_restart_ch0 trigger status.\\0: Invalid, No effect\\1: Clear - 4 - 1 - write-only - - - LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR - Configures whether or not to clear LEDC_task_gamma_restart_ch1 trigger status.\\0: Invalid, No effect\\1: Clear - 5 - 1 - write-only - - - LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR - Configures whether or not to clear LEDC_task_gamma_restart_ch2 trigger status.\\0: Invalid, No effect\\1: Clear - 6 - 1 - write-only - - - LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR - Configures whether or not to clear LEDC_task_gamma_restart_ch3 trigger status.\\0: Invalid, No effect\\1: Clear - 7 - 1 - write-only - - - LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR - Configures whether or not to clear LEDC_task_gamma_restart_ch4 trigger status.\\0: Invalid, No effect\\1: Clear - 8 - 1 - write-only - - - LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR - Configures whether or not to clear LEDC_task_gamma_restart_ch5 trigger status.\\0: Invalid, No effect\\1: Clear - 9 - 1 - write-only - - - LEDC_TASK_GAMMA_RESTART_CH6_ST_CLR - Configures whether or not to clear LEDC_task_gamma_restart_ch6 trigger status.\\0: Invalid, No effect\\1: Clear - 10 - 1 - write-only - - - LEDC_TASK_GAMMA_RESTART_CH7_ST_CLR - Configures whether or not to clear LEDC_task_gamma_restart_ch7 trigger status.\\0: Invalid, No effect\\1: Clear - 11 - 1 - write-only - - - LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR - Configures whether or not to clear LEDC_task_gamma_pause_ch0 trigger status.\\0: Invalid, No effect\\1: Clear - 12 - 1 - write-only - - - LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR - Configures whether or not to clear LEDC_task_gamma_pause_ch1 trigger status.\\0: Invalid, No effect\\1: Clear - 13 - 1 - write-only - - - LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR - Configures whether or not to clear LEDC_task_gamma_pause_ch2 trigger status.\\0: Invalid, No effect\\1: Clear - 14 - 1 - write-only - - - LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR - Configures whether or not to clear LEDC_task_gamma_pause_ch3 trigger status.\\0: Invalid, No effect\\1: Clear - 15 - 1 - write-only - - - LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR - Configures whether or not to clear LEDC_task_gamma_pause_ch4 trigger status.\\0: Invalid, No effect\\1: Clear - 16 - 1 - write-only - - - LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR - Configures whether or not to clear LEDC_task_gamma_pause_ch5 trigger status.\\0: Invalid, No effect\\1: Clear - 17 - 1 - write-only - - - LEDC_TASK_GAMMA_PAUSE_CH6_ST_CLR - Configures whether or not to clear LEDC_task_gamma_pause_ch6 trigger status.\\0: Invalid, No effect\\1: Clear - 18 - 1 - write-only - - - LEDC_TASK_GAMMA_PAUSE_CH7_ST_CLR - Configures whether or not to clear LEDC_task_gamma_pause_ch7 trigger status.\\0: Invalid, No effect\\1: Clear - 19 - 1 - write-only - - - LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR - Configures whether or not to clear LEDC_task_gamma_resume_ch0 trigger status.\\0: Invalid, No effect\\1: Clear - 20 - 1 - write-only - - - LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR - Configures whether or not to clear LEDC_task_gamma_resume_ch1 trigger status.\\0: Invalid, No effect\\1: Clear - 21 - 1 - write-only - - - LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR - Configures whether or not to clear LEDC_task_gamma_resume_ch2 trigger status.\\0: Invalid, No effect\\1: Clear - 22 - 1 - write-only - - - LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR - Configures whether or not to clear LEDC_task_gamma_resume_ch3 trigger status.\\0: Invalid, No effect\\1: Clear - 23 - 1 - write-only - - - LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR - Configures whether or not to clear LEDC_task_gamma_resume_ch4 trigger status.\\0: Invalid, No effect\\1: Clear - 24 - 1 - write-only - - - LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR - Configures whether or not to clear LEDC_task_gamma_resume_ch5 trigger status.\\0: Invalid, No effect\\1: Clear - 25 - 1 - write-only - - - LEDC_TASK_GAMMA_RESUME_CH6_ST_CLR - Configures whether or not to clear LEDC_task_gamma_resume_ch6 trigger status.\\0: Invalid, No effect\\1: Clear - 26 - 1 - write-only - - - LEDC_TASK_GAMMA_RESUME_CH7_ST_CLR - Configures whether or not to clear LEDC_task_gamma_resume_ch7 trigger status.\\0: Invalid, No effect\\1: Clear - 27 - 1 - write-only - - - TG0_TASK_CNT_START_TIMER0_ST_CLR - Configures whether or not to clear TG0_task_cnt_start_timer0 trigger status.\\0: Invalid, No effect\\1: Clear - 28 - 1 - write-only - - - TG0_TASK_ALARM_START_TIMER0_ST_CLR - Configures whether or not to clear TG0_task_alarm_start_timer0 trigger status.\\0: Invalid, No effect\\1: Clear - 29 - 1 - write-only - - - TG0_TASK_CNT_STOP_TIMER0_ST_CLR - Configures whether or not to clear TG0_task_cnt_stop_timer0 trigger status.\\0: Invalid, No effect\\1: Clear - 30 - 1 - write-only - - - TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR - Configures whether or not to clear TG0_task_cnt_reload_timer0 trigger status.\\0: Invalid, No effect\\1: Clear - 31 - 1 - write-only - - - - - TASK_ST3 - Tasks trigger status register - 0x200 - 0x20 - - - TG0_TASK_CNT_CAP_TIMER0_ST - Represents TG0_task_cnt_cap_timer0 trigger status.\\0: Not triggered\\1: Triggered - 0 - 1 - read-write - - - TG0_TASK_CNT_START_TIMER1_ST - Represents TG0_task_cnt_start_timer1 trigger status.\\0: Not triggered\\1: Triggered - 1 - 1 - read-write - - - TG0_TASK_ALARM_START_TIMER1_ST - Represents TG0_task_alarm_start_timer1 trigger status.\\0: Not triggered\\1: Triggered - 2 - 1 - read-write - - - TG0_TASK_CNT_STOP_TIMER1_ST - Represents TG0_task_cnt_stop_timer1 trigger status.\\0: Not triggered\\1: Triggered - 3 - 1 - read-write - - - TG0_TASK_CNT_RELOAD_TIMER1_ST - Represents TG0_task_cnt_reload_timer1 trigger status.\\0: Not triggered\\1: Triggered - 4 - 1 - read-write - - - TG0_TASK_CNT_CAP_TIMER1_ST - Represents TG0_task_cnt_cap_timer1 trigger status.\\0: Not triggered\\1: Triggered - 5 - 1 - read-write - - - TG1_TASK_CNT_START_TIMER0_ST - Represents TG1_task_cnt_start_timer0 trigger status.\\0: Not triggered\\1: Triggered - 6 - 1 - read-write - - - TG1_TASK_ALARM_START_TIMER0_ST - Represents TG1_task_alarm_start_timer0 trigger status.\\0: Not triggered\\1: Triggered - 7 - 1 - read-write - - - TG1_TASK_CNT_STOP_TIMER0_ST - Represents TG1_task_cnt_stop_timer0 trigger status.\\0: Not triggered\\1: Triggered - 8 - 1 - read-write - - - TG1_TASK_CNT_RELOAD_TIMER0_ST - Represents TG1_task_cnt_reload_timer0 trigger status.\\0: Not triggered\\1: Triggered - 9 - 1 - read-write - - - TG1_TASK_CNT_CAP_TIMER0_ST - Represents TG1_task_cnt_cap_timer0 trigger status.\\0: Not triggered\\1: Triggered - 10 - 1 - read-write - - - TG1_TASK_CNT_START_TIMER1_ST - Represents TG1_task_cnt_start_timer1 trigger status.\\0: Not triggered\\1: Triggered - 11 - 1 - read-write - - - TG1_TASK_ALARM_START_TIMER1_ST - Represents TG1_task_alarm_start_timer1 trigger status.\\0: Not triggered\\1: Triggered - 12 - 1 - read-write - - - TG1_TASK_CNT_STOP_TIMER1_ST - Represents TG1_task_cnt_stop_timer1 trigger status.\\0: Not triggered\\1: Triggered - 13 - 1 - read-write - - - TG1_TASK_CNT_RELOAD_TIMER1_ST - Represents TG1_task_cnt_reload_timer1 trigger status.\\0: Not triggered\\1: Triggered - 14 - 1 - read-write - - - TG1_TASK_CNT_CAP_TIMER1_ST - Represents TG1_task_cnt_cap_timer1 trigger status.\\0: Not triggered\\1: Triggered - 15 - 1 - read-write - - - MCPWM0_TASK_CMPR0_A_UP_ST - Represents MCPWM0_task_cmpr0_a_up trigger status.\\0: Not triggered\\1: Triggered - 16 - 1 - read-write - - - MCPWM0_TASK_CMPR1_A_UP_ST - Represents MCPWM0_task_cmpr1_a_up trigger status.\\0: Not triggered\\1: Triggered - 17 - 1 - read-write - - - MCPWM0_TASK_CMPR2_A_UP_ST - Represents MCPWM0_task_cmpr2_a_up trigger status.\\0: Not triggered\\1: Triggered - 18 - 1 - read-write - - - MCPWM0_TASK_CMPR0_B_UP_ST - Represents MCPWM0_task_cmpr0_b_up trigger status.\\0: Not triggered\\1: Triggered - 19 - 1 - read-write - - - MCPWM0_TASK_CMPR1_B_UP_ST - Represents MCPWM0_task_cmpr1_b_up trigger status.\\0: Not triggered\\1: Triggered - 20 - 1 - read-write - - - MCPWM0_TASK_CMPR2_B_UP_ST - Represents MCPWM0_task_cmpr2_b_up trigger status.\\0: Not triggered\\1: Triggered - 21 - 1 - read-write - - - MCPWM0_TASK_GEN_STOP_ST - Represents MCPWM0_task_gen_stop trigger status.\\0: Not triggered\\1: Triggered - 22 - 1 - read-write - - - MCPWM0_TASK_TIMER0_SYN_ST - Represents MCPWM0_task_timer0_syn trigger status.\\0: Not triggered\\1: Triggered - 23 - 1 - read-write - - - MCPWM0_TASK_TIMER1_SYN_ST - Represents MCPWM0_task_timer1_syn trigger status.\\0: Not triggered\\1: Triggered - 24 - 1 - read-write - - - MCPWM0_TASK_TIMER2_SYN_ST - Represents MCPWM0_task_timer2_syn trigger status.\\0: Not triggered\\1: Triggered - 25 - 1 - read-write - - - MCPWM0_TASK_TIMER0_PERIOD_UP_ST - Represents MCPWM0_task_timer0_period_up trigger status.\\0: Not triggered\\1: Triggered - 26 - 1 - read-write - - - MCPWM0_TASK_TIMER1_PERIOD_UP_ST - Represents MCPWM0_task_timer1_period_up trigger status.\\0: Not triggered\\1: Triggered - 27 - 1 - read-write - - - MCPWM0_TASK_TIMER2_PERIOD_UP_ST - Represents MCPWM0_task_timer2_period_up trigger status.\\0: Not triggered\\1: Triggered - 28 - 1 - read-write - - - MCPWM0_TASK_TZ0_OST_ST - Represents MCPWM0_task_tz0_ost trigger status.\\0: Not triggered\\1: Triggered - 29 - 1 - read-write - - - MCPWM0_TASK_TZ1_OST_ST - Represents MCPWM0_task_tz1_ost trigger status.\\0: Not triggered\\1: Triggered - 30 - 1 - read-write - - - MCPWM0_TASK_TZ2_OST_ST - Represents MCPWM0_task_tz2_ost trigger status.\\0: Not triggered\\1: Triggered - 31 - 1 - read-write - - - - - TASK_ST3_CLR - Tasks trigger status clear register - 0x204 - 0x20 - - - TG0_TASK_CNT_CAP_TIMER0_ST_CLR - Configures whether or not to clear TG0_task_cnt_cap_timer0 trigger status.\\0: Invalid, No effect\\1: Clear - 0 - 1 - write-only - - - TG0_TASK_CNT_START_TIMER1_ST_CLR - Configures whether or not to clear TG0_task_cnt_start_timer1 trigger status.\\0: Invalid, No effect\\1: Clear - 1 - 1 - write-only - - - TG0_TASK_ALARM_START_TIMER1_ST_CLR - Configures whether or not to clear TG0_task_alarm_start_timer1 trigger status.\\0: Invalid, No effect\\1: Clear - 2 - 1 - write-only - - - TG0_TASK_CNT_STOP_TIMER1_ST_CLR - Configures whether or not to clear TG0_task_cnt_stop_timer1 trigger status.\\0: Invalid, No effect\\1: Clear - 3 - 1 - write-only - - - TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR - Configures whether or not to clear TG0_task_cnt_reload_timer1 trigger status.\\0: Invalid, No effect\\1: Clear - 4 - 1 - write-only - - - TG0_TASK_CNT_CAP_TIMER1_ST_CLR - Configures whether or not to clear TG0_task_cnt_cap_timer1 trigger status.\\0: Invalid, No effect\\1: Clear - 5 - 1 - write-only - - - TG1_TASK_CNT_START_TIMER0_ST_CLR - Configures whether or not to clear TG1_task_cnt_start_timer0 trigger status.\\0: Invalid, No effect\\1: Clear - 6 - 1 - write-only - - - TG1_TASK_ALARM_START_TIMER0_ST_CLR - Configures whether or not to clear TG1_task_alarm_start_timer0 trigger status.\\0: Invalid, No effect\\1: Clear - 7 - 1 - write-only - - - TG1_TASK_CNT_STOP_TIMER0_ST_CLR - Configures whether or not to clear TG1_task_cnt_stop_timer0 trigger status.\\0: Invalid, No effect\\1: Clear - 8 - 1 - write-only - - - TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR - Configures whether or not to clear TG1_task_cnt_reload_timer0 trigger status.\\0: Invalid, No effect\\1: Clear - 9 - 1 - write-only - - - TG1_TASK_CNT_CAP_TIMER0_ST_CLR - Configures whether or not to clear TG1_task_cnt_cap_timer0 trigger status.\\0: Invalid, No effect\\1: Clear - 10 - 1 - write-only - - - TG1_TASK_CNT_START_TIMER1_ST_CLR - Configures whether or not to clear TG1_task_cnt_start_timer1 trigger status.\\0: Invalid, No effect\\1: Clear - 11 - 1 - write-only - - - TG1_TASK_ALARM_START_TIMER1_ST_CLR - Configures whether or not to clear TG1_task_alarm_start_timer1 trigger status.\\0: Invalid, No effect\\1: Clear - 12 - 1 - write-only - - - TG1_TASK_CNT_STOP_TIMER1_ST_CLR - Configures whether or not to clear TG1_task_cnt_stop_timer1 trigger status.\\0: Invalid, No effect\\1: Clear - 13 - 1 - write-only - - - TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR - Configures whether or not to clear TG1_task_cnt_reload_timer1 trigger status.\\0: Invalid, No effect\\1: Clear - 14 - 1 - write-only - - - TG1_TASK_CNT_CAP_TIMER1_ST_CLR - Configures whether or not to clear TG1_task_cnt_cap_timer1 trigger status.\\0: Invalid, No effect\\1: Clear - 15 - 1 - write-only - - - MCPWM0_TASK_CMPR0_A_UP_ST_CLR - Configures whether or not to clear MCPWM0_task_cmpr0_a_up trigger status.\\0: Invalid, No effect\\1: Clear - 16 - 1 - write-only - - - MCPWM0_TASK_CMPR1_A_UP_ST_CLR - Configures whether or not to clear MCPWM0_task_cmpr1_a_up trigger status.\\0: Invalid, No effect\\1: Clear - 17 - 1 - write-only - - - MCPWM0_TASK_CMPR2_A_UP_ST_CLR - Configures whether or not to clear MCPWM0_task_cmpr2_a_up trigger status.\\0: Invalid, No effect\\1: Clear - 18 - 1 - write-only - - - MCPWM0_TASK_CMPR0_B_UP_ST_CLR - Configures whether or not to clear MCPWM0_task_cmpr0_b_up trigger status.\\0: Invalid, No effect\\1: Clear - 19 - 1 - write-only - - - MCPWM0_TASK_CMPR1_B_UP_ST_CLR - Configures whether or not to clear MCPWM0_task_cmpr1_b_up trigger status.\\0: Invalid, No effect\\1: Clear - 20 - 1 - write-only - - - MCPWM0_TASK_CMPR2_B_UP_ST_CLR - Configures whether or not to clear MCPWM0_task_cmpr2_b_up trigger status.\\0: Invalid, No effect\\1: Clear - 21 - 1 - write-only - - - MCPWM0_TASK_GEN_STOP_ST_CLR - Configures whether or not to clear MCPWM0_task_gen_stop trigger status.\\0: Invalid, No effect\\1: Clear - 22 - 1 - write-only - - - MCPWM0_TASK_TIMER0_SYN_ST_CLR - Configures whether or not to clear MCPWM0_task_timer0_syn trigger status.\\0: Invalid, No effect\\1: Clear - 23 - 1 - write-only - - - MCPWM0_TASK_TIMER1_SYN_ST_CLR - Configures whether or not to clear MCPWM0_task_timer1_syn trigger status.\\0: Invalid, No effect\\1: Clear - 24 - 1 - write-only - - - MCPWM0_TASK_TIMER2_SYN_ST_CLR - Configures whether or not to clear MCPWM0_task_timer2_syn trigger status.\\0: Invalid, No effect\\1: Clear - 25 - 1 - write-only - - - MCPWM0_TASK_TIMER0_PERIOD_UP_ST_CLR - Configures whether or not to clear MCPWM0_task_timer0_period_up trigger status.\\0: Invalid, No effect\\1: Clear - 26 - 1 - write-only - - - MCPWM0_TASK_TIMER1_PERIOD_UP_ST_CLR - Configures whether or not to clear MCPWM0_task_timer1_period_up trigger status.\\0: Invalid, No effect\\1: Clear - 27 - 1 - write-only - - - MCPWM0_TASK_TIMER2_PERIOD_UP_ST_CLR - Configures whether or not to clear MCPWM0_task_timer2_period_up trigger status.\\0: Invalid, No effect\\1: Clear - 28 - 1 - write-only - - - MCPWM0_TASK_TZ0_OST_ST_CLR - Configures whether or not to clear MCPWM0_task_tz0_ost trigger status.\\0: Invalid, No effect\\1: Clear - 29 - 1 - write-only - - - MCPWM0_TASK_TZ1_OST_ST_CLR - Configures whether or not to clear MCPWM0_task_tz1_ost trigger status.\\0: Invalid, No effect\\1: Clear - 30 - 1 - write-only - - - MCPWM0_TASK_TZ2_OST_ST_CLR - Configures whether or not to clear MCPWM0_task_tz2_ost trigger status.\\0: Invalid, No effect\\1: Clear - 31 - 1 - write-only - - - - - TASK_ST4 - Tasks trigger status register - 0x208 - 0x20 - - - MCPWM0_TASK_CLR0_OST_ST - Represents MCPWM0_task_clr0_ost trigger status.\\0: Not triggered\\1: Triggered - 0 - 1 - read-write - - - MCPWM0_TASK_CLR1_OST_ST - Represents MCPWM0_task_clr1_ost trigger status.\\0: Not triggered\\1: Triggered - 1 - 1 - read-write - - - MCPWM0_TASK_CLR2_OST_ST - Represents MCPWM0_task_clr2_ost trigger status.\\0: Not triggered\\1: Triggered - 2 - 1 - read-write - - - MCPWM0_TASK_CAP0_ST - Represents MCPWM0_task_cap0 trigger status.\\0: Not triggered\\1: Triggered - 3 - 1 - read-write - - - MCPWM0_TASK_CAP1_ST - Represents MCPWM0_task_cap1 trigger status.\\0: Not triggered\\1: Triggered - 4 - 1 - read-write - - - MCPWM0_TASK_CAP2_ST - Represents MCPWM0_task_cap2 trigger status.\\0: Not triggered\\1: Triggered - 5 - 1 - read-write - - - MCPWM1_TASK_CMPR0_A_UP_ST - Represents MCPWM1_task_cmpr0_a_up trigger status.\\0: Not triggered\\1: Triggered - 6 - 1 - read-write - - - MCPWM1_TASK_CMPR1_A_UP_ST - Represents MCPWM1_task_cmpr1_a_up trigger status.\\0: Not triggered\\1: Triggered - 7 - 1 - read-write - - - MCPWM1_TASK_CMPR2_A_UP_ST - Represents MCPWM1_task_cmpr2_a_up trigger status.\\0: Not triggered\\1: Triggered - 8 - 1 - read-write - - - MCPWM1_TASK_CMPR0_B_UP_ST - Represents MCPWM1_task_cmpr0_b_up trigger status.\\0: Not triggered\\1: Triggered - 9 - 1 - read-write - - - MCPWM1_TASK_CMPR1_B_UP_ST - Represents MCPWM1_task_cmpr1_b_up trigger status.\\0: Not triggered\\1: Triggered - 10 - 1 - read-write - - - MCPWM1_TASK_CMPR2_B_UP_ST - Represents MCPWM1_task_cmpr2_b_up trigger status.\\0: Not triggered\\1: Triggered - 11 - 1 - read-write - - - MCPWM1_TASK_GEN_STOP_ST - Represents MCPWM1_task_gen_stop trigger status.\\0: Not triggered\\1: Triggered - 12 - 1 - read-write - - - MCPWM1_TASK_TIMER0_SYN_ST - Represents MCPWM1_task_timer0_syn trigger status.\\0: Not triggered\\1: Triggered - 13 - 1 - read-write - - - MCPWM1_TASK_TIMER1_SYN_ST - Represents MCPWM1_task_timer1_syn trigger status.\\0: Not triggered\\1: Triggered - 14 - 1 - read-write - - - MCPWM1_TASK_TIMER2_SYN_ST - Represents MCPWM1_task_timer2_syn trigger status.\\0: Not triggered\\1: Triggered - 15 - 1 - read-write - - - MCPWM1_TASK_TIMER0_PERIOD_UP_ST - Represents MCPWM1_task_timer0_period_up trigger status.\\0: Not triggered\\1: Triggered - 16 - 1 - read-write - - - MCPWM1_TASK_TIMER1_PERIOD_UP_ST - Represents MCPWM1_task_timer1_period_up trigger status.\\0: Not triggered\\1: Triggered - 17 - 1 - read-write - - - MCPWM1_TASK_TIMER2_PERIOD_UP_ST - Represents MCPWM1_task_timer2_period_up trigger status.\\0: Not triggered\\1: Triggered - 18 - 1 - read-write - - - MCPWM1_TASK_TZ0_OST_ST - Represents MCPWM1_task_tz0_ost trigger status.\\0: Not triggered\\1: Triggered - 19 - 1 - read-write - - - MCPWM1_TASK_TZ1_OST_ST - Represents MCPWM1_task_tz1_ost trigger status.\\0: Not triggered\\1: Triggered - 20 - 1 - read-write - - - MCPWM1_TASK_TZ2_OST_ST - Represents MCPWM1_task_tz2_ost trigger status.\\0: Not triggered\\1: Triggered - 21 - 1 - read-write - - - MCPWM1_TASK_CLR0_OST_ST - Represents MCPWM1_task_clr0_ost trigger status.\\0: Not triggered\\1: Triggered - 22 - 1 - read-write - - - MCPWM1_TASK_CLR1_OST_ST - Represents MCPWM1_task_clr1_ost trigger status.\\0: Not triggered\\1: Triggered - 23 - 1 - read-write - - - MCPWM1_TASK_CLR2_OST_ST - Represents MCPWM1_task_clr2_ost trigger status.\\0: Not triggered\\1: Triggered - 24 - 1 - read-write - - - MCPWM1_TASK_CAP0_ST - Represents MCPWM1_task_cap0 trigger status.\\0: Not triggered\\1: Triggered - 25 - 1 - read-write - - - MCPWM1_TASK_CAP1_ST - Represents MCPWM1_task_cap1 trigger status.\\0: Not triggered\\1: Triggered - 26 - 1 - read-write - - - MCPWM1_TASK_CAP2_ST - Represents MCPWM1_task_cap2 trigger status.\\0: Not triggered\\1: Triggered - 27 - 1 - read-write - - - ADC_TASK_SAMPLE0_ST - Represents ADC_task_sample0 trigger status.\\0: Not triggered\\1: Triggered - 28 - 1 - read-write - - - ADC_TASK_SAMPLE1_ST - Represents ADC_task_sample1 trigger status.\\0: Not triggered\\1: Triggered - 29 - 1 - read-write - - - ADC_TASK_START0_ST - Represents ADC_task_start0 trigger status.\\0: Not triggered\\1: Triggered - 30 - 1 - read-write - - - ADC_TASK_STOP0_ST - Represents ADC_task_stop0 trigger status.\\0: Not triggered\\1: Triggered - 31 - 1 - read-write - - - - - TASK_ST4_CLR - Tasks trigger status clear register - 0x20C - 0x20 - - - MCPWM0_TASK_CLR0_OST_ST_CLR - Configures whether or not to clear MCPWM0_task_clr0_ost trigger status.\\0: Invalid, No effect\\1: Clear - 0 - 1 - write-only - - - MCPWM0_TASK_CLR1_OST_ST_CLR - Configures whether or not to clear MCPWM0_task_clr1_ost trigger status.\\0: Invalid, No effect\\1: Clear - 1 - 1 - write-only - - - MCPWM0_TASK_CLR2_OST_ST_CLR - Configures whether or not to clear MCPWM0_task_clr2_ost trigger status.\\0: Invalid, No effect\\1: Clear - 2 - 1 - write-only - - - MCPWM0_TASK_CAP0_ST_CLR - Configures whether or not to clear MCPWM0_task_cap0 trigger status.\\0: Invalid, No effect\\1: Clear - 3 - 1 - write-only - - - MCPWM0_TASK_CAP1_ST_CLR - Configures whether or not to clear MCPWM0_task_cap1 trigger status.\\0: Invalid, No effect\\1: Clear - 4 - 1 - write-only - - - MCPWM0_TASK_CAP2_ST_CLR - Configures whether or not to clear MCPWM0_task_cap2 trigger status.\\0: Invalid, No effect\\1: Clear - 5 - 1 - write-only - - - MCPWM1_TASK_CMPR0_A_UP_ST_CLR - Configures whether or not to clear MCPWM1_task_cmpr0_a_up trigger status.\\0: Invalid, No effect\\1: Clear - 6 - 1 - write-only - - - MCPWM1_TASK_CMPR1_A_UP_ST_CLR - Configures whether or not to clear MCPWM1_task_cmpr1_a_up trigger status.\\0: Invalid, No effect\\1: Clear - 7 - 1 - write-only - - - MCPWM1_TASK_CMPR2_A_UP_ST_CLR - Configures whether or not to clear MCPWM1_task_cmpr2_a_up trigger status.\\0: Invalid, No effect\\1: Clear - 8 - 1 - write-only - - - MCPWM1_TASK_CMPR0_B_UP_ST_CLR - Configures whether or not to clear MCPWM1_task_cmpr0_b_up trigger status.\\0: Invalid, No effect\\1: Clear - 9 - 1 - write-only - - - MCPWM1_TASK_CMPR1_B_UP_ST_CLR - Configures whether or not to clear MCPWM1_task_cmpr1_b_up trigger status.\\0: Invalid, No effect\\1: Clear - 10 - 1 - write-only - - - MCPWM1_TASK_CMPR2_B_UP_ST_CLR - Configures whether or not to clear MCPWM1_task_cmpr2_b_up trigger status.\\0: Invalid, No effect\\1: Clear - 11 - 1 - write-only - - - MCPWM1_TASK_GEN_STOP_ST_CLR - Configures whether or not to clear MCPWM1_task_gen_stop trigger status.\\0: Invalid, No effect\\1: Clear - 12 - 1 - write-only - - - MCPWM1_TASK_TIMER0_SYN_ST_CLR - Configures whether or not to clear MCPWM1_task_timer0_syn trigger status.\\0: Invalid, No effect\\1: Clear - 13 - 1 - write-only - - - MCPWM1_TASK_TIMER1_SYN_ST_CLR - Configures whether or not to clear MCPWM1_task_timer1_syn trigger status.\\0: Invalid, No effect\\1: Clear - 14 - 1 - write-only - - - MCPWM1_TASK_TIMER2_SYN_ST_CLR - Configures whether or not to clear MCPWM1_task_timer2_syn trigger status.\\0: Invalid, No effect\\1: Clear - 15 - 1 - write-only - - - MCPWM1_TASK_TIMER0_PERIOD_UP_ST_CLR - Configures whether or not to clear MCPWM1_task_timer0_period_up trigger status.\\0: Invalid, No effect\\1: Clear - 16 - 1 - write-only - - - MCPWM1_TASK_TIMER1_PERIOD_UP_ST_CLR - Configures whether or not to clear MCPWM1_task_timer1_period_up trigger status.\\0: Invalid, No effect\\1: Clear - 17 - 1 - write-only - - - MCPWM1_TASK_TIMER2_PERIOD_UP_ST_CLR - Configures whether or not to clear MCPWM1_task_timer2_period_up trigger status.\\0: Invalid, No effect\\1: Clear - 18 - 1 - write-only - - - MCPWM1_TASK_TZ0_OST_ST_CLR - Configures whether or not to clear MCPWM1_task_tz0_ost trigger status.\\0: Invalid, No effect\\1: Clear - 19 - 1 - write-only - - - MCPWM1_TASK_TZ1_OST_ST_CLR - Configures whether or not to clear MCPWM1_task_tz1_ost trigger status.\\0: Invalid, No effect\\1: Clear - 20 - 1 - write-only - - - MCPWM1_TASK_TZ2_OST_ST_CLR - Configures whether or not to clear MCPWM1_task_tz2_ost trigger status.\\0: Invalid, No effect\\1: Clear - 21 - 1 - write-only - - - MCPWM1_TASK_CLR0_OST_ST_CLR - Configures whether or not to clear MCPWM1_task_clr0_ost trigger status.\\0: Invalid, No effect\\1: Clear - 22 - 1 - write-only - - - MCPWM1_TASK_CLR1_OST_ST_CLR - Configures whether or not to clear MCPWM1_task_clr1_ost trigger status.\\0: Invalid, No effect\\1: Clear - 23 - 1 - write-only - - - MCPWM1_TASK_CLR2_OST_ST_CLR - Configures whether or not to clear MCPWM1_task_clr2_ost trigger status.\\0: Invalid, No effect\\1: Clear - 24 - 1 - write-only - - - MCPWM1_TASK_CAP0_ST_CLR - Configures whether or not to clear MCPWM1_task_cap0 trigger status.\\0: Invalid, No effect\\1: Clear - 25 - 1 - write-only - - - MCPWM1_TASK_CAP1_ST_CLR - Configures whether or not to clear MCPWM1_task_cap1 trigger status.\\0: Invalid, No effect\\1: Clear - 26 - 1 - write-only - - - MCPWM1_TASK_CAP2_ST_CLR - Configures whether or not to clear MCPWM1_task_cap2 trigger status.\\0: Invalid, No effect\\1: Clear - 27 - 1 - write-only - - - ADC_TASK_SAMPLE0_ST_CLR - Configures whether or not to clear ADC_task_sample0 trigger status.\\0: Invalid, No effect\\1: Clear - 28 - 1 - write-only - - - ADC_TASK_SAMPLE1_ST_CLR - Configures whether or not to clear ADC_task_sample1 trigger status.\\0: Invalid, No effect\\1: Clear - 29 - 1 - write-only - - - ADC_TASK_START0_ST_CLR - Configures whether or not to clear ADC_task_start0 trigger status.\\0: Invalid, No effect\\1: Clear - 30 - 1 - write-only - - - ADC_TASK_STOP0_ST_CLR - Configures whether or not to clear ADC_task_stop0 trigger status.\\0: Invalid, No effect\\1: Clear - 31 - 1 - write-only - - - - - TASK_ST5 - Tasks trigger status register - 0x210 - 0x20 - - - REGDMA_TASK_START0_ST - Represents REGDMA_task_start0 trigger status.\\0: Not triggered\\1: Triggered - 0 - 1 - read-write - - - REGDMA_TASK_START1_ST - Represents REGDMA_task_start1 trigger status.\\0: Not triggered\\1: Triggered - 1 - 1 - read-write - - - REGDMA_TASK_START2_ST - Represents REGDMA_task_start2 trigger status.\\0: Not triggered\\1: Triggered - 2 - 1 - read-write - - - REGDMA_TASK_START3_ST - Represents REGDMA_task_start3 trigger status.\\0: Not triggered\\1: Triggered - 3 - 1 - read-write - - - TMPSNSR_TASK_START_SAMPLE_ST - Represents TMPSNSR_task_start_sample trigger status.\\0: Not triggered\\1: Triggered - 4 - 1 - read-write - - - TMPSNSR_TASK_STOP_SAMPLE_ST - Represents TMPSNSR_task_stop_sample trigger status.\\0: Not triggered\\1: Triggered - 5 - 1 - read-write - - - I2S0_TASK_START_RX_ST - Represents I2S0_task_start_rx trigger status.\\0: Not triggered\\1: Triggered - 6 - 1 - read-write - - - I2S0_TASK_START_TX_ST - Represents I2S0_task_start_tx trigger status.\\0: Not triggered\\1: Triggered - 7 - 1 - read-write - - - I2S0_TASK_STOP_RX_ST - Represents I2S0_task_stop_rx trigger status.\\0: Not triggered\\1: Triggered - 8 - 1 - read-write - - - I2S0_TASK_STOP_TX_ST - Represents I2S0_task_stop_tx trigger status.\\0: Not triggered\\1: Triggered - 9 - 1 - read-write - - - I2S1_TASK_START_RX_ST - Represents I2S1_task_start_rx trigger status.\\0: Not triggered\\1: Triggered - 10 - 1 - read-write - - - I2S1_TASK_START_TX_ST - Represents I2S1_task_start_tx trigger status.\\0: Not triggered\\1: Triggered - 11 - 1 - read-write - - - I2S1_TASK_STOP_RX_ST - Represents I2S1_task_stop_rx trigger status.\\0: Not triggered\\1: Triggered - 12 - 1 - read-write - - - I2S1_TASK_STOP_TX_ST - Represents I2S1_task_stop_tx trigger status.\\0: Not triggered\\1: Triggered - 13 - 1 - read-write - - - I2S2_TASK_START_RX_ST - Represents I2S2_task_start_rx trigger status.\\0: Not triggered\\1: Triggered - 14 - 1 - read-write - - - I2S2_TASK_START_TX_ST - Represents I2S2_task_start_tx trigger status.\\0: Not triggered\\1: Triggered - 15 - 1 - read-write - - - I2S2_TASK_STOP_RX_ST - Represents I2S2_task_stop_rx trigger status.\\0: Not triggered\\1: Triggered - 16 - 1 - read-write - - - I2S2_TASK_STOP_TX_ST - Represents I2S2_task_stop_tx trigger status.\\0: Not triggered\\1: Triggered - 17 - 1 - read-write - - - ULP_TASK_WAKEUP_CPU_ST - Represents ULP_task_wakeup_cpu trigger status.\\0: Not triggered\\1: Triggered - 18 - 1 - read-write - - - ULP_TASK_INT_CPU_ST - Represents ULP_task_int_cpu trigger status.\\0: Not triggered\\1: Triggered - 19 - 1 - read-write - - - RTC_TASK_START_ST - Represents RTC_task_start trigger status.\\0: Not triggered\\1: Triggered - 20 - 1 - read-write - - - RTC_TASK_STOP_ST - Represents RTC_task_stop trigger status.\\0: Not triggered\\1: Triggered - 21 - 1 - read-write - - - RTC_TASK_CLR_ST - Represents RTC_task_clr trigger status.\\0: Not triggered\\1: Triggered - 22 - 1 - read-write - - - RTC_TASK_TRIGGERFLW_ST - Represents RTC_task_triggerflw trigger status.\\0: Not triggered\\1: Triggered - 23 - 1 - read-write - - - PDMA_AHB_TASK_IN_START_CH0_ST - Represents PDMA_AHB_task_in_start_ch0 trigger status.\\0: Not triggered\\1: Triggered - 24 - 1 - read-write - - - PDMA_AHB_TASK_IN_START_CH1_ST - Represents PDMA_AHB_task_in_start_ch1 trigger status.\\0: Not triggered\\1: Triggered - 25 - 1 - read-write - - - PDMA_AHB_TASK_IN_START_CH2_ST - Represents PDMA_AHB_task_in_start_ch2 trigger status.\\0: Not triggered\\1: Triggered - 26 - 1 - read-write - - - PDMA_AHB_TASK_OUT_START_CH0_ST - Represents PDMA_AHB_task_out_start_ch0 trigger status.\\0: Not triggered\\1: Triggered - 27 - 1 - read-write - - - PDMA_AHB_TASK_OUT_START_CH1_ST - Represents PDMA_AHB_task_out_start_ch1 trigger status.\\0: Not triggered\\1: Triggered - 28 - 1 - read-write - - - PDMA_AHB_TASK_OUT_START_CH2_ST - Represents PDMA_AHB_task_out_start_ch2 trigger status.\\0: Not triggered\\1: Triggered - 29 - 1 - read-write - - - PDMA_AXI_TASK_IN_START_CH0_ST - Represents PDMA_AXI_task_in_start_ch0 trigger status.\\0: Not triggered\\1: Triggered - 30 - 1 - read-write - - - PDMA_AXI_TASK_IN_START_CH1_ST - Represents PDMA_AXI_task_in_start_ch1 trigger status.\\0: Not triggered\\1: Triggered - 31 - 1 - read-write - - - - - TASK_ST5_CLR - Tasks trigger status clear register - 0x214 - 0x20 - - - REGDMA_TASK_START0_ST_CLR - Configures whether or not to clear REGDMA_task_start0 trigger status.\\0: Invalid, No effect\\1: Clear - 0 - 1 - write-only - - - REGDMA_TASK_START1_ST_CLR - Configures whether or not to clear REGDMA_task_start1 trigger status.\\0: Invalid, No effect\\1: Clear - 1 - 1 - write-only - - - REGDMA_TASK_START2_ST_CLR - Configures whether or not to clear REGDMA_task_start2 trigger status.\\0: Invalid, No effect\\1: Clear - 2 - 1 - write-only - - - REGDMA_TASK_START3_ST_CLR - Configures whether or not to clear REGDMA_task_start3 trigger status.\\0: Invalid, No effect\\1: Clear - 3 - 1 - write-only - - - TMPSNSR_TASK_START_SAMPLE_ST_CLR - Configures whether or not to clear TMPSNSR_task_start_sample trigger status.\\0: Invalid, No effect\\1: Clear - 4 - 1 - write-only - - - TMPSNSR_TASK_STOP_SAMPLE_ST_CLR - Configures whether or not to clear TMPSNSR_task_stop_sample trigger status.\\0: Invalid, No effect\\1: Clear - 5 - 1 - write-only - - - I2S0_TASK_START_RX_ST_CLR - Configures whether or not to clear I2S0_task_start_rx trigger status.\\0: Invalid, No effect\\1: Clear - 6 - 1 - write-only - - - I2S0_TASK_START_TX_ST_CLR - Configures whether or not to clear I2S0_task_start_tx trigger status.\\0: Invalid, No effect\\1: Clear - 7 - 1 - write-only - - - I2S0_TASK_STOP_RX_ST_CLR - Configures whether or not to clear I2S0_task_stop_rx trigger status.\\0: Invalid, No effect\\1: Clear - 8 - 1 - write-only - - - I2S0_TASK_STOP_TX_ST_CLR - Configures whether or not to clear I2S0_task_stop_tx trigger status.\\0: Invalid, No effect\\1: Clear - 9 - 1 - write-only - - - I2S1_TASK_START_RX_ST_CLR - Configures whether or not to clear I2S1_task_start_rx trigger status.\\0: Invalid, No effect\\1: Clear - 10 - 1 - write-only - - - I2S1_TASK_START_TX_ST_CLR - Configures whether or not to clear I2S1_task_start_tx trigger status.\\0: Invalid, No effect\\1: Clear - 11 - 1 - write-only - - - I2S1_TASK_STOP_RX_ST_CLR - Configures whether or not to clear I2S1_task_stop_rx trigger status.\\0: Invalid, No effect\\1: Clear - 12 - 1 - write-only - - - I2S1_TASK_STOP_TX_ST_CLR - Configures whether or not to clear I2S1_task_stop_tx trigger status.\\0: Invalid, No effect\\1: Clear - 13 - 1 - write-only - - - I2S2_TASK_START_RX_ST_CLR - Configures whether or not to clear I2S2_task_start_rx trigger status.\\0: Invalid, No effect\\1: Clear - 14 - 1 - write-only - - - I2S2_TASK_START_TX_ST_CLR - Configures whether or not to clear I2S2_task_start_tx trigger status.\\0: Invalid, No effect\\1: Clear - 15 - 1 - write-only - - - I2S2_TASK_STOP_RX_ST_CLR - Configures whether or not to clear I2S2_task_stop_rx trigger status.\\0: Invalid, No effect\\1: Clear - 16 - 1 - write-only - - - I2S2_TASK_STOP_TX_ST_CLR - Configures whether or not to clear I2S2_task_stop_tx trigger status.\\0: Invalid, No effect\\1: Clear - 17 - 1 - write-only - - - ULP_TASK_WAKEUP_CPU_ST_CLR - Configures whether or not to clear ULP_task_wakeup_cpu trigger status.\\0: Invalid, No effect\\1: Clear - 18 - 1 - write-only - - - ULP_TASK_INT_CPU_ST_CLR - Configures whether or not to clear ULP_task_int_cpu trigger status.\\0: Invalid, No effect\\1: Clear - 19 - 1 - write-only - - - RTC_TASK_START_ST_CLR - Configures whether or not to clear RTC_task_start trigger status.\\0: Invalid, No effect\\1: Clear - 20 - 1 - write-only - - - RTC_TASK_STOP_ST_CLR - Configures whether or not to clear RTC_task_stop trigger status.\\0: Invalid, No effect\\1: Clear - 21 - 1 - write-only - - - RTC_TASK_CLR_ST_CLR - Configures whether or not to clear RTC_task_clr trigger status.\\0: Invalid, No effect\\1: Clear - 22 - 1 - write-only - - - RTC_TASK_TRIGGERFLW_ST_CLR - Configures whether or not to clear RTC_task_triggerflw trigger status.\\0: Invalid, No effect\\1: Clear - 23 - 1 - write-only - - - PDMA_AHB_TASK_IN_START_CH0_ST_CLR - Configures whether or not to clear PDMA_AHB_task_in_start_ch0 trigger status.\\0: Invalid, No effect\\1: Clear - 24 - 1 - write-only - - - PDMA_AHB_TASK_IN_START_CH1_ST_CLR - Configures whether or not to clear PDMA_AHB_task_in_start_ch1 trigger status.\\0: Invalid, No effect\\1: Clear - 25 - 1 - write-only - - - PDMA_AHB_TASK_IN_START_CH2_ST_CLR - Configures whether or not to clear PDMA_AHB_task_in_start_ch2 trigger status.\\0: Invalid, No effect\\1: Clear - 26 - 1 - write-only - - - PDMA_AHB_TASK_OUT_START_CH0_ST_CLR - Configures whether or not to clear PDMA_AHB_task_out_start_ch0 trigger status.\\0: Invalid, No effect\\1: Clear - 27 - 1 - write-only - - - PDMA_AHB_TASK_OUT_START_CH1_ST_CLR - Configures whether or not to clear PDMA_AHB_task_out_start_ch1 trigger status.\\0: Invalid, No effect\\1: Clear - 28 - 1 - write-only - - - PDMA_AHB_TASK_OUT_START_CH2_ST_CLR - Configures whether or not to clear PDMA_AHB_task_out_start_ch2 trigger status.\\0: Invalid, No effect\\1: Clear - 29 - 1 - write-only - - - PDMA_AXI_TASK_IN_START_CH0_ST_CLR - Configures whether or not to clear PDMA_AXI_task_in_start_ch0 trigger status.\\0: Invalid, No effect\\1: Clear - 30 - 1 - write-only - - - PDMA_AXI_TASK_IN_START_CH1_ST_CLR - Configures whether or not to clear PDMA_AXI_task_in_start_ch1 trigger status.\\0: Invalid, No effect\\1: Clear - 31 - 1 - write-only - - - - - TASK_ST6 - Tasks trigger status register - 0x218 - 0x20 - - - PDMA_AXI_TASK_IN_START_CH2_ST - Represents PDMA_AXI_task_in_start_ch2 trigger status.\\0: Not triggered\\1: Triggered - 0 - 1 - read-write - - - PDMA_AXI_TASK_OUT_START_CH0_ST - Represents PDMA_AXI_task_out_start_ch0 trigger status.\\0: Not triggered\\1: Triggered - 1 - 1 - read-write - - - PDMA_AXI_TASK_OUT_START_CH1_ST - Represents PDMA_AXI_task_out_start_ch1 trigger status.\\0: Not triggered\\1: Triggered - 2 - 1 - read-write - - - PDMA_AXI_TASK_OUT_START_CH2_ST - Represents PDMA_AXI_task_out_start_ch2 trigger status.\\0: Not triggered\\1: Triggered - 3 - 1 - read-write - - - PMU_TASK_SLEEP_REQ_ST - Represents PMU_task_sleep_req trigger status.\\0: Not triggered\\1: Triggered - 4 - 1 - read-write - - - DMA2D_TASK_IN_START_CH0_ST - Represents DMA2D_task_in_start_ch0 trigger status.\\0: Not triggered\\1: Triggered - 5 - 1 - read-write - - - DMA2D_TASK_IN_START_CH1_ST - Represents DMA2D_task_in_start_ch1 trigger status.\\0: Not triggered\\1: Triggered - 6 - 1 - read-write - - - DMA2D_TASK_IN_DSCR_READY_CH0_ST - Represents DMA2D_task_in_dscr_ready_ch0 trigger status.\\0: Not triggered\\1: Triggered - 7 - 1 - read-write - - - DMA2D_TASK_IN_DSCR_READY_CH1_ST - Represents DMA2D_task_in_dscr_ready_ch1 trigger status.\\0: Not triggered\\1: Triggered - 8 - 1 - read-write - - - DMA2D_TASK_OUT_START_CH0_ST - Represents DMA2D_task_out_start_ch0 trigger status.\\0: Not triggered\\1: Triggered - 9 - 1 - read-write - - - DMA2D_TASK_OUT_START_CH1_ST - Represents DMA2D_task_out_start_ch1 trigger status.\\0: Not triggered\\1: Triggered - 10 - 1 - read-write - - - DMA2D_TASK_OUT_START_CH2_ST - Represents DMA2D_task_out_start_ch2 trigger status.\\0: Not triggered\\1: Triggered - 11 - 1 - read-write - - - DMA2D_TASK_OUT_DSCR_READY_CH0_ST - Represents DMA2D_task_out_dscr_ready_ch0 trigger status.\\0: Not triggered\\1: Triggered - 12 - 1 - read-write - - - DMA2D_TASK_OUT_DSCR_READY_CH1_ST - Represents DMA2D_task_out_dscr_ready_ch1 trigger status.\\0: Not triggered\\1: Triggered - 13 - 1 - read-write - - - DMA2D_TASK_OUT_DSCR_READY_CH2_ST - Represents DMA2D_task_out_dscr_ready_ch2 trigger status.\\0: Not triggered\\1: Triggered - 14 - 1 - read-write - - - - - TASK_ST6_CLR - Tasks trigger status clear register - 0x21C - 0x20 - - - PDMA_AXI_TASK_IN_START_CH2_ST_CLR - Configures whether or not to clear PDMA_AXI_task_in_start_ch2 trigger status.\\0: Invalid, No effect\\1: Clear - 0 - 1 - write-only - - - PDMA_AXI_TASK_OUT_START_CH0_ST_CLR - Configures whether or not to clear PDMA_AXI_task_out_start_ch0 trigger status.\\0: Invalid, No effect\\1: Clear - 1 - 1 - write-only - - - PDMA_AXI_TASK_OUT_START_CH1_ST_CLR - Configures whether or not to clear PDMA_AXI_task_out_start_ch1 trigger status.\\0: Invalid, No effect\\1: Clear - 2 - 1 - write-only - - - PDMA_AXI_TASK_OUT_START_CH2_ST_CLR - Configures whether or not to clear PDMA_AXI_task_out_start_ch2 trigger status.\\0: Invalid, No effect\\1: Clear - 3 - 1 - write-only - - - PMU_TASK_SLEEP_REQ_ST_CLR - Configures whether or not to clear PMU_task_sleep_req trigger status.\\0: Invalid, No effect\\1: Clear - 4 - 1 - write-only - - - DMA2D_TASK_IN_START_CH0_ST_CLR - Configures whether or not to clear DMA2D_task_in_start_ch0 trigger status.\\0: Invalid, No effect\\1: Clear - 5 - 1 - write-only - - - DMA2D_TASK_IN_START_CH1_ST_CLR - Configures whether or not to clear DMA2D_task_in_start_ch1 trigger status.\\0: Invalid, No effect\\1: Clear - 6 - 1 - write-only - - - DMA2D_TASK_IN_DSCR_READY_CH0_ST_CLR - Configures whether or not to clear DMA2D_task_in_dscr_ready_ch0 trigger status.\\0: Invalid, No effect\\1: Clear - 7 - 1 - write-only - - - DMA2D_TASK_IN_DSCR_READY_CH1_ST_CLR - Configures whether or not to clear DMA2D_task_in_dscr_ready_ch1 trigger status.\\0: Invalid, No effect\\1: Clear - 8 - 1 - write-only - - - DMA2D_TASK_OUT_START_CH0_ST_CLR - Configures whether or not to clear DMA2D_task_out_start_ch0 trigger status.\\0: Invalid, No effect\\1: Clear - 9 - 1 - write-only - - - DMA2D_TASK_OUT_START_CH1_ST_CLR - Configures whether or not to clear DMA2D_task_out_start_ch1 trigger status.\\0: Invalid, No effect\\1: Clear - 10 - 1 - write-only - - - DMA2D_TASK_OUT_START_CH2_ST_CLR - Configures whether or not to clear DMA2D_task_out_start_ch2 trigger status.\\0: Invalid, No effect\\1: Clear - 11 - 1 - write-only - - - DMA2D_TASK_OUT_DSCR_READY_CH0_ST_CLR - Configures whether or not to clear DMA2D_task_out_dscr_ready_ch0 trigger status.\\0: Invalid, No effect\\1: Clear - 12 - 1 - write-only - - - DMA2D_TASK_OUT_DSCR_READY_CH1_ST_CLR - Configures whether or not to clear DMA2D_task_out_dscr_ready_ch1 trigger status.\\0: Invalid, No effect\\1: Clear - 13 - 1 - write-only - - - DMA2D_TASK_OUT_DSCR_READY_CH2_ST_CLR - Configures whether or not to clear DMA2D_task_out_dscr_ready_ch2 trigger status.\\0: Invalid, No effect\\1: Clear - 14 - 1 - write-only - - - - - CLK_EN - ETM clock enable register - 0x220 - 0x20 - - - CLK_EN - Configures whether or not to open register clock gate.\\0: Open the clock gate only when application writes registers\\1: Force open the clock gate for register - 0 - 1 - read-write - - - - - DATE - ETM date register - 0x224 - 0x20 - 0x02303031 - - - DATE - Configures the version. - 0 - 28 - read-write - - - - - - - SPI0 - SPI (Serial Peripheral Interface) Controller 0 - SPI0 - 0x5008C000 - - 0x0 - 0x14C - registers - - - - SPI_MEM_CMD - SPI0 FSM status register - 0x0 - 0x20 - - - SPI_MEM_MST_ST - The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT , 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent data is stored in SPI0 TX FIFO, 5: SPI0 write data state. - 0 - 4 - read-only - - - SPI_MEM_SLV_ST - The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state. - 4 - 4 - read-only - - - SPI_MEM_USR - SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. - 18 - 1 - read-only - - - - - SPI_MEM_CTRL - SPI0 control register. - 0x8 - 0x20 - 0x802C200C - - - SPI_MEM_WDUMMY_DQS_ALWAYS_OUT - In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_DQS is output by the MSPI controller. - 0 - 1 - read-write - - - SPI_MEM_WDUMMY_ALWAYS_OUT - In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller. - 1 - 1 - read-write - - - SPI_MEM_FDUMMY_RIN - In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller in the first half part of dummy phase. It is used to mask invalid SPI_DQS in the half part of dummy phase. - 2 - 1 - read-write - - - SPI_MEM_FDUMMY_WOUT - In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller in the second half part of dummy phase. It is used to pre-drive flash. - 3 - 1 - read-write - - - SPI_MEM_FDOUT_OCT - Apply 8 signals during write-data phase 1:enable 0: disable - 4 - 1 - read-write - - - SPI_MEM_FDIN_OCT - Apply 8 signals during read-data phase 1:enable 0: disable - 5 - 1 - read-write - - - SPI_MEM_FADDR_OCT - Apply 8 signals during address phase 1:enable 0: disable - 6 - 1 - read-write - - - SPI_MEM_FCMD_QUAD - Apply 4 signals during command phase 1:enable 0: disable - 8 - 1 - read-write - - - SPI_MEM_FCMD_OCT - Apply 8 signals during command phase 1:enable 0: disable - 9 - 1 - read-write - - - SPI_MEM_FASTRD_MODE - This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT and SPI_MEM_FREAD_DOUT. 1: enable 0: disable. - 13 - 1 - read-write - - - SPI_MEM_FREAD_DUAL - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. - 14 - 1 - read-write - - - SPI_MEM_Q_POL - The bit is used to set MISO line polarity, 1: high 0, low - 18 - 1 - read-write - - - SPI_MEM_D_POL - The bit is used to set MOSI line polarity, 1: high 0, low - 19 - 1 - read-write - - - SPI_MEM_FREAD_QUAD - In the read operations read-data phase apply 4 signals. 1: enable 0: disable. - 20 - 1 - read-write - - - SPI_MEM_WP - Write protect signal output when SPI is idle. 1: output high, 0: output low. - 21 - 1 - read-write - - - SPI_MEM_FREAD_DIO - In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable. - 23 - 1 - read-write - - - SPI_MEM_FREAD_QIO - In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable. - 24 - 1 - read-write - - - SPI_MEM_DQS_IE_ALWAYS_ON - When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others. - 30 - 1 - read-write - - - SPI_MEM_DATA_IE_ALWAYS_ON - When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are always 1. 0: Others. - 31 - 1 - read-write - - - - - SPI_MEM_CTRL1 - SPI0 control1 register. - 0xC - 0x20 - 0x28E00000 - - - SPI_MEM_CLK_MODE - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. - 0 - 2 - read-write - - - SPI_AR_SIZE0_1_SUPPORT_EN - 1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR. - 21 - 1 - read-write - - - SPI_AW_SIZE0_1_SUPPORT_EN - 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR. - 22 - 1 - read-write - - - SPI_AXI_RDATA_BACK_FAST - 1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: Reply AXI read data to AXI bus when all the read data is available. - 23 - 1 - read-write - - - SPI_MEM_RRESP_ECC_ERR_EN - 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY when there is a ECC error in AXI read data. The ECC error information is recorded in SPI_MEM_ECC_ERR_ADDR_REG. - 24 - 1 - read-write - - - SPI_MEM_AR_SPLICE_EN - Set this bit to enable AXI Read Splice-transfer. - 25 - 1 - read-write - - - SPI_MEM_AW_SPLICE_EN - Set this bit to enable AXI Write Splice-transfer. - 26 - 1 - read-write - - - SPI_MEM_RAM0_EN - When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be accessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 will be accessed. When SPI_MEM_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be accessed at the same time. - 27 - 1 - read-only - - - SPI_MEM_DUAL_RAM_EN - Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at the same time. - 28 - 1 - read-only - - - SPI_MEM_FAST_WRITE_EN - Set this bit to write data faster, do not wait write data has been stored in tx_bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored in tx_bus_fifo_l2. - 29 - 1 - read-write - - - SPI_MEM_RXFIFO_RST - The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to receive signals from AXI. Set this bit to reset these FIFO. - 30 - 1 - write-only - - - SPI_MEM_TXFIFO_RST - The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to send signals to AXI. Set this bit to reset these FIFO. - 31 - 1 - write-only - - - - - SPI_MEM_CTRL2 - SPI0 control2 register. - 0x10 - 0x20 - 0x01002C21 - - - SPI_MEM_CS_SETUP_TIME - (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with SPI_MEM_CS_SETUP bit. - 0 - 5 - read-write - - - SPI_MEM_CS_HOLD_TIME - SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with SPI_MEM_CS_HOLD bit. - 5 - 5 - read-write - - - SPI_MEM_ECC_CS_HOLD_TIME - SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC mode when accessed flash. - 10 - 3 - read-write - - - SPI_MEM_ECC_SKIP_PAGE_CORNER - 1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when accesses flash. - 13 - 1 - read-write - - - SPI_MEM_ECC_16TO18_BYTE_EN - Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses flash. - 14 - 1 - read-write - - - SPI_MEM_SPLIT_TRANS_EN - Set this bit to enable SPI0 split one AXI read flash transfer into two SPI transfers when one transfer will cross flash or EXT_RAM page corner, valid no matter whether there is an ECC region or not. - 24 - 1 - read-write - - - SPI_MEM_CS_HOLD_DELAY - These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles. - 25 - 6 - read-write - - - SPI_MEM_SYNC_RESET - The spi0_mst_st and spi0_slv_st will be reset. - 31 - 1 - write-only - - - - - SPI_MEM_CLOCK - SPI clock division control register. - 0x14 - 0x20 - 0x00030103 - - - SPI_MEM_CLKCNT_L - In the master mode it must be equal to spi_mem_clkcnt_N. - 0 - 8 - read-write - - - SPI_MEM_CLKCNT_H - In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). - 8 - 8 - read-write - - - SPI_MEM_CLKCNT_N - In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1) - 16 - 8 - read-write - - - SPI_MEM_CLK_EQU_SYSCLK - 1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module clock. - 31 - 1 - read-write - - - - - SPI_MEM_USER - SPI0 user register. - 0x18 - 0x20 - - - SPI_MEM_CS_HOLD - spi cs keep low when spi is in done phase. 1: enable 0: disable. - 6 - 1 - read-write - - - SPI_MEM_CS_SETUP - spi cs is enable when spi is in prepare phase. 1: enable 0: disable. - 7 - 1 - read-write - - - SPI_MEM_CK_OUT_EDGE - The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3. - 9 - 1 - read-write - - - SPI_MEM_USR_DUMMY_IDLE - spi clock is disable in dummy phase when the bit is enable. - 26 - 1 - read-write - - - SPI_MEM_USR_DUMMY - This bit enable the dummy phase of an operation. - 29 - 1 - read-write - - - - - SPI_MEM_USER1 - SPI0 user1 register. - 0x1C - 0x20 - 0x5C000047 - - - SPI_MEM_USR_DUMMY_CYCLELEN - The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1). - 0 - 6 - read-write - - - SPI_MEM_USR_DBYTELEN - SPI0 USR_CMD read or write data byte length -1 - 6 - 3 - read-only - - - SPI_MEM_USR_ADDR_BITLEN - The length in bits of address phase. The register value shall be (bit_num-1). - 26 - 6 - read-write - - - - - SPI_MEM_USER2 - SPI0 user2 register. - 0x20 - 0x20 - 0x70000000 - - - SPI_MEM_USR_COMMAND_VALUE - The value of command. - 0 - 16 - read-write - - - SPI_MEM_USR_COMMAND_BITLEN - The length in bits of command phase. The register value shall be (bit_num-1) - 28 - 4 - read-write - - - - - SPI_MEM_RD_STATUS - SPI0 read control register. - 0x2C - 0x20 - - - SPI_MEM_WB_MODE - Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. - 16 - 8 - read-write - - - - - SPI_MEM_MISC - SPI0 misc register - 0x34 - 0x20 - - - SPI_MEM_FSUB_PIN - For SPI0, flash is connected to SUBPINs. - 7 - 1 - read-write - - - SPI_MEM_SSUB_PIN - For SPI0, sram is connected to SUBPINs. - 8 - 1 - read-write - - - SPI_MEM_CK_IDLE_EDGE - 1: SPI_CLK line is high when idle 0: spi clk line is low when idle - 9 - 1 - read-write - - - SPI_MEM_CS_KEEP_ACTIVE - SPI_CS line keep low when the bit is set. - 10 - 1 - read-write - - - - - SPI_MEM_CACHE_FCTRL - SPI0 bit mode control register. - 0x3C - 0x20 - 0xC0000000 - - - SPI_MEM_AXI_REQ_EN - For SPI0, AXI master access enable, 1: enable, 0:disable. - 0 - 1 - read-write - - - SPI_MEM_CACHE_USR_ADDR_4BYTE - For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable. - 1 - 1 - read-write - - - SPI_MEM_CACHE_FLASH_USR_CMD - For SPI0, cache read flash for user define command, 1: enable, 0:disable. - 2 - 1 - read-write - - - SPI_MEM_FDIN_DUAL - For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. - 3 - 1 - read-write - - - SPI_MEM_FDOUT_DUAL - For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. - 4 - 1 - read-write - - - SPI_MEM_FADDR_DUAL - For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. - 5 - 1 - read-write - - - SPI_MEM_FDIN_QUAD - For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. - 6 - 1 - read-write - - - SPI_MEM_FDOUT_QUAD - For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. - 7 - 1 - read-write - - - SPI_MEM_FADDR_QUAD - For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. - 8 - 1 - read-write - - - SPI_SAME_AW_AR_ADDR_CHK_EN - Set this bit to check AXI read/write the same address region. - 30 - 1 - read-write - - - SPI_CLOSE_AXI_INF_EN - Set this bit to close AXI read/write transfer to MSPI, which means that only SLV_ERR will be replied to BRESP/RRESP. - 31 - 1 - read-write - - - - - SPI_MEM_CACHE_SCTRL - SPI0 external RAM control register - 0x40 - 0x20 - 0x0055C070 - - - SPI_MEM_CACHE_USR_SADDR_4BYTE - For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: enable, 0:disable. - 0 - 1 - read-write - - - SPI_MEM_USR_SRAM_DIO - For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disable - 1 - 1 - read-write - - - SPI_MEM_USR_SRAM_QIO - For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disable - 2 - 1 - read-write - - - SPI_MEM_USR_WR_SRAM_DUMMY - For SPI0, In the external RAM mode, it is the enable bit of dummy phase for write operations. - 3 - 1 - read-write - - - SPI_MEM_USR_RD_SRAM_DUMMY - For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read operations. - 4 - 1 - read-write - - - SPI_MEM_CACHE_SRAM_USR_RCMD - For SPI0, In the external RAM mode cache read external RAM for user define command. - 5 - 1 - read-write - - - SPI_MEM_SRAM_RDUMMY_CYCLELEN - For SPI0, In the external RAM mode, it is the length in bits of read dummy phase. The register value shall be (bit_num-1). - 6 - 6 - read-write - - - SPI_MEM_SRAM_ADDR_BITLEN - For SPI0, In the external RAM mode, it is the length in bits of address phase. The register value shall be (bit_num-1). - 14 - 6 - read-write - - - SPI_MEM_CACHE_SRAM_USR_WCMD - For SPI0, In the external RAM mode cache write sram for user define command - 20 - 1 - read-write - - - SPI_MEM_SRAM_OCT - reserved - 21 - 1 - read-write - - - SPI_MEM_SRAM_WDUMMY_CYCLELEN - For SPI0, In the external RAM mode, it is the length in bits of write dummy phase. The register value shall be (bit_num-1). - 22 - 6 - read-write - - - - - SPI_MEM_SRAM_CMD - SPI0 external RAM mode control register - 0x44 - 0x20 - 0x80C00000 - - - SPI_MEM_SCLK_MODE - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on. - 0 - 2 - read-write - - - SPI_MEM_SWB_MODE - Mode bits in the external RAM fast read mode it is combined with spi_mem_fastrd_mode bit. - 2 - 8 - read-write - - - SPI_MEM_SDIN_DUAL - For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio. - 10 - 1 - read-write - - - SPI_MEM_SDOUT_DUAL - For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio. - 11 - 1 - read-write - - - SPI_MEM_SADDR_DUAL - For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio. - 12 - 1 - read-write - - - SPI_MEM_SDIN_QUAD - For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio. - 14 - 1 - read-write - - - SPI_MEM_SDOUT_QUAD - For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio. - 15 - 1 - read-write - - - SPI_MEM_SADDR_QUAD - For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio. - 16 - 1 - read-write - - - SPI_MEM_SCMD_QUAD - For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio. - 17 - 1 - read-write - - - SPI_MEM_SDIN_OCT - For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable. - 18 - 1 - read-write - - - SPI_MEM_SDOUT_OCT - For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable. - 19 - 1 - read-write - - - SPI_MEM_SADDR_OCT - For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. - 20 - 1 - read-write - - - SPI_MEM_SCMD_OCT - For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable. - 21 - 1 - read-write - - - SPI_MEM_SDUMMY_RIN - In the dummy phase of a MSPI read data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller. - 22 - 1 - read-write - - - SPI_MEM_SDUMMY_WOUT - In the dummy phase of a MSPI write data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller. - 23 - 1 - read-write - - - SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT - In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_DQS is output by the MSPI controller. - 24 - 1 - read-write - - - SPI_SMEM_WDUMMY_ALWAYS_OUT - In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_IO[7:0] is output by the MSPI controller. - 25 - 1 - read-write - - - SPI_MEM_SDIN_HEX - For SPI0 external RAM , din phase apply 16 signals. 1: enable 0: disable. - 26 - 1 - read-write - - - SPI_MEM_SDOUT_HEX - For SPI0 external RAM , dout phase apply 16 signals. 1: enable 0: disable. - 27 - 1 - read-write - - - SPI_SMEM_DQS_IE_ALWAYS_ON - When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others. - 30 - 1 - read-write - - - SPI_SMEM_DATA_IE_ALWAYS_ON - When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0] are always 1. 0: Others. - 31 - 1 - read-write - - - - - SPI_MEM_SRAM_DRD_CMD - SPI0 external RAM DDR read command control register - 0x48 - 0x20 - - - SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE - For SPI0,When cache mode is enable it is the read command value of command phase for sram. - 0 - 16 - read-write - - - SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN - For SPI0,When cache mode is enable it is the length in bits of command phase for sram. The register value shall be (bit_num-1). - 28 - 4 - read-write - - - - - SPI_MEM_SRAM_DWR_CMD - SPI0 external RAM DDR write command control register - 0x4C - 0x20 - - - SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE - For SPI0,When cache mode is enable it is the write command value of command phase for sram. - 0 - 16 - read-write - - - SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN - For SPI0,When cache mode is enable it is the in bits of command phase for sram. The register value shall be (bit_num-1). - 28 - 4 - read-write - - - - - SPI_MEM_SRAM_CLK - SPI0 external RAM clock control register - 0x50 - 0x20 - 0x00030103 - - - SPI_MEM_SCLKCNT_L - For SPI0 external RAM interface, it must be equal to spi_mem_clkcnt_N. - 0 - 8 - read-write - - - SPI_MEM_SCLKCNT_H - For SPI0 external RAM interface, it must be floor((spi_mem_clkcnt_N+1)/2-1). - 8 - 8 - read-write - - - SPI_MEM_SCLKCNT_N - For SPI0 external RAM interface, it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1) - 16 - 8 - read-write - - - SPI_MEM_SCLK_EQU_SYSCLK - For SPI0 external RAM interface, 1: spi_mem_clk is eqaul to system 0: spi_mem_clk is divided from system clock. - 31 - 1 - read-write - - - - - SPI_MEM_FSM - SPI0 FSM status register - 0x54 - 0x20 - 0x00000200 - - - SPI_MEM_LOCK_DELAY_TIME - The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1. - 7 - 5 - read-write - - - - - SPI_MEM_INT_ENA - SPI0 interrupt enable register - 0xC0 - 0x20 - - - SPI_MEM_SLV_ST_END_INT_ENA - The enable bit for SPI_MEM_SLV_ST_END_INT interrupt. - 3 - 1 - read-write - - - SPI_MEM_MST_ST_END_INT_ENA - The enable bit for SPI_MEM_MST_ST_END_INT interrupt. - 4 - 1 - read-write - - - SPI_MEM_ECC_ERR_INT_ENA - The enable bit for SPI_MEM_ECC_ERR_INT interrupt. - 5 - 1 - read-write - - - SPI_MEM_PMS_REJECT_INT_ENA - The enable bit for SPI_MEM_PMS_REJECT_INT interrupt. - 6 - 1 - read-write - - - SPI_MEM_AXI_RADDR_ERR_INT_ENA - The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. - 7 - 1 - read-write - - - SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA - The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. - 8 - 1 - read-write - - - SPI_MEM_AXI_WADDR_ERR_INT__ENA - The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. - 9 - 1 - read-write - - - SPI_MEM_DQS0_AFIFO_OVF_INT_ENA - The enable bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. - 28 - 1 - read-write - - - SPI_MEM_DQS1_AFIFO_OVF_INT_ENA - The enable bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. - 29 - 1 - read-write - - - SPI_MEM_BUS_FIFO1_UDF_INT_ENA - The enable bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. - 30 - 1 - read-write - - - SPI_MEM_BUS_FIFO0_UDF_INT_ENA - The enable bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. - 31 - 1 - read-write - - - - - SPI_MEM_INT_CLR - SPI0 interrupt clear register - 0xC4 - 0x20 - - - SPI_MEM_SLV_ST_END_INT_CLR - The clear bit for SPI_MEM_SLV_ST_END_INT interrupt. - 3 - 1 - write-only - - - SPI_MEM_MST_ST_END_INT_CLR - The clear bit for SPI_MEM_MST_ST_END_INT interrupt. - 4 - 1 - write-only - - - SPI_MEM_ECC_ERR_INT_CLR - The clear bit for SPI_MEM_ECC_ERR_INT interrupt. - 5 - 1 - write-only - - - SPI_MEM_PMS_REJECT_INT_CLR - The clear bit for SPI_MEM_PMS_REJECT_INT interrupt. - 6 - 1 - write-only - - - SPI_MEM_AXI_RADDR_ERR_INT_CLR - The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. - 7 - 1 - write-only - - - SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR - The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. - 8 - 1 - write-only - - - SPI_MEM_AXI_WADDR_ERR_INT_CLR - The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. - 9 - 1 - write-only - - - SPI_MEM_DQS0_AFIFO_OVF_INT_CLR - The clear bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. - 28 - 1 - write-only - - - SPI_MEM_DQS1_AFIFO_OVF_INT_CLR - The clear bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. - 29 - 1 - write-only - - - SPI_MEM_BUS_FIFO1_UDF_INT_CLR - The clear bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. - 30 - 1 - write-only - - - SPI_MEM_BUS_FIFO0_UDF_INT_CLR - The clear bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. - 31 - 1 - write-only - - - - - SPI_MEM_INT_RAW - SPI0 interrupt raw register - 0xC8 - 0x20 - - - SPI_MEM_SLV_ST_END_INT_RAW - The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others - 3 - 1 - read-write - - - SPI_MEM_MST_ST_END_INT_RAW - The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is changed from non idle state to idle state. 0: Others. - 4 - 1 - read-write - - - SPI_MEM_ECC_ERR_INT_RAW - The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set and SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN is cleared and SPI_SMEM_ECC_ERR_INT_EN is set, this bit is triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times of SPI0/1 ECC read external RAM and flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN are cleared, this bit will not be triggered. - 5 - 1 - read-write - - - SPI_MEM_PMS_REJECT_INT_RAW - The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is rejected. 0: Others. - 6 - 1 - read-write - - - SPI_MEM_AXI_RADDR_ERR_INT_RAW - The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read address is invalid by compared to MMU configuration. 0: Others. - 7 - 1 - read-write - - - SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW - The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write flash request is received. 0: Others. - 8 - 1 - read-write - - - SPI_MEM_AXI_WADDR_ERR_INT_RAW - The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write address is invalid by compared to MMU configuration. 0: Others. - 9 - 1 - read-write - - - SPI_MEM_DQS0_AFIFO_OVF_INT_RAW - The raw bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO connected to SPI_DQS1 is overflow. - 28 - 1 - read-write - - - SPI_MEM_DQS1_AFIFO_OVF_INT_RAW - The raw bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO connected to SPI_DQS is overflow. - 29 - 1 - read-write - - - SPI_MEM_BUS_FIFO1_UDF_INT_RAW - The raw bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. 1: Triggered when BUS1 FIFO is underflow. - 30 - 1 - read-write - - - SPI_MEM_BUS_FIFO0_UDF_INT_RAW - The raw bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. 1: Triggered when BUS0 FIFO is underflow. - 31 - 1 - read-write - - - - - SPI_MEM_INT_ST - SPI0 interrupt status register - 0xCC - 0x20 - - - SPI_MEM_SLV_ST_END_INT_ST - The status bit for SPI_MEM_SLV_ST_END_INT interrupt. - 3 - 1 - read-only - - - SPI_MEM_MST_ST_END_INT_ST - The status bit for SPI_MEM_MST_ST_END_INT interrupt. - 4 - 1 - read-only - - - SPI_MEM_ECC_ERR_INT_ST - The status bit for SPI_MEM_ECC_ERR_INT interrupt. - 5 - 1 - read-only - - - SPI_MEM_PMS_REJECT_INT_ST - The status bit for SPI_MEM_PMS_REJECT_INT interrupt. - 6 - 1 - read-only - - - SPI_MEM_AXI_RADDR_ERR_INT_ST - The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. - 7 - 1 - read-only - - - SPI_MEM_AXI_WR_FLASH_ERR_INT_ST - The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. - 8 - 1 - read-only - - - SPI_MEM_AXI_WADDR_ERR_INT_ST - The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. - 9 - 1 - read-only - - - SPI_MEM_DQS0_AFIFO_OVF_INT_ST - The status bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. - 28 - 1 - read-only - - - SPI_MEM_DQS1_AFIFO_OVF_INT_ST - The status bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. - 29 - 1 - read-only - - - SPI_MEM_BUS_FIFO1_UDF_INT_ST - The status bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. - 30 - 1 - read-only - - - SPI_MEM_BUS_FIFO0_UDF_INT_ST - The status bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. - 31 - 1 - read-only - - - - - SPI_MEM_DDR - SPI0 flash DDR mode control register - 0xD4 - 0x20 - 0x00003020 - - - SPI_FMEM_DDR_EN - 1: in DDR mode, 0 in SDR mode - 0 - 1 - read-write - - - SPI_FMEM_VAR_DUMMY - Set the bit to enable variable dummy cycle in spi DDR mode. - 1 - 1 - read-write - - - SPI_FMEM_DDR_RDAT_SWP - Set the bit to reorder rx data of the word in spi DDR mode. - 2 - 1 - read-write - - - SPI_FMEM_DDR_WDAT_SWP - Set the bit to reorder tx data of the word in spi DDR mode. - 3 - 1 - read-write - - - SPI_FMEM_DDR_CMD_DIS - the bit is used to disable dual edge in command phase when DDR mode. - 4 - 1 - read-write - - - SPI_FMEM_OUTMINBYTELEN - It is the minimum output data length in the panda device. - 5 - 7 - read-write - - - SPI_FMEM_TX_DDR_MSK_EN - Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when accesses to flash. - 12 - 1 - read-write - - - SPI_FMEM_RX_DDR_MSK_EN - Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when accesses to flash. - 13 - 1 - read-write - - - SPI_FMEM_USR_DDR_DQS_THD - The delay number of data strobe which from memory based on SPI clock. - 14 - 7 - read-write - - - SPI_FMEM_DDR_DQS_LOOP - 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS. - 21 - 1 - read-write - - - SPI_FMEM_CLK_DIFF_EN - Set this bit to enable the differential SPI_CLK#. - 24 - 1 - read-write - - - SPI_FMEM_DQS_CA_IN - Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. - 26 - 1 - read-write - - - SPI_FMEM_HYPERBUS_DUMMY_2X - Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram. - 27 - 1 - read-write - - - SPI_FMEM_CLK_DIFF_INV - Set this bit to invert SPI_DIFF when accesses to flash. . - 28 - 1 - read-write - - - SPI_FMEM_OCTA_RAM_ADDR - Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. - 29 - 1 - read-write - - - SPI_FMEM_HYPERBUS_CA - Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. - 30 - 1 - read-write - - - - - SPI_SMEM_DDR - SPI0 external RAM DDR mode control register - 0xD8 - 0x20 - 0x00003020 - - - EN - 1: in DDR mode, 0 in SDR mode - 0 - 1 - read-write - - - SPI_SMEM_VAR_DUMMY - Set the bit to enable variable dummy cycle in spi DDR mode. - 1 - 1 - read-write - - - RDAT_SWP - Set the bit to reorder rx data of the word in spi DDR mode. - 2 - 1 - read-write - - - WDAT_SWP - Set the bit to reorder tx data of the word in spi DDR mode. - 3 - 1 - read-write - - - CMD_DIS - the bit is used to disable dual edge in command phase when DDR mode. - 4 - 1 - read-write - - - SPI_SMEM_OUTMINBYTELEN - It is the minimum output data length in the DDR psram. - 5 - 7 - read-write - - - SPI_SMEM_TX_DDR_MSK_EN - Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when accesses to external RAM. - 12 - 1 - read-write - - - SPI_SMEM_RX_DDR_MSK_EN - Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when accesses to external RAM. - 13 - 1 - read-write - - - SPI_SMEM_USR_DDR_DQS_THD - The delay number of data strobe which from memory based on SPI clock. - 14 - 7 - read-write - - - DQS_LOOP - 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS. - 21 - 1 - read-write - - - SPI_SMEM_CLK_DIFF_EN - Set this bit to enable the differential SPI_CLK#. - 24 - 1 - read-write - - - SPI_SMEM_DQS_CA_IN - Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. - 26 - 1 - read-write - - - SPI_SMEM_HYPERBUS_DUMMY_2X - Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram. - 27 - 1 - read-write - - - SPI_SMEM_CLK_DIFF_INV - Set this bit to invert SPI_DIFF when accesses to external RAM. . - 28 - 1 - read-write - - - SPI_SMEM_OCTA_RAM_ADDR - Set this bit to enable octa_ram address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. - 29 - 1 - read-write - - - SPI_SMEM_HYPERBUS_CA - Set this bit to enable HyperRAM address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. - 30 - 1 - read-write - - - - - 4 - 0x4 - SPI_FMEM_PMS%s_ATTR - MSPI flash PMS section %s attribute register - 0x100 - 0x20 - 0x00000003 - - - SPI_FMEM_PMS_RD_ATTR - 1: SPI1 flash PMS section %s read accessible. 0: Not allowed. - 0 - 1 - read-write - - - SPI_FMEM_PMS_WR_ATTR - 1: SPI1 flash PMS section %s write accessible. 0: Not allowed. - 1 - 1 - read-write - - - SPI_FMEM_PMS_ECC - SPI1 flash PMS section %s ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS section %s is configured by registers SPI_FMEM_PMS%s_ADDR_REG and SPI_FMEM_PMS%s_SIZE_REG. - 2 - 1 - read-write - - - - - 4 - 0x4 - SPI_FMEM_PMS%s_ADDR - SPI1 flash PMS section %s start address register - 0x110 - 0x20 - - - S - SPI1 flash PMS section %s start address value - 0 - 27 - read-write - - - - - 4 - 0x4 - SPI_FMEM_PMS%s_SIZE - SPI1 flash PMS section %s start address register - 0x120 - 0x20 - 0x00001000 - - - SPI_FMEM_PMS_SIZE - SPI1 flash PMS section %s address region is (SPI_FMEM_PMS%s_ADDR_S, SPI_FMEM_PMS%s_ADDR_S + SPI_FMEM_PMS%s_SIZE) - 0 - 15 - read-write - - - - - 4 - 0x4 - SPI_SMEM_PMS%s_ATTR - SPI1 flash PMS section %s start address register - 0x130 - 0x20 - 0x00000003 - - - SPI_SMEM_PMS_RD_ATTR - 1: SPI1 external RAM PMS section %s read accessible. 0: Not allowed. - 0 - 1 - read-write - - - SPI_SMEM_PMS_WR_ATTR - 1: SPI1 external RAM PMS section %s write accessible. 0: Not allowed. - 1 - 1 - read-write - - - SPI_SMEM_PMS_ECC - SPI1 external RAM PMS section %s ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM PMS section %s is configured by registers SPI_SMEM_PMS%s_ADDR_REG and SPI_SMEM_PMS%s_SIZE_REG. - 2 - 1 - read-write - - - - - 4 - 0x4 - SPI_SMEM_PMS%s_ADDR - SPI1 external RAM PMS section %s start address register - 0x140 - 0x20 - - - S - SPI1 external RAM PMS section %s start address value - 0 - 27 - read-write - - - - - 4 - 0x4 - SPI_SMEM_PMS%s_SIZE - SPI1 external RAM PMS section %s start address register - 0x150 - 0x20 - 0x00001000 - - - SPI_SMEM_PMS_SIZE - SPI1 external RAM PMS section %s address region is (SPI_SMEM_PMS%s_ADDR_S, SPI_SMEM_PMS%s_ADDR_S + SPI_SMEM_PMS%s_SIZE) - 0 - 15 - read-write - - - - - SPI_MEM_PMS_REJECT - SPI1 access reject register - 0x164 - 0x20 - - - SPI_MEM_REJECT_ADDR - This bits show the first SPI1 access error address. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. - 0 - 27 - read-only - - - SPI_MEM_PM_EN - Set this bit to enable SPI0/1 transfer permission control function. - 27 - 1 - read-write - - - SPI_MEM_PMS_LD - 1: SPI1 write access error. 0: No write access error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. - 28 - 1 - read-only - - - SPI_MEM_PMS_ST - 1: SPI1 read access error. 0: No read access error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. - 29 - 1 - read-only - - - SPI_MEM_PMS_MULTI_HIT - 1: SPI1 access is rejected because of address miss. 0: No address miss error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. - 30 - 1 - read-only - - - SPI_MEM_PMS_IVD - 1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. - 31 - 1 - read-only - - - - - SPI_MEM_ECC_CTRL - MSPI ECC control register - 0x168 - 0x20 - 0x01005000 - - - SPI_MEM_ECC_ERR_CNT - This bits show the error times of MSPI ECC read. It is cleared by when SPI_MEM_ECC_ERR_INT_CLR bit is set. - 5 - 6 - read-only - - - SPI_FMEM_ECC_ERR_INT_NUM - Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt. - 11 - 6 - read-write - - - SPI_FMEM_ECC_ERR_INT_EN - Set this bit to calculate the error times of MSPI ECC read when accesses to flash. - 17 - 1 - read-write - - - SPI_FMEM_PAGE_SIZE - Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes. - 18 - 2 - read-write - - - SPI_FMEM_ECC_ADDR_EN - Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the ECC region or non-ECC region of flash. If there is no ECC region in flash, this bit should be 0. Otherwise, this bit should be 1. - 20 - 1 - read-write - - - SPI_MEM_USR_ECC_ADDR_EN - Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer. - 21 - 1 - read-write - - - SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN - 1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is updated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR record the first ECC error information. - 24 - 1 - read-write - - - SPI_MEM_ECC_ERR_BITS - Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding to byte 0 bit 0 to byte 15 bit 7) - 25 - 7 - read-only - - - - - SPI_MEM_ECC_ERR_ADDR - MSPI ECC error address register - 0x16C - 0x20 - - - SPI_MEM_ECC_ERR_ADDR - This bits show the first MSPI ECC error address. It is cleared by when SPI_MEM_ECC_ERR_INT_CLR bit is set. - 0 - 27 - read-only - - - - - SPI_MEM_AXI_ERR_ADDR - SPI0 AXI request error address. - 0x170 - 0x20 - - - SPI_MEM_AXI_ERR_ADDR - This bits show the first AXI write/read invalid error or AXI write flash error address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set. - 0 - 27 - read-only - - - - - SPI_SMEM_ECC_CTRL - MSPI ECC control register - 0x174 - 0x20 - 0x00080000 - - - SPI_SMEM_ECC_ERR_INT_EN - Set this bit to calculate the error times of MSPI ECC read when accesses to external RAM. - 17 - 1 - read-write - - - SPI_SMEM_PAGE_SIZE - Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes. - 18 - 2 - read-write - - - SPI_SMEM_ECC_ADDR_EN - Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the ECC region or non-ECC region of external RAM. If there is no ECC region in external RAM, this bit should be 0. Otherwise, this bit should be 1. - 20 - 1 - read-write - - - - - SPI_SMEM_AXI_ADDR_CTRL - SPI0 AXI address control register - 0x178 - 0x20 - 0xFC000000 - - - SPI_MEM_ALL_FIFO_EMPTY - The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers and SPI0 transfers are done. 0: Others. - 26 - 1 - read-only - - - SPI_RDATA_AFIFO_REMPTY - 1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending. - 27 - 1 - read-only - - - SPI_RADDR_AFIFO_REMPTY - 1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending. - 28 - 1 - read-only - - - SPI_WDATA_AFIFO_REMPTY - 1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending. - 29 - 1 - read-only - - - SPI_WBLEN_AFIFO_REMPTY - 1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending. - 30 - 1 - read-only - - - SPI_ALL_AXI_TRANS_AFIFO_EMPTY - This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO and RDATA_AFIFO are empty and spi0_mst_st is IDLE. - 31 - 1 - read-only - - - - - SPI_MEM_AXI_ERR_RESP_EN - SPI0 AXI error response enable register - 0x17C - 0x20 - - - SPI_MEM_AW_RESP_EN_MMU_VLD - Set this bit to enable AXI response function for mmu valid err in axi write trans. - 0 - 1 - read-write - - - SPI_MEM_AW_RESP_EN_MMU_GID - Set this bit to enable AXI response function for mmu gid err in axi write trans. - 1 - 1 - read-write - - - SPI_MEM_AW_RESP_EN_AXI_SIZE - Set this bit to enable AXI response function for axi size err in axi write trans. - 2 - 1 - read-write - - - SPI_MEM_AW_RESP_EN_AXI_FLASH - Set this bit to enable AXI response function for axi flash err in axi write trans. - 3 - 1 - read-write - - - SPI_MEM_AW_RESP_EN_MMU_ECC - Set this bit to enable AXI response function for mmu ecc err in axi write trans. - 4 - 1 - read-write - - - SPI_MEM_AW_RESP_EN_MMU_SENS - Set this bit to enable AXI response function for mmu sens in err axi write trans. - 5 - 1 - read-write - - - SPI_MEM_AW_RESP_EN_AXI_WSTRB - Set this bit to enable AXI response function for axi wstrb err in axi write trans. - 6 - 1 - read-write - - - SPI_MEM_AR_RESP_EN_MMU_VLD - Set this bit to enable AXI response function for mmu valid err in axi read trans. - 7 - 1 - read-write - - - SPI_MEM_AR_RESP_EN_MMU_GID - Set this bit to enable AXI response function for mmu gid err in axi read trans. - 8 - 1 - read-write - - - SPI_MEM_AR_RESP_EN_MMU_ECC - Set this bit to enable AXI response function for mmu ecc err in axi read trans. - 9 - 1 - read-write - - - SPI_MEM_AR_RESP_EN_MMU_SENS - Set this bit to enable AXI response function for mmu sensitive err in axi read trans. - 10 - 1 - read-write - - - SPI_MEM_AR_RESP_EN_AXI_SIZE - Set this bit to enable AXI response function for axi size err in axi read trans. - 11 - 1 - read-write - - - - - SPI_MEM_TIMING_CALI - SPI0 flash timing calibration register - 0x180 - 0x20 - 0x00000001 - - - SPI_MEM_TIMING_CLK_ENA - The bit is used to enable timing adjust clock for all reading operations. - 0 - 1 - read-write - - - SPI_MEM_TIMING_CALI - The bit is used to enable timing auto-calibration for all reading operations. - 1 - 1 - read-write - - - SPI_MEM_EXTRA_DUMMY_CYCLELEN - add extra dummy spi clock cycle length for spi clock calibration. - 2 - 3 - read-write - - - SPI_MEM_DLL_TIMING_CALI - Set this bit to enable DLL for timing calibration in DDR mode when accessed to flash. - 5 - 1 - read-write - - - UPDATE - Set this bit to update delay mode, delay num and extra dummy in MSPI. - 6 - 1 - write-only - - - - - SPI_MEM_DIN_MODE - MSPI flash input timing delay mode control register - 0x184 - 0x20 - - - SPI_MEM_DIN0_MODE - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge - 0 - 3 - read-write - - - SPI_MEM_DIN1_MODE - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge - 3 - 3 - read-write - - - SPI_MEM_DIN2_MODE - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge - 6 - 3 - read-write - - - SPI_MEM_DIN3_MODE - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge - 9 - 3 - read-write - - - SPI_MEM_DIN4_MODE - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk - 12 - 3 - read-write - - - SPI_MEM_DIN5_MODE - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk - 15 - 3 - read-write - - - SPI_MEM_DIN6_MODE - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk - 18 - 3 - read-write - - - SPI_MEM_DIN7_MODE - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk - 21 - 3 - read-write - - - SPI_MEM_DINS_MODE - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk - 24 - 3 - read-write - - - - - SPI_MEM_DIN_NUM - MSPI flash input timing delay number control register - 0x188 - 0x20 - - - SPI_MEM_DIN0_NUM - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... - 0 - 2 - read-write - - - SPI_MEM_DIN1_NUM - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... - 2 - 2 - read-write - - - SPI_MEM_DIN2_NUM - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... - 4 - 2 - read-write - - - SPI_MEM_DIN3_NUM - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... - 6 - 2 - read-write - - - SPI_MEM_DIN4_NUM - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... - 8 - 2 - read-write - - - SPI_MEM_DIN5_NUM - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... - 10 - 2 - read-write - - - SPI_MEM_DIN6_NUM - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... - 12 - 2 - read-write - - - SPI_MEM_DIN7_NUM - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... - 14 - 2 - read-write - - - SPI_MEM_DINS_NUM - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... - 16 - 2 - read-write - - - - - SPI_MEM_DOUT_MODE - MSPI flash output timing adjustment control register - 0x18C - 0x20 - - - SPI_MEM_DOUT0_MODE - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge - 0 - 1 - read-write - - - SPI_MEM_DOUT1_MODE - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge - 1 - 1 - read-write - - - SPI_MEM_DOUT2_MODE - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge - 2 - 1 - read-write - - - SPI_MEM_DOUT3_MODE - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge - 3 - 1 - read-write - - - SPI_MEM_DOUT4_MODE - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk - 4 - 1 - read-write - - - SPI_MEM_DOUT5_MODE - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk - 5 - 1 - read-write - - - SPI_MEM_DOUT6_MODE - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk - 6 - 1 - read-write - - - SPI_MEM_DOUT7_MODE - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk - 7 - 1 - read-write - - - SPI_MEM_DOUTS_MODE - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk - 8 - 1 - read-write - - - - - SPI_SMEM_TIMING_CALI - MSPI external RAM timing calibration register - 0x190 - 0x20 - 0x00000001 - - - SPI_SMEM_TIMING_CLK_ENA - For sram, the bit is used to enable timing adjust clock for all reading operations. - 0 - 1 - read-write - - - SPI_SMEM_TIMING_CALI - For sram, the bit is used to enable timing auto-calibration for all reading operations. - 1 - 1 - read-write - - - SPI_SMEM_EXTRA_DUMMY_CYCLELEN - For sram, add extra dummy spi clock cycle length for spi clock calibration. - 2 - 3 - read-write - - - SPI_SMEM_DLL_TIMING_CALI - Set this bit to enable DLL for timing calibration in DDR mode when accessed to EXT_RAM. - 5 - 1 - read-write - - - - - SPI_SMEM_DIN_MODE - MSPI external RAM input timing delay mode control register - 0x194 - 0x20 - - - SPI_SMEM_DIN0_MODE - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge - 0 - 3 - read-write - - - SPI_SMEM_DIN1_MODE - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge - 3 - 3 - read-write - - - SPI_SMEM_DIN2_MODE - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge - 6 - 3 - read-write - - - SPI_SMEM_DIN3_MODE - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge - 9 - 3 - read-write - - - SPI_SMEM_DIN4_MODE - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge - 12 - 3 - read-write - - - SPI_SMEM_DIN5_MODE - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge - 15 - 3 - read-write - - - SPI_SMEM_DIN6_MODE - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge - 18 - 3 - read-write - - - SPI_SMEM_DIN7_MODE - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge - 21 - 3 - read-write - - - SPI_SMEM_DINS_MODE - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge - 24 - 3 - read-write - - - - - SPI_SMEM_DIN_NUM - MSPI external RAM input timing delay number control register - 0x198 - 0x20 - - - SPI_SMEM_DIN0_NUM - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... - 0 - 2 - read-write - - - SPI_SMEM_DIN1_NUM - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... - 2 - 2 - read-write - - - SPI_SMEM_DIN2_NUM - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... - 4 - 2 - read-write - - - SPI_SMEM_DIN3_NUM - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... - 6 - 2 - read-write - - - SPI_SMEM_DIN4_NUM - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... - 8 - 2 - read-write - - - SPI_SMEM_DIN5_NUM - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... - 10 - 2 - read-write - - - SPI_SMEM_DIN6_NUM - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... - 12 - 2 - read-write - - - SPI_SMEM_DIN7_NUM - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... - 14 - 2 - read-write - - - SPI_SMEM_DINS_NUM - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... - 16 - 2 - read-write - - - - - SPI_SMEM_DOUT_MODE - MSPI external RAM output timing adjustment control register - 0x19C - 0x20 - - - SPI_SMEM_DOUT0_MODE - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge - 0 - 1 - read-write - - - SPI_SMEM_DOUT1_MODE - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge - 1 - 1 - read-write - - - SPI_SMEM_DOUT2_MODE - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge - 2 - 1 - read-write - - - SPI_SMEM_DOUT3_MODE - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge - 3 - 1 - read-write - - - SPI_SMEM_DOUT4_MODE - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge - 4 - 1 - read-write - - - SPI_SMEM_DOUT5_MODE - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge - 5 - 1 - read-write - - - SPI_SMEM_DOUT6_MODE - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge - 6 - 1 - read-write - - - SPI_SMEM_DOUT7_MODE - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge - 7 - 1 - read-write - - - SPI_SMEM_DOUTS_MODE - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge - 8 - 1 - read-write - - - - - SPI_SMEM_AC - MSPI external RAM ECC and SPI CS timing control register - 0x1A0 - 0x20 - 0x8000B084 - - - SPI_SMEM_CS_SETUP - For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: disable. - 0 - 1 - read-write - - - SPI_SMEM_CS_HOLD - For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disable. - 1 - 1 - read-write - - - SPI_SMEM_CS_SETUP_TIME - For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit. - 2 - 5 - read-write - - - SPI_SMEM_CS_HOLD_TIME - For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit. - 7 - 5 - read-write - - - SPI_SMEM_ECC_CS_HOLD_TIME - SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold cycles in ECC mode when accessed external RAM. - 12 - 3 - read-write - - - SPI_SMEM_ECC_SKIP_PAGE_CORNER - 1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner when accesses external RAM. - 15 - 1 - read-write - - - SPI_SMEM_ECC_16TO18_BYTE_EN - Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses external RAM. - 16 - 1 - read-write - - - SPI_SMEM_CS_HOLD_DELAY - These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles. - 25 - 6 - read-write - - - SPI_SMEM_SPLIT_TRANS_EN - Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI transfers when one transfer will cross flash/EXT_RAM page corner, valid no matter whether there is an ECC region or not. - 31 - 1 - read-write - - - - - SPI_SMEM_DIN_HEX_MODE - MSPI 16x external RAM input timing delay mode control register - 0x1A4 - 0x20 - - - SPI_SMEM_DIN08_MODE - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge - 0 - 3 - read-write - - - SPI_SMEM_DIN09_MODE - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge - 3 - 3 - read-write - - - SPI_SMEM_DIN10_MODE - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge - 6 - 3 - read-write - - - SPI_SMEM_DIN11_MODE - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge - 9 - 3 - read-write - - - SPI_SMEM_DIN12_MODE - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge - 12 - 3 - read-write - - - SPI_SMEM_DIN13_MODE - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge - 15 - 3 - read-write - - - SPI_SMEM_DIN14_MODE - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge - 18 - 3 - read-write - - - SPI_SMEM_DIN15_MODE - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge - 21 - 3 - read-write - - - SPI_SMEM_DINS_HEX_MODE - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge - 24 - 3 - read-write - - - - - SPI_SMEM_DIN_HEX_NUM - MSPI 16x external RAM input timing delay number control register - 0x1A8 - 0x20 - - - SPI_SMEM_DIN08_NUM - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... - 0 - 2 - read-write - - - SPI_SMEM_DIN09_NUM - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... - 2 - 2 - read-write - - - SPI_SMEM_DIN10_NUM - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... - 4 - 2 - read-write - - - SPI_SMEM_DIN11_NUM - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... - 6 - 2 - read-write - - - SPI_SMEM_DIN12_NUM - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... - 8 - 2 - read-write - - - SPI_SMEM_DIN13_NUM - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... - 10 - 2 - read-write - - - SPI_SMEM_DIN14_NUM - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... - 12 - 2 - read-write - - - SPI_SMEM_DIN15_NUM - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... - 14 - 2 - read-write - - - SPI_SMEM_DINS_HEX_NUM - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... - 16 - 2 - read-write - - - - - SPI_SMEM_DOUT_HEX_MODE - MSPI 16x external RAM output timing adjustment control register - 0x1AC - 0x20 - - - SPI_SMEM_DOUT08_MODE - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge - 0 - 1 - read-write - - - SPI_SMEM_DOUT09_MODE - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge - 1 - 1 - read-write - - - SPI_SMEM_DOUT10_MODE - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge - 2 - 1 - read-write - - - SPI_SMEM_DOUT11_MODE - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge - 3 - 1 - read-write - - - SPI_SMEM_DOUT12_MODE - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge - 4 - 1 - read-write - - - SPI_SMEM_DOUT13_MODE - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge - 5 - 1 - read-write - - - SPI_SMEM_DOUT14_MODE - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge - 6 - 1 - read-write - - - SPI_SMEM_DOUT15_MODE - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge - 7 - 1 - read-write - - - SPI_SMEM_DOUTS_HEX_MODE - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge - 8 - 1 - read-write - - - - - SPI_MEM_CLOCK_GATE - SPI0 clock gate register - 0x200 - 0x20 - 0x00000001 - - - SPI_CLK_EN - Register clock gate enable signal. 1: Enable. 0: Disable. - 0 - 1 - read-write - - - - - SPI_MEM_XTS_PLAIN_BASE - The base address of the memory that stores plaintext in Manual Encryption - 0x300 - 0x20 - - - SPI_XTS_PLAIN - This field is only used to generate include file in c case. This field is useless. Please do not use this field. - 0 - 32 - read-write - - - - - SPI_MEM_XTS_LINESIZE - Manual Encryption Line-Size register - 0x340 - 0x20 - - - SPI_XTS_LINESIZE - This bits stores the line-size parameter which will be used in manual encryption calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, 1: 32-bytes, 2: 64-bytes, 3:reserved. - 0 - 2 - read-write - - - - - SPI_MEM_XTS_DESTINATION - Manual Encryption destination register - 0x344 - 0x20 - - - SPI_XTS_DESTINATION - This bit stores the destination parameter which will be used in manual encryption calculation. 0: flash(default), 1: psram(reserved). Only default value can be used. - 0 - 1 - read-write - - - - - SPI_MEM_XTS_PHYSICAL_ADDRESS - Manual Encryption physical address register - 0x348 - 0x20 - - - SPI_XTS_PHYSICAL_ADDRESS - This bits stores the physical-address parameter which will be used in manual encryption calculation. This value should aligned with byte number decided by line-size parameter. - 0 - 26 - read-write - - - - - SPI_MEM_XTS_TRIGGER - Manual Encryption physical address register - 0x34C - 0x20 - - - SPI_XTS_TRIGGER - Set this bit to trigger the process of manual encryption calculation. This action should only be asserted when manual encryption status is 0. After this action, manual encryption status becomes 1. After calculation is done, manual encryption status becomes 2. - 0 - 1 - write-only - - - - - SPI_MEM_XTS_RELEASE - Manual Encryption physical address register - 0x350 - 0x20 - - - SPI_XTS_RELEASE - Set this bit to release encrypted result to mspi. This action should only be asserted when manual encryption status is 2. After this action, manual encryption status will become 3. - 0 - 1 - write-only - - - - - SPI_MEM_XTS_DESTROY - Manual Encryption physical address register - 0x354 - 0x20 - - - SPI_XTS_DESTROY - Set this bit to destroy encrypted result. This action should be asserted only when manual encryption status is 3. After this action, manual encryption status will become 0. - 0 - 1 - write-only - - - - - SPI_MEM_XTS_STATE - Manual Encryption physical address register - 0x358 - 0x20 - - - SPI_XTS_STATE - This bits stores the status of manual encryption. 0: idle, 1: busy of encryption calculation, 2: encryption calculation is done but the encrypted result is invisible to mspi, 3: the encrypted result is visible to mspi. - 0 - 2 - read-only - - - - - SPI_MEM_XTS_DATE - Manual Encryption version register - 0x35C - 0x20 - 0x20201010 - - - SPI_XTS_DATE - This bits stores the last modified-time of manual encryption feature. - 0 - 30 - read-write - - - - - SPI_MEM_MMU_ITEM_CONTENT - MSPI-MMU item content register - 0x37C - 0x20 - 0x0000037C - - - SPI_MMU_ITEM_CONTENT - MSPI-MMU item content - 0 - 32 - read-write - - - - - SPI_MEM_MMU_ITEM_INDEX - MSPI-MMU item index register - 0x380 - 0x20 - - - SPI_MMU_ITEM_INDEX - MSPI-MMU item index - 0 - 32 - read-write - - - - - SPI_MEM_MMU_POWER_CTRL - MSPI MMU power control register - 0x384 - 0x20 - 0x13200004 - - - SPI_MMU_MEM_FORCE_ON - Set this bit to enable mmu-memory clock force on - 0 - 1 - read-write - - - SPI_MMU_MEM_FORCE_PD - Set this bit to force mmu-memory powerdown - 1 - 1 - read-write - - - SPI_MMU_MEM_FORCE_PU - Set this bit to force mmu-memory powerup, in this case, the power should also be controlled by rtc. - 2 - 1 - read-write - - - SPI_MEM_AUX_CTRL - MMU PSRAM aux control register - 16 - 14 - read-write - - - SPI_MEM_RDN_ENA - ECO register enable bit - 30 - 1 - read-write - - - SPI_MEM_RDN_RESULT - MSPI module clock domain and AXI clock domain ECO register result register - 31 - 1 - read-only - - - - - SPI_MEM_DPA_CTRL - SPI memory cryption DPA register - 0x388 - 0x20 - 0x0000000F - - - SPI_CRYPT_SECURITY_LEVEL - Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-7: The bigger the number is, the more secure the cryption is. (Note that the performance of cryption will decrease together with this number increasing) - 0 - 3 - read-write - - - SPI_CRYPT_CALC_D_DPA_EN - Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that using key 1. - 3 - 1 - read-write - - - SPI_CRYPT_DPA_SELECT_REGISTER - 1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits. - 4 - 1 - read-write - - - - - SPI_MEM_REGISTERRND_ECO_HIGH - MSPI ECO high register - 0x3F0 - 0x20 - 0x0000037C - - - SPI_MEM_REGISTERRND_ECO_HIGH - ECO high register - 0 - 32 - read-write - - - - - SPI_MEM_REGISTERRND_ECO_LOW - MSPI ECO low register - 0x3F4 - 0x20 - 0x0000037C - - - SPI_MEM_REGISTERRND_ECO_LOW - ECO low register - 0 - 32 - read-write - - - - - SPI_MEM_DATE - SPI0 version control register - 0x3FC - 0x20 - 0x02303100 - - - SPI_MEM_DATE - SPI0 register version. - 0 - 28 - read-write - - - - - - - SPI1 - SPI (Serial Peripheral Interface) Controller 1 - SPI1 - 0x5008D000 - - 0x0 - 0xAC - registers - - - - SPI_MEM_CMD - SPI1 memory command register - 0x0 - 0x20 - - - SPI_MEM_MST_ST - The current status of SPI1 master FSM. - 0 - 4 - read-only - - - SPI_MEM_SLV_ST - The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state. - 4 - 4 - read-only - - - SPI_MEM_FLASH_PE - In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable. - 17 - 1 - read-write - - - SPI_MEM_USR - User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. - 18 - 1 - read-write - - - SPI_MEM_FLASH_HPM - Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable. - 19 - 1 - read-write - - - SPI_MEM_FLASH_RES - This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable. - 20 - 1 - read-write - - - SPI_MEM_FLASH_DP - Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. - 21 - 1 - read-write - - - SPI_MEM_FLASH_CE - Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. - 22 - 1 - read-write - - - SPI_MEM_FLASH_BE - Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. - 23 - 1 - read-write - - - SPI_MEM_FLASH_SE - Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. - 24 - 1 - read-write - - - SPI_MEM_FLASH_PP - Page program enable(1 byte ~256 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable. - 25 - 1 - read-write - - - SPI_MEM_FLASH_WRSR - Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. - 26 - 1 - read-write - - - SPI_MEM_FLASH_RDSR - Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. - 27 - 1 - read-write - - - SPI_MEM_FLASH_RDID - Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. - 28 - 1 - read-write - - - SPI_MEM_FLASH_WRDI - Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. - 29 - 1 - read-write - - - SPI_MEM_FLASH_WREN - Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. - 30 - 1 - read-write - - - SPI_MEM_FLASH_READ - Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. - 31 - 1 - read-write - - - - - SPI_MEM_ADDR - SPI1 address register - 0x4 - 0x20 - - - SPI_MEM_USR_ADDR_VALUE - In user mode, it is the memory address. other then the bit0-bit23 is the memory address, the bit24-bit31 are the byte length of a transfer. - 0 - 32 - read-write - - - - - SPI_MEM_CTRL - SPI1 control register. - 0x8 - 0x20 - 0x002CA00C - - - SPI_MEM_FDUMMY_RIN - In the dummy phase of a MSPI read data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller. - 2 - 1 - read-write - - - SPI_MEM_FDUMMY_WOUT - In the dummy phase of a MSPI write data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller. - 3 - 1 - read-write - - - SPI_MEM_FDOUT_OCT - Apply 8 signals during write-data phase 1:enable 0: disable - 4 - 1 - read-write - - - SPI_MEM_FDIN_OCT - Apply 8 signals during read-data phase 1:enable 0: disable - 5 - 1 - read-write - - - SPI_MEM_FADDR_OCT - Apply 8 signals during address phase 1:enable 0: disable - 6 - 1 - read-write - - - SPI_MEM_FCMD_QUAD - Apply 4 signals during command phase 1:enable 0: disable - 8 - 1 - read-write - - - SPI_MEM_FCMD_OCT - Apply 8 signals during command phase 1:enable 0: disable - 9 - 1 - read-write - - - SPI_MEM_FCS_CRC_EN - For SPI1, initialize crc32 module before writing encrypted data to flash. Active low. - 10 - 1 - read-write - - - SPI_MEM_TX_CRC_EN - For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable - 11 - 1 - read-write - - - SPI_MEM_FASTRD_MODE - This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable. - 13 - 1 - read-write - - - SPI_MEM_FREAD_DUAL - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. - 14 - 1 - read-write - - - SPI_MEM_RESANDRES - The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable. - 15 - 1 - read-write - - - SPI_MEM_Q_POL - The bit is used to set MISO line polarity, 1: high 0, low - 18 - 1 - read-write - - - SPI_MEM_D_POL - The bit is used to set MOSI line polarity, 1: high 0, low - 19 - 1 - read-write - - - SPI_MEM_FREAD_QUAD - In the read operations read-data phase apply 4 signals. 1: enable 0: disable. - 20 - 1 - read-write - - - SPI_MEM_WP - Write protect signal output when SPI is idle. 1: output high, 0: output low. - 21 - 1 - read-write - - - SPI_MEM_WRSR_2B - two bytes data will be written to status register when it is set. 1: enable 0: disable. - 22 - 1 - read-write - - - SPI_MEM_FREAD_DIO - In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable. - 23 - 1 - read-write - - - SPI_MEM_FREAD_QIO - In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable. - 24 - 1 - read-write - - - - - SPI_MEM_CTRL1 - SPI1 control1 register. - 0xC - 0x20 - 0x00000FFC - - - SPI_MEM_CLK_MODE - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. - 0 - 2 - read-write - - - SPI_MEM_CS_HOLD_DLY_RES - After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles. - 2 - 10 - read-write - - - - - SPI_MEM_CTRL2 - SPI1 control2 register. - 0x10 - 0x20 - - - SPI_MEM_SYNC_RESET - The FSM will be reset. - 31 - 1 - write-only - - - - - SPI_MEM_CLOCK - SPI1 clock division control register. - 0x14 - 0x20 - 0x00030103 - - - SPI_MEM_CLKCNT_L - In the master mode it must be equal to spi_mem_clkcnt_N. - 0 - 8 - read-write - - - SPI_MEM_CLKCNT_H - In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). - 8 - 8 - read-write - - - SPI_MEM_CLKCNT_N - In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1) - 16 - 8 - read-write - - - SPI_MEM_CLK_EQU_SYSCLK - reserved - 31 - 1 - read-write - - - - - SPI_MEM_USER - SPI1 user register. - 0x18 - 0x20 - 0x80000000 - - - SPI_MEM_CK_OUT_EDGE - the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode. - 9 - 1 - read-write - - - SPI_MEM_FWRITE_DUAL - In the write operations read-data phase apply 2 signals - 12 - 1 - read-write - - - SPI_MEM_FWRITE_QUAD - In the write operations read-data phase apply 4 signals - 13 - 1 - read-write - - - SPI_MEM_FWRITE_DIO - In the write operations address phase and read-data phase apply 2 signals. - 14 - 1 - read-write - - - SPI_MEM_FWRITE_QIO - In the write operations address phase and read-data phase apply 4 signals. - 15 - 1 - read-write - - - SPI_MEM_USR_MISO_HIGHPART - read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable. - 24 - 1 - read-write - - - SPI_MEM_USR_MOSI_HIGHPART - write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable. - 25 - 1 - read-write - - - SPI_MEM_USR_DUMMY_IDLE - SPI clock is disable in dummy phase when the bit is enable. - 26 - 1 - read-write - - - SPI_MEM_USR_MOSI - This bit enable the write-data phase of an operation. - 27 - 1 - read-write - - - SPI_MEM_USR_MISO - This bit enable the read-data phase of an operation. - 28 - 1 - read-write - - - SPI_MEM_USR_DUMMY - This bit enable the dummy phase of an operation. - 29 - 1 - read-write - - - SPI_MEM_USR_ADDR - This bit enable the address phase of an operation. - 30 - 1 - read-write - - - SPI_MEM_USR_COMMAND - This bit enable the command phase of an operation. - 31 - 1 - read-write - - - - - SPI_MEM_USER1 - SPI1 user1 register. - 0x1C - 0x20 - 0x5C000007 - - - SPI_MEM_USR_DUMMY_CYCLELEN - The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1). - 0 - 6 - read-write - - - SPI_MEM_USR_ADDR_BITLEN - The length in bits of address phase. The register value shall be (bit_num-1). - 26 - 6 - read-write - - - - - SPI_MEM_USER2 - SPI1 user2 register. - 0x20 - 0x20 - 0x70000000 - - - SPI_MEM_USR_COMMAND_VALUE - The value of command. - 0 - 16 - read-write - - - SPI_MEM_USR_COMMAND_BITLEN - The length in bits of command phase. The register value shall be (bit_num-1) - 28 - 4 - read-write - - - - - SPI_MEM_MOSI_DLEN - SPI1 send data bit length control register. - 0x24 - 0x20 - - - SPI_MEM_USR_MOSI_DBITLEN - The length in bits of write-data. The register value shall be (bit_num-1). - 0 - 10 - read-write - - - - - SPI_MEM_MISO_DLEN - SPI1 receive data bit length control register. - 0x28 - 0x20 - - - SPI_MEM_USR_MISO_DBITLEN - The length in bits of read-data. The register value shall be (bit_num-1). - 0 - 10 - read-write - - - - - SPI_MEM_RD_STATUS - SPI1 status register. - 0x2C - 0x20 - - - SPI_MEM_STATUS - The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit. - 0 - 16 - read-write - - - SPI_MEM_WB_MODE - Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. - 16 - 8 - read-write - - - - - SPI_MEM_MISC - SPI1 misc register - 0x34 - 0x20 - 0x00000002 - - - SPI_MEM_CS0_DIS - SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI device, such as flash, external RAM and so on. - 0 - 1 - read-write - - - SPI_MEM_CS1_DIS - SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI device, such as flash, external RAM and so on. - 1 - 1 - read-write - - - SPI_MEM_CK_IDLE_EDGE - 1: spi clk line is high when idle 0: spi clk line is low when idle - 9 - 1 - read-write - - - SPI_MEM_CS_KEEP_ACTIVE - spi cs line keep low when the bit is set. - 10 - 1 - read-write - - - - - SPI_MEM_TX_CRC - SPI1 TX CRC data register. - 0x38 - 0x20 - 0xFFFFFFFF - - - DATA - For SPI1, the value of crc32. - 0 - 32 - read-only - - - - - SPI_MEM_CACHE_FCTRL - SPI1 bit mode control register. - 0x3C - 0x20 - - - SPI_MEM_CACHE_USR_ADDR_4BYTE - For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable. - 1 - 1 - read-write - - - SPI_MEM_FDIN_DUAL - For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. - 3 - 1 - read-write - - - SPI_MEM_FDOUT_DUAL - For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. - 4 - 1 - read-write - - - SPI_MEM_FADDR_DUAL - For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. - 5 - 1 - read-write - - - SPI_MEM_FDIN_QUAD - For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. - 6 - 1 - read-write - - - SPI_MEM_FDOUT_QUAD - For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. - 7 - 1 - read-write - - - SPI_MEM_FADDR_QUAD - For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. - 8 - 1 - read-write - - - - - SPI_MEM_W0 - SPI1 memory data buffer0 - 0x58 - 0x20 - - - SPI_MEM_BUF0 - data buffer - 0 - 32 - read-write - - - - - SPI_MEM_W1 - SPI1 memory data buffer1 - 0x5C - 0x20 - - - SPI_MEM_BUF1 - data buffer - 0 - 32 - read-write - - - - - SPI_MEM_W2 - SPI1 memory data buffer2 - 0x60 - 0x20 - - - SPI_MEM_BUF2 - data buffer - 0 - 32 - read-write - - - - - SPI_MEM_W3 - SPI1 memory data buffer3 - 0x64 - 0x20 - - - SPI_MEM_BUF3 - data buffer - 0 - 32 - read-write - - - - - SPI_MEM_W4 - SPI1 memory data buffer4 - 0x68 - 0x20 - - - SPI_MEM_BUF4 - data buffer - 0 - 32 - read-write - - - - - SPI_MEM_W5 - SPI1 memory data buffer5 - 0x6C - 0x20 - - - SPI_MEM_BUF5 - data buffer - 0 - 32 - read-write - - - - - SPI_MEM_W6 - SPI1 memory data buffer6 - 0x70 - 0x20 - - - SPI_MEM_BUF6 - data buffer - 0 - 32 - read-write - - - - - SPI_MEM_W7 - SPI1 memory data buffer7 - 0x74 - 0x20 - - - SPI_MEM_BUF7 - data buffer - 0 - 32 - read-write - - - - - SPI_MEM_W8 - SPI1 memory data buffer8 - 0x78 - 0x20 - - - SPI_MEM_BUF8 - data buffer - 0 - 32 - read-write - - - - - SPI_MEM_W9 - SPI1 memory data buffer9 - 0x7C - 0x20 - - - SPI_MEM_BUF9 - data buffer - 0 - 32 - read-write - - - - - SPI_MEM_W10 - SPI1 memory data buffer10 - 0x80 - 0x20 - - - SPI_MEM_BUF10 - data buffer - 0 - 32 - read-write - - - - - SPI_MEM_W11 - SPI1 memory data buffer11 - 0x84 - 0x20 - - - SPI_MEM_BUF11 - data buffer - 0 - 32 - read-write - - - - - SPI_MEM_W12 - SPI1 memory data buffer12 - 0x88 - 0x20 - - - SPI_MEM_BUF12 - data buffer - 0 - 32 - read-write - - - - - SPI_MEM_W13 - SPI1 memory data buffer13 - 0x8C - 0x20 - - - SPI_MEM_BUF13 - data buffer - 0 - 32 - read-write - - - - - SPI_MEM_W14 - SPI1 memory data buffer14 - 0x90 - 0x20 - - - SPI_MEM_BUF14 - data buffer - 0 - 32 - read-write - - - - - SPI_MEM_W15 - SPI1 memory data buffer15 - 0x94 - 0x20 - - - SPI_MEM_BUF15 - data buffer - 0 - 32 - read-write - - - - - SPI_MEM_FLASH_WAITI_CTRL - SPI1 wait idle control register - 0x98 - 0x20 - 0x00050001 - - - SPI_MEM_WAITI_EN - 1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto Suspend/Resume are not supported. - 0 - 1 - read-write - - - SPI_MEM_WAITI_DUMMY - The dummy phase enable when wait flash idle (RDSR) - 1 - 1 - read-write - - - SPI_MEM_WAITI_ADDR_EN - 1: Output address 0 in RDSR or read SUS command transfer. 0: Do not send out address in RDSR or read SUS command transfer. - 2 - 1 - read-write - - - SPI_MEM_WAITI_ADDR_CYCLELEN - When SPI_MEM_WAITI_ADDR_EN is set, the cycle length of sent out address is (SPI_MEM_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI bus clock cycles. It is not active when SPI_MEM_WAITI_ADDR_EN is cleared. - 3 - 2 - read-write - - - SPI_MEM_WAITI_CMD_2B - 1:The wait idle command bit length is 16. 0: The wait idle command bit length is 8. - 9 - 1 - read-write - - - SPI_MEM_WAITI_DUMMY_CYCLELEN - The dummy cycle length when wait flash idle(RDSR). - 10 - 6 - read-write - - - SPI_MEM_WAITI_CMD - The command value to wait flash idle(RDSR). - 16 - 16 - read-write - - - - - SPI_MEM_FLASH_SUS_CTRL - SPI1 flash suspend control register - 0x9C - 0x20 - 0x08002000 - - - SPI_MEM_FLASH_PER - program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. - 0 - 1 - read-write - - - SPI_MEM_FLASH_PES - program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. - 1 - 1 - read-write - - - SPI_MEM_FLASH_PER_WAIT_EN - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase resume command is sent. 0: SPI1 does not wait after program erase resume command is sent. - 2 - 1 - read-write - - - SPI_MEM_FLASH_PES_WAIT_EN - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase suspend command is sent. 0: SPI1 does not wait after program erase suspend command is sent. - 3 - 1 - read-write - - - SPI_MEM_PES_PER_EN - Set this bit to enable PES end triggers PER transfer option. If this bit is 0, application should send PER after PES is done. - 4 - 1 - read-write - - - SPI_MEM_FLASH_PES_EN - Set this bit to enable Auto-suspending function. - 5 - 1 - read-write - - - SPI_MEM_PESR_END_MSK - The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0]. - 6 - 16 - read-write - - - SPI_FMEM_RD_SUS_2B - 1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte when check flash SUS/SUS1/SUS2 status bit - 22 - 1 - read-write - - - SPI_MEM_PER_END_EN - 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0. - 23 - 1 - read-write - - - SPI_MEM_PES_END_EN - 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0. - 24 - 1 - read-write - - - SPI_MEM_SUS_TIMEOUT_CNT - When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, it will be treated as check pass. - 25 - 7 - read-write - - - - - SPI_MEM_FLASH_SUS_CMD - SPI1 flash suspend command register - 0xA0 - 0x20 - 0x00057575 - - - SPI_MEM_FLASH_PES_COMMAND - Program/Erase suspend command. - 0 - 16 - read-write - - - SPI_MEM_WAIT_PESR_COMMAND - Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash. - 16 - 16 - read-write - - - - - SPI_MEM_SUS_STATUS - SPI1 flash suspend status register - 0xA4 - 0x20 - 0x7A7A0000 - - - SPI_MEM_FLASH_SUS - The status of flash suspend, only used in SPI1. - 0 - 1 - read-write - - - SPI_MEM_WAIT_PESR_CMD_2B - 1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit. - 1 - 1 - read-write - - - SPI_MEM_FLASH_HPM_DLY_128 - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent. - 2 - 1 - read-write - - - SPI_MEM_FLASH_RES_DLY_128 - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent. - 3 - 1 - read-write - - - SPI_MEM_FLASH_DP_DLY_128 - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent. - 4 - 1 - read-write - - - SPI_MEM_FLASH_PER_DLY_128 - Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent. - 5 - 1 - read-write - - - SPI_MEM_FLASH_PES_DLY_128 - Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent. - 6 - 1 - read-write - - - SPI_MEM_SPI0_LOCK_EN - 1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it. - 7 - 1 - read-write - - - SPI_MEM_FLASH_PESR_CMD_2B - 1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit length of Program/Erase Suspend/Resume command is 8. - 15 - 1 - read-write - - - SPI_MEM_FLASH_PER_COMMAND - Program/Erase resume command. - 16 - 16 - read-write - - - - - SPI_MEM_INT_ENA - SPI1 interrupt enable register - 0xC0 - 0x20 - - - SPI_MEM_PER_END_INT_ENA - The enable bit for SPI_MEM_PER_END_INT interrupt. - 0 - 1 - read-write - - - SPI_MEM_PES_END_INT_ENA - The enable bit for SPI_MEM_PES_END_INT interrupt. - 1 - 1 - read-write - - - SPI_MEM_WPE_END_INT_ENA - The enable bit for SPI_MEM_WPE_END_INT interrupt. - 2 - 1 - read-write - - - SPI_MEM_SLV_ST_END_INT_ENA - The enable bit for SPI_MEM_SLV_ST_END_INT interrupt. - 3 - 1 - read-write - - - SPI_MEM_MST_ST_END_INT_ENA - The enable bit for SPI_MEM_MST_ST_END_INT interrupt. - 4 - 1 - read-write - - - SPI_MEM_BROWN_OUT_INT_ENA - The enable bit for SPI_MEM_BROWN_OUT_INT interrupt. - 10 - 1 - read-write - - - - - SPI_MEM_INT_CLR - SPI1 interrupt clear register - 0xC4 - 0x20 - - - SPI_MEM_PER_END_INT_CLR - The clear bit for SPI_MEM_PER_END_INT interrupt. - 0 - 1 - write-only - - - SPI_MEM_PES_END_INT_CLR - The clear bit for SPI_MEM_PES_END_INT interrupt. - 1 - 1 - write-only - - - SPI_MEM_WPE_END_INT_CLR - The clear bit for SPI_MEM_WPE_END_INT interrupt. - 2 - 1 - write-only - - - SPI_MEM_SLV_ST_END_INT_CLR - The clear bit for SPI_MEM_SLV_ST_END_INT interrupt. - 3 - 1 - write-only - - - SPI_MEM_MST_ST_END_INT_CLR - The clear bit for SPI_MEM_MST_ST_END_INT interrupt. - 4 - 1 - write-only - - - SPI_MEM_BROWN_OUT_INT_CLR - The status bit for SPI_MEM_BROWN_OUT_INT interrupt. - 10 - 1 - write-only - - - - - SPI_MEM_INT_RAW - SPI1 interrupt raw register - 0xC8 - 0x20 - - - SPI_MEM_PER_END_INT_RAW - The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed successfully. 0: Others. - 0 - 1 - read-write - - - SPI_MEM_PES_END_INT_RAW - The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended successfully. 0: Others. - 1 - 1 - read-write - - - SPI_MEM_WPE_END_INT_RAW - The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others. - 2 - 1 - read-write - - - SPI_MEM_SLV_ST_END_INT_RAW - The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others - 3 - 1 - read-write - - - SPI_MEM_MST_ST_END_INT_RAW - The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is changed from non idle state to idle state. 0: Others. - 4 - 1 - read-write - - - SPI_MEM_BROWN_OUT_INT_RAW - The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is loosing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others. - 10 - 1 - read-write - - - - - SPI_MEM_INT_ST - SPI1 interrupt status register - 0xCC - 0x20 - - - SPI_MEM_PER_END_INT_ST - The status bit for SPI_MEM_PER_END_INT interrupt. - 0 - 1 - read-only - - - SPI_MEM_PES_END_INT_ST - The status bit for SPI_MEM_PES_END_INT interrupt. - 1 - 1 - read-only - - - SPI_MEM_WPE_END_INT_ST - The status bit for SPI_MEM_WPE_END_INT interrupt. - 2 - 1 - read-only - - - SPI_MEM_SLV_ST_END_INT_ST - The status bit for SPI_MEM_SLV_ST_END_INT interrupt. - 3 - 1 - read-only - - - SPI_MEM_MST_ST_END_INT_ST - The status bit for SPI_MEM_MST_ST_END_INT interrupt. - 4 - 1 - read-only - - - SPI_MEM_BROWN_OUT_INT_ST - The status bit for SPI_MEM_BROWN_OUT_INT interrupt. - 10 - 1 - read-only - - - - - SPI_MEM_DDR - SPI1 DDR control register - 0xD4 - 0x20 - 0x00000020 - - - SPI_FMEM_DDR_EN - 1: in ddr mode, 0 in sdr mode - 0 - 1 - read-write - - - SPI_FMEM_VAR_DUMMY - Set the bit to enable variable dummy cycle in spi ddr mode. - 1 - 1 - read-write - - - SPI_FMEM_DDR_RDAT_SWP - Set the bit to reorder rx data of the word in spi ddr mode. - 2 - 1 - read-write - - - SPI_FMEM_DDR_WDAT_SWP - Set the bit to reorder tx data of the word in spi ddr mode. - 3 - 1 - read-write - - - SPI_FMEM_DDR_CMD_DIS - the bit is used to disable dual edge in command phase when ddr mode. - 4 - 1 - read-write - - - SPI_FMEM_OUTMINBYTELEN - It is the minimum output data length in the panda device. - 5 - 7 - read-write - - - SPI_FMEM_USR_DDR_DQS_THD - The delay number of data strobe which from memory based on SPI clock. - 14 - 7 - read-write - - - SPI_FMEM_DDR_DQS_LOOP - 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS. - 21 - 1 - read-write - - - SPI_FMEM_CLK_DIFF_EN - Set this bit to enable the differential SPI_CLK#. - 24 - 1 - read-write - - - SPI_FMEM_DQS_CA_IN - Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. - 26 - 1 - read-write - - - SPI_FMEM_HYPERBUS_DUMMY_2X - Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram. - 27 - 1 - read-write - - - SPI_FMEM_CLK_DIFF_INV - Set this bit to invert SPI_DIFF when accesses to flash. . - 28 - 1 - read-write - - - SPI_FMEM_OCTA_RAM_ADDR - Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. - 29 - 1 - read-write - - - SPI_FMEM_HYPERBUS_CA - Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. - 30 - 1 - read-write - - - - - SPI_MEM_TIMING_CALI - SPI1 timing control register - 0x180 - 0x20 - - - SPI_MEM_TIMING_CALI - The bit is used to enable timing auto-calibration for all reading operations. - 1 - 1 - read-write - - - SPI_MEM_EXTRA_DUMMY_CYCLELEN - add extra dummy spi clock cycle length for spi clock calibration. - 2 - 3 - read-write - - - - - SPI_MEM_CLOCK_GATE - SPI1 clk_gate register - 0x200 - 0x20 - 0x00000001 - - - SPI_MEM_CLK_EN - Register clock gate enable signal. 1: Enable. 0: Disable. - 0 - 1 - read-write - - - - - SPI_MEM_DATE - Version control register - 0x3FC - 0x20 - 0x02111240 - - - SPI_MEM_DATE - Version control register - 0 - 28 - read-write - - - - - - - SPI2 - SPI (Serial Peripheral Interface) Controller 2 - SPI2 - 0x500D0000 - - 0x0 - 0x98 - registers - - - SPI2 - 25 - - - - SPI_CMD - Command control register - 0x0 - 0x20 - - - SPI_CONF_BITLEN - Define the APB cycles of SPI_CONF state. Can be configured in CONF state. - 0 - 18 - read-write - - - SPI_UPDATE - Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode. - 23 - 1 - write-only - - - SPI_USR - User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf. - 24 - 1 - read-write - - - - - SPI_ADDR - Address value register - 0x4 - 0x20 - - - SPI_USR_ADDR_VALUE - Address to slave. Can be configured in CONF state. - 0 - 32 - read-write - - - - - SPI_CTRL - SPI control register - 0x8 - 0x20 - 0x003C0000 - - - SPI_DUMMY_OUT - 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state. - 3 - 1 - read-write - - - SPI_FADDR_DUAL - Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state. - 5 - 1 - read-write - - - SPI_FADDR_QUAD - Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state. - 6 - 1 - read-write - - - SPI_FADDR_OCT - Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF state. - 7 - 1 - read-write - - - SPI_FCMD_DUAL - Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state. - 8 - 1 - read-write - - - SPI_FCMD_QUAD - Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state. - 9 - 1 - read-write - - - SPI_FCMD_OCT - Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF state. - 10 - 1 - read-write - - - SPI_FREAD_DUAL - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state. - 14 - 1 - read-write - - - SPI_FREAD_QUAD - In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state. - 15 - 1 - read-write - - - SPI_FREAD_OCT - In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can be configured in CONF state. - 16 - 1 - read-write - - - SPI_Q_POL - The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state. - 18 - 1 - read-write - - - SPI_D_POL - The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state. - 19 - 1 - read-write - - - SPI_HOLD_POL - SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state. - 20 - 1 - read-write - - - SPI_WP_POL - Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state. - 21 - 1 - read-write - - - SPI_RD_BIT_ORDER - In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state. - 23 - 2 - read-write - - - SPI_WR_BIT_ORDER - In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state. - 25 - 2 - read-write - - - - - SPI_CLOCK - SPI clock control register - 0xC - 0x20 - 0x80003043 - - - SPI_CLKCNT_L - In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state. - 0 - 6 - read-write - - - SPI_CLKCNT_H - In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state. - 6 - 6 - read-write - - - SPI_CLKCNT_N - In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state. - 12 - 6 - read-write - - - SPI_CLKDIV_PRE - In the master mode it is pre-divider of spi_clk. Can be configured in CONF state. - 18 - 4 - read-write - - - SPI_CLK_EQU_SYSCLK - In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state. - 31 - 1 - read-write - - - - - SPI_USER - SPI USER control register - 0x10 - 0x20 - 0x800000C0 - - - SPI_DOUTDIN - Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state. - 0 - 1 - read-write - - - SPI_QPI_MODE - Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state. - 3 - 1 - read-write - - - SPI_OPI_MODE - Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. Can be configured in CONF state. - 4 - 1 - read-write - - - SPI_TSCK_I_EDGE - In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i. - 5 - 1 - read-write - - - SPI_CS_HOLD - spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state. - 6 - 1 - read-write - - - SPI_CS_SETUP - spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state. - 7 - 1 - read-write - - - SPI_RSCK_I_EDGE - In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i. - 8 - 1 - read-write - - - SPI_CK_OUT_EDGE - the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state. - 9 - 1 - read-write - - - SPI_FWRITE_DUAL - In the write operations read-data phase apply 2 signals. Can be configured in CONF state. - 12 - 1 - read-write - - - SPI_FWRITE_QUAD - In the write operations read-data phase apply 4 signals. Can be configured in CONF state. - 13 - 1 - read-write - - - SPI_FWRITE_OCT - In the write operations read-data phase apply 8 signals. Can be configured in CONF state. - 14 - 1 - read-write - - - SPI_USR_CONF_NXT - 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state. - 15 - 1 - read-write - - - SPI_SIO - Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state. - 17 - 1 - read-write - - - SPI_USR_MISO_HIGHPART - read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state. - 24 - 1 - read-write - - - SPI_USR_MOSI_HIGHPART - write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state. - 25 - 1 - read-write - - - SPI_USR_DUMMY_IDLE - spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state. - 26 - 1 - read-write - - - SPI_USR_MOSI - This bit enable the write-data phase of an operation. Can be configured in CONF state. - 27 - 1 - read-write - - - SPI_USR_MISO - This bit enable the read-data phase of an operation. Can be configured in CONF state. - 28 - 1 - read-write - - - SPI_USR_DUMMY - This bit enable the dummy phase of an operation. Can be configured in CONF state. - 29 - 1 - read-write - - - SPI_USR_ADDR - This bit enable the address phase of an operation. Can be configured in CONF state. - 30 - 1 - read-write - - - SPI_USR_COMMAND - This bit enable the command phase of an operation. Can be configured in CONF state. - 31 - 1 - read-write - - - - - SPI_USER1 - SPI USER control register 1 - 0x14 - 0x20 - 0xB8410007 - - - SPI_USR_DUMMY_CYCLELEN - The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state. - 0 - 8 - read-write - - - SPI_MST_WFULL_ERR_END_EN - 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. - 16 - 1 - read-write - - - SPI_CS_SETUP_TIME - (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state. - 17 - 5 - read-write - - - SPI_CS_HOLD_TIME - delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state. - 22 - 5 - read-write - - - SPI_USR_ADDR_BITLEN - The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state. - 27 - 5 - read-write - - - - - SPI_USER2 - SPI USER control register 2 - 0x18 - 0x20 - 0x78000000 - - - SPI_USR_COMMAND_VALUE - The value of command. Can be configured in CONF state. - 0 - 16 - read-write - - - SPI_MST_REMPTY_ERR_END_EN - 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. - 27 - 1 - read-write - - - SPI_USR_COMMAND_BITLEN - The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state. - 28 - 4 - read-write - - - - - SPI_MS_DLEN - SPI data bit length control register - 0x1C - 0x20 - - - SPI_MS_DATA_BITLEN - The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state. - 0 - 18 - read-write - - - - - SPI_MISC - SPI misc register - 0x20 - 0x20 - 0x0000003E - - - SPI_CS0_DIS - SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state. - 0 - 1 - read-write - - - SPI_CS1_DIS - SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state. - 1 - 1 - read-write - - - SPI_CS2_DIS - SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state. - 2 - 1 - read-write - - - SPI_CS3_DIS - SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to CS3 pin. Can be configured in CONF state. - 3 - 1 - read-write - - - SPI_CS4_DIS - SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be configured in CONF state. - 4 - 1 - read-write - - - SPI_CS5_DIS - SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be configured in CONF state. - 5 - 1 - read-write - - - SPI_CK_DIS - 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state. - 6 - 1 - read-write - - - SPI_MASTER_CS_POL - In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state. - 7 - 6 - read-write - - - SPI_CLK_DATA_DTR_EN - 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR mode is only applied to spi_dqs. This bit should be used with bit 17/18/19. - 16 - 1 - read-write - - - SPI_DATA_DTR_EN - 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state. - 17 - 1 - read-write - - - SPI_ADDR_DTR_EN - 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state. - 18 - 1 - read-write - - - SPI_CMD_DTR_EN - 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state. - 19 - 1 - read-write - - - SPI_SLAVE_CS_POL - spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state. - 23 - 1 - read-write - - - SPI_DQS_IDLE_EDGE - The default value of spi_dqs. Can be configured in CONF state. - 24 - 1 - read-write - - - SPI_CK_IDLE_EDGE - 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state. - 29 - 1 - read-write - - - SPI_CS_KEEP_ACTIVE - spi cs line keep low when the bit is set. Can be configured in CONF state. - 30 - 1 - read-write - - - SPI_QUAD_DIN_PIN_SWAP - 1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0: spi quad input swap disable. Can be configured in CONF state. - 31 - 1 - read-write - - - - - SPI_DIN_MODE - SPI input delay mode configuration - 0x24 - 0x20 - - - SPI_DIN0_MODE - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. - 0 - 2 - read-write - - - SPI_DIN1_MODE - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. - 2 - 2 - read-write - - - SPI_DIN2_MODE - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. - 4 - 2 - read-write - - - SPI_DIN3_MODE - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. - 6 - 2 - read-write - - - SPI_DIN4_MODE - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. - 8 - 2 - read-write - - - SPI_DIN5_MODE - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. - 10 - 2 - read-write - - - SPI_DIN6_MODE - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. - 12 - 2 - read-write - - - SPI_DIN7_MODE - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. - 14 - 2 - read-write - - - SPI_TIMING_HCLK_ACTIVE - 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state. - 16 - 1 - read-write - - - - - SPI_DIN_NUM - SPI input delay number configuration - 0x28 - 0x20 - - - SPI_DIN0_NUM - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. - 0 - 2 - read-write - - - SPI_DIN1_NUM - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. - 2 - 2 - read-write - - - SPI_DIN2_NUM - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. - 4 - 2 - read-write - - - SPI_DIN3_NUM - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. - 6 - 2 - read-write - - - SPI_DIN4_NUM - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. - 8 - 2 - read-write - - - SPI_DIN5_NUM - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. - 10 - 2 - read-write - - - SPI_DIN6_NUM - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. - 12 - 2 - read-write - - - SPI_DIN7_NUM - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. - 14 - 2 - read-write - - - - - SPI_DOUT_MODE - SPI output delay mode configuration - 0x2C - 0x20 - - - SPI_DOUT0_MODE - The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. - 0 - 1 - read-write - - - SPI_DOUT1_MODE - The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. - 1 - 1 - read-write - - - SPI_DOUT2_MODE - The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. - 2 - 1 - read-write - - - SPI_DOUT3_MODE - The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. - 3 - 1 - read-write - - - SPI_DOUT4_MODE - The output signal 4 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. - 4 - 1 - read-write - - - SPI_DOUT5_MODE - The output signal 5 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. - 5 - 1 - read-write - - - SPI_DOUT6_MODE - The output signal 6 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. - 6 - 1 - read-write - - - SPI_DOUT7_MODE - The output signal 7 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. - 7 - 1 - read-write - - - SPI_D_DQS_MODE - The output signal SPI_DQS is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. - 8 - 1 - read-write - - - - - SPI_DMA_CONF - SPI DMA control register - 0x30 - 0x20 - 0x00000003 - - - SPI_DMA_OUTFIFO_EMPTY - Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: DMA TX FIFO is ready for sending data. - 0 - 1 - read-only - - - SPI_DMA_INFIFO_FULL - Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. 0: DMA RX FIFO is ready for receiving data. - 1 - 1 - read-only - - - SPI_DMA_SLV_SEG_TRANS_EN - Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable. - 18 - 1 - read-write - - - SPI_SLV_RX_SEG_TRANS_CLR_EN - 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done. - 19 - 1 - read-write - - - SPI_SLV_TX_SEG_TRANS_CLR_EN - 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done. - 20 - 1 - read-write - - - SPI_RX_EOF_EN - 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans. - 21 - 1 - read-write - - - SPI_DMA_RX_ENA - Set this bit to enable SPI DMA controlled receive data mode. - 27 - 1 - read-write - - - SPI_DMA_TX_ENA - Set this bit to enable SPI DMA controlled send data mode. - 28 - 1 - read-write - - - SPI_RX_AFIFO_RST - Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer. - 29 - 1 - write-only - - - SPI_BUF_AFIFO_RST - Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer. - 30 - 1 - write-only - - - SPI_DMA_AFIFO_RST - Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer. - 31 - 1 - write-only - - - - - SPI_DMA_INT_ENA - SPI interrupt enable register - 0x34 - 0x20 - - - SPI_DMA_INFIFO_FULL_ERR_INT_ENA - The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. - 0 - 1 - read-write - - - SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA - The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. - 1 - 1 - read-write - - - SPI_SLV_EX_QPI_INT_ENA - The enable bit for SPI slave Ex_QPI interrupt. - 2 - 1 - read-write - - - SPI_SLV_EN_QPI_INT_ENA - The enable bit for SPI slave En_QPI interrupt. - 3 - 1 - read-write - - - SPI_SLV_CMD7_INT_ENA - The enable bit for SPI slave CMD7 interrupt. - 4 - 1 - read-write - - - SPI_SLV_CMD8_INT_ENA - The enable bit for SPI slave CMD8 interrupt. - 5 - 1 - read-write - - - SPI_SLV_CMD9_INT_ENA - The enable bit for SPI slave CMD9 interrupt. - 6 - 1 - read-write - - - SPI_SLV_CMDA_INT_ENA - The enable bit for SPI slave CMDA interrupt. - 7 - 1 - read-write - - - SPI_SLV_RD_DMA_DONE_INT_ENA - The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt. - 8 - 1 - read-write - - - SPI_SLV_WR_DMA_DONE_INT_ENA - The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt. - 9 - 1 - read-write - - - SPI_SLV_RD_BUF_DONE_INT_ENA - The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt. - 10 - 1 - read-write - - - SPI_SLV_WR_BUF_DONE_INT_ENA - The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt. - 11 - 1 - read-write - - - SPI_TRANS_DONE_INT_ENA - The enable bit for SPI_TRANS_DONE_INT interrupt. - 12 - 1 - read-write - - - SPI_DMA_SEG_TRANS_DONE_INT_ENA - The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. - 13 - 1 - read-write - - - SPI_SEG_MAGIC_ERR_INT_ENA - The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt. - 14 - 1 - read-write - - - SPI_SLV_BUF_ADDR_ERR_INT_ENA - The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. - 15 - 1 - read-write - - - SPI_SLV_CMD_ERR_INT_ENA - The enable bit for SPI_SLV_CMD_ERR_INT interrupt. - 16 - 1 - read-write - - - SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA - The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. - 17 - 1 - read-write - - - SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA - The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. - 18 - 1 - read-write - - - SPI_APP2_INT_ENA - The enable bit for SPI_APP2_INT interrupt. - 19 - 1 - read-write - - - SPI_APP1_INT_ENA - The enable bit for SPI_APP1_INT interrupt. - 20 - 1 - read-write - - - - - SPI_DMA_INT_CLR - SPI interrupt clear register - 0x38 - 0x20 - - - SPI_DMA_INFIFO_FULL_ERR_INT_CLR - The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. - 0 - 1 - write-only - - - SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR - The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. - 1 - 1 - write-only - - - SPI_SLV_EX_QPI_INT_CLR - The clear bit for SPI slave Ex_QPI interrupt. - 2 - 1 - write-only - - - SPI_SLV_EN_QPI_INT_CLR - The clear bit for SPI slave En_QPI interrupt. - 3 - 1 - write-only - - - SPI_SLV_CMD7_INT_CLR - The clear bit for SPI slave CMD7 interrupt. - 4 - 1 - write-only - - - SPI_SLV_CMD8_INT_CLR - The clear bit for SPI slave CMD8 interrupt. - 5 - 1 - write-only - - - SPI_SLV_CMD9_INT_CLR - The clear bit for SPI slave CMD9 interrupt. - 6 - 1 - write-only - - - SPI_SLV_CMDA_INT_CLR - The clear bit for SPI slave CMDA interrupt. - 7 - 1 - write-only - - - SPI_SLV_RD_DMA_DONE_INT_CLR - The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt. - 8 - 1 - write-only - - - SPI_SLV_WR_DMA_DONE_INT_CLR - The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt. - 9 - 1 - write-only - - - SPI_SLV_RD_BUF_DONE_INT_CLR - The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt. - 10 - 1 - write-only - - - SPI_SLV_WR_BUF_DONE_INT_CLR - The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt. - 11 - 1 - write-only - - - SPI_TRANS_DONE_INT_CLR - The clear bit for SPI_TRANS_DONE_INT interrupt. - 12 - 1 - write-only - - - SPI_DMA_SEG_TRANS_DONE_INT_CLR - The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. - 13 - 1 - write-only - - - SPI_SEG_MAGIC_ERR_INT_CLR - The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt. - 14 - 1 - write-only - - - SPI_SLV_BUF_ADDR_ERR_INT_CLR - The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. - 15 - 1 - write-only - - - SPI_SLV_CMD_ERR_INT_CLR - The clear bit for SPI_SLV_CMD_ERR_INT interrupt. - 16 - 1 - write-only - - - SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR - The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. - 17 - 1 - write-only - - - SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR - The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. - 18 - 1 - write-only - - - SPI_APP2_INT_CLR - The clear bit for SPI_APP2_INT interrupt. - 19 - 1 - write-only - - - SPI_APP1_INT_CLR - The clear bit for SPI_APP1_INT interrupt. - 20 - 1 - write-only - - - - - SPI_DMA_INT_RAW - SPI interrupt raw register - 0x3C - 0x20 - - - SPI_DMA_INFIFO_FULL_ERR_INT_RAW - 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others. - 0 - 1 - read-write - - - SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW - 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode. 0: Others. - 1 - 1 - read-write - - - SPI_SLV_EX_QPI_INT_RAW - The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others. - 2 - 1 - read-write - - - SPI_SLV_EN_QPI_INT_RAW - The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others. - 3 - 1 - read-write - - - SPI_SLV_CMD7_INT_RAW - The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others. - 4 - 1 - read-write - - - SPI_SLV_CMD8_INT_RAW - The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others. - 5 - 1 - read-write - - - SPI_SLV_CMD9_INT_RAW - The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others. - 6 - 1 - read-write - - - SPI_SLV_CMDA_INT_RAW - The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others. - 7 - 1 - read-write - - - SPI_SLV_RD_DMA_DONE_INT_RAW - The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others. - 8 - 1 - read-write - - - SPI_SLV_WR_DMA_DONE_INT_RAW - The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others. - 9 - 1 - read-write - - - SPI_SLV_RD_BUF_DONE_INT_RAW - The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others. - 10 - 1 - read-write - - - SPI_SLV_WR_BUF_DONE_INT_RAW - The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others. - 11 - 1 - read-write - - - SPI_TRANS_DONE_INT_RAW - The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others. - 12 - 1 - read-write - - - SPI_DMA_SEG_TRANS_DONE_INT_RAW - The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is not ended or not occurred. - 13 - 1 - read-write - - - SPI_SEG_MAGIC_ERR_INT_RAW - The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others. - 14 - 1 - read-write - - - SPI_SLV_BUF_ADDR_ERR_INT_RAW - The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others. - 15 - 1 - read-write - - - SPI_SLV_CMD_ERR_INT_RAW - The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others. - 16 - 1 - read-write - - - SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW - The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others. - 17 - 1 - read-write - - - SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW - The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others. - 18 - 1 - read-write - - - SPI_APP2_INT_RAW - The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software. - 19 - 1 - read-write - - - SPI_APP1_INT_RAW - The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software. - 20 - 1 - read-write - - - - - SPI_DMA_INT_ST - SPI interrupt status register - 0x40 - 0x20 - - - SPI_DMA_INFIFO_FULL_ERR_INT_ST - The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. - 0 - 1 - read-only - - - SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST - The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. - 1 - 1 - read-only - - - SPI_SLV_EX_QPI_INT_ST - The status bit for SPI slave Ex_QPI interrupt. - 2 - 1 - read-only - - - SPI_SLV_EN_QPI_INT_ST - The status bit for SPI slave En_QPI interrupt. - 3 - 1 - read-only - - - SPI_SLV_CMD7_INT_ST - The status bit for SPI slave CMD7 interrupt. - 4 - 1 - read-only - - - SPI_SLV_CMD8_INT_ST - The status bit for SPI slave CMD8 interrupt. - 5 - 1 - read-only - - - SPI_SLV_CMD9_INT_ST - The status bit for SPI slave CMD9 interrupt. - 6 - 1 - read-only - - - SPI_SLV_CMDA_INT_ST - The status bit for SPI slave CMDA interrupt. - 7 - 1 - read-only - - - SPI_SLV_RD_DMA_DONE_INT_ST - The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt. - 8 - 1 - read-only - - - SPI_SLV_WR_DMA_DONE_INT_ST - The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt. - 9 - 1 - read-only - - - SPI_SLV_RD_BUF_DONE_INT_ST - The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt. - 10 - 1 - read-only - - - SPI_SLV_WR_BUF_DONE_INT_ST - The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt. - 11 - 1 - read-only - - - SPI_TRANS_DONE_INT_ST - The status bit for SPI_TRANS_DONE_INT interrupt. - 12 - 1 - read-only - - - SPI_DMA_SEG_TRANS_DONE_INT_ST - The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. - 13 - 1 - read-only - - - SPI_SEG_MAGIC_ERR_INT_ST - The status bit for SPI_SEG_MAGIC_ERR_INT interrupt. - 14 - 1 - read-only - - - SPI_SLV_BUF_ADDR_ERR_INT_ST - The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. - 15 - 1 - read-only - - - SPI_SLV_CMD_ERR_INT_ST - The status bit for SPI_SLV_CMD_ERR_INT interrupt. - 16 - 1 - read-only - - - SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST - The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. - 17 - 1 - read-only - - - SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST - The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. - 18 - 1 - read-only - - - SPI_APP2_INT_ST - The status bit for SPI_APP2_INT interrupt. - 19 - 1 - read-only - - - SPI_APP1_INT_ST - The status bit for SPI_APP1_INT interrupt. - 20 - 1 - read-only - - - - - SPI_DMA_INT_SET - SPI interrupt software set register - 0x44 - 0x20 - - - SPI_DMA_INFIFO_FULL_ERR_INT_SET - The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. - 0 - 1 - write-only - - - SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET - The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. - 1 - 1 - write-only - - - SPI_SLV_EX_QPI_INT_SET - The software set bit for SPI slave Ex_QPI interrupt. - 2 - 1 - write-only - - - SPI_SLV_EN_QPI_INT_SET - The software set bit for SPI slave En_QPI interrupt. - 3 - 1 - write-only - - - SPI_SLV_CMD7_INT_SET - The software set bit for SPI slave CMD7 interrupt. - 4 - 1 - write-only - - - SPI_SLV_CMD8_INT_SET - The software set bit for SPI slave CMD8 interrupt. - 5 - 1 - write-only - - - SPI_SLV_CMD9_INT_SET - The software set bit for SPI slave CMD9 interrupt. - 6 - 1 - write-only - - - SPI_SLV_CMDA_INT_SET - The software set bit for SPI slave CMDA interrupt. - 7 - 1 - write-only - - - SPI_SLV_RD_DMA_DONE_INT_SET - The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt. - 8 - 1 - write-only - - - SPI_SLV_WR_DMA_DONE_INT_SET - The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt. - 9 - 1 - write-only - - - SPI_SLV_RD_BUF_DONE_INT_SET - The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt. - 10 - 1 - write-only - - - SPI_SLV_WR_BUF_DONE_INT_SET - The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt. - 11 - 1 - write-only - - - SPI_TRANS_DONE_INT_SET - The software set bit for SPI_TRANS_DONE_INT interrupt. - 12 - 1 - write-only - - - SPI_DMA_SEG_TRANS_DONE_INT_SET - The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. - 13 - 1 - write-only - - - SPI_SEG_MAGIC_ERR_INT_SET - The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt. - 14 - 1 - write-only - - - SPI_SLV_BUF_ADDR_ERR_INT_SET - The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. - 15 - 1 - write-only - - - SPI_SLV_CMD_ERR_INT_SET - The software set bit for SPI_SLV_CMD_ERR_INT interrupt. - 16 - 1 - write-only - - - SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET - The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. - 17 - 1 - write-only - - - SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET - The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. - 18 - 1 - write-only - - - SPI_APP2_INT_SET - The software set bit for SPI_APP2_INT interrupt. - 19 - 1 - write-only - - - SPI_APP1_INT_SET - The software set bit for SPI_APP1_INT interrupt. - 20 - 1 - write-only - - - - - SPI_W0 - SPI CPU-controlled buffer0 - 0x98 - 0x20 - - - SPI_BUF0 - data buffer - 0 - 32 - read-write - - - - - SPI_W1 - SPI CPU-controlled buffer1 - 0x9C - 0x20 - - - SPI_BUF1 - data buffer - 0 - 32 - read-write - - - - - SPI_W2 - SPI CPU-controlled buffer2 - 0xA0 - 0x20 - - - SPI_BUF2 - data buffer - 0 - 32 - read-write - - - - - SPI_W3 - SPI CPU-controlled buffer3 - 0xA4 - 0x20 - - - SPI_BUF3 - data buffer - 0 - 32 - read-write - - - - - SPI_W4 - SPI CPU-controlled buffer4 - 0xA8 - 0x20 - - - SPI_BUF4 - data buffer - 0 - 32 - read-write - - - - - SPI_W5 - SPI CPU-controlled buffer5 - 0xAC - 0x20 - - - SPI_BUF5 - data buffer - 0 - 32 - read-write - - - - - SPI_W6 - SPI CPU-controlled buffer6 - 0xB0 - 0x20 - - - SPI_BUF6 - data buffer - 0 - 32 - read-write - - - - - SPI_W7 - SPI CPU-controlled buffer7 - 0xB4 - 0x20 - - - SPI_BUF7 - data buffer - 0 - 32 - read-write - - - - - SPI_W8 - SPI CPU-controlled buffer8 - 0xB8 - 0x20 - - - SPI_BUF8 - data buffer - 0 - 32 - read-write - - - - - SPI_W9 - SPI CPU-controlled buffer9 - 0xBC - 0x20 - - - SPI_BUF9 - data buffer - 0 - 32 - read-write - - - - - SPI_W10 - SPI CPU-controlled buffer10 - 0xC0 - 0x20 - - - SPI_BUF10 - data buffer - 0 - 32 - read-write - - - - - SPI_W11 - SPI CPU-controlled buffer11 - 0xC4 - 0x20 - - - SPI_BUF11 - data buffer - 0 - 32 - read-write - - - - - SPI_W12 - SPI CPU-controlled buffer12 - 0xC8 - 0x20 - - - SPI_BUF12 - data buffer - 0 - 32 - read-write - - - - - SPI_W13 - SPI CPU-controlled buffer13 - 0xCC - 0x20 - - - SPI_BUF13 - data buffer - 0 - 32 - read-write - - - - - SPI_W14 - SPI CPU-controlled buffer14 - 0xD0 - 0x20 - - - SPI_BUF14 - data buffer - 0 - 32 - read-write - - - - - SPI_W15 - SPI CPU-controlled buffer15 - 0xD4 - 0x20 - - - SPI_BUF15 - data buffer - 0 - 32 - read-write - - - - - SPI_SLAVE - SPI slave control register - 0xE0 - 0x20 - 0x02800000 - - - SPI_CLK_MODE - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state. - 0 - 2 - read-write - - - SPI_CLK_MODE_13 - {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6]. - 2 - 1 - read-write - - - SPI_RSCK_DATA_OUT - It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge - 3 - 1 - read-write - - - SPI_SLV_RDDMA_BITLEN_EN - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others - 8 - 1 - read-write - - - SPI_SLV_WRDMA_BITLEN_EN - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others - 9 - 1 - read-write - - - SPI_SLV_RDBUF_BITLEN_EN - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others - 10 - 1 - read-write - - - SPI_SLV_WRBUF_BITLEN_EN - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others - 11 - 1 - read-write - - - SPI_SLV_LAST_BYTE_STRB - Represents the effective bit of the last received data byte in SPI slave FD and HD mode. - 12 - 8 - read-only - - - SPI_DMA_SEG_MAGIC_VALUE - The magic value of BM table in master DMA seg-trans. - 22 - 4 - read-write - - - MODE - Set SPI work mode. 1: slave mode 0: master mode. - 26 - 1 - read-write - - - SPI_SOFT_RESET - Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state. - 27 - 1 - write-only - - - SPI_USR_CONF - 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode. - 28 - 1 - read-write - - - SPI_MST_FD_WAIT_DMA_TX_DATA - In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI transfer. - 29 - 1 - read-write - - - - - SPI_SLAVE1 - SPI slave control register 1 - 0xE4 - 0x20 - - - SPI_SLV_DATA_BITLEN - The transferred data bit length in SPI slave FD and HD mode. - 0 - 18 - read-write - - - SPI_SLV_LAST_COMMAND - In the slave mode it is the value of command. - 18 - 8 - read-write - - - SPI_SLV_LAST_ADDR - In the slave mode it is the value of address. - 26 - 6 - read-write - - - - - SPI_CLK_GATE - SPI module clock and register clock control - 0xE8 - 0x20 - - - SPI_CLK_EN - Set this bit to enable clk gate - 0 - 1 - read-write - - - SPI_MST_CLK_ACTIVE - Set this bit to power on the SPI module clock. - 1 - 1 - read-write - - - SPI_MST_CLK_SEL - This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK. - 2 - 1 - read-write - - - - - SPI_DATE - Version control - 0xF0 - 0x20 - 0x02207202 - - - SPI_DATE - SPI register version. - 0 - 28 - read-write - - - - - - - SPI3 - SPI (Serial Peripheral Interface) Controller 3 - SPI3 - 0x500D1000 - - 0x0 - 0x98 - registers - - - SPI3 - 26 - - - - SPI_CMD - Command control register - 0x0 - 0x20 - - - SPI_UPDATE - Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode. - 23 - 1 - write-only - - - SPI_USR - User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf. - 24 - 1 - read-write - - - - - SPI_ADDR - Address value register - 0x4 - 0x20 - - - SPI_USR_ADDR_VALUE - Address to slave. Can be configured in CONF state. - 0 - 32 - read-write - - - - - SPI_CTRL - SPI control register - 0x8 - 0x20 - 0x003C0000 - - - SPI_DUMMY_OUT - 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state. - 3 - 1 - read-write - - - SPI_FADDR_DUAL - Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state. - 5 - 1 - read-write - - - SPI_FADDR_QUAD - Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state. - 6 - 1 - read-write - - - SPI_FCMD_DUAL - Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state. - 8 - 1 - read-write - - - SPI_FCMD_QUAD - Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state. - 9 - 1 - read-write - - - SPI_FREAD_DUAL - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state. - 14 - 1 - read-write - - - SPI_FREAD_QUAD - In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state. - 15 - 1 - read-write - - - SPI_Q_POL - The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state. - 18 - 1 - read-write - - - SPI_D_POL - The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state. - 19 - 1 - read-write - - - SPI_HOLD_POL - SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state. - 20 - 1 - read-write - - - SPI_WP_POL - Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state. - 21 - 1 - read-write - - - SPI_RD_BIT_ORDER - In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state. - 23 - 2 - read-write - - - SPI_WR_BIT_ORDER - In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state. - 25 - 2 - read-write - - - - - SPI_CLOCK - SPI clock control register - 0xC - 0x20 - 0x80003043 - - - SPI_CLKCNT_L - In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state. - 0 - 6 - read-write - - - SPI_CLKCNT_H - In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state. - 6 - 6 - read-write - - - SPI_CLKCNT_N - In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state. - 12 - 6 - read-write - - - SPI_CLKDIV_PRE - In the master mode it is pre-divider of spi_clk. Can be configured in CONF state. - 18 - 4 - read-write - - - SPI_CLK_EQU_SYSCLK - In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state. - 31 - 1 - read-write - - - - - SPI_USER - SPI USER control register - 0x10 - 0x20 - 0x800000C0 - - - SPI_DOUTDIN - Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state. - 0 - 1 - read-write - - - SPI_QPI_MODE - Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state. - 3 - 1 - read-write - - - SPI_TSCK_I_EDGE - In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i. - 5 - 1 - read-write - - - SPI_CS_HOLD - spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state. - 6 - 1 - read-write - - - SPI_CS_SETUP - spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state. - 7 - 1 - read-write - - - SPI_RSCK_I_EDGE - In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i. - 8 - 1 - read-write - - - SPI_CK_OUT_EDGE - the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state. - 9 - 1 - read-write - - - SPI_FWRITE_DUAL - In the write operations read-data phase apply 2 signals. Can be configured in CONF state. - 12 - 1 - read-write - - - SPI_FWRITE_QUAD - In the write operations read-data phase apply 4 signals. Can be configured in CONF state. - 13 - 1 - read-write - - - SPI_SIO - Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state. - 17 - 1 - read-write - - - SPI_USR_MISO_HIGHPART - read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state. - 24 - 1 - read-write - - - SPI_USR_MOSI_HIGHPART - write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state. - 25 - 1 - read-write - - - SPI_USR_DUMMY_IDLE - spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state. - 26 - 1 - read-write - - - SPI_USR_MOSI - This bit enable the write-data phase of an operation. Can be configured in CONF state. - 27 - 1 - read-write - - - SPI_USR_MISO - This bit enable the read-data phase of an operation. Can be configured in CONF state. - 28 - 1 - read-write - - - SPI_USR_DUMMY - This bit enable the dummy phase of an operation. Can be configured in CONF state. - 29 - 1 - read-write - - - SPI_USR_ADDR - This bit enable the address phase of an operation. Can be configured in CONF state. - 30 - 1 - read-write - - - SPI_USR_COMMAND - This bit enable the command phase of an operation. Can be configured in CONF state. - 31 - 1 - read-write - - - - - SPI_USER1 - SPI USER control register 1 - 0x14 - 0x20 - 0xB8410007 - - - SPI_USR_DUMMY_CYCLELEN - The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state. - 0 - 8 - read-write - - - SPI_MST_WFULL_ERR_END_EN - 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. - 16 - 1 - read-write - - - SPI_CS_SETUP_TIME - (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state. - 17 - 5 - read-write - - - SPI_CS_HOLD_TIME - delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state. - 22 - 5 - read-write - - - SPI_USR_ADDR_BITLEN - The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state. - 27 - 5 - read-write - - - - - SPI_USER2 - SPI USER control register 2 - 0x18 - 0x20 - 0x78000000 - - - SPI_USR_COMMAND_VALUE - The value of command. Can be configured in CONF state. - 0 - 16 - read-write - - - SPI_MST_REMPTY_ERR_END_EN - 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. - 27 - 1 - read-write - - - SPI_USR_COMMAND_BITLEN - The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state. - 28 - 4 - read-write - - - - - SPI_MS_DLEN - SPI data bit length control register - 0x1C - 0x20 - - - SPI_MS_DATA_BITLEN - The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state. - 0 - 18 - read-write - - - - - SPI_MISC - SPI misc register - 0x20 - 0x20 - 0x00000006 - - - SPI_CS0_DIS - SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state. - 0 - 1 - read-write - - - SPI_CS1_DIS - SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state. - 1 - 1 - read-write - - - SPI_CS2_DIS - SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state. - 2 - 1 - read-write - - - SPI_CK_DIS - 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state. - 6 - 1 - read-write - - - SPI_MASTER_CS_POL - In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state. - 7 - 3 - read-write - - - SPI_SLAVE_CS_POL - spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state. - 23 - 1 - read-write - - - SPI_CK_IDLE_EDGE - 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state. - 29 - 1 - read-write - - - SPI_CS_KEEP_ACTIVE - spi cs line keep low when the bit is set. Can be configured in CONF state. - 30 - 1 - read-write - - - SPI_QUAD_DIN_PIN_SWAP - 1: spi quad input swap enable 0: spi quad input swap disable. Can be configured in CONF state. - 31 - 1 - read-write - - - - - SPI_DIN_MODE - SPI input delay mode configuration - 0x24 - 0x20 - - - SPI_DIN0_MODE - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. - 0 - 2 - read-write - - - SPI_DIN1_MODE - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. - 2 - 2 - read-write - - - SPI_DIN2_MODE - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. - 4 - 2 - read-write - - - SPI_DIN3_MODE - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. - 6 - 2 - read-write - - - SPI_TIMING_HCLK_ACTIVE - 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state. - 16 - 1 - read-write - - - - - SPI_DIN_NUM - SPI input delay number configuration - 0x28 - 0x20 - - - SPI_DIN0_NUM - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. - 0 - 2 - read-write - - - SPI_DIN1_NUM - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. - 2 - 2 - read-write - - - SPI_DIN2_NUM - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. - 4 - 2 - read-write - - - SPI_DIN3_NUM - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. - 6 - 2 - read-write - - - - - SPI_DOUT_MODE - SPI output delay mode configuration - 0x2C - 0x20 - - - SPI_DOUT0_MODE - The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. - 0 - 1 - read-write - - - SPI_DOUT1_MODE - The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. - 1 - 1 - read-write - - - SPI_DOUT2_MODE - The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. - 2 - 1 - read-write - - - SPI_DOUT3_MODE - The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. - 3 - 1 - read-write - - - - - SPI_DMA_CONF - SPI DMA control register - 0x30 - 0x20 - 0x00000003 - - - SPI_DMA_OUTFIFO_EMPTY - Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: DMA TX FIFO is ready for sending data. - 0 - 1 - read-only - - - SPI_DMA_INFIFO_FULL - Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. 0: DMA RX FIFO is ready for receiving data. - 1 - 1 - read-only - - - SPI_DMA_SLV_SEG_TRANS_EN - Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable. - 18 - 1 - read-write - - - SPI_SLV_RX_SEG_TRANS_CLR_EN - 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done. - 19 - 1 - read-write - - - SPI_SLV_TX_SEG_TRANS_CLR_EN - 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done. - 20 - 1 - read-write - - - SPI_RX_EOF_EN - 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans. - 21 - 1 - read-write - - - SPI_DMA_RX_ENA - Set this bit to enable SPI DMA controlled receive data mode. - 27 - 1 - read-write - - - SPI_DMA_TX_ENA - Set this bit to enable SPI DMA controlled send data mode. - 28 - 1 - read-write - - - SPI_RX_AFIFO_RST - Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer. - 29 - 1 - write-only - - - SPI_BUF_AFIFO_RST - Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer. - 30 - 1 - write-only - - - SPI_DMA_AFIFO_RST - Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer. - 31 - 1 - write-only - - - - - SPI_DMA_INT_ENA - SPI interrupt enable register - 0x34 - 0x20 - - - SPI_DMA_INFIFO_FULL_ERR_INT_ENA - The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. - 0 - 1 - read-write - - - SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA - The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. - 1 - 1 - read-write - - - SPI_SLV_EX_QPI_INT_ENA - The enable bit for SPI slave Ex_QPI interrupt. - 2 - 1 - read-write - - - SPI_SLV_EN_QPI_INT_ENA - The enable bit for SPI slave En_QPI interrupt. - 3 - 1 - read-write - - - SPI_SLV_CMD7_INT_ENA - The enable bit for SPI slave CMD7 interrupt. - 4 - 1 - read-write - - - SPI_SLV_CMD8_INT_ENA - The enable bit for SPI slave CMD8 interrupt. - 5 - 1 - read-write - - - SPI_SLV_CMD9_INT_ENA - The enable bit for SPI slave CMD9 interrupt. - 6 - 1 - read-write - - - SPI_SLV_CMDA_INT_ENA - The enable bit for SPI slave CMDA interrupt. - 7 - 1 - read-write - - - SPI_SLV_RD_DMA_DONE_INT_ENA - The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt. - 8 - 1 - read-write - - - SPI_SLV_WR_DMA_DONE_INT_ENA - The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt. - 9 - 1 - read-write - - - SPI_SLV_RD_BUF_DONE_INT_ENA - The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt. - 10 - 1 - read-write - - - SPI_SLV_WR_BUF_DONE_INT_ENA - The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt. - 11 - 1 - read-write - - - SPI_TRANS_DONE_INT_ENA - The enable bit for SPI_TRANS_DONE_INT interrupt. - 12 - 1 - read-write - - - SPI_DMA_SEG_TRANS_DONE_INT_ENA - The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. - 13 - 1 - read-write - - - SPI_SLV_BUF_ADDR_ERR_INT_ENA - The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. - 15 - 1 - read-write - - - SPI_SLV_CMD_ERR_INT_ENA - The enable bit for SPI_SLV_CMD_ERR_INT interrupt. - 16 - 1 - read-write - - - SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA - The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. - 17 - 1 - read-write - - - SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA - The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. - 18 - 1 - read-write - - - SPI_APP2_INT_ENA - The enable bit for SPI_APP2_INT interrupt. - 19 - 1 - read-write - - - SPI_APP1_INT_ENA - The enable bit for SPI_APP1_INT interrupt. - 20 - 1 - read-write - - - - - SPI_DMA_INT_CLR - SPI interrupt clear register - 0x38 - 0x20 - - - SPI_DMA_INFIFO_FULL_ERR_INT_CLR - The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. - 0 - 1 - write-only - - - SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR - The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. - 1 - 1 - write-only - - - SPI_SLV_EX_QPI_INT_CLR - The clear bit for SPI slave Ex_QPI interrupt. - 2 - 1 - write-only - - - SPI_SLV_EN_QPI_INT_CLR - The clear bit for SPI slave En_QPI interrupt. - 3 - 1 - write-only - - - SPI_SLV_CMD7_INT_CLR - The clear bit for SPI slave CMD7 interrupt. - 4 - 1 - write-only - - - SPI_SLV_CMD8_INT_CLR - The clear bit for SPI slave CMD8 interrupt. - 5 - 1 - write-only - - - SPI_SLV_CMD9_INT_CLR - The clear bit for SPI slave CMD9 interrupt. - 6 - 1 - write-only - - - SPI_SLV_CMDA_INT_CLR - The clear bit for SPI slave CMDA interrupt. - 7 - 1 - write-only - - - SPI_SLV_RD_DMA_DONE_INT_CLR - The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt. - 8 - 1 - write-only - - - SPI_SLV_WR_DMA_DONE_INT_CLR - The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt. - 9 - 1 - write-only - - - SPI_SLV_RD_BUF_DONE_INT_CLR - The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt. - 10 - 1 - write-only - - - SPI_SLV_WR_BUF_DONE_INT_CLR - The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt. - 11 - 1 - write-only - - - SPI_TRANS_DONE_INT_CLR - The clear bit for SPI_TRANS_DONE_INT interrupt. - 12 - 1 - write-only - - - SPI_DMA_SEG_TRANS_DONE_INT_CLR - The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. - 13 - 1 - write-only - - - SPI_SLV_BUF_ADDR_ERR_INT_CLR - The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. - 15 - 1 - write-only - - - SPI_SLV_CMD_ERR_INT_CLR - The clear bit for SPI_SLV_CMD_ERR_INT interrupt. - 16 - 1 - write-only - - - SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR - The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. - 17 - 1 - write-only - - - SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR - The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. - 18 - 1 - write-only - - - SPI_APP2_INT_CLR - The clear bit for SPI_APP2_INT interrupt. - 19 - 1 - write-only - - - SPI_APP1_INT_CLR - The clear bit for SPI_APP1_INT interrupt. - 20 - 1 - write-only - - - - - SPI_DMA_INT_RAW - SPI interrupt raw register - 0x3C - 0x20 - - - SPI_DMA_INFIFO_FULL_ERR_INT_RAW - 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others. - 0 - 1 - read-write - - - SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW - 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode. 0: Others. - 1 - 1 - read-write - - - SPI_SLV_EX_QPI_INT_RAW - The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others. - 2 - 1 - read-write - - - SPI_SLV_EN_QPI_INT_RAW - The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others. - 3 - 1 - read-write - - - SPI_SLV_CMD7_INT_RAW - The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others. - 4 - 1 - read-write - - - SPI_SLV_CMD8_INT_RAW - The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others. - 5 - 1 - read-write - - - SPI_SLV_CMD9_INT_RAW - The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others. - 6 - 1 - read-write - - - SPI_SLV_CMDA_INT_RAW - The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others. - 7 - 1 - read-write - - - SPI_SLV_RD_DMA_DONE_INT_RAW - The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others. - 8 - 1 - read-write - - - SPI_SLV_WR_DMA_DONE_INT_RAW - The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others. - 9 - 1 - read-write - - - SPI_SLV_RD_BUF_DONE_INT_RAW - The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others. - 10 - 1 - read-write - - - SPI_SLV_WR_BUF_DONE_INT_RAW - The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others. - 11 - 1 - read-write - - - SPI_TRANS_DONE_INT_RAW - The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others. - 12 - 1 - read-write - - - SPI_DMA_SEG_TRANS_DONE_INT_RAW - The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is not ended or not occurred. - 13 - 1 - read-write - - - SPI_SLV_BUF_ADDR_ERR_INT_RAW - The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others. - 15 - 1 - read-write - - - SPI_SLV_CMD_ERR_INT_RAW - The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others. - 16 - 1 - read-write - - - SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW - The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others. - 17 - 1 - read-write - - - SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW - The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others. - 18 - 1 - read-write - - - SPI_APP2_INT_RAW - The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software. - 19 - 1 - read-write - - - SPI_APP1_INT_RAW - The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software. - 20 - 1 - read-write - - - - - SPI_DMA_INT_ST - SPI interrupt status register - 0x40 - 0x20 - - - SPI_DMA_INFIFO_FULL_ERR_INT_ST - The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. - 0 - 1 - read-only - - - SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST - The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. - 1 - 1 - read-only - - - SPI_SLV_EX_QPI_INT_ST - The status bit for SPI slave Ex_QPI interrupt. - 2 - 1 - read-only - - - SPI_SLV_EN_QPI_INT_ST - The status bit for SPI slave En_QPI interrupt. - 3 - 1 - read-only - - - SPI_SLV_CMD7_INT_ST - The status bit for SPI slave CMD7 interrupt. - 4 - 1 - read-only - - - SPI_SLV_CMD8_INT_ST - The status bit for SPI slave CMD8 interrupt. - 5 - 1 - read-only - - - SPI_SLV_CMD9_INT_ST - The status bit for SPI slave CMD9 interrupt. - 6 - 1 - read-only - - - SPI_SLV_CMDA_INT_ST - The status bit for SPI slave CMDA interrupt. - 7 - 1 - read-only - - - SPI_SLV_RD_DMA_DONE_INT_ST - The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt. - 8 - 1 - read-only - - - SPI_SLV_WR_DMA_DONE_INT_ST - The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt. - 9 - 1 - read-only - - - SPI_SLV_RD_BUF_DONE_INT_ST - The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt. - 10 - 1 - read-only - - - SPI_SLV_WR_BUF_DONE_INT_ST - The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt. - 11 - 1 - read-only - - - SPI_TRANS_DONE_INT_ST - The status bit for SPI_TRANS_DONE_INT interrupt. - 12 - 1 - read-only - - - SPI_DMA_SEG_TRANS_DONE_INT_ST - The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. - 13 - 1 - read-only - - - SPI_SLV_BUF_ADDR_ERR_INT_ST - The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. - 15 - 1 - read-only - - - SPI_SLV_CMD_ERR_INT_ST - The status bit for SPI_SLV_CMD_ERR_INT interrupt. - 16 - 1 - read-only - - - SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST - The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. - 17 - 1 - read-only - - - SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST - The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. - 18 - 1 - read-only - - - SPI_APP2_INT_ST - The status bit for SPI_APP2_INT interrupt. - 19 - 1 - read-only - - - SPI_APP1_INT_ST - The status bit for SPI_APP1_INT interrupt. - 20 - 1 - read-only - - - - - SPI_DMA_INT_SET - SPI interrupt software set register - 0x44 - 0x20 - - - SPI_DMA_INFIFO_FULL_ERR_INT_SET - The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. - 0 - 1 - write-only - - - SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET - The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. - 1 - 1 - write-only - - - SPI_SLV_EX_QPI_INT_SET - The software set bit for SPI slave Ex_QPI interrupt. - 2 - 1 - write-only - - - SPI_SLV_EN_QPI_INT_SET - The software set bit for SPI slave En_QPI interrupt. - 3 - 1 - write-only - - - SPI_SLV_CMD7_INT_SET - The software set bit for SPI slave CMD7 interrupt. - 4 - 1 - write-only - - - SPI_SLV_CMD8_INT_SET - The software set bit for SPI slave CMD8 interrupt. - 5 - 1 - write-only - - - SPI_SLV_CMD9_INT_SET - The software set bit for SPI slave CMD9 interrupt. - 6 - 1 - write-only - - - SPI_SLV_CMDA_INT_SET - The software set bit for SPI slave CMDA interrupt. - 7 - 1 - write-only - - - SPI_SLV_RD_DMA_DONE_INT_SET - The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt. - 8 - 1 - write-only - - - SPI_SLV_WR_DMA_DONE_INT_SET - The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt. - 9 - 1 - write-only - - - SPI_SLV_RD_BUF_DONE_INT_SET - The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt. - 10 - 1 - write-only - - - SPI_SLV_WR_BUF_DONE_INT_SET - The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt. - 11 - 1 - write-only - - - SPI_TRANS_DONE_INT_SET - The software set bit for SPI_TRANS_DONE_INT interrupt. - 12 - 1 - write-only - - - SPI_DMA_SEG_TRANS_DONE_INT_SET - The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. - 13 - 1 - write-only - - - SPI_SLV_BUF_ADDR_ERR_INT_SET - The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. - 15 - 1 - write-only - - - SPI_SLV_CMD_ERR_INT_SET - The software set bit for SPI_SLV_CMD_ERR_INT interrupt. - 16 - 1 - write-only - - - SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET - The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. - 17 - 1 - write-only - - - SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET - The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. - 18 - 1 - write-only - - - SPI_APP2_INT_SET - The software set bit for SPI_APP2_INT interrupt. - 19 - 1 - write-only - - - SPI_APP1_INT_SET - The software set bit for SPI_APP1_INT interrupt. - 20 - 1 - write-only - - - - - SPI_W0 - SPI CPU-controlled buffer0 - 0x98 - 0x20 - - - SPI_BUF0 - data buffer - 0 - 32 - read-write - - - - - SPI_W1 - SPI CPU-controlled buffer1 - 0x9C - 0x20 - - - SPI_BUF1 - data buffer - 0 - 32 - read-write - - - - - SPI_W2 - SPI CPU-controlled buffer2 - 0xA0 - 0x20 - - - SPI_BUF2 - data buffer - 0 - 32 - read-write - - - - - SPI_W3 - SPI CPU-controlled buffer3 - 0xA4 - 0x20 - - - SPI_BUF3 - data buffer - 0 - 32 - read-write - - - - - SPI_W4 - SPI CPU-controlled buffer4 - 0xA8 - 0x20 - - - SPI_BUF4 - data buffer - 0 - 32 - read-write - - - - - SPI_W5 - SPI CPU-controlled buffer5 - 0xAC - 0x20 - - - SPI_BUF5 - data buffer - 0 - 32 - read-write - - - - - SPI_W6 - SPI CPU-controlled buffer6 - 0xB0 - 0x20 - - - SPI_BUF6 - data buffer - 0 - 32 - read-write - - - - - SPI_W7 - SPI CPU-controlled buffer7 - 0xB4 - 0x20 - - - SPI_BUF7 - data buffer - 0 - 32 - read-write - - - - - SPI_W8 - SPI CPU-controlled buffer8 - 0xB8 - 0x20 - - - SPI_BUF8 - data buffer - 0 - 32 - read-write - - - - - SPI_W9 - SPI CPU-controlled buffer9 - 0xBC - 0x20 - - - SPI_BUF9 - data buffer - 0 - 32 - read-write - - - - - SPI_W10 - SPI CPU-controlled buffer10 - 0xC0 - 0x20 - - - SPI_BUF10 - data buffer - 0 - 32 - read-write - - - - - SPI_W11 - SPI CPU-controlled buffer11 - 0xC4 - 0x20 - - - SPI_BUF11 - data buffer - 0 - 32 - read-write - - - - - SPI_W12 - SPI CPU-controlled buffer12 - 0xC8 - 0x20 - - - SPI_BUF12 - data buffer - 0 - 32 - read-write - - - - - SPI_W13 - SPI CPU-controlled buffer13 - 0xCC - 0x20 - - - SPI_BUF13 - data buffer - 0 - 32 - read-write - - - - - SPI_W14 - SPI CPU-controlled buffer14 - 0xD0 - 0x20 - - - SPI_BUF14 - data buffer - 0 - 32 - read-write - - - - - SPI_W15 - SPI CPU-controlled buffer15 - 0xD4 - 0x20 - - - SPI_BUF15 - data buffer - 0 - 32 - read-write - - - - - SPI_SLAVE - SPI slave control register - 0xE0 - 0x20 - - - SPI_CLK_MODE - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state. - 0 - 2 - read-write - - - SPI_CLK_MODE_13 - {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6]. - 2 - 1 - read-write - - - SPI_RSCK_DATA_OUT - It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge - 3 - 1 - read-write - - - SPI_SLV_RDDMA_BITLEN_EN - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others - 8 - 1 - read-write - - - SPI_SLV_WRDMA_BITLEN_EN - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others - 9 - 1 - read-write - - - SPI_SLV_RDBUF_BITLEN_EN - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others - 10 - 1 - read-write - - - SPI_SLV_WRBUF_BITLEN_EN - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others - 11 - 1 - read-write - - - SPI_SLV_LAST_BYTE_STRB - Represents the effective bit of the last received data byte in SPI slave FD and HD mode. - 12 - 8 - read-only - - - MODE - Set SPI work mode. 1: slave mode 0: master mode. - 26 - 1 - read-write - - - SPI_SOFT_RESET - Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state. - 27 - 1 - write-only - - - SPI_MST_FD_WAIT_DMA_TX_DATA - In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI transfer. - 29 - 1 - read-write - - - - - SPI_SLAVE1 - SPI slave control register 1 - 0xE4 - 0x20 - - - SPI_SLV_DATA_BITLEN - The transferred data bit length in SPI slave FD and HD mode. - 0 - 18 - read-write - - - SPI_SLV_LAST_COMMAND - In the slave mode it is the value of command. - 18 - 8 - read-write - - - SPI_SLV_LAST_ADDR - In the slave mode it is the value of address. - 26 - 6 - read-write - - - - - SPI_CLK_GATE - SPI module clock and register clock control - 0xE8 - 0x20 - - - SPI_CLK_EN - Set this bit to enable clk gate - 0 - 1 - read-write - - - SPI_MST_CLK_ACTIVE - Set this bit to power on the SPI module clock. - 1 - 1 - read-write - - - SPI_MST_CLK_SEL - This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK. - 2 - 1 - read-write - - - - - SPI_DATE - Version control - 0xF0 - 0x20 - 0x02207202 - - - SPI_DATE - SPI register version. - 0 - 28 - read-write - - - - - - - SYSTIMER - System Timer - SYSTIMER - 0x500E2000 - - 0x0 - 0x90 - registers - - - SYSTIMER_TARGET0 - 53 - - - SYSTIMER_TARGET1 - 54 - - - SYSTIMER_TARGET2 - 55 - - - - CONF - Configure system timer clock - 0x0 - 0x20 - 0x46000000 - - - SYSTIMER_CLK_FO - systimer clock force on - 0 - 1 - read-write - - - ETM_EN - enable systimer's etm task and event - 1 - 1 - read-write - - - TARGET2_WORK_EN - target2 work enable - 22 - 1 - read-write - - - TARGET1_WORK_EN - target1 work enable - 23 - 1 - read-write - - - TARGET0_WORK_EN - target0 work enable - 24 - 1 - read-write - - - TIMER_UNIT1_CORE1_STALL_EN - If timer unit1 is stalled when core1 stalled - 25 - 1 - read-write - - - TIMER_UNIT1_CORE0_STALL_EN - If timer unit1 is stalled when core0 stalled - 26 - 1 - read-write - - - TIMER_UNIT0_CORE1_STALL_EN - If timer unit0 is stalled when core1 stalled - 27 - 1 - read-write - - - TIMER_UNIT0_CORE0_STALL_EN - If timer unit0 is stalled when core0 stalled - 28 - 1 - read-write - - - TIMER_UNIT1_WORK_EN - timer unit1 work enable - 29 - 1 - read-write - - - TIMER_UNIT0_WORK_EN - timer unit0 work enable - 30 - 1 - read-write - - - CLK_EN - register file clk gating - 31 - 1 - read-write - - - - - UNIT0_OP - system timer unit0 value update register - 0x4 - 0x20 - - - TIMER_UNIT0_VALUE_VALID - timer value is sync and valid - 29 - 1 - read-only - - - TIMER_UNIT0_UPDATE - update timer_unit0 - 30 - 1 - write-only - - - - - UNIT1_OP - system timer unit1 value update register - 0x8 - 0x20 - - - TIMER_UNIT1_VALUE_VALID - timer value is sync and valid - 29 - 1 - read-only - - - TIMER_UNIT1_UPDATE - update timer unit1 - 30 - 1 - write-only - - - - - UNIT0_LOAD_HI - system timer unit0 value high load register - 0xC - 0x20 - - - TIMER_UNIT0_LOAD_HI - timer unit0 load high 20 bits - 0 - 20 - read-write - - - - - UNIT0_LOAD_LO - system timer unit0 value low load register - 0x10 - 0x20 - - - TIMER_UNIT0_LOAD_LO - timer unit0 load low 32 bits - 0 - 32 - read-write - - - - - UNIT1_LOAD_HI - system timer unit1 value high load register - 0x14 - 0x20 - - - TIMER_UNIT1_LOAD_HI - timer unit1 load high 20 bits - 0 - 20 - read-write - - - - - UNIT1_LOAD_LO - system timer unit1 value low load register - 0x18 - 0x20 - - - TIMER_UNIT1_LOAD_LO - timer unit1 load low 32 bits - 0 - 32 - read-write - - - - - TARGET0_HI - system timer comp0 value high register - 0x1C - 0x20 - - - TIMER_TARGET0_HI - timer taget0 high 20 bits - 0 - 20 - read-write - - - - - TARGET0_LO - system timer comp0 value low register - 0x20 - 0x20 - - - TIMER_TARGET0_LO - timer taget0 low 32 bits - 0 - 32 - read-write - - - - - TARGET1_HI - system timer comp1 value high register - 0x24 - 0x20 - - - TIMER_TARGET1_HI - timer taget1 high 20 bits - 0 - 20 - read-write - - - - - TARGET1_LO - system timer comp1 value low register - 0x28 - 0x20 - - - TIMER_TARGET1_LO - timer taget1 low 32 bits - 0 - 32 - read-write - - - - - TARGET2_HI - system timer comp2 value high register - 0x2C - 0x20 - - - TIMER_TARGET2_HI - timer taget2 high 20 bits - 0 - 20 - read-write - - - - - TARGET2_LO - system timer comp2 value low register - 0x30 - 0x20 - - - TIMER_TARGET2_LO - timer taget2 low 32 bits - 0 - 32 - read-write - - - - - TARGET0_CONF - system timer comp0 target mode register - 0x34 - 0x20 - - - TARGET0_PERIOD - target0 period - 0 - 26 - read-write - - - TARGET0_PERIOD_MODE - Set target0 to period mode - 30 - 1 - read-write - - - TARGET0_TIMER_UNIT_SEL - select which unit to compare - 31 - 1 - read-write - - - - - TARGET1_CONF - system timer comp1 target mode register - 0x38 - 0x20 - - - TARGET1_PERIOD - target1 period - 0 - 26 - read-write - - - TARGET1_PERIOD_MODE - Set target1 to period mode - 30 - 1 - read-write - - - TARGET1_TIMER_UNIT_SEL - select which unit to compare - 31 - 1 - read-write - - - - - TARGET2_CONF - system timer comp2 target mode register - 0x3C - 0x20 - - - TARGET2_PERIOD - target2 period - 0 - 26 - read-write - - - TARGET2_PERIOD_MODE - Set target2 to period mode - 30 - 1 - read-write - - - TARGET2_TIMER_UNIT_SEL - select which unit to compare - 31 - 1 - read-write - - - - - UNIT0_VALUE_HI - system timer unit0 value high register - 0x40 - 0x20 - - - TIMER_UNIT0_VALUE_HI - timer read value high 20bits - 0 - 20 - read-only - - - - - UNIT0_VALUE_LO - system timer unit0 value low register - 0x44 - 0x20 - - - TIMER_UNIT0_VALUE_LO - timer read value low 32bits - 0 - 32 - read-only - - - - - UNIT1_VALUE_HI - system timer unit1 value high register - 0x48 - 0x20 - - - TIMER_UNIT1_VALUE_HI - timer read value high 20bits - 0 - 20 - read-only - - - - - UNIT1_VALUE_LO - system timer unit1 value low register - 0x4C - 0x20 - - - TIMER_UNIT1_VALUE_LO - timer read value low 32bits - 0 - 32 - read-only - - - - - COMP0_LOAD - system timer comp0 conf sync register - 0x50 - 0x20 - - - TIMER_COMP0_LOAD - timer comp0 sync enable signal - 0 - 1 - write-only - - - - - COMP1_LOAD - system timer comp1 conf sync register - 0x54 - 0x20 - - - TIMER_COMP1_LOAD - timer comp1 sync enable signal - 0 - 1 - write-only - - - - - COMP2_LOAD - system timer comp2 conf sync register - 0x58 - 0x20 - - - TIMER_COMP2_LOAD - timer comp2 sync enable signal - 0 - 1 - write-only - - - - - UNIT0_LOAD - system timer unit0 conf sync register - 0x5C - 0x20 - - - TIMER_UNIT0_LOAD - timer unit0 sync enable signal - 0 - 1 - write-only - - - - - UNIT1_LOAD - system timer unit1 conf sync register - 0x60 - 0x20 - - - TIMER_UNIT1_LOAD - timer unit1 sync enable signal - 0 - 1 - write-only - - - - - INT_ENA - systimer interrupt enable register - 0x64 - 0x20 - - - TARGET0_INT_ENA - interupt0 enable - 0 - 1 - read-write - - - TARGET1_INT_ENA - interupt1 enable - 1 - 1 - read-write - - - TARGET2_INT_ENA - interupt2 enable - 2 - 1 - read-write - - - - - INT_RAW - systimer interrupt raw register - 0x68 - 0x20 - - - TARGET0_INT_RAW - interupt0 raw - 0 - 1 - read-write - - - TARGET1_INT_RAW - interupt1 raw - 1 - 1 - read-write - - - TARGET2_INT_RAW - interupt2 raw - 2 - 1 - read-write - - - - - INT_CLR - systimer interrupt clear register - 0x6C - 0x20 - - - TARGET0_INT_CLR - interupt0 clear - 0 - 1 - write-only - - - TARGET1_INT_CLR - interupt1 clear - 1 - 1 - write-only - - - TARGET2_INT_CLR - interupt2 clear - 2 - 1 - write-only - - - - - INT_ST - systimer interrupt status register - 0x70 - 0x20 - - - TARGET0_INT_ST - interupt0 status - 0 - 1 - read-only - - - TARGET1_INT_ST - interupt1 status - 1 - 1 - read-only - - - TARGET2_INT_ST - interupt2 status - 2 - 1 - read-only - - - - - REAL_TARGET0_LO - system timer comp0 actual target value low register - 0x74 - 0x20 - - - TARGET0_LO_RO - actual target value value low 32bits - 0 - 32 - read-only - - - - - REAL_TARGET0_HI - system timer comp0 actual target value high register - 0x78 - 0x20 - - - TARGET0_HI_RO - actual target value value high 20bits - 0 - 20 - read-only - - - - - REAL_TARGET1_LO - system timer comp1 actual target value low register - 0x7C - 0x20 - - - TARGET1_LO_RO - actual target value value low 32bits - 0 - 32 - read-only - - - - - REAL_TARGET1_HI - system timer comp1 actual target value high register - 0x80 - 0x20 - - - TARGET1_HI_RO - actual target value value high 20bits - 0 - 20 - read-only - - - - - REAL_TARGET2_LO - system timer comp2 actual target value low register - 0x84 - 0x20 - - - TARGET2_LO_RO - actual target value value low 32bits - 0 - 32 - read-only - - - - - REAL_TARGET2_HI - system timer comp2 actual target value high register - 0x88 - 0x20 - - - TARGET2_HI_RO - actual target value value high 20bits - 0 - 20 - read-only - - - - - DATE - system timer version control register - 0xFC - 0x20 - 0x02201073 - - - DATE - systimer register version - 0 - 32 - read-write - - - - - - - TIMG0 - Timer Group 0 - TIMG - 0x500C2000 - - 0x0 - 0x68 - registers - - - TG0_T0 - 46 - - - TG0_T1 - 47 - - - TG0_WDT - 48 - - - - T0CONFIG - Timer %s configuration register - 0x0 - 0x20 - 0x60002000 - - - USE_XTAL - 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source clock of timer group. - 9 - 1 - read-write - - - ALARM_EN - When set, the alarm is enabled. This bit is automatically cleared once an -alarm occurs. - 10 - 1 - read-write - - - DIVCNT_RST - When set, Timer %s 's clock divider counter will be reset. - 12 - 1 - write-only - - - DIVIDER - Timer %s clock (T%s_clk) prescaler value. - 13 - 16 - read-write - - - AUTORELOAD - When set, timer %s auto-reload at alarm is enabled. - 29 - 1 - read-write - - - INCREASE - When set, the timer %s time-base counter will increment every clock tick. When -cleared, the timer %s time-base counter will decrement. - 30 - 1 - read-write - - - EN - When set, the timer %s time-base counter is enabled. - 31 - 1 - read-write - - - - - T0LO - Timer %s current value, low 32 bits - 0x4 - 0x20 - - - LO - After writing to TIMG_T%sUPDATE_REG, the low 32 bits of the time-base counter -of timer %s can be read here. - 0 - 32 - read-only - - - - - T0HI - Timer %s current value, high 22 bits - 0x8 - 0x20 - - - HI - After writing to TIMG_T%sUPDATE_REG, the high 22 bits of the time-base counter -of timer %s can be read here. - 0 - 22 - read-only - - - - - T0UPDATE - Write to copy current timer value to TIMGn_T%s_(LO/HI)_REG - 0xC - 0x20 - - - UPDATE - After writing 0 or 1 to TIMG_T%sUPDATE_REG, the counter value is latched. - 31 - 1 - read-write - - - - - T0ALARMLO - Timer %s alarm value, low 32 bits - 0x10 - 0x20 - - - ALARM_LO - Timer %s alarm trigger time-base counter value, low 32 bits. - 0 - 32 - read-write - - - - - T0ALARMHI - Timer %s alarm value, high bits - 0x14 - 0x20 - - - ALARM_HI - Timer %s alarm trigger time-base counter value, high 22 bits. - 0 - 22 - read-write - - - - - T0LOADLO - Timer %s reload value, low 32 bits - 0x18 - 0x20 - - - LOAD_LO - Low 32 bits of the value that a reload will load onto timer %s time-base -Counter. - 0 - 32 - read-write - - - - - T0LOADHI - Timer %s reload value, high 22 bits - 0x1C - 0x20 - - - LOAD_HI - High 22 bits of the value that a reload will load onto timer %s time-base -counter. - 0 - 22 - read-write - - - - - T0LOAD - Write to reload timer from TIMG_T%s_(LOADLOLOADHI)_REG - 0x20 - 0x20 - - - LOAD - Write any value to trigger a timer %s time-base counter reload. - 0 - 32 - write-only - - - - - WDTCONFIG0 - Watchdog timer configuration register - 0x48 - 0x20 - 0x0004C000 - - - WDT_APPCPU_RESET_EN - WDT reset CPU enable. - 12 - 1 - read-write - - - WDT_PROCPU_RESET_EN - WDT reset CPU enable. - 13 - 1 - read-write - - - WDT_FLASHBOOT_MOD_EN - When set, Flash boot protection is enabled. - 14 - 1 - read-write - - - WDT_SYS_RESET_LENGTH - System reset signal length selection. 0: 100 ns, 1: 200 ns, -2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. - 15 - 3 - read-write - - - WDT_CPU_RESET_LENGTH - CPU reset signal length selection. 0: 100 ns, 1: 200 ns, -2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. - 18 - 3 - read-write - - - WDT_USE_XTAL - choose WDT clock:0-apb_clk, 1-xtal_clk. - 21 - 1 - read-write - - - WDT_CONF_UPDATE_EN - update the WDT configuration registers - 22 - 1 - write-only - - - WDT_STG3 - Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. - 23 - 2 - read-write - - - WDT_STG2 - Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. - 25 - 2 - read-write - - - WDT_STG1 - Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. - 27 - 2 - read-write - - - WDT_STG0 - Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. - 29 - 2 - read-write - - - WDT_EN - When set, MWDT is enabled. - 31 - 1 - read-write - - - - - WDTCONFIG1 - Watchdog timer prescaler register - 0x4C - 0x20 - 0x00010000 - - - WDT_DIVCNT_RST - When set, WDT 's clock divider counter will be reset. - 0 - 1 - write-only - - - WDT_CLK_PRESCALE - MWDT clock prescaler value. MWDT clock period = 12.5 ns * -TIMG_WDT_CLK_PRESCALE. - 16 - 16 - read-write - - - - - WDTCONFIG2 - Watchdog timer stage 0 timeout value - 0x50 - 0x20 - 0x018CBA80 - - - WDT_STG0_HOLD - Stage 0 timeout value, in MWDT clock cycles. - 0 - 32 - read-write - - - - - WDTCONFIG3 - Watchdog timer stage 1 timeout value - 0x54 - 0x20 - 0x07FFFFFF - - - WDT_STG1_HOLD - Stage 1 timeout value, in MWDT clock cycles. - 0 - 32 - read-write - - - - - WDTCONFIG4 - Watchdog timer stage 2 timeout value - 0x58 - 0x20 - 0x000FFFFF - - - WDT_STG2_HOLD - Stage 2 timeout value, in MWDT clock cycles. - 0 - 32 - read-write - - - - - WDTCONFIG5 - Watchdog timer stage 3 timeout value - 0x5C - 0x20 - 0x000FFFFF - - - WDT_STG3_HOLD - Stage 3 timeout value, in MWDT clock cycles. - 0 - 32 - read-write - - - - - WDTFEED - Write to feed the watchdog timer - 0x60 - 0x20 - - - WDT_FEED - Write any value to feed the MWDT. (WO) - 0 - 32 - write-only - - - - - WDTWPROTECT - Watchdog write protect register - 0x64 - 0x20 - 0x50D83AA1 - - - WDT_WKEY - If the register contains a different value than its reset value, write -protection is enabled. - 0 - 32 - read-write - - - - - RTCCALICFG - RTC calibration configure register - 0x68 - 0x20 - 0x00011000 - - - RTC_CALI_START_CYCLING - 0: one-shot frequency calculation,1: periodic frequency calculation, - 12 - 1 - read-write - - - RTC_CALI_CLK_SEL - 0:rtc slow clock. 1:clk_8m, 2:xtal_32k. - 13 - 2 - read-write - - - RTC_CALI_RDY - indicate one-shot frequency calculation is done. - 15 - 1 - read-only - - - RTC_CALI_MAX - Configure the time to calculate RTC slow clock's frequency. - 16 - 15 - read-write - - - RTC_CALI_START - Set this bit to start one-shot frequency calculation. - 31 - 1 - read-write - - - - - RTCCALICFG1 - RTC calibration configure1 register - 0x6C - 0x20 - - - RTC_CALI_CYCLING_DATA_VLD - indicate periodic frequency calculation is done. - 0 - 1 - read-only - - - RTC_CALI_VALUE - When one-shot or periodic frequency calculation is done, read this value to calculate RTC slow clock's frequency. - 7 - 25 - read-only - - - - - INT_ENA_TIMERS - Interrupt enable bits - 0x70 - 0x20 - - - T0_INT_ENA - The interrupt enable bit for the TIMG_T0_INT interrupt. - 0 - 1 - read-write - - - T1_INT_ENA - The interrupt enable bit for the TIMG_T1_INT interrupt. - 1 - 1 - read-write - - - WDT_INT_ENA - The interrupt enable bit for the TIMG_WDT_INT interrupt. - 2 - 1 - read-write - - - - - INT_RAW_TIMERS - Raw interrupt status - 0x74 - 0x20 - - - T0_INT_RAW - The raw interrupt status bit for the TIMG_T0_INT interrupt. - 0 - 1 - read-only - - - T1_INT_RAW - The raw interrupt status bit for the TIMG_T1_INT interrupt. - 1 - 1 - read-only - - - WDT_INT_RAW - The raw interrupt status bit for the TIMG_WDT_INT interrupt. - 2 - 1 - read-only - - - - - INT_ST_TIMERS - Masked interrupt status - 0x78 - 0x20 - - - T0_INT_ST - The masked interrupt status bit for the TIMG_T0_INT interrupt. - 0 - 1 - read-only - - - T1_INT_ST - The masked interrupt status bit for the TIMG_T1_INT interrupt. - 1 - 1 - read-only - - - WDT_INT_ST - The masked interrupt status bit for the TIMG_WDT_INT interrupt. - 2 - 1 - read-only - - - - - INT_CLR_TIMERS - Interrupt clear bits - 0x7C - 0x20 - - - T0_INT_CLR - Set this bit to clear the TIMG_T0_INT interrupt. - 0 - 1 - write-only - - - T1_INT_CLR - Set this bit to clear the TIMG_T1_INT interrupt. - 1 - 1 - write-only - - - WDT_INT_CLR - Set this bit to clear the TIMG_WDT_INT interrupt. - 2 - 1 - write-only - - - - - RTCCALICFG2 - Timer group calibration register - 0x80 - 0x20 - 0xFFFFFF98 - - - RTC_CALI_TIMEOUT - RTC calibration timeout indicator - 0 - 1 - read-only - - - RTC_CALI_TIMEOUT_RST_CNT - Cycles that release calibration timeout reset - 3 - 4 - read-write - - - RTC_CALI_TIMEOUT_THRES - Threshold value for the RTC calibration timer. If the calibration timer's value exceeds this threshold, a timeout is triggered. - 7 - 25 - read-write - - - - - NTIMERS_DATE - Timer version control register - 0xF8 - 0x20 - 0x02209142 - - - NTIMGS_DATE - Timer version control register - 0 - 28 - read-write - - - - - REGCLK - Timer group clock gate register - 0xFC - 0x20 - 0x70000000 - - - ETM_EN - enable timer's etm task and event - 28 - 1 - read-write - - - WDT_CLK_IS_ACTIVE - enable WDT's clock - 29 - 1 - read-write - - - TIMER_CLK_IS_ACTIVE - enable Timer 30's clock - 30 - 1 - read-write - - - CLK_EN - Register clock gate signal. 1: Registers can be read and written to by software. 0: Registers can not be read or written to by software. - 31 - 1 - read-write - - - - - - - TIMG1 - Timer Group 1 - 0x500C3000 - - TG1_T0 - 49 - - - TG1_T1 - 50 - - - TG1_WDT - 51 - - - - TRACE0 - TRACE0 Peripheral - TRACE - 0x3FF04000 - - 0x0 - 0x4C - registers - - - - MEM_START_ADDR - mem start addr - 0x0 - 0x20 - - - MEM_START_ADDR - The start address of trace memory - 0 - 32 - read-write - - - - - MEM_END_ADDR - mem end addr - 0x4 - 0x20 - 0xFFFFFFFF - - - MEM_END_ADDR - The end address of trace memory - 0 - 32 - read-write - - - - - MEM_CURRENT_ADDR - mem current addr - 0x8 - 0x20 - - - MEM_CURRENT_ADDR - current_mem_addr,indicate that next writing addr - 0 - 32 - read-only - - - - - MEM_ADDR_UPDATE - mem addr update - 0xC - 0x20 - - - MEM_CURRENT_ADDR_UPDATE - when set, the will \hyperref[fielddesc:TRACEMEMCURRENTADDR]{TRACE_MEM_CURRENT_ADDR} update to \hyperref[fielddesc:TRACEMEMSTARTADDR]{TRACE_MEM_START_ADDR}. - 0 - 1 - write-only - - - - - FIFO_STATUS - fifo status register - 0x10 - 0x20 - 0x00000001 - - - FIFO_EMPTY - Represent whether the fifo is empty. \\1: empty \\0: not empty - 0 - 1 - read-only - - - WORK_STATUS - Represent trace work status: \\0: idle state \\1: working state\\ 2: wait state due to hart halted or havereset \\3: lost state - 1 - 2 - read-only - - - - - INTR_ENA - interrupt enable register - 0x14 - 0x20 - - - FIFO_OVERFLOW_INTR_ENA - Set 1 enable fifo_overflow interrupt - 0 - 1 - read-write - - - MEM_FULL_INTR_ENA - Set 1 enable mem_full interrupt - 1 - 1 - read-write - - - - - INTR_RAW - interrupt status register - 0x18 - 0x20 - - - FIFO_OVERFLOW_INTR_RAW - fifo_overflow interrupt status - 0 - 1 - read-only - - - MEM_FULL_INTR_RAW - mem_full interrupt status - 1 - 1 - read-only - - - - - INTR_CLR - interrupt clear register - 0x1C - 0x20 - - - FIFO_OVERFLOW_INTR_CLR - Set 1 clear fifo overflow interrupt - 0 - 1 - write-only - - - MEM_FULL_INTR_CLR - Set 1 clear mem full interrupt - 1 - 1 - write-only - - - - - TRIGGER - trigger register - 0x20 - 0x20 - 0x0000000C - - - ON - Configure whether or not start trace.\\1: start trace \\0: invalid\\ - 0 - 1 - write-only - - - OFF - Configure whether or not stop trace.\\1: stop trace \\0: invalid\\ - 1 - 1 - write-only - - - MEM_LOOP - Configure memory loop mode. \\1: trace will loop wrtie trace_mem. \\0: when mem_current_addr at mem_end_addr, it will stop at the mem_end_addr\\ - 2 - 1 - read-write - - - RESTART_ENA - Configure whether or not enable auto-restart.\\1: enable\\0: disable\\ - 3 - 1 - read-write - - - - - CONFIG - trace configuration register - 0x24 - 0x20 - - - DM_TRIGGER_ENA - Configure whether or not enable cpu trigger action.\\1: enable\\0:disable\\ - 0 - 1 - read-write - - - RESET_ENA - Configure whether or not enable trace cpu haverest, when enabeld, if cpu have reset, the encoder will output a packet to report the address of the last instruction, and upon reset deassertion, the encoder start again.\\1: enabeld\\0: disabled\\ - 1 - 1 - read-write - - - HALT_ENA - Configure whether or not enable trace cpu is halted, when enabeld, if the cpu halted, the encoder will output a packet to report the address of the last instruction, and upon halted deassertion, the encoder start again.When disabled, encoder will not report the last address before halted and first address after halted, cpu halted information will not be tracked. \\1: enabeld\\0: disabled\\ - 2 - 1 - read-write - - - STALL_ENA - Configure whether or not enable stall cpu. When enabled, when the fifo almost full, the cpu will be stalled until the packets is able to write to fifo.\\1: enabled.\\0: disabled\\ - 3 - 1 - read-write - - - FULL_ADDRESS - Configure whether or not enable full-address mode.\\1: full address mode.\\0: delta address mode\\ - 4 - 1 - read-write - - - IMPLICIT_EXCEPT - Configure whether or not enabel implicit exception mode. When enabled,, do not sent exception address, only exception cause in exception packets.\\1: enabled\\0: disabled\\ - 5 - 1 - read-write - - - - - FILTER_CONTROL - filter control register - 0x28 - 0x20 - - - FILTER_EN - Configure whether or not enable filter unit. \\1: enable filter.\\ 0: always match - 0 - 1 - read-write - - - MATCH_COMP - when set, the comparator must be high in order for the filter to match - 1 - 1 - read-write - - - MATCH_PRIVILEGE - when set, match privilege levels specified by \hyperref[fielddesc:TRACEMATCHCHOICEPRIVILEGE]{TRACE_MATCH_CHOICE_PRIVILEGE}. - 2 - 1 - read-write - - - MATCH_ECAUSE - when set, start matching from exception cause codes specified by \hyperref[fielddesc:TRACEMATCHCHOICEECAUSE]{TRACE_MATCH_CHOICE_ECAUSE}, and stop matching upon return from the 1st matching exception. - 3 - 1 - read-write - - - MATCH_INTERRUPT - when set, start matching from a trap with the interrupt level codes specified by \hyperref[fielddesc:TRACEMATCHVALUEINTERRUPT]{TRACE_MATCH_VALUE_INTERRUPT}, and stop matching upon return from the 1st matching trap. - 4 - 1 - read-write - - - - - FILTER_MATCH_CONTROL - filter match control register - 0x2C - 0x20 - - - MATCH_CHOICE_PRIVILEGE - Select match which privilege level when \hyperref[fielddesc:TRACEMATCHPRIVILEGE]{TRACE_MATCH_PRIVILEGE} is set. \\1: machine mode. \\0: user mode - 0 - 1 - read-write - - - MATCH_VALUE_INTERRUPT - Select which match which itype when \hyperref[fielddesc:TRACEMATCHINTERRUPT]{TRACE_MATCH_INTERRUP} is set. \\1: match itype of 2. \\0: match itype or 1. - 1 - 1 - read-write - - - MATCH_CHOICE_ECAUSE - specified which ecause matched. - 2 - 6 - read-write - - - - - FILTER_COMPARATOR_CONTROL - filter comparator match control register - 0x30 - 0x20 - - - P_INPUT - Determines which input to compare against the primary comparator, \\0: iaddr, \\1: tval. - 0 - 1 - read-write - - - P_FUNCTION - Select the primary comparator function. \\0: equal, \\1: not equal, \\2: less than, \\3: less than or equal, \\4: greater than, \\5: greater than or equal, \\other: always match - 2 - 3 - read-write - - - P_NOTIFY - Generate a trace packet explicitly reporting the address that cause the primary match - 5 - 1 - read-write - - - S_INPUT - Determines which input to compare against the secondary comparator, \\0: iaddr, \\1: tval. - 8 - 1 - read-write - - - S_FUNCTION - Select the secondary comparator function. \\0: equal, \\1: not equal, \\2: less than, \\3: less than or equal, \\4: greater than, \\5: greater than or equal, \\other: always match - 10 - 3 - read-write - - - S_NOTIFY - Generate a trace packet explicitly reporting the address that cause the secondary match - 13 - 1 - read-write - - - MATCH_MODE - 0: only primary matches, \\1: primary and secondary comparator both matches(P\&\&S),\\ 2:either primary or secondary comparator matches !(P\&\&S), \\3: set when primary matches and continue to match until after secondary comparator matches - 16 - 2 - read-write - - - - - FILTER_P_COMPARATOR_MATCH - primary comparator match value - 0x34 - 0x20 - - - P_MATCH - primary comparator match value - 0 - 32 - read-write - - - - - FILTER_S_COMPARATOR_MATCH - secondary comparator match value - 0x38 - 0x20 - - - S_MATCH - secondary comparator match value - 0 - 32 - read-write - - - - - RESYNC_PROLONGED - resync configuration register - 0x3C - 0x20 - 0x00000080 - - - RESYNC_PROLONGED - count number, when count to this value, send a sync package - 0 - 24 - read-write - - - RESYNC_MODE - resyc mode sel: \\0: off, \\2: cycle count \\3: package num count - 24 - 2 - read-write - - - - - AHB_CONFIG - AHB config register - 0x40 - 0x20 - - - HBURST - set hburst - 0 - 3 - read-write - - - MAX_INCR - set max continuous access for incr mode - 3 - 3 - read-write - - - - - CLOCK_GATE - Clock gate control register - 0x44 - 0x20 - 0x00000001 - - - CLK_EN - The bit is used to enable clock gate when access all registers in this module. - 0 - 1 - read-write - - - - - DATE - Version control register - 0x3FC - 0x20 - 0x02211300 - - - DATE - version control register. Note that this default value stored is the latest date when the hardware logic was updated. - 0 - 28 - read-write - - - - - - - TRACE1 - TRACE1 Peripheral - 0x3FF05000 - - - LP_TSENS - Low-power Temperature Sensor - TSENS - 0x5012F000 - - 0x0 - 0x38 - registers - - - LP_TSENS - 15 - - - - CTRL - Tsens configuration. - 0x0 - 0x20 - 0x00019400 - - - OUT - Temperature sensor data out. - 0 - 8 - read-only - - - READY - Indicate temperature sensor out ready. - 8 - 1 - read-only - - - SAMPLE_EN - Enable sample signal for wakeup module. - 9 - 1 - read-write - - - WAKEUP_MASK - Wake up signal mask. - 10 - 1 - read-write - - - INT_EN - Enable temperature sensor to send out interrupt. - 12 - 1 - read-write - - - IN_INV - Invert temperature sensor data. - 13 - 1 - read-write - - - CLK_DIV - Temperature sensor clock divider. - 14 - 8 - read-write - - - POWER_UP - Temperature sensor power up. - 22 - 1 - read-write - - - POWER_UP_FORCE - 1: dump out & power up controlled by SW, 0: by FSM. - 23 - 1 - read-write - - - - - CTRL2 - Tsens configuration. - 0x4 - 0x20 - 0x00004002 - - - XPD_WAIT - N/A - 0 - 12 - read-write - - - XPD_FORCE - N/A - 12 - 2 - read-write - - - CLK_INV - N/A - 14 - 1 - read-write - - - - - INT_RAW - Tsens interrupt raw registers. - 0x8 - 0x20 - - - COCPU_TSENS_WAKE_INT_RAW - Tsens wakeup interrupt raw. - 0 - 1 - read-write - - - - - INT_ST - Tsens interrupt status registers. - 0xC - 0x20 - - - COCPU_TSENS_WAKE_INT_ST - Tsens wakeup interrupt status. - 0 - 1 - read-only - - - - - INT_ENA - Tsens interrupt enable registers. - 0x10 - 0x20 - - - COCPU_TSENS_WAKE_INT_ENA - Tsens wakeup interrupt enable. - 0 - 1 - read-write - - - - - INT_CLR - Tsens interrupt clear registers. - 0x14 - 0x20 - - - COCPU_TSENS_WAKE_INT_CLR - Tsens wakeup interrupt clear. - 0 - 1 - write-only - - - - - CLK_CONF - Tsens regbank configuration registers. - 0x18 - 0x20 - - - CLK_EN - Tsens regbank clock gating enable. - 0 - 1 - read-write - - - - - INT_ENA_W1TS - Tsens wakeup interrupt enable assert. - 0x1C - 0x20 - - - COCPU_TSENS_WAKE_INT_ENA_W1TS - Write 1 to this field to assert interrupt enable. - 0 - 1 - write-only - - - - - INT_ENA_W1TC - Tsens wakeup interrupt enable deassert. - 0x20 - 0x20 - - - COCPU_TSENS_WAKE_INT_ENA_W1TC - Write 1 to this field to deassert interrupt enable. - 0 - 1 - write-only - - - - - WAKEUP_CTRL - Tsens wakeup control registers. - 0x24 - 0x20 - 0x003FC000 - - - WAKEUP_TH_LOW - Lower threshold. - 0 - 8 - read-write - - - WAKEUP_TH_HIGH - Upper threshold. - 14 - 8 - read-write - - - WAKEUP_OVER_UPPER_TH - Indicates that this wakeup event arose from exceeding upper threshold. - 29 - 1 - read-only - - - WAKEUP_EN - Tsens wakeup enable. - 30 - 1 - read-write - - - WAKEUP_MODE - 0:absolute value comparison mode. 1: relative value comparison mode. - 31 - 1 - read-write - - - - - SAMPLE_RATE - Hardware automatic sampling control registers. - 0x28 - 0x20 - 0x00000014 - - - SAMPLE_RATE - Hardware automatic sampling rate. - 0 - 16 - read-write - - - - - RND_ECO_LOW - N/A - 0x2C - 0x20 - - - RND_ECO_LOW - N/A - 0 - 32 - read-write - - - - - RND_ECO_HIGH - N/A - 0x30 - 0x20 - 0xFFFFFFFF - - - RND_ECO_HIGH - N/A - 0 - 32 - read-write - - - - - RND_ECO_CS - N/A - 0x34 - 0x20 - - - RND_ECO_EN - N/A - 0 - 1 - read-write - - - RND_ECO_RESULT - N/A - 1 - 1 - read-only - - - - - - - TWAI0 - Two-Wire Automotive Interface - TWAI - 0x500D7000 - - 0x0 - 0x8C - registers - - - TWAI0 - 40 - - - - MODE - TWAI mode register. - 0x0 - 0x20 - 0x00000001 - - - RESET_MODE - 1: reset, detection of a set reset mode bit results in aborting the current transmission/reception of a message and entering the reset mode. 0: normal, on the '1-to-0' transition of the reset mode bit, the TWAI controller returns to the operating mode. - 0 - 1 - read-write - - - LISTEN_ONLY_MODE - 1: listen only, in this mode the TWAI controller would give no acknowledge to the TWAI-bus, even if a message is received successfully. The error counters are stopped at the current value. 0: normal. - 1 - 1 - read-write - - - SELF_TEST_MODE - 1: self test, in this mode a full node test is possible without any other active node on the bus using the self reception request command. The TWAI controller will perform a successful transmission, even if there is no acknowledge received. 0: normal, an acknowledge is required for successful transmission. - 2 - 1 - read-write - - - ACCEPTANCE_FILTER_MODE - 1:single, the single acceptance filter option is enabled (one filter with the length of 32 bit is active). 0:dual, the dual acceptance filter option is enabled (two filters, each with the length of 16 bit are active). - 3 - 1 - read-write - - - - - CMD - TWAI command register. - 0x4 - 0x20 - - - TX_REQUEST - 1: present, a message shall be transmitted. 0: absent - 0 - 1 - write-only - - - ABORT_TX - 1: present, if not already in progress, a pending transmission request is cancelled. 0: absent - 1 - 1 - write-only - - - RELEASE_BUFFER - 1: released, the receive buffer, representing the message memory space in the RXFIFO is released. 0: no action - 2 - 1 - write-only - - - CLEAR_DATA_OVERRUN - 1: clear, the data overrun status bit is cleared. 0: no action. - 3 - 1 - write-only - - - SELF_RX_REQUEST - 1: present, a message shall be transmitted and received simultaneously. 0: absent. - 4 - 1 - write-only - - - - - STATUS - TWAI status register. - 0x8 - 0x20 - - - RECEIVE_BUFFER - 1: full, one or more complete messages are available in the RXFIFO. 0: empty, no message is available - 0 - 1 - read-only - - - OVERRUN - 1: overrun, a message was lost because there was not enough space for that message in the RXFIFO. 0: absent, no data overrun has occurred since the last clear data overrun command was given - 1 - 1 - read-only - - - TRANSMIT_BUFFER - 1: released, the CPU may write a message into the transmit buffer. 0: locked, the CPU cannot access the transmit buffer, a message is either waiting for transmission or is in the process of being transmitted - 2 - 1 - read-only - - - TRANSMISSION_COMPLETE - 1: complete, last requested transmission has been successfully completed. 0: incomplete, previously requested transmission is not yet completed - 3 - 1 - read-only - - - RECEIVE - 1: receive, the TWAI controller is receiving a message. 0: idle - 4 - 1 - read-only - - - TRANSMIT - 1: transmit, the TWAI controller is transmitting a message. 0: idle - 5 - 1 - read-only - - - ERR - 1: error, at least one of the error counters has reached or exceeded the CPU warning limit defined by the Error Warning Limit Register (EWLR). 0: ok, both error counters are below the warning limit - 6 - 1 - read-only - - - NODE_BUS_OFF - 1: bus-off, the TWAI controller is not involved in bus activities. 0: bus-on, the TWAI controller is involved in bus activities - 7 - 1 - read-only - - - MISS - 1: current message is destroyed because of FIFO overflow. - 8 - 1 - read-only - - - - - INTERRUPT - Interrupt signals' register. - 0xC - 0x20 - - - RECEIVE_INT_ST - 1: this bit is set while the receive FIFO is not empty and the RIE bit is set within the interrupt enable register. 0: reset - 0 - 1 - read-only - - - TRANSMIT_INT_ST - 1: this bit is set whenever the transmit buffer status changes from '0-to-1' (released) and the TIE bit is set within the interrupt enable register. 0: reset - 1 - 1 - read-only - - - ERR_WARNING_INT_ST - 1: this bit is set on every change (set and clear) of either the error status or bus status bits and the EIE bit is set within the interrupt enable register. 0: reset - 2 - 1 - read-only - - - DATA_OVERRUN_INT_ST - 1: this bit is set on a '0-to-1' transition of the data overrun status bit and the DOIE bit is set within the interrupt enable register. 0: reset - 3 - 1 - read-only - - - TS_COUNTER_OVFL_INT_ST - 1: this bit is set then the timestamp counter reaches the maximum value and overflow. - 4 - 1 - read-only - - - ERR_PASSIVE_INT_ST - 1: this bit is set whenever the TWAI controller has reached the error passive status (at least one error counter exceeds the protocol-defined level of 127) or if the TWAI controller is in the error passive status and enters the error active status again and the EPIE bit is set within the interrupt enable register. 0: reset - 5 - 1 - read-only - - - ARBITRATION_LOST_INT_ST - 1: this bit is set when the TWAI controller lost the arbitration and becomes a receiver and the ALIE bit is set within the interrupt enable register. 0: reset - 6 - 1 - read-only - - - BUS_ERR_INT_ST - 1: this bit is set when the TWAI controller detects an error on the TWAI-bus and the BEIE bit is set within the interrupt enable register. 0: reset - 7 - 1 - read-only - - - IDLE_INT_ST - 1: this bit is set when the TWAI controller detects state of TWAI become IDLE and this interrupt enable bit is set within the interrupt enable register. 0: reset - 8 - 1 - read-only - - - - - INTERRUPT_ENABLE - Interrupt enable register. - 0x10 - 0x20 - - - EXT_RECEIVE_INT_ENA - 1: enabled, when the receive buffer status is 'full' the TWAI controller requests the respective interrupt. 0: disable - 0 - 1 - read-write - - - EXT_TRANSMIT_INT_ENA - 1: enabled, when a message has been successfully transmitted or the transmit buffer is accessible again (e.g. after an abort transmission command), the TWAI controller requests the respective interrupt. 0: disable - 1 - 1 - read-write - - - EXT_ERR_WARNING_INT_ENA - 1: enabled, if the error or bus status change (see status register. Table 14), the TWAI controllerrequests the respective interrupt. 0: disable - 2 - 1 - read-write - - - EXT_DATA_OVERRUN_INT_ENA - 1: enabled, if the data overrun status bit is set (see status register. Table 14), the TWAI controllerrequests the respective interrupt. 0: disable - 3 - 1 - read-write - - - TS_COUNTER_OVFL_INT_ENA - enable the timestamp counter overflow interrupt request. - 4 - 1 - read-write - - - ERR_PASSIVE_INT_ENA - 1: enabled, if the error status of the TWAI controller changes from error active to error passive or vice versa, the respective interrupt is requested. 0: disable - 5 - 1 - read-write - - - ARBITRATION_LOST_INT_ENA - 1: enabled, if the TWAI controller has lost arbitration, the respective interrupt is requested. 0: disable - 6 - 1 - read-write - - - BUS_ERR_INT_ENA - 1: enabled, if an bus error has been detected, the TWAI controller requests the respective interrupt. 0: disable - 7 - 1 - read-write - - - IDLE_INT_ENA - 1: enabled, if state of TWAI become IDLE, the TWAI controller requests the respective interrupt. 0: disable - 8 - 1 - read-only - - - - - BUS_TIMING_0 - Bit timing configuration register 0. - 0x18 - 0x20 - - - BAUD_PRESC - The period of the TWAI system clock is programmable and determines the individual bit timing. Software has R/W permission in reset mode and RO permission in operation mode. - 0 - 14 - read-write - - - SYNC_JUMP_WIDTH - The synchronization jump width defines the maximum number of clock cycles a bit period may be shortened or lengthened. Software has R/W permission in reset mode and RO in operation mode. - 14 - 2 - read-write - - - - - BUS_TIMING_1 - Bit timing configuration register 1. - 0x1C - 0x20 - - - TIME_SEGMENT1 - The number of clock cycles in TSEG1 per bit timing. Software has R/W permission in reset mode and RO in operation mode. - 0 - 4 - read-write - - - TIME_SEGMENT2 - The number of clock cycles in TSEG2 per bit timing. Software has R/W permission in reset mode and RO in operation mode. - 4 - 3 - read-write - - - TIME_SAMPLING - 1: triple, the bus is sampled three times. 0: single, the bus is sampled once. Software has R/W permission in reset mode and RO in operation mode. - 7 - 1 - read-write - - - - - ARB_LOST_CAP - TWAI arbiter lost capture register. - 0x2C - 0x20 - - - ARBITRATION_LOST_CAPTURE - This register contains information about the bit position of losing arbitration. - 0 - 5 - read-only - - - - - ERR_CODE_CAP - TWAI error info capture register. - 0x30 - 0x20 - - - ERR_CAPTURE_CODE_SEGMENT - This register contains information about the location of errors on the bus. - 0 - 5 - read-only - - - ERR_CAPTURE_CODE_DIRECTION - 1: RX, error occurred during reception. 0: TX, error occurred during transmission. - 5 - 1 - read-only - - - ERR_CAPTURE_CODE_TYPE - 00: bit error. 01: form error. 10:stuff error. 11:other type of error. - 6 - 2 - read-only - - - - - ERR_WARNING_LIMIT - TWAI error threshold configuration register. - 0x34 - 0x20 - 0x00000060 - - - ERR_WARNING_LIMIT - The threshold that trigger error warning interrupt when this interrupt is enabled. Software has R/W permission in reset mode and RO in operation mode. - 0 - 8 - read-write - - - - - RX_ERR_CNT - Rx error counter register. - 0x38 - 0x20 - - - RX_ERR_CNT - The RX error counter register reflects the current value of the transmit error counter. Software has R/W permission in reset mode and RO in operation mode. - 0 - 8 - read-write - - - - - TX_ERR_CNT - Tx error counter register. - 0x3C - 0x20 - - - TX_ERR_CNT - The TX error counter register reflects the current value of the transmit error counter. Software has R/W permission in reset mode and RO in operation mode. - 0 - 8 - read-write - - - - - DATA_0 - Data register 0. - 0x40 - 0x20 - - - DATA_0 - In reset mode, it is acceptance code register 0 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 0 and when software initiate read operation, it is rx data register 0. - 0 - 8 - read-write - - - - - DATA_1 - Data register 1. - 0x44 - 0x20 - - - DATA_1 - In reset mode, it is acceptance code register 1 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 1 and when software initiate read operation, it is rx data register 1. - 0 - 8 - read-write - - - - - DATA_2 - Data register 2. - 0x48 - 0x20 - - - DATA_2 - In reset mode, it is acceptance code register 2 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 2 and when software initiate read operation, it is rx data register 2. - 0 - 8 - read-write - - - - - DATA_3 - Data register 3. - 0x4C - 0x20 - - - DATA_3 - In reset mode, it is acceptance code register 3 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 3 and when software initiate read operation, it is rx data register 3. - 0 - 8 - read-write - - - - - DATA_4 - Data register 4. - 0x50 - 0x20 - - - DATA_4 - In reset mode, it is acceptance mask register 0 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 4 and when software initiate read operation, it is rx data register 4. - 0 - 8 - read-write - - - - - DATA_5 - Data register 5. - 0x54 - 0x20 - - - DATA_5 - In reset mode, it is acceptance mask register 1 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 5 and when software initiate read operation, it is rx data register 5. - 0 - 8 - read-write - - - - - DATA_6 - Data register 6. - 0x58 - 0x20 - - - DATA_6 - In reset mode, it is acceptance mask register 2 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 6 and when software initiate read operation, it is rx data register 6. - 0 - 8 - read-write - - - - - DATA_7 - Data register 7. - 0x5C - 0x20 - - - DATA_7 - In reset mode, it is acceptance mask register 3 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 7 and when software initiate read operation, it is rx data register 7. - 0 - 8 - read-write - - - - - DATA_8 - Data register 8. - 0x60 - 0x20 - - - DATA_8 - In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 8 and when software initiate read operation, it is rx data register 8. - 0 - 8 - read-write - - - - - DATA_9 - Data register 9. - 0x64 - 0x20 - - - DATA_9 - In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 9 and when software initiate read operation, it is rx data register 9. - 0 - 8 - read-write - - - - - DATA_10 - Data register 10. - 0x68 - 0x20 - - - DATA_10 - In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 10 and when software initiate read operation, it is rx data register 10. - 0 - 8 - read-write - - - - - DATA_11 - Data register 11. - 0x6C - 0x20 - - - DATA_11 - In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 11 and when software initiate read operation, it is rx data register 11. - 0 - 8 - read-write - - - - - DATA_12 - Data register 12. - 0x70 - 0x20 - - - DATA_12 - In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 12 and when software initiate read operation, it is rx data register 12. - 0 - 8 - read-write - - - - - RX_MESSAGE_COUNTER - Received message counter register. - 0x74 - 0x20 - - - RX_MESSAGE_COUNTER - Reflects the number of messages available within the RXFIFO. The value is incremented with each receive event and decremented by the release receive buffer command. - 0 - 7 - read-only - - - - - CLOCK_DIVIDER - Clock divider register. - 0x7C - 0x20 - - - CD - These bits are used to define the frequency at the external CLKOUT pin. - 0 - 8 - read-write - - - CLOCK_OFF - 1: Disable the external CLKOUT pin. 0: Enable the external CLKOUT pin. Software has R/W permission in reset mode and RO in operation mode. - 8 - 1 - read-write - - - - - SW_STANDBY_CFG - Software configure standby pin directly. - 0x80 - 0x20 - 0x00000002 - - - SW_STANDBY_EN - Enable standby pin. - 0 - 1 - read-write - - - SW_STANDBY_CLR - Clear standby pin. - 1 - 1 - read-write - - - - - HW_CFG - Hardware configure standby pin. - 0x84 - 0x20 - - - HW_STANDBY_EN - Enable function that hardware control standby pin. - 0 - 1 - read-write - - - - - HW_STANDBY_CNT - Configure standby counter. - 0x88 - 0x20 - 0x00000001 - - - STANDBY_WAIT_CNT - Configure the number of cycles before standby becomes high when TWAI_HW_STANDBY_EN is enabled. - 0 - 32 - read-write - - - - - IDLE_INTR_CNT - Configure idle interrupt counter. - 0x8C - 0x20 - 0x00000001 - - - IDLE_INTR_CNT - Configure the number of cycles before triggering idle interrupt. - 0 - 32 - read-write - - - - - ECO_CFG - ECO configuration register. - 0x90 - 0x20 - 0x00000002 - - - RDN_ENA - Enable eco module. - 0 - 1 - read-write - - - RDN_RESULT - Output of eco module. - 1 - 1 - read-only - - - - - TIMESTAMP_DATA - Timestamp data register - 0x94 - 0x20 - - - TIMESTAMP_DATA - Data of timestamp of a CAN frame. - 0 - 32 - read-only - - - - - TIMESTAMP_PRESCALER - Timestamp configuration register - 0x98 - 0x20 - 0x0000001F - - - TS_DIV_NUM - Configures the clock division number of timestamp counter. - 0 - 16 - read-write - - - - - TIMESTAMP_CFG - Timestamp configuration register - 0x9C - 0x20 - - - TS_ENABLE - enable the timestamp collection function. - 0 - 1 - read-write - - - - - - - TWAI1 - Two-Wire Automotive Interface - 0x500D8000 - - TWAI1 - 41 - - - - TWAI2 - Two-Wire Automotive Interface - 0x500D9000 - - TWAI2 - 42 - - - - UART0 - UART (Universal Asynchronous Receiver-Transmitter) Controller 0 - UART - 0x500CA000 - - 0x0 - 0x98 - registers - - - UART0 - 31 - - - - FIFO - FIFO data register - 0x0 - 0x20 - - - RXFIFO_RD_BYTE - UART 0 accesses FIFO via this register. - 0 - 8 - read-only - - - - - INT_RAW - Raw interrupt status - 0x4 - 0x20 - 0x00000002 - - - RXFIFO_FULL_INT_RAW - This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies. - 0 - 1 - read-write - - - TXFIFO_EMPTY_INT_RAW - This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies . - 1 - 1 - read-write - - - PARITY_ERR_INT_RAW - This interrupt raw bit turns to high level when receiver detects a parity error in the data. - 2 - 1 - read-write - - - FRM_ERR_INT_RAW - This interrupt raw bit turns to high level when receiver detects a data frame error . - 3 - 1 - read-write - - - RXFIFO_OVF_INT_RAW - This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store. - 4 - 1 - read-write - - - DSR_CHG_INT_RAW - This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal. - 5 - 1 - read-write - - - CTS_CHG_INT_RAW - This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal. - 6 - 1 - read-write - - - BRK_DET_INT_RAW - This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit. - 7 - 1 - read-write - - - RXFIFO_TOUT_INT_RAW - This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte. - 8 - 1 - read-write - - - SW_XON_INT_RAW - This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1. - 9 - 1 - read-write - - - SW_XOFF_INT_RAW - This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1. - 10 - 1 - read-write - - - GLITCH_DET_INT_RAW - This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit. - 11 - 1 - read-write - - - TX_BRK_DONE_INT_RAW - This interrupt raw bit turns to high level when transmitter completes sending NULL characters after all data in Tx-FIFO are sent. - 12 - 1 - read-write - - - TX_BRK_IDLE_DONE_INT_RAW - This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data. - 13 - 1 - read-write - - - TX_DONE_INT_RAW - This interrupt raw bit turns to high level when transmitter has send out all data in FIFO. - 14 - 1 - read-write - - - RS485_PARITY_ERR_INT_RAW - This interrupt raw bit turns to high level when receiver detects a parity error from the echo of transmitter in rs485 mode. - 15 - 1 - read-write - - - RS485_FRM_ERR_INT_RAW - This interrupt raw bit turns to high level when receiver detects a data frame error from the echo of transmitter in rs485 mode. - 16 - 1 - read-write - - - RS485_CLASH_INT_RAW - This interrupt raw bit turns to high level when detects a clash between transmitter and receiver in rs485 mode. - 17 - 1 - read-write - - - AT_CMD_CHAR_DET_INT_RAW - This interrupt raw bit turns to high level when receiver detects the configured at_cmd char. - 18 - 1 - read-write - - - WAKEUP_INT_RAW - This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode. - 19 - 1 - read-write - - - - - INT_ST - Masked interrupt status - 0x8 - 0x20 - - - RXFIFO_FULL_INT_ST - This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. - 0 - 1 - read-only - - - TXFIFO_EMPTY_INT_ST - This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1. - 1 - 1 - read-only - - - PARITY_ERR_INT_ST - This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. - 2 - 1 - read-only - - - FRM_ERR_INT_ST - This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1. - 3 - 1 - read-only - - - RXFIFO_OVF_INT_ST - This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. - 4 - 1 - read-only - - - DSR_CHG_INT_ST - This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. - 5 - 1 - read-only - - - CTS_CHG_INT_ST - This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. - 6 - 1 - read-only - - - BRK_DET_INT_ST - This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. - 7 - 1 - read-only - - - RXFIFO_TOUT_INT_ST - This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. - 8 - 1 - read-only - - - SW_XON_INT_ST - This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. - 9 - 1 - read-only - - - SW_XOFF_INT_ST - This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. - 10 - 1 - read-only - - - GLITCH_DET_INT_ST - This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. - 11 - 1 - read-only - - - TX_BRK_DONE_INT_ST - This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. - 12 - 1 - read-only - - - TX_BRK_IDLE_DONE_INT_ST - This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1. - 13 - 1 - read-only - - - TX_DONE_INT_ST - This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. - 14 - 1 - read-only - - - RS485_PARITY_ERR_INT_ST - This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1. - 15 - 1 - read-only - - - RS485_FRM_ERR_INT_ST - This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set to 1. - 16 - 1 - read-only - - - RS485_CLASH_INT_ST - This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1. - 17 - 1 - read-only - - - AT_CMD_CHAR_DET_INT_ST - This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1. - 18 - 1 - read-only - - - WAKEUP_INT_ST - This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1. - 19 - 1 - read-only - - - - - INT_ENA - Interrupt enable bits - 0xC - 0x20 - - - RXFIFO_FULL_INT_ENA - This is the enable bit for rxfifo_full_int_st register. - 0 - 1 - read-write - - - TXFIFO_EMPTY_INT_ENA - This is the enable bit for txfifo_empty_int_st register. - 1 - 1 - read-write - - - PARITY_ERR_INT_ENA - This is the enable bit for parity_err_int_st register. - 2 - 1 - read-write - - - FRM_ERR_INT_ENA - This is the enable bit for frm_err_int_st register. - 3 - 1 - read-write - - - RXFIFO_OVF_INT_ENA - This is the enable bit for rxfifo_ovf_int_st register. - 4 - 1 - read-write - - - DSR_CHG_INT_ENA - This is the enable bit for dsr_chg_int_st register. - 5 - 1 - read-write - - - CTS_CHG_INT_ENA - This is the enable bit for cts_chg_int_st register. - 6 - 1 - read-write - - - BRK_DET_INT_ENA - This is the enable bit for brk_det_int_st register. - 7 - 1 - read-write - - - RXFIFO_TOUT_INT_ENA - This is the enable bit for rxfifo_tout_int_st register. - 8 - 1 - read-write - - - SW_XON_INT_ENA - This is the enable bit for sw_xon_int_st register. - 9 - 1 - read-write - - - SW_XOFF_INT_ENA - This is the enable bit for sw_xoff_int_st register. - 10 - 1 - read-write - - - GLITCH_DET_INT_ENA - This is the enable bit for glitch_det_int_st register. - 11 - 1 - read-write - - - TX_BRK_DONE_INT_ENA - This is the enable bit for tx_brk_done_int_st register. - 12 - 1 - read-write - - - TX_BRK_IDLE_DONE_INT_ENA - This is the enable bit for tx_brk_idle_done_int_st register. - 13 - 1 - read-write - - - TX_DONE_INT_ENA - This is the enable bit for tx_done_int_st register. - 14 - 1 - read-write - - - RS485_PARITY_ERR_INT_ENA - This is the enable bit for rs485_parity_err_int_st register. - 15 - 1 - read-write - - - RS485_FRM_ERR_INT_ENA - This is the enable bit for rs485_parity_err_int_st register. - 16 - 1 - read-write - - - RS485_CLASH_INT_ENA - This is the enable bit for rs485_clash_int_st register. - 17 - 1 - read-write - - - AT_CMD_CHAR_DET_INT_ENA - This is the enable bit for at_cmd_char_det_int_st register. - 18 - 1 - read-write - - - WAKEUP_INT_ENA - This is the enable bit for uart_wakeup_int_st register. - 19 - 1 - read-write - - - - - INT_CLR - Interrupt clear bits - 0x10 - 0x20 - - - RXFIFO_FULL_INT_CLR - Set this bit to clear the rxfifo_full_int_raw interrupt. - 0 - 1 - write-only - - - TXFIFO_EMPTY_INT_CLR - Set this bit to clear txfifo_empty_int_raw interrupt. - 1 - 1 - write-only - - - PARITY_ERR_INT_CLR - Set this bit to clear parity_err_int_raw interrupt. - 2 - 1 - write-only - - - FRM_ERR_INT_CLR - Set this bit to clear frm_err_int_raw interrupt. - 3 - 1 - write-only - - - RXFIFO_OVF_INT_CLR - Set this bit to clear rxfifo_ovf_int_raw interrupt. - 4 - 1 - write-only - - - DSR_CHG_INT_CLR - Set this bit to clear the dsr_chg_int_raw interrupt. - 5 - 1 - write-only - - - CTS_CHG_INT_CLR - Set this bit to clear the cts_chg_int_raw interrupt. - 6 - 1 - write-only - - - BRK_DET_INT_CLR - Set this bit to clear the brk_det_int_raw interrupt. - 7 - 1 - write-only - - - RXFIFO_TOUT_INT_CLR - Set this bit to clear the rxfifo_tout_int_raw interrupt. - 8 - 1 - write-only - - - SW_XON_INT_CLR - Set this bit to clear the sw_xon_int_raw interrupt. - 9 - 1 - write-only - - - SW_XOFF_INT_CLR - Set this bit to clear the sw_xoff_int_raw interrupt. - 10 - 1 - write-only - - - GLITCH_DET_INT_CLR - Set this bit to clear the glitch_det_int_raw interrupt. - 11 - 1 - write-only - - - TX_BRK_DONE_INT_CLR - Set this bit to clear the tx_brk_done_int_raw interrupt.. - 12 - 1 - write-only - - - TX_BRK_IDLE_DONE_INT_CLR - Set this bit to clear the tx_brk_idle_done_int_raw interrupt. - 13 - 1 - write-only - - - TX_DONE_INT_CLR - Set this bit to clear the tx_done_int_raw interrupt. - 14 - 1 - write-only - - - RS485_PARITY_ERR_INT_CLR - Set this bit to clear the rs485_parity_err_int_raw interrupt. - 15 - 1 - write-only - - - RS485_FRM_ERR_INT_CLR - Set this bit to clear the rs485_frm_err_int_raw interrupt. - 16 - 1 - write-only - - - RS485_CLASH_INT_CLR - Set this bit to clear the rs485_clash_int_raw interrupt. - 17 - 1 - write-only - - - AT_CMD_CHAR_DET_INT_CLR - Set this bit to clear the at_cmd_char_det_int_raw interrupt. - 18 - 1 - write-only - - - WAKEUP_INT_CLR - Set this bit to clear the uart_wakeup_int_raw interrupt. - 19 - 1 - write-only - - - - - CLKDIV_SYNC - Clock divider configuration - 0x14 - 0x20 - 0x000002B6 - - - CLKDIV - The integral part of the frequency divider factor. - 0 - 12 - read-write - - - CLKDIV_FRAG - The decimal part of the frequency divider factor. - 20 - 4 - read-write - - - - - RX_FILT - Rx Filter configuration - 0x18 - 0x20 - 0x00000008 - - - GLITCH_FILT - when input pulse width is lower than this value the pulse is ignored. - 0 - 8 - read-write - - - GLITCH_FILT_EN - Set this bit to enable Rx signal filter. - 8 - 1 - read-write - - - - - STATUS - UART status register - 0x1C - 0x20 - 0xE000C000 - - - RXFIFO_CNT - Stores the byte number of valid data in Rx-FIFO. - 0 - 8 - read-only - - - DSRN - The register represent the level value of the internal uart dsr signal. - 13 - 1 - read-only - - - CTSN - This register represent the level value of the internal uart cts signal. - 14 - 1 - read-only - - - RXD - This register represent the level value of the internal uart rxd signal. - 15 - 1 - read-only - - - TXFIFO_CNT - Stores the byte number of data in Tx-FIFO. - 16 - 8 - read-only - - - DTRN - This bit represents the level of the internal uart dtr signal. - 29 - 1 - read-only - - - RTSN - This bit represents the level of the internal uart rts signal. - 30 - 1 - read-only - - - TXD - This bit represents the level of the internal uart txd signal. - 31 - 1 - read-only - - - - - CONF0_SYNC - a - 0x20 - 0x20 - 0x0000001C - - - PARITY - This register is used to configure the parity check mode. - 0 - 1 - read-write - - - PARITY_EN - Set this bit to enable uart parity check. - 1 - 1 - read-write - - - BIT_NUM - This register is used to set the length of data. - 2 - 2 - read-write - - - STOP_BIT_NUM - This register is used to set the length of stop bit. - 4 - 2 - read-write - - - TXD_BRK - Set this bit to enbale transmitter to send NULL when the process of sending data is done. - 6 - 1 - read-write - - - IRDA_DPLX - Set this bit to enable IrDA loopback mode. - 7 - 1 - read-write - - - IRDA_TX_EN - This is the start enable bit for IrDA transmitter. - 8 - 1 - read-write - - - IRDA_WCTL - 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0. - 9 - 1 - read-write - - - IRDA_TX_INV - Set this bit to invert the level of IrDA transmitter. - 10 - 1 - read-write - - - IRDA_RX_INV - Set this bit to invert the level of IrDA receiver. - 11 - 1 - read-write - - - LOOPBACK - Set this bit to enable uart loopback test mode. - 12 - 1 - read-write - - - TX_FLOW_EN - Set this bit to enable flow control function for transmitter. - 13 - 1 - read-write - - - IRDA_EN - Set this bit to enable IrDA protocol. - 14 - 1 - read-write - - - RXD_INV - Set this bit to inverse the level value of uart rxd signal. - 15 - 1 - read-write - - - TXD_INV - Set this bit to inverse the level value of uart txd signal. - 16 - 1 - read-write - - - DIS_RX_DAT_OVF - Disable UART Rx data overflow detect. - 17 - 1 - read-write - - - ERR_WR_MASK - 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong. - 18 - 1 - read-write - - - AUTOBAUD_EN - This is the enable bit for detecting baudrate. - 19 - 1 - read-write - - - MEM_CLK_EN - UART memory clock gate enable signal. - 20 - 1 - read-write - - - SW_RTS - This register is used to configure the software rts signal which is used in software flow control. - 21 - 1 - read-write - - - RXFIFO_RST - Set this bit to reset the uart receive-FIFO. - 22 - 1 - read-write - - - TXFIFO_RST - Set this bit to reset the uart transmit-FIFO. - 23 - 1 - read-write - - - - - CONF1 - Configuration register 1 - 0x24 - 0x20 - 0x00006060 - - - RXFIFO_FULL_THRHD - It will produce rxfifo_full_int interrupt when receiver receives more data than this register value. - 0 - 8 - read-write - - - TXFIFO_EMPTY_THRHD - It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value. - 8 - 8 - read-write - - - CTS_INV - Set this bit to inverse the level value of uart cts signal. - 16 - 1 - read-write - - - DSR_INV - Set this bit to inverse the level value of uart dsr signal. - 17 - 1 - read-write - - - RTS_INV - Set this bit to inverse the level value of uart rts signal. - 18 - 1 - read-write - - - DTR_INV - Set this bit to inverse the level value of uart dtr signal. - 19 - 1 - read-write - - - SW_DTR - This register is used to configure the software dtr signal which is used in software flow control. - 20 - 1 - read-write - - - CLK_EN - 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers. - 21 - 1 - read-write - - - - - HWFC_CONF_SYNC - Hardware flow-control configuration - 0x2C - 0x20 - - - RX_FLOW_THRHD - This register is used to configure the maximum amount of data that can be received when hardware flow control works. - 0 - 8 - read-write - - - RX_FLOW_EN - This is the flow enable bit for UART receiver. - 8 - 1 - read-write - - - - - SLEEP_CONF0 - UART sleep configure register 0 - 0x30 - 0x20 - - - WK_CHAR1 - This register restores the specified wake up char1 to wake up - 0 - 8 - read-write - - - WK_CHAR2 - This register restores the specified wake up char2 to wake up - 8 - 8 - read-write - - - WK_CHAR3 - This register restores the specified wake up char3 to wake up - 16 - 8 - read-write - - - WK_CHAR4 - This register restores the specified wake up char4 to wake up - 24 - 8 - read-write - - - - - SLEEP_CONF1 - UART sleep configure register 1 - 0x34 - 0x20 - - - WK_CHAR0 - This register restores the specified char0 to wake up - 0 - 8 - read-write - - - - - SLEEP_CONF2 - UART sleep configure register 2 - 0x38 - 0x20 - 0x001404F0 - - - ACTIVE_THRESHOLD - The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value. - 0 - 10 - read-write - - - RX_WAKE_UP_THRHD - In wake up mode 1 this field is used to set the received data number threshold to wake up chip. - 10 - 8 - read-write - - - WK_CHAR_NUM - This register is used to select number of wake up char. - 18 - 3 - read-write - - - WK_CHAR_MASK - This register is used to mask wake up char. - 21 - 5 - read-write - - - WK_MODE_SEL - This register is used to select wake up mode. 0: RXD toggling to wake up. 1: received data number larger than - 26 - 2 - read-write - - - - - SWFC_CONF0_SYNC - Software flow-control character configuration - 0x3C - 0x20 - 0x00001311 - - - XON_CHAR - This register stores the Xon flow control char. - 0 - 8 - read-write - - - XOFF_CHAR - This register stores the Xoff flow control char. - 8 - 8 - read-write - - - XON_XOFF_STILL_SEND - In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In this status, UART Tx can not transmit XOFF even the received data number is larger than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when UART Tx is disabled. - 16 - 1 - read-write - - - SW_FLOW_CON_EN - Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff. - 17 - 1 - read-write - - - XONOFF_DEL - Set this bit to remove flow control char from the received data. - 18 - 1 - read-write - - - FORCE_XON - Set this bit to enable the transmitter to go on sending data. - 19 - 1 - read-write - - - FORCE_XOFF - Set this bit to stop the transmitter from sending data. - 20 - 1 - read-write - - - SEND_XON - Set this bit to send Xon char. It is cleared by hardware automatically. - 21 - 1 - read-write - - - SEND_XOFF - Set this bit to send Xoff char. It is cleared by hardware automatically. - 22 - 1 - read-write - - - - - SWFC_CONF1 - Software flow-control character configuration - 0x40 - 0x20 - 0x0000E000 - - - XON_THRESHOLD - When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1 it will send a Xon char. - 0 - 8 - read-write - - - XOFF_THRESHOLD - When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1 it will send a Xoff char. - 8 - 8 - read-write - - - - - TXBRK_CONF_SYNC - Tx Break character configuration - 0x44 - 0x20 - 0x0000000A - - - TX_BRK_NUM - This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1. - 0 - 8 - read-write - - - - - IDLE_CONF_SYNC - Frame-end idle configuration - 0x48 - 0x20 - 0x00040100 - - - RX_IDLE_THRHD - It will produce frame end signal when receiver takes more time to receive one byte data than this register value. - 0 - 10 - read-write - - - TX_IDLE_NUM - This register is used to configure the duration time between transfers. - 10 - 10 - read-write - - - - - RS485_CONF_SYNC - RS485 mode configuration - 0x4C - 0x20 - - - RS485_EN - Set this bit to choose the rs485 mode. - 0 - 1 - read-write - - - DL0_EN - Set this bit to delay the stop bit by 1 bit. - 1 - 1 - read-write - - - DL1_EN - Set this bit to delay the stop bit by 1 bit. - 2 - 1 - read-write - - - RS485TX_RX_EN - Set this bit to enable receiver could receive data when the transmitter is transmitting data in rs485 mode. - 3 - 1 - read-write - - - RS485RXBY_TX_EN - 1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy. - 4 - 1 - read-write - - - RS485_RX_DLY_NUM - This register is used to delay the receiver's internal data signal. - 5 - 1 - read-write - - - RS485_TX_DLY_NUM - This register is used to delay the transmitter's internal data signal. - 6 - 4 - read-write - - - - - AT_CMD_PRECNT_SYNC - Pre-sequence timing configuration - 0x50 - 0x20 - 0x00000901 - - - PRE_IDLE_NUM - This register is used to configure the idle duration time before the first at_cmd is received by receiver. - 0 - 16 - read-write - - - - - AT_CMD_POSTCNT_SYNC - Post-sequence timing configuration - 0x54 - 0x20 - 0x00000901 - - - POST_IDLE_NUM - This register is used to configure the duration time between the last at_cmd and the next data. - 0 - 16 - read-write - - - - - AT_CMD_GAPTOUT_SYNC - Timeout configuration - 0x58 - 0x20 - 0x0000000B - - - RX_GAP_TOUT - This register is used to configure the duration time between the at_cmd chars. - 0 - 16 - read-write - - - - - AT_CMD_CHAR_SYNC - AT escape sequence detection configuration - 0x5C - 0x20 - 0x0000032B - - - AT_CMD_CHAR - This register is used to configure the content of at_cmd char. - 0 - 8 - read-write - - - CHAR_NUM - This register is used to configure the num of continuous at_cmd chars received by receiver. - 8 - 8 - read-write - - - - - MEM_CONF - UART memory power configuration - 0x60 - 0x20 - - - MEM_FORCE_PD - Set this bit to force power down UART memory. - 25 - 1 - read-write - - - MEM_FORCE_PU - Set this bit to force power up UART memory. - 26 - 1 - read-write - - - - - TOUT_CONF_SYNC - UART threshold and allocation configuration - 0x64 - 0x20 - 0x00000028 - - - RX_TOUT_EN - This is the enble bit for uart receiver's timeout function. - 0 - 1 - read-write - - - RX_TOUT_FLOW_DIS - Set this bit to stop accumulating idle_cnt when hardware flow control works. - 1 - 1 - read-write - - - RX_TOUT_THRHD - This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1. - 2 - 10 - read-write - - - - - MEM_TX_STATUS - Tx-SRAM write and read offset address. - 0x68 - 0x20 - - - TX_SRAM_WADDR - This register stores the offset write address in Tx-SRAM. - 0 - 8 - read-only - - - TX_SRAM_RADDR - This register stores the offset read address in Tx-SRAM. - 9 - 8 - read-only - - - - - MEM_RX_STATUS - Rx-SRAM write and read offset address. - 0x6C - 0x20 - 0x00010080 - - - RX_SRAM_RADDR - This register stores the offset read address in RX-SRAM. - 0 - 8 - read-only - - - RX_SRAM_WADDR - This register stores the offset write address in Rx-SRAM. - 9 - 8 - read-only - - - - - FSM_STATUS - UART transmit and receive status. - 0x70 - 0x20 - - - ST_URX_OUT - This is the status register of receiver. - 0 - 4 - read-only - - - ST_UTX_OUT - This is the status register of transmitter. - 4 - 4 - read-only - - - - - POSPULSE - Autobaud high pulse register - 0x74 - 0x20 - 0x00000FFF - - - POSEDGE_MIN_CNT - This register stores the minimal input clock count between two positive edges. It is used in boudrate-detect process. - 0 - 12 - read-only - - - - - NEGPULSE - Autobaud low pulse register - 0x78 - 0x20 - 0x00000FFF - - - NEGEDGE_MIN_CNT - This register stores the minimal input clock count between two negative edges. It is used in boudrate-detect process. - 0 - 12 - read-only - - - - - LOWPULSE - Autobaud minimum low pulse duration register - 0x7C - 0x20 - 0x00000FFF - - - MIN_CNT - This register stores the value of the minimum duration time of the low level pulse. It is used in baud rate-detect process. - 0 - 12 - read-only - - - - - HIGHPULSE - Autobaud minimum high pulse duration register - 0x80 - 0x20 - 0x00000FFF - - - MIN_CNT - This register stores the value of the maxinum duration time for the high level pulse. It is used in baud rate-detect process. - 0 - 12 - read-only - - - - - RXD_CNT - Autobaud edge change count register - 0x84 - 0x20 - - - RXD_EDGE_CNT - This register stores the count of rxd edge change. It is used in baud rate-detect process. - 0 - 10 - read-only - - - - - CLK_CONF - UART core clock configuration - 0x88 - 0x20 - 0x03000000 - - - TX_SCLK_EN - Set this bit to enable UART Tx clock. - 24 - 1 - read-write - - - RX_SCLK_EN - Set this bit to enable UART Rx clock. - 25 - 1 - read-write - - - TX_RST_CORE - Write 1 then write 0 to this bit to reset UART Tx. - 26 - 1 - read-write - - - RX_RST_CORE - Write 1 then write 0 to this bit to reset UART Rx. - 27 - 1 - read-write - - - - - DATE - UART Version register - 0x8C - 0x20 - 0x02305050 - - - DATE - This is the version register. - 0 - 32 - read-write - - - - - AFIFO_STATUS - UART AFIFO Status - 0x90 - 0x20 - 0x0000000A - - - TX_AFIFO_FULL - Full signal of APB TX AFIFO. - 0 - 1 - read-only - - - TX_AFIFO_EMPTY - Empty signal of APB TX AFIFO. - 1 - 1 - read-only - - - RX_AFIFO_FULL - Full signal of APB RX AFIFO. - 2 - 1 - read-only - - - RX_AFIFO_EMPTY - Empty signal of APB RX AFIFO. - 3 - 1 - read-only - - - - - REG_UPDATE - UART Registers Configuration Update register - 0x98 - 0x20 - - - REG_UPDATE - Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done. - 0 - 1 - read-write - - - - - ID - UART ID register - 0x9C - 0x20 - 0x00000500 - - - ID - This register is used to configure the uart_id. - 0 - 32 - read-write - - - - - - - UART1 - UART (Universal Asynchronous Receiver-Transmitter) Controller 1 - 0x500CB000 - - UART1 - 32 - - - - UART2 - UART (Universal Asynchronous Receiver-Transmitter) Controller 2 - 0x500CC000 - - UART2 - 33 - - - - UART3 - UART (Universal Asynchronous Receiver-Transmitter) Controller 3 - 0x500CD000 - - UART3 - 34 - - - - UART4 - UART (Universal Asynchronous Receiver-Transmitter) Controller 4 - 0x500CE000 - - UART4 - 35 - - - - UHCI0 - Universal Host Controller Interface 0 - UHCI - 0x500DF000 - - 0x0 - 0x84 - registers - - - UHCI0 - 30 - - - - CONF0 - UHCI Configuration Register0 - 0x0 - 0x20 - 0x000006E0 - - - TX_RST - Write 1 then write 0 to this bit to reset decode state machine. - 0 - 1 - read-write - - - RX_RST - Write 1 then write 0 to this bit to reset encode state machine. - 1 - 1 - read-write - - - UART_SEL - Select which uart to connect with GDMA. - 2 - 3 - read-write - - - SEPER_EN - Set this bit to separate the data frame using a special char. - 5 - 1 - read-write - - - HEAD_EN - Set this bit to encode the data packet with a formatting header. - 6 - 1 - read-write - - - CRC_REC_EN - Set this bit to enable UHCI to receive the 16 bit CRC. - 7 - 1 - read-write - - - UART_IDLE_EOF_EN - If this bit is set to 1 UHCI will end the payload receiving process when UART has been in idle state. - 8 - 1 - read-write - - - LEN_EOF_EN - If this bit is set to 1 UHCI decoder receiving payload data is end when the receiving byte count has reached the specified value. The value is payload length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0 UHCI decoder receiving payload data is end when 0xc0 is received. - 9 - 1 - read-write - - - ENCODE_CRC_EN - Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to end of the payload. - 10 - 1 - read-write - - - CLK_EN - 1'b1: Force clock on for register. 1'b0: Support clock only when application writes registers. - 11 - 1 - read-write - - - UART_RX_BRK_EOF_EN - If this bit is set to 1 UHCI will end payload receive process when NULL frame is received by UART. - 12 - 1 - read-write - - - - - INT_RAW - UHCI Interrupt Raw Register - 0x4 - 0x20 - - - RX_START_INT_RAW - Indicates the raw interrupt of UHCI_RX_START_INT. Interrupt will be triggered when delimiter is sent successfully. - 0 - 1 - read-write - - - TX_START_INT_RAW - Indicates the raw interrupt of UHCI_TX_START_INT. Interrupt will be triggered when DMA detects delimiter. - 1 - 1 - read-write - - - RX_HUNG_INT_RAW - Indicates the raw interrupt of UHCI_RX_HUNG_INT. Interrupt will be triggered when the required time of DMA receiving data exceeds the configuration value. - 2 - 1 - read-write - - - TX_HUNG_INT_RAW - Indicates the raw interrupt of UHCI_TX_HUNG_INT. Interrupt will be triggered when the required time of DMA reading RAM data exceeds the configuration value. - 3 - 1 - read-write - - - SEND_S_REG_Q_INT_RAW - Indicates the raw interrupt of UHCI_SEND_S_REG_Q_INT. Interrupt will be triggered when UHCI sends short packet successfully with single_send mode. - 4 - 1 - read-write - - - SEND_A_REG_Q_INT_RAW - Indicates the raw interrupt of UHCI_SEND_A_REG_Q_INT. Interrupt will be triggered when UHCI sends short packet successfully with always_send mode. - 5 - 1 - read-write - - - OUT_EOF_INT_RAW - Indicates the raw interrupt of UHCI_OUT_EOF_INT. Interrupt will be triggered when there are errors in EOF. - 6 - 1 - read-write - - - APP_CTRL0_INT_RAW - Indicates the raw interrupt of UHCI_APP_CTRL0_INT. Interrupt will be triggered when UHCI_APP_CTRL0_IN_SET is set to 1. - 7 - 1 - read-write - - - APP_CTRL1_INT_RAW - Indicates the raw interrupt of UHCI_APP_CTRL1_INT. Interrupt will be triggered when UHCI_APP_CTRL1_IN_SET is set to 1. - 8 - 1 - read-write - - - - - INT_ST - UHCI Interrupt Status Register - 0x8 - 0x20 - - - RX_START_INT_ST - Indicates the interrupt status of UHCI_RX_START_INT. - 0 - 1 - read-only - - - TX_START_INT_ST - Indicates the interrupt status of UHCI_TX_START_INT. - 1 - 1 - read-only - - - RX_HUNG_INT_ST - Indicates the interrupt status of UHCI_RX_HUNG_INT. - 2 - 1 - read-only - - - TX_HUNG_INT_ST - Indicates the interrupt status of UHCI_TX_HUNG_INT. - 3 - 1 - read-only - - - SEND_S_REG_Q_INT_ST - Indicates the interrupt status of UHCI_SEND_S_REG_Q_INT. - 4 - 1 - read-only - - - SEND_A_REG_Q_INT_ST - Indicates the interrupt status of UHCI_SEND_A_REG_Q_INT. - 5 - 1 - read-only - - - OUTLINK_EOF_ERR_INT_ST - Indicates the interrupt status of UHCI_OUT_EOF_INT. - 6 - 1 - read-only - - - APP_CTRL0_INT_ST - Indicates the interrupt status of UHCI_APP_CTRL0_INT. - 7 - 1 - read-only - - - APP_CTRL1_INT_ST - Indicates the interrupt status of UHCI_APP_CTRL1_INT. - 8 - 1 - read-only - - - - - INT_ENA - UHCI Interrupt Enable Register - 0xC - 0x20 - - - RX_START_INT_ENA - Set this bit to enable the interrupt of UHCI_RX_START_INT. - 0 - 1 - read-write - - - TX_START_INT_ENA - Set this bit to enable the interrupt of UHCI_TX_START_INT. - 1 - 1 - read-write - - - RX_HUNG_INT_ENA - Set this bit to enable the interrupt of UHCI_RX_HUNG_INT. - 2 - 1 - read-write - - - TX_HUNG_INT_ENA - Set this bit to enable the interrupt of UHCI_TX_HUNG_INT. - 3 - 1 - read-write - - - SEND_S_REG_Q_INT_ENA - Set this bit to enable the interrupt of UHCI_SEND_S_REG_Q_INT. - 4 - 1 - read-write - - - SEND_A_REG_Q_INT_ENA - Set this bit to enable the interrupt of UHCI_SEND_A_REG_Q_INT. - 5 - 1 - read-write - - - OUTLINK_EOF_ERR_INT_ENA - Set this bit to enable the interrupt of UHCI_OUT_EOF_INT. - 6 - 1 - read-write - - - APP_CTRL0_INT_ENA - Set this bit to enable the interrupt of UHCI_APP_CTRL0_INT. - 7 - 1 - read-write - - - APP_CTRL1_INT_ENA - Set this bit to enable the interrupt of UHCI_APP_CTRL1_INT. - 8 - 1 - read-write - - - - - INT_CLR - UHCI Interrupt Clear Register - 0x10 - 0x20 - - - RX_START_INT_CLR - Set this bit to clear the raw interrupt of UHCI_RX_START_INT. - 0 - 1 - write-only - - - TX_START_INT_CLR - Set this bit to clear the raw interrupt of UHCI_TX_START_INT. - 1 - 1 - write-only - - - RX_HUNG_INT_CLR - Set this bit to clear the raw interrupt of UHCI_RX_HUNG_INT. - 2 - 1 - write-only - - - TX_HUNG_INT_CLR - Set this bit to clear the raw interrupt of UHCI_TX_HUNG_INT. - 3 - 1 - write-only - - - SEND_S_REG_Q_INT_CLR - Set this bit to clear the raw interrupt of UHCI_SEND_S_REG_Q_INT. - 4 - 1 - write-only - - - SEND_A_REG_Q_INT_CLR - Set this bit to clear the raw interrupt of UHCI_SEND_A_REG_Q_INT. - 5 - 1 - write-only - - - OUTLINK_EOF_ERR_INT_CLR - Set this bit to clear the raw interrupt of UHCI_OUT_EOF_INT. - 6 - 1 - write-only - - - APP_CTRL0_INT_CLR - Set this bit to clear the raw interrupt of UHCI_APP_CTRL0_INT. - 7 - 1 - write-only - - - APP_CTRL1_INT_CLR - Set this bit to clear the raw interrupt of UHCI_APP_CTRL1_INT. - 8 - 1 - write-only - - - - - CONF1 - UHCI Configuration Register1 - 0x14 - 0x20 - 0x00000033 - - - CHECK_SUM_EN - Set this bit to enable head checksum check when receiving. - 0 - 1 - read-write - - - CHECK_SEQ_EN - Set this bit to enable sequence number check when receiving. - 1 - 1 - read-write - - - CRC_DISABLE - Set this bit to support CRC calculation, and data integrity check bit should 1. - 2 - 1 - read-write - - - SAVE_HEAD - Set this bit to save data packet head when UHCI receive data. - 3 - 1 - read-write - - - TX_CHECK_SUM_RE - Set this bit to encode data packet with checksum. - 4 - 1 - read-write - - - TX_ACK_NUM_RE - Set this bit to encode data packet with ACK when reliable data packet is ready. - 5 - 1 - read-write - - - WAIT_SW_START - Set this bit to enable UHCI encoder transfer to ST_SW_WAIT status. - 7 - 1 - read-write - - - SW_START - Set this bit to transmit data packet if UCHI_ENCODE_STATE is ST_SW_WAIT. - 8 - 1 - write-only - - - - - STATE0 - UHCI Receive Status Register - 0x18 - 0x20 - - - RX_ERR_CAUSE - Indicates the error types when DMA receives the error frame. 3'b001: UHCI packet checksum error. 3'b010: UHCI packet sequence number error. 3'b011: UHCI packet CRC bit error. 3'b100: find 0xC0, but received packet is uncompleted. 3'b101: 0xC0 is not found, but received packet is completed. 3'b110: CRC check error. - 0 - 3 - read-only - - - DECODE_STATE - Indicates UHCI decoder status. - 3 - 3 - read-only - - - - - STATE1 - UHCI Transmit Status Register - 0x1C - 0x20 - - - ENCODE_STATE - Indicates UHCI encoder status. - 0 - 3 - read-only - - - - - ESCAPE_CONF - UHCI Escapes Configuration Register0 - 0x20 - 0x20 - 0x00000033 - - - TX_C0_ESC_EN - Set this bit to enable resolve char 0xC0 when DMA receiving data. - 0 - 1 - read-write - - - TX_DB_ESC_EN - Set this bit to enable resolve char 0xDB when DMA receiving data. - 1 - 1 - read-write - - - TX_11_ESC_EN - Set this bit to enable resolve flow control char 0x11 when DMA receiving data. - 2 - 1 - read-write - - - TX_13_ESC_EN - Set this bit to enable resolve flow control char 0x13 when DMA receiving data. - 3 - 1 - read-write - - - RX_C0_ESC_EN - Set this bit to enable replacing 0xC0 with special char when DMA receiving data. - 4 - 1 - read-write - - - RX_DB_ESC_EN - Set this bit to enable replacing 0xDB with special char when DMA receiving data. - 5 - 1 - read-write - - - RX_11_ESC_EN - Set this bit to enable replacing 0x11 with special char when DMA receiving data. - 6 - 1 - read-write - - - RX_13_ESC_EN - Set this bit to enable replacing 0x13 with special char when DMA receiving data. - 7 - 1 - read-write - - - - - HUNG_CONF - UHCI Hung Configuration Register0 - 0x24 - 0x20 - 0x00810810 - - - TXFIFO_TIMEOUT - Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for timeout when receiving data. - 0 - 8 - read-write - - - TXFIFO_TIMEOUT_SHIFT - Configures the maximum counter value. - 8 - 3 - read-write - - - TXFIFO_TIMEOUT_ENA - Set this bit to enable TX FIFO timeout when receiving. - 11 - 1 - read-write - - - RXFIFO_TIMEOUT - Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for timeout when reading RAM data. - 12 - 8 - read-write - - - RXFIFO_TIMEOUT_SHIFT - Configures the maximum counter value. - 20 - 3 - read-write - - - RXFIFO_TIMEOUT_ENA - Set this bit to enable TX FIFO timeout when DMA sending data. - 23 - 1 - read-write - - - - - ACK_NUM - UHCI Ack Value Configuration Register0 - 0x28 - 0x20 - - - ACK_NUM - Indicates the ACK number during software flow control. - 0 - 3 - read-write - - - LOAD - Set this bit to load the ACK value of UHCI_ACK_NUM. - 3 - 1 - write-only - - - - - RX_HEAD - UHCI Head Register - 0x2C - 0x20 - - - RX_HEAD - Stores the head of received packet. - 0 - 32 - read-only - - - - - QUICK_SENT - UCHI Quick send Register - 0x30 - 0x20 - - - SINGLE_SEND_NUM - Configures single_send mode. - 0 - 3 - read-write - - - SINGLE_SEND_EN - Set this bit to enable sending short packet with single_send mode. - 3 - 1 - write-only - - - ALWAYS_SEND_NUM - Configures always_send mode. - 4 - 3 - read-write - - - ALWAYS_SEND_EN - Set this bit to enable sending short packet with always_send mode. - 7 - 1 - read-write - - - - - REG_Q0_WORD0 - UHCI Q0_WORD0 Quick Send Register - 0x34 - 0x20 - - - SEND_Q0_WORD0 - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. - 0 - 32 - read-write - - - - - REG_Q0_WORD1 - UHCI Q0_WORD1 Quick Send Register - 0x38 - 0x20 - - - SEND_Q0_WORD1 - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. - 0 - 32 - read-write - - - - - REG_Q1_WORD0 - UHCI Q1_WORD0 Quick Send Register - 0x3C - 0x20 - - - SEND_Q1_WORD0 - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. - 0 - 32 - read-write - - - - - REG_Q1_WORD1 - UHCI Q1_WORD1 Quick Send Register - 0x40 - 0x20 - - - SEND_Q1_WORD1 - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. - 0 - 32 - read-write - - - - - REG_Q2_WORD0 - UHCI Q2_WORD0 Quick Send Register - 0x44 - 0x20 - - - SEND_Q2_WORD0 - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. - 0 - 32 - read-write - - - - - REG_Q2_WORD1 - UHCI Q2_WORD1 Quick Send Register - 0x48 - 0x20 - - - SEND_Q2_WORD1 - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. - 0 - 32 - read-write - - - - - REG_Q3_WORD0 - UHCI Q3_WORD0 Quick Send Register - 0x4C - 0x20 - - - SEND_Q3_WORD0 - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. - 0 - 32 - read-write - - - - - REG_Q3_WORD1 - UHCI Q3_WORD1 Quick Send Register - 0x50 - 0x20 - - - SEND_Q3_WORD1 - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. - 0 - 32 - read-write - - - - - REG_Q4_WORD0 - UHCI Q4_WORD0 Quick Send Register - 0x54 - 0x20 - - - SEND_Q4_WORD0 - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. - 0 - 32 - read-write - - - - - REG_Q4_WORD1 - UHCI Q4_WORD1 Quick Send Register - 0x58 - 0x20 - - - SEND_Q4_WORD1 - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. - 0 - 32 - read-write - - - - - REG_Q5_WORD0 - UHCI Q5_WORD0 Quick Send Register - 0x5C - 0x20 - - - SEND_Q5_WORD0 - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. - 0 - 32 - read-write - - - - - REG_Q5_WORD1 - UHCI Q5_WORD1 Quick Send Register - 0x60 - 0x20 - - - SEND_Q5_WORD1 - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. - 0 - 32 - read-write - - - - - REG_Q6_WORD0 - UHCI Q6_WORD0 Quick Send Register - 0x64 - 0x20 - - - SEND_Q6_WORD0 - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. - 0 - 32 - read-write - - - - - REG_Q6_WORD1 - UHCI Q6_WORD1 Quick Send Register - 0x68 - 0x20 - - - SEND_Q6_WORD1 - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. - 0 - 32 - read-write - - - - - ESC_CONF0 - UHCI Escapes Sequence Configuration Register0 - 0x6C - 0x20 - 0x00DCDBC0 - - - SEPER_CHAR - Configures the delimiter for encoding, default value is 0xC0. - 0 - 8 - read-write - - - SEPER_ESC_CHAR0 - Configures the first char of SLIP escape character, default value is 0xDB. - 8 - 8 - read-write - - - SEPER_ESC_CHAR1 - Configures the second char of SLIP escape character, default value is 0xDC. - 16 - 8 - read-write - - - - - ESC_CONF1 - UHCI Escapes Sequence Configuration Register1 - 0x70 - 0x20 - 0x00DDDBDB - - - ESC_SEQ0 - Configures the char needing encoding, which is 0xDB as flow control char by default. - 0 - 8 - read-write - - - ESC_SEQ0_CHAR0 - Configures the first char of SLIP escape character, default value is 0xDB. - 8 - 8 - read-write - - - ESC_SEQ0_CHAR1 - Configures the second char of SLIP escape character, default value is 0xDD. - 16 - 8 - read-write - - - - - ESC_CONF2 - UHCI Escapes Sequence Configuration Register2 - 0x74 - 0x20 - 0x00DEDB11 - - - ESC_SEQ1 - Configures the char needing encoding, which is 0x11 as flow control char by default. - 0 - 8 - read-write - - - ESC_SEQ1_CHAR0 - Configures the first char of SLIP escape character, default value is 0xDB. - 8 - 8 - read-write - - - ESC_SEQ1_CHAR1 - Configures the second char of SLIP escape character, default value is 0xDE. - 16 - 8 - read-write - - - - - ESC_CONF3 - UHCI Escapes Sequence Configuration Register3 - 0x78 - 0x20 - 0x00DFDB13 - - - ESC_SEQ2 - Configures the char needing encoding, which is 0x13 as flow control char by default. - 0 - 8 - read-write - - - ESC_SEQ2_CHAR0 - Configures the first char of SLIP escape character, default value is 0xDB. - 8 - 8 - read-write - - - ESC_SEQ2_CHAR1 - Configures the second char of SLIP escape character, default value is 0xDF. - 16 - 8 - read-write - - - - - PKT_THRES - UCHI Packet Length Configuration Register - 0x7C - 0x20 - 0x00000080 - - - PKT_THRS - Configures the data packet's maximum length when UHCI_HEAD_EN is 0. - 0 - 13 - read-write - - - - - DATE - UHCI Version Register - 0x80 - 0x20 - 0x02201100 - - - DATE - Configures version. - 0 - 32 - read-write - - - - - - - USB_DEVICE - Full-speed USB Serial/JTAG Controller - USB_DEVICE - 0x500D2000 - - 0x0 - 0x8C - registers - - - USB_DEVICE - 22 - - - - EP1 - FIFO access for the CDC-ACM data IN and OUT endpoints. - 0x0 - 0x20 - - - USB_SERIAL_JTAG_RDWR_BYTE - Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is received, then read data from UART Rx FIFO. - 0 - 8 - read-only - - - - - EP1_CONF - Configuration and control registers for the CDC-ACM FIFOs. - 0x4 - 0x20 - 0x00000002 - - - USB_SERIAL_JTAG_WR_DONE - Set this bit to indicate writing byte data to UART Tx FIFO is done. - 0 - 1 - write-only - - - USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE - 1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by USB Host. - 1 - 1 - read-only - - - USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL - 1'b1: Indicate there is data in UART Rx FIFO. - 2 - 1 - read-only - - - - - INT_RAW - Interrupt raw status register. - 0x8 - 0x20 - 0x00000008 - - - USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW - The raw interrupt bit turns to high level when flush cmd is received for IN endpoint 2 of JTAG. - 0 - 1 - read-write - - - USB_SERIAL_JTAG_SOF_INT_RAW - The raw interrupt bit turns to high level when SOF frame is received. - 1 - 1 - read-write - - - USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW - The raw interrupt bit turns to high level when Serial Port OUT Endpoint received one packet. - 2 - 1 - read-write - - - USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW - The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty. - 3 - 1 - read-write - - - USB_SERIAL_JTAG_PID_ERR_INT_RAW - The raw interrupt bit turns to high level when pid error is detected. - 4 - 1 - read-write - - - USB_SERIAL_JTAG_CRC5_ERR_INT_RAW - The raw interrupt bit turns to high level when CRC5 error is detected. - 5 - 1 - read-write - - - USB_SERIAL_JTAG_CRC16_ERR_INT_RAW - The raw interrupt bit turns to high level when CRC16 error is detected. - 6 - 1 - read-write - - - USB_SERIAL_JTAG_STUFF_ERR_INT_RAW - The raw interrupt bit turns to high level when stuff error is detected. - 7 - 1 - read-write - - - USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW - The raw interrupt bit turns to high level when IN token for IN endpoint 1 is received. - 8 - 1 - read-write - - - USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW - The raw interrupt bit turns to high level when usb bus reset is detected. - 9 - 1 - read-write - - - USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW - The raw interrupt bit turns to high level when OUT endpoint 1 received packet with zero palyload. - 10 - 1 - read-write - - - USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW - The raw interrupt bit turns to high level when OUT endpoint 2 received packet with zero palyload. - 11 - 1 - read-write - - - USB_SERIAL_JTAG_RTS_CHG_INT_RAW - The raw interrupt bit turns to high level when level of RTS from usb serial channel is changed. - 12 - 1 - read-write - - - USB_SERIAL_JTAG_DTR_CHG_INT_RAW - The raw interrupt bit turns to high level when level of DTR from usb serial channel is changed. - 13 - 1 - read-write - - - USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW - The raw interrupt bit turns to high level when level of GET LINE CODING request is received. - 14 - 1 - read-write - - - USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW - The raw interrupt bit turns to high level when level of SET LINE CODING request is received. - 15 - 1 - read-write - - - - - INT_ST - Interrupt status register. - 0xC - 0x20 - - - USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST - The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. - 0 - 1 - read-only - - - USB_SERIAL_JTAG_SOF_INT_ST - The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt. - 1 - 1 - read-only - - - USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST - The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. - 2 - 1 - read-only - - - USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST - The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. - 3 - 1 - read-only - - - USB_SERIAL_JTAG_PID_ERR_INT_ST - The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt. - 4 - 1 - read-only - - - USB_SERIAL_JTAG_CRC5_ERR_INT_ST - The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt. - 5 - 1 - read-only - - - USB_SERIAL_JTAG_CRC16_ERR_INT_ST - The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt. - 6 - 1 - read-only - - - USB_SERIAL_JTAG_STUFF_ERR_INT_ST - The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt. - 7 - 1 - read-only - - - USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST - The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt. - 8 - 1 - read-only - - - USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST - The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt. - 9 - 1 - read-only - - - USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST - The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. - 10 - 1 - read-only - - - USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST - The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. - 11 - 1 - read-only - - - USB_SERIAL_JTAG_RTS_CHG_INT_ST - The raw interrupt status bit for the USB_DEVICE_RTS_CHG_INT interrupt. - 12 - 1 - read-only - - - USB_SERIAL_JTAG_DTR_CHG_INT_ST - The raw interrupt status bit for the USB_DEVICE_DTR_CHG_INT interrupt. - 13 - 1 - read-only - - - USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST - The raw interrupt status bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt. - 14 - 1 - read-only - - - USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST - The raw interrupt status bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt. - 15 - 1 - read-only - - - - - INT_ENA - Interrupt enable status register. - 0x10 - 0x20 - - - USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA - The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. - 0 - 1 - read-write - - - USB_SERIAL_JTAG_SOF_INT_ENA - The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt. - 1 - 1 - read-write - - - USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA - The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. - 2 - 1 - read-write - - - USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA - The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. - 3 - 1 - read-write - - - USB_SERIAL_JTAG_PID_ERR_INT_ENA - The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt. - 4 - 1 - read-write - - - USB_SERIAL_JTAG_CRC5_ERR_INT_ENA - The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt. - 5 - 1 - read-write - - - USB_SERIAL_JTAG_CRC16_ERR_INT_ENA - The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt. - 6 - 1 - read-write - - - USB_SERIAL_JTAG_STUFF_ERR_INT_ENA - The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt. - 7 - 1 - read-write - - - USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA - The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt. - 8 - 1 - read-write - - - USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA - The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt. - 9 - 1 - read-write - - - USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA - The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. - 10 - 1 - read-write - - - USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA - The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. - 11 - 1 - read-write - - - USB_SERIAL_JTAG_RTS_CHG_INT_ENA - The interrupt enable bit for the USB_DEVICE_RTS_CHG_INT interrupt. - 12 - 1 - read-write - - - USB_SERIAL_JTAG_DTR_CHG_INT_ENA - The interrupt enable bit for the USB_DEVICE_DTR_CHG_INT interrupt. - 13 - 1 - read-write - - - USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA - The interrupt enable bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt. - 14 - 1 - read-write - - - USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA - The interrupt enable bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt. - 15 - 1 - read-write - - - - - INT_CLR - Interrupt clear status register. - 0x14 - 0x20 - - - USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR - Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. - 0 - 1 - write-only - - - USB_SERIAL_JTAG_SOF_INT_CLR - Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt. - 1 - 1 - write-only - - - USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR - Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. - 2 - 1 - write-only - - - USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR - Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. - 3 - 1 - write-only - - - USB_SERIAL_JTAG_PID_ERR_INT_CLR - Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt. - 4 - 1 - write-only - - - USB_SERIAL_JTAG_CRC5_ERR_INT_CLR - Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt. - 5 - 1 - write-only - - - USB_SERIAL_JTAG_CRC16_ERR_INT_CLR - Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt. - 6 - 1 - write-only - - - USB_SERIAL_JTAG_STUFF_ERR_INT_CLR - Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt. - 7 - 1 - write-only - - - USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR - Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt. - 8 - 1 - write-only - - - USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR - Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt. - 9 - 1 - write-only - - - USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR - Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. - 10 - 1 - write-only - - - USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR - Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. - 11 - 1 - write-only - - - USB_SERIAL_JTAG_RTS_CHG_INT_CLR - Set this bit to clear the USB_DEVICE_RTS_CHG_INT interrupt. - 12 - 1 - write-only - - - USB_SERIAL_JTAG_DTR_CHG_INT_CLR - Set this bit to clear the USB_DEVICE_DTR_CHG_INT interrupt. - 13 - 1 - write-only - - - USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR - Set this bit to clear the USB_DEVICE_GET_LINE_CODE_INT interrupt. - 14 - 1 - write-only - - - USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR - Set this bit to clear the USB_DEVICE_SET_LINE_CODE_INT interrupt. - 15 - 1 - write-only - - - - - CONF0 - PHY hardware configuration. - 0x18 - 0x20 - 0x00004200 - - - USB_SERIAL_JTAG_PHY_SEL - Select internal/external PHY - 0 - 1 - read-write - - - USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE - Enable software control USB D+ D- exchange - 1 - 1 - read-write - - - USB_SERIAL_JTAG_EXCHG_PINS - USB D+ D- exchange - 2 - 1 - read-write - - - USB_SERIAL_JTAG_VREFH - Control single-end input high threshold,1.76V to 2V, step 80mV - 3 - 2 - read-write - - - USB_SERIAL_JTAG_VREFL - Control single-end input low threshold,0.8V to 1.04V, step 80mV - 5 - 2 - read-write - - - USB_SERIAL_JTAG_VREF_OVERRIDE - Enable software control input threshold - 7 - 1 - read-write - - - USB_SERIAL_JTAG_PAD_PULL_OVERRIDE - Enable software control USB D+ D- pullup pulldown - 8 - 1 - read-write - - - USB_SERIAL_JTAG_DP_PULLUP - Control USB D+ pull up. - 9 - 1 - read-write - - - USB_SERIAL_JTAG_DP_PULLDOWN - Control USB D+ pull down. - 10 - 1 - read-write - - - USB_SERIAL_JTAG_DM_PULLUP - Control USB D- pull up. - 11 - 1 - read-write - - - USB_SERIAL_JTAG_DM_PULLDOWN - Control USB D- pull down. - 12 - 1 - read-write - - - USB_SERIAL_JTAG_PULLUP_VALUE - Control pull up value. - 13 - 1 - read-write - - - USB_SERIAL_JTAG_USB_PAD_ENABLE - Enable USB pad function. - 14 - 1 - read-write - - - USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN - Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input through GPIO Matrix. - 15 - 1 - read-write - - - - - TEST - Registers used for debugging the PHY. - 0x1C - 0x20 - 0x00000030 - - - USB_SERIAL_JTAG_TEST_ENABLE - Enable test of the USB pad - 0 - 1 - read-write - - - USB_SERIAL_JTAG_TEST_USB_OE - USB pad oen in test - 1 - 1 - read-write - - - USB_SERIAL_JTAG_TEST_TX_DP - USB D+ tx value in test - 2 - 1 - read-write - - - USB_SERIAL_JTAG_TEST_TX_DM - USB D- tx value in test - 3 - 1 - read-write - - - USB_SERIAL_JTAG_TEST_RX_RCV - USB RCV value in test - 4 - 1 - read-only - - - USB_SERIAL_JTAG_TEST_RX_DP - USB D+ rx value in test - 5 - 1 - read-only - - - USB_SERIAL_JTAG_TEST_RX_DM - USB D- rx value in test - 6 - 1 - read-only - - - - - JFIFO_ST - JTAG FIFO status and control registers. - 0x20 - 0x20 - 0x00000044 - - - USB_SERIAL_JTAG_IN_FIFO_CNT - JTAT in fifo counter. - 0 - 2 - read-only - - - USB_SERIAL_JTAG_IN_FIFO_EMPTY - 1: JTAG in fifo is empty. - 2 - 1 - read-only - - - USB_SERIAL_JTAG_IN_FIFO_FULL - 1: JTAG in fifo is full. - 3 - 1 - read-only - - - USB_SERIAL_JTAG_OUT_FIFO_CNT - JTAT out fifo counter. - 4 - 2 - read-only - - - USB_SERIAL_JTAG_OUT_FIFO_EMPTY - 1: JTAG out fifo is empty. - 6 - 1 - read-only - - - USB_SERIAL_JTAG_OUT_FIFO_FULL - 1: JTAG out fifo is full. - 7 - 1 - read-only - - - USB_SERIAL_JTAG_IN_FIFO_RESET - Write 1 to reset JTAG in fifo. - 8 - 1 - read-write - - - USB_SERIAL_JTAG_OUT_FIFO_RESET - Write 1 to reset JTAG out fifo. - 9 - 1 - read-write - - - - - FRAM_NUM - Last received SOF frame index register. - 0x24 - 0x20 - - - USB_SERIAL_JTAG_SOF_FRAME_INDEX - Frame index of received SOF frame. - 0 - 11 - read-only - - - - - IN_EP0_ST - Control IN endpoint status information. - 0x28 - 0x20 - 0x00000001 - - - USB_SERIAL_JTAG_IN_EP0_STATE - State of IN Endpoint 0. - 0 - 2 - read-only - - - USB_SERIAL_JTAG_IN_EP0_WR_ADDR - Write data address of IN endpoint 0. - 2 - 7 - read-only - - - USB_SERIAL_JTAG_IN_EP0_RD_ADDR - Read data address of IN endpoint 0. - 9 - 7 - read-only - - - - - IN_EP1_ST - CDC-ACM IN endpoint status information. - 0x2C - 0x20 - 0x00000001 - - - USB_SERIAL_JTAG_IN_EP1_STATE - State of IN Endpoint 1. - 0 - 2 - read-only - - - USB_SERIAL_JTAG_IN_EP1_WR_ADDR - Write data address of IN endpoint 1. - 2 - 7 - read-only - - - USB_SERIAL_JTAG_IN_EP1_RD_ADDR - Read data address of IN endpoint 1. - 9 - 7 - read-only - - - - - IN_EP2_ST - CDC-ACM interrupt IN endpoint status information. - 0x30 - 0x20 - 0x00000001 - - - USB_SERIAL_JTAG_IN_EP2_STATE - State of IN Endpoint 2. - 0 - 2 - read-only - - - USB_SERIAL_JTAG_IN_EP2_WR_ADDR - Write data address of IN endpoint 2. - 2 - 7 - read-only - - - USB_SERIAL_JTAG_IN_EP2_RD_ADDR - Read data address of IN endpoint 2. - 9 - 7 - read-only - - - - - IN_EP3_ST - JTAG IN endpoint status information. - 0x34 - 0x20 - 0x00000001 - - - USB_SERIAL_JTAG_IN_EP3_STATE - State of IN Endpoint 3. - 0 - 2 - read-only - - - USB_SERIAL_JTAG_IN_EP3_WR_ADDR - Write data address of IN endpoint 3. - 2 - 7 - read-only - - - USB_SERIAL_JTAG_IN_EP3_RD_ADDR - Read data address of IN endpoint 3. - 9 - 7 - read-only - - - - - OUT_EP0_ST - Control OUT endpoint status information. - 0x38 - 0x20 - - - USB_SERIAL_JTAG_OUT_EP0_STATE - State of OUT Endpoint 0. - 0 - 2 - read-only - - - USB_SERIAL_JTAG_OUT_EP0_WR_ADDR - Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0. - 2 - 7 - read-only - - - USB_SERIAL_JTAG_OUT_EP0_RD_ADDR - Read data address of OUT endpoint 0. - 9 - 7 - read-only - - - - - OUT_EP1_ST - CDC-ACM OUT endpoint status information. - 0x3C - 0x20 - - - USB_SERIAL_JTAG_OUT_EP1_STATE - State of OUT Endpoint 1. - 0 - 2 - read-only - - - USB_SERIAL_JTAG_OUT_EP1_WR_ADDR - Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1. - 2 - 7 - read-only - - - USB_SERIAL_JTAG_OUT_EP1_RD_ADDR - Read data address of OUT endpoint 1. - 9 - 7 - read-only - - - USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT - Data count in OUT endpoint 1 when one packet is received. - 16 - 7 - read-only - - - - - OUT_EP2_ST - JTAG OUT endpoint status information. - 0x40 - 0x20 - - - USB_SERIAL_JTAG_OUT_EP2_STATE - State of OUT Endpoint 2. - 0 - 2 - read-only - - - USB_SERIAL_JTAG_OUT_EP2_WR_ADDR - Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2. - 2 - 7 - read-only - - - USB_SERIAL_JTAG_OUT_EP2_RD_ADDR - Read data address of OUT endpoint 2. - 9 - 7 - read-only - - - - - MISC_CONF - Clock enable control - 0x44 - 0x20 - - - USB_SERIAL_JTAG_CLK_EN - 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers. - 0 - 1 - read-write - - - - - MEM_CONF - Memory power control - 0x48 - 0x20 - 0x00000002 - - - USB_SERIAL_JTAG_USB_MEM_PD - 1: power down usb memory. - 0 - 1 - read-write - - - USB_SERIAL_JTAG_USB_MEM_CLK_EN - 1: Force clock on for usb memory. - 1 - 1 - read-write - - - - - CHIP_RST - CDC-ACM chip reset control. - 0x4C - 0x20 - - - USB_SERIAL_JTAG_RTS - 1: Chip reset is detected from usb serial channel. Software write 1 to clear it. - 0 - 1 - read-only - - - USB_SERIAL_JTAG_DTR - 1: Chip reset is detected from usb jtag channel. Software write 1 to clear it. - 1 - 1 - read-only - - - USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS - Set this bit to disable chip reset from usb serial channel to reset chip. - 2 - 1 - read-write - - - - - SET_LINE_CODE_W0 - W0 of SET_LINE_CODING command. - 0x50 - 0x20 - - - USB_SERIAL_JTAG_DW_DTE_RATE - The value of dwDTERate set by host through SET_LINE_CODING command. - 0 - 32 - read-only - - - - - SET_LINE_CODE_W1 - W1 of SET_LINE_CODING command. - 0x54 - 0x20 - - - USB_SERIAL_JTAG_BCHAR_FORMAT - The value of bCharFormat set by host through SET_LINE_CODING command. - 0 - 8 - read-only - - - USB_SERIAL_JTAG_BPARITY_TYPE - The value of bParityTpye set by host through SET_LINE_CODING command. - 8 - 8 - read-only - - - USB_SERIAL_JTAG_BDATA_BITS - The value of bDataBits set by host through SET_LINE_CODING command. - 16 - 8 - read-only - - - - - GET_LINE_CODE_W0 - W0 of GET_LINE_CODING command. - 0x58 - 0x20 - - - USB_SERIAL_JTAG_GET_DW_DTE_RATE - The value of dwDTERate set by software which is requested by GET_LINE_CODING command. - 0 - 32 - read-write - - - - - GET_LINE_CODE_W1 - W1 of GET_LINE_CODING command. - 0x5C - 0x20 - - - USB_SERIAL_JTAG_GET_BDATA_BITS - The value of bCharFormat set by software which is requested by GET_LINE_CODING command. - 0 - 8 - read-write - - - USB_SERIAL_JTAG_GET_BPARITY_TYPE - The value of bParityTpye set by software which is requested by GET_LINE_CODING command. - 8 - 8 - read-write - - - USB_SERIAL_JTAG_GET_BCHAR_FORMAT - The value of bDataBits set by software which is requested by GET_LINE_CODING command. - 16 - 8 - read-write - - - - - CONFIG_UPDATE - Configuration registers' value update - 0x60 - 0x20 - - - USB_SERIAL_JTAG_CONFIG_UPDATE - Write 1 to this register would update the value of configure registers from APB clock domain to 48MHz clock domain. - 0 - 1 - write-only - - - - - SER_AFIFO_CONFIG - Serial AFIFO configure register - 0x64 - 0x20 - 0x00000010 - - - USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR - Write 1 to reset CDC_ACM IN async FIFO write clock domain. - 0 - 1 - read-write - - - USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD - Write 1 to reset CDC_ACM IN async FIFO read clock domain. - 1 - 1 - read-write - - - USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR - Write 1 to reset CDC_ACM OUT async FIFO write clock domain. - 2 - 1 - read-write - - - USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD - Write 1 to reset CDC_ACM OUT async FIFO read clock domain. - 3 - 1 - read-write - - - USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY - CDC_ACM OUTOUT async FIFO empty signal in read clock domain. - 4 - 1 - read-only - - - USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL - CDC_ACM OUT IN async FIFO empty signal in write clock domain. - 5 - 1 - read-only - - - - - BUS_RESET_ST - USB Bus reset status register - 0x68 - 0x20 - 0x00000001 - - - USB_SERIAL_JTAG_USB_BUS_RESET_ST - USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset status. 1: USB bus reset is released. - 0 - 1 - read-only - - - - - ECO_LOW_48 - Reserved. - 0x6C - 0x20 - - - USB_SERIAL_JTAG_RND_ECO_LOW_48 - Reserved. - 0 - 32 - read-write - - - - - ECO_HIGH_48 - Reserved. - 0x70 - 0x20 - 0xFFFFFFFF - - - USB_SERIAL_JTAG_RND_ECO_HIGH_48 - Reserved. - 0 - 32 - read-write - - - - - ECO_CELL_CTRL_48 - Reserved. - 0x74 - 0x20 - - - USB_SERIAL_JTAG_RDN_RESULT_48 - Reserved. - 0 - 1 - read-only - - - USB_SERIAL_JTAG_RDN_ENA_48 - Reserved. - 1 - 1 - read-write - - - - - ECO_LOW_APB - Reserved. - 0x78 - 0x20 - - - USB_SERIAL_JTAG_RND_ECO_LOW_APB - Reserved. - 0 - 32 - read-write - - - - - ECO_HIGH_APB - Reserved. - 0x7C - 0x20 - 0xFFFFFFFF - - - USB_SERIAL_JTAG_RND_ECO_HIGH_APB - Reserved. - 0 - 32 - read-write - - - - - ECO_CELL_CTRL_APB - Reserved. - 0x80 - 0x20 - - - USB_SERIAL_JTAG_RDN_RESULT_APB - Reserved. - 0 - 1 - read-only - - - USB_SERIAL_JTAG_RDN_ENA_APB - Reserved. - 1 - 1 - read-write - - - - - SRAM_CTRL - PPA SRAM Control Register - 0x84 - 0x20 - 0x00001320 - - - USB_SERIAL_JTAG_MEM_AUX_CTRL - Control signals - 0 - 14 - read-write - - - - - DATE - Date register - 0x88 - 0x20 - 0x02112010 - - - USB_SERIAL_JTAG_DATE - register version. - 0 - 32 - read-write - - - - - - - USB_WRAP - USB_WRAP Peripheral - USB_WRAP - 0x50080000 - - 0x0 - 0xC - registers - - - - OTG_CONF - USB wrapper configuration registers. - 0x0 - 0x20 - 0x00100000 - - - SRP_SESSEND_OVERRIDE - This bit is used to enable the software over-ride of srp session end signal. 1'b0: the signal is controlled by the chip input, 1'b1: the signal is controlled by the software. - 0 - 1 - read-write - - - SRP_SESSEND_VALUE - Software over-ride value of srp session end signal. - 1 - 1 - read-write - - - PHY_SEL - Select internal external PHY. 1'b0: Select internal PHY, 1'b1: Select external PHY. - 2 - 1 - read-write - - - DFIFO_FORCE_PD - Force the dfifo to go into low power mode. The data in dfifo will not lost. - 3 - 1 - read-write - - - DBNCE_FLTR_BYPASS - Bypass Debounce filters for avalid,bvalid,vbusvalid,session end, id signals - 4 - 1 - read-write - - - EXCHG_PINS_OVERRIDE - Enable software controlle USB D+ D- exchange - 5 - 1 - read-write - - - EXCHG_PINS - USB D+ D- exchange. 1'b0: don't change, 1'b1: exchange D+ D-. - 6 - 1 - read-write - - - VREFH - Control single-end input high threshold,1.76V to 2V, step 80mV. - 7 - 2 - read-write - - - VREFL - Control single-end input low threshold,0.8V to 1.04V, step 80mV. - 9 - 2 - read-write - - - VREF_OVERRIDE - Enable software controlle input threshold. - 11 - 1 - read-write - - - PAD_PULL_OVERRIDE - Enable software controlle USB D+ D- pullup pulldown. - 12 - 1 - read-write - - - DP_PULLUP - Controlle USB D+ pullup. - 13 - 1 - read-write - - - DP_PULLDOWN - Controlle USB D+ pulldown. - 14 - 1 - read-write - - - DM_PULLUP - Controlle USB D+ pullup. - 15 - 1 - read-write - - - DM_PULLDOWN - Controlle USB D+ pulldown. - 16 - 1 - read-write - - - PULLUP_VALUE - Controlle pullup value. 1'b0: typical value is 2.4K, 1'b1: typical value is 1.2K. - 17 - 1 - read-write - - - USB_PAD_ENABLE - Enable USB pad function. - 18 - 1 - read-write - - - AHB_CLK_FORCE_ON - Force ahb clock always on. - 19 - 1 - read-write - - - PHY_CLK_FORCE_ON - Force phy clock always on. - 20 - 1 - read-write - - - PHY_TX_EDGE_SEL - Select phy tx signal output clock edge. 1'b0: negedge, 1'b1: posedge. - 21 - 1 - read-write - - - DFIFO_FORCE_PU - Disable the dfifo to go into low power mode. The data in dfifo will not lost. - 22 - 1 - read-write - - - CLK_EN - Disable auto clock gating of CSR registers. - 31 - 1 - read-write - - - - - TEST_CONF - USB wrapper test configuration registers. - 0x4 - 0x20 - - - TEST_ENABLE - Enable test of the USB pad. - 0 - 1 - read-write - - - TEST_USB_OE - USB pad oen in test. - 1 - 1 - read-write - - - TEST_TX_DP - USB D+ tx value in test. - 2 - 1 - read-write - - - TEST_TX_DM - USB D- tx value in test. - 3 - 1 - read-write - - - TEST_RX_RCV - USB differential rx value in test. - 4 - 1 - read-only - - - TEST_RX_DP - USB D+ rx value in test. - 5 - 1 - read-only - - - TEST_RX_DM - USB D- rx value in test. - 6 - 1 - read-only - - - - - DATE - Date register. - 0x3FC - 0x20 - 0x23030504 - - - USB_WRAP_DATE - Date register. - 0 - 32 - read-only - - - - - - - \ No newline at end of file diff --git a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/gpio.c b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/gpio.c index d13f265b4..56076fd3c 100644 --- a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/gpio.c +++ b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/gpio.c @@ -1,3 +1,12 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright Christopher Kormanyos 2026. +// Distributed under the Boost Software License, +// Version 1.0. (See accompanying file LICENSE_1_0.txt +// or copy at http://www.boost.org/LICENSE_1_0.txt) +// + +// Originally from: + /****************************************************************************************** Filename : gpio.c @@ -15,15 +24,17 @@ ******************************************************************************************/ -//----------------------------------------------------------------------------------------- -// Includes -//----------------------------------------------------------------------------------------- #include +#include -//----------------------------------------------------------------------------------------- -// Types -//----------------------------------------------------------------------------------------- +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +#define GPIO_BASE 0x500E0000UL +#define LP_IO_MUX_BASE 0x5012B000UL +#define IO_MUX_BASE 0x500E1000UL typedef union { diff --git a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/gpio.h b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/gpio.h index 63ad51656..34a6d0343 100644 --- a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/gpio.h +++ b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/gpio.h @@ -1,3 +1,12 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright Christopher Kormanyos 2026. +// Distributed under the Boost Software License, +// Version 1.0. (See accompanying file LICENSE_1_0.txt +// or copy at http://www.boost.org/LICENSE_1_0.txt) +// + +// Originally from: + /****************************************************************************************** Filename : gpio.h @@ -20,8 +29,6 @@ // Includes //----------------------------------------------------------------------------------------- -#include - #include #include diff --git a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/interrupt.h b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/interrupt.h deleted file mode 100644 index d82de87c6..000000000 --- a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/interrupt.h +++ /dev/null @@ -1,96 +0,0 @@ -/****************************************************************************************** - Filename : interrrupt.h - - Core : RISC-V - - MCU : ESP32-P4 - - Author : Chalandi Amine - - Owner : Chalandi Amine - - Date : 25.01.2026 - - Description : CLIC and CLINT register definition file - -******************************************************************************************/ - -#ifndef __INTERRUPT_H__ -#define __INTERRUPT_H__ - -#include - -#if defined(__cplusplus) -extern "C" -{ -#endif - -typedef struct -{ - - uint8_t clicintip; /* Interrupt pending register */ - uint8_t clicintie; /* Interrupt enable register */ - uint8_t clicintattr; /* Interrupt attribute register */ - uint8_t clicintct; /* Interrupt level control register*/ -} -clicint_t; - -typedef struct -{ - uint32_t mcliccfg; /* CLIC machine mode global configuration register */ - uint32_t clicinfo; /* CLIC information register */ - uint32_t mintthresh; /* CLIC machine mode interrupt threshold register */ - clicint_t interrupt[48] __attribute__((aligned(0x1000))); /* CLIC interrupt configuration registers */ -} -clic_t; - -#define CLIC_BASE 0x20800000ul -#define CLIC ((volatile clic_t*)(CLIC_BASE)) - -#define CLINT_BASE 0x20000000ul -#define CLINT_MTIMECMP (*(volatile uint64_t*)(CLINT_BASE + 0x4000ul)) -#define CLINT_MTIMELOAD (*(volatile uint64_t*)(CLINT_BASE + 0x4008ul)) -#define CLINT_MTIMECTL (*(volatile uint32_t*)(CLINT_BASE + 0x4010ul)) -#define CLINT_MTIME (*(volatile uint64_t*)(CLINT_BASE + 0xBFF8ul)) - - -#define INT_SW_ID 3 -#define INT_TIMER_ID 7 -#define EXT_INT00_ID 16 -#define EXT_INT01_ID 17 -#define EXT_INT02_ID 18 -#define EXT_INT03_ID 19 -#define EXT_INT04_ID 20 -#define EXT_INT05_ID 21 -#define EXT_INT06_ID 22 -#define EXT_INT07_ID 23 -#define EXT_INT08_ID 24 -#define EXT_INT09_ID 25 -#define EXT_INT10_ID 26 -#define EXT_INT11_ID 27 -#define EXT_INT12_ID 28 -#define EXT_INT13_ID 29 -#define EXT_INT14_ID 30 -#define EXT_INT15_ID 31 -#define EXT_INT16_ID 32 -#define EXT_INT17_ID 33 -#define EXT_INT18_ID 34 -#define EXT_INT19_ID 35 -#define EXT_INT20_ID 36 -#define EXT_INT21_ID 37 -#define EXT_INT22_ID 38 -#define EXT_INT23_ID 39 -#define EXT_INT24_ID 40 -#define EXT_INT25_ID 41 -#define EXT_INT26_ID 42 -#define EXT_INT27_ID 43 -#define EXT_INT28_ID 44 -#define EXT_INT29_ID 45 -#define EXT_INT30_ID 46 -#define EXT_INT31_ID 47 - -#if defined(__cplusplus) -} -#endif - -#endif /* __INTERRUPT_H__ */ diff --git a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/riscv-csr.h b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/riscv-csr.h deleted file mode 100644 index 9a7c4f779..000000000 --- a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Mcal/riscv-csr.h +++ /dev/null @@ -1,3799 +0,0 @@ -/* - Register access functions for RISC-V system registers. - SPDX-License-Identifier: Unlicense - - https://five-embeddev.com/ - -*/ - -#ifndef RISCV_CSR_H -#define RISCV_CSR_H - -#include - -#if defined(__cplusplus) -extern "C" -{ -#endif - -#if __riscv_xlen==32 -typedef uint32_t uint_xlen_t; -typedef uint32_t uint_csr32_t; -typedef uint32_t uint_csr64_t; -#elif __riscv_xlen==64 -typedef uint64_t uint_xlen_t; -typedef uint32_t uint_csr32_t; -typedef uint64_t uint_csr64_t; -#else -#error "Unknown XLEN" -#endif - -// Test for Zicsr extension, if relevant -#if defined(__riscv_arch_test) -#if !defined(__riscv_zicsr) -#error "-march must include zicsr to access CSRs" -#endif -#endif - -/******************************************* - * misa - MRW - Machine ISA - */ -static inline uint_xlen_t csr_read_misa(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, misa" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_misa(uint_xlen_t value) { - __asm__ volatile ("csrw misa, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_misa(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, misa, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * mvendorid - MRO - Machine Vendor ID - */ -static inline uint32_t csr_read_mvendorid(void) { - uint_csr32_t value; - __asm__ volatile ("csrr %0, mvendorid" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} - -/******************************************* - * marchid - MRO - Machine Architecture ID - */ -static inline uint_xlen_t csr_read_marchid(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, marchid" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} - -/******************************************* - * mimpid - MRO - Machine Implementation ID - */ -static inline uint_xlen_t csr_read_mimpid(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, mimpid" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} - -/******************************************* - * mhartid - MRO - Hardware Thread ID - */ -static inline uint_xlen_t csr_read_mhartid(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, mhartid" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} - -/******************************************* - * mstatus - MRW - Machine Status - */ -static inline uint_xlen_t csr_read_mstatus(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, mstatus" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_mstatus(uint_xlen_t value) { - __asm__ volatile ("csrw mstatus, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_mstatus(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, mstatus, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} -/* Register CSR bit set and clear instructions */ -static inline void csr_set_bits_mstatus(uint_xlen_t mask) { - __asm__ volatile ("csrrs zero, mstatus, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); -} -static inline void csr_clr_bits_mstatus(uint_xlen_t mask) { - __asm__ volatile ("csrrc zero, mstatus, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_set_bits_mstatus(uint_xlen_t mask) { - uint_xlen_t value; - __asm__ volatile ("csrrs %0, mstatus, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); - return value; -} -static inline uint_xlen_t csr_read_clr_bits_mstatus(uint_xlen_t mask) { - uint_xlen_t value; - __asm__ volatile ("csrrc %0, mstatus, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); - return value; -} -/* mstatus, CSR write value via immediate value (only up to 5 bits) */ -#define CSR_WRITE_IMM_MSTATUS(VALUE) \ - __asm__ volatile ("csrrwi zero, mstatus, %0" \ - : /* output: none */ \ - : "i" (VALUE) /* input : immediate */ \ - : /* clobbers: none */) - -/* mstatus, CSR set bits via immediate value mask (only up to 5 bits) */ -#define CSR_SET_BITS_IMM_MSTATUS(MASK) \ - __asm__ volatile ("csrrsi zero, mstatus, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) - -/* mstatus, CSR clear bits via immediate value mask (only up to 5 bits) */ -#define CSR_CLR_BITS_IMM_MSTATUS(MASK) \ - __asm__ volatile ("csrrci zero, mstatus, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) -#define MSTATUS_MIE_BIT_OFFSET 3 -#define MSTATUS_MIE_BIT_WIDTH 1 -#define MSTATUS_MIE_BIT_MASK 0x8 -#define MSTATUS_MIE_ALL_SET_MASK 0x1 -#define MSTATUS_SIE_BIT_OFFSET 2 -#define MSTATUS_SIE_BIT_WIDTH 1 -#define MSTATUS_SIE_BIT_MASK 0x4 -#define MSTATUS_SIE_ALL_SET_MASK 0x1 -#define MSTATUS_MPIE_BIT_OFFSET 7 -#define MSTATUS_MPIE_BIT_WIDTH 1 -#define MSTATUS_MPIE_BIT_MASK 0x80 -#define MSTATUS_MPIE_ALL_SET_MASK 0x1 -#define MSTATUS_SPIE_BIT_OFFSET 5 -#define MSTATUS_SPIE_BIT_WIDTH 1 -#define MSTATUS_SPIE_BIT_MASK 0x20 -#define MSTATUS_SPIE_ALL_SET_MASK 0x1 -#define MSTATUS_MPRV_BIT_OFFSET 17 -#define MSTATUS_MPRV_BIT_WIDTH 1 -#define MSTATUS_MPRV_BIT_MASK 0x20000 -#define MSTATUS_MPRV_ALL_SET_MASK 0x1 -#define MSTATUS_MPP_BIT_OFFSET 11 -#define MSTATUS_MPP_BIT_WIDTH 2 -#define MSTATUS_MPP_BIT_MASK 0x1800 -#define MSTATUS_MPP_ALL_SET_MASK 0x3 -#define MSTATUS_SPP_BIT_OFFSET 8 -#define MSTATUS_SPP_BIT_WIDTH 1 -#define MSTATUS_SPP_BIT_MASK 0x100 -#define MSTATUS_SPP_ALL_SET_MASK 0x1 - -/******************************************* - * mstatush - MRW - Additional machine status register, RV32 only. - */ -static inline uint_xlen_t csr_read_mstatush(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, mstatush" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_mstatush(uint_xlen_t value) { - __asm__ volatile ("csrw mstatush, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_mstatush(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, mstatush, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * mtvec - MRW - Machine Trap Vector Base Address - */ -static inline uint_xlen_t csr_read_mtvec(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, mtvec" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_mtvec(uint_xlen_t value) { - __asm__ volatile ("csrw mtvec, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_mtvec(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, mtvec, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} -/* Register CSR bit set and clear instructions */ -static inline void csr_set_bits_mtvec(uint_xlen_t mask) { - __asm__ volatile ("csrrs zero, mtvec, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); -} -static inline void csr_clr_bits_mtvec(uint_xlen_t mask) { - __asm__ volatile ("csrrc zero, mtvec, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_set_bits_mtvec(uint_xlen_t mask) { - uint_xlen_t value; - __asm__ volatile ("csrrs %0, mtvec, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); - return value; -} -static inline uint_xlen_t csr_read_clr_bits_mtvec(uint_xlen_t mask) { - uint_xlen_t value; - __asm__ volatile ("csrrc %0, mtvec, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); - return value; -} -/* mtvec, CSR write value via immediate value (only up to 5 bits) */ -#define CSR_WRITE_IMM_MTVEC(VALUE) \ - __asm__ volatile ("csrrwi zero, mtvec, %0" \ - : /* output: none */ \ - : "i" (VALUE) /* input : immediate */ \ - : /* clobbers: none */) - -/* mtvec, CSR set bits via immediate value mask (only up to 5 bits) */ -#define CSR_SET_BITS_IMM_MTVEC(MASK) \ - __asm__ volatile ("csrrsi zero, mtvec, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) - -/* mtvec, CSR clear bits via immediate value mask (only up to 5 bits) */ -#define CSR_CLR_BITS_IMM_MTVEC(MASK) \ - __asm__ volatile ("csrrci zero, mtvec, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) -#define MTVEC_BASE_BIT_OFFSET 2 -#define MTVEC_BASE_BIT_WIDTH ((__riscv_xlen-1)-(2) + 1) -#define MTVEC_BASE_BIT_MASK ((1UL<<(((__riscv_xlen-1)-(2) + 1)-1)) << (2)) -#define MTVEC_BASE_ALL_SET_MASK ((1UL<<(((__riscv_xlen-1)-(2) + 1)-1)) << (0)) -#define MTVEC_MODE_BIT_OFFSET 0 -#define MTVEC_MODE_BIT_WIDTH 2 -#define MTVEC_MODE_BIT_MASK 0x3 -#define MTVEC_MODE_ALL_SET_MASK 0x3 - -/******************************************* - * medeleg - MRW - Machine Exception Delegation - */ -static inline uint_xlen_t csr_read_medeleg(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, medeleg" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_medeleg(uint_xlen_t value) { - __asm__ volatile ("csrw medeleg, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_medeleg(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, medeleg, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * mideleg - MRW - Machine Interrupt Delegation - */ -static inline uint_xlen_t csr_read_mideleg(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, mideleg" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_mideleg(uint_xlen_t value) { - __asm__ volatile ("csrw mideleg, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_mideleg(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, mideleg, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * mip - MRW - Machine Interrupt Pending - */ -static inline uint_xlen_t csr_read_mip(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, mip" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_mip(uint_xlen_t value) { - __asm__ volatile ("csrw mip, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_mip(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, mip, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} -/* Register CSR bit set and clear instructions */ -static inline void csr_set_bits_mip(uint_xlen_t mask) { - __asm__ volatile ("csrrs zero, mip, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); -} -static inline void csr_clr_bits_mip(uint_xlen_t mask) { - __asm__ volatile ("csrrc zero, mip, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_set_bits_mip(uint_xlen_t mask) { - uint_xlen_t value; - __asm__ volatile ("csrrs %0, mip, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); - return value; -} -static inline uint_xlen_t csr_read_clr_bits_mip(uint_xlen_t mask) { - uint_xlen_t value; - __asm__ volatile ("csrrc %0, mip, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); - return value; -} -/* mip, CSR write value via immediate value (only up to 5 bits) */ -#define CSR_WRITE_IMM_MIP(VALUE) \ - __asm__ volatile ("csrrwi zero, mip, %0" \ - : /* output: none */ \ - : "i" (VALUE) /* input : immediate */ \ - : /* clobbers: none */) - -/* mip, CSR set bits via immediate value mask (only up to 5 bits) */ -#define CSR_SET_BITS_IMM_MIP(MASK) \ - __asm__ volatile ("csrrsi zero, mip, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) - -/* mip, CSR clear bits via immediate value mask (only up to 5 bits) */ -#define CSR_CLR_BITS_IMM_MIP(MASK) \ - __asm__ volatile ("csrrci zero, mip, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) -#define MIP_MSI_BIT_OFFSET 3 -#define MIP_MSI_BIT_WIDTH 1 -#define MIP_MSI_BIT_MASK 0x8 -#define MIP_MSI_ALL_SET_MASK 0x1 -#define MIP_MTI_BIT_OFFSET 7 -#define MIP_MTI_BIT_WIDTH 1 -#define MIP_MTI_BIT_MASK 0x80 -#define MIP_MTI_ALL_SET_MASK 0x1 -#define MIP_MEI_BIT_OFFSET 11 -#define MIP_MEI_BIT_WIDTH 1 -#define MIP_MEI_BIT_MASK 0x800 -#define MIP_MEI_ALL_SET_MASK 0x1 -#define MIP_SSI_BIT_OFFSET 1 -#define MIP_SSI_BIT_WIDTH 1 -#define MIP_SSI_BIT_MASK 0x2 -#define MIP_SSI_ALL_SET_MASK 0x1 -#define MIP_STI_BIT_OFFSET 5 -#define MIP_STI_BIT_WIDTH 1 -#define MIP_STI_BIT_MASK 0x20 -#define MIP_STI_ALL_SET_MASK 0x1 -#define MIP_SEI_BIT_OFFSET 9 -#define MIP_SEI_BIT_WIDTH 1 -#define MIP_SEI_BIT_MASK 0x200 -#define MIP_SEI_ALL_SET_MASK 0x1 -#define MIP_USI_BIT_OFFSET 0 -#define MIP_USI_BIT_WIDTH 1 -#define MIP_USI_BIT_MASK 0x1 -#define MIP_USI_ALL_SET_MASK 0x1 -#define MIP_UTI_BIT_OFFSET 4 -#define MIP_UTI_BIT_WIDTH 1 -#define MIP_UTI_BIT_MASK 0x10 -#define MIP_UTI_ALL_SET_MASK 0x1 -#define MIP_UEI_BIT_OFFSET 8 -#define MIP_UEI_BIT_WIDTH 1 -#define MIP_UEI_BIT_MASK 0x100 -#define MIP_UEI_ALL_SET_MASK 0x1 -#define MIP_PLATFORM_DEFINED_BIT_OFFSET 16 -#define MIP_PLATFORM_DEFINED_BIT_WIDTH ((__riscv_xlen)-(16) + 1) -#define MIP_PLATFORM_DEFINED_BIT_MASK ((1UL<<(((__riscv_xlen)-(16) + 1)-1)) << (16)) -#define MIP_PLATFORM_DEFINED_ALL_SET_MASK ((1UL<<(((__riscv_xlen)-(16) + 1)-1)) << (0)) - -/******************************************* - * mie - MRW - Machine Interrupt Enable - */ -static inline uint_xlen_t csr_read_mie(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, mie" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_mie(uint_xlen_t value) { - __asm__ volatile ("csrw mie, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_mie(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, mie, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} -/* Register CSR bit set and clear instructions */ -static inline void csr_set_bits_mie(uint_xlen_t mask) { - __asm__ volatile ("csrrs zero, mie, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); -} -static inline void csr_clr_bits_mie(uint_xlen_t mask) { - __asm__ volatile ("csrrc zero, mie, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_set_bits_mie(uint_xlen_t mask) { - uint_xlen_t value; - __asm__ volatile ("csrrs %0, mie, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); - return value; -} -static inline uint_xlen_t csr_read_clr_bits_mie(uint_xlen_t mask) { - uint_xlen_t value; - __asm__ volatile ("csrrc %0, mie, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); - return value; -} -/* mie, CSR write value via immediate value (only up to 5 bits) */ -#define CSR_WRITE_IMM_MIE(VALUE) \ - __asm__ volatile ("csrrwi zero, mie, %0" \ - : /* output: none */ \ - : "i" (VALUE) /* input : immediate */ \ - : /* clobbers: none */) - -/* mie, CSR set bits via immediate value mask (only up to 5 bits) */ -#define CSR_SET_BITS_IMM_MIE(MASK) \ - __asm__ volatile ("csrrsi zero, mie, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) - -/* mie, CSR clear bits via immediate value mask (only up to 5 bits) */ -#define CSR_CLR_BITS_IMM_MIE(MASK) \ - __asm__ volatile ("csrrci zero, mie, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) -#define MIE_MSI_BIT_OFFSET 3 -#define MIE_MSI_BIT_WIDTH 1 -#define MIE_MSI_BIT_MASK 0x8 -#define MIE_MSI_ALL_SET_MASK 0x1 -#define MIE_MTI_BIT_OFFSET 7 -#define MIE_MTI_BIT_WIDTH 1 -#define MIE_MTI_BIT_MASK 0x80 -#define MIE_MTI_ALL_SET_MASK 0x1 -#define MIE_MEI_BIT_OFFSET 11 -#define MIE_MEI_BIT_WIDTH 1 -#define MIE_MEI_BIT_MASK 0x800 -#define MIE_MEI_ALL_SET_MASK 0x1 -#define MIE_SSI_BIT_OFFSET 1 -#define MIE_SSI_BIT_WIDTH 1 -#define MIE_SSI_BIT_MASK 0x2 -#define MIE_SSI_ALL_SET_MASK 0x1 -#define MIE_STI_BIT_OFFSET 5 -#define MIE_STI_BIT_WIDTH 1 -#define MIE_STI_BIT_MASK 0x20 -#define MIE_STI_ALL_SET_MASK 0x1 -#define MIE_SEI_BIT_OFFSET 9 -#define MIE_SEI_BIT_WIDTH 1 -#define MIE_SEI_BIT_MASK 0x200 -#define MIE_SEI_ALL_SET_MASK 0x1 -#define MIE_USI_BIT_OFFSET 0 -#define MIE_USI_BIT_WIDTH 1 -#define MIE_USI_BIT_MASK 0x1 -#define MIE_USI_ALL_SET_MASK 0x1 -#define MIE_UTI_BIT_OFFSET 4 -#define MIE_UTI_BIT_WIDTH 1 -#define MIE_UTI_BIT_MASK 0x10 -#define MIE_UTI_ALL_SET_MASK 0x1 -#define MIE_UEI_BIT_OFFSET 8 -#define MIE_UEI_BIT_WIDTH 1 -#define MIE_UEI_BIT_MASK 0x100 -#define MIE_UEI_ALL_SET_MASK 0x1 -#define MIE_PLATFORM_DEFINED_BIT_OFFSET 16 -#define MIE_PLATFORM_DEFINED_BIT_WIDTH ((__riscv_xlen)-(16) + 1) -#define MIE_PLATFORM_DEFINED_BIT_MASK ((1UL<<(((__riscv_xlen)-(16) + 1)-1)) << (16)) -#define MIE_PLATFORM_DEFINED_ALL_SET_MASK ((1UL<<(((__riscv_xlen)-(16) + 1)-1)) << (0)) - -/******************************************* - * mcountinhibit - MRW - Machine Counter Inhibit - */ -static inline uint32_t csr_read_mcountinhibit(void) { - uint_csr32_t value; - __asm__ volatile ("csrr %0, mcountinhibit" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_mcountinhibit(uint_csr32_t value) { - __asm__ volatile ("csrw mcountinhibit, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint32_t csr_read_write_mcountinhibit(uint32_t new_value) { - uint_csr32_t prev_value; - __asm__ volatile ("csrrw %0, mcountinhibit, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} -/* Register CSR bit set and clear instructions */ -static inline void csr_set_bits_mcountinhibit(uint32_t mask) { - __asm__ volatile ("csrrs zero, mcountinhibit, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); -} -static inline void csr_clr_bits_mcountinhibit(uint32_t mask) { - __asm__ volatile ("csrrc zero, mcountinhibit, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); -} -static inline uint32_t csr_read_set_bits_mcountinhibit(uint32_t mask) { - uint_csr32_t value; - __asm__ volatile ("csrrs %0, mcountinhibit, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); - return value; -} -static inline uint32_t csr_read_clr_bits_mcountinhibit(uint32_t mask) { - uint_csr32_t value; - __asm__ volatile ("csrrc %0, mcountinhibit, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); - return value; -} -/* mcountinhibit, CSR write value via immediate value (only up to 5 bits) */ -#define CSR_WRITE_IMM_MCOUNTINHIBIT(VALUE) \ - __asm__ volatile ("csrrwi zero, mcountinhibit, %0" \ - : /* output: none */ \ - : "i" (VALUE) /* input : immediate */ \ - : /* clobbers: none */) - -/* mcountinhibit, CSR set bits via immediate value mask (only up to 5 bits) */ -#define CSR_SET_BITS_IMM_MCOUNTINHIBIT(MASK) \ - __asm__ volatile ("csrrsi zero, mcountinhibit, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) - -/* mcountinhibit, CSR clear bits via immediate value mask (only up to 5 bits) */ -#define CSR_CLR_BITS_IMM_MCOUNTINHIBIT(MASK) \ - __asm__ volatile ("csrrci zero, mcountinhibit, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) -#define MCOUNTINHIBIT_CY_BIT_OFFSET 0 -#define MCOUNTINHIBIT_CY_BIT_WIDTH 1 -#define MCOUNTINHIBIT_CY_BIT_MASK 0x1 -#define MCOUNTINHIBIT_CY_ALL_SET_MASK 0x1 -#define MCOUNTINHIBIT_IR_BIT_OFFSET 2 -#define MCOUNTINHIBIT_IR_BIT_WIDTH 1 -#define MCOUNTINHIBIT_IR_BIT_MASK 0x4 -#define MCOUNTINHIBIT_IR_ALL_SET_MASK 0x1 -#define MCOUNTINHIBIT_HPM_BIT_OFFSET 3 -#define MCOUNTINHIBIT_HPM_BIT_WIDTH 29 -#define MCOUNTINHIBIT_HPM_BIT_MASK 0xfffffff8 -#define MCOUNTINHIBIT_HPM_ALL_SET_MASK 0x1fffffff - -/******************************************* - * mcycle - MRW - Clock Cycles Executed Counter - */ -static inline uint64_t csr_read_mcycle(void) { - uint_csr64_t value; - __asm__ volatile ("csrr %0, mcycle" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_mcycle(uint_csr64_t value) { - __asm__ volatile ("csrw mcycle, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint64_t csr_read_write_mcycle(uint64_t new_value) { - uint_csr64_t prev_value; - __asm__ volatile ("csrrw %0, mcycle, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * minstret - MRW - Number of Instructions Retired Counter - */ -static inline uint64_t csr_read_minstret(void) { - uint_csr64_t value; - __asm__ volatile ("csrr %0, minstret" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_minstret(uint_csr64_t value) { - __asm__ volatile ("csrw minstret, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint64_t csr_read_write_minstret(uint64_t new_value) { - uint_csr64_t prev_value; - __asm__ volatile ("csrrw %0, minstret, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * mhpmcounter3 - MRW - Event Counters - */ -static inline uint64_t csr_read_mhpmcounter3(void) { - uint_csr64_t value; - __asm__ volatile ("csrr %0, mhpmcounter3" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_mhpmcounter3(uint_csr64_t value) { - __asm__ volatile ("csrw mhpmcounter3, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint64_t csr_read_write_mhpmcounter3(uint64_t new_value) { - uint_csr64_t prev_value; - __asm__ volatile ("csrrw %0, mhpmcounter3, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * mhpmevent3 - MRW - Event Counter Event Select - */ -static inline uint_xlen_t csr_read_mhpmevent3(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, mhpmevent3" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_mhpmevent3(uint_xlen_t value) { - __asm__ volatile ("csrw mhpmevent3, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_mhpmevent3(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, mhpmevent3, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * mcounteren - MRW - Counter Enable - */ -static inline uint32_t csr_read_mcounteren(void) { - uint_csr32_t value; - __asm__ volatile ("csrr %0, mcounteren" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_mcounteren(uint_csr32_t value) { - __asm__ volatile ("csrw mcounteren, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint32_t csr_read_write_mcounteren(uint32_t new_value) { - uint_csr32_t prev_value; - __asm__ volatile ("csrrw %0, mcounteren, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} -/* Register CSR bit set and clear instructions */ -static inline void csr_set_bits_mcounteren(uint32_t mask) { - __asm__ volatile ("csrrs zero, mcounteren, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); -} -static inline void csr_clr_bits_mcounteren(uint32_t mask) { - __asm__ volatile ("csrrc zero, mcounteren, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); -} -static inline uint32_t csr_read_set_bits_mcounteren(uint32_t mask) { - uint_csr32_t value; - __asm__ volatile ("csrrs %0, mcounteren, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); - return value; -} -static inline uint32_t csr_read_clr_bits_mcounteren(uint32_t mask) { - uint_csr32_t value; - __asm__ volatile ("csrrc %0, mcounteren, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); - return value; -} -/* mcounteren, CSR write value via immediate value (only up to 5 bits) */ -#define CSR_WRITE_IMM_MCOUNTEREN(VALUE) \ - __asm__ volatile ("csrrwi zero, mcounteren, %0" \ - : /* output: none */ \ - : "i" (VALUE) /* input : immediate */ \ - : /* clobbers: none */) - -/* mcounteren, CSR set bits via immediate value mask (only up to 5 bits) */ -#define CSR_SET_BITS_IMM_MCOUNTEREN(MASK) \ - __asm__ volatile ("csrrsi zero, mcounteren, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) - -/* mcounteren, CSR clear bits via immediate value mask (only up to 5 bits) */ -#define CSR_CLR_BITS_IMM_MCOUNTEREN(MASK) \ - __asm__ volatile ("csrrci zero, mcounteren, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) -#define MCOUNTEREN_CY_BIT_OFFSET 0 -#define MCOUNTEREN_CY_BIT_WIDTH 1 -#define MCOUNTEREN_CY_BIT_MASK 0x1 -#define MCOUNTEREN_CY_ALL_SET_MASK 0x1 -#define MCOUNTEREN_TM_BIT_OFFSET 1 -#define MCOUNTEREN_TM_BIT_WIDTH 1 -#define MCOUNTEREN_TM_BIT_MASK 0x2 -#define MCOUNTEREN_TM_ALL_SET_MASK 0x1 -#define MCOUNTEREN_IR_BIT_OFFSET 2 -#define MCOUNTEREN_IR_BIT_WIDTH 1 -#define MCOUNTEREN_IR_BIT_MASK 0x4 -#define MCOUNTEREN_IR_ALL_SET_MASK 0x1 -#define MCOUNTEREN_HPM_BIT_OFFSET 3 -#define MCOUNTEREN_HPM_BIT_WIDTH 29 -#define MCOUNTEREN_HPM_BIT_MASK 0xfffffff8 -#define MCOUNTEREN_HPM_ALL_SET_MASK 0x1fffffff - -/******************************************* - * scounteren - SRW - Counter Enable - */ -static inline uint_xlen_t csr_read_scounteren(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, scounteren" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_scounteren(uint_xlen_t value) { - __asm__ volatile ("csrw scounteren, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_scounteren(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, scounteren, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * mscratch - MRW - Machine Mode Scratch Register - */ -static inline uint_xlen_t csr_read_mscratch(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, mscratch" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_mscratch(uint_xlen_t value) { - __asm__ volatile ("csrw mscratch, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_mscratch(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, mscratch, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * mepc - MRW - Machine Exception Program Counter - */ -static inline uint_xlen_t csr_read_mepc(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, mepc" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_mepc(uint_xlen_t value) { - __asm__ volatile ("csrw mepc, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_mepc(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, mepc, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * mcause - MRW - Machine Exception Cause - */ -static inline uint_xlen_t csr_read_mcause(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, mcause" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_mcause(uint_xlen_t value) { - __asm__ volatile ("csrw mcause, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_mcause(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, mcause, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} -/* Register CSR bit set and clear instructions */ -static inline void csr_set_bits_mcause(uint_xlen_t mask) { - __asm__ volatile ("csrrs zero, mcause, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); -} -static inline void csr_clr_bits_mcause(uint_xlen_t mask) { - __asm__ volatile ("csrrc zero, mcause, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_set_bits_mcause(uint_xlen_t mask) { - uint_xlen_t value; - __asm__ volatile ("csrrs %0, mcause, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); - return value; -} -static inline uint_xlen_t csr_read_clr_bits_mcause(uint_xlen_t mask) { - uint_xlen_t value; - __asm__ volatile ("csrrc %0, mcause, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); - return value; -} -/* mcause, CSR write value via immediate value (only up to 5 bits) */ -#define CSR_WRITE_IMM_MCAUSE(VALUE) \ - __asm__ volatile ("csrrwi zero, mcause, %0" \ - : /* output: none */ \ - : "i" (VALUE) /* input : immediate */ \ - : /* clobbers: none */) - -/* mcause, CSR set bits via immediate value mask (only up to 5 bits) */ -#define CSR_SET_BITS_IMM_MCAUSE(MASK) \ - __asm__ volatile ("csrrsi zero, mcause, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) - -/* mcause, CSR clear bits via immediate value mask (only up to 5 bits) */ -#define CSR_CLR_BITS_IMM_MCAUSE(MASK) \ - __asm__ volatile ("csrrci zero, mcause, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) -#define MCAUSE_INTERRUPT_BIT_OFFSET (__riscv_xlen-1) -#define MCAUSE_INTERRUPT_BIT_WIDTH 1 -#define MCAUSE_INTERRUPT_BIT_MASK (0x1UL << ((__riscv_xlen-1))) -#define MCAUSE_INTERRUPT_ALL_SET_MASK 0x1 -#define MCAUSE_EXCEPTION_CODE_BIT_OFFSET 0 -#define MCAUSE_EXCEPTION_CODE_BIT_WIDTH ((__riscv_xlen-2)-(0) + 1) -#define MCAUSE_EXCEPTION_CODE_BIT_MASK ((1UL<<(((__riscv_xlen-2)-(0) + 1)-1)) << (0)) -#define MCAUSE_EXCEPTION_CODE_ALL_SET_MASK ((1UL<<(((__riscv_xlen-2)-(0) + 1)-1)) << (0)) - -/******************************************* - * mtval - MRW - Machine Trap Value - */ -static inline uint_xlen_t csr_read_mtval(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, mtval" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_mtval(uint_xlen_t value) { - __asm__ volatile ("csrw mtval, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_mtval(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, mtval, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * sscratch - SRW - Supervisor Mode Scratch Register - */ -static inline uint_xlen_t csr_read_sscratch(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, sscratch" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_sscratch(uint_xlen_t value) { - __asm__ volatile ("csrw sscratch, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_sscratch(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, sscratch, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * sepc - SRW - Supervisor Exception Program Counter - */ -static inline uint_xlen_t csr_read_sepc(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, sepc" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_sepc(uint_xlen_t value) { - __asm__ volatile ("csrw sepc, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_sepc(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, sepc, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * scause - SRW - Supervisor Exception Cause - */ -static inline uint_xlen_t csr_read_scause(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, scause" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_scause(uint_xlen_t value) { - __asm__ volatile ("csrw scause, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_scause(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, scause, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} -/* Register CSR bit set and clear instructions */ -static inline void csr_set_bits_scause(uint_xlen_t mask) { - __asm__ volatile ("csrrs zero, scause, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); -} -static inline void csr_clr_bits_scause(uint_xlen_t mask) { - __asm__ volatile ("csrrc zero, scause, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_set_bits_scause(uint_xlen_t mask) { - uint_xlen_t value; - __asm__ volatile ("csrrs %0, scause, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); - return value; -} -static inline uint_xlen_t csr_read_clr_bits_scause(uint_xlen_t mask) { - uint_xlen_t value; - __asm__ volatile ("csrrc %0, scause, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); - return value; -} -/* scause, CSR write value via immediate value (only up to 5 bits) */ -#define CSR_WRITE_IMM_SCAUSE(VALUE) \ - __asm__ volatile ("csrrwi zero, scause, %0" \ - : /* output: none */ \ - : "i" (VALUE) /* input : immediate */ \ - : /* clobbers: none */) - -/* scause, CSR set bits via immediate value mask (only up to 5 bits) */ -#define CSR_SET_BITS_IMM_SCAUSE(MASK) \ - __asm__ volatile ("csrrsi zero, scause, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) - -/* scause, CSR clear bits via immediate value mask (only up to 5 bits) */ -#define CSR_CLR_BITS_IMM_SCAUSE(MASK) \ - __asm__ volatile ("csrrci zero, scause, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) -#define SCAUSE_INTERRUPT_BIT_OFFSET (__riscv_xlen-1) -#define SCAUSE_INTERRUPT_BIT_WIDTH 1 -#define SCAUSE_INTERRUPT_BIT_MASK (0x1UL << ((__riscv_xlen-1))) -#define SCAUSE_INTERRUPT_ALL_SET_MASK 0x1 -#define SCAUSE_EXCEPTION_CODE_BIT_OFFSET 0 -#define SCAUSE_EXCEPTION_CODE_BIT_WIDTH ((__riscv_xlen-2)-(0) + 1) -#define SCAUSE_EXCEPTION_CODE_BIT_MASK ((1UL<<(((__riscv_xlen-2)-(0) + 1)-1)) << (0)) -#define SCAUSE_EXCEPTION_CODE_ALL_SET_MASK ((1UL<<(((__riscv_xlen-2)-(0) + 1)-1)) << (0)) - -/******************************************* - * sstatus - SRW - Supervisor Status - */ -static inline uint_xlen_t csr_read_sstatus(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, sstatus" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_sstatus(uint_xlen_t value) { - __asm__ volatile ("csrw sstatus, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_sstatus(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, sstatus, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} -/* Register CSR bit set and clear instructions */ -static inline void csr_set_bits_sstatus(uint_xlen_t mask) { - __asm__ volatile ("csrrs zero, sstatus, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); -} -static inline void csr_clr_bits_sstatus(uint_xlen_t mask) { - __asm__ volatile ("csrrc zero, sstatus, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_set_bits_sstatus(uint_xlen_t mask) { - uint_xlen_t value; - __asm__ volatile ("csrrs %0, sstatus, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); - return value; -} -static inline uint_xlen_t csr_read_clr_bits_sstatus(uint_xlen_t mask) { - uint_xlen_t value; - __asm__ volatile ("csrrc %0, sstatus, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); - return value; -} -/* sstatus, CSR write value via immediate value (only up to 5 bits) */ -#define CSR_WRITE_IMM_SSTATUS(VALUE) \ - __asm__ volatile ("csrrwi zero, sstatus, %0" \ - : /* output: none */ \ - : "i" (VALUE) /* input : immediate */ \ - : /* clobbers: none */) - -/* sstatus, CSR set bits via immediate value mask (only up to 5 bits) */ -#define CSR_SET_BITS_IMM_SSTATUS(MASK) \ - __asm__ volatile ("csrrsi zero, sstatus, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) - -/* sstatus, CSR clear bits via immediate value mask (only up to 5 bits) */ -#define CSR_CLR_BITS_IMM_SSTATUS(MASK) \ - __asm__ volatile ("csrrci zero, sstatus, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) -#define SSTATUS_SIE_BIT_OFFSET 2 -#define SSTATUS_SIE_BIT_WIDTH 1 -#define SSTATUS_SIE_BIT_MASK 0x4 -#define SSTATUS_SIE_ALL_SET_MASK 0x1 -#define SSTATUS_SPIE_BIT_OFFSET 5 -#define SSTATUS_SPIE_BIT_WIDTH 1 -#define SSTATUS_SPIE_BIT_MASK 0x20 -#define SSTATUS_SPIE_ALL_SET_MASK 0x1 -#define SSTATUS_SPP_BIT_OFFSET 8 -#define SSTATUS_SPP_BIT_WIDTH 1 -#define SSTATUS_SPP_BIT_MASK 0x100 -#define SSTATUS_SPP_ALL_SET_MASK 0x1 - -/******************************************* - * stvec - SRW - Supervisor Trap Vector Base Address - */ -static inline uint_xlen_t csr_read_stvec(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, stvec" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_stvec(uint_xlen_t value) { - __asm__ volatile ("csrw stvec, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_stvec(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, stvec, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} -/* Register CSR bit set and clear instructions */ -static inline void csr_set_bits_stvec(uint_xlen_t mask) { - __asm__ volatile ("csrrs zero, stvec, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); -} -static inline void csr_clr_bits_stvec(uint_xlen_t mask) { - __asm__ volatile ("csrrc zero, stvec, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_set_bits_stvec(uint_xlen_t mask) { - uint_xlen_t value; - __asm__ volatile ("csrrs %0, stvec, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); - return value; -} -static inline uint_xlen_t csr_read_clr_bits_stvec(uint_xlen_t mask) { - uint_xlen_t value; - __asm__ volatile ("csrrc %0, stvec, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); - return value; -} -/* stvec, CSR write value via immediate value (only up to 5 bits) */ -#define CSR_WRITE_IMM_STVEC(VALUE) \ - __asm__ volatile ("csrrwi zero, stvec, %0" \ - : /* output: none */ \ - : "i" (VALUE) /* input : immediate */ \ - : /* clobbers: none */) - -/* stvec, CSR set bits via immediate value mask (only up to 5 bits) */ -#define CSR_SET_BITS_IMM_STVEC(MASK) \ - __asm__ volatile ("csrrsi zero, stvec, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) - -/* stvec, CSR clear bits via immediate value mask (only up to 5 bits) */ -#define CSR_CLR_BITS_IMM_STVEC(MASK) \ - __asm__ volatile ("csrrci zero, stvec, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) -#define STVEC_BASE_BIT_OFFSET 2 -#define STVEC_BASE_BIT_WIDTH ((__riscv_xlen-1)-(2) + 1) -#define STVEC_BASE_BIT_MASK ((1UL<<(((__riscv_xlen-1)-(2) + 1)-1)) << (2)) -#define STVEC_BASE_ALL_SET_MASK ((1UL<<(((__riscv_xlen-1)-(2) + 1)-1)) << (0)) -#define STVEC_MODE_BIT_OFFSET 0 -#define STVEC_MODE_BIT_WIDTH 2 -#define STVEC_MODE_BIT_MASK 0x3 -#define STVEC_MODE_ALL_SET_MASK 0x3 - -/******************************************* - * sideleg - SRW - Supervisor Interrupt Delegation - */ -static inline uint_xlen_t csr_read_sideleg(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, sideleg" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_sideleg(uint_xlen_t value) { - __asm__ volatile ("csrw sideleg, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_sideleg(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, sideleg, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * sedeleg - SRW - Supervisor Exception Delegation - */ -static inline uint_xlen_t csr_read_sedeleg(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, sedeleg" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_sedeleg(uint_xlen_t value) { - __asm__ volatile ("csrw sedeleg, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_sedeleg(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, sedeleg, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * sip - SRW - Supervisor Interrupt Pending - */ -static inline uint_xlen_t csr_read_sip(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, sip" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_sip(uint_xlen_t value) { - __asm__ volatile ("csrw sip, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_sip(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, sip, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} -/* Register CSR bit set and clear instructions */ -static inline void csr_set_bits_sip(uint_xlen_t mask) { - __asm__ volatile ("csrrs zero, sip, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); -} -static inline void csr_clr_bits_sip(uint_xlen_t mask) { - __asm__ volatile ("csrrc zero, sip, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_set_bits_sip(uint_xlen_t mask) { - uint_xlen_t value; - __asm__ volatile ("csrrs %0, sip, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); - return value; -} -static inline uint_xlen_t csr_read_clr_bits_sip(uint_xlen_t mask) { - uint_xlen_t value; - __asm__ volatile ("csrrc %0, sip, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); - return value; -} -/* sip, CSR write value via immediate value (only up to 5 bits) */ -#define CSR_WRITE_IMM_SIP(VALUE) \ - __asm__ volatile ("csrrwi zero, sip, %0" \ - : /* output: none */ \ - : "i" (VALUE) /* input : immediate */ \ - : /* clobbers: none */) - -/* sip, CSR set bits via immediate value mask (only up to 5 bits) */ -#define CSR_SET_BITS_IMM_SIP(MASK) \ - __asm__ volatile ("csrrsi zero, sip, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) - -/* sip, CSR clear bits via immediate value mask (only up to 5 bits) */ -#define CSR_CLR_BITS_IMM_SIP(MASK) \ - __asm__ volatile ("csrrci zero, sip, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) -#define SIP_SSI_BIT_OFFSET 1 -#define SIP_SSI_BIT_WIDTH 1 -#define SIP_SSI_BIT_MASK 0x2 -#define SIP_SSI_ALL_SET_MASK 0x1 -#define SIP_STI_BIT_OFFSET 5 -#define SIP_STI_BIT_WIDTH 1 -#define SIP_STI_BIT_MASK 0x20 -#define SIP_STI_ALL_SET_MASK 0x1 -#define SIP_SEI_BIT_OFFSET 9 -#define SIP_SEI_BIT_WIDTH 1 -#define SIP_SEI_BIT_MASK 0x200 -#define SIP_SEI_ALL_SET_MASK 0x1 -#define SIP_USI_BIT_OFFSET 0 -#define SIP_USI_BIT_WIDTH 1 -#define SIP_USI_BIT_MASK 0x1 -#define SIP_USI_ALL_SET_MASK 0x1 -#define SIP_UTI_BIT_OFFSET 4 -#define SIP_UTI_BIT_WIDTH 1 -#define SIP_UTI_BIT_MASK 0x10 -#define SIP_UTI_ALL_SET_MASK 0x1 -#define SIP_UEI_BIT_OFFSET 8 -#define SIP_UEI_BIT_WIDTH 1 -#define SIP_UEI_BIT_MASK 0x100 -#define SIP_UEI_ALL_SET_MASK 0x1 - -/******************************************* - * sie - SRW - Supervisor Interrupt Enable - */ -static inline uint_xlen_t csr_read_sie(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, sie" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_sie(uint_xlen_t value) { - __asm__ volatile ("csrw sie, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_sie(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, sie, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} -/* Register CSR bit set and clear instructions */ -static inline void csr_set_bits_sie(uint_xlen_t mask) { - __asm__ volatile ("csrrs zero, sie, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); -} -static inline void csr_clr_bits_sie(uint_xlen_t mask) { - __asm__ volatile ("csrrc zero, sie, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_set_bits_sie(uint_xlen_t mask) { - uint_xlen_t value; - __asm__ volatile ("csrrs %0, sie, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); - return value; -} -static inline uint_xlen_t csr_read_clr_bits_sie(uint_xlen_t mask) { - uint_xlen_t value; - __asm__ volatile ("csrrc %0, sie, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); - return value; -} -/* sie, CSR write value via immediate value (only up to 5 bits) */ -#define CSR_WRITE_IMM_SIE(VALUE) \ - __asm__ volatile ("csrrwi zero, sie, %0" \ - : /* output: none */ \ - : "i" (VALUE) /* input : immediate */ \ - : /* clobbers: none */) - -/* sie, CSR set bits via immediate value mask (only up to 5 bits) */ -#define CSR_SET_BITS_IMM_SIE(MASK) \ - __asm__ volatile ("csrrsi zero, sie, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) - -/* sie, CSR clear bits via immediate value mask (only up to 5 bits) */ -#define CSR_CLR_BITS_IMM_SIE(MASK) \ - __asm__ volatile ("csrrci zero, sie, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) -#define SIE_SSI_BIT_OFFSET 1 -#define SIE_SSI_BIT_WIDTH 1 -#define SIE_SSI_BIT_MASK 0x2 -#define SIE_SSI_ALL_SET_MASK 0x1 -#define SIE_STI_BIT_OFFSET 5 -#define SIE_STI_BIT_WIDTH 1 -#define SIE_STI_BIT_MASK 0x20 -#define SIE_STI_ALL_SET_MASK 0x1 -#define SIE_SEI_BIT_OFFSET 9 -#define SIE_SEI_BIT_WIDTH 1 -#define SIE_SEI_BIT_MASK 0x200 -#define SIE_SEI_ALL_SET_MASK 0x1 -#define SIE_USI_BIT_OFFSET 0 -#define SIE_USI_BIT_WIDTH 1 -#define SIE_USI_BIT_MASK 0x1 -#define SIE_USI_ALL_SET_MASK 0x1 -#define SIE_UTI_BIT_OFFSET 4 -#define SIE_UTI_BIT_WIDTH 1 -#define SIE_UTI_BIT_MASK 0x10 -#define SIE_UTI_ALL_SET_MASK 0x1 -#define SIE_UEI_BIT_OFFSET 8 -#define SIE_UEI_BIT_WIDTH 1 -#define SIE_UEI_BIT_MASK 0x100 -#define SIE_UEI_ALL_SET_MASK 0x1 - -/******************************************* - * ustatus - URW - User mode restricted view of mstatus - */ -static inline uint_xlen_t csr_read_ustatus(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, ustatus" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_ustatus(uint_xlen_t value) { - __asm__ volatile ("csrw ustatus, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_ustatus(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, ustatus, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} -/* Register CSR bit set and clear instructions */ -static inline void csr_set_bits_ustatus(uint_xlen_t mask) { - __asm__ volatile ("csrrs zero, ustatus, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); -} -static inline void csr_clr_bits_ustatus(uint_xlen_t mask) { - __asm__ volatile ("csrrc zero, ustatus, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_set_bits_ustatus(uint_xlen_t mask) { - uint_xlen_t value; - __asm__ volatile ("csrrs %0, ustatus, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); - return value; -} -static inline uint_xlen_t csr_read_clr_bits_ustatus(uint_xlen_t mask) { - uint_xlen_t value; - __asm__ volatile ("csrrc %0, ustatus, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); - return value; -} -/* ustatus, CSR write value via immediate value (only up to 5 bits) */ -#define CSR_WRITE_IMM_USTATUS(VALUE) \ - __asm__ volatile ("csrrwi zero, ustatus, %0" \ - : /* output: none */ \ - : "i" (VALUE) /* input : immediate */ \ - : /* clobbers: none */) - -/* ustatus, CSR set bits via immediate value mask (only up to 5 bits) */ -#define CSR_SET_BITS_IMM_USTATUS(MASK) \ - __asm__ volatile ("csrrsi zero, ustatus, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) - -/* ustatus, CSR clear bits via immediate value mask (only up to 5 bits) */ -#define CSR_CLR_BITS_IMM_USTATUS(MASK) \ - __asm__ volatile ("csrrci zero, ustatus, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) -#define USTATUS_UIE_BIT_OFFSET 1 -#define USTATUS_UIE_BIT_WIDTH 1 -#define USTATUS_UIE_BIT_MASK 0x2 -#define USTATUS_UIE_ALL_SET_MASK 0x1 -#define USTATUS_UPIE_BIT_OFFSET 3 -#define USTATUS_UPIE_BIT_WIDTH 1 -#define USTATUS_UPIE_BIT_MASK 0x8 -#define USTATUS_UPIE_ALL_SET_MASK 0x1 - -/******************************************* - * uip - URW - User Interrupt Pending - */ -static inline uint_xlen_t csr_read_uip(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, uip" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_uip(uint_xlen_t value) { - __asm__ volatile ("csrw uip, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_uip(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, uip, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} -/* Register CSR bit set and clear instructions */ -static inline void csr_set_bits_uip(uint_xlen_t mask) { - __asm__ volatile ("csrrs zero, uip, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); -} -static inline void csr_clr_bits_uip(uint_xlen_t mask) { - __asm__ volatile ("csrrc zero, uip, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_set_bits_uip(uint_xlen_t mask) { - uint_xlen_t value; - __asm__ volatile ("csrrs %0, uip, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); - return value; -} -static inline uint_xlen_t csr_read_clr_bits_uip(uint_xlen_t mask) { - uint_xlen_t value; - __asm__ volatile ("csrrc %0, uip, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); - return value; -} -/* uip, CSR write value via immediate value (only up to 5 bits) */ -#define CSR_WRITE_IMM_UIP(VALUE) \ - __asm__ volatile ("csrrwi zero, uip, %0" \ - : /* output: none */ \ - : "i" (VALUE) /* input : immediate */ \ - : /* clobbers: none */) - -/* uip, CSR set bits via immediate value mask (only up to 5 bits) */ -#define CSR_SET_BITS_IMM_UIP(MASK) \ - __asm__ volatile ("csrrsi zero, uip, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) - -/* uip, CSR clear bits via immediate value mask (only up to 5 bits) */ -#define CSR_CLR_BITS_IMM_UIP(MASK) \ - __asm__ volatile ("csrrci zero, uip, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) -#define UIP_USI_BIT_OFFSET 0 -#define UIP_USI_BIT_WIDTH 1 -#define UIP_USI_BIT_MASK 0x1 -#define UIP_USI_ALL_SET_MASK 0x1 -#define UIP_UTI_BIT_OFFSET 4 -#define UIP_UTI_BIT_WIDTH 1 -#define UIP_UTI_BIT_MASK 0x10 -#define UIP_UTI_ALL_SET_MASK 0x1 -#define UIP_UEI_BIT_OFFSET 8 -#define UIP_UEI_BIT_WIDTH 1 -#define UIP_UEI_BIT_MASK 0x100 -#define UIP_UEI_ALL_SET_MASK 0x1 - -/******************************************* - * uie - URW - User Interrupt Enable - */ -static inline uint_xlen_t csr_read_uie(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, uie" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_uie(uint_xlen_t value) { - __asm__ volatile ("csrw uie, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_uie(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, uie, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} -/* Register CSR bit set and clear instructions */ -static inline void csr_set_bits_uie(uint_xlen_t mask) { - __asm__ volatile ("csrrs zero, uie, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); -} -static inline void csr_clr_bits_uie(uint_xlen_t mask) { - __asm__ volatile ("csrrc zero, uie, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_set_bits_uie(uint_xlen_t mask) { - uint_xlen_t value; - __asm__ volatile ("csrrs %0, uie, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); - return value; -} -static inline uint_xlen_t csr_read_clr_bits_uie(uint_xlen_t mask) { - uint_xlen_t value; - __asm__ volatile ("csrrc %0, uie, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); - return value; -} -/* uie, CSR write value via immediate value (only up to 5 bits) */ -#define CSR_WRITE_IMM_UIE(VALUE) \ - __asm__ volatile ("csrrwi zero, uie, %0" \ - : /* output: none */ \ - : "i" (VALUE) /* input : immediate */ \ - : /* clobbers: none */) - -/* uie, CSR set bits via immediate value mask (only up to 5 bits) */ -#define CSR_SET_BITS_IMM_UIE(MASK) \ - __asm__ volatile ("csrrsi zero, uie, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) - -/* uie, CSR clear bits via immediate value mask (only up to 5 bits) */ -#define CSR_CLR_BITS_IMM_UIE(MASK) \ - __asm__ volatile ("csrrci zero, uie, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) -#define UIE_USI_BIT_OFFSET 0 -#define UIE_USI_BIT_WIDTH 1 -#define UIE_USI_BIT_MASK 0x1 -#define UIE_USI_ALL_SET_MASK 0x1 -#define UIE_UTI_BIT_OFFSET 4 -#define UIE_UTI_BIT_WIDTH 1 -#define UIE_UTI_BIT_MASK 0x10 -#define UIE_UTI_ALL_SET_MASK 0x1 -#define UIE_UEI_BIT_OFFSET 8 -#define UIE_UEI_BIT_WIDTH 1 -#define UIE_UEI_BIT_MASK 0x100 -#define UIE_UEI_ALL_SET_MASK 0x1 - -/******************************************* - * uscratch - URW - User Mode Scratch Register - */ -static inline uint_xlen_t csr_read_uscratch(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, uscratch" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_uscratch(uint_xlen_t value) { - __asm__ volatile ("csrw uscratch, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_uscratch(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, uscratch, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * uepc - URW - User Exception Program Counter - */ -static inline uint_xlen_t csr_read_uepc(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, uepc" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_uepc(uint_xlen_t value) { - __asm__ volatile ("csrw uepc, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_uepc(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, uepc, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * ucause - URW - User Exception Cause - */ -static inline uint_xlen_t csr_read_ucause(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, ucause" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_ucause(uint_xlen_t value) { - __asm__ volatile ("csrw ucause, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_ucause(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, ucause, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} -/* Register CSR bit set and clear instructions */ -static inline void csr_set_bits_ucause(uint_xlen_t mask) { - __asm__ volatile ("csrrs zero, ucause, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); -} -static inline void csr_clr_bits_ucause(uint_xlen_t mask) { - __asm__ volatile ("csrrc zero, ucause, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_set_bits_ucause(uint_xlen_t mask) { - uint_xlen_t value; - __asm__ volatile ("csrrs %0, ucause, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); - return value; -} -static inline uint_xlen_t csr_read_clr_bits_ucause(uint_xlen_t mask) { - uint_xlen_t value; - __asm__ volatile ("csrrc %0, ucause, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); - return value; -} -/* ucause, CSR write value via immediate value (only up to 5 bits) */ -#define CSR_WRITE_IMM_UCAUSE(VALUE) \ - __asm__ volatile ("csrrwi zero, ucause, %0" \ - : /* output: none */ \ - : "i" (VALUE) /* input : immediate */ \ - : /* clobbers: none */) - -/* ucause, CSR set bits via immediate value mask (only up to 5 bits) */ -#define CSR_SET_BITS_IMM_UCAUSE(MASK) \ - __asm__ volatile ("csrrsi zero, ucause, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) - -/* ucause, CSR clear bits via immediate value mask (only up to 5 bits) */ -#define CSR_CLR_BITS_IMM_UCAUSE(MASK) \ - __asm__ volatile ("csrrci zero, ucause, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) -#define UCAUSE_INTERRUPT_BIT_OFFSET (__riscv_xlen-1) -#define UCAUSE_INTERRUPT_BIT_WIDTH 1 -#define UCAUSE_INTERRUPT_BIT_MASK (0x1UL << ((__riscv_xlen-1))) -#define UCAUSE_INTERRUPT_ALL_SET_MASK 0x1 -#define UCAUSE_EXCEPTION_CODE_BIT_OFFSET 0 -#define UCAUSE_EXCEPTION_CODE_BIT_WIDTH ((__riscv_xlen-2)-(0) + 1) -#define UCAUSE_EXCEPTION_CODE_BIT_MASK ((1UL<<(((__riscv_xlen-2)-(0) + 1)-1)) << (0)) -#define UCAUSE_EXCEPTION_CODE_ALL_SET_MASK ((1UL<<(((__riscv_xlen-2)-(0) + 1)-1)) << (0)) - -/******************************************* - * utvec - URW - User Trap Vector Base Address - */ -static inline uint_xlen_t csr_read_utvec(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, utvec" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_utvec(uint_xlen_t value) { - __asm__ volatile ("csrw utvec, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_utvec(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, utvec, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} -/* Register CSR bit set and clear instructions */ -static inline void csr_set_bits_utvec(uint_xlen_t mask) { - __asm__ volatile ("csrrs zero, utvec, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); -} -static inline void csr_clr_bits_utvec(uint_xlen_t mask) { - __asm__ volatile ("csrrc zero, utvec, %0" - : /* output: none */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_set_bits_utvec(uint_xlen_t mask) { - uint_xlen_t value; - __asm__ volatile ("csrrs %0, utvec, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); - return value; -} -static inline uint_xlen_t csr_read_clr_bits_utvec(uint_xlen_t mask) { - uint_xlen_t value; - __asm__ volatile ("csrrc %0, utvec, %1" - : "=r" (value) /* output: register %0 */ - : "r" (mask) /* input : register */ - : /* clobbers: none */); - return value; -} -/* utvec, CSR write value via immediate value (only up to 5 bits) */ -#define CSR_WRITE_IMM_UTVEC(VALUE) \ - __asm__ volatile ("csrrwi zero, utvec, %0" \ - : /* output: none */ \ - : "i" (VALUE) /* input : immediate */ \ - : /* clobbers: none */) - -/* utvec, CSR set bits via immediate value mask (only up to 5 bits) */ -#define CSR_SET_BITS_IMM_UTVEC(MASK) \ - __asm__ volatile ("csrrsi zero, utvec, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) - -/* utvec, CSR clear bits via immediate value mask (only up to 5 bits) */ -#define CSR_CLR_BITS_IMM_UTVEC(MASK) \ - __asm__ volatile ("csrrci zero, utvec, %0" \ - : /* output: none */ \ - : "i" (MASK) /* input : immediate */ \ - : /* clobbers: none */) -#define UTVEC_BASE_BIT_OFFSET 2 -#define UTVEC_BASE_BIT_WIDTH ((__riscv_xlen-1)-(2) + 1) -#define UTVEC_BASE_BIT_MASK ((1UL<<(((__riscv_xlen-1)-(2) + 1)-1)) << (2)) -#define UTVEC_BASE_ALL_SET_MASK ((1UL<<(((__riscv_xlen-1)-(2) + 1)-1)) << (0)) -#define UTVEC_MODE_BIT_OFFSET 0 -#define UTVEC_MODE_BIT_WIDTH 2 -#define UTVEC_MODE_BIT_MASK 0x3 -#define UTVEC_MODE_ALL_SET_MASK 0x3 - -/******************************************* - * utval - URW - User Trap Value - */ -static inline uint_xlen_t csr_read_utval(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, utval" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_utval(uint_xlen_t value) { - __asm__ volatile ("csrw utval, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_utval(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, utval, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * fflags - URW - Floating-Point Accrued Exceptions. - */ -static inline uint_xlen_t csr_read_fflags(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, fflags" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_fflags(uint_xlen_t value) { - __asm__ volatile ("csrw fflags, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_fflags(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, fflags, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * frm - URW - Floating-Point Dynamic Rounding Mode. - */ -static inline uint_xlen_t csr_read_frm(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, frm" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_frm(uint_xlen_t value) { - __asm__ volatile ("csrw frm, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_frm(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, frm, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * fcsr - URW - Floating-Point Control and Status - */ -static inline uint_xlen_t csr_read_fcsr(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, fcsr" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_fcsr(uint_xlen_t value) { - __asm__ volatile ("csrw fcsr, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_fcsr(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, fcsr, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * cycle - URO - Cycle counter for RDCYCLE instruction. - */ -static inline uint_xlen_t csr_read_cycle(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, cycle" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} - -/******************************************* - * time - URO - Timer for RDTIME instruction. - */ -static inline uint_xlen_t csr_read_time(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, time" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} - -/******************************************* - * instret - URO - Instructions-retired counter for RDINSTRET instruction. - */ -static inline uint_xlen_t csr_read_instret(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, instret" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} - -/******************************************* - * hpmcounter3 - URO - Performance-monitoring counter. - */ -static inline uint_xlen_t csr_read_hpmcounter3(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, hpmcounter3" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} - -/******************************************* - * hpmcounter4 - URO - Performance-monitoring counter. - */ -static inline uint_xlen_t csr_read_hpmcounter4(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, hpmcounter4" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} - -/******************************************* - * hpmcounter31 - URO - Performance-monitoring counter. - */ -static inline uint_xlen_t csr_read_hpmcounter31(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, hpmcounter31" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} - -/******************************************* - * cycleh - URO - Upper 32 bits of cycle, RV32I only. - */ -static inline uint_xlen_t csr_read_cycleh(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, cycleh" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} - -/******************************************* - * timeh - URO - Upper 32 bits of time, RV32I only. - */ -static inline uint_xlen_t csr_read_timeh(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, timeh" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} - -/******************************************* - * instreth - URO - Upper 32 bits of instret, RV32I only. - */ -static inline uint_xlen_t csr_read_instreth(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, instreth" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} - -/******************************************* - * hpmcounter3h - URO - Upper 32 bits of hpmcounter3, RV32I only. - */ -static inline uint_xlen_t csr_read_hpmcounter3h(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, hpmcounter3h" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} - -/******************************************* - * hpmcounter4h - URO - Upper 32 bits of hpmcounter4, RV32I only. - */ -static inline uint_xlen_t csr_read_hpmcounter4h(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, hpmcounter4h" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} - -/******************************************* - * hpmcounter31h - URO - Upper 32 bits of hpmcounter31, RV32I only. - */ -static inline uint_xlen_t csr_read_hpmcounter31h(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, hpmcounter31h" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} - -/******************************************* - * stval - SRW - Supervisor bad address or instruction. - */ -static inline uint_xlen_t csr_read_stval(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, stval" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_stval(uint_xlen_t value) { - __asm__ volatile ("csrw stval, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_stval(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, stval, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * satp - SRW - Supervisor address translation and protection. - */ -static inline uint_xlen_t csr_read_satp(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, satp" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_satp(uint_xlen_t value) { - __asm__ volatile ("csrw satp, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_satp(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, satp, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * hstatus - HRW - Hypervisor status register. - */ -static inline uint_xlen_t csr_read_hstatus(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, hstatus" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_hstatus(uint_xlen_t value) { - __asm__ volatile ("csrw hstatus, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_hstatus(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, hstatus, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * hedeleg - HRW - Hypervisor exception delegation register. - */ -static inline uint_xlen_t csr_read_hedeleg(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, hedeleg" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_hedeleg(uint_xlen_t value) { - __asm__ volatile ("csrw hedeleg, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_hedeleg(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, hedeleg, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * hideleg - HRW - Hypervisor interrupt delegation register. - */ -static inline uint_xlen_t csr_read_hideleg(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, hideleg" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_hideleg(uint_xlen_t value) { - __asm__ volatile ("csrw hideleg, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_hideleg(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, hideleg, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * hcounteren - HRW - Hypervisor counter enable. - */ -static inline uint_xlen_t csr_read_hcounteren(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, hcounteren" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_hcounteren(uint_xlen_t value) { - __asm__ volatile ("csrw hcounteren, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_hcounteren(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, hcounteren, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * hgatp - HRW - Hypervisor guest address translation and protection. - */ -static inline uint_xlen_t csr_read_hgatp(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, hgatp" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_hgatp(uint_xlen_t value) { - __asm__ volatile ("csrw hgatp, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_hgatp(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, hgatp, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * htimedelta - HRW - Delta for VS/VU-mode timer. - */ -static inline uint_xlen_t csr_read_htimedelta(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, htimedelta" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_htimedelta(uint_xlen_t value) { - __asm__ volatile ("csrw htimedelta, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_htimedelta(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, htimedelta, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * htimedeltah - HRW - Upper 32 bits of htimedelta, RV32I only. - */ -static inline uint_xlen_t csr_read_htimedeltah(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, htimedeltah" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_htimedeltah(uint_xlen_t value) { - __asm__ volatile ("csrw htimedeltah, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_htimedeltah(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, htimedeltah, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * vsstatus - HRW - Virtual supervisor status register. - */ -static inline uint_xlen_t csr_read_vsstatus(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, vsstatus" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_vsstatus(uint_xlen_t value) { - __asm__ volatile ("csrw vsstatus, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_vsstatus(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, vsstatus, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * vsie - HRW - Virtual supervisor interrupt-enable register. - */ -static inline uint_xlen_t csr_read_vsie(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, vsie" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_vsie(uint_xlen_t value) { - __asm__ volatile ("csrw vsie, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_vsie(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, vsie, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * vstvec - HRW - Virtual supervisor trap handler base address. - */ -static inline uint_xlen_t csr_read_vstvec(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, vstvec" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_vstvec(uint_xlen_t value) { - __asm__ volatile ("csrw vstvec, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_vstvec(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, vstvec, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * vsscratch - HRW - Virtual supervisor scratch register. - */ -static inline uint_xlen_t csr_read_vsscratch(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, vsscratch" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_vsscratch(uint_xlen_t value) { - __asm__ volatile ("csrw vsscratch, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_vsscratch(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, vsscratch, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * vsepc - HRW - Virtual supervisor exception program counter. - */ -static inline uint_xlen_t csr_read_vsepc(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, vsepc" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_vsepc(uint_xlen_t value) { - __asm__ volatile ("csrw vsepc, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_vsepc(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, vsepc, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * vscause - HRW - Virtual supervisor trap cause. - */ -static inline uint_xlen_t csr_read_vscause(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, vscause" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_vscause(uint_xlen_t value) { - __asm__ volatile ("csrw vscause, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_vscause(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, vscause, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * vstval - HRW - Virtual supervisor bad address or instruction. - */ -static inline uint_xlen_t csr_read_vstval(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, vstval" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_vstval(uint_xlen_t value) { - __asm__ volatile ("csrw vstval, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_vstval(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, vstval, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * vsip - HRW - Virtual supervisor interrupt pending. - */ -static inline uint_xlen_t csr_read_vsip(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, vsip" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_vsip(uint_xlen_t value) { - __asm__ volatile ("csrw vsip, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_vsip(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, vsip, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * vsatp - HRW - Virtual supervisor address translation and protection. - */ -static inline uint_xlen_t csr_read_vsatp(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, vsatp" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_vsatp(uint_xlen_t value) { - __asm__ volatile ("csrw vsatp, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_vsatp(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, vsatp, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * mbase - MRW - Base register. - */ -static inline uint_xlen_t csr_read_mbase(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, mbase" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_mbase(uint_xlen_t value) { - __asm__ volatile ("csrw mbase, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_mbase(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, mbase, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * mbound - MRW - Bound register. - */ -static inline uint_xlen_t csr_read_mbound(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, mbound" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_mbound(uint_xlen_t value) { - __asm__ volatile ("csrw mbound, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_mbound(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, mbound, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * mibase - MRW - Instruction base register. - */ -static inline uint_xlen_t csr_read_mibase(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, mibase" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_mibase(uint_xlen_t value) { - __asm__ volatile ("csrw mibase, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_mibase(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, mibase, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * mibound - MRW - Instruction bound register. - */ -static inline uint_xlen_t csr_read_mibound(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, mibound" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_mibound(uint_xlen_t value) { - __asm__ volatile ("csrw mibound, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_mibound(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, mibound, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * mdbase - MRW - Data base register. - */ -static inline uint_xlen_t csr_read_mdbase(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, mdbase" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_mdbase(uint_xlen_t value) { - __asm__ volatile ("csrw mdbase, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_mdbase(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, mdbase, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * mdbound - MRW - Data bound register. - */ -static inline uint_xlen_t csr_read_mdbound(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, mdbound" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_mdbound(uint_xlen_t value) { - __asm__ volatile ("csrw mdbound, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_mdbound(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, mdbound, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * pmpcfg0 - MRW - Physical memory protection configuration. - */ -static inline uint_xlen_t csr_read_pmpcfg0(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, pmpcfg0" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_pmpcfg0(uint_xlen_t value) { - __asm__ volatile ("csrw pmpcfg0, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_pmpcfg0(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, pmpcfg0, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * pmpcfg1 - MRW - Physical memory protection configuration, RV32 only. - */ -static inline uint_xlen_t csr_read_pmpcfg1(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, pmpcfg1" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_pmpcfg1(uint_xlen_t value) { - __asm__ volatile ("csrw pmpcfg1, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_pmpcfg1(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, pmpcfg1, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * pmpcfg2 - MRW - Physical memory protection configuration. - */ -static inline uint_xlen_t csr_read_pmpcfg2(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, pmpcfg2" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_pmpcfg2(uint_xlen_t value) { - __asm__ volatile ("csrw pmpcfg2, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_pmpcfg2(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, pmpcfg2, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * pmpcfg3 - MRW - Physical memory protection configuration, RV32 only. - */ -static inline uint_xlen_t csr_read_pmpcfg3(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, pmpcfg3" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_pmpcfg3(uint_xlen_t value) { - __asm__ volatile ("csrw pmpcfg3, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_pmpcfg3(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, pmpcfg3, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * pmpaddr0 - MRW - Physical memory protection address register. - */ -static inline uint_xlen_t csr_read_pmpaddr0(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, pmpaddr0" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_pmpaddr0(uint_xlen_t value) { - __asm__ volatile ("csrw pmpaddr0, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_pmpaddr0(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, pmpaddr0, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * pmpaddr1 - MRW - Physical memory protection address register. - */ -static inline uint_xlen_t csr_read_pmpaddr1(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, pmpaddr1" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_pmpaddr1(uint_xlen_t value) { - __asm__ volatile ("csrw pmpaddr1, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_pmpaddr1(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, pmpaddr1, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * pmpaddr15 - MRW - Physical memory protection address register. - */ -static inline uint_xlen_t csr_read_pmpaddr15(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, pmpaddr15" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_pmpaddr15(uint_xlen_t value) { - __asm__ volatile ("csrw pmpaddr15, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_pmpaddr15(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, pmpaddr15, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * mhpmcounter4 - MRW - Machine performance-monitoring counter. - */ -static inline uint_xlen_t csr_read_mhpmcounter4(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, mhpmcounter4" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_mhpmcounter4(uint_xlen_t value) { - __asm__ volatile ("csrw mhpmcounter4, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_mhpmcounter4(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, mhpmcounter4, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * mhpmcounter31 - MRW - Machine performance-monitoring counter. - */ -static inline uint_xlen_t csr_read_mhpmcounter31(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, mhpmcounter31" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_mhpmcounter31(uint_xlen_t value) { - __asm__ volatile ("csrw mhpmcounter31, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_mhpmcounter31(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, mhpmcounter31, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * mcycleh - MRW - Upper 32 bits of mcycle, RV32I only. - */ -static inline uint32_t csr_read_mcycleh(void) { - uint_csr32_t value; - __asm__ volatile ("csrr %0, mcycleh" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_mcycleh(uint_csr32_t value) { - __asm__ volatile ("csrw mcycleh, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint32_t csr_read_write_mcycleh(uint32_t new_value) { - uint_csr32_t prev_value; - __asm__ volatile ("csrrw %0, mcycleh, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * minstreth - MRW - Upper 32 bits of minstret, RV32I only. - */ -static inline uint32_t csr_read_minstreth(void) { - uint_csr32_t value; - __asm__ volatile ("csrr %0, minstreth" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_minstreth(uint_csr32_t value) { - __asm__ volatile ("csrw minstreth, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint32_t csr_read_write_minstreth(uint32_t new_value) { - uint_csr32_t prev_value; - __asm__ volatile ("csrrw %0, minstreth, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * mhpmcounter3h - MRW - Upper 32 bits of mhpmcounter3, RV32I only. - */ -static inline uint32_t csr_read_mhpmcounter3h(void) { - uint_csr32_t value; - __asm__ volatile ("csrr %0, mhpmcounter3h" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_mhpmcounter3h(uint_csr32_t value) { - __asm__ volatile ("csrw mhpmcounter3h, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint32_t csr_read_write_mhpmcounter3h(uint32_t new_value) { - uint_csr32_t prev_value; - __asm__ volatile ("csrrw %0, mhpmcounter3h, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * mhpmcounter4h - MRW - Upper 32 bits of mhpmcounter4, RV32I only. - */ -static inline uint32_t csr_read_mhpmcounter4h(void) { - uint_csr32_t value; - __asm__ volatile ("csrr %0, mhpmcounter4h" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_mhpmcounter4h(uint_csr32_t value) { - __asm__ volatile ("csrw mhpmcounter4h, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint32_t csr_read_write_mhpmcounter4h(uint32_t new_value) { - uint_csr32_t prev_value; - __asm__ volatile ("csrrw %0, mhpmcounter4h, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * mhpmcounter31h - MRW - Upper 32 bits of mhpmcounter31, RV32I only. - */ -static inline uint32_t csr_read_mhpmcounter31h(void) { - uint_csr32_t value; - __asm__ volatile ("csrr %0, mhpmcounter31h" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_mhpmcounter31h(uint_csr32_t value) { - __asm__ volatile ("csrw mhpmcounter31h, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint32_t csr_read_write_mhpmcounter31h(uint32_t new_value) { - uint_csr32_t prev_value; - __asm__ volatile ("csrrw %0, mhpmcounter31h, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * mhpmevent4 - MRW - Machine performance-monitoring event selector. - */ -static inline uint_xlen_t csr_read_mhpmevent4(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, mhpmevent4" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_mhpmevent4(uint_xlen_t value) { - __asm__ volatile ("csrw mhpmevent4, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_mhpmevent4(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, mhpmevent4, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * mhpmevent31 - MRW - Machine performance-monitoring event selector. - */ -static inline uint_xlen_t csr_read_mhpmevent31(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, mhpmevent31" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_mhpmevent31(uint_xlen_t value) { - __asm__ volatile ("csrw mhpmevent31, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_mhpmevent31(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, mhpmevent31, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * tselect - MRW - Debug/Trace trigger register select. - */ -static inline uint_xlen_t csr_read_tselect(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, tselect" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_tselect(uint_xlen_t value) { - __asm__ volatile ("csrw tselect, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_tselect(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, tselect, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * tdata1 - MRW - First Debug/Trace trigger data register. - */ -static inline uint_xlen_t csr_read_tdata1(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, tdata1" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_tdata1(uint_xlen_t value) { - __asm__ volatile ("csrw tdata1, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_tdata1(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, tdata1, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * tdata2 - MRW - Second Debug/Trace trigger data register. - */ -static inline uint_xlen_t csr_read_tdata2(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, tdata2" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_tdata2(uint_xlen_t value) { - __asm__ volatile ("csrw tdata2, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_tdata2(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, tdata2, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * tdata3 - MRW - Third Debug/Trace trigger data register. - */ -static inline uint_xlen_t csr_read_tdata3(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, tdata3" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_tdata3(uint_xlen_t value) { - __asm__ volatile ("csrw tdata3, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_tdata3(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, tdata3, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * dcsr - DRW - Debug control and status register. - */ -static inline uint_xlen_t csr_read_dcsr(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, dcsr" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_dcsr(uint_xlen_t value) { - __asm__ volatile ("csrw dcsr, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_dcsr(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, dcsr, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * dpc - DRW - Debug PC. - */ -static inline uint_xlen_t csr_read_dpc(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, dpc" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_dpc(uint_xlen_t value) { - __asm__ volatile ("csrw dpc, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_dpc(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, dpc, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * dscratch0 - DRW - Debug scratch register 0. - */ -static inline uint_xlen_t csr_read_dscratch0(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, dscratch0" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_dscratch0(uint_xlen_t value) { - __asm__ volatile ("csrw dscratch0, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_dscratch0(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, dscratch0, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * dscratch1 - DRW - Debug scratch register 1. - */ -static inline uint_xlen_t csr_read_dscratch1(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, dscratch1" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_dscratch1(uint_xlen_t value) { - __asm__ volatile ("csrw dscratch1, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_dscratch1(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, dscratch1, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * hie - HRW - Hypervisor interrupt-enable register. - */ -static inline uint_xlen_t csr_read_hie(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, hie" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_hie(uint_xlen_t value) { - __asm__ volatile ("csrw hie, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_hie(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, hie, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * hgeie - HRW - Hypervisor guest external interrupt-enable register. - */ -static inline uint_xlen_t csr_read_hgeie(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, hgeie" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_hgeie(uint_xlen_t value) { - __asm__ volatile ("csrw hgeie, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_hgeie(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, hgeie, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * htval - HRW - Hypervisor bad guest physical address. - */ -static inline uint_xlen_t csr_read_htval(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, htval" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_htval(uint_xlen_t value) { - __asm__ volatile ("csrw htval, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_htval(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, htval, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * hip - HRW - Hypervisor interrupt pending. - */ -static inline uint_xlen_t csr_read_hip(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, hip" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_hip(uint_xlen_t value) { - __asm__ volatile ("csrw hip, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_hip(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, hip, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * htinst - HRW - Hypervisor trap instruction (transformed). - */ -static inline uint_xlen_t csr_read_htinst(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, htinst" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_htinst(uint_xlen_t value) { - __asm__ volatile ("csrw htinst, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_htinst(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, htinst, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * hgeip - HRO - Hypervisor guest external interrupt pending. - */ -static inline uint_xlen_t csr_read_hgeip(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, hgeip" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} - -/******************************************* - * mtinst - MRW - Machine trap instruction (transformed). - */ -static inline uint_xlen_t csr_read_mtinst(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, mtinst" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_mtinst(uint_xlen_t value) { - __asm__ volatile ("csrw mtinst, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_mtinst(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, mtinst, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -/******************************************* - * mtval2 - MRW - Machine bad guest physical address. - */ -static inline uint_xlen_t csr_read_mtval2(void) { - uint_xlen_t value; - __asm__ volatile ("csrr %0, mtval2" - : "=r" (value) /* output : register */ - : /* input : none */ - : /* clobbers: none */); - return value; -} -static inline void csr_write_mtval2(uint_xlen_t value) { - __asm__ volatile ("csrw mtval2, %0" - : /* output: none */ - : "r" (value) /* input : from register */ - : /* clobbers: none */); -} -static inline uint_xlen_t csr_read_write_mtval2(uint_xlen_t new_value) { - uint_xlen_t prev_value; - __asm__ volatile ("csrrw %0, mtval2, %1" - : "=r" (prev_value) /* output: register %0 */ - : "r" (new_value) /* input : register */ - : /* clobbers: none */); - return prev_value; -} - -#if defined(__cplusplus) -} -#endif - -#endif // #define RISCV_CSR_H diff --git a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Startup/Startup.c b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Startup/Startup.c index 45457473f..e57215024 100644 --- a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Startup/Startup.c +++ b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Startup/Startup.c @@ -1,3 +1,12 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright Christopher Kormanyos 2026. +// Distributed under the Boost Software License, +// Version 1.0. (See accompanying file LICENSE_1_0.txt +// or copy at http://www.boost.org/LICENSE_1_0.txt) +// + +// Originally from: + // *************************************************************************************** // Filename : Startup.c // diff --git a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Startup/boot.s b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Startup/boot.s index e207f85ee..2af61f36c 100644 --- a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Startup/boot.s +++ b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Startup/boot.s @@ -1,3 +1,14 @@ +/****************************************************************************************** +/////////////////////////////////////////////////////////////////////////////// +// Copyright Christopher Kormanyos 2026. +// Distributed under the Boost Software License, +// Version 1.0. (See accompanying file LICENSE_1_0.txt +// or copy at http://www.boost.org/LICENSE_1_0.txt) +// + +// Originally from: +******************************************************************************************/ + /****************************************************************************************** Filename : boot.s diff --git a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Startup/intvect.c b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Startup/intvect.c index 077bc0493..391b26a49 100644 --- a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Startup/intvect.c +++ b/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Startup/intvect.c @@ -1,3 +1,12 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright Christopher Kormanyos 2026. +// Distributed under the Boost Software License, +// Version 1.0. (See accompanying file LICENSE_1_0.txt +// or copy at http://www.boost.org/LICENSE_1_0.txt) +// + +// Originally from: + /****************************************************************************************************** Filename : intvect.c