diff --git a/.github/workflows/real-time-cpp.yml b/.github/workflows/real-time-cpp.yml index 2fafaae2f..d4bcbb186 100644 --- a/.github/workflows/real-time-cpp.yml +++ b/.github/workflows/real-time-cpp.yml @@ -236,7 +236,7 @@ jobs: strategy: fail-fast: false matrix: - suite: [ bl602_sifive_e24_riscv, riscvfe310, wch_ch32v307, xtensa_esp32_p4, xtensa_esp32_s3_riscv_cop ] + suite: [ bl602_sifive_e24_riscv, esp32p4_riscv_soc, riscvfe310, wch_ch32v307, xtensa_esp32_s3_riscv_cop ] steps: - uses: actions/checkout@v4 with: diff --git a/readme.md b/readme.md index 6473bda34..f9d1a5343 100644 --- a/readme.md +++ b/readme.md @@ -75,6 +75,7 @@ The reference application supports the following targets (in alpha-numeric order | `bcm2835_raspi_b` | RaspberryPi(R) Zero with ARM1176-JZFS(TM) | X | | `bl602_sifive_e24_riscv` | BL602 single-core RISC-V (SiFive E24) | X | | `Debug`/`Release` | PC on `Win*` via MSVC x64 compiler `Debug`/`Release` | | +| `esp32p4_riscv_soc` | Espressif ESP32-P4 multicore RISC-V SoC | X | | `host` | PC/Workstation on `Win*`/`mingw64`/`*nix` via host compiler | | | `lpc11c24` | NXP(R) OM13093 LPC11C24 board ARM(R) Cortex(R)-M0+ | | | `nxp_imxrt1062` | Teensy 4.0 Board / NXP(R) iMXRT1062 ARM(R) Cortex(R)-M7 | X | @@ -96,7 +97,6 @@ The reference application supports the following targets (in alpha-numeric order | `wch_ch32v307` | WCH CH32v307 RISC-V board | | | `wch_ch32v307_llvm` | WCH CH32v307 RISC-V board (but using an LLVM toolchain) | | | `x86_64-w64-mingw32` | PC on `Win*`/`mingw64` via GNU/GCC x86_x64 compiler | | -| `xtensa_esp32_p4` | Espressif (XTENSA) ESP32-P4 multicore RISC-V SoC | X | | `xtensa_esp32_s3` | Espressif (XTENSA) NodeMCU ESP32-S3 | X | | `xtensa32` | Espressif (XTENSA) NodeMCU ESP32 | X | diff --git a/ref_app/ref_app.sln b/ref_app/ref_app.sln index bc2dabede..efe3f38b5 100644 --- a/ref_app/ref_app.sln +++ b/ref_app/ref_app.sln @@ -53,6 +53,7 @@ Global target avr|x64 = target avr|x64 target bcm2835_raspi_b|x64 = target bcm2835_raspi_b|x64 target bl602_sifive_e24_riscv|x64 = target bl602_sifive_e24_riscv|x64 + target esp32p4_riscv_soc|x64 = target esp32p4_riscv_soc|x64 target lpc11c24|x64 = target lpc11c24|x64 target nxp_imxrt1062|x64 = target nxp_imxrt1062|x64 target r7fa4m1ab|x64 = target r7fa4m1ab|x64 @@ -73,7 +74,6 @@ Global target wch_ch32v307_llvm|x64 = target wch_ch32v307_llvm|x64 target wch_ch32v307|x64 = target wch_ch32v307|x64 target x86_64-w64-mingw32|x64 = target x86_64-w64-mingw32|x64 - target xtensa_esp32_p4|x64 = target xtensa_esp32_p4|x64 target xtensa_esp32_s3_riscv_cop|x64 = target xtensa_esp32_s3_riscv_cop|x64 target xtensa_esp32_s3|x64 = target xtensa_esp32_s3|x64 target xtensa32|x64 = target xtensa32|x64 @@ -90,6 +90,7 @@ Global {C8B59726-9319-45C3-8F11-F9F388FB6A2C}.target avr|x64.ActiveCfg = Release|x64 {C8B59726-9319-45C3-8F11-F9F388FB6A2C}.target bcm2835_raspi_b|x64.ActiveCfg = Release|x64 {C8B59726-9319-45C3-8F11-F9F388FB6A2C}.target bl602_sifive_e24_riscv|x64.ActiveCfg = Release|x64 + {C8B59726-9319-45C3-8F11-F9F388FB6A2C}.target esp32p4_riscv_soc|x64.ActiveCfg = Release|x64 {C8B59726-9319-45C3-8F11-F9F388FB6A2C}.target lpc11c24|x64.ActiveCfg = Release|x64 {C8B59726-9319-45C3-8F11-F9F388FB6A2C}.target nxp_imxrt1062|x64.ActiveCfg = Release|x64 {C8B59726-9319-45C3-8F11-F9F388FB6A2C}.target r7fa4m1ab|x64.ActiveCfg = Release|x64 @@ -110,7 +111,6 @@ Global {C8B59726-9319-45C3-8F11-F9F388FB6A2C}.target wch_ch32v307_llvm|x64.ActiveCfg = Release|x64 {C8B59726-9319-45C3-8F11-F9F388FB6A2C}.target wch_ch32v307|x64.ActiveCfg = Release|x64 {C8B59726-9319-45C3-8F11-F9F388FB6A2C}.target x86_64-w64-mingw32|x64.ActiveCfg = Release|x64 - {C8B59726-9319-45C3-8F11-F9F388FB6A2C}.target xtensa_esp32_p4|x64.ActiveCfg = Release|x64 {C8B59726-9319-45C3-8F11-F9F388FB6A2C}.target xtensa_esp32_s3_riscv_cop|x64.ActiveCfg = Release|x64 {C8B59726-9319-45C3-8F11-F9F388FB6A2C}.target xtensa_esp32_s3|x64.ActiveCfg = Release|x64 {C8B59726-9319-45C3-8F11-F9F388FB6A2C}.target xtensa32|x64.ActiveCfg = Release|x64 @@ -130,6 +130,8 @@ Global {30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target bcm2835_raspi_b|x64.Build.0 = target bcm2835_raspi_b|x64 {30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target bl602_sifive_e24_riscv|x64.ActiveCfg = target bl602_sifive_e24_riscv|x64 {30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target bl602_sifive_e24_riscv|x64.Build.0 = target bl602_sifive_e24_riscv|x64 + {30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target esp32p4_riscv_soc|x64.ActiveCfg = target esp32p4_riscv_soc|x64 + {30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target esp32p4_riscv_soc|x64.Build.0 = target esp32p4_riscv_soc|x64 {30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target lpc11c24|x64.ActiveCfg = target lpc11c24|x64 {30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target lpc11c24|x64.Build.0 = target lpc11c24|x64 {30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target nxp_imxrt1062|x64.ActiveCfg = target nxp_imxrt1062|x64 @@ -170,8 +172,6 @@ Global {30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target wch_ch32v307|x64.Build.0 = target wch_ch32v307|x64 {30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target x86_64-w64-mingw32|x64.ActiveCfg = target x86_64-w64-mingw32|x64 {30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target x86_64-w64-mingw32|x64.Build.0 = target x86_64-w64-mingw32|x64 - {30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target xtensa_esp32_p4|x64.ActiveCfg = target xtensa_esp32_p4|x64 - {30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target xtensa_esp32_p4|x64.Build.0 = target xtensa_esp32_p4|x64 {30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target xtensa_esp32_s3_riscv_cop|x64.ActiveCfg = target xtensa_esp32_s3_riscv_cop|x64 {30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target xtensa_esp32_s3_riscv_cop|x64.Build.0 = target xtensa_esp32_s3_riscv_cop|x64 {30CE370B-40F3-4BCD-8986-64AAFF8971BD}.target xtensa_esp32_s3|x64.ActiveCfg = target xtensa_esp32_s3|x64 diff --git a/ref_app/ref_app.vcxproj b/ref_app/ref_app.vcxproj index 9faabde92..e5d74e585 100644 --- a/ref_app/ref_app.vcxproj +++ b/ref_app/ref_app.vcxproj @@ -513,6 +513,46 @@ true true + + true + true + + + true + true + + + true + true + + + true + true + + + true + true + + + true + true + + + true + true + + + true + true + + + true + true + + + true + true + @@ -1401,46 +1441,6 @@ true true - - true - true - - - true - true - - - true - true - - - true - true - - - true - true - - - true - true - - - true - true - - - true - true - - - true - true - - - true - true - true true @@ -2045,6 +2045,62 @@ true true + + true + true + + + true + true + + + true + true + + + true + true + + + true + true + + + true + true + + + true + true + + + true + true + + + true + true + + + true + true + + + true + true + + + true + true + + + true + true + + + true + true + @@ -3273,62 +3329,6 @@ true true - - true - true - - - true - true - - - true - true - - - true - true - - - true - true - - - true - true - - - true - true - - - true - true - - - true - true - - - true - true - - - true - true - - - true - true - - - true - true - - - true - true - true true diff --git a/ref_app/ref_app.vcxproj.filters b/ref_app/ref_app.vcxproj.filters index 3c8d1f3da..4b0018f4e 100644 --- a/ref_app/ref_app.vcxproj.filters +++ b/ref_app/ref_app.vcxproj.filters @@ -287,7 +287,7 @@ {40be70da-9086-46f9-b158-4dc468860fc7} - + {cc6519dd-1588-4aed-9bd1-c4cc22a5e560} @@ -1372,35 +1372,35 @@ src\mcal\r7fa4m1ab - - src\mcal\xtensa_esp32_p4 + + src\mcal\esp32p4_riscv_soc - - src\mcal\xtensa_esp32_p4 + + src\mcal\esp32p4_riscv_soc - - src\mcal\xtensa_esp32_p4 + + src\mcal\esp32p4_riscv_soc - - src\mcal\xtensa_esp32_p4 + + src\mcal\esp32p4_riscv_soc - - src\mcal\xtensa_esp32_p4 + + src\mcal\esp32p4_riscv_soc - - src\mcal\xtensa_esp32_p4 + + src\mcal\esp32p4_riscv_soc - - src\mcal\xtensa_esp32_p4 + + src\mcal\esp32p4_riscv_soc - - src\mcal\xtensa_esp32_p4 + + src\mcal\esp32p4_riscv_soc - - src\mcal\xtensa_esp32_p4 + + src\mcal\esp32p4_riscv_soc - - src\mcal\xtensa_esp32_p4 + + src\mcal\esp32p4_riscv_soc @@ -3153,47 +3153,47 @@ src\mcal\r7fa4m1ab - - src\mcal\xtensa_esp32_p4 + + src\mcal\esp32p4_riscv_soc - - src\mcal\xtensa_esp32_p4 + + src\mcal\esp32p4_riscv_soc - - src\mcal\xtensa_esp32_p4 + + src\mcal\esp32p4_riscv_soc - - src\mcal\xtensa_esp32_p4 + + src\mcal\esp32p4_riscv_soc - - src\mcal\xtensa_esp32_p4 + + src\mcal\esp32p4_riscv_soc - - src\mcal\xtensa_esp32_p4 + + src\mcal\esp32p4_riscv_soc - - src\mcal\xtensa_esp32_p4 + + src\mcal\esp32p4_riscv_soc - - src\mcal\xtensa_esp32_p4 + + src\mcal\esp32p4_riscv_soc - - src\mcal\xtensa_esp32_p4 + + src\mcal\esp32p4_riscv_soc - - src\mcal\xtensa_esp32_p4 + + src\mcal\esp32p4_riscv_soc - - src\mcal\xtensa_esp32_p4 + + src\mcal\esp32p4_riscv_soc - - src\mcal\xtensa_esp32_p4 + + src\mcal\esp32p4_riscv_soc - - src\mcal\xtensa_esp32_p4 + + src\mcal\esp32p4_riscv_soc - - src\mcal\xtensa_esp32_p4 + + src\mcal\esp32p4_riscv_soc diff --git a/ref_app/src/app/benchmark/readme.md b/ref_app/src/app/benchmark/readme.md index d9e2d4134..8bcaf463a 100644 --- a/ref_app/src/app/benchmark/readme.md +++ b/ref_app/src/app/benchmark/readme.md @@ -85,7 +85,7 @@ The benchmark used is a ${\sim}100$ decimal digit AGM $\pi$ calculation. |---------------------------|-----------------|------------| | `am6254_soc` | 0.37 | 1.0 | | `am335x` | 1.5 | 4.1 | -| `xtensa_esp32_p4` | 2.5 | 6.8 | +| `esp32p4_riscv_soc` | 2.5 | 6.8 | | `stm32f446` | 5.1 | 14 | | `rpi_pico2_rp2350` | 6.3 | 17 | | `wch_ch32v307` | 8.0 | 22 | @@ -122,7 +122,7 @@ running the benchmark in about $10~{\text{ms}}$. Running on only one core (core0) of the $32$-bit controller of the `xtensa_esp32_s3` board results in a runtime of $9.1~{\text{ms}}$ for the calculation. -The next generation `xtensa_esp32_p4` with a dual RISC-V core +The next generation `esp32p4_riscv_soc` with a dual RISC-V core architecture is significantly faster coming in at $2.5~{\text{ms}}$ (running the benchmark on one core). diff --git a/ref_app/src/mcal/xtensa_esp32_p4/mcal_benchmark.h b/ref_app/src/mcal/esp32p4_riscv_soc/mcal_benchmark.h similarity index 100% rename from ref_app/src/mcal/xtensa_esp32_p4/mcal_benchmark.h rename to ref_app/src/mcal/esp32p4_riscv_soc/mcal_benchmark.h diff --git a/ref_app/src/mcal/xtensa_esp32_p4/mcal_cpu.cpp b/ref_app/src/mcal/esp32p4_riscv_soc/mcal_cpu.cpp similarity index 100% rename from ref_app/src/mcal/xtensa_esp32_p4/mcal_cpu.cpp rename to ref_app/src/mcal/esp32p4_riscv_soc/mcal_cpu.cpp diff --git a/ref_app/src/mcal/xtensa_esp32_p4/mcal_cpu.h b/ref_app/src/mcal/esp32p4_riscv_soc/mcal_cpu.h similarity index 100% rename from ref_app/src/mcal/xtensa_esp32_p4/mcal_cpu.h rename to ref_app/src/mcal/esp32p4_riscv_soc/mcal_cpu.h diff --git a/ref_app/src/mcal/xtensa_esp32_p4/mcal_eep.cpp b/ref_app/src/mcal/esp32p4_riscv_soc/mcal_eep.cpp similarity index 100% rename from ref_app/src/mcal/xtensa_esp32_p4/mcal_eep.cpp rename to ref_app/src/mcal/esp32p4_riscv_soc/mcal_eep.cpp diff --git a/ref_app/src/mcal/xtensa_esp32_p4/mcal_eep.h b/ref_app/src/mcal/esp32p4_riscv_soc/mcal_eep.h similarity index 100% rename from ref_app/src/mcal/xtensa_esp32_p4/mcal_eep.h rename to ref_app/src/mcal/esp32p4_riscv_soc/mcal_eep.h diff --git a/ref_app/src/mcal/xtensa_esp32_p4/mcal_gpt.cpp b/ref_app/src/mcal/esp32p4_riscv_soc/mcal_gpt.cpp similarity index 100% rename from ref_app/src/mcal/xtensa_esp32_p4/mcal_gpt.cpp rename to ref_app/src/mcal/esp32p4_riscv_soc/mcal_gpt.cpp diff --git a/ref_app/src/mcal/xtensa_esp32_p4/mcal_gpt.h b/ref_app/src/mcal/esp32p4_riscv_soc/mcal_gpt.h similarity index 100% rename from ref_app/src/mcal/xtensa_esp32_p4/mcal_gpt.h rename to ref_app/src/mcal/esp32p4_riscv_soc/mcal_gpt.h diff --git a/ref_app/src/mcal/xtensa_esp32_p4/mcal_irq.cpp b/ref_app/src/mcal/esp32p4_riscv_soc/mcal_irq.cpp similarity index 100% rename from ref_app/src/mcal/xtensa_esp32_p4/mcal_irq.cpp rename to ref_app/src/mcal/esp32p4_riscv_soc/mcal_irq.cpp diff --git a/ref_app/src/mcal/xtensa_esp32_p4/mcal_irq.h b/ref_app/src/mcal/esp32p4_riscv_soc/mcal_irq.h similarity index 100% rename from ref_app/src/mcal/xtensa_esp32_p4/mcal_irq.h rename to ref_app/src/mcal/esp32p4_riscv_soc/mcal_irq.h diff --git a/ref_app/src/mcal/xtensa_esp32_p4/mcal_led.cpp b/ref_app/src/mcal/esp32p4_riscv_soc/mcal_led.cpp similarity index 100% rename from ref_app/src/mcal/xtensa_esp32_p4/mcal_led.cpp rename to ref_app/src/mcal/esp32p4_riscv_soc/mcal_led.cpp diff --git a/ref_app/src/mcal/xtensa_esp32_p4/mcal_led.h b/ref_app/src/mcal/esp32p4_riscv_soc/mcal_led.h similarity index 100% rename from ref_app/src/mcal/xtensa_esp32_p4/mcal_led.h rename to ref_app/src/mcal/esp32p4_riscv_soc/mcal_led.h diff --git a/ref_app/src/mcal/xtensa_esp32_p4/mcal_memory_progmem.h b/ref_app/src/mcal/esp32p4_riscv_soc/mcal_memory_progmem.h similarity index 100% rename from ref_app/src/mcal/xtensa_esp32_p4/mcal_memory_progmem.h rename to ref_app/src/mcal/esp32p4_riscv_soc/mcal_memory_progmem.h diff --git a/ref_app/src/mcal/xtensa_esp32_p4/mcal_osc.cpp b/ref_app/src/mcal/esp32p4_riscv_soc/mcal_osc.cpp similarity index 100% rename from ref_app/src/mcal/xtensa_esp32_p4/mcal_osc.cpp rename to ref_app/src/mcal/esp32p4_riscv_soc/mcal_osc.cpp diff --git a/ref_app/src/mcal/xtensa_esp32_p4/mcal_osc.h b/ref_app/src/mcal/esp32p4_riscv_soc/mcal_osc.h similarity index 100% rename from ref_app/src/mcal/xtensa_esp32_p4/mcal_osc.h rename to ref_app/src/mcal/esp32p4_riscv_soc/mcal_osc.h diff --git a/ref_app/src/mcal/xtensa_esp32_p4/mcal_port.cpp b/ref_app/src/mcal/esp32p4_riscv_soc/mcal_port.cpp similarity index 100% rename from ref_app/src/mcal/xtensa_esp32_p4/mcal_port.cpp rename to ref_app/src/mcal/esp32p4_riscv_soc/mcal_port.cpp diff --git a/ref_app/src/mcal/xtensa_esp32_p4/mcal_port.h b/ref_app/src/mcal/esp32p4_riscv_soc/mcal_port.h similarity index 100% rename from ref_app/src/mcal/xtensa_esp32_p4/mcal_port.h rename to ref_app/src/mcal/esp32p4_riscv_soc/mcal_port.h diff --git a/ref_app/src/mcal/xtensa_esp32_p4/mcal_pwm.cpp b/ref_app/src/mcal/esp32p4_riscv_soc/mcal_pwm.cpp similarity index 100% rename from ref_app/src/mcal/xtensa_esp32_p4/mcal_pwm.cpp rename to ref_app/src/mcal/esp32p4_riscv_soc/mcal_pwm.cpp diff --git a/ref_app/src/mcal/xtensa_esp32_p4/mcal_pwm.h b/ref_app/src/mcal/esp32p4_riscv_soc/mcal_pwm.h similarity index 100% rename from ref_app/src/mcal/xtensa_esp32_p4/mcal_pwm.h rename to ref_app/src/mcal/esp32p4_riscv_soc/mcal_pwm.h diff --git a/ref_app/src/mcal/xtensa_esp32_p4/mcal_reg.h b/ref_app/src/mcal/esp32p4_riscv_soc/mcal_reg.h similarity index 100% rename from ref_app/src/mcal/xtensa_esp32_p4/mcal_reg.h rename to ref_app/src/mcal/esp32p4_riscv_soc/mcal_reg.h diff --git a/ref_app/src/mcal/xtensa_esp32_p4/mcal_ser.h b/ref_app/src/mcal/esp32p4_riscv_soc/mcal_ser.h similarity index 100% rename from ref_app/src/mcal/xtensa_esp32_p4/mcal_ser.h rename to ref_app/src/mcal/esp32p4_riscv_soc/mcal_ser.h diff --git a/ref_app/src/mcal/xtensa_esp32_p4/mcal_spi.cpp b/ref_app/src/mcal/esp32p4_riscv_soc/mcal_spi.cpp similarity index 100% rename from ref_app/src/mcal/xtensa_esp32_p4/mcal_spi.cpp rename to ref_app/src/mcal/esp32p4_riscv_soc/mcal_spi.cpp diff --git a/ref_app/src/mcal/xtensa_esp32_p4/mcal_spi.h b/ref_app/src/mcal/esp32p4_riscv_soc/mcal_spi.h similarity index 100% rename from ref_app/src/mcal/xtensa_esp32_p4/mcal_spi.h rename to ref_app/src/mcal/esp32p4_riscv_soc/mcal_spi.h diff --git a/ref_app/src/mcal/xtensa_esp32_p4/mcal_wdg.cpp b/ref_app/src/mcal/esp32p4_riscv_soc/mcal_wdg.cpp similarity index 100% rename from ref_app/src/mcal/xtensa_esp32_p4/mcal_wdg.cpp rename to ref_app/src/mcal/esp32p4_riscv_soc/mcal_wdg.cpp diff --git a/ref_app/src/mcal/xtensa_esp32_p4/mcal_wdg.h b/ref_app/src/mcal/esp32p4_riscv_soc/mcal_wdg.h similarity index 100% rename from ref_app/src/mcal/xtensa_esp32_p4/mcal_wdg.h rename to ref_app/src/mcal/esp32p4_riscv_soc/mcal_wdg.h diff --git a/ref_app/target.vcxproj b/ref_app/target.vcxproj index 990577012..e42c6e18d 100644 --- a/ref_app/target.vcxproj +++ b/ref_app/target.vcxproj @@ -113,8 +113,8 @@ target xtensa32 x64 - - target xtensa_esp32_p4 + + target esp32p4_riscv_soc x64 @@ -266,7 +266,7 @@ true v143 - + Makefile Unicode true @@ -426,7 +426,7 @@ - + @@ -476,7 +476,7 @@ target\build\build.bat stm32h7a3 target\build\build.bat xtensa32 target\build\build.bat xtensa_esp32_s3 - target\build\build.bat xtensa_esp32_p4 + target\build\build.bat esp32p4_riscv_soc target\build\build.bat xtensa_esp32_s3_riscv_cop target\build\build.bat stm32f429 target\build\build.bat am335x @@ -507,7 +507,7 @@ target\build\build.bat stm32h7a3 rebuild target\build\build.bat xtensa32 rebuild target\build\build.bat xtensa_esp32_s3 rebuild - target\build\build.bat xtensa_esp32_p4 rebuild + target\build\build.bat esp32p4_riscv_soc rebuild target\build\build.bat xtensa_esp32_s3_riscv_cop rebuild target\build\build.bat stm32f429 rebuild @@ -539,7 +539,7 @@ target\build\build.bat stm32h7a3 clean_all target\build\build.bat xtensa32 clean_all target\build\build.bat xtensa_esp32_s3 clean_all - target\build\build.bat xtensa_esp32_p4 clean_all + target\build\build.bat esp32p4_riscv_soc clean_all target\build\build.bat xtensa_esp32_s3_riscv_cop clean_all target\build\build.bat stm32f429 clean_all @@ -571,7 +571,7 @@ $(SolutionDir)bin\ref_app.hex $(SolutionDir)bin\ref_app.hex $(SolutionDir)bin\ref_app.hex - $(SolutionDir)bin\ref_app.hex + $(SolutionDir)bin\ref_app.hex $(SolutionDir)bin\ref_app.hex $(SolutionDir)bin\ref_app.hex $(SolutionDir)bin\ref_app.hex @@ -603,7 +603,7 @@ ESP_PLATFORM; MBEDTLS_CONFIG_FILE="mbedtls/esp_config.h"; HAVE_CONFIG_H; GCC_NOT_5_2_0=1; WITH_POSIX; F_CPU=240000000L; ARDUINO=10813; ARDUINO_ESP32_DEV; ARDUINO_ARCH_ESP32; ARDUINO_BOARD="ESP32_DEV"; ARDUINO_VARIANT="esp32"; ESP32; CORE_DEBUG_LEVEL=0 - + @@ -634,7 +634,7 @@ $(SolutionDir)src\util\STL_C++XX_stdfloat;$(SolutionDir)src\util\STL;$(SolutionDir)/src;$(SolutionDir)/src/mcal/stm32f446 $(ProjectDir)/src/util/STL_C++XX_stdfloat; $(ProjectDir)/src/util/STL; $(ProjectDir)/src; $(ProjectDir)/src/mcal/xtensa32; $(ProjectDir)/src/util/STL_C++XX_stdfloat; $(ProjectDir)/src/util/STL; $(ProjectDir)/src; $(ProjectDir)/src/mcal/xtensa_esp32_s3; - $(ProjectDir)/target/micros/xtensa_esp32_p4/startup/Code; $(ProjectDir)/target/micros/xtensa_esp32_p4/startup/Code/Appli; $(ProjectDir)/target/micros/xtensa_esp32_p4/startup/Code/Mcal; $(ProjectDir)/target/micros/xtensa_esp32_p4/startup/Code/Startup; $(ProjectDir)/src; $(ProjectDir)/src/mcal/xtensa_esp32_p4; + $(ProjectDir)/target/micros/esp32p4_riscv_soc/startup/Code; $(ProjectDir)/target/micros/esp32p4_riscv_soc/startup/Code/Appli; $(ProjectDir)/target/micros/esp32p4_riscv_soc/startup/Code/Mcal; $(ProjectDir)/target/micros/esp32p4_riscv_soc/startup/Code/Startup; $(ProjectDir)/src; $(ProjectDir)/src/mcal/esp32p4_riscv_soc; $(ProjectDir)/src/util/STL_C++XX_stdfloat; $(ProjectDir)/src/util/STL; $(ProjectDir)/src; $(ProjectDir)/src/mcal/xtensa_esp32_s3; $(SolutionDir)src\util\STL_C++XX_stdfloat;$(SolutionDir)src\util\STL;$(SolutionDir)/src;$(SolutionDir)/src/mcal/stm32f429 $(SolutionDir)/src;$(SolutionDir)/src/mcal/am335x @@ -665,7 +665,7 @@ - + @@ -696,7 +696,7 @@ - + @@ -727,7 +727,7 @@ - + @@ -971,7 +971,7 @@ $(SolutionDir)tmp\log\ref_app.log - + $(SolutionDir)tmp\log\ref_app.log @@ -1068,6 +1068,10 @@ + + + + @@ -1153,10 +1157,6 @@ - - - - @@ -1197,6 +1197,13 @@ + + + + + + + @@ -1283,13 +1290,6 @@ - - - - - - - diff --git a/ref_app/target.vcxproj.filters b/ref_app/target.vcxproj.filters index b27cbdfcc..371d669d2 100644 --- a/ref_app/target.vcxproj.filters +++ b/ref_app/target.vcxproj.filters @@ -340,25 +340,25 @@ {e85df680-7e70-4f5d-87c0-73dbb822c1ba} - + {4ce9fafb-0c5d-4593-b8f8-c16c3fc11c9c} - + {c72d0dcc-9b1a-4a96-b2e4-0d2f5b65711c} - + {cdb1aef0-d686-4790-8231-17b7cd6185cf} - + {b2aaad4e-1735-4de1-a6dc-ac965b62d05e} - + {a4e34517-143d-491c-925b-5d3e7d7bd195} - + {17889d6f-9174-40cb-bcad-01e3995207e5} - + {65c5c603-a019-41d0-8a19-3cadaca7fd3c} @@ -801,17 +801,17 @@ micros\r7fa4m1ab\make - - micros\xtensa_esp32_p4\make + + micros\esp32p4_riscv_soc\make - - micros\xtensa_esp32_p4\make + + micros\esp32p4_riscv_soc\make - - micros\xtensa_esp32_p4\make + + micros\esp32p4_riscv_soc\make - - micros\xtensa_esp32_p4\startup\Code\Startup + + micros\esp32p4_riscv_soc\startup\Code\Startup @@ -1166,26 +1166,26 @@ micros\r7fa4m1ab\startup - - micros\xtensa_esp32_p4\startup\Code\Appli + + micros\esp32p4_riscv_soc\startup - - micros\xtensa_esp32_p4\startup\Code\Startup + + micros\esp32p4_riscv_soc\startup - - micros\xtensa_esp32_p4\startup\Code\Startup + + micros\esp32p4_riscv_soc\startup\Code\Appli - - micros\xtensa_esp32_p4\startup\Code\Appli + + micros\esp32p4_riscv_soc\startup\Code\Appli - - micros\xtensa_esp32_p4\startup + + micros\esp32p4_riscv_soc\startup\Code\Startup - - micros\xtensa_esp32_p4\startup + + micros\esp32p4_riscv_soc\startup\Code\Startup - - micros\xtensa_esp32_p4\startup\Code\StdLib + + micros\esp32p4_riscv_soc\startup\Code\StdLib diff --git a/ref_app/target/micros/xtensa_esp32_p4/make/xtensa_esp32_p4.ld b/ref_app/target/micros/esp32p4_riscv_soc/make/esp32p4_riscv_soc.ld similarity index 100% rename from ref_app/target/micros/xtensa_esp32_p4/make/xtensa_esp32_p4.ld rename to ref_app/target/micros/esp32p4_riscv_soc/make/esp32p4_riscv_soc.ld diff --git a/ref_app/target/micros/xtensa_esp32_p4/make/xtensa_esp32_p4_files.gmk b/ref_app/target/micros/esp32p4_riscv_soc/make/esp32p4_riscv_soc_files.gmk similarity index 100% rename from ref_app/target/micros/xtensa_esp32_p4/make/xtensa_esp32_p4_files.gmk rename to ref_app/target/micros/esp32p4_riscv_soc/make/esp32p4_riscv_soc_files.gmk diff --git a/ref_app/target/micros/xtensa_esp32_p4/make/xtensa_esp32_p4_flags.gmk b/ref_app/target/micros/esp32p4_riscv_soc/make/esp32p4_riscv_soc_flags.gmk similarity index 98% rename from ref_app/target/micros/xtensa_esp32_p4/make/xtensa_esp32_p4_flags.gmk rename to ref_app/target/micros/esp32p4_riscv_soc/make/esp32p4_riscv_soc_flags.gmk index 72dc8f211..a66a9c08c 100644 --- a/ref_app/target/micros/xtensa_esp32_p4/make/xtensa_esp32_p4_flags.gmk +++ b/ref_app/target/micros/esp32p4_riscv_soc/make/esp32p4_riscv_soc_flags.gmk @@ -20,7 +20,7 @@ WARN_FLAGS := TGT_ALLFLAGS = -O2 \ -march=rv32imafc_zicsr_zifencei_xesppie \ -mabi=ilp32f \ - -msmall-data-limit=32 \ + -msmall-data-limit=64 \ -mrelax \ -mrelax \ -fno-common \ diff --git a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Appli/main.c b/ref_app/target/micros/esp32p4_riscv_soc/startup/Code/Appli/main.c similarity index 100% rename from ref_app/target/micros/xtensa_esp32_p4/startup/Code/Appli/main.c rename to ref_app/target/micros/esp32p4_riscv_soc/startup/Code/Appli/main.c diff --git a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Appli/main_cores.cpp b/ref_app/target/micros/esp32p4_riscv_soc/startup/Code/Appli/main_cores.cpp similarity index 100% rename from ref_app/target/micros/xtensa_esp32_p4/startup/Code/Appli/main_cores.cpp rename to ref_app/target/micros/esp32p4_riscv_soc/startup/Code/Appli/main_cores.cpp diff --git a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/SBL/Output/SBL.bin b/ref_app/target/micros/esp32p4_riscv_soc/startup/Code/SBL/Output/SBL.bin similarity index 100% rename from ref_app/target/micros/xtensa_esp32_p4/startup/Code/SBL/Output/SBL.bin rename to ref_app/target/micros/esp32p4_riscv_soc/startup/Code/SBL/Output/SBL.bin diff --git a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/SBL/Output/SBL.elf b/ref_app/target/micros/esp32p4_riscv_soc/startup/Code/SBL/Output/SBL.elf similarity index 100% rename from ref_app/target/micros/xtensa_esp32_p4/startup/Code/SBL/Output/SBL.elf rename to ref_app/target/micros/esp32p4_riscv_soc/startup/Code/SBL/Output/SBL.elf diff --git a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/SBL/Output/SBL.hex b/ref_app/target/micros/esp32p4_riscv_soc/startup/Code/SBL/Output/SBL.hex similarity index 100% rename from ref_app/target/micros/xtensa_esp32_p4/startup/Code/SBL/Output/SBL.hex rename to ref_app/target/micros/esp32p4_riscv_soc/startup/Code/SBL/Output/SBL.hex diff --git a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/SBL/Output/SBL.map b/ref_app/target/micros/esp32p4_riscv_soc/startup/Code/SBL/Output/SBL.map similarity index 100% rename from ref_app/target/micros/xtensa_esp32_p4/startup/Code/SBL/Output/SBL.map rename to ref_app/target/micros/esp32p4_riscv_soc/startup/Code/SBL/Output/SBL.map diff --git a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/SBL/Output/SBL.readelf b/ref_app/target/micros/esp32p4_riscv_soc/startup/Code/SBL/Output/SBL.readelf similarity index 100% rename from ref_app/target/micros/xtensa_esp32_p4/startup/Code/SBL/Output/SBL.readelf rename to ref_app/target/micros/esp32p4_riscv_soc/startup/Code/SBL/Output/SBL.readelf diff --git a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Startup/Startup.c b/ref_app/target/micros/esp32p4_riscv_soc/startup/Code/Startup/Startup.c similarity index 100% rename from ref_app/target/micros/xtensa_esp32_p4/startup/Code/Startup/Startup.c rename to ref_app/target/micros/esp32p4_riscv_soc/startup/Code/Startup/Startup.c diff --git a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Startup/boot.s b/ref_app/target/micros/esp32p4_riscv_soc/startup/Code/Startup/boot.s similarity index 100% rename from ref_app/target/micros/xtensa_esp32_p4/startup/Code/Startup/boot.s rename to ref_app/target/micros/esp32p4_riscv_soc/startup/Code/Startup/boot.s diff --git a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/Startup/intvect.c b/ref_app/target/micros/esp32p4_riscv_soc/startup/Code/Startup/intvect.c similarity index 100% rename from ref_app/target/micros/xtensa_esp32_p4/startup/Code/Startup/intvect.c rename to ref_app/target/micros/esp32p4_riscv_soc/startup/Code/Startup/intvect.c diff --git a/ref_app/target/micros/xtensa_esp32_p4/startup/Code/StdLib/StdLib.cpp b/ref_app/target/micros/esp32p4_riscv_soc/startup/Code/StdLib/StdLib.cpp similarity index 100% rename from ref_app/target/micros/xtensa_esp32_p4/startup/Code/StdLib/StdLib.cpp rename to ref_app/target/micros/esp32p4_riscv_soc/startup/Code/StdLib/StdLib.cpp diff --git a/ref_app/target/micros/xtensa_esp32_p4/startup/crt0_init_ram.cpp b/ref_app/target/micros/esp32p4_riscv_soc/startup/crt0_init_ram.cpp similarity index 100% rename from ref_app/target/micros/xtensa_esp32_p4/startup/crt0_init_ram.cpp rename to ref_app/target/micros/esp32p4_riscv_soc/startup/crt0_init_ram.cpp diff --git a/ref_app/target/micros/xtensa_esp32_p4/startup/crt1.cpp b/ref_app/target/micros/esp32p4_riscv_soc/startup/crt1.cpp similarity index 100% rename from ref_app/target/micros/xtensa_esp32_p4/startup/crt1.cpp rename to ref_app/target/micros/esp32p4_riscv_soc/startup/crt1.cpp