pvh: Add code to transition from 32-bit to 64-bit

PVH starts in 32-bit mode, so we have to transition to 64-bit mode
before we can start running Rust code. As we have not yet initialized
the stack, we can only use registers and static memory.

This transition does the following:
  - Sets up page tables to identity map 2 MiB
  - Loads page tables into CR3
  - Sets CR4.PAE, EFER.LME, and CRO.PG
  - Sets up a 64-bit GDT
  - Long Jumps to 64-bit code

We put the GDT in the .rodata section, and we put the 32-bit code in its
own section. This makes it easier to debug and dissassemble the binary.

Signed-off-by: Joe Richey <joerichey@google.com>

Author: josephlr

layout.ld

@@ -22,6 +22,7 @@ SECTIONS
 	data_start = .;
 	.rodata : { *(.rodata .rodata.*) } :ram
 	.text   : { *(.text .text.*)     }
+	.text32 : { *(.text32)           }
 	.data   : { *(.data .data.*)     }
 	data_size = . - data_start;
 

src/asm/gdt64.s

@@ -0,0 +1,32 @@
+.section .rodata, "a"
+
+gdt64_ptr:
+    .short gdt64_end - gdt64_start - 1 # GDT length is actually (length - 1)
+    .quad gdt64_start
+
+gdt64_start: # First descriptor is always null
+    .quad 0
+code64_desc: # 64-bit Code-Segments always have: Base = 0, Limit = 4G
+    # CS.Limit[15:00] = 0                - Ignored
+    .short 0x0000
+    # CS.Base[15:00]  = 0                - Ignored
+    .short 0x0000
+    # CS.Base[23:16]  = 0   (bits 0-7)   - Ignored
+    .byte 0x00
+    # CS.Accessed     = 1   (bit  8)     - Don't write to segment on first use
+    # CS.ReadEnable   = 1   (bit  9)     - Read/Execute Code-Segment
+    # CS.Conforming   = 0   (bit  10)    - Nonconforming, no lower-priv access
+    # CS.Executable   = 1   (bit  11)    - Code-Segement
+    # CS.S            = 1   (bit  12)    - Not a System-Segement
+    # CS.DPL          = 0   (bits 13-14) - We only use this segment in Ring 0
+    # CS.P            = 1   (bit  15)    - Segment is present
+    .byte 0b10011011
+    # CS.Limit[19:16] = 0   (bits 16-19) - Ignored
+    # CS.AVL          = 0   (bit  20)    - Our software doesn't use this bit
+    # CS.L            = 1   (bit  21)    - This isn't a 64-bit segment
+    # CS.D            = 0   (bit  22)    - This is a 32-bit segment
+    # CS.G            = 0   (bit  23)    - Ignored
+    .byte 0b00100000
+    # CS.Base[31:24]  = 0   (bits 24-31) - Ignored
+    .byte 0x00
+gdt64_end:

src/asm/mod.rs

@@ -1 +1,3 @@
+global_asm!(include_str!("ram32.s"));
 global_asm!(include_str!("ram64.s"));
+global_asm!(include_str!("gdt64.s"));

src/asm/ram32.s

@@ -0,0 +1,46 @@
+.section .text32, "ax"
+.code32
+
+ram32_start:
+    # Stash the PVH start_info struct in %rdi.
+    movl %ebx, %edi
+    # Zero out %rsi, its value is unspecificed in the PVH Boot Protocol.
+    xorl %esi, %esi
+
+setup_page_tables:
+    # First L2 entry identity maps [0, 2 MiB)
+    movl $0b10000011, (L2_TABLES) # huge (bit 7), writable (bit 1), present (bit 0)
+    # First L3 entry points to L2 table
+    movl $L2_TABLES, %eax
+    orb  $0b00000011, %al # writable (bit 1), present (bit 0)
+    movl %eax, (L3_TABLE)
+    # First L4 entry points to L3 table
+    movl $L3_TABLE, %eax
+    orb  $0b00000011, %al # writable (bit 1), present (bit 0)
+    movl %eax, (L4_TABLE)
+
+enable_paging:
+    # Load page table root into CR3
+    movl $L4_TABLE, %eax
+    movl %eax, %cr3
+
+    # Set CR4.PAE (Physical Address Extension)
+    movl %cr4, %eax
+    orb  $0b00100000, %al # Set bit 5
+    movl %eax, %cr4
+    # Set EFER.LME (Long Mode Enable)
+    movl $0xC0000080, %ecx
+    rdmsr
+    orb  $0b00000001, %ah # Set bit 8
+    wrmsr
+    # Set CRO.PG (Paging)
+    movl %cr0, %eax
+    orl  $(1 << 31), %eax
+    movl %eax, %cr0
+
+jump_to_64bit:
+    # We are now in 32-bit compatibility mode. To enter 64-bit mode, we need to
+    # load a 64-bit code segment into our GDT.
+    lgdtl gdt64_ptr
+    # Set CS to a 64-bit segment and jump to 64-bit code.
+    ljmpl $(code64_desc - gdt64_start), $ram64_start