Beyond Phase 4
The supervisor currently runs single-core by design. Several modules document this assumption (e.g., "Single-core: no locking needed. Revisit when adding SMP.").
Work
- Per-CPU run queues with work stealing
- Spinlocks / ticket locks for shared kernel state (PMM, capability tables, IPC channels)
- AP (application processor) boot via ACPI MADT + SIPI sequence
- Per-CPU IDT/GDT/TSS
- Shard affinity and migration policy
Context
SMP is intentionally deferred — the single-core model keeps the supervisor simple and auditable. This issue tracks the eventual path to multi-core when the security model is proven and the single-core path is fully hardened.
Beyond Phase 4
The supervisor currently runs single-core by design. Several modules document this assumption (e.g., "Single-core: no locking needed. Revisit when adding SMP.").
Work
Context
SMP is intentionally deferred — the single-core model keeps the supervisor simple and auditable. This issue tracks the eventual path to multi-core when the security model is proven and the single-core path is fully hardened.