feat: GateFlow v2.2.1 — IP auto-detection, pattern matching, CDC scanning

New: gf-ip-detect skill, sv-ip-scanner agent, /gf-detect command
- Scans codebases for missing module implementations
- Pattern-matches standard IP (FIFO, CDC, SPI, UART, AXI)
- Detects CDC crossings without synchronizers (CRITICAL)
- Auto-fill: dispatches agents to implement gaps with user approval
- Sub-agent: other agents can invoke IP scanning mid-task
- Updated README, CLAUDE.md, router with new intents

Author: codejunkie99

.claude-plugin/marketplace.json

@@ -10,7 +10,7 @@
     {
       "name": "gateflow",
       "description": "AI-powered SystemVerilog development assistant with lint fixing, code generation, simulation, and waveform analysis",
-      "version": "2.2.0",
+      "version": "2.2.1",
       "author": {
         "name": "codejunkie99"
       },

README.md

@@ -251,7 +251,7 @@ GateFlow watches your workflow and helps proactively:
 
 ## Components
 
-### Skills (24)
+### Skills (25)
 
 | Skill | Description | Source |
 |-------|-------------|--------|
@@ -279,8 +279,9 @@ GateFlow watches your workflow and helps proactively:
 | `gf-cocotb` | Python testbenches via Cocotb | [SKILL.md](plugins/gateflow/skills/gf-cocotb/SKILL.md) |
 | `gf-fusesoc` | FuseSoC build system integration | [SKILL.md](plugins/gateflow/skills/gf-fusesoc/SKILL.md) |
 | `gf-learn-ctx` | Contextual learning — micro-lessons in workflows | [SKILL.md](plugins/gateflow/skills/gf-learn-ctx/SKILL.md) |
+| `gf-ip-detect` | **Auto-detect IP blocks** — scan, match, auto-fill gaps | [SKILL.md](plugins/gateflow/skills/gf-ip-detect/SKILL.md) |
 
-### Agents (17)
+### Agents (18)
 
 | Agent | Expertise | Source |
 |-------|-----------|--------|
@@ -301,8 +302,9 @@ GateFlow watches your workflow and helps proactively:
 | `vhdl-codegen` | **VHDL code generation** — entities and architectures | [vhdl-codegen.md](plugins/gateflow/agents/vhdl-codegen.md) |
 | `vhdl-testbench` | **VHDL testbench** — GHDL-compatible verification | [vhdl-testbench.md](plugins/gateflow/agents/vhdl-testbench.md) |
 | `pcb-designer` | **KiCad PCB** — AI-verified schematics and layouts | [pcb-designer.md](plugins/gateflow/agents/pcb-designer.md) |
+| `sv-ip-scanner` | **IP scanner** — detect missing modules, auto-fill | [sv-ip-scanner.md](plugins/gateflow/agents/sv-ip-scanner.md) |
 
-### Commands (13)
+### Commands (14)
 
 | Command | Description | Source |
 |---------|-------------|--------|
@@ -319,6 +321,7 @@ GateFlow watches your workflow and helps proactively:
 | `/gf-sim` | Run simulation | [gf-sim.md](plugins/gateflow/commands/gf-sim.md) |
 | `/gf-pnr` | Place & route (nextpnr) | [gf-pnr.md](plugins/gateflow/commands/gf-pnr.md) |
 | `/gf-flash` | Flash FPGA board | [gf-flash.md](plugins/gateflow/commands/gf-flash.md) |
+| `/gf-detect` | Scan for missing IP blocks and CDC issues | [gf-detect.md](plugins/gateflow/commands/gf-detect.md) |
 
 ### IP Library (8 verified blocks)
 
@@ -512,9 +515,9 @@ clock_freq: 100MHz
 Gateflow-Plugin/
 ├── plugins/gateflow/          # Main plugin source
 │   ├── .claude-plugin/        #   Plugin manifest
-│   ├── agents/                #   17 specialized AI agents
-│   ├── commands/              #   13 slash commands
-│   ├── skills/                #   24 auto-activating skills
+│   ├── agents/                #   18 specialized AI agents
+│   ├── commands/              #   14 slash commands
+│   ├── skills/                #   25 auto-activating skills
 │   ├── hooks/                 #   Automation hooks + session tracking
 │   ├── boards/                #   Curated FPGA board database (4 boards)
 │   ├── ip/                    #   Verified IP block library (8 blocks)

plugins/gateflow/.claude-plugin/plugin.json

@@ -1,6 +1,6 @@
 {
   "name": "gateflow",
-  "version": "2.2.0",
+  "version": "2.2.1",
   "description": "AI-powered SystemVerilog development assistant with lint fixing, code generation, simulation, and waveform analysis",
   "author": {
     "name": "codejunkie99",

plugins/gateflow/CLAUDE.md

@@ -174,6 +174,8 @@ Use Task tool (call 2 - same message, parallel):
 | `gateflow:sv-pinmap` | Pin assignment | "pin mapping", "constraints", "board pinout" |
 | `gateflow:vhdl-codegen` | VHDL code generation | "VHDL", "create VHDL", "entity", "architecture" |
 | `gateflow:vhdl-testbench` | VHDL testbench | "VHDL testbench", "VHDL TB", "GHDL" |
+| `gateflow:sv-ip-scanner` | IP detection + auto-fill | "scan for IP", "what's missing", "detect CDC", "auto-fill" |
+| `gateflow:pcb-designer` | KiCad schematic/PCB | "design board", "create schematic", "PCB layout" |
 
 ---
 

plugins/gateflow/skills/gf-router/SKILL.md

@@ -106,6 +106,9 @@ else:
 | PROTOCOL | Protocol interface scaffold | gf-protocols |
 | VHDL_CREATE | Create VHDL module | gateflow:vhdl-codegen |
 | VHDL_TB | Create VHDL testbench | gateflow:vhdl-testbench |
+| IP_DETECT | Scan for missing IP, find gaps | gf-ip-detect |
+| IP_AUTOFILL | Detect and implement missing modules | gf-ip-detect (auto-fill) |
+| CDC_SCAN | Find clock domain crossing issues | gf-ip-detect (cdc-only) |
 
 ### Meta Intents
 | Intent | Meaning |

releases.md

@@ -1,5 +1,20 @@
 # Releases
 
+## 2.2.1 (2026-03-26) — IP Auto-Detection & Auto-Fill
+
+### New Features
+- **IP auto-detection** (`/gf-detect`): Scans codebases for missing module implementations, stub modules, and standard IP patterns
+- **Auto-fill**: Detects gaps and dispatches agents to implement using verified IP library blocks
+- **CDC violation scanning**: Identifies clock domain crossings without synchronizers (CRITICAL severity)
+- **Pattern matching**: Recognizes FIFO, CDC, UART, SPI, AXI patterns in ad-hoc code and suggests verified replacements
+- **Sub-agent capability**: sv-ip-scanner works as a skill other agents can invoke mid-task
+
+### New Agent
+- `sv-ip-scanner` — IP block detection and auto-fill agent
+
+### New Command
+- `/gf-detect` — Scan for missing IP, stubs, CDC issues (`--auto-fill` to implement)
+
 ## 2.2.0 (2026-03-26) — Community + KiCad + Ecosystem
 
 ### New Features