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GateFlow v2.2.0 — The Open-Source Hardware Platform

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@codejunkie99 codejunkie99 released this 26 Mar 18:06
Immutable release. Only release title and notes can be modified.
v2.2.0
4196b12

GateFlow v2.2.0 — The Open-Source Hardware Platform

AI-powered hardware development — design, verify, synthesize, and deploy working RTL with natural language.

What's New

This release transforms GateFlow from an RTL assistant into a full-stack open-source hardware platform covering the entire development lifecycle.

Formal Verification from Natural Language ⚡

The killer feature. Describe what to prove in plain English:

"Formally verify that the FIFO never overflows and the pointers are always consistent"

GateFlow generates SVA properties, configures SymbiYosys, runs bounded model checking, and explains results — or counterexamples — in English.

Yosys Synthesis with Resource Reports

"Synthesize my design for the iCEBreaker"
→ LUTs: 142, FFs: 87, BRAM: 1, DSP: 0

Warns about unsupported SystemVerilog constructs before failing.

Drop-In IP Library (8 Verified Blocks)

Every block is lint-clean, simulation-tested, and formally verified:

  • fifo_sync / fifo_async — Synchronous and async FIFOs
  • cdc_2ff / cdc_handshake — Clock domain crossing primitives
  • uart — TX+RX with configurable baud rate
  • spi_master — All 4 CPOL/CPHA modes
  • axi4lite_slave — AXI4-Lite register interface
  • debouncer — Button debouncer with edge detection

Install with: /gf-ip add fifo_sync or "add a FIFO to my project"

Board-Aware Pin Mapping

Curated constraint files for 4 popular FPGA boards:

  • Digilent Arty A7-35T (Xilinx)
  • Digilent Basys 3 (Xilinx)
  • 1BitSquared iCEBreaker (Lattice iCE40)
  • Sipeed Tang Nano 9K (Gowin)

Query with /gf-boards arty-a7-35t or "what pins does the Arty A7 have?"

Multi-HDL Support

  • SystemVerilog — Verilator, Icarus Verilog
  • Verilog — Verilator, Icarus Verilog
  • VHDL — GHDL (agents: vhdl-codegen, vhdl-testbench)

KiCad Schematic & PCB Generation

AI-verified draft designs with self-improving DRC/ERC/AI review loop. Confidence scoring and mandatory disclaimers on all outputs.

Full Pipeline

Natural Language → Plan → Build → Lint → Simulate
→ Formal Verify → Synthesize → Place & Route → Pin Map → Flash

Platform Support

Works across 7 AI coding platforms + OpenClaw:
Claude Code (native) | OpenCode | Cursor | Cline | Windsurf | Codex CLI | Copilot CLI | OpenClaw (ClawHub skill)

By the Numbers

Component Count
Agents 17
Commands 13
Skills 24
IP Blocks 8 (with real SystemVerilog)
Board Definitions 4
SystemVerilog Files 25
Protocol References 3 (AXI4-Lite, SPI, I2C)
Integrations 5 (OpenClaw, F4PGA, OpenFPGA, OpenLane, platforms)

New Components

Agents (+6)

  • sv-formal — Formal verification (SVA + SymbiYosys)
  • sv-synth — Yosys synthesis optimization
  • sv-pinmap — Board-aware pin assignment
  • vhdl-codegen — VHDL entity/architecture generation
  • vhdl-testbench — VHDL testbenches (GHDL-compatible)
  • pcb-designer — KiCad schematic/PCB with AI verification

Commands (+6)

  • /gf-demo — Zero-config showcase project
  • /gf-formal — Run formal verification
  • /gf-ip — Manage IP block library
  • /gf-boards — Query board pinouts
  • /gf-pnr — Place & route with nextpnr
  • /gf-flash — Flash FPGA via openFPGALoader

Skills (+12)

  • gf-formal — Formal verification from natural language
  • gf-synth — Yosys synthesis with resource reports
  • gf-ip — IP block library manager
  • gf-errors — 3-layer error translation (what/why/fix)
  • gf-project — Project context (.gateflow/project.yaml)
  • gf-pinmap — Board-aware pin mapping
  • gf-pnr — nextpnr place & route
  • gf-protocols — Protocol scaffolding (AXI4, SPI, I2C)
  • gf-pcb — KiCad schematic/PCB generation
  • gf-cocotb — Python testbenches via Cocotb
  • gf-fusesoc — FuseSoC build system integration
  • gf-learn-ctx — Contextual micro-lessons in workflows

Quick Start

# Install
claude plugin marketplace add codejunkie99/Gateflow-Plugin

# Try the demo
/gf-demo

# Or just describe what you want
"Create a FIFO and formally verify it never overflows"

Ecosystem Roadmap

Integration Status
OpenClaw (ClawHub) Ready
F4PGA (Xilinx open-source) Ready
OpenFPGA (custom architectures) Planned
OpenLane (ASIC tapeout) Planned
Cocotb (Python verification) Ready
FuseSoC (build system) Ready

Built for hardware engineers who want to move faster.
Design. Verify. Ship.

Assets 3
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