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| 1 | +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT |
| 2 | + |
| 3 | +/dts-v1/; |
| 4 | + |
| 5 | +#include "ipq6018-512m.dtsi" |
| 6 | +#include "ipq6018-ess.dtsi" |
| 7 | +#include "ipq6018-mp5496.dtsi" |
| 8 | +#include "ipq6018-nss.dtsi" |
| 9 | + |
| 10 | +#include <dt-bindings/gpio/gpio.h> |
| 11 | +#include <dt-bindings/input/input.h> |
| 12 | +#include <dt-bindings/leds/common.h> |
| 13 | + |
| 14 | +/ { |
| 15 | + model = "DPtech AP3000-2C"; |
| 16 | + compatible = "dptech,ap3000-2c", "qcom,ipq6018"; |
| 17 | + |
| 18 | + aliases { |
| 19 | + serial0 = &blsp1_uart3; |
| 20 | + led-boot = &led_power; |
| 21 | + led-failsafe = &led_power; |
| 22 | + led-running = &led_power; |
| 23 | + led-upgrade = &led_power; |
| 24 | + label-mac-device = &dp4; |
| 25 | + }; |
| 26 | + |
| 27 | + chosen { |
| 28 | + stdout-path = "serial0:115200n8"; |
| 29 | + bootargs-append = " root=/dev/ubiblock0_1"; |
| 30 | + }; |
| 31 | + |
| 32 | + keys { |
| 33 | + compatible = "gpio-keys"; |
| 34 | + pinctrl-0 = <&button_pins>; |
| 35 | + pinctrl-names = "default"; |
| 36 | + |
| 37 | + reset { |
| 38 | + label = "reset"; |
| 39 | + linux,code = <KEY_RESTART>; |
| 40 | + gpios = <&tlmm 9 GPIO_ACTIVE_LOW>; |
| 41 | + }; |
| 42 | + }; |
| 43 | + |
| 44 | + leds { |
| 45 | + compatible = "gpio-leds"; |
| 46 | + pinctrl-0 = <&led_pins>; |
| 47 | + pinctrl-names = "default"; |
| 48 | + |
| 49 | + led_power: power { |
| 50 | + color = <LED_COLOR_ID_GREEN>; |
| 51 | + function = LED_FUNCTION_POWER; |
| 52 | + gpios = <&tlmm 23 GPIO_ACTIVE_HIGH>; |
| 53 | + }; |
| 54 | + |
| 55 | + wlan2g { |
| 56 | + color = <LED_COLOR_ID_GREEN>; |
| 57 | + function = LED_FUNCTION_WLAN_2GHZ; |
| 58 | + gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>; |
| 59 | + linux,default-trigger = "phy1radio"; |
| 60 | + }; |
| 61 | + |
| 62 | + wlan5g { |
| 63 | + color = <LED_COLOR_ID_GREEN>; |
| 64 | + function = LED_FUNCTION_WLAN_5GHZ; |
| 65 | + gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>; |
| 66 | + linux,default-trigger = "phy0radio"; |
| 67 | + }; |
| 68 | + }; |
| 69 | +}; |
| 70 | + |
| 71 | +&tlmm { |
| 72 | + button_pins: button_pinmux { |
| 73 | + pins = "gpio9"; |
| 74 | + function = "gpio"; |
| 75 | + drive-strength = <8>; |
| 76 | + bias-pull-up; |
| 77 | + }; |
| 78 | + |
| 79 | + led_pins: led_pinmux { |
| 80 | + pins = "gpio23", "gpio37", "gpio55"; |
| 81 | + function = "gpio"; |
| 82 | + drive-strength = <8>; |
| 83 | + bias-pull-up; |
| 84 | + }; |
| 85 | + |
| 86 | + mdio_pins: mdio_pinmux { |
| 87 | + mdc { |
| 88 | + pins = "gpio64"; |
| 89 | + function = "mdc"; |
| 90 | + drive-strength = <8>; |
| 91 | + bias-pull-up; |
| 92 | + }; |
| 93 | + |
| 94 | + mdio { |
| 95 | + pins = "gpio65"; |
| 96 | + function = "mdio"; |
| 97 | + drive-strength = <8>; |
| 98 | + bias-pull-up; |
| 99 | + }; |
| 100 | + }; |
| 101 | + |
| 102 | + spi_pins: spi_pinmux { |
| 103 | + pins = "gpio38", "gpio39", "gpio40", "gpio41"; |
| 104 | + function = "blsp0_spi"; |
| 105 | + drive-strength = <8>; |
| 106 | + bias-pull-down; |
| 107 | + }; |
| 108 | +}; |
| 109 | + |
| 110 | +&blsp1_uart3 { |
| 111 | + status = "okay"; |
| 112 | + |
| 113 | + pinctrl-0 = <&serial_3_pins>; |
| 114 | + pinctrl-names = "default"; |
| 115 | +}; |
| 116 | + |
| 117 | +&blsp1_spi1 { |
| 118 | + status = "okay"; |
| 119 | + |
| 120 | + pinctrl-0 = <&spi_pins>; |
| 121 | + pinctrl-names = "default"; |
| 122 | + |
| 123 | + flash@0 { |
| 124 | + reg = <0>; |
| 125 | + compatible = "jedec,spi-nor"; |
| 126 | + spi-max-frequency = <50000000>; |
| 127 | + |
| 128 | + partitions { |
| 129 | + compatible = "fixed-partitions"; |
| 130 | + #address-cells = <1>; |
| 131 | + #size-cells = <1>; |
| 132 | + |
| 133 | + partition@0 { |
| 134 | + label = "0:sbl1"; |
| 135 | + reg = <0x0 0xc0000>; |
| 136 | + read-only; |
| 137 | + }; |
| 138 | + |
| 139 | + partition@c0000 { |
| 140 | + label = "0:mibib"; |
| 141 | + reg = <0xc0000 0x10000>; |
| 142 | + read-only; |
| 143 | + }; |
| 144 | + |
| 145 | + partition@d0000 { |
| 146 | + label = "0:bootconfig"; |
| 147 | + reg = <0xd0000 0x20000>; |
| 148 | + }; |
| 149 | + |
| 150 | + partition@f0000 { |
| 151 | + label = "0:bootconfig1"; |
| 152 | + reg = <0xf0000 0x20000>; |
| 153 | + }; |
| 154 | + |
| 155 | + partition@110000 { |
| 156 | + label = "0:qsee"; |
| 157 | + reg = <0x110000 0x1a0000>; |
| 158 | + read-only; |
| 159 | + }; |
| 160 | + |
| 161 | + partition@2b0000 { |
| 162 | + label = "0:qsee_1"; |
| 163 | + reg = <0x2b0000 0x1a0000>; |
| 164 | + read-only; |
| 165 | + }; |
| 166 | + |
| 167 | + partition@450000 { |
| 168 | + label = "0:devcfg"; |
| 169 | + reg = <0x450000 0x10000>; |
| 170 | + read-only; |
| 171 | + }; |
| 172 | + |
| 173 | + partition@460000 { |
| 174 | + label = "0:devcfg_1"; |
| 175 | + reg = <0x460000 0x10000>; |
| 176 | + read-only; |
| 177 | + }; |
| 178 | + |
| 179 | + partition@470000 { |
| 180 | + label = "0:rpm"; |
| 181 | + reg = <0x470000 0x40000>; |
| 182 | + read-only; |
| 183 | + }; |
| 184 | + |
| 185 | + partition@4b0000 { |
| 186 | + label = "0:rpm_1"; |
| 187 | + reg = <0x4b0000 0x40000>; |
| 188 | + read-only; |
| 189 | + }; |
| 190 | + |
| 191 | + partition@4f0000 { |
| 192 | + label = "0:cdt"; |
| 193 | + reg = <0x4f0000 0x10000>; |
| 194 | + read-only; |
| 195 | + }; |
| 196 | + |
| 197 | + partition@500000 { |
| 198 | + label = "0:cdt_1"; |
| 199 | + reg = <0x500000 0x10000>; |
| 200 | + read-only; |
| 201 | + }; |
| 202 | + |
| 203 | + partition@510000 { |
| 204 | + compatible = "u-boot,env"; |
| 205 | + label = "0:appsblenv"; |
| 206 | + reg = <0x510000 0x10000>; |
| 207 | + }; |
| 208 | + |
| 209 | + partition@520000 { |
| 210 | + label = "0:appsbl"; |
| 211 | + reg = <0x520000 0xa0000>; |
| 212 | + read-only; |
| 213 | + }; |
| 214 | + |
| 215 | + partition@5c0000 { |
| 216 | + label = "0:appsbl_1"; |
| 217 | + reg = <0x5c0000 0xa0000>; |
| 218 | + read-only; |
| 219 | + }; |
| 220 | + |
| 221 | + partition@660000 { |
| 222 | + label = "0:art"; |
| 223 | + reg = <0x660000 0x40000>; |
| 224 | + read-only; |
| 225 | + |
| 226 | + nvmem-layout { |
| 227 | + compatible = "fixed-layout"; |
| 228 | + #address-cells = <1>; |
| 229 | + #size-cells = <1>; |
| 230 | + |
| 231 | + macaddr_art_0: macaddr@0 { |
| 232 | + reg = <0x0 0x6>; |
| 233 | + }; |
| 234 | + |
| 235 | + macaddr_art_6: macaddr@6 { |
| 236 | + reg = <0x6 0x6>; |
| 237 | + }; |
| 238 | + }; |
| 239 | + }; |
| 240 | + }; |
| 241 | + }; |
| 242 | +}; |
| 243 | + |
| 244 | +&qpic_bam { |
| 245 | + status = "okay"; |
| 246 | +}; |
| 247 | + |
| 248 | +&qpic_nand { |
| 249 | + status = "okay"; |
| 250 | + |
| 251 | + compatible = "qcom,ipq6018-nand", "qcom,ebi2-nandc-bam-v1.5.0"; |
| 252 | + |
| 253 | + nand@0 { |
| 254 | + reg = <0>; |
| 255 | + nand-bus-width = <8>; |
| 256 | + }; |
| 257 | +}; |
| 258 | + |
| 259 | +&qusb_phy_0 { |
| 260 | + status = "okay"; |
| 261 | +}; |
| 262 | + |
| 263 | +&ssphy_0 { |
| 264 | + status = "okay"; |
| 265 | +}; |
| 266 | + |
| 267 | +&usb3 { |
| 268 | + status = "okay"; |
| 269 | +}; |
| 270 | + |
| 271 | +&mdio { |
| 272 | + status = "okay"; |
| 273 | + |
| 274 | + pinctrl-0 = <&mdio_pins>; |
| 275 | + pinctrl-names = "default"; |
| 276 | + reset-gpios = <&tlmm 75 GPIO_ACTIVE_LOW>; |
| 277 | + |
| 278 | + qca8075_2: ethernet-phy@2 { |
| 279 | + compatible = "ethernet-phy-ieee802.3-c22"; |
| 280 | + reg = <2>; |
| 281 | + }; |
| 282 | + |
| 283 | + qca8075_3: ethernet-phy@3 { |
| 284 | + compatible = "ethernet-phy-ieee802.3-c22"; |
| 285 | + reg = <3>; |
| 286 | + }; |
| 287 | + |
| 288 | + qca8075_4: ethernet-phy@4 { |
| 289 | + compatible = "ethernet-phy-ieee802.3-c22"; |
| 290 | + reg = <4>; |
| 291 | + }; |
| 292 | +}; |
| 293 | + |
| 294 | +&switch { |
| 295 | + status = "okay"; |
| 296 | + |
| 297 | + switch_cpu_bmp = <0x1>; |
| 298 | + switch_lan_bmp = <0x1e>; |
| 299 | + switch_wan_bmp = <0x20>; |
| 300 | + switch_inner_bmp = <0xc0>; |
| 301 | + switch_mac_mode = <0x0>; |
| 302 | + switch_mac_mode1 = <0xff>; |
| 303 | + switch_mac_mode2 = <0xff>; |
| 304 | + bm_tick_mode = <0x00>; |
| 305 | + tm_tick_mode = <0x00>; |
| 306 | + |
| 307 | + qcom,port_phyinfo { |
| 308 | + port@2 { |
| 309 | + port_id = <3>; |
| 310 | + phy_address = <2>; |
| 311 | + }; |
| 312 | + port@3 { |
| 313 | + port_id = <4>; |
| 314 | + phy_address = <3>; |
| 315 | + }; |
| 316 | + port@4 { |
| 317 | + port_id = <5>; |
| 318 | + phy_address = <4>; |
| 319 | + }; |
| 320 | + }; |
| 321 | +}; |
| 322 | + |
| 323 | +&edma { |
| 324 | + status = "okay"; |
| 325 | +}; |
| 326 | + |
| 327 | +&dp3 { |
| 328 | + status = "okay"; |
| 329 | + |
| 330 | + phy-handle = <&qca8075_2>; |
| 331 | + label = "wan"; |
| 332 | + nvmem-cells = <&macaddr_art_0>; |
| 333 | + nvmem-cell-names = "mac-address"; |
| 334 | +}; |
| 335 | + |
| 336 | +&dp4 { |
| 337 | + status = "okay"; |
| 338 | + |
| 339 | + phy-handle = <&qca8075_3>; |
| 340 | + label = "lan1"; |
| 341 | + nvmem-cells = <&macaddr_art_6>; |
| 342 | + nvmem-cell-names = "mac-address"; |
| 343 | +}; |
| 344 | + |
| 345 | +&dp5 { |
| 346 | + status = "okay"; |
| 347 | + |
| 348 | + phy-handle = <&qca8075_4>; |
| 349 | + label = "lan2"; |
| 350 | + nvmem-cells = <&macaddr_art_6>; |
| 351 | + nvmem-cell-names = "mac-address"; |
| 352 | +}; |
| 353 | + |
| 354 | +&wifi { |
| 355 | + status = "okay"; |
| 356 | + |
| 357 | + qcom,ath11k-calibration-variant = "DPtech-AP3000-2C"; |
| 358 | + qcom,ath11k-fw-memory-mode = <1>; |
| 359 | +}; |
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