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| 1 | +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ |
| 2 | + |
| 3 | +/dts-v1/; |
| 4 | +#include "mt7987a.dtsi" |
| 5 | +#include <dt-bindings/input/input.h> |
| 6 | + |
| 7 | +/ { |
| 8 | + model = "GL.iNet GL-MT5000"; |
| 9 | + compatible = "glinet,gl-mt5000", |
| 10 | + "mediatek,mt7987a", "mediatek,mt7987"; |
| 11 | + |
| 12 | + aliases { |
| 13 | + label-mac-device = &gmac0; |
| 14 | + led-boot = &led_power; |
| 15 | + led-failsafe = &led_power; |
| 16 | + led-running = &led_power; |
| 17 | + led-upgrade = &led_power; |
| 18 | + }; |
| 19 | + |
| 20 | + chosen { |
| 21 | + bootargs = "console=ttyS0,115200n1 loglevel=8 \ |
| 22 | + earlycon=uart8250,mmio32,0x11000000 \ |
| 23 | + root=PARTLABEL=rootfs rootwait \ |
| 24 | + rootfstype=squashfs,f2fs pci=pcie_bus_perf"; |
| 25 | + }; |
| 26 | + |
| 27 | + gpio-keys { |
| 28 | + compatible = "gpio-keys"; |
| 29 | + |
| 30 | + reset { |
| 31 | + label = "reset"; |
| 32 | + linux,code = <KEY_RESTART>; |
| 33 | + gpios = <&pio 4 GPIO_ACTIVE_LOW>; |
| 34 | + debounce-interval = <10>; |
| 35 | + }; |
| 36 | + }; |
| 37 | + |
| 38 | + gpio-export { |
| 39 | + compatible = "gpio-export"; |
| 40 | + |
| 41 | + usb_power { |
| 42 | + gpio-export,name = "usb_power"; |
| 43 | + gpio-export,output = <1>; |
| 44 | + gpios = <&pio 9 GPIO_ACTIVE_HIGH>; |
| 45 | + }; |
| 46 | + }; |
| 47 | + |
| 48 | + leds { |
| 49 | + compatible = "gpio-leds"; |
| 50 | + |
| 51 | + led_power: led@0 { |
| 52 | + label = "blue:run"; |
| 53 | + gpios = <&pio 44 GPIO_ACTIVE_LOW>; |
| 54 | + default-state = "on"; |
| 55 | + }; |
| 56 | + |
| 57 | + led@1 { |
| 58 | + label = "white:system"; |
| 59 | + gpios = <&pio 7 GPIO_ACTIVE_LOW>; |
| 60 | + }; |
| 61 | + |
| 62 | + led@2 { |
| 63 | + label = "vpn"; |
| 64 | + gpios = <&pio 43 GPIO_ACTIVE_LOW>; |
| 65 | + }; |
| 66 | + }; |
| 67 | + |
| 68 | + reg_1p8v: regulator-1p8v { |
| 69 | + compatible = "regulator-fixed"; |
| 70 | + regulator-name = "fixed-1.8V"; |
| 71 | + regulator-min-microvolt = <1800000>; |
| 72 | + regulator-max-microvolt = <1800000>; |
| 73 | + regulator-boot-on; |
| 74 | + regulator-always-on; |
| 75 | + }; |
| 76 | + |
| 77 | + reg_3p3v: regulator-3p3v { |
| 78 | + compatible = "regulator-fixed"; |
| 79 | + regulator-name = "fixed-3.3V"; |
| 80 | + regulator-min-microvolt = <3300000>; |
| 81 | + regulator-max-microvolt = <3300000>; |
| 82 | + regulator-boot-on; |
| 83 | + regulator-always-on; |
| 84 | + }; |
| 85 | +}; |
| 86 | + |
| 87 | +&mmc0 { |
| 88 | + pinctrl-names = "default", "state_uhs"; |
| 89 | + pinctrl-0 = <&mmc_pins_default>; |
| 90 | + pinctrl-1 = <&mmc_pins_uhs>; |
| 91 | + bus-width = <8>; |
| 92 | + max-frequency = <26000000>; |
| 93 | + cap-mmc-highspeed; |
| 94 | + vqmmc-supply = <®_3p3v>; |
| 95 | + vmmc-supply = <®_3p3v>; |
| 96 | + mmc-ddr-3_3v; |
| 97 | + non-removable; |
| 98 | + no-sd; |
| 99 | + no-sdio; |
| 100 | + status = "okay"; |
| 101 | + |
| 102 | + card@0 { |
| 103 | + compatible = "mmc-card"; |
| 104 | + reg = <0>; |
| 105 | + |
| 106 | + block { |
| 107 | + compatible = "block-device"; |
| 108 | + partitions { |
| 109 | + block-partition-env { |
| 110 | + partname = "u-boot-env"; |
| 111 | + |
| 112 | + nvmem-layout { |
| 113 | + compatible = "u-boot,env"; |
| 114 | + }; |
| 115 | + }; |
| 116 | + |
| 117 | + block-partition-factory { |
| 118 | + partname = "factory"; |
| 119 | + |
| 120 | + nvmem-layout { |
| 121 | + compatible = "fixed-layout"; |
| 122 | + #address-cells = <1>; |
| 123 | + #size-cells = <1>; |
| 124 | + |
| 125 | + macaddr_base: macaddr@4000 { |
| 126 | + compatible = "mac-base"; |
| 127 | + reg = <0x4000 0x6>; |
| 128 | + #nvmem-cell-cells = <1>; |
| 129 | + }; |
| 130 | + }; |
| 131 | + |
| 132 | + }; |
| 133 | + }; |
| 134 | + }; |
| 135 | + }; |
| 136 | +}; |
| 137 | + |
| 138 | +&gmac0 { |
| 139 | + compatible = "mediatek,eth-mac"; |
| 140 | + reg = <0>; |
| 141 | + mac-type = "gdm"; |
| 142 | + phy-mode = "2500base-x"; |
| 143 | + status = "okay"; |
| 144 | + nvmem-cells = <&macaddr_base 0>; |
| 145 | + nvmem-cell-names = "mac-address"; |
| 146 | + |
| 147 | + fixed-link { |
| 148 | + speed = <2500>; |
| 149 | + full-duplex; |
| 150 | + pause; |
| 151 | + }; |
| 152 | +}; |
| 153 | + |
| 154 | +&gmac1 { |
| 155 | + reg = <1>; |
| 156 | + mac-type = "xgdm"; |
| 157 | + phy-mode = "internal"; |
| 158 | + phy-handle = <&phy15>; |
| 159 | + status = "okay"; |
| 160 | + nvmem-cells = <&macaddr_base 1>; |
| 161 | + nvmem-cell-names = "mac-address"; |
| 162 | +}; |
| 163 | + |
| 164 | +&mdio { |
| 165 | + #address-cells = <1>; |
| 166 | + #size-cells = <0>; |
| 167 | + reset-gpios = <&pio 0 GPIO_ACTIVE_LOW>; |
| 168 | + reset-delay-us = <10000>; |
| 169 | + |
| 170 | + phy15: phy@f { |
| 171 | + compatible = "ethernet-phy-ieee802.3-c45"; |
| 172 | + reg = <15>; |
| 173 | + pinctrl-names = "i2p5gbe-led"; |
| 174 | + pinctrl-0 = <&i2p5gbe_led0_pins>; |
| 175 | + phy-mode = "internal"; |
| 176 | + }; |
| 177 | +}; |
| 178 | + |
| 179 | +&ssusb { |
| 180 | + status = "okay"; |
| 181 | +}; |
| 182 | + |
| 183 | +&tphyu3port0 { |
| 184 | + status = "okay"; |
| 185 | +}; |
| 186 | + |
| 187 | +&uart0 { |
| 188 | + pinctrl-names = "default"; |
| 189 | + pinctrl-0 = <&uart0_pins>; |
| 190 | + status = "okay"; |
| 191 | +}; |
| 192 | + |
| 193 | +&infra_bus_prot { |
| 194 | + status = "okay"; |
| 195 | +}; |
| 196 | + |
| 197 | +&boottrap { |
| 198 | + status = "okay"; |
| 199 | +}; |
| 200 | + |
| 201 | +&trng { |
| 202 | + status = "okay"; |
| 203 | +}; |
| 204 | + |
| 205 | +&lvts { |
| 206 | + status = "okay"; |
| 207 | +}; |
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