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| 1 | +// SPDX-License-Identifier: (GPL-2.0 OR MIT) |
| 2 | +// Author: Developer X <dev@x-wrt.com> |
| 3 | + |
| 4 | +/dts-v1/; |
| 5 | +#include "mt7987a.dtsi" |
| 6 | +#include <dt-bindings/input/input.h> |
| 7 | + |
| 8 | +/ { |
| 9 | + model = "Tenda BE12 Pro"; |
| 10 | + compatible = "tenda,be12-pro", "mediatek,mt7987a", "mediatek,mt7987"; |
| 11 | + |
| 12 | + aliases { |
| 13 | + label-mac-device = &gmac0; |
| 14 | + led-boot = &led_status_green; |
| 15 | + led-failsafe = &led_status_red; |
| 16 | + led-running = &led_status_green; |
| 17 | + led-upgrade = &led_status_red; |
| 18 | + }; |
| 19 | + |
| 20 | + chosen { |
| 21 | + bootargs-override = "console=ttyS0,115200n1 earlycon=uart8250,mmio32,0x11000000 pci=pcie_bus_perf"; |
| 22 | + }; |
| 23 | + |
| 24 | + gpio-keys { |
| 25 | + compatible = "gpio-keys"; |
| 26 | + |
| 27 | + reset { |
| 28 | + label = "reset"; |
| 29 | + linux,code = <KEY_RESTART>; |
| 30 | + gpios = <&pio 1 GPIO_ACTIVE_LOW>; |
| 31 | + debounce-interval = <10>; |
| 32 | + }; |
| 33 | + |
| 34 | + wps { |
| 35 | + label = "wps"; |
| 36 | + linux,code = <KEY_WPS_BUTTON>; |
| 37 | + gpios = <&pio 0 GPIO_ACTIVE_LOW>; |
| 38 | + debounce-interval = <10>; |
| 39 | + }; |
| 40 | + }; |
| 41 | + |
| 42 | + gpio-leds { |
| 43 | + compatible = "gpio-leds"; |
| 44 | + |
| 45 | + led_status_green: status_green { |
| 46 | + function = LED_FUNCTION_STATUS; |
| 47 | + color = <LED_COLOR_ID_GREEN>; |
| 48 | + gpios = <&pio 6 GPIO_ACTIVE_LOW>; |
| 49 | + }; |
| 50 | + |
| 51 | + led_status_red: status_red { |
| 52 | + function = LED_FUNCTION_STATUS; |
| 53 | + color = <LED_COLOR_ID_RED>; |
| 54 | + gpios = <&pio 7 GPIO_ACTIVE_LOW>; |
| 55 | + }; |
| 56 | + }; |
| 57 | +}; |
| 58 | + |
| 59 | +&spi0 { |
| 60 | + pinctrl-names = "default"; |
| 61 | + pinctrl-0 = <&spi0_flash_pins>; |
| 62 | + status = "okay"; |
| 63 | + |
| 64 | + flash@0 { |
| 65 | + compatible = "spi-nand"; |
| 66 | + reg = <0>; |
| 67 | + spi-max-frequency = <52000000>; |
| 68 | + spi-tx-bus-width = <4>; |
| 69 | + spi-rx-bus-width = <4>; |
| 70 | + mediatek,nmbm; |
| 71 | + mediatek,bmt-max-ratio = <1>; |
| 72 | + mediatek,bmt-max-reserved-blocks = <64>; |
| 73 | + |
| 74 | + partitions { |
| 75 | + compatible = "fixed-partitions"; |
| 76 | + #address-cells = <1>; |
| 77 | + #size-cells = <1>; |
| 78 | + |
| 79 | + partition@0 { |
| 80 | + label = "Bootloader"; |
| 81 | + reg = <0x000000 0x0300000>; |
| 82 | + read-only; |
| 83 | + }; |
| 84 | + |
| 85 | + partition@300000 { |
| 86 | + label = "u-boot-env"; |
| 87 | + reg = <0x300000 0x0080000>; |
| 88 | + }; |
| 89 | + |
| 90 | + partition@380000 { |
| 91 | + label = "Factory"; |
| 92 | + reg = <0x380000 0x0400000>; |
| 93 | + read-only; |
| 94 | + |
| 95 | + nvmem-layout { |
| 96 | + compatible = "fixed-layout"; |
| 97 | + #address-cells = <1>; |
| 98 | + #size-cells = <1>; |
| 99 | + |
| 100 | + eeprom_factory_0: eeprom@0 { |
| 101 | + reg = <0x0 0x1e00>; |
| 102 | + }; |
| 103 | + |
| 104 | + macaddr_factory_4: macaddr@4 { |
| 105 | + compatible = "mac-base"; |
| 106 | + reg = <0x4 0x6>; |
| 107 | + #nvmem-cell-cells = <1>; |
| 108 | + }; |
| 109 | + }; |
| 110 | + }; |
| 111 | + |
| 112 | + partition@780000 { |
| 113 | + label = "kernel"; |
| 114 | + reg = <0x780000 0x0600000>; |
| 115 | + }; |
| 116 | + |
| 117 | + partition@d80000 { |
| 118 | + label = "ubi"; |
| 119 | + reg = <0xd80000 0x5a00000>; |
| 120 | + }; |
| 121 | + |
| 122 | + partition@6780000 { |
| 123 | + label = "CFG"; |
| 124 | + reg = <0x6780000 0x400000>; |
| 125 | + read-only; |
| 126 | + }; |
| 127 | + |
| 128 | + partition@6b80000 { |
| 129 | + label = "MISC2"; |
| 130 | + reg = <0x6b80000 0x400000>; |
| 131 | + read-only; |
| 132 | + }; |
| 133 | + }; |
| 134 | + }; |
| 135 | +}; |
| 136 | + |
| 137 | +&gmac0 { |
| 138 | + phy-mode = "2500base-x"; |
| 139 | + status = "okay"; |
| 140 | + |
| 141 | + nvmem-cells = <&macaddr_factory_4 (-2)>; |
| 142 | + nvmem-cell-names = "mac-address"; |
| 143 | + |
| 144 | + fixed-link { |
| 145 | + speed = <2500>; |
| 146 | + full-duplex; |
| 147 | + pause; |
| 148 | + }; |
| 149 | +}; |
| 150 | + |
| 151 | +&gmac1 { |
| 152 | + phy-mode = "internal"; |
| 153 | + phy-handle = <&phy15>; |
| 154 | + status = "okay"; |
| 155 | + |
| 156 | + nvmem-cells = <&macaddr_factory_4 (-2)>; |
| 157 | + nvmem-cell-names = "mac-address"; |
| 158 | +}; |
| 159 | + |
| 160 | +&gmac2 { |
| 161 | + phy-mode = "2500base-x"; |
| 162 | + phy-handle = <&phy11>; |
| 163 | + status = "okay"; |
| 164 | + |
| 165 | + nvmem-cells = <&macaddr_factory_4 (-1)>; |
| 166 | + nvmem-cell-names = "mac-address"; |
| 167 | +}; |
| 168 | + |
| 169 | +&mdio { |
| 170 | + phy11: phy@11 { |
| 171 | + compatible = "ethernet-phy-ieee802.3-c45"; |
| 172 | + reg = <11>; |
| 173 | + |
| 174 | + reset-assert-us = <10000>; |
| 175 | + reset-deassert-us = <20000>; |
| 176 | + reset-gpios = <&pio 48 GPIO_ACTIVE_LOW>; |
| 177 | + }; |
| 178 | + |
| 179 | + phy15: phy@15 { |
| 180 | + compatible = "ethernet-phy-ieee802.3-c45"; |
| 181 | + reg = <15>; |
| 182 | + }; |
| 183 | + |
| 184 | + mfd@1 { |
| 185 | + compatible = "airoha,an8855-mfd"; |
| 186 | + reg = <1>; |
| 187 | + |
| 188 | + efuse { |
| 189 | + compatible = "airoha,an8855-efuse"; |
| 190 | + #nvmem-cell-cells = <0>; |
| 191 | + |
| 192 | + nvmem-layout { |
| 193 | + compatible = "fixed-layout"; |
| 194 | + #address-cells = <1>; |
| 195 | + #size-cells = <1>; |
| 196 | + |
| 197 | + shift_sel_port0_tx_a: shift-sel-port0-tx-a@c { |
| 198 | + reg = <0xc 0x4>; |
| 199 | + }; |
| 200 | + |
| 201 | + shift_sel_port0_tx_b: shift-sel-port0-tx-b@10 { |
| 202 | + reg = <0x10 0x4>; |
| 203 | + }; |
| 204 | + |
| 205 | + shift_sel_port0_tx_c: shift-sel-port0-tx-c@14 { |
| 206 | + reg = <0x14 0x4>; |
| 207 | + }; |
| 208 | + |
| 209 | + shift_sel_port0_tx_d: shift-sel-port0-tx-d@18 { |
| 210 | + reg = <0x18 0x4>; |
| 211 | + }; |
| 212 | + |
| 213 | + shift_sel_port1_tx_a: shift-sel-port1-tx-a@1c { |
| 214 | + reg = <0x1c 0x4>; |
| 215 | + }; |
| 216 | + |
| 217 | + shift_sel_port1_tx_b: shift-sel-port1-tx-b@20 { |
| 218 | + reg = <0x20 0x4>; |
| 219 | + }; |
| 220 | + |
| 221 | + shift_sel_port1_tx_c: shift-sel-port1-tx-c@24 { |
| 222 | + reg = <0x24 0x4>; |
| 223 | + }; |
| 224 | + |
| 225 | + shift_sel_port1_tx_d: shift-sel-port1-tx-d@28 { |
| 226 | + reg = <0x28 0x4>; |
| 227 | + }; |
| 228 | + |
| 229 | + shift_sel_port2_tx_a: shift-sel-port2-tx-a@2c { |
| 230 | + reg = <0x2c 0x4>; |
| 231 | + }; |
| 232 | + |
| 233 | + shift_sel_port2_tx_b: shift-sel-port2-tx-b@30 { |
| 234 | + reg = <0x30 0x4>; |
| 235 | + }; |
| 236 | + |
| 237 | + shift_sel_port2_tx_c: shift-sel-port2-tx-c@34 { |
| 238 | + reg = <0x34 0x4>; |
| 239 | + }; |
| 240 | + |
| 241 | + shift_sel_port2_tx_d: shift-sel-port2-tx-d@38 { |
| 242 | + reg = <0x38 0x4>; |
| 243 | + }; |
| 244 | + |
| 245 | + shift_sel_port3_tx_a: shift-sel-port3-tx-a@4c { |
| 246 | + reg = <0x4c 0x4>; |
| 247 | + }; |
| 248 | + |
| 249 | + shift_sel_port3_tx_b: shift-sel-port3-tx-b@50 { |
| 250 | + reg = <0x50 0x4>; |
| 251 | + }; |
| 252 | + |
| 253 | + shift_sel_port3_tx_c: shift-sel-port3-tx-c@54 { |
| 254 | + reg = <0x54 0x4>; |
| 255 | + }; |
| 256 | + |
| 257 | + shift_sel_port3_tx_d: shift-sel-port3-tx-d@58 { |
| 258 | + reg = <0x58 0x4>; |
| 259 | + }; |
| 260 | + }; |
| 261 | + }; |
| 262 | + |
| 263 | + ethernet-switch { |
| 264 | + compatible = "airoha,an8855-switch"; |
| 265 | + reset-gpios = <&pio 42 GPIO_ACTIVE_HIGH>; |
| 266 | + airoha,ext-surge; |
| 267 | + |
| 268 | + ports { |
| 269 | + #address-cells = <1>; |
| 270 | + #size-cells = <0>; |
| 271 | + |
| 272 | + port@0 { |
| 273 | + reg = <0>; |
| 274 | + label = "lan5"; |
| 275 | + phy-mode = "internal"; |
| 276 | + phy-handle = <&internal_phy1>; |
| 277 | + }; |
| 278 | + |
| 279 | + port@1 { |
| 280 | + reg = <1>; |
| 281 | + label = "lan4"; |
| 282 | + phy-mode = "internal"; |
| 283 | + phy-handle = <&internal_phy2>; |
| 284 | + }; |
| 285 | + |
| 286 | + port@2 { |
| 287 | + reg = <2>; |
| 288 | + label = "lan3"; |
| 289 | + phy-mode = "internal"; |
| 290 | + phy-handle = <&internal_phy3>; |
| 291 | + }; |
| 292 | + |
| 293 | + port@5 { |
| 294 | + reg = <5>; |
| 295 | + ethernet = <&gmac0>; |
| 296 | + phy-mode = "2500base-x"; |
| 297 | + |
| 298 | + fixed-link { |
| 299 | + speed = <2500>; |
| 300 | + full-duplex; |
| 301 | + pause; |
| 302 | + }; |
| 303 | + }; |
| 304 | + }; |
| 305 | + }; |
| 306 | + |
| 307 | + mdio { |
| 308 | + compatible = "airoha,an8855-mdio"; |
| 309 | + #address-cells = <1>; |
| 310 | + #size-cells = <0>; |
| 311 | + |
| 312 | + internal_phy1: phy@1 { |
| 313 | + reg = <1>; |
| 314 | + |
| 315 | + nvmem-cells = <&shift_sel_port0_tx_a>, |
| 316 | + <&shift_sel_port0_tx_b>, |
| 317 | + <&shift_sel_port0_tx_c>, |
| 318 | + <&shift_sel_port0_tx_d>; |
| 319 | + nvmem-cell-names = "tx_a", "tx_b", "tx_c", "tx_d"; |
| 320 | + }; |
| 321 | + |
| 322 | + internal_phy2: phy@2 { |
| 323 | + reg = <2>; |
| 324 | + |
| 325 | + nvmem-cells = <&shift_sel_port1_tx_a>, |
| 326 | + <&shift_sel_port1_tx_b>, |
| 327 | + <&shift_sel_port1_tx_c>, |
| 328 | + <&shift_sel_port1_tx_d>; |
| 329 | + nvmem-cell-names = "tx_a", "tx_b", "tx_c", "tx_d"; |
| 330 | + }; |
| 331 | + |
| 332 | + internal_phy3: phy@3 { |
| 333 | + reg = <3>; |
| 334 | + |
| 335 | + nvmem-cells = <&shift_sel_port2_tx_a>, |
| 336 | + <&shift_sel_port2_tx_b>, |
| 337 | + <&shift_sel_port2_tx_c>, |
| 338 | + <&shift_sel_port2_tx_d>; |
| 339 | + nvmem-cell-names = "tx_a", "tx_b", "tx_c", "tx_d"; |
| 340 | + }; |
| 341 | + }; |
| 342 | + }; |
| 343 | +}; |
| 344 | + |
| 345 | +&pcie0 { |
| 346 | + pinctrl-names = "default"; |
| 347 | + pinctrl-0 = <&pcie0_pins>; |
| 348 | + status = "okay"; |
| 349 | + |
| 350 | + pcie@0,0 { |
| 351 | + reg = <0x0000 0 0 0 0>; |
| 352 | + device_type = "pci"; |
| 353 | + #address-cells = <3>; |
| 354 | + #size-cells = <2>; |
| 355 | + |
| 356 | + wifi@0,0 { |
| 357 | + compatible = "mediatek,mt76"; |
| 358 | + reg = <0x0000 0 0 0 0>; |
| 359 | + |
| 360 | + nvmem-cells = <&eeprom_factory_0>; |
| 361 | + nvmem-cell-names = "eeprom"; |
| 362 | + |
| 363 | + #address-cells = <1>; |
| 364 | + #size-cells = <0>; |
| 365 | + |
| 366 | + band@0 { |
| 367 | + reg = <0>; |
| 368 | + nvmem-cells = <&macaddr_factory_4 1>; |
| 369 | + nvmem-cell-names = "mac-address"; |
| 370 | + }; |
| 371 | + |
| 372 | + band@1 { |
| 373 | + reg = <1>; |
| 374 | + nvmem-cells = <&macaddr_factory_4 3>; |
| 375 | + nvmem-cell-names = "mac-address"; |
| 376 | + }; |
| 377 | + }; |
| 378 | + }; |
| 379 | +}; |
| 380 | + |
| 381 | +&uart0 { |
| 382 | + pinctrl-names = "default"; |
| 383 | + pinctrl-0 = <&uart0_pins>; |
| 384 | + status = "okay"; |
| 385 | +}; |
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