arm64: errata: Mitigate TLBI errata on Microsoft Azure Cobalt 100 CPU

jira VULN-XXXXXX
cve CVE-2025-10263
commit-author Will Deacon <will@kernel.org>
commit 1940e70

The Microsoft Azure Cobalt 100 CPU is based on the Arm Neoverse N2, so
enable the fix for the latest broadcast TLB invalidation bug on these
parts.

Signed-off-by: Will Deacon <will@kernel.org>
(cherry picked from commit 1940e70)
Signed-off-by: Brett Mastbergen <bmastbergen@ciq.com>

Author: bmastbergen

Documentation/arm64/silicon-errata.rst

@@ -281,3 +281,5 @@ stable kernels.
 +----------------+-----------------+-----------------+-----------------------------+
 | Microsoft      | Azure Cobalt 100| #2253138        | ARM64_ERRATUM_2253138       |
 +----------------+-----------------+-----------------+-----------------------------+
+| Microsoft      | Azure Cobalt 100| #4193789        | ARM64_ERRATUM_4118414       |
++----------------+-----------------+-----------------+-----------------------------+

arch/arm64/Kconfig

@@ -1049,6 +1049,7 @@ config ARM64_ERRATUM_4118414
 	  * ARM Neoverse-V2 erratum 4193787
 	  * ARM Neoverse-V3 erratum 4193784
 	  * ARM Neoverse-V3AE erratum 4193784
+	  * Microsoft Azure Cobalt 100 4193789
 	  * NVIDIA Olympus erratum T410-OLY-1029
 
 	  On affected cores, some memory accesses might not be completed by

arch/arm64/kernel/cpu_errata.c

@@ -266,6 +266,7 @@ static const struct arm64_cpu_capabilities arm64_repeat_tlbi_list[] = {
 			MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3),
 			MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3AE),
 			MIDR_ALL_VERSIONS(MIDR_NVIDIA_OLYMPUS),
+			MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100),
 			{}
 		})),
 	},