arm64: Subscribe Microsoft Azure Cobalt 100 to ARM Neoverse N2 errata

jira VULN-187519
cve-pre CVE-2025-10263
commit-author Easwar Hariharan <eahariha@linux.microsoft.com>
commit fb091ff
upstream-diff Only the MIDR definition is backported. The N2 errata
  subscriptions (TRBE overwrite fill mode, TSB flush failure, TRBE write
  out of range) are omitted because those errata and their workaround
  infrastructure do not exist in this kernel version.

Add the MIDR value of Microsoft Azure Cobalt 100, which is a Microsoft
implemented CPU based on r0p0 of the ARM Neoverse N2 CPU, and therefore
suffers from all the same errata.

	CC: stable@vger.kernel.org # 5.15+
	Signed-off-by: Easwar Hariharan <eahariha@linux.microsoft.com>
	Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>
	Acked-by: Mark Rutland <mark.rutland@arm.com>
	Acked-by: Marc Zyngier <maz@kernel.org>
	Reviewed-by: Oliver Upton <oliver.upton@linux.dev>
Link: https://lore.kernel.org/r/20240214175522.2457857-1-eahariha@linux.microsoft.com
	Signed-off-by: Will Deacon <will@kernel.org>
(cherry picked from commit fb091ff)
	Signed-off-by: Brett Mastbergen <bmastbergen@ciq.com>

Author: bmastbergen

arch/arm64/include/asm/cputype.h

@@ -78,6 +78,7 @@
 #define ARM_CPU_IMP_NVIDIA		0x4E
 #define ARM_CPU_IMP_FUJITSU		0x46
 #define ARM_CPU_IMP_HISI		0x48
+#define ARM_CPU_IMP_MICROSOFT		0x6D
 
 #define ARM_CPU_PART_AEM_V8		0xD0F
 #define ARM_CPU_PART_FOUNDATION		0xD00
@@ -132,6 +133,8 @@
 
 #define HISI_CPU_PART_TSV110		0xD01
 
+#define MICROSOFT_CPU_PART_AZURE_COBALT_100	0xD49 /* Based on r0p0 of ARM Neoverse N2 */
+
 #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
 #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
 #define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72)
@@ -174,6 +177,7 @@
 #define MIDR_NVIDIA_OLYMPUS MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_OLYMPUS)
 #define MIDR_FUJITSU_A64FX MIDR_CPU_MODEL(ARM_CPU_IMP_FUJITSU, FUJITSU_CPU_PART_A64FX)
 #define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110)
+#define MIDR_MICROSOFT_AZURE_COBALT_100 MIDR_CPU_MODEL(ARM_CPU_IMP_MICROSOFT, MICROSOFT_CPU_PART_AZURE_COBALT_100)
 
 /* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */
 #define MIDR_FUJITSU_ERRATUM_010001		MIDR_FUJITSU_A64FX