Skip to content

Commit c1e3e36

Browse files
bmastbergenroxanan1996
bmastbergen
authored and
roxanan1996
committed
arm64: errata: Mitigate TLBI errata on various Arm CPUs
jira VULN-187521 cve CVE-2025-10263 commit-author Mark Rutland <mark.rutland@arm.com> commit - commit-source-sha cfd391e commit-source arm64 upstream-diff silicon-errata.rst at different path (Documentation/arm64/ vs Documentation/arch/arm64/) and required manual conflict resolution due to condensed table formatting and missing entries in our branch. Content is identical. A number of CPUs developed by Arm suffer from errata whereby a broadcast TLBI;DSB sequence may complete before the global observation of writes which are translated by an affected TLB entry. These errata ONLY affect the completion of memory accesses which have been translated by an invalidated TLB entry, and these errata DO NOT affect the actual invalidation of TLB entries. TLB entries are removed correctly. This issue has been assigned CVE ID CVE-2025-10263. To mitigate this issue, Arm recommends that software follows any affected TLBI;DSB sequence with an additional TLBI;DSB, which will ensure that all memory write effects affected by the first TLBI have been globally observed. The additional TLBI can use any operation that is broadcast to affected CPUs, and the additional DSB can use any option that is sufficient to complete the additional TLBI. The ARM64_WORKAROUND_REPEAT_TLBI workaround is sufficient to mitigate the issue. Enable this workaround for affected CPUs, and update the silicon errata documentation accordingly. Note that due to the manner in which Arm develops IP and tracks errata, some CPUs share a common erratum number. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Signed-off-by: Will Deacon <will@kernel.org> (cherry picked from commit cfd391e) Signed-off-by: Brett Mastbergen <bmastbergen@ciq.com>
1 parent 3371cbc commit c1e3e36

3 files changed

Lines changed: 108 additions & 2 deletions

File tree

‎Documentation/arm64/silicon-errata.rst‎

Lines changed: 42 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -100,8 +100,20 @@ stable kernels.
100100
+----------------+-----------------+-----------------+-----------------------------+
101101
| ARM | Cortex-A76 | #1463225 | ARM64_ERRATUM_1463225 |
102102
+----------------+-----------------+-----------------+-----------------------------+
103+
| ARM | Cortex-A76 | #4193800 | ARM64_ERRATUM_4118414 |
104+
+----------------+-----------------+-----------------+-----------------------------+
105+
| ARM | Cortex-A76AE | #4193801 | ARM64_ERRATUM_4118414 |
106+
+----------------+-----------------+-----------------+-----------------------------+
103107
| ARM | Cortex-A77 | #1508412 | ARM64_ERRATUM_1508412 |
104108
+----------------+-----------------+-----------------+-----------------------------+
109+
| ARM | Cortex-A77 | #4193798 | ARM64_ERRATUM_4118414 |
110+
+----------------+-----------------+-----------------+-----------------------------+
111+
| ARM | Cortex-A78 | #4193791 | ARM64_ERRATUM_4118414 |
112+
+----------------+-----------------+-----------------+-----------------------------+
113+
| ARM | Cortex-A78AE | #4193793 | ARM64_ERRATUM_4118414 |
114+
+----------------+-----------------+-----------------+-----------------------------+
115+
| ARM | Cortex-A78C | #4193794 | ARM64_ERRATUM_4118414 |
116+
+----------------+-----------------+-----------------+-----------------------------+
105117
| ARM | Cortex-A510 | #2051678 | ARM64_ERRATUM_2051678 |
106118
+----------------+-----------------+-----------------+-----------------------------+
107119
| ARM | Cortex-A510 | #2077057 | ARM64_ERRATUM_2077057 |
@@ -114,22 +126,52 @@ stable kernels.
114126
+----------------+-----------------+-----------------+-----------------------------+
115127
| ARM | Cortex-A710 | #2224489 | ARM64_ERRATUM_2224489 |
116128
+----------------+-----------------+-----------------+-----------------------------+
129+
| ARM | Cortex-A710 | #4193788 | ARM64_ERRATUM_4118414 |
130+
+----------------+-----------------+-----------------+-----------------------------+
131+
| ARM | Cortex-X1 | #4193791 | ARM64_ERRATUM_4118414 |
132+
+----------------+-----------------+-----------------+-----------------------------+
133+
| ARM | Cortex-X1C | #4193792 | ARM64_ERRATUM_4118414 |
134+
+----------------+-----------------+-----------------+-----------------------------+
117135
| ARM | Cortex-X2 | #2119858 | ARM64_ERRATUM_2119858 |
118136
+----------------+-----------------+-----------------+-----------------------------+
119137
| ARM | Cortex-X2 | #2224489 | ARM64_ERRATUM_2224489 |
120138
+----------------+-----------------+-----------------+-----------------------------+
139+
| ARM | Cortex-X2 | #4193788 | ARM64_ERRATUM_4118414 |
140+
+----------------+-----------------+-----------------+-----------------------------+
141+
| ARM | Cortex-X3 | #4193786 | ARM64_ERRATUM_4118414 |
142+
+----------------+-----------------+-----------------+-----------------------------+
143+
| ARM | Cortex-X4 | #4118414 | ARM64_ERRATUM_4118414 |
144+
+----------------+-----------------+-----------------+-----------------------------+
145+
| ARM | Cortex-X925 | #4193781 | ARM64_ERRATUM_4118414 |
146+
+----------------+-----------------+-----------------+-----------------------------+
121147
| ARM | Neoverse-N1 | #1188873,1418040| ARM64_ERRATUM_1418040 |
122148
+----------------+-----------------+-----------------+-----------------------------+
123149
| ARM | Neoverse-N1 | #1349291 | N/A |
124150
+----------------+-----------------+-----------------+-----------------------------+
125151
| ARM | Neoverse-N1 | #1542419 | ARM64_ERRATUM_1542419 |
126152
+----------------+-----------------+-----------------+-----------------------------+
153+
| ARM | Neoverse-N1 | #4193800 | ARM64_ERRATUM_4118414 |
154+
+----------------+-----------------+-----------------+-----------------------------+
127155
| ARM | Neoverse-N2 | #2139208 | ARM64_ERRATUM_2139208 |
128156
+----------------+-----------------+-----------------+-----------------------------+
129157
| ARM | Neoverse-N2 | #2067961 | ARM64_ERRATUM_2067961 |
130158
+----------------+-----------------+-----------------+-----------------------------+
131159
| ARM | Neoverse-N2 | #2253138 | ARM64_ERRATUM_2253138 |
132160
+----------------+-----------------+-----------------+-----------------------------+
161+
| ARM | Neoverse-N2 | #4193789 | ARM64_ERRATUM_4118414 |
162+
+----------------+-----------------+-----------------+-----------------------------+
163+
| ARM | Neoverse-V2 | #4193787 | ARM64_ERRATUM_4118414 |
164+
+----------------+-----------------+-----------------+-----------------------------+
165+
| ARM | Neoverse-V3 | #4193784 | ARM64_ERRATUM_4118414 |
166+
+----------------+-----------------+-----------------+-----------------------------+
167+
| ARM | Neoverse-V3AE | #4193784 | ARM64_ERRATUM_4118414 |
168+
+----------------+-----------------+-----------------+-----------------------------+
169+
| ARM | Neoverse-V1 | #4193790 | ARM64_ERRATUM_4118414 |
170+
+----------------+-----------------+-----------------+-----------------------------+
171+
| ARM | C1-Premium | #4193780 | ARM64_ERRATUM_4118414 |
172+
+----------------+-----------------+-----------------+-----------------------------+
173+
| ARM | C1-Ultra | #4193780 | ARM64_ERRATUM_4118414 |
174+
+----------------+-----------------+-----------------+-----------------------------+
133175
| ARM | MMU-500 | #841119,826419 | N/A |
134176
+----------------+-----------------+-----------------+-----------------------------+
135177
+----------------+-----------------+-----------------+-----------------------------+

‎arch/arm64/Kconfig‎

Lines changed: 36 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -906,6 +906,42 @@ config ARM64_ERRATUM_1902691
906906

907907
If unsure, say Y.
908908

909+
config ARM64_ERRATUM_4118414
910+
bool "Cortex-*/Neoverse-*/C1-*: Completion of affected memory accesses might not be guaranteed by completion of a TLBI"
911+
default y
912+
select ARM64_WORKAROUND_REPEAT_TLBI
913+
help
914+
This option adds a workaround for the following errata:
915+
916+
* ARM C1-Premium erratum 4193780
917+
* ARM C1-Ultra erratum 4193780
918+
* ARM Cortex-A76 erratum 4193800
919+
* ARM Cortex-A76AE erratum 4193801
920+
* ARM Cortex-A77 erratum 4193798
921+
* ARM Cortex-A78 erratum 4193791
922+
* ARM Cortex-A78AE erratum 4193793
923+
* ARM Cortex-A78C erratum 4193794
924+
* ARM Cortex-A710 erratum 4193788
925+
* ARM Cortex-X1 erratum 4193791
926+
* ARM Cortex-X1C erratum 4193792
927+
* ARM Cortex-X2 erratum 4193788
928+
* ARM Cortex-X3 erratum 4193786
929+
* ARM Cortex-X4 erratum 4118414
930+
* ARM Cortex-X925 erratum 4193781
931+
* ARM Neoverse-N1 erratum 4193800
932+
* ARM Neoverse-N2 erratum 4193789
933+
* ARM Neoverse-V1 erratum 4193790
934+
* ARM Neoverse-V2 erratum 4193787
935+
* ARM Neoverse-V3 erratum 4193784
936+
* ARM Neoverse-V3AE erratum 4193784
937+
938+
On affected cores, some memory accesses might not be completed by
939+
broadcast TLB invalidation.
940+
941+
This issue is also known as CVE-2025-10263.
942+
943+
If unsure, say Y.
944+
909945
config CAVIUM_ERRATUM_22375
910946
bool "Cavium erratum 22375, 24313"
911947
default y

‎arch/arm64/kernel/cpu_errata.c‎

Lines changed: 30 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -218,7 +218,35 @@ static const struct arm64_cpu_capabilities arm64_repeat_tlbi_list[] = {
218218
ERRATA_MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1),
219219
},
220220
#endif
221-
{},
221+
#ifdef CONFIG_ARM64_ERRATUM_4118414
222+
{
223+
ERRATA_MIDR_RANGE_LIST(((const struct midr_range[]) {
224+
MIDR_ALL_VERSIONS(MIDR_C1_PREMIUM),
225+
MIDR_ALL_VERSIONS(MIDR_C1_ULTRA),
226+
MIDR_ALL_VERSIONS(MIDR_CORTEX_A76),
227+
MIDR_ALL_VERSIONS(MIDR_CORTEX_A76AE),
228+
MIDR_ALL_VERSIONS(MIDR_CORTEX_A77),
229+
MIDR_ALL_VERSIONS(MIDR_CORTEX_A78),
230+
MIDR_ALL_VERSIONS(MIDR_CORTEX_A78AE),
231+
MIDR_ALL_VERSIONS(MIDR_CORTEX_A78C),
232+
MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
233+
MIDR_ALL_VERSIONS(MIDR_CORTEX_X1),
234+
MIDR_ALL_VERSIONS(MIDR_CORTEX_X1C),
235+
MIDR_ALL_VERSIONS(MIDR_CORTEX_X2),
236+
MIDR_ALL_VERSIONS(MIDR_CORTEX_X3),
237+
MIDR_ALL_VERSIONS(MIDR_CORTEX_X4),
238+
MIDR_ALL_VERSIONS(MIDR_CORTEX_X925),
239+
MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1),
240+
MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
241+
MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1),
242+
MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V2),
243+
MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3),
244+
MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3AE),
245+
{}
246+
})),
247+
},
248+
#endif
249+
{}
222250
};
223251
#endif
224252

@@ -497,7 +525,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
497525
#endif
498526
#ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI
499527
{
500-
.desc = "Qualcomm erratum 1009, or ARM erratum 1286807, 2441009",
528+
.desc = "Broken broadcast TLBI completion",
501529
.capability = ARM64_WORKAROUND_REPEAT_TLBI,
502530
.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
503531
.matches = cpucap_multi_entry_cap_matches,

0 commit comments

Comments
 (0)