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arm64: errata: Mitigate TLBI errata on various Arm CPUs
jira VULN-XXXXXX cve CVE-2025-10263 commit-author Mark Rutland <mark.rutland@arm.com> commit - commit-source https://lore.kernel.org/all/20260609101203.1512409-4-mark.rutland@arm.com/ upstream-diff silicon-errata.rst at different path (Documentation/arm64/ vs Documentation/arch/arm64/) and required manual conflict resolution due to condensed table formatting and missing entries in our branch. Content is identical. A number of CPUs developed by Arm suffer from errata whereby a broadcast TLBI;DSB sequence may complete before the global observation of writes which are translated by an affected TLB entry. These errata ONLY affect the completion of memory accesses which have been translated by an invalidated TLB entry, and these errata DO NOT affect the actual invalidation of TLB entries. TLB entries are removed correctly. This issue has been assigned CVE ID CVE-2025-10263. To mitigate this issue, Arm recommends that software follows any affected TLBI;DSB sequence with an additional TLBI;DSB, which will ensure that all memory write effects affected by the first TLBI have been globally observed. The additional TLBI can use any operation that is broadcast to affected CPUs, and the additional DSB can use any option that is sufficient to complete the additional TLBI. The ARM64_WORKAROUND_REPEAT_TLBI workaround is sufficient to mitigate the issue. Enable this workaround for affected CPUs, and update the silicon errata documentation accordingly. Note that due to the manner in which Arm develops IP and tracks errata, some CPUs share a common erratum number. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Signed-off-by: Brett Mastbergen <bmastbergen@ciq.com>
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‎Documentation/arm64/silicon-errata.rst‎

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@@ -109,8 +109,20 @@ stable kernels.
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A76 | #1463225 | ARM64_ERRATUM_1463225 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A76 | #4193800 | ARM64_ERRATUM_4118414 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A76AE | #4193801 | ARM64_ERRATUM_4118414 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A77 | #1508412 | ARM64_ERRATUM_1508412 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A77 | #4193798 | ARM64_ERRATUM_4118414 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A78 | #4193791 | ARM64_ERRATUM_4118414 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A78AE | #4193793 | ARM64_ERRATUM_4118414 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A78C | #4193794 | ARM64_ERRATUM_4118414 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A510 | #2051678 | ARM64_ERRATUM_2051678 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A510 | #2077057 | ARM64_ERRATUM_2077057 |
@@ -127,22 +139,52 @@ stable kernels.
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A715 | #2645198 | ARM64_ERRATUM_2645198 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A710 | #4193788 | ARM64_ERRATUM_4118414 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-X1 | #4193791 | ARM64_ERRATUM_4118414 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-X1C | #4193792 | ARM64_ERRATUM_4118414 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-X2 | #2119858 | ARM64_ERRATUM_2119858 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-X2 | #2224489 | ARM64_ERRATUM_2224489 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-X2 | #4193788 | ARM64_ERRATUM_4118414 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-X3 | #4193786 | ARM64_ERRATUM_4118414 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-X4 | #4118414 | ARM64_ERRATUM_4118414 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-X925 | #4193781 | ARM64_ERRATUM_4118414 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-N1 | #1188873,1418040| ARM64_ERRATUM_1418040 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-N1 | #1349291 | N/A |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-N1 | #1542419 | ARM64_ERRATUM_1542419 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-N1 | #4193800 | ARM64_ERRATUM_4118414 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-N2 | #2139208 | ARM64_ERRATUM_2139208 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-N2 | #2067961 | ARM64_ERRATUM_2067961 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-N2 | #2253138 | ARM64_ERRATUM_2253138 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-N2 | #4193789 | ARM64_ERRATUM_4118414 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-V2 | #4193787 | ARM64_ERRATUM_4118414 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-V3 | #4193784 | ARM64_ERRATUM_4118414 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-V3AE | #4193784 | ARM64_ERRATUM_4118414 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-V1 | #4193790 | ARM64_ERRATUM_4118414 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | C1-Premium | #4193780 | ARM64_ERRATUM_4118414 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | C1-Ultra | #4193780 | ARM64_ERRATUM_4118414 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | MMU-500 | #841119,826419 | N/A |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | MMU-600 | #1076982,1209401| N/A |

‎arch/arm64/Kconfig‎

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@@ -1021,6 +1021,42 @@ config ARM64_ERRATUM_2966298
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If unsure, say Y.
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config ARM64_ERRATUM_4118414
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bool "Cortex-*/Neoverse-*/C1-*: Completion of affected memory accesses might not be guaranteed by completion of a TLBI"
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default y
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select ARM64_WORKAROUND_REPEAT_TLBI
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help
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This option adds a workaround for the following errata:
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* ARM C1-Premium erratum 4193780
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* ARM C1-Ultra erratum 4193780
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* ARM Cortex-A76 erratum 4193800
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* ARM Cortex-A76AE erratum 4193801
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* ARM Cortex-A77 erratum 4193798
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* ARM Cortex-A78 erratum 4193791
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* ARM Cortex-A78AE erratum 4193793
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* ARM Cortex-A78C erratum 4193794
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* ARM Cortex-A710 erratum 4193788
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* ARM Cortex-X1 erratum 4193791
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* ARM Cortex-X1C erratum 4193792
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* ARM Cortex-X2 erratum 4193788
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* ARM Cortex-X3 erratum 4193786
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* ARM Cortex-X4 erratum 4118414
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* ARM Cortex-X925 erratum 4193781
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* ARM Neoverse-N1 erratum 4193800
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* ARM Neoverse-N2 erratum 4193789
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* ARM Neoverse-V1 erratum 4193790
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* ARM Neoverse-V2 erratum 4193787
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* ARM Neoverse-V3 erratum 4193784
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* ARM Neoverse-V3AE erratum 4193784
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On affected cores, some memory accesses might not be completed by
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broadcast TLB invalidation.
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This issue is also known as CVE-2025-10263.
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If unsure, say Y.
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config CAVIUM_ERRATUM_22375
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bool "Cavium erratum 22375, 24313"
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default y

‎arch/arm64/kernel/cpu_errata.c‎

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@@ -241,7 +241,35 @@ static const struct arm64_cpu_capabilities arm64_repeat_tlbi_list[] = {
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ERRATA_MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1),
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},
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#endif
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{},
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#ifdef CONFIG_ARM64_ERRATUM_4118414
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{
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ERRATA_MIDR_RANGE_LIST(((const struct midr_range[]) {
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MIDR_ALL_VERSIONS(MIDR_C1_PREMIUM),
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MIDR_ALL_VERSIONS(MIDR_C1_ULTRA),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A76),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A76AE),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A77),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A78),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A78AE),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A78C),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_X1),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_X1C),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_X2),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_X3),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_X4),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_X925),
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MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1),
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MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
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MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1),
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MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V2),
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MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3),
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MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3AE),
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{}
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})),
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},
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#endif
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{}
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};
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#endif
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#endif
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#ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI
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{
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.desc = "Qualcomm erratum 1009, or ARM erratum 1286807, 2441009",
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.desc = "Broken broadcast TLBI completion",
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.capability = ARM64_WORKAROUND_REPEAT_TLBI,
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.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
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.matches = cpucap_multi_entry_cap_matches,

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