[ciqlts9_6] Multiple patches tested (12 commits) by ciq-kernel-automation[bot] · Pull Request #1322 · ctrliq/kernel-src-tree

ciq-kernel-automation · 2026-06-10T23:51:54Z

Summary

This PR has been automatically created after successful completion of all CI stages.

Commit Message(s)

arm64: cputype: Add MIDR_CORTEX_A76AE

jira VULN-187523
cve-pre CVE-2025-10263
commit-author Douglas Anderson <dianders@chromium.org>
commit a9b5bd81b294d30a747edd125e9f6aef2def7c79

arm64: cputype: Add Cortex-A725 definitions

jira VULN-187523
cve-pre CVE-2025-10263
commit-author Mark Rutland <mark.rutland@arm.com>
commit 9ef54a384526911095db465e77acc1cb5266b32c

arm64: cputype: Add Cortex-A720AE definitions

jira VULN-187523
cve-pre CVE-2025-10263
commit-author Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
commit f38c2c3e572ce0ce5c01de0358ed70328e0cb5af

arm64: cputype: Add Neoverse-N3 definitions

jira VULN-187523
cve-pre CVE-2025-10263
commit-author Mark Rutland <mark.rutland@arm.com>
commit 924725707d80bc2588cefafef76ff3f164d299bc

arm64: cputype: Add Neoverse-V3AE definitions

jira VULN-187523
cve-pre CVE-2025-10263
commit-author Mark Rutland <mark.rutland@arm.com>
commit 3bbf004c4808e2c3241e5c1ad6cc102f38a03c39

arm64: cputype: Add C1-Pro definitions

jira VULN-187523
cve-pre CVE-2025-10263
commit-author Catalin Marinas <catalin.marinas@arm.com>
commit 2c99561016c591f4c3d5ad7d22a61b8726e79735

arm64: cputype: Add NVIDIA Olympus definitions

jira VULN-187523
cve-pre CVE-2025-10263
commit-author Shanker Donthineni <sdonthineni@nvidia.com>
commit e185c8a0d84236d14af61faff8147c953a878a77

arm64: cputype: Add C1-Ultra definitions

jira VULN-187523
cve-pre CVE-2025-10263
commit-author Mark Rutland <mark.rutland@arm.com>
commit -
commit-source-sha 60349e64a6c65f9f0aa118af711b3c7e137f07ff
commit-source arm64

arm64: cputype: Add C1-Premium definitions

jira VULN-187523
cve-pre CVE-2025-10263
commit-author Mark Rutland <mark.rutland@arm.com>
commit -
commit-source-sha d28413bfc5a255957241f1df5d7fd0c2cd74fe18
commit-source arm64

arm64: errata: Mitigate TLBI errata on various Arm CPUs

jira VULN-187523
cve CVE-2025-10263
commit-author Mark Rutland <mark.rutland@arm.com>
commit -
commit-source-sha cfd391e74134db664feb499d43af286380b10ba8
commit-source arm64
upstream-diff silicon-errata.rst at different path (Documentation/arm64/ vs
  Documentation/arch/arm64/) and required manual conflict resolution due to
  condensed table formatting and missing entries in our branch. Content is
  identical.

arm64: errata: Mitigate TLBI errata on NVIDIA Olympus CPU

jira VULN-187523
cve CVE-2025-10263
commit-author Shanker Donthineni <sdonthineni@nvidia.com>
commit -
commit-source-sha ec7216f92e4ebd485b1c6dc6aa3f6064b71a5768
commit-source arm64

arm64: errata: Mitigate TLBI errata on Microsoft Azure Cobalt 100 CPU

jira VULN-187523
cve CVE-2025-10263
commit-author Will Deacon <will@kernel.org>
commit -
commit-source-sha 1940e70a8144bf75e6df26bf6f600862ea7f7ea1
commit-source arm64

Test Results

✅ Build Stage

Architecture	Build Time	Total Time
x86_64	31m 4s	32m 0s
aarch64	18m 49s	19m 30s

View build logs

✅ Boot Verification

Status: Passed (all architectures)
View boot logs

✅ Kernel Selftests

Architecture	Passed	Failed	Compared Against	Status
x86_64	208	41	ciqlts9_6	✅ No regressions
aarch64	155	44	ciqlts9_6	✅ No regressions

View kselftest logs

✅ LTP Results

Architecture	Passed	Failed	Compared Against	Status
x86_64	1453	82	ciqlts9_6	✅ No regressions
aarch64	1426	83	ciqlts9_6	✅ No regressions

View LTP logs

x86_64 newly passing:

futex_wake04 (FAIL -> PASS)

🤖 This PR was automatically generated by GitHub Actions
Run ID: 27339722346

github-actions · 2026-06-11T00:00:50Z

🤖 Validation Checks In Progress Workflow run: https://github.com/ctrliq/kernel-src-tree/actions/runs/27314338098

github-actions · 2026-06-11T00:00:51Z

🔍 Upstream Linux Kernel Commit Check

❗ PR commit e6b40b6ab9e (arm64: errata: Mitigate TLBI errata on NVIDIA Olympus CPU) references upstream commit
ec7216f92e4e which does not exist in the upstream Linux kernel.
❗ PR commit d5d69305b49 (arm64: errata: Mitigate TLBI errata on Microsoft Azure Cobalt 100 CPU) references upstream commit
1940e70a8144 which does not exist in the upstream Linux kernel.

This is an automated message from the kernel commit checker workflow.

github-actions · 2026-06-11T00:00:52Z

🔍 Interdiff Analysis

⚠️ PR commit e6a941fed86 (arm64: cputype: Add Cortex-A720AE definitions) → upstream f38c2c3e572c
Differences found:

================================================================================
*    DELTA DIFFERENCES - code changes that differ between the patches          *
================================================================================

--- b/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -95,8 +95,6 @@
 #define ARM_CPU_PART_NEOVERSE_V3	0xD84
 #define ARM_CPU_PART_CORTEX_X925	0xD85
 #define ARM_CPU_PART_CORTEX_A725	0xD87
-#define ARM_CPU_PART_CORTEX_A720AE	0xD89
-#define ARM_CPU_PART_NEOVERSE_N3	0xD8E
 
 #define APM_CPU_PART_XGENE		0x000
 #define APM_CPU_VAR_POTENZA		0x00
@@ -179,8 +177,6 @@
 #define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3)
 #define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925)
 #define MIDR_CORTEX_A725 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A725)
-#define MIDR_CORTEX_A720AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720AE)
-#define MIDR_NEOVERSE_N3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N3)
 #define MIDR_THUNDERX	MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
 #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
 #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)

################################################################################
!    REJECTED PATCH2 HUNKS - could not be compared; manual review needed       !
################################################################################

--- b/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -96,6 +96,7 @@
 #define ARM_CPU_PART_NEOVERSE_V3	0xD84
 #define ARM_CPU_PART_CORTEX_X925	0xD85
 #define ARM_CPU_PART_CORTEX_A725	0xD87
+#define ARM_CPU_PART_CORTEX_A720AE	0xD89
 #define ARM_CPU_PART_NEOVERSE_N3	0xD8E
 
 #define APM_CPU_PART_XGENE		0x000
@@ -185,6 +186,7 @@
 #define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3)
 #define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925)
 #define MIDR_CORTEX_A725 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A725)
+#define MIDR_CORTEX_A720AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720AE)
 #define MIDR_NEOVERSE_N3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N3)
 #define MIDR_THUNDERX	MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
 #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)

================================================================================
*    CONTEXT DIFFERENCES - surrounding code differences between the patches    *
================================================================================

--- b/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -93,4 +93,5 @@
 #define ARM_CPU_PART_CORTEX_X925	0xD85
 #define ARM_CPU_PART_CORTEX_A725	0xD87
+#define ARM_CPU_PART_NEOVERSE_N3	0xD8E
 
 #define APM_CPU_PART_XGENE		0x000
@@ -178,4 +186,5 @@
 #define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925)
 #define MIDR_CORTEX_A725 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A725)
+#define MIDR_NEOVERSE_N3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N3)
 #define MIDR_THUNDERX	MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
 #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)

⚠️ PR commit cbaa65452f0 (arm64: cputype: Add NVIDIA Olympus definitions) → upstream e185c8a0d842
Differences found:

================================================================================
*    CONTEXT DIFFERENCES - surrounding code differences between the patches    *
================================================================================

--- b/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -204,5 +205,5 @@
 #define MIDR_NVIDIA_DENVER MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_DENVER)
 #define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL)
 #define MIDR_FUJITSU_A64FX MIDR_CPU_MODEL(ARM_CPU_IMP_FUJITSU, FUJITSU_CPU_PART_A64FX)
 #define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110)
-#define MIDR_APPLE_M1_ICESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM)
+#define MIDR_HISI_HIP09 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_HIP09)

❌ PR commit e6b40b6ab9e (arm64: errata: Mitigate TLBI errata on NVIDIA Olympus CPU) → ec7216f92e4e
Error: Failed to generate patch for upstream commit: Git command failed: format-patch -1 --stdout ec7216f
fatal: bad object ec7216f
❌ PR commit d5d69305b49 (arm64: errata: Mitigate TLBI errata on Microsoft Azure Cobalt 100 CPU) → 1940e70a8144
Error: Failed to generate patch for upstream commit: Git command failed: format-patch -1 --stdout 1940e70
fatal: bad object 1940e70

This is an automated interdiff check for backported commits.

github-actions · 2026-06-11T00:02:26Z

JIRA PR Check Results

11 commit(s) with issues found:

Commit `d5d69305b490`

Summary: arm64: errata: Mitigate TLBI errata on Microsoft Azure Cobalt 100 CPU

❌ Errors:

VULN-XXXXXX: Failed to retrieve ticket: JiraError HTTP 404 url: https://ciqinc.atlassian.net/rest/api/2/issue/VULN-XXXXXX
text: Issue does not exist or you do not have permission to see it.

response headers = {'Content-Type': 'application/json;charset=UTF-8', 'Transfer-Encoding': 'chunked', 'Connection': 'keep-alive', 'Date': 'Thu, 11 Jun 2026 00:02:23 GMT', 'Server': 'AtlassianEdge', 'Timing-Allow-Origin': '*', 'X-Arequestid': '877c264db06e838e070ea6163dee4bb8', 'X-Aaccountid': '712020%3A43f5a558-0b78-4cc1-ad9e-a61d9b0317de', 'Cache-Control': 'no-cache, no-store, no-transform', 'Ratelimit-Policy': '"jira-burst-based";q=150;w=1', 'Ratelimit': '"jira-burst-based";r=399;t=1', 'X-Ratelimit-Limit': '400', 'X-Ratelimit-Remaining': '399', 'Content-Encoding': 'gzip', 'X-Content-Type-Options': 'nosniff', 'X-Xss-Protection': '1; mode=block', 'Atl-Traceid': '5fe148d7868f40a09be49decbd5b80b2', 'Atl-Request-Id': '5fe148d7-868f-40a0-9be4-9decbd5b80b2', 'Strict-Transport-Security': 'max-age=63072000; includeSubDomains; preload', 'Report-To': '{"endpoints": [{"url": "https://dz8aopenkvv6s.cloudfront.net"}], "group": "endpoint-1", "include_subdomains": true, "max_age": 600}', 'Nel': '{"failure_fraction": 0.01, "include_subdomains": true, "max_age": 600, "report_to": "endpoint-1"}', 'Server-Timing': 'atl-edge;dur=61,atl-edge-internal;dur=15,atl-edge-upstream;dur=46,atl-edge-pop;desc="aws-us-west-2"', 'X-Cache': 'Error from cloudfront', 'Via': '1.1 4165698929ff6aa963c860cf9537dfb6.cloudfront.net (CloudFront)', 'X-Amz-Cf-Pop': 'DFW59-P8', 'X-Amz-Cf-Id': 'vR6Jm_q0_6BJZWq01G0dhhdX3WeMcPRmfZyROQ8RW0E6vw2QXVGuFA=='}
response text = {"errorMessages":["Issue does not exist or you do not have permission to see it."],"errors":{}}

Commit `e6b40b6ab9ed`

Summary: arm64: errata: Mitigate TLBI errata on NVIDIA Olympus CPU

❌ Errors:

VULN-XXXXXX: Failed to retrieve ticket: JiraError HTTP 404 url: https://ciqinc.atlassian.net/rest/api/2/issue/VULN-XXXXXX
text: Issue does not exist or you do not have permission to see it.

response headers = {'Content-Type': 'application/json;charset=UTF-8', 'Transfer-Encoding': 'chunked', 'Connection': 'keep-alive', 'Date': 'Thu, 11 Jun 2026 00:02:24 GMT', 'Server': 'AtlassianEdge', 'Timing-Allow-Origin': '*', 'X-Arequestid': 'dd2dfce3cc7d69efce0dd4034629fb69', 'X-Aaccountid': '712020%3A43f5a558-0b78-4cc1-ad9e-a61d9b0317de', 'Cache-Control': 'no-cache, no-store, no-transform', 'Ratelimit-Policy': '"jira-burst-based";q=150;w=1', 'Ratelimit': '"jira-burst-based";r=398;t=1', 'X-Ratelimit-Limit': '400', 'X-Ratelimit-Remaining': '398', 'Content-Encoding': 'gzip', 'X-Content-Type-Options': 'nosniff', 'X-Xss-Protection': '1; mode=block', 'Atl-Traceid': 'be420e4cce1b4e33bbb12d426fd8a1fc', 'Atl-Request-Id': 'be420e4c-ce1b-4e33-bbb1-2d426fd8a1fc', 'Strict-Transport-Security': 'max-age=63072000; includeSubDomains; preload', 'Report-To': '{"endpoints": [{"url": "https://dz8aopenkvv6s.cloudfront.net"}], "group": "endpoint-1", "include_subdomains": true, "max_age": 600}', 'Nel': '{"failure_fraction": 0.01, "include_subdomains": true, "max_age": 600, "report_to": "endpoint-1"}', 'Server-Timing': 'atl-edge;dur=62,atl-edge-internal;dur=18,atl-edge-upstream;dur=44,atl-edge-pop;desc="aws-us-west-2"', 'X-Cache': 'Error from cloudfront', 'Via': '1.1 4165698929ff6aa963c860cf9537dfb6.cloudfront.net (CloudFront)', 'X-Amz-Cf-Pop': 'DFW59-P8', 'X-Amz-Cf-Id': 'RoCRvt7NEl_IxpxtQXQgsPxdy7rInsj_9d61Tr-JtycIW2Md3MheYg=='}
response text = {"errorMessages":["Issue does not exist or you do not have permission to see it."],"errors":{}}

Commit `61fb9b9b3c5d`

Summary: arm64: errata: Mitigate TLBI errata on various Arm CPUs

❌ Errors:

VULN-XXXXXX: Failed to retrieve ticket: JiraError HTTP 404 url: https://ciqinc.atlassian.net/rest/api/2/issue/VULN-XXXXXX
text: Issue does not exist or you do not have permission to see it.

response headers = {'Content-Type': 'application/json;charset=UTF-8', 'Transfer-Encoding': 'chunked', 'Connection': 'keep-alive', 'Date': 'Thu, 11 Jun 2026 00:02:24 GMT', 'Server': 'AtlassianEdge', 'Timing-Allow-Origin': '*', 'X-Arequestid': 'b6a40b036cf63794722b59c9b3a7b865', 'X-Aaccountid': '712020%3A43f5a558-0b78-4cc1-ad9e-a61d9b0317de', 'Cache-Control': 'no-cache, no-store, no-transform', 'Ratelimit-Policy': '"jira-burst-based";q=150;w=1', 'Ratelimit': '"jira-burst-based";r=397;t=1', 'X-Ratelimit-Limit': '400', 'X-Ratelimit-Remaining': '397', 'Content-Encoding': 'gzip', 'X-Content-Type-Options': 'nosniff', 'X-Xss-Protection': '1; mode=block', 'Atl-Traceid': '28b7a50dbb1343f1b441abc4aa2e92bb', 'Atl-Request-Id': '28b7a50d-bb13-43f1-b441-abc4aa2e92bb', 'Strict-Transport-Security': 'max-age=63072000; includeSubDomains; preload', 'Report-To': '{"endpoints": [{"url": "https://dz8aopenkvv6s.cloudfront.net"}], "group": "endpoint-1", "include_subdomains": true, "max_age": 600}', 'Nel': '{"failure_fraction": 0.01, "include_subdomains": true, "max_age": 600, "report_to": "endpoint-1"}', 'Server-Timing': 'atl-edge;dur=56,atl-edge-internal;dur=15,atl-edge-upstream;dur=42,atl-edge-pop;desc="aws-us-west-2"', 'X-Cache': 'Error from cloudfront', 'Via': '1.1 4165698929ff6aa963c860cf9537dfb6.cloudfront.net (CloudFront)', 'X-Amz-Cf-Pop': 'DFW59-P8', 'X-Amz-Cf-Id': 'gwxQmBu4lxNw6ywplhhlVUvJlbYy0yKe5cBdXUwa2ybYNgebfuzocQ=='}
response text = {"errorMessages":["Issue does not exist or you do not have permission to see it."],"errors":{}}

Commit `16b020e24ab2`

Summary: arm64: cputype: Add C1-Premium definitions

❌ Errors:

VULN-XXXXXX: Failed to retrieve ticket: JiraError HTTP 404 url: https://ciqinc.atlassian.net/rest/api/2/issue/VULN-XXXXXX
text: Issue does not exist or you do not have permission to see it.

response headers = {'Content-Type': 'application/json;charset=UTF-8', 'Transfer-Encoding': 'chunked', 'Connection': 'keep-alive', 'Date': 'Thu, 11 Jun 2026 00:02:24 GMT', 'Server': 'AtlassianEdge', 'Timing-Allow-Origin': '*', 'X-Arequestid': '84b391944aeaff1fdf43f2c9854a0ef4', 'X-Aaccountid': '712020%3A43f5a558-0b78-4cc1-ad9e-a61d9b0317de', 'Cache-Control': 'no-cache, no-store, no-transform', 'Ratelimit-Policy': '"jira-burst-based";q=150;w=1', 'Ratelimit': '"jira-burst-based";r=396;t=1', 'X-Ratelimit-Limit': '400', 'X-Ratelimit-Remaining': '396', 'Content-Encoding': 'gzip', 'X-Content-Type-Options': 'nosniff', 'X-Xss-Protection': '1; mode=block', 'Atl-Traceid': '5a784bef661a4ce785d9d29b90b25acc', 'Atl-Request-Id': '5a784bef-661a-4ce7-85d9-d29b90b25acc', 'Strict-Transport-Security': 'max-age=63072000; includeSubDomains; preload', 'Report-To': '{"endpoints": [{"url": "https://dz8aopenkvv6s.cloudfront.net"}], "group": "endpoint-1", "include_subdomains": true, "max_age": 600}', 'Nel': '{"failure_fraction": 0.01, "include_subdomains": true, "max_age": 600, "report_to": "endpoint-1"}', 'Server-Timing': 'atl-edge;dur=66,atl-edge-internal;dur=24,atl-edge-upstream;dur=41,atl-edge-pop;desc="aws-us-west-2"', 'X-Cache': 'Error from cloudfront', 'Via': '1.1 4165698929ff6aa963c860cf9537dfb6.cloudfront.net (CloudFront)', 'X-Amz-Cf-Pop': 'DFW59-P8', 'X-Amz-Cf-Id': '64WgmCzwG8fV7iZbHPyjZTZhXzDtVo0B0Ni_E94w_JyXEplyRGtNLw=='}
response text = {"errorMessages":["Issue does not exist or you do not have permission to see it."],"errors":{}}

Commit `3123c8097a7a`

Summary: arm64: cputype: Add C1-Ultra definitions

❌ Errors:

VULN-XXXXXX: Failed to retrieve ticket: JiraError HTTP 404 url: https://ciqinc.atlassian.net/rest/api/2/issue/VULN-XXXXXX
text: Issue does not exist or you do not have permission to see it.

response headers = {'Content-Type': 'application/json;charset=UTF-8', 'Transfer-Encoding': 'chunked', 'Connection': 'keep-alive', 'Date': 'Thu, 11 Jun 2026 00:02:24 GMT', 'Server': 'AtlassianEdge', 'Timing-Allow-Origin': '*', 'X-Arequestid': '652aa8fc93e7794a3a8f59b6572c6aac', 'X-Aaccountid': '712020%3A43f5a558-0b78-4cc1-ad9e-a61d9b0317de', 'Cache-Control': 'no-cache, no-store, no-transform', 'Ratelimit-Policy': '"jira-burst-based";q=150;w=1', 'Ratelimit': '"jira-burst-based";r=395;t=1', 'X-Ratelimit-Limit': '400', 'X-Ratelimit-Remaining': '395', 'Content-Encoding': 'gzip', 'X-Content-Type-Options': 'nosniff', 'X-Xss-Protection': '1; mode=block', 'Atl-Traceid': '3df13f61a34c48419e618463fc798790', 'Atl-Request-Id': '3df13f61-a34c-4841-9e61-8463fc798790', 'Strict-Transport-Security': 'max-age=63072000; includeSubDomains; preload', 'Report-To': '{"endpoints": [{"url": "https://dz8aopenkvv6s.cloudfront.net"}], "group": "endpoint-1", "include_subdomains": true, "max_age": 600}', 'Nel': '{"failure_fraction": 0.01, "include_subdomains": true, "max_age": 600, "report_to": "endpoint-1"}', 'Server-Timing': 'atl-edge;dur=70,atl-edge-internal;dur=16,atl-edge-upstream;dur=54,atl-edge-pop;desc="aws-us-west-2"', 'X-Cache': 'Error from cloudfront', 'Via': '1.1 4165698929ff6aa963c860cf9537dfb6.cloudfront.net (CloudFront)', 'X-Amz-Cf-Pop': 'DFW59-P8', 'X-Amz-Cf-Id': 'T7eZB4h4jd_Q7IWd7yfR-nL6LWMTp8_IW3BsYEUzjI-bBgSEQZ_TBw=='}
response text = {"errorMessages":["Issue does not exist or you do not have permission to see it."],"errors":{}}

Commit `cbaa65452f03`

Summary: arm64: cputype: Add NVIDIA Olympus definitions

❌ Errors:

VULN-XXXXXX: Failed to retrieve ticket: JiraError HTTP 404 url: https://ciqinc.atlassian.net/rest/api/2/issue/VULN-XXXXXX
text: Issue does not exist or you do not have permission to see it.

response headers = {'Content-Type': 'application/json;charset=UTF-8', 'Transfer-Encoding': 'chunked', 'Connection': 'keep-alive', 'Date': 'Thu, 11 Jun 2026 00:02:24 GMT', 'Server': 'AtlassianEdge', 'Timing-Allow-Origin': '*', 'X-Arequestid': '0ce4be3fb769ba49560a73a9e2835961', 'X-Aaccountid': '712020%3A43f5a558-0b78-4cc1-ad9e-a61d9b0317de', 'Cache-Control': 'no-cache, no-store, no-transform', 'Ratelimit-Policy': '"jira-burst-based";q=150;w=1', 'Ratelimit': '"jira-burst-based";r=394;t=1', 'X-Ratelimit-Limit': '400', 'X-Ratelimit-Remaining': '394', 'Content-Encoding': 'gzip', 'X-Content-Type-Options': 'nosniff', 'X-Xss-Protection': '1; mode=block', 'Atl-Traceid': '86ca08fff9b64f67991a2796bde50da9', 'Atl-Request-Id': '86ca08ff-f9b6-4f67-991a-2796bde50da9', 'Strict-Transport-Security': 'max-age=63072000; includeSubDomains; preload', 'Report-To': '{"endpoints": [{"url": "https://dz8aopenkvv6s.cloudfront.net"}], "group": "endpoint-1", "include_subdomains": true, "max_age": 600}', 'Nel': '{"failure_fraction": 0.01, "include_subdomains": true, "max_age": 600, "report_to": "endpoint-1"}', 'Server-Timing': 'atl-edge;dur=79,atl-edge-internal;dur=16,atl-edge-upstream;dur=46,atl-edge-pop;desc="aws-us-west-2"', 'X-Cache': 'Error from cloudfront', 'Via': '1.1 4165698929ff6aa963c860cf9537dfb6.cloudfront.net (CloudFront)', 'X-Amz-Cf-Pop': 'DFW59-P8', 'X-Amz-Cf-Id': '4wqXazDVFoE7jw1T4IhYxL2BWQxzPwpVm87ecpKf_AzIZ4CEZUCxXQ=='}
response text = {"errorMessages":["Issue does not exist or you do not have permission to see it."],"errors":{}}

Commit `813d93bbb626`

Summary: arm64: cputype: Add C1-Pro definitions

❌ Errors:

VULN-XXXXXX: Failed to retrieve ticket: JiraError HTTP 404 url: https://ciqinc.atlassian.net/rest/api/2/issue/VULN-XXXXXX
text: Issue does not exist or you do not have permission to see it.

response headers = {'Content-Type': 'application/json;charset=UTF-8', 'Transfer-Encoding': 'chunked', 'Connection': 'keep-alive', 'Date': 'Thu, 11 Jun 2026 00:02:24 GMT', 'Server': 'AtlassianEdge', 'Timing-Allow-Origin': '*', 'X-Arequestid': '3b79e2fec2183fe4ae69a6cc2e10a7b8', 'X-Aaccountid': '712020%3A43f5a558-0b78-4cc1-ad9e-a61d9b0317de', 'Cache-Control': 'no-cache, no-store, no-transform', 'Ratelimit-Policy': '"jira-burst-based";q=150;w=1', 'Ratelimit': '"jira-burst-based";r=393;t=1', 'X-Ratelimit-Limit': '400', 'X-Ratelimit-Remaining': '393', 'Content-Encoding': 'gzip', 'X-Content-Type-Options': 'nosniff', 'X-Xss-Protection': '1; mode=block', 'Atl-Traceid': '3b2cd109e98c41e6838a02f944c606dd', 'Atl-Request-Id': '3b2cd109-e98c-41e6-838a-02f944c606dd', 'Strict-Transport-Security': 'max-age=63072000; includeSubDomains; preload', 'Report-To': '{"endpoints": [{"url": "https://dz8aopenkvv6s.cloudfront.net"}], "group": "endpoint-1", "include_subdomains": true, "max_age": 600}', 'Nel': '{"failure_fraction": 0.01, "include_subdomains": true, "max_age": 600, "report_to": "endpoint-1"}', 'Server-Timing': 'atl-edge;dur=60,atl-edge-internal;dur=13,atl-edge-upstream;dur=47,atl-edge-pop;desc="aws-us-west-2"', 'X-Cache': 'Error from cloudfront', 'Via': '1.1 4165698929ff6aa963c860cf9537dfb6.cloudfront.net (CloudFront)', 'X-Amz-Cf-Pop': 'DFW59-P8', 'X-Amz-Cf-Id': 'ibim1gNzLhZOT264lTgl9S94I7o32f5dUrkNo48ZqvCEFos3QLpuqA=='}
response text = {"errorMessages":["Issue does not exist or you do not have permission to see it."],"errors":{}}

Commit `7e1561e3bbf5`

Summary: arm64: cputype: Add Neoverse-V3AE definitions

❌ Errors:

VULN-XXXXXX: Failed to retrieve ticket: JiraError HTTP 404 url: https://ciqinc.atlassian.net/rest/api/2/issue/VULN-XXXXXX
text: Issue does not exist or you do not have permission to see it.

response headers = {'Content-Type': 'application/json;charset=UTF-8', 'Transfer-Encoding': 'chunked', 'Connection': 'keep-alive', 'Date': 'Thu, 11 Jun 2026 00:02:24 GMT', 'Server': 'AtlassianEdge', 'Timing-Allow-Origin': '*', 'X-Arequestid': '87dea55d45ff731cd921c8c7284f6607', 'X-Aaccountid': '712020%3A43f5a558-0b78-4cc1-ad9e-a61d9b0317de', 'Cache-Control': 'no-cache, no-store, no-transform', 'Ratelimit-Policy': '"jira-burst-based";q=150;w=1', 'Ratelimit': '"jira-burst-based";r=392;t=1', 'X-Ratelimit-Limit': '400', 'X-Ratelimit-Remaining': '392', 'Content-Encoding': 'gzip', 'X-Content-Type-Options': 'nosniff', 'X-Xss-Protection': '1; mode=block', 'Atl-Traceid': 'b508d58e03d242b88495ab686ade3170', 'Atl-Request-Id': 'b508d58e-03d2-42b8-8495-ab686ade3170', 'Strict-Transport-Security': 'max-age=63072000; includeSubDomains; preload', 'Report-To': '{"endpoints": [{"url": "https://dz8aopenkvv6s.cloudfront.net"}], "group": "endpoint-1", "include_subdomains": true, "max_age": 600}', 'Nel': '{"failure_fraction": 0.01, "include_subdomains": true, "max_age": 600, "report_to": "endpoint-1"}', 'Server-Timing': 'atl-edge;dur=58,atl-edge-internal;dur=14,atl-edge-upstream;dur=44,atl-edge-pop;desc="aws-us-west-2"', 'X-Cache': 'Error from cloudfront', 'Via': '1.1 4165698929ff6aa963c860cf9537dfb6.cloudfront.net (CloudFront)', 'X-Amz-Cf-Pop': 'DFW59-P8', 'X-Amz-Cf-Id': 'Y1IJaSm8kqeu6jAL31t7YtGaubzvql5RCvhBGURI3mnp3JsLgM3_8g=='}
response text = {"errorMessages":["Issue does not exist or you do not have permission to see it."],"errors":{}}

Commit `e6a941fed86c`

Summary: arm64: cputype: Add Cortex-A720AE definitions

❌ Errors:

VULN-XXXXXX: Failed to retrieve ticket: JiraError HTTP 404 url: https://ciqinc.atlassian.net/rest/api/2/issue/VULN-XXXXXX
text: Issue does not exist or you do not have permission to see it.

response headers = {'Content-Type': 'application/json;charset=UTF-8', 'Transfer-Encoding': 'chunked', 'Connection': 'keep-alive', 'Date': 'Thu, 11 Jun 2026 00:02:25 GMT', 'Server': 'AtlassianEdge', 'Timing-Allow-Origin': '*', 'X-Arequestid': 'f7a9e5a8c4983076d76f215991878b91', 'X-Aaccountid': '712020%3A43f5a558-0b78-4cc1-ad9e-a61d9b0317de', 'Cache-Control': 'no-cache, no-store, no-transform', 'Ratelimit-Policy': '"jira-burst-based";q=150;w=1', 'Ratelimit': '"jira-burst-based";r=399;t=1', 'X-Ratelimit-Limit': '400', 'X-Ratelimit-Remaining': '399', 'Content-Encoding': 'gzip', 'X-Content-Type-Options': 'nosniff', 'X-Xss-Protection': '1; mode=block', 'Atl-Traceid': 'ed7dcf24d9ce4bfaac99f82524a0610e', 'Atl-Request-Id': 'ed7dcf24-d9ce-4bfa-ac99-f82524a0610e', 'Strict-Transport-Security': 'max-age=63072000; includeSubDomains; preload', 'Report-To': '{"endpoints": [{"url": "https://dz8aopenkvv6s.cloudfront.net"}], "group": "endpoint-1", "include_subdomains": true, "max_age": 600}', 'Nel': '{"failure_fraction": 0.01, "include_subdomains": true, "max_age": 600, "report_to": "endpoint-1"}', 'Server-Timing': 'atl-edge;dur=63,atl-edge-internal;dur=13,atl-edge-upstream;dur=49,atl-edge-pop;desc="aws-us-west-2"', 'X-Cache': 'Error from cloudfront', 'Via': '1.1 4165698929ff6aa963c860cf9537dfb6.cloudfront.net (CloudFront)', 'X-Amz-Cf-Pop': 'DFW59-P8', 'X-Amz-Cf-Id': 'IXyv38qHi2hfFh4YqrGJv4noW_VHL5w9G-ak4gYVKBD35NRGGncJrQ=='}
response text = {"errorMessages":["Issue does not exist or you do not have permission to see it."],"errors":{}}

Commit `27e45d4ebb33`

Summary: arm64: cputype: Add Cortex-A725 definitions

❌ Errors:

VULN-XXXXXX: Failed to retrieve ticket: JiraError HTTP 404 url: https://ciqinc.atlassian.net/rest/api/2/issue/VULN-XXXXXX
text: Issue does not exist or you do not have permission to see it.

response headers = {'Content-Type': 'application/json;charset=UTF-8', 'Transfer-Encoding': 'chunked', 'Connection': 'keep-alive', 'Date': 'Thu, 11 Jun 2026 00:02:25 GMT', 'Server': 'AtlassianEdge', 'Timing-Allow-Origin': '*', 'X-Arequestid': '5944747d94e9ac15b5ef78918742e4f7', 'X-Aaccountid': '712020%3A43f5a558-0b78-4cc1-ad9e-a61d9b0317de', 'Cache-Control': 'no-cache, no-store, no-transform', 'Ratelimit-Policy': '"jira-burst-based";q=150;w=1', 'Ratelimit': '"jira-burst-based";r=398;t=1', 'X-Ratelimit-Limit': '400', 'X-Ratelimit-Remaining': '398', 'Content-Encoding': 'gzip', 'X-Content-Type-Options': 'nosniff', 'X-Xss-Protection': '1; mode=block', 'Atl-Traceid': '2c9fb10f9237414cab2e2e005af59cd9', 'Atl-Request-Id': '2c9fb10f-9237-414c-ab2e-2e005af59cd9', 'Strict-Transport-Security': 'max-age=63072000; includeSubDomains; preload', 'Report-To': '{"endpoints": [{"url": "https://dz8aopenkvv6s.cloudfront.net"}], "group": "endpoint-1", "include_subdomains": true, "max_age": 600}', 'Nel': '{"failure_fraction": 0.01, "include_subdomains": true, "max_age": 600, "report_to": "endpoint-1"}', 'Server-Timing': 'atl-edge;dur=58,atl-edge-internal;dur=16,atl-edge-upstream;dur=42,atl-edge-pop;desc="aws-us-west-2"', 'X-Cache': 'Error from cloudfront', 'Via': '1.1 4165698929ff6aa963c860cf9537dfb6.cloudfront.net (CloudFront)', 'X-Amz-Cf-Pop': 'DFW59-P8', 'X-Amz-Cf-Id': 'Sap_KoJfTelzRiid52qS39CqO6za7KdLrOwVwcGrUcSpRqHv4uu1Sw=='}
response text = {"errorMessages":["Issue does not exist or you do not have permission to see it."],"errors":{}}

Commit `a26f650679fc`

Summary: arm64: cputype: Add MIDR_CORTEX_A76AE

❌ Errors:

VULN-XXXXXX: Failed to retrieve ticket: JiraError HTTP 404 url: https://ciqinc.atlassian.net/rest/api/2/issue/VULN-XXXXXX
text: Issue does not exist or you do not have permission to see it.

response headers = {'Content-Type': 'application/json;charset=UTF-8', 'Transfer-Encoding': 'chunked', 'Connection': 'keep-alive', 'Date': 'Thu, 11 Jun 2026 00:02:25 GMT', 'Server': 'AtlassianEdge', 'Timing-Allow-Origin': '*', 'X-Arequestid': 'd337ef7eacd865ea163691cfc314d064', 'X-Aaccountid': '712020%3A43f5a558-0b78-4cc1-ad9e-a61d9b0317de', 'Cache-Control': 'no-cache, no-store, no-transform', 'Ratelimit-Policy': '"jira-burst-based";q=150;w=1', 'Ratelimit': '"jira-burst-based";r=397;t=1', 'X-Ratelimit-Limit': '400', 'X-Ratelimit-Remaining': '397', 'Content-Encoding': 'gzip', 'X-Content-Type-Options': 'nosniff', 'X-Xss-Protection': '1; mode=block', 'Atl-Traceid': 'c97e7398a49b4d6fb7a70586eeeb78bf', 'Atl-Request-Id': 'c97e7398-a49b-4d6f-b7a7-0586eeeb78bf', 'Strict-Transport-Security': 'max-age=63072000; includeSubDomains; preload', 'Report-To': '{"endpoints": [{"url": "https://dz8aopenkvv6s.cloudfront.net"}], "group": "endpoint-1", "include_subdomains": true, "max_age": 600}', 'Nel': '{"failure_fraction": 0.01, "include_subdomains": true, "max_age": 600, "report_to": "endpoint-1"}', 'Server-Timing': 'atl-edge;dur=62,atl-edge-internal;dur=14,atl-edge-upstream;dur=47,atl-edge-pop;desc="aws-us-west-2"', 'X-Cache': 'Error from cloudfront', 'Via': '1.1 4165698929ff6aa963c860cf9537dfb6.cloudfront.net (CloudFront)', 'X-Amz-Cf-Pop': 'DFW59-P8', 'X-Amz-Cf-Id': 'sdocCry4xHECD_AX2SYXf6X0adwXxX3PwtWQ8QU7uZUNA6ZSJhy_ag=='}
response text = {"errorMessages":["Issue does not exist or you do not have permission to see it."],"errors":{}}

Summary: Checked 11 commit(s) total.

github-actions · 2026-06-11T00:02:26Z

❌ Validation checks completed with issues View full results: https://github.com/ctrliq/kernel-src-tree/actions/runs/27314338098

github-actions · 2026-06-11T00:11:34Z

🤖 Validation Checks In Progress Workflow run: https://github.com/ctrliq/kernel-src-tree/actions/runs/27314772468

github-actions · 2026-06-11T00:11:35Z

🔍 Upstream Linux Kernel Commit Check

❗ PR commit cbb22e5d703 (arm64: errata: Mitigate TLBI errata on NVIDIA Olympus CPU) references upstream commit
ec7216f92e4e which does not exist in the upstream Linux kernel.
❗ PR commit 03f010f69cf (arm64: errata: Mitigate TLBI errata on Microsoft Azure Cobalt 100 CPU) references upstream commit
1940e70a8144 which does not exist in the upstream Linux kernel.

This is an automated message from the kernel commit checker workflow.

github-actions · 2026-06-11T00:11:36Z

🔍 Interdiff Analysis

⚠️ PR commit df7f112585e (arm64: cputype: Add Cortex-A720AE definitions) → upstream f38c2c3e572c
Differences found:

################################################################################
!    REJECTED PATCH2 HUNKS - could not be compared; manual review needed       !
################################################################################

--- b/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -96,6 +96,7 @@
 #define ARM_CPU_PART_NEOVERSE_V3	0xD84
 #define ARM_CPU_PART_CORTEX_X925	0xD85
 #define ARM_CPU_PART_CORTEX_A725	0xD87
+#define ARM_CPU_PART_CORTEX_A720AE	0xD89
 #define ARM_CPU_PART_NEOVERSE_N3	0xD8E
 
 #define APM_CPU_PART_XGENE		0x000
@@ -185,6 +186,7 @@
 #define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3)
 #define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925)
 #define MIDR_CORTEX_A725 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A725)
+#define MIDR_CORTEX_A720AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720AE)
 #define MIDR_NEOVERSE_N3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N3)
 #define MIDR_THUNDERX	MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
 #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)

================================================================================
*    CONTEXT DIFFERENCES - surrounding code differences between the patches    *
================================================================================

--- b/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -93,4 +93,5 @@
 #define ARM_CPU_PART_CORTEX_X925	0xD85
 #define ARM_CPU_PART_CORTEX_A725	0xD87
+#define ARM_CPU_PART_NEOVERSE_N3	0xD8E
 
 #define APM_CPU_PART_XGENE		0x000
@@ -178,4 +186,5 @@
 #define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925)
 #define MIDR_CORTEX_A725 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A725)
+#define MIDR_NEOVERSE_N3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N3)
 #define MIDR_THUNDERX	MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
 #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)

⚠️ PR commit b21d14dfa9c (arm64: cputype: Add Neoverse-N3 definitions) → upstream 924725707d80
Differences found:

################################################################################
!    REJECTED PATCH2 HUNKS - could not be compared; manual review needed       !
################################################################################

--- b/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -94,6 +94,7 @@
 #define ARM_CPU_PART_NEOVERSE_V3	0xD84
 #define ARM_CPU_PART_CORTEX_X925	0xD85
 #define ARM_CPU_PART_CORTEX_A725	0xD87
+#define ARM_CPU_PART_NEOVERSE_N3	0xD8E
 
 #define APM_CPU_PART_XGENE		0x000
 #define APM_CPU_VAR_POTENZA		0x00
@@ -176,6 +177,7 @@
 #define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3)
 #define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925)
 #define MIDR_CORTEX_A725 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A725)
+#define MIDR_NEOVERSE_N3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N3)
 #define MIDR_THUNDERX	MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
 #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
 #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)

================================================================================
*    CONTEXT DIFFERENCES - surrounding code differences between the patches    *
================================================================================

--- b/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -91,6 +92,5 @@
 #define ARM_CPU_PART_CORTEX_X925	0xD85
 #define ARM_CPU_PART_CORTEX_A725	0xD87
-#define ARM_CPU_PART_CORTEX_A720AE	0xD89
 
 #define APM_CPU_PART_XGENE		0x000
 #define APM_CPU_VAR_POTENZA		0x00
@@ -175,6 +174,5 @@
 #define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925)
 #define MIDR_CORTEX_A725 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A725)
-#define MIDR_CORTEX_A720AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720AE)
 #define MIDR_THUNDERX	MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
 #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
 #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)

⚠️ PR commit dabba7d2c7c (arm64: cputype: Add NVIDIA Olympus definitions) → upstream e185c8a0d842
Differences found:

================================================================================
*    CONTEXT DIFFERENCES - surrounding code differences between the patches    *
================================================================================

--- b/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -204,5 +205,5 @@
 #define MIDR_NVIDIA_DENVER MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_DENVER)
 #define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL)
 #define MIDR_FUJITSU_A64FX MIDR_CPU_MODEL(ARM_CPU_IMP_FUJITSU, FUJITSU_CPU_PART_A64FX)
 #define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110)
-#define MIDR_APPLE_M1_ICESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM)
+#define MIDR_HISI_HIP09 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_HIP09)

❌ PR commit cbb22e5d703 (arm64: errata: Mitigate TLBI errata on NVIDIA Olympus CPU) → ec7216f92e4e
Error: Failed to generate patch for upstream commit: Git command failed: format-patch -1 --stdout ec7216f
fatal: bad object ec7216f
❌ PR commit 03f010f69cf (arm64: errata: Mitigate TLBI errata on Microsoft Azure Cobalt 100 CPU) → 1940e70a8144
Error: Failed to generate patch for upstream commit: Git command failed: format-patch -1 --stdout 1940e70
fatal: bad object 1940e70

This is an automated interdiff check for backported commits.

github-actions · 2026-06-11T00:13:11Z

JIRA PR Check Results

12 commit(s) with issues found:

Commit `03f010f69cfe`

Summary: arm64: errata: Mitigate TLBI errata on Microsoft Azure Cobalt 100 CPU

❌ Errors:

VULN-XXXXXX: Failed to retrieve ticket: JiraError HTTP 404 url: https://ciqinc.atlassian.net/rest/api/2/issue/VULN-XXXXXX
text: Issue does not exist or you do not have permission to see it.

response headers = {'Content-Type': 'application/json;charset=UTF-8', 'Transfer-Encoding': 'chunked', 'Connection': 'keep-alive', 'Date': 'Thu, 11 Jun 2026 00:13:08 GMT', 'Server': 'AtlassianEdge', 'Timing-Allow-Origin': '*', 'X-Arequestid': '7c6c5857e36b03d6b955f77f49a9e7c5', 'X-Aaccountid': '712020%3A43f5a558-0b78-4cc1-ad9e-a61d9b0317de', 'Cache-Control': 'no-cache, no-store, no-transform', 'Ratelimit-Policy': '"jira-burst-based";q=150;w=1', 'Ratelimit': '"jira-burst-based";r=399;t=1', 'X-Ratelimit-Limit': '400', 'X-Ratelimit-Remaining': '399', 'Content-Encoding': 'gzip', 'X-Content-Type-Options': 'nosniff', 'X-Xss-Protection': '1; mode=block', 'Atl-Traceid': 'cafff843fcd143a6863811f3ddd84916', 'Atl-Request-Id': 'cafff843-fcd1-43a6-8638-11f3ddd84916', 'Strict-Transport-Security': 'max-age=63072000; includeSubDomains; preload', 'Report-To': '{"endpoints": [{"url": "https://dz8aopenkvv6s.cloudfront.net"}], "group": "endpoint-1", "include_subdomains": true, "max_age": 600}', 'Nel': '{"failure_fraction": 0.01, "include_subdomains": true, "max_age": 600, "report_to": "endpoint-1"}', 'Server-Timing': 'atl-edge;dur=105,atl-edge-internal;dur=17,atl-edge-upstream;dur=85,atl-edge-pop;desc="aws-us-west-2"', 'X-Cache': 'Error from cloudfront', 'Via': '1.1 440c3e61ef47079d909a882c3cc08ec4.cloudfront.net (CloudFront)', 'X-Amz-Cf-Pop': 'LAX54-P11', 'X-Amz-Cf-Id': '4unP_GjhKKRDSXn3xKzvGxBpeux5dAYGBTvFgrYGPtMf_7KchaXBIw=='}
response text = {"errorMessages":["Issue does not exist or you do not have permission to see it."],"errors":{}}

Commit `cbb22e5d7038`

Summary: arm64: errata: Mitigate TLBI errata on NVIDIA Olympus CPU

❌ Errors:

VULN-XXXXXX: Failed to retrieve ticket: JiraError HTTP 404 url: https://ciqinc.atlassian.net/rest/api/2/issue/VULN-XXXXXX
text: Issue does not exist or you do not have permission to see it.

response headers = {'Content-Type': 'application/json;charset=UTF-8', 'Transfer-Encoding': 'chunked', 'Connection': 'keep-alive', 'Date': 'Thu, 11 Jun 2026 00:13:09 GMT', 'Server': 'AtlassianEdge', 'Timing-Allow-Origin': '*', 'X-Arequestid': '4913a97ac14869c7150f055012d73991', 'X-Aaccountid': '712020%3A43f5a558-0b78-4cc1-ad9e-a61d9b0317de', 'Cache-Control': 'no-cache, no-store, no-transform', 'Ratelimit-Policy': '"jira-burst-based";q=150;w=1', 'Ratelimit': '"jira-burst-based";r=398;t=1', 'X-Ratelimit-Limit': '400', 'X-Ratelimit-Remaining': '398', 'Content-Encoding': 'gzip', 'X-Content-Type-Options': 'nosniff', 'X-Xss-Protection': '1; mode=block', 'Atl-Traceid': '58cbaaf01a9a41b0800d20e109264dea', 'Atl-Request-Id': '58cbaaf0-1a9a-41b0-800d-20e109264dea', 'Strict-Transport-Security': 'max-age=63072000; includeSubDomains; preload', 'Report-To': '{"endpoints": [{"url": "https://dz8aopenkvv6s.cloudfront.net"}], "group": "endpoint-1", "include_subdomains": true, "max_age": 600}', 'Nel': '{"failure_fraction": 0.01, "include_subdomains": true, "max_age": 600, "report_to": "endpoint-1"}', 'Server-Timing': 'atl-edge;dur=63,atl-edge-internal;dur=12,atl-edge-upstream;dur=50,atl-edge-pop;desc="aws-us-west-2"', 'X-Cache': 'Error from cloudfront', 'Via': '1.1 440c3e61ef47079d909a882c3cc08ec4.cloudfront.net (CloudFront)', 'X-Amz-Cf-Pop': 'LAX54-P11', 'X-Amz-Cf-Id': 'ySMxYJGoSzkDmz3nB24Zqj7Opj41Y6r0cuCx6uBmJXi0U1ThWT8NDg=='}
response text = {"errorMessages":["Issue does not exist or you do not have permission to see it."],"errors":{}}

Commit `6f8c66f07d32`

Summary: arm64: errata: Mitigate TLBI errata on various Arm CPUs

❌ Errors:

VULN-XXXXXX: Failed to retrieve ticket: JiraError HTTP 404 url: https://ciqinc.atlassian.net/rest/api/2/issue/VULN-XXXXXX
text: Issue does not exist or you do not have permission to see it.

response headers = {'Content-Type': 'application/json;charset=UTF-8', 'Transfer-Encoding': 'chunked', 'Connection': 'keep-alive', 'Date': 'Thu, 11 Jun 2026 00:13:09 GMT', 'Server': 'AtlassianEdge', 'Timing-Allow-Origin': '*', 'X-Arequestid': '8d3acee13c92a0e62a85823af27c66f2', 'X-Aaccountid': '712020%3A43f5a558-0b78-4cc1-ad9e-a61d9b0317de', 'Cache-Control': 'no-cache, no-store, no-transform', 'Ratelimit-Policy': '"jira-burst-based";q=150;w=1', 'Ratelimit': '"jira-burst-based";r=397;t=1', 'X-Ratelimit-Limit': '400', 'X-Ratelimit-Remaining': '397', 'Content-Encoding': 'gzip', 'X-Content-Type-Options': 'nosniff', 'X-Xss-Protection': '1; mode=block', 'Atl-Traceid': '64f6f64608484c7cb13d5240defa30ee', 'Atl-Request-Id': '64f6f646-0848-4c7c-b13d-5240defa30ee', 'Strict-Transport-Security': 'max-age=63072000; includeSubDomains; preload', 'Report-To': '{"endpoints": [{"url": "https://dz8aopenkvv6s.cloudfront.net"}], "group": "endpoint-1", "include_subdomains": true, "max_age": 600}', 'Nel': '{"failure_fraction": 0.01, "include_subdomains": true, "max_age": 600, "report_to": "endpoint-1"}', 'Server-Timing': 'atl-edge;dur=56,atl-edge-internal;dur=14,atl-edge-upstream;dur=41,atl-edge-pop;desc="aws-us-west-2"', 'X-Cache': 'Error from cloudfront', 'Via': '1.1 440c3e61ef47079d909a882c3cc08ec4.cloudfront.net (CloudFront)', 'X-Amz-Cf-Pop': 'LAX54-P11', 'X-Amz-Cf-Id': 'PAGVw5tXvFqqH7RcSa6yaAl6zyO87g1OkJor-TYdOCnpjVVjnSZlyg=='}
response text = {"errorMessages":["Issue does not exist or you do not have permission to see it."],"errors":{}}

Commit `6a83f0d3e2ae`

Summary: arm64: cputype: Add C1-Premium definitions

❌ Errors:

VULN-XXXXXX: Failed to retrieve ticket: JiraError HTTP 404 url: https://ciqinc.atlassian.net/rest/api/2/issue/VULN-XXXXXX
text: Issue does not exist or you do not have permission to see it.

response headers = {'Content-Type': 'application/json;charset=UTF-8', 'Transfer-Encoding': 'chunked', 'Connection': 'keep-alive', 'Date': 'Thu, 11 Jun 2026 00:13:09 GMT', 'Server': 'AtlassianEdge', 'Timing-Allow-Origin': '*', 'X-Arequestid': '856c819a92aab52ca65a100abdadcccf', 'X-Aaccountid': '712020%3A43f5a558-0b78-4cc1-ad9e-a61d9b0317de', 'Cache-Control': 'no-cache, no-store, no-transform', 'Ratelimit-Policy': '"jira-burst-based";q=150;w=1', 'Ratelimit': '"jira-burst-based";r=396;t=1', 'X-Ratelimit-Limit': '400', 'X-Ratelimit-Remaining': '396', 'Content-Encoding': 'gzip', 'X-Content-Type-Options': 'nosniff', 'X-Xss-Protection': '1; mode=block', 'Atl-Traceid': 'c8e9fc3f91864952be9f1aabced8d349', 'Atl-Request-Id': 'c8e9fc3f-9186-4952-be9f-1aabced8d349', 'Strict-Transport-Security': 'max-age=63072000; includeSubDomains; preload', 'Report-To': '{"endpoints": [{"url": "https://dz8aopenkvv6s.cloudfront.net"}], "group": "endpoint-1", "include_subdomains": true, "max_age": 600}', 'Nel': '{"failure_fraction": 0.01, "include_subdomains": true, "max_age": 600, "report_to": "endpoint-1"}', 'Server-Timing': 'atl-edge;dur=64,atl-edge-internal;dur=14,atl-edge-upstream;dur=50,atl-edge-pop;desc="aws-us-west-2"', 'X-Cache': 'Error from cloudfront', 'Via': '1.1 440c3e61ef47079d909a882c3cc08ec4.cloudfront.net (CloudFront)', 'X-Amz-Cf-Pop': 'LAX54-P11', 'X-Amz-Cf-Id': 'vhOyAMtqAmi9sSvxnAaUGMX6eL6VhTzGK8wlDI8ym_Ix-wyRryWDSQ=='}
response text = {"errorMessages":["Issue does not exist or you do not have permission to see it."],"errors":{}}

Commit `a24fd60bcec7`

Summary: arm64: cputype: Add C1-Ultra definitions

❌ Errors:

VULN-XXXXXX: Failed to retrieve ticket: JiraError HTTP 404 url: https://ciqinc.atlassian.net/rest/api/2/issue/VULN-XXXXXX
text: Issue does not exist or you do not have permission to see it.

response headers = {'Content-Type': 'application/json;charset=UTF-8', 'Transfer-Encoding': 'chunked', 'Connection': 'keep-alive', 'Date': 'Thu, 11 Jun 2026 00:13:09 GMT', 'Server': 'AtlassianEdge', 'Timing-Allow-Origin': '*', 'X-Arequestid': 'adafe5f4e3a86d3238e2ebe5ff499de8', 'X-Aaccountid': '712020%3A43f5a558-0b78-4cc1-ad9e-a61d9b0317de', 'Cache-Control': 'no-cache, no-store, no-transform', 'Ratelimit-Policy': '"jira-burst-based";q=150;w=1', 'Ratelimit': '"jira-burst-based";r=395;t=1', 'X-Ratelimit-Limit': '400', 'X-Ratelimit-Remaining': '395', 'Content-Encoding': 'gzip', 'X-Content-Type-Options': 'nosniff', 'X-Xss-Protection': '1; mode=block', 'Atl-Traceid': 'dd633e6793c744db8c79f94aa43aabce', 'Atl-Request-Id': 'dd633e67-93c7-44db-8c79-f94aa43aabce', 'Strict-Transport-Security': 'max-age=63072000; includeSubDomains; preload', 'Report-To': '{"endpoints": [{"url": "https://dz8aopenkvv6s.cloudfront.net"}], "group": "endpoint-1", "include_subdomains": true, "max_age": 600}', 'Nel': '{"failure_fraction": 0.01, "include_subdomains": true, "max_age": 600, "report_to": "endpoint-1"}', 'Server-Timing': 'atl-edge;dur=52,atl-edge-internal;dur=14,atl-edge-upstream;dur=39,atl-edge-pop;desc="aws-us-west-2"', 'X-Cache': 'Error from cloudfront', 'Via': '1.1 440c3e61ef47079d909a882c3cc08ec4.cloudfront.net (CloudFront)', 'X-Amz-Cf-Pop': 'LAX54-P11', 'X-Amz-Cf-Id': '2RFqGOrDstJKaCqBmVIUciTiqqTp3vxSaFnUqRPxZuu5zF4vgMTsOQ=='}
response text = {"errorMessages":["Issue does not exist or you do not have permission to see it."],"errors":{}}

Commit `dabba7d2c7c0`

Summary: arm64: cputype: Add NVIDIA Olympus definitions

❌ Errors:

VULN-XXXXXX: Failed to retrieve ticket: JiraError HTTP 404 url: https://ciqinc.atlassian.net/rest/api/2/issue/VULN-XXXXXX
text: Issue does not exist or you do not have permission to see it.

response headers = {'Content-Type': 'application/json;charset=UTF-8', 'Transfer-Encoding': 'chunked', 'Connection': 'keep-alive', 'Date': 'Thu, 11 Jun 2026 00:13:09 GMT', 'Server': 'AtlassianEdge', 'Timing-Allow-Origin': '*', 'X-Arequestid': 'a1fd3260a0c4f0985fbc81c249b4acf9', 'X-Aaccountid': '712020%3A43f5a558-0b78-4cc1-ad9e-a61d9b0317de', 'Cache-Control': 'no-cache, no-store, no-transform', 'Ratelimit-Policy': '"jira-burst-based";q=150;w=1', 'Ratelimit': '"jira-burst-based";r=394;t=1', 'X-Ratelimit-Limit': '400', 'X-Ratelimit-Remaining': '394', 'Content-Encoding': 'gzip', 'X-Content-Type-Options': 'nosniff', 'X-Xss-Protection': '1; mode=block', 'Atl-Traceid': '78c6790fe34546a39422475e7bdc3380', 'Atl-Request-Id': '78c6790f-e345-46a3-9422-475e7bdc3380', 'Strict-Transport-Security': 'max-age=63072000; includeSubDomains; preload', 'Report-To': '{"endpoints": [{"url": "https://dz8aopenkvv6s.cloudfront.net"}], "group": "endpoint-1", "include_subdomains": true, "max_age": 600}', 'Nel': '{"failure_fraction": 0.01, "include_subdomains": true, "max_age": 600, "report_to": "endpoint-1"}', 'Server-Timing': 'atl-edge;dur=55,atl-edge-internal;dur=14,atl-edge-upstream;dur=41,atl-edge-pop;desc="aws-us-west-2"', 'X-Cache': 'Error from cloudfront', 'Via': '1.1 440c3e61ef47079d909a882c3cc08ec4.cloudfront.net (CloudFront)', 'X-Amz-Cf-Pop': 'LAX54-P11', 'X-Amz-Cf-Id': 'XL3J5S1c5AB2bZaGWeHF_FmEvajeSQ-Li2bNn5GDYWT49Hv2I0QRww=='}
response text = {"errorMessages":["Issue does not exist or you do not have permission to see it."],"errors":{}}

Commit `3bf06b78835e`

Summary: arm64: cputype: Add C1-Pro definitions

❌ Errors:

VULN-XXXXXX: Failed to retrieve ticket: JiraError HTTP 404 url: https://ciqinc.atlassian.net/rest/api/2/issue/VULN-XXXXXX
text: Issue does not exist or you do not have permission to see it.

response headers = {'Content-Type': 'application/json;charset=UTF-8', 'Transfer-Encoding': 'chunked', 'Connection': 'keep-alive', 'Date': 'Thu, 11 Jun 2026 00:13:09 GMT', 'Server': 'AtlassianEdge', 'Timing-Allow-Origin': '*', 'X-Arequestid': '5284ea1e5771195af597081ac67b0057', 'X-Aaccountid': '712020%3A43f5a558-0b78-4cc1-ad9e-a61d9b0317de', 'Cache-Control': 'no-cache, no-store, no-transform', 'Ratelimit-Policy': '"jira-burst-based";q=150;w=1', 'Ratelimit': '"jira-burst-based";r=399;t=1', 'X-Ratelimit-Limit': '400', 'X-Ratelimit-Remaining': '399', 'Content-Encoding': 'gzip', 'X-Content-Type-Options': 'nosniff', 'X-Xss-Protection': '1; mode=block', 'Atl-Traceid': 'b57e21cbd112448592932e57bdeb8d26', 'Atl-Request-Id': 'b57e21cb-d112-4485-9293-2e57bdeb8d26', 'Strict-Transport-Security': 'max-age=63072000; includeSubDomains; preload', 'Report-To': '{"endpoints": [{"url": "https://dz8aopenkvv6s.cloudfront.net"}], "group": "endpoint-1", "include_subdomains": true, "max_age": 600}', 'Nel': '{"failure_fraction": 0.01, "include_subdomains": true, "max_age": 600, "report_to": "endpoint-1"}', 'Server-Timing': 'atl-edge;dur=87,atl-edge-internal;dur=15,atl-edge-upstream;dur=70,atl-edge-pop;desc="aws-us-west-2"', 'X-Cache': 'Error from cloudfront', 'Via': '1.1 440c3e61ef47079d909a882c3cc08ec4.cloudfront.net (CloudFront)', 'X-Amz-Cf-Pop': 'LAX54-P11', 'X-Amz-Cf-Id': 'uDgZtAFZ_AfwmiQkxDyoQtFP2nqXWNO3AVWiRm5kgfZqIr8ArzyX2w=='}
response text = {"errorMessages":["Issue does not exist or you do not have permission to see it."],"errors":{}}

Commit `bc5518ad561b`

Summary: arm64: cputype: Add Neoverse-V3AE definitions

❌ Errors:

VULN-XXXXXX: Failed to retrieve ticket: JiraError HTTP 404 url: https://ciqinc.atlassian.net/rest/api/2/issue/VULN-XXXXXX
text: Issue does not exist or you do not have permission to see it.

response headers = {'Content-Type': 'application/json;charset=UTF-8', 'Transfer-Encoding': 'chunked', 'Connection': 'keep-alive', 'Date': 'Thu, 11 Jun 2026 00:13:10 GMT', 'Server': 'AtlassianEdge', 'Timing-Allow-Origin': '*', 'X-Arequestid': '210201b854281bab7260279dac7f5c73', 'X-Aaccountid': '712020%3A43f5a558-0b78-4cc1-ad9e-a61d9b0317de', 'Cache-Control': 'no-cache, no-store, no-transform', 'Ratelimit-Policy': '"jira-burst-based";q=150;w=1', 'Ratelimit': '"jira-burst-based";r=398;t=1', 'X-Ratelimit-Limit': '400', 'X-Ratelimit-Remaining': '398', 'Content-Encoding': 'gzip', 'X-Content-Type-Options': 'nosniff', 'X-Xss-Protection': '1; mode=block', 'Atl-Traceid': '5645550bda9f4a7c9fad50f2a5b92db0', 'Atl-Request-Id': '5645550b-da9f-4a7c-9fad-50f2a5b92db0', 'Strict-Transport-Security': 'max-age=63072000; includeSubDomains; preload', 'Report-To': '{"endpoints": [{"url": "https://dz8aopenkvv6s.cloudfront.net"}], "group": "endpoint-1", "include_subdomains": true, "max_age": 600}', 'Nel': '{"failure_fraction": 0.01, "include_subdomains": true, "max_age": 600, "report_to": "endpoint-1"}', 'Server-Timing': 'atl-edge;dur=76,atl-edge-internal;dur=13,atl-edge-upstream;dur=63,atl-edge-pop;desc="aws-us-west-2"', 'X-Cache': 'Error from cloudfront', 'Via': '1.1 440c3e61ef47079d909a882c3cc08ec4.cloudfront.net (CloudFront)', 'X-Amz-Cf-Pop': 'LAX54-P11', 'X-Amz-Cf-Id': 'IPPwXRP5Yo3--cQ71EGLNEt7GXTK4GJhENexcMqE28mVAI8kiMglrA=='}
response text = {"errorMessages":["Issue does not exist or you do not have permission to see it."],"errors":{}}

Commit `b21d14dfa9cc`

Summary: arm64: cputype: Add Neoverse-N3 definitions

❌ Errors:

VULN-XXXXXX: Failed to retrieve ticket: JiraError HTTP 404 url: https://ciqinc.atlassian.net/rest/api/2/issue/VULN-XXXXXX
text: Issue does not exist or you do not have permission to see it.

response headers = {'Content-Type': 'application/json;charset=UTF-8', 'Transfer-Encoding': 'chunked', 'Connection': 'keep-alive', 'Date': 'Thu, 11 Jun 2026 00:13:10 GMT', 'Server': 'AtlassianEdge', 'Timing-Allow-Origin': '*', 'X-Arequestid': '19c35e4c0c9bccbef44a2c6014ae3dfd', 'X-Aaccountid': '712020%3A43f5a558-0b78-4cc1-ad9e-a61d9b0317de', 'Cache-Control': 'no-cache, no-store, no-transform', 'Ratelimit-Policy': '"jira-burst-based";q=150;w=1', 'Ratelimit': '"jira-burst-based";r=397;t=1', 'X-Ratelimit-Limit': '400', 'X-Ratelimit-Remaining': '397', 'Content-Encoding': 'gzip', 'X-Content-Type-Options': 'nosniff', 'X-Xss-Protection': '1; mode=block', 'Atl-Traceid': '7bbe58afc78741619152be288476b176', 'Atl-Request-Id': '7bbe58af-c787-4161-9152-be288476b176', 'Strict-Transport-Security': 'max-age=63072000; includeSubDomains; preload', 'Report-To': '{"endpoints": [{"url": "https://dz8aopenkvv6s.cloudfront.net"}], "group": "endpoint-1", "include_subdomains": true, "max_age": 600}', 'Nel': '{"failure_fraction": 0.01, "include_subdomains": true, "max_age": 600, "report_to": "endpoint-1"}', 'Server-Timing': 'atl-edge;dur=59,atl-edge-internal;dur=14,atl-edge-upstream;dur=45,atl-edge-pop;desc="aws-us-west-2"', 'X-Cache': 'Error from cloudfront', 'Via': '1.1 440c3e61ef47079d909a882c3cc08ec4.cloudfront.net (CloudFront)', 'X-Amz-Cf-Pop': 'LAX54-P11', 'X-Amz-Cf-Id': 'PVsclXXeKCrVvTlwYj5bMS1ChJFAJljW34Xu3YIu13BIr6N-wiAdRQ=='}
response text = {"errorMessages":["Issue does not exist or you do not have permission to see it."],"errors":{}}

Commit `df7f112585e1`

Summary: arm64: cputype: Add Cortex-A720AE definitions

❌ Errors:

VULN-XXXXXX: Failed to retrieve ticket: JiraError HTTP 404 url: https://ciqinc.atlassian.net/rest/api/2/issue/VULN-XXXXXX
text: Issue does not exist or you do not have permission to see it.

response headers = {'Content-Type': 'application/json;charset=UTF-8', 'Transfer-Encoding': 'chunked', 'Connection': 'keep-alive', 'Date': 'Thu, 11 Jun 2026 00:13:10 GMT', 'Server': 'AtlassianEdge', 'Timing-Allow-Origin': '*', 'X-Arequestid': '45561ab11bad5da589fe0d1f59da5dbb', 'X-Aaccountid': '712020%3A43f5a558-0b78-4cc1-ad9e-a61d9b0317de', 'Cache-Control': 'no-cache, no-store, no-transform', 'Ratelimit-Policy': '"jira-burst-based";q=150;w=1', 'Ratelimit': '"jira-burst-based";r=396;t=1', 'X-Ratelimit-Limit': '400', 'X-Ratelimit-Remaining': '396', 'Content-Encoding': 'gzip', 'X-Content-Type-Options': 'nosniff', 'X-Xss-Protection': '1; mode=block', 'Atl-Traceid': '216601fc44844c72aa06f5b58e4e76ac', 'Atl-Request-Id': '216601fc-4484-4c72-aa06-f5b58e4e76ac', 'Strict-Transport-Security': 'max-age=63072000; includeSubDomains; preload', 'Report-To': '{"endpoints": [{"url": "https://dz8aopenkvv6s.cloudfront.net"}], "group": "endpoint-1", "include_subdomains": true, "max_age": 600}', 'Nel': '{"failure_fraction": 0.01, "include_subdomains": true, "max_age": 600, "report_to": "endpoint-1"}', 'Server-Timing': 'atl-edge;dur=54,atl-edge-internal;dur=14,atl-edge-upstream;dur=42,atl-edge-pop;desc="aws-us-west-2"', 'X-Cache': 'Error from cloudfront', 'Via': '1.1 440c3e61ef47079d909a882c3cc08ec4.cloudfront.net (CloudFront)', 'X-Amz-Cf-Pop': 'LAX54-P11', 'X-Amz-Cf-Id': 'VGGyNaZoHPdivSMWHAnuvJeXhE8rDG3Z3HB3NlPkgUKWyfNhq1KHhQ=='}
response text = {"errorMessages":["Issue does not exist or you do not have permission to see it."],"errors":{}}

Commit `27e45d4ebb33`

Summary: arm64: cputype: Add Cortex-A725 definitions

❌ Errors:

VULN-XXXXXX: Failed to retrieve ticket: JiraError HTTP 404 url: https://ciqinc.atlassian.net/rest/api/2/issue/VULN-XXXXXX
text: Issue does not exist or you do not have permission to see it.

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Commit `a26f650679fc`

Summary: arm64: cputype: Add MIDR_CORTEX_A76AE

❌ Errors:

VULN-XXXXXX: Failed to retrieve ticket: JiraError HTTP 404 url: https://ciqinc.atlassian.net/rest/api/2/issue/VULN-XXXXXX
text: Issue does not exist or you do not have permission to see it.

response headers = {'Content-Type': 'application/json;charset=UTF-8', 'Transfer-Encoding': 'chunked', 'Connection': 'keep-alive', 'Date': 'Thu, 11 Jun 2026 00:13:10 GMT', 'Server': 'AtlassianEdge', 'Timing-Allow-Origin': '*', 'X-Arequestid': '1950d2aae45e9c67dca31f67ad8f08cc', 'X-Aaccountid': '712020%3A43f5a558-0b78-4cc1-ad9e-a61d9b0317de', 'Cache-Control': 'no-cache, no-store, no-transform', 'Ratelimit-Policy': '"jira-burst-based";q=150;w=1', 'Ratelimit': '"jira-burst-based";r=394;t=1', 'X-Ratelimit-Limit': '400', 'X-Ratelimit-Remaining': '394', 'Content-Encoding': 'gzip', 'X-Content-Type-Options': 'nosniff', 'X-Xss-Protection': '1; mode=block', 'Atl-Traceid': '845441f0d14842abb960a043065f469e', 'Atl-Request-Id': '845441f0-d148-42ab-b960-a043065f469e', 'Strict-Transport-Security': 'max-age=63072000; includeSubDomains; preload', 'Report-To': '{"endpoints": [{"url": "https://dz8aopenkvv6s.cloudfront.net"}], "group": "endpoint-1", "include_subdomains": true, "max_age": 600}', 'Nel': '{"failure_fraction": 0.01, "include_subdomains": true, "max_age": 600, "report_to": "endpoint-1"}', 'Server-Timing': 'atl-edge;dur=73,atl-edge-internal;dur=13,atl-edge-upstream;dur=59,atl-edge-pop;desc="aws-us-west-2"', 'X-Cache': 'Error from cloudfront', 'Via': '1.1 440c3e61ef47079d909a882c3cc08ec4.cloudfront.net (CloudFront)', 'X-Amz-Cf-Pop': 'LAX54-P11', 'X-Amz-Cf-Id': 'qY31dcbm1kJm5qGSLFQqbxO9qX629TPccGJKYMOR4tc9_VsqHDz3jQ=='}
response text = {"errorMessages":["Issue does not exist or you do not have permission to see it."],"errors":{}}

Summary: Checked 12 commit(s) total.

github-actions · 2026-06-11T00:13:12Z

❌ Validation checks completed with issues View full results: https://github.com/ctrliq/kernel-src-tree/actions/runs/27314772468

github-actions · 2026-06-11T07:49:13Z

🤖 Validation Checks In Progress Workflow run: https://github.com/ctrliq/kernel-src-tree/actions/runs/27332082530

github-actions · 2026-06-11T07:49:14Z

🔍 Upstream Linux Kernel Commit Check

❗ PR commit a6d0134f963 (arm64: errata: Mitigate TLBI errata on NVIDIA Olympus CPU) references upstream commit
ec7216f92e4e which does not exist in the upstream Linux kernel.
❗ PR commit 12ca48aef78 (arm64: errata: Mitigate TLBI errata on Microsoft Azure Cobalt 100 CPU) references upstream commit
1940e70a8144 which does not exist in the upstream Linux kernel.

This is an automated message from the kernel commit checker workflow.

github-actions · 2026-06-11T07:49:14Z

🔍 Interdiff Analysis

⚠️ PR commit c233982c7da (arm64: cputype: Add Cortex-A720AE definitions) → upstream f38c2c3e572c
Differences found:

################################################################################
!    REJECTED PATCH2 HUNKS - could not be compared; manual review needed       !
################################################################################

--- b/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -96,6 +96,7 @@
 #define ARM_CPU_PART_NEOVERSE_V3	0xD84
 #define ARM_CPU_PART_CORTEX_X925	0xD85
 #define ARM_CPU_PART_CORTEX_A725	0xD87
+#define ARM_CPU_PART_CORTEX_A720AE	0xD89
 #define ARM_CPU_PART_NEOVERSE_N3	0xD8E
 
 #define APM_CPU_PART_XGENE		0x000
@@ -185,6 +186,7 @@
 #define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3)
 #define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925)
 #define MIDR_CORTEX_A725 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A725)
+#define MIDR_CORTEX_A720AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720AE)
 #define MIDR_NEOVERSE_N3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N3)
 #define MIDR_THUNDERX	MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
 #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)

================================================================================
*    CONTEXT DIFFERENCES - surrounding code differences between the patches    *
================================================================================

--- b/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -93,4 +93,5 @@
 #define ARM_CPU_PART_CORTEX_X925	0xD85
 #define ARM_CPU_PART_CORTEX_A725	0xD87
+#define ARM_CPU_PART_NEOVERSE_N3	0xD8E
 
 #define APM_CPU_PART_XGENE		0x000
@@ -178,4 +186,5 @@
 #define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925)
 #define MIDR_CORTEX_A725 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A725)
+#define MIDR_NEOVERSE_N3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N3)
 #define MIDR_THUNDERX	MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
 #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)

⚠️ PR commit bf9fba09d1b (arm64: cputype: Add Neoverse-N3 definitions) → upstream 924725707d80
Differences found:

################################################################################
!    REJECTED PATCH2 HUNKS - could not be compared; manual review needed       !
################################################################################

--- b/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -94,6 +94,7 @@
 #define ARM_CPU_PART_NEOVERSE_V3	0xD84
 #define ARM_CPU_PART_CORTEX_X925	0xD85
 #define ARM_CPU_PART_CORTEX_A725	0xD87
+#define ARM_CPU_PART_NEOVERSE_N3	0xD8E
 
 #define APM_CPU_PART_XGENE		0x000
 #define APM_CPU_VAR_POTENZA		0x00
@@ -176,6 +177,7 @@
 #define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3)
 #define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925)
 #define MIDR_CORTEX_A725 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A725)
+#define MIDR_NEOVERSE_N3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N3)
 #define MIDR_THUNDERX	MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
 #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
 #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)

================================================================================
*    CONTEXT DIFFERENCES - surrounding code differences between the patches    *
================================================================================

--- b/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -91,6 +92,5 @@
 #define ARM_CPU_PART_CORTEX_X925	0xD85
 #define ARM_CPU_PART_CORTEX_A725	0xD87
-#define ARM_CPU_PART_CORTEX_A720AE	0xD89
 
 #define APM_CPU_PART_XGENE		0x000
 #define APM_CPU_VAR_POTENZA		0x00
@@ -175,6 +174,5 @@
 #define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925)
 #define MIDR_CORTEX_A725 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A725)
-#define MIDR_CORTEX_A720AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720AE)
 #define MIDR_THUNDERX	MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
 #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
 #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)

⚠️ PR commit 6464a30eee9 (arm64: cputype: Add NVIDIA Olympus definitions) → upstream e185c8a0d842
Differences found:

================================================================================
*    CONTEXT DIFFERENCES - surrounding code differences between the patches    *
================================================================================

--- b/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -204,5 +205,5 @@
 #define MIDR_NVIDIA_DENVER MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_DENVER)
 #define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL)
 #define MIDR_FUJITSU_A64FX MIDR_CPU_MODEL(ARM_CPU_IMP_FUJITSU, FUJITSU_CPU_PART_A64FX)
 #define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110)
-#define MIDR_APPLE_M1_ICESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM)
+#define MIDR_HISI_HIP09 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_HIP09)

❌ PR commit a6d0134f963 (arm64: errata: Mitigate TLBI errata on NVIDIA Olympus CPU) → ec7216f92e4e
Error: Failed to generate patch for upstream commit: Git command failed: format-patch -1 --stdout ec7216f
fatal: bad object ec7216f
❌ PR commit 12ca48aef78 (arm64: errata: Mitigate TLBI errata on Microsoft Azure Cobalt 100 CPU) → 1940e70a8144
Error: Failed to generate patch for upstream commit: Git command failed: format-patch -1 --stdout 1940e70
fatal: bad object 1940e70

This is an automated interdiff check for backported commits.

github-actions · 2026-06-11T07:50:50Z

JIRA PR Check Results

12 commit(s) with issues found:

Commit `12ca48aef783`

Summary: arm64: errata: Mitigate TLBI errata on Microsoft Azure Cobalt 100 CPU

❌ Errors:

VULN-187523: Status is 'To Do', expected 'In Progress'

⚠️ Warnings:

VULN-187523: No time logged - please log time manually

Commit `a6d0134f9630`

Summary: arm64: errata: Mitigate TLBI errata on NVIDIA Olympus CPU

❌ Errors:

VULN-187523: Status is 'To Do', expected 'In Progress'

⚠️ Warnings:

VULN-187523: No time logged - please log time manually

Commit `285efd53085a`

Summary: arm64: errata: Mitigate TLBI errata on various Arm CPUs

❌ Errors:

VULN-187523: Status is 'To Do', expected 'In Progress'

⚠️ Warnings:

VULN-187523: No time logged - please log time manually

Commit `e5bfae73f2d0`

Summary: arm64: cputype: Add C1-Premium definitions

❌ Errors:

VULN-187523: Status is 'To Do', expected 'In Progress'

⚠️ Warnings:

VULN-187523: No time logged - please log time manually

Commit `52b79c177428`

Summary: arm64: cputype: Add C1-Ultra definitions

❌ Errors:

VULN-187523: Status is 'To Do', expected 'In Progress'

⚠️ Warnings:

VULN-187523: No time logged - please log time manually

Commit `6464a30eee90`

Summary: arm64: cputype: Add NVIDIA Olympus definitions

❌ Errors:

VULN-187523: Status is 'To Do', expected 'In Progress'

⚠️ Warnings:

VULN-187523: No time logged - please log time manually

Commit `c7d2c819dcad`

Summary: arm64: cputype: Add C1-Pro definitions

❌ Errors:

VULN-187523: Status is 'To Do', expected 'In Progress'

⚠️ Warnings:

VULN-187523: No time logged - please log time manually

Commit `b085f2979626`

Summary: arm64: cputype: Add Neoverse-V3AE definitions

❌ Errors:

VULN-187523: Status is 'To Do', expected 'In Progress'

⚠️ Warnings:

VULN-187523: No time logged - please log time manually

Commit `bf9fba09d1b8`

Summary: arm64: cputype: Add Neoverse-N3 definitions

❌ Errors:

VULN-187523: Status is 'To Do', expected 'In Progress'

⚠️ Warnings:

VULN-187523: No time logged - please log time manually

Commit `c233982c7da7`

Summary: arm64: cputype: Add Cortex-A720AE definitions

❌ Errors:

VULN-187523: Status is 'To Do', expected 'In Progress'

⚠️ Warnings:

VULN-187523: No time logged - please log time manually

Commit `70cc196a9f93`

Summary: arm64: cputype: Add Cortex-A725 definitions

❌ Errors:

VULN-187523: Status is 'To Do', expected 'In Progress'

⚠️ Warnings:

VULN-187523: No time logged - please log time manually

Commit `9476983ead71`

Summary: arm64: cputype: Add MIDR_CORTEX_A76AE

❌ Errors:

VULN-187523: Status is 'To Do', expected 'In Progress'

⚠️ Warnings:

VULN-187523: No time logged - please log time manually

Summary: Checked 12 commit(s) total.

github-actions · 2026-06-11T07:50:51Z

❌ Validation checks completed with issues View full results: https://github.com/ctrliq/kernel-src-tree/actions/runs/27332082530

jira VULN-187523 cve-pre CVE-2025-10263 commit-author Douglas Anderson <dianders@chromium.org> commit a9b5bd8 >From the TRM, MIDR_CORTEX_A76AE has a partnum of 0xDOE and an implementor of 0x41 (ARM). Add the values. Cc: stable@vger.kernel.org # dependency of the next fix in the series Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20250107120555.v4.4.I151f3b7ee323bcc3082179b8c60c3cd03308aa94@changeid Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit a9b5bd8) Signed-off-by: Brett Mastbergen <bmastbergen@ciq.com>

jira VULN-187523 cve-pre CVE-2025-10263 commit-author Mark Rutland <mark.rutland@arm.com> commit 9ef54a3 Add cputype definitions for Cortex-A725. These will be used for errata detection in subsequent patches. These values can be found in the Cortex-A725 TRM: https://developer.arm.com/documentation/107652/0001/ ... in table A-247 ("MIDR_EL1 bit descriptions"). Signed-off-by: Mark Rutland <mark.rutland@arm.com> Cc: James Morse <james.morse@arm.com> Cc: Will Deacon <will@kernel.org> Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com> Link: https://lore.kernel.org/r/20240801101803.1982459-3-mark.rutland@arm.com Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit 9ef54a3) Signed-off-by: Brett Mastbergen <bmastbergen@ciq.com>

jira VULN-187523 cve-pre CVE-2025-10263 commit-author Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> commit f38c2c3 Add cputype definitions for Cortex-A720AE. These will be used for errata detection in subsequent patches. These values can be found in the Cortex-A720AE TRM: https://developer.arm.com/documentation/102828/0001/ ... in Table A-187 Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Will Deacon <will@kernel.org> (cherry picked from commit f38c2c3) Signed-off-by: Brett Mastbergen <bmastbergen@ciq.com>

jira VULN-187523 cve-pre CVE-2025-10263 commit-author Mark Rutland <mark.rutland@arm.com> commit 9247257 Add cputype definitions for Neoverse-N3. These will be used for errata detection in subsequent patches. These values can be found in Table A-261 ("MIDR_EL1 bit descriptions") in issue 02 of the Neoverse-N3 TRM, which can be found at: https://developer.arm.com/documentation/107997/0000/?lang=en Signed-off-by: Mark Rutland <mark.rutland@arm.com> Cc: James Morse <james.morse@arm.com> Cc: Will Deacon <will@kernel.org> Link: https://lore.kernel.org/r/20240930111705.3352047-2-mark.rutland@arm.com Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit 9247257) Signed-off-by: Brett Mastbergen <bmastbergen@ciq.com>

jira VULN-187523 cve-pre CVE-2025-10263 commit-author Mark Rutland <mark.rutland@arm.com> commit 3bbf004 Add cputype definitions for Neoverse-V3AE. These will be used for errata detection in subsequent patches. These values can be found in the Neoverse-V3AE TRM: https://developer.arm.com/documentation/SDEN-2615521/9-0/ ... in section A.6.1 ("MIDR_EL1, Main ID Register"). Signed-off-by: Mark Rutland <mark.rutland@arm.com> Cc: James Morse <james.morse@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Ryan Roberts <ryan.roberts@arm.com> Signed-off-by: Will Deacon <will@kernel.org> (cherry picked from commit 3bbf004) Signed-off-by: Brett Mastbergen <bmastbergen@ciq.com>

jira VULN-187523 cve-pre CVE-2025-10263 commit-author Catalin Marinas <catalin.marinas@arm.com> commit 2c99561 Add cputype definitions for C1-Pro. These will be used for errata detection in subsequent patches. These values can be found in "Table A-303: MIDR_EL1 bit descriptions" in issue 07 of the C1-Pro TRM: https://documentation-service.arm.com/static/6930126730f8f55a656570af Acked-by: Mark Rutland <mark.rutland@arm.com> Cc: Will Deacon <will@kernel.org> Cc: James Morse <james.morse@arm.com> Reviewed-by: Will Deacon <will@kernel.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit 2c99561) Signed-off-by: Brett Mastbergen <bmastbergen@ciq.com>

jira VULN-187523 cve-pre CVE-2025-10263 commit-author Shanker Donthineni <sdonthineni@nvidia.com> commit e185c8a Add cpu part and model macro definitions for NVIDIA Olympus core. Signed-off-by: Shanker Donthineni <sdonthineni@nvidia.com> Signed-off-by: Will Deacon <will@kernel.org> (cherry picked from commit e185c8a) Signed-off-by: Brett Mastbergen <bmastbergen@ciq.com>

roxanan1996 · 2026-06-11T10:12:06Z

I had to update all commit message bodies as they were not consistent with mainline/arm64.
And modified to the last 5 commits to reflect they were cherry picks from the arm64 subtree.

The actual code has not changed.

jira VULN-187523 cve-pre CVE-2025-10263 commit-author Mark Rutland <mark.rutland@arm.com> commit - commit-source-sha 60349e6 commit-source arm64 Add cputype definitions for C1-Ultra. These will be used for errata detection in subsequent patches. These values can be found in the C1-Ultra TRM: https://developer.arm.com/documentation/108014/0100/ ... in section A.5.1 ("MIDR_EL1, Main ID Register"). Signed-off-by: Mark Rutland <mark.rutland@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Signed-off-by: Will Deacon <will@kernel.org> (cherry picked from commit 60349e6) Signed-off-by: Brett Mastbergen <bmastbergen@ciq.com>

jira VULN-187523 cve-pre CVE-2025-10263 commit-author Mark Rutland <mark.rutland@arm.com> commit - commit-source-sha d28413b commit-source arm64 Add cputype definitions for C1-Premium. These will be used for errata detection in subsequent patches. These values can be found in the C1-Premium TRM: https://developer.arm.com/documentation/109416/0100/ ... in section A.5.1 ("MIDR_EL1, Main ID Register"). Signed-off-by: Mark Rutland <mark.rutland@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Signed-off-by: Will Deacon <will@kernel.org> (cherry picked from commit d28413b) Signed-off-by: Brett Mastbergen <bmastbergen@ciq.com>

jira VULN-187523 cve CVE-2025-10263 commit-author Mark Rutland <mark.rutland@arm.com> commit - commit-source-sha cfd391e commit-source arm64 upstream-diff silicon-errata.rst at different path (Documentation/arm64/ vs Documentation/arch/arm64/) and required manual conflict resolution due to condensed table formatting and missing entries in our branch. Content is identical. A number of CPUs developed by Arm suffer from errata whereby a broadcast TLBI;DSB sequence may complete before the global observation of writes which are translated by an affected TLB entry. These errata ONLY affect the completion of memory accesses which have been translated by an invalidated TLB entry, and these errata DO NOT affect the actual invalidation of TLB entries. TLB entries are removed correctly. This issue has been assigned CVE ID CVE-2025-10263. To mitigate this issue, Arm recommends that software follows any affected TLBI;DSB sequence with an additional TLBI;DSB, which will ensure that all memory write effects affected by the first TLBI have been globally observed. The additional TLBI can use any operation that is broadcast to affected CPUs, and the additional DSB can use any option that is sufficient to complete the additional TLBI. The ARM64_WORKAROUND_REPEAT_TLBI workaround is sufficient to mitigate the issue. Enable this workaround for affected CPUs, and update the silicon errata documentation accordingly. Note that due to the manner in which Arm develops IP and tracks errata, some CPUs share a common erratum number. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Signed-off-by: Will Deacon <will@kernel.org> (cherry picked from commit cfd391e) Signed-off-by: Brett Mastbergen <bmastbergen@ciq.com>

jira VULN-187523 cve CVE-2025-10263 commit-author Shanker Donthineni <sdonthineni@nvidia.com> commit - commit-source-sha ec7216f commit-source arm64 NVIDIA Olympus cores are affected by the TLBI completion issue tracked as CVE-2025-10263. The existing ARM64_ERRATUM_4118414 handling already uses ARM64_WORKAROUND_REPEAT_TLBI to issue an additional broadcast TLBI;DSB sequence and ensure affected memory write effects are globally observed. Add MIDR_NVIDIA_OLYMPUS to the repeat-TLBI match list so the same mitigation is enabled on affected Olympus systems. Also document the NVIDIA Olympus erratum in the arm64 silicon errata table and list it in the Kconfig help text. Signed-off-by: Shanker Donthineni <sdonthineni@nvidia.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Will Deacon <will@kernel.org> (cherry picked from commit ec7216f) Signed-off-by: Brett Mastbergen <bmastbergen@ciq.com>

jira VULN-187523 cve CVE-2025-10263 commit-author Will Deacon <will@kernel.org> commit - commit-source-sha 1940e70 commit-source arm64 Commit fb091ff ("arm64: Subscribe Microsoft Azure Cobalt 100 to ARM Neoverse N2 errata") states that Microsoft Azure Cobalt 100 CPU "is a Microsoft implemented CPU based on r0p0 of the ARM Neoverse N2 CPU, and therefore suffers from all the same errata.". So enable the workaround for the latest broadcast TLB invalidation bug on these parts. Signed-off-by: Will Deacon <will@kernel.org> (cherry picked from commit 1940e70) Signed-off-by: Brett Mastbergen <bmastbergen@ciq.com>

github-actions · 2026-06-11T10:22:55Z

🤖 Validation Checks In Progress Workflow run: https://github.com/ctrliq/kernel-src-tree/actions/runs/27340266027

github-actions · 2026-06-11T10:22:56Z

🔍 Interdiff Analysis

⚠️ PR commit 8bbe36352c4 (arm64: cputype: Add Cortex-A720AE definitions) → upstream f38c2c3e572c
Differences found:

################################################################################
!    REJECTED PATCH2 HUNKS - could not be compared; manual review needed       !
################################################################################

--- b/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -96,6 +96,7 @@
 #define ARM_CPU_PART_NEOVERSE_V3	0xD84
 #define ARM_CPU_PART_CORTEX_X925	0xD85
 #define ARM_CPU_PART_CORTEX_A725	0xD87
+#define ARM_CPU_PART_CORTEX_A720AE	0xD89
 #define ARM_CPU_PART_NEOVERSE_N3	0xD8E
 
 #define APM_CPU_PART_XGENE		0x000
@@ -185,6 +186,7 @@
 #define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3)
 #define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925)
 #define MIDR_CORTEX_A725 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A725)
+#define MIDR_CORTEX_A720AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720AE)
 #define MIDR_NEOVERSE_N3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N3)
 #define MIDR_THUNDERX	MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
 #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)

================================================================================
*    CONTEXT DIFFERENCES - surrounding code differences between the patches    *
================================================================================

--- b/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -93,4 +93,5 @@
 #define ARM_CPU_PART_CORTEX_X925	0xD85
 #define ARM_CPU_PART_CORTEX_A725	0xD87
+#define ARM_CPU_PART_NEOVERSE_N3	0xD8E
 
 #define APM_CPU_PART_XGENE		0x000
@@ -178,4 +186,5 @@
 #define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925)
 #define MIDR_CORTEX_A725 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A725)
+#define MIDR_NEOVERSE_N3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N3)
 #define MIDR_THUNDERX	MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
 #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)

⚠️ PR commit ac0febdadf6 (arm64: cputype: Add Neoverse-N3 definitions) → upstream 924725707d80
Differences found:

################################################################################
!    REJECTED PATCH2 HUNKS - could not be compared; manual review needed       !
################################################################################

--- b/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -94,6 +94,7 @@
 #define ARM_CPU_PART_NEOVERSE_V3	0xD84
 #define ARM_CPU_PART_CORTEX_X925	0xD85
 #define ARM_CPU_PART_CORTEX_A725	0xD87
+#define ARM_CPU_PART_NEOVERSE_N3	0xD8E
 
 #define APM_CPU_PART_XGENE		0x000
 #define APM_CPU_VAR_POTENZA		0x00
@@ -176,6 +177,7 @@
 #define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3)
 #define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925)
 #define MIDR_CORTEX_A725 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A725)
+#define MIDR_NEOVERSE_N3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N3)
 #define MIDR_THUNDERX	MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
 #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
 #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)

================================================================================
*    CONTEXT DIFFERENCES - surrounding code differences between the patches    *
================================================================================

--- b/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -91,6 +92,5 @@
 #define ARM_CPU_PART_CORTEX_X925	0xD85
 #define ARM_CPU_PART_CORTEX_A725	0xD87
-#define ARM_CPU_PART_CORTEX_A720AE	0xD89
 
 #define APM_CPU_PART_XGENE		0x000
 #define APM_CPU_VAR_POTENZA		0x00
@@ -175,6 +174,5 @@
 #define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925)
 #define MIDR_CORTEX_A725 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A725)
-#define MIDR_CORTEX_A720AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720AE)
 #define MIDR_THUNDERX	MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
 #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
 #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)

⚠️ PR commit a8276ce9198 (arm64: cputype: Add NVIDIA Olympus definitions) → upstream e185c8a0d842
Differences found:

================================================================================
*    CONTEXT DIFFERENCES - surrounding code differences between the patches    *
================================================================================

--- b/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -204,5 +205,5 @@
 #define MIDR_NVIDIA_DENVER MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_DENVER)
 #define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL)
 #define MIDR_FUJITSU_A64FX MIDR_CPU_MODEL(ARM_CPU_IMP_FUJITSU, FUJITSU_CPU_PART_A64FX)
 #define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110)
-#define MIDR_APPLE_M1_ICESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM)
+#define MIDR_HISI_HIP09 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_HIP09)

This is an automated interdiff check for backported commits.

github-actions · 2026-06-11T10:24:35Z

JIRA PR Check Results

12 commit(s) with issues found:

Commit `96e893d2dfa7`

Summary: arm64: errata: Mitigate TLBI errata on Microsoft Azure Cobalt 100 CPU

⚠️ Warnings:

VULN-187523: No time logged - please log time manually

Commit `ded68e326d61`

Summary: arm64: errata: Mitigate TLBI errata on NVIDIA Olympus CPU

⚠️ Warnings:

VULN-187523: No time logged - please log time manually

Commit `3549cc968a09`

Summary: arm64: errata: Mitigate TLBI errata on various Arm CPUs

⚠️ Warnings:

VULN-187523: No time logged - please log time manually

Commit `b5cd69c5f99e`

Summary: arm64: cputype: Add C1-Premium definitions

⚠️ Warnings:

VULN-187523: No time logged - please log time manually

Commit `47c6b403cba2`

Summary: arm64: cputype: Add C1-Ultra definitions

⚠️ Warnings:

VULN-187523: No time logged - please log time manually

Commit `a8276ce91983`

Summary: arm64: cputype: Add NVIDIA Olympus definitions

⚠️ Warnings:

VULN-187523: No time logged - please log time manually

Commit `c0bd7cc8a4c4`

Summary: arm64: cputype: Add C1-Pro definitions

⚠️ Warnings:

VULN-187523: No time logged - please log time manually

Commit `8b07d0fcd8bd`

Summary: arm64: cputype: Add Neoverse-V3AE definitions

⚠️ Warnings:

VULN-187523: No time logged - please log time manually

Commit `ac0febdadf6c`

Summary: arm64: cputype: Add Neoverse-N3 definitions

⚠️ Warnings:

VULN-187523: No time logged - please log time manually

Commit `8bbe36352c4c`

Summary: arm64: cputype: Add Cortex-A720AE definitions

⚠️ Warnings:

VULN-187523: No time logged - please log time manually

Commit `5b0e77ac9be2`

Summary: arm64: cputype: Add Cortex-A725 definitions

⚠️ Warnings:

VULN-187523: No time logged - please log time manually

Commit `e1199ec742e2`

Summary: arm64: cputype: Add MIDR_CORTEX_A76AE

⚠️ Warnings:

VULN-187523: No time logged - please log time manually

Summary: Checked 12 commit(s) total.

github-actions · 2026-06-11T10:24:36Z

✅ Validation checks completed successfully View full results: https://github.com/ctrliq/kernel-src-tree/actions/runs/27340266027

github-actions · 2026-06-11T11:58:35Z

🤖 Validation Checks In Progress Workflow run: https://github.com/ctrliq/kernel-src-tree/actions/runs/27345132475

github-actions · 2026-06-11T11:58:36Z

🔍 Interdiff Analysis

⚠️ PR commit 8bbe36352c4 (arm64: cputype: Add Cortex-A720AE definitions) → upstream f38c2c3e572c
Differences found:

################################################################################
!    REJECTED PATCH2 HUNKS - could not be compared; manual review needed       !
################################################################################

--- b/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -96,6 +96,7 @@
 #define ARM_CPU_PART_NEOVERSE_V3	0xD84
 #define ARM_CPU_PART_CORTEX_X925	0xD85
 #define ARM_CPU_PART_CORTEX_A725	0xD87
+#define ARM_CPU_PART_CORTEX_A720AE	0xD89
 #define ARM_CPU_PART_NEOVERSE_N3	0xD8E
 
 #define APM_CPU_PART_XGENE		0x000
@@ -185,6 +186,7 @@
 #define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3)
 #define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925)
 #define MIDR_CORTEX_A725 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A725)
+#define MIDR_CORTEX_A720AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720AE)
 #define MIDR_NEOVERSE_N3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N3)
 #define MIDR_THUNDERX	MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
 #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)

================================================================================
*    CONTEXT DIFFERENCES - surrounding code differences between the patches    *
================================================================================

--- b/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -93,4 +93,5 @@
 #define ARM_CPU_PART_CORTEX_X925	0xD85
 #define ARM_CPU_PART_CORTEX_A725	0xD87
+#define ARM_CPU_PART_NEOVERSE_N3	0xD8E
 
 #define APM_CPU_PART_XGENE		0x000
@@ -178,4 +186,5 @@
 #define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925)
 #define MIDR_CORTEX_A725 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A725)
+#define MIDR_NEOVERSE_N3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N3)
 #define MIDR_THUNDERX	MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
 #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)

⚠️ PR commit ac0febdadf6 (arm64: cputype: Add Neoverse-N3 definitions) → upstream 924725707d80
Differences found:

################################################################################
!    REJECTED PATCH2 HUNKS - could not be compared; manual review needed       !
################################################################################

--- b/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -94,6 +94,7 @@
 #define ARM_CPU_PART_NEOVERSE_V3	0xD84
 #define ARM_CPU_PART_CORTEX_X925	0xD85
 #define ARM_CPU_PART_CORTEX_A725	0xD87
+#define ARM_CPU_PART_NEOVERSE_N3	0xD8E
 
 #define APM_CPU_PART_XGENE		0x000
 #define APM_CPU_VAR_POTENZA		0x00
@@ -176,6 +177,7 @@
 #define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3)
 #define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925)
 #define MIDR_CORTEX_A725 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A725)
+#define MIDR_NEOVERSE_N3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N3)
 #define MIDR_THUNDERX	MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
 #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
 #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)

================================================================================
*    CONTEXT DIFFERENCES - surrounding code differences between the patches    *
================================================================================

--- b/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -91,6 +92,5 @@
 #define ARM_CPU_PART_CORTEX_X925	0xD85
 #define ARM_CPU_PART_CORTEX_A725	0xD87
-#define ARM_CPU_PART_CORTEX_A720AE	0xD89
 
 #define APM_CPU_PART_XGENE		0x000
 #define APM_CPU_VAR_POTENZA		0x00
@@ -175,6 +174,5 @@
 #define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925)
 #define MIDR_CORTEX_A725 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A725)
-#define MIDR_CORTEX_A720AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720AE)
 #define MIDR_THUNDERX	MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
 #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
 #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)

⚠️ PR commit a8276ce9198 (arm64: cputype: Add NVIDIA Olympus definitions) → upstream e185c8a0d842
Differences found:

================================================================================
*    CONTEXT DIFFERENCES - surrounding code differences between the patches    *
================================================================================

--- b/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -204,5 +205,5 @@
 #define MIDR_NVIDIA_DENVER MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_DENVER)
 #define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL)
 #define MIDR_FUJITSU_A64FX MIDR_CPU_MODEL(ARM_CPU_IMP_FUJITSU, FUJITSU_CPU_PART_A64FX)
 #define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110)
-#define MIDR_APPLE_M1_ICESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM)
+#define MIDR_HISI_HIP09 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_HIP09)

This is an automated interdiff check for backported commits.

github-actions · 2026-06-11T12:00:38Z

JIRA PR Check Results

93 commit(s) with issues found:

Commit `15e4e4e3e566`

Summary: arm64: errata: Mitigate TLBI errata on Microsoft Azure Cobalt 100 CPU

⚠️ Warnings:

VULN-187523: No time logged - please log time manually

Commit `e37bbda6a481`

Summary: arm64: errata: Mitigate TLBI errata on NVIDIA Olympus CPU

⚠️ Warnings:

VULN-187523: No time logged - please log time manually

Commit `85119bd5bb8d`

Summary: arm64: errata: Mitigate TLBI errata on various Arm CPUs

⚠️ Warnings:

VULN-187523: No time logged - please log time manually

Commit `b2711ee22a8e`

Summary: arm64: cputype: Add C1-Premium definitions

⚠️ Warnings:

VULN-187523: No time logged - please log time manually

Commit `3ed89eeaaa9c`

Summary: arm64: cputype: Add C1-Ultra definitions

⚠️ Warnings:

VULN-187523: No time logged - please log time manually

Commit `a8276ce91983`

Summary: arm64: cputype: Add NVIDIA Olympus definitions

⚠️ Warnings:

VULN-187523: No time logged - please log time manually

Commit `c0bd7cc8a4c4`

Summary: arm64: cputype: Add C1-Pro definitions

⚠️ Warnings:

VULN-187523: No time logged - please log time manually

Commit `8b07d0fcd8bd`

Summary: arm64: cputype: Add Neoverse-V3AE definitions

⚠️ Warnings:

VULN-187523: No time logged - please log time manually

Commit `ac0febdadf6c`

Summary: arm64: cputype: Add Neoverse-N3 definitions

⚠️ Warnings:

VULN-187523: No time logged - please log time manually

Commit `8bbe36352c4c`

Summary: arm64: cputype: Add Cortex-A720AE definitions

⚠️ Warnings:

VULN-187523: No time logged - please log time manually

Commit `5b0e77ac9be2`

Summary: arm64: cputype: Add Cortex-A725 definitions

⚠️ Warnings:

VULN-187523: No time logged - please log time manually

Commit `e1199ec742e2`

Summary: arm64: cputype: Add MIDR_CORTEX_A76AE

⚠️ Warnings:

VULN-187523: No time logged - please log time manually

Commit `f0663d715980`

Summary: netfilter: ip6t_eui64: reject invalid MAC header for all packets

❌ Errors:

VULN-183038: Status is 'Publish CSAF', expected 'In Progress'

Commit `794f919c95ad`

Summary: usbip: validate number_of_packets in usbip_pack_ret_submit()

❌ Errors:

VULN-183086: Status is 'Publish CSAF', expected 'In Progress'

Commit `9484ae8cff1b`

Summary: KVM: arm64: Reassign nested_mmus array behind mmu_lock

❌ Errors:

VULN-187401: Status is 'Publish CSAF', expected 'In Progress'

Commit `59eb886d4b84`

Summary: KVM: arm64: Fix nested S2 MMU structures reallocation

❌ Errors:

VULN-187401: Status is 'Publish CSAF', expected 'In Progress'

Commit `ea987423ccd5`

Summary: KVM: arm64: vgic-its: Drop the translation cache reference only for the erased entry

❌ Errors:

VULN-187400: Status is 'Publish CSAF', expected 'In Progress'

Commit `62ae594cabee`

Summary: ip6_tunnel: clear skb2->cb[] in ip4ip6_err()

❌ Errors:

VULN-183733: Status is 'Publish CSAF', expected 'In Progress'

Commit `5991eddcf3dd`

Summary: ipv6: icmp: clear skb2->cb[] in ip6_err_gen_icmpv6_unreach()

❌ Errors:

VULN-183739: Status is 'Publish CSAF', expected 'In Progress'

Commit `08cba4c1ff08`

Summary: netfilter: nf_tables: release flowtable after rcu grace period on error

❌ Errors:

VULN-179375: Status is 'Publish CSAF', expected 'In Progress'

Commit `a2fb277fdbeb`

Summary: net/sched: Only allow act_ct to bind to clsact/ingress qdiscs and shared blocks

❌ Errors:

VULN-178618: Status is 'Publish CSAF', expected 'In Progress'

Commit `7b94d511b7c6`

Summary: md/bitmap: fix GPF in write_page caused by resize race

❌ Errors:

VULN-184502: Status is 'Publish CSAF', expected 'In Progress'

Commit `cecc05702f05`

Summary: nbd: defer config unlock in nbd_genl_connect

❌ Errors:

VULN-171936: Status is 'Publish CSAF', expected 'In Progress'

Commit `900e91192ae4`

Summary: net/sched: sch_cake: Fix incorrect qlen reduction in cake_drop

❌ Errors:

VULN-187235: Status is 'Publish CSAF', expected 'In Progress'

Commit `ecd30ec566cf`

Summary: net/sched: Make cake_enqueue return NET_XMIT_CN when past buffer_limit

❌ Errors:

VULN-161937: Status is 'Publish CSAF', expected 'In Progress'

Commit `64a032d7cc69`

Summary: proc: fix type confusion in pde_set_flags()

❌ Errors:

VULN-163195: Status is 'Publish CSAF', expected 'In Progress'

Commit `df7ac4ac3237`

Summary: proc: fix missing pde_set_flags() for net proc files

❌ Errors:

VULN-163195: Status is 'Publish CSAF', expected 'In Progress'

Commit `103485ee89c5`

Summary: proc: use the same treatment to check proc_lseek as ones for proc_read_iter et.al

❌ Errors:

VULN-163195: Status is 'Publish CSAF', expected 'In Progress'

Commit `14aca461ae35`

Summary: bonding: fix use-after-free due to enslave fail after slave array update

❌ Errors:

VULN-176288: Status is 'Publish CSAF', expected 'In Progress'

Commit `85a7d0c51cbb`

Summary: migrate: correct lock ordering for hugetlb file folios

❌ Errors:

VULN-175621: Status is 'Publish CSAF', expected 'In Progress'

Commit `87ab54b911a7`

Summary: rxrpc: Fix recvmsg() unconditional requeue

❌ Errors:

VULN-175573: Status is 'Publish CSAF', expected 'In Progress'

Commit `3413fc4d7aa1`

Summary: nfsd: fix heap overflow in NFSv4.0 LOCK replay cache

❌ Errors:

VULN-180165: Status is 'Publish CSAF', expected 'In Progress'

Commit `b465bc7ca82a`

Summary: ptrace: slightly saner 'get_dumpable()' logic

❌ Errors:

VULN-185424: Status is 'Done', expected 'In Progress'

Commit `21735e78f46a`

Summary: net: skbuff: propagate shared-frag marker through frag-transfer helpers

❌ Errors:

VULN-185344: Status is 'Done', expected 'In Progress'

Commit `329c95f5762e`

Summary: xfrm: esp: avoid in-place decrypt on shared skb frags

❌ Errors:

VULN-184827: Status is 'Done', expected 'In Progress'

Commit `ef2dfebcaaa7`

Summary: can: raw: fix ro->uniq use-after-free in raw_rcv()

❌ Errors:

VULN-182366: Status is 'Done', expected 'In Progress'

Commit `53ed09bb4deb`

Summary: KVM: x86/mmu: Drop/zap existing present SPTE even when creating an MMIO SPTE

❌ Errors:

VULN-180397: Status is 'Done', expected 'In Progress'

Commit `8057bc2bf77a`

Summary: RDMA/umad: Reject negative data_len in ib_umad_write

❌ Errors:

VULN-178542: Status is 'Done', expected 'In Progress'

Commit `3f85829e99ad`

Summary: scsi: qla2xxx: Fix improper freeing of purex item

❌ Errors:

VULN-171237: Status is 'Done', expected 'In Progress'

Commit `c0c6833c097e`

Summary: bridge: mcast: Fix use-after-free during router port configuration

❌ Errors:

VULN-162934: Status is 'Done', expected 'In Progress'

Commit `67d7407aeff0`

Summary: net: bridge: mcast: update multicast contex when vlan state is changed

❌ Errors:

VULN-162934: Status is 'Done', expected 'In Progress'

Commit `10cab5a1faed`

Summary: net: bridge: mcast: re-implement br_multicast_{enable, disable}_port functions

❌ Errors:

VULN-162934: Status is 'Done', expected 'In Progress'

Commit `d385aa8bc3e7`

Summary: smb: client: let recv_done verify data_offset, data_length and remaining_data_length

❌ Errors:

VULN-161396: Status is 'Done', expected 'In Progress'

Commit `48f2beed4a9e`

Summary: io_uring/net: commit partial buffers on retry

❌ Errors:

VULN-163643: Status is 'Done', expected 'In Progress'

Commit `f7ecc9ae3a29`

Summary: io_uring/kbuf: add io_kbuf_commit() helper

❌ Errors:

VULN-163643: Status is 'Done', expected 'In Progress'

Commit `f8bf170cc6ea`

Summary: io_uring/kbuf: use 'bl' directly rather than req->buf_list

❌ Errors:

VULN-163643: Status is 'Done', expected 'In Progress'

Commit `8787ee97ffe7`

Summary: squashfs: fix memory leak in squashfs_fill_super

❌ Errors:

VULN-163295: Status is 'Done', expected 'In Progress'

Commit `0245e4bf66bf`

Summary: Squashfs: check return result of sb_min_blocksize

❌ Errors:

VULN-163295: Status is 'Done', expected 'In Progress'

Commit `62cf4f1d9e95`

Summary: can: j1939: add missing calls in NETDEV_UNREGISTER notification handler

❌ Errors:

VULN-161560: Status is 'Done', expected 'In Progress'

Commit `177e1ccfee92`

Summary: can: j1939: make j1939_sk_bind() fail if device is no longer registered

❌ Errors:

VULN-161560: Status is 'Done', expected 'In Progress'

Commit `0e96f71ec986`

Summary: can: j1939: implement NETDEV_UNREGISTER notification handler

❌ Errors:

VULN-161560: Status is 'Done', expected 'In Progress'

Commit `a5a792697ba5`

Summary: HID: multitouch: fix slab out-of-bounds access in mt_report_fixup()

❌ Errors:

VULN-162161: Status is 'Done', expected 'In Progress'

Commit `d05bcac120bd`

Summary: net/sched: mqprio: fix stack out-of-bounds write in tc entry parsing

❌ Errors:

VULN-163237: Status is 'Done', expected 'In Progress'

Commit `2fe5a1b522a5`

Summary: Bluetooth: MGMT: Fix dangling pointer on mgmt_add_adv_patterns_monitor_complete

❌ Errors:

VULN-182134: Status is 'Done', expected 'In Progress'

Commit `6d333d5551ce`

Summary: Bluetooth: MGMT: Fix list corruption and UAF in command complete handlers

❌ Errors:

VULN-161958: Status is 'Done', expected 'In Progress'

Commit `d16d54b67caf`

Summary: Bluetooth: MGMT: Fix memory leak in set_ssp_complete

❌ Errors:

VULN-176260: Status is 'Done', expected 'In Progress'

Commit `7db92a34e4ea`

Summary: Bluetooth: hci_sock: Prevent race in socket write iter and sock bind

❌ Errors:

VULN-170111: Status is 'Done', expected 'In Progress'

Commit `89264591bef1`

Summary: Bluetooth: MGMT: fix crash in set_mesh_sync and set_mesh_complete

❌ Errors:

VULN-181745: Status is 'Done', expected 'In Progress'

Commit `799f085c7aa7`

Summary: Bluetooth: MGMT: Fix possible UAFs

❌ Errors:

VULN-161958: Status is 'Done', expected 'In Progress'

Commit `fcde335b2832`

Summary: Bluetooth: hci_sync: fix set_local_name race condition

❌ Errors:

VULN-161958: Status is 'Done', expected 'In Progress'

Commit `4a92c023d442`

Summary: Bluetooth: MGMT: set_mesh: update LE scan interval and window

❌ Errors:

VULN-161958: Status is 'Done', expected 'In Progress'

Commit `e3c265f00bbf`

Summary: Bluetooth: MGMT: Protect mgmt_pending list with its own lock

❌ Errors:

VULN-162978: Status is 'Done', expected 'In Progress'

Commit `9f3908d225e1`

Summary: crypto: algif_aead - snapshot IV for async AEAD requests

❌ Errors:

VULN-181881: Status is 'Done', expected 'In Progress'

Commit `b4b2cffbe610`

Summary: crypto: algif_aead - Fix minimum RX size check for decryption

❌ Errors:

VULN-181881: Status is 'Done', expected 'In Progress'

Commit `07d00783737e`

Summary: crypto: authencesn - reject short ahash digests during instance creation

❌ Errors:

VULN-181881: Status is 'Done', expected 'In Progress'

Commit `11d1d2c143d9`

Summary: crypto: authencesn - Fix src offset when decrypting in-place

❌ Errors:

VULN-181881: Status is 'Done', expected 'In Progress'

Commit `d08cb27e2389`

Summary: crypto: authencesn - Do not place hiseq at end of dst for out-of-place decryption

❌ Errors:

VULN-181881: Status is 'Done', expected 'In Progress'

Commit `579007c5ff3a`

Summary: crypto: authencesn - reject too-short AAD (assoclen<8) to match ESP/ESN spec

❌ Errors:

VULN-175569: Status is 'Done', expected 'In Progress'

Commit `419e39eb1ae7`

Summary: crypto: af_alg - Fix page reassignment overflow in af_alg_pull_tsgl

❌ Errors:

VULN-182991: Status is 'Done', expected 'In Progress'

Commit `c5c2993b7304`

Summary: crypto: af_alg - limit RX SG extraction by receive buffer budget

❌ Errors:

VULN-182991: Status is 'Done', expected 'In Progress'

Commit `6b87a405fbe3`

Summary: crypto: algif_aead - Revert to operating out-of-place

❌ Errors:

VULN-181881: Status is 'Done', expected 'In Progress'

Commit `3e71c6913704`

Summary: crypto: af-alg - fix NULL pointer dereference in scatterwalk

❌ Errors:

VULN-181881: Status is 'Done', expected 'In Progress'

Commit `1ec6863e24ca`

Summary: irqchip/gic-v2m: Prevent use after free of gicv2m_get_fwnode()

❌ Errors:

VULN-162593: Status is 'Done', expected 'In Progress'

Commit `072f071aff57`

Summary: net: openvswitch: fix nested key length validation in the set() action

❌ Errors:

VULN-162463: Status is 'Done', expected 'In Progress'

Commit `29809bb2ec03`

Summary: drm/xe: Use local fence in error path of xe_migrate_clear

❌ Errors:

VULN-162597: Status is 'Done', expected 'In Progress'

Commit `043a6f56f6d8`

Summary: ntb_hw_switchtec: Fix shift-out-of-bounds in switchtec_ntb_mw_set_trans

❌ Errors:

VULN-164393: Status is 'Done', expected 'In Progress'

Commit `cd333e56cbfd`

Summary: usb: xhci: Fix isochronous Ring Underrun/Overrun event handling

❌ Errors:

VULN-162623: Status is 'Done', expected 'In Progress'

Commit `0abd7b95fbd3`

Summary: NFSD: fix hang in nfsd4_shutdown_callback

❌ Errors:

VULN-162091: Status is 'Done', expected 'In Progress'

Commit `2e1c2c90fd45`

Summary: scsi: mpi3mr: Synchronous access b/w reset and tm thread for reply queue

❌ Errors:

VULN-162605: Status is 'Done', expected 'In Progress'

Commit `155d4e2e66a5`

Summary: crypto: pcrypt - Call crypto layer directly when padata_do_parallel() return -EBUSY

❌ Errors:

VULN-166865: Status is 'Done', expected 'In Progress'

Commit `bb9afc275817`

Summary: netfilter: nf_tables: fix inverted genmask check in nft_map_catchall_activate()

❌ Errors:

VULN-176074: Status is 'Done', expected 'In Progress'

Commit `309a002696d6`

Summary: net/sched: cls_u32: use skb_header_pointer_careful()

❌ Errors:

VULN-176131: Status is 'Done', expected 'In Progress'

Commit `ba5b59cd80e7`

Summary: net: add skb_header_pointer_careful() helper

❌ Errors:

VULN-176131: Status is 'Done', expected 'In Progress'

Commit `0c57897b0e28`

Summary: scsi: target: iscsi: Fix use-after-free in iscsit_dec_session_usage_count()

❌ Errors:

VULN-176315: Status is 'Done', expected 'In Progress'

Commit `13e96b4d8e3f`

Summary: mm/damon/sysfs: cleanup attrs subdirs on context dir setup failure

❌ Errors:

VULN-176248: Status is 'Done', expected 'In Progress'

Commit `bfdaea2a7992`

Summary: io_uring/sqpoll: don't put task_struct on tctx setup failure

❌ Errors:

VULN-162982: Status is 'Done', expected 'In Progress'

Commit `2a8ee16e66ad`

Summary: io_uring: consistently use rcu semantics with sqpoll thread

❌ Errors:

VULN-162982: Status is 'Done', expected 'In Progress'

Commit `70f632164f65`

Summary: io_uring: fix use-after-free of sq->thread in __io_uring_show_fdinfo()

❌ Errors:

VULN-162982: Status is 'Done', expected 'In Progress'

Commit `dd254fe8d1f0`

Summary: io_uring: simplify the SQPOLL thread check when cancelling requests

❌ Errors:

VULN-162982: Status is 'Done', expected 'In Progress'

Commit `ac4b7503f7e7`

Summary: io_uring: don't touch sqd->thread off tw add

❌ Errors:

VULN-162982: Status is 'Done', expected 'In Progress'

Commit `34a077bfac32`

Summary: io_uring/sqpoll: fix sqpoll error handling races

❌ Errors:

VULN-162982: Status is 'Done', expected 'In Progress'

Commit `9f80f0bfb700`

Summary: io_uring/sqpoll: annotate debug task == current with data_race()

❌ Errors:

VULN-162982: Status is 'Done', expected 'In Progress'

Commit `615ec657cbcd`

Summary: kernfs: Fix UAF in polling when open file is released

❌ Errors:

VULN-161581: Status is 'Done', expected 'In Progress'

Summary: Checked 100 commit(s) total.

github-actions · 2026-06-11T12:00:39Z

❌ Validation checks completed with issues View full results: https://github.com/ctrliq/kernel-src-tree/actions/runs/27345132475

ciq-kernel-automation Bot added the created-by-kernelci Tag PRs that were automatically created when a user branch was pushed to the repo (kernelCI) label Jun 10, 2026

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ciq-kernel-automation Bot changed the title ~~[ciqlts9_6] Multiple patches tested (11 commits)~~ [ciqlts9_6] Multiple patches tested (12 commits) Jun 11, 2026

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shreeya-patel98 merged commit 123e224 into ciqlts9_6 Jun 11, 2026
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Commit 16b020e24ab2

Commit 3123c8097a7a

Commit cbaa65452f03

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Commit a24fd60bcec7

Commit dabba7d2c7c0

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