[ciqlts9_6] Multiple patches tested (12 commits)#1327
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[ciqlts9_6] Multiple patches tested (12 commits)#1327ciq-kernel-automation[bot] wants to merge 12 commits into
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jira VULN-187523 cve-pre CVE-2025-10263 commit-author Douglas Anderson <dianders@chromium.org> commit a9b5bd8 >From the TRM, MIDR_CORTEX_A76AE has a partnum of 0xDOE and an implementor of 0x41 (ARM). Add the values. Cc: stable@vger.kernel.org # dependency of the next fix in the series Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20250107120555.v4.4.I151f3b7ee323bcc3082179b8c60c3cd03308aa94@changeid Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit a9b5bd8) Signed-off-by: Brett Mastbergen <bmastbergen@ciq.com>
jira VULN-187523 cve-pre CVE-2025-10263 commit-author Mark Rutland <mark.rutland@arm.com> commit 9ef54a3 Add cputype definitions for Cortex-A725. These will be used for errata detection in subsequent patches. These values can be found in the Cortex-A725 TRM: https://developer.arm.com/documentation/107652/0001/ ... in table A-247 ("MIDR_EL1 bit descriptions"). Signed-off-by: Mark Rutland <mark.rutland@arm.com> Cc: James Morse <james.morse@arm.com> Cc: Will Deacon <will@kernel.org> Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com> Link: https://lore.kernel.org/r/20240801101803.1982459-3-mark.rutland@arm.com Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit 9ef54a3) Signed-off-by: Brett Mastbergen <bmastbergen@ciq.com>
jira VULN-187523 cve-pre CVE-2025-10263 commit-author Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> commit f38c2c3 Add cputype definitions for Cortex-A720AE. These will be used for errata detection in subsequent patches. These values can be found in the Cortex-A720AE TRM: https://developer.arm.com/documentation/102828/0001/ ... in Table A-187 Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Will Deacon <will@kernel.org> (cherry picked from commit f38c2c3) Signed-off-by: Brett Mastbergen <bmastbergen@ciq.com>
jira VULN-187523 cve-pre CVE-2025-10263 commit-author Mark Rutland <mark.rutland@arm.com> commit 9247257 Add cputype definitions for Neoverse-N3. These will be used for errata detection in subsequent patches. These values can be found in Table A-261 ("MIDR_EL1 bit descriptions") in issue 02 of the Neoverse-N3 TRM, which can be found at: https://developer.arm.com/documentation/107997/0000/?lang=en Signed-off-by: Mark Rutland <mark.rutland@arm.com> Cc: James Morse <james.morse@arm.com> Cc: Will Deacon <will@kernel.org> Link: https://lore.kernel.org/r/20240930111705.3352047-2-mark.rutland@arm.com Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit 9247257) Signed-off-by: Brett Mastbergen <bmastbergen@ciq.com>
jira VULN-187523 cve-pre CVE-2025-10263 commit-author Mark Rutland <mark.rutland@arm.com> commit 3bbf004 Add cputype definitions for Neoverse-V3AE. These will be used for errata detection in subsequent patches. These values can be found in the Neoverse-V3AE TRM: https://developer.arm.com/documentation/SDEN-2615521/9-0/ ... in section A.6.1 ("MIDR_EL1, Main ID Register"). Signed-off-by: Mark Rutland <mark.rutland@arm.com> Cc: James Morse <james.morse@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Ryan Roberts <ryan.roberts@arm.com> Signed-off-by: Will Deacon <will@kernel.org> (cherry picked from commit 3bbf004) Signed-off-by: Brett Mastbergen <bmastbergen@ciq.com>
jira VULN-187523 cve-pre CVE-2025-10263 commit-author Catalin Marinas <catalin.marinas@arm.com> commit 2c99561 Add cputype definitions for C1-Pro. These will be used for errata detection in subsequent patches. These values can be found in "Table A-303: MIDR_EL1 bit descriptions" in issue 07 of the C1-Pro TRM: https://documentation-service.arm.com/static/6930126730f8f55a656570af Acked-by: Mark Rutland <mark.rutland@arm.com> Cc: Will Deacon <will@kernel.org> Cc: James Morse <james.morse@arm.com> Reviewed-by: Will Deacon <will@kernel.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit 2c99561) Signed-off-by: Brett Mastbergen <bmastbergen@ciq.com>
jira VULN-187523 cve-pre CVE-2025-10263 commit-author Shanker Donthineni <sdonthineni@nvidia.com> commit e185c8a Add cpu part and model macro definitions for NVIDIA Olympus core. Signed-off-by: Shanker Donthineni <sdonthineni@nvidia.com> Signed-off-by: Will Deacon <will@kernel.org> (cherry picked from commit e185c8a) Signed-off-by: Brett Mastbergen <bmastbergen@ciq.com>
jira VULN-187523 cve-pre CVE-2025-10263 commit-author Mark Rutland <mark.rutland@arm.com> commit-source-sha 60349e6 commit-source arm64 Add cputype definitions for C1-Ultra. These will be used for errata detection in subsequent patches. These values can be found in the C1-Ultra TRM: https://developer.arm.com/documentation/108014/0100/ ... in section A.5.1 ("MIDR_EL1, Main ID Register"). Signed-off-by: Mark Rutland <mark.rutland@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Signed-off-by: Will Deacon <will@kernel.org> (cherry picked from commit 60349e6) Signed-off-by: Brett Mastbergen <bmastbergen@ciq.com>
jira VULN-187523 cve-pre CVE-2025-10263 commit-author Mark Rutland <mark.rutland@arm.com> commit-source-sha d28413b commit-source arm64 Add cputype definitions for C1-Premium. These will be used for errata detection in subsequent patches. These values can be found in the C1-Premium TRM: https://developer.arm.com/documentation/109416/0100/ ... in section A.5.1 ("MIDR_EL1, Main ID Register"). Signed-off-by: Mark Rutland <mark.rutland@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Signed-off-by: Will Deacon <will@kernel.org> (cherry picked from commit d28413b) Signed-off-by: Brett Mastbergen <bmastbergen@ciq.com>
jira VULN-187523 cve CVE-2025-10263 commit-author Mark Rutland <mark.rutland@arm.com> commit-source-sha cfd391e commit-source arm64 upstream-diff silicon-errata.rst at different path (Documentation/arm64/ vs Documentation/arch/arm64/) and required manual conflict resolution due to condensed table formatting and missing entries in our branch. Content is identical. A number of CPUs developed by Arm suffer from errata whereby a broadcast TLBI;DSB sequence may complete before the global observation of writes which are translated by an affected TLB entry. These errata ONLY affect the completion of memory accesses which have been translated by an invalidated TLB entry, and these errata DO NOT affect the actual invalidation of TLB entries. TLB entries are removed correctly. This issue has been assigned CVE ID CVE-2025-10263. To mitigate this issue, Arm recommends that software follows any affected TLBI;DSB sequence with an additional TLBI;DSB, which will ensure that all memory write effects affected by the first TLBI have been globally observed. The additional TLBI can use any operation that is broadcast to affected CPUs, and the additional DSB can use any option that is sufficient to complete the additional TLBI. The ARM64_WORKAROUND_REPEAT_TLBI workaround is sufficient to mitigate the issue. Enable this workaround for affected CPUs, and update the silicon errata documentation accordingly. Note that due to the manner in which Arm develops IP and tracks errata, some CPUs share a common erratum number. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Signed-off-by: Will Deacon <will@kernel.org> (cherry picked from commit cfd391e) Signed-off-by: Brett Mastbergen <bmastbergen@ciq.com>
jira VULN-187523 cve CVE-2025-10263 commit-author Shanker Donthineni <sdonthineni@nvidia.com> commit-source-sha ec7216f commit-source arm64 NVIDIA Olympus cores are affected by the TLBI completion issue tracked as CVE-2025-10263. The existing ARM64_ERRATUM_4118414 handling already uses ARM64_WORKAROUND_REPEAT_TLBI to issue an additional broadcast TLBI;DSB sequence and ensure affected memory write effects are globally observed. Add MIDR_NVIDIA_OLYMPUS to the repeat-TLBI match list so the same mitigation is enabled on affected Olympus systems. Also document the NVIDIA Olympus erratum in the arm64 silicon errata table and list it in the Kconfig help text. Signed-off-by: Shanker Donthineni <sdonthineni@nvidia.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Will Deacon <will@kernel.org> (cherry picked from commit ec7216f) Signed-off-by: Brett Mastbergen <bmastbergen@ciq.com>
jira VULN-187523 cve CVE-2025-10263 commit-author Will Deacon <will@kernel.org> commit-source-sha 1940e70 commit-source arm64 Commit fb091ff ("arm64: Subscribe Microsoft Azure Cobalt 100 to ARM Neoverse N2 errata") states that Microsoft Azure Cobalt 100 CPU "is a Microsoft implemented CPU based on r0p0 of the ARM Neoverse N2 CPU, and therefore suffers from all the same errata.". So enable the workaround for the latest broadcast TLB invalidation bug on these parts. Signed-off-by: Will Deacon <will@kernel.org> (cherry picked from commit 1940e70) Signed-off-by: Brett Mastbergen <bmastbergen@ciq.com>
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