(Part 3/6) Export C++ reference implementation and FPGA/ASIC algorithm parameters#108
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(Part 3/6) Export C++ reference implementation and FPGA/ASIC algorithm parameters#108antonysigma wants to merge 3 commits into
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Given the auto-generated C99 header file and C file `pdaqp.[ch]`, decode the problem sizes. Decode constant integer array. Decode the floating point array. Do not decode the algorithm implementation for now. Implement `cvxgen.hwgen.decode.decode()` function to return a `hwgen.PDAQPConfig` with basic parameters. Derived parameters can be generated on the fly, so they are omitted from the dataclass. Floating point data format defaults to `FIX16`. This eliminates `HWGen/scripts/config/parsers.py` and `writers.py`.
The hardware synthesis step (`PDAQPConfig` -> `design_verilog.v`) is too big. Decouple the "what to compute" and "how to synthesize" into two separate intermediate representations: `PDAQPAlgoConfig` and `PDAQPHWConfig`. Implement `specialise(PDAQPAlgoConfig) -> HWConfig` to synthesize the following high-level hardware-accelerated modules: - GEMV: combined matrix-vector multiply and addition, for the feedback step; - DotProductLeq: combined vector dot product and less-than-or-equal operation, used during the tree talking step; - TreeWalkerFSM: a finite state machine for walking along the half-planes. Implement `quantize()` to truncate the precisions of the floating point numbers to `Q2.14` fixed-point decimal format.
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Given the PDA-QP parameters `PDAQPAlgoConfig`, generate the reference implementation in C++20: `constants.hpp` and `problem-def.hpp`. Also, given the hardware accelerator config `PDAQPHWConfig`, generate the corresponding config file in Chisel HDL language `Constants.scala`. The hardware accelerator project code will be released soon.
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(Click this commit 23d40e5 for the incremental code changes specific to this pull request.)
Given the PDA-QP algorithm parameters
PDAQPAlgoConfig, generate the reference implementation in C++20:constants.hppandproblem-def.hpp. Download the C++20 project boilerplate pdqap-solver-cpp.Configure the project to enable commonly-used CPU hardware accelerations, (e.g. branch prediction, immediate operands, SIMD instructions), so as to speed up hardware design validation (more to that below).
The reference implementation is used for model-in-the-loop validation of the FPGA/ASIC design.
Also, given the hardware accelerator's high-level modular design
PDAQPHWConfig, generate the corresponding config file in Chisel HDL languageConstants.scala. The hardware accelerator project code, model-in-the-loop tests, correctness tests, monkey tests will be released soon.Related to: #94