ARM-Single-Cycle-CPU/Main_Decoder.bsf at master · cyusuftas/ARM-Single-Cycle-CPU · GitHub

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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2017  Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors.  Please
refer to the applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
	(rect 16 16 232 192)
	(text "Main_Decoder" (rect 5 0 64 12)(font "Arial" ))
	(text "inst" (rect 8 160 20 172)(font "Arial" ))
	(port
		(pt 0 32)
		(input)
		(text "funct5_0[5..0]" (rect 0 0 55 12)(font "Arial" ))
		(text "funct5_0[5..0]" (rect 21 27 76 39)(font "Arial" ))
		(line (pt 0 32)(pt 16 32)(line_width 3))
	)
	(port
		(pt 0 48)
		(input)
		(text "Op[1..0]" (rect 0 0 30 12)(font "Arial" ))
		(text "Op[1..0]" (rect 21 43 51 55)(font "Arial" ))
		(line (pt 0 48)(pt 16 48)(line_width 3))
	)
	(port
		(pt 0 64)
		(input)
		(text "Rd[3..0]" (rect 0 0 33 12)(font "Arial" ))
		(text "Rd[3..0]" (rect 21 59 54 71)(font "Arial" ))
		(line (pt 0 64)(pt 16 64)(line_width 3))
	)
	(port
		(pt 216 32)
		(output)
		(text "PCS" (rect 0 0 18 12)(font "Arial" ))
		(text "PCS" (rect 177 27 195 39)(font "Arial" ))
		(line (pt 216 32)(pt 200 32)(line_width 1))
	)
	(port
		(pt 216 48)
		(output)
		(text "RegW" (rect 0 0 28 12)(font "Arial" ))
		(text "RegW" (rect 167 43 195 55)(font "Arial" ))
		(line (pt 216 48)(pt 200 48)(line_width 1))
	)
	(port
		(pt 216 64)
		(output)
		(text "MemW" (rect 0 0 31 12)(font "Arial" ))
		(text "MemW" (rect 164 59 195 71)(font "Arial" ))
		(line (pt 216 64)(pt 200 64)(line_width 1))
	)
	(port
		(pt 216 80)
		(output)
		(text "ResultSrc[1..0]" (rect 0 0 59 12)(font "Arial" ))
		(text "ResultSrc[1..0]" (rect 136 75 195 87)(font "Arial" ))
		(line (pt 216 80)(pt 200 80)(line_width 3))
	)
	(port
		(pt 216 96)
		(output)
		(text "ALUSrc" (rect 0 0 35 12)(font "Arial" ))
		(text "ALUSrc" (rect 160 91 195 103)(font "Arial" ))
		(line (pt 216 96)(pt 200 96)(line_width 1))
	)
	(port
		(pt 216 112)
		(output)
		(text "RegSrc" (rect 0 0 31 12)(font "Arial" ))
		(text "RegSrc" (rect 164 107 195 119)(font "Arial" ))
		(line (pt 216 112)(pt 200 112)(line_width 1))
	)
	(port
		(pt 216 128)
		(output)
		(text "ALUOp" (rect 0 0 33 12)(font "Arial" ))
		(text "ALUOp" (rect 162 123 195 135)(font "Arial" ))
		(line (pt 216 128)(pt 200 128)(line_width 1))
	)
	(port
		(pt 216 144)
		(output)
		(text "sh_dir" (rect 0 0 24 12)(font "Arial" ))
		(text "sh_dir" (rect 171 139 195 151)(font "Arial" ))
		(line (pt 216 144)(pt 200 144)(line_width 1))
	)
	(drawing
		(rectangle (rect 16 16 200 160)(line_width 1))
	)
)