Skip to content

Commit dcd25ae

Browse files
AaronDotopsiff
AaronDot
authored and
opsiff
committed
drm/amdgpu: Make eleven EOP packet for GFX10_0/GFX11_0 have real content
The duplication of EOP packets for GFX10_0/GFX11_0, with the former one have seq written and the latter one have seq written, seems to confuse some hardware platform (e.g. Loongson 7A series PCIe controllers). Signed-off-by: wuqianhai <wuqianhai@loongson.cn> Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn> [Conflict for drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c because of commit cb17fff ("drm/amdgpu/mes: remove unused functions") upstreamed] (cherry picked from commit df704ac) Signed-off-by: Wentao Guan <guanwentao@uniontech.com> Conflicts: drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
1 parent 52a187a commit dcd25ae

2 files changed

Lines changed: 110 additions & 1 deletion

File tree

‎drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c‎

Lines changed: 50 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4672,8 +4672,13 @@ static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
46724672
irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
46734673
hw_prio = amdgpu_gfx_is_high_priority_graphics_queue(adev, ring) ?
46744674
AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
4675+
#ifdef CONFIG_LOONGARCH
4676+
return amdgpu_ring_init(adev, ring, 1024*2, &adev->gfx.eop_irq, irq_type,
4677+
hw_prio, NULL);
4678+
#else
46754679
return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
46764680
hw_prio, NULL);
4681+
#endif
46774682
}
46784683

46794684
static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
@@ -4704,8 +4709,13 @@ static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
47044709
hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
47054710
AMDGPU_RING_PRIO_2 : AMDGPU_RING_PRIO_DEFAULT;
47064711
/* type-2 packets are deprecated on MEC, use type-3 instead */
4712+
#ifdef CONFIG_LOONGARCH
4713+
return amdgpu_ring_init(adev, ring, 1024*2, &adev->gfx.eop_irq, irq_type,
4714+
hw_prio, NULL);
4715+
#else
47074716
return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
47084717
hw_prio, NULL);
4718+
#endif
47094719
}
47104720

47114721
static void gfx_v10_0_alloc_ip_dump(struct amdgpu_device *adev)
@@ -8715,7 +8725,35 @@ static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
87158725
{
87168726
bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
87178727
bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
8728+
#ifdef CONFIG_LOONGARCH
8729+
int i;
87188730

8731+
for (i = 0; i < 10; i++) {
8732+
/* RELEASE_MEM - flush caches, send int */
8733+
amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
8734+
amdgpu_ring_write(
8735+
ring,
8736+
(PACKET3_RELEASE_MEM_GCR_SEQ |
8737+
PACKET3_RELEASE_MEM_GCR_GL2_WB |
8738+
PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */
8739+
PACKET3_RELEASE_MEM_GCR_GLM_WB |
8740+
PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
8741+
PACKET3_RELEASE_MEM_EVENT_TYPE(
8742+
CACHE_FLUSH_AND_INV_TS_EVENT) |
8743+
PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
8744+
amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(
8745+
write64bit ? 2 : 1) |
8746+
PACKET3_RELEASE_MEM_INT_SEL(0)));
8747+
amdgpu_ring_write(ring, lower_32_bits(addr));
8748+
amdgpu_ring_write(ring, upper_32_bits(addr));
8749+
amdgpu_ring_write(ring, lower_32_bits(seq));
8750+
amdgpu_ring_write(ring, upper_32_bits(seq));
8751+
amdgpu_ring_write(ring, ring->is_mes_queue ?
8752+
(ring->hw_queue_id |
8753+
AMDGPU_FENCE_MES_QUEUE_FLAG) :
8754+
0);
8755+
}
8756+
#endif
87198757
/* RELEASE_MEM - flush caches, send int */
87208758
amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
87218759
amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
@@ -9842,7 +9880,11 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
98429880
SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
98439881
SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
98449882
4 + /* VM_FLUSH */
9883+
#ifdef CONFIG_LOONGARCH
9884+
8*11 + /* FENCE for VM_FLUSH */
9885+
#else
98459886
8 + /* FENCE for VM_FLUSH */
9887+
#endif
98469888
20 + /* GDS switch */
98479889
4 + /* double SWITCH_BUFFER,
98489890
* the first COND_EXEC jump to the place
@@ -9855,7 +9897,11 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
98559897
31 + /* DE_META */
98569898
3 + /* CNTX_CTRL */
98579899
5 + /* HDP_INVL */
9900+
#ifdef CONFIG_LOONGARCH
9901+
8*11 + 8*11 + /* FENCE x2 */
9902+
#else
98589903
8 + 8 + /* FENCE x2 */
9904+
#endif
98599905
2 + /* SWITCH_BUFFER */
98609906
8 + /* gfx_v10_0_emit_mem_sync */
98619907
2, /* gfx_v10_0_ring_emit_cleaner_shader */
@@ -9901,7 +9947,11 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
99019947
SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
99029948
SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
99039949
2 + /* gfx_v10_0_ring_emit_vm_flush */
9950+
#ifdef CONFIG_LOONGARCH
9951+
8*11 + 8*11 + 8*11 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */
9952+
#else
99049953
8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */
9954+
#endif
99059955
8 + /* gfx_v10_0_emit_mem_sync */
99069956
2, /* gfx_v10_0_ring_emit_cleaner_shader */
99079957
.emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */

‎drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c‎

Lines changed: 60 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1151,8 +1151,16 @@ static int gfx_v11_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
11511151
irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
11521152
hw_prio = amdgpu_gfx_is_high_priority_graphics_queue(adev, ring) ?
11531153
AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
1154-
return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
1154+
#ifdef CONFIG_LOONGARCH
1155+
r = amdgpu_ring_init(adev, ring, 1024*2, &adev->gfx.eop_irq, irq_type,
11551156
hw_prio, NULL);
1157+
#else
1158+
r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
1159+
hw_prio, NULL);
1160+
#endif
1161+
if (r)
1162+
return r;
1163+
return 0;
11561164
}
11571165

11581166
static int gfx_v11_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
@@ -1184,8 +1192,13 @@ static int gfx_v11_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
11841192
hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
11851193
AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
11861194
/* type-2 packets are deprecated on MEC, use type-3 instead */
1195+
#ifdef CONFIG_LOONGARCH
1196+
r = amdgpu_ring_init(adev, ring, 1024*2, &adev->gfx.eop_irq, irq_type,
1197+
hw_prio, NULL);
1198+
#else
11871199
r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
11881200
hw_prio, NULL);
1201+
#endif
11891202
if (r)
11901203
return r;
11911204

@@ -5930,7 +5943,37 @@ static void gfx_v11_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
59305943
{
59315944
bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
59325945
bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
5946+
#ifdef CONFIG_LOONGARCH
5947+
int i;
59335948

5949+
for (i = 0; i < 10; i++) {
5950+
/* RELEASE_MEM - flush caches, send int */
5951+
amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
5952+
amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
5953+
PACKET3_RELEASE_MEM_GCR_GL2_WB |
5954+
PACKET3_RELEASE_MEM_GCR_GL2_INV |
5955+
PACKET3_RELEASE_MEM_GCR_GL2_US |
5956+
PACKET3_RELEASE_MEM_GCR_GL1_INV |
5957+
PACKET3_RELEASE_MEM_GCR_GLV_INV |
5958+
PACKET3_RELEASE_MEM_GCR_GLM_INV |
5959+
PACKET3_RELEASE_MEM_GCR_GLM_WB |
5960+
PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
5961+
PACKET3_RELEASE_MEM_EVENT_TYPE(
5962+
CACHE_FLUSH_AND_INV_TS_EVENT) |
5963+
PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
5964+
amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(
5965+
write64bit ? 2 : 1) |
5966+
PACKET3_RELEASE_MEM_INT_SEL(0)));
5967+
amdgpu_ring_write(ring, lower_32_bits(addr));
5968+
amdgpu_ring_write(ring, upper_32_bits(addr));
5969+
amdgpu_ring_write(ring, lower_32_bits(seq));
5970+
amdgpu_ring_write(ring, upper_32_bits(seq));
5971+
amdgpu_ring_write(ring, ring->is_mes_queue ?
5972+
(ring->hw_queue_id |
5973+
AMDGPU_FENCE_MES_QUEUE_FLAG) :
5974+
0);
5975+
}
5976+
#endif
59345977
/* RELEASE_MEM - flush caches, send int */
59355978
amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
59365979
amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
@@ -7217,7 +7260,11 @@ static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_gfx = {
72177260
SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
72187261
SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
72197262
4 + /* VM_FLUSH */
7263+
#ifdef CONFIG_LOONGARCH
7264+
8*11 + /* FENCE for VM_FLUSH */
7265+
#else
72207266
8 + /* FENCE for VM_FLUSH */
7267+
#endif
72217268
20 + /* GDS switch */
72227269
5 + /* COND_EXEC */
72237270
7 + /* HDP_flush */
@@ -7226,7 +7273,11 @@ static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_gfx = {
72267273
3 + /* CNTX_CTRL */
72277274
5 + /* HDP_INVL */
72287275
22 + /* SET_Q_PREEMPTION_MODE */
7276+
#ifdef CONFIG_LOONGARCH
7277+
8*11 + 8*11 + /* FENCE x2 */
7278+
#else
72297279
8 + 8 + /* FENCE x2 */
7280+
#endif
72307281
8 + /* gfx_v11_0_emit_mem_sync */
72317282
2, /* gfx_v11_0_ring_emit_cleaner_shader */
72327283
.emit_ib_size = 4, /* gfx_v11_0_ring_emit_ib_gfx */
@@ -7272,9 +7323,17 @@ static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_compute = {
72727323
SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
72737324
SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
72747325
2 + /* gfx_v11_0_ring_emit_vm_flush */
7326+
#ifdef CONFIG_LOONGARCH
7327+
8*11 + 8*11 + 8*11 + /* gfx_v11_0_ring_emit_fence x3 for user fence, vm fence */
7328+
#else
72757329
8 + 8 + 8 + /* gfx_v11_0_ring_emit_fence x3 for user fence, vm fence */
7330+
<<<<<<< HEAD
72767331
8 + /* gfx_v11_0_emit_mem_sync */
72777332
2, /* gfx_v11_0_ring_emit_cleaner_shader */
7333+
=======
7334+
#endif
7335+
8, /* gfx_v11_0_emit_mem_sync */
7336+
>>>>>>> df704acbdb160 (drm/amdgpu: Make eleven EOP packet for GFX10_0/GFX11_0 have real content)
72787337
.emit_ib_size = 7, /* gfx_v11_0_ring_emit_ib_compute */
72797338
.emit_ib = gfx_v11_0_ring_emit_ib_compute,
72807339
.emit_fence = gfx_v11_0_ring_emit_fence,

0 commit comments

Comments
 (0)