[linux-6.6.y] LoongArch Stage Patch Synchronization 260302 by AaronDot · Pull Request #1519 · deepin-community/kernel

AaronDot · 2026-03-02T04:31:48Z

Introduction to the patchset:

Patch 1: backported from upstream;
Patch 2-4: Fixing legacy issues with the data sequence dislocation scheme;
Patch 5-7: Driver bug fixes;
Patch 8-11: Default config enabled.

commit f7794a4 upstream. The default COMMAND_LINE_SIZE of 512, inherited from asm-generic, is too small for modern use cases. For example, kdump configurations or extensive debugging parameters can easily exceed this limit. Therefore, increase the command line size to 4096 bytes, aligning LoongArch with the MIPS architecture. This change follows a broader trend among architectures to raise this limit to support modern needs; for instance, PowerPC increased its value for similar reasons in the commit a5980d0 ("powerpc: Bump COMMAND_LINE_SIZE to 2048"). Similar to the change made for RISC-V in the commit 61fc1ee ("riscv: Bump COMMAND_LINE_SIZE value to 1024"), this is considered a safe change. The broader kernel community has reached a consensus that modifying COMMAND_LINE_SIZE from UAPI headers does not constitute a uABI breakage, as well-behaved userspace applications should not rely on this macro. Suggested-by: Huang Cun <cunhuang@tencent.com> Signed-off-by: Ming Wang <wangming01@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn> Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>

Add the missing code when migrating this patch from 4.19 which can cause kernel deadlock. Fixes: bcaf362 (drm/amdgpu: Fix pcie order dislocation) Signed-off-by: wuqianhai <wuqianhai@loongson.cn> Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>

Fix the pointer error of wptr/rptr in ih_fix_loongarch_pcie_order(). Fixes: bcaf362 (drm/amdgpu: Fix pcie order dislocation) Signed-off-by: zhaotianrui <zhaotianrui@loongson.cn> Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>

The duplication of EOP packets for GFX10_0/GFX11_0, with the former one have seq written and the latter one have seq written, seems to confuse some hardware platform (e.g. Loongson 7A series PCIe controllers). Signed-off-by: wuqianhai <wuqianhai@loongson.cn> Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>

Export symbol for pwm_add_table, so that other drivers can use this function. For example, loonggpu backlight driver need to call pwm_add_table() to add loongson_pwm information into pwm_lookup_list, then pwm dev can be found by calling pwm_get(). The usage of pwm_add_table in loonggpu backlight driver like this: static struct pwm_lookup loongson_pwm_lookup; static void init_loongson_pwm_lookup(int pwm_id, const char *dev_name) { char provider[20]; sprintf(provider, "LOON0006:0%d", pwm_id); loongson_pwm_lookup.provider = provider; loongson_pwm_lookup.index = 0; loongson_pwm_lookup.dev_id = dev_name; loongson_pwm_lookup.con_id = NULL; loongson_pwm_lookup.period = 0; loongson_pwm_lookup.polarity = PWM_POLARITY_NORMAL; loongson_pwm_lookup.module = "pwm-loongson"; } static void loonggpu_backlight_init() { ... init_loongson_pwm_lookup(pwm, dev_name(dev)); pwm_add_table(&loongson_pwm_lookup, 1); pwm = pwm_get(dev, NULL); ... } Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn> Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>

Signed-off-by: Haowei Zheng <zhenghaowei@loongson.cn> Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>

some chipset only support 8bit read/write in BIT_CTRL_MODE, so change to readb/writeb uniformly. ---------------------------------------------------------- 2k2000/2k3000 7a2000 3a6000 ---------------------------------------------------------- node_gpio Bit: b/l/q - Bit: b/l/q Byte: Not Support - Byte: Not Support ---------------------------------------------------------- chipset_gpio Bit: b Bit: b - Byte: b Byte: b - -------------------------------------------------------------- acpi_gpio Bit: b/l/q Bit: b/l - Byte: Not Support Byte: Not Support - -------------------------------------------------------------- b：writeb/readb l：writel/readl q：writeq/readq Signed-off-by: wanghongliang <wanghongliang@loongson.cn> Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>

…lures The legacy PTY driver (CONFIG_LEGACY_PTYS) is deprecated and not required for most modern systems. It causes unexpected behavior during gnulib tests, leading to test failures related to pseudo-terminal handling. Disabling CONFIG_LEGACY_PTYS removes the old /dev/pty* and /dev/tty* interfaces, allowing gnulib tests to run successfully with the modern /dev/pts/* subsystem. Signed-off-by: yangxiaojuan <yangxiaojuan@loongson.cn> Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>

Like this: [ 130.469445] [ T759] do_page_fault(): sending SIGSEGV to pipewire for invalid read access from 000055560db01c91 [ 130.479455] [ T759] era = 00007fffeea0406c in libasound.so.2.0.0[7fffee940000+11c000] [ 130.487283] [ T759] ra = 00007fffeeafe990 in libspa-alsa.so[7fffeea80000+104000] [ 130.669705] [ T967] do_page_fault(): sending SIGSEGV to pipewire for invalid read access from 00005555619e4000 [ 130.679771] [ T967] era = 00007fffee88e9ac in libspa-alsa.so[7fffee810000+104000] [ 130.687229] [ T967] ra = 00007fffee88e9a0 in libspa-alsa.so[7fffee810000+104000] Signed-off-by: yangxiaojuan <yangxiaojuan@loongson.cn> Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>

Enable this configuration to prevent PSI from working by default, thereby improving system performance Signed-off-by: zhangtianyang <zhangtianyang@loongson.cn> Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>

Support for LEDS connected to GPIO. Signed-off-by: wanghongliang <wanghongliang@loongson.cn> Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>

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deepin-ci-robot · 2026-03-02T04:32:06Z

Hi @AaronDot. Thanks for your PR.

I'm waiting for a deepin-community member to verify that this patch is reasonable to test. If it is, they should reply with /ok-to-test on its own line. Until that is done, I will not automatically test new commits in this PR, but the usual testing commands by org members will still work. Regular contributors should join the org to skip this step.

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deepin-ci-robot · 2026-03-02T05:53:57Z

[APPROVALNOTIFIER] This PR is APPROVED

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opsiff · 2026-03-02T05:54:43Z

已合并

opsiff · 2026-03-03T02:12:01Z


 	mutex_unlock(&pwm_lookup_lock);
 }
+EXPORT_SYMBOL_GPL(pwm_add_table);


导出pwm_add_table这个，是否需要导出pwm_remove_table做错误处理?

可以参考一下这里的讨论 https://lists.freedesktop.org/archives/dri-devel/2016-December/126086.html

Copilot

Pull request overview

This patchset synchronizes several LoongArch-stage backports and fixes, including LoongArch-specific workarounds in AMDGPU, a PWM symbol export for module consumers, a UAPI header addition for LoongArch setup, and LoongArch defconfig updates.

Changes:

Export pwm_add_table() to make PWM lookup table registration available to GPL modules.
Add LoongArch-specific AMDGPU adjustments (ring sizes, fence emission behavior, IH processing/workqueue changes).
Add LoongArch UAPI asm/setup.h and enable/adjust defaults in LoongArch defconfigs.

Reviewed changes

Copilot reviewed 11 out of 11 changed files in this pull request and generated 7 comments.

Show a summary per file

File	Description
drivers/pwm/core.c	Exports `pwm_add_table()` for use by GPL modules.
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c	LoongArch-specific ring sizing and fence emission changes for GFX11.
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c	LoongArch-specific ring sizing and fence emission changes for GFX10.
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c	LoongArch-conditional MES ring sizing for selected GC IP versions.
drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h	Extends IH ring struct with LoongArch-only fields for fixup work/locking.
drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c	Moves LoongArch fixup work into `amdgpu_ih_ring`, adds atomic lock usage.
drivers/gpio/gpio-loongson-64bit.c	Adjusts BIT_CTRL_MODE GPIO register access patterns (byte-based).
drivers/cpufreq/loongson3-acpi-cpufreq.c	Adjusts CPU ID field packing usage; touched macro region.
arch/loongarch/include/uapi/asm/setup.h	Adds LoongArch UAPI header defining `COMMAND_LINE_SIZE`.
arch/loongarch/configs/loongson3_defconfig	Enables/disables several defaults (PSI default disabled, audio UMP, LEDs GPIO, etc.).
arch/loongarch/configs/deepin_loongarch_desktop_defconfig	Mirrors similar default config updates for Deepin desktop.

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Copilot · 2026-03-03T02:37:36Z

+#ifdef CONFIG_LOONGARCH
+		8*11 + 8*11 + /* FENCE x2 */
+#else
 		8 + 8 + /* FENCE x2 */
+#endif


The LoongArch fence size adjustment (8*11, etc.) is tightly coupled to the hard-coded loop count in gfx_v10_0_ring_emit_fence(). If the loop count changes, these sizes can silently become wrong and cause ring allocation/overflow issues. Consider deriving these sizes from a shared named constant used by both the emit_fence() loop and the emit size expressions.

Copilot · 2026-03-03T02:37:37Z

+	INIT_WORK(&ih->fix_work, amdgpu_ih_handle_fix_work);
+	ih->adev = adev;
+	atomic_set(&ih->lock, 0);
+	for (r = 0; r < (ih->ring_size >> 2); r++)
+		ih->ring[r] = 0xDEADBEFF;


In amdgpu_ih_ring_init(), the variable "r" is used both as an error code earlier in the function and then reused as the loop index when initializing ih->ring[] under CONFIG_LOONGARCH. This is easy to misread and can hide future bugs if additional error handling is added after the loop. Consider using a dedicated loop variable (e.g., i) for the ring initialization.

Suggested change

INIT_WORK(&ih->fix_work, amdgpu_ih_handle_fix_work);

ih->adev = adev;

atomic_set(&ih->lock, 0);

for (r = 0; r < (ih->ring_size >> 2); r++)

ih->ring[r] = 0xDEADBEFF;

unsigned int i;

INIT_WORK(&ih->fix_work, amdgpu_ih_handle_fix_work);

ih->adev = adev;

atomic_set(&ih->lock, 0);

for (i = 0; i < (ih->ring_size >> 2); i++)

ih->ring[i] = 0xDEADBEFF;

Copilot · 2026-03-03T02:37:37Z

 #define BOOST_THRESHOLD			(900)
 #define MAX_CORES_PER_PACKAGE		64
-#define CPU_ID_FIELD			0xf
 #define VOLTAGE_COMMAND			0x21


VOLTAGE_COMMAND is defined twice in this file (#define VOLTAGE_COMMAND 0x21 appears earlier and again here). This can trigger a macro redefinition warning and is easy to miss. Please keep a single definition (or #undef before redefining if intentional).

Suggested change

#define VOLTAGE_COMMAND 0x21

Copilot · 2026-03-03T02:37:37Z


 	mutex_unlock(&pwm_lookup_lock);
 }
+EXPORT_SYMBOL_GPL(pwm_add_table);


Exporting pwm_add_table() for modules makes it possible for a module to register lookup entries, but pwm_remove_table() is still not exported. That makes it hard/impossible for a module to clean up its registrations on unload, potentially leaving stale list entries. Consider exporting pwm_remove_table() as well (or otherwise providing a safe teardown path for modules that call pwm_add_table()).

Copilot · 2026-03-03T02:37:37Z

+	for (i = 0; i < 10; i++) {
+		/* RELEASE_MEM - flush caches, send int */
+		amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
+		amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
+					 PACKET3_RELEASE_MEM_GCR_GL2_WB |
+					 PACKET3_RELEASE_MEM_GCR_GL2_INV |
+					 PACKET3_RELEASE_MEM_GCR_GL2_US |
+					 PACKET3_RELEASE_MEM_GCR_GL1_INV |
+					 PACKET3_RELEASE_MEM_GCR_GLV_INV |
+					 PACKET3_RELEASE_MEM_GCR_GLM_INV |
+					 PACKET3_RELEASE_MEM_GCR_GLM_WB |
+					 PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
+					 PACKET3_RELEASE_MEM_EVENT_TYPE(
+						 CACHE_FLUSH_AND_INV_TS_EVENT) |
+					 PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
+		amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(
+						 write64bit ? 2 : 1) |
+					 PACKET3_RELEASE_MEM_INT_SEL(0)));
+		amdgpu_ring_write(ring, lower_32_bits(addr));


The LoongArch-only loop emits RELEASE_MEM 10 times with PACKET3_RELEASE_MEM_INT_SEL(0), but the comment says "send int". Also, the retry count "10" is an unexplained magic number duplicated across gfx versions; please add a clear rationale (e.g., link to the ordering issue/erratum) and consider making it a named constant so the loop count and the corresponding emit size calculations stay in sync.

Copilot · 2026-03-03T02:37:38Z

+#ifdef CONFIG_LOONGARCH
+		8*11 + /* FENCE for VM_FLUSH */
+#else
 		8 + /* FENCE for VM_FLUSH */
+#endif


The LoongArch fence size adjustment (8*11, etc.) is tightly coupled to the hard-coded loop count in gfx_v11_0_ring_emit_fence(). If the loop count changes, these sizes can silently become wrong and cause ring allocation/overflow issues. Consider deriving these sizes from a shared named constant used by both the emit_fence() loop and the emit size expressions.

Copilot · 2026-03-03T02:37:38Z

+	for (i = 0; i < 10; i++) {
+		/* RELEASE_MEM - flush caches, send int */
+		amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
+		amdgpu_ring_write(
+			ring,
+			(PACKET3_RELEASE_MEM_GCR_SEQ |
+			 PACKET3_RELEASE_MEM_GCR_GL2_WB |
+			 PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */
+			 PACKET3_RELEASE_MEM_GCR_GLM_WB |
+			 PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
+			 PACKET3_RELEASE_MEM_EVENT_TYPE(
+				 CACHE_FLUSH_AND_INV_TS_EVENT) |
+			 PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
+		amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(
+						 write64bit ? 2 : 1) |
+					 PACKET3_RELEASE_MEM_INT_SEL(0)));
+		amdgpu_ring_write(ring, lower_32_bits(addr));


The LoongArch-only loop emits RELEASE_MEM 10 times with PACKET3_RELEASE_MEM_INT_SEL(0), but the comment says "send int". Also, the retry count "10" is an unexplained magic number duplicated across gfx versions; please add a clear rationale (e.g., link to the ordering issue/erratum) and consider making it a named constant so the loop count and the corresponding emit size calculations stay in sync.

AaronDot and others added 11 commits March 2, 2026 12:07

cpufreq: loongson3-acpi: Expand cpu id field for 3C6000

fb09d04

Signed-off-by: Haowei Zheng <zhenghaowei@loongson.cn> Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>

Loongarch: configs: Enable CONFIG_PSI_DEFAULT_DISABLED

b5a3b47

Enable this configuration to prevent PSI from working by default, thereby improving system performance Signed-off-by: zhangtianyang <zhangtianyang@loongson.cn> Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>

LoongArch: configs: Enable CONFIG_LEDS_GPIO

d300356

Support for LEDS connected to GPIO. Signed-off-by: wanghongliang <wanghongliang@loongson.cn> Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>

sourcery-ai Bot reviewed Mar 2, 2026

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deepin-ci-robot added the needs-ok-to-test label Mar 2, 2026

deepin-ci-robot requested review from Ink-Paper, MingcongBai and shy129 March 2, 2026 04:32

opsiff approved these changes Mar 2, 2026

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opsiff merged commit 3eb2bb0 into deepin-community:linux-6.6.y Mar 2, 2026
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Avenger-285714 requested review from Avenger-285714 and Copilot March 3, 2026 02:28

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opsiff mentioned this pull request Mar 17, 2026

[Deepin-Kernel-SIG] [linux 6.18-y] [LoongArch] LoongArch Stage Patch Synchronization 260302 #1569

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