From df4ac1400db5f4f77eff2fd42dd25ba24b53dcd0 Mon Sep 17 00:00:00 2001 From: Binbin Zhou Date: Mon, 2 Mar 2026 12:07:12 +0800 Subject: [PATCH 01/13] Loongarch: configs: Enable CONFIG_PSI_DEFAULT_DISABLED Enable this configuration to prevent PSI from working by default, thereby improving system performance Signed-off-by: zhangtianyang Signed-off-by: Binbin Zhou Link: https://github.com/deepin-community/kernel/pull/1519/changes/b5a3b475c823a7bb533ba88eab69ab8c1bae4700 (cherry picked from commit cdf27e00f8a313d5d623c5dae67a3c809c955af0) Signed-off-by: Wentao Guan Conflicts: arch/loongarch/configs/loongson3_defconfig --- arch/loongarch/configs/deepin_loongarch_desktop_defconfig | 1 + arch/loongarch/configs/loongson3_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/loongarch/configs/deepin_loongarch_desktop_defconfig b/arch/loongarch/configs/deepin_loongarch_desktop_defconfig index b926abedee7d6..09bb412dbe78f 100644 --- a/arch/loongarch/configs/deepin_loongarch_desktop_defconfig +++ b/arch/loongarch/configs/deepin_loongarch_desktop_defconfig @@ -21,6 +21,7 @@ CONFIG_TASK_DELAY_ACCT=y CONFIG_TASK_XACCT=y CONFIG_TASK_IO_ACCOUNTING=y CONFIG_PSI=y +CONFIG_PSI_DEFAULT_DISABLED=y CONFIG_RCU_EXPERT=y CONFIG_RCU_BOOST=y CONFIG_RCU_NOCB_CPU=y diff --git a/arch/loongarch/configs/loongson3_defconfig b/arch/loongarch/configs/loongson3_defconfig index 0aa6f478cc7c4..da33b7bcb6400 100644 --- a/arch/loongarch/configs/loongson3_defconfig +++ b/arch/loongarch/configs/loongson3_defconfig @@ -16,6 +16,7 @@ CONFIG_TASK_DELAY_ACCT=y CONFIG_TASK_XACCT=y CONFIG_TASK_IO_ACCOUNTING=y CONFIG_PSI=y +CONFIG_PSI_DEFAULT_DISABLED=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_IKHEADERS=y From 0b3b249ebf78b85ef6c50010adafb045aff582f6 Mon Sep 17 00:00:00 2001 From: Wentao Guan Date: Tue, 17 Mar 2026 11:54:39 +0800 Subject: [PATCH 02/13] Revert "drm: amdgpu: radeon: disable cache flush workaround for LoongArch and Loongson64" This reverts commit 727f03e42d0fac0cd15e9a9c13eec4be2ffa9743. A more complete workaround is coming. This reverts commit 79c3ae8158205a9197f689604cea5d4140be7495. Signed-off-by: Binbin Zhou Signed-off-by: Wentao Guan --- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 9 --------- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 8 -------- drivers/gpu/drm/radeon/cik.c | 8 -------- 3 files changed, 25 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index e9a1957806b79..2b7aba22ecc19 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -2125,14 +2125,6 @@ static void gfx_v7_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr, bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; bool exec = flags & AMDGPU_FENCE_FLAG_EXEC; - -/* This workaround causes instability for LoongArch/Loongson (MIPS) - * devices based on the 7A1000/2000 chipset under heavy I/O load. - * - * FIXME: Disable this workaround until we find a better fix (possibly in - * the platform-specific PCI code). - */ -#ifndef CONFIG_MACH_LOONGSON64 /* Workaround for cache flush problems. First send a dummy EOP * event down the pipe with seq one below. */ @@ -2146,7 +2138,6 @@ static void gfx_v7_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr, DATA_SEL(1) | INT_SEL(0)); amdgpu_ring_write(ring, lower_32_bits(seq - 1)); amdgpu_ring_write(ring, upper_32_bits(seq - 1)); -#endif /* Then send the real EOP event down the pipe. */ amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 61b999f2e8c80..8a81713d97aac 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -6113,13 +6113,6 @@ static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr, bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; bool exec = flags & AMDGPU_FENCE_FLAG_EXEC; -/* This workaround causes instability for LoongArch/Loongson (MIPS) - * devices based on the 7A1000/2000 chipset under heavy I/O load. - * - * FIXME: Disable this workaround until we find a better fix (possibly in - * the platform-specific PCI code). - */ -#ifndef CONFIG_MACH_LOONGSON64 /* Workaround for cache flush problems. First send a dummy EOP * event down the pipe with seq one below. */ @@ -6134,7 +6127,6 @@ static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr, DATA_SEL(1) | INT_SEL(0)); amdgpu_ring_write(ring, lower_32_bits(seq - 1)); amdgpu_ring_write(ring, upper_32_bits(seq - 1)); -#endif /* Then send the real EOP event down the pipe: * EVENT_WRITE_EOP - flush caches, send int */ diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c index 8e2e9eaa87b4f..e4f0286047360 100644 --- a/drivers/gpu/drm/radeon/cik.c +++ b/drivers/gpu/drm/radeon/cik.c @@ -3543,13 +3543,6 @@ void cik_fence_gfx_ring_emit(struct radeon_device *rdev, struct radeon_ring *ring = &rdev->ring[fence->ring]; u64 addr = rdev->fence_drv[fence->ring].gpu_addr; -/* This workaround causes instability for LoongArch/Loongson (MIPS) - * devices based on the 7A1000/2000 chipset under heavy I/O load. - * - * FIXME: Disable this workaround until we find a better fix (possibly in - * the platform-specific PCI code). - */ -#ifndef CONFIG_MACH_LOONGSON64 /* Workaround for cache flush problems. First send a dummy EOP * event down the pipe with seq one below. */ @@ -3563,7 +3556,6 @@ void cik_fence_gfx_ring_emit(struct radeon_device *rdev, DATA_SEL(1) | INT_SEL(0)); radeon_ring_write(ring, fence->seq - 1); radeon_ring_write(ring, 0); -#endif /* Then send the real EOP event down the pipe. */ radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); From 90e642edc9ba6915c3c397076887368a56d884d5 Mon Sep 17 00:00:00 2001 From: Binbin Zhou Date: Wed, 17 Sep 2025 17:34:25 +0800 Subject: [PATCH 03/13] drm/radeon: repeat the same EOP packet for EOP workaround on CIK maillist inclusion category: bugfix Ths first EOP packet with a sequence number as seq-1 seems to confuse some PCIe hardware (e.g. Loongson 7A PCHs). Use the real sequence number instead. Fixes: a9c73a0e022c ("drm/radeon: workaround for CP HW bug on CIK") Link: https://lore.kernel.org/all/73597116d4f004c5f75cf4f13da1af405ea8da8b.camel@icenowy.me/ Link:https://github.com/deepin-community/kernel/pull/1182 Signed-off-by: Icenowy Zheng Signed-off-by: lvjianmin Signed-off-by: Hongchen Zhang Signed-off-by: Binbin Zhou Signed-off-by: Wentao Guan (cherry picked from commit b74f17f220792adb1533d12cf0d9bcf227167b12) Signed-off-by: Wentao Guan --- drivers/gpu/drm/radeon/cik.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c index e4f0286047360..77e0c0be7aad1 100644 --- a/drivers/gpu/drm/radeon/cik.c +++ b/drivers/gpu/drm/radeon/cik.c @@ -3554,7 +3554,11 @@ void cik_fence_gfx_ring_emit(struct radeon_device *rdev, radeon_ring_write(ring, addr & 0xfffffffc); radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | DATA_SEL(1) | INT_SEL(0)); +#ifdef CONFIG_LOONGARCH + radeon_ring_write(ring, fence->seq); +#else radeon_ring_write(ring, fence->seq - 1); +#endif radeon_ring_write(ring, 0); /* Then send the real EOP event down the pipe. */ From 2b76df07ddf9b49f72e7f014366095b6aaefb79f Mon Sep 17 00:00:00 2001 From: Binbin Zhou Date: Wed, 17 Sep 2025 17:34:25 +0800 Subject: [PATCH 04/13] drm/amdgpu: make duplicated EOP packet for GFX7/8 have real content maillist inclusion category: bugfix The duplication of EOP packets for GFX7/8, with the former one have seq-1 written and the latter one have seq written, seems to confuse some hardware platform (e.g. Loongson 7A series PCIe controllers). Make the content of the duplicated EOP packet the same with the real one, only masking any possible interrupts. Fixes: bf26da927a1c ("drm/amdgpu: add cache flush workaround to gfx8 emit_fence") Fixes: a2e73f56fa62 ("drm/amdgpu: Add support for CIK parts") Link: https://lore.kernel.org/all/20240617105846.1516006-3-uwu@icenowy.me/ Link: https://github.com/deepin-community/kernel/pull/1182 Signed-off-by: Icenowy Zheng Signed-off-by: lvjianmin Signed-off-by: Hongchen Zhang Signed-off-by: Binbin Zhou Signed-off-by: Wentao Guan (cherry picked from commit 275fc45f08424bf0e33f22a042f798c9b76f2765) Signed-off-by: Wentao Guan --- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 6 ++++++ drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index 2b7aba22ecc19..6135a6d81a7d4 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -2135,11 +2135,17 @@ static void gfx_v7_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr, EVENT_INDEX(5))); amdgpu_ring_write(ring, addr & 0xfffffffc); amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | +#ifdef CONFIG_LOONGARCH + DATA_SEL(write64bit ? 2 : 1) | INT_SEL(0)); + amdgpu_ring_write(ring, lower_32_bits(seq)); + amdgpu_ring_write(ring, upper_32_bits(seq)); +#else DATA_SEL(1) | INT_SEL(0)); amdgpu_ring_write(ring, lower_32_bits(seq - 1)); amdgpu_ring_write(ring, upper_32_bits(seq - 1)); /* Then send the real EOP event down the pipe. */ +#endif amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | EOP_TC_ACTION_EN | diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 8a81713d97aac..70025c2f27c3d 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -6124,12 +6124,18 @@ static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr, EVENT_INDEX(5))); amdgpu_ring_write(ring, addr & 0xfffffffc); amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | +#ifdef CONFIG_LOONGARCH + DATA_SEL(write64bit ? 2 : 1) | INT_SEL(0)); + amdgpu_ring_write(ring, lower_32_bits(seq)); + amdgpu_ring_write(ring, upper_32_bits(seq)); +#else DATA_SEL(1) | INT_SEL(0)); amdgpu_ring_write(ring, lower_32_bits(seq - 1)); amdgpu_ring_write(ring, upper_32_bits(seq - 1)); /* Then send the real EOP event down the pipe: * EVENT_WRITE_EOP - flush caches, send int */ +#endif amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | EOP_TC_ACTION_EN | From c48aea9b8cb529e31963ef26bfef2b113264ba60 Mon Sep 17 00:00:00 2001 From: Binbin Zhou Date: Wed, 17 Sep 2025 17:34:25 +0800 Subject: [PATCH 05/13] drm/amdgpu: make duplicated EOP packet for GFX6 have real content maillist inclusion category: bugfix Link: https://github.com/deepin-community/kernel/pull/1182 Signed-off-by: Tianrui Zhao Signed-off-by: Hongchen Zhang Signed-off-by: Binbin Zhou Signed-off-by: Wentao Guan (cherry picked from commit 2364f257439b2126a2ebcf9e9a5a55c59784d84b) Signed-off-by: Wentao Guan --- drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c index 80565392313f1..075968bebc944 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c @@ -1839,6 +1839,17 @@ static void gfx_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, amdgpu_ring_write(ring, 0xFFFFFFFF); amdgpu_ring_write(ring, 0); amdgpu_ring_write(ring, 10); /* poll interval */ +#ifdef CONFIG_LOONGARCH + /* EVENT_WRITE_EOP - flush caches, no send int */ + amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); + amdgpu_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5)); + amdgpu_ring_write(ring, addr & 0xfffffffc); + amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | + ((write64bit ? 2 : 1) << CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT) | + (0 << CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT)); + amdgpu_ring_write(ring, lower_32_bits(seq)); + amdgpu_ring_write(ring, upper_32_bits(seq)); +#endif /* EVENT_WRITE_EOP - flush caches, send int */ amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); amdgpu_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5)); @@ -3460,7 +3471,11 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = { .set_wptr = gfx_v6_0_ring_set_wptr_gfx, .emit_frame_size = 5 + 5 + /* hdp flush / invalidate */ +#ifdef CONFIG_LOONGARCH + 20 + 20 + 20 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */ +#else 14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */ +#endif 7 + 4 + /* gfx_v6_0_ring_emit_pipeline_sync */ SI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + 6 + /* gfx_v6_0_ring_emit_vm_flush */ 3 + 2 + /* gfx_v6_ring_emit_cntxcntl including vgt flush */ @@ -3489,7 +3504,11 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = { 5 + 5 + /* hdp flush / invalidate */ 7 + /* gfx_v6_0_ring_emit_pipeline_sync */ SI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v6_0_ring_emit_vm_flush */ +#ifdef CONFIG_LOONGARCH + 20 + 20 + 20 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */ +#else 14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */ +#endif 5, /* SURFACE_SYNC */ .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */ .emit_ib = gfx_v6_0_ring_emit_ib, From 38b2fd22c4aee684d0517948e5255c7dd09fd1d0 Mon Sep 17 00:00:00 2001 From: Binbin Zhou Date: Wed, 17 Sep 2025 17:34:25 +0800 Subject: [PATCH 06/13] drm/amdgpu: Fix pcie order dislocation Signed-off-by: Tianrui Zhao Signed-off-by: Hongchen Zhang Signed-off-by: Binbin Zhou (cherry picked from commit bcaf362d57b0235324fd6ff3812c2c5463abe782) Signed-off-by: Wentao Guan Conflicts: drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 5 + drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c | 154 ++++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h | 6 + drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 4 + drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h | 3 + 5 files changed, 172 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 2f6a96af7fb12..fe43c5ddf0364 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -1289,6 +1289,11 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, uint64_t seq; int r; +#ifdef CONFIG_LOONGARCH + while (amdgpu_ih_fix_is_busy(p->adev)) + msleep(20); +#endif + for (i = 0; i < p->gang_size; ++i) drm_sched_job_arm(&p->jobs[i]->base); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c index a6419246e9c24..5ab4beed7c127 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c @@ -27,6 +27,10 @@ #include "amdgpu_ih.h" #include "amdgpu_reset.h" +#ifdef CONFIG_LOONGARCH +static void amdgpu_ih_handle_fix_work(struct work_struct *work); +#endif + /** * amdgpu_ih_ring_init - initialize the IH state * @@ -72,6 +76,15 @@ int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih, ih->wptr_cpu = &ih->ring[ih->ring_size / 4]; ih->rptr_addr = dma_addr + ih->ring_size + 4; ih->rptr_cpu = &ih->ring[(ih->ring_size / 4) + 1]; + + #ifdef CONFIG_LOONGARCH + INIT_WORK(&adev->irq.ih.fix_work, amdgpu_ih_handle_fix_work); + for (r = 0; r < (adev->irq.ih.ring_size >> 2); r++) + adev->irq.ih.ring[r] = 0xDEADBEFF; + /* memory barrier for writing into ih ring */ + mb(); + #endif + } else { unsigned wptr_offs, rptr_offs; @@ -99,6 +112,15 @@ int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih, ih->wptr_cpu = &adev->wb.wb[wptr_offs]; ih->rptr_addr = adev->wb.gpu_addr + rptr_offs * 4; ih->rptr_cpu = &adev->wb.wb[rptr_offs]; + + #ifdef CONFIG_LOONGARCH + INIT_WORK(&adev->irq.ih.fix_work, amdgpu_ih_handle_fix_work); + for (r = 0; r < (adev->irq.ih.ring_size >> 2); r++) + adev->irq.ih.ring[r] = 0xDEADBEFF; + /* memory barrier for writing into ih ring */ + mb(); + #endif + } init_waitqueue_head(&ih->wait_process); @@ -120,6 +142,10 @@ void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) if (!ih->ring) return; +#ifdef CONFIG_LOONGARCH + cancel_work_sync(&adev->irq.ih.fix_work); +#endif + if (ih->use_bus_addr) { /* add 8 bytes for the rptr/wptr shadows and @@ -136,6 +162,113 @@ void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) } } +#ifdef CONFIG_LOONGARCH + +int amdgpu_ih_fix_is_busy(struct amdgpu_device *adev) +{ + return atomic_read(&adev->irq.cs_lock); +} + +static int amdgpu_ih_fix_loongarch_pcie_order_start(struct amdgpu_ih_ring *ih, + u32 rptr, u32 wptr, + bool forever) +{ + int i; + int check_cnt = 0; + u32 ring_end = ih->ring_size >> 2; + + if (rptr == wptr) + return 0; + + rptr = rptr >> 2; + wptr = wptr >> 2; + + wptr = (rptr > wptr) ? ring_end : wptr; + +restart_check: + if (!forever && ++check_cnt > 1) + return -ENAVAIL; + + if (forever) + msleep(20); + + for (i = rptr; i < wptr; i += 1) { + if (le32_to_cpu(ih->ring[i]) == 0xDEADBEFF) + goto restart_check; + } + + if (rptr > wptr) { + for (i = 0; i < wptr; i += 1) { + if (le32_to_cpu(ih->ring[i]) == 0xDEADBEFF) + goto restart_check; + } + } + + return 0; +} + +static int amdgpu_ih_fix_loongarch_pcie_order_end(struct amdgpu_ih_ring *ih, + u32 rptr, u32 wptr) +{ + int i; + u32 ring_end = ih->ring_size >> 2; + + if (rptr == wptr) + return 0; + + rptr = rptr >> 2; + wptr = wptr >> 2; + + wptr = (rptr > wptr) ? ring_end : wptr; + + for (i = rptr; i < wptr; i += 1) + ih->ring[i] = 0xDEADBEFF; + + if (rptr > wptr) { + for (i = 0; i < wptr; i += 1) + ih->ring[i] = 0xDEADBEFF; + } + /* memory barrier for writing into ih ring */ + mb(); + return 0; +} + +static void amdgpu_ih_handle_fix_work(struct work_struct *work) +{ + struct amdgpu_device *adev = + container_of(work, struct amdgpu_device, irq.ih.fix_work); + struct amdgpu_ih_ring *ih = &adev->irq.ih; + + u32 wptr; + u32 old_rptr; + +restart: + + wptr = amdgpu_ih_get_wptr(adev, ih); + /* Order reading of wptr vs. reading of IH ring data */ + rmb(); + + old_rptr = ih->rptr; + amdgpu_ih_fix_loongarch_pcie_order_start(&adev->irq.ih, old_rptr, wptr, true); + + while (adev->irq.ih.rptr != wptr) { + amdgpu_irq_dispatch(adev, ih); + ih->rptr &= ih->ptr_mask; + } + + amdgpu_ih_fix_loongarch_pcie_order_end(&adev->irq.ih, old_rptr, adev->irq.ih.rptr); + + amdgpu_ih_set_rptr(adev, ih); + /* memory barrier for setting rptr */ + mb(); + + if (ih->rptr != amdgpu_ih_get_wptr(adev, ih)) + goto restart; + + atomic_set(&adev->irq.cs_lock, 0); +} +#endif + /** * amdgpu_ih_ring_write - write IV to the ring buffer * @@ -210,6 +343,10 @@ int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) { unsigned int count; u32 wptr; +#ifdef CONFIG_LOONGARCH + u32 old_rptr; + int r; +#endif if (!ih->enabled || adev->shutdown) return IRQ_NONE; @@ -223,11 +360,28 @@ int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) /* Order reading of wptr vs. reading of IH ring data */ rmb(); +#ifdef CONFIG_LOONGARCH + old_rptr = adev->irq.ih.rptr; + r = amdgpu_ih_fix_loongarch_pcie_order_start(&adev->irq.ih, old_rptr, wptr, false); + if (r) { + if (old_rptr == ((wptr + 16) & adev->irq.ih.ptr_mask)) + return IRQ_NONE; + + atomic_xchg(&adev->irq.cs_lock, 1); + schedule_work(&adev->irq.ih.fix_work); + return IRQ_NONE; + } +#endif + while (ih->rptr != wptr && --count) { amdgpu_irq_dispatch(adev, ih); ih->rptr &= ih->ptr_mask; } +#ifdef CONFIG_LOONGARCH + amdgpu_ih_fix_loongarch_pcie_order_end(&adev->irq.ih, old_rptr, adev->irq.ih.rptr); +#endif + if (!ih->overflow) amdgpu_ih_set_rptr(adev, ih); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h index f58b6be7fccc0..2ad15a8ed29a3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h @@ -73,6 +73,9 @@ struct amdgpu_ih_ring { wait_queue_head_t wait_process; uint64_t processed_timestamp; bool overflow; +#ifdef CONFIG_LOONGARCH + struct work_struct fix_work; +#endif }; /* return true if time stamp t2 is after t1 with 48bit wrap around */ @@ -115,4 +118,7 @@ void amdgpu_ih_decode_iv_helper(struct amdgpu_device *adev, uint64_t amdgpu_ih_decode_iv_ts_helper(struct amdgpu_ih_ring *ih, u32 rptr, signed int offset); const char *amdgpu_ih_ring_name(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih); +#ifdef CONFIG_LOONGARCH +int amdgpu_ih_fix_is_busy(struct amdgpu_device *adev); +#endif #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c index 8112ffc85995e..2f06e7841461e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c @@ -276,6 +276,10 @@ int amdgpu_irq_init(struct amdgpu_device *adev) spin_lock_init(&adev->irq.lock); +#ifdef CONFIG_LOONGARCH + atomic_set(&adev->irq.cs_lock, 0); +#endif + /* Enable MSI if not disabled by module parameter */ adev->irq.msi_enabled = false; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h index 9f0417456abda..281c2d6852848 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h @@ -100,6 +100,9 @@ struct amdgpu_irq { uint32_t srbm_soft_reset; u32 retry_cam_doorbell_index; bool retry_cam_enabled; +#ifdef CONFIG_LOONGARCH + atomic_t cs_lock; +#endif }; enum interrupt_node_id_per_aid { From 20f9d9ca6dcef59132b77b6506b8cc36bd7865bd Mon Sep 17 00:00:00 2001 From: Binbin Zhou Date: Wed, 17 Sep 2025 17:34:25 +0800 Subject: [PATCH 07/13] drm/amdgpu: Fix RX550 pcie order dislocation. Signed-off-by: Tianrui Zhao Signed-off-by: Hongchen Zhang Signed-off-by: Binbin Zhou (cherry picked from commit 89494b3deddabeb1f5fb058eda1aeccc95caf196) Signed-off-by: Wentao Guan --- drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c index 5ab4beed7c127..dd0c5883e2a2e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c @@ -193,13 +193,13 @@ static int amdgpu_ih_fix_loongarch_pcie_order_start(struct amdgpu_ih_ring *ih, msleep(20); for (i = rptr; i < wptr; i += 1) { - if (le32_to_cpu(ih->ring[i]) == 0xDEADBEFF) + if (le32_to_cpu(ih->ring[i]) == 0xDEADBEFF && (i % 4) != 3) goto restart_check; } if (rptr > wptr) { for (i = 0; i < wptr; i += 1) { - if (le32_to_cpu(ih->ring[i]) == 0xDEADBEFF) + if (le32_to_cpu(ih->ring[i]) == 0xDEADBEFF && (i % 4) != 3) goto restart_check; } } @@ -364,7 +364,8 @@ int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) old_rptr = adev->irq.ih.rptr; r = amdgpu_ih_fix_loongarch_pcie_order_start(&adev->irq.ih, old_rptr, wptr, false); if (r) { - if (old_rptr == ((wptr + 16) & adev->irq.ih.ptr_mask)) + if (old_rptr == ((wptr + 16) & adev->irq.ih.ptr_mask) || + old_rptr == ((wptr + 32) & adev->irq.ih.ptr_mask)) return IRQ_NONE; atomic_xchg(&adev->irq.cs_lock, 1); From 82eaa05077ef2b4af1b9fc728464e96ef91c6d5c Mon Sep 17 00:00:00 2001 From: wuqianhai Date: Mon, 2 Mar 2026 12:07:10 +0800 Subject: [PATCH 08/13] drm/amdgpu: Fix kernel deadlock for missing code Add the missing code when migrating this patch from 4.19 which can cause kernel deadlock. Fixes: bcaf362d57b0 (drm/amdgpu: Fix pcie order dislocation) Signed-off-by: wuqianhai Signed-off-by: Binbin Zhou (cherry picked from commit 98acedf4a12d3ebe221dbbc1c2056515caf05c70) Signed-off-by: Wentao Guan Conflicts: drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c --- drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c | 84 +++++++++++++++----------- drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h | 2 + 2 files changed, 52 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c index dd0c5883e2a2e..f66b4cb67e16c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c @@ -77,13 +77,6 @@ int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih, ih->rptr_addr = dma_addr + ih->ring_size + 4; ih->rptr_cpu = &ih->ring[(ih->ring_size / 4) + 1]; - #ifdef CONFIG_LOONGARCH - INIT_WORK(&adev->irq.ih.fix_work, amdgpu_ih_handle_fix_work); - for (r = 0; r < (adev->irq.ih.ring_size >> 2); r++) - adev->irq.ih.ring[r] = 0xDEADBEFF; - /* memory barrier for writing into ih ring */ - mb(); - #endif } else { unsigned wptr_offs, rptr_offs; @@ -113,16 +106,17 @@ int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih, ih->rptr_addr = adev->wb.gpu_addr + rptr_offs * 4; ih->rptr_cpu = &adev->wb.wb[rptr_offs]; - #ifdef CONFIG_LOONGARCH - INIT_WORK(&adev->irq.ih.fix_work, amdgpu_ih_handle_fix_work); - for (r = 0; r < (adev->irq.ih.ring_size >> 2); r++) - adev->irq.ih.ring[r] = 0xDEADBEFF; - /* memory barrier for writing into ih ring */ - mb(); - #endif - } +#ifdef CONFIG_LOONGARCH + INIT_WORK(&ih->fix_work, amdgpu_ih_handle_fix_work); + ih->adev = adev; + atomic_set(&ih->lock, 0); + for (r = 0; r < (ih->ring_size >> 2); r++) + ih->ring[r] = 0xDEADBEFF; + /* ensure data active */ + mb(); +#endif init_waitqueue_head(&ih->wait_process); return 0; } @@ -143,7 +137,7 @@ void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) return; #ifdef CONFIG_LOONGARCH - cancel_work_sync(&adev->irq.ih.fix_work); + cancel_work_sync(&ih->fix_work); #endif if (ih->use_bus_addr) { @@ -173,7 +167,7 @@ static int amdgpu_ih_fix_loongarch_pcie_order_start(struct amdgpu_ih_ring *ih, u32 rptr, u32 wptr, bool forever) { - int i; + int i, j; int check_cnt = 0; u32 ring_end = ih->ring_size >> 2; @@ -193,13 +187,19 @@ static int amdgpu_ih_fix_loongarch_pcie_order_start(struct amdgpu_ih_ring *ih, msleep(20); for (i = rptr; i < wptr; i += 1) { - if (le32_to_cpu(ih->ring[i]) == 0xDEADBEFF && (i % 4) != 3) + j = i + 1; + j = (j < wptr) ? j : rptr; + if (le32_to_cpu(ih->ring[i]) == 0xDEADBEFF && + le32_to_cpu(ih->ring[j]) == 0xDEADBEFF) goto restart_check; } if (rptr > wptr) { for (i = 0; i < wptr; i += 1) { - if (le32_to_cpu(ih->ring[i]) == 0xDEADBEFF && (i % 4) != 3) + j = i + 1; + j = (j < wptr) ? j : 0; + if (le32_to_cpu(ih->ring[i]) == 0xDEADBEFF && + le32_to_cpu(ih->ring[j]) == 0xDEADBEFF) goto restart_check; } } @@ -235,35 +235,42 @@ static int amdgpu_ih_fix_loongarch_pcie_order_end(struct amdgpu_ih_ring *ih, static void amdgpu_ih_handle_fix_work(struct work_struct *work) { - struct amdgpu_device *adev = - container_of(work, struct amdgpu_device, irq.ih.fix_work); - struct amdgpu_ih_ring *ih = &adev->irq.ih; + struct amdgpu_ih_ring *ih = + container_of(work, struct amdgpu_ih_ring, fix_work); + struct amdgpu_device *adev = ih->adev; u32 wptr; u32 old_rptr; + int restart_fg = 0; restart: + if (restart_fg && atomic_xchg(&ih->lock, 1)) { + atomic_set(&adev->irq.cs_lock, 0); + return; + } wptr = amdgpu_ih_get_wptr(adev, ih); /* Order reading of wptr vs. reading of IH ring data */ rmb(); old_rptr = ih->rptr; - amdgpu_ih_fix_loongarch_pcie_order_start(&adev->irq.ih, old_rptr, wptr, true); + amdgpu_ih_fix_loongarch_pcie_order_start(ih, old_rptr, wptr, true); - while (adev->irq.ih.rptr != wptr) { + while (ih->rptr != wptr) { amdgpu_irq_dispatch(adev, ih); ih->rptr &= ih->ptr_mask; } - amdgpu_ih_fix_loongarch_pcie_order_end(&adev->irq.ih, old_rptr, adev->irq.ih.rptr); + amdgpu_ih_fix_loongarch_pcie_order_end(ih, old_rptr, ih->rptr); amdgpu_ih_set_rptr(adev, ih); - /* memory barrier for setting rptr */ + atomic_set(&ih->lock, 0); mb(); - if (ih->rptr != amdgpu_ih_get_wptr(adev, ih)) + if (ih->rptr != amdgpu_ih_get_wptr(adev, ih)) { + restart_fg = 1; goto restart; + } atomic_set(&adev->irq.cs_lock, 0); } @@ -354,6 +361,11 @@ int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) wptr = amdgpu_ih_get_wptr(adev, ih); restart_ih: +#ifdef CONFIG_LOONGARCH + /* is somebody else already processing irqs? */ + if (atomic_xchg(&ih->lock, 1)) + return IRQ_NONE; +#endif count = AMDGPU_IH_MAX_NUM_IVS; dev_dbg(adev->dev, "%s: rptr %d, wptr %d\n", __func__, ih->rptr, wptr); @@ -361,15 +373,16 @@ int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) rmb(); #ifdef CONFIG_LOONGARCH - old_rptr = adev->irq.ih.rptr; - r = amdgpu_ih_fix_loongarch_pcie_order_start(&adev->irq.ih, old_rptr, wptr, false); + old_rptr = ih->rptr; + r = amdgpu_ih_fix_loongarch_pcie_order_start(ih, old_rptr, wptr, false); if (r) { - if (old_rptr == ((wptr + 16) & adev->irq.ih.ptr_mask) || - old_rptr == ((wptr + 32) & adev->irq.ih.ptr_mask)) + if (old_rptr == ((wptr + 16) & ih->ptr_mask) || + old_rptr == ((wptr + 32) & ih->ptr_mask)) { + atomic_set(&ih->lock, 0); return IRQ_NONE; - + } atomic_xchg(&adev->irq.cs_lock, 1); - schedule_work(&adev->irq.ih.fix_work); + schedule_work(&ih->fix_work); return IRQ_NONE; } #endif @@ -380,12 +393,15 @@ int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) } #ifdef CONFIG_LOONGARCH - amdgpu_ih_fix_loongarch_pcie_order_end(&adev->irq.ih, old_rptr, adev->irq.ih.rptr); + amdgpu_ih_fix_loongarch_pcie_order_end(ih, old_rptr, ih->rptr); #endif if (!ih->overflow) amdgpu_ih_set_rptr(adev, ih); +#ifdef CONFIG_LOONGARCH + atomic_set(&ih->lock, 0); +#endif wake_up_all(&ih->wait_process); /* make sure wptr hasn't changed while processing */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h index 2ad15a8ed29a3..888eba233cad9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h @@ -74,7 +74,9 @@ struct amdgpu_ih_ring { uint64_t processed_timestamp; bool overflow; #ifdef CONFIG_LOONGARCH + atomic_t lock; struct work_struct fix_work; + struct amdgpu_device *adev; #endif }; From 52a187a56951054254cf038d095d81c4ada8ed6a Mon Sep 17 00:00:00 2001 From: Binbin Zhou Date: Mon, 2 Mar 2026 12:07:10 +0800 Subject: [PATCH 09/13] drm/amdgpu: Fix wptr/rptr error in ih_fix_loongarch_pcie_order() Fix the pointer error of wptr/rptr in ih_fix_loongarch_pcie_order(). Fixes: bcaf362d57b0 (drm/amdgpu: Fix pcie order dislocation) Signed-off-by: zhaotianrui Signed-off-by: Binbin Zhou (cherry picked from commit c41045a0709af3b92dc89b6f845d281d607ba30d) Signed-off-by: Wentao Guan --- drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c index f66b4cb67e16c..6c25eb6f42855 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c @@ -169,14 +169,14 @@ static int amdgpu_ih_fix_loongarch_pcie_order_start(struct amdgpu_ih_ring *ih, { int i, j; int check_cnt = 0; - u32 ring_end = ih->ring_size >> 2; + u32 old_wptr, ring_end = ih->ring_size >> 2; if (rptr == wptr) return 0; rptr = rptr >> 2; wptr = wptr >> 2; - + old_wptr = wptr; wptr = (rptr > wptr) ? ring_end : wptr; restart_check: @@ -194,10 +194,10 @@ static int amdgpu_ih_fix_loongarch_pcie_order_start(struct amdgpu_ih_ring *ih, goto restart_check; } - if (rptr > wptr) { - for (i = 0; i < wptr; i += 1) { + if (rptr > old_wptr) { + for (i = 0; i < old_wptr; i += 1) { j = i + 1; - j = (j < wptr) ? j : 0; + j = (j < old_wptr) ? j : 0; if (le32_to_cpu(ih->ring[i]) == 0xDEADBEFF && le32_to_cpu(ih->ring[j]) == 0xDEADBEFF) goto restart_check; @@ -211,21 +211,21 @@ static int amdgpu_ih_fix_loongarch_pcie_order_end(struct amdgpu_ih_ring *ih, u32 rptr, u32 wptr) { int i; - u32 ring_end = ih->ring_size >> 2; + u32 old_wptr, ring_end = ih->ring_size >> 2; if (rptr == wptr) return 0; rptr = rptr >> 2; wptr = wptr >> 2; - + old_wptr = wptr; wptr = (rptr > wptr) ? ring_end : wptr; for (i = rptr; i < wptr; i += 1) ih->ring[i] = 0xDEADBEFF; - if (rptr > wptr) { - for (i = 0; i < wptr; i += 1) + if (rptr > old_wptr) { + for (i = 0; i < old_wptr; i += 1) ih->ring[i] = 0xDEADBEFF; } /* memory barrier for writing into ih ring */ From 52d5f03120ae07df1591039da96da847a7997952 Mon Sep 17 00:00:00 2001 From: Binbin Zhou Date: Mon, 2 Mar 2026 12:07:11 +0800 Subject: [PATCH 10/13] drm/amdgpu: Make eleven EOP packet for GFX10_0/GFX11_0 have real content The duplication of EOP packets for GFX10_0/GFX11_0, with the former one have seq written and the latter one have seq written, seems to confuse some hardware platform (e.g. Loongson 7A series PCIe controllers). Signed-off-by: wuqianhai Signed-off-by: Binbin Zhou [Conflict for drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c because of commit cb17fff3a254 ("drm/amdgpu/mes: remove unused functions") upstreamed] (cherry picked from commit df704acbdb1605947e64881dc193254d3157d15d) Signed-off-by: Wentao Guan Conflicts: drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 46 ++++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 48 ++++++++++++++++++++++++++ 2 files changed, 94 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 003bcece715eb..255a5c964f736 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -4672,8 +4672,13 @@ static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; hw_prio = amdgpu_gfx_is_high_priority_graphics_queue(adev, ring) ? AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; +#ifdef CONFIG_LOONGARCH + return amdgpu_ring_init(adev, ring, 1024*2, &adev->gfx.eop_irq, irq_type, + hw_prio, NULL); +#else return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, hw_prio, NULL); +#endif } static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, @@ -4704,8 +4709,13 @@ static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? AMDGPU_RING_PRIO_2 : AMDGPU_RING_PRIO_DEFAULT; /* type-2 packets are deprecated on MEC, use type-3 instead */ +#ifdef CONFIG_LOONGARCH + return amdgpu_ring_init(adev, ring, 1024*2, &adev->gfx.eop_irq, irq_type, + hw_prio, NULL); +#else return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, hw_prio, NULL); +#endif } static void gfx_v10_0_alloc_ip_dump(struct amdgpu_device *adev) @@ -8715,7 +8725,31 @@ static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, { bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; +#ifdef CONFIG_LOONGARCH + int i; + for (i = 0; i < 10; i++) { + /* RELEASE_MEM - flush caches, send int */ + amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); + amdgpu_ring_write( + ring, + (PACKET3_RELEASE_MEM_GCR_SEQ | + PACKET3_RELEASE_MEM_GCR_GL2_WB | + PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */ + PACKET3_RELEASE_MEM_GCR_GLM_WB | + PACKET3_RELEASE_MEM_CACHE_POLICY(3) | + PACKET3_RELEASE_MEM_EVENT_TYPE( + CACHE_FLUSH_AND_INV_TS_EVENT) | + PACKET3_RELEASE_MEM_EVENT_INDEX(5))); + amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL( + write64bit ? 2 : 1) | + PACKET3_RELEASE_MEM_INT_SEL(0))); + amdgpu_ring_write(ring, lower_32_bits(addr)); + amdgpu_ring_write(ring, upper_32_bits(addr)); + amdgpu_ring_write(ring, lower_32_bits(seq)); + amdgpu_ring_write(ring, upper_32_bits(seq)); + } +#endif /* RELEASE_MEM - flush caches, send int */ amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | @@ -9842,7 +9876,11 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = { SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4 + /* VM_FLUSH */ +#ifdef CONFIG_LOONGARCH + 8*11 + /* FENCE for VM_FLUSH */ +#else 8 + /* FENCE for VM_FLUSH */ +#endif 20 + /* GDS switch */ 4 + /* double SWITCH_BUFFER, * the first COND_EXEC jump to the place @@ -9855,7 +9893,11 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = { 31 + /* DE_META */ 3 + /* CNTX_CTRL */ 5 + /* HDP_INVL */ +#ifdef CONFIG_LOONGARCH + 8*11 + 8*11 + /* FENCE x2 */ +#else 8 + 8 + /* FENCE x2 */ +#endif 2 + /* SWITCH_BUFFER */ 8 + /* gfx_v10_0_emit_mem_sync */ 2, /* gfx_v10_0_ring_emit_cleaner_shader */ @@ -9901,7 +9943,11 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = { SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 2 + /* gfx_v10_0_ring_emit_vm_flush */ +#ifdef CONFIG_LOONGARCH + 8*11 + 8*11 + 8*11 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */ +#else 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */ +#endif 8 + /* gfx_v10_0_emit_mem_sync */ 2, /* gfx_v10_0_ring_emit_cleaner_shader */ .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index 1dd9fd486eecf..b4d9e0539e22c 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -1151,8 +1151,13 @@ static int gfx_v11_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; hw_prio = amdgpu_gfx_is_high_priority_graphics_queue(adev, ring) ? AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; +#ifdef CONFIG_LOONGARCH + return amdgpu_ring_init(adev, ring, 1024*2, &adev->gfx.eop_irq, irq_type, + hw_prio, NULL); +#else return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, hw_prio, NULL); +#endif } static int gfx_v11_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, @@ -1184,8 +1189,13 @@ static int gfx_v11_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; /* type-2 packets are deprecated on MEC, use type-3 instead */ +#ifdef CONFIG_LOONGARCH + r = amdgpu_ring_init(adev, ring, 1024*2, &adev->gfx.eop_irq, irq_type, + hw_prio, NULL); +#else r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, hw_prio, NULL); +#endif if (r) return r; @@ -5930,7 +5940,33 @@ static void gfx_v11_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, { bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; +#ifdef CONFIG_LOONGARCH + int i; + for (i = 0; i < 10; i++) { + /* RELEASE_MEM - flush caches, send int */ + amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); + amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | + PACKET3_RELEASE_MEM_GCR_GL2_WB | + PACKET3_RELEASE_MEM_GCR_GL2_INV | + PACKET3_RELEASE_MEM_GCR_GL2_US | + PACKET3_RELEASE_MEM_GCR_GL1_INV | + PACKET3_RELEASE_MEM_GCR_GLV_INV | + PACKET3_RELEASE_MEM_GCR_GLM_INV | + PACKET3_RELEASE_MEM_GCR_GLM_WB | + PACKET3_RELEASE_MEM_CACHE_POLICY(3) | + PACKET3_RELEASE_MEM_EVENT_TYPE( + CACHE_FLUSH_AND_INV_TS_EVENT) | + PACKET3_RELEASE_MEM_EVENT_INDEX(5))); + amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL( + write64bit ? 2 : 1) | + PACKET3_RELEASE_MEM_INT_SEL(0))); + amdgpu_ring_write(ring, lower_32_bits(addr)); + amdgpu_ring_write(ring, upper_32_bits(addr)); + amdgpu_ring_write(ring, lower_32_bits(seq)); + amdgpu_ring_write(ring, upper_32_bits(seq)); + } +#endif /* RELEASE_MEM - flush caches, send int */ amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | @@ -7217,7 +7253,11 @@ static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_gfx = { SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4 + /* VM_FLUSH */ +#ifdef CONFIG_LOONGARCH + 8*11 + /* FENCE for VM_FLUSH */ +#else 8 + /* FENCE for VM_FLUSH */ +#endif 20 + /* GDS switch */ 5 + /* COND_EXEC */ 7 + /* HDP_flush */ @@ -7226,7 +7266,11 @@ static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_gfx = { 3 + /* CNTX_CTRL */ 5 + /* HDP_INVL */ 22 + /* SET_Q_PREEMPTION_MODE */ +#ifdef CONFIG_LOONGARCH + 8*11 + 8*11 + /* FENCE x2 */ +#else 8 + 8 + /* FENCE x2 */ +#endif 8 + /* gfx_v11_0_emit_mem_sync */ 2, /* gfx_v11_0_ring_emit_cleaner_shader */ .emit_ib_size = 4, /* gfx_v11_0_ring_emit_ib_gfx */ @@ -7272,7 +7316,11 @@ static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_compute = { SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 2 + /* gfx_v11_0_ring_emit_vm_flush */ +#ifdef CONFIG_LOONGARCH + 8*11 + 8*11 + 8*11 + /* gfx_v11_0_ring_emit_fence x3 for user fence, vm fence */ +#else 8 + 8 + 8 + /* gfx_v11_0_ring_emit_fence x3 for user fence, vm fence */ +#endif 8 + /* gfx_v11_0_emit_mem_sync */ 2, /* gfx_v11_0_ring_emit_cleaner_shader */ .emit_ib_size = 7, /* gfx_v11_0_ring_emit_ib_compute */ From 2cb9e68b38539d3aab9641a9877c7255c64568f0 Mon Sep 17 00:00:00 2001 From: Binbin Zhou Date: Mon, 2 Mar 2026 12:07:11 +0800 Subject: [PATCH 11/13] LoongArch: configs: Disable CONFIG_LEGACY_PTYS to fix gnulib test failures The legacy PTY driver (CONFIG_LEGACY_PTYS) is deprecated and not required for most modern systems. It causes unexpected behavior during gnulib tests, leading to test failures related to pseudo-terminal handling. Disabling CONFIG_LEGACY_PTYS removes the old /dev/pty* and /dev/tty* interfaces, allowing gnulib tests to run successfully with the modern /dev/pts/* subsystem. Signed-off-by: yangxiaojuan Signed-off-by: Binbin Zhou (cherry picked from commit 026f0201abb3806fac45bfe9b2025431cedab975) Signed-off-by: Wentao Guan Conflicts: arch/loongarch/configs/loongson3_defconfig --- arch/loongarch/configs/deepin_loongarch_desktop_defconfig | 1 + arch/loongarch/configs/loongson3_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/loongarch/configs/deepin_loongarch_desktop_defconfig b/arch/loongarch/configs/deepin_loongarch_desktop_defconfig index 09bb412dbe78f..f269e38b635a4 100644 --- a/arch/loongarch/configs/deepin_loongarch_desktop_defconfig +++ b/arch/loongarch/configs/deepin_loongarch_desktop_defconfig @@ -5839,3 +5839,4 @@ CONFIG_RV=y CONFIG_RV_MON_WWNR=y # CONFIG_STRICT_DEVMEM is not set # CONFIG_RUNTIME_TESTING_MENU is not set +# CONFIG_LEGACY_PTYS is not set diff --git a/arch/loongarch/configs/loongson3_defconfig b/arch/loongarch/configs/loongson3_defconfig index da33b7bcb6400..f726f10e79c1a 100644 --- a/arch/loongarch/configs/loongson3_defconfig +++ b/arch/loongarch/configs/loongson3_defconfig @@ -1153,3 +1153,4 @@ CONFIG_SCHEDSTATS=y # CONFIG_DEBUG_PREEMPT is not set # CONFIG_FTRACE is not set CONFIG_UNWINDER_ORC=y +# CONFIG_LEGACY_PTYS is not set From 15aab63d10ccd331f6b15787bd5fea712f7863bb Mon Sep 17 00:00:00 2001 From: Binbin Zhou Date: Mon, 2 Mar 2026 12:07:12 +0800 Subject: [PATCH 12/13] LoongArch: configs: Enable UMP related configs to solve do_page_fault Like this: [ 130.469445] [ T759] do_page_fault(): sending SIGSEGV to pipewire for invalid read access from 000055560db01c91 [ 130.479455] [ T759] era = 00007fffeea0406c in libasound.so.2.0.0[7fffee940000+11c000] [ 130.487283] [ T759] ra = 00007fffeeafe990 in libspa-alsa.so[7fffeea80000+104000] [ 130.669705] [ T967] do_page_fault(): sending SIGSEGV to pipewire for invalid read access from 00005555619e4000 [ 130.679771] [ T967] era = 00007fffee88e9ac in libspa-alsa.so[7fffee810000+104000] [ 130.687229] [ T967] ra = 00007fffee88e9a0 in libspa-alsa.so[7fffee810000+104000] Signed-off-by: yangxiaojuan Signed-off-by: Binbin Zhou (cherry picked from commit f1cc6c0f5278d911d65331970a7125a899756f3b) Signed-off-by: Wentao Guan Conflicts: arch/loongarch/configs/loongson3_defconfig --- arch/loongarch/configs/deepin_loongarch_desktop_defconfig | 3 +++ arch/loongarch/configs/loongson3_defconfig | 5 ++++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/loongarch/configs/deepin_loongarch_desktop_defconfig b/arch/loongarch/configs/deepin_loongarch_desktop_defconfig index f269e38b635a4..06ba3a1c1d622 100644 --- a/arch/loongarch/configs/deepin_loongarch_desktop_defconfig +++ b/arch/loongarch/configs/deepin_loongarch_desktop_defconfig @@ -3682,6 +3682,7 @@ CONFIG_LOGO=y CONFIG_DRM_ACCEL=y CONFIG_SOUND=m CONFIG_SND=m +CONFIG_SND_UMP=m CONFIG_SND_OSSEMUL=y CONFIG_SND_MIXER_OSS=m CONFIG_SND_PCM_OSS=m @@ -3690,6 +3691,8 @@ CONFIG_SND_CTL_INPUT_VALIDATION=y CONFIG_SND_SEQUENCER=m CONFIG_SND_SEQ_DUMMY=m CONFIG_SND_SEQUENCER_OSS=m +CONFIG_SND_SEQ_UMP=y +CONFIG_SND_SEQ_UMP_CLIENT=m CONFIG_SND_DUMMY=m CONFIG_SND_ALOOP=m CONFIG_SND_VIRMIDI=m diff --git a/arch/loongarch/configs/loongson3_defconfig b/arch/loongarch/configs/loongson3_defconfig index f726f10e79c1a..40fceabbd136c 100644 --- a/arch/loongarch/configs/loongson3_defconfig +++ b/arch/loongarch/configs/loongson3_defconfig @@ -833,8 +833,11 @@ CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y CONFIG_LOGO=y CONFIG_SOUND=y CONFIG_SND=y +CONFIG_SND_UMP=m CONFIG_SND_SEQUENCER=m CONFIG_SND_SEQ_DUMMY=m +CONFIG_SND_SEQ_UMP=y +CONFIG_SND_SEQ_UMP_CLIENT=m CONFIG_SND_BT87X=m CONFIG_SND_BT87X_OVERCLOCK=y CONFIG_SND_HDA_INTEL=y @@ -861,7 +864,7 @@ CONFIG_SND_HDA_CODEC_HDMI_ATI=y CONFIG_SND_HDA_CODEC_HDMI_NVIDIA=y CONFIG_SND_HDA_CODEC_CONEXANT=y CONFIG_SND_USB_AUDIO=m -CONFIG_SND_USB_AUDIO_MIDI_V2=y +CONFIG_SND_USB_AUDIO_MIDI_V2=m CONFIG_SND_SOC=m CONFIG_SND_SOC_LOONGSON_CARD=m CONFIG_SND_SOC_ES7134=m From 88a138e9215b954910efd1d7bdcb5903842d0f4f Mon Sep 17 00:00:00 2001 From: Wentao Guan Date: Tue, 17 Mar 2026 14:07:24 +0800 Subject: [PATCH 13/13] drm/amdgpu: use CONFIG_MACH_LOONGSON64 deepin inclusion category: feature Reported-by: WangYuli Signed-off-by: Wentao Guan --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c | 18 +++++++++--------- drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h | 2 +- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 12 ++++++------ drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 12 ++++++------ drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 2 +- drivers/gpu/drm/radeon/cik.c | 4 ++-- drivers/gpu/drm/radeon/evergreen.c | 2 +- drivers/gpu/drm/radeon/r600.c | 2 +- drivers/gpu/drm/radeon/si.c | 2 +- 14 files changed, 36 insertions(+), 36 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index fe43c5ddf0364..e3f997843ae23 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -1289,7 +1289,7 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, uint64_t seq; int r; -#ifdef CONFIG_LOONGARCH +#ifdef CONFIG_MACH_LOONGSON64 while (amdgpu_ih_fix_is_busy(p->adev)) msleep(20); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c index 6c25eb6f42855..69838e6489715 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c @@ -27,7 +27,7 @@ #include "amdgpu_ih.h" #include "amdgpu_reset.h" -#ifdef CONFIG_LOONGARCH +#ifdef CONFIG_MACH_LOONGSON64 static void amdgpu_ih_handle_fix_work(struct work_struct *work); #endif @@ -108,7 +108,7 @@ int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih, } -#ifdef CONFIG_LOONGARCH +#ifdef CONFIG_MACH_LOONGSON64 INIT_WORK(&ih->fix_work, amdgpu_ih_handle_fix_work); ih->adev = adev; atomic_set(&ih->lock, 0); @@ -136,7 +136,7 @@ void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) if (!ih->ring) return; -#ifdef CONFIG_LOONGARCH +#ifdef CONFIG_MACH_LOONGSON64 cancel_work_sync(&ih->fix_work); #endif @@ -156,7 +156,7 @@ void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) } } -#ifdef CONFIG_LOONGARCH +#ifdef CONFIG_MACH_LOONGSON64 int amdgpu_ih_fix_is_busy(struct amdgpu_device *adev) { @@ -350,7 +350,7 @@ int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) { unsigned int count; u32 wptr; -#ifdef CONFIG_LOONGARCH +#ifdef CONFIG_MACH_LOONGSON64 u32 old_rptr; int r; #endif @@ -361,7 +361,7 @@ int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) wptr = amdgpu_ih_get_wptr(adev, ih); restart_ih: -#ifdef CONFIG_LOONGARCH +#ifdef CONFIG_MACH_LOONGSON64 /* is somebody else already processing irqs? */ if (atomic_xchg(&ih->lock, 1)) return IRQ_NONE; @@ -372,7 +372,7 @@ int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) /* Order reading of wptr vs. reading of IH ring data */ rmb(); -#ifdef CONFIG_LOONGARCH +#ifdef CONFIG_MACH_LOONGSON64 old_rptr = ih->rptr; r = amdgpu_ih_fix_loongarch_pcie_order_start(ih, old_rptr, wptr, false); if (r) { @@ -392,14 +392,14 @@ int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) ih->rptr &= ih->ptr_mask; } -#ifdef CONFIG_LOONGARCH +#ifdef CONFIG_MACH_LOONGSON64 amdgpu_ih_fix_loongarch_pcie_order_end(ih, old_rptr, ih->rptr); #endif if (!ih->overflow) amdgpu_ih_set_rptr(adev, ih); -#ifdef CONFIG_LOONGARCH +#ifdef CONFIG_MACH_LOONGSON64 atomic_set(&ih->lock, 0); #endif wake_up_all(&ih->wait_process); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h index 888eba233cad9..861a24101c373 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h @@ -73,7 +73,7 @@ struct amdgpu_ih_ring { wait_queue_head_t wait_process; uint64_t processed_timestamp; bool overflow; -#ifdef CONFIG_LOONGARCH +#ifdef CONFIG_MACH_LOONGSON64 atomic_t lock; struct work_struct fix_work; struct amdgpu_device *adev; @@ -120,7 +120,7 @@ void amdgpu_ih_decode_iv_helper(struct amdgpu_device *adev, uint64_t amdgpu_ih_decode_iv_ts_helper(struct amdgpu_ih_ring *ih, u32 rptr, signed int offset); const char *amdgpu_ih_ring_name(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih); -#ifdef CONFIG_LOONGARCH +#ifdef CONFIG_MACH_LOONGSON64 int amdgpu_ih_fix_is_busy(struct amdgpu_device *adev); #endif #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c index 2f06e7841461e..a2e45fdfe527d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c @@ -276,7 +276,7 @@ int amdgpu_irq_init(struct amdgpu_device *adev) spin_lock_init(&adev->irq.lock); -#ifdef CONFIG_LOONGARCH +#ifdef CONFIG_MACH_LOONGSON64 atomic_set(&adev->irq.cs_lock, 0); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h index 281c2d6852848..44f99a099bed0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h @@ -100,7 +100,7 @@ struct amdgpu_irq { uint32_t srbm_soft_reset; u32 retry_cam_doorbell_index; bool retry_cam_enabled; -#ifdef CONFIG_LOONGARCH +#ifdef CONFIG_MACH_LOONGSON64 atomic_t cs_lock; #endif }; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 255a5c964f736..d28c8e12fbce7 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -4672,7 +4672,7 @@ static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; hw_prio = amdgpu_gfx_is_high_priority_graphics_queue(adev, ring) ? AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; -#ifdef CONFIG_LOONGARCH +#ifdef CONFIG_MACH_LOONGSON64 return amdgpu_ring_init(adev, ring, 1024*2, &adev->gfx.eop_irq, irq_type, hw_prio, NULL); #else @@ -4709,7 +4709,7 @@ static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? AMDGPU_RING_PRIO_2 : AMDGPU_RING_PRIO_DEFAULT; /* type-2 packets are deprecated on MEC, use type-3 instead */ -#ifdef CONFIG_LOONGARCH +#ifdef CONFIG_MACH_LOONGSON64 return amdgpu_ring_init(adev, ring, 1024*2, &adev->gfx.eop_irq, irq_type, hw_prio, NULL); #else @@ -8725,7 +8725,7 @@ static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, { bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; -#ifdef CONFIG_LOONGARCH +#ifdef CONFIG_MACH_LOONGSON64 int i; for (i = 0; i < 10; i++) { @@ -9876,7 +9876,7 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = { SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4 + /* VM_FLUSH */ -#ifdef CONFIG_LOONGARCH +#ifdef CONFIG_MACH_LOONGSON64 8*11 + /* FENCE for VM_FLUSH */ #else 8 + /* FENCE for VM_FLUSH */ @@ -9893,7 +9893,7 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = { 31 + /* DE_META */ 3 + /* CNTX_CTRL */ 5 + /* HDP_INVL */ -#ifdef CONFIG_LOONGARCH +#ifdef CONFIG_MACH_LOONGSON64 8*11 + 8*11 + /* FENCE x2 */ #else 8 + 8 + /* FENCE x2 */ @@ -9943,7 +9943,7 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = { SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 2 + /* gfx_v10_0_ring_emit_vm_flush */ -#ifdef CONFIG_LOONGARCH +#ifdef CONFIG_MACH_LOONGSON64 8*11 + 8*11 + 8*11 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */ #else 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */ diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index b4d9e0539e22c..8ddefbe4554d6 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -1151,7 +1151,7 @@ static int gfx_v11_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; hw_prio = amdgpu_gfx_is_high_priority_graphics_queue(adev, ring) ? AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; -#ifdef CONFIG_LOONGARCH +#ifdef CONFIG_MACH_LOONGSON64 return amdgpu_ring_init(adev, ring, 1024*2, &adev->gfx.eop_irq, irq_type, hw_prio, NULL); #else @@ -1189,7 +1189,7 @@ static int gfx_v11_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; /* type-2 packets are deprecated on MEC, use type-3 instead */ -#ifdef CONFIG_LOONGARCH +#ifdef CONFIG_MACH_LOONGSON64 r = amdgpu_ring_init(adev, ring, 1024*2, &adev->gfx.eop_irq, irq_type, hw_prio, NULL); #else @@ -5940,7 +5940,7 @@ static void gfx_v11_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, { bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; -#ifdef CONFIG_LOONGARCH +#ifdef CONFIG_MACH_LOONGSON64 int i; for (i = 0; i < 10; i++) { @@ -7253,7 +7253,7 @@ static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_gfx = { SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4 + /* VM_FLUSH */ -#ifdef CONFIG_LOONGARCH +#ifdef CONFIG_MACH_LOONGSON64 8*11 + /* FENCE for VM_FLUSH */ #else 8 + /* FENCE for VM_FLUSH */ @@ -7266,7 +7266,7 @@ static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_gfx = { 3 + /* CNTX_CTRL */ 5 + /* HDP_INVL */ 22 + /* SET_Q_PREEMPTION_MODE */ -#ifdef CONFIG_LOONGARCH +#ifdef CONFIG_MACH_LOONGSON64 8*11 + 8*11 + /* FENCE x2 */ #else 8 + 8 + /* FENCE x2 */ @@ -7316,7 +7316,7 @@ static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_compute = { SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 2 + /* gfx_v11_0_ring_emit_vm_flush */ -#ifdef CONFIG_LOONGARCH +#ifdef CONFIG_MACH_LOONGSON64 8*11 + 8*11 + 8*11 + /* gfx_v11_0_ring_emit_fence x3 for user fence, vm fence */ #else 8 + 8 + 8 + /* gfx_v11_0_ring_emit_fence x3 for user fence, vm fence */ diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c index 075968bebc944..fe2eef0f95539 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c @@ -1839,7 +1839,7 @@ static void gfx_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, amdgpu_ring_write(ring, 0xFFFFFFFF); amdgpu_ring_write(ring, 0); amdgpu_ring_write(ring, 10); /* poll interval */ -#ifdef CONFIG_LOONGARCH +#ifdef CONFIG_MACH_LOONGSON64 /* EVENT_WRITE_EOP - flush caches, no send int */ amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); amdgpu_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5)); @@ -3471,7 +3471,7 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = { .set_wptr = gfx_v6_0_ring_set_wptr_gfx, .emit_frame_size = 5 + 5 + /* hdp flush / invalidate */ -#ifdef CONFIG_LOONGARCH +#ifdef CONFIG_MACH_LOONGSON64 20 + 20 + 20 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */ #else 14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */ @@ -3504,7 +3504,7 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = { 5 + 5 + /* hdp flush / invalidate */ 7 + /* gfx_v6_0_ring_emit_pipeline_sync */ SI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v6_0_ring_emit_vm_flush */ -#ifdef CONFIG_LOONGARCH +#ifdef CONFIG_MACH_LOONGSON64 20 + 20 + 20 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */ #else 14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */ diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index 6135a6d81a7d4..dc6f965ff5305 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -2135,7 +2135,7 @@ static void gfx_v7_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr, EVENT_INDEX(5))); amdgpu_ring_write(ring, addr & 0xfffffffc); amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | -#ifdef CONFIG_LOONGARCH +#ifdef CONFIG_MACH_LOONGSON64 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(0)); amdgpu_ring_write(ring, lower_32_bits(seq)); amdgpu_ring_write(ring, upper_32_bits(seq)); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 70025c2f27c3d..98b4e7bf9f96a 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -6124,7 +6124,7 @@ static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr, EVENT_INDEX(5))); amdgpu_ring_write(ring, addr & 0xfffffffc); amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | -#ifdef CONFIG_LOONGARCH +#ifdef CONFIG_MACH_LOONGSON64 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(0)); amdgpu_ring_write(ring, lower_32_bits(seq)); amdgpu_ring_write(ring, upper_32_bits(seq)); diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c index 77e0c0be7aad1..909d51fdae016 100644 --- a/drivers/gpu/drm/radeon/cik.c +++ b/drivers/gpu/drm/radeon/cik.c @@ -3554,7 +3554,7 @@ void cik_fence_gfx_ring_emit(struct radeon_device *rdev, radeon_ring_write(ring, addr & 0xfffffffc); radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | DATA_SEL(1) | INT_SEL(0)); -#ifdef CONFIG_LOONGARCH +#ifdef CONFIG_MACH_LOONGSON64 radeon_ring_write(ring, fence->seq); #else radeon_ring_write(ring, fence->seq - 1); @@ -8097,7 +8097,7 @@ int cik_irq_process(struct radeon_device *rdev) if (queue_thermal) schedule_work(&rdev->pm.dpm.thermal.work); rdev->ih.rptr = rptr; -#ifdef CONFIG_LOONGARCH +#ifdef CONFIG_MACH_LOONGSON64 WREG32(IH_RB_RPTR, rptr); #endif atomic_set(&rdev->ih.lock, 0); diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index a0b3e6268e6be..b08b0ad796f36 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c @@ -4919,7 +4919,7 @@ int evergreen_irq_process(struct radeon_device *rdev) if (queue_thermal && rdev->pm.dpm_enabled) schedule_work(&rdev->pm.dpm.thermal.work); rdev->ih.rptr = rptr; -#ifdef CONFIG_LOONGARCH +#ifdef CONFIG_MACH_LOONGSON64 WREG32(IH_RB_RPTR, rptr); #endif atomic_set(&rdev->ih.lock, 0); diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index df075e025801c..7d17c70de343b 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c @@ -4328,7 +4328,7 @@ int r600_irq_process(struct radeon_device *rdev) if (queue_thermal && rdev->pm.dpm_enabled) schedule_work(&rdev->pm.dpm.thermal.work); rdev->ih.rptr = rptr; -#ifdef CONFIG_LOONGARCH +#ifdef CONFIG_MACH_LOONGSON64 WREG32(IH_RB_RPTR, rptr); #endif atomic_set(&rdev->ih.lock, 0); diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c index 479d12ed82dee..d086ee64dc0ff 100644 --- a/drivers/gpu/drm/radeon/si.c +++ b/drivers/gpu/drm/radeon/si.c @@ -6423,7 +6423,7 @@ int si_irq_process(struct radeon_device *rdev) if (queue_thermal && rdev->pm.dpm_enabled) schedule_work(&rdev->pm.dpm.thermal.work); rdev->ih.rptr = rptr; -#ifdef CONFIG_LOONGARCH +#ifdef CONFIG_MACH_LOONGSON64 WREG32(IH_RB_RPTR, rptr); #endif atomic_set(&rdev->ih.lock, 0);