irq: phytium: update phytium irq controller driver support to 6.6.0.4#1708
irq: phytium: update phytium irq controller driver support to 6.6.0.4#1708wangchenlu2236 wants to merge 3 commits into
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There are two hacks needed for IOMMU enablement on Phytium Ps17064 SoC. One is the MSI hack, the other is the SMMU hack. When using this enablement, we assumes that users would set CONIFIG_IOMMU_DEFAULT_PASSTHROUGH=y or pass 'iommu.passthrough=on' or 'iommu.pt' as the kernel command-line parameters. Therefore, we also force default iommu domain type to IOMMU_DOMAIN_IDENTITY on Ps17064 to avoid unnecessary troubles. Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn> Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn> Signed-off-by: Wang Chenlu <wangchenlu2236@phytium.com.cn>
When compiling with the aarch32 compiler, the arm64-specific macros were not defined. Add restriction to bring these macros only into effect on arm64 architecture. Mainline: NA Signed-off-by: Li Mingzhe <limingzhe1839@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn> Signed-off-by: Wang Chenlu <wangchenlu2236@phytium.com.cn>
Fix the logic in its_irq_compose_msi() where CONFIG_ARCH_PHYTIUM filtering accidentally changed the original behavior. Now iommu_dma_compose_msi_msg() is skipped only on PS17064 SoCs, and executed on all other platforms as intended. Mainline: NA Signed-off-by: Li Mingzhe <limingzhe1839@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn> Signed-off-by: Wang Chenlu <wangchenlu2236@phytium.com.cn>
Reviewer's GuideUpdates Phytium PS17064-specific handling in the IOMMU core, ARM SMMU driver, and GICv3 ITS MSI composition path to implement a SoC-specific SMMU workaround and avoid faulty MSI/IOMMU interactions on Phytium SoCs. Sequence diagram for MSI message composition on Phytium PS17064sequenceDiagram
participant DeviceDriver
participant GICv3_ITS as its_irq_compose_msi_msg
participant IOMMU_DMA as iommu_dma_compose_msi_msg
DeviceDriver->>GICv3_ITS: its_irq_compose_msi_msg(irq_data, msg)
GICv3_ITS->>GICv3_ITS: its_get_event_id(irq_data)
GICv3_ITS->>GICv3_ITS: read_cpuid_id()
alt [CPU model != MIDR_PHYTIUM_PS17064]
GICv3_ITS->>IOMMU_DMA: iommu_dma_compose_msi_msg(msi_desc, msg)
else [CPU model == MIDR_PHYTIUM_PS17064]
GICv3_ITS-->>DeviceDriver: return without calling IOMMU_DMA
end
Sequence diagram for IOMMU default domain selection on Phytium PS17064sequenceDiagram
participant Kernel as kernel_init
participant IOMMUCore as iommu_subsys_init
participant CPU as read_cpuid_id
Kernel->>IOMMUCore: iommu_subsys_init()
IOMMUCore->>CPU: read_cpuid_id()
CPU-->>IOMMUCore: midr
alt [midr & MIDR_CPU_MODEL_MASK == MIDR_PHYTIUM_PS17064]
IOMMUCore->>IOMMUCore: iommu_set_default_passthrough(true)
else [other SoCs]
IOMMUCore->>IOMMUCore: iommu_set_default_translated()<br/>iommu_set_default_passthrough(false)
end
File-Level Changes
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Hey - I've left some high level feedback:
- The Phytium PS17064 CPU model check using
read_cpuid_id() & MIDR_CPU_MODEL_MASKis duplicated across multiple files; consider factoring this into a shared helper or macro so future model handling changes only need to be made in one place. - In
iommu_set_def_domain_type(), the Phytium-specific block silently overrides the user-specified default domain; it would be helpful to emit apr_info/pr_warnexplaining that the requested setting is being ignored on PS17064 due to the SMMU workaround. - In
arm_smmu_probe_device(), the loop invokingiommu_fwspec_add_ids()for the Phytium workaround does not check the return value and may create duplicate or unexpected IDs; consider handling the return code and/or documenting the expected resulting ID list to avoid subtle fwspec corruption.
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Please address the comments from this code review:
## Overall Comments
- The Phytium PS17064 CPU model check using `read_cpuid_id() & MIDR_CPU_MODEL_MASK` is duplicated across multiple files; consider factoring this into a shared helper or macro so future model handling changes only need to be made in one place.
- In `iommu_set_def_domain_type()`, the Phytium-specific block silently overrides the user-specified default domain; it would be helpful to emit a `pr_info`/`pr_warn` explaining that the requested setting is being ignored on PS17064 due to the SMMU workaround.
- In `arm_smmu_probe_device()`, the loop invoking `iommu_fwspec_add_ids()` for the Phytium workaround does not check the return value and may create duplicate or unexpected IDs; consider handling the return code and/or documenting the expected resulting ID list to avoid subtle fwspec corruption.Help me be more useful! Please click 👍 or 👎 on each comment and I'll use the feedback to improve your reviews.
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Pull request overview
This PR adds Phytium PS17064-specific workarounds across the IOMMU/SMMU and GICv3 ITS paths to adjust default IOMMU behavior, stream IDs, and MSI message composition.
Changes:
- Forces default IOMMU passthrough/identity behavior on PS17064.
- Adds PS17064 SMMU firmware ID adjustment during device probing.
- Skips IOMMU-backed MSI message composition for PS17064 ITS interrupts.
Reviewed changes
Copilot reviewed 4 out of 4 changed files in this pull request and generated 2 comments.
| File | Description |
|---|---|
drivers/irqchip/irq-gic-v3-its.c |
Adds PS17064-specific early return before IOMMU MSI composition. |
drivers/iommu/iommu.c |
Forces default IOMMU passthrough behavior for PS17064. |
drivers/iommu/arm/arm-smmu/arm-smmu.h |
Adds CPU type include and Phytium FWID transformation macro. |
drivers/iommu/arm/arm-smmu/arm-smmu.c |
Applies Phytium FWID workaround during SMMU device probing. |
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| #include <asm/cputype.h> |
| for (i = 0; i < num; i++) { | ||
| u32 fwid = FWID_READ(fwspec->ids[i]); | ||
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| iommu_fwspec_add_ids(dev, &fwid, 1); |
This patches updates the support for phytium irq controller driver.
1.iommu/arm-smmu: Add SMMU workaround for Phytium Ps17064
2.arm64: Phytium: Slove the error on aarch32 compiler
3.arm64: Phytium: Fix incorrect MSI compose logic on Phytium PS17064 SoCs
Summary by Sourcery
Update IOMMU, SMMU, and GICv3 ITS handling to apply Phytium PS17064-specific workarounds and defaults.
Bug Fixes:
Enhancements: