[Deepin-Kernel-SIG] [linux 6.6-y] [Upstream] [Intel] Intel: Backport SRF LBR branch counter support to kernel v6.6#828
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June 1, 2025 21:52
ANBZ: #8006 commit 571d91d upstream. Currently, the additional information of a branch entry is stored in a u64 space. With more and more information added, the space is running out. For example, the information of occurrences of events will be added for each branch. Two places were suggested to append the counters. https://lore.kernel.org/lkml/20230802215814.GH231007@hirez.programming.kicks-ass.net/ One place is right after the flags of each branch entry. It changes the existing struct perf_branch_entry. The later ARCH specific implementation has to be really careful to consistently pick the right struct. The other place is right after the entire struct perf_branch_stack. The disadvantage is that the pointer of the extra space has to be recorded. The common interface perf_sample_save_brstack() has to be updated. The latter is much straightforward, and should be easily understood and maintained. It is implemented in the patch. Add a new branch sample type, PERF_SAMPLE_BRANCH_COUNTERS, to indicate the event which is recorded in the branch info. The "u64 counters" may store the occurrences of several events. The information regarding the number of events/counters and the width of each counter should be exposed via sysfs as a reference for the perf tool. Define the branch_counter_nr and branch_counter_width ABI here. The support will be implemented later in the Intel-specific patch. Intel-SIG: commit 571d91d perf: Add branch stack counters Backport LBR branch counter support to kernel v6.6. Suggested-by: Peter Zijlstra (Intel) <peterz@infradead.org> Signed-off-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lkml.kernel.org/r/20231025201626.3000228-1-kan.liang@linux.intel.com [ Yunying Sun: amend commit log ] Signed-off-by: Yunying Sun <yunying.sun@intel.com>
ANBZ: #8006 commit 85846b2 upstream. Currently, branch_sample_type !=0 is used to check whether a branch stack setup is required. But it doesn't check the sample type, unnecessary branch stack setup may be done for a counting event. E.g., perf record -e "{branch-instructions,branch-misses}:S" -j any Also, the event only with the new PERF_SAMPLE_BRANCH_COUNTERS branch sample type may not require a branch stack setup either. Add a new flag NEEDS_BRANCH_STACK to indicate whether the event requires a branch stack setup. Replace the needs_branch_stack() by checking the new flag. The counting event check is implemented here. The later patch will take the new PERF_SAMPLE_BRANCH_COUNTERS into account. Intel-SIG: commit 85846b2 perf/x86: Add PERF_X86_EVENT_NEEDS_BRANCH_STACK flag Backport LBR branch counter support to kernel v6.6. Signed-off-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lkml.kernel.org/r/20231025201626.3000228-2-kan.liang@linux.intel.com [ Yunying Sun: amend commit log ] Signed-off-by: Yunying Sun <yunying.sun@intel.com>
ANBZ: #8006 commit 1f2376c upstream. Add a helper function to check call stack sample type. The later patch will invoke the function in several places. Intel-SIG: commit 1f2376c perf: Add branch_sample_call_stack Backport LBR branch counter support to kernel v6.6. Signed-off-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lkml.kernel.org/r/20231025201626.3000228-3-kan.liang@linux.intel.com [ Yunying Sun: amend commit log ] Signed-off-by: Yunying Sun <yunying.sun@intel.com>
ANBZ: #8006 commit 3374491 upstream. The branch counters logging (A.K.A LBR event logging) introduces a per-counter indication of precise event occurrences in LBRs. It can provide a means to attribute exposed retirement latency to combinations of events across a block of instructions. It also provides a means of attributing Timed LBR latencies to events. The feature is first introduced on SRF/GRR. It is an enhancement of the ARCH LBR. It adds new fields in the LBR_INFO MSRs to log the occurrences of events on the GP counters. The information is displayed by the order of counters. The design proposed in this patch requires that the events which are logged must be in a group with the event that has LBR. If there are more than one LBR group, the counters logging information only from the current group (overflowed) are stored for the perf tool, otherwise the perf tool cannot know which and when other groups are scheduled especially when multiplexing is triggered. The user can ensure it uses the maximum number of counters that support LBR info (4 by now) by making the group large enough. The HW only logs events by the order of counters. The order may be different from the order of enabling which the perf tool can understand. When parsing the information of each branch entry, convert the counter order to the enabled order, and store the enabled order in the extension space. Unconditionally reset LBRs for an LBR event group when it's deleted. The logged counter information is only valid for the current LBR group. If another LBR group is scheduled later, the information from the stale LBRs would be otherwise wrongly interpreted. Add a sanity check in intel_pmu_hw_config(). Disable the feature if other counter filters (inv, cmask, edge, in_tx) are set or LBR call stack mode is enabled. (For the LBR call stack mode, we cannot simply flush the LBR, since it will break the call stack. Also, there is no obvious usage with the call stack mode for now.) Only applying the PERF_SAMPLE_BRANCH_COUNTERS doesn't require any branch stack setup. Expose the maximum number of supported counters and the width of the counters into the sysfs. The perf tool can use the information to parse the logged counters in each branch. Intel-SIG: commit 3374491 perf/x86/intel: Support branch counters logging Backport LBR branch counter support to kernel v6.6. Signed-off-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lkml.kernel.org/r/20231025201626.3000228-5-kan.liang@linux.intel.com [ Yunying Sun: amend commit log ] Signed-off-by: Yunying Sun <yunying.sun@intel.com>
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Reviewer's GuideThis PR backports Intel SRF/GRR Architectural LBR branch counter logging support to Linux 6.6 by integrating new PMU flags, sample types, MSR definitions, data paths and sysfs attributes to enable counting and exporting per-branch event occurrences alongside existing LBR stacks. Sequence Diagram for Branch Counter Data Collection PathsequenceDiagram
actor UserApp
participant Kernel_PerfEventCore as Perf Core
participant Kernel_IntelPMUDriver as Intel PMU Driver
participant CPU_Hardware as CPU (PMU/LBR)
UserApp->>Perf Core: Configure event (attr.branch_sample_type |= PERF_SAMPLE_BRANCH_COUNTERS)
Perf Core->>Intel PMU Driver: intel_pmu_hw_config(event)
Intel PMU Driver->>Intel PMU Driver: Set event->hw.flags (e.g., PERF_X86_EVENT_BRANCH_COUNTERS)
Intel PMU Driver->>CPU_Hardware: Program EVENTSEL MSR (incl. ARCH_PERFMON_EVENTSEL_BR_CNTR)
Note over CPU_Hardware, Intel PMU Driver: Later, on Performance Monitoring Interrupt (PMI)
CPU_Hardware->>Intel PMU Driver: PMI occurs
Intel PMU Driver->>Intel PMU Driver: intel_pmu_handle_pmi()
Intel PMU Driver->>CPU_Hardware: Read LBR MSRs (From, To, Info with raw counters)
Intel PMU Driver->>Intel PMU Driver: intel_pmu_store_lbr() (stores raw counters in cpuc->lbr_entries[i].reserved)
Intel PMU Driver->>Intel PMU Driver: intel_pmu_lbr_save_brstack(data, cpuc, event)
alt is_branch_counters_group(event)
Intel PMU Driver->>Intel PMU Driver: intel_pmu_lbr_counters_reorder(cpuc, event) (populates cpuc->lbr_counters)
Intel PMU Driver->>Perf Core: perf_sample_save_brstack(data, event, &cpuc->lbr_stack, cpuc->lbr_counters)
else Not a branch counter group
Intel PMU Driver->>Perf Core: perf_sample_save_brstack(data, event, &cpuc->lbr_stack, NULL)
end
Perf Core->>Perf Core: Populate data->br_stack_cntr (if applicable)
Intel PMU Driver->>Perf Core: perf_event_overflow(event, &data, regs)
Perf Core->>Perf Core: perf_output_sample(handle, ..., data, ...)
alt data->br_stack_cntr is not NULL
Perf Core->>Perf Core: Copy counter data to perf buffer
end
Perf Core->>UserApp: Data available in perf buffer
Entity Relationship Diagram for Modified Performance Event StructureserDiagram
perf_sample_data {
u64_ptr br_stack_cntr "New field: Pointer to array of branch counters"
perf_branch_stack_ptr br_stack "Pointer to branch stack structure"
}
cpu_hw_events {
u64_array lbr_counters "New field: Array of reordered branch counters"
perf_branch_entry_array lbr_entries "Array of LBR entries from hardware"
perf_branch_stack lbr_stack "LBR stack structure"
}
perf_branch_entry {
u64 from_address "Branch from address"
u64 to_address "Branch to address"
u64 flags "Branch flags"
u64 reserved "Modified: Temporarily stores raw counter data from MSRs"
}
x86_pmu {
unsigned_int lbr_counters_capability "New field: Indicates LBR counter support (from CPUID)"
unsigned_int flags "Modified: Includes PMU_FL_BR_CNTR flag"
}
perf_sample_data }o--|| perf_branch_stack : references
cpu_hw_events }o--|| perf_branch_stack : contains
cpu_hw_events }o--|| perf_branch_entry : "has array of"
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Pull Request Overview
Backport Intel SRF LBR branch counter support from kernel v6.8 to v6.6, adding the ability to record per-branch event occurrences in LBR stacks and expose them through perf and sysfs.
- Introduce
PERF_SAMPLE_BRANCH_COUNTERSand extendperf_branch_stackto carry counter data. - Update core perf I/O routines and UAPI headers to copy and describe branch counters.
- Enhance the Intel PMU backend (MSRs, enable masks, ordering, reset, sysfs attributes, and constraint checks) to support branch counter logging.
Reviewed Changes
Copilot reviewed 14 out of 14 changed files in this pull request and generated 3 comments.
Show a summary per file
| File | Description |
|---|---|
| kernel/events/core.c | Copy additional branch-counter data in perf_output_sample. |
| include/uapi/linux/perf_event.h | Define PERF_SAMPLE_BRANCH_COUNTERS flag and document format. |
| include/linux/perf_event.h | Add br_stack_cntr field and helper functions. |
| arch/x86/include/asm/perf_event.h | Add ARCH_PERFMON_EVENTSEL_BR_CNTR mask. |
| arch/x86/include/asm/msr-index.h | Define MSR masks/offsets for branch counters. |
| arch/x86/events/perf_event_flags.h | Add BRANCH_COUNTERS PMU flag. |
| arch/x86/events/perf_event.h | Introduce group check and storage for branch counters. |
| arch/x86/events/intel/lbr.c | Store, reorder, and clear branch counters in LBR handling. |
| arch/x86/events/intel/ds.c | Pass NULL counter pointer when PEBS branch stack is saved. |
| arch/x86/events/intel/core.c | Integrate branch-counter flags into event setup and teardown. |
| arch/x86/events/core.c | Call new save API with NULL for non-Intel backends. |
| arch/x86/events/amd/core.c | Update AMD handler to pass NULL counters. |
| arch/powerpc/perf/core-book3s.c | Update PowerPC to pass NULL counters. |
| Documentation/ABI/testing/sysfs-bus-event_source-devices-caps | Document branch_counter_nr and branch_counter_width. |
Comments suppressed due to low confidence (1)
arch/x86/include/asm/perf_event.h:34
- [nitpick] The abbreviation
BR_CNTRmay be unclear; consider renaming toBRANCH_COUNTERor aligning with otherBRANCH_*macros for consistency.
#define ARCH_PERFMON_EVENTSEL_BR_CNTR (1ULL << 35)
| * Leverage the reserved field of cpuc->lbr_entries[i] to | ||
| * temporarily store the branch counters information. | ||
| * The later code will decide what content can be disclosed | ||
| * to the perf tool. Pleae see intel_pmu_lbr_counters_reorder(). |
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Fix typo: change "Pleae" to "Please" in the comment.
Suggested change
| * to the perf tool. Pleae see intel_pmu_lbr_counters_reorder(). | |
| * to the perf tool. Please see intel_pmu_lbr_counters_reorder(). |
| } | ||
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| if (needs_branch_stack(event)) { | ||
| if (needs_branch_stack(event) && is_sampling_event(event)) |
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Use the new intel_pmu_needs_branch_stack(event) helper instead of needs_branch_stack(event) to include branch counter setups consistently.
Suggested change
| if (needs_branch_stack(event) && is_sampling_event(event)) | |
| if (intel_pmu_needs_branch_stack(event) && is_sampling_event(event)) |
| * { u64 from, to, flags } lbr[nr]; | ||
| * # | ||
| * # The format of the counters is decided by the | ||
| * # "branch_counter_nr" and "branch_counter_width", |
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[nitpick] The # markers in the comment block are unconventional; remove or replace them with standard * prefixes for consistency.
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Hey @Avenger-285714 - I've reviewed your changes and they look great!
Here's what I looked at during the review
- 🟡 General issues: 1 issue found
- 🟢 Security: all looks good
- 🟢 Testing: all looks good
- 🟢 Complexity: all looks good
- 🟢 Documentation: all looks good
Help me be more useful! Please click 👍 or 👎 on each comment and I'll use the feedback to improve your reviews.
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| static __always_inline bool intel_pmu_needs_branch_stack(struct perf_event *event) | ||
| { | ||
| return event->hw.flags & PERF_X86_EVENT_NEEDS_BRANCH_STACK; |
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suggestion: Use explicit boolean conversion in intel_pmu_needs_branch_stack
Use !!(event->hw.flags & PERF_X86_EVENT_NEEDS_BRANCH_STACK) to ensure the function returns a true boolean value.
Suggested change
| return event->hw.flags & PERF_X86_EVENT_NEEDS_BRANCH_STACK; | |
| return !!(event->hw.flags & PERF_X86_EVENT_NEEDS_BRANCH_STACK); |
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bugzilla: https://bugzilla.openanolis.cn/show_bug.cgi?id=8006
The branch counters logging (A.K.A LBR event logging) introduces a per-counter indication of precise event occurrences in LBRs. It can provide a means to attribute exposed retirement latency to combinations of events across a block of instructions. It also provides a means of attributing Timed LBR latencies to events.
The feature will be first introduced with next Intel E-core Xeon Sierra Forest(SRF)/Grand Ridge(GRR). It is an enhancement of the Architectural LBR. It adds new fields in the LBR_INFO MSRs to log the occurrences of events on the GP counters. The information is displayed by the order of counters.
To support this feature, both kernel PMU changes and user space perf tool changes are needed.
Kernel commits(5 patches, from mainline kernel v6.8-rc1):
3374491 perf/x86/intel: Support branch counters logging
318c498 perf/x86/intel: Reorganize attrs and is_visible
1f2376c perf: Add branch_sample_call_stack
85846b2 perf/x86: Add PERF_X86_EVENT_NEEDS_BRANCH_STACK flag
571d91d perf: Add branch stack counters
Reference: https://lore.kernel.org/lkml/20231025201626.3000228-5-kan.liang@linux.intel.com/
(deepin: Skip 318c498 perf/x86/intel: Reorganize attrs and is_visible because of merged before.)
Perf tool commits(4 patches, from mainline kernel v6.8-rc1):
6975796 perf test: Basic branch counter support
9fbb4b0 perf tools: Add branch counter knob
ac9cd72 perf header: Support num and width of branch counters
76db7aa tools headers UAPI: Sync include/uapi/linux/perf_event.h header with the kernel
Reference: https://lore.kernel.org/lkml/20240109222804.28583-1-acme@kernel.org/
Since perf tool changes are independent to kernel versions, this ticket is only created for backporting the kernel commits to kernel v6.6. The perf tool commits will be useful for testing the kernel backport.
Note: The backported patches have no deviations from the upstream version, and have been verified on Intel internal SRF platforms.
Link: https://gitee.com/anolis/cloud-kernel/pulls/2680
Summary by Sourcery
Backport Intel SRF/GRR LBR branch counter logging support to kernel v6.6, enabling collection and reporting of per-branch event occurrence counters in perf.
New Features:
Enhancements:
Documentation: